From 247978cdd7a69b4a9fcff5aad5ac835e0f13c1ac Mon Sep 17 00:00:00 2001 From: ciceron Date: Thu, 3 May 2001 21:09:28 +0000 Subject: [PATCH] * config/m68hc11/m68hc11.md ("bitcmpqi"): New pattern for bitb instruction. ("bitcmpqi2"): New pattern for bit-extract and test. ("bitcmphi"): New pattern for bitb/bita instructions. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@41812 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 7 ++++ gcc/config/m68hc11/m68hc11.md | 81 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d752c56..9c9e4ca 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2001-05-03 Stephane Carrez + + * config/m68hc11/m68hc11.md ("bitcmpqi"): New pattern for bitb + instruction. + ("bitcmpqi2"): New pattern for bit-extract and test. + ("bitcmphi"): New pattern for bitb/bita instructions. + 2001-05-03 Joseph S. Myers * gccbug.in: Use a temporary directory when the mktemp command is diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md index ec6956e..a4380c3 100644 --- a/gcc/config/m68hc11/m68hc11.md +++ b/gcc/config/m68hc11/m68hc11.md @@ -383,6 +383,87 @@ DONE; }") +(define_insn "bitcmpqi" + [(set (cc0) + (and:QI (match_operand:QI 0 "tst_operand" "d,d,d") + (match_operand:QI 1 "cmp_operand" "im,*A,u")))] + "" + "@ + bitb\\t%1 + # + bitb\\t%1") + +(define_insn "bitcmpqi_z_used" + [(set (cc0) + (and:QI (match_operand:QI 0 "tst_operand" "d") + (match_operand:QI 1 "cmp_operand" "m"))) + (use (match_operand:HI 2 "hard_reg_operand" "xy")) + (use (reg:HI 11))] + "" + "#") + +(define_split /* "bitcmpqi_z_used" */ + [(set (cc0) + (and:QI (match_operand:QI 0 "tst_operand" "d") + (match_operand:QI 1 "cmp_operand" "m"))) + (use (match_operand:HI 2 "hard_reg_operand" "xy")) + (use (reg:HI 11))] + "z_replacement_completed == 2" + [(set (mem:HI (pre_dec:HI (reg:HI 3))) (match_dup 2)) + (set (match_dup 2) (match_dup 3)) + (set (cc0) (and:QI (match_dup 0) (match_dup 1))) + (set (match_dup 2) (mem:HI (post_inc:HI (reg:HI 3))))] + "operands[3] = gen_rtx (REG, HImode, SOFT_Z_REGNUM);") + +(define_insn "bitcmphi" + [(set (cc0) + (and:HI (match_operand:HI 0 "tst_operand" "d") + (match_operand:HI 1 "const_int_operand" "i")))] + "(INTVAL (operands[1]) & 0x0ff) == 0 + || (INTVAL (operands[1]) & 0x0ff00) == 0" + "* +{ + if ((INTVAL (operands[1]) & 0x0ff) == 0) + return \"bita\\t%h1\"; + else + return \"bitb\\t%1\"; +}") + +(define_insn "bitcmpqi_12" + [(set (cc0) + (zero_extract (match_operand:HI 0 "tst_operand" "d") + (match_operand:HI 1 "const_int_operand" "i") + (match_operand:HI 2 "const_int_operand" "i")))] + "(unsigned) (INTVAL (operands[2]) + INTVAL (operands[1])) <= 8 + || (((unsigned) (INTVAL (operands[2]) + INTVAL (operands[1])) <= 16) + && (unsigned) INTVAL (operands[2]) >= 8)" + "* +{ + rtx ops[1]; + int mask; + int startpos = INTVAL (operands[2]); + int bitsize = INTVAL (operands[1]); + + if (startpos >= 8) + { + startpos -= 8; + mask = (1 << (startpos + bitsize)) - 1; + mask &= ~((1 << startpos) - 1); + + ops[0] = GEN_INT (mask); + output_asm_insn (\"bita\\t%0\", ops); + } + else + { + mask = (1 << (startpos + bitsize)) - 1; + mask &= ~((1 << startpos) - 1); + + ops[0] = GEN_INT (mask); + output_asm_insn (\"bitb\\t%0\", ops); + } + return \"\"; +}") + (define_insn "cmpqi_1" [(set (cc0) (compare (match_operand:QI 0 "tst_operand" "d,d,*x*y,*x*y") -- 2.7.4