From 2447156b3c9ebc54fafb921075cb94c5205dc3b1 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Fri, 14 Apr 2023 15:44:43 +0100 Subject: [PATCH] aco: implement strict_wqm_coord_amd Signed-off-by: Rhys Perry Reviewed-by: Georg Lehmann Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 27 ++++++++++++++++++++++ .../compiler/aco_instruction_selection_setup.cpp | 7 ++++++ 2 files changed, 34 insertions(+) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 9f2b52e..1a9a296 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -9044,6 +9044,33 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) ctx->block->kind |= block_kind_export_end; break; } + case nir_intrinsic_strict_wqm_coord_amd: { + Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); + Temp src = get_ssa_temp(ctx, instr->src[0].ssa); + Temp tmp = bld.tmp(RegClass::get(RegType::vgpr, dst.bytes())); + unsigned begin_size = nir_intrinsic_base(instr); + + unsigned num_src = 1; + auto it = ctx->allocated_vec.find(src.id()); + if (it != ctx->allocated_vec.end()) + num_src = src.bytes() / it->second[0].bytes(); + + aco_ptr vec{create_instruction( + aco_opcode::p_create_vector, Format::PSEUDO, num_src + !!begin_size, 1)}; + + if (begin_size) + vec->operands[0] = Operand(RegClass::get(RegType::vgpr, begin_size)); + for (unsigned i = 0; i < num_src; i++) { + Temp comp = it != ctx->allocated_vec.end() ? it->second[i] : src; + vec->operands[i + !!begin_size] = Operand(comp); + } + + vec->definitions[0] = Definition(tmp); + ctx->block->instructions.emplace_back(std::move(vec)); + + bld.pseudo(aco_opcode::p_start_linear_vgpr, Definition(dst), tmp); + break; + } default: isel_err(&instr->instr, "Unimplemented intrinsic instr"); abort(); diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index 0a67a2f..28184fa 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -464,6 +464,13 @@ init_context(isel_context* ctx, nir_shader* shader) nir_intrinsic_instr* intrinsic = nir_instr_as_intrinsic(instr); if (!nir_intrinsic_infos[intrinsic->intrinsic].has_dest) break; + if (intrinsic->intrinsic == nir_intrinsic_strict_wqm_coord_amd) { + regclasses[intrinsic->dest.ssa.index] = + RegClass::get(RegType::vgpr, intrinsic->dest.ssa.num_components * 4 + + nir_intrinsic_base(intrinsic)) + .as_linear(); + break; + } RegType type = RegType::sgpr; switch (intrinsic->intrinsic) { case nir_intrinsic_load_push_constant: -- 2.7.4