From 241789a114c4ef0250d7298144b15841416c196e Mon Sep 17 00:00:00 2001 From: Egor Chesakov Date: Mon, 20 Aug 2018 20:19:08 -0700 Subject: [PATCH] Stop using size_t for passing immediate values in CodeGen CodeGenInterface (#19544) --- src/jit/codegen.h | 21 +++++++++++---------- src/jit/codegenarm.cpp | 11 +++++++---- src/jit/codegencommon.cpp | 2 +- src/jit/codegeninterface.h | 10 +++++----- src/jit/instr.cpp | 39 ++++++++++++++++++++------------------- 5 files changed, 44 insertions(+), 39 deletions(-) diff --git a/src/jit/codegen.h b/src/jit/codegen.h index c00afb4..19d64b2 100644 --- a/src/jit/codegen.h +++ b/src/jit/codegen.h @@ -251,7 +251,7 @@ protected: void genDefineTempLabel(BasicBlock* label); - void genAdjustSP(ssize_t delta); + void genAdjustSP(target_ssize_t delta); void genAdjustStackLevel(BasicBlock* block); @@ -1181,7 +1181,8 @@ public: void inst_IV_handle(instruction ins, int val); void inst_FS(instruction ins, unsigned stk = 0); - void inst_RV_IV(instruction ins, regNumber reg, ssize_t val, emitAttr size, insFlags flags = INS_FLAGS_DONT_CARE); + void inst_RV_IV( + instruction ins, regNumber reg, target_ssize_t val, emitAttr size, insFlags flags = INS_FLAGS_DONT_CARE); void inst_ST_RV(instruction ins, TempDsc* tmp, unsigned ofs, regNumber reg, var_types type); void inst_ST_IV(instruction ins, TempDsc* tmp, unsigned ofs, int val, var_types type); @@ -1265,13 +1266,13 @@ public: void inst_set_SV_var(GenTree* tree); #ifdef _TARGET_ARM_ - bool arm_Valid_Imm_For_Instr(instruction ins, ssize_t imm, insFlags flags); - bool arm_Valid_Disp_For_LdSt(ssize_t disp, var_types type); - bool arm_Valid_Imm_For_Alu(ssize_t imm); - bool arm_Valid_Imm_For_Mov(ssize_t imm); - bool arm_Valid_Imm_For_Small_Mov(regNumber reg, ssize_t imm, insFlags flags); - bool arm_Valid_Imm_For_Add(ssize_t imm, insFlags flag); - bool arm_Valid_Imm_For_Add_SP(ssize_t imm); + bool arm_Valid_Imm_For_Instr(instruction ins, target_ssize_t imm, insFlags flags); + bool arm_Valid_Disp_For_LdSt(target_ssize_t disp, var_types type); + bool arm_Valid_Imm_For_Alu(target_ssize_t imm); + bool arm_Valid_Imm_For_Mov(target_ssize_t imm); + bool arm_Valid_Imm_For_Small_Mov(regNumber reg, target_ssize_t imm, insFlags flags); + bool arm_Valid_Imm_For_Add(target_ssize_t imm, insFlags flag); + bool arm_Valid_Imm_For_Add_SP(target_ssize_t imm); bool arm_Valid_Imm_For_BL(ssize_t addr); bool ins_Writes_Dest(instruction ins); @@ -1306,7 +1307,7 @@ public: void instGen_Compare_Reg_To_Reg(emitAttr size, regNumber reg1, regNumber reg2); - void instGen_Compare_Reg_To_Imm(emitAttr size, regNumber reg, ssize_t imm); + void instGen_Compare_Reg_To_Imm(emitAttr size, regNumber reg, target_ssize_t imm); void instGen_Load_Reg_From_Lcl(var_types srcType, regNumber dstReg, int varNum, int offs); diff --git a/src/jit/codegenarm.cpp b/src/jit/codegenarm.cpp index 45616c7..f45bbfe 100644 --- a/src/jit/codegenarm.cpp +++ b/src/jit/codegenarm.cpp @@ -78,6 +78,7 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr size, regNumber reg, ssize_t imm, if (EA_IS_RELOC(size)) { + // TODO-CrossBitness: we wouldn't need the cast below if we had CodeGen::instGen_Set_Reg_To_Reloc_Imm. genMov32RelocatableImmediate(size, (BYTE*)imm, reg); } else if (imm == 0) @@ -86,14 +87,16 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr size, regNumber reg, ssize_t imm, } else { - if (arm_Valid_Imm_For_Mov(imm)) + // TODO-CrossBitness: we wouldn't need the cast below if we had CodeGen::instGen_Set_Reg_To_Reloc_Imm. + const int val32 = (int)imm; + if (arm_Valid_Imm_For_Mov(val32)) { - getEmitter()->emitIns_R_I(INS_mov, size, reg, imm, flags); + getEmitter()->emitIns_R_I(INS_mov, size, reg, val32, flags); } else // We have to use a movw/movt pair of instructions { - ssize_t imm_lo16 = (imm & 0xffff); - ssize_t imm_hi16 = (imm >> 16) & 0xffff; + const int imm_lo16 = val32 & 0xffff; + const int imm_hi16 = (val32 >> 16) & 0xffff; assert(arm_Valid_Imm_For_Mov(imm_lo16)); assert(imm_hi16 != 0); diff --git a/src/jit/codegencommon.cpp b/src/jit/codegencommon.cpp index 67faf40..9c79e48 100644 --- a/src/jit/codegencommon.cpp +++ b/src/jit/codegencommon.cpp @@ -1038,7 +1038,7 @@ void CodeGen::genDefineTempLabel(BasicBlock* label) * return value) are used at this point. */ -void CodeGen::genAdjustSP(ssize_t delta) +void CodeGen::genAdjustSP(target_ssize_t delta) { #if defined(_TARGET_X86_) && !defined(UNIX_X86_ABI) if (delta == sizeof(int)) diff --git a/src/jit/codegeninterface.h b/src/jit/codegeninterface.h index 72f78c9..72beee4 100644 --- a/src/jit/codegeninterface.h +++ b/src/jit/codegeninterface.h @@ -276,11 +276,11 @@ public: // Methods to abstract target information - bool validImmForInstr(instruction ins, ssize_t val, insFlags flags = INS_FLAGS_DONT_CARE); - bool validDispForLdSt(ssize_t disp, var_types type); - bool validImmForAdd(ssize_t imm, insFlags flags); - bool validImmForAlu(ssize_t imm); - bool validImmForMov(ssize_t imm); + bool validImmForInstr(instruction ins, target_ssize_t val, insFlags flags = INS_FLAGS_DONT_CARE); + bool validDispForLdSt(target_ssize_t disp, var_types type); + bool validImmForAdd(target_ssize_t imm, insFlags flags); + bool validImmForAlu(target_ssize_t imm); + bool validImmForMov(target_ssize_t imm); bool validImmForBL(ssize_t addr); instruction ins_Load(var_types srcType, bool aligned = false); diff --git a/src/jit/instr.cpp b/src/jit/instr.cpp index 68d2355..763a403 100644 --- a/src/jit/instr.cpp +++ b/src/jit/instr.cpp @@ -489,7 +489,7 @@ void CodeGen::inst_set_SV_var(GenTree* tree) */ void CodeGen::inst_RV_IV( - instruction ins, regNumber reg, ssize_t val, emitAttr size, insFlags flags /* = INS_FLAGS_DONT_CARE */) + instruction ins, regNumber reg, target_ssize_t val, emitAttr size, insFlags flags /* = INS_FLAGS_DONT_CARE */) { #if !defined(_TARGET_64BIT_) assert(size != EA_8BYTE); @@ -903,7 +903,8 @@ AGAIN: assert(offs == 0); - inst_RV_IV(ins, reg, tree->gtIntCon.gtIconVal, emitActualTypeSize(tree->TypeGet()), flags); + // TODO-CrossBitness: we wouldn't need the cast below if GenTreeIntCon::gtIconVal had target_ssize_t type. + inst_RV_IV(ins, reg, (target_ssize_t)tree->gtIntCon.gtIconVal, emitActualTypeSize(tree->TypeGet()), flags); break; case GT_CNS_LNG: @@ -914,16 +915,16 @@ AGAIN: assert(offs == 0); #endif // _TARGET_AMD64_ - ssize_t constVal; - emitAttr size; + target_ssize_t constVal; + emitAttr size; if (offs == 0) { - constVal = (ssize_t)(tree->gtLngCon.gtLconVal); + constVal = (target_ssize_t)(tree->gtLngCon.gtLconVal); size = EA_PTRSIZE; } else { - constVal = (ssize_t)(tree->gtLngCon.gtLconVal >> 32); + constVal = (target_ssize_t)(tree->gtLngCon.gtLconVal >> 32); size = EA_4BYTE; } @@ -1165,7 +1166,7 @@ void CodeGen::inst_FS_ST(instruction ins, emitAttr size, TempDsc* tmp, unsigned #endif #ifdef _TARGET_ARM_ -bool CodeGenInterface::validImmForInstr(instruction ins, ssize_t imm, insFlags flags) +bool CodeGenInterface::validImmForInstr(instruction ins, target_ssize_t imm, insFlags flags) { if (getEmitter()->emitInsIsLoadOrStore(ins) && !instIsFP(ins)) { @@ -1236,12 +1237,12 @@ bool CodeGenInterface::validImmForInstr(instruction ins, ssize_t imm, insFlags f } return result; } -bool CodeGen::arm_Valid_Imm_For_Instr(instruction ins, ssize_t imm, insFlags flags) +bool CodeGen::arm_Valid_Imm_For_Instr(instruction ins, target_ssize_t imm, insFlags flags) { return validImmForInstr(ins, imm, flags); } -bool CodeGenInterface::validDispForLdSt(ssize_t disp, var_types type) +bool CodeGenInterface::validDispForLdSt(target_ssize_t disp, var_types type) { if (varTypeIsFloating(type)) { @@ -1258,45 +1259,45 @@ bool CodeGenInterface::validDispForLdSt(ssize_t disp, var_types type) return false; } } -bool CodeGen::arm_Valid_Disp_For_LdSt(ssize_t disp, var_types type) +bool CodeGen::arm_Valid_Disp_For_LdSt(target_ssize_t disp, var_types type) { return validDispForLdSt(disp, type); } -bool CodeGenInterface::validImmForAlu(ssize_t imm) +bool CodeGenInterface::validImmForAlu(target_ssize_t imm) { return emitter::emitIns_valid_imm_for_alu(imm); } -bool CodeGen::arm_Valid_Imm_For_Alu(ssize_t imm) +bool CodeGen::arm_Valid_Imm_For_Alu(target_ssize_t imm) { return validImmForAlu(imm); } -bool CodeGenInterface::validImmForMov(ssize_t imm) +bool CodeGenInterface::validImmForMov(target_ssize_t imm) { return emitter::emitIns_valid_imm_for_mov(imm); } -bool CodeGen::arm_Valid_Imm_For_Mov(ssize_t imm) +bool CodeGen::arm_Valid_Imm_For_Mov(target_ssize_t imm) { return validImmForMov(imm); } -bool CodeGen::arm_Valid_Imm_For_Small_Mov(regNumber reg, ssize_t imm, insFlags flags) +bool CodeGen::arm_Valid_Imm_For_Small_Mov(regNumber reg, target_ssize_t imm, insFlags flags) { return emitter::emitIns_valid_imm_for_small_mov(reg, imm, flags); } -bool CodeGenInterface::validImmForAdd(ssize_t imm, insFlags flags) +bool CodeGenInterface::validImmForAdd(target_ssize_t imm, insFlags flags) { return emitter::emitIns_valid_imm_for_add(imm, flags); } -bool CodeGen::arm_Valid_Imm_For_Add(ssize_t imm, insFlags flags) +bool CodeGen::arm_Valid_Imm_For_Add(target_ssize_t imm, insFlags flags) { return emitter::emitIns_valid_imm_for_add(imm, flags); } // Check "add Rd,SP,i10" -bool CodeGen::arm_Valid_Imm_For_Add_SP(ssize_t imm) +bool CodeGen::arm_Valid_Imm_For_Add_SP(target_ssize_t imm) { return emitter::emitIns_valid_imm_for_add_sp(imm); } @@ -2182,7 +2183,7 @@ void CodeGen::instGen_Compare_Reg_To_Reg(emitAttr size, regNumber reg1, regNumbe * Machine independent way to set the flags based upon * comparing a register with an immediate */ -void CodeGen::instGen_Compare_Reg_To_Imm(emitAttr size, regNumber reg, ssize_t imm) +void CodeGen::instGen_Compare_Reg_To_Imm(emitAttr size, regNumber reg, target_ssize_t imm) { if (imm == 0) { -- 2.7.4