From 23da702d69b1562828cc40d948403fa4be2c5e2a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 19 Mar 2020 20:46:08 -0400 Subject: [PATCH] GlobalISel: Translate llvm.fshl/llvm.fshr --- llvm/include/llvm/Support/TargetOpcodes.def | 6 ++++++ llvm/include/llvm/Target/GenericOpcodes.td | 16 +++++++++++++++ .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 2 ++ llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 6 +++++- .../AArch64/GlobalISel/arm64-irtranslator.ll | 24 ++++++++++++++++++++++ .../GlobalISel/legalizer-info-validation.mir | 6 ++++++ 6 files changed, 59 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def index 12bd1a7..6d5bef11 100644 --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -385,6 +385,12 @@ HANDLE_TARGET_OPCODE(G_LSHR) // Generic arithmetic right-shift HANDLE_TARGET_OPCODE(G_ASHR) +// Generic funnel left shift +HANDLE_TARGET_OPCODE(G_FSHL) + +// Generic funnel right shift +HANDLE_TARGET_OPCODE(G_FSHR) + /// Generic integer-base comparison, also applicable to vectors of integers. HANDLE_TARGET_OPCODE(G_ICMP) diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td index 901c3d1..d314d7d 100644 --- a/llvm/include/llvm/Target/GenericOpcodes.td +++ b/llvm/include/llvm/Target/GenericOpcodes.td @@ -308,6 +308,22 @@ def G_ASHR : GenericInstruction { let hasSideEffects = 0; } +/// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount. +/// fshl(X,Y,Z): (X << (Z % bitwidth)) | (Y >> (bitwidth - (Z % bitwidth))) +def G_FSHL : GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1, type0:$src2, type1:$src3); + let hasSideEffects = 0; +} + +/// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount. +/// fshr(X,Y,Z): (X << (bitwidth - (Z % bitwidth))) | (Y >> (Z % bitwidth)) +def G_FSHR : GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1, type0:$src2, type1:$src3); + let hasSideEffects = 0; +} + // Generic integer comparison. def G_ICMP : GenericInstruction { let OutOperandList = (outs type0:$dst); diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index 2129588..dec8797 100644 --- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -93,6 +93,8 @@ def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; +def : GINodeEquiv; +def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index bb4324c..f812971 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1220,8 +1220,12 @@ unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) { break; case Intrinsic::bswap: return TargetOpcode::G_BSWAP; - case Intrinsic::bitreverse: + case Intrinsic::bitreverse: return TargetOpcode::G_BITREVERSE; + case Intrinsic::fshl: + return TargetOpcode::G_FSHL; + case Intrinsic::fshr: + return TargetOpcode::G_FSHR; case Intrinsic::ceil: return TargetOpcode::G_FCEIL; case Intrinsic::cos: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index f200cf2..4946e8a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1396,6 +1396,30 @@ define i32 @test_bitreverse_intrinsic(i32 %a) { ret i32 %res } +declare i32 @llvm.fshl.i32(i32, i32, i32) +define i32 @test_fshl_intrinsic(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: name: test_fshl_intrinsic +; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0 +; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $w1 +; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $w2 +; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FSHL [[A]], [[B]], [[C]] +; CHECK: $w0 = COPY [[RES]] + %res = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c) + ret i32 %res +} + +declare i32 @llvm.fshr.i32(i32, i32, i32) +define i32 @test_fshr_intrinsic(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: name: test_fshr_intrinsic +; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0 +; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $w1 +; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $w2 +; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FSHR [[A]], [[B]], [[C]] +; CHECK: $w0 = COPY [[RES]] + %res = call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c) + ret i32 %res +} + declare void @llvm.lifetime.start.p0i8(i64, i8*) declare void @llvm.lifetime.end.p0i8(i64, i8*) define void @test_lifetime_intrin() { diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir index 0c06a11..7163ece 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir @@ -263,6 +263,12 @@ # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_FSHL (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FSHR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined # DEBUG-NEXT: G_ICMP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected -- 2.7.4