From 23cf992f4ac3a325ebf015b22955a359a986a488 Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Thu, 15 Jan 1998 01:48:51 +0000 Subject: [PATCH] Support for disassembling parallel instructions added. Insn attributes hand patched until cgen can generate the correct values. --- opcodes/ChangeLog | 13 + opcodes/m32r-asm.c | 454 ++----------------- opcodes/m32r-dis.c | 492 +++++++-------------- opcodes/m32r-dis.in | 252 +++++++++++ opcodes/m32r-opc.c | 1230 ++++++++++++++++++++++++++++++++++++++------------- opcodes/m32r-opc.h | 234 ++++++++++ 6 files changed, 1610 insertions(+), 1065 deletions(-) create mode 100644 opcodes/m32r-dis.in create mode 100644 opcodes/m32r-opc.h diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b772d4b..0c631aa 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,16 @@ +Wed Jan 14 17:37:03 1998 Nick Clifton + + * m32r-dis.in: Generated file imported from cgen. + * cgen-asm.in: Formatting changes to improve readability. + * m32r-asm.c: Formatting changes to improve readability. + * cgen-dis.c: Formatting changes to improve readability. + * m32r-dis.c: Add support for disassembling parallel + instructions. + * m32r-opc.h: Update with latest version generated by cgen. + * m32r-opc.c: Update with latest version generated by cgen, plus + hand patches to allow attributes to work until cgen can generate + these correctly. + start-sanitize-r5900 Tue Jan 13 09:21:56 1998 Jeffrey A Law (law@cygnus.com) diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c index fb028c2..f63c373 100644 --- a/opcodes/m32r-asm.c +++ b/opcodes/m32r-asm.c @@ -21,6 +21,7 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include "sysdep.h" #include #include #include "ansidecl.h" @@ -34,10 +35,10 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ compiled with GCC), or switch to macros, or use something else. */ -static const char *parse_insn_normal - PARAMS ((const struct cgen_insn *, const char **, struct cgen_fields *)); +static const char * parse_insn_normal + PARAMS ((const CGEN_INSN *, const char **, CGEN_FIELDS *)); static void insert_insn_normal - PARAMS ((const struct cgen_insn *, struct cgen_fields *, cgen_insn_t *)); + PARAMS ((const CGEN_INSN *, CGEN_FIELDS *, cgen_insn_t *)); /* Default insertion routine. @@ -119,393 +120,6 @@ insert_normal (value, attrs, start, length, shift, total_length, buffer) } /* -- assembler routines inserted here */ -/* -- asm.c */ - -/* Handle shigh(), high(). */ - -static const char * -parse_h_hi16 (strp, opindex, min, max, valuep) - const char **strp; - int opindex; - unsigned long min, max; - unsigned long *valuep; -{ - const char *errmsg; - - /* FIXME: Need # in assembler syntax (means '#' is optional). */ - if (**strp == '#') - ++*strp; - - if (strncmp (*strp, "high(", 5) == 0) - { - *strp += 5; - /* FIXME: If value was a number, right shift by 16. */ - errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_ULO, valuep); - if (**strp != ')') - return "missing `)'"; - ++*strp; - return errmsg; - } - else if (strncmp (*strp, "shigh(", 6) == 0) - { - *strp += 6; - /* FIXME: If value was a number, right shift by 16 (+ sign test). */ - errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_SLO, valuep); - if (**strp != ')') - return "missing `)'"; - ++*strp; - return errmsg; - } - - return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep); -} - -/* Handle low() in a signed context. Also handle sda(). - The signedness of the value doesn't matter to low(), but this also - handles the case where low() isn't present. */ - -static const char * -parse_h_slo16 (strp, opindex, min, max, valuep) - const char **strp; - int opindex; - long min, max; - long *valuep; -{ - const char *errmsg; - - /* FIXME: Need # in assembler syntax (means '#' is optional). */ - if (**strp == '#') - ++*strp; - - if (strncmp (*strp, "low(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16, valuep); - if (**strp != ')') - return "missing `)'"; - ++*strp; - return errmsg; - } - - if (strncmp (*strp, "sda(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_SDA16, valuep); - if (**strp != ')') - return "missing `)'"; - ++*strp; - return errmsg; - } - - return cgen_parse_signed_integer (strp, opindex, min, max, valuep); -} - -/* Handle low() in an unsigned context. - The signedness of the value doesn't matter to low(), but this also - handles the case where low() isn't present. */ - -static const char * -parse_h_ulo16 (strp, opindex, min, max, valuep) - const char **strp; - int opindex; - unsigned long min, max; - unsigned long *valuep; -{ - const char *errmsg; - - /* FIXME: Need # in assembler syntax (means '#' is optional). */ - if (**strp == '#') - ++*strp; - - if (strncmp (*strp, "low(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16, valuep); - if (**strp != ')') - return "missing `)'"; - ++*strp; - return errmsg; - } - - return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep); -} - -/* -- */ - -/* Main entry point for operand parsing. - - This function is basically just a big switch statement. Earlier versions - used tables to look up the function to use, but - - if the table contains both assembler and disassembler functions then - the disassembler contains much of the assembler and vice-versa, - - there's a lot of inlining possibilities as things grow, - - using a switch statement avoids the function call overhead. - - This function could be moved into `parse_insn_normal', but keeping it - separate makes clear the interface between `parse_insn_normal' and each of - the handlers. -*/ - -CGEN_INLINE const char * -m32r_cgen_parse_operand (opindex, strp, fields) - int opindex; - const char **strp; - struct cgen_fields *fields; -{ - const char *errmsg; - - switch (opindex) - { - case 0 : - errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2); - break; - case 1 : - errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1); - break; - case 2 : - errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1); - break; - case 3 : - errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2); - break; - case 4 : - errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r2); - break; - case 5 : - errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r1); - break; - case 6 : - errmsg = cgen_parse_signed_integer (strp, 6, -128, 127, &fields->f_simm8); - break; - case 7 : - errmsg = cgen_parse_signed_integer (strp, 7, -32768, 32767, &fields->f_simm16); - break; - case 8 : - errmsg = cgen_parse_unsigned_integer (strp, 8, 0, 15, &fields->f_uimm4); - break; - case 9 : - errmsg = cgen_parse_unsigned_integer (strp, 9, 0, 31, &fields->f_uimm5); - break; - case 10 : - errmsg = cgen_parse_unsigned_integer (strp, 10, 0, 65535, &fields->f_uimm16); - break; - case 11 : - errmsg = parse_h_hi16 (strp, 11, 0, 65535, &fields->f_hi16); - break; - case 12 : - errmsg = parse_h_slo16 (strp, 12, -32768, 32767, &fields->f_simm16); - break; - case 13 : - errmsg = parse_h_ulo16 (strp, 13, 0, 65535, &fields->f_uimm16); - break; - case 14 : - errmsg = cgen_parse_address (strp, 14, 0, &fields->f_uimm24); - break; - case 15 : - errmsg = cgen_parse_address (strp, 15, 0, &fields->f_disp8); - break; - case 16 : - errmsg = cgen_parse_address (strp, 16, 0, &fields->f_disp16); - break; - case 17 : - errmsg = cgen_parse_address (strp, 17, 0, &fields->f_disp24); - break; - - default : - fprintf (stderr, "Unrecognized field %d while parsing.\n", opindex); - abort (); - } - - return errmsg; -} - -/* Main entry point for operand insertion. - - This function is basically just a big switch statement. Earlier versions - used tables to look up the function to use, but - - if the table contains both assembler and disassembler functions then - the disassembler contains much of the assembler and vice-versa, - - there's a lot of inlining possibilities as things grow, - - using a switch statement avoids the function call overhead. - - This function could be moved into `parse_insn_normal', but keeping it - separate makes clear the interface between `parse_insn_normal' and each of - the handlers. It's also needed by GAS to insert operands that couldn't be - resolved during parsing. -*/ - -CGEN_INLINE void -m32r_cgen_insert_operand (opindex, fields, buffer) - int opindex; - struct cgen_fields *fields; - cgen_insn_t *buffer; -{ - switch (opindex) - { - case 0 : - insert_normal (fields->f_r2, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_r2, 0|(1<f_r2, 0|(1<f_r1, 0|(1<f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer); - break; - case 7 : - insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer); - break; - case 8 : - insert_normal (fields->f_uimm4, 0|(1<f_uimm5, 0|(1<f_uimm16, 0|(1<f_hi16, 0|(1<f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer); - break; - case 13 : - insert_normal (fields->f_uimm16, 0|(1<f_uimm24, 0|(1<f_disp8, 0|(1<f_disp16, 0|(1<f_disp24, 0|(1<f_simm8, -128, 127); - break; - case 7 : - errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767); - break; - case 8 : - errmsg = cgen_validate_unsigned_integer (fields->f_uimm4, 0, 15); - break; - case 9 : - errmsg = cgen_validate_unsigned_integer (fields->f_uimm5, 0, 31); - break; - case 10 : - errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535); - break; - case 11 : - errmsg = cgen_validate_unsigned_integer (fields->f_hi16, 0, 65535); - break; - case 12 : - errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767); - break; - case 13 : - errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535); - break; - case 14 : - /* nothing to do */ - break; - case 15 : - /* nothing to do */ - break; - case 16 : - /* nothing to do */ - break; - case 17 : - /* nothing to do */ - break; - - default : - fprintf (stderr, "Unrecognized field %d while validating operand.\n", - opindex); - abort (); - } - - return errmsg; -} - -cgen_parse_fn *m32r_cgen_parse_handlers[] = { - 0, /* default */ - parse_insn_normal, -}; - -cgen_insert_fn *m32r_cgen_insert_handlers[] = { - 0, /* default */ - insert_insn_normal, -}; - -void -m32r_cgen_init_asm (mach, endian) - int mach; - enum cgen_endian endian; -{ - m32r_cgen_init_tables (mach); - cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian); - cgen_asm_init (); -} - /* Default insn parser. @@ -523,32 +137,26 @@ m32r_cgen_init_asm (mach, endian) static const char * parse_insn_normal (insn, strp, fields) - const struct cgen_insn *insn; + const CGEN_INSN *insn; const char **strp; - struct cgen_fields *fields; + CGEN_FIELDS *fields; { - const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); const char *str = *strp; const char *errmsg; + const char *p; const unsigned char *syn; #ifdef CGEN_MNEMONIC_OPERANDS int past_opcode_p; #endif - /* If mnemonics are constant, they're not stored with the syntax string. */ -#ifndef CGEN_MNEMONIC_OPERANDS - { - const char *p = syntax->mnemonic; - - while (*p && *p == *str) - ++p, ++str; - if (*p || (*str && !isspace (*str))) - return "unrecognized instruction"; - - while (isspace (*str)) - ++str; - } -#endif + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && *p == *str) + ++p, ++str; + if (*p || (*str && !isspace (*str))) + return "unrecognized instruction"; CGEN_INIT_PARSE (); cgen_init_parse_operand (); @@ -558,7 +166,12 @@ parse_insn_normal (insn, strp, fields) /* We don't check for (*str != '\0') here because we want to parse any trailing fake arguments in the syntax string. */ - for (syn = syntax->syntax; *syn != '\0'; ) + syn = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn)); + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (*syn)) + abort (); + ++syn; + while (*syn != 0) { /* Non operand chars must match exactly. */ /* FIXME: Need to better handle whitespace. */ @@ -617,16 +230,16 @@ parse_insn_normal (insn, strp, fields) static void insert_insn_normal (insn, fields, buffer) - const struct cgen_insn *insn; - struct cgen_fields *fields; + const CGEN_INSN *insn; + CGEN_FIELDS *fields; cgen_insn_t *buffer; { - const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); bfd_vma value; const unsigned char *syn; CGEN_INIT_INSERT (); - value = syntax->value; + value = CGEN_INSN_VALUE (insn); /* If we're recording insns as numbers (rather than a string of bytes), target byte order handling is deferred until later. */ @@ -660,7 +273,7 @@ insert_insn_normal (insn, fields, buffer) /* ??? Rather than scanning the syntax string again, we could store in `fields' a null terminated list of the fields that are present. */ - for (syn = syntax->syntax; *syn != '\0'; ++syn) + for (syn = CGEN_SYNTAX_STRING (syntax); *syn != '\0'; ++syn) { if (CGEN_SYNTAX_CHAR_P (*syn)) continue; @@ -677,10 +290,10 @@ insert_insn_normal (insn, fields, buffer) or NULL if an error occured (an error message will have already been printed). */ -const struct cgen_insn * +const CGEN_INSN * m32r_cgen_assemble_insn (str, fields, buf, errmsg) const char *str; - struct cgen_fields *fields; + CGEN_FIELDS *fields; cgen_insn_t *buf; char **errmsg; { @@ -700,7 +313,7 @@ m32r_cgen_assemble_insn (str, fields, buf, errmsg) start = str; for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) { - const struct cgen_insn *insn = ilist->insn; + const CGEN_INSN *insn = ilist->insn; #if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */ /* Is this insn supported by the selected cpu? */ @@ -758,12 +371,15 @@ m32r_cgen_assemble_insn (str, fields, buf, errmsg) This lets GAS parse registers for us. ??? Interesting idea but not currently used. */ +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + void m32r_cgen_asm_hash_keywords (opvals) - struct cgen_keyword *opvals; + CGEN_KEYWORD *opvals; { - struct cgen_keyword_search search = cgen_keyword_search_init (opvals, NULL); - const struct cgen_keyword_entry *ke; + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY *ke; while ((ke = cgen_keyword_search_next (&search)) != NULL) { diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index 7f29019..d320d53 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -21,11 +21,12 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include "sysdep.h" #include #include "ansidecl.h" #include "dis-asm.h" -#include "m32r-opc.h" #include "bfd.h" +#include "m32r-opc.h" /* ??? The layout of this stuff is still work in progress. For speed in assembly/disassembly, we use inline functions. That of course @@ -45,9 +46,14 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ static int print_insn PARAMS ((bfd_vma, disassemble_info *, char *, int)); static int extract_insn_normal - PARAMS ((const struct cgen_insn *, void *, cgen_insn_t, struct cgen_fields *)); + PARAMS ((const CGEN_INSN *, void *, cgen_insn_t, CGEN_FIELDS *)); static void print_insn_normal - PARAMS ((void *, const struct cgen_insn *, struct cgen_fields *, bfd_vma, int)); + PARAMS ((void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int)); + +CGEN_INLINE void +m32r_cgen_print_operand + PARAMS ((int opindex, disassemble_info * info, CGEN_FIELDS * fields, void const * attrs, bfd_vma pc, int length)); + /* Default extraction routine. @@ -56,11 +62,14 @@ static void print_insn_normal static int extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, valuep) - void *buf_ctrl; - cgen_insn_t insn_value; + void * buf_ctrl; + cgen_insn_t insn_value; unsigned int attrs; - int start, length, shift, total_length; - long *valuep; + int start; + int length; + int shift; + int total_length; + long * valuep; { long value; @@ -85,7 +94,7 @@ extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, else value <<= shift; - *valuep = value; + * valuep = value; return 1; } @@ -93,13 +102,13 @@ extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, static void print_normal (dis_info, value, attrs, pc, length) - void *dis_info; - long value; - unsigned int attrs; + void * dis_info; + long value; + unsigned int attrs; unsigned long pc; /* FIXME: should be bfd_vma */ - int length; + int length; { - disassemble_info *info = dis_info; + disassemble_info * info = dis_info; /* Print the operand as directed by the attributes. */ if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_FAKE)) @@ -120,264 +129,19 @@ print_normal (dis_info, value, attrs, pc, length) static void print_keyword (dis_info, keyword_table, value, attrs) - void *dis_info; - struct cgen_keyword *keyword_table; - long value; - CGEN_ATTR *attrs; + void * dis_info; + CGEN_KEYWORD * keyword_table; + long value; + CGEN_ATTR * attrs; { - disassemble_info *info = dis_info; - const struct cgen_keyword_entry *ke; + disassemble_info * info = dis_info; + const CGEN_KEYWORD_ENTRY * ke; ke = cgen_keyword_lookup_value (keyword_table, value); - if (ke != NULL) - (*info->fprintf_func) (info->stream, "%s", ke->name); - else - (*info->fprintf_func) (info->stream, "???"); + info->fprintf_func (info->stream, "%s", ke == NULL ? "???" : ke->name); } /* -- disassembler routines inserted here */ -/* -- dis.c */ - -#undef CGEN_PRINT_INSN -#define CGEN_PRINT_INSN my_print_insn - -static int -my_print_insn (pc, info, buf, buflen) - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; -{ - unsigned long insn_value; - - /* 32 bit insn? */ - if ((pc & 3) == 0 && (buf[0] & 0x80) != 0) - return print_insn (pc, info, buf, buflen); - - /* Print the first insn. */ - if ((pc & 3) == 0) - { - if (print_insn (pc, info, buf, 16) == 0) - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - buf += 2; - } - - if (buf[0] & 0x80) - { - /* Parallel. */ - (*info->fprintf_func) (info->stream, " || "); - buf[0] &= 0x7f; - } - else - (*info->fprintf_func) (info->stream, " -> "); - - /* The "& 3" is to ensure the branch address is computed correctly - [if it is a branch]. */ - if (print_insn (pc & ~ (bfd_vma) 3, info, buf, 16) == 0) - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - - return (pc & 3) ? 2 : 4; -} - -/* -- */ - -/* Main entry point for operand extraction. - - This function is basically just a big switch statement. Earlier versions - used tables to look up the function to use, but - - if the table contains both assembler and disassembler functions then - the disassembler contains much of the assembler and vice-versa, - - there's a lot of inlining possibilities as things grow, - - using a switch statement avoids the function call overhead. - - This function could be moved into `print_insn_normal', but keeping it - separate makes clear the interface between `print_insn_normal' and each of - the handlers. -*/ - -CGEN_INLINE int -m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields) - int opindex; - void *buf_ctrl; - cgen_insn_t insn_value; - struct cgen_fields *fields; -{ - int length; - - switch (opindex) - { - case 0 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); - break; - case 1 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); - break; - case 2 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); - break; - case 3 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); - break; - case 4 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); - break; - case 5 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); - break; - case 6 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm8); - break; - case 7 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16); - break; - case 8 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm4); - break; - case 9 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm5); - break; - case 10 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm16); - break; - case 11 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_hi16); - break; - case 12 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16); - break; - case 13 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm16); - break; - case 14 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm24); - break; - case 15 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp8); - break; - case 16 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp16); - break; - case 17 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp24); - break; - - default : - fprintf (stderr, "Unrecognized field %d while decoding insn.\n", - opindex); - abort (); - } - - return length; -} - -/* Main entry point for printing operands. - - This function is basically just a big switch statement. Earlier versions - used tables to look up the function to use, but - - if the table contains both assembler and disassembler functions then - the disassembler contains much of the assembler and vice-versa, - - there's a lot of inlining possibilities as things grow, - - using a switch statement avoids the function call overhead. - - This function could be moved into `print_insn_normal', but keeping it - separate makes clear the interface between `print_insn_normal' and each of - the handlers. -*/ - -CGEN_INLINE void -m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length) - int opindex; - disassemble_info *info; - struct cgen_fields *fields; - int attrs; - bfd_vma pc; - int length; -{ - switch (opindex) - { - case 0 : - print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_r2, 0|(1<f_r2, 0|(1<f_r1, 0|(1<f_simm8, 0, pc, length); - break; - case 7 : - print_normal (info, fields->f_simm16, 0, pc, length); - break; - case 8 : - print_normal (info, fields->f_uimm4, 0|(1<f_uimm5, 0|(1<f_uimm16, 0|(1<f_hi16, 0|(1<f_simm16, 0, pc, length); - break; - case 13 : - print_normal (info, fields->f_uimm16, 0|(1<f_uimm24, 0|(1<f_disp8, 0|(1<f_disp16, 0|(1<f_disp24, 0|(1<syntax; *syn; ++syn) + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) { int length; - if (CGEN_SYNTAX_CHAR_P (*syn)) + if (CGEN_SYNTAX_CHAR_P (* syn)) continue; - length = m32r_cgen_extract_operand (CGEN_SYNTAX_FIELD (*syn), + length = m32r_cgen_extract_operand (CGEN_SYNTAX_FIELD (* syn), buf_ctrl, insn_value, fields); if (length == 0) return 0; } - /* We recognized and successfully extracted this insn. - If a length is recorded with this insn, it has a fixed length. - Otherwise we require the syntax string to have a fake operand which - sets the `length' field in `flds'. */ - /* FIXME: wip */ - if (syntax->length > 0) - return syntax->length; - return fields->length; + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); } /* Default insn printer. @@ -433,28 +188,33 @@ extract_insn_normal (insn, buf_ctrl, insn_value, fields) static void print_insn_normal (dis_info, insn, fields, pc, length) - void *dis_info; - const struct cgen_insn *insn; - struct cgen_fields *fields; - bfd_vma pc; - int length; + void * dis_info; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + bfd_vma pc; + int length; { - const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn); - disassemble_info *info = dis_info; - const unsigned char *syn; + const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info * info = dis_info; + const unsigned char * syn; CGEN_INIT_PRINT (); - for (syn = syntax->syntax; *syn; ++syn) + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) { - if (CGEN_SYNTAX_CHAR_P (*syn)) + if (CGEN_SYNTAX_MNEMONIC_P (* syn)) + { + info->fprintf_func (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (* syn)) { - (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + info->fprintf_func (info->stream, "%c", CGEN_SYNTAX_CHAR (* syn)); continue; } /* We have an operand. */ - m32r_cgen_print_operand (CGEN_SYNTAX_FIELD (*syn), info, + m32r_cgen_print_operand (CGEN_SYNTAX_FIELD (* syn), info, fields, CGEN_INSN_ATTRS (insn), pc, length); } } @@ -471,15 +231,16 @@ print_insn_normal (dis_info, insn, fields, pc, length) static int print_insn (pc, info, buf, buflen) - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; + bfd_vma pc; + disassemble_info * info; + char * buf; + int buflen; { - int i; - unsigned long insn_value; - const CGEN_INSN_LIST *insn_list; - + int i; + unsigned long insn_value; + const CGEN_INSN_LIST * insn_list; + int extra_bytes; + switch (buflen) { case 8: @@ -495,16 +256,52 @@ print_insn (pc, info, buf, buflen) abort (); } + /* Special case - a 32 bit instruction which is actually two 16 bit instructions + being executed in parallel. */ + if (buflen == 32 + && ((insn_value & 0x80008000) == 0x00008000)) + { + if (info->endian == BFD_ENDIAN_BIG) + { + static char buf2 [4]; + + print_insn (pc, info, buf, 16); + + info->fprintf_func (info->stream, " || "); + + buf2 [0] = buf [2] & ~ 0x80; + buf2 [1] = buf [3]; + buf2 [2] = 0; + buf2 [3] = 0; + buf = buf2; + + insn_value <<= 17; + insn_value >>= 1; + } + else + { + print_insn (pc, info, buf + 2, 16); + + info->fprintf_func (info->stream, " || "); + + insn_value &= 0x7fff; + } + + pc += 2; + extra_bytes = 2; + } + else + extra_bytes = 0; + /* The instructions are stored in hash lists. Pick the first one and keep trying until we find the right one. */ insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value); + while (insn_list != NULL) { - const CGEN_INSN *insn = insn_list->insn; - const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn); - struct cgen_fields fields; - int length; + const CGEN_INSN * insn = insn_list->insn; + unsigned long value; #if 0 /* not needed as insn shouldn't be in hash lists if not supported */ /* Supported by this cpu? */ @@ -512,28 +309,43 @@ print_insn (pc, info, buf, buflen) continue; #endif + /* If we are looking at a 16 bit insn we may have to adjust the value being examined. */ + value = insn_value; + if (CGEN_INSN_BITSIZE (insn) == 16) + { + /* If this is a big endian target, + and we have read 32 bits for the instruction value, + then we must examine the top 16 bits, not the bottom. */ + if (buflen == 32 && info->endian == BFD_ENDIAN_BIG) + value >>= 16; + } + /* Basic bit mask must be correct. */ /* ??? May wish to allow target to defer this check until the extract handler. */ - if ((insn_value & syntax->mask) == syntax->value) + if ((value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn)) { + CGEN_FIELDS fields; + int length; + /* Printing is handled in two passes. The first pass parses the machine insn and extracts the fields. The second pass prints them. */ - length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, &fields); + length = CGEN_EXTRACT_FN (insn) (insn, NULL, value, & fields); if (length > 0) { - (*CGEN_PRINT_FN (insn)) (info, insn, &fields, pc, length); + CGEN_PRINT_FN (insn) (info, insn, & fields, pc, length); + /* length is in bits, result is in bytes */ - return length / 8; + return (length / 8) + extra_bytes; } } - + insn_list = CGEN_DIS_NEXT_INSN (insn_list); } - return 0; + return extra_bytes; } /* Main entry point. @@ -542,44 +354,58 @@ print_insn (pc, info, buf, buflen) int print_insn_m32r (pc, info) - bfd_vma pc; - disassemble_info *info; + bfd_vma pc; + disassemble_info * info; { - char buffer[CGEN_MAX_INSN_SIZE]; - int status, length; - static int initialized = 0; - static int current_mach = 0; - static int current_big_p = 0; - int mach = info->mach; - int big_p = info->endian == BFD_ENDIAN_BIG; + char buffer [CGEN_MAX_INSN_SIZE]; + int status; + int length; + static int initialized = 0; + static int current_mach = 0; + static int current_bigend = 0; + int mach = info->mach; + int bigend = info->endian == BFD_ENDIAN_BIG; /* If we haven't initialized yet, or if we've switched cpu's, initialize. */ - if (!initialized || mach != current_mach || big_p != current_big_p) + if (!initialized || mach != current_mach || bigend != current_bigend) { - initialized = 1; - current_mach = mach; - current_big_p = big_p; - m32r_cgen_init_dis (mach, big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); + initialized = 1; + current_mach = mach; + current_bigend = bigend; + + m32r_cgen_init_dis (mach, bigend ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); } /* Read enough of the insn so we can look it up in the hash lists. */ - status = (*info->read_memory_func) (pc, buffer, CGEN_BASE_INSN_SIZE, info); + status = info->read_memory_func (pc, buffer, CGEN_BASE_INSN_SIZE, info); if (status != 0) { - (*info->memory_error_func) (status, pc, info); + /* Try reading a 16 bit instruction. */ + info->bytes_per_chunk = 2; + status = info->read_memory_func (pc, buffer, CGEN_BASE_INSN_SIZE / 2, info); + buffer [2] = buffer [3] = 0; + } + if (status != 0) + { + info->memory_error_func (status, pc, info); return -1; } /* We try to have as much common code as possible. But at this point some targets need to take over. */ /* ??? Some targets may need a hook elsewhere. Try to avoid this, - but if not possible, try to move this hook elsewhere rather than + but if not possible try to move this hook elsewhere rather than have two hooks. */ length = CGEN_PRINT_INSN (pc, info, buffer, CGEN_BASE_INSN_BITSIZE); + if (length) return length; - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + info->fprintf_func (info->stream, UNKNOWN_INSN_MSG); + return CGEN_DEFAULT_INSN_SIZE; } + +/* Get the generate machine specific code. */ +#include "m32r-dis.in" diff --git a/opcodes/m32r-dis.in b/opcodes/m32r-dis.in new file mode 100644 index 0000000..3e5fb7f --- /dev/null +++ b/opcodes/m32r-dis.in @@ -0,0 +1,252 @@ +/* -- dis.c */ + +#undef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN my_print_insn + +static int +my_print_insn (pc, info, buf, buflen) + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; +{ + /* 32 bit insn? */ + if ((pc & 3) == 0 && (buf[0] & 0x80) != 0) + return print_insn (pc, info, buf, buflen); + + /* Print the first insn. */ + if ((pc & 3) == 0) + { + if (print_insn (pc, info, buf, 16) == 0) + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + buf += 2; + } + + if (buf[0] & 0x80) + { + /* Parallel. */ + (*info->fprintf_func) (info->stream, " || "); + buf[0] &= 0x7f; + } + else + (*info->fprintf_func) (info->stream, " -> "); + + /* The "& 3" is to ensure the branch address is computed correctly + [if it is a branch]. */ + if (print_insn (pc & ~ (bfd_vma) 3, info, buf, 16) == 0) + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + + return (pc & 3) ? 2 : 4; +} + +/* -- */ + +/* Main entry point for operand extraction. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. +*/ + +CGEN_INLINE int +m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields) + int opindex; + void *buf_ctrl; + cgen_insn_t insn_value; + CGEN_FIELDS *fields; +{ + int length; + + switch (opindex) + { + case M32R_OPERAND_SR : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); + break; + case M32R_OPERAND_DR : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); + break; + case M32R_OPERAND_SRC1 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); + break; + case M32R_OPERAND_SRC2 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); + break; + case M32R_OPERAND_SCR : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); + break; + case M32R_OPERAND_DCR : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); + break; + case M32R_OPERAND_SIMM8 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm8); + break; + case M32R_OPERAND_SIMM16 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16); + break; + case M32R_OPERAND_UIMM4 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm4); + break; + case M32R_OPERAND_UIMM5 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm5); + break; + case M32R_OPERAND_UIMM16 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm16); + break; + case M32R_OPERAND_ACC_S : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_acc_s); + break; + case M32R_OPERAND_ACC : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_acc); + break; + case M32R_OPERAND_HI16 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_hi16); + break; + case M32R_OPERAND_SLO16 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16); + break; + case M32R_OPERAND_ULO16 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm16); + break; + case M32R_OPERAND_UIMM24 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm24); + break; + case M32R_OPERAND_DISP8 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp8); + break; + case M32R_OPERAND_DISP16 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp16); + break; + case M32R_OPERAND_DISP24 : + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp24); + break; + + default : + fprintf (stderr, "Unrecognized field %d while decoding insn.\n", + opindex); + abort (); + } + + return length; +} + +/* Main entry point for printing operands. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. +*/ + +CGEN_INLINE void +m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length) + int opindex; + disassemble_info *info; + CGEN_FIELDS *fields; + void const * attrs; + bfd_vma pc; + int length; +{ + switch (opindex) + { + case M32R_OPERAND_SR : + print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_r2, 0|(1<f_r2, 0|(1<f_r1, 0|(1<f_simm8, 0, pc, length); + break; + case M32R_OPERAND_SIMM16 : + print_normal (info, fields->f_simm16, 0, pc, length); + break; + case M32R_OPERAND_UIMM4 : + print_normal (info, fields->f_uimm4, 0|(1<f_uimm5, 0|(1<f_uimm16, 0|(1<f_acc_s, 0|(1<f_acc, 0|(1<f_hi16, 0|(1<f_simm16, 0, pc, length); + break; + case M32R_OPERAND_ULO16 : + print_normal (info, fields->f_uimm16, 0|(1<f_uimm24, 0|(1<f_disp8, 0|(1<f_disp16, 0|(1<f_disp24, 0|(1< #include "ansidecl.h" #include "libiberty.h" #include "bfd.h" #include "m32r-opc.h" -struct cgen_keyword_entry m32r_cgen_opval_mach_entries[] = { - { "m32r", 0 }, - { "test", 1 } +/* Attributes. */ + +static const CGEN_ATTR_ENTRY MACH_attr[] = { + { "m32r", MACH_M32R }, + { "m32rx", MACH_M32RX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY PIPE_attr[] = { + { "NONE", PIPE_NONE }, + { "O", PIPE_O }, + { "S", PIPE_S }, + { "OS", PIPE_OS }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = { + { "ABS-ADDR", NULL }, + { "FAKE", NULL }, + { "NEGATIVE", NULL }, + { "PC", NULL }, + { "PCREL-ADDR", NULL }, + { "RELAX", NULL }, + { "RELOC", NULL }, + { "SIGN-OPT", NULL }, + { "UNSIGNED", NULL }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = { + { "MACH", & MACH_attr[0] }, + { "PIPE", & PIPE_attr[0] }, + { "ALIAS", NULL }, + { "COND-CTI", NULL }, + { "FILL-SLOT", NULL }, + { "PARALLEL", NULL }, + { "RELAX", NULL }, + { "RELAX-BC", NULL }, + { "RELAX-BCL", NULL }, + { "RELAX-BL", NULL }, + { "RELAX-BNC", NULL }, + { "RELAX-BNCL", NULL }, + { "RELAX-BRA", NULL }, + { "RELAXABLE", NULL }, + { "UNCOND-CTI", NULL }, + { 0, 0 } }; -struct cgen_keyword m32r_cgen_opval_mach = { +CGEN_KEYWORD_ENTRY m32r_cgen_opval_mach_entries[] = { + { "m32r", MACH_M32R }, + { "m32rx", MACH_M32RX } +}; + +CGEN_KEYWORD m32r_cgen_opval_mach = { & m32r_cgen_opval_mach_entries[0], 2 }; -struct cgen_keyword_entry m32r_cgen_opval_h_gr_entries[] = { +CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] = { { "fp", 13 }, { "lr", 14 }, { "sp", 15 }, @@ -62,12 +110,12 @@ struct cgen_keyword_entry m32r_cgen_opval_h_gr_entries[] = { { "r15", 15 } }; -struct cgen_keyword m32r_cgen_opval_h_gr = { +CGEN_KEYWORD m32r_cgen_opval_h_gr = { & m32r_cgen_opval_h_gr_entries[0], 19 }; -struct cgen_keyword_entry m32r_cgen_opval_h_cr_entries[] = { +CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] = { { "psw", 0 }, { "cbr", 1 }, { "spi", 2 }, @@ -82,14 +130,24 @@ struct cgen_keyword_entry m32r_cgen_opval_h_cr_entries[] = { { "cr6", 6 } }; -struct cgen_keyword m32r_cgen_opval_h_cr = { +CGEN_KEYWORD m32r_cgen_opval_h_cr = { & m32r_cgen_opval_h_cr_entries[0], 12 }; +CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] = { + { "a0", 0 }, + { "a1", 1 } +}; + +CGEN_KEYWORD m32r_cgen_opval_h_accums = { + & m32r_cgen_opval_h_accums_entries[0], + 2 +}; + static CGEN_HW_ENTRY m32r_cgen_hw_entries[] = { - { & m32r_cgen_hw_entries[1], "pc", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[1], "h-pc", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[2], "h-memory", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[3], "h-sint", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[4], "h-uint", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, @@ -101,18 +159,22 @@ static CGEN_HW_ENTRY m32r_cgen_hw_entries[] = { { & m32r_cgen_hw_entries[10], "h-gr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_gr }, { & m32r_cgen_hw_entries[11], "h-cr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_cr }, { & m32r_cgen_hw_entries[12], "h-accum", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, - { & m32r_cgen_hw_entries[13], "h-cond", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, - { & m32r_cgen_hw_entries[14], "h-sm", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, - { & m32r_cgen_hw_entries[15], "h-bsm", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, - { & m32r_cgen_hw_entries[16], "h-ie", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, - { & m32r_cgen_hw_entries[17], "h-bie", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, - { & m32r_cgen_hw_entries[18], "h-bcond", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[13], "h-accums", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_accums }, + { & m32r_cgen_hw_entries[14], "h-abort", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[15], "h-cond", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[16], "h-sm", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[17], "h-bsm", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[18], "h-ie", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[19], "h-bie", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, + { & m32r_cgen_hw_entries[20], "h-bcond", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { NULL, "h-bpc", CGEN_ASM_KEYWORD /*FIXME*/, 0 } }; -const struct cgen_operand m32r_cgen_operand_table[CGEN_NUM_OPERANDS] = +const CGEN_OPERAND m32r_cgen_operand_table[CGEN_NUM_OPERANDS] = { +/* pc: program counter */ + { "pc", 0, 0, { 0, 0|(1< $dr,$sr */ +/* 0 */ { OP, ' ', 130, ',', 129, 0 }, +/* $dr,$sr,$slo16 */ +/* 1 */ { OP, ' ', 130, ',', 129, ',', 143, 0 }, +/* $dr,$sr,$uimm16 */ +/* 2 */ { OP, ' ', 130, ',', 129, ',', 139, 0 }, +/* $dr,$sr,$ulo16 */ +/* 3 */ { OP, ' ', 130, ',', 129, ',', 144, 0 }, +/* $dr,$simm8 */ +/* 4 */ { OP, ' ', 130, ',', 135, 0 }, +/* $dr,$sr,$simm16 */ +/* 5 */ { OP, ' ', 130, ',', 129, ',', 136, 0 }, +/* $disp8 */ +/* 6 */ { OP, ' ', 146, 0 }, +/* $disp24 */ +/* 7 */ { OP, ' ', 148, 0 }, +/* $src1,$src2,$disp16 */ +/* 8 */ { OP, ' ', 131, ',', 132, ',', 147, 0 }, +/* $src2,$disp16 */ +/* 9 */ { OP, ' ', 132, ',', 147, 0 }, +/* $src1,$src2 */ +/* 10 */ { OP, ' ', 131, ',', 132, 0 }, +/* $src2,$simm16 */ +/* 11 */ { OP, ' ', 132, ',', 136, 0 }, +/* $src2,$uimm16 */ +/* 12 */ { OP, ' ', 132, ',', 139, 0 }, +/* $src2 */ +/* 13 */ { OP, ' ', 132, 0 }, +/* $sr */ +/* 14 */ { OP, ' ', 129, 0 }, +/* $dr,@$sr */ +/* 15 */ { OP, ' ', 130, ',', '@', 129, 0 }, +/* $dr,@($sr) */ +/* 16 */ { OP, ' ', 130, ',', '@', '(', 129, ')', 0 }, +/* $dr,@($slo16,$sr) */ +/* 17 */ { OP, ' ', 130, ',', '@', '(', 143, ',', 129, ')', 0 }, +/* $dr,@($sr,$slo16) */ +/* 18 */ { OP, ' ', 130, ',', '@', '(', 129, ',', 143, ')', 0 }, +/* $dr,@$sr+ */ +/* 19 */ { OP, ' ', 130, ',', '@', 129, '+', 0 }, +/* $dr,$uimm24 */ +/* 20 */ { OP, ' ', 130, ',', 145, 0 }, +/* $dr,$slo16 */ +/* 21 */ { OP, ' ', 130, ',', 143, 0 }, +/* $src1,$src2,$acc */ +/* 22 */ { OP, ' ', 131, ',', 132, ',', 141, 0 }, +/* $dr */ +/* 23 */ { OP, ' ', 130, 0 }, +/* $dr,$accs */ +/* 24 */ { OP, ' ', 130, ',', 141, 0 }, +/* $dr,$scr */ +/* 25 */ { OP, ' ', 130, ',', 133, 0 }, +/* $src1 */ +/* 26 */ { OP, ' ', 131, 0 }, +/* $src1,$accs */ +/* 27 */ { OP, ' ', 131, ',', 141, 0 }, +/* $sr,$dcr */ +/* 28 */ { OP, ' ', 129, ',', 134, 0 }, +/* */ +/* 29 */ { OP, 0 }, +/* $acc-s */ +/* 30 */ { OP, ' ', 141, 0 }, +/* $dr,$hi16 */ +/* 31 */ { OP, ' ', 130, ',', 142, 0 }, +/* $dr,$uimm5 */ +/* 32 */ { OP, ' ', 130, ',', 138, 0 }, +/* $src1,@$src2 */ +/* 33 */ { OP, ' ', 131, ',', '@', 132, 0 }, +/* $src1,@($src2) */ +/* 34 */ { OP, ' ', 131, ',', '@', '(', 132, ')', 0 }, +/* $src1,@($slo16,$src2) */ +/* 35 */ { OP, ' ', 131, ',', '@', '(', 143, ',', 132, ')', 0 }, +/* $src1,@($src2,$slo16) */ +/* 36 */ { OP, ' ', 131, ',', '@', '(', 132, ',', 143, ')', 0 }, +/* $src1,@+$src2 */ +/* 37 */ { OP, ' ', 131, ',', '@', '+', 132, 0 }, +/* $src1,@-$src2 */ +/* 38 */ { OP, ' ', 131, ',', '@', '-', 132, 0 }, +/* $uimm4 */ +/* 39 */ { OP, ' ', 137, 0 }, +/* $dr,$src2 */ +/* 40 */ { OP, ' ', 130, ',', 132, 0 }, +}; + +#undef OP + +static const CGEN_FORMAT format_table[] = { +/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */ +/* 0 */ { 16, 16, 0xf0f0 }, +/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16. */ +/* 1 */ { 32, 32, 0xf0f00000 }, +/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.uimm16. */ +/* 2 */ { 32, 32, 0xf0f00000 }, +/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.ulo16. */ +/* 3 */ { 32, 32, 0xf0f00000 }, +/* f-op1.number.f-r1.dr.f-simm8.simm8. */ +/* 4 */ { 16, 16, 0xf000 }, +/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.simm16. */ +/* 5 */ { 32, 32, 0xf0f00000 }, +/* f-op1.number.f-r1.number.f-disp8.disp8. */ +/* 6 */ { 16, 16, 0xff00 }, +/* f-op1.number.f-r1.number.f-disp24.disp24. */ +/* 7 */ { 32, 32, 0xff000000 }, +/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-disp16.disp16. */ +/* 8 */ { 32, 32, 0xf0f00000 }, +/* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-disp16.disp16. */ +/* 9 */ { 32, 32, 0xfff00000 }, +/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2. */ +/* 10 */ { 16, 16, 0xf0f0 }, +/* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-simm16.simm16. */ +/* 11 */ { 32, 32, 0xfff00000 }, +/* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-uimm16.uimm16. */ +/* 12 */ { 32, 32, 0xfff00000 }, +/* f-op1.number.f-r1.number.f-op2.number.f-r2.src2. */ +/* 13 */ { 16, 16, 0xfff0 }, +/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.number. */ +/* 14 */ { 32, 32, 0xf0f0ffff }, +/* f-op1.number.f-r1.number.f-op2.number.f-r2.sr. */ +/* 15 */ { 16, 16, 0xfff0 }, +/* f-op1.number.f-r1.dr.f-uimm24.uimm24. */ +/* 16 */ { 32, 32, 0xf0000000 }, +/* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-simm16.slo16. */ +/* 17 */ { 32, 32, 0xf0ff0000 }, +/* f-op1.number.f-r1.src1.f-acc.acc.f-op23.number.f-r2.src2. */ +/* 18 */ { 16, 16, 0xf070 }, +/* f-op1.number.f-r1.dr.f-op2.number.f-r2.number. */ +/* 19 */ { 16, 16, 0xf0ff }, +/* f-op1.number.f-r1.dr.f-op2.number.f-acc-s.acc-s.f-op3.number. */ +/* 20 */ { 16, 16, 0xf0f3 }, +/* f-op1.number.f-r1.dr.f-op2.number.f-r2.scr. */ +/* 21 */ { 16, 16, 0xf0f0 }, +/* f-op1.number.f-r1.src1.f-op2.number.f-r2.number. */ +/* 22 */ { 16, 16, 0xf0ff }, +/* f-op1.number.f-r1.src1.f-op2.number.f-acc-s.acc-s.f-op3.number. */ +/* 23 */ { 16, 16, 0xf0f3 }, +/* f-op1.number.f-r1.dcr.f-op2.number.f-r2.sr. */ +/* 24 */ { 16, 16, 0xf0f0 }, +/* f-op1.number.f-r1.number.f-op2.number.f-r2.number. */ +/* 25 */ { 16, 16, 0xffff }, +/* f-op1.number.f-r1.number.f-op2.number.f-acc-s.acc-s.f-op3.number. */ +/* 26 */ { 16, 16, 0xfff3 }, +/* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-hi16.hi16. */ +/* 27 */ { 32, 32, 0xf0ff0000 }, +/* f-op1.number.f-r1.dr.f-shift-op2.number.f-uimm5.uimm5. */ +/* 28 */ { 16, 16, 0xf0e0 }, +/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16. */ +/* 29 */ { 32, 32, 0xf0f00000 }, +/* f-op1.number.f-r1.number.f-op2.number.f-uimm4.uimm4. */ +/* 30 */ { 16, 16, 0xfff0 }, +/* f-op1.number.f-r1.dr.f-op2.number.f-r2.src2.f-uimm16.number. */ +/* 31 */ { 32, 32, 0xf0f0ffff }, }; -const struct cgen_insn m32r_cgen_insn_table_entries[CGEN_NUM_INSNS] = { +#define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a)) +#define SYN(n) (& syntax_table[n]) +#define FMT(n) (& format_table[n]) + +const CGEN_INSN m32r_cgen_insn_table_entries[CGEN_NUM_INSNS] = { /* null first entry, end of all hash chains */ - { { 0 }, { 0 } }, + { { 0 }, 0 }, /* add $dr,$sr */ { - { 1, 1, 1, 1, { 0, 0, { 0 } } }, - { "add $dr,$sr", "add", "add", {'a', 'd', 'd', ' ', 129, ',', 128, }, 0xf0f0, 0xa0, 16 } + { 1, 1, 1, 1 }, + "add", "add", SYN (0), FMT (0), 0xa0, + { 2, 0|A(PARALLEL), { [CGEN_INSN_PIPE] = PIPE_OS } } }, /* add3 $dr,$sr,$slo16 */ { - { 1, 1, 1, 1, { 0, 0, { 0 } } }, - { "add3 $dr,$sr,$slo16", "add3", "add3", {'a', 'd', 'd', '3', ' ', 129, ',', 128, ',', 140, }, 0xf0f00000, 0x80a00000, 32 } + { 1, 1, 1, 1 }, + "add3", "add3", SYN (1), FMT (1), 0x80a00000, + { 2, 0, { 0 } } }, /* and $dr,$sr */ { - { 1, 1, 1, 1, { 0, 0, { 0 } } }, - { "and $dr,$sr", "and", "and", {'a', 'n', 'd', ' ', 129, ',', 128, }, 0xf0f0, 0xc0, 16 } + { 1, 1, 1, 1 }, + "and", "and", SYN (0), FMT (0), 0xc0, + { 2, 0|A(PARALLEL), { [CGEN_INSN_PIPE] = PIPE_OS } } }, /* and3 $dr,$sr,$uimm16 */ { - { 1, 1, 1, 1, { 0, 0, { 0 } } }, - { "and3 $dr,$sr,$uimm16", "and3", "and3", {'a', 'n', 'd', '3', ' ', 129, ',', 128, ',', 138, }, 0xf0f00000, 0x80c00000, 32 } + { 1, 1, 1, 1 }, + "and3", "and3", SYN (2), FMT (2), 0x80c00000, + { 2, 0, { 0 } } }, /* or $dr,$sr */ { - { 1, 1, 1, 1, { 0, 0, { 0 } } }, - { "or $dr,$sr", "or", "or", {'o', 'r', ' ', 129, ',', 128, }, 0xf0f0, 0xe0, 16 } + { 1, 1, 1, 1 }, + "or", "or", SYN (0), FMT (0), 0xe0, + { 2, 0|A(PARALLEL), { [CGEN_INSN_PIPE] = PIPE_OS } } }, /* or3 $dr,$sr,$ulo16 */ { - { 1, 1, 1, 1, { 0, 0, { 0 } } }, - { "or3 $dr,$sr,$ulo16", "or3", "or3", {'o', 'r', '3', ' ', 129, ',', 128, ',', 141, }, 0xf0f00000, 0x80e00000, 32 } + { 1, 1, 1, 1 }, + "or3", "or3", SYN (3), FMT (3), 0x80e00000, + { 2, 0, { 0 } } }, /* xor $dr,$sr */ { - { 1, 1, 1, 1, { 0, 0, { 0 } } }, - { "xor $dr,$sr", "xor", "xor", {'x', 'o', 'r', ' ', 129, ',', 128, }, 0xf0f0, 0xd0, 16 } + { 1, 1, 1, 1 }, + "xor", "xor", SYN (0), FMT (0), 0xd0, + { 2, 0|A(PARALLEL), { [CGEN_INSN_PIPE] = PIPE_OS } } }, /* xor3 $dr,$sr,$uimm16 */ { - { 1, 1, 1, 1, { 0, 0, { 0 } } }, - { "xor3 $dr,$sr,$uimm16", "xor3", "xor3", {'x', 'o', 'r', '3', ' ', 129, ',', 128, ',', 138, }, 0xf0f00000, 0x80d00000, 32 } + { 1, 1, 1, 1 }, + "xor3", "xor3", SYN (2), FMT (2), 0x80d00000, + { 2, 0, { 0 } } }, /* addi $dr,$simm8 */ { - { 1, 1, 1, 1, { 0, 0, { 0 } } }, - { "addi $dr,$simm8", "addi", "addi", {'a', 'd', 'd', 'i', ' ', 129, ',', 134, }, 0xf000, 0x4000, 16 } + { 1, 1, 1, 1 }, + "addi", "addi", SYN (4), FMT (4), 0x4000, + { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } } }, /* addv $dr,$sr */ { - { 1, 1, 1, 1, { 0, 0, { 0 } } }, - { "addv $dr,$sr", "addv", "addv", {'a', 'd', 'd', 'v', ' ', 129, ',', 128, }, 0xf0f0, 0x80, 16 } + { 1, 1, 1, 1 }, + "addv", "addv", SYN (0), FMT (0), 0x80, + { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } } }, /* addv3 $dr,$sr,$simm16 */ { - { 1, 1, 1, 1, { 0, 0, { 0 } } }, - { "addv3 $dr,$sr,$simm16", "addv3", "addv3", {'a', 'd', 'd', 'v', '3', ' ', 129, ',', 128, ',', 135, }, 0xf0f00000, 0x80800000, 32 } + { 1, 1, 1, 1 }, + "addv3", "addv3", SYN (5), FMT (5), 0x80800000, + { 2, 0, { 0 } } }, /* addx $dr,$sr */ { - { 1, 1, 1, 1, { 0, 0, { 0 } } }, - { "addx $dr,$sr", "addx", "addx", {'a', 'd', 'd', 'x', ' ', 129, ',', 128, }, 0xf0f0, 0x90, 16 } + { 1, 1, 1, 1 }, + "addx", "addx", SYN (0), FMT (0), 0x90, + { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } } }, /* bc $disp8 */ { - { 1, 1, 1, 1, { 0, 0|(1<f_r2 = *valuep; break; - case 1 : + case M32R_OPERAND_DR : fields->f_r1 = *valuep; break; - case 2 : + case M32R_OPERAND_SRC1 : fields->f_r1 = *valuep; break; - case 3 : + case M32R_OPERAND_SRC2 : fields->f_r2 = *valuep; break; - case 4 : + case M32R_OPERAND_SCR : fields->f_r2 = *valuep; break; - case 5 : + case M32R_OPERAND_DCR : fields->f_r1 = *valuep; break; - case 6 : + case M32R_OPERAND_SIMM8 : fields->f_simm8 = *valuep; break; - case 7 : + case M32R_OPERAND_SIMM16 : fields->f_simm16 = *valuep; break; - case 8 : + case M32R_OPERAND_UIMM4 : fields->f_uimm4 = *valuep; break; - case 9 : + case M32R_OPERAND_UIMM5 : fields->f_uimm5 = *valuep; break; - case 10 : + case M32R_OPERAND_UIMM16 : fields->f_uimm16 = *valuep; break; - case 11 : + case M32R_OPERAND_ACC_S : + fields->f_acc_s = *valuep; + break; + case M32R_OPERAND_ACC : + fields->f_acc = *valuep; + break; + case M32R_OPERAND_HI16 : fields->f_hi16 = *valuep; break; - case 12 : + case M32R_OPERAND_SLO16 : fields->f_simm16 = *valuep; break; - case 13 : + case M32R_OPERAND_ULO16 : fields->f_uimm16 = *valuep; break; - case 14 : + case M32R_OPERAND_UIMM24 : fields->f_uimm24 = *valuep; break; - case 15 : + case M32R_OPERAND_DISP8 : fields->f_disp8 = *valuep; break; - case 16 : + case M32R_OPERAND_DISP16 : fields->f_disp16 = *valuep; break; - case 17 : + case M32R_OPERAND_DISP24 : fields->f_disp24 = *valuep; break; @@ -905,64 +1503,70 @@ m32r_cgen_set_operand (opindex, valuep, fields) CGEN_INLINE long m32r_cgen_get_operand (opindex, fields) int opindex; - const struct cgen_fields *fields; + const CGEN_FIELDS *fields; { long value; switch (opindex) { - case 0 : + case M32R_OPERAND_SR : value = fields->f_r2; break; - case 1 : + case M32R_OPERAND_DR : value = fields->f_r1; break; - case 2 : + case M32R_OPERAND_SRC1 : value = fields->f_r1; break; - case 3 : + case M32R_OPERAND_SRC2 : value = fields->f_r2; break; - case 4 : + case M32R_OPERAND_SCR : value = fields->f_r2; break; - case 5 : + case M32R_OPERAND_DCR : value = fields->f_r1; break; - case 6 : + case M32R_OPERAND_SIMM8 : value = fields->f_simm8; break; - case 7 : + case M32R_OPERAND_SIMM16 : value = fields->f_simm16; break; - case 8 : + case M32R_OPERAND_UIMM4 : value = fields->f_uimm4; break; - case 9 : + case M32R_OPERAND_UIMM5 : value = fields->f_uimm5; break; - case 10 : + case M32R_OPERAND_UIMM16 : value = fields->f_uimm16; break; - case 11 : + case M32R_OPERAND_ACC_S : + value = fields->f_acc_s; + break; + case M32R_OPERAND_ACC : + value = fields->f_acc; + break; + case M32R_OPERAND_HI16 : value = fields->f_hi16; break; - case 12 : + case M32R_OPERAND_SLO16 : value = fields->f_simm16; break; - case 13 : + case M32R_OPERAND_ULO16 : value = fields->f_uimm16; break; - case 14 : + case M32R_OPERAND_UIMM24 : value = fields->f_uimm24; break; - case 15 : + case M32R_OPERAND_DISP8 : value = fields->f_disp8; break; - case 16 : + case M32R_OPERAND_DISP16 : value = fields->f_disp16; break; - case 17 : + case M32R_OPERAND_DISP24 : value = fields->f_disp24; break; diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h new file mode 100644 index 0000000..0c8f2f0 --- /dev/null +++ b/opcodes/m32r-opc.h @@ -0,0 +1,234 @@ +/* Instruction description for m32r. + +This file is machine generated. + +Copyright (C) 1996, 1997 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef m32r_OPC_H +#define m32r_OPC_H + +#define CGEN_ARCH m32r +/* Given symbol S, return m32r_cgen_. */ +#define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s) + +#define CGEN_WORD_BITSIZE 32 +#define CGEN_DEFAULT_INSN_BITSIZE 32 +#define CGEN_BASE_INSN_BITSIZE 32 +#define CGEN_MAX_INSN_BITSIZE 32 +#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8) +#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8) +#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8) +#define CGEN_INT_INSN + +/* +1 because the first entry is reserved (null) */ +#define CGEN_NUM_INSNS (165 + 1) +#define CGEN_NUM_OPERANDS (24) + +/* Number of non-boolean attributes. */ +#define CGEN_MAX_INSN_ATTRS 2 +#define CGEN_MAX_OPERAND_ATTRS 0 + +/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */ + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Number of architecture variants. */ +#define MAX_MACHS 2 + +/* Enums. */ + +/* Enum declaration for insn format enums. */ +typedef enum insn_op1 { + OP1_0 = 0, OP1_1 = 1, OP1_2 = 2, OP1_3 = 3, + OP1_4 = 4, OP1_5 = 5, OP1_6 = 6, OP1_7 = 7, + OP1_8 = 8, OP1_9 = 9, OP1_10 = 10, OP1_11 = 11, + OP1_12 = 12, OP1_13 = 13, OP1_14 = 14, OP1_15 = 15 +} INSN_OP1; + +/* Enum declaration for op2 enums. */ +typedef enum insn_op2 { + OP2_0 = 0, OP2_1 = 1, OP2_2 = 2, OP2_3 = 3, + OP2_4 = 4, OP2_5 = 5, OP2_6 = 6, OP2_7 = 7, + OP2_8 = 8, OP2_9 = 9, OP2_10 = 10, OP2_11 = 11, + OP2_12 = 12, OP2_13 = 13, OP2_14 = 14, OP2_15 = 15 +} INSN_OP2; + +/* Enum declaration for m32r operand types. */ +typedef enum cgen_operand_type { + M32R_OPERAND_PC = 0, M32R_OPERAND_SR = 1, M32R_OPERAND_DR = 2, M32R_OPERAND_SRC1 = 3, + M32R_OPERAND_SRC2 = 4, M32R_OPERAND_SCR = 5, M32R_OPERAND_DCR = 6, M32R_OPERAND_SIMM8 = 7, + M32R_OPERAND_SIMM16 = 8, M32R_OPERAND_UIMM4 = 9, M32R_OPERAND_UIMM5 = 10, M32R_OPERAND_UIMM16 = 11, + M32R_OPERAND_ACC_S = 12, M32R_OPERAND_ACC = 13, M32R_OPERAND_HI16 = 14, M32R_OPERAND_SLO16 = 15, + M32R_OPERAND_ULO16 = 16, M32R_OPERAND_UIMM24 = 17, M32R_OPERAND_DISP8 = 18, M32R_OPERAND_DISP16 = 19, + M32R_OPERAND_DISP24 = 20, M32R_OPERAND_CONDBIT = 21, M32R_OPERAND_ACCUM = 22, M32R_OPERAND_ABORT_PARALLEL_EXECUTION = 23 +} CGEN_OPERAND_TYPE; + +/* Non-boolean attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_M32R = 0, MACH_M32RX = 1 +} MACH_ATTR; + +/* Enum declaration for parallel execution pipeline selection. */ +typedef enum pipe_attr { + PIPE_NONE = 0, PIPE_O = 1, PIPE_S = 2, PIPE_OS = 3 +} PIPE_ATTR; + +/* Operand and instruction attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC, + CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT, + CGEN_OPERAND_UNSIGNED +} CGEN_OPERAND_ATTR; + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, + CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAX_BC, + CGEN_INSN_RELAX_BCL, CGEN_INSN_RELAX_BL, CGEN_INSN_RELAX_BNC, CGEN_INSN_RELAX_BNCL, + CGEN_INSN_RELAX_BRA, CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI +} CGEN_INSN_ATTR; + +/* Insn types are used by the simulator. */ +/* Enum declaration for m32r instruction types. */ +typedef enum cgen_insn_type { + M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND, + M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR, + M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3, + M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC8_S, M32R_INSN_BC24, + M32R_INSN_BC24_L, M32R_INSN_BEQ, M32R_INSN_BEQZ, M32R_INSN_BGEZ, + M32R_INSN_BGTZ, M32R_INSN_BLEZ, M32R_INSN_BLTZ, M32R_INSN_BNEZ, + M32R_INSN_BL8, M32R_INSN_BL8_S, M32R_INSN_BL24, M32R_INSN_BL24_L, + M32R_INSN_BCL8, M32R_INSN_BCL8_S, M32R_INSN_BCL24, M32R_INSN_BCL24_L, + M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L, + M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24, + M32R_INSN_BRA24_L, M32R_INSN_BNCL8, M32R_INSN_BNCL8_S, M32R_INSN_BNCL24, + M32R_INSN_BNCL24_L, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU, + M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV, + M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_JC, + M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, + M32R_INSN_LD_2, M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB, + M32R_INSN_LDB_2, M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH, + M32R_INSN_LDH_2, M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB, + M32R_INSN_LDUB_2, M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH, + M32R_INSN_LDUH_2, M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS, + M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI8A, M32R_INSN_LDI16, + M32R_INSN_LDI16A, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACHI_A, + M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI, M32R_INSN_MACWHI_A, + M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL, M32R_INSN_MULHI, + M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A, M32R_INSN_MULWHI, + M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A, M32R_INSN_MV, + M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO, M32R_INSN_MVFACLO_A, + M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC, M32R_INSN_MVTACHI, + M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A, M32R_INSN_MVTC, + M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC, + M32R_INSN_RAC_A, M32R_INSN_RACH, M32R_INSN_RACH_A, M32R_INSN_RTE, + M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3, M32R_INSN_SLLI, + M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI, M32R_INSN_SRL, + M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST, M32R_INSN_ST_2, + M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB, M32R_INSN_STB_2, + M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH, M32R_INSN_STH_2, + M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, + M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, + M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP, M32R_INSN_SATB, + M32R_INSN_SATH, M32R_INSN_SAT, M32R_INSN_PCMPBZ, M32R_INSN_SADD, + M32R_INSN_MACWU1, M32R_INSN_MSBLO, M32R_INSN_MULWU1, M32R_INSN_MACHL1, + M32R_INSN_SC, M32R_INSN_SNC, M32R_INSN_MAX +} CGEN_INSN_TYPE; + +/* Index of `illegal' insn place holder. */ +#define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL +/* Total number of insns in table. */ +#define CGEN_MAX_INSNS ((int) M32R_INSN_MAX) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +/* This struct records data prior to insertion or after extraction. */ +typedef struct cgen_fields { + long f_nil; + long f_op1; + long f_op2; + long f_cond; + long f_r1; + long f_r2; + long f_simm8; + long f_simm16; + long f_shift_op2; + long f_uimm4; + long f_uimm5; + long f_uimm16; + long f_uimm24; + long f_hi16; + long f_disp8; + long f_disp16; + long f_disp24; + long f_op23; + long f_op3; + long f_acc; + long f_acc_s; + int length; +} CGEN_FIELDS; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[]; + +extern CGEN_KEYWORD m32r_cgen_opval_mach; +extern CGEN_KEYWORD m32r_cgen_opval_h_gr; +extern CGEN_KEYWORD m32r_cgen_opval_h_cr; +extern CGEN_KEYWORD m32r_cgen_opval_h_accums; + +#define CGEN_INIT_PARSE() \ +{\ +} +#define CGEN_INIT_INSERT() \ +{\ +} +#define CGEN_INIT_EXTRACT() \ +{\ +} +#define CGEN_INIT_PRINT() \ +{\ +} + +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 256 +#undef CGEN_DIS_HASH +#define X(b) (((unsigned char *) (b))[0] & 0xf0) +#define CGEN_DIS_HASH(buffer, insn) \ +(X (buffer) | \ + (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \ + : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \ + : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4))) + +/* -- */ + + +#endif /* m32r_OPC_H */ -- 2.7.4