From 23ce94ff7e28ee1771f53931d20c0ed1fe87c4a5 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 21 Jun 2021 13:56:32 +0300 Subject: [PATCH] intel/nir/rt: add a new number of SIMD lanes per DSS helper v2: Add prefix brw_nir_rt (Caio) Signed-off-by: Lionel Landwerlin Reviewed-by: Caio Oliveira Part-of: --- src/intel/compiler/brw_nir_rt_builder.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/intel/compiler/brw_nir_rt_builder.h b/src/intel/compiler/brw_nir_rt_builder.h index 1ff439c..a220e0d 100644 --- a/src/intel/compiler/brw_nir_rt_builder.h +++ b/src/intel/compiler/brw_nir_rt_builder.h @@ -33,6 +33,15 @@ brw_load_btd_dss_id(nir_builder *b) return nir_build_load_topology_id_intel(b, .base = BRW_TOPOLOGY_ID_DSS); } +static inline nir_ssa_def * +brw_nir_rt_load_num_simd_lanes_per_dss(nir_builder *b, + const struct intel_device_info *devinfo) +{ + return nir_imm_int(b, devinfo->num_thread_per_eu * + devinfo->max_eus_per_subslice * + 16 /* The RT computation is based off SIMD16 */); +} + /* We have our own load/store scratch helpers because they emit a global * memory read or write based on the scratch_base_ptr system value rather * than a load/store_scratch intrinsic. -- 2.7.4