From 234eba90f4f346a4b0d260cdd61a9aae647b2b48 Mon Sep 17 00:00:00 2001
From: Changpeng Fang <changpeng.fang@gmail.com>
Date: Sat, 30 May 2020 20:45:27 -0700
Subject: [PATCH] AMDGPU: Add setTruncStoreAction for vector i64 types made
 legal recently

Reviewers:
  rampitec, arsenm

Differential Revision:
  https://reviews.llvm.org/D80853
---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp   |  6 ++++
 llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll | 50 +++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 452ff78..5d97b9f4 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -220,6 +220,12 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
   setTruncStoreAction(MVT::v16i16, MVT::v16i8, Expand);
   setTruncStoreAction(MVT::v32i16, MVT::v32i8, Expand);
 
+  setTruncStoreAction(MVT::v4i64, MVT::v4i8, Expand);
+  setTruncStoreAction(MVT::v8i64, MVT::v8i8, Expand);
+  setTruncStoreAction(MVT::v8i64, MVT::v8i16, Expand);
+  setTruncStoreAction(MVT::v8i64, MVT::v8i32, Expand);
+  setTruncStoreAction(MVT::v16i64, MVT::v16i32, Expand);
+
   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
   setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
 
diff --git a/llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll b/llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
new file mode 100644
index 0000000..627ba9e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
@@ -0,0 +1,50 @@
+; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}trunc_store_v4i64_v4i8:
+; GCN: global_store_dword v{{\[[0-9]:[0-9]+\]}}, v{{[0-9]+}}, off
+define amdgpu_kernel void @trunc_store_v4i64_v4i8(< 4 x i8> addrspace(1)* %out, <4 x i64> %in) {
+entry:
+  %trunc = trunc <4 x i64> %in to < 4 x i8>
+  store <4 x i8> %trunc, <4 x i8> addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}trunc_store_v8i64_v8i8:
+; GCN: global_store_dwordx2 v{{\[[0-9]:[0-9]+\]}}, v{{\[[0-9]:[0-9]+\]}}, off
+define amdgpu_kernel void @trunc_store_v8i64_v8i8(< 8 x i8> addrspace(1)* %out, <8 x i64> %in) {
+entry:
+  %trunc = trunc <8 x i64> %in to < 8 x i8>
+  store <8 x i8> %trunc, <8 x i8> addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}trunc_store_v8i64_v8i16:
+; GCN: global_store_dwordx4 v{{\[[0-9]:[0-9]+\]}}, v{{\[[0-9]:[0-9]+\]}}, off
+define amdgpu_kernel void @trunc_store_v8i64_v8i16(< 8 x i16> addrspace(1)* %out, <8 x i64> %in) {
+entry:
+  %trunc = trunc <8 x i64> %in to < 8 x i16>
+  store <8 x i16> %trunc, <8 x i16> addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}trunc_store_v8i64_v8i32:
+; GCN: global_store_dwordx4 v{{\[[0-9]:[0-9]+\]}}, v{{\[[0-9]:[0-9]+\]}}, off offset:16
+; GCN: global_store_dwordx4 v{{\[[0-9]:[0-9]+\]}}, v{{\[[0-9]:[0-9]+\]}}, off
+define amdgpu_kernel void @trunc_store_v8i64_v8i32(< 8 x i32> addrspace(1)* %out, <8 x i64> %in) {
+entry:
+  %trunc = trunc <8 x i64> %in to <8 x i32>
+  store <8 x i32> %trunc, <8 x i32> addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}trunc_store_v16i64_v16i32:
+; GCN: global_store_dwordx4 v{{\[[0-9]:[0-9]+\]}}, v{{\[[0-9]:[0-9]+\]}}, off offset:48
+; GCN: global_store_dwordx4 v{{\[[0-9]:[0-9]+\]}}, v{{\[[0-9]:[0-9]+\]}}, off offset:32
+; GCN: global_store_dwordx4 v{{\[[0-9]:[0-9]+\]}}, v{{\[[0-9]:[0-9]+\]}}, off offset:16
+; GCN: global_store_dwordx4 v{{\[[0-9]:[0-9]+\]}}, v{{\[[0-9]:[0-9]+\]}}, off
+define amdgpu_kernel void @trunc_store_v16i64_v16i32(< 16 x i32> addrspace(1)* %out, <16 x i64> %in) {
+entry:
+  %trunc = trunc <16 x i64> %in to <16 x i32>
+  store <16 x i32> %trunc, <16 x i32> addrspace(1)* %out
+  ret void
+}
-- 
2.7.4