From 22e99c434fb65ca8a9d5e3dbf5db5965681ce5c3 Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Wed, 5 Jun 2019 14:03:13 +0000 Subject: [PATCH] [MIPS GlobalISel] Select fcmp Select floating point compare for MIPS32. Differential Revision: https://reviews.llvm.org/D62721 llvm-svn: 362603 --- llvm/lib/Target/Mips/MipsInstructionSelector.cpp | 79 ++ llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 4 + llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 11 + .../Mips/GlobalISel/instruction-select/fcmp.mir | 1152 ++++++++++++++++++++ .../CodeGen/Mips/GlobalISel/legalizer/fcmp.mir | 73 ++ llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll | 438 ++++++++ .../CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir | 75 ++ 7 files changed, 1832 insertions(+) create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp index 442244a..8fddcca 100644 --- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp +++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp @@ -11,6 +11,7 @@ /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// +#include "MCTargetDesc/MipsInstPrinter.h" #include "MipsMachineFunction.h" #include "MipsRegisterBankInfo.h" #include "MipsTargetMachine.h" @@ -492,6 +493,84 @@ bool MipsInstructionSelector::select(MachineInstr &I, I.eraseFromParent(); return true; } + case G_FCMP: { + unsigned MipsFCMPCondCode; + bool isLogicallyNegated; + switch (CmpInst::Predicate Cond = static_cast( + I.getOperand(1).getPredicate())) { + case CmpInst::FCMP_UNO: // Unordered + case CmpInst::FCMP_ORD: // Ordered (OR) + MipsFCMPCondCode = Mips::FCOND_UN; + isLogicallyNegated = Cond != CmpInst::FCMP_UNO; + break; + case CmpInst::FCMP_OEQ: // Equal + case CmpInst::FCMP_UNE: // Not Equal (NEQ) + MipsFCMPCondCode = Mips::FCOND_OEQ; + isLogicallyNegated = Cond != CmpInst::FCMP_OEQ; + break; + case CmpInst::FCMP_UEQ: // Unordered or Equal + case CmpInst::FCMP_ONE: // Ordered or Greater Than or Less Than (OGL) + MipsFCMPCondCode = Mips::FCOND_UEQ; + isLogicallyNegated = Cond != CmpInst::FCMP_UEQ; + break; + case CmpInst::FCMP_OLT: // Ordered or Less Than + case CmpInst::FCMP_UGE: // Unordered or Greater Than or Equal (UGE) + MipsFCMPCondCode = Mips::FCOND_OLT; + isLogicallyNegated = Cond != CmpInst::FCMP_OLT; + break; + case CmpInst::FCMP_ULT: // Unordered or Less Than + case CmpInst::FCMP_OGE: // Ordered or Greater Than or Equal (OGE) + MipsFCMPCondCode = Mips::FCOND_ULT; + isLogicallyNegated = Cond != CmpInst::FCMP_ULT; + break; + case CmpInst::FCMP_OLE: // Ordered or Less Than or Equal + case CmpInst::FCMP_UGT: // Unordered or Greater Than (UGT) + MipsFCMPCondCode = Mips::FCOND_OLE; + isLogicallyNegated = Cond != CmpInst::FCMP_OLE; + break; + case CmpInst::FCMP_ULE: // Unordered or Less Than or Equal + case CmpInst::FCMP_OGT: // Ordered or Greater Than (OGT) + MipsFCMPCondCode = Mips::FCOND_ULE; + isLogicallyNegated = Cond != CmpInst::FCMP_ULE; + break; + default: + return false; + } + + // Default compare result in gpr register will be `true`. + // We will move `false` (MIPS::Zero) to gpr result when fcmp gives false + // using MOVF_I. When orignal predicate (Cond) is logically negated + // MipsFCMPCondCode, result is inverted i.e. MOVT_I is used. + unsigned MoveOpcode = isLogicallyNegated ? Mips::MOVT_I : Mips::MOVF_I; + + unsigned TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) + .addDef(TrueInReg) + .addUse(Mips::ZERO) + .addImm(1); + + unsigned Size = MRI.getType(I.getOperand(2).getReg()).getSizeInBits(); + unsigned FCMPOpcode = + Size == 32 ? Mips::FCMP_S32 + : STI.isFP64bit() ? Mips::FCMP_D64 : Mips::FCMP_D32; + MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode)) + .addUse(I.getOperand(2).getReg()) + .addUse(I.getOperand(3).getReg()) + .addImm(MipsFCMPCondCode); + if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI)) + return false; + + MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode)) + .addDef(I.getOperand(0).getReg()) + .addUse(Mips::ZERO) + .addUse(Mips::FCC0) + .addUse(TrueInReg); + if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI)) + return false; + + I.eraseFromParent(); + return true; + } default: return false; } diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index fcad2a9..cabaed8 100644 --- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -97,6 +97,10 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) .legalFor({s32, s64}); + getActionDefinitionsBuilder(G_FCMP) + .legalFor({{s32, s32}, {s32, s64}}) + .minScalar(0, s32); + computeTables(); verify(*ST.getInstrInfo()); } diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp index 4814ef4..0f9d106 100644 --- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -149,6 +149,17 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OperandsMapping = getOperandsMapping({FPRValueMapping, nullptr}); break; } + case G_FCMP: { + unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); + assert((Size == 32 || Size == 64) && "Unsupported floating point size"); + const RegisterBankInfo::ValueMapping *FPRValueMapping = + Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx] + : &Mips::ValueMappings[Mips::DPRIdx]; + OperandsMapping = + getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr, + FPRValueMapping, FPRValueMapping}); + break; + } case G_CONSTANT: case G_FRAME_INDEX: case G_GLOBAL_VALUE: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir new file mode 100644 index 0000000..b861dc6 --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir @@ -0,0 +1,1152 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32 +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64 +--- | + + define void @false_s() {entry: ret void} + define void @true_s() {entry: ret void} + define void @uno_s() {entry: ret void} + define void @ord_s() {entry: ret void} + define void @oeq_s() {entry: ret void} + define void @une_s() {entry: ret void} + define void @ueq_s() {entry: ret void} + define void @one_s() {entry: ret void} + define void @olt_s() {entry: ret void} + define void @uge_s() {entry: ret void} + define void @ult_s() {entry: ret void} + define void @oge_s() {entry: ret void} + define void @ole_s() {entry: ret void} + define void @ugt_s() {entry: ret void} + define void @ule_s() {entry: ret void} + define void @ogt_s() {entry: ret void} + + define void @false_d() {entry: ret void} + define void @true_d() {entry: ret void} + define void @uno_d() {entry: ret void} + define void @ord_d() {entry: ret void} + define void @oeq_d() {entry: ret void} + define void @une_d() {entry: ret void} + define void @ueq_d() {entry: ret void} + define void @one_d() {entry: ret void} + define void @olt_d() {entry: ret void} + define void @uge_d() {entry: ret void} + define void @ult_d() {entry: ret void} + define void @oge_d() {entry: ret void} + define void @ole_d() {entry: ret void} + define void @ugt_d() {entry: ret void} + define void @ule_d() {entry: ret void} + define void @ogt_d() {entry: ret void} + +... +--- +name: false_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: false_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0 + ; FP32: $v0 = COPY [[ORi]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: false_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0 + ; FP64: $v0 = COPY [[ORi]] + ; FP64: RetRA implicit $v0 + %5:gprb(s32) = G_CONSTANT i32 0 + %4:gprb(s32) = COPY %5(s32) + $v0 = COPY %4(s32) + RetRA implicit $v0 + +... +--- +name: true_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: true_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535 + ; FP32: $v0 = COPY [[ADDiu]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: true_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535 + ; FP64: $v0 = COPY [[ADDiu]] + ; FP64: RetRA implicit $v0 + %5:gprb(s32) = G_CONSTANT i32 -1 + %4:gprb(s32) = COPY %5(s32) + $v0 = COPY %4(s32) + RetRA implicit $v0 + +... +--- +name: uno_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: uno_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: uno_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(uno), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ord_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: ord_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ord_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(ord), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: oeq_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: oeq_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: oeq_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(oeq), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: une_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: une_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: une_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(une), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ueq_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: ueq_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ueq_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(ueq), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: one_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: one_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: one_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(one), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: olt_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: olt_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: olt_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(olt), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: uge_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: uge_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: uge_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(uge), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ult_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: ult_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ult_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(ult), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: oge_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: oge_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: oge_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(oge), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ole_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: ole_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ole_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(ole), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ugt_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: ugt_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ugt_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(ugt), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ule_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: ule_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ule_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(ule), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ogt_s +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: ogt_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ogt_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s32) = COPY $f12 + %1:fprb(s32) = COPY $f14 + %4:gprb(s32) = G_FCMP floatpred(ogt), %0(s32), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: false_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: false_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0 + ; FP32: $v0 = COPY [[ORi]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: false_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0 + ; FP64: $v0 = COPY [[ORi]] + ; FP64: RetRA implicit $v0 + %5:gprb(s32) = G_CONSTANT i32 0 + %4:gprb(s32) = COPY %5(s32) + $v0 = COPY %4(s32) + RetRA implicit $v0 + +... +--- +name: true_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: true_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535 + ; FP32: $v0 = COPY [[ADDiu]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: true_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535 + ; FP64: $v0 = COPY [[ADDiu]] + ; FP64: RetRA implicit $v0 + %5:gprb(s32) = G_CONSTANT i32 -1 + %4:gprb(s32) = COPY %5(s32) + $v0 = COPY %4(s32) + RetRA implicit $v0 + +... +--- +name: uno_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: uno_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: uno_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 1, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(uno), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ord_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: ord_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ord_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 1, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(ord), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: oeq_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: oeq_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: oeq_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 2, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(oeq), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: une_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: une_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: une_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 2, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(une), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ueq_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: ueq_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ueq_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 3, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(ueq), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: one_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: one_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: one_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 3, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(one), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: olt_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: olt_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: olt_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 4, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(olt), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: uge_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: uge_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: uge_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 4, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(uge), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ult_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: ult_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ult_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 5, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(ult), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: oge_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: oge_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: oge_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 5, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(oge), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ole_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: ole_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ole_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 6, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(ole), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ugt_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: ugt_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ugt_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 6, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(ugt), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ule_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: ule_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0 + ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVF_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ule_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 7, implicit-def $fcc0 + ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVF_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(ule), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: ogt_d +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: ogt_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7 + ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0 + ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP32: $v0 = COPY [[MOVT_I]] + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: ogt_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7 + ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1 + ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 7, implicit-def $fcc0 + ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]] + ; FP64: $v0 = COPY [[MOVT_I]] + ; FP64: RetRA implicit $v0 + %0:fprb(s64) = COPY $d6 + %1:fprb(s64) = COPY $d7 + %4:gprb(s32) = G_FCMP floatpred(ogt), %0(s64), %1 + %3:gprb(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir new file mode 100644 index 0000000..9df4edd --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir @@ -0,0 +1,73 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32 +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64 +--- | + + define void @oeq_s() {entry: ret void} + define void @oeq_d() {entry: ret void} + +... +--- +name: oeq_s +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: oeq_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14 + ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]] + ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) + ; FP32: $v0 = COPY [[COPY2]](s32) + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: oeq_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14 + ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]] + ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) + ; FP64: $v0 = COPY [[COPY2]](s32) + ; FP64: RetRA implicit $v0 + %0:_(s32) = COPY $f12 + %1:_(s32) = COPY $f14 + %2:_(s1) = G_FCMP floatpred(oeq), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: oeq_d +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: oeq_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7 + ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]] + ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) + ; FP32: $v0 = COPY [[COPY2]](s32) + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: oeq_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7 + ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]] + ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) + ; FP64: $v0 = COPY [[COPY2]](s32) + ; FP64: RetRA implicit $v0 + %0:_(s64) = COPY $d6 + %1:_(s64) = COPY $d7 + %2:_(s1) = G_FCMP floatpred(oeq), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll new file mode 100644 index 0000000..8f55963 --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll @@ -0,0 +1,438 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32 +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64 + +define i1 @false_s(float %x, float %y) { +; MIPS32-LABEL: false_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: ori $2, $zero, 0 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp false float %x, %y + ret i1 %cmp +} +define i1 @true_s(float %x, float %y) { +; MIPS32-LABEL: true_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $2, $zero, 65535 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp true float %x, %y + ret i1 %cmp +} + + +define i1 @uno_s(float %x, float %y) { +; MIPS32-LABEL: uno_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.un.s $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp uno float %x, %y + ret i1 %cmp +} +define i1 @ord_s(float %x, float %y) { +; MIPS32-LABEL: ord_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.un.s $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ord float %x, %y + ret i1 %cmp +} + + +define i1 @oeq_s(float %x, float %y) { +; MIPS32-LABEL: oeq_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.eq.s $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp oeq float %x, %y + ret i1 %cmp +} +define i1 @une_s(float %x, float %y) { +; MIPS32-LABEL: une_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.eq.s $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp une float %x, %y + ret i1 %cmp +} + + +define i1 @ueq_s(float %x, float %y) { +; MIPS32-LABEL: ueq_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ueq.s $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ueq float %x, %y + ret i1 %cmp +} +define i1 @one_s(float %x, float %y) { +; MIPS32-LABEL: one_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ueq.s $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp one float %x, %y + ret i1 %cmp +} + + +define i1 @olt_s(float %x, float %y) { +; MIPS32-LABEL: olt_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.olt.s $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp olt float %x, %y + ret i1 %cmp +} +define i1 @uge_s(float %x, float %y) { +; MIPS32-LABEL: uge_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.olt.s $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp uge float %x, %y + ret i1 %cmp +} + + +define i1 @ult_s(float %x, float %y) { +; MIPS32-LABEL: ult_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ult.s $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ult float %x, %y + ret i1 %cmp +} +define i1 @oge_s(float %x, float %y) { +; MIPS32-LABEL: oge_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ult.s $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp oge float %x, %y + ret i1 %cmp +} + + +define i1 @ole_s(float %x, float %y) { +; MIPS32-LABEL: ole_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ole.s $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ole float %x, %y + ret i1 %cmp +} +define i1 @ugt_s(float %x, float %y) { +; MIPS32-LABEL: ugt_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ole.s $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ugt float %x, %y + ret i1 %cmp +} + + +define i1 @ule_s(float %x, float %y) { +; MIPS32-LABEL: ule_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ule.s $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ule float %x, %y + ret i1 %cmp +} +define i1 @ogt_s(float %x, float %y) { +; MIPS32-LABEL: ogt_s: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ule.s $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ogt float %x, %y + ret i1 %cmp +} + + +define i1 @false_d(double %x, double %y) { +; MIPS32-LABEL: false_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: ori $2, $zero, 0 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp false double %x, %y + ret i1 %cmp +} +define i1 @true_d(double %x, double %y) { +; MIPS32-LABEL: true_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $2, $zero, 65535 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp true double %x, %y + ret i1 %cmp +} + + +define i1 @uno_d(double %x, double %y) { +; MIPS32-LABEL: uno_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.un.d $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp uno double %x, %y + ret i1 %cmp +} +define i1 @ord_d(double %x, double %y) { +; MIPS32-LABEL: ord_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.un.d $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ord double %x, %y + ret i1 %cmp +} + + +define i1 @oeq_d(double %x, double %y) { +; MIPS32-LABEL: oeq_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.eq.d $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp oeq double %x, %y + ret i1 %cmp +} +define i1 @une_d(double %x, double %y) { +; MIPS32-LABEL: une_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.eq.d $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp une double %x, %y + ret i1 %cmp +} + + +define i1 @ueq_d(double %x, double %y) { +; MIPS32-LABEL: ueq_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ueq.d $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ueq double %x, %y + ret i1 %cmp +} +define i1 @one_d(double %x, double %y) { +; MIPS32-LABEL: one_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ueq.d $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp one double %x, %y + ret i1 %cmp +} + + +define i1 @olt_d(double %x, double %y) { +; MIPS32-LABEL: olt_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.olt.d $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp olt double %x, %y + ret i1 %cmp +} +define i1 @uge_d(double %x, double %y) { +; MIPS32-LABEL: uge_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.olt.d $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp uge double %x, %y + ret i1 %cmp +} + + +define i1 @ult_d(double %x, double %y) { +; MIPS32-LABEL: ult_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ult.d $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ult double %x, %y + ret i1 %cmp +} +define i1 @oge_d(double %x, double %y) { +; MIPS32-LABEL: oge_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ult.d $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp oge double %x, %y + ret i1 %cmp +} + + +define i1 @ole_d(double %x, double %y) { +; MIPS32-LABEL: ole_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ole.d $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ole double %x, %y + ret i1 %cmp +} +define i1 @ugt_d(double %x, double %y) { +; MIPS32-LABEL: ugt_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ole.d $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ugt double %x, %y + ret i1 %cmp +} + + +define i1 @ule_d(double %x, double %y) { +; MIPS32-LABEL: ule_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ule.d $f12, $f14 +; MIPS32-NEXT: movf $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ule double %x, %y + ret i1 %cmp +} +define i1 @ogt_d(double %x, double %y) { +; MIPS32-LABEL: ogt_d: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $1, $zero, 1 +; MIPS32-NEXT: c.ule.d $f12, $f14 +; MIPS32-NEXT: movt $1, $zero, $fcc0 +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = fcmp ogt double %x, %y + ret i1 %cmp +} diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir new file mode 100644 index 0000000..ed5f3df --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir @@ -0,0 +1,75 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32 +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64 +--- | + + define void @oeq_s() {entry: ret void} + define void @oeq_d() {entry: ret void} + +... +--- +name: oeq_s +alignment: 2 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $f12, $f14 + + ; FP32-LABEL: name: oeq_s + ; FP32: liveins: $f12, $f14 + ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12 + ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14 + ; FP32: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]] + ; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32) + ; FP32: $v0 = COPY [[COPY2]](s32) + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: oeq_s + ; FP64: liveins: $f12, $f14 + ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12 + ; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14 + ; FP64: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]] + ; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32) + ; FP64: $v0 = COPY [[COPY2]](s32) + ; FP64: RetRA implicit $v0 + %0:_(s32) = COPY $f12 + %1:_(s32) = COPY $f14 + %4:_(s32) = G_FCMP floatpred(oeq), %0(s32), %1 + %3:_(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... +--- +name: oeq_d +alignment: 2 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $d6, $d7 + + ; FP32-LABEL: name: oeq_d + ; FP32: liveins: $d6, $d7 + ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6 + ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7 + ; FP32: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]] + ; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32) + ; FP32: $v0 = COPY [[COPY2]](s32) + ; FP32: RetRA implicit $v0 + ; FP64-LABEL: name: oeq_d + ; FP64: liveins: $d6, $d7 + ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6 + ; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7 + ; FP64: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]] + ; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32) + ; FP64: $v0 = COPY [[COPY2]](s32) + ; FP64: RetRA implicit $v0 + %0:_(s64) = COPY $d6 + %1:_(s64) = COPY $d7 + %4:_(s32) = G_FCMP floatpred(oeq), %0(s64), %1 + %3:_(s32) = COPY %4(s32) + $v0 = COPY %3(s32) + RetRA implicit $v0 + +... -- 2.7.4