From 22d18caa56027041fcfe695019c4f7b332c205e1 Mon Sep 17 00:00:00 2001 From: Dezhi Kong Date: Mon, 1 Jan 2018 20:05:06 +0800 Subject: [PATCH] vpp: config vdin/sr for g12a PD#156734: vpp: config vdin/sr for g12a 1.config vd1 vpp patch default 2.add viuin debug path 3.merged sr from 3.14 4.add vdin support 5.enable sr for g12a Change-Id: Ica1a7e7e31330e223528329accb149db74e00cf5 Signed-off-by: Dezhi Kong --- arch/arm64/boot/dts/amlogic/g12a_pxp.dts | 71 +++++- arch/arm64/boot/dts/amlogic/g12a_skt.dts | 71 ++++++ drivers/amlogic/media/deinterlace/register.h | 1 + .../media/video_processor/video_dev/amlvideo2.c | 28 +-- drivers/amlogic/media/video_sink/video.c | 3 +- drivers/amlogic/media/video_sink/vpp.c | 18 +- drivers/amlogic/media/vin/tvin/tvin_global.c | 4 +- drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.c | 74 ++++--- drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c | 246 ++++++++++++++++++++- drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c | 49 ++-- drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c | 28 +-- drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h | 4 + drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h | 64 ++++++ drivers/amlogic/media/vin/tvin/viu/viuin.c | 94 +++++++- include/linux/amlogic/media/amvecm/amvecm.h | 4 +- .../linux/amlogic/media/frame_provider/tvin/tvin.h | 26 ++- .../linux/amlogic/media/registers/regs/vdin_regs.h | 64 ++++++ 17 files changed, 739 insertions(+), 110 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/g12a_pxp.dts b/arch/arm64/boot/dts/amlogic/g12a_pxp.dts index 62a8742..7f69ea7 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_pxp.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_pxp.dts @@ -107,6 +107,22 @@ alignment = <0x0 0x100000>; //no-map; }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x0 0x04000000>; + alignment = <0x0 0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x0 0x04000000>; + alignment = <0x0 0x400000>; + }; }; vout { @@ -220,7 +236,6 @@ */ }; }; - canvas{ compatible = "amlogic, meson, canvas"; dev_name = "amlogic-canvas"; @@ -348,6 +363,60 @@ nrds-enable = <1>; pps-enable = <1>; }; + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + memory-region = <&vdin0_cma_reserved>; + dev_name = "vdin0"; + status = "okay"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + /*cma_size = <16>;*/ + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "okay"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; amlvecm { compatible = "amlogic, vecm"; diff --git a/arch/arm64/boot/dts/amlogic/g12a_skt.dts b/arch/arm64/boot/dts/amlogic/g12a_skt.dts index 2b5381a..4ca6bca 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_skt.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_skt.dts @@ -110,6 +110,22 @@ alignment = <0x0 0x100000>; //no-map; }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x0 0x04000000>; + alignment = <0x0 0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x0 0x04000000>; + alignment = <0x0 0x400000>; + }; }; vout { @@ -605,6 +621,61 @@ nrds-enable = <1>; pps-enable = <1>; }; + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + memory-region = <&vdin0_cma_reserved>; + dev_name = "vdin0"; + status = "okay"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + /*cma_size = <16>;*/ + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "okay"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + amlvecm { compatible = "amlogic, vecm"; dev_name = "aml_vecm"; diff --git a/drivers/amlogic/media/deinterlace/register.h b/drivers/amlogic/media/deinterlace/register.h index 1be93fa..3e1d5de 100644 --- a/drivers/amlogic/media/deinterlace/register.h +++ b/drivers/amlogic/media/deinterlace/register.h @@ -2048,6 +2048,7 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr, /* Bit 7:1 vertical formatter phase step (3.4) */ /* Bit 0 vertical formatter enable */ #define VIU_VD1_FMT_W 0x1a69 +/*g12a addr change to 0x3219*/ /* ((0x1a69 << 2) + 0xd0100000) */ /* Bit 27:16 horizontal formatter width */ /* Bit 11:0 vertical formatter width */ diff --git a/drivers/amlogic/media/video_processor/video_dev/amlvideo2.c b/drivers/amlogic/media/video_processor/video_dev/amlvideo2.c index c9cee06..518d705 100644 --- a/drivers/amlogic/media/video_processor/video_dev/amlvideo2.c +++ b/drivers/amlogic/media/video_processor/video_dev/amlvideo2.c @@ -950,13 +950,13 @@ struct amlvideo2_node *node) else cur_angle = cur_angle % 360; - if (node->porttype == TVIN_PORT_VIU) { + if (node->porttype == TVIN_PORT_VIU1) { if (src_width < src_height) cur_angle = (cur_angle + 90) % 360; } if ((node->crop_info.capture_crop_enable == 0) && - (node->porttype != TVIN_PORT_VIDEO)) { + (node->porttype != TVIN_PORT_VIU1_VIDEO)) { output_axis_adjust( src_width, src_height, &dst_width, &dst_height, @@ -1318,7 +1318,7 @@ struct amlvideo2_node *node) if (src_width < src_height) cur_angle = (cur_angle + 90) % 360; if ((node->crop_info.capture_crop_enable == 0) && - (node->porttype != TVIN_PORT_VIDEO)) { + (node->porttype != TVIN_PORT_VIU1_VIDEO)) { output_axis_adjust( src_width, src_height, &dst_width, &dst_height, @@ -1689,13 +1689,13 @@ struct amlvideo2_node *node) else cur_angle = cur_angle % 360; - if (node->porttype == TVIN_PORT_VIU) { + if (node->porttype == TVIN_PORT_VIU1) { if (src_width < src_height) cur_angle = (cur_angle + 90) % 360; } if ((node->crop_info.capture_crop_enable == 0) && - (node->porttype != TVIN_PORT_VIDEO)) { + (node->porttype != TVIN_PORT_VIU1_VIDEO)) { output_axis_adjust( src_width, src_height, &dst_width, &dst_height, @@ -2091,13 +2091,13 @@ struct amlvideo2_node *node) else cur_angle = cur_angle % 360; - if (node->porttype == TVIN_PORT_VIU) { + if (node->porttype == TVIN_PORT_VIU1) { if (src_width < src_height) cur_angle = (cur_angle + 90) % 360; } if ((node->crop_info.capture_crop_enable == 0) && - (node->porttype != TVIN_PORT_VIDEO)) { + (node->porttype != TVIN_PORT_VIU1_VIDEO)) { output_axis_adjust( src_width, src_height, &dst_width, &dst_height, @@ -2491,13 +2491,13 @@ struct amlvideo2_node *node) else cur_angle = cur_angle % 360; - if (node->porttype == TVIN_PORT_VIU) { + if (node->porttype == TVIN_PORT_VIU1) { if (src_width < src_height) cur_angle = (cur_angle + 90) % 360; } if ((node->crop_info.capture_crop_enable == 0) && - (node->porttype != TVIN_PORT_VIDEO)) { + (node->porttype != TVIN_PORT_VIU1_VIDEO)) { output_axis_adjust( src_width, src_height, &dst_width, &dst_height, @@ -3099,13 +3099,13 @@ int amlvideo2_ge2d_pre_process(struct vframe_s *vf, else cur_angle = cur_angle % 360; - if (node->porttype == TVIN_PORT_VIU) { + if (node->porttype == TVIN_PORT_VIU1) { if (src_width < src_height) cur_angle = (cur_angle + 90) % 360; } if ((node->crop_info.capture_crop_enable == 0) && - (node->porttype != TVIN_PORT_VIDEO)) { + (node->porttype != TVIN_PORT_VIU1_VIDEO)) { output_axis_adjust( src_width, src_height, &dst_width, &dst_height, @@ -3462,7 +3462,7 @@ static int amlvideo2_fillbuff(struct amlvideo2_fh *fh, & VIDTYPE_INTERLACE_TOP)) { if (vf->canvas0Addr == vf->canvas1Addr) { if ((node->p_type == AML_PROVIDE_VDIN0) && - (node->porttype == TVIN_PORT_VIU)) { + (node->porttype == TVIN_PORT_VIU1)) { src_canvas = amlvideo2_ge2d_interlace_vdindata_process( vf, node->context, &ge2d_config, @@ -4773,7 +4773,7 @@ static int amlvideo2_start_tvin_service(struct amlvideo2_node *node) para.dest_vactive = dst_h; if (para.scan_mode == TVIN_SCAN_MODE_INTERLACED) para.dest_vactive = para.dest_vactive / 2; - if (para.port == TVIN_PORT_VIDEO) { + if (para.port == TVIN_PORT_VIU1_VIDEO) { para.dest_hactive = 0; para.dest_vactive = 0; } @@ -5018,7 +5018,7 @@ static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i) para.dest_vactive = dst_h; if (para.scan_mode == TVIN_SCAN_MODE_INTERLACED) para.dest_vactive = para.dest_vactive / 2; - if (para.port == TVIN_PORT_VIDEO) { + if (para.port == TVIN_PORT_VIU1_VIDEO) { if (node->ge2d_multi_process_flag) { para.dest_hactive = 384; para.dest_vactive = 216; diff --git a/drivers/amlogic/media/video_sink/video.c b/drivers/amlogic/media/video_sink/video.c index 2b30d49..dcb1289 100644 --- a/drivers/amlogic/media/video_sink/video.c +++ b/drivers/amlogic/media/video_sink/video.c @@ -5152,8 +5152,7 @@ SET_FILTER: 16) | (cur_frame_par->video_input_h & 0x1fff)); /* vpp super scaler */ - if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) && - (get_cpu_type() != MESON_CPU_MAJOR_ID_G12A)) + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) vpp_set_super_scaler_regs(cur_frame_par->supscl_path, cur_frame_par->supsc0_enable, cur_frame_par->spsc0_w_in, diff --git a/drivers/amlogic/media/video_sink/vpp.c b/drivers/amlogic/media/video_sink/vpp.c index 891b21d..db07e15a 100644 --- a/drivers/amlogic/media/video_sink/vpp.c +++ b/drivers/amlogic/media/video_sink/vpp.c @@ -404,7 +404,7 @@ static int force_filter_mode = 1; MODULE_PARM_DESC(force_filter_mode, "force_filter_mode"); module_param(force_filter_mode, int, 0664); #endif -bool super_scaler; +bool super_scaler = 1; static unsigned int sr_support; static u32 sr_reg_offt; static unsigned int super_debug; @@ -1643,6 +1643,7 @@ int vpp_set_super_scaler_regs(int scaler_path_sel, ((~(reg_srscl0_hori_ratio&0x1))&0x1), 0, 1); } /* core1 config */ + if (sr_support & SUPER_CORE1_SUPPORT) { if (is_meson_gxtvbb_cpu()) tmp_data = sharpness1_sr2_ctrl_32d7; else @@ -1668,14 +1669,16 @@ int vpp_set_super_scaler_regs(int scaler_path_sel, sharpness1_sr2_ctrl_32d7 = tmp_data; } } + } /* size config */ tmp_data = ((reg_srscl0_hsize & 0x1fff) << 16) | (reg_srscl0_vsize & 0x1fff); tmp_data2 = VSYNC_RD_MPEG_REG( - SRSHARP0_SHARP_SR2_CTRL + sr_reg_offt); + SRSHARP0_SHARP_HVSIZE + sr_reg_offt); if (tmp_data != tmp_data2) - VSYNC_WR_MPEG_REG(SRSHARP0_SHARP_HVSIZE, tmp_data); + VSYNC_WR_MPEG_REG(SRSHARP0_SHARP_HVSIZE + sr_reg_offt, + tmp_data); tmp_data = ((reg_srscl1_hsize & 0x1fff) << 16) | (reg_srscl1_vsize & 0x1fff); @@ -1741,9 +1744,12 @@ int vpp_set_super_scaler_regs(int scaler_path_sel, VSYNC_WR_MPEG_REG_BITS(VPP_VE_ENABLE_CTRL, 0, data_path_chose, 1); } else { - if (is_meson_g12a_cpu()) - VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 0, 1, 1); - else + if (is_meson_g12a_cpu()) { + if (scaler_path_sel == CORE0_AFTER_PPS) + VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 0, 1, 1); + else + VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 1, 1, 1); + } else VSYNC_WR_MPEG_REG_BITS(VPP_VE_ENABLE_CTRL, 1, data_path_chose, 1); } diff --git a/drivers/amlogic/media/vin/tvin/tvin_global.c b/drivers/amlogic/media/vin/tvin/tvin_global.c index 144fef3..6f23b2c 100644 --- a/drivers/amlogic/media/vin/tvin/tvin_global.c +++ b/drivers/amlogic/media/vin/tvin/tvin_global.c @@ -111,8 +111,8 @@ const char *tvin_port_str(enum tvin_port_e port) return "TVIN_PORT_HDMI7"; case TVIN_PORT_DVIN0: return "TVIN_PORT_DVIN0"; - case TVIN_PORT_VIU: - return "TVIN_PORT_VIU"; + case TVIN_PORT_VIU1: + return "TVIN_PORT_VIU1"; case TVIN_PORT_MIPI: return "TVIN_PORT_MIPI"; case TVIN_PORT_ISP: diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.c b/drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.c index 98fc976..97ea8fc 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.c +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.c @@ -89,7 +89,7 @@ void vdin_canvas_init(struct vdin_dev_s *devp) if (devp->canvas_max_num > VDIN_CANVAS_MAX_CNT) devp->canvas_max_num = VDIN_CANVAS_MAX_CNT; - devp->mem_start = roundup(devp->mem_start, 32); + devp->mem_start = roundup(devp->mem_start, devp->canvas_align); pr_info("vdin.%d canvas initial table:\n", devp->index); for (i = 0; i < devp->canvas_max_num; i++) { canvas_id = vdin_canvas_ids[devp->index][i]; @@ -131,9 +131,7 @@ void vdin_canvas_start_config(struct vdin_dev_s *devp) (devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV444) || (devp->format_convert == VDIN_FORMAT_CONVERT_RGB_RGB) || (devp->format_convert == VDIN_FORMAT_CONVERT_YUV_GBR) || - - (devp->format_convert == VDIN_FORMAT_CONVERT_YUV_BRG) || - (devp->force_yuv444_malloc == 1)) { + (devp->format_convert == VDIN_FORMAT_CONVERT_YUV_BRG)) { if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) devp->canvas_w = max_buf_width * VDIN_YUV444_10BIT_PER_PIXEL_BYTE; @@ -164,8 +162,16 @@ void vdin_canvas_start_config(struct vdin_dev_s *devp) } /*backup before roundup*/ devp->canvas_active_w = devp->canvas_w; + if (devp->force_yuv444_malloc == 1) { + if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) + devp->canvas_w = devp->h_active * + VDIN_YUV444_10BIT_PER_PIXEL_BYTE; + else + devp->canvas_w = devp->h_active * + VDIN_YUV444_8BIT_PER_PIXEL_BYTE; + } /*canvas_w must ensure divided exact by 256bit(32byte)*/ - devp->canvas_w = roundup(devp->canvas_w, 32); + devp->canvas_w = roundup(devp->canvas_w, devp->canvas_align); devp->canvas_h = devp->v_active; if ((devp->prop.dest_cfmt == TVIN_NV12) || @@ -181,7 +187,7 @@ void vdin_canvas_start_config(struct vdin_dev_s *devp) if ((devp->cma_config_en != 1) || !(devp->cma_config_flag & 0x100)) { /*use_reserved_mem or alloc_from_contiguous*/ - devp->mem_start = roundup(devp->mem_start, 32); + devp->mem_start = roundup(devp->mem_start, devp->canvas_align); #ifdef VDIN_DEBUG pr_info("vdin%d cnavas start configuration table:\n", devp->index); @@ -215,7 +221,8 @@ void vdin_canvas_start_config(struct vdin_dev_s *devp) #endif for (i = 0; i < devp->canvas_max_num; i++) { devp->vfmem_start[i] = - roundup(devp->vfmem_start[i], 32); + roundup(devp->vfmem_start[i], + devp->canvas_align); canvas_id = vdin_canvas_ids[devp->index][i*canvas_step]; canvas_addr = devp->vfmem_start[i]; canvas_config(canvas_id, canvas_addr, @@ -265,9 +272,7 @@ void vdin_canvas_auto_config(struct vdin_dev_s *devp) (devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV444) || (devp->format_convert == VDIN_FORMAT_CONVERT_RGB_RGB) || (devp->format_convert == VDIN_FORMAT_CONVERT_YUV_GBR) || - - (devp->format_convert == VDIN_FORMAT_CONVERT_YUV_BRG) || - (devp->force_yuv444_malloc == 1)) { + (devp->format_convert == VDIN_FORMAT_CONVERT_YUV_BRG)) { if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) devp->canvas_w = devp->h_active * VDIN_YUV444_10BIT_PER_PIXEL_BYTE; @@ -299,8 +304,16 @@ void vdin_canvas_auto_config(struct vdin_dev_s *devp) } /*backup before roundup*/ devp->canvas_active_w = devp->canvas_w; + if (devp->force_yuv444_malloc == 1) { + if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) + devp->canvas_w = devp->h_active * + VDIN_YUV444_10BIT_PER_PIXEL_BYTE; + else + devp->canvas_w = devp->h_active * + VDIN_YUV444_8BIT_PER_PIXEL_BYTE; + } /*canvas_w must ensure divided exact by 256bit(32byte)*/ - devp->canvas_w = roundup(devp->canvas_w, 32); + devp->canvas_w = roundup(devp->canvas_w, devp->canvas_align); devp->canvas_h = devp->v_active; if ((devp->prop.dest_cfmt == TVIN_NV12) || @@ -315,7 +328,7 @@ void vdin_canvas_auto_config(struct vdin_dev_s *devp) devp->canvas_max_num = min(devp->canvas_max_num, max_buffer_num); if ((devp->cma_config_en != 1) || !(devp->cma_config_flag & 0x100)) { /*use_reserved_mem or alloc_from_contiguous*/ - devp->mem_start = roundup(devp->mem_start, 32); + devp->mem_start = roundup(devp->mem_start, devp->canvas_align); #ifdef VDIN_DEBUG pr_info("vdin%d cnavas auto configuration table:\n", devp->index); @@ -349,7 +362,8 @@ void vdin_canvas_auto_config(struct vdin_dev_s *devp) #endif for (i = 0; i < devp->canvas_max_num; i++) { devp->vfmem_start[i] = - roundup(devp->vfmem_start[i], 32); + roundup(devp->vfmem_start[i], + devp->canvas_align); canvas_id = vdin_canvas_ids[devp->index][i*canvas_step]; canvas_addr = devp->vfmem_start[i]; canvas_config(canvas_id, canvas_addr, @@ -419,12 +433,14 @@ unsigned int vdin_cma_alloc(struct vdin_dev_s *devp) (devp->force_yuv444_malloc == 1)) { if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) { h_size = roundup(h_size * - VDIN_YUV444_10BIT_PER_PIXEL_BYTE, 32); + VDIN_YUV444_10BIT_PER_PIXEL_BYTE, + devp->canvas_align); devp->canvas_alin_w = h_size / VDIN_YUV444_10BIT_PER_PIXEL_BYTE; } else { h_size = roundup(h_size * - VDIN_YUV444_8BIT_PER_PIXEL_BYTE, 32); + VDIN_YUV444_8BIT_PER_PIXEL_BYTE, + devp->canvas_align); devp->canvas_alin_w = h_size / VDIN_YUV444_8BIT_PER_PIXEL_BYTE; } @@ -432,7 +448,7 @@ unsigned int vdin_cma_alloc(struct vdin_dev_s *devp) (devp->format_convert == VDIN_FORMAT_CONVERT_YUV_NV21) || (devp->format_convert == VDIN_FORMAT_CONVERT_RGB_NV12) || (devp->format_convert == VDIN_FORMAT_CONVERT_RGB_NV21)) { - h_size = roundup(h_size, 32); + h_size = roundup(h_size, devp->canvas_align); devp->canvas_alin_w = h_size; /*todo change with canvas alloc!!*/ /* nv21/nv12 only have 8bit mode */ @@ -446,17 +462,19 @@ unsigned int vdin_cma_alloc(struct vdin_dev_s *devp) (devp->format_convert == VDIN_FORMAT_CONVERT_GBR_YUV422) || (devp->format_convert == VDIN_FORMAT_CONVERT_BRG_YUV422)) && (devp->color_depth_mode == 1)) { - h_size = roundup((h_size * 5)/2, 32); + h_size = roundup((h_size * 5)/2, devp->canvas_align); devp->canvas_alin_w = (h_size * 2) / 5; } else if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) && (devp->color_depth_mode == 0)) { h_size = roundup(h_size * - VDIN_YUV422_10BIT_PER_PIXEL_BYTE, 32); + VDIN_YUV422_10BIT_PER_PIXEL_BYTE, + devp->canvas_align); devp->canvas_alin_w = h_size / VDIN_YUV422_10BIT_PER_PIXEL_BYTE; } else { h_size = roundup(h_size * - VDIN_YUV422_8BIT_PER_PIXEL_BYTE, 32); + VDIN_YUV422_8BIT_PER_PIXEL_BYTE, + devp->canvas_align); devp->canvas_alin_w = h_size / VDIN_YUV422_8BIT_PER_PIXEL_BYTE; } @@ -487,11 +505,12 @@ unsigned int vdin_cma_alloc(struct vdin_dev_s *devp) devp->index, i); devp->cma_mem_alloc = 0; return 1; + } else { + devp->cma_mem_alloc = 1; + pr_info("vdin%d buf[%d] mem_start = 0x%lx, mem_size = 0x%x\n", + devp->index, i, + devp->vfmem_start[i], devp->vfmem_size); } - devp->cma_mem_alloc = 1; - pr_info("vdin%d buf[%d] mem_start = 0x%lx, mem_size = 0x%x\n", - devp->index, i, - devp->vfmem_start[i], devp->vfmem_size); } pr_info("vdin%d codec cma alloc ok!\n", devp->index); devp->mem_size = mem_size; @@ -504,11 +523,12 @@ unsigned int vdin_cma_alloc(struct vdin_dev_s *devp) devp->index); devp->cma_mem_alloc = 0; return 1; + } else { + devp->cma_mem_alloc = 1; + pr_info("vdin%d mem_start = 0x%lx, mem_size = 0x%x\n", + devp->index, devp->mem_start, devp->mem_size); + pr_info("vdin%d codec cma alloc ok!\n", devp->index); } - devp->cma_mem_alloc = 1; - pr_info("vdin%d mem_start = 0x%lx, mem_size = 0x%x\n", - devp->index, devp->mem_start, devp->mem_size); - pr_info("vdin%d codec cma alloc ok!\n", devp->index); } else if (devp->cma_config_flag == 0x100) { for (i = 0; i < max_buffer_num; i++) { devp->vfvenc_pages[i] = dma_alloc_from_contiguous( diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c b/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c index 37c2b1a..f18927e 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c @@ -119,10 +119,11 @@ static unsigned int vpu_reg_27af = 0x3; #define VDIN_MUX_CVD2 4 #define VDIN_MUX_HDMI 5 #define VDIN_MUX_DVIN 6 - -#define VDIN_MUX_VIU 7 +#define VDIN_MUX_VIU_1 7 #define VDIN_MUX_MIPI 8 -#define VDIN_MUX_ISP 9 +#define VDIN_MUX_ISP 9 +/*g12a new add*/ +#define VDIN_MUX_VIU_2 9 #define VDIN_MUX_656_B 10 #define VDIN_MAP_Y_G 0 @@ -724,16 +725,24 @@ void vdin_set_top(unsigned int offset, wr_bits(offset, VDIN_ASFIFO_CTRL2, 0xe4, VDI5_ASFIFO_CTRL_BIT, VDI5_ASFIFO_CTRL_WID); break; - case 0xa0: - case 0xc0: /* viu */ - vdin_mux = VDIN_MUX_VIU; - if (port == TVIN_PORT_VIDEO) + case 0xa0:/*viu1*/ + vdin_mux = VDIN_MUX_VIU_1; + if (port == TVIN_PORT_VIU1_VIDEO) wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xe4, VDI6_ASFIFO_CTRL_BIT, VDI6_ASFIFO_CTRL_WID); else wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xf4, VDI6_ASFIFO_CTRL_BIT, VDI6_ASFIFO_CTRL_WID); break; + case 0xc0: /* viu2 */ + vdin_mux = VDIN_MUX_VIU_2; + if (port == TVIN_PORT_VIU1_VIDEO) + wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xe4, + VDI8_ASFIFO_CTRL_BIT, VDI8_ASFIFO_CTRL_WID); + else + wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xf4, + VDI8_ASFIFO_CTRL_BIT, VDI8_ASFIFO_CTRL_WID); + break; case 0x100:/* mipi in mybe need modify base on truth */ vdin_mux = VDIN_MUX_MIPI; wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xe0, @@ -1260,6 +1269,181 @@ static inline void vdin_set_color_matrix0(unsigned int offset, VDIN_MATRIX_EN_BIT, VDIN_MATRIX_EN_WID); } } +static void vdin_set_color_matrix0_g12a(unsigned int offset, + struct tvin_format_s *tvin_fmt_p, + enum vdin_format_convert_e format_convert, + enum tvin_port_e port, + enum tvin_color_fmt_range_e color_fmt_range, + unsigned int vdin_hdr_flag, + unsigned int color_range_mode) +{ + enum vdin_matrix_csc_e matrix_csc = VDIN_MATRIX_NULL; + struct vdin_matrix_lup_s *matrix_tbl; + struct tvin_format_s *fmt_info = tvin_fmt_p; + + switch (format_convert) { + case VDIN_MATRIX_XXX_YUV_BLACK: + matrix_csc = VDIN_MATRIX_XXX_YUV601_BLACK; + break; + case VDIN_FORMAT_CONVERT_RGB_YUV422: + case VDIN_FORMAT_CONVERT_RGB_NV12: + case VDIN_FORMAT_CONVERT_RGB_NV21: + if ((port >= TVIN_PORT_HDMI0) && + (port <= TVIN_PORT_HDMI7)) { + if (color_range_mode == 1) { + if (color_fmt_range == TVIN_RGB_FULL) { + matrix_csc = VDIN_MATRIX_RGB_YUV709F; + if (vdin_hdr_flag == 1) + matrix_csc = + VDIN_MATRIX_RGB_YUV709; + } else { + matrix_csc = + VDIN_MATRIX_RGBS_YUV709F; + if (vdin_hdr_flag == 1) + matrix_csc = + VDIN_MATRIX_RGBS_YUV709; + } + } else { + if (color_fmt_range == TVIN_RGB_FULL) + matrix_csc = VDIN_MATRIX_RGB_YUV709; + else + matrix_csc = VDIN_MATRIX_RGBS_YUV709; + } + } else { + if (color_range_mode == 1) + matrix_csc = VDIN_MATRIX_RGB_YUV709F; + else + matrix_csc = VDIN_MATRIX_RGB_YUV709; + } + break; + case VDIN_FORMAT_CONVERT_GBR_YUV422: + matrix_csc = VDIN_MATRIX_GBR_YUV601; + break; + case VDIN_FORMAT_CONVERT_BRG_YUV422: + matrix_csc = VDIN_MATRIX_BRG_YUV601; + break; + case VDIN_FORMAT_CONVERT_RGB_YUV444: + if ((port >= TVIN_PORT_HDMI0) && + (port <= TVIN_PORT_HDMI7)) { + if (color_range_mode == 1) { + if (color_fmt_range == TVIN_RGB_FULL) { + matrix_csc = VDIN_MATRIX_RGB_YUV709F; + if (vdin_hdr_flag == 1) + matrix_csc = + VDIN_MATRIX_RGB_YUV709; + } else { + matrix_csc = VDIN_MATRIX_RGBS_YUV709F; + if (vdin_hdr_flag == 1) + matrix_csc = + VDIN_MATRIX_RGBS_YUV709; + } + } else { + if (color_fmt_range == TVIN_RGB_FULL) + matrix_csc = VDIN_MATRIX_RGB_YUV709; + else + matrix_csc = VDIN_MATRIX_RGBS_YUV709; + } + } else { + if (color_range_mode == 1) + matrix_csc = VDIN_MATRIX_RGB_YUV709F; + else + matrix_csc = VDIN_MATRIX_RGB_YUV709; + } + break; + case VDIN_FORMAT_CONVERT_YUV_RGB: + if (((fmt_info->scan_mode == TVIN_SCAN_MODE_PROGRESSIVE) && + (fmt_info->v_active >= 720)) || /* 720p & above */ + ((fmt_info->scan_mode == TVIN_SCAN_MODE_INTERLACED) && + (fmt_info->v_active >= 540)) /* 1080i & above */ + ) + matrix_csc = VDIN_MATRIX_YUV709_RGB; + else + matrix_csc = VDIN_MATRIX_YUV601_RGB; + break; + case VDIN_FORMAT_CONVERT_YUV_GBR: + if (((fmt_info->scan_mode == TVIN_SCAN_MODE_PROGRESSIVE) && + (fmt_info->v_active >= 720)) || /* 720p & above */ + ((fmt_info->scan_mode == TVIN_SCAN_MODE_INTERLACED) && + (fmt_info->v_active >= 540)) /* 1080i & above */ + ) + matrix_csc = VDIN_MATRIX_YUV709_GBR; + else + matrix_csc = VDIN_MATRIX_YUV601_GBR; + break; + case VDIN_FORMAT_CONVERT_YUV_BRG: + if (((fmt_info->scan_mode == TVIN_SCAN_MODE_PROGRESSIVE) && + (fmt_info->v_active >= 720)) || /* 720p & above */ + ((fmt_info->scan_mode == TVIN_SCAN_MODE_INTERLACED) && + (fmt_info->v_active >= 540)) /* 1080i & above */ + ) + matrix_csc = VDIN_MATRIX_YUV709_BRG; + else + matrix_csc = VDIN_MATRIX_YUV601_BRG; + break; + case VDIN_FORMAT_CONVERT_YUV_YUV422: + case VDIN_FORMAT_CONVERT_YUV_YUV444: + case VDIN_FORMAT_CONVERT_YUV_NV12: + case VDIN_FORMAT_CONVERT_YUV_NV21: + if (((fmt_info->scan_mode == TVIN_SCAN_MODE_PROGRESSIVE) && + (fmt_info->v_active >= 720)) || /* 720p & above */ + ((fmt_info->scan_mode == TVIN_SCAN_MODE_INTERLACED) && + (fmt_info->v_active >= 540)) /* 1080i & above */ + ) { + if ((color_range_mode == 1) && + (color_fmt_range != TVIN_YUV_FULL)) + matrix_csc = VDIN_MATRIX_YUV709_YUV709F; + else if ((color_range_mode == 0) && + (color_fmt_range == TVIN_YUV_FULL)) + matrix_csc = VDIN_MATRIX_YUV709F_YUV709; + } else { + if (color_range_mode == 1) { + if (color_fmt_range == TVIN_YUV_FULL) + matrix_csc = + VDIN_MATRIX_YUV601F_YUV709F; + else + matrix_csc = VDIN_MATRIX_YUV601_YUV709F; + } else { + if (color_fmt_range == TVIN_YUV_FULL) + matrix_csc = VDIN_MATRIX_YUV601F_YUV709; + else + matrix_csc = VDIN_MATRIX_YUV601_YUV709; + } + } + if (vdin_hdr_flag == 1) + matrix_csc = VDIN_MATRIX_NULL; + break; + default: + matrix_csc = VDIN_MATRIX_NULL; + break; + } + + if (matrix_csc == VDIN_MATRIX_NULL) { + wr_bits(offset, VDIN_MATRIX_CTRL, 0, + VDIN_MATRIX_EN_BIT, VDIN_MATRIX_EN_WID); + } else { + matrix_tbl = &vdin_matrix_lup[matrix_csc - 1]; + + /*coefficient index select matrix0*/ + wr_bits(offset, VDIN_MATRIX_CTRL, 0, + VDIN_MATRIX_COEF_INDEX_BIT, VDIN_MATRIX_COEF_INDEX_WID); + + wr(offset, + VDIN_MATRIX_PRE_OFFSET0_1, matrix_tbl->pre_offset0_1); + wr(offset, + VDIN_MATRIX_PRE_OFFSET2, matrix_tbl->pre_offset2); + wr(offset, VDIN_HDR2_MATRIXI_COEF00_01, matrix_tbl->coef00_01); + wr(offset, VDIN_HDR2_MATRIXI_COEF02_10, matrix_tbl->coef02_10); + wr(offset, VDIN_HDR2_MATRIXI_COEF11_12, matrix_tbl->coef11_12); + wr(offset, VDIN_HDR2_MATRIXI_COEF20_21, matrix_tbl->coef20_21); + wr(offset, VDIN_HDR2_MATRIXI_COEF22, matrix_tbl->coef22); + wr(offset, VDIN_HDR2_MATRIXI_OFFSET0_1, + matrix_tbl->post_offset0_1); + wr(offset, VDIN_HDR2_MATRIXI_OFFSET2, matrix_tbl->post_offset2); + wr_bits(offset, VDIN_HDR2_MATRIXI_EN_CTRL, 1, 0, 1); + wr_bits(offset, VDIN_HDR2_CTRL, 1, 16, 1); + wr_bits(offset, VDIN_HDR2_CTRL, 0, 13, 1); + } +} /*set matrix based on rgb_info_enable: * 0:set matrix0, disable matrix1 @@ -1278,7 +1462,17 @@ void vdin_set_matrix(struct vdin_dev_s *devp) */ wr_bits(offset, VDIN_MATRIX_CTRL, 0, VDIN_MATRIX1_EN_BIT, VDIN_MATRIX1_EN_WID); - vdin_set_color_matrix0(devp->addr_offset, devp->fmt_info_p, + if (is_meson_g12a_cpu()) + vdin_set_color_matrix0_g12a(devp->addr_offset, + devp->fmt_info_p, + devp->format_convert, + devp->parm.port, + devp->prop.color_fmt_range, + devp->prop.vdin_hdr_Flag, + devp->color_range_mode); + else + vdin_set_color_matrix0(devp->addr_offset, + devp->fmt_info_p, devp->format_convert, devp->parm.port, devp->prop.color_fmt_range, @@ -1297,7 +1491,17 @@ void vdin_set_matrix(struct vdin_dev_s *devp) devp->prop.color_fmt_range, devp->prop.vdin_hdr_Flag, devp->color_range_mode); - vdin_set_color_matrix0(devp->addr_offset, devp->fmt_info_p, + if (is_meson_g12a_cpu()) + vdin_set_color_matrix0_g12a(devp->addr_offset, + devp->fmt_info_p, + devp->format_convert, + devp->parm.port, + devp->prop.color_fmt_range, + devp->prop.vdin_hdr_Flag, + devp->color_range_mode); + else + vdin_set_color_matrix0(devp->addr_offset, + devp->fmt_info_p, format_convert_matrix0, devp->parm.port, devp->prop.color_fmt_range, @@ -1322,7 +1526,16 @@ void vdin_set_matrixs(struct vdin_dev_s *devp, unsigned char id, { switch (id) { case 0: - vdin_set_color_matrix0(devp->addr_offset, + if (is_meson_g12a_cpu()) + vdin_set_color_matrix0_g12a(devp->addr_offset, + devp->fmt_info_p, + devp->format_convert, + devp->parm.port, + devp->prop.color_fmt_range, + devp->prop.vdin_hdr_Flag, + devp->color_range_mode); + else + vdin_set_color_matrix0(devp->addr_offset, devp->fmt_info_p, csc, devp->parm.port, devp->prop.color_fmt_range, @@ -1363,7 +1576,16 @@ void vdin_set_prob_xy(unsigned int offset, devp->prop.color_fmt_range, devp->prop.vdin_hdr_Flag, devp->color_range_mode); - vdin_set_color_matrix0(devp->addr_offset, devp->fmt_info_p, + if (is_meson_g12a_cpu()) + vdin_set_color_matrix0_g12a(devp->addr_offset, + devp->fmt_info_p, + devp->format_convert, + devp->parm.port, + devp->prop.color_fmt_range, + devp->prop.vdin_hdr_Flag, + devp->color_range_mode); + else + vdin_set_color_matrix0(devp->addr_offset, devp->fmt_info_p, format_convert_matrix0, devp->parm.port, devp->prop.color_fmt_range, @@ -1719,7 +1941,7 @@ void vdin_set_wr_mif(struct vdin_dev_s *devp) width = ((rd(0, VPP_POSTBLEND_VD1_H_START_END) & 0xfff) - ((rd(0, VPP_POSTBLEND_VD1_H_START_END) >> 16) & 0xfff) + 1); - if ((devp->parm.port == TVIN_PORT_VIDEO) && (devp->index == 1) && + if ((devp->parm.port == TVIN_PORT_VIU1_VIDEO) && (devp->index == 1) && ((height != temp_height) && (width != temp_width))) { if ((width%2) && (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) && diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c b/drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c index a56204f..a1170a4 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c @@ -110,10 +110,10 @@ static ssize_t sig_det_store(struct device *dev, if (!buf) return len; /* port = simple_strtol(buf, NULL, 10); */ - if (kstrtol(buf, 10, &val) == 0) - port = val; - else + if (kstrtol(buf, 10, &val) < 0) return -EINVAL; + else + port = val; frontend = tvin_get_frontend(port, 0); if (frontend && frontend->dec_ops && @@ -308,14 +308,15 @@ static void vdin_dump_mem(char *path, struct vdin_dev_s *devp) { struct file *filp = NULL; loff_t pos = 0; - loff_t i = 0; + loff_t i = 0, j = 0; + unsigned int mem_size = 0; void *buf = NULL; void *vfbuf[VDIN_CANVAS_MAX_CNT]; mm_segment_t old_fs = get_fs(); - set_fs(KERNEL_DS); filp = filp_open(path, O_RDWR|O_CREAT, 0666); + mem_size = devp->canvas_active_w * devp->canvas_h; for (i = 0; i < VDIN_CANVAS_MAX_CNT; i++) vfbuf[i] = NULL; if (IS_ERR(filp)) { @@ -328,7 +329,7 @@ static void vdin_dump_mem(char *path, struct vdin_dev_s *devp) return; } for (i = 0; i < devp->canvas_max_num; i++) { - pos = devp->canvas_max_size * i; + pos = mem_size * i; if (devp->cma_config_flag == 0x1) buf = codec_mm_phys_to_virt(devp->mem_start + devp->canvas_max_size*i); @@ -340,11 +341,18 @@ static void vdin_dump_mem(char *path, struct vdin_dev_s *devp) else buf = phys_to_virt(devp->mem_start + devp->canvas_max_size*i); - if (devp->cma_config_flag & 0x100) - vfs_write(filp, vfbuf[i], devp->canvas_max_size, &pos); - else - vfs_write(filp, buf, devp->canvas_max_size, &pos); - + /*only write active data*/ + for (j = 0; j < devp->canvas_h; j++) { + if (devp->cma_config_flag & 0x100) { + vfs_write(filp, vfbuf[i], + devp->canvas_active_w, &pos); + vfbuf[i] += devp->canvas_w; + } else { + vfs_write(filp, buf, + devp->canvas_active_w, &pos); + buf += devp->canvas_w; + } + } pr_info("write buffer %lld of %2u to %s.\n", i, devp->canvas_max_num, path); } @@ -431,8 +439,10 @@ static void vdin_dump_state(struct vdin_dev_s *devp) struct vf_pool *vfp = devp->vfp; pr_info("h_active = %d, v_active = %d\n", devp->h_active, devp->v_active); - pr_info("canvas_w = %d, canvas_h = %d, canvas_alin_w = %d\n", - devp->canvas_w, devp->canvas_h, devp->canvas_alin_w); + pr_info("canvas_w = %d, canvas_h = %d\n", + devp->canvas_w, devp->canvas_h); + pr_info("canvas_alin_w = %d, canvas_active_w = %d\n", + devp->canvas_alin_w, devp->canvas_active_w); if ((devp->cma_config_en != 1) || !(devp->cma_config_flag & 0x1)) pr_info("mem_start = %ld, mem_size = %d\n", devp->mem_start, devp->mem_size); @@ -564,11 +574,10 @@ static void vdin_write_mem( struct vf_pool *p = devp->vfp; /* vtype = simple_strtol(type, NULL, 10); */ - if (kstrtol(type, 10, &val) == 0) - vtype = val; - else + if (kstrtol(type, 10, &val) < 0) return; + vtype = val; if (!devp->curr_wr_vfe) { devp->curr_wr_vfe = provider_vf_get(devp->vfp); if (!devp->curr_wr_vfe) { @@ -961,11 +970,11 @@ start_chk: param.port = TVIN_PORT_CAMERA; pr_info(" port is TVIN_PORT_CAMERA\n"); } else if (!strcmp(parm[1], "viuin")) { - param.port = TVIN_PORT_VIU; - pr_info(" port is TVIN_PORT_VIU\n"); + param.port = TVIN_PORT_VIU1; + pr_info(" port is TVIN_PORT_VIU1\n"); } else if (!strcmp(parm[1], "video")) { - param.port = TVIN_PORT_VIDEO; - pr_info(" port is TVIN_PORT_VIDEO\n"); + param.port = TVIN_PORT_VIU1_VIDEO; + pr_info(" port is TVIN_PORT_VIU1_VIDEO\n"); } else if (!strcmp(parm[1], "isp")) { param.port = TVIN_PORT_ISP; pr_info(" port is TVIN_PORT_ISP\n"); diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c b/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c index 41b3905..b89299f 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c @@ -505,10 +505,8 @@ void vdin_start_dec(struct vdin_dev_s *devp) devp->curr_field_type = vdin_get_curr_field_type(devp); /* configure regs and enable hw */ -#ifdef CONFIG_AML_VPU switch_vpu_mem_pd_vmod(devp->addr_offset?VPU_VIU_VDIN1:VPU_VIU_VDIN0, VPU_MEM_POWER_ON); -#endif vdin_hw_enable(devp->addr_offset); vdin_set_all_regs(devp); @@ -539,7 +537,7 @@ void vdin_start_dec(struct vdin_dev_s *devp) else vf_notify_receiver(devp->name, VFRAME_EVENT_PROVIDER_START, NULL); - if ((devp->parm.port != TVIN_PORT_VIU) || + if ((devp->parm.port != TVIN_PORT_VIU1) || (viu_hw_irq != 0)) { /*enable irq */ enable_irq(devp->irq); @@ -551,7 +549,7 @@ void vdin_start_dec(struct vdin_dev_s *devp) if (vdin_dbg_en) pr_info("****[%s]ok!****\n", __func__); #ifdef CONFIG_AM_TIMESYNC - if (devp->parm.port != TVIN_PORT_VIU) { + if (devp->parm.port != TVIN_PORT_VIU1) { /*disable audio&video sync used for libplayer*/ tsync_set_enable(0); /* enable system_time */ @@ -617,10 +615,8 @@ void vdin_stop_dec(struct vdin_dev_s *devp) vdin_dolby_addr_release(devp, devp->vfp->size); -#ifdef CONFIG_AML_VPU switch_vpu_mem_pd_vmod(devp->addr_offset?VPU_VIU_VDIN1:VPU_VIU_VDIN0, VPU_MEM_POWER_DOWN); -#endif memset(&devp->prop, 0, sizeof(struct tvin_sig_property_s)); #ifdef CONFIG_AML_RDMA rdma_clear(devp->rdma_handle); @@ -673,7 +669,7 @@ int start_tvin_service(int no, struct vdin_parm_s *para) ret = -EBUSY; return ret; } - if ((para->port != TVIN_PORT_VIU) || + if ((para->port != TVIN_PORT_VIU1) || (viu_hw_irq != 0)) { ret = request_irq(devp->irq, vdin_v4l2_isr, IRQF_SHARED, devp->irq_name, (void *)devp); @@ -707,7 +703,7 @@ int start_tvin_service(int no, struct vdin_parm_s *para) para->h_active >>= 1; devp->fmt_info_p->h_active = para->h_active; devp->fmt_info_p->v_active = para->v_active; - if ((devp->parm.port == TVIN_PORT_VIDEO) && + if ((devp->parm.port == TVIN_PORT_VIU1_VIDEO) && (!(devp->flags & VDIN_FLAG_V4L2_DEBUG))) { devp->fmt_info_p->v_active = ((rd(0, VPP_POSTBLEND_VD1_V_START_END) & @@ -792,7 +788,7 @@ int stop_tvin_service(int no) /* #endif */ devp->flags &= (~VDIN_FLAG_DEC_OPENED); devp->flags &= (~VDIN_FLAG_DEC_STARTED); - if ((devp->parm.port != TVIN_PORT_VIU) || + if ((devp->parm.port != TVIN_PORT_VIU1) || (viu_hw_irq != 0)) { free_irq(devp->irq, (void *)devp); devp->flags &= (~VDIN_FLAG_ISR_REQ); @@ -840,13 +836,13 @@ static int vdin_ioctl_fe(int no, struct fe_arg_s *parm) } /* - * if parm.port is TVIN_PORT_VIU,call vdin_v4l2_isr + * if parm.port is TVIN_PORT_VIU1,call vdin_v4l2_isr * vdin_v4l2_isr is used to the sample * v4l2 application such as camera,viu */ static void vdin_rdma_isr(struct vdin_dev_s *devp) { - if (devp->parm.port == TVIN_PORT_VIU) + if (devp->parm.port == TVIN_PORT_VIU1) vdin_v4l2_isr(devp->irq, devp); } @@ -964,7 +960,6 @@ void vdin_resume_dec(struct vdin_dev_s *devp) { vdin_hw_enable(devp->addr_offset); } - /*register provider & notify receiver */ void vdin_vf_reg(struct vdin_dev_s *devp) { @@ -1543,7 +1538,7 @@ irqreturn_t vdin_v4l2_isr(int irq, void *dev_id) goto irq_handled; } - if ((devp->parm.port == TVIN_PORT_VIU) || + if ((devp->parm.port == TVIN_PORT_VIU1) || (devp->parm.port == TVIN_PORT_CAMERA)) { if (!vdin_write_done_check(offset, devp)) { if (vdin_dbg_en) @@ -2371,8 +2366,15 @@ static int vdin_drv_probe(struct platform_device *pdev) /* @todo vdin_addr_offset */ if (is_meson_gxbb_cpu() && vdevp->index) vdin_addr_offset[vdevp->index] = 0x70; + else if (is_meson_g12a_cpu() && vdevp->index) + vdin_addr_offset[vdevp->index] = 0x100; vdevp->addr_offset = vdin_addr_offset[vdevp->index]; vdevp->flags = 0; + /*canvas align number*/ + if (is_meson_g12a_cpu()) + vdevp->canvas_align = 64; + else + vdevp->canvas_align = 32; /*mif reset patch for vdin wr ram bug on gxtvbb*/ if (is_meson_gxtvbb_cpu()) enable_reset = 1; diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h b/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h index c31e9e6..5776835d7 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h @@ -211,6 +211,10 @@ struct vdin_dev_s { unsigned int canvas_alin_w; unsigned int canvas_max_size; unsigned int canvas_max_num; + /*before G12A:32byte(256bit)align; + *after G12A:64byte(512bit)align + */ + unsigned int canvas_align; unsigned int irq; unsigned int rdma_irq; diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h b/drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h index 7873e4b..ac49237 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h @@ -647,6 +647,70 @@ #define VDIN_DOLBY_DSC_STATUS3 0x121d +/*g12a new add begin*/ +#define VDIN_HDR2_CTRL 0x1280 +#define VDIN_HDR2_CLK_GATE 0x1281 +#define VDIN_HDR2_MATRIXI_COEF00_01 0x1282 +#define VDIN_HDR2_MATRIXI_COEF02_10 0x1283 +#define VDIN_HDR2_MATRIXI_COEF11_12 0x1284 +#define VDIN_HDR2_MATRIXI_COEF20_21 0x1285 +#define VDIN_HDR2_MATRIXI_COEF22 0x1286 +#define VDIN_HDR2_MATRIXI_COEF30_31 0x1287 +#define VDIN_HDR2_MATRIXI_COEF32_40 0x1288 +#define VDIN_HDR2_MATRIXI_COEF41_42 0x1289 +#define VDIN_HDR2_MATRIXI_OFFSET0_1 0x128a +#define VDIN_HDR2_MATRIXI_OFFSET2 0x128b +#define VDIN_HDR2_MATRIXI_PRE_OFFSET0_1 0x128c +#define VDIN_HDR2_MATRIXI_PRE_OFFSET2 0x128d +#define VDIN_HDR2_MATRIXO_COEF00_01 0x128e +#define VDIN_HDR2_MATRIXO_COEF02_10 0x128f +#define VDIN_HDR2_MATRIXO_COEF11_12 0x1290 +#define VDIN_HDR2_MATRIXO_COEF20_21 0x1291 +#define VDIN_HDR2_MATRIXO_COEF22 0x1292 +#define VDIN_HDR2_MATRIXO_COEF30_31 0x1293 +#define VDIN_HDR2_MATRIXO_COEF32_40 0x1294 +#define VDIN_HDR2_MATRIXO_COEF41_42 0x1295 +#define VDIN_HDR2_MATRIXO_OFFSET0_1 0x1296 +#define VDIN_HDR2_MATRIXO_OFFSET2 0x1297 +#define VDIN_HDR2_MATRIXO_PRE_OFFSET0_1 0x1298 +#define VDIN_HDR2_MATRIXO_PRE_OFFSET2 0x1299 +#define VDIN_HDR2_MATRIXI_CLIP 0x129a +#define VDIN_HDR2_MATRIXO_CLIP 0x129b +#define VDIN_HDR2_CGAIN_OFFT 0x129c +#define VDIN_EOTF_LUT_ADDR_PORT 0x129e +#define VDIN_EOTF_LUT_DATA_PORT 0x129f +#define VDIN_OETF_LUT_ADDR_PORT 0x12a0 +#define VDIN_OETF_LUT_DATA_PORT 0x12a1 +#define VDIN_CGAIN_LUT_ADDR_PORT 0x12a2 +#define VDIN_CGAIN_LUT_DATA_PORT 0x12a3 +#define VDIN_HDR2_CGAIN_COEF0 0x12a4 +#define VDIN_HDR2_CGAIN_COEF1 0x12a5 +#define VDIN_OGAIN_LUT_ADDR_PORT 0x12a6 +#define VDIN_OGAIN_LUT_DATA_PORT 0x12a7 +#define VDIN_HDR2_ADPS_CTRL 0x12a8 +#define VDIN_HDR2_ADPS_ALPHA0 0x12a9 +#define VDIN_HDR2_ADPS_ALPHA1 0x12aa +#define VDIN_HDR2_ADPS_BETA0 0x12ab +#define VDIN_HDR2_ADPS_BETA1 0x12ac +#define VDIN_HDR2_ADPS_BETA2 0x12ad +#define VDIN_HDR2_ADPS_COEF0 0x12ae +#define VDIN_HDR2_ADPS_COEF1 0x12af +#define VDIN_HDR2_GMUT_CTRL 0x12b0 +#define VDIN_HDR2_GMUT_COEF0 0x12b1 +#define VDIN_HDR2_GMUT_COEF1 0x12b2 +#define VDIN_HDR2_GMUT_COEF2 0x12b3 +#define VDIN_HDR2_GMUT_COEF3 0x12b4 +#define VDIN_HDR2_GMUT_COEF4 0x12b5 +#define VDIN_HDR2_PIPE_CTRL1 0x12b6 +#define VDIN_HDR2_PIPE_CTRL2 0x12b7 +#define VDIN_HDR2_PIPE_CTRL3 0x12b8 +#define VDIN_HDR2_PROC_WIN1 0x12b9 +#define VDIN_HDR2_PROC_WIN2 0x12ba +#define VDIN_HDR2_MATRIXI_EN_CTRL 0x12bb +#define VDIN_HDR2_MATRIXO_EN_CTRL 0x12bc + +/*g12a new add end*/ + /* #define VDIN_SCALE_COEF_IDX 0x1200 */ /* #define VDIN_SCALE_COEF 0x1201 */ diff --git a/drivers/amlogic/media/vin/tvin/viu/viuin.c b/drivers/amlogic/media/vin/tvin/viu/viuin.c index cfb8d70..846a617 100644 --- a/drivers/amlogic/media/vin/tvin/viu/viuin.c +++ b/drivers/amlogic/media/vin/tvin/viu/viuin.c @@ -54,6 +54,15 @@ #define ENCL_INFO_READ 0x271f #define VPU_VIU2VDIN_HDN_CTRL 0x2780 +/*g12a new add*/ +#define VPU_VIU_ASYNC_MASK 0x2781 +#define VDIN_MISC_CTRL 0x2782 +#define VPU_VIU_VDIN_IF_MUX_CTRL 0x2783 +#define VPU_VIU2VDIN1_HDN_CTRL 0x2784 +#define VPU_VENCX_CLK_CTRL 0x2785 +#define VPP_WRBAK_CTRL 0x1df9 + + static unsigned int vsync_enter_line_curr; module_param(vsync_enter_line_curr, uint, 0664); MODULE_PARM_DESC(vsync_enter_line_curr, @@ -130,7 +139,7 @@ static inline uint32_t rd_bits_viu(uint32_t reg, static int viuin_support(struct tvin_frontend_s *fe, enum tvin_port_e port) { - if (port == TVIN_PORT_VIU || port == TVIN_PORT_VIDEO) + if (port == TVIN_PORT_VIU1 || port == TVIN_PORT_VIU1_VIDEO) return 0; else return -1; @@ -154,7 +163,7 @@ void viuin_check_venc_line(struct viuin_s *devp_local) static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port) { struct viuin_s *devp = container_of(fe, struct viuin_s, frontend); - unsigned int viu_mux = 0; + unsigned int viu_mux = 0, viu_sel = 0; if (!memcpy(&devp->parm, fe->private_data, sizeof(struct vdin_parm_s))) { @@ -183,7 +192,7 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port) break; } viuin_check_venc_line(devp); - if (port == TVIN_PORT_VIDEO) { + if (port == TVIN_PORT_VIU1_VIDEO) { /* enable hsync for vdin loop */ wr_bits_viu(VIU_MISC_CTRL1, 1, 28, 1); viu_mux = 0x4; @@ -193,8 +202,68 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port) /* 1/2 down scaling */ wr_viu(VPU_VIU2VDIN_HDN_CTRL, 0x40f00); } - wr_bits_viu(VPU_VIU_VENC_MUX_CTRL, viu_mux, 4, 4); - wr_bits_viu(VPU_VIU_VENC_MUX_CTRL, viu_mux, 8, 4); + if (is_meson_g12a_cpu()) { + if (((port >= TVIN_PORT_VIU1_WB0_VD1) && + (port <= TVIN_PORT_VIU1_WB0_POST_BLEND)) || + ((port >= TVIN_PORT_VIU2_WB0_VD1) && + (port <= TVIN_PORT_VIU2_WB0_POST_BLEND))) + viu_mux = 8; + else if (((port >= TVIN_PORT_VIU1_WB1_VD1) && + (port <= TVIN_PORT_VIU1_WB1_POST_BLEND)) || + ((port >= TVIN_PORT_VIU2_WB1_VD1) && + (port <= TVIN_PORT_VIU2_WB1_POST_BLEND))) + viu_mux = 16; + if (port >> 8 == 0xa0) + viu_sel = 1; + else if (port >> 8 == 0xc0) + viu_sel = 2; + if (viu_sel == 1) { + wr_bits_viu(VPU_VIU_VDIN_IF_MUX_CTRL, viu_mux, 0, 5); + wr_bits_viu(VPU_VIU_VDIN_IF_MUX_CTRL, viu_mux, 8, 5); + } else if (viu_sel == 2) { + wr_bits_viu(VPU_VIU_VDIN_IF_MUX_CTRL, viu_mux, 16, 5); + wr_bits_viu(VPU_VIU_VDIN_IF_MUX_CTRL, viu_mux, 24, 5); + } else { + wr_viu(VPU_VIU_VDIN_IF_MUX_CTRL, 0); + } + if ((port == TVIN_PORT_VIU1_WB0_VD1) || + (port == TVIN_PORT_VIU2_WB0_VD1)) + wr_bits_viu(VPP_WRBAK_CTRL, 1, 0, 3); + else if ((port == TVIN_PORT_VIU1_WB0_VD2) || + (port == TVIN_PORT_VIU2_WB0_VD2)) + wr_bits_viu(VPP_WRBAK_CTRL, 2, 0, 3); + else if ((port == TVIN_PORT_VIU1_WB0_OSD1) || + (port == TVIN_PORT_VIU2_WB0_OSD1)) + wr_bits_viu(VPP_WRBAK_CTRL, 3, 0, 3); + else if ((port == TVIN_PORT_VIU1_WB0_OSD2) || + (port == TVIN_PORT_VIU2_WB0_OSD2)) + wr_bits_viu(VPP_WRBAK_CTRL, 4, 0, 3); + else if ((port == TVIN_PORT_VIU1_WB0_POST_BLEND) || + (port == TVIN_PORT_VIU2_WB0_POST_BLEND)) + wr_bits_viu(VPP_WRBAK_CTRL, 5, 0, 3); + else + wr_bits_viu(VPP_WRBAK_CTRL, 0, 4, 3); + if ((port == TVIN_PORT_VIU1_WB1_VD1) || + (port == TVIN_PORT_VIU2_WB1_VD1)) + wr_bits_viu(VPP_WRBAK_CTRL, 1, 4, 3); + else if ((port == TVIN_PORT_VIU1_WB1_VD2) || + (port == TVIN_PORT_VIU2_WB1_VD2)) + wr_bits_viu(VPP_WRBAK_CTRL, 2, 4, 3); + else if ((port == TVIN_PORT_VIU1_WB1_OSD1) || + (port == TVIN_PORT_VIU2_WB1_OSD1)) + wr_bits_viu(VPP_WRBAK_CTRL, 3, 4, 3); + else if ((port == TVIN_PORT_VIU1_WB1_OSD2) || + (port == TVIN_PORT_VIU2_WB1_OSD2)) + wr_bits_viu(VPP_WRBAK_CTRL, 4, 4, 3); + else if ((port == TVIN_PORT_VIU1_WB1_POST_BLEND) || + (port == TVIN_PORT_VIU2_WB1_POST_BLEND)) + wr_bits_viu(VPP_WRBAK_CTRL, 5, 4, 3); + else + wr_bits_viu(VPP_WRBAK_CTRL, 0, 4, 3); + } else { + wr_bits_viu(VPU_VIU_VENC_MUX_CTRL, viu_mux, 4, 4); + wr_bits_viu(VPU_VIU_VENC_MUX_CTRL, viu_mux, 8, 4); + } devp->flag = 0; open_cnt++; return 0; @@ -203,14 +272,21 @@ static void viuin_close(struct tvin_frontend_s *fe) { struct viuin_s *devp = container_of(fe, struct viuin_s, frontend); - viuin_check_venc_line(devp); + if (0)/*temp mark for pxp verify*/ + viuin_check_venc_line(devp); memset(&devp->parm, 0, sizeof(struct vdin_parm_s)); /*close the venc to vdin path*/ if (open_cnt) open_cnt--; if (open_cnt == 0) { - wr_bits_viu(VPU_VIU_VENC_MUX_CTRL, 0, 8, 4); - wr_bits_viu(VPU_VIU_VENC_MUX_CTRL, 0, 4, 4); + if (is_meson_g12a_cpu()) { + wr_viu(VPU_VIU_VDIN_IF_MUX_CTRL, 0); + wr_viu(VPP_WRBAK_CTRL, 0); + + } else { + wr_bits_viu(VPU_VIU_VENC_MUX_CTRL, 0, 8, 4); + wr_bits_viu(VPU_VIU_VENC_MUX_CTRL, 0, 4, 4); + } } if (rd_viu(VPU_VIU2VDIN_HDN_CTRL) != 0) wr_viu(VPU_VIU2VDIN_HDN_CTRL, 0x0); @@ -278,7 +354,7 @@ static void viuin_sig_property(struct tvin_frontend_s *fe, static const struct vinfo_s *vinfo; struct viuin_s *devp = container_of(fe, struct viuin_s, frontend); - if (devp->parm.port == TVIN_PORT_VIDEO) + if (devp->parm.port == TVIN_PORT_VIU1_VIDEO) prop->color_format = TVIN_YUV444; else { vinfo = get_current_vinfo(); diff --git a/include/linux/amlogic/media/amvecm/amvecm.h b/include/linux/amlogic/media/amvecm/amvecm.h index c60b340..c4e9762 100644 --- a/include/linux/amlogic/media/amvecm/amvecm.h +++ b/include/linux/amlogic/media/amvecm/amvecm.h @@ -204,8 +204,8 @@ static inline void WRITE_VPP_REG_BITS(uint32_t reg, const uint32_t len) { WRITE_VPP_REG(reg, ((READ_VPP_REG(reg) & - ~(((1L << (len)) - 1) << (start))) | - (((value) & ((1L << (len)) - 1)) << (start)))); + ~(((1L << (len)) - 1) << (start))) | + (((value) & ((1L << (len)) - 1)) << (start)))); } static inline uint32_t READ_VPP_REG_BITS(uint32_t reg, diff --git a/include/linux/amlogic/media/frame_provider/tvin/tvin.h b/include/linux/amlogic/media/frame_provider/tvin/tvin.h index f1ea549..abf1b37 100644 --- a/include/linux/amlogic/media/frame_provider/tvin/tvin.h +++ b/include/linux/amlogic/media/frame_provider/tvin/tvin.h @@ -58,8 +58,30 @@ enum tvin_port_e { TVIN_PORT_HDMI6, TVIN_PORT_HDMI7, TVIN_PORT_DVIN0 = 0x00008000, - TVIN_PORT_VIDEO = 0x0000a000, - TVIN_PORT_VIU = 0x0000C000, + TVIN_PORT_VIU1 = 0x0000a000, + TVIN_PORT_VIU1_VIDEO, + TVIN_PORT_VIU1_WB0_VD1, + TVIN_PORT_VIU1_WB0_VD2, + TVIN_PORT_VIU1_WB0_OSD1, + TVIN_PORT_VIU1_WB0_OSD2, + TVIN_PORT_VIU1_WB0_POST_BLEND, + TVIN_PORT_VIU1_WB1_VD1, + TVIN_PORT_VIU1_WB1_VD2, + TVIN_PORT_VIU1_WB1_OSD1, + TVIN_PORT_VIU1_WB1_OSD2, + TVIN_PORT_VIU1_WB1_POST_BLEND, + TVIN_PORT_VIU2 = 0x0000C000, + TVIN_PORT_VIU2_VIDEO, + TVIN_PORT_VIU2_WB0_VD1, + TVIN_PORT_VIU2_WB0_VD2, + TVIN_PORT_VIU2_WB0_OSD1, + TVIN_PORT_VIU2_WB0_OSD2, + TVIN_PORT_VIU2_WB0_POST_BLEND, + TVIN_PORT_VIU2_WB1_VD1, + TVIN_PORT_VIU2_WB1_VD2, + TVIN_PORT_VIU2_WB1_OSD1, + TVIN_PORT_VIU2_WB1_OSD2, + TVIN_PORT_VIU2_WB1_POST_BLEND, TVIN_PORT_MIPI = 0x00010000, TVIN_PORT_ISP = 0x00020000, TVIN_PORT_MAX = 0x80000000, diff --git a/include/linux/amlogic/media/registers/regs/vdin_regs.h b/include/linux/amlogic/media/registers/regs/vdin_regs.h index 8b6276c..f41ab42 100644 --- a/include/linux/amlogic/media/registers/regs/vdin_regs.h +++ b/include/linux/amlogic/media/registers/regs/vdin_regs.h @@ -129,5 +129,69 @@ #define VDIN_WIN_V_START_END 0x126e #define VDIN_ASFIFO_CTRL3 0x126f +/*g12a new add begin*/ +#define VDIN_HDR2_CTRL 0x1280 +#define VDIN_HDR2_CLK_GATE 0x1281 +#define VDIN_HDR2_MATRIXI_COEF00_01 0x1282 +#define VDIN_HDR2_MATRIXI_COEF02_10 0x1283 +#define VDIN_HDR2_MATRIXI_COEF11_12 0x1284 +#define VDIN_HDR2_MATRIXI_COEF20_21 0x1285 +#define VDIN_HDR2_MATRIXI_COEF22 0x1286 +#define VDIN_HDR2_MATRIXI_COEF30_31 0x1287 +#define VDIN_HDR2_MATRIXI_COEF32_40 0x1288 +#define VDIN_HDR2_MATRIXI_COEF41_42 0x1289 +#define VDIN_HDR2_MATRIXI_OFFSET0_1 0x128a +#define VDIN_HDR2_MATRIXI_OFFSET2 0x128b +#define VDIN_HDR2_MATRIXI_PRE_OFFSET0_1 0x128c +#define VDIN_HDR2_MATRIXI_PRE_OFFSET2 0x128d +#define VDIN_HDR2_MATRIXO_COEF00_01 0x128e +#define VDIN_HDR2_MATRIXO_COEF02_10 0x128f +#define VDIN_HDR2_MATRIXO_COEF11_12 0x1290 +#define VDIN_HDR2_MATRIXO_COEF20_21 0x1291 +#define VDIN_HDR2_MATRIXO_COEF22 0x1292 +#define VDIN_HDR2_MATRIXO_COEF30_31 0x1293 +#define VDIN_HDR2_MATRIXO_COEF32_40 0x1294 +#define VDIN_HDR2_MATRIXO_COEF41_42 0x1295 +#define VDIN_HDR2_MATRIXO_OFFSET0_1 0x1296 +#define VDIN_HDR2_MATRIXO_OFFSET2 0x1297 +#define VDIN_HDR2_MATRIXO_PRE_OFFSET0_1 0x1298 +#define VDIN_HDR2_MATRIXO_PRE_OFFSET2 0x1299 +#define VDIN_HDR2_MATRIXI_CLIP 0x129a +#define VDIN_HDR2_MATRIXO_CLIP 0x129b +#define VDIN_HDR2_CGAIN_OFFT 0x129c +#define VDIN_EOTF_LUT_ADDR_PORT 0x129e +#define VDIN_EOTF_LUT_DATA_PORT 0x129f +#define VDIN_OETF_LUT_ADDR_PORT 0x12a0 +#define VDIN_OETF_LUT_DATA_PORT 0x12a1 +#define VDIN_CGAIN_LUT_ADDR_PORT 0x12a2 +#define VDIN_CGAIN_LUT_DATA_PORT 0x12a3 +#define VDIN_HDR2_CGAIN_COEF0 0x12a4 +#define VDIN_HDR2_CGAIN_COEF1 0x12a5 +#define VDIN_OGAIN_LUT_ADDR_PORT 0x12a6 +#define VDIN_OGAIN_LUT_DATA_PORT 0x12a7 +#define VDIN_HDR2_ADPS_CTRL 0x12a8 +#define VDIN_HDR2_ADPS_ALPHA0 0x12a9 +#define VDIN_HDR2_ADPS_ALPHA1 0x12aa +#define VDIN_HDR2_ADPS_BETA0 0x12ab +#define VDIN_HDR2_ADPS_BETA1 0x12ac +#define VDIN_HDR2_ADPS_BETA2 0x12ad +#define VDIN_HDR2_ADPS_COEF0 0x12ae +#define VDIN_HDR2_ADPS_COEF1 0x12af +#define VDIN_HDR2_GMUT_CTRL 0x12b0 +#define VDIN_HDR2_GMUT_COEF0 0x12b1 +#define VDIN_HDR2_GMUT_COEF1 0x12b2 +#define VDIN_HDR2_GMUT_COEF2 0x12b3 +#define VDIN_HDR2_GMUT_COEF3 0x12b4 +#define VDIN_HDR2_GMUT_COEF4 0x12b5 +#define VDIN_HDR2_PIPE_CTRL1 0x12b6 +#define VDIN_HDR2_PIPE_CTRL2 0x12b7 +#define VDIN_HDR2_PIPE_CTRL3 0x12b8 +#define VDIN_HDR2_PROC_WIN1 0x12b9 +#define VDIN_HDR2_PROC_WIN2 0x12ba +#define VDIN_HDR2_MATRIXI_EN_CTRL 0x12bb +#define VDIN_HDR2_MATRIXO_EN_CTRL 0x12bc + +/*g12a new add end*/ + #endif -- 2.7.4