From 22c8ce0aa274cea2ff538ffdf723053ecf77d78b Mon Sep 17 00:00:00 2001 From: Sai Krishna Potthuri Date: Mon, 20 Mar 2023 15:29:30 +0530 Subject: [PATCH] spi: cadence-quadspi: Update the read timeout based on the length When performing indirect read via external DMA the timeout for completion is set equal to the read length instead of fixed timeout value. For reads larger than 500 bytes, the timeout will continue to be equal to the read length whereas for a small read like the Read Status Register command, the timeout would be 1 or 2 milliseconds. This is not enough to cover the overhead needed in setting up DMA, in that case make sure the timeout is at least 500ms to allow DMA to finish. This solution is inline with the timeout used for Direct read via DMA. Signed-off-by: Sai Krishna Potthuri Link: https://lore.kernel.org/r/20230320095931.2651714-2-sai.krishna.potthuri@amd.com Signed-off-by: Mark Brown --- drivers/spi/spi-cadence-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 79ab7e3..e281732 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -863,7 +863,7 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, reinit_completion(&cqspi->transfer_complete); if (!wait_for_completion_timeout(&cqspi->transfer_complete, - msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) { + msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) { ret = -ETIMEDOUT; goto failrd; } -- 2.7.4