From 2286b5158a567a8ddf1842238564f84bc2e4ff75 Mon Sep 17 00:00:00 2001 From: MingLiang Dong Date: Thu, 20 Apr 2017 20:37:42 +0800 Subject: [PATCH] amvecm: add amvecm driver PD#138714: add amvecm driver Change-Id: Ieb0be7a4b02b7a8daa549544a97ee23e0daeb6da Signed-off-by: MingLiang Dong --- MAINTAINERS | 19 + arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts | 9 + arch/arm64/boot/dts/amlogic/gxl_p212_2g.dts | 9 + arch/arm64/boot/dts/amlogic/gxm_q200_2g.dts | 10 + arch/arm64/boot/dts/amlogic/gxm_skt.dts | 8 + arch/arm64/configs/meson64_defconfig | 2 + drivers/amlogic/media/Kconfig | 1 + drivers/amlogic/media/Makefile | 3 +- drivers/amlogic/media/common/vfm/vframe_provider.c | 20 + drivers/amlogic/media/enhancement/Kconfig | 16 + drivers/amlogic/media/enhancement/Makefile | 1 + drivers/amlogic/media/enhancement/amvecm/Kconfig | 14 + drivers/amlogic/media/enhancement/amvecm/Makefile | 8 + drivers/amlogic/media/enhancement/amvecm/amcm.c | 512 ++ drivers/amlogic/media/enhancement/amvecm/amcm.h | 88 + .../amlogic/media/enhancement/amvecm/amcm_regmap.h | 922 ++++ drivers/amlogic/media/enhancement/amvecm/amcsc.c | 4415 ++++++++++++++++ drivers/amlogic/media/enhancement/amvecm/amcsc.h | 123 + .../media/enhancement/amvecm/amdolby_vision.c | 2056 ++++++++ drivers/amlogic/media/enhancement/amvecm/amve.c | 5304 ++++++++++++++++++++ drivers/amlogic/media/enhancement/amvecm/amve.h | 175 + .../media/enhancement/amvecm/amve_gamma_table.h | 87 + drivers/amlogic/media/enhancement/amvecm/amvecm.c | 3124 ++++++++++++ .../media/enhancement/amvecm/amvecm_vlock_regmap.h | 84 + .../media/enhancement/amvecm/arch/cm_regs.h | 193 + .../media/enhancement/amvecm/arch/hdr_curve.h | 1130 +++++ .../media/enhancement/amvecm/arch/ve_regs.h | 529 ++ .../enhancement/amvecm/arch/vpp_dolbyvision_regs.h | 206 + .../media/enhancement/amvecm/arch/vpp_hdr_regs.h | 39 + .../media/enhancement/amvecm/arch/vpp_regs.h | 747 +++ .../enhancement/amvecm/dolby_vision/dolby_vision.h | 302 ++ drivers/amlogic/media/video_sink/video.c | 6 +- include/linux/amlogic/media/amvecm/amvecm.h | 199 + include/linux/amlogic/media/amvecm/cm.h | 105 +- include/linux/amlogic/media/amvecm/ve.h | 336 ++ 35 files changed, 20741 insertions(+), 61 deletions(-) create mode 100644 drivers/amlogic/media/enhancement/Kconfig create mode 100644 drivers/amlogic/media/enhancement/Makefile create mode 100644 drivers/amlogic/media/enhancement/amvecm/Kconfig create mode 100644 drivers/amlogic/media/enhancement/amvecm/Makefile create mode 100644 drivers/amlogic/media/enhancement/amvecm/amcm.c create mode 100644 drivers/amlogic/media/enhancement/amvecm/amcm.h create mode 100644 drivers/amlogic/media/enhancement/amvecm/amcm_regmap.h create mode 100644 drivers/amlogic/media/enhancement/amvecm/amcsc.c create mode 100644 drivers/amlogic/media/enhancement/amvecm/amcsc.h create mode 100644 drivers/amlogic/media/enhancement/amvecm/amdolby_vision.c create mode 100644 drivers/amlogic/media/enhancement/amvecm/amve.c create mode 100644 drivers/amlogic/media/enhancement/amvecm/amve.h create mode 100644 drivers/amlogic/media/enhancement/amvecm/amve_gamma_table.h create mode 100644 drivers/amlogic/media/enhancement/amvecm/amvecm.c create mode 100644 drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h create mode 100644 drivers/amlogic/media/enhancement/amvecm/arch/cm_regs.h create mode 100644 drivers/amlogic/media/enhancement/amvecm/arch/hdr_curve.h create mode 100644 drivers/amlogic/media/enhancement/amvecm/arch/ve_regs.h create mode 100644 drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h create mode 100644 drivers/amlogic/media/enhancement/amvecm/arch/vpp_hdr_regs.h create mode 100644 drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h create mode 100644 drivers/amlogic/media/enhancement/amvecm/dolby_vision/dolby_vision.h create mode 100644 include/linux/amlogic/media/amvecm/amvecm.h create mode 100644 include/linux/amlogic/media/amvecm/ve.h diff --git a/MAINTAINERS b/MAINTAINERS index 73a7f50..c7ec290 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13817,3 +13817,22 @@ F: arch/arm/boot/dts/amlogic/meson8b_m400.dts AMLOGIC LOCAL TIMER M: Jianxin Pan F: drivers/amlogic/clocksource + +AMLOGIC AMVECM, PQ, HDR +M: Mingliang Dong +F: drivers/amlogic/media/enhancement/amvecm/amcm.c +F: drivers/amlogic/media/enhancement/amvecm/amcm.h +F: drivers/amlogic/media/enhancement/amvecm/amcm_regmap.h +F: drivers/amlogic/media/enhancement/amvecm/amcsc.c +F: drivers/amlogic/media/enhancement/amvecm/amcsc.h +F: drivers/amlogic/media/enhancement/amvecm/amdolby_vision.c +F: drivers/amlogic/media/enhancement/amvecm/amve.c +F: drivers/amlogic/media/enhancement/amvecm/amve.h +F: drivers/amlogic/media/enhancement/amvecm/amve_gamma_table.h +F: drivers/amlogic/media/enhancement/amvecm/amvecm.c +F: drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h +F: drivers/amlogic/media/enhancement/amvecm/Kconfig +F: drivers/amlogic/media/enhancement/amvecm/Makefile +F: drivers/amlogic/media/enhancement/amvecm/dolby_vision/* +F: drivers/amlogic/media/enhancement/amvecm/arch/* +F: include/linux/amlogic/media/amvecm/* diff --git a/arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts b/arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts index 56dc6f4..28ee87b 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts @@ -1057,6 +1057,15 @@ tv_bit_mode = <1>; }; + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + unifykey{ compatible = "amlogic, unifykey"; status = "ok"; diff --git a/arch/arm64/boot/dts/amlogic/gxl_p212_2g.dts b/arch/arm64/boot/dts/amlogic/gxl_p212_2g.dts index f1e3362..9cfbae5 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p212_2g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p212_2g.dts @@ -1058,6 +1058,15 @@ tv_bit_mode = <1>; }; + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + unifykey{ compatible = "amlogic, unifykey"; status = "ok"; diff --git a/arch/arm64/boot/dts/amlogic/gxm_q200_2g.dts b/arch/arm64/boot/dts/amlogic/gxm_q200_2g.dts index 9cc1997..0f7bdc0 100644 --- a/arch/arm64/boot/dts/amlogic/gxm_q200_2g.dts +++ b/arch/arm64/boot/dts/amlogic/gxm_q200_2g.dts @@ -1077,6 +1077,16 @@ */ tv_bit_mode = <1>; }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + unifykey{ compatible = "amlogic, unifykey"; status = "ok"; diff --git a/arch/arm64/boot/dts/amlogic/gxm_skt.dts b/arch/arm64/boot/dts/amlogic/gxm_skt.dts index 246e25d..e2a657e 100644 --- a/arch/arm64/boot/dts/amlogic/gxm_skt.dts +++ b/arch/arm64/boot/dts/amlogic/gxm_skt.dts @@ -877,6 +877,14 @@ tv_bit_mode = <1>; }; + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; partitions: partitions{ parts = <11>; diff --git a/arch/arm64/configs/meson64_defconfig b/arch/arm64/configs/meson64_defconfig index abb6be8..da768ef 100644 --- a/arch/arm64/configs/meson64_defconfig +++ b/arch/arm64/configs/meson64_defconfig @@ -221,6 +221,8 @@ CONFIG_AMLOGIC_MEDIA_VIN=y CONFIG_AMLOGIC_MEDIA_TVIN=y CONFIG_AMLOGIC_MEDIA_VDIN=y CONFIG_AMLOGIC_MEDIA_VIUIN=y +CONFIG_AMLOGIC_MEDIA_ENHANCEMENT=y +CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM=y CONFIG_AMLOGIC_VIDEO_PROCESSOR=y CONFIG_AMLOGIC_V4L_VIDEO=y CONFIG_AMLOGIC_V4L_VIDEO2=y diff --git a/drivers/amlogic/media/Kconfig b/drivers/amlogic/media/Kconfig index ea35a8a..e04b50f 100644 --- a/drivers/amlogic/media/Kconfig +++ b/drivers/amlogic/media/Kconfig @@ -47,6 +47,7 @@ source "drivers/amlogic/media/osd_ext/Kconfig" source "drivers/amlogic/media/deinterlace/Kconfig" source "drivers/amlogic/media/vin/Kconfig" source "drivers/amlogic/media/video_processor/Kconfig" +source "drivers/amlogic/media/enhancement/Kconfig" endif endmenu diff --git a/drivers/amlogic/media/Makefile b/drivers/amlogic/media/Makefile index e42b2a9..f89222e 100644 --- a/drivers/amlogic/media/Makefile +++ b/drivers/amlogic/media/Makefile @@ -6,4 +6,5 @@ obj-$(CONFIG_AMLOGIC_MEDIA_DRIVERS) += osd/ obj-$(CONFIG_AMLOGIC_MEDIA_DRIVERS) += osd_ext/ obj-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += deinterlace/ obj-$(CONFIG_AMLOGIC_MEDIA_VIN) += vin/ -obj-$(CONFIG_AMLOGIC_MEDIA_DRIVERS) += video_processor/ \ No newline at end of file +obj-$(CONFIG_AMLOGIC_MEDIA_DRIVERS) += video_processor/ +obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT) += enhancement/ \ No newline at end of file diff --git a/drivers/amlogic/media/common/vfm/vframe_provider.c b/drivers/amlogic/media/common/vfm/vframe_provider.c index b21663a..54f34aa 100644 --- a/drivers/amlogic/media/common/vfm/vframe_provider.c +++ b/drivers/amlogic/media/common/vfm/vframe_provider.c @@ -105,6 +105,26 @@ int vf_notify_provider(const char *receiver_name, int event_type, void *data) } EXPORT_SYMBOL(vf_notify_provider); +int vf_notify_provider_by_name(const char *provider_name, int event_type, + void *data) +{ + int ret = -1; + struct vframe_provider_s *provider = + vf_get_provider_by_name(provider_name); + if (provider) { + if (provider->ops && provider->ops->event_cb) { + provider->ops->event_cb(event_type, data, + provider->op_arg); + ret = 0; + } + } else{ + /* pr_err("Error: %s, fail to get provider of receiver %s\n",*/ + /*__func__, receiver_name); */ + } + return ret; +} +EXPORT_SYMBOL(vf_notify_provider_by_name); + void vf_provider_init(struct vframe_provider_s *prov, const char *name, const struct vframe_operations_s *ops, void *op_arg) { diff --git a/drivers/amlogic/media/enhancement/Kconfig b/drivers/amlogic/media/enhancement/Kconfig new file mode 100644 index 0000000..4934a96 --- /dev/null +++ b/drivers/amlogic/media/enhancement/Kconfig @@ -0,0 +1,16 @@ +# +# Amlogic multimedia input configuration +# +menu "Amlogic Enhancement drivers" +config AMLOGIC_MEDIA_ENHANCEMENT + bool "Amlogic driver of enhancement" + depends on AMLOGIC_MEDIA_DRIVERS + default n + help + "Amlogic amvecm module init" + +if AMLOGIC_MEDIA_ENHANCEMENT +source "drivers/amlogic/media/enhancement/amvecm/Kconfig" +endif + +endmenu diff --git a/drivers/amlogic/media/enhancement/Makefile b/drivers/amlogic/media/enhancement/Makefile new file mode 100644 index 0000000..d7762a8 --- /dev/null +++ b/drivers/amlogic/media/enhancement/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) += amvecm/ diff --git a/drivers/amlogic/media/enhancement/amvecm/Kconfig b/drivers/amlogic/media/enhancement/amvecm/Kconfig new file mode 100644 index 0000000..6d54133 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/Kconfig @@ -0,0 +1,14 @@ +# +# AMLOGIC amvecm devices configuration +# + +comment "Amlogic VECM Drivers" + +menu "Amlogic amvecm Driver" + +config AMLOGIC_MEDIA_ENHANCEMENT_VECM + bool "Amlogic amvecm driver" + default n + help + "Amlogic amvecm module init" +endmenu diff --git a/drivers/amlogic/media/enhancement/amvecm/Makefile b/drivers/amlogic/media/enhancement/amvecm/Makefile new file mode 100644 index 0000000..78611ec --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/Makefile @@ -0,0 +1,8 @@ +# +# AMLOGIC VE & CM. +# + +ccflags-y := -I$(PWD)/$(src)/dolby_vision/ +obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) += am_vecm.o +am_vecm-objs := amve.o amcm.o amcsc.o amvecm.o amdolby_vision.o + diff --git a/drivers/amlogic/media/enhancement/amvecm/amcm.c b/drivers/amlogic/media/enhancement/amvecm/amcm.c new file mode 100644 index 0000000..4b0967e --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/amcm.c @@ -0,0 +1,512 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amcm.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/* #include */ +#include +#include + +#include +/* #include */ +#include +#include +#include +#include "arch/vpp_regs.h" +#include "arch/cm_regs.h" +#include "amcm.h" +#include "amcm_regmap.h" + +#define pr_amcm_dbg(fmt, args...)\ + do {\ + if (debug_amcm)\ + pr_info("AMCM: " fmt, ## args);\ + } while (0)\ + +static bool debug_amcm; +module_param(debug_amcm, bool, 0664); +MODULE_PARM_DESC(debug_amcm, "\n debug_amcm\n"); + +static bool debug_regload; +module_param(debug_regload, bool, 0664); +MODULE_PARM_DESC(debug_regload, "\n debug_regload\n"); + +static int cm_level = 1;/* 0:optimize;1:enhancement */ +module_param(cm_level, int, 0664); +MODULE_PARM_DESC(cm_level, "\n selcet cm lever\n"); + +int cm_en;/* 0:disabel;1:enable */ +module_param(cm_en, int, 0664); +MODULE_PARM_DESC(cm_en, "\n enable or disable cm\n"); + +static unsigned int cm_width_limit = 50;/* vlsi adjust */ +module_param(cm_width_limit, uint, 0664); +MODULE_PARM_DESC(cm_width_limit, "\n cm_width_limit\n"); + +#if 0 +struct cm_region_s cm_region; +struct cm_top_s cm_top; +struct cm_demo_s cm_demo; +#endif +static int cm_level_last = 0xff;/* 0:optimize;1:enhancement */ +unsigned int cm2_patch_flag; +unsigned int cm_size; +static struct am_regs_s amregs0; +static struct am_regs_s amregs1; +static struct am_regs_s amregs2; +static struct am_regs_s amregs3; +static struct am_regs_s amregs4; +static struct am_regs_s amregs5; + +static struct sr1_regs_s sr1_regs[101]; + +/* extern unsigned int vecm_latch_flag; */ + +void am_set_regmap(struct am_regs_s *p) +{ + unsigned short i; + unsigned int temp = 0; + unsigned short sr1_temp = 0; + + for (i = 0; i < p->length; i++) { + switch (p->am_reg[i].type) { + case REG_TYPE_PHY: + break; + case REG_TYPE_CBUS: + if (p->am_reg[i].mask == 0xffffffff) + /* WRITE_CBUS_REG(p->am_reg[i].addr,*/ + /* p->am_reg[i].val); */ + aml_write_cbus(p->am_reg[i].addr, + p->am_reg[i].val); + else + /* WRITE_CBUS_REG(p->am_reg[i].addr, */ + /* (READ_CBUS_REG(p->am_reg[i].addr) & */ + /* (~(p->am_reg[i].mask))) | */ + /* (p->am_reg[i].val & p->am_reg[i].mask)); */ + aml_write_cbus(p->am_reg[i].addr, + (aml_read_cbus(p->am_reg[i].addr) & + (~(p->am_reg[i].mask))) | + (p->am_reg[i].val & p->am_reg[i].mask)); + break; + case REG_TYPE_APB: + /* if (p->am_reg[i].mask == 0xffffffff) */ + /* WRITE_APB_REG(p->am_reg[i].addr,*/ + /* p->am_reg[i].val); */ + /* else */ + /* WRITE_APB_REG(p->am_reg[i].addr, */ + /* (READ_APB_REG(p->am_reg[i].addr) & */ + /* (~(p->am_reg[i].mask))) | */ + /* (p->am_reg[i].val & p->am_reg[i].mask)); */ + break; + case REG_TYPE_MPEG: + /* if (p->am_reg[i].mask == 0xffffffff) */ + /* WRITE_MPEG_REG(p->am_reg[i].addr,*/ + /* p->am_reg[i].val); */ + /* else */ + /* WRITE_MPEG_REG(p->am_reg[i].addr, */ + /* (READ_MPEG_REG(p->am_reg[i].addr) & */ + /* (~(p->am_reg[i].mask))) | */ + /* (p->am_reg[i].val & p->am_reg[i].mask)); */ + break; + case REG_TYPE_AXI: + /* if (p->am_reg[i].mask == 0xffffffff) */ + /* WRITE_AXI_REG(p->am_reg[i].addr,*/ + /* p->am_reg[i].val); */ + /* else */ + /* WRITE_AXI_REG(p->am_reg[i].addr, */ + /* (READ_AXI_REG(p->am_reg[i].addr) & */ + /* (~(p->am_reg[i].mask))) | */ + /* (p->am_reg[i].val & p->am_reg[i].mask)); */ + break; + case REG_TYPE_INDEX_VPPCHROMA: + /* add for vm2 demo frame size setting */ + if (p->am_reg[i].addr == 0x20f) { + if ((p->am_reg[i].val & 0xff) != 0) { + cm2_patch_flag = p->am_reg[i].val; + p->am_reg[i].val = + p->am_reg[i].val & 0xffffff00; + } else + cm2_patch_flag = 0; + } + /* add for cm patch size config */ + if ((p->am_reg[i].addr == 0x205) || + (p->am_reg[i].addr == 0x209) || + (p->am_reg[i].addr == 0x20a)) { + pr_amcm_dbg("[amcm]:%s REG_TYPE_INDEX_VPPCHROMA addr:0x%x", + __func__, p->am_reg[i].addr); + break; + } + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, + p->am_reg[i].addr); + if (p->am_reg[i].mask == 0xffffffff) + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, + p->am_reg[i].val); + else { + temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, + p->am_reg[i].addr); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, + (temp & (~(p->am_reg[i].mask))) | + (p->am_reg[i].val & p->am_reg[i].mask)); + } + break; + case REG_TYPE_INDEX_GAMMA: + break; + case VALUE_TYPE_CONTRAST_BRIGHTNESS: + break; + case REG_TYPE_INDEX_VPP_COEF: + if (((p->am_reg[i].addr&0xf) == 0) || + ((p->am_reg[i].addr&0xf) == 0x8)) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, + p->am_reg[i].addr); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, + p->am_reg[i].val); + } else + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, + p->am_reg[i].val); + break; +/* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESONG9TV) */ + case REG_TYPE_VCBUS: + if (p->am_reg[i].mask == 0xffffffff) + /* WRITE_VCBUS_REG(p->am_reg[i].addr,*/ + /* p->am_reg[i].val); */ + aml_write_vcbus(p->am_reg[i].addr, + p->am_reg[i].val); + else + /* WRITE_VCBUS_REG(p->am_reg[i].addr, */ + /* (READ_VCBUS_REG(p->am_reg[i].addr) & */ + /* (~(p->am_reg[i].mask))) | */ + /* (p->am_reg[i].val & p->am_reg[i].mask)); */ + if ((is_meson_gxtvbb_cpu()) && + (p->am_reg[i].addr >= 0x3280) + && (p->am_reg[i].addr <= 0x32e4)) { + if (p->am_reg[i].addr == 0x32d7) + break; + sr1_temp = p->am_reg[i].addr - 0x3280; + sr1_regs[sr1_temp].addr = + p->am_reg[i].addr; + sr1_regs[sr1_temp].mask = + p->am_reg[i].mask; + sr1_regs[sr1_temp].val = + (sr1_regs[sr1_temp].val & + (~(p->am_reg[i].mask))) | + (p->am_reg[i].val & p->am_reg[i].mask); + sr1_reg_val[sr1_temp] = + sr1_regs[sr1_temp].val; + aml_write_vcbus(p->am_reg[i].addr, + sr1_regs[sr1_temp].val); + } else { + if (p->am_reg[i].addr == 0x1d26) + break; + aml_write_vcbus(p->am_reg[i].addr, + (aml_read_vcbus(p->am_reg[i].addr) & + (~(p->am_reg[i].mask))) | + (p->am_reg[i].val & p->am_reg[i].mask)); + } + break; +/* #endif */ + default: + break; + } + } +} + +void amcm_disable(void) +{ + int temp; + + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208); + temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + if (temp & 0x2) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, temp & 0xfffffffd); + } +} + +void amcm_enable(void) +{ + int temp; + + if (!is_dolby_vision_enable()) { + if (!(READ_VPP_REG(VPP_MISC) & (0x1 << 28))) + WRITE_VPP_REG_BITS(VPP_MISC, 1, 28, 1); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208); + temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + if (!(temp & 0x2)) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, temp | 0x2); + } + } +} + + +void cm_regmap_latch(struct am_regs_s *am_regs, unsigned int reg_map) +{ + am_set_regmap(am_regs); + vecm_latch_flag &= ~reg_map; + pr_amcm_dbg("\n[amcm..] load reg %d table OK!!!\n", reg_map); +} + +void amcm_level_sel(unsigned int cm_level) +{ + int temp; + + if (cm_level == 1) + am_set_regmap(&cmreg_lever1); + else if (cm_level == 2) + am_set_regmap(&cmreg_lever2); + else if (cm_level == 3) + am_set_regmap(&cmreg_lever3); + else if (cm_level == 4) + am_set_regmap(&cmreg_enhancement); + else + am_set_regmap(&cmreg_optimize); + + if (!is_dolby_vision_enable()) { + if (!(READ_VPP_REG(VPP_MISC) & (0x1 << 28))) + WRITE_VPP_REG_BITS(VPP_MISC, 1, 28, 1); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208); + temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + if (!(temp & 0x2)) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, temp | 0x2); + } + } +} + +void cm2_frame_size_patch(unsigned int width, unsigned int height) +{ + unsigned int vpp_size; + + if (width < cm_width_limit) + amcm_disable(); + if (!cm_en) + return; + + vpp_size = width|(height << 16); + if (cm_size != vpp_size) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x205); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, vpp_size); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x209); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, width<<15); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x20a); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, height<<16); + cm_size = vpp_size; + pr_amcm_dbg("\n[amcm..]cm2_frame_patch: set cm2 framesize %x, ", + vpp_size); + pr_amcm_dbg("set demo mode %x\n", cm2_patch_flag); + } +} + + +/* set the frame size for cm2 demo*/ +void cm2_frame_switch_patch(void) +{ + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x20f); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, cm2_patch_flag); +} + +void cm_latch_process(void) +{ + /*if ((vecm_latch_flag & FLAG_REG_MAP0) ||*/ + /*(vecm_latch_flag & FLAG_REG_MAP1) ||*/ + /*(vecm_latch_flag & FLAG_REG_MAP2) ||*/ + /*(vecm_latch_flag & FLAG_REG_MAP3) ||*/ + /*(vecm_latch_flag & FLAG_REG_MAP4) ||*/ + /* (vecm_latch_flag & FLAG_REG_MAP5)){*/ + do { + if (vecm_latch_flag & FLAG_REG_MAP0) { + cm_regmap_latch(&amregs0, FLAG_REG_MAP0); + break; + } + if (vecm_latch_flag & FLAG_REG_MAP1) { + cm_regmap_latch(&amregs1, FLAG_REG_MAP1); + break; + } + if (vecm_latch_flag & FLAG_REG_MAP2) { + cm_regmap_latch(&amregs2, FLAG_REG_MAP2); + break; + } + if (vecm_latch_flag & FLAG_REG_MAP3) { + cm_regmap_latch(&amregs3, FLAG_REG_MAP3); + break; + } + if (vecm_latch_flag & FLAG_REG_MAP4) { + cm_regmap_latch(&amregs4, FLAG_REG_MAP4); + break; + } + if (vecm_latch_flag & FLAG_REG_MAP5) { + cm_regmap_latch(&amregs5, FLAG_REG_MAP5); + break; + } + if ((cm2_patch_flag & 0xff) > 0) + cm2_frame_switch_patch(); + } while (0); + if (cm_en && (cm_level_last != cm_level)) { + cm_level_last = cm_level; + if ((!is_meson_gxtvbb_cpu()) && (!is_meson_txl_cpu())) + amcm_level_sel(cm_level); + amcm_enable(); + pr_amcm_dbg("\n[amcm..] set cm2 load OK!!!\n"); + } else if ((cm_en == 0) && (cm_level_last != 0xff)) { + cm_level_last = 0xff; + amcm_disable();/* CM manage disable */ + } +} + +static int amvecm_regmap_info(struct am_regs_s *p) +{ + unsigned short i; + + for (i = 0; i < p->length; i++) { + switch (p->am_reg[i].type) { + case REG_TYPE_PHY: + pr_info("%s:%d bus type: phy...\n", __func__, i); + break; + case REG_TYPE_CBUS: + pr_info("%s:%-3d cbus: 0x%-4x=0x%-8x (%-5u)=(%-10u)", + __func__, i, p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask), + p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask)); + pr_info(" mask=%-8x(%u)\n", + p->am_reg[i].mask, + p->am_reg[i].mask); + break; + case REG_TYPE_APB: + pr_info("%s:%-3d apb: 0x%-4x=0x%-8x (%-5u)=(%-10u)", + __func__, i, p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask), + p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask)); + pr_info(" mask=%-8x(%u)\n", + p->am_reg[i].mask, + p->am_reg[i].mask); + break; + case REG_TYPE_MPEG: + pr_info("%s:%-3d mpeg: 0x%-4x=0x%-8x (%-5u)=(%-10u)", + __func__, i, p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask), + p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask)); + pr_info(" mask=%-8x(%u)\n", + p->am_reg[i].mask, + p->am_reg[i].mask); + break; + case REG_TYPE_AXI: + pr_info("%s:%-3d axi: 0x%-4x=0x%-8x (%-5u)=(%-10u)", + __func__, i, p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask), + p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask)); + pr_info(" mask=%-8x(%u)\n", + p->am_reg[i].mask, + p->am_reg[i].mask); + break; + case REG_TYPE_INDEX_VPPCHROMA: + pr_info("%s:%-3d chroma: 0x%-4x=0x%-8x (%-5u)=(%-10u)", + __func__, i, p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask), + p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask)); + pr_info(" mask=%-8x(%u)\n", + p->am_reg[i].mask, + p->am_reg[i].mask); + break; + case REG_TYPE_INDEX_GAMMA: + pr_info("%s:%-3d bus type: REG_TYPE_INDEX_GAMMA...\n", + __func__, i); + break; + case VALUE_TYPE_CONTRAST_BRIGHTNESS: + pr_info("%s:%-3d bus type: VALUE_TYPE_CONTRAST_BRIGHTNESS...\n", + __func__, i); + break; + case REG_TYPE_INDEX_VPP_COEF: + pr_info("%s:%-3d vpp coef: 0x%-4x=0x%-8x (%-5u)=(%-10u)", + __func__, i, p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask), + p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask)); + pr_info(" mask=%-8x(%u)\n", + p->am_reg[i].mask, + p->am_reg[i].mask); + break; + case REG_TYPE_VCBUS: + pr_info("%s:%-3d vcbus: 0x%-4x=0x%-8x (%-5u)=(%-10u)", + __func__, i, p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask), + p->am_reg[i].addr, + (p->am_reg[i].val & p->am_reg[i].mask)); + pr_info(" mask=%-8x(%u)\n", p->am_reg[i].mask, + p->am_reg[i].mask); + break; + default: + pr_info("%s:%3d bus type error!!!bustype = 0x%x...\n", + __func__, i, p->am_reg[i].type); + break; + } + } + return 0; +} + +static long amvecm_regmap_set(struct am_regs_s *regs, + struct am_regs_s *arg, unsigned int reg_map) +{ + int ret = 0; + + if (!(memcpy(regs, arg, sizeof(struct am_regs_s)))) { + pr_amcm_dbg( + "[amcm..]0x%x load reg errors: can't get buffer length\n", + reg_map); + return -EFAULT; + } + if (!regs->length || (regs->length > am_reg_size)) { + pr_amcm_dbg( + "[amcm..]0x%x load regs error: buf length error!!!, length=0x%x\n", + reg_map, regs->length); + return -EINVAL; + } + pr_amcm_dbg("\n[amcm..]0x%x reg length=0x%x ......\n", + reg_map, regs->length); + + if (debug_regload) + amvecm_regmap_info(regs); + + vecm_latch_flag |= reg_map; + + return ret; +} + +int cm_load_reg(struct am_regs_s *arg) +{ + int ret = 0; + /*force set cm size to 0,enable check vpp size*/ + cm_size = 0; + if (!(vecm_latch_flag & FLAG_REG_MAP0)) + ret = amvecm_regmap_set(&amregs0, arg, FLAG_REG_MAP0); + else if (!(vecm_latch_flag & FLAG_REG_MAP1)) + ret = amvecm_regmap_set(&amregs1, arg, FLAG_REG_MAP1); + else if (!(vecm_latch_flag & FLAG_REG_MAP2)) + ret = amvecm_regmap_set(&amregs2, arg, FLAG_REG_MAP2); + else if (!(vecm_latch_flag & FLAG_REG_MAP3)) + ret = amvecm_regmap_set(&amregs3, arg, FLAG_REG_MAP3); + else if (!(vecm_latch_flag & FLAG_REG_MAP4)) + ret = amvecm_regmap_set(&amregs4, arg, FLAG_REG_MAP4); + else if (!(vecm_latch_flag & FLAG_REG_MAP5)) + ret = amvecm_regmap_set(&amregs5, arg, FLAG_REG_MAP5); + + return ret; +} + diff --git a/drivers/amlogic/media/enhancement/amvecm/amcm.h b/drivers/amlogic/media/enhancement/amvecm/amcm.h new file mode 100644 index 0000000..32fe90f --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/amcm.h @@ -0,0 +1,88 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amcm.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __AM_CM_H +#define __AM_CM_H + + +#include +#include "linux/amlogic/media/amvecm/cm.h" + +struct cm_regs_s { + unsigned int val:32; + unsigned int reg:14; + unsigned int port:2; + /* 0 NA NA direct access */ + /* 1 VPP_CHROMA_ADDR_PORT */ + /* VPP_CHROMA_DATA_PORT CM port registers */ + /* 2 NA NA reserved */ + /* 3 NA NA reserved */ + unsigned int bit:5; + unsigned int wid:5; + unsigned int mode:1; + unsigned int rsv:5; +}; + +struct sr1_regs_s { + unsigned int addr; + unsigned int mask; + unsigned int val; +}; + +extern unsigned int vecm_latch_flag; +extern unsigned int cm_size; +extern unsigned int cm2_patch_flag; +extern int cm_en; /* 0:disabel;1:enable */ +extern int dnlp_en;/*0:disabel;1:enable */ + +extern unsigned int sr1_reg_val[101]; + +/* *********************************************************************** */ +/* *** IOCTL-oriented functions ****************************************** */ +/* *********************************************************************** */ +void am_set_regmap(struct am_regs_s *p); +extern void amcm_disable(void); +extern void amcm_enable(void); +extern void amcm_level_sel(unsigned int cm_level); +extern void cm2_frame_size_patch(unsigned int width, unsigned int height); +extern void cm2_frame_switch_patch(void); +extern void cm_latch_process(void); +extern int cm_load_reg(struct am_regs_s *arg); + +/* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8) */ +/* #define WRITE_VPP_REG(x,val) */ +/* WRITE_VCBUS_REG(x,val) */ +/* #define WRITE_VPP_REG_BITS(x,val,start,length) */ +/* WRITE_VCBUS_REG_BITS(x,val,start,length) */ +/* #define READ_VPP_REG(x) */ +/* READ_VCBUS_REG(x) */ +/* #define READ_VPP_REG_BITS(x,start,length) */ +/* READ_VCBUS_REG_BITS(x,start,length) */ +/* #else */ +/* #define WRITE_VPP_REG(x,val) */ +/* WRITE_CBUS_REG(x,val) */ +/* #define WRITE_VPP_REG_BITS(x,val,start,length) */ +/* WRITE_CBUS_REG_BITS(x,val,start,length) */ +/* #define READ_VPP_REG(x) */ +/* READ_CBUS_REG(x) */ +/* #define READ_VPP_REG_BITS(x,start,length) */ +/* READ_CBUS_REG_BITS(x,start,length) */ +/* #endif */ + + +#endif + diff --git a/drivers/amlogic/media/enhancement/amvecm/amcm_regmap.h b/drivers/amlogic/media/enhancement/amvecm/amcm_regmap.h new file mode 100644 index 0000000..504a574 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/amcm_regmap.h @@ -0,0 +1,922 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amcm_regmap.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __AM_CM_REGMAP_H +#define __AM_CM_REGMAP_H + +#include + +static struct am_regs_s cmreg_lever1 = { + 172, + { + /* optimize */ + {REG_TYPE_INDEX_VPPCHROMA, 512, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 513, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 514, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 515, 0xffffffff, 134218752 }, + {REG_TYPE_INDEX_VPPCHROMA, 516, 0xffffffff, 144 }, + {REG_TYPE_INDEX_VPPCHROMA, 518, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 519, 0xffffffff, 33554432 }, + {REG_TYPE_INDEX_VPPCHROMA, 520, 0xffffffff, 118 }, + {REG_TYPE_INDEX_VPPCHROMA, 521, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 522, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 527, 0xf, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 517, 0xffffffff, 70715263 }, + {REG_TYPE_INDEX_VPP_COEF, 256, 0xffffffff, 532992 }, + {REG_TYPE_INDEX_VPP_COEF, 257, 0xffffffff, 0xf3f600af }, + {REG_TYPE_INDEX_VPP_COEF, 258, 0xffffffff, 0xe3000000 }, + {REG_TYPE_INDEX_VPP_COEF, 259, 0xffffffff, 240 }, + {REG_TYPE_INDEX_VPP_COEF, 260, 0xffffffff, 63506 }, + {REG_TYPE_INDEX_VPP_COEF, 264, 0xffffffff, 16650496 }, + {REG_TYPE_INDEX_VPP_COEF, 265, 0xffffffff, 249 }, + {REG_TYPE_INDEX_VPP_COEF, 266, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 267, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 268, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 272, 0xffffffff, 135936 }, + {REG_TYPE_INDEX_VPP_COEF, 273, 0xffffffff, 253 }, + {REG_TYPE_INDEX_VPP_COEF, 274, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 275, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 276, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 280, 0xffffffff, 0xf3f11300 }, + {REG_TYPE_INDEX_VPP_COEF, 281, 0xffffffff, 214 }, + {REG_TYPE_INDEX_VPP_COEF, 282, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 283, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 284, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 288, 0xffffffff, 0xede91300 }, + {REG_TYPE_INDEX_VPP_COEF, 289, 0xffffffff, 177 }, + {REG_TYPE_INDEX_VPP_COEF, 290, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 291, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 292, 0xffffffff, 15660544 }, + {REG_TYPE_INDEX_VPP_COEF, 296, 0xffffffff, 0xe9e61100 }, + {REG_TYPE_INDEX_VPP_COEF, 297, 0xffffffff, 184 }, + {REG_TYPE_INDEX_VPP_COEF, 298, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 299, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 300, 0xffffffff, 15464448 }, + {REG_TYPE_INDEX_VPP_COEF, 304, 0xffffffff, 0xeff80f00 }, + {REG_TYPE_INDEX_VPP_COEF, 305, 0xffffffff, 232 }, + {REG_TYPE_INDEX_VPP_COEF, 306, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 307, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 308, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 312, 0xffffffff, 0xf60a0d00 }, + {REG_TYPE_INDEX_VPP_COEF, 313, 0xffffffff, 245 }, + {REG_TYPE_INDEX_VPP_COEF, 314, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 315, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 316, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 320, 0xffffffff, 526848 }, + {REG_TYPE_INDEX_VPP_COEF, 321, 0xffffffff, 238 }, + {REG_TYPE_INDEX_VPP_COEF, 322, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 323, 0xffffffff, 10 }, + {REG_TYPE_INDEX_VPP_COEF, 324, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 328, 0xffffffff, 527616 }, + {REG_TYPE_INDEX_VPP_COEF, 329, 0xffffffff, 134742245 }, + {REG_TYPE_INDEX_VPP_COEF, 330, 0xffffffff, 167903232 }, + {REG_TYPE_INDEX_VPP_COEF, 331, 0xffffffff, 21 }, + {REG_TYPE_INDEX_VPP_COEF, 332, 0xffffffff, 3328 }, + {REG_TYPE_INDEX_VPP_COEF, 336, 0xffffffff, 397056 }, + {REG_TYPE_INDEX_VPP_COEF, 337, 0xffffffff, 0xf80d00da }, + {REG_TYPE_INDEX_VPP_COEF, 338, 0xffffffff, 0xf80500fb }, + {REG_TYPE_INDEX_VPP_COEF, 339, 0xffffffff, 2 }, + {REG_TYPE_INDEX_VPP_COEF, 340, 0xffffffff, 132357 }, + {REG_TYPE_INDEX_VPP_COEF, 344, 0xffffffff, 526848 }, + {REG_TYPE_INDEX_VPP_COEF, 345, 0xffffffff, 0xfb0a00c7 }, + {REG_TYPE_INDEX_VPP_COEF, 346, 0xffffffff, 0xf6020002 }, + {REG_TYPE_INDEX_VPP_COEF, 347, 0xffffffff, 251 }, + {REG_TYPE_INDEX_VPP_COEF, 348, 0xffffffff, 16646656 }, + {REG_TYPE_INDEX_VPP_COEF, 352, 0xffffffff, 657408 }, + {REG_TYPE_INDEX_VPP_COEF, 353, 0xffffffff, 327857 }, + {REG_TYPE_INDEX_VPP_COEF, 354, 0xffffffff, 0xf6050000 }, + {REG_TYPE_INDEX_VPP_COEF, 355, 0xffffffff, 2 }, + {REG_TYPE_INDEX_VPP_COEF, 356, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 360, 0xffffffff, 526336 }, + {REG_TYPE_INDEX_VPP_COEF, 361, 0xffffffff, 162 }, + {REG_TYPE_INDEX_VPP_COEF, 362, 0xffffffff, 0xf600f600 }, + {REG_TYPE_INDEX_VPP_COEF, 363, 0xffffffff, 254 }, + {REG_TYPE_INDEX_VPP_COEF, 364, 0xffffffff, 33554432 }, + {REG_TYPE_INDEX_VPP_COEF, 368, 0xffffffff, 986368 }, + {REG_TYPE_INDEX_VPP_COEF, 369, 0xffffffff, 166 }, + {REG_TYPE_INDEX_VPP_COEF, 370, 0xffffffff, 0xf300eef6 }, + {REG_TYPE_INDEX_VPP_COEF, 371, 0xffffffff, 243 }, + {REG_TYPE_INDEX_VPP_COEF, 372, 0xffffffff, 0xfb050000 }, + {REG_TYPE_INDEX_VPP_COEF, 376, 0xffffffff, 34541312 }, + {REG_TYPE_INDEX_VPP_COEF, 377, 0xffffffff, 83886277 }, + {REG_TYPE_INDEX_VPP_COEF, 378, 0xffffffff, 0xfbfef8f8 }, + {REG_TYPE_INDEX_VPP_COEF, 379, 0xffffffff, 246 }, + {REG_TYPE_INDEX_VPP_COEF, 380, 0xffffffff, 0xf8080200 }, + {REG_TYPE_INDEX_VPP_COEF, 384, 0xffffffff, 286331136 }, + {REG_TYPE_INDEX_VPP_COEF, 385, 0xffffffff, 353698041 }, + {REG_TYPE_INDEX_VPP_COEF, 386, 0xffffffff, 168427768 }, + {REG_TYPE_INDEX_VPP_COEF, 387, 0xffffffff, 13 }, + {REG_TYPE_INDEX_VPP_COEF, 388, 0xffffffff, 0xfb081000 }, + {REG_TYPE_INDEX_VPP_COEF, 392, 0xffffffff, 218960128 }, + {REG_TYPE_INDEX_VPP_COEF, 393, 0xffffffff, 674758687 }, + {REG_TYPE_INDEX_VPP_COEF, 394, 0xffffffff, 573177856 }, + {REG_TYPE_INDEX_VPP_COEF, 395, 0xffffffff, 21 }, + {REG_TYPE_INDEX_VPP_COEF, 396, 0xffffffff, 854766 }, + {REG_TYPE_INDEX_VPP_COEF, 400, 0xffffffff, 168430080 }, + {REG_TYPE_INDEX_VPP_COEF, 401, 0xffffffff, 809304110 }, + {REG_TYPE_INDEX_VPP_COEF, 402, 0xffffffff, 674234389 }, + {REG_TYPE_INDEX_VPP_COEF, 403, 0xffffffff, 13 }, + {REG_TYPE_INDEX_VPP_COEF, 404, 0xffffffff, 716515 }, + {REG_TYPE_INDEX_VPP_COEF, 408, 0xffffffff, 134745344 }, + {REG_TYPE_INDEX_VPP_COEF, 409, 0xffffffff, 807731246 }, + {REG_TYPE_INDEX_VPP_COEF, 410, 0xffffffff, 403308562 }, + {REG_TYPE_INDEX_VPP_COEF, 411, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 412, 0xffffffff, 59590 }, + {REG_TYPE_INDEX_VPP_COEF, 416, 0xffffffff, 67504640 }, + {REG_TYPE_INDEX_VPP_COEF, 417, 0xffffffff, 269484072 }, + {REG_TYPE_INDEX_VPP_COEF, 418, 0xffffffff, 182845440 }, + {REG_TYPE_INDEX_VPP_COEF, 419, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 420, 0xffffffff, 61139 }, + {REG_TYPE_INDEX_VPP_COEF, 424, 0xffffffff, 396544 }, + {REG_TYPE_INDEX_VPP_COEF, 425, 0xffffffff, 134217757 }, + {REG_TYPE_INDEX_VPP_COEF, 426, 0xffffffff, 0xfb0b0000 }, + {REG_TYPE_INDEX_VPP_COEF, 427, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 428, 0xffffffff, 246 }, + {REG_TYPE_INDEX_VPP_COEF, 432, 0xffffffff, 527616 }, + {REG_TYPE_INDEX_VPP_COEF, 433, 0xffffffff, 12 }, + {REG_TYPE_INDEX_VPP_COEF, 434, 0xffffffff, 15597568 }, + {REG_TYPE_INDEX_VPP_COEF, 435, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 436, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 440, 0xffffffff, 658688 }, + {REG_TYPE_INDEX_VPP_COEF, 441, 0xffffffff, 7 }, + {REG_TYPE_INDEX_VPP_COEF, 442, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 443, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 444, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 448, 0xffffffff, 986880 }, + {REG_TYPE_INDEX_VPP_COEF, 449, 0xffffffff, 255 }, + {REG_TYPE_INDEX_VPP_COEF, 450, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 451, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 452, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 456, 0xffffffff, 219811584 }, + {REG_TYPE_INDEX_VPP_COEF, 457, 0xffffffff, 238 }, + {REG_TYPE_INDEX_VPP_COEF, 458, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 459, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 460, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 464, 0xffffffff, 287183104 }, + {REG_TYPE_INDEX_VPP_COEF, 465, 0xffffffff, 197 }, + {REG_TYPE_INDEX_VPP_COEF, 466, 0xffffffff, 0xf3000000 }, + {REG_TYPE_INDEX_VPP_COEF, 467, 0xffffffff, 246 }, + {REG_TYPE_INDEX_VPP_COEF, 468, 0xffffffff, 0xfb000000 }, + {REG_TYPE_INDEX_VPP_COEF, 472, 0xffffffff, 219943168 }, + {REG_TYPE_INDEX_VPP_COEF, 473, 0xffffffff, 169 }, + {REG_TYPE_INDEX_VPP_COEF, 474, 0xffffffff, 0xf0000000 }, + {REG_TYPE_INDEX_VPP_COEF, 475, 0xffffffff, 232 }, + {REG_TYPE_INDEX_VPP_COEF, 476, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 480, 0xffffffff, 1707264 }, + {REG_TYPE_INDEX_VPP_COEF, 481, 0xffffffff, 0xfb0000ab }, + {REG_TYPE_INDEX_VPP_COEF, 482, 0xffffffff, 0xe300f3f3 }, + {REG_TYPE_INDEX_VPP_COEF, 483, 0xffffffff, 219 }, + {REG_TYPE_INDEX_VPP_COEF, 484, 0xffffffff, 15597568 }, + {REG_TYPE_INDEX_VPP_COEF, 488, 0xffffffff, 1509888 }, + {REG_TYPE_INDEX_VPP_COEF, 489, 0xffffffff, 0xf30000b6 }, + {REG_TYPE_INDEX_VPP_COEF, 490, 0xffffffff, 0xd800e8e3 }, + {REG_TYPE_INDEX_VPP_COEF, 491, 0xffffffff, 222 }, + {REG_TYPE_INDEX_VPP_COEF, 492, 0xffffffff, 14876680 }, + {REG_TYPE_INDEX_VPP_COEF, 496, 0xffffffff, 1117440 }, + {REG_TYPE_INDEX_VPP_COEF, 497, 0xffffffff, 0xf3fb00ba }, + {REG_TYPE_INDEX_VPP_COEF, 498, 0xffffffff, 0xd300ebe6 }, + {REG_TYPE_INDEX_VPP_COEF, 499, 0xffffffff, 232 }, + {REG_TYPE_INDEX_VPP_COEF, 500, 0xffffffff, 15661840 }, + {REG_TYPE_INDEX_VPP_COEF, 504, 0xffffffff, 989696 }, + {REG_TYPE_INDEX_VPP_COEF, 505, 0xffffffff, 0xf6f800b6 }, + {REG_TYPE_INDEX_VPP_COEF, 506, 0xffffffff, 0xe600f3f3 }, + {REG_TYPE_INDEX_VPP_COEF, 507, 0xffffffff, 235 }, + {REG_TYPE_INDEX_VPP_COEF, 508, 0xffffffff, 18 }, + {0} + } +}; +static struct am_regs_s cmreg_lever2 = { + 172, + { + /* optimize */ + {REG_TYPE_INDEX_VPPCHROMA, 512, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 513, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 514, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 515, 0xffffffff, 134218752 }, + {REG_TYPE_INDEX_VPPCHROMA, 516, 0xffffffff, 144 }, + {REG_TYPE_INDEX_VPPCHROMA, 518, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 519, 0xffffffff, 33554432 }, + {REG_TYPE_INDEX_VPPCHROMA, 520, 0xffffffff, 122 }, + {REG_TYPE_INDEX_VPPCHROMA, 521, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 522, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 527, 0xf, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 517, 0xffffffff, 70715263 }, + {REG_TYPE_INDEX_VPP_COEF, 256, 0xffffffff, 2840064 }, + {REG_TYPE_INDEX_VPP_COEF, 257, 0xffffffff, 12 }, + {REG_TYPE_INDEX_VPP_COEF, 258, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 259, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 260, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 264, 0xffffffff, 2708992 }, + {REG_TYPE_INDEX_VPP_COEF, 265, 0xffffffff, 31 }, + {REG_TYPE_INDEX_VPP_COEF, 266, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 267, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 268, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 272, 0xffffffff, 2708992 }, + {REG_TYPE_INDEX_VPP_COEF, 273, 0xffffffff, 51 }, + {REG_TYPE_INDEX_VPP_COEF, 274, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 275, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 276, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 280, 0xffffffff, 2840064 }, + {REG_TYPE_INDEX_VPP_COEF, 281, 0xffffffff, 63 }, + {REG_TYPE_INDEX_VPP_COEF, 282, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 283, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 284, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 288, 0xffffffff, 2840064 }, + {REG_TYPE_INDEX_VPP_COEF, 289, 0xffffffff, 63 }, + {REG_TYPE_INDEX_VPP_COEF, 290, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 291, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 292, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 296, 0xffffffff, 2708992 }, + {REG_TYPE_INDEX_VPP_COEF, 297, 0xffffffff, 63 }, + {REG_TYPE_INDEX_VPP_COEF, 298, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 299, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 300, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 304, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 305, 0xffffffff, 63 }, + {REG_TYPE_INDEX_VPP_COEF, 306, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 307, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 308, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 312, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 313, 0xffffffff, 51 }, + {REG_TYPE_INDEX_VPP_COEF, 314, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 315, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 316, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 320, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 321, 0xffffffff, 9 }, + {REG_TYPE_INDEX_VPP_COEF, 322, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 323, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 324, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 328, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 329, 0xffffffff, 234 }, + {REG_TYPE_INDEX_VPP_COEF, 330, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 331, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 332, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 336, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 337, 0xffffffff, 212 }, + {REG_TYPE_INDEX_VPP_COEF, 338, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 339, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 340, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 344, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 345, 0xffffffff, 197 }, + {REG_TYPE_INDEX_VPP_COEF, 346, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 347, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 348, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 352, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 353, 0xffffffff, 193 }, + {REG_TYPE_INDEX_VPP_COEF, 354, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 355, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 356, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 360, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 361, 0xffffffff, 203 }, + {REG_TYPE_INDEX_VPP_COEF, 362, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 363, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 364, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 368, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 369, 0xffffffff, 214 }, + {REG_TYPE_INDEX_VPP_COEF, 370, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 371, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 372, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 376, 0xffffffff, 2708992 }, + {REG_TYPE_INDEX_VPP_COEF, 377, 0xffffffff, 219 }, + {REG_TYPE_INDEX_VPP_COEF, 378, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 379, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 380, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 384, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 385, 0xffffffff, 236 }, + {REG_TYPE_INDEX_VPP_COEF, 386, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 387, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 388, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 392, 0xffffffff, 2708992 }, + {REG_TYPE_INDEX_VPP_COEF, 393, 0xffffffff, 249 }, + {REG_TYPE_INDEX_VPP_COEF, 394, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 395, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 396, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 400, 0xffffffff, 2708992 }, + {REG_TYPE_INDEX_VPP_COEF, 401, 0xffffffff, 3 }, + {REG_TYPE_INDEX_VPP_COEF, 402, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 403, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 404, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 408, 0xffffffff, 2708992 }, + {REG_TYPE_INDEX_VPP_COEF, 409, 0xffffffff, 9 }, + {REG_TYPE_INDEX_VPP_COEF, 410, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 411, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 412, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 416, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 417, 0xffffffff, 12 }, + {REG_TYPE_INDEX_VPP_COEF, 418, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 419, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 420, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 424, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 425, 0xffffffff, 14 }, + {REG_TYPE_INDEX_VPP_COEF, 426, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 427, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 428, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 432, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 433, 0xffffffff, 12 }, + {REG_TYPE_INDEX_VPP_COEF, 434, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 435, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 436, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 440, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 441, 0xffffffff, 7 }, + {REG_TYPE_INDEX_VPP_COEF, 442, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 443, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 444, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 448, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 449, 0xffffffff, 251 }, + {REG_TYPE_INDEX_VPP_COEF, 450, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 451, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 452, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 456, 0xffffffff, 2708480 }, + {REG_TYPE_INDEX_VPP_COEF, 457, 0xffffffff, 242 }, + {REG_TYPE_INDEX_VPP_COEF, 458, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 459, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 460, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 464, 0xffffffff, 36262912 }, + {REG_TYPE_INDEX_VPP_COEF, 465, 0xffffffff, 238 }, + {REG_TYPE_INDEX_VPP_COEF, 466, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 467, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 468, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 472, 0xffffffff, 69817344 }, + {REG_TYPE_INDEX_VPP_COEF, 473, 0xffffffff, 245 }, + {REG_TYPE_INDEX_VPP_COEF, 474, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 475, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 476, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 480, 0xffffffff, 136926208 }, + {REG_TYPE_INDEX_VPP_COEF, 481, 0xffffffff, 1 }, + {REG_TYPE_INDEX_VPP_COEF, 482, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 483, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 484, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 488, 0xffffffff, 136926208 }, + {REG_TYPE_INDEX_VPP_COEF, 489, 0xffffffff, 5 }, + {REG_TYPE_INDEX_VPP_COEF, 490, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 491, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 492, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 496, 0xffffffff, 136926208 }, + {REG_TYPE_INDEX_VPP_COEF, 497, 0xffffffff, 5 }, + {REG_TYPE_INDEX_VPP_COEF, 498, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 499, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 500, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 504, 0xffffffff, 69817344 }, + {REG_TYPE_INDEX_VPP_COEF, 505, 0xffffffff, 7 }, + {REG_TYPE_INDEX_VPP_COEF, 506, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 507, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 508, 0xffffffff, 0 }, + {0} + } +}; +static struct am_regs_s cmreg_lever3 = { + 172, + { + /* optimize */ + {REG_TYPE_INDEX_VPPCHROMA, 512, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 513, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 514, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 515, 0xffffffff, 134218752 }, + {REG_TYPE_INDEX_VPPCHROMA, 516, 0xffffffff, 144 }, + {REG_TYPE_INDEX_VPPCHROMA, 518, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPPCHROMA, 519, 0xffffffff, 33554432 }, + {REG_TYPE_INDEX_VPPCHROMA, 520, 0xffffffff, 118 }, + {REG_TYPE_INDEX_VPPCHROMA, 521, 0xffffffff, 62914560 }, + {REG_TYPE_INDEX_VPPCHROMA, 522, 0xffffffff, 70778880 }, + {REG_TYPE_INDEX_VPPCHROMA, 527, 0xf, 1 }, + {REG_TYPE_INDEX_VPPCHROMA, 517, 0xffffffff, 70780799 }, + {REG_TYPE_INDEX_VPP_COEF, 256, 0xffffffff, 16648704 }, + {REG_TYPE_INDEX_VPP_COEF, 257, 0xffffffff, 0xf3f6000b }, + {REG_TYPE_INDEX_VPP_COEF, 258, 0xffffffff, 0xe3000000 }, + {REG_TYPE_INDEX_VPP_COEF, 259, 0xffffffff, 240 }, + {REG_TYPE_INDEX_VPP_COEF, 260, 0xffffffff, 63742 }, + {REG_TYPE_INDEX_VPP_COEF, 264, 0xffffffff, 16650496 }, + {REG_TYPE_INDEX_VPP_COEF, 265, 0xffffffff, 14 }, + {REG_TYPE_INDEX_VPP_COEF, 266, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 267, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 268, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 272, 0xffffffff, 135936 }, + {REG_TYPE_INDEX_VPP_COEF, 273, 0xffffffff, 253 }, + {REG_TYPE_INDEX_VPP_COEF, 274, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 275, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 276, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 280, 0xffffffff, 0xf3f11300 }, + {REG_TYPE_INDEX_VPP_COEF, 281, 0xffffffff, 214 }, + {REG_TYPE_INDEX_VPP_COEF, 282, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 283, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 284, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 288, 0xffffffff, 0xede91300 }, + {REG_TYPE_INDEX_VPP_COEF, 289, 0xffffffff, 177 }, + {REG_TYPE_INDEX_VPP_COEF, 290, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 291, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 292, 0xffffffff, 15660544 }, + {REG_TYPE_INDEX_VPP_COEF, 296, 0xffffffff, 0xe9e61100 }, + {REG_TYPE_INDEX_VPP_COEF, 297, 0xffffffff, 184 }, + {REG_TYPE_INDEX_VPP_COEF, 298, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 299, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 300, 0xffffffff, 15464448 }, + {REG_TYPE_INDEX_VPP_COEF, 304, 0xffffffff, 0xeff80f00 }, + {REG_TYPE_INDEX_VPP_COEF, 305, 0xffffffff, 232 }, + {REG_TYPE_INDEX_VPP_COEF, 306, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 307, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 308, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 312, 0xffffffff, 0xf60a0d00 }, + {REG_TYPE_INDEX_VPP_COEF, 313, 0xffffffff, 5 }, + {REG_TYPE_INDEX_VPP_COEF, 314, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 315, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 316, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 320, 0xffffffff, 526848 }, + {REG_TYPE_INDEX_VPP_COEF, 321, 0xffffffff, 5 }, + {REG_TYPE_INDEX_VPP_COEF, 322, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 323, 0xffffffff, 10 }, + {REG_TYPE_INDEX_VPP_COEF, 324, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 328, 0xffffffff, 526848 }, + {REG_TYPE_INDEX_VPP_COEF, 329, 0xffffffff, 134742265 }, + {REG_TYPE_INDEX_VPP_COEF, 330, 0xffffffff, 167903232 }, + {REG_TYPE_INDEX_VPP_COEF, 331, 0xffffffff, 21 }, + {REG_TYPE_INDEX_VPP_COEF, 332, 0xffffffff, 3328 }, + {REG_TYPE_INDEX_VPP_COEF, 336, 0xffffffff, 131072 }, + {REG_TYPE_INDEX_VPP_COEF, 337, 0xffffffff, 0xf80d00ea }, + {REG_TYPE_INDEX_VPP_COEF, 338, 0xffffffff, 0xf80500fb }, + {REG_TYPE_INDEX_VPP_COEF, 339, 0xffffffff, 2 }, + {REG_TYPE_INDEX_VPP_COEF, 340, 0xffffffff, 132357 }, + {REG_TYPE_INDEX_VPP_COEF, 344, 0xffffffff, 131584 }, + {REG_TYPE_INDEX_VPP_COEF, 345, 0xffffffff, 0xfb0100da }, + {REG_TYPE_INDEX_VPP_COEF, 346, 0xffffffff, 0xf6020002 }, + {REG_TYPE_INDEX_VPP_COEF, 347, 0xffffffff, 251 }, + {REG_TYPE_INDEX_VPP_COEF, 348, 0xffffffff, 16646656 }, + {REG_TYPE_INDEX_VPP_COEF, 352, 0xffffffff, 657408 }, + {REG_TYPE_INDEX_VPP_COEF, 353, 0xffffffff, 327872 }, + {REG_TYPE_INDEX_VPP_COEF, 354, 0xffffffff, 0xf6050000 }, + {REG_TYPE_INDEX_VPP_COEF, 355, 0xffffffff, 2 }, + {REG_TYPE_INDEX_VPP_COEF, 356, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 360, 0xffffffff, 526336 }, + {REG_TYPE_INDEX_VPP_COEF, 361, 0xffffffff, 175 }, + {REG_TYPE_INDEX_VPP_COEF, 362, 0xffffffff, 0xf600f600 }, + {REG_TYPE_INDEX_VPP_COEF, 363, 0xffffffff, 254 }, + {REG_TYPE_INDEX_VPP_COEF, 364, 0xffffffff, 33554432 }, + {REG_TYPE_INDEX_VPP_COEF, 368, 0xffffffff, 986368 }, + {REG_TYPE_INDEX_VPP_COEF, 369, 0xffffffff, 169 }, + {REG_TYPE_INDEX_VPP_COEF, 370, 0xffffffff, 0xf300eef6 }, + {REG_TYPE_INDEX_VPP_COEF, 371, 0xffffffff, 243 }, + {REG_TYPE_INDEX_VPP_COEF, 372, 0xffffffff, 0xfb050000 }, + {REG_TYPE_INDEX_VPP_COEF, 376, 0xffffffff, 34541312 }, + {REG_TYPE_INDEX_VPP_COEF, 377, 0xffffffff, 83886277 }, + {REG_TYPE_INDEX_VPP_COEF, 378, 0xffffffff, 0xfbfef8f8 }, + {REG_TYPE_INDEX_VPP_COEF, 379, 0xffffffff, 246 }, + {REG_TYPE_INDEX_VPP_COEF, 380, 0xffffffff, 0xf8080200 }, + {REG_TYPE_INDEX_VPP_COEF, 384, 0xffffffff, 135339520 }, + {REG_TYPE_INDEX_VPP_COEF, 385, 0xffffffff, 353697836 }, + {REG_TYPE_INDEX_VPP_COEF, 386, 0xffffffff, 168427768 }, + {REG_TYPE_INDEX_VPP_COEF, 387, 0xffffffff, 13 }, + {REG_TYPE_INDEX_VPP_COEF, 388, 0xffffffff, 0xfb080800 }, + {REG_TYPE_INDEX_VPP_COEF, 392, 0xffffffff, 219356160 }, + {REG_TYPE_INDEX_VPP_COEF, 393, 0xffffffff, 674758739 }, + {REG_TYPE_INDEX_VPP_COEF, 394, 0xffffffff, 573177856 }, + {REG_TYPE_INDEX_VPP_COEF, 395, 0xffffffff, 21 }, + {REG_TYPE_INDEX_VPP_COEF, 396, 0xffffffff, 657920 }, + {REG_TYPE_INDEX_VPP_COEF, 400, 0xffffffff, 219223808 }, + {REG_TYPE_INDEX_VPP_COEF, 401, 0xffffffff, 809304160 }, + {REG_TYPE_INDEX_VPP_COEF, 402, 0xffffffff, 674562069 }, + {REG_TYPE_INDEX_VPP_COEF, 403, 0xffffffff, 13 }, + {REG_TYPE_INDEX_VPP_COEF, 404, 0xffffffff, 657920 }, + {REG_TYPE_INDEX_VPP_COEF, 408, 0xffffffff, 168629504 }, + {REG_TYPE_INDEX_VPP_COEF, 409, 0xffffffff, 807731289 }, + {REG_TYPE_INDEX_VPP_COEF, 410, 0xffffffff, 403308562 }, + {REG_TYPE_INDEX_VPP_COEF, 411, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 412, 0xffffffff, 526848 }, + {REG_TYPE_INDEX_VPP_COEF, 416, 0xffffffff, 395776 }, + {REG_TYPE_INDEX_VPP_COEF, 417, 0xffffffff, 269484098 }, + {REG_TYPE_INDEX_VPP_COEF, 418, 0xffffffff, 167772160 }, + {REG_TYPE_INDEX_VPP_COEF, 419, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 420, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 424, 0xffffffff, 396544 }, + {REG_TYPE_INDEX_VPP_COEF, 425, 0xffffffff, 134217757 }, + {REG_TYPE_INDEX_VPP_COEF, 426, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 427, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 428, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 432, 0xffffffff, 527616 }, + {REG_TYPE_INDEX_VPP_COEF, 433, 0xffffffff, 12 }, + {REG_TYPE_INDEX_VPP_COEF, 434, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 435, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 436, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 440, 0xffffffff, 658688 }, + {REG_TYPE_INDEX_VPP_COEF, 441, 0xffffffff, 7 }, + {REG_TYPE_INDEX_VPP_COEF, 442, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 443, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 444, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 448, 0xffffffff, 986880 }, + {REG_TYPE_INDEX_VPP_COEF, 449, 0xffffffff, 5 }, + {REG_TYPE_INDEX_VPP_COEF, 450, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 451, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 452, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 456, 0xffffffff, 219811584 }, + {REG_TYPE_INDEX_VPP_COEF, 457, 0xffffffff, 244 }, + {REG_TYPE_INDEX_VPP_COEF, 458, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 459, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 460, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 464, 0xffffffff, 287183104 }, + {REG_TYPE_INDEX_VPP_COEF, 465, 0xffffffff, 186 }, + {REG_TYPE_INDEX_VPP_COEF, 466, 0xffffffff, 0xf3000000 }, + {REG_TYPE_INDEX_VPP_COEF, 467, 0xffffffff, 246 }, + {REG_TYPE_INDEX_VPP_COEF, 468, 0xffffffff, 0xfb000000 }, + {REG_TYPE_INDEX_VPP_COEF, 472, 0xffffffff, 219944192 }, + {REG_TYPE_INDEX_VPP_COEF, 473, 0xffffffff, 158 }, + {REG_TYPE_INDEX_VPP_COEF, 474, 0xffffffff, 0xf0000000 }, + {REG_TYPE_INDEX_VPP_COEF, 475, 0xffffffff, 232 }, + {REG_TYPE_INDEX_VPP_COEF, 476, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 480, 0xffffffff, 1382912 }, + {REG_TYPE_INDEX_VPP_COEF, 481, 0xffffffff, 0xfb0000a4 }, + {REG_TYPE_INDEX_VPP_COEF, 482, 0xffffffff, 0xe300f3f3 }, + {REG_TYPE_INDEX_VPP_COEF, 483, 0xffffffff, 219 }, + {REG_TYPE_INDEX_VPP_COEF, 484, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 488, 0xffffffff, 1514496 }, + {REG_TYPE_INDEX_VPP_COEF, 489, 0xffffffff, 0xf30000ba }, + {REG_TYPE_INDEX_VPP_COEF, 490, 0xffffffff, 0xe600f3f0 }, + {REG_TYPE_INDEX_VPP_COEF, 491, 0xffffffff, 222 }, + {REG_TYPE_INDEX_VPP_COEF, 492, 0xffffffff, 0 }, + {REG_TYPE_INDEX_VPP_COEF, 496, 0xffffffff, 1120000 }, + {REG_TYPE_INDEX_VPP_COEF, 497, 0xffffffff, 0xf3fb00db }, + {REG_TYPE_INDEX_VPP_COEF, 498, 0xffffffff, 0xe800f6ee }, + {REG_TYPE_INDEX_VPP_COEF, 499, 0xffffffff, 232 }, + {REG_TYPE_INDEX_VPP_COEF, 500, 0xffffffff, 64256 }, + {REG_TYPE_INDEX_VPP_COEF, 504, 0xffffffff, 397056 }, + {REG_TYPE_INDEX_VPP_COEF, 505, 0xffffffff, 0xf6f800f7 }, + {REG_TYPE_INDEX_VPP_COEF, 506, 0xffffffff, 0xe60000f8 }, + {REG_TYPE_INDEX_VPP_COEF, 507, 0xffffffff, 235 }, + {REG_TYPE_INDEX_VPP_COEF, 508, 0xffffffff, 65278 }, + {0} + } +}; + +static struct am_regs_s cmreg_optimize = { + 172, + { + /* optimize */ + {REG_TYPE_INDEX_VPPCHROMA, 0x200, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x201, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x202, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x203, 0xffffffff, 0x8000400}, + {REG_TYPE_INDEX_VPPCHROMA, 0x204, 0xffffffff, 0x90 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x205, 0xffffffff, 0x437077f}, + {REG_TYPE_INDEX_VPPCHROMA, 0x206, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x207, 0xffffffff, 0x1f60000}, + {REG_TYPE_INDEX_VPPCHROMA, 0x208, 0xffffffff, 0x76 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x209, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x20a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x20f, 0xf, 0x0, }, + {REG_TYPE_INDEX_VPP_COEF, 0x100, 0xffffffff, 0xa1100 }, + {REG_TYPE_INDEX_VPP_COEF, 0x101, 0xffffffff, 0xc }, + {REG_TYPE_INDEX_VPP_COEF, 0x102, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x103, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x104, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x108, 0xffffffff, 0xd1100 }, + {REG_TYPE_INDEX_VPP_COEF, 0x109, 0xffffffff, 0x1f }, + {REG_TYPE_INDEX_VPP_COEF, 0x10a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x10b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x10c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x110, 0xffffffff, 0xf1300 }, + {REG_TYPE_INDEX_VPP_COEF, 0x111, 0xffffffff, 0x33 }, + {REG_TYPE_INDEX_VPP_COEF, 0x112, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x113, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x114, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x118, 0xffffffff, 0xf1300 }, + {REG_TYPE_INDEX_VPP_COEF, 0x119, 0xffffffff, 0x3f }, + {REG_TYPE_INDEX_VPP_COEF, 0x11a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x11b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x11c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x120, 0xffffffff, 0xf1300 }, + {REG_TYPE_INDEX_VPP_COEF, 0x121, 0xffffffff, 0x40 }, + {REG_TYPE_INDEX_VPP_COEF, 0x122, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x123, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x124, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x128, 0xffffffff, 0xf1100 }, + {REG_TYPE_INDEX_VPP_COEF, 0x129, 0xffffffff, 0x40 }, + {REG_TYPE_INDEX_VPP_COEF, 0x12a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x12b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x12c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x130, 0xffffffff, 0xd0f00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x131, 0xffffffff, 0x3f }, + {REG_TYPE_INDEX_VPP_COEF, 0x132, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x133, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x134, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x138, 0xffffffff, 0xa0d00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x139, 0xffffffff, 0x32 }, + {REG_TYPE_INDEX_VPP_COEF, 0x13a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x13b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x13c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x140, 0xffffffff, 0x80a00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x141, 0xffffffff, 0x9 }, + {REG_TYPE_INDEX_VPP_COEF, 0x142, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x143, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x144, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x148, 0xffffffff, 0x80a00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x149, 0xffffffff, 0xea }, + {REG_TYPE_INDEX_VPP_COEF, 0x14a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x14b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x14c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x150, 0xffffffff, 0xa0a00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x151, 0xffffffff, 0xd4 }, + {REG_TYPE_INDEX_VPP_COEF, 0x152, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x153, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x154, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x158, 0xffffffff, 0xa0800 }, + {REG_TYPE_INDEX_VPP_COEF, 0x159, 0xffffffff, 0xc3 }, + {REG_TYPE_INDEX_VPP_COEF, 0x15a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x15b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x15c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x160, 0xffffffff, 0xa0800 }, + {REG_TYPE_INDEX_VPP_COEF, 0x161, 0xffffffff, 0xc0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x162, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x163, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x164, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x168, 0xffffffff, 0x80800 }, + {REG_TYPE_INDEX_VPP_COEF, 0x169, 0xffffffff, 0xcb }, + {REG_TYPE_INDEX_VPP_COEF, 0x16a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x16b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x16c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x170, 0xffffffff, 0x60800 }, + {REG_TYPE_INDEX_VPP_COEF, 0x171, 0xffffffff, 0xd4 }, + {REG_TYPE_INDEX_VPP_COEF, 0x172, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x173, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x174, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x178, 0xffffffff, 0x40600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x179, 0xffffffff, 0xdb }, + {REG_TYPE_INDEX_VPP_COEF, 0x17a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x17b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x17c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x180, 0xffffffff, 0x60600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x181, 0xffffffff, 0xea }, + {REG_TYPE_INDEX_VPP_COEF, 0x182, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x183, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x184, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x188, 0xffffffff, 0x60600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x189, 0xffffffff, 0xf7 }, + {REG_TYPE_INDEX_VPP_COEF, 0x18a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x18b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x18c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x190, 0xffffffff, 0x60600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x191, 0xffffffff, 0x3 }, + {REG_TYPE_INDEX_VPP_COEF, 0x192, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x193, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x194, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x198, 0xffffffff, 0x80800 }, + {REG_TYPE_INDEX_VPP_COEF, 0x199, 0xffffffff, 0x9 }, + {REG_TYPE_INDEX_VPP_COEF, 0x19a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x19b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x19c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a0, 0xffffffff, 0x60a00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a1, 0xffffffff, 0xc }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a2, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a3, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a4, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a8, 0xffffffff, 0x60d00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a9, 0xffffffff, 0xe }, + {REG_TYPE_INDEX_VPP_COEF, 0x1aa, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1ab, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1ac, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b0, 0xffffffff, 0x80d00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b1, 0xffffffff, 0xc }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b2, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b3, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b4, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b8, 0xffffffff, 0xa0d00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b9, 0xffffffff, 0x7 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1ba, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1bb, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1bc, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c0, 0xffffffff, 0xf0f00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c1, 0xffffffff, 0xfb }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c2, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c3, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c4, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c8, 0xffffffff, 0x110f00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c9, 0xffffffff, 0xf2 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1ca, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1cb, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1cc, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1d0, 0xffffffff, 0x131100 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1d1, 0xffffffff, 0xee }, + {REG_TYPE_INDEX_VPP_COEF, 0x1d2, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1d3, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1d4, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1d8, 0xffffffff, 0x131500 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1d9, 0xffffffff, 0xf5 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1da, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1db, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1dc, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1e0, 0xffffffff, 0x151a00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1e1, 0xffffffff, 0x1 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1e2, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1e3, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1e4, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1e8, 0xffffffff, 0x171c00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1e9, 0xffffffff, 0x5 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1ea, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1eb, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1ec, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1f0, 0xffffffff, 0x171a00 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1f1, 0xffffffff, 0x5 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1f2, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1f3, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1f4, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1f8, 0xffffffff, 0x131500 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1f9, 0xffffffff, 0x7 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1fa, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1fb, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1fc, 0xffffffff, 0x0 }, + {0} + } +}; +static struct am_regs_s cmreg_enhancement = { + 172, + { + /* enhancement */ + {REG_TYPE_INDEX_VPPCHROMA, 0x200, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x201, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x202, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x203, 0xffffffff, 0x8000400}, + {REG_TYPE_INDEX_VPPCHROMA, 0x204, 0xffffffff, 0x90 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x205, 0xffffffff, 0x437077f}, + {REG_TYPE_INDEX_VPPCHROMA, 0x206, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x207, 0xffffffff, 0x2640000}, + {REG_TYPE_INDEX_VPPCHROMA, 0x208, 0xffffffff, 0x7a }, + {REG_TYPE_INDEX_VPPCHROMA, 0x209, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x20a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPPCHROMA, 0x20f, 0xf, 0x0, }, + {REG_TYPE_INDEX_VPP_COEF, 0x100, 0xffffffff, 0x2b5600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x101, 0xffffffff, 0xc }, + {REG_TYPE_INDEX_VPP_COEF, 0x102, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x103, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x104, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x108, 0xffffffff, 0x295600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x109, 0xffffffff, 0x1f }, + {REG_TYPE_INDEX_VPP_COEF, 0x10a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x10b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x10c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x110, 0xffffffff, 0x295600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x111, 0xffffffff, 0x33 }, + {REG_TYPE_INDEX_VPP_COEF, 0x112, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x113, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x114, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x118, 0xffffffff, 0x2b5600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x119, 0xffffffff, 0x3f }, + {REG_TYPE_INDEX_VPP_COEF, 0x11a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x11b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x11c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x120, 0xffffffff, 0x2b5600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x121, 0xffffffff, 0x3f }, + {REG_TYPE_INDEX_VPP_COEF, 0x122, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x123, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x124, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x128, 0xffffffff, 0x295600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x129, 0xffffffff, 0x3f }, + {REG_TYPE_INDEX_VPP_COEF, 0x12a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x12b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x12c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x130, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x131, 0xffffffff, 0x3f }, + {REG_TYPE_INDEX_VPP_COEF, 0x132, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x133, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x134, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x138, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x139, 0xffffffff, 0x33 }, + {REG_TYPE_INDEX_VPP_COEF, 0x13a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x13b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x13c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x140, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x141, 0xffffffff, 0x9 }, + {REG_TYPE_INDEX_VPP_COEF, 0x142, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x143, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x144, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x148, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x149, 0xffffffff, 0xea }, + {REG_TYPE_INDEX_VPP_COEF, 0x14a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x14b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x14c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x150, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x151, 0xffffffff, 0xd4 }, + {REG_TYPE_INDEX_VPP_COEF, 0x152, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x153, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x154, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x158, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x159, 0xffffffff, 0xc5 }, + {REG_TYPE_INDEX_VPP_COEF, 0x15a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x15b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x15c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x160, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x161, 0xffffffff, 0xc1 }, + {REG_TYPE_INDEX_VPP_COEF, 0x162, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x163, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x164, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x168, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x169, 0xffffffff, 0xcb }, + {REG_TYPE_INDEX_VPP_COEF, 0x16a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x16b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x16c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x170, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x171, 0xffffffff, 0xd6 }, + {REG_TYPE_INDEX_VPP_COEF, 0x172, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x173, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x174, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x178, 0xffffffff, 0x295600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x179, 0xffffffff, 0xdb }, + {REG_TYPE_INDEX_VPP_COEF, 0x17a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x17b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x17c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x180, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x181, 0xffffffff, 0xec }, + {REG_TYPE_INDEX_VPP_COEF, 0x182, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x183, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x184, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x188, 0xffffffff, 0x295600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x189, 0xffffffff, 0xf9 }, + {REG_TYPE_INDEX_VPP_COEF, 0x18a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x18b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x18c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x190, 0xffffffff, 0x295600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x191, 0xffffffff, 0x3 }, + {REG_TYPE_INDEX_VPP_COEF, 0x192, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x193, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x194, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x198, 0xffffffff, 0x295600 }, + {REG_TYPE_INDEX_VPP_COEF, 0x199, 0xffffffff, 0x9 }, + {REG_TYPE_INDEX_VPP_COEF, 0x19a, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x19b, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x19c, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a0, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a1, 0xffffffff, 0xc }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a2, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a3, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a4, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a8, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1a9, 0xffffffff, 0xe }, + {REG_TYPE_INDEX_VPP_COEF, 0x1aa, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1ab, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1ac, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b0, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b1, 0xffffffff, 0xc }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b2, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b3, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b4, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b8, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1b9, 0xffffffff, 0x7 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1ba, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1bb, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1bc, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c0, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c1, 0xffffffff, 0xfb }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c2, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c3, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c4, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c8, 0xffffffff, 0x295400 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1c9, 0xffffffff, 0xf2 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1ca, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1cb, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1cc, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1d0, 0xffffffff, 0x2295400}, + {REG_TYPE_INDEX_VPP_COEF, 0x1d1, 0xffffffff, 0xee }, + {REG_TYPE_INDEX_VPP_COEF, 0x1d2, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1d3, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1d4, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1d8, 0xffffffff, 0x4295400}, + {REG_TYPE_INDEX_VPP_COEF, 0x1d9, 0xffffffff, 0xf5 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1da, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1db, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1dc, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1e0, 0xffffffff, 0x8295400}, + {REG_TYPE_INDEX_VPP_COEF, 0x1e1, 0xffffffff, 0x1 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1e2, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1e3, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1e4, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1e8, 0xffffffff, 0x8295400}, + {REG_TYPE_INDEX_VPP_COEF, 0x1e9, 0xffffffff, 0x5 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1ea, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1eb, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1ec, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1f0, 0xffffffff, 0x8295400}, + {REG_TYPE_INDEX_VPP_COEF, 0x1f1, 0xffffffff, 0x5 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1f2, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1f3, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1f4, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1f8, 0xffffffff, 0x4295400}, + {REG_TYPE_INDEX_VPP_COEF, 0x1f9, 0xffffffff, 0x7 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1fa, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1fb, 0xffffffff, 0x0 }, + {REG_TYPE_INDEX_VPP_COEF, 0x1fc, 0xffffffff, 0x0 }, + {0} + } +}; + + +#endif + diff --git a/drivers/amlogic/media/enhancement/amvecm/amcsc.c b/drivers/amlogic/media/enhancement/amvecm/amcsc.c new file mode 100644 index 0000000..996e9c7 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/amcsc.c @@ -0,0 +1,4415 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amcsc.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/* Standard Linux headers */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "arch/vpp_regs.h" +#include "../../vin/tvin/tvin_global.h" +#include "arch/vpp_hdr_regs.h" +#include "arch/hdr_curve.h" + +/* use osd rdma reg w/r */ +#include "../../osd/osd_rdma.h" + +#include "amcsc.h" + +#define pr_csc(fmt, args...)\ + do {\ + if (debug_csc)\ + pr_info(fmt, ## args);\ + } while (0) + +signed int vd1_contrast_offset; + +signed int saturation_offset; + +struct hdr_osd_reg_s hdr_osd_reg = { + 0x00000001, /* VIU_OSD1_MATRIX_CTRL 0x1a90 */ + 0x00ba0273, /* VIU_OSD1_MATRIX_COEF00_01 0x1a91 */ + 0x003f1f9a, /* VIU_OSD1_MATRIX_COEF02_10 0x1a92 */ + 0x1ea801c0, /* VIU_OSD1_MATRIX_COEF11_12 0x1a93 */ + 0x01c01e6a, /* VIU_OSD1_MATRIX_COEF20_21 0x1a94 */ + 0x00000000, /* VIU_OSD1_MATRIX_COLMOD_COEF42 0x1a95 */ + 0x00400200, /* VIU_OSD1_MATRIX_OFFSET0_1 0x1a96 */ + 0x00000200, /* VIU_OSD1_MATRIX_PRE_OFFSET2 0x1a97 */ + 0x00000000, /* VIU_OSD1_MATRIX_PRE_OFFSET0_1 0x1a98 */ + 0x00000000, /* VIU_OSD1_MATRIX_PRE_OFFSET2 0x1a99 */ + 0x1fd80000, /* VIU_OSD1_MATRIX_COEF22_30 0x1a9d */ + 0x00000000, /* VIU_OSD1_MATRIX_COEF31_32 0x1a9e */ + 0x00000000, /* VIU_OSD1_MATRIX_COEF40_41 0x1a9f */ + 0x00000000, /* VIU_OSD1_EOTF_CTL 0x1ad4 */ + 0x08000000, /* VIU_OSD1_EOTF_COEF00_01 0x1ad5 */ + 0x00000000, /* VIU_OSD1_EOTF_COEF02_10 0x1ad6 */ + 0x08000000, /* VIU_OSD1_EOTF_COEF11_12 0x1ad7 */ + 0x00000000, /* VIU_OSD1_EOTF_COEF20_21 0x1ad8 */ + 0x08000001, /* VIU_OSD1_EOTF_COEF22_RS 0x1ad9 */ + 0x01c00000, /* VIU_OSD1_OETF_CTL 0x1adc */ + { + /* eotf table */ + { /* r map */ + 0x0000, 0x0200, 0x0400, 0x0600, 0x0800, 0x0a00, + 0x0c00, 0x0e00, 0x1000, 0x1200, 0x1400, 0x1600, + 0x1800, 0x1a00, 0x1c00, 0x1e00, 0x2000, 0x2200, + 0x2400, 0x2600, 0x2800, 0x2a00, 0x2c00, 0x2e00, + 0x3000, 0x3200, 0x3400, 0x3600, 0x3800, 0x3a00, + 0x3c00, 0x3e00, 0x4000 + }, + { /* g map */ + 0x0000, 0x0200, 0x0400, 0x0600, 0x0800, 0x0a00, + 0x0c00, 0x0e00, 0x1000, 0x1200, 0x1400, 0x1600, + 0x1800, 0x1a00, 0x1c00, 0x1e00, 0x2000, 0x2200, + 0x2400, 0x2600, 0x2800, 0x2a00, 0x2c00, 0x2e00, + 0x3000, 0x3200, 0x3400, 0x3600, 0x3800, 0x3a00, + 0x3c00, 0x3e00, 0x4000 + }, + { /* b map */ + 0x0000, 0x0200, 0x0400, 0x0600, 0x0800, 0x0a00, + 0x0c00, 0x0e00, 0x1000, 0x1200, 0x1400, 0x1600, + 0x1800, 0x1a00, 0x1c00, 0x1e00, 0x2000, 0x2200, + 0x2400, 0x2600, 0x2800, 0x2a00, 0x2c00, 0x2e00, + 0x3000, 0x3200, 0x3400, 0x3600, 0x3800, 0x3a00, + 0x3c00, 0x3e00, 0x4000 + }, + /* oetf table */ + { /* or map */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 + }, + { /* og map */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 + }, + { /* ob map */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 + } + } +}; + +static struct vframe_s *dbg_vf; +static struct master_display_info_s dbg_hdr_send; +static struct hdr_info receiver_hdr_info; + +static bool debug_csc; +module_param(debug_csc, bool, 0664); +MODULE_PARM_DESC(debug_csc, "\n debug_csc\n"); + +static bool skip_csc_en; +module_param(skip_csc_en, bool, 0664); +MODULE_PARM_DESC(skip_csc_en, "\n skip_csc_en\n"); + +/* white balance adjust */ +static bool cur_eye_protect_mode; + +static int num_wb_val = 10; +static int wb_val[10] = { + 0, /* wb enable */ + 0, /* -1024~1023, r_pre_offset */ + 0, /* -1024~1023, g_pre_offset */ + 0, /* -1024~1023, b_pre_offset */ + 1024, /* 0~2047, r_gain */ + 1024, /* 0~2047, g_gain */ + 1024, /* 0~2047, b_gain */ + 0, /* -1024~1023, r_post_offset */ + 0, /* -1024~1023, g_post_offset */ + 0 /* -1024~1023, b_post_offset */ +}; +module_param_array(wb_val, int, &num_wb_val, 0664); +MODULE_PARM_DESC(wb_val, "\n white balance setting\n"); + +static enum vframe_source_type_e pre_src_type = VFRAME_SOURCE_TYPE_COMP; +static uint cur_csc_type = 0xffff; +module_param(cur_csc_type, uint, 0444); +MODULE_PARM_DESC(cur_csc_type, "\n current color space convert type\n"); + +static uint hdr_mode = 2; /* 0: hdr->hdr, 1:hdr->sdr, 2:auto */ +module_param(hdr_mode, uint, 0664); +MODULE_PARM_DESC(hdr_mode, "\n set hdr_mode\n"); + +static uint hdr_process_mode = 1; /* 0: hdr->hdr, 1:hdr->sdr */ +static uint cur_hdr_process_mode = 2; /* 0: hdr->hdr, 1:hdr->sdr */ +module_param(hdr_process_mode, uint, 0444); +MODULE_PARM_DESC(hdr_process_mode, "\n current hdr_process_mode\n"); + +unsigned int sdr_mode; /* 0: sdr->sdr, 1:sdr->hdr, 2:auto */ +static uint sdr_process_mode = 2; /* 0: sdr->sdr, 1:sdr->hdr */ +static uint cur_sdr_process_mode = 2; /* 0: sdr->sdr, 1:sdr->hdr */ +static int sdr_saturation_offset = 20; /* 0: sdr->sdr, 1:sdr->hdr */ +module_param(sdr_mode, uint, 0664); +MODULE_PARM_DESC(sdr_mode, "\n set sdr_mode\n"); +module_param(sdr_process_mode, uint, 0444); +MODULE_PARM_DESC(sdr_process_mode, "\n current hdr_process_mode\n"); +module_param(sdr_saturation_offset, int, 0664); +MODULE_PARM_DESC(sdr_saturation_offset, "\n add saturation\n"); + +static uint force_csc_type = 0xff; +module_param(force_csc_type, uint, 0664); +MODULE_PARM_DESC(force_csc_type, "\n force colour space convert type\n"); + +static uint cur_hdr_support; +module_param(cur_hdr_support, uint, 0664); +MODULE_PARM_DESC(cur_hdr_support, "\n cur_hdr_support\n"); + +static uint range_control; +module_param(range_control, uint, 0664); +MODULE_PARM_DESC(range_control, "\n range_control 0:limit 1:full\n"); + +/* bit 0: use source primary,*/ +/* bit 1: use display primary,*/ +/* bit 2: adjust contrast according to source lumin,*/ +/* bit 3: adjust saturation according to source lumin */ +uint hdr_flag = (1 << 0) | (1 << 1) | (0 << 2) | (0 << 3); +module_param(hdr_flag, uint, 0664); +MODULE_PARM_DESC(hdr_flag, "\n set hdr_flag\n"); + +static uint rdma_flag = + (1 << VPP_MATRIX_XVYCC); +module_param(rdma_flag, uint, 0664); +MODULE_PARM_DESC(rdma_flag, "\n set rdma_flag\n"); + +#define MAX_KNEE_SETTING 35 +/* recommended setting for 100 nits panel: */ +/* 0,16,96,224,320,544,720,864,1000,1016,1023 */ +/* knee factor = 256 */ +static int num_knee_setting = MAX_KNEE_SETTING; +static int knee_setting[MAX_KNEE_SETTING] = { + /* 0, 16, 96, 224, 320, 544, 720, 864, 1000, 1016, 1023 */ + 0, 16, 36, 59, 71, 96, + 120, 145, 170, 204, 230, 258, + 288, 320, 355, 390, 428, 470, + 512, 554, 598, 650, 720, 758, + 790, 832, 864, 894, 920, 945, + 968, 980, 1000, 1016, 1023 +}; + +static int num_knee_linear_setting = MAX_KNEE_SETTING; +static int knee_linear_setting[MAX_KNEE_SETTING] = { + 0x000, + 0x010, + 0x02f, + 0x04e, + 0x06d, + 0x08c, + 0x0ab, + 0x0ca, + 0x0e9, + 0x108, + 0x127, + 0x146, + 0x165, + 0x184, + 0x1a3, + 0x1c2, + 0x1e1, + 0x200, + 0x21f, + 0x23e, + 0x25d, + 0x27c, + 0x29b, + 0x2ba, + 0x2d9, + 0x2f8, + 0x317, + 0x336, + 0x355, + 0x374, + 0x393, + 0x3b2, + 0x3d1, + 0x3f0, + 0x3ff +}; + +static bool lut_289_en = 1; +module_param(lut_289_en, bool, 0664); +MODULE_PARM_DESC(lut_289_en, "\n if enable 289 lut\n"); + +/*for gxtvbb(968), only 289 point lut for hdr curve set */ +/*default for 350nit panel*/ +unsigned int lut_289_mapping[LUT_289_SIZE] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0x9, 0xa, 0xb, 0xd, 0xe, 0x10, 0x11, 0x12, + 0x14, 0x15, 0x17, 0x18, 0x1a, 0x1c, 0x1d, 0x1f, + 0x20, 0x22, 0x24, 0x26, 0x27, 0x29, 0x2b, 0x2d, + 0x2f, 0x31, 0x33, 0x35, 0x37, 0x39, 0x3b, 0x3d, + 0x40, 0x42, 0x44, 0x46, 0x49, 0x4b, 0x4e, 0x50, + 0x53, 0x55, 0x58, 0x5a, 0x5d, 0x60, 0x62, 0x65, + 0x68, 0x6b, 0x6e, 0x71, 0x74, 0x77, 0x7a, 0x7e, + 0x81, 0x84, 0x87, 0x8b, 0x8e, 0x92, 0x95, 0x99, + 0x9d, 0xa1, 0xa4, 0xa8, 0xac, 0xb0, 0xb4, 0xb8, + 0xbc, 0xc1, 0xc5, 0xc9, 0xce, 0xd2, 0xd7, 0xdc, + 0xe0, 0xe5, 0xea, 0xef, 0xf4, 0xf9, 0xfe, 0x104, + 0x109, 0x10e, 0x114, 0x11a, 0x11f, 0x125, 0x12b, 0x131, + 0x137, 0x13d, 0x143, 0x14a, 0x150, 0x156, 0x15d, 0x164, + 0x16b, 0x172, 0x179, 0x180, 0x187, 0x18e, 0x196, 0x19d, + 0x1a5, 0x1ad, 0x1b5, 0x1bd, 0x1c5, 0x1cd, 0x1d6, 0x1de, + 0x1e7, 0x1f0, 0x1f9, 0x202, 0x20b, 0x214, 0x21e, 0x227, + 0x231, 0x23b, 0x245, 0x24f, 0x25a, 0x264, 0x26f, 0x27a, + 0x285, 0x290, 0x29c, 0x2a7, 0x2b3, 0x2bf, 0x2cb, 0x2d7, + 0x2e3, 0x2f0, 0x2fd, 0x30a, 0x317, 0x325, 0x332, 0x33e, + 0x34a, 0x356, 0x362, 0x36d, 0x377, 0x381, 0x38b, 0x394, + 0x39c, 0x3a4, 0x3ac, 0x3b3, 0x3ba, 0x3c1, 0x3c7, 0x3cd, + 0x3d2, 0x3d7, 0x3db, 0x3df, 0x3e3, 0x3e6, 0x3e9, 0x3ec, + 0x3ef, 0x3f1, 0x3f3, 0x3f5, 0x3f6, 0x3f7, 0x3f8, 0x3f9, + 0x3fa, 0x3fa, 0x3fb, 0x3fb, 0x3fb, 0x3fc, 0x3fc, 0x3fc, + 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, + 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, + 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, + 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, + 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, + 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, + 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, 0x3fc, + 0x3fc, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, + 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, + 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, + 0x3ff +}; + +static int knee_factor; /* 0 ~ 256, 128 = 0.5 */ +static int knee_interpolation_mode = 1; /* 0: linear, 1: cubic */ + +module_param_array(knee_setting, int, &num_knee_setting, 0664); +MODULE_PARM_DESC(knee_setting, "\n knee_setting, 256=1.0\n"); + +module_param_array(knee_linear_setting, int, &num_knee_linear_setting, 0444); +MODULE_PARM_DESC(knee_linear_setting, "\n reference linear knee_setting\n"); + +module_param(knee_factor, int, 0664); +MODULE_PARM_DESC(knee_factor, "\n knee_factor, 255=1.0\n"); + +module_param(knee_interpolation_mode, int, 0664); +MODULE_PARM_DESC(knee_interpolation_mode, "\n 0: linear, 1: cubic\n"); + +#define NUM_MATRIX_PARAM 16 +static uint num_customer_matrix_param = NUM_MATRIX_PARAM; +static uint customer_matrix_param[NUM_MATRIX_PARAM] = { + 0, 0, 0, + 0x0d49, 0x1b4d, 0x1f6b, + 0x1f01, 0x0910, 0x1fef, + 0x1fdb, 0x1f32, 0x08f3, + 0, 0, 0, + 1 +}; + +static bool customer_matrix_en = true; + +#define INORM 50000 +#define BL 16 + +static u32 bt709_primaries[3][2] = { + {0.30 * INORM + 0.5, 0.60 * INORM + 0.5}, /* G */ + {0.15 * INORM + 0.5, 0.06 * INORM + 0.5}, /* B */ + {0.64 * INORM + 0.5, 0.33 * INORM + 0.5}, /* R */ +}; + +static u32 bt709_white_point[2] = { + 0.3127 * INORM + 0.5, 0.3290 * INORM + 0.5 +}; + +static u32 bt2020_primaries[3][2] = { + {0.17 * INORM + 0.5, 0.797 * INORM + 0.5}, /* G */ + {0.131 * INORM + 0.5, 0.046 * INORM + 0.5}, /* B */ + {0.708 * INORM + 0.5, 0.292 * INORM + 0.5}, /* R */ +}; + +static u32 bt2020_white_point[2] = { + 0.3127 * INORM + 0.5, 0.3290 * INORM + 0.5 +}; + +/* 0: off, 1: on */ +static int customer_master_display_en; +static uint num_customer_master_display_param = 12; +static uint customer_master_display_param[12] = { + 0.17 * INORM + 0.5, 0.797 * INORM + 0.5, /* G */ + 0.131 * INORM + 0.5, 0.046 * INORM + 0.5, /* B */ + 0.708 * INORM + 0.5, 0.292 * INORM + 0.5, /* R */ + 0.3127 * INORM + 0.5, 0.3290 * INORM + 0.5, /* W */ + 5000 * 10000, 50, + /* man/min lumin */ + 5000, 50 + /* content lumin and frame average */ +}; + +module_param(customer_matrix_en, bool, 0664); +MODULE_PARM_DESC(customer_matrix_en, "\n if enable customer matrix\n"); + +module_param_array(customer_matrix_param, uint, + &num_customer_matrix_param, 0664); +MODULE_PARM_DESC(customer_matrix_param, + "\n matrix from source primary to panel primary\n"); + +module_param(customer_master_display_en, int, 0664); +MODULE_PARM_DESC(customer_master_display_en, + "\n if enable customer primaries and white point\n"); + +module_param_array(customer_master_display_param, uint, + &num_customer_master_display_param, 0664); +MODULE_PARM_DESC(customer_master_display_param, + "\n matrix from source primary and white point\n"); + +/* 0: off, 1: on */ +static int customer_hdmi_display_en; +static uint num_customer_hdmi_display_param = 14; +static uint customer_hdmi_display_param[14] = { + 9, /* color priamry = bt2020 */ + 16, /* characteristic = st2084 */ + 0.17 * INORM + 0.5, 0.797 * INORM + 0.5, /* G */ + 0.131 * INORM + 0.5, 0.046 * INORM + 0.5, /* B */ + 0.708 * INORM + 0.5, 0.292 * INORM + 0.5, /* R */ + 0.3127 * INORM + 0.5, 0.3290 * INORM + 0.5, /* W */ + 9997 * 10000, 0, + /* man/min lumin */ + 5000, 50 + /* content lumin and frame average */ +}; + +module_param(customer_hdmi_display_en, int, 0664); +MODULE_PARM_DESC(customer_hdmi_display_en, + "\n if enable customer primaries and white point\n"); + +module_param_array(customer_hdmi_display_param, uint, + &num_customer_hdmi_display_param, 0664); +MODULE_PARM_DESC(customer_hdmi_display_param, + "\n matrix from source primary and white point\n"); + +/* sat offset when > 1200 and <= 1200 */ +static uint num_extra_sat_lut = 2; +static uint extra_sat_lut[] = {16, 32}; +module_param_array(extra_sat_lut, uint, + &num_extra_sat_lut, 0664); +MODULE_PARM_DESC(extra_sat_lut, + "\n lookup table for saturation match source luminance.\n"); + +/* norm to 128 as 1, LUT can be changed */ +static uint num_extra_con_lut = 5; +static uint extra_con_lut[] = {144, 136, 132, 130, 128}; +module_param_array(extra_con_lut, uint, + &num_extra_con_lut, 0664); +MODULE_PARM_DESC(extra_con_lut, + "\n lookup table for contrast match source luminance.\n"); + +#define clip(y, ymin, ymax) ((y > ymax) ? ymax : ((y < ymin) ? ymin : y)) +static const int coef[] = { + 0, 256, 0, 0, /* phase 0 */ + -2, 256, 2, 0, /* phase 1 */ + -4, 256, 4, 0, /* phase 2 */ + -5, 254, 7, 0, /* phase 3 */ + -7, 254, 10, -1, /* phase 4 */ + -8, 252, 13, -1, /* phase 5 */ + -10, 251, 16, -1, /* phase 6 */ + -11, 249, 19, -1, /* phase 7 */ + -12, 247, 23, -2, /* phase 8 */ + -13, 244, 27, -2, /* phase 9 */ + -14, 242, 31, -3, /* phase 10 */ + -15, 239, 35, -3, /* phase 11 */ + -16, 236, 40, -4, /* phase 12 */ + -17, 233, 44, -4, /* phase 13 */ + -17, 229, 49, -5, /* phase 14 */ + -18, 226, 53, -5, /* phase 15 */ + -18, 222, 58, -6, /* phase 16 */ + -18, 218, 63, -7, /* phase 17 */ + -19, 214, 68, -7, /* phase 18 */ + -19, 210, 73, -8, /* phase 19 */ + -19, 205, 79, -9, /* phase 20 */ + -19, 201, 83, -9, /* phase 21 */ + -19, 196, 89, -10, /* phase 22 */ + -19, 191, 94, -10, /* phase 23 */ + -19, 186, 100, -11, /* phase 24 */ + -18, 181, 105, -12, /* phase 25 */ + -18, 176, 111, -13, /* phase 26 */ + -18, 171, 116, -13, /* phase 27 */ + -18, 166, 122, -14, /* phase 28 */ + -17, 160, 127, -14, /* phase 28 */ + -17, 155, 133, -15, /* phase 30 */ + -16, 149, 138, -15, /* phase 31 */ + -16, 144, 144, -16 /* phase 32 */ +}; + +int cubic_interpolation(int y0, int y1, int y2, int y3, int mu) +{ + int c0, c1, c2, c3; + int d0, d1, d2, d3; + + if (mu <= 32) { + c0 = coef[(mu << 2) + 0]; + c1 = coef[(mu << 2) + 1]; + c2 = coef[(mu << 2) + 2]; + c3 = coef[(mu << 2) + 3]; + d0 = y0; d1 = y1; d2 = y2; d3 = y3; + } else { + c0 = coef[((64 - mu) << 2) + 0]; + c1 = coef[((64 - mu) << 2) + 1]; + c2 = coef[((64 - mu) << 2) + 2]; + c3 = coef[((64 - mu) << 2) + 3]; + d0 = y3; d1 = y2; d2 = y1; d3 = y0; + } + return (d0 * c0 + d1 * c1 + d2 * c2 + d3 * c3 + 128) >> 8; +} + +static int knee_lut_on; +static int cur_knee_factor = -1; +static void load_knee_lut(int on) +{ + int i, j, k; + int value; + int final_knee_setting[MAX_KNEE_SETTING]; + + if ((cur_knee_factor != knee_factor) && (!lut_289_en)) { + pr_csc("Knee_factor changed from %d to %d\n", + cur_knee_factor, knee_factor); + for (i = 0; i < MAX_KNEE_SETTING; i++) { + final_knee_setting[i] = + knee_linear_setting[i] + (((knee_setting[i] + - knee_linear_setting[i]) * knee_factor) >> 8); + if (final_knee_setting[i] > 0x3ff) + final_knee_setting[i] = 0x3ff; + else if (final_knee_setting[i] < 0) + final_knee_setting[i] = 0; + } + WRITE_VPP_REG(XVYCC_LUT_CTL, 0x0); + for (j = 0; j < 3; j++) { + for (i = 0; i < 16; i++) { + WRITE_VPP_REG(XVYCC_LUT_R_ADDR_PORT + 2 * j, i); + value = final_knee_setting[0] + + (((final_knee_setting[1] + - final_knee_setting[0]) * i) >> 4); + value = clip(value, 0, 0x3ff); + WRITE_VPP_REG(XVYCC_LUT_R_DATA_PORT + 2 * j, + value); + if (j == 0) + pr_csc("xvycc_lut[%1d][%3d] = 0x%03x\n", + j, i, value); + } + for (i = 16; i < 272; i++) { + k = 1 + ((i - 16) >> 3); + WRITE_VPP_REG(XVYCC_LUT_R_ADDR_PORT + 2 * j, i); + if (knee_interpolation_mode == 0) + value = final_knee_setting[k] + + (((final_knee_setting[k+1] + - final_knee_setting[k]) + * ((i - 16) & 0x7)) >> 3); + else + value = cubic_interpolation( + final_knee_setting[k-1], + final_knee_setting[k], + final_knee_setting[k+1], + final_knee_setting[k+2], + ((i - 16) & 0x7) << 3); + value = clip(value, 0, 0x3ff); + WRITE_VPP_REG(XVYCC_LUT_R_DATA_PORT + 2 * j, + value); + if (j == 0) + pr_csc("xvycc_lut[%1d][%3d] = 0x%03x\n", + j, i, value); + } + for (i = 272; i < 289; i++) { + k = MAX_KNEE_SETTING - 2; + WRITE_VPP_REG(XVYCC_LUT_R_ADDR_PORT + 2 * j, i); + value = final_knee_setting[k] + + (((final_knee_setting[k+1] + - final_knee_setting[k]) + * (i - 272)) >> 4); + value = clip(value, 0, 0x3ff); + WRITE_VPP_REG(XVYCC_LUT_R_DATA_PORT + 2 * j, + value); + if (j == 0) + pr_csc("xvycc_lut[%1d][%3d] = 0x%03x\n", + j, i, value); + } + } + cur_knee_factor = knee_factor; + } + + if ((cur_knee_factor != knee_factor) && (lut_289_en)) { + WRITE_VPP_REG(XVYCC_LUT_CTL, 0x0); + WRITE_VPP_REG(XVYCC_LUT_R_ADDR_PORT, 0); + for (i = 0; i < LUT_289_SIZE; i++) + WRITE_VPP_REG(XVYCC_LUT_R_DATA_PORT, + lut_289_mapping[i]); + WRITE_VPP_REG(XVYCC_LUT_R_ADDR_PORT + 2, 0); + for (i = 0; i < LUT_289_SIZE; i++) + WRITE_VPP_REG(XVYCC_LUT_R_DATA_PORT + 2, + lut_289_mapping[i]); + WRITE_VPP_REG(XVYCC_LUT_R_ADDR_PORT + 4, 0); + for (i = 0; i < LUT_289_SIZE; i++) + WRITE_VPP_REG(XVYCC_LUT_R_DATA_PORT + 4, + lut_289_mapping[i]); + cur_knee_factor = knee_factor; + } + + if (on) { + WRITE_VPP_REG(XVYCC_LUT_CTL, 0x7f); + knee_lut_on = 1; + } else { + WRITE_VPP_REG(XVYCC_LUT_CTL, 0x0f); + knee_lut_on = 0; + } +} + +/***************************** gxl hdr ****************************/ +/* 16 for [-2048, 0), 32 for [0, 1024), 17 for [1024, 2048) */ +#define EOTF_INV_LUT_NEG2048_SIZE 16 +#define EOTF_INV_LUT_SIZE 32 +#define EOTF_INV_LUT_1024_SIZE 17 + +static unsigned int num_invlut_neg_mapping = EOTF_INV_LUT_NEG2048_SIZE; +static int invlut_y_neg[EOTF_INV_LUT_NEG2048_SIZE] = { + -2048, -1920, -1792, -1664, + -1536, -1408, -1280, -1152, + -1024, -896, -768, -640, + -512, -384, -256, -128 +}; + +static unsigned int num_invlut_mapping = EOTF_INV_LUT_SIZE; +static unsigned int invlut_y[EOTF_INV_LUT_SIZE] = { + 0, 32, 64, 96, 128, 160, 192, 224, + 256, 288, 320, 352, 384, 416, 448, 480, + 512, 544, 576, 608, 640, 672, 704, 736, + 768, 800, 832, 864, 896, 928, 960, 992 +}; + +static unsigned int num_invlut_1024_mapping = EOTF_INV_LUT_1024_SIZE; +static unsigned int invlut_y_1024[EOTF_INV_LUT_1024_SIZE] = { + 1024, 1088, 1152, 1216, + 1280, 1344, 1408, 1472, + 1536, 1600, 1664, 1728, + 1792, 1856, 1920, 1984, + 2047 +}; + +#define EOTF_LUT_SIZE 33 +static unsigned int num_osd_eotf_r_mapping = EOTF_LUT_SIZE; +static unsigned int osd_eotf_r_mapping[EOTF_LUT_SIZE] = { + 0x0000, 0x0200, 0x0400, 0x0600, + 0x0800, 0x0a00, 0x0c00, 0x0e00, + 0x1000, 0x1200, 0x1400, 0x1600, + 0x1800, 0x1a00, 0x1c00, 0x1e00, + 0x2000, 0x2200, 0x2400, 0x2600, + 0x2800, 0x2a00, 0x2c00, 0x2e00, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3800, 0x3a00, 0x3c00, 0x3e00, + 0x4000 +}; + +static unsigned int num_osd_eotf_g_mapping = EOTF_LUT_SIZE; +static unsigned int osd_eotf_g_mapping[EOTF_LUT_SIZE] = { + 0x0000, 0x0200, 0x0400, 0x0600, + 0x0800, 0x0a00, 0x0c00, 0x0e00, + 0x1000, 0x1200, 0x1400, 0x1600, + 0x1800, 0x1a00, 0x1c00, 0x1e00, + 0x2000, 0x2200, 0x2400, 0x2600, + 0x2800, 0x2a00, 0x2c00, 0x2e00, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3800, 0x3a00, 0x3c00, 0x3e00, + 0x4000 +}; + +static unsigned int num_osd_eotf_b_mapping = EOTF_LUT_SIZE; +static unsigned int osd_eotf_b_mapping[EOTF_LUT_SIZE] = { + 0x0000, 0x0200, 0x0400, 0x0600, + 0x0800, 0x0a00, 0x0c00, 0x0e00, + 0x1000, 0x1200, 0x1400, 0x1600, + 0x1800, 0x1a00, 0x1c00, 0x1e00, + 0x2000, 0x2200, 0x2400, 0x2600, + 0x2800, 0x2a00, 0x2c00, 0x2e00, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3800, 0x3a00, 0x3c00, 0x3e00, + 0x4000 +}; + +static unsigned int num_video_eotf_r_mapping = EOTF_LUT_SIZE; +static unsigned int video_eotf_r_mapping[EOTF_LUT_SIZE] = { + 0x0000, 0x0200, 0x0400, 0x0600, + 0x0800, 0x0a00, 0x0c00, 0x0e00, + 0x1000, 0x1200, 0x1400, 0x1600, + 0x1800, 0x1a00, 0x1c00, 0x1e00, + 0x2000, 0x2200, 0x2400, 0x2600, + 0x2800, 0x2a00, 0x2c00, 0x2e00, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3800, 0x3a00, 0x3c00, 0x3e00, + 0x4000 +}; + +static unsigned int num_video_eotf_g_mapping = EOTF_LUT_SIZE; +static unsigned int video_eotf_g_mapping[EOTF_LUT_SIZE] = { + 0x0000, 0x0200, 0x0400, 0x0600, + 0x0800, 0x0a00, 0x0c00, 0x0e00, + 0x1000, 0x1200, 0x1400, 0x1600, + 0x1800, 0x1a00, 0x1c00, 0x1e00, + 0x2000, 0x2200, 0x2400, 0x2600, + 0x2800, 0x2a00, 0x2c00, 0x2e00, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3800, 0x3a00, 0x3c00, 0x3e00, + 0x4000 +}; + +static unsigned int num_video_eotf_b_mapping = EOTF_LUT_SIZE; +static unsigned int video_eotf_b_mapping[EOTF_LUT_SIZE] = { + 0x0000, 0x0200, 0x0400, 0x0600, + 0x0800, 0x0a00, 0x0c00, 0x0e00, + 0x1000, 0x1200, 0x1400, 0x1600, + 0x1800, 0x1a00, 0x1c00, 0x1e00, + 0x2000, 0x2200, 0x2400, 0x2600, + 0x2800, 0x2a00, 0x2c00, 0x2e00, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3800, 0x3a00, 0x3c00, 0x3e00, + 0x4000 +}; + +#define EOTF_COEFF_NORM(a) ((int)((((a) * 4096.0) + 1) / 2)) +#define EOTF_COEFF_SIZE 10 +#define EOTF_COEFF_RIGHTSHIFT 1 +static unsigned int num_osd_eotf_coeff = EOTF_COEFF_SIZE; +static int osd_eotf_coeff[EOTF_COEFF_SIZE] = { + EOTF_COEFF_NORM(1.0), EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(0.0), + EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(1.0), EOTF_COEFF_NORM(0.0), + EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(1.0), + EOTF_COEFF_RIGHTSHIFT /* right shift */ +}; + +static unsigned int num_video_eotf_coeff = EOTF_COEFF_SIZE; +static int video_eotf_coeff[EOTF_COEFF_SIZE] = { + EOTF_COEFF_NORM(1.0), EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(0.0), + EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(1.0), EOTF_COEFF_NORM(0.0), + EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(1.0), + EOTF_COEFF_RIGHTSHIFT /* right shift */ +}; + +static unsigned int reload_mtx; +static unsigned int reload_lut; + +/******************** osd oetf **************/ + +static unsigned int num_osd_oetf_r_mapping = OSD_OETF_LUT_SIZE; +static unsigned int osd_oetf_r_mapping[OSD_OETF_LUT_SIZE] = { + 0, 4, 8, 12, + 16, 20, 24, 28, + 31, 62, 93, 124, + 155, 186, 217, 248, + 279, 310, 341, 372, + 403, 434, 465, 496, + 527, 558, 589, 620, + 651, 682, 713, 744, + 775, 806, 837, 868, + 899, 930, 961, 992, + 1023 +}; + +static unsigned int num_osd_oetf_g_mapping = OSD_OETF_LUT_SIZE; +static unsigned int osd_oetf_g_mapping[OSD_OETF_LUT_SIZE] = { + 0, 4, 8, 12, + 16, 20, 24, 28, + 31, 62, 93, 124, + 155, 186, 217, 248, + 279, 310, 341, 372, + 403, 434, 465, 496, + 527, 558, 589, 620, + 651, 682, 713, 744, + 775, 806, 837, 868, + 899, 930, 961, 992, + 1023 +}; + +static unsigned int num_osd_oetf_b_mapping = OSD_OETF_LUT_SIZE; +static unsigned int osd_oetf_b_mapping[OSD_OETF_LUT_SIZE] = { + 0, 4, 8, 12, + 16, 20, 24, 28, + 31, 62, 93, 124, + 155, 186, 217, 248, + 279, 310, 341, 372, + 403, 434, 465, 496, + 527, 558, 589, 620, + 651, 682, 713, 744, + 775, 806, 837, 868, + 899, 930, 961, 992, + 1023 +}; + +/************ video oetf ***************/ + +#define VIDEO_OETF_LUT_SIZE 289 +static unsigned int num_video_oetf_r_mapping = VIDEO_OETF_LUT_SIZE; +static unsigned int video_oetf_r_mapping[VIDEO_OETF_LUT_SIZE] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 4, 8, 12, 16, 20, 24, 28, 32, + 36, 40, 44, 48, 52, 56, 60, 64, + 68, 72, 76, 80, 84, 88, 92, 96, + 100, 104, 108, 112, 116, 120, 124, 128, + 132, 136, 140, 144, 148, 152, 156, 160, + 164, 168, 172, 176, 180, 184, 188, 192, + 196, 200, 204, 208, 212, 216, 220, 224, + 228, 232, 236, 240, 244, 248, 252, 256, + 260, 264, 268, 272, 276, 280, 284, 288, + 292, 296, 300, 304, 308, 312, 316, 320, + 324, 328, 332, 336, 340, 344, 348, 352, + 356, 360, 364, 368, 372, 376, 380, 384, + 388, 392, 396, 400, 404, 408, 412, 416, + 420, 424, 428, 432, 436, 440, 444, 448, + 452, 456, 460, 464, 468, 472, 476, 480, + 484, 488, 492, 496, 500, 504, 508, 512, + 516, 520, 524, 528, 532, 536, 540, 544, + 548, 552, 556, 560, 564, 568, 572, 576, + 580, 584, 588, 592, 596, 600, 604, 608, + 612, 616, 620, 624, 628, 632, 636, 640, + 644, 648, 652, 656, 660, 664, 668, 672, + 676, 680, 684, 688, 692, 696, 700, 704, + 708, 712, 716, 720, 724, 728, 732, 736, + 740, 744, 748, 752, 756, 760, 764, 768, + 772, 776, 780, 784, 788, 792, 796, 800, + 804, 808, 812, 816, 820, 824, 828, 832, + 836, 840, 844, 848, 852, 856, 860, 864, + 868, 872, 876, 880, 884, 888, 892, 896, + 900, 904, 908, 912, 916, 920, 924, 928, + 932, 936, 940, 944, 948, 952, 956, 960, + 964, 968, 972, 976, 980, 984, 988, 992, + 996, 1000, 1004, 1008, 1012, 1016, 1020, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; + +static unsigned int num_video_oetf_g_mapping = VIDEO_OETF_LUT_SIZE; +static unsigned int video_oetf_g_mapping[VIDEO_OETF_LUT_SIZE] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 4, 8, 12, 16, 20, 24, 28, 32, + 36, 40, 44, 48, 52, 56, 60, 64, + 68, 72, 76, 80, 84, 88, 92, 96, + 100, 104, 108, 112, 116, 120, 124, 128, + 132, 136, 140, 144, 148, 152, 156, 160, + 164, 168, 172, 176, 180, 184, 188, 192, + 196, 200, 204, 208, 212, 216, 220, 224, + 228, 232, 236, 240, 244, 248, 252, 256, + 260, 264, 268, 272, 276, 280, 284, 288, + 292, 296, 300, 304, 308, 312, 316, 320, + 324, 328, 332, 336, 340, 344, 348, 352, + 356, 360, 364, 368, 372, 376, 380, 384, + 388, 392, 396, 400, 404, 408, 412, 416, + 420, 424, 428, 432, 436, 440, 444, 448, + 452, 456, 460, 464, 468, 472, 476, 480, + 484, 488, 492, 496, 500, 504, 508, 512, + 516, 520, 524, 528, 532, 536, 540, 544, + 548, 552, 556, 560, 564, 568, 572, 576, + 580, 584, 588, 592, 596, 600, 604, 608, + 612, 616, 620, 624, 628, 632, 636, 640, + 644, 648, 652, 656, 660, 664, 668, 672, + 676, 680, 684, 688, 692, 696, 700, 704, + 708, 712, 716, 720, 724, 728, 732, 736, + 740, 744, 748, 752, 756, 760, 764, 768, + 772, 776, 780, 784, 788, 792, 796, 800, + 804, 808, 812, 816, 820, 824, 828, 832, + 836, 840, 844, 848, 852, 856, 860, 864, + 868, 872, 876, 880, 884, 888, 892, 896, + 900, 904, 908, 912, 916, 920, 924, 928, + 932, 936, 940, 944, 948, 952, 956, 960, + 964, 968, 972, 976, 980, 984, 988, 992, + 996, 1000, 1004, 1008, 1012, 1016, 1020, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; + +static unsigned int num_video_oetf_b_mapping = VIDEO_OETF_LUT_SIZE; +static unsigned int video_oetf_b_mapping[VIDEO_OETF_LUT_SIZE] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 4, 8, 12, 16, 20, 24, 28, 32, + 36, 40, 44, 48, 52, 56, 60, 64, + 68, 72, 76, 80, 84, 88, 92, 96, + 100, 104, 108, 112, 116, 120, 124, 128, + 132, 136, 140, 144, 148, 152, 156, 160, + 164, 168, 172, 176, 180, 184, 188, 192, + 196, 200, 204, 208, 212, 216, 220, 224, + 228, 232, 236, 240, 244, 248, 252, 256, + 260, 264, 268, 272, 276, 280, 284, 288, + 292, 296, 300, 304, 308, 312, 316, 320, + 324, 328, 332, 336, 340, 344, 348, 352, + 356, 360, 364, 368, 372, 376, 380, 384, + 388, 392, 396, 400, 404, 408, 412, 416, + 420, 424, 428, 432, 436, 440, 444, 448, + 452, 456, 460, 464, 468, 472, 476, 480, + 484, 488, 492, 496, 500, 504, 508, 512, + 516, 520, 524, 528, 532, 536, 540, 544, + 548, 552, 556, 560, 564, 568, 572, 576, + 580, 584, 588, 592, 596, 600, 604, 608, + 612, 616, 620, 624, 628, 632, 636, 640, + 644, 648, 652, 656, 660, 664, 668, 672, + 676, 680, 684, 688, 692, 696, 700, 704, + 708, 712, 716, 720, 724, 728, 732, 736, + 740, 744, 748, 752, 756, 760, 764, 768, + 772, 776, 780, 784, 788, 792, 796, 800, + 804, 808, 812, 816, 820, 824, 828, 832, + 836, 840, 844, 848, 852, 856, 860, 864, + 868, 872, 876, 880, 884, 888, 892, 896, + 900, 904, 908, 912, 916, 920, 924, 928, + 932, 936, 940, 944, 948, 952, 956, 960, + 964, 968, 972, 976, 980, 984, 988, 992, + 996, 1000, 1004, 1008, 1012, 1016, 1020, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; + +#define COEFF_NORM(a) ((int)((((a) * 2048.0) + 1) / 2)) +#define MATRIX_5x3_COEF_SIZE 24 +/******* osd1 matrix0 *******/ +/* default rgb to yuv_limit */ +static unsigned int num_osd_matrix_coeff = MATRIX_5x3_COEF_SIZE; +static int osd_matrix_coeff[MATRIX_5x3_COEF_SIZE] = { + 0, 0, 0, /* pre offset */ + COEFF_NORM(0.2126), COEFF_NORM(0.7152), COEFF_NORM(0.0722), + COEFF_NORM(-0.11457), COEFF_NORM(-0.38543), COEFF_NORM(0.5), + COEFF_NORM(0.5), COEFF_NORM(-0.45415), COEFF_NORM(-0.045847), + 0, 0, 0, /* 30/31/32 */ + 0, 0, 0, /* 40/41/42 */ + 0, 512, 512, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +static unsigned int num_vd1_matrix_coeff = MATRIX_5x3_COEF_SIZE; +static int vd1_matrix_coeff[MATRIX_5x3_COEF_SIZE] = { + 0, 0, 0, /* pre offset */ + COEFF_NORM(1.0), COEFF_NORM(0.0), COEFF_NORM(0.0), + COEFF_NORM(0.0), COEFF_NORM(1.0), COEFF_NORM(0.0), + COEFF_NORM(0.0), COEFF_NORM(0.0), COEFF_NORM(1.0), + 0, 0, 0, /* 30/31/32 */ + 0, 0, 0, /* 40/41/42 */ + 0, 0, 0, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +static unsigned int num_vd2_matrix_coeff = MATRIX_5x3_COEF_SIZE; +static int vd2_matrix_coeff[MATRIX_5x3_COEF_SIZE] = { + 0, 0, 0, /* pre offset */ + COEFF_NORM(1.0), COEFF_NORM(0.0), COEFF_NORM(0.0), + COEFF_NORM(0.0), COEFF_NORM(1.0), COEFF_NORM(0.0), + COEFF_NORM(0.0), COEFF_NORM(0.0), COEFF_NORM(1.0), + 0, 0, 0, /* 30/31/32 */ + 0, 0, 0, /* 40/41/42 */ + 0, 0, 0, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +static unsigned int num_post_matrix_coeff = MATRIX_5x3_COEF_SIZE; +static int post_matrix_coeff[MATRIX_5x3_COEF_SIZE] = { + 0, 0, 0, /* pre offset */ + COEFF_NORM(1.0), COEFF_NORM(0.0), COEFF_NORM(0.0), + COEFF_NORM(0.0), COEFF_NORM(1.0), COEFF_NORM(0.0), + COEFF_NORM(0.0), COEFF_NORM(0.0), COEFF_NORM(1.0), + 0, 0, 0, /* 30/31/32 */ + 0, 0, 0, /* 40/41/42 */ + 0, 0, 0, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +static unsigned int num_xvycc_matrix_coeff = MATRIX_5x3_COEF_SIZE; +static int xvycc_matrix_coeff[MATRIX_5x3_COEF_SIZE] = { + 0, 0, 0, /* pre offset */ + COEFF_NORM(1.0), COEFF_NORM(0.0), COEFF_NORM(0.0), + COEFF_NORM(0.0), COEFF_NORM(1.0), COEFF_NORM(0.0), + COEFF_NORM(0.0), COEFF_NORM(0.0), COEFF_NORM(1.0), + 0, 0, 0, /* 30/31/32 */ + 0, 0, 0, /* 40/41/42 */ + 0, 0, 0, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +/****************** osd eotf ********************/ +module_param_array(osd_eotf_coeff, int, + &num_osd_eotf_coeff, 0664); +MODULE_PARM_DESC(osd_eotf_coeff, "\n matrix for osd eotf\n"); + +module_param_array(osd_eotf_r_mapping, uint, + &num_osd_eotf_r_mapping, 0664); +MODULE_PARM_DESC(osd_eotf_r_mapping, "\n lut for osd r eotf\n"); + +module_param_array(osd_eotf_g_mapping, uint, + &num_osd_eotf_g_mapping, 0664); +MODULE_PARM_DESC(osd_eotf_g_mapping, "\n lut for osd g eotf\n"); + +module_param_array(osd_eotf_b_mapping, uint, + &num_osd_eotf_b_mapping, 0664); +MODULE_PARM_DESC(osd_eotf_b_mapping, "\n lut for osd b eotf\n"); + +module_param_array(osd_matrix_coeff, int, + &num_osd_matrix_coeff, 0664); +MODULE_PARM_DESC(osd_matrix_coeff, "\n coef for osd matrix\n"); + +/****************** video eotf ********************/ +module_param_array(invlut_y_neg, int, + &num_invlut_neg_mapping, 0664); +MODULE_PARM_DESC(invlut_y_neg, "\n lut for inv y -2048..0 eotf\n"); + +module_param_array(invlut_y, uint, + &num_invlut_mapping, 0664); +MODULE_PARM_DESC(invlut_y, "\n lut for inv y 0..1024 eotf\n"); + +module_param_array(invlut_y_1024, uint, + &num_invlut_1024_mapping, 0664); +MODULE_PARM_DESC(invlut_y_1024, "\n lut for inv y 1024..2048 eotf\n"); + +module_param_array(video_eotf_coeff, int, + &num_video_eotf_coeff, 0664); +MODULE_PARM_DESC(video_eotf_coeff, "\n matrix for video eotf\n"); + +module_param_array(video_eotf_r_mapping, uint, + &num_video_eotf_r_mapping, 0664); +MODULE_PARM_DESC(video_eotf_r_mapping, "\n lut for video r eotf\n"); + +module_param_array(video_eotf_g_mapping, uint, + &num_video_eotf_g_mapping, 0664); +MODULE_PARM_DESC(video_eotf_g_mapping, "\n lut for video g eotf\n"); + +module_param_array(video_eotf_b_mapping, uint, + &num_video_eotf_b_mapping, 0664); +MODULE_PARM_DESC(video_eotf_b_mapping, "\n lut for video b eotf\n"); + +/****************** osd oetf ********************/ +module_param_array(osd_oetf_r_mapping, uint, + &num_osd_oetf_r_mapping, 0664); +MODULE_PARM_DESC(osd_oetf_r_mapping, "\n lut for osd r oetf\n"); + +module_param_array(osd_oetf_g_mapping, uint, + &num_osd_oetf_g_mapping, 0664); +MODULE_PARM_DESC(osd_oetf_g_mapping, "\n lut for osd g oetf\n"); + +module_param_array(osd_oetf_b_mapping, uint, + &num_osd_oetf_b_mapping, 0664); +MODULE_PARM_DESC(osd_oetf_b_mapping, "\n lut for osd b oetf\n"); + +/****************** video oetf ********************/ +module_param_array(video_oetf_r_mapping, uint, + &num_video_oetf_r_mapping, 0664); +MODULE_PARM_DESC(video_oetf_r_mapping, "\n lut for video r oetf\n"); + +module_param_array(video_oetf_g_mapping, uint, + &num_video_oetf_g_mapping, 0664); +MODULE_PARM_DESC(video_oetf_g_mapping, "\n lut for video g oetf\n"); + +module_param_array(video_oetf_b_mapping, uint, + &num_video_oetf_b_mapping, 0664); +MODULE_PARM_DESC(video_oetf_b_mapping, "\n lut for video b oetf\n"); + +/****************** vpp matrix ********************/ + +module_param_array(vd1_matrix_coeff, int, + &num_vd1_matrix_coeff, 0664); +MODULE_PARM_DESC(vd1_matrix_coeff, "\n vd1 matrix\n"); + +module_param_array(vd2_matrix_coeff, int, + &num_vd2_matrix_coeff, 0664); +MODULE_PARM_DESC(vd2_matrix_coeff, "\n vd2 matrix\n"); + +module_param_array(post_matrix_coeff, int, + &num_post_matrix_coeff, 0664); +MODULE_PARM_DESC(post_matrix_coeff, "\n post matrix\n"); + +module_param_array(xvycc_matrix_coeff, int, + &num_xvycc_matrix_coeff, 0664); +MODULE_PARM_DESC(xvycc_matrix_coeff, "\n xvycc matrix\n"); + +/****************** matrix/lut reload********************/ + +module_param(reload_mtx, uint, 0664); +MODULE_PARM_DESC(reload_mtx, "\n reload matrix coeff\n"); + +module_param(reload_lut, uint, 0664); +MODULE_PARM_DESC(reload_lut, "\n reload lut settings\n"); + +static int RGB709_to_YUV709_coeff[MATRIX_5x3_COEF_SIZE] = { + 0, 0, 0, /* pre offset */ + COEFF_NORM(0.2126), COEFF_NORM(0.7152), COEFF_NORM(0.0722), + COEFF_NORM(-0.114572), COEFF_NORM(-0.385428), COEFF_NORM(0.5), + COEFF_NORM(0.5), COEFF_NORM(-0.454153), COEFF_NORM(-0.045847), + 0, 0, 0, /* 10'/11'/12' */ + 0, 0, 0, /* 20'/21'/22' */ + 0, 512, 512, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +static int RGB709_to_YUV709l_coeff[MATRIX_5x3_COEF_SIZE] = { + 0, 0, 0, /* pre offset */ + COEFF_NORM(0.181873), COEFF_NORM(0.611831), COEFF_NORM(0.061765), + COEFF_NORM(-0.100251), COEFF_NORM(-0.337249), COEFF_NORM(0.437500), + COEFF_NORM(0.437500), COEFF_NORM(-0.397384), COEFF_NORM(-0.040116), + 0, 0, 0, /* 10'/11'/12' */ + 0, 0, 0, /* 20'/21'/22' */ + 64, 512, 512, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +static int RGB2020_to_YUV2020l_coeff[MATRIX_5x3_COEF_SIZE] = { + 0, 0, 0, /* pre offset */ + COEFF_NORM(0.224732), COEFF_NORM(0.580008), COEFF_NORM(0.050729), + COEFF_NORM(-0.122176), COEFF_NORM(-0.315324), COEFF_NORM(0.437500), + COEFF_NORM(0.437500), COEFF_NORM(-0.402312), COEFF_NORM(-0.035188), + 0, 0, 0, /* 30/31/32 */ + 0, 0, 0, /* 40/41/42 */ + 64, 512, 512, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +static int YUV709f_to_YUV709l_coeff[MATRIX_5x3_COEF_SIZE] = { + 0, -512, -512, /* pre offset */ + COEFF_NORM(0.859), COEFF_NORM(0), COEFF_NORM(0), + COEFF_NORM(0), COEFF_NORM(0.878), COEFF_NORM(0), + COEFF_NORM(0), COEFF_NORM(0), COEFF_NORM(0.878), + 0, 0, 0, /* 10'/11'/12' */ + 0, 0, 0, /* 20'/21'/22' */ + 64, 512, 512, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +static int YUV709l_to_YUV709f_coeff[MATRIX_5x3_COEF_SIZE] = { + 64, -512, -512, /* pre offset */ + COEFF_NORM(1.16895), COEFF_NORM(0), COEFF_NORM(0), + COEFF_NORM(0), COEFF_NORM(1.14286), COEFF_NORM(0), + COEFF_NORM(0), COEFF_NORM(0), COEFF_NORM(1.14286), + 0, 0, 0, /* 10'/11'/12' */ + 0, 0, 0, /* 20'/21'/22' */ + 0, 512, 512, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +static int YUV709l_to_RGB709_coeff[MATRIX_5x3_COEF_SIZE] = { + -64, -512, -512, /* pre offset */ + COEFF_NORM(1.16895), COEFF_NORM(0.00000), COEFF_NORM(1.79977), + COEFF_NORM(1.16895), COEFF_NORM(-0.21408), COEFF_NORM(-0.53500), + COEFF_NORM(1.16895), COEFF_NORM(2.12069), COEFF_NORM(0.00000), + 0, 0, 0, /* 30/31/32 */ + 0, 0, 0, /* 40/41/42 */ + 0, 0, 0, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +#if 0 +/* eotf matrix: RGB2020 to RGB709 */ +static int eotf_RGB2020_to_RGB709_coeff[EOTF_COEFF_SIZE] = { + EOTF_COEFF_NORM(1.6607056/2), EOTF_COEFF_NORM(-0.5877533/2), + EOTF_COEFF_NORM(-0.0729065/2), + EOTF_COEFF_NORM(-0.1245575/2), EOTF_COEFF_NORM(1.1329346/2), + EOTF_COEFF_NORM(-0.0083771/2), + EOTF_COEFF_NORM(-0.0181122/2), EOTF_COEFF_NORM(-0.1005249/2), + EOTF_COEFF_NORM(1.1186371/2), + EOTF_COEFF_RIGHTSHIFT +}; +#endif + +static int bypass_coeff[MATRIX_5x3_COEF_SIZE] = { + 0, 0, 0, /* pre offset */ + COEFF_NORM(1.0), COEFF_NORM(0.0), COEFF_NORM(0.0), + COEFF_NORM(0.0), COEFF_NORM(1.0), COEFF_NORM(0.0), + COEFF_NORM(0.0), COEFF_NORM(0.0), COEFF_NORM(1.0), + 0, 0, 0, /* 10'/11'/12' */ + 0, 0, 0, /* 20'/21'/22' */ + 0, 0, 0, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +/* eotf matrix: bypass */ +static int eotf_bypass_coeff[EOTF_COEFF_SIZE] = { + EOTF_COEFF_NORM(1.0), EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(0.0), + EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(1.0), EOTF_COEFF_NORM(0.0), + EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(1.0), + EOTF_COEFF_RIGHTSHIFT /* right shift */ +}; + +static int eotf_RGB709_to_RGB2020_coeff[EOTF_COEFF_SIZE] = { + EOTF_COEFF_NORM(0.627441), EOTF_COEFF_NORM(0.329285), + EOTF_COEFF_NORM(0.043274), + EOTF_COEFF_NORM(0.069092), EOTF_COEFF_NORM(0.919556), + EOTF_COEFF_NORM(0.011322), + EOTF_COEFF_NORM(0.016418), EOTF_COEFF_NORM(0.088058), + EOTF_COEFF_NORM(0.895554), + EOTF_COEFF_RIGHTSHIFT /* right shift */ +}; + +/* post matrix: YUV2020 limit to RGB2020 */ +static int YUV2020l_to_RGB2020_coeff[MATRIX_5x3_COEF_SIZE] = { + -64, -512, -512, /* pre offset */ + COEFF_NORM(1.16895), COEFF_NORM(0.00000), COEFF_NORM(1.68526), + COEFF_NORM(1.16895), COEFF_NORM(-0.18806), COEFF_NORM(-0.65298), + COEFF_NORM(1.16895), COEFF_NORM(2.15017), COEFF_NORM(0.00000), + 0, 0, 0, /* 30/31/32 */ + 0, 0, 0, /* 40/41/42 */ + 0, 0, 0, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +/* eotf lut: linear */ +static unsigned int eotf_33_linear_mapping[EOTF_LUT_SIZE] = { + 0x0000, 0x0200, 0x0400, 0x0600, + 0x0800, 0x0a00, 0x0c00, 0x0e00, + 0x1000, 0x1200, 0x1400, 0x1600, + 0x1800, 0x1a00, 0x1c00, 0x1e00, + 0x2000, 0x2200, 0x2400, 0x2600, + 0x2800, 0x2a00, 0x2c00, 0x2e00, + 0x3000, 0x3200, 0x3400, 0x3600, + 0x3800, 0x3a00, 0x3c00, 0x3e00, + 0x4000 +}; + +/* osd oetf lut: linear */ +static unsigned int oetf_41_linear_mapping[OSD_OETF_LUT_SIZE] = { + 0, 4, 8, 12, + 16, 20, 24, 28, + 31, 62, 93, 124, + 155, 186, 217, 248, + 279, 310, 341, 372, + 403, 434, 465, 496, + 527, 558, 589, 620, + 651, 682, 713, 744, + 775, 806, 837, 868, + 899, 930, 961, 992, + 1023 +}; + +/* following array generated from model, do not edit */ +static int video_lut_swtich; +module_param(video_lut_swtich, int, 0664); +MODULE_PARM_DESC(video_lut_swtich, "\n video_lut_swtich\n"); + +/* gamma=2.200000 lumin=500 boost=0.075000 */ +static unsigned int display_scale_factor = + (unsigned int)((((1.000000) * 4096.0) + 1) / 2); + +static unsigned int eotf_33_2084_mapping[EOTF_LUT_SIZE] = { + 0, 3, 6, 11, 18, 27, 40, 58, + 84, 119, 169, 237, 329, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 +}; + +static unsigned int oetf_289_gamma22_mapping[VIDEO_OETF_LUT_SIZE] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 125, 171, 206, 235, 259, 281, 302, + 321, 339, 356, 371, 386, 401, 414, 427, + 440, 453, 465, 476, 488, 498, 509, 519, + 529, 539, 549, 558, 568, 577, 586, 595, + 603, 612, 620, 628, 637, 645, 652, 660, + 668, 675, 683, 690, 697, 705, 712, 719, + 726, 733, 740, 748, 755, 763, 771, 778, + 786, 793, 801, 808, 814, 821, 827, 832, + 837, 842, 846, 849, 852, 854, 856, 858, + 860, 862, 864, 866, 867, 869, 871, 873, + 875, 877, 879, 880, 882, 884, 886, 887, + 889, 891, 893, 894, 896, 898, 899, 901, + 902, 904, 906, 907, 909, 910, 912, 914, + 915, 917, 918, 920, 921, 923, 924, 925, + 927, 928, 930, 931, 933, 934, 935, 937, + 938, 939, 941, 942, 943, 945, 946, 947, + 948, 950, 951, 952, 953, 954, 956, 957, + 958, 959, 960, 961, 962, 963, 965, 966, + 967, 968, 969, 970, 971, 972, 973, 974, + 975, 976, 977, 978, 979, 980, 981, 981, + 982, 983, 984, 985, 986, 987, 987, 988, + 989, 990, 991, 991, 992, 993, 994, 995, + 995, 996, 997, 997, 998, 999, 999, 1000, + 1001, 1001, 1002, 1003, 1003, 1004, 1004, 1005, + 1006, 1006, 1007, 1007, 1008, 1008, 1009, 1009, + 1010, 1010, 1011, 1011, 1012, 1012, 1012, 1013, + 1013, 1014, 1014, 1015, 1015, 1015, 1016, 1016, + 1016, 1017, 1017, 1017, 1018, 1018, 1018, 1019, + 1019, 1019, 1019, 1020, 1020, 1020, 1020, 1020, + 1021, 1021, 1021, 1021, 1021, 1022, 1022, 1022, + 1022, 1022, 1022, 1022, 1022, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; + +/* osd eotf lut: 709 */ +static unsigned int osd_eotf_33_709_mapping[EOTF_LUT_SIZE] = { + 0, 512, 1024, 1536, 2048, 2560, 3072, 3584, + 4096, 4608, 5120, 5632, 6144, 6656, 7168, 7680, + 8192, 8704, 9216, 9728, 10240, 10752, 11264, 11776, + 12288, 12800, 13312, 13824, 14336, 14848, 15360, 15872, + 16383 +}; + +/* osd oetf lut: 2084 */ +static unsigned int osd_oetf_41_2084_mapping[OSD_OETF_LUT_SIZE] = { + 0, 21, 43, 64, 79, 90, 101, 111, + 120, 174, 208, 233, 277, 313, 344, 372, + 398, 420, 440, 459, 476, 492, 507, 522, + 536, 549, 561, 574, 585, 596, 606, 616, + 624, 632, 642, 661, 684, 706, 727, 749, + 1023 +}; + +/* sdr eotf lut: 709 */ +static unsigned int eotf_33_sdr_709_mapping[EOTF_LUT_SIZE] = { + 0, 512, 1024, 1536, 2048, 2560, 3072, 3584, + 4096, 4608, 5120, 5632, 6144, 6656, 7168, 7680, + 8192, 8704, 9216, 9728, 10240, 10752, 11264, 11776, + 12288, 12800, 13312, 13824, 14336, 14848, 15360, 15872, + 16383 +}; + +/* sdr oetf lut: 2084 */ +static unsigned int oetf_sdr_2084_mapping[VIDEO_OETF_LUT_SIZE] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 32, 55, 72, 85, 96, 106, 115, + 124, 132, 140, 147, 154, 160, 166, 171, + 176, 181, 186, 190, 194, 198, 204, 208, + 211, 215, 218, 221, 224, 227, 230, 233, + 239, 245, 252, 257, 263, 268, 274, 279, + 283, 288, 292, 296, 302, 306, 310, 315, + 319, 323, 326, 331, 334, 339, 342, 346, + 350, 354, 357, 361, 365, 368, 372, 376, + 379, 382, 386, 389, 392, 396, 399, 402, + 405, 408, 411, 413, 416, 419, 422, 424, + 427, 429, 432, 434, 437, 439, 442, 444, + 446, 449, 451, 454, 456, 459, 461, 463, + 465, 468, 470, 472, 474, 476, 478, 481, + 483, 485, 487, 489, 491, 493, 495, 497, + 499, 501, 503, 505, 507, 509, 511, 513, + 515, 516, 518, 520, 522, 524, 526, 527, + 529, 531, 533, 535, 536, 538, 540, 541, + 543, 545, 546, 548, 550, 551, 553, 555, + 556, 558, 559, 561, 562, 564, 566, 567, + 569, 570, 572, 573, 575, 576, 578, 579, + 580, 582, 584, 585, 586, 588, 589, 591, + 592, 594, 595, 596, 598, 599, 600, 602, + 603, 604, 606, 607, 608, 609, 611, 612, + 613, 615, 616, 617, 618, 619, 620, 621, + 622, 623, 624, 625, 626, 627, 628, 629, + 630, 631, 632, 634, 635, 636, 637, 638, + 640, 641, 642, 644, 646, 648, 651, 654, + 657, 661, 664, 666, 670, 672, 676, 678, + 681, 684, 687, 690, 692, 695, 698, 701, + 704, 706, 709, 712, 715, 718, 720, 723, + 726, 729, 731, 734, 737, 740, 743, 746, + 748, 751, 754, 758, 763, 772, 797, 833, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; + +/* end of array generated from model */ + +module_param(display_scale_factor, uint, 0664); +MODULE_PARM_DESC(display_scale_factor, "\n display scale factor\n"); + +/* video oetf: linear */ +#if 0 +static unsigned int oetf_289_linear_mapping[VIDEO_OETF_LUT_SIZE] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 4, 8, 12, 16, 20, 24, 28, 32, + 36, 40, 44, 48, 52, 56, 60, 64, + 68, 72, 76, 80, 84, 88, 92, 96, + 100, 104, 108, 112, 116, 120, 124, 128, + 132, 136, 140, 144, 148, 152, 156, 160, + 164, 168, 172, 176, 180, 184, 188, 192, + 196, 200, 204, 208, 212, 216, 220, 224, + 228, 232, 236, 240, 244, 248, 252, 256, + 260, 264, 268, 272, 276, 280, 284, 288, + 292, 296, 300, 304, 308, 312, 316, 320, + 324, 328, 332, 336, 340, 344, 348, 352, + 356, 360, 364, 368, 372, 376, 380, 384, + 388, 392, 396, 400, 404, 408, 412, 416, + 420, 424, 428, 432, 436, 440, 444, 448, + 452, 456, 460, 464, 468, 472, 476, 480, + 484, 488, 492, 496, 500, 504, 508, 512, + 516, 520, 524, 528, 532, 536, 540, 544, + 548, 552, 556, 560, 564, 568, 572, 576, + 580, 584, 588, 592, 596, 600, 604, 608, + 612, 616, 620, 624, 628, 632, 636, 640, + 644, 648, 652, 656, 660, 664, 668, 672, + 676, 680, 684, 688, 692, 696, 700, 704, + 708, 712, 716, 720, 724, 728, 732, 736, + 740, 744, 748, 752, 756, 760, 764, 768, + 772, 776, 780, 784, 788, 792, 796, 800, + 804, 808, 812, 816, 820, 824, 828, 832, + 836, 840, 844, 848, 852, 856, 860, 864, + 868, 872, 876, 880, 884, 888, 892, 896, + 900, 904, 908, 912, 916, 920, 924, 928, + 932, 936, 940, 944, 948, 952, 956, 960, + 964, 968, 972, 976, 980, 984, 988, 992, + 996, 1000, 1004, 1008, 1012, 1016, 1020, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; + +/* video oetf: 709 */ +static unsigned int oetf_289_709_mapping[VIDEO_OETF_LUT_SIZE] = { + 0, 2, 4, 6, 8, 10, 12, 14, + 16, 18, 20, 22, 24, 26, 28, 30, + 32, 34, 36, 54, 72, 90, 106, 121, + 135, 148, 160, 172, 183, 193, 203, 213, + 222, 231, 239, 248, 256, 264, 272, 279, + 286, 294, 301, 308, 314, 321, 327, 334, + 340, 346, 352, 358, 364, 370, 376, 381, + 387, 392, 398, 403, 408, 413, 418, 423, + 428, 433, 438, 443, 448, 453, 457, 462, + 467, 471, 476, 480, 484, 489, 493, 497, + 502, 506, 510, 514, 518, 522, 527, 531, + 535, 538, 542, 546, 550, 554, 558, 562, + 565, 569, 573, 577, 580, 584, 587, 591, + 595, 598, 602, 605, 609, 612, 616, 619, + 622, 626, 629, 633, 636, 639, 642, 646, + 649, 652, 655, 659, 662, 665, 668, 671, + 674, 678, 681, 684, 687, 690, 693, 696, + 699, 702, 705, 708, 711, 714, 717, 720, + 722, 725, 728, 731, 734, 737, 740, 742, + 745, 748, 751, 754, 756, 759, 762, 765, + 767, 770, 773, 775, 778, 781, 783, 786, + 789, 791, 794, 797, 799, 802, 804, 807, + 809, 812, 815, 817, 820, 822, 825, 827, + 830, 832, 835, 837, 840, 842, 845, 847, + 849, 852, 854, 857, 859, 861, 864, 866, + 869, 871, 873, 876, 878, 880, 883, 885, + 887, 890, 892, 894, 897, 899, 901, 903, + 906, 908, 910, 912, 915, 917, 919, 921, + 924, 926, 928, 930, 932, 935, 937, 939, + 941, 943, 945, 948, 950, 952, 954, 956, + 958, 960, 963, 965, 967, 969, 971, 973, + 975, 977, 979, 981, 984, 986, 988, 990, + 992, 994, 996, 998, 1000, 1002, 1004, 1006, + 1008, 1010, 1012, 1014, 1016, 1018, 1020, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; +#endif + +#define SIGN(a) ((a < 0) ? "-" : "+") +#define DECI(a) ((a) / 1024) +#define FRAC(a) ((((a) >= 0) ? \ + ((a) & 0x3ff) : ((~(a) + 1) & 0x3ff)) * 10000 / 1024) + +const char matrix_name[7][16] = { + "OSD", + "VD1", + "POST", + "XVYCC", + "EOTF", + "OSD_EOTF", + "VD2" +}; +static void print_vpp_matrix(int m_select, int *s, int on) +{ + unsigned int size; + + if (s == NULL) + return; + if (m_select == VPP_MATRIX_OSD) + size = MATRIX_5x3_COEF_SIZE; + else if (m_select == VPP_MATRIX_POST) + size = MATRIX_5x3_COEF_SIZE; + else if (m_select == VPP_MATRIX_VD1) + size = MATRIX_5x3_COEF_SIZE; + else if (m_select == VPP_MATRIX_VD2) + size = MATRIX_5x3_COEF_SIZE; + else if (m_select == VPP_MATRIX_XVYCC) + size = MATRIX_5x3_COEF_SIZE; + else if (m_select == VPP_MATRIX_EOTF) + size = EOTF_COEFF_SIZE; + else if (m_select == VPP_MATRIX_OSD_EOTF) + size = EOTF_COEFF_SIZE; + else + return; + + pr_csc("%s matrix %s:\n", matrix_name[m_select], + on ? "on" : "off"); + + if (size == MATRIX_5x3_COEF_SIZE) { + pr_csc( + "\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\n", + SIGN(s[0]), DECI(s[0]), FRAC(s[0]), + SIGN(s[3]), DECI(s[3]), FRAC(s[3]), + SIGN(s[4]), DECI(s[4]), FRAC(s[4]), + SIGN(s[5]), DECI(s[5]), FRAC(s[5]), + SIGN(s[18]), DECI(s[18]), FRAC(s[18])); + pr_csc( + "\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\n", + SIGN(s[1]), DECI(s[1]), FRAC(s[1]), + SIGN(s[6]), DECI(s[6]), FRAC(s[6]), + SIGN(s[7]), DECI(s[7]), FRAC(s[7]), + SIGN(s[8]), DECI(s[8]), FRAC(s[8]), + SIGN(s[19]), DECI(s[19]), FRAC(s[19])); + pr_csc( + "\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\n", + SIGN(s[2]), DECI(s[2]), FRAC(s[2]), + SIGN(s[9]), DECI(s[9]), FRAC(s[9]), + SIGN(s[10]), DECI(s[10]), FRAC(s[10]), + SIGN(s[11]), DECI(s[11]), FRAC(s[11]), + SIGN(s[20]), DECI(s[20]), FRAC(s[20])); + if (s[21]) { + pr_csc("\t\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\n", + SIGN(s[12]), DECI(s[12]), FRAC(s[12]), + SIGN(s[13]), DECI(s[13]), FRAC(s[13]), + SIGN(s[14]), DECI(s[14]), FRAC(s[14])); + pr_csc("\t\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\n", + SIGN(s[15]), DECI(s[15]), FRAC(s[15]), + SIGN(s[16]), DECI(s[16]), FRAC(s[16]), + SIGN(s[17]), DECI(s[17]), FRAC(s[17])); + } + if (s[22]) + pr_csc("\tright shift=%d\n", s[22]); + } else { + pr_csc("\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\n", + SIGN(s[0]), DECI(s[0]), FRAC(s[0]), + SIGN(s[1]), DECI(s[1]), FRAC(s[1]), + SIGN(s[2]), DECI(s[2]), FRAC(s[2])); + pr_csc("\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\n", + SIGN(s[3]), DECI(s[3]), FRAC(s[3]), + SIGN(s[4]), DECI(s[4]), FRAC(s[4]), + SIGN(s[5]), DECI(s[5]), FRAC(s[5])); + pr_csc("\t%s%1d.%04d\t%s%1d.%04d\t%s%1d.%04d\n", + SIGN(s[6]), DECI(s[6]), FRAC(s[6]), + SIGN(s[7]), DECI(s[7]), FRAC(s[7]), + SIGN(s[8]), DECI(s[8]), FRAC(s[8])); + if (s[9]) + pr_csc("\tright shift=%d\n", s[9]); + } + pr_csc("\n"); +} + +static int *cur_osd_mtx = RGB709_to_YUV709l_coeff; +void set_vpp_matrix(int m_select, int *s, int on) +{ + int *m = NULL; + int size = 0; + int i; + + if (debug_csc) + print_vpp_matrix(m_select, s, on); + if (m_select == VPP_MATRIX_OSD) { + m = osd_matrix_coeff; + size = MATRIX_5x3_COEF_SIZE; + cur_osd_mtx = s; + } else if (m_select == VPP_MATRIX_POST) { + m = post_matrix_coeff; + size = MATRIX_5x3_COEF_SIZE; + } else if (m_select == VPP_MATRIX_VD1) { + m = vd1_matrix_coeff; + size = MATRIX_5x3_COEF_SIZE; + } else if (m_select == VPP_MATRIX_VD2) { + m = vd2_matrix_coeff; + size = MATRIX_5x3_COEF_SIZE; + } else if (m_select == VPP_MATRIX_XVYCC) { + m = xvycc_matrix_coeff; + size = MATRIX_5x3_COEF_SIZE; + } else if (m_select == VPP_MATRIX_EOTF) { + m = video_eotf_coeff; + size = EOTF_COEFF_SIZE; + } else if (m_select == VPP_MATRIX_OSD_EOTF) { + m = osd_eotf_coeff; + size = EOTF_COEFF_SIZE; + } else + return; + + if (s) + for (i = 0; i < size; i++) + m[i] = s[i]; + else + reload_mtx &= ~(1 << m_select); + + if (m_select == VPP_MATRIX_OSD) { + /* osd matrix, VPP_MATRIX_0 */ + /* not enable latched */ + hdr_osd_reg.viu_osd1_matrix_pre_offset0_1 = + ((m[0] & 0xfff) << 16) | (m[1] & 0xfff); + hdr_osd_reg.viu_osd1_matrix_pre_offset2 = + m[2] & 0xfff; + hdr_osd_reg.viu_osd1_matrix_coef00_01 = + ((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff); + hdr_osd_reg.viu_osd1_matrix_coef02_10 = + ((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff); + hdr_osd_reg.viu_osd1_matrix_coef11_12 = + ((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff); + hdr_osd_reg.viu_osd1_matrix_coef20_21 = + ((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff); + if (m[21]) { + hdr_osd_reg.viu_osd1_matrix_coef22_30 = + ((m[11] & 0x1fff) << 16) | (m[12] & 0x1fff); + hdr_osd_reg.viu_osd1_matrix_coef31_32 = + ((m[13] & 0x1fff) << 16) | (m[14] & 0x1fff); + hdr_osd_reg.viu_osd1_matrix_coef40_41 = + ((m[15] & 0x1fff) << 16) | (m[16] & 0x1fff); + hdr_osd_reg.viu_osd1_matrix_colmod_coef42 = + m[17] & 0x1fff; + } else { + hdr_osd_reg.viu_osd1_matrix_coef22_30 = + (m[11] & 0x1fff) << 16; + } + hdr_osd_reg.viu_osd1_matrix_offset0_1 = + ((m[18] & 0xfff) << 16) | (m[19] & 0xfff); + hdr_osd_reg.viu_osd1_matrix_offset2 = + m[20] & 0xfff; + + hdr_osd_reg.viu_osd1_matrix_colmod_coef42 &= 0x3ff8ffff; + hdr_osd_reg.viu_osd1_matrix_colmod_coef42 |= + (m[21] << 30) | (m[22] << 16); + + /* 23 reserved for clipping control */ + hdr_osd_reg.viu_osd1_matrix_ctrl &= 0xfffffffc; + hdr_osd_reg.viu_osd1_matrix_ctrl |= on; + } else if (m_select == VPP_MATRIX_EOTF) { + /* eotf matrix, VPP_MATRIX_EOTF */ + /* enable latched */ + for (i = 0; i < 5; i++) + VSYNC_WR_MPEG_REG(VIU_EOTF_CTL + i + 1, + ((m[i * 2] & 0x1fff) << 16) + | (m[i * 2 + 1] & 0x1fff)); + WRITE_VPP_REG_BITS(VIU_EOTF_CTL, on, 30, 1); + WRITE_VPP_REG_BITS(VIU_EOTF_CTL, on, 31, 1); + } else if (m_select == VPP_MATRIX_OSD_EOTF) { + /* osd eotf matrix, VPP_MATRIX_OSD_EOTF */ + /* enable latched */ + hdr_osd_reg.viu_osd1_eotf_coef00_01 = + ((m[0 * 2] & 0x1fff) << 16) + | (m[0 * 2 + 1] & 0x1fff); + + hdr_osd_reg.viu_osd1_eotf_coef02_10 = + ((m[1 * 2] & 0x1fff) << 16) + | (m[1 * 2 + 1] & 0x1fff); + + hdr_osd_reg.viu_osd1_eotf_coef11_12 = + ((m[2 * 2] & 0x1fff) << 16) + | (m[2 * 2 + 1] & 0x1fff); + + hdr_osd_reg.viu_osd1_eotf_coef20_21 = + ((m[3 * 2] & 0x1fff) << 16) + | (m[3 * 2 + 1] & 0x1fff); + hdr_osd_reg.viu_osd1_eotf_coef22_rs = + ((m[4 * 2] & 0x1fff) << 16) + | (m[4 * 2 + 1] & 0x1fff); + + hdr_osd_reg.viu_osd1_eotf_ctl &= 0x3fffffff; + hdr_osd_reg.viu_osd1_eotf_ctl |= (on << 30) | (on << 31); + } else { + /* vd1 matrix, VPP_MATRIX_1 */ + /* post matrix, VPP_MATRIX_2 */ + /* xvycc matrix, VPP_MATRIX_3 */ + /* vd2 matrix, VPP_MATRIX_6 */ + if (m_select == VPP_MATRIX_POST) { + /* post matrix */ + m = post_matrix_coeff; + /* set bit for enable latched */ + WRITE_VPP_REG_BITS(VPP_XVYCC_MISC, 1, 14, 1); + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 0, 1); + if (on) { + if (rdma_flag & (1 << m_select)) + VSYNC_WR_MPEG_REG_BITS( + VPP_MATRIX_CTRL, 0, 8, 2); + else + WRITE_VPP_REG_BITS( + VPP_MATRIX_CTRL, 0, 8, 2); + } + } else if (m_select == VPP_MATRIX_VD1) { + /* vd1 matrix, latched */ + m = vd1_matrix_coeff; + /* set bit for enable latched */ + WRITE_VPP_REG_BITS(VPP_XVYCC_MISC, 1, 9, 1); + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 5, 1); + if (on) { + if (rdma_flag & (1 << m_select)) + VSYNC_WR_MPEG_REG_BITS( + VPP_MATRIX_CTRL, 1, 8, 2); + else + WRITE_VPP_REG_BITS( + VPP_MATRIX_CTRL, 1, 8, 2); + } + } else if (m_select == VPP_MATRIX_VD2) { + /* vd2 matrix, not latched */ + m = vd2_matrix_coeff; + if (rdma_flag & (1 << m_select)) + VSYNC_WR_MPEG_REG_BITS( + VPP_MATRIX_CTRL, on, 4, 1); + else + WRITE_VPP_REG_BITS( + VPP_MATRIX_CTRL, on, 4, 1); + if (on) { + if (rdma_flag & (1 << m_select)) + VSYNC_WR_MPEG_REG_BITS( + VPP_MATRIX_CTRL, 2, 8, 2); + else + WRITE_VPP_REG_BITS( + VPP_MATRIX_CTRL, 2, 8, 2); + } + } else if (m_select == VPP_MATRIX_XVYCC) { + /* xvycc matrix, not latched */ + m = xvycc_matrix_coeff; + if (rdma_flag & (1 << m_select)) + VSYNC_WR_MPEG_REG_BITS( + VPP_MATRIX_CTRL, on, 6, 1); + else + WRITE_VPP_REG_BITS( + VPP_MATRIX_CTRL, on, 6, 1); + if (on) { + if (rdma_flag & (1 << m_select)) + VSYNC_WR_MPEG_REG_BITS( + VPP_MATRIX_CTRL, 3, 8, 2); + else + WRITE_VPP_REG_BITS( + VPP_MATRIX_CTRL, 3, 8, 2); + } + } + if (on) { + if (rdma_flag & (1 << m_select)) { + VSYNC_WR_MPEG_REG(VPP_MATRIX_PRE_OFFSET0_1, + ((m[0] & 0xfff) << 16) + | (m[1] & 0xfff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_PRE_OFFSET2, + m[2] & 0xfff); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF00_01, + ((m[3] & 0x1fff) << 16) + | (m[4] & 0x1fff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF02_10, + ((m[5] & 0x1fff) << 16) + | (m[6] & 0x1fff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF11_12, + ((m[7] & 0x1fff) << 16) + | (m[8] & 0x1fff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF20_21, + ((m[9] & 0x1fff) << 16) + | (m[10] & 0x1fff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF22, + m[11] & 0x1fff); + if (m[21]) { + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF13_14, + ((m[12] & 0x1fff) << 16) + | (m[13] & 0x1fff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF15_25, + ((m[14] & 0x1fff) << 16) + | (m[17] & 0x1fff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF23_24, + ((m[15] & 0x1fff) << 16) + | (m[16] & 0x1fff)); + } + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET0_1, + ((m[18] & 0xfff) << 16) + | (m[19] & 0xfff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET2, + m[20] & 0xfff); + VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CLIP, + m[21], 3, 2); + VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CLIP, + m[22], 5, 3); + } else { + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, + ((m[0] & 0xfff) << 16) + | (m[1] & 0xfff)); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, + m[2] & 0xfff); + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, + ((m[3] & 0x1fff) << 16) + | (m[4] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, + ((m[5] & 0x1fff) << 16) + | (m[6] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, + ((m[7] & 0x1fff) << 16) + | (m[8] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, + ((m[9] & 0x1fff) << 16) + | (m[10] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF22, + m[11] & 0x1fff); + if (m[21]) { + WRITE_VPP_REG(VPP_MATRIX_COEF13_14, + ((m[12] & 0x1fff) << 16) + | (m[13] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF15_25, + ((m[14] & 0x1fff) << 16) + | (m[17] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF23_24, + ((m[15] & 0x1fff) << 16) + | (m[16] & 0x1fff)); + } + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, + ((m[18] & 0xfff) << 16) + | (m[19] & 0xfff)); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, + m[20] & 0xfff); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, + m[21], 3, 2); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, + m[22], 5, 3); + } + } + } +} + +void enable_osd_path(int on) +{ + static int *osd1_mtx_backup; + static uint32_t osd1_eotf_ctl_backup; + static uint32_t osd1_oetf_ctl_backup; + + if (!on) { + osd1_mtx_backup = cur_osd_mtx; + osd1_eotf_ctl_backup = hdr_osd_reg.viu_osd1_eotf_ctl; + osd1_oetf_ctl_backup = hdr_osd_reg.viu_osd1_oetf_ctl; + + set_vpp_matrix(VPP_MATRIX_OSD, bypass_coeff, CSC_ON); + hdr_osd_reg.viu_osd1_eotf_ctl &= 0x07ffffff; + hdr_osd_reg.viu_osd1_oetf_ctl &= 0x1fffffff; + } else { + set_vpp_matrix(VPP_MATRIX_OSD, osd1_mtx_backup, CSC_ON); + hdr_osd_reg.viu_osd1_eotf_ctl = osd1_eotf_ctl_backup; + hdr_osd_reg.viu_osd1_eotf_ctl = osd1_oetf_ctl_backup; + } +} +EXPORT_SYMBOL(enable_osd_path); + +const char lut_name[NUM_LUT][16] = { + "OSD_EOTF", + "OSD_OETF", + "EOTF", + "OETF", + "INV_EOTF" +}; +/* VIDEO_OETF_LUT_SIZE 289 >*/ +/* OSD_OETF_LUT_SIZE 41 >*/ +/* OSD_OETF_LUT_SIZE 33 */ +static void print_vpp_lut( + enum vpp_lut_sel_e lut_sel, + int on) +{ + unsigned short r_map[VIDEO_OETF_LUT_SIZE]; + unsigned short g_map[VIDEO_OETF_LUT_SIZE]; + unsigned short b_map[VIDEO_OETF_LUT_SIZE]; + unsigned int addr_port; + unsigned int data_port; + unsigned int ctrl_port; + unsigned int data; + int i; + + if (lut_sel == VPP_LUT_OSD_EOTF) { + addr_port = VIU_OSD1_EOTF_LUT_ADDR_PORT; + data_port = VIU_OSD1_EOTF_LUT_DATA_PORT; + ctrl_port = VIU_OSD1_EOTF_CTL; + return; + } else if (lut_sel == VPP_LUT_EOTF) { + addr_port = VIU_EOTF_LUT_ADDR_PORT; + data_port = VIU_EOTF_LUT_DATA_PORT; + ctrl_port = VIU_EOTF_CTL; + } else if (lut_sel == VPP_LUT_OSD_OETF) { + addr_port = VIU_OSD1_OETF_LUT_ADDR_PORT; + data_port = VIU_OSD1_OETF_LUT_DATA_PORT; + ctrl_port = VIU_OSD1_OETF_CTL; + return; + } else if (lut_sel == VPP_LUT_OETF) { + addr_port = XVYCC_LUT_R_ADDR_PORT; + data_port = XVYCC_LUT_R_DATA_PORT; + ctrl_port = XVYCC_LUT_CTL; + } else if (lut_sel == VPP_LUT_INV_EOTF) { + addr_port = XVYCC_INV_LUT_Y_ADDR_PORT; + data_port = XVYCC_INV_LUT_Y_DATA_PORT; + ctrl_port = XVYCC_INV_LUT_CTL; + } else + return; + if (lut_sel == VPP_LUT_OSD_OETF) { + for (i = 0; i < 20; i++) { + WRITE_VPP_REG(addr_port, i); + data = READ_VPP_REG(data_port); + r_map[i * 2] = data & 0xffff; + r_map[i * 2 + 1] = (data >> 16) & 0xffff; + } + WRITE_VPP_REG(addr_port, 20); + data = READ_VPP_REG(data_port); + r_map[OSD_OETF_LUT_SIZE - 1] = data & 0xffff; + g_map[0] = (data >> 16) & 0xffff; + for (i = 0; i < 20; i++) { + WRITE_VPP_REG(addr_port, 21 + i); + data = READ_VPP_REG(data_port); + g_map[i * 2 + 1] = data & 0xffff; + g_map[i * 2 + 2] = (data >> 16) & 0xffff; + } + for (i = 0; i < 20; i++) { + WRITE_VPP_REG(addr_port, 41 + i); + data = READ_VPP_REG(data_port); + b_map[i * 2] = data & 0xffff; + b_map[i * 2 + 1] = (data >> 16) & 0xffff; + } + WRITE_VPP_REG(addr_port, 61); + data = READ_VPP_REG(data_port); + b_map[OSD_OETF_LUT_SIZE - 1] = data & 0xffff; + pr_csc("%s lut %s:\n", lut_name[lut_sel], on ? "on" : "off"); + for (i = 0; i < OSD_OETF_LUT_SIZE; i++) { + pr_csc("\t[%d] = 0x%04x 0x%04x 0x%04x\n", + i, r_map[i], g_map[i], b_map[i]); + } + pr_csc("\n"); + } else if (lut_sel == VPP_LUT_OSD_EOTF) { + WRITE_VPP_REG(addr_port, 0); + for (i = 0; i < 16; i++) { + data = READ_VPP_REG(data_port); + r_map[i * 2] = data & 0xffff; + r_map[i * 2 + 1] = (data >> 16) & 0xffff; + } + data = READ_VPP_REG(data_port); + r_map[EOTF_LUT_SIZE - 1] = data & 0xffff; + g_map[0] = (data >> 16) & 0xffff; + for (i = 0; i < 16; i++) { + data = READ_VPP_REG(data_port); + g_map[i * 2 + 1] = data & 0xffff; + g_map[i * 2 + 2] = (data >> 16) & 0xffff; + } + for (i = 0; i < 16; i++) { + data = READ_VPP_REG(data_port); + b_map[i * 2] = data & 0xffff; + b_map[i * 2 + 1] = (data >> 16) & 0xffff; + } + data = READ_VPP_REG(data_port); + b_map[EOTF_LUT_SIZE - 1] = data & 0xffff; + pr_csc("%s lut %s:\n", lut_name[lut_sel], on ? "on" : "off"); + for (i = 0; i < EOTF_LUT_SIZE; i++) { + pr_csc("\t[%d] = 0x%04x 0x%04x 0x%04x\n", + i, r_map[i], g_map[i], b_map[i]); + } + pr_csc("\n"); + } else if (lut_sel == VPP_LUT_EOTF) { + WRITE_VPP_REG(addr_port, 0); + for (i = 0; i < 16; i++) { + data = READ_VPP_REG(data_port); + r_map[i * 2] = data & 0xffff; + r_map[i * 2 + 1] = (data >> 16) & 0xffff; + } + data = READ_VPP_REG(data_port); + r_map[EOTF_LUT_SIZE - 1] = data & 0xffff; + g_map[0] = (data >> 16) & 0xffff; + for (i = 0; i < 16; i++) { + data = READ_VPP_REG(data_port); + g_map[i * 2 + 1] = data & 0xffff; + g_map[i * 2 + 2] = (data >> 16) & 0xffff; + } + for (i = 0; i < 16; i++) { + data = READ_VPP_REG(data_port); + b_map[i * 2] = data & 0xffff; + b_map[i * 2 + 1] = (data >> 16) & 0xffff; + } + data = READ_VPP_REG(data_port); + b_map[EOTF_LUT_SIZE - 1] = data & 0xffff; + pr_csc("%s lut %s:\n", lut_name[lut_sel], on ? "on" : "off"); + for (i = 0; i < EOTF_LUT_SIZE; i++) { + pr_csc("\t[%d] = 0x%04x 0x%04x 0x%04x\n", + i, r_map[i], g_map[i], b_map[i]); + } + pr_csc("\n"); + } else if (lut_sel == VPP_LUT_OETF) { + WRITE_VPP_REG(ctrl_port, 0x0); + WRITE_VPP_REG(addr_port, 0); + for (i = 0; i < VIDEO_OETF_LUT_SIZE; i++) + r_map[i] = READ_VPP_REG(data_port) & 0x3ff; + WRITE_VPP_REG(addr_port + 2, 0); + for (i = 0; i < VIDEO_OETF_LUT_SIZE; i++) + g_map[i] = READ_VPP_REG(data_port + 2) & 0x3ff; + WRITE_VPP_REG(addr_port + 4, 0); + for (i = 0; i < VIDEO_OETF_LUT_SIZE; i++) + b_map[i] = READ_VPP_REG(data_port + 4) & 0x3ff; + pr_csc("%s lut %s:\n", lut_name[lut_sel], on ? "on" : "off"); + for (i = 0; i < VIDEO_OETF_LUT_SIZE; i++) { + pr_csc("\t[%d] = 0x%04x 0x%04x 0x%04x\n", + i, r_map[i], g_map[i], b_map[i]); + } + pr_csc("\n"); + if (on) + WRITE_VPP_REG(ctrl_port, 0x7f); + } else if (lut_sel == VPP_LUT_INV_EOTF) { + WRITE_VPP_REG_BITS(ctrl_port, 0, 12, 3); + pr_csc("%s lut %s:\n", lut_name[lut_sel], on ? "on" : "off"); + for (i = 0; + i < EOTF_INV_LUT_NEG2048_SIZE + + EOTF_INV_LUT_SIZE + EOTF_INV_LUT_1024_SIZE; + i++) { + WRITE_VPP_REG(addr_port, i); + data = READ_VPP_REG(data_port) & 0xfff; + if (data & 0x800) + pr_csc("\t[%d] = %d\n", + i, -(~(data|0xfffff000) + 1)); + else + pr_csc("\t[%d] = %d\n", i, data); + } + pr_csc("\n"); + if (on) + WRITE_VPP_REG_BITS(ctrl_port, 1<<2, 12, 3); + } +} + +void set_vpp_lut( + enum vpp_lut_sel_e lut_sel, + unsigned int *r, + unsigned int *g, + unsigned int *b, + int on) +{ + unsigned int *r_map = NULL; + unsigned int *g_map = NULL; + unsigned int *b_map = NULL; + unsigned int addr_port; + unsigned int data_port; + unsigned int ctrl_port; + int i; + + if (reload_lut & (1 << lut_sel)) + reload_lut &= ~(1 << lut_sel); + if (lut_sel == VPP_LUT_OSD_EOTF) { + r_map = osd_eotf_r_mapping; + g_map = osd_eotf_g_mapping; + b_map = osd_eotf_b_mapping; + addr_port = VIU_OSD1_EOTF_LUT_ADDR_PORT; + data_port = VIU_OSD1_EOTF_LUT_DATA_PORT; + ctrl_port = VIU_OSD1_EOTF_CTL; + } else if (lut_sel == VPP_LUT_EOTF) { + r_map = video_eotf_r_mapping; + g_map = video_eotf_g_mapping; + b_map = video_eotf_b_mapping; + addr_port = VIU_EOTF_LUT_ADDR_PORT; + data_port = VIU_EOTF_LUT_DATA_PORT; + ctrl_port = VIU_EOTF_CTL; + } else if (lut_sel == VPP_LUT_OSD_OETF) { + r_map = osd_oetf_r_mapping; + g_map = osd_oetf_g_mapping; + b_map = osd_oetf_b_mapping; + addr_port = VIU_OSD1_OETF_LUT_ADDR_PORT; + data_port = VIU_OSD1_OETF_LUT_DATA_PORT; + ctrl_port = VIU_OSD1_OETF_CTL; + } else if (lut_sel == VPP_LUT_OETF) { +#if 0 + load_knee_lut(on); + return; +#else + r_map = video_oetf_r_mapping; + g_map = video_oetf_g_mapping; + b_map = video_oetf_b_mapping; + addr_port = XVYCC_LUT_R_ADDR_PORT; + data_port = XVYCC_LUT_R_DATA_PORT; + ctrl_port = XVYCC_LUT_CTL; +#endif + } else if (lut_sel == VPP_LUT_INV_EOTF) { + addr_port = XVYCC_INV_LUT_Y_ADDR_PORT; + data_port = XVYCC_INV_LUT_Y_DATA_PORT; + ctrl_port = XVYCC_INV_LUT_CTL; + } else + return; + + if (lut_sel == VPP_LUT_OSD_OETF) { + /* enable latched */ + if (r && r_map) + for (i = 0; i < OSD_OETF_LUT_SIZE; i++) + r_map[i] = r[i]; + if (g && g_map) + for (i = 0; i < OSD_OETF_LUT_SIZE; i++) + g_map[i] = g[i]; + if (r && r_map) + for (i = 0; i < OSD_OETF_LUT_SIZE; i++) + b_map[i] = b[i]; + + for (i = 0; i < OSD_OETF_LUT_SIZE; i++) { + hdr_osd_reg.lut_val.or_map[i] = r_map[i]; + hdr_osd_reg.lut_val.og_map[i] = g_map[i]; + hdr_osd_reg.lut_val.ob_map[i] = b_map[i]; + } + hdr_osd_reg.viu_osd1_oetf_ctl &= 0x1fffffff; + hdr_osd_reg.viu_osd1_oetf_ctl |= 7 << 22; + if (on) + hdr_osd_reg.viu_osd1_oetf_ctl |= 7 << 29; + } else if (lut_sel == VPP_LUT_OSD_EOTF) { + /* enable latched */ + if (r && r_map) + for (i = 0; i < EOTF_LUT_SIZE; i++) + r_map[i] = r[i]; + if (g && g_map) + for (i = 0; i < EOTF_LUT_SIZE; i++) + g_map[i] = g[i]; + if (r && r_map) + for (i = 0; i < EOTF_LUT_SIZE; i++) + b_map[i] = b[i]; + + for (i = 0; i < EOTF_LUT_SIZE; i++) { + hdr_osd_reg.lut_val.r_map[i] = r_map[i]; + hdr_osd_reg.lut_val.g_map[i] = g_map[i]; + hdr_osd_reg.lut_val.b_map[i] = b_map[i]; + } + hdr_osd_reg.viu_osd1_eotf_ctl &= 0xc7ffffff; + if (on) + hdr_osd_reg.viu_osd1_eotf_ctl |= 7 << 27; + hdr_osd_reg.viu_osd1_eotf_ctl |= 1 << 31; + } else if (lut_sel == VPP_LUT_EOTF) { + /* enable latched */ + if (r && r_map) + for (i = 0; i < EOTF_LUT_SIZE; i++) + r_map[i] = r[i]; + if (g && g_map) + for (i = 0; i < EOTF_LUT_SIZE; i++) + g_map[i] = g[i]; + if (r && r_map) + for (i = 0; i < EOTF_LUT_SIZE; i++) + b_map[i] = b[i]; + if (on) { + for (i = 0; i < 16; i++) { + VSYNC_WR_MPEG_REG(addr_port, i); + VSYNC_WR_MPEG_REG(data_port, + r_map[i * 2] + | (r_map[i * 2 + 1] << 16)); + } + VSYNC_WR_MPEG_REG(addr_port, 16); + VSYNC_WR_MPEG_REG(data_port, + r_map[EOTF_LUT_SIZE - 1] + | (g_map[0] << 16)); + for (i = 0; i < 16; i++) { + VSYNC_WR_MPEG_REG(addr_port, i + 17); + VSYNC_WR_MPEG_REG(data_port, + g_map[i * 2 + 1] + | (g_map[i * 2 + 2] << 16)); + } + for (i = 0; i < 16; i++) { + VSYNC_WR_MPEG_REG(addr_port, i + 33); + VSYNC_WR_MPEG_REG(data_port, + b_map[i * 2] + | (b_map[i * 2 + 1] << 16)); + } + VSYNC_WR_MPEG_REG(addr_port, 49); + VSYNC_WR_MPEG_REG(data_port, b_map[EOTF_LUT_SIZE - 1]); + WRITE_VPP_REG_BITS(ctrl_port, 7, 27, 3); + } else + WRITE_VPP_REG_BITS(ctrl_port, 0, 27, 3); + WRITE_VPP_REG_BITS(ctrl_port, 1, 31, 1); + } else if (lut_sel == VPP_LUT_OETF) { + /* set bit to disable latched */ + WRITE_VPP_REG_BITS(VPP_XVYCC_MISC, 0, 18, 3); + if (r && r_map) + for (i = 0; i < VIDEO_OETF_LUT_SIZE; i++) + r_map[i] = r[i]; + if (g && g_map) + for (i = 0; i < VIDEO_OETF_LUT_SIZE; i++) + g_map[i] = g[i]; + if (r && r_map) + for (i = 0; i < VIDEO_OETF_LUT_SIZE; i++) + b_map[i] = b[i]; + if (on) { + VSYNC_WR_MPEG_REG(ctrl_port, 0x0f); + for (i = 0; i < VIDEO_OETF_LUT_SIZE; i++) { + VSYNC_WR_MPEG_REG(addr_port, i); + VSYNC_WR_MPEG_REG(data_port, r_map[i]); + } + for (i = 0; i < VIDEO_OETF_LUT_SIZE; i++) { + VSYNC_WR_MPEG_REG(addr_port + 2, i); + VSYNC_WR_MPEG_REG(data_port + 2, g_map[i]); + } + for (i = 0; i < VIDEO_OETF_LUT_SIZE; i++) { + VSYNC_WR_MPEG_REG(addr_port + 4, i); + VSYNC_WR_MPEG_REG(data_port + 4, b_map[i]); + } + VSYNC_WR_MPEG_REG(ctrl_port, 0x7f); + knee_lut_on = 1; + } else { + VSYNC_WR_MPEG_REG(ctrl_port, 0x0f); + knee_lut_on = 0; + } + cur_knee_factor = knee_factor; + } else if (lut_sel == VPP_LUT_INV_EOTF) { + /* set bit to enable latched */ + WRITE_VPP_REG_BITS(VPP_XVYCC_MISC, 0x7, 4, 3); + if (on) { + VSYNC_WR_MPEG_REG(addr_port, 0); + for (i = 0; i < EOTF_INV_LUT_NEG2048_SIZE; i++) { + VSYNC_WR_MPEG_REG(addr_port, i); + VSYNC_WR_MPEG_REG(data_port, invlut_y_neg[i]); + } + for (i = 0; i < EOTF_INV_LUT_SIZE; i++) { + VSYNC_WR_MPEG_REG(addr_port, + EOTF_INV_LUT_NEG2048_SIZE + i); + VSYNC_WR_MPEG_REG(data_port, invlut_y[i]); + } + for (i = 0; i < EOTF_INV_LUT_1024_SIZE; i++) { + VSYNC_WR_MPEG_REG(addr_port, + EOTF_INV_LUT_NEG2048_SIZE + + EOTF_INV_LUT_SIZE + i); + VSYNC_WR_MPEG_REG(data_port, invlut_y_1024[i]); + } + WRITE_VPP_REG_BITS(ctrl_port, 1<<2, 12, 3); + } else + WRITE_VPP_REG_BITS(ctrl_port, 0, 12, 3); + } + if (debug_csc) + print_vpp_lut(lut_sel, on); +} + +/***************************** end of gxl hdr **************************/ + +/* extern unsigned int cm_size; */ +/* extern unsigned int ve_size; */ +/* extern unsigned int cm2_patch_flag; */ +/* extern struct ve_dnlp_s am_ve_dnlp; */ +/* extern struct ve_dnlp_table_s am_ve_new_dnlp; */ +/* extern int cm_en; //0:disabel;1:enable */ +/* extern struct tcon_gamma_table_s video_gamma_table_r; */ +/* extern struct tcon_gamma_table_s video_gamma_table_g; */ +/* extern struct tcon_gamma_table_s video_gamma_table_b; */ +/* extern struct tcon_gamma_table_s video_gamma_table_r_adj; */ +/* extern struct tcon_gamma_table_s video_gamma_table_g_adj; */ +/* extern struct tcon_gamma_table_s video_gamma_table_b_adj; */ +/* extern struct tcon_rgb_ogo_s video_rgb_ogo; */ + +/* csc mode:*/ +/* 0: 601 limit to RGB*/ +/* vd1 for ycbcr to rgb*/ +/* 1: 601 full to RGB*/ +/* vd1 for ycbcr to rgb*/ +/* 2: 709 limit to RGB*/ +/* vd1 for ycbcr to rgb*/ +/* 3: 709 full to RGB*/ +/* vd1 for ycbcr to rgb*/ +/* 4: 2020 limit to RGB*/ +/* vd1 for ycbcr to rgb*/ +/* post for rgb to r'g'b'*/ +/* 5: 2020(G:33c2,86c4 B:1d4c,0bb8 R:84d0,3e80) limit to RGB*/ +/* vd1 for ycbcr to rgb*/ +/* post for rgb to r'g'b'*/ +/* 6: customer matrix calculation according to src and dest primary*/ +/* vd1 for ycbcr to rgb*/ +/* post for rgb to r'g'b' */ +static void vpp_set_matrix( + enum vpp_matrix_sel_e vd1_or_vd2_or_post, + unsigned int on, + enum vpp_matrix_csc_e csc_mode, + struct matrix_s *m) +{ + if (force_csc_type != 0xff) + csc_mode = force_csc_type; + + if (vd1_or_vd2_or_post == VPP_MATRIX_VD1) { + /* vd1 matrix */ + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 5, 1); + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 1, 8, 2); + } else if (vd1_or_vd2_or_post == VPP_MATRIX_VD2) { + /* vd2 matrix */ + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 4, 1); + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 2, 8, 2); + } else { + /* post matrix */ + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 0, 1); + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 0, 8, 2); + /* saturation enable for 601 & 709 limited input */ + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 0, 1, 2); + } + if (!on) + return; + + if (csc_mode == VPP_MATRIX_YUV601_RGB) { + /* ycbcr limit, 601 to RGB */ + /* -16 1.164 0 1.596 0*/ + /* -128 1.164 -0.392 -0.813 0*/ + /* -128 1.164 2.017 0 0 */ + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x04A80000); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x066204A8); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1e701cbf); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x04A80812); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x00000000); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x00000000); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x00000000); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + } else if (csc_mode == VPP_MATRIX_YUV601F_RGB) { + /* ycbcr full range, 601F to RGB */ + /* 0 1 0 1.402 0*/ + /* -128 1 -0.34414 -0.71414 0*/ + /* -128 1 1.772 0 0 */ + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, (0x400 << 16) | 0); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, (0x59c << 16) | 0x400); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, (0x1ea0 << 16) | 0x1d24); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, (0x400 << 16) | 0x718); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + } else if (csc_mode == VPP_MATRIX_YUV709_RGB) { + /* ycbcr limit range, 709 to RGB */ + /* -16 1.164 0 1.793 0 */ + /* -128 1.164 -0.213 -0.534 0 */ + /* -128 1.164 2.115 0 0 */ + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x04A80000); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x072C04A8); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1F261DDD); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x04A80876); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); + + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + } else if (csc_mode == VPP_MATRIX_YUV709F_RGB) { + /* ycbcr full range, 709F to RGB */ + /* 0 1 0 1.575 0*/ + /* -128 1 -0.187 -0.468 0*/ + /* -128 1 1.856 0 0 */ + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x04000000); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x064D0400); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1F411E21); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x0400076D); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + } else if (csc_mode == VPP_MATRIX_NULL) { + /* bypass matrix */ + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x04000000); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x04000000); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x00000000); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x00000400); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + } else if (csc_mode >= VPP_MATRIX_BT2020YUV_BT2020RGB) { + if (vd1_or_vd2_or_post == VPP_MATRIX_VD1) { + /* bt2020 limit to bt2020 RGB */ + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x4ad0000); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x6e50492); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1f3f1d63); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x492089a); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + } + if (vd1_or_vd2_or_post == VPP_MATRIX_POST) { + if (csc_mode == VPP_MATRIX_BT2020YUV_BT2020RGB) { + /* 2020 RGB to R'G'B */ + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, 0x0); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, 0x0); + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0xd491b4d); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x1f6b1f01); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x9101fef); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x1fdb1f32); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x108f3); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 1, 5, 3); + } else if (csc_mode == VPP_MATRIX_BT2020RGB_CUSRGB) { + /* customer matrix 2020 RGB to R'G'B' */ + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, + (m->pre_offset[0] << 16) + | (m->pre_offset[1] & 0xffff)); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, + m->pre_offset[2] & 0xffff); + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, + (m->matrix[0][0] << 16) + | (m->matrix[0][1] & 0xffff)); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, + (m->matrix[0][2] << 16) + | (m->matrix[1][0] & 0xffff)); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, + (m->matrix[1][1] << 16) + | (m->matrix[1][2] & 0xffff)); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, + (m->matrix[2][0] << 16) + | (m->matrix[2][1] & 0xffff)); + WRITE_VPP_REG(VPP_MATRIX_COEF22, + (m->right_shift << 16) + | (m->matrix[2][2] & 0xffff)); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, + (m->offset[0] << 16) + | (m->offset[1] & 0xffff)); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, + m->offset[2] & 0xffff); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, + m->right_shift, 5, 3); + } + } + } +} + +/* matrix betreen xvycclut and linebuffer*/ +static uint cur_csc_mode = 0xff; +static void vpp_set_matrix3( + unsigned int on, + enum vpp_matrix_csc_e csc_mode) +{ + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 6, 1); + if (!on) + return; + + if (cur_csc_mode == csc_mode) + return; + + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 3, 8, 2); + if (csc_mode == VPP_MATRIX_RGB_YUV709F) { + /* RGB -> 709F*/ + /*WRITE_VPP_REG(VPP_MATRIX_CTRL, 0x7360);*/ + + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0xda02dc); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x4a1f8a); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1e760200); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x2001e2f); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x1fd1); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x200); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x200); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, 0x0); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, 0x0); + } else if (csc_mode == VPP_MATRIX_RGB_YUV709) { + /* RGB -> 709 limit */ + /*WRITE_VPP_REG(VPP_MATRIX_CTRL, 0x7360);*/ + + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x00bb0275); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x003f1f99); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1ea601c2); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x01c21e67); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x00001fd7); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x00400200); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x00000200); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, 0x0); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, 0x0); + } + cur_csc_mode = csc_mode; +} + +static uint cur_signal_type = 0xffffffff; +module_param(cur_signal_type, uint, 0664); +MODULE_PARM_DESC(cur_signal_type, "\n cur_signal_type\n"); + +static struct vframe_master_display_colour_s cur_master_display_colour = { + 0, + { + {0, 0}, + {0, 0}, + {0, 0}, + }, + {0, 0}, + {0, 0} +}; + +#define SIG_CS_CHG 0x01 +#define SIG_SRC_CHG 0x02 +#define SIG_PRI_INFO 0x04 +#define SIG_KNEE_FACTOR 0x08 +#define SIG_HDR_MODE 0x10 +#define SIG_HDR_SUPPORT 0x20 +#define SIG_WB_CHG 0x40 + +int signal_type_changed(struct vframe_s *vf, struct vinfo_s *vinfo) +{ + u32 signal_type = 0; + u32 default_signal_type; + int change_flag = 0; + int i, j; + struct vframe_master_display_colour_s *p_cur; + struct vframe_master_display_colour_s *p_new; + struct vframe_master_display_colour_s cus; + + if ((vf->source_type == VFRAME_SOURCE_TYPE_TUNER) || + (vf->source_type == VFRAME_SOURCE_TYPE_CVBS) || + (vf->source_type == VFRAME_SOURCE_TYPE_COMP) || + (vf->source_type == VFRAME_SOURCE_TYPE_HDMI)) { + if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB) + default_signal_type = + /* default 709 full */ + (1 << 29) /* video available */ + | (5 << 26) /* unspecified */ + | (1 << 25) /* limit */ + | (1 << 24) /* color available */ + | (1 << 16) /* bt709 */ + | (1 << 8) /* bt709 */ + | (1 << 0); /* bt709 */ + else + default_signal_type = + /* default 709 limit */ + (1 << 29) /* video available */ + | (5 << 26) /* unspecified */ + | (0 << 25) /* limit */ + | (1 << 24) /* color available */ + | (1 << 16) /* bt709 */ + | (1 << 8) /* bt709 */ + | (1 << 0); /* bt709 */ + } else { /* for local play */ + if (vf->height >= 720) + default_signal_type = + /* HD default 709 limit */ + (1 << 29) /* video available */ + | (5 << 26) /* unspecified */ + | (0 << 25) /* limit */ + | (1 << 24) /* color available */ + | (1 << 16) /* bt709 */ + | (1 << 8) /* bt709 */ + | (1 << 0); /* bt709 */ + else + default_signal_type = + /* SD default 601 limited */ + (1 << 29) /* video available */ + | (5 << 26) /* unspecified */ + | (0 << 25) /* limited */ + | (1 << 24) /* color available */ + | (3 << 16) /* bt601 */ + | (3 << 8) /* bt601 */ + | (3 << 0); /* bt601 */ + } + if (vf->signal_type & (1 << 29)) + signal_type = vf->signal_type; + else + signal_type = default_signal_type; + + p_new = &vf->prop.master_display_colour; + p_cur = &cur_master_display_colour; + /* customer overwrite */ + if (customer_master_display_en + && ((p_new->present_flag & 0x80000000) == 0)) { + signal_type = (1 << 29) /* video available */ + | (5 << 26) /* unspecified */ + | (0 << 25) /* limit */ + | (1 << 24) /* color available */ + | (9 << 16) /* 2020 */ + | (16 << 8) /* 2084 */ + | (9 << 0); /* 2020 */ + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) + cus.primaries[i][j] = + customer_master_display_param[i*2+j]; + for (i = 0; i < 2; i++) + cus.white_point[i] = + customer_master_display_param[6+i]; + for (i = 0; i < 2; i++) + cus.luminance[i] = + customer_master_display_param[8+i]; + cus.present_flag = 1; + p_new = &cus; + } + if (p_new->present_flag & 1) { + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) { + if (p_cur->primaries[i][j] + != p_new->primaries[i][j]) + change_flag |= SIG_PRI_INFO; + p_cur->primaries[i][j] + = p_new->primaries[i][j]; + } + for (i = 0; i < 2; i++) { + if (p_cur->white_point[i] + != p_new->white_point[i]) + change_flag |= SIG_PRI_INFO; + p_cur->white_point[i] + = p_new->white_point[i]; + } + for (i = 0; i < 2; i++) { + if (p_cur->luminance[i] + != p_new->luminance[i]) + change_flag |= SIG_PRI_INFO; + p_cur->luminance[i] + = p_new->luminance[i]; + } + if (!p_cur->present_flag) { + p_cur->present_flag = 1; + change_flag |= SIG_PRI_INFO; + } + } else if (p_cur->present_flag) { + p_cur->present_flag = 0; + change_flag |= SIG_PRI_INFO; + } + if (change_flag & SIG_PRI_INFO) + pr_csc("Master_display_colour changed.\n"); + + if (signal_type != cur_signal_type) { + pr_csc("Signal type changed from 0x%x to 0x%x.\n", + cur_signal_type, signal_type); + change_flag |= SIG_CS_CHG; + cur_signal_type = signal_type; + } + if (pre_src_type != vf->source_type) { + pr_csc("Signal source changed from 0x%x to 0x%x.\n", + pre_src_type, vf->source_type); + change_flag |= SIG_SRC_CHG; + pre_src_type = vf->source_type; + } + if (cur_knee_factor != knee_factor) { + pr_csc("Knee factor changed.\n"); + change_flag |= SIG_KNEE_FACTOR; + } + if (cur_hdr_process_mode != hdr_process_mode) { + pr_csc("HDR mode changed.\n"); + change_flag |= SIG_HDR_MODE; + cur_hdr_process_mode = hdr_process_mode; + } + if (cur_sdr_process_mode != sdr_process_mode) { + pr_csc("SDR mode changed.\n"); + change_flag |= SIG_HDR_MODE; + cur_sdr_process_mode = sdr_process_mode; + } + if (cur_hdr_support != (vinfo->hdr_info.hdr_support & 0x4)) { + pr_csc("Tx HDR support changed.\n"); + change_flag |= SIG_HDR_SUPPORT; + cur_hdr_support = vinfo->hdr_info.hdr_support & 0x4; + } + + if ((cur_eye_protect_mode != wb_val[0]) || + (cur_eye_protect_mode == 1)) { + pr_csc(" eye protect mode changed.\n"); + change_flag |= SIG_WB_CHG; + } + + return change_flag; +} + +#define signal_range ((cur_signal_type >> 25) & 1) +#define signal_color_primaries ((cur_signal_type >> 16) & 0xff) +#define signal_transfer_characteristic ((cur_signal_type >> 8) & 0xff) +enum vpp_matrix_csc_e get_csc_type(void) +{ + enum vpp_matrix_csc_e csc_type = VPP_MATRIX_NULL; + + if (signal_color_primaries == 1) { + if (signal_range == 0) + csc_type = VPP_MATRIX_YUV709_RGB; + else + csc_type = VPP_MATRIX_YUV709F_RGB; + } else if (signal_color_primaries == 3) { + if (signal_range == 0) + csc_type = VPP_MATRIX_YUV601_RGB; + else + csc_type = VPP_MATRIX_YUV601F_RGB; + } else if ((signal_color_primaries == 9) || + (signal_transfer_characteristic == 16)) { + if (signal_transfer_characteristic == 16) { + /* smpte st-2084 */ + if (signal_color_primaries != 9) + pr_csc("\tWARNING: non-standard HDR!!!\n"); + + if (signal_range == 0) + csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; + else { + pr_csc("\tWARNING: full range HDR!!!\n"); + csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; + } + } else if (signal_transfer_characteristic == 14) { + /* bt2020-10 */ + pr_csc("\tWARNING: bt2020-10 HDR!!!\n"); + if (signal_range == 0) + csc_type = VPP_MATRIX_YUV709_RGB; + else + csc_type = VPP_MATRIX_YUV709F_RGB; + } else if (signal_transfer_characteristic == 15) { + /* bt2020-12 */ + pr_csc("\tWARNING: bt2020-12 HDR!!!\n"); + if (signal_range == 0) + csc_type = VPP_MATRIX_YUV709_RGB; + else + csc_type = VPP_MATRIX_YUV709F_RGB; + } else { + /* unknown transfer characteristic */ + pr_csc("\tWARNING: unknown HDR!!!\n"); + if (signal_range == 0) + csc_type = VPP_MATRIX_YUV709_RGB; + else + csc_type = VPP_MATRIX_YUV709F_RGB; + } + } else { + pr_csc("\tWARNING: unsupported colour space!!!\n"); + if (signal_range == 0) + csc_type = VPP_MATRIX_YUV601_RGB; + else + csc_type = VPP_MATRIX_YUV601F_RGB; + } + return csc_type; +} + +static void mtx_dot_mul( + int64_t (*a)[3], int64_t (*b)[3], + int64_t (*out)[3], int32_t norm) +{ + int i, j; + + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) + out[i][j] = (a[i][j] * b[i][j] + (norm >> 1)) / norm; +} + +static void mtx_mul(int64_t (*a)[3], int64_t *b, int64_t *out, int32_t norm) +{ + int j, k; + + for (j = 0; j < 3; j++) { + out[j] = 0; + for (k = 0; k < 3; k++) + out[j] += a[k][j] * b[k]; + out[j] = (out[j] + (norm >> 1)) / norm; + } +} + +static void mtx_mul_mtx( + int64_t (*a)[3], int64_t (*b)[3], + int64_t (*out)[3], int32_t norm) +{ + int i, j, k; + + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) { + out[i][j] = 0; + for (k = 0; k < 3; k++) + out[i][j] += a[k][j] * b[i][k]; + out[i][j] = (out[i][j] + (norm >> 1)) / norm; + } +} + +static void inverse_3x3( + int64_t (*in)[3], int64_t (*out)[3], + int32_t norm, int32_t obl) +{ + int i, j; + int64_t determinant = 0; + + for (i = 0; i < 3; i++) + determinant += + in[0][i] * (in[1][(i + 1) % 3] * in[2][(i + 2) % 3] + - in[1][(i + 2) % 3] * in[2][(i + 1) % 3]); + determinant = (determinant + 1) >> 1; + + for (i = 0; i < 3; i++) { + for (j = 0; j < 3; j++) { + out[j][i] = (in[(i + 1) % 3][(j + 1) % 3] + * in[(i + 2) % 3][(j + 2) % 3]); + out[j][i] -= (in[(i + 1) % 3][(j + 2) % 3] + * in[(i + 2) % 3][(j + 1) % 3]); + out[j][i] = (out[j][i] * norm) << (obl - 1); + out[j][i] = + (out[j][i] + (determinant >> 1)) / determinant; + } + } +} + +static void calc_T( + int32_t (*prmy)[2], int64_t (*Tout)[3], + int32_t norm, int32_t obl) +{ + int i, j; + int64_t z[4]; + int64_t A[3][3]; + int64_t B[3]; + int64_t C[3]; + int64_t D[3][3]; + int64_t E[3][3]; + + for (i = 0; i < 4; i++) + z[i] = norm - prmy[i][0] - prmy[i][1]; + + for (i = 0; i < 3; i++) { + for (j = 0; j < 2; j++) + A[i][j] = prmy[i][j]; + A[i][2] = z[i]; + } + B[0] = (norm * prmy[3][0] * 2 / prmy[3][1] + 1) >> 1; + B[1] = norm; + B[2] = (norm * z[3] * 2 / prmy[3][1] + 1) >> 1; + inverse_3x3(A, D, norm, obl); + mtx_mul(D, B, C, norm); + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) + E[i][j] = C[i]; + mtx_dot_mul(A, E, Tout, norm); +} + +static void gamut_mtx( + int32_t (*src_prmy)[2], int32_t (*dst_prmy)[2], + int64_t (*Tout)[3], int32_t norm, int32_t obl) +{ + int64_t Tsrc[3][3]; + int64_t Tdst[3][3]; + int64_t out[3][3]; + + calc_T(src_prmy, Tsrc, norm, obl); + calc_T(dst_prmy, Tdst, norm, obl); + inverse_3x3(Tdst, out, 1 << obl, obl); + mtx_mul_mtx(out, Tsrc, Tout, 1 << obl); +} + +static void apply_scale_factor(int64_t (*in)[3], int32_t *rs) +{ + int i, j; + int32_t right_shift; + + if (display_scale_factor > 2 * 2048) + right_shift = -2; + else if (display_scale_factor > 2048) + right_shift = -1; + else + right_shift = 0; + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) { + in[i][j] *= display_scale_factor; + in[i][j] >>= 11 - right_shift; + } + right_shift += 1; + if (right_shift < 0) + *rs = 8 + right_shift; + else + *rs = right_shift; +} + +static void N2C(int64_t (*in)[3], int32_t ibl, int32_t obl) +{ + int i, j; + + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) { + in[i][j] = + (in[i][j] + (1 << (ibl - 12))) >> (ibl - 11); + if (in[i][j] < 0) + in[i][j] += 1 << obl; + } +} + +static void cal_mtx_seting( + int64_t (*in)[3], + int32_t ibl, int32_t obl, + struct matrix_s *m) +{ + int i, j; + int32_t right_shift; + + if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) { + apply_scale_factor(in, &right_shift); + m->right_shift = right_shift; + } + N2C(in, ibl, obl); + pr_csc("\tHDR color convert matrix:\n"); + for (i = 0; i < 3; i++) { + m->pre_offset[i] = 0; + for (j = 0; j < 3; j++) + m->matrix[i][j] = in[j][i]; + m->offset[i] = 0; + pr_csc("\t\t%04x %04x %04x\n", + (int)(m->matrix[i][0] & 0xffff), + (int)(m->matrix[i][1] & 0xffff), + (int)(m->matrix[i][2] & 0xffff)); + } +} + +static int check_primaries( + /* src primaries and white point */ + uint (*p)[3][2], + uint (*w)[2], + /* dst display info from vinfo */ + const struct vinfo_s *v, + /* prepare src and dst color info array */ + int32_t (*si)[4][2], int32_t (*di)[4][2]) +{ + int i, j; + /* always calculate to apply scale factor */ + int need_calculate_mtx = 1; + const struct master_display_info_s *d; + + /* check and copy primaries */ + if (hdr_flag & 1) { + if (((*p)[0][1] > (*p)[1][1]) + && ((*p)[0][1] > (*p)[2][1]) + && ((*p)[2][0] > (*p)[0][0]) + && ((*p)[2][0] > (*p)[1][0])) { + /* reasonable g,b,r */ + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) { + (*si)[i][j] = (*p)[(i + 2) % 3][j]; + if ((*si)[i][j] != + bt2020_primaries[(i + 2) % 3][j]) + need_calculate_mtx = 1; + } + } else if (((*p)[0][0] > (*p)[1][0]) + && ((*p)[0][0] > (*p)[2][0]) + && ((*p)[1][1] > (*p)[0][1]) + && ((*p)[1][1] > (*p)[2][1])) { + /* reasonable r,g,b */ + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) { + (*si)[i][j] = (*p)[i][j]; + if ((*si)[i][j] != + bt2020_primaries[(i + 2) % 3][j]) + need_calculate_mtx = 1; + } + } else { + /* source not usable, use standard bt2020 */ + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) + (*si)[i][j] = + bt2020_primaries + [(i + 2) % 3][j]; + } + /* check white point */ + if (need_calculate_mtx == 1) { + if (((*w)[0] > (*si)[2][0]) && + ((*w)[0] < (*si)[0][0]) && + ((*w)[1] > (*si)[2][1]) && + ((*w)[1] < (*si)[1][1])) { + for (i = 0; i < 2; i++) + (*si)[3][i] = (*w)[i]; + } else { + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) + (*si)[i][j] = + bt2020_primaries[(i + 2) % 3][j]; + + for (i = 0; i < 2; i++) + (*si)[3][i] = bt2020_white_point[i]; + /* need_calculate_mtx = 0; */ + } + } else { + if (((*w)[0] > (*si)[2][0]) && + ((*w)[0] < (*si)[0][0]) && + ((*w)[1] > (*si)[2][1]) && + ((*w)[1] < (*si)[1][1])) { + for (i = 0; i < 2; i++) { + (*si)[3][i] = (*w)[i]; + if ((*si)[3][i] != + bt2020_white_point[i]) + need_calculate_mtx = 1; + } + } else { + for (i = 0; i < 2; i++) + (*si)[3][i] = bt2020_white_point[i]; + } + } + } else { + /* use standard bt2020 */ + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) + (*si)[i][j] = bt2020_primaries[(i + 2) % 3][j]; + for (i = 0; i < 2; i++) + (*si)[3][i] = bt2020_white_point[i]; + } + + /* check display */ + if ((v->master_display_info.present_flag) && (hdr_flag & 2)) { + d = &v->master_display_info; + for (i = 0; i < 3; i++) { + for (j = 0; j < 2; j++) { + (*di)[i][j] = d->primaries[(i + 2) % 3][j]; + if ((*di)[i][j] != + bt709_primaries[(i + 2) % 3][j]) + need_calculate_mtx = 1; + } + } + for (i = 0; i < 2; i++) { + (*di)[3][i] = d->white_point[i]; + if ((*di)[3][i] != bt709_white_point[i]) + need_calculate_mtx = 1; + } + } else { + for (i = 0; i < 3; i++) { + for (j = 0; j < 2; j++) + (*di)[i][j] = bt709_primaries[(i + 2) % 3][j]; + } + for (i = 0; i < 2; i++) + (*di)[3][i] = bt709_white_point[i]; + } + return need_calculate_mtx; +} + +enum vpp_matrix_csc_e prepare_customer_matrix( + u32 (*s)[3][2], /* source primaries */ + u32 (*w)[2], /* source white point */ + const struct vinfo_s *v, /* vinfo carry display primaries */ + struct matrix_s *m, + bool inverse_flag) +{ + int32_t prmy_src[4][2]; + int32_t prmy_dst[4][2]; + int64_t out[3][3]; + int i, j; + + if ((customer_matrix_en && + get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB)) { + for (i = 0; i < 3; i++) { + m->pre_offset[i] = + customer_matrix_param[i]; + for (j = 0; j < 3; j++) + m->matrix[i][j] = + customer_matrix_param[3 + i * 3 + j]; + m->offset[i] = + customer_matrix_param[12 + i]; + } + m->right_shift = + customer_matrix_param[15]; + return VPP_MATRIX_BT2020RGB_CUSRGB; + } + + if (inverse_flag) { + if (check_primaries(s, w, v, &prmy_src, &prmy_dst)) { + gamut_mtx(prmy_dst, prmy_src, out, INORM, BL); + cal_mtx_seting(out, BL, 13, m); + } + } else { + if (check_primaries(s, w, v, &prmy_src, &prmy_dst)) { + gamut_mtx(prmy_src, prmy_dst, out, INORM, BL); + cal_mtx_seting(out, BL, 13, m); + } + } + return VPP_MATRIX_BT2020RGB_CUSRGB; + + /*return VPP_MATRIX_BT2020YUV_BT2020RGB;*/ +} + +/* Max luminance lookup table for contrast */ +static const int maxLuma_thrd[5] = {512, 1024, 2048, 4096, 8192}; +static int calculate_contrast_adj(int max_lumin) +{ + int k; + int left, right, norm, alph; + int ratio, target_contrast; + + if (max_lumin < maxLuma_thrd[0]) + k = 0; + else if (max_lumin < maxLuma_thrd[1]) + k = 1; + else if (max_lumin < maxLuma_thrd[2]) + k = 2; + else if (max_lumin < maxLuma_thrd[3]) + k = 3; + else if (max_lumin < maxLuma_thrd[4]) + k = 4; + else + k = 5; + + if (k == 0) + ratio = extra_con_lut[0]; + else if (k == 5) + ratio = extra_con_lut[4]; + else { + left = extra_con_lut[k - 1]; + right = extra_con_lut[k]; + norm = maxLuma_thrd[k] - maxLuma_thrd[k - 1]; + alph = max_lumin - maxLuma_thrd[k - 1]; + ratio = left + (alph * (right - left) + (norm >> 1)) / norm; + } + target_contrast = ((vd1_contrast + 1024) * ratio + 64) >> 7; + target_contrast = clip(target_contrast, 0, 2047); + target_contrast -= 1024; + return target_contrast - vd1_contrast; +} + +static void print_primaries_info(struct vframe_master_display_colour_s *p) +{ + int i, j; + + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) + pr_csc( + "\t\tprimaries[%1d][%1d] = %04x\n", + i, j, + p->primaries[i][j]); + pr_csc("\t\twhite_point = (%04x, %04x)\n", + p->white_point[0], p->white_point[1]); + pr_csc("\t\tmax,min luminance = %08x, %08x\n", + p->luminance[0], p->luminance[1]); +} + +static void amvecm_cp_hdr_info(struct master_display_info_s *hdr_data, + struct vframe_master_display_colour_s *p) +{ + int i, j; + + if (customer_hdmi_display_en) { + hdr_data->features = + (1 << 29) /* video available */ + | (5 << 26) /* unspecified */ + | (0 << 25) /* limit */ + | (1 << 24) /* color available */ + | (customer_hdmi_display_param[0] << 16) /* bt2020 */ + | (customer_hdmi_display_param[1] << 8) /* 2084 */ + | (10 << 0); /* bt2020c */ + memcpy(hdr_data->primaries, + &customer_hdmi_display_param[2], + sizeof(u32)*6); + memcpy(hdr_data->white_point, + &customer_hdmi_display_param[8], + sizeof(u32)*2); + hdr_data->luminance[0] = + customer_hdmi_display_param[10]; + hdr_data->luminance[1] = + customer_hdmi_display_param[11]; + hdr_data->max_content = + customer_hdmi_display_param[12]; + hdr_data->max_frame_average = + customer_hdmi_display_param[13]; + } else if (((hdr_data->features >> 16) & 0xff) == 9) { + if (p->present_flag & 1) { + memcpy(hdr_data->primaries, + p->primaries, + sizeof(u32)*6); + memcpy(hdr_data->white_point, + p->white_point, + sizeof(u32)*2); + hdr_data->luminance[0] = + p->luminance[0]; + hdr_data->luminance[1] = + p->luminance[1]; + if (p->content_light_level.present_flag == 1) { + hdr_data->max_content = + p->content_light_level.max_content; + hdr_data->max_frame_average = + p->content_light_level.max_pic_average; + } else { + hdr_data->max_content = 0; + hdr_data->max_frame_average = 0; + } + } else { + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) + hdr_data->primaries[i][j] = + bt2020_primaries[i][j]; + hdr_data->white_point[0] = bt709_white_point[0]; + hdr_data->white_point[1] = bt709_white_point[1]; + /* default luminance */ + hdr_data->luminance[0] = 5000 * 10000; + hdr_data->luminance[1] = 50; + + /* content_light_level */ + hdr_data->max_content = 0; + hdr_data->max_frame_average = 0; + } + hdr_data->luminance[0] = hdr_data->luminance[0] / 10000; + hdr_data->present_flag = 1; + } else + memset(hdr_data->primaries, 0, 10 * sizeof(unsigned int)); + + /* hdr send information debug */ + memcpy(&dbg_hdr_send, hdr_data, + sizeof(struct master_display_info_s)); + +} + +static void hdr_process_pq_enable(int enable) +{ + dnlp_en = enable; + /*cm_en = enable;*/ +} + +static void vpp_lut_curve_set(enum vpp_lut_sel_e lut_sel) +{ + if (lut_sel == VPP_LUT_EOTF) { + /* eotf lut 2048 */ + if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXL) || + (get_cpu_type() == MESON_CPU_MAJOR_ID_GXM)) { + if (video_lut_swtich == 1) + /*350nit alpha_low = 0.12; */ + set_vpp_lut(VPP_LUT_EOTF, + eotf_33_2084_mapping_level1_box, /* R */ + eotf_33_2084_mapping_level1_box, /* G */ + eotf_33_2084_mapping_level1_box, /* B */ + CSC_ON); + else if (video_lut_swtich == 2) + /*800nit alpha_low = 0.12; */ + set_vpp_lut(VPP_LUT_EOTF, + eotf_33_2084_mapping_level2_box, /* R */ + eotf_33_2084_mapping_level2_box, /* G */ + eotf_33_2084_mapping_level2_box, /* B */ + CSC_ON); + else if (video_lut_swtich == 3) + /*400nit alpha_low = 0.20; */ + set_vpp_lut(VPP_LUT_EOTF, + eotf_33_2084_mapping_level3_box, /* R */ + eotf_33_2084_mapping_level3_box, /* G */ + eotf_33_2084_mapping_level3_box, /* B */ + CSC_ON); + else if (video_lut_swtich == 4) + /*450nit alpha_low = 0.12; */ + set_vpp_lut(VPP_LUT_EOTF, + eotf_33_2084_mapping_level4_box, /* R */ + eotf_33_2084_mapping_level4_box, /* G */ + eotf_33_2084_mapping_level4_box, /* B */ + CSC_ON); + else + /* eotf lut 2048 */ + /*600nit alpha_low = 0.12;*/ + set_vpp_lut(VPP_LUT_EOTF, + eotf_33_2084_mapping_box, /* R */ + eotf_33_2084_mapping_box, /* G */ + eotf_33_2084_mapping_box, /* B */ + CSC_ON); + } else + set_vpp_lut(VPP_LUT_EOTF, + eotf_33_2084_mapping, /* R */ + eotf_33_2084_mapping, /* G */ + eotf_33_2084_mapping, /* B */ + CSC_ON); + } else if (lut_sel == VPP_LUT_OETF) { + /* oetf lut bypass */ + if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXL) || + (get_cpu_type() == MESON_CPU_MAJOR_ID_GXM)) { + if (video_lut_swtich == 1) + set_vpp_lut(VPP_LUT_OETF, + oetf_289_gamma22_mapping_level1_box, + oetf_289_gamma22_mapping_level1_box, + oetf_289_gamma22_mapping_level1_box, + CSC_ON); + else if (video_lut_swtich == 2) + set_vpp_lut(VPP_LUT_OETF, + oetf_289_gamma22_mapping_level2_box, + oetf_289_gamma22_mapping_level2_box, + oetf_289_gamma22_mapping_level2_box, + CSC_ON); + else if (video_lut_swtich == 3) + set_vpp_lut(VPP_LUT_OETF, + oetf_289_gamma22_mapping_level3_box, + oetf_289_gamma22_mapping_level3_box, + oetf_289_gamma22_mapping_level3_box, + CSC_ON); + else if (video_lut_swtich == 4) + set_vpp_lut(VPP_LUT_OETF, + oetf_289_gamma22_mapping_level4_box, + oetf_289_gamma22_mapping_level4_box, + oetf_289_gamma22_mapping_level4_box, + CSC_ON); + else + /* oetf lut bypass */ + set_vpp_lut(VPP_LUT_OETF, + oetf_289_gamma22_mapping_box, + oetf_289_gamma22_mapping_box, + oetf_289_gamma22_mapping_box, + CSC_ON); + } else + set_vpp_lut(VPP_LUT_OETF, + oetf_289_gamma22_mapping, + oetf_289_gamma22_mapping, + oetf_289_gamma22_mapping, + CSC_ON); + } +} +static int hdr_process( + enum vpp_matrix_csc_e csc_type, + struct vinfo_s *vinfo, + struct vframe_master_display_colour_s *master_info) +{ + int need_adjust_contrast_saturation = 0; + int max_lumin = 10000; + struct matrix_s m = { + {0, 0, 0}, + { + {0x0d49, 0x1b4d, 0x1f6b}, + {0x1f01, 0x0910, 0x1fef}, + {0x1fdb, 0x1f32, 0x08f3}, + }, + {0, 0, 0}, + 1 + }; + struct matrix_s osd_m = { + {0, 0, 0}, + { + {0x505, 0x2A2, 0x059}, + {0x08E, 0x75B, 0x017}, + {0x022, 0x0B4, 0x72A}, + }, + {0, 0, 0}, + 1 + }; + int mtx[EOTF_COEFF_SIZE] = { + EOTF_COEFF_NORM(1.6607056/2), EOTF_COEFF_NORM(-0.5877533/2), + EOTF_COEFF_NORM(-0.0729065/2), + EOTF_COEFF_NORM(-0.1245575/2), EOTF_COEFF_NORM(1.1329346/2), + EOTF_COEFF_NORM(-0.0083771/2), + EOTF_COEFF_NORM(-0.0181122/2), EOTF_COEFF_NORM(-0.1005249/2), + EOTF_COEFF_NORM(1.1186371/2), + EOTF_COEFF_RIGHTSHIFT, + }; + int osd_mtx[EOTF_COEFF_SIZE] = { + EOTF_COEFF_NORM(0.627441), EOTF_COEFF_NORM(0.329285), + EOTF_COEFF_NORM(0.043274), + EOTF_COEFF_NORM(0.069092), EOTF_COEFF_NORM(0.919556), + EOTF_COEFF_NORM(0.011322), + EOTF_COEFF_NORM(0.016418), EOTF_COEFF_NORM(0.088058), + EOTF_COEFF_NORM(0.895554), + EOTF_COEFF_RIGHTSHIFT + }; + int i, j; + + if (master_info->present_flag & 1) { + pr_csc("\tMaster_display_colour available.\n"); + print_primaries_info(master_info); + /* for VIDEO */ + csc_type = + prepare_customer_matrix( + &master_info->primaries, + &master_info->white_point, + vinfo, &m, 0); + /* for OSD */ + if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) + prepare_customer_matrix( + &master_info->primaries, + &master_info->white_point, + vinfo, &osd_m, 1); + need_adjust_contrast_saturation |= 1; + } else { + /* use bt2020 primaries */ + pr_csc("\tNo master_display_colour.\n"); + /* for VIDEO */ + csc_type = + prepare_customer_matrix( + &bt2020_primaries, + &bt2020_white_point, + vinfo, &m, 0); + /* for OSD */ + if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) + prepare_customer_matrix( + &bt2020_primaries, + &bt2020_white_point, + vinfo, &osd_m, 1); + } + + if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) { + /************** OSD ***************/ + /* RGB to YUV */ + /* not using old RGB2YUV convert HW */ + /* use new 10bit OSD convert matrix */ + /* WRITE_VPP_REG_BITS */ + /*(VIU_OSD1_BLK0_CFG_W0,0, 7, 1); */ + + /* eotf lut 709 */ + set_vpp_lut(VPP_LUT_OSD_EOTF, + osd_eotf_33_709_mapping, /* R */ + osd_eotf_33_709_mapping, /* G */ + osd_eotf_33_709_mapping, /* B */ + CSC_ON); + + /* eotf matrix 709->2020 */ + osd_mtx[EOTF_COEFF_SIZE - 1] = osd_m.right_shift; + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) { + if (osd_m.matrix[i][j] & 0x1000) + osd_mtx[i * 3 + j] = + -(((~osd_m.matrix[i][j]) & 0xfff) + 1); + else + osd_mtx[i * 3 + j] = osd_m.matrix[i][j]; + } + set_vpp_matrix(VPP_MATRIX_OSD_EOTF, + osd_mtx, + CSC_ON); + + /* oetf lut 2084 */ + set_vpp_lut(VPP_LUT_OSD_OETF, + osd_oetf_41_2084_mapping, /* R */ + osd_oetf_41_2084_mapping, /* G */ + osd_oetf_41_2084_mapping, /* B */ + CSC_ON); + + /* osd matrix RGB2020 to YUV2020 limit */ + set_vpp_matrix(VPP_MATRIX_OSD, + RGB2020_to_YUV2020l_coeff, + CSC_ON); + + /************** VIDEO **************/ + /* vd1 matrix bypass */ + set_vpp_matrix(VPP_MATRIX_VD1, + bypass_coeff, + CSC_OFF); + + /* post matrix YUV2020 to RGB2020 */ + set_vpp_matrix(VPP_MATRIX_POST, + YUV2020l_to_RGB2020_coeff, + CSC_ON); + + /* eotf lut 2048 */ + vpp_lut_curve_set(VPP_LUT_EOTF); + + need_adjust_contrast_saturation = 0; + saturation_offset = 0; + if (hdr_flag & 8) { + need_adjust_contrast_saturation |= 2; + saturation_offset = extra_sat_lut[0]; + } + if (master_info->present_flag & 1) { + max_lumin = master_info->luminance[0] + / 10000; + if ((max_lumin <= 1200) && (max_lumin > 0)) { + if (hdr_flag & 4) + need_adjust_contrast_saturation |= 1; + if (hdr_flag & 8) + saturation_offset = + extra_sat_lut[1]; + } + } + /* eotf matrix RGB2020 to RGB709 */ + mtx[EOTF_COEFF_SIZE - 1] = m.right_shift; + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) { + if (m.matrix[i][j] & 0x1000) + mtx[i * 3 + j] = + -(((~m.matrix[i][j]) & 0xfff) + 1); + else + mtx[i * 3 + j] = m.matrix[i][j]; + } + set_vpp_matrix(VPP_MATRIX_EOTF, + mtx, + CSC_ON); + + vpp_lut_curve_set(VPP_LUT_OETF); + + /* xvyccc matrix3: bypass */ + if (vinfo->viu_color_fmt != COLOR_FMT_RGB444) + set_vpp_matrix(VPP_MATRIX_XVYCC, + RGB709_to_YUV709l_coeff, + CSC_ON); + } else { + + /* turn vd1 matrix on */ + vpp_set_matrix(VPP_MATRIX_VD1, CSC_ON, + csc_type, NULL); + /* turn post matrix on */ + vpp_set_matrix(VPP_MATRIX_POST, CSC_ON, + csc_type, &m); + /* xvycc lut on */ + load_knee_lut(CSC_ON); + + vecm_latch_flag |= FLAG_VADJ1_BRI; + hdr_process_pq_enable(0); + /* if GXTVBB HDMI output(YUV) case */ + /* xvyccc matrix3: RGB to YUV */ + /* other cases */ + /* xvyccc matrix3: bypass */ + if ((vinfo->viu_color_fmt != COLOR_FMT_RGB444) && + (get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB)) + vpp_set_matrix3(CSC_ON, VPP_MATRIX_RGB_YUV709); + else + vpp_set_matrix3(CSC_OFF, VPP_MATRIX_NULL); + } + return need_adjust_contrast_saturation; +} + +static void bypass_hdr_process( + enum vpp_matrix_csc_e csc_type, + struct vinfo_s *vinfo, + struct vframe_master_display_colour_s *master_info) +{ + struct matrix_s osd_m = { + {0, 0, 0}, + { + {0x505, 0x2A2, 0x059}, + {0x08E, 0x75B, 0x017}, + {0x022, 0x0B4, 0x72A}, + }, + {0, 0, 0}, + 1 + }; + int osd_mtx[EOTF_COEFF_SIZE] = { + EOTF_COEFF_NORM(0.627441), EOTF_COEFF_NORM(0.329285), + EOTF_COEFF_NORM(0.043274), + EOTF_COEFF_NORM(0.069092), EOTF_COEFF_NORM(0.919556), + EOTF_COEFF_NORM(0.011322), + EOTF_COEFF_NORM(0.016418), EOTF_COEFF_NORM(0.088058), + EOTF_COEFF_NORM(0.895554), + EOTF_COEFF_RIGHTSHIFT + }; + int i, j; + + if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) { + /************** OSD ***************/ + /* RGB to YUV */ + /* not using old RGB2YUV convert HW */ + /* use new 10bit OSD convert matrix */ + /* WRITE_VPP_REG_BITS*/ + /*(VIU_OSD1_BLK0_CFG_W0,0, 7, 1);*/ + if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && + (((vinfo->hdr_info.hdr_support & 0x4) && + (vinfo->viu_color_fmt != COLOR_FMT_RGB444)) || + (vinfo->viu_color_fmt == COLOR_FMT_RGB444))) { + /* OSD convert to HDR to match HDR video */ + /* osd eotf lut 709 */ + set_vpp_lut(VPP_LUT_OSD_EOTF, + osd_eotf_33_709_mapping, /* R */ + osd_eotf_33_709_mapping, /* G */ + osd_eotf_33_709_mapping, /* B */ + CSC_ON); + + /* osd eotf matrix 709->2020 */ + if (master_info->present_flag & 1) { + pr_csc("\tMaster_display_colour available.\n"); + print_primaries_info(master_info); + prepare_customer_matrix( + &master_info->primaries, + &master_info->white_point, + vinfo, &osd_m, 1); + } else { + pr_csc("\tNo master_display_colour.\n"); + prepare_customer_matrix( + &bt2020_primaries, + &bt2020_white_point, + vinfo, &osd_m, 1); + } + osd_mtx[EOTF_COEFF_SIZE - 1] = osd_m.right_shift; + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) { + if (osd_m.matrix[i][j] & 0x1000) { + osd_mtx[i * 3 + j] = + (~osd_m.matrix[i][j]) & 0xfff; + osd_mtx[i * 3 + j] = + -(1 + osd_mtx[i * 3 + j]); + } else + osd_mtx[i * 3 + j] = + osd_m.matrix[i][j]; + } + set_vpp_matrix(VPP_MATRIX_OSD_EOTF, + osd_mtx, + CSC_ON); + + /* osd oetf lut 2084 */ + set_vpp_lut(VPP_LUT_OSD_OETF, + osd_oetf_41_2084_mapping, /* R */ + osd_oetf_41_2084_mapping, /* G */ + osd_oetf_41_2084_mapping, /* B */ + CSC_ON); + + /* osd matrix RGB2020 to YUV2020 limit */ + set_vpp_matrix(VPP_MATRIX_OSD, + RGB2020_to_YUV2020l_coeff, + CSC_ON); + } else { + /* OSD convert to 709 limited to match SDR video */ + /* eotf lut bypass */ + set_vpp_lut(VPP_LUT_OSD_EOTF, + eotf_33_linear_mapping, /* R */ + eotf_33_linear_mapping, /* G */ + eotf_33_linear_mapping, /* B */ + CSC_OFF); + + /* eotf matrix bypass */ + set_vpp_matrix(VPP_MATRIX_OSD_EOTF, + eotf_bypass_coeff, + CSC_OFF); + + /* oetf lut bypass */ + set_vpp_lut(VPP_LUT_OSD_OETF, + oetf_41_linear_mapping, /* R */ + oetf_41_linear_mapping, /* G */ + oetf_41_linear_mapping, /* B */ + CSC_OFF); + + /* osd matrix RGB709 to YUV709 limit/full */ + if (range_control) + set_vpp_matrix(VPP_MATRIX_OSD, + RGB709_to_YUV709_coeff, + CSC_ON); /* use full range */ + else + set_vpp_matrix(VPP_MATRIX_OSD, + RGB709_to_YUV709l_coeff, + CSC_ON); /* use limit range */ + } + + /************** VIDEO **************/ + /* vd1 matrix: bypass */ + if (csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) + set_vpp_matrix(VPP_MATRIX_VD1, + bypass_coeff, + CSC_OFF); /* limit->limit range */ + else { + if (range_control) { + if (signal_range == 0) /* limit range */ + set_vpp_matrix(VPP_MATRIX_VD1, + YUV709l_to_YUV709f_coeff, + CSC_ON); + /* limit->full range */ + else + set_vpp_matrix(VPP_MATRIX_VD1, + bypass_coeff, + CSC_OFF); + /* full->full range */ + } else { + if (signal_range == 0) /* limit range */ + set_vpp_matrix(VPP_MATRIX_VD1, + bypass_coeff, + CSC_OFF); + /* limit->limit range */ + else + set_vpp_matrix(VPP_MATRIX_VD1, + YUV709f_to_YUV709l_coeff, + CSC_ON); + /* full->limit range */ + } + } + + /* post matrix bypass */ + if (vinfo->viu_color_fmt != COLOR_FMT_RGB444) + /* yuv2rgb for eye protect mode */ + set_vpp_matrix(VPP_MATRIX_POST, + bypass_coeff, + CSC_OFF); + else /* matrix yuv2rgb for LCD */ + set_vpp_matrix(VPP_MATRIX_POST, + YUV709l_to_RGB709_coeff, + CSC_ON); + /* xvycc inv lut */ + if (sdr_process_mode && + (csc_type < VPP_MATRIX_BT2020YUV_BT2020RGB) && + ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB) || + (get_cpu_type() == MESON_CPU_MAJOR_ID_TXL))) + set_vpp_lut(VPP_LUT_INV_EOTF, + NULL, + NULL, + NULL, + CSC_ON); + else + set_vpp_lut(VPP_LUT_INV_EOTF, + NULL, + NULL, + NULL, + CSC_OFF); + + /* eotf lut bypass */ + set_vpp_lut(VPP_LUT_EOTF, + NULL, /* R */ + NULL, /* G */ + NULL, /* B */ + CSC_OFF); + + /* eotf matrix bypass */ + set_vpp_matrix(VPP_MATRIX_EOTF, + eotf_bypass_coeff, + CSC_OFF); + + /* oetf lut bypass */ + set_vpp_lut(VPP_LUT_OETF, + NULL, + NULL, + NULL, + CSC_OFF); + + /* xvycc matrix full2limit or bypass */ + if (vinfo->viu_color_fmt != COLOR_FMT_RGB444) { + if (csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) + set_vpp_matrix(VPP_MATRIX_XVYCC, + bypass_coeff, + CSC_OFF); + else { + if (range_control) + set_vpp_matrix(VPP_MATRIX_XVYCC, + YUV709f_to_YUV709l_coeff, + CSC_ON); + else + set_vpp_matrix(VPP_MATRIX_XVYCC, + bypass_coeff, + CSC_OFF); + } + } + } else { + /* OSD */ + /* keep RGB */ + + /* VIDEO */ + if (csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) { + /* vd1 matrix: convert YUV to RGB */ + csc_type = VPP_MATRIX_YUV709_RGB; + } + /* vd1 matrix on to convert YUV to RGB */ + vpp_set_matrix(VPP_MATRIX_VD1, CSC_ON, + csc_type, NULL); + /* post matrix off */ + vpp_set_matrix(VPP_MATRIX_POST, CSC_OFF, + csc_type, NULL); + /* xvycc lut off */ + load_knee_lut(CSC_OFF); + /* xvycc inv lut */ + + if (sdr_process_mode) + set_vpp_lut(VPP_LUT_INV_EOTF, + NULL, + NULL, + NULL, + CSC_ON); + else + set_vpp_lut(VPP_LUT_INV_EOTF, + NULL, + NULL, + NULL, + CSC_OFF); + + vecm_latch_flag |= FLAG_VADJ1_BRI; + hdr_process_pq_enable(1); + /* if GXTVBB HDMI output(YUV) case */ + /* xvyccc matrix3: RGB to YUV */ + /* other cases */ + /* xvyccc matrix3: bypass */ + if ((vinfo->viu_color_fmt != COLOR_FMT_RGB444) && + (get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB)) + vpp_set_matrix3(CSC_ON, VPP_MATRIX_RGB_YUV709); + else + vpp_set_matrix3(CSC_OFF, VPP_MATRIX_NULL); + } +} + +static void sdr_hdr_process( + enum vpp_matrix_csc_e csc_type, + struct vinfo_s *vinfo, + struct vframe_master_display_colour_s *master_info) +{ + if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXL) || + (get_cpu_type() == MESON_CPU_MAJOR_ID_GXM)) { + /* OSD convert to 709 limited to match SDR video */ + /* eotf lut bypass */ + set_vpp_lut(VPP_LUT_OSD_EOTF, + eotf_33_linear_mapping, /* R */ + eotf_33_linear_mapping, /* G */ + eotf_33_linear_mapping, /* B */ + CSC_OFF); + + /* eotf matrix bypass */ + set_vpp_matrix(VPP_MATRIX_OSD_EOTF, + eotf_bypass_coeff, + CSC_OFF); + + /* oetf lut bypass */ + set_vpp_lut(VPP_LUT_OSD_OETF, + oetf_41_linear_mapping, /* R */ + oetf_41_linear_mapping, /* G */ + oetf_41_linear_mapping, /* B */ + CSC_OFF); + + /* osd matrix RGB709 to YUV709 limit/full */ + if (range_control) + set_vpp_matrix(VPP_MATRIX_OSD, + RGB709_to_YUV709_coeff, + CSC_ON); /* use full range */ + else + set_vpp_matrix(VPP_MATRIX_OSD, + RGB709_to_YUV709l_coeff, + CSC_ON); /* use limit range */ + + /************** VIDEO **************/ + /* convert SDR Video to HDR */ + if (range_control) { + if (signal_range == 0) /* limit range */ + set_vpp_matrix(VPP_MATRIX_VD1, + YUV709l_to_YUV709f_coeff, + CSC_ON); /* limit->full range */ + else + set_vpp_matrix(VPP_MATRIX_VD1, + bypass_coeff, + CSC_OFF); /* full->full range */ + } else { + if (signal_range == 0) /* limit range */ + set_vpp_matrix(VPP_MATRIX_VD1, + bypass_coeff, + CSC_OFF); /* limit->limit range */ + else + set_vpp_matrix(VPP_MATRIX_VD1, + YUV709f_to_YUV709l_coeff, + CSC_ON); /* full->limit range */ + } + + set_vpp_matrix(VPP_MATRIX_POST, + YUV709l_to_RGB709_coeff, + CSC_ON); + + /* eotf lut bypass */ + set_vpp_lut(VPP_LUT_EOTF, + eotf_33_sdr_709_mapping, /* R */ + eotf_33_sdr_709_mapping, /* G */ + eotf_33_sdr_709_mapping, /* B */ + CSC_ON); + + /* eotf matrix bypass */ + set_vpp_matrix(VPP_MATRIX_EOTF, + eotf_RGB709_to_RGB2020_coeff, + CSC_ON); + + /* oetf lut bypass */ + set_vpp_lut(VPP_LUT_OETF, + oetf_sdr_2084_mapping, + oetf_sdr_2084_mapping, + oetf_sdr_2084_mapping, + CSC_ON); + + /* xvycc matrix bypass */ + set_vpp_matrix(VPP_MATRIX_XVYCC, + RGB2020_to_YUV2020l_coeff, + CSC_ON); + } else if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB) || + (get_cpu_type() == MESON_CPU_MAJOR_ID_TXL)) { + bypass_hdr_process(csc_type, vinfo, master_info); + } +} + +static int vpp_eye_protection_process( + enum vpp_matrix_csc_e csc_type, + struct vinfo_s *vinfo) +{ + cur_eye_protect_mode = wb_val[0]; + memcpy(&video_rgb_ogo, wb_val, + sizeof(struct tcon_rgb_ogo_s)); + ve_ogo_param_update(); + + /* only SDR need switch csc */ + if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && + hdr_process_mode) + return 0; + if ((csc_type < VPP_MATRIX_BT2020YUV_BT2020RGB) && + sdr_process_mode) + return 0; + + /* post matrix bypass */ + if ((vinfo->viu_color_fmt != COLOR_FMT_RGB444) && + (cur_eye_protect_mode == 0)) + /* yuv2rgb for eye protect mode */ + set_vpp_matrix(VPP_MATRIX_POST, + bypass_coeff, + CSC_ON); + else /* matrix yuv2rgb for LCD */ + set_vpp_matrix(VPP_MATRIX_POST, + YUV709l_to_RGB709_coeff, + CSC_ON); + + /* xvycc matrix bypass */ + if ((vinfo->viu_color_fmt != COLOR_FMT_RGB444) && + (cur_eye_protect_mode == 1)) + /* for eye protect mode */ + video_rgb_ogo_xvy_mtx_latch &= MTX_RGB2YUVL_RGB_OGO; + else /* matrix yuv2rgb for LCD */ + set_vpp_matrix(VPP_MATRIX_XVYCC, + bypass_coeff, + CSC_ON); + + return 0; +} + +static void vpp_matrix_update(struct vframe_s *vf, struct vinfo_s *vinfo) +{ + enum vpp_matrix_csc_e csc_type = VPP_MATRIX_NULL; + int signal_change_flag = 0; + struct vframe_master_display_colour_s *p = &cur_master_display_colour; + struct master_display_info_s send_info; + int need_adjust_contrast_saturation = 0; + + /* Tx hdr information */ + memcpy(&receiver_hdr_info, &vinfo->hdr_info, + sizeof(struct hdr_info)); + + /* check hdr support info from Tx or Panel */ + if (hdr_mode == 2) { /* auto */ + if (vinfo->hdr_info.hdr_support & 0x4) + hdr_process_mode = 0; /* hdr->hdr*/ + else + hdr_process_mode = 1; /* hdr->sdr*/ + } else + hdr_process_mode = hdr_mode; + + if (sdr_mode == 2) { /* auto */ + if ((vinfo->hdr_info.hdr_support & 0x4) && + ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXL) || + (get_cpu_type() == MESON_CPU_MAJOR_ID_GXM))) + sdr_process_mode = 1; /*box sdr->hdr*/ + else if ((vinfo->viu_color_fmt == COLOR_FMT_RGB444) && + ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB) || + (get_cpu_type() == MESON_CPU_MAJOR_ID_TXL))) + sdr_process_mode = 1; /*tv sdr->hdr*/ + else + sdr_process_mode = 0; /* sdr->sdr*/ + } else + sdr_process_mode = sdr_mode; /* force sdr->hdr */ + + signal_change_flag = signal_type_changed(vf, vinfo); + + if ((!signal_change_flag) && (force_csc_type == 0xff)) + return; + + vecm_latch_flag |= FLAG_MATRIX_UPDATE; + + if (force_csc_type != 0xff) + csc_type = force_csc_type; + else + csc_type = get_csc_type(); + + if ((vinfo->viu_color_fmt != COLOR_FMT_RGB444) && + (vinfo->hdr_info.hdr_support & 0x4)) { + if (sdr_process_mode && + (csc_type < VPP_MATRIX_BT2020YUV_BT2020RGB)) { + /* sdr source convert to hdr */ + /* send hdr info */ + /* use the features to discribe source info */ + send_info.features = + (1 << 29) /* video available */ + | (5 << 26) /* unspecified */ + | (0 << 25) /* limit */ + | (1 << 24) /* color available */ + | (9 << 16) /* bt2020 */ + | (14 << 8) /* bt2020-10 */ + | (10 << 0); /* bt2020c */ + } else if ((hdr_process_mode == 0) && + (csc_type >= VPP_MATRIX_BT2020YUV_BT2020RGB)) { + /* source is hdr, send hdr info */ + /* use the features to discribe source info */ + send_info.features = + (1 << 29) /* video available */ + | (5 << 26) /* unspecified */ + | (0 << 25) /* limit */ + | (1 << 24) /* color available */ + | (9 << 16) /* bt2020 */ + | (14 << 8) /* bt2020-10 */ + | (10 << 0); /* bt2020c */ + } else { + /* sdr source send normal info*/ + /* use the features to discribe source info */ + send_info.features = + /* default 709 full */ + (1 << 29) /* video available */ + | (5 << 26) /* unspecified */ + | (1 << 25) /* full */ + | (1 << 24) /* color available */ + | (1 << 16) /* bt709 */ + | (1 << 8) /* bt709 */ + | (1 << 0); /* bt709 */ + } + amvecm_cp_hdr_info(&send_info, p); + if (vinfo->fresh_tx_hdr_pkt) + vinfo->fresh_tx_hdr_pkt(&send_info); + } + + if ((cur_csc_type != csc_type) + || (signal_change_flag + & (SIG_PRI_INFO | SIG_KNEE_FACTOR | SIG_HDR_MODE))) { + /* decided by edid or panel info or user setting */ + if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && + hdr_process_mode) { + /* hdr->sdr */ + if ((signal_change_flag & + (SIG_PRI_INFO | + SIG_KNEE_FACTOR | + SIG_HDR_MODE) + ) || + (cur_csc_type < + VPP_MATRIX_BT2020YUV_BT2020RGB)) { + need_adjust_contrast_saturation = + hdr_process(csc_type, vinfo, p); + } + } else { + if ((csc_type < VPP_MATRIX_BT2020YUV_BT2020RGB) && + sdr_process_mode) + /* for gxl and gxm SDR to HDR process */ + sdr_hdr_process(csc_type, vinfo, p); + else + /* for gxtvbb and gxl HDR bypass process */ + bypass_hdr_process(csc_type, vinfo, p); + + if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && + (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB)) + csc_type = VPP_MATRIX_YUV709_RGB; + } + if (need_adjust_contrast_saturation & 1) { + if (lut_289_en && + (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB)) + vd1_contrast_offset = 0; + else + vd1_contrast_offset = + calculate_contrast_adj(p->luminance[0] / 10000); + vecm_latch_flag |= FLAG_VADJ1_CON; + } else { + vd1_contrast_offset = 0; + vecm_latch_flag |= FLAG_VADJ1_CON; + } + if (need_adjust_contrast_saturation & 2) { + vecm_latch_flag |= FLAG_VADJ1_COLOR; + } else { + if (((get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB) || + (get_cpu_type() == MESON_CPU_MAJOR_ID_TXL)) && + (sdr_process_mode == 1)) + saturation_offset = sdr_saturation_offset; + else + saturation_offset = 0; + vecm_latch_flag |= FLAG_VADJ1_COLOR; + } + if (cur_csc_type != csc_type) { + pr_csc("CSC from 0x%x to 0x%x.\n", + cur_csc_type, csc_type); + pr_csc("contrast offset = %d.\n", + vd1_contrast_offset); + pr_csc("saturation offset = %d.\n", + saturation_offset); + cur_csc_type = csc_type; + } + } + + /* eye protection mode */ + if (signal_change_flag & SIG_WB_CHG) + vpp_eye_protection_process(csc_type, vinfo); + + vecm_latch_flag &= ~FLAG_MATRIX_UPDATE; +} + +static struct vframe_s *last_vf; +static int null_vf_cnt; + +static unsigned int fg_vf_sw_dbg; +unsigned int null_vf_max = 5; +module_param(null_vf_max, uint, 0664); +MODULE_PARM_DESC(null_vf_max, "\n null_vf_max\n"); +void amvecm_matrix_process(struct vframe_s *vf) +{ + struct vframe_s fake_vframe; + struct vinfo_s *vinfo = get_current_vinfo(); + int i; + + if ((get_cpu_type() < MESON_CPU_MAJOR_ID_GXTVBB) || + is_meson_gxl_package_905M2() || + skip_csc_en) + return; + + if (reload_mtx) { + for (i = 0; i < NUM_MATRIX; i++) + if (reload_mtx & (1 << i)) + set_vpp_matrix(i, NULL, CSC_ON); + } + + if (reload_lut) { + for (i = 0; i < NUM_LUT; i++) + if (reload_lut & (1 << i)) + set_vpp_lut(i, + NULL, /* R */ + NULL, /* G */ + NULL, /* B */ + CSC_ON); + } + + /* OSD sdr -> hdr in first vsync when hdr output */ + if ((vinfo->hdr_info.hdr_support & 0x4) && (vf == NULL) && + ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXL) || + (get_cpu_type() == MESON_CPU_MAJOR_ID_GXM))) { + if (((sdr_process_mode != 1) && (sdr_mode > 0)) + || ((sdr_process_mode > 0) && (sdr_mode == 0))) + null_vf_cnt = null_vf_max + 1; + } + + if ((vf == last_vf) && (null_vf_cnt <= null_vf_max) && + (cur_eye_protect_mode == wb_val[0])) + return; + + if (is_dolby_vision_on()) + return; + + if (vf != NULL) { + vpp_matrix_update(vf, vinfo); + last_vf = vf; + null_vf_cnt = 0; + fg_vf_sw_dbg = 1; + + /* debug vframe info backup */ + dbg_vf = vf; + } else { + /* check last signal type */ + if ((last_vf != NULL) && + ((((last_vf->signal_type >> 16) & 0xff) == 9) + || customer_master_display_en)) + null_vf_cnt++; + + if ((((READ_VPP_REG(VPP_MISC) & (1<<10)) == 0) + && (null_vf_cnt > null_vf_max)) || + (cur_eye_protect_mode != wb_val[0])) { + /* send a faked vframe to switch matrix*/ + /* from 2020 to 601 when video disabled */ + fake_vframe.source_type = VFRAME_SOURCE_TYPE_OTHERS; + fake_vframe.signal_type = 0; + fake_vframe.width = 720; + fake_vframe.height = 480; + fake_vframe.prop.master_display_colour.present_flag + = 0x80000000; + vpp_matrix_update(&fake_vframe, vinfo); + pr_csc("change CSC when disable video.\n"); + last_vf = vf; + null_vf_cnt = 0; + fg_vf_sw_dbg = 2; + } else + fg_vf_sw_dbg = 3; + } +} + +int amvecm_hdr_dbg(u32 sel) +{ + int i, j; + + /* select debug information */ + if (sel == 1) /* dump reg */ + goto reg_dump; + + if (dbg_vf == NULL) + goto hdr_dump; + + /*pr_err("----vframe info----\n");*/ + /*pr_err("index:%d, type:0x%x, type_backup:0x%x, blend_mode:%d\n",*/ + /* dbg_vf->index, dbg_vf->type,*/ + /* dbg_vf->type_backup, dbg_vf->blend_mode);*/ + /*pr_err("duration:%d, duration_pulldown:%d, pts:%d, flag:0x%x\n",*/ + /* dbg_vf->duration, dbg_vf->duration_pulldown,*/ + /* dbg_vf->pts, dbg_vf->flag);*/ + /*pr_err("canvas0Addr:0x%x, canvas1Addr:0x%x, bufWidth:%d\n",*/ + /* dbg_vf->canvas0Addr, dbg_vf->canvas1Addr,*/ + /* dbg_vf->bufWidth);*/ + /*pr_err("width:%d, height:%d, ratio_control:0x%x, bitdepth:%d\n",*/ + /* dbg_vf->width, dbg_vf->height,*/ + /* dbg_vf->ratio_control, dbg_vf->bitdepth);*/ + /*pr_err("signal_type:%x, orientation:%d, video_angle:0x%x\n",*/ + /* dbg_vf->signal_type, dbg_vf->orientation,*/ + /* dbg_vf->video_angle);*/ + /*pr_err("source_type:%d, phase:%d, soruce_mode:%d, sig_fmt:0x%x\n",*/ + /* dbg_vf->source_type, dbg_vf->phase,*/ + /* dbg_vf->source_mode, dbg_vf->sig_fmt);*/ + /*pr_err(*/ + /* "trans_fmt 0x%x, lefteye(%d %d %d %d),*/ + /*righteye(%d %d %d %d)\n",*/ + /* vf->trans_fmt, vf->left_eye.start_x, vf->left_eye.start_y,*/ + /* vf->left_eye.width, vf->left_eye.height,*/ + /* vf->right_eye.start_x, vf->right_eye.start_y,*/ + /* vf->right_eye.width, vf->right_eye.height);*/ + /*pr_err("mode_3d_enable %d",*/ + /* vf->mode_3d_enable);*/ + /*pr_err("early_process_fun 0x%p, process_fun 0x%p,*/ + /*private_data %p\n",*/ + /* vf->early_process_fun, vf->process_fun, vf->private_data);*/ + + /*pr_err("hist_pow %d, luma_sum %d, chroma_sum %d, pixel_sum %d\n",*/ + /* vf->prop.hist.hist_pow, vf->prop.hist.luma_sum,*/ + /* vf->prop.hist.chroma_sum, vf->prop.hist.pixel_sum);*/ + + /*pr_err("height %d, width %d, luma_max %d, luma_min %d\n",*/ + /* vf->prop.hist.hist_pow, vf->prop.hist.hist_pow,*/ + /* vf->prop.hist.hist_pow, vf->prop.hist.hist_pow);*/ + + /*pr_err("vpp_luma_sum %d, vpp_chroma_sum %d, vpp_pixel_sum %d\n",*/ + /* vf->prop.hist.vpp_luma_sum, vf->prop.hist.vpp_chroma_sum,*/ + /* vf->prop.hist.vpp_pixel_sum);*/ + + /*pr_err("vpp_height %d, vpp_width %d, vpp_luma_max %d,*/ + /* vpp_luma_min %d\n",*/ + /* vf->prop.hist.vpp_height, vf->prop.hist.vpp_width,*/ + /* vf->prop.hist.vpp_luma_max, vf->prop.hist.vpp_luma_min);*/ + + /*pr_err("vs_span_cnt %d, vs_cnt %d, hs_cnt0 %d, hs_cnt1 %d\n",*/ + /* vf->prop.meas.vs_span_cnt, vf->prop.meas.vs_cnt,*/ + /* vf->prop.meas.hs_cnt0, vf->prop.meas.hs_cnt1);*/ + + /*pr_err("hs_cnt2 %d, vs_cnt %d, hs_cnt3 %d,*/ + /* vs_cycle %d, vs_stamp %d\n",*/ + /* vf->prop.meas.hs_cnt2, vf->prop.meas.hs_cnt3,*/ + /* vf->prop.meas.vs_cycle, vf->prop.meas.vs_stamp);*/ + + /*pr_err("pixel_ratio:%d list:%p ready_jiffies64:%lld,*/ + /*frame_dirty %d\n",*/ + /* dbg_vf->pixel_ratio, &dbg_vf->list,*/ + /* dbg_vf->ready_jiffies64, dbg_vf->frame_dirty);*/ + + pr_err("----Video frame info----\n"); + pr_err("bitdepth:0x%x, signal_type:0x%x, present_flag:0x%x\n", + dbg_vf->bitdepth, + dbg_vf->signal_type, + dbg_vf->prop.master_display_colour.present_flag); + + if (((dbg_vf->signal_type >> 16) & 0xff) == 9) { + pr_err("HDR color primaries:0x%x\n", + ((dbg_vf->signal_type >> 16) & 0xff)); + pr_err("HDR transfer_characteristic:0x%x\n", + ((dbg_vf->signal_type >> 8) & 0xff)); + } else + pr_err("SDR color primaries:0x%x\n", signal_color_primaries); + + if (dbg_vf->prop.master_display_colour.present_flag == 1) { + pr_err("----SEI info----\n"); + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) + pr_err( + "\tprimaries[%1d][%1d] = %04x\n", + i, j, + dbg_vf->prop.master_display_colour.primaries[i][j]); + pr_err("\twhite_point = (%04x, %04x)\n", + dbg_vf->prop.master_display_colour.white_point[0], + dbg_vf->prop.master_display_colour.white_point[1]); + pr_err("\tmax,min luminance = %08x, %08x\n", + dbg_vf->prop.master_display_colour.luminance[0], + dbg_vf->prop.master_display_colour.luminance[1]); + } + +hdr_dump: + pr_err("----HDR process info----\n"); + pr_err("customer_master_display_en:0x%x\n", customer_master_display_en); + + pr_err("hdr_mode:0x%x, hdr_process_mode:0x%x, cur_hdr_process_mode:0x%x\n", + hdr_mode, hdr_process_mode, cur_hdr_process_mode); + + pr_err("sdr_mode:0x%x, sdr_process_mode:0x%x, cur_sdr_process_mode:0x%x\n", + sdr_mode, sdr_process_mode, cur_sdr_process_mode); + + pr_err("hdr_flag:0x%x, fg_vf_sw_dbg:0x%x\n", + hdr_flag, fg_vf_sw_dbg); + pr_err("cur_signal_type:0x%x, cur_csc_mode:0x%x, cur_csc_type:0x%x\n", + cur_signal_type, cur_csc_mode, cur_csc_type); + + pr_err("knee_lut_on:0x%x,knee_interpolation_mode:0x%x,cur_knee_factor:0x%x\n", + knee_lut_on, knee_interpolation_mode, cur_knee_factor); + + if ((receiver_hdr_info.hdr_support & 0x4) == 0) + goto dbg_end; + pr_err("----TV EDID info----\n"); + pr_err("hdr_support:0x%x, lumi_max:%d, lumi_avg:%d, lumi_min:%d\n", + receiver_hdr_info.hdr_support, + receiver_hdr_info.lumi_max, + receiver_hdr_info.lumi_avg, + receiver_hdr_info.lumi_min); + + pr_err("----Tx HDR package info----\n"); + pr_err("\tfeatures = 0x%08x\n", dbg_hdr_send.features); + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) + pr_err( + "\tprimaries[%1d][%1d] = %04x\n", + i, j, + dbg_hdr_send.primaries[i][j]); + pr_err("\twhite_point = (%04x, %04x)\n", + dbg_hdr_send.white_point[0], + dbg_hdr_send.white_point[1]); + pr_err("\tmax,min luminance = %08x, %08x\n", + dbg_hdr_send.luminance[0], dbg_hdr_send.luminance[1]); + + goto dbg_end; + + /************************dump reg start***************************/ +reg_dump: + + /* osd matrix, VPP_MATRIX_0 */ + pr_err("----dump regs VPP_MATRIX_OSD----\n"); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_PRE_OFFSET0_1, + READ_VPP_REG(VIU_OSD1_MATRIX_PRE_OFFSET0_1)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_PRE_OFFSET2, + READ_VPP_REG(VIU_OSD1_MATRIX_PRE_OFFSET2)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_COEF00_01, + READ_VPP_REG(VIU_OSD1_MATRIX_COEF00_01)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_COEF02_10, + READ_VPP_REG(VIU_OSD1_MATRIX_COEF02_10)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_COEF11_12, + READ_VPP_REG(VIU_OSD1_MATRIX_COEF11_12)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_COEF20_21, + READ_VPP_REG(VIU_OSD1_MATRIX_COEF20_21)); + + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_COEF22_30, + READ_VPP_REG(VIU_OSD1_MATRIX_COEF22_30)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_COEF31_32, + READ_VPP_REG(VIU_OSD1_MATRIX_COEF31_32)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_COEF40_41, + READ_VPP_REG(VIU_OSD1_MATRIX_COEF40_41)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_COLMOD_COEF42, + READ_VPP_REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_COEF22_30, + READ_VPP_REG(VIU_OSD1_MATRIX_COEF22_30)); + + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_OFFSET0_1, + READ_VPP_REG(VIU_OSD1_MATRIX_OFFSET0_1)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_OFFSET2, + READ_VPP_REG(VIU_OSD1_MATRIX_OFFSET2)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_COLMOD_COEF42, + READ_VPP_REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_COLMOD_COEF42, + READ_VPP_REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_PRE_OFFSET0_1, + READ_VPP_REG(VIU_OSD1_MATRIX_PRE_OFFSET0_1)); + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_MATRIX_CTRL, + READ_VPP_REG(VIU_OSD1_MATRIX_CTRL)); + + /* osd eotf matrix, VPP_MATRIX_OSD_EOTF */ + pr_err("----dump regs VPP_MATRIX_OSD_EOTF----\n"); + + for (i = 0; i < 5; i++) + pr_err("\taddr = %08x, val = %08x\n", + (VIU_OSD1_EOTF_CTL + i + 1), + READ_VPP_REG(VIU_OSD1_EOTF_CTL + i + 1)); + + pr_err("\taddr = %08x, val = %08x\n", + VIU_OSD1_EOTF_CTL, + READ_VPP_REG(VIU_OSD1_EOTF_CTL)); + + { + unsigned short r_map[VIDEO_OETF_LUT_SIZE]; + unsigned short g_map[VIDEO_OETF_LUT_SIZE]; + unsigned short b_map[VIDEO_OETF_LUT_SIZE]; + unsigned int addr_port; + unsigned int data_port; + unsigned int ctrl_port; + unsigned int data; + int i; + + pr_err("----dump regs VPP_LUT_OSD_OETF----\n"); + + addr_port = VIU_OSD1_OETF_LUT_ADDR_PORT; + data_port = VIU_OSD1_OETF_LUT_DATA_PORT; + ctrl_port = VIU_OSD1_OETF_CTL; + + pr_err("\taddr = %08x, val = %08x\n", + ctrl_port, READ_VPP_REG(ctrl_port)); + + for (i = 0; i < 20; i++) { + WRITE_VPP_REG(addr_port, i); + data = READ_VPP_REG(data_port); + r_map[i * 2] = data & 0xffff; + r_map[i * 2 + 1] = (data >> 16) & 0xffff; + } + WRITE_VPP_REG(addr_port, 20); + data = READ_VPP_REG(data_port); + r_map[OSD_OETF_LUT_SIZE - 1] = data & 0xffff; + g_map[0] = (data >> 16) & 0xffff; + for (i = 0; i < 20; i++) { + WRITE_VPP_REG(addr_port, 21 + i); + data = READ_VPP_REG(data_port); + g_map[i * 2 + 1] = data & 0xffff; + g_map[i * 2 + 2] = (data >> 16) & 0xffff; + } + for (i = 0; i < 20; i++) { + WRITE_VPP_REG(addr_port, 41 + i); + data = READ_VPP_REG(data_port); + b_map[i * 2] = data & 0xffff; + b_map[i * 2 + 1] = (data >> 16) & 0xffff; + } + WRITE_VPP_REG(addr_port, 61); + data = READ_VPP_REG(data_port); + b_map[OSD_OETF_LUT_SIZE - 1] = data & 0xffff; + + for (i = 0; i < OSD_OETF_LUT_SIZE; i++) { + pr_err("\t[%d] = 0x%04x 0x%04x 0x%04x\n", + i, r_map[i], g_map[i], b_map[i]); + } + + addr_port = VIU_OSD1_EOTF_LUT_ADDR_PORT; + data_port = VIU_OSD1_EOTF_LUT_DATA_PORT; + ctrl_port = VIU_OSD1_EOTF_CTL; + pr_err("----dump regs VPP_LUT_OSD_EOTF----\n"); + WRITE_VPP_REG(addr_port, 0); + for (i = 0; i < 16; i++) { + data = READ_VPP_REG(data_port); + r_map[i * 2] = data & 0xffff; + r_map[i * 2 + 1] = (data >> 16) & 0xffff; + } + data = READ_VPP_REG(data_port); + r_map[EOTF_LUT_SIZE - 1] = data & 0xffff; + g_map[0] = (data >> 16) & 0xffff; + for (i = 0; i < 16; i++) { + data = READ_VPP_REG(data_port); + g_map[i * 2 + 1] = data & 0xffff; + g_map[i * 2 + 2] = (data >> 16) & 0xffff; + } + for (i = 0; i < 16; i++) { + data = READ_VPP_REG(data_port); + b_map[i * 2] = data & 0xffff; + b_map[i * 2 + 1] = (data >> 16) & 0xffff; + } + data = READ_VPP_REG(data_port); + b_map[EOTF_LUT_SIZE - 1] = data & 0xffff; + + for (i = 0; i < EOTF_LUT_SIZE; i++) { + pr_err("\t[%d] = 0x%04x 0x%04x 0x%04x\n", + i, r_map[i], g_map[i], b_map[i]); + } + + pr_err("----dump hdr_osd_reg structure ----\n"); + + pr_err("\tviu_osd1_matrix_ctrl = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_ctrl); + pr_err("\tviu_osd1_matrix_coef00_01 = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_coef00_01); + pr_err("\tviu_osd1_matrix_coef02_10 = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_coef02_10); + pr_err("\tviu_osd1_matrix_coef11_12 = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_coef11_12); + pr_err("\tviu_osd1_matrix_coef20_21 = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_coef20_21); + pr_err("\tviu_osd1_matrix_colmod_coef42 = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_colmod_coef42); + pr_err("\tviu_osd1_matrix_offset0_1 = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_offset0_1); + pr_err("\tviu_osd1_matrix_offset2 = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_offset2); + pr_err("\tviu_osd1_matrix_pre_offset0_1 = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_pre_offset0_1); + pr_err("\tviu_osd1_matrix_pre_offset2 = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_pre_offset2); + pr_err("\tviu_osd1_matrix_coef22_30 = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_coef22_30); + pr_err("\tviu_osd1_matrix_coef31_32 = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_coef31_32); + pr_err("\tviu_osd1_matrix_coef40_41 = 0x%04x\n", + hdr_osd_reg.viu_osd1_matrix_coef40_41); + pr_err("\tviu_osd1_eotf_ctl = 0x%04x\n", + hdr_osd_reg.viu_osd1_eotf_ctl); + pr_err("\tviu_osd1_eotf_coef00_01 = 0x%04x\n", + hdr_osd_reg.viu_osd1_eotf_coef00_01); + pr_err("\tviu_osd1_eotf_coef02_10 = 0x%04x\n", + hdr_osd_reg.viu_osd1_eotf_coef02_10); + pr_err("\tviu_osd1_eotf_coef11_12 = 0x%04x\n", + hdr_osd_reg.viu_osd1_eotf_coef11_12); + pr_err("\tviu_osd1_eotf_coef20_21 = 0x%04x\n", + hdr_osd_reg.viu_osd1_eotf_coef20_21); + pr_err("\tviu_osd1_eotf_coef22_rs = 0x%04x\n", + hdr_osd_reg.viu_osd1_eotf_coef22_rs); + pr_err("\tviu_osd1_oetf_ctl = 0x%04x\n", + hdr_osd_reg.viu_osd1_oetf_ctl); + + for (i = 0; i < EOTF_LUT_SIZE; i++) { + pr_err("\t[%d] = 0x%04x 0x%04x 0x%04x\n", + i, + hdr_osd_reg.lut_val.r_map[i], + hdr_osd_reg.lut_val.g_map[i], + hdr_osd_reg.lut_val.b_map[i]); + } + for (i = 0; i < OSD_OETF_LUT_SIZE; i++) { + pr_err("\t[%d] = 0x%04x 0x%04x 0x%04x\n", + i, + hdr_osd_reg.lut_val.or_map[i], + hdr_osd_reg.lut_val.og_map[i], + hdr_osd_reg.lut_val.ob_map[i]); + } + pr_err("\n"); + } + pr_err("----dump regs VPP_LUT_EOTF----\n"); + print_vpp_lut(VPP_LUT_EOTF, READ_VPP_REG(VIU_EOTF_CTL) & (7 << 27)); + pr_err("----dump regs VPP_LUT_OETF----\n"); + print_vpp_lut(VPP_LUT_OETF, READ_VPP_REG(XVYCC_LUT_CTL) & 0x7f); + /*********************dump reg end*********************/ +dbg_end: + + return 0; +} diff --git a/drivers/amlogic/media/enhancement/amvecm/amcsc.h b/drivers/amlogic/media/enhancement/amvecm/amcsc.h new file mode 100644 index 0000000..e396ba8 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/amcsc.h @@ -0,0 +1,123 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amcsc.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef AM_CSC_H +#define AM_CSC_H + +/* white balance value */ +extern void ve_ogo_param_update(void); +extern struct tcon_rgb_ogo_s video_rgb_ogo; + +enum vpp_matrix_sel_e { + VPP_MATRIX_0 = 0, /* OSD convert matrix - new from GXL */ + VPP_MATRIX_1, /* vd1 matrix before post-blend */ + VPP_MATRIX_2, /* post matrix */ + VPP_MATRIX_3, /* xvycc matrix */ + VPP_MATRIX_4, /* in video eotf - new from GXL */ + VPP_MATRIX_5, /* in osd eotf - new from GXL */ + VPP_MATRIX_6 /* vd2 matrix before pre-blend */ +}; +#define NUM_MATRIX 6 + +/* matrix names */ +#define VPP_MATRIX_OSD VPP_MATRIX_0 +#define VPP_MATRIX_VD1 VPP_MATRIX_1 +#define VPP_MATRIX_POST VPP_MATRIX_2 +#define VPP_MATRIX_XVYCC VPP_MATRIX_3 +#define VPP_MATRIX_EOTF VPP_MATRIX_4 +#define VPP_MATRIX_OSD_EOTF VPP_MATRIX_5 +#define VPP_MATRIX_VD2 VPP_MATRIX_6 + +/* osd->eotf->matrix5->oetf->matrix0-+->post blend*/ +/* ->vadj2->matrix2->eotf->matrix4->oetf->matrix3*/ +/* video1->cm->lut->vadj1->matrix1-^*/ +/* video2->matrix6-^*/ + + +enum vpp_matrix_csc_e { + VPP_MATRIX_NULL = 0, + VPP_MATRIX_RGB_YUV601 = 0x1, + VPP_MATRIX_RGB_YUV601F = 0x2, + VPP_MATRIX_RGB_YUV709 = 0x3, + VPP_MATRIX_RGB_YUV709F = 0x4, + VPP_MATRIX_YUV601_RGB = 0x10, + VPP_MATRIX_YUV601_YUV601F = 0x11, + VPP_MATRIX_YUV601_YUV709 = 0x12, + VPP_MATRIX_YUV601_YUV709F = 0x13, + VPP_MATRIX_YUV601F_RGB = 0x14, + VPP_MATRIX_YUV601F_YUV601 = 0x15, + VPP_MATRIX_YUV601F_YUV709 = 0x16, + VPP_MATRIX_YUV601F_YUV709F = 0x17, + VPP_MATRIX_YUV709_RGB = 0x20, + VPP_MATRIX_YUV709_YUV601 = 0x21, + VPP_MATRIX_YUV709_YUV601F = 0x22, + VPP_MATRIX_YUV709_YUV709F = 0x23, + VPP_MATRIX_YUV709F_RGB = 0x24, + VPP_MATRIX_YUV709F_YUV601 = 0x25, + VPP_MATRIX_YUV709F_YUV709 = 0x26, + VPP_MATRIX_BT2020YUV_BT2020RGB = 0x40, + VPP_MATRIX_BT2020RGB_709RGB, + VPP_MATRIX_BT2020RGB_CUSRGB, +}; + +#define CSC_ON 1 +#define CSC_OFF 0 + +enum vpp_lut_sel_e { + VPP_LUT_OSD_EOTF = 0, + VPP_LUT_OSD_OETF, + VPP_LUT_EOTF, + VPP_LUT_OETF, + VPP_LUT_INV_EOTF +}; +#define NUM_LUT 5 + +/* matrix registers */ +struct matrix_s { + u16 pre_offset[3]; + u16 matrix[3][3]; + u16 offset[3]; + u16 right_shift; +}; + +#define LUT_289_SIZE 289 +extern unsigned int lut_289_mapping[LUT_289_SIZE]; +extern int dnlp_en; +/*extern int cm_en;*/ + +extern unsigned int vecm_latch_flag; +extern signed int vd1_contrast_offset; +extern signed int saturation_offset; +extern uint sdr_mode; +extern uint hdr_flag; +extern int video_rgb_ogo_xvy_mtx_latch; + +extern void amvecm_matrix_process(struct vframe_s *vf); +extern int amvecm_hdr_dbg(u32 sel); +#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA +#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val) +#define VSYNC_RD_MPEG_REG(adr) READ_VPP_REG(adr) +#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \ + WRITE_VPP_REG_BITS(adr, val, start, len) +#else +extern int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len); +extern u32 VSYNC_RD_MPEG_REG(u32 adr); +extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val); +#endif + +#endif /* AM_CSC_H */ + diff --git a/drivers/amlogic/media/enhancement/amvecm/amdolby_vision.c b/drivers/amlogic/media/enhancement/amvecm/amdolby_vision.c new file mode 100644 index 0000000..a97e3a3 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/amdolby_vision.c @@ -0,0 +1,2056 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amdolby_vision.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "arch/vpp_regs.h" +#include "arch/vpp_hdr_regs.h" +#include "arch/vpp_dolbyvision_regs.h" +#include "dolby_vision/dolby_vision.h" + +DEFINE_SPINLOCK(dovi_lock); +static const struct dolby_vision_func_s *p_funcs; + +#define DOLBY_VISION_OUTPUT_MODE_IPT 0 +#define DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL 1 +#define DOLBY_VISION_OUTPUT_MODE_HDR10 2 +#define DOLBY_VISION_OUTPUT_MODE_SDR10 3 +#define DOLBY_VISION_OUTPUT_MODE_SDR8 4 +#define DOLBY_VISION_OUTPUT_MODE_BYPASS 5 +static unsigned int dolby_vision_mode = DOLBY_VISION_OUTPUT_MODE_BYPASS; +module_param(dolby_vision_mode, uint, 0664); +MODULE_PARM_DESC(dolby_vision_mode, "\n dolby_vision_mode\n"); + +/* if sink support DV, always output DV */ +/* else always output SDR/HDR */ +#define DOLBY_VISION_FOLLOW_SINK 0 +/* output DV only if source is DV and sink support DV */ +/* else always output SDR/HDR */ +#define DOLBY_VISION_FOLLOW_SOURCE 1 +/* always follow dolby_vision_mode */ +#define DOLBY_VISION_FORCE_OUTPUT_MODE 2 +static unsigned int dolby_vision_policy; +module_param(dolby_vision_policy, uint, 0664); +MODULE_PARM_DESC(dolby_vision_policy, "\n dolby_vision_policy\n"); + +static bool dolby_vision_enable; +module_param(dolby_vision_enable, bool, 0664); +MODULE_PARM_DESC(dolby_vision_enable, "\n dolby_vision_enable\n"); + +#define BYPASS_PROCESS 0 +#define SDR_PROCESS 1 +#define HDR_PROCESS 2 +#define DV_PROCESS 3 +static uint dolby_vision_status; +module_param(dolby_vision_status, uint, 0664); +MODULE_PARM_DESC(dolby_vision_status, "\n dolby_vision_status\n"); + +#define FLAG_RESET_EACH_FRAME 0x01 +#define FLAG_META_FROM_BL 0x02 +#define FLAG_BYPASS_CVM 0x04 +#define FLAG_USE_SINK_MIN_MAX 0x08 +#define FLAG_CLKGATE_WHEN_LOAD_LUT 0x10 +#define FLAG_SINGLE_STEP 0x20 +#define FLAG_CERTIFICAION 0x40 +#define FLAG_CHANGE_SEQ_HEAD 0x80 +#define FLAG_DISABLE_COMPOSER 0x100 +#define FLAG_BYPASS_CSC 0x200 +#define FLAG_CHECK_ES_PTS 0x400 +#define FLAG_TOGGLE_FRAME 0x80000000 +static unsigned int dolby_vision_flags = + FLAG_META_FROM_BL | FLAG_BYPASS_CVM; +module_param(dolby_vision_flags, uint, 0664); +MODULE_PARM_DESC(dolby_vision_flags, "\n dolby_vision_flags\n"); + +static unsigned int htotal_add = 0x140; +static unsigned int vtotal_add = 0x40; +static unsigned int vsize_add; +static unsigned int vwidth = 0x8; +static unsigned int hwidth = 0x8; +static unsigned int vpotch = 0x10; +static unsigned int hpotch = 0x8; +static unsigned int g_htotal_add = 0x40; +static unsigned int g_vtotal_add = 0x80; +static unsigned int g_vsize_add; +static unsigned int g_vwidth = 0x18; +static unsigned int g_hwidth = 0x10; +static unsigned int g_vpotch = 0x8; +static unsigned int g_hpotch = 0x10; + +module_param(vtotal_add, uint, 0664); +MODULE_PARM_DESC(vtotal_add, "\n vtotal_add\n"); +module_param(vpotch, uint, 0664); +MODULE_PARM_DESC(vpotch, "\n vpotch\n"); + +static unsigned int dolby_vision_target_min = 50; /* 0.0001 */ +static unsigned int dolby_vision_target_max[3][3] = { + { 4000, 4000, 100 }, /* DOVI => DOVI/HDR/SDR */ + { 1000, 1000, 100 }, /* HDR => DOVI/HDR/SDR */ + { 600, 1000, 100 }, /* SDR => DOVI/HDR/SDR */ +}; + +static unsigned int dolby_vision_default_max[3][3] = { + { 4000, 4000, 100 }, /* DOVI => DOVI/HDR/SDR */ + { 1000, 1000, 100 }, /* HDR => DOVI/HDR/SDR */ + { 600, 1000, 100 }, /* SDR => DOVI/HDR/SDR */ +}; + +static unsigned int dolby_vision_graphic_min = 50; /* 0.0001 */ +static unsigned int dolby_vision_graphic_max = 100; /* 1 */ +module_param(dolby_vision_graphic_min, uint, 0664); +MODULE_PARM_DESC(dolby_vision_graphic_min, "\n dolby_vision_graphic_min\n"); + +static unsigned int debug_dolby; +module_param(debug_dolby, uint, 0664); +MODULE_PARM_DESC(debug_dolby, "\n debug_dolby\n"); + +static unsigned int debug_dolby_frame = 0xffff; +module_param(debug_dolby_frame, uint, 0664); +MODULE_PARM_DESC(debug_dolby_frame, "\n debug_dolby_frame\n"); + +#define pr_dolby_dbg(fmt, args...)\ + do {\ + if (debug_dolby)\ + pr_info("DOLBY: " fmt, ## args);\ + } while (0) +#define pr_dolby_error(fmt, args...)\ + pr_info("DOLBY ERROR: " fmt, ## args) +#define dump_enable \ + ((debug_dolby_frame >= 0xffff) || (debug_dolby_frame == frame_count)) +#define is_graphics_output_off() \ + (!(READ_VPP_REG(VPP_MISC) & (1<<12))) + +static bool dolby_vision_on; +static bool dolby_vision_wait_on; +static unsigned int frame_count; +static struct hdr10_param_s hdr10_param; +static struct master_display_info_s hdr10_data; +static struct dovi_setting_s dovi_setting; +static struct dovi_setting_s new_dovi_setting; + +static int dolby_core1_set( + uint32_t dm_count, + uint32_t comp_count, + uint32_t lut_count, + uint32_t *p_core1_dm_regs, + uint32_t *p_core1_comp_regs, + uint32_t *p_core1_lut, + int hsize, + int vsize, + int bl_enable, + int el_enable, + int el_41_mode, + int scramble_en, + bool dovi_src, + int lut_endian) +{ + uint32_t count; + uint32_t bypass_flag = 0; + int composer_enable = el_enable; + int i; + + if (dolby_vision_flags & FLAG_DISABLE_COMPOSER) + composer_enable = 0; + + if ((!dolby_vision_on) + || (dolby_vision_flags & FLAG_RESET_EACH_FRAME)) { + VSYNC_WR_MPEG_REG(VIU_SW_RESET, (1 << 10)|(1 << 9)); + VSYNC_WR_MPEG_REG(VIU_SW_RESET, 0); + } + + VSYNC_WR_MPEG_REG(DOLBY_CORE1_SWAP_CTRL0, 0); + VSYNC_WR_MPEG_REG(DOLBY_CORE1_SWAP_CTRL1, + ((hsize + 0x40) << 16) | (vsize + 0x20)); + VSYNC_WR_MPEG_REG(DOLBY_CORE1_SWAP_CTRL3, (hwidth << 16) | vwidth); + VSYNC_WR_MPEG_REG(DOLBY_CORE1_SWAP_CTRL4, (hpotch << 16) | vpotch); + VSYNC_WR_MPEG_REG(DOLBY_CORE1_SWAP_CTRL2, (hsize << 16) | vsize); + VSYNC_WR_MPEG_REG(DOLBY_CORE1_SWAP_CTRL5, 0xa); + VSYNC_WR_MPEG_REG(DOLBY_CORE1_DMA_CTRL, 0x0); + VSYNC_WR_MPEG_REG(DOLBY_CORE1_REG_START + 4, 4); + VSYNC_WR_MPEG_REG(DOLBY_CORE1_REG_START + 2, 1); + + /* bypass composer to get 12bit when SDR and HDR source */ + if (!dovi_src) + bypass_flag |= 1 << 0; + if (scramble_en) { + if (dolby_vision_flags & FLAG_BYPASS_CSC) + bypass_flag |= 1 << 1; + if (dolby_vision_flags & FLAG_BYPASS_CVM) + bypass_flag |= 1 << 2; + } + VSYNC_WR_MPEG_REG(DOLBY_CORE1_REG_START + 1, + 0x78 | bypass_flag); /* bypass CVM and/or CSC */ + VSYNC_WR_MPEG_REG(DOLBY_CORE1_REG_START + 1, + 0x78 | bypass_flag); /* for delay */ + if ((dolby_vision_flags & FLAG_RESET_EACH_FRAME) && (dm_count == 0)) + count = 24; + else + count = dm_count; + for (i = 0; i < count; i++) + VSYNC_WR_MPEG_REG(DOLBY_CORE1_REG_START + 6 + i, + p_core1_dm_regs[i]); + + if ((dolby_vision_flags & FLAG_RESET_EACH_FRAME) && (comp_count == 0)) + count = 173; + else + count = comp_count; + for (i = 0; i < count; i++) + VSYNC_WR_MPEG_REG(DOLBY_CORE1_REG_START + 6 + 44 + i, + p_core1_comp_regs[i]); + + /* metadata program done */ + VSYNC_WR_MPEG_REG(DOLBY_CORE1_REG_START + 3, 1); + + if ((dolby_vision_flags & FLAG_RESET_EACH_FRAME) && (lut_count == 0)) + count = 256 * 5; + else + count = lut_count; + if (count) { + if (dolby_vision_flags & FLAG_CLKGATE_WHEN_LOAD_LUT) + VSYNC_WR_MPEG_REG_BITS(DOLBY_CORE1_CLKGATE_CTRL, + 2, 2, 2); + VSYNC_WR_MPEG_REG(DOLBY_CORE1_DMA_CTRL, 0x1401); + if (lut_endian) + for (i = 0; i < count; i += 4) { + VSYNC_WR_MPEG_REG(DOLBY_CORE1_DMA_PORT, + p_core1_lut[i+3]); + VSYNC_WR_MPEG_REG(DOLBY_CORE1_DMA_PORT, + p_core1_lut[i+2]); + VSYNC_WR_MPEG_REG(DOLBY_CORE1_DMA_PORT, + p_core1_lut[i+1]); + VSYNC_WR_MPEG_REG(DOLBY_CORE1_DMA_PORT, + p_core1_lut[i]); + } + else + for (i = 0; i < count; i++) + VSYNC_WR_MPEG_REG(DOLBY_CORE1_DMA_PORT, + p_core1_lut[i]); + if (dolby_vision_flags & FLAG_CLKGATE_WHEN_LOAD_LUT) + VSYNC_WR_MPEG_REG_BITS(DOLBY_CORE1_CLKGATE_CTRL, + 0, 2, 2); + } + + /* enable core1 */ + VSYNC_WR_MPEG_REG(DOLBY_CORE1_SWAP_CTRL0, + bl_enable << 0 | + composer_enable << 1 | + el_41_mode << 2); + return 0; +} + +static int dolby_core2_set( + uint32_t dm_count, + uint32_t lut_count, + uint32_t *p_core2_dm_regs, + uint32_t *p_core2_lut, + int hsize, + int vsize, + int dolby_enable, + int lut_endian) +{ + uint32_t count; + int i; + + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_SWAP_CTRL0, 0); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_SWAP_CTRL1, + ((hsize + g_htotal_add) << 16) + | (vsize + g_vtotal_add + g_vsize_add)); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_SWAP_CTRL3, + (g_hwidth << 16) | g_vwidth); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_SWAP_CTRL4, + (g_hpotch << 16) | g_vpotch); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_SWAP_CTRL2, + (hsize << 16) | (vsize + g_vsize_add)); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_SWAP_CTRL5, 0x0); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_DMA_CTRL, 0x0); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_REG_START + 2, 1); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_REG_START + 1, 2); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_REG_START + 1, 2); + + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_CTRL, 0); + + if ((dolby_vision_flags & FLAG_RESET_EACH_FRAME) + && (dm_count == 0)) + count = 24; + else + count = dm_count; + for (i = 0; i < count; i++) + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_REG_START + 6 + i, + p_core2_dm_regs[i]); + /* core2 metadata program done */ + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_REG_START + 3, 1); + + if (dolby_vision_flags & FLAG_RESET_EACH_FRAME) + count = 256 * 5; + else + count = lut_count; + if (count) { + if (dolby_vision_flags & FLAG_CLKGATE_WHEN_LOAD_LUT) + VSYNC_WR_MPEG_REG_BITS(DOLBY_CORE2A_CLKGATE_CTRL, + 2, 2, 2); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_DMA_CTRL, 0x1401); + if (lut_endian) + for (i = 0; i < count; i += 4) { + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_DMA_PORT, + p_core2_lut[i+3]); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_DMA_PORT, + p_core2_lut[i+2]); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_DMA_PORT, + p_core2_lut[i+1]); + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_DMA_PORT, + p_core2_lut[i]); + } + else + for (i = 0; i < count; i++) + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_DMA_PORT, + p_core2_lut[i]); + /* core1 lookup table program done */ + if (dolby_vision_flags & FLAG_CLKGATE_WHEN_LOAD_LUT) + VSYNC_WR_MPEG_REG_BITS( + DOLBY_CORE2A_CLKGATE_CTRL, 0, 2, 2); + } + + /* enable core2 */ + VSYNC_WR_MPEG_REG(DOLBY_CORE2A_SWAP_CTRL0, dolby_enable << 0); + return 0; +} + +static int dolby_core3_set( + uint32_t dm_count, + uint32_t md_count, + uint32_t *p_core3_dm_regs, + uint32_t *p_core3_md_regs, + int hsize, + int vsize, + int dolby_enable, + int scramble_en) +{ + uint32_t count; + int i; + int vsize_hold = 0x10; + + /* turn off free run clock */ + VSYNC_WR_MPEG_REG(DOLBY_CORE3_CLKGATE_CTRL, 0); + VSYNC_WR_MPEG_REG(DOLBY_CORE3_SWAP_CTRL1, + ((hsize + htotal_add) << 16) + | (vsize + vtotal_add + vsize_add + vsize_hold * 2)); + VSYNC_WR_MPEG_REG(DOLBY_CORE3_SWAP_CTRL2, + (hsize << 16) | (vsize + vsize_add)); + VSYNC_WR_MPEG_REG(DOLBY_CORE3_SWAP_CTRL3, + (0x80 << 16) | vsize_hold); + VSYNC_WR_MPEG_REG(DOLBY_CORE3_SWAP_CTRL4, + (0x04 << 16) | vsize_hold); + VSYNC_WR_MPEG_REG(DOLBY_CORE3_SWAP_CTRL5, 0x0000); + if (dolby_vision_mode != + DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL) + VSYNC_WR_MPEG_REG(DOLBY_CORE3_SWAP_CTRL6, 0); + else + VSYNC_WR_MPEG_REG(DOLBY_CORE3_SWAP_CTRL6, + 0x10000000); /* swap UV */ + VSYNC_WR_MPEG_REG(DOLBY_CORE3_REG_START + 5, 7); + VSYNC_WR_MPEG_REG(DOLBY_CORE3_REG_START + 4, 4); + VSYNC_WR_MPEG_REG(DOLBY_CORE3_REG_START + 4, 2); + VSYNC_WR_MPEG_REG(DOLBY_CORE3_REG_START + 2, 1); + /* Control Register, address 0x04 2:0 RW */ + /* Output_operating mode*/ + /* 00- IPT 12 bit 444 bypass Dolby Vision output*/ + /* 01- IPT 12 bit tunnelled over RGB 8 bit 444, dolby vision output*/ + /* 02- HDR10 output, RGB 10 bit 444 PQ*/ + /* 03- Deep color SDR, RGB 10 bit 444 Gamma*/ + /* 04- SDR, RGB 8 bit 444 Gamma*/ + VSYNC_WR_MPEG_REG(DOLBY_CORE3_REG_START + 1, dolby_vision_mode); + VSYNC_WR_MPEG_REG(DOLBY_CORE3_REG_START + 1, dolby_vision_mode); + /* for delay */ + + if ((dolby_vision_flags & FLAG_RESET_EACH_FRAME) + && (dm_count == 0)) + count = 26; + else + count = dm_count; + for (i = 0; i < count; i++) + VSYNC_WR_MPEG_REG(DOLBY_CORE3_REG_START + 0x6 + i, + p_core3_dm_regs[i]); + /* from addr 0x18 */ + + count = md_count; + for (i = 0; i < count; i++) + VSYNC_WR_MPEG_REG(DOLBY_CORE3_REG_START + 0x24 + i, + p_core3_md_regs[i]); + for (; i < 30; i++) + VSYNC_WR_MPEG_REG(DOLBY_CORE3_REG_START + 0x24 + i, 0); + + /* from addr 0x90 */ + /* core3 metadata program done */ + VSYNC_WR_MPEG_REG(DOLBY_CORE3_REG_START + 3, 1); + + /* enable core3 */ + VSYNC_WR_MPEG_REG(DOLBY_CORE3_SWAP_CTRL0, (dolby_enable << 0)); + return 0; +} + +static uint32_t dolby_ctrl_backup; +static uint32_t viu_misc_ctrl_backup; +static uint32_t vpu_hdmi_fmt_backup; +static uint32_t viu_eotf_ctrl_backup; +static uint32_t xvycc_lut_ctrl_backup; +static uint32_t inv_lut_ctrl_backup; +static uint32_t vpp_matrix_backup; +static uint32_t vpp_vadj_backup; +static uint32_t vpp_dummy1_backup; +static uint32_t vpp_gainoff_backup; +void enable_dolby_vision(int enable) +{ + if (enable) { + if (!dolby_vision_on) { + dolby_ctrl_backup = + VSYNC_RD_MPEG_REG(VPP_DOLBY_CTRL); + viu_misc_ctrl_backup = + VSYNC_RD_MPEG_REG(VIU_MISC_CTRL1); + vpu_hdmi_fmt_backup = + VSYNC_RD_MPEG_REG(VPU_HDMI_FMT_CTRL); + viu_eotf_ctrl_backup = + VSYNC_RD_MPEG_REG(VIU_EOTF_CTL); + xvycc_lut_ctrl_backup = + VSYNC_RD_MPEG_REG(XVYCC_LUT_CTL); + inv_lut_ctrl_backup = + VSYNC_RD_MPEG_REG(XVYCC_INV_LUT_CTL); + vpp_matrix_backup = + VSYNC_RD_MPEG_REG(VPP_MATRIX_CTRL); + vpp_vadj_backup = + VSYNC_RD_MPEG_REG(VPP_VADJ_CTRL); + vpp_dummy1_backup = + VSYNC_RD_MPEG_REG(VPP_DUMMY_DATA1); + vpp_gainoff_backup = + VSYNC_RD_MPEG_REG(VPP_GAINOFF_CTRL0); + VSYNC_WR_MPEG_REG(VPP_DOLBY_CTRL, + (0x0<<21) /* cm_datx4_mode */ + |(0x0<<20) /* reg_front_cti_bit_mode */ + |(0x0<<17) /* vpp_clip_ext_mode 19:17 */ + |(0x1<<16) /* vpp_dolby2_en */ + |(0x0<<15) /* mat_xvy_dat_mode */ + |(0x1<<14) /* vpp_ve_din_mode */ + |(0x1<<12) /* mat_vd2_dat_mode 13:12 */ + |(0x3<<8) /* vpp_dpath_sel 10:8 */ + |0x1f); /* vpp_uns2s_mode 7:0 */ + VSYNC_WR_MPEG_REG_BITS(VIU_MISC_CTRL1, + (0 << 4) /* 23-20 ext mode */ + | (0 << 3) /* 19 osd bypass */ + | (0 << 2) /* 18 core2 bypass */ + | (0 << 1) /* 17 core1 el bypass */ + | (0 << 0), /* 16 core1 bl bypass */ + 16, 8); + VSYNC_WR_MPEG_REG(VPU_HDMI_FMT_CTRL, 0); + VSYNC_WR_MPEG_REG(VIU_EOTF_CTL, 0); + VSYNC_WR_MPEG_REG(XVYCC_LUT_CTL, 0); + VSYNC_WR_MPEG_REG(XVYCC_INV_LUT_CTL, 0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_CTRL, 0); + VSYNC_WR_MPEG_REG(VPP_VADJ_CTRL, 0); + VSYNC_WR_MPEG_REG(VPP_DUMMY_DATA1, 0x20000000); + VSYNC_WR_MPEG_REG(VPP_GAINOFF_CTRL0, 0); + VSYNC_WR_MPEG_REG_BITS(VIU_OSD1_MATRIX_CTRL, 0, 0, 1); + VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 0, 28, 1); + enable_osd_path(0); + pr_dolby_dbg("Dolby Vision turn on\n"); + } + dolby_vision_on = true; + dolby_vision_wait_on = false; + } else { + if (dolby_vision_on) { + VSYNC_WR_MPEG_REG(VPP_DOLBY_CTRL, + dolby_ctrl_backup); + VSYNC_WR_MPEG_REG(VIU_MISC_CTRL1, + viu_misc_ctrl_backup); + VSYNC_WR_MPEG_REG(VPU_HDMI_FMT_CTRL, + vpu_hdmi_fmt_backup); + VSYNC_WR_MPEG_REG(VIU_EOTF_CTL, + viu_eotf_ctrl_backup); + VSYNC_WR_MPEG_REG(XVYCC_LUT_CTL, + xvycc_lut_ctrl_backup); + VSYNC_WR_MPEG_REG(XVYCC_INV_LUT_CTL, + inv_lut_ctrl_backup); + VSYNC_WR_MPEG_REG(VPP_MATRIX_CTRL, + vpp_matrix_backup); + VSYNC_WR_MPEG_REG(VPP_VADJ_CTRL, + vpp_vadj_backup); + VSYNC_WR_MPEG_REG(VPP_DUMMY_DATA1, + vpp_dummy1_backup); + VSYNC_WR_MPEG_REG(VPP_GAINOFF_CTRL0, + vpp_gainoff_backup); + VSYNC_WR_MPEG_REG_BITS(VIU_OSD1_MATRIX_CTRL, 1, 0, 1); + enable_osd_path(1); + pr_dolby_dbg("Dolby Vision turn off\n"); + } + dolby_vision_on = false; + dolby_vision_wait_on = false; + dolby_vision_status = BYPASS_PROCESS; + } +} +EXPORT_SYMBOL(enable_dolby_vision); + +static bool video_is_hdr10; +module_param(video_is_hdr10, bool, 0664); +MODULE_PARM_DESC(video_is_hdr10, "\n video_is_hdr10\n"); + +/* dolby vision enhanced layer receiver*/ +#define DVEL_RECV_NAME "dvel" + +static inline void dvel_vf_put(struct vframe_s *vf) +{ + struct vframe_provider_s *vfp = vf_get_provider(DVEL_RECV_NAME); + int event = 0; + + if (vfp) { + vf_put(vf, DVEL_RECV_NAME); + event |= VFRAME_EVENT_RECEIVER_PUT; + vf_notify_provider(DVEL_RECV_NAME, event, NULL); + } +} + +static inline struct vframe_s *dvel_vf_peek(void) +{ + return vf_peek(DVEL_RECV_NAME); +} + +static inline struct vframe_s *dvel_vf_get(void) +{ + int event = 0; + struct vframe_s *vf = vf_get(DVEL_RECV_NAME); + + if (vf) { + event |= VFRAME_EVENT_RECEIVER_GET; + vf_notify_provider(DVEL_RECV_NAME, event, NULL); + } + return vf; +} + +static struct vframe_s *dv_vf[16][2]; +static void *metadata_parser; +static bool metadata_parser_reset_flag; +static char meta_buf[1024]; +static char md_buf[1024]; +static char comp_buf[8196]; + +static int dvel_receiver_event_fun(int type, void *data, void *arg) +{ + char *provider_name = (char *)data; + int i; + unsigned long flags; + + if (type == VFRAME_EVENT_PROVIDER_UNREG) { + pr_info("%s, provider %s unregistered\n", + __func__, provider_name); + spin_lock_irqsave(&dovi_lock, flags); + for (i = 0; i < 16; i++) { + if (dv_vf[i][0]) { + if (dv_vf[i][1]) + dvel_vf_put(dv_vf[i][1]); + dv_vf[i][1] = NULL; + } + dv_vf[i][0] = NULL; + } + if (metadata_parser && p_funcs) { + p_funcs->metadata_parser_release(); + metadata_parser = NULL; + }; + new_dovi_setting.video_width = + new_dovi_setting.video_height = 0; + spin_unlock_irqrestore(&dovi_lock, flags); + memset(&hdr10_data, 0, sizeof(hdr10_data)); + memset(&hdr10_param, 0, sizeof(hdr10_param)); + frame_count = 0; + return -1; + } else if (type == VFRAME_EVENT_PROVIDER_QUREY_STATE) { + return RECEIVER_ACTIVE; + } else if (type == VFRAME_EVENT_PROVIDER_REG) { + pr_info("%s, provider %s registered\n", + __func__, provider_name); + spin_lock_irqsave(&dovi_lock, flags); + for (i = 0; i < 16; i++) + dv_vf[i][0] = dv_vf[i][1] = NULL; + new_dovi_setting.video_width = + new_dovi_setting.video_height = 0; + spin_unlock_irqrestore(&dovi_lock, flags); + memset(&hdr10_data, 0, sizeof(hdr10_data)); + memset(&hdr10_param, 0, sizeof(hdr10_param)); + frame_count = 0; + } + return 0; +} + +static const struct vframe_receiver_op_s dvel_vf_receiver = { + .event_cb = dvel_receiver_event_fun +}; + +static struct vframe_receiver_s dvel_vf_recv; + +void dolby_vision_init_receiver(void) +{ + pr_info("%s(%s)\n", __func__, DVEL_RECV_NAME); + vf_receiver_init(&dvel_vf_recv, DVEL_RECV_NAME, + &dvel_vf_receiver, &dvel_vf_recv); + vf_reg_receiver(&dvel_vf_recv); + pr_info("%s: %s\n", __func__, dvel_vf_recv.name); +} +EXPORT_SYMBOL(dolby_vision_init_receiver); + +#define MAX_FILENAME_LENGTH 64 +static const char comp_file[] = "%s_comp.%04d.reg"; +static const char dm_reg_core1_file[] = "%s_dm_core1.%04d.reg"; +static const char dm_reg_core2_file[] = "%s_dm_core2.%04d.reg"; +static const char dm_reg_core3_file[] = "%s_dm_core3.%04d.reg"; +static const char dm_lut_core1_file[] = "%s_dm_core1.%04d.lut"; +static const char dm_lut_core2_file[] = "%s_dm_core2.%04d.lut"; + +static void dump_struct(void *structure, int struct_length, + const char file_string[], int frame_nr) +{ + char fn[MAX_FILENAME_LENGTH]; + struct file *fp; + loff_t pos = 0; + mm_segment_t old_fs = get_fs(); + + if (frame_nr == 0) + return; + set_fs(KERNEL_DS); + snprintf(fn, MAX_FILENAME_LENGTH, file_string, + "/data/tmp/tmp", frame_nr-1); + fp = filp_open(fn, O_RDWR|O_CREAT, 0666); + if (fp == NULL) + pr_info("Error open file for writing %s\n", fn); + vfs_write(fp, structure, struct_length, &pos); + vfs_fsync(fp, 0); + filp_close(fp, NULL); + set_fs(old_fs); +} + +void dolby_vision_dump_struct(void) +{ + dump_struct(&dovi_setting.dm_reg1, + sizeof(dovi_setting.dm_reg1), + dm_reg_core1_file, frame_count); + if (dovi_setting.el_flag) + dump_struct(&dovi_setting.comp_reg, + sizeof(dovi_setting.comp_reg), + comp_file, frame_count); + + if (!is_graphics_output_off()) + dump_struct(&dovi_setting.dm_reg2, + sizeof(dovi_setting.dm_reg2), + dm_reg_core2_file, frame_count); + + dump_struct(&dovi_setting.dm_reg3, + sizeof(dovi_setting.dm_reg3), + dm_reg_core3_file, frame_count); + + dump_struct(&dovi_setting.dm_lut1, + sizeof(dovi_setting.dm_lut1), + dm_lut_core1_file, frame_count); + if (!is_graphics_output_off()) + dump_struct(&dovi_setting.dm_lut2, + sizeof(dovi_setting.dm_lut2), + dm_lut_core2_file, frame_count); + pr_dolby_dbg("setting for frame %d dumped\n", frame_count); +} +EXPORT_SYMBOL(dolby_vision_dump_struct); + +static void dump_setting( + struct dovi_setting_s *setting, + int frame_cnt, int debug_flag) +{ + int i; + uint32_t *p; + + if ((debug_flag & 0x10) && dump_enable) { + pr_info("core1\n"); + p = (uint32_t *)&setting->dm_reg1; + for (i = 0; i < 26; i++) + pr_info("%x\n", p[i]); + if (setting->el_flag) { + pr_info("\ncomposer\n"); + p = (uint32_t *)&setting->comp_reg; + for (i = 0; i < 173; i++) + pr_info("%x\n", p[i]); + } + } + + if ((debug_flag & 0x20) && dump_enable) { + pr_info("\ncore1lut\n"); + p = (uint32_t *)&setting->dm_lut1.TmLutI; + for (i = 0; i < 64; i++) + pr_info("%x, %x, %x, %x\n", + p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]); + pr_info("\n"); + p = (uint32_t *)&setting->dm_lut1.TmLutS; + for (i = 0; i < 64; i++) + pr_info("%x, %x, %x, %x\n", + p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]); + pr_info("\n"); + p = (uint32_t *)&setting->dm_lut1.SmLutI; + for (i = 0; i < 64; i++) + pr_info("%x, %x, %x, %x\n", + p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]); + pr_info("\n"); + p = (uint32_t *)&setting->dm_lut1.SmLutS; + for (i = 0; i < 64; i++) + pr_info("%x, %x, %x, %x\n", + p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]); + pr_info("\n"); + p = (uint32_t *)&setting->dm_lut1.G2L; + for (i = 0; i < 64; i++) + pr_info("%x, %x, %x, %x\n", + p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]); + pr_info("\n"); + } + + if ((debug_flag & 0x10) && dump_enable && !is_graphics_output_off()) { + pr_info("core2\n"); + p = (uint32_t *)&setting->dm_reg2; + for (i = 0; i < 24; i++) + pr_info("%x\n", p[i]); + } + + if ((debug_flag & 0x20) && dump_enable && !is_graphics_output_off()) { + pr_info("\ncore2lut\n"); + p = (uint32_t *)&setting->dm_lut2.TmLutI; + for (i = 0; i < 64; i++) + pr_info("%x, %x, %x, %x\n", + p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]); + pr_info("\n"); + p = (uint32_t *)&setting->dm_lut2.TmLutS; + for (i = 0; i < 64; i++) + pr_info("%x, %x, %x, %x\n", + p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]); + pr_info("\n"); + p = (uint32_t *)&setting->dm_lut2.SmLutI; + for (i = 0; i < 64; i++) + pr_info("%x, %x, %x, %x\n", + p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]); + pr_info("\n"); + p = (uint32_t *)&setting->dm_lut2.SmLutS; + for (i = 0; i < 64; i++) + pr_info("%x, %x, %x, %x\n", + p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]); + pr_info("\n"); + p = (uint32_t *)&setting->dm_lut2.G2L; + for (i = 0; i < 64; i++) + pr_info("%x, %x, %x, %x\n", + p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]); + pr_info("\n"); + } + + if ((debug_flag & 0x10) && dump_enable) { + pr_info("core3\n"); + p = (uint32_t *)&setting->dm_reg3; + for (i = 0; i < 26; i++) + pr_info("%x\n", p[i]); + } + + if ((debug_flag & 0x40) && dump_enable + && (dolby_vision_mode <= DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL)) { + pr_info("\ncore3_meta %d\n", setting->md_reg3.size); + p = setting->md_reg3.raw_metadata; + for (i = 0; i < setting->md_reg3.size; i++) + pr_info("%x\n", p[i]); + pr_info("\n"); + } +} + +void dolby_vision_dump_setting(int debug_flag) +{ + pr_dolby_dbg("\n====== setting for frame %d ======\n", frame_count); + dump_setting(&new_dovi_setting, frame_count, debug_flag); + pr_dolby_dbg("=== setting for frame %d dumped ===\n\n", frame_count); +} +EXPORT_SYMBOL(dolby_vision_dump_setting); + +static int sink_support_dolby_vision(const struct vinfo_s *vinfo) +{ + if (!vinfo || !vinfo->dv_info) + return 0; + if (vinfo->dv_info->ieeeoui != 0x00d046) + return 0; + /* 2160p60 if TV support */ + if ((vinfo->width >= 3840) + && (vinfo->height >= 2160) + && (vinfo->dv_info->sup_2160p60hz == 1)) + return 1; + /* 1080p~2160p30 if TV support */ + else if (((vinfo->width == 1920) + && (vinfo->height == 1080)) + || ((vinfo->width >= 3840) + && (vinfo->height >= 2160) + && (vinfo->dv_info->sup_2160p60hz == 0))) + return 1; + return 0; +} + +static int dolby_vision_policy_process( + int *mode, enum signal_format_e src_format) +{ + const struct vinfo_s *vinfo; + int mode_change = 0; + + if ((!dolby_vision_enable) || (!p_funcs) + || ((get_cpu_type() != MESON_CPU_MAJOR_ID_GXM))) + return mode_change; + + vinfo = get_current_vinfo(); + if (dolby_vision_policy == DOLBY_VISION_FOLLOW_SINK) { + if (vinfo && sink_support_dolby_vision(vinfo)) { + /* TV support DOVI, All -> DOVI */ + if (dolby_vision_mode != + DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL) { + pr_dolby_dbg("dovi output -> DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL\n"); + *mode = DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL; + mode_change = 1; + } + } else { + /* TV not support DOVI */ + if (src_format == FORMAT_DOVI) { + /* DOVI to SDR */ + if (dolby_vision_mode != + DOLBY_VISION_OUTPUT_MODE_SDR8) { + pr_dolby_dbg("dovi output -> DOLBY_VISION_OUTPUT_MODE_SDR8\n"); + *mode = DOLBY_VISION_OUTPUT_MODE_SDR8; + mode_change = 1; + } + } else if (dolby_vision_mode != + DOLBY_VISION_OUTPUT_MODE_BYPASS) { + /* HDR/SDR bypass */ + pr_dolby_dbg("dovi output -> DOLBY_VISION_OUTPUT_MODE_BYPASS\n"); + *mode = DOLBY_VISION_OUTPUT_MODE_BYPASS; + mode_change = 1; + } + } + } else if (dolby_vision_policy == DOLBY_VISION_FOLLOW_SOURCE) { + if (src_format == FORMAT_DOVI) { + /* DOVI source */ + if (vinfo && sink_support_dolby_vision(vinfo)) { + /* TV support DOVI, DOVI -> DOVI */ + if (dolby_vision_mode != + DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL) { + pr_dolby_dbg("dovi output -> DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL\n"); + *mode = + DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL; + mode_change = 1; + } + } else { + /* TV not support DOVI, DOVI -> SDR */ + if (dolby_vision_mode != + DOLBY_VISION_OUTPUT_MODE_SDR8) { + pr_dolby_dbg("dovi output -> DOLBY_VISION_OUTPUT_MODE_SDR8\n"); + *mode = DOLBY_VISION_OUTPUT_MODE_SDR8; + mode_change = 1; + } + } + } else if (dolby_vision_mode != + DOLBY_VISION_OUTPUT_MODE_BYPASS) { + /* HDR/SDR bypass */ + pr_dolby_dbg("dovi output -> DOLBY_VISION_OUTPUT_MODE_BYPASS"); + *mode = DOLBY_VISION_OUTPUT_MODE_BYPASS; + mode_change = 1; + } + } else if (dolby_vision_policy == DOLBY_VISION_FORCE_OUTPUT_MODE) { + if (dolby_vision_mode != *mode) { + pr_dolby_dbg("dovi output mode change %d -> %d\n", + dolby_vision_mode, *mode); + mode_change = 1; + } + } + return mode_change; +} + +static bool is_dovi_frame(struct vframe_s *vf) +{ + struct provider_aux_req_s req; + char *p; + unsigned int size = 0; + unsigned int type = 0; + + req.vf = vf; + req.bot_flag = 0; + req.aux_buf = NULL; + req.aux_size = 0; + req.dv_enhance_exist = 0; + vf_notify_provider_by_name("dvbldec", + VFRAME_EVENT_RECEIVER_GET_AUX_DATA, + (void *)&req); + if (req.dv_enhance_exist) + return true; + if (!req.aux_buf || !req.aux_size) + return 0; + p = req.aux_buf; + while (p < req.aux_buf + req.aux_size - 8) { + size = *p++; + size = (size << 8) | *p++; + size = (size << 8) | *p++; + size = (size << 8) | *p++; + type = *p++; + type = (type << 8) | *p++; + type = (type << 8) | *p++; + type = (type << 8) | *p++; + if (type == 0x01000000) + return true; + p += size; + } + return false; +} + +/* 0: no el; >0: with el */ +/* 1: need wait el vf */ +/* 2: no match el found */ +/* 3: found match el */ +int dolby_vision_wait_metadata(struct vframe_s *vf) +{ + struct provider_aux_req_s req; + struct vframe_s *el_vf; + int ret = 0; + unsigned int mode; + + if (debug_dolby & 0x80) { + if (dolby_vision_flags & FLAG_SINGLE_STEP) + /* wait fake el for "step" */ + return 1; + + dolby_vision_flags |= FLAG_SINGLE_STEP; + } + req.vf = vf; + req.bot_flag = 0; + req.aux_buf = NULL; + req.aux_size = 0; + req.dv_enhance_exist = 0; + vf_notify_provider_by_name("dvbldec", + VFRAME_EVENT_RECEIVER_GET_AUX_DATA, + (void *)&req); + if (req.dv_enhance_exist) { + el_vf = dvel_vf_peek(); + while (el_vf) { + if (debug_dolby & 2) + pr_dolby_dbg("=== peek bl(%p-%lld) with el(%p-%lld) ===\n", + vf, vf->pts_us64, + el_vf, el_vf->pts_us64); + if ((el_vf->pts_us64 == vf->pts_us64) + || !(dolby_vision_flags & FLAG_CHECK_ES_PTS)) { + /* found el */ + ret = 3; + break; + } else if (el_vf->pts_us64 < vf->pts_us64) { + if (debug_dolby & 2) + pr_dolby_dbg("bl(%p-%lld) => skip el pts(%p-%lld)\n", + vf, vf->pts_us64, + el_vf, el_vf->pts_us64); + el_vf = dvel_vf_get(); + dvel_vf_put(el_vf); + vf_notify_provider(DVEL_RECV_NAME, + VFRAME_EVENT_RECEIVER_PUT, NULL); + if (debug_dolby & 2) { + pr_dolby_dbg("=== get & put el(%p-%lld) ===\n", + el_vf, el_vf->pts_us64); + } + /* skip old el and peek new */ + el_vf = dvel_vf_peek(); + } else { + /* no el found */ + ret = 2; + break; + } + } + /* need wait el */ + if (el_vf == NULL) { + pr_dolby_dbg("=== bl wait el(%p-%lld) ===\n", + vf, vf->pts_us64); + ret = 1; + } + } + if (is_dovi_frame(vf) && !dolby_vision_on) { + /* dovi source, but dovi not enabled */ + mode = dolby_vision_mode; + if (dolby_vision_policy_process( + &mode, FORMAT_DOVI)) { + dolby_vision_set_toggle_flag(1); + if ((mode != DOLBY_VISION_OUTPUT_MODE_BYPASS) + && (dolby_vision_mode == + DOLBY_VISION_OUTPUT_MODE_BYPASS)) + dolby_vision_wait_on = true; + dolby_vision_mode = mode; + ret = 1; + } + } + return ret; +} + +void dolby_vision_vf_put(struct vframe_s *vf) +{ + int i; + + if (vf) + for (i = 0; i < 16; i++) { + if (dv_vf[i][0] == vf) { + if (dv_vf[i][1]) { + if (debug_dolby & 2) + pr_dolby_dbg("--- put bl(%p-%lld) with el(%p-%lld) ---\n", + vf, vf->pts_us64, + dv_vf[i][1], + dv_vf[i][1]->pts_us64); + dvel_vf_put(dv_vf[i][1]); + } else if (debug_dolby & 2) { + pr_dolby_dbg("--- put bl(%p-%lld) ---\n", + vf, vf->pts_us64); + } + dv_vf[i][0] = NULL; + dv_vf[i][1] = NULL; + } + } +} +EXPORT_SYMBOL(dolby_vision_vf_put); + +struct vframe_s *dolby_vision_vf_peek_el(struct vframe_s *vf) +{ + int i; + + if (dolby_vision_flags) { + for (i = 0; i < 16; i++) { + if (dv_vf[i][0] == vf) { + if (dv_vf[i][1] + && (dolby_vision_status == BYPASS_PROCESS)) + dv_vf[i][1]->type |= VIDTYPE_VD2; + return dv_vf[i][1]; + } + } + } + return NULL; +} +EXPORT_SYMBOL(dolby_vision_vf_peek_el); + +static void dolby_vision_vf_add(struct vframe_s *vf, struct vframe_s *el_vf) +{ + int i; + + for (i = 0; i < 16; i++) { + if (dv_vf[i][0] == NULL) { + dv_vf[i][0] = vf; + dv_vf[i][1] = el_vf; + break; + } + } +} + +static int dolby_vision_vf_check(struct vframe_s *vf) +{ + int i; + + for (i = 0; i < 16; i++) { + if (dv_vf[i][0] == vf) { + if (debug_dolby & 2) { + if (dv_vf[i][1]) + pr_dolby_dbg("=== bl(%p-%lld) with el(%p-%lld) toggled ===\n", + vf, + vf->pts_us64, + dv_vf[i][1], + dv_vf[i][1]->pts_us64); + else + pr_dolby_dbg("=== bl(%p-%lld) toggled ===\n", + vf, + vf->pts_us64); + } + return 0; + } + } + return 1; +} + +static int parse_sei_and_meta( + struct vframe_s *vf, + struct provider_aux_req_s *req, + int *total_comp_size, + int *total_md_size, + enum signal_format_e *src_format) +{ + int i; + char *p; + unsigned int size = 0; + unsigned int type = 0; + int md_size = 0; + int comp_size = 0; + int parser_ready = 0; + int ret = 2; + unsigned long flags; + + if ((req->aux_buf == NULL) + || (req->aux_size == 0)) + return 1; + + p = req->aux_buf; + while (p < req->aux_buf + req->aux_size - 8) { + size = *p++; + size = (size << 8) | *p++; + size = (size << 8) | *p++; + size = (size << 8) | *p++; + type = *p++; + type = (type << 8) | *p++; + type = (type << 8) | *p++; + type = (type << 8) | *p++; + + if (type == 0x01000000) { + /* source is VS10 */ + *src_format = FORMAT_DOVI; + meta_buf[0] = meta_buf[1] = meta_buf[2] = 0; + memcpy(&meta_buf[3], p+1, size-1); + if ((debug_dolby & 4) && dump_enable) { + pr_dolby_dbg("metadata(%d):\n", size); + for (i = 0; i < size+2; i += 8) + pr_info("\t%02x %02x %02x %02x %02x %02x %02x %02x\n", + meta_buf[i], + meta_buf[i+1], + meta_buf[i+2], + meta_buf[i+3], + meta_buf[i+4], + meta_buf[i+5], + meta_buf[i+6], + meta_buf[i+7]); + } + + /* prepare metadata parser */ + parser_ready = 0; + if (metadata_parser == NULL) { + metadata_parser = + p_funcs->metadata_parser_init( + dolby_vision_flags + & FLAG_CHANGE_SEQ_HEAD + ? 1 : 0); + p_funcs->metadata_parser_reset(1); + if (metadata_parser != NULL) { + parser_ready = 1; + pr_dolby_dbg("metadata parser init OK\n"); + } + } else { + if (p_funcs->metadata_parser_reset( + metadata_parser_reset_flag) == 0) + metadata_parser_reset_flag = 0; + parser_ready = 1; + } + if (!parser_ready) { + pr_dolby_error( + "meta(%d), pts(%lld) -> metadata parser init fail\n", + size, vf->pts_us64); + return 2; + } + + md_size = comp_size = 0; + spin_lock_irqsave(&dovi_lock, flags); + if (p_funcs->metadata_parser_process( + meta_buf, size + 2, + comp_buf + *total_comp_size, + &comp_size, + md_buf + *total_md_size, + &md_size, + true)) { + pr_dolby_error( + "meta(%d), pts(%lld) -> metadata parser process fail\n", + size, vf->pts_us64); + ret = 2; + } else { + *total_comp_size += comp_size; + *total_md_size += md_size; + ret = 0; + } + spin_unlock_irqrestore(&dovi_lock, flags); + } + p += size; + } + if (*total_md_size) { + pr_dolby_dbg( + "meta(%d), pts(%lld) -> md(%d), comp(%d)\n", + size, vf->pts_us64, + *total_md_size, *total_comp_size); + if ((debug_dolby & 8) && dump_enable) { + pr_dolby_dbg("parsed md(%d):\n", *total_md_size); + for (i = 0; i < *total_md_size + 7; i += 8) { + pr_info("\t%02x %02x %02x %02x %02x %02x %02x %02x\n", + md_buf[i], + md_buf[i+1], + md_buf[i+2], + md_buf[i+3], + md_buf[i+4], + md_buf[i+5], + md_buf[i+6], + md_buf[i+7]); + } + } + } + return ret; +} + +#define INORM 50000 +static u32 bt2020_primaries[3][2] = { + {0.17 * INORM + 0.5, 0.797 * INORM + 0.5}, /* G */ + {0.131 * INORM + 0.5, 0.046 * INORM + 0.5}, /* B */ + {0.708 * INORM + 0.5, 0.292 * INORM + 0.5}, /* R */ +}; + +static u32 bt2020_white_point[2] = { + 0.3127 * INORM + 0.5, 0.3290 * INORM + 0.5 +}; + +void prepare_hdr10_param( + struct vframe_master_display_colour_s *p_mdc, + struct hdr10_param_s *p_hdr10_param) +{ + struct vframe_content_light_level_s *p_cll = + &p_mdc->content_light_level; + bool flag = false; + uint32_t max_lum = 1000 * 10000; + uint32_t min_lum = 50; + + if ((p_mdc->present_flag) + && !(dolby_vision_flags & FLAG_CERTIFICAION)) { + if (p_mdc->luminance[0]) + max_lum = p_mdc->luminance[0]; + if (p_mdc->luminance[1]) + min_lum = p_mdc->luminance[1]; + if ((p_hdr10_param-> + max_display_mastering_luminance + != max_lum) + || (p_hdr10_param-> + min_display_mastering_luminance + != min_lum) + || (p_hdr10_param->Rx + != p_mdc->primaries[2][0]) + || (p_hdr10_param->Ry + != p_mdc->primaries[2][1]) + || (p_hdr10_param->Gx + != p_mdc->primaries[0][0]) + || (p_hdr10_param->Gy + != p_mdc->primaries[0][1]) + || (p_hdr10_param->Bx + != p_mdc->primaries[1][0]) + || (p_hdr10_param->By + != p_mdc->primaries[1][1]) + || (p_hdr10_param->Wx + != p_mdc->white_point[0]) + || (p_hdr10_param->Wy + != p_mdc->white_point[1])) + flag = true; + if (true) { + p_hdr10_param-> + max_display_mastering_luminance + = max_lum; + p_hdr10_param-> + min_display_mastering_luminance + = min_lum; + p_hdr10_param->Rx + = p_mdc->primaries[2][0]; + p_hdr10_param->Ry + = p_mdc->primaries[2][1]; + p_hdr10_param->Gx + = p_mdc->primaries[0][0]; + p_hdr10_param->Gy + = p_mdc->primaries[0][1]; + p_hdr10_param->Bx + = p_mdc->primaries[1][0]; + p_hdr10_param->By + = p_mdc->primaries[1][1]; + p_hdr10_param->Wx + = p_mdc->white_point[0]; + p_hdr10_param->Wy + = p_mdc->white_point[1]; + } + } else { + if ((p_hdr10_param-> + min_display_mastering_luminance + != max_lum) + || (p_hdr10_param-> + max_display_mastering_luminance + != min_lum) + || (p_hdr10_param->Rx + != bt2020_primaries[2][0]) + || (p_hdr10_param->Ry + != bt2020_primaries[2][1]) + || (p_hdr10_param->Gx + != bt2020_primaries[0][0]) + || (p_hdr10_param->Gy + != bt2020_primaries[0][1]) + || (p_hdr10_param->Bx + != bt2020_primaries[1][0]) + || (p_hdr10_param->By + != bt2020_primaries[1][1]) + || (p_hdr10_param->Wx + != bt2020_white_point[0]) + || (p_hdr10_param->Wy + != bt2020_white_point[1])) + flag = true; + if (true) { + p_hdr10_param-> + min_display_mastering_luminance + = min_lum; + p_hdr10_param-> + max_display_mastering_luminance + = max_lum; + p_hdr10_param->Rx + = bt2020_primaries[2][0]; + p_hdr10_param->Ry + = bt2020_primaries[2][1]; + p_hdr10_param->Gx + = bt2020_primaries[0][0]; + p_hdr10_param->Gy + = bt2020_primaries[0][1]; + p_hdr10_param->Bx + = bt2020_primaries[1][0]; + p_hdr10_param->By + = bt2020_primaries[1][1]; + p_hdr10_param->Wx + = bt2020_white_point[0]; + p_hdr10_param->Wy + = bt2020_white_point[1]; + } + } + + if (p_cll->present_flag) { + if ((p_hdr10_param->max_content_light_level + != p_cll->max_content) + || (p_hdr10_param->max_pic_average_light_level + != p_cll->max_pic_average)) + flag = true; + if (flag) { + p_hdr10_param->max_content_light_level + = p_cll->max_content; + p_hdr10_param->max_pic_average_light_level + = p_cll->max_pic_average; + } + } else { + if ((p_hdr10_param->max_content_light_level != 0) + || (p_hdr10_param->max_pic_average_light_level != 0)) + flag = true; + if (true) { + p_hdr10_param->max_content_light_level = 0; + p_hdr10_param->max_pic_average_light_level = 0; + } + } + + if (flag) { + pr_dolby_dbg("HDR10:\n"); + pr_dolby_dbg("\tR = %04x, %04x\n", + p_hdr10_param->Rx, + p_hdr10_param->Ry); + pr_dolby_dbg("\tG = %04x, %04x\n", + p_hdr10_param->Gx, + p_hdr10_param->Gy); + pr_dolby_dbg("\tB = %04x, %04x\n", + p_hdr10_param->Bx, + p_hdr10_param->By); + pr_dolby_dbg("\tW = %04x, %04x\n", + p_hdr10_param->Wx, + p_hdr10_param->Wy); + pr_dolby_dbg("\tMax = %d\n", + p_hdr10_param-> + max_display_mastering_luminance); + pr_dolby_dbg("\tMin = %d\n", + p_hdr10_param-> + min_display_mastering_luminance); + pr_dolby_dbg("\tMCLL = %d\n", + p_hdr10_param-> + max_content_light_level); + pr_dolby_dbg("\tMPALL = %d\n\n", + p_hdr10_param-> + max_pic_average_light_level); + } +} + +static bool send_hdmi_pkt( + enum signal_format_e dst_format, + const struct vinfo_s *vinfo) +{ + struct hdr_10_infoframe_s *p_hdr; + int i; + bool flag = false; + + if (dst_format == FORMAT_HDR10) { + p_hdr = &dovi_setting.hdr_info; + hdr10_data.features = + (1 << 29) /* video available */ + | (5 << 26) /* unspecified */ + | (0 << 25) /* limit */ + | (1 << 24) /* color available */ + | (9 << 16) /* bt2020 */ + | (14 << 8) /* bt2020-10 */ + | (10 << 0);/* bt2020c */ + if (hdr10_data.primaries[0][0] != + ((p_hdr->display_primaries_x_0_MSB << 8) + | p_hdr->display_primaries_x_0_LSB)) + flag = true; + hdr10_data.primaries[0][0] = + (p_hdr->display_primaries_x_0_MSB << 8) + | p_hdr->display_primaries_x_0_LSB; + + if (hdr10_data.primaries[0][1] != + ((p_hdr->display_primaries_y_0_MSB << 8) + | p_hdr->display_primaries_y_0_LSB)) + flag = true; + hdr10_data.primaries[0][1] = + (p_hdr->display_primaries_y_0_MSB << 8) + | p_hdr->display_primaries_y_0_LSB; + + if (hdr10_data.primaries[1][0] != + ((p_hdr->display_primaries_x_1_MSB << 8) + | p_hdr->display_primaries_x_1_LSB)) + flag = true; + hdr10_data.primaries[1][0] = + (p_hdr->display_primaries_x_1_MSB << 8) + | p_hdr->display_primaries_x_1_LSB; + + if (hdr10_data.primaries[1][1] != + ((p_hdr->display_primaries_y_1_MSB << 8) + | p_hdr->display_primaries_y_1_LSB)) + flag = true; + hdr10_data.primaries[1][1] = + (p_hdr->display_primaries_y_1_MSB << 8) + | p_hdr->display_primaries_y_1_LSB; + + if (hdr10_data.primaries[2][0] != + ((p_hdr->display_primaries_x_2_MSB << 8) + | p_hdr->display_primaries_x_2_LSB)) + flag = true; + hdr10_data.primaries[2][0] = + (p_hdr->display_primaries_x_2_MSB << 8) + | p_hdr->display_primaries_x_2_LSB; + + if (hdr10_data.primaries[2][1] != + ((p_hdr->display_primaries_y_2_MSB << 8) + | p_hdr->display_primaries_y_2_LSB)) + flag = true; + hdr10_data.primaries[2][1] = + (p_hdr->display_primaries_y_2_MSB << 8) + | p_hdr->display_primaries_y_2_LSB; + + if (hdr10_data.white_point[0] != + ((p_hdr->white_point_x_MSB << 8) + | p_hdr->white_point_x_LSB)) + flag = true; + hdr10_data.white_point[0] = + (p_hdr->white_point_x_MSB << 8) + | p_hdr->white_point_x_LSB; + + if (hdr10_data.white_point[1] != + ((p_hdr->white_point_y_MSB << 8) + | p_hdr->white_point_y_LSB)) + flag = true; + hdr10_data.white_point[1] = + (p_hdr->white_point_y_MSB << 8) + | p_hdr->white_point_y_LSB; + + if (hdr10_data.luminance[0] != + ((p_hdr->max_display_mastering_luminance_MSB << 8) + | p_hdr->max_display_mastering_luminance_LSB)) + flag = true; + hdr10_data.luminance[0] = + (p_hdr->max_display_mastering_luminance_MSB << 8) + | p_hdr->max_display_mastering_luminance_LSB; + + if (hdr10_data.luminance[1] != + ((p_hdr->min_display_mastering_luminance_MSB << 8) + | p_hdr->min_display_mastering_luminance_LSB)) + flag = true; + hdr10_data.luminance[1] = + (p_hdr->min_display_mastering_luminance_MSB << 8) + | p_hdr->min_display_mastering_luminance_LSB; + + if (hdr10_data.max_content != + ((p_hdr->max_content_light_level_MSB << 8) + | p_hdr->max_content_light_level_LSB)) + flag = true; + hdr10_data.max_content = + (p_hdr->max_content_light_level_MSB << 8) + | p_hdr->max_content_light_level_LSB; + + if (hdr10_data.max_frame_average != + ((p_hdr->max_frame_average_light_level_MSB << 8) + | p_hdr->max_frame_average_light_level_LSB)) + flag = true; + hdr10_data.max_frame_average = + (p_hdr->max_frame_average_light_level_MSB << 8) + | p_hdr->max_frame_average_light_level_LSB; + if (vinfo->fresh_tx_hdr_pkt) + vinfo->fresh_tx_hdr_pkt(&hdr10_data); + if (vinfo->fresh_tx_vsif_pkt) + vinfo->fresh_tx_vsif_pkt(0, 0); + + if (flag) { + pr_dolby_dbg("Info frame for hdr10 changed:\n"); + for (i = 0; i < 3; i++) + pr_dolby_dbg( + "\tprimaries[%1d] = %04x, %04x\n", + i, + hdr10_data.primaries[i][0], + hdr10_data.primaries[i][1]); + pr_dolby_dbg("\twhite_point = %04x, %04x\n", + hdr10_data.white_point[0], + hdr10_data.white_point[1]); + pr_dolby_dbg("\tMax = %d\n", + hdr10_data.luminance[0]); + pr_dolby_dbg("\tMin = %d\n", + hdr10_data.luminance[1]); + pr_dolby_dbg("\tMCLL = %d\n", + hdr10_data.max_content); + pr_dolby_dbg("\tMPALL = %d\n\n", + hdr10_data.max_frame_average); + } + } else if (dst_format == FORMAT_DOVI) { + hdr10_data.features = + (1 << 29) /* video available */ + | (5 << 26) /* unspecified */ + | (0 << 25) /* limit */ + | (1 << 24) /* color available */ + | (1 << 16) /* bt709 */ + | (1 << 8) /* bt709 */ + | (1 << 0); /* bt709 */ + for (i = 0; i < 3; i++) { + hdr10_data.primaries[i][0] = 0; + hdr10_data.primaries[i][1] = 0; + } + hdr10_data.white_point[0] = 0; + hdr10_data.white_point[1] = 0; + hdr10_data.luminance[0] = 0; + hdr10_data.luminance[1] = 0; + hdr10_data.max_content = 0; + hdr10_data.max_frame_average = 0; + if (vinfo->fresh_tx_hdr_pkt) + vinfo->fresh_tx_hdr_pkt(&hdr10_data); + if (vinfo->fresh_tx_vsif_pkt) + vinfo->fresh_tx_vsif_pkt( + 1, dolby_vision_mode == + DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL + ? 1 : 0); + } else { + hdr10_data.features = + (1 << 29) /* video available */ + | (5 << 26) /* unspecified */ + | (0 << 25) /* limit */ + | (1 << 24) /* color available */ + | (1 << 16) /* bt709 */ + | (1 << 8) /* bt709 */ + | (1 << 0); /* bt709 */ + for (i = 0; i < 3; i++) { + hdr10_data.primaries[i][0] = 0; + hdr10_data.primaries[i][1] = 0; + } + hdr10_data.white_point[0] = 0; + hdr10_data.white_point[1] = 0; + hdr10_data.luminance[0] = 0; + hdr10_data.luminance[1] = 0; + hdr10_data.max_content = 0; + hdr10_data.max_frame_average = 0; + if (vinfo->fresh_tx_hdr_pkt) + vinfo->fresh_tx_hdr_pkt(&hdr10_data); + if (vinfo->fresh_tx_vsif_pkt) + vinfo->fresh_tx_vsif_pkt(0, 0); + } + return flag; +} + +static uint32_t null_vf_cnt; +static bool video_off_handled; +static int is_video_output_off(struct vframe_s *vf) +{ + if ((READ_VPP_REG(VPP_MISC) & (1<<10)) == 0) { + if (vf == NULL) + null_vf_cnt++; + else + null_vf_cnt = 0; + if (null_vf_cnt > 5) { + null_vf_cnt = 0; + return 1; + } + } else + video_off_handled = 0; + return 0; +} + +#define signal_color_primaries ((vf->signal_type >> 16) & 0xff) +#define signal_transfer_characteristic ((vf->signal_type >> 8) & 0xff) +static int dolby_vision_parse_metadata(struct vframe_s *vf) +{ + const struct vinfo_s *vinfo = get_current_vinfo(); + struct vframe_s *el_vf; + struct provider_aux_req_s req; + struct provider_aux_req_s el_req; + int flag; + enum signal_format_e src_format = FORMAT_SDR; + enum signal_format_e dst_format; + int total_md_size = 0; + int total_comp_size = 0; + bool el_flag = 0; + bool el_halfsize_flag = 1; + uint32_t w = vinfo->width; + uint32_t h = vinfo->height; + int meta_flag_bl = 1; + int meta_flag_el = 1; + struct vframe_master_display_colour_s *p_mdc = + &vf->prop.master_display_colour; + unsigned int current_mode = dolby_vision_mode; + uint32_t target_lumin_max = 0; + + if ((!dolby_vision_enable) || (!p_funcs)) + return -1; + + if (vf) { + pr_dolby_dbg("frame %d pts %lld:\n", frame_count, vf->pts_us64); + + /* check source format */ + if (signal_transfer_characteristic == 16) + video_is_hdr10 = true; + else + video_is_hdr10 = false; + + if (video_is_hdr10 || p_mdc->present_flag) + src_format = FORMAT_HDR10; + + /* prepare parameter from SEI for hdr10 */ + if (src_format == FORMAT_HDR10) + prepare_hdr10_param(p_mdc, &hdr10_param); + + req.vf = vf; + req.bot_flag = 0; + req.aux_buf = NULL; + req.aux_size = 0; + req.dv_enhance_exist = 0; + vf_notify_provider_by_name("dvbldec", + VFRAME_EVENT_RECEIVER_GET_AUX_DATA, + (void *)&req); + /* parse meta in base layer */ + if (dolby_vision_flags & FLAG_META_FROM_BL) + meta_flag_bl = parse_sei_and_meta( + vf, &req, + &total_comp_size, &total_md_size, + &src_format); + if (req.dv_enhance_exist) { + el_vf = dvel_vf_get(); + if (el_vf && + ((el_vf->pts_us64 == vf->pts_us64) + || !(dolby_vision_flags & FLAG_CHECK_ES_PTS))) { + if (debug_dolby & 2) + pr_dolby_dbg("+++ get bl(%p-%lld) with el(%p-%lld) +++\n", + vf, vf->pts_us64, + el_vf, el_vf->pts_us64); + el_req.vf = el_vf; + el_req.bot_flag = 0; + el_req.aux_buf = NULL; + el_req.aux_size = 0; + vf_notify_provider_by_name("dveldec", + VFRAME_EVENT_RECEIVER_GET_AUX_DATA, + (void *)&el_req); + /* parse meta in enhanced layer */ + if (!(dolby_vision_flags & FLAG_META_FROM_BL)) + meta_flag_el = parse_sei_and_meta( + el_vf, &el_req, + &total_comp_size, + &total_md_size, + &src_format); + dolby_vision_vf_add(vf, el_vf); + if (dolby_vision_flags) { + el_flag = 1; + if (vf->width == el_vf->width) + el_halfsize_flag = 0; + } + } else { + if (!el_vf) + pr_dolby_error( + "bl(%p-%lld) not found el\n", + vf, vf->pts_us64); + else + pr_dolby_error( + "bl(%p-%lld) not found el(%p-%lld)\n", + vf, vf->pts_us64, + el_vf, el_vf->pts_us64); + } + } else { + if (debug_dolby & 2) + pr_dolby_dbg( + "+++ get bl(%p-%lld) +++\n", + vf, vf->pts_us64); + dolby_vision_vf_add(vf, NULL); + } + if ((src_format == FORMAT_DOVI) + && meta_flag_bl && meta_flag_el) { + /* dovi frame no meta or meta error */ + /* use old setting for this frame */ + return -1; + } + w = (vf->type & VIDTYPE_COMPRESS) ? + vf->compWidth : vf->width; + h = (vf->type & VIDTYPE_COMPRESS) ? + vf->compHeight : vf->height; + } + + /* if not DOVI, release metadata_parser */ + if ((src_format != FORMAT_DOVI) && metadata_parser) { + p_funcs->metadata_parser_release(); + metadata_parser = NULL; + } + + current_mode = dolby_vision_mode; + if (dolby_vision_policy_process( + ¤t_mode, src_format)) { + dolby_vision_set_toggle_flag(1); + if ((current_mode != DOLBY_VISION_OUTPUT_MODE_BYPASS) + && (dolby_vision_mode == DOLBY_VISION_OUTPUT_MODE_BYPASS)) + dolby_vision_wait_on = true; + dolby_vision_mode = current_mode; + } + + if (dolby_vision_mode == DOLBY_VISION_OUTPUT_MODE_BYPASS) { + new_dovi_setting.video_width = 0; + new_dovi_setting.video_height = 0; + return -1; + } + + /* check target luminance */ + if (is_graphics_output_off()) { + dolby_vision_graphic_min = 0; + dolby_vision_graphic_max = 0; + } else { + dolby_vision_graphic_min = 50; + dolby_vision_graphic_max = 100; + } + if (dolby_vision_flags & FLAG_USE_SINK_MIN_MAX) { + if (vinfo->dv_info->ieeeoui == 0x00d046) { + if (vinfo->dv_info->ver == 0) { + /* need lookup PQ table ... */ + /*dolby_vision_graphic_min =*/ + /*dolby_vision_target_min =*/ + /* vinfo->dv_info.ver0.target_min_pq;*/ + /*dolby_vision_graphic_max =*/ + /*target_lumin_max =*/ + /* vinfo->dv_info.ver0.target_max_pq;*/ + } else if (vinfo->dv_info->ver == 1) { + if (vinfo->dv_info->vers.ver1.target_max_lum) { + /* Target max luminance = 100+50*CV */ + dolby_vision_graphic_max = + target_lumin_max = + (vinfo->dv_info-> + vers.ver1.target_max_lum + * 50 + 100); + /* Target min luminance = (CV/127)^2 */ + dolby_vision_graphic_min = + dolby_vision_target_min = + (vinfo->dv_info-> + vers.ver1.target_min_lum ^ 2) + * 10000 / (127 * 127); + } + } + } else if (vinfo->hdr_info.hdr_support & 4) { + if (vinfo->hdr_info.lumi_max) { + /* Luminance value = 50 * (2 ^ (CV/32)) */ + dolby_vision_graphic_max = + target_lumin_max = 50 * + (2 ^ (vinfo->hdr_info.lumi_max >> 5)); + /* Desired Content Min Luminance =*/ + /*Desired Content Max Luminance*/ + /* (CV/255) * (CV/255) / 100 */ + dolby_vision_graphic_min = + dolby_vision_target_min = + target_lumin_max * 10000 + * vinfo->hdr_info.lumi_min + * vinfo->hdr_info.lumi_min + / (255 * 255 * 100); + } + } + if (target_lumin_max) { + dolby_vision_target_max[0][0] = + dolby_vision_target_max[0][1] = + dolby_vision_target_max[1][0] = + dolby_vision_target_max[1][1] = + dolby_vision_target_max[2][0] = + dolby_vision_target_max[2][1] = + target_lumin_max; + } else { + memcpy( + dolby_vision_target_max, + dolby_vision_default_max, + sizeof(dolby_vision_target_max)); + } + } + + /* check dst format */ + if ((dolby_vision_mode == DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL) + || (dolby_vision_mode == DOLBY_VISION_OUTPUT_MODE_IPT)) + dst_format = FORMAT_DOVI; + else if (dolby_vision_mode == DOLBY_VISION_OUTPUT_MODE_HDR10) + dst_format = FORMAT_HDR10; + else + dst_format = FORMAT_SDR; + + new_dovi_setting.video_width = w << 16; + new_dovi_setting.video_height = h << 16; + flag = p_funcs->control_path( + src_format, dst_format, + comp_buf, total_comp_size, + md_buf, total_md_size, + VIDEO_PRIORITY, + 12, 0, SIG_RANGE_SMPTE, /* bit/chroma/range */ + dolby_vision_graphic_min, + dolby_vision_graphic_max * 10000, + dolby_vision_target_min, + dolby_vision_target_max[src_format][dst_format] * 10000, + (!el_flag) || + (dolby_vision_flags & FLAG_DISABLE_COMPOSER), + &hdr10_param, + &new_dovi_setting); + if (flag >= 0) { + new_dovi_setting.src_format = src_format; + new_dovi_setting.dst_format = dst_format; + new_dovi_setting.el_flag = el_flag; + new_dovi_setting.el_halfsize_flag = el_halfsize_flag; + new_dovi_setting.video_width = w; + new_dovi_setting.video_height = h; + if (el_flag) + pr_dolby_dbg("setting %d->%d(T:%d-%d): flag=%02x,md_%s=%d,comp=%d\n", + src_format, dst_format, + dolby_vision_target_min, + dolby_vision_target_max[src_format][dst_format], + flag, meta_flag_bl ? "el" : "bl", + total_md_size, total_comp_size); + else + pr_dolby_dbg("setting %d->%d(T:%d-%d): flag=%02x,md_%s=%d\n", + src_format, dst_format, + dolby_vision_target_min, + dolby_vision_target_max[src_format][dst_format], + flag, meta_flag_bl ? "el" : "bl", + total_md_size); + dump_setting(&new_dovi_setting, frame_count, debug_dolby); + return 0; /* setting updated */ + } + + new_dovi_setting.video_width = 0; + new_dovi_setting.video_height = 0; + pr_dolby_error("control_path() failed\n"); + + return -1; /* do nothing for this frame */ +} + +int dolby_vision_update_metadata(struct vframe_s *vf) +{ + int ret = -1; + + if (!dolby_vision_enable) + return -1; + + if (vf && dolby_vision_vf_check(vf)) { + ret = dolby_vision_parse_metadata(vf); + frame_count++; + } + + return ret; +} +EXPORT_SYMBOL(dolby_vision_update_metadata); + +static unsigned int last_dolby_vision_policy; +int dolby_vision_process(struct vframe_s *vf) +{ + const struct vinfo_s *vinfo = get_current_vinfo(); + + if (get_cpu_type() != MESON_CPU_MAJOR_ID_GXM) + return -1; + + if ((!dolby_vision_enable) || (!p_funcs)) + return -1; + + if (is_dolby_vision_on() + && is_video_output_off(vf) + && !video_off_handled) { + dolby_vision_set_toggle_flag(1); + pr_dolby_dbg("video off\n"); + if (debug_dolby) + video_off_handled = 1; + } + + if (last_dolby_vision_policy != dolby_vision_policy) { + /* handle policy change */ + dolby_vision_set_toggle_flag(1); + last_dolby_vision_policy = dolby_vision_policy; + } else if (dolby_vision_mode == DOLBY_VISION_OUTPUT_MODE_BYPASS) { + if (dolby_vision_status != BYPASS_PROCESS) { + enable_dolby_vision(0); + send_hdmi_pkt(FORMAT_SDR, vinfo); + if (dolby_vision_flags & FLAG_TOGGLE_FRAME) + dolby_vision_flags &= ~FLAG_TOGGLE_FRAME; + } + return 0; + } + + if (!vf) { + if ((dolby_vision_flags & FLAG_TOGGLE_FRAME)) + dolby_vision_parse_metadata(NULL); + } + if (dolby_vision_flags & FLAG_RESET_EACH_FRAME) + dolby_vision_set_toggle_flag(1); + + if (dolby_vision_flags & FLAG_TOGGLE_FRAME) { + if ((new_dovi_setting.video_width & 0xffff) + && (new_dovi_setting.video_height & 0xffff)) { + memcpy(&dovi_setting, &new_dovi_setting, + sizeof(dovi_setting)); + new_dovi_setting.video_width = + new_dovi_setting.video_height = 0; + } + dolby_core1_set( + 24, 173, 256 * 5, + (uint32_t *)&dovi_setting.dm_reg1, + (uint32_t *)&dovi_setting.comp_reg, + (uint32_t *)&dovi_setting.dm_lut1, + dovi_setting.video_width, + dovi_setting.video_height, + 1, /* BL enable */ + dovi_setting.el_flag, /* EL enable */ + dovi_setting.el_halfsize_flag, /* if BL and EL is 4:1 */ + dolby_vision_mode == + DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL, + dovi_setting.src_format == FORMAT_DOVI, + 1); + dolby_core2_set( + 24, 256 * 5, + (uint32_t *)&dovi_setting.dm_reg2, + (uint32_t *)&dovi_setting.dm_lut2, + 1920, 1080, 1, 1); + dolby_core3_set( + 26, dovi_setting.md_reg3.size, + (uint32_t *)&dovi_setting.dm_reg3, + dovi_setting.md_reg3.raw_metadata, + vinfo->width, vinfo->height, 1, + dolby_vision_mode == + DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL); + enable_dolby_vision(1); + /* update dolby_vision_status */ + if ((dovi_setting.src_format == FORMAT_DOVI) + && (dolby_vision_status != DV_PROCESS)) { + pr_dolby_dbg( + "Dolby Vision mode changed to DV_PROCESS %d\n", + dovi_setting.src_format); + dolby_vision_status = DV_PROCESS; + } else if ((dovi_setting.src_format == FORMAT_HDR10) + && (dolby_vision_status != HDR_PROCESS)) { + pr_dolby_dbg( + "Dolby Vision mode changed to HDR_PROCESS %d\n", + dovi_setting.src_format); + dolby_vision_status = HDR_PROCESS; + } else if ((dovi_setting.src_format == FORMAT_SDR) + && (dolby_vision_status != SDR_PROCESS)) { + pr_dolby_dbg( + "Dolby Vision mode changed to SDR_PROCESS %d\n", + dovi_setting.src_format); + dolby_vision_status = SDR_PROCESS; + } + /* send HDMI packet according to dst_format */ + send_hdmi_pkt(dovi_setting.dst_format, vinfo); + dolby_vision_flags &= ~FLAG_TOGGLE_FRAME; + } + return 0; +} +EXPORT_SYMBOL(dolby_vision_process); + +bool is_dolby_vision_on(void) +{ + return dolby_vision_on + || dolby_vision_wait_on; +} +EXPORT_SYMBOL(is_dolby_vision_on); + +bool for_dolby_vision_certification(void) +{ + return is_dolby_vision_on() && + dolby_vision_flags & FLAG_CERTIFICAION; +} +EXPORT_SYMBOL(for_dolby_vision_certification); + +void dolby_vision_set_toggle_flag(int flag) +{ + if (flag) + dolby_vision_flags |= FLAG_TOGGLE_FRAME; + else + dolby_vision_flags &= ~FLAG_TOGGLE_FRAME; +} +EXPORT_SYMBOL(dolby_vision_set_toggle_flag); + +void set_dolby_vision_mode(int mode) +{ + if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXM) + && dolby_vision_enable) { + video_is_hdr10 = false; + if (dolby_vision_policy_process( + &mode, FORMAT_SDR)) { + dolby_vision_set_toggle_flag(1); + if ((mode != DOLBY_VISION_OUTPUT_MODE_BYPASS) + && (dolby_vision_mode == + DOLBY_VISION_OUTPUT_MODE_BYPASS)) + dolby_vision_wait_on = true; + pr_info("DOVI output change from %d to %d\n", + dolby_vision_mode, mode); + dolby_vision_mode = mode; + } + } +} +EXPORT_SYMBOL(set_dolby_vision_mode); + +int get_dolby_vision_mode(void) +{ + return dolby_vision_mode; +} +EXPORT_SYMBOL(get_dolby_vision_mode); + +bool is_dolby_vision_enable(void) +{ + return dolby_vision_enable; +} +EXPORT_SYMBOL(is_dolby_vision_enable); + +int register_dv_functions(const struct dolby_vision_func_s *func) +{ + int ret = -1; + + if (!p_funcs && func) { + pr_info("*** register_dv_functions\n ***"); + p_funcs = func; + ret = 0; + } + return ret; +} +EXPORT_SYMBOL(register_dv_functions); + +int unregister_dv_functions(void) +{ + int ret = -1; + + if (p_funcs) { + pr_info("*** unregister_dv_functions\n ***"); + p_funcs = NULL; + ret = 0; + } + return ret; +} +EXPORT_SYMBOL(unregister_dv_functions); diff --git a/drivers/amlogic/media/enhancement/amvecm/amve.c b/drivers/amlogic/media/enhancement/amvecm/amve.c new file mode 100644 index 0000000..784fa9e --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/amve.c @@ -0,0 +1,5304 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amve.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +/* #include */ +#include +#include +/* #include */ +#include +#include +#include +#include +#include +#include "arch/vpp_regs.h" +#include "arch/ve_regs.h" +#include "amve.h" +#include "amve_gamma_table.h" +#include "amvecm_vlock_regmap.h" +#include + +#define pr_amve_dbg(fmt, args...)\ + do {\ + if (dnlp_debug&0x1)\ + pr_info("AMVE: " fmt, ## args);\ + } while (0)\ +/* #define pr_amve_error(fmt, args...) */ +/* printk(KERN_##(KERN_INFO) "AMVECM: " fmt, ## args) */ + +#define GAMMA_RETRY 1000 + +/* 0: Invalid */ +/* 1: Valid */ +/* 2: Updated in 2D mode */ +/* 3: Updated in 3D mode */ +unsigned long flags; + +/* #if (MESON_CPU_TYPE>=MESON_CPU_TYPE_MESONG9TV) */ +#define NEW_DNLP_IN_SHARPNESS 2 +#define NEW_DNLP_IN_VPP 1 + +unsigned int dnlp_sel = NEW_DNLP_IN_VPP; +module_param(dnlp_sel, int, 0664); +MODULE_PARM_DESC(dnlp_sel, "dnlp_sel"); +/* #endif */ + +struct ve_hist_s video_ve_hist; + +static unsigned char ve_dnlp_tgt[64]; +bool ve_en; +unsigned int ve_dnlp_white_factor; +unsigned int ve_dnlp_rt; +unsigned int ve_dnlp_rl; +unsigned int ve_dnlp_black; +unsigned int ve_dnlp_white; +unsigned int ve_dnlp_luma_sum; +static ulong ve_dnlp_lpf[64], ve_dnlp_reg[16]; +static ulong ve_dnlp_reg_def[16] = { + 0x0b070400, 0x1915120e, 0x2723201c, 0x35312e2a, + 0x47423d38, 0x5b56514c, 0x6f6a6560, 0x837e7974, + 0x97928d88, 0xaba6a19c, 0xbfbab5b0, 0xcfccc9c4, + 0xdad7d5d2, 0xe6e3e0dd, 0xf2efece9, 0xfdfaf7f4 +}; + +/*static bool frame_lock_nosm = 1;*/ +static int ve_dnlp_waist_h = 128; +static int ve_dnlp_waist_l = 128; +static int ve_dnlp_ankle = 16; +static int ve_dnlp_strength = 255; +unsigned int vpp_log[128][10]; +struct ve_dnlp_s am_ve_dnlp; +struct ve_dnlp_table_s am_ve_new_dnlp; +#if 0 +static unsigned int lock_range_50hz_fast = 7; /* <= 14 */ +static unsigned int lock_range_50hz_slow = 7; /* <= 14 */ +static unsigned int lock_range_60hz_fast = 5; /* <= 4 */ +static unsigned int lock_range_60hz_slow = 2; /* <= 10 */ +#endif +struct tcon_gamma_table_s video_gamma_table_r; +struct tcon_gamma_table_s video_gamma_table_g; +struct tcon_gamma_table_s video_gamma_table_b; +struct tcon_gamma_table_s video_gamma_table_r_adj; +struct tcon_gamma_table_s video_gamma_table_g_adj; +struct tcon_gamma_table_s video_gamma_table_b_adj; +struct tcon_rgb_ogo_s video_rgb_ogo = { + 0, /* wb enable */ + 0, /* -1024~1023, r_pre_offset */ + 0, /* -1024~1023, g_pre_offset */ + 0, /* -1024~1023, b_pre_offset */ + 1024, /* 0~2047, r_gain */ + 1024, /* 0~2047, g_gain */ + 1024, /* 0~2047, b_gain */ + 0, /* -1024~1023, r_post_offset */ + 0, /* -1024~1023, g_post_offset */ + 0 /* -1024~1023, b_post_offset */ +}; + +#define FLAG_LVDS_FREQ_SW1 (1 << 6) + + +int amvecm_hiu_reg_read(unsigned int reg, unsigned int *val) +{ + *val = readl(amvecm_hiu_reg_base+((reg - 0x1000)<<2)); + return 0; +} + +int amvecm_hiu_reg_write(unsigned int reg, unsigned int val) +{ + writel(val, (amvecm_hiu_reg_base+((reg - 0x1000)<<2))); + return 0; +} +static int amvecm_hiu_reg_write_bits(unsigned int reg, unsigned int value, + unsigned int start, unsigned int len) +{ + unsigned int rd_val; + + amvecm_hiu_reg_read(reg, &rd_val); + amvecm_hiu_reg_write(reg, ((rd_val & + ~(((1L << (len)) - 1) << (start))) | + (((value) & ((1L << (len)) - 1)) << (start)))); + return 0; +} + + +module_param(ve_dnlp_waist_h, int, 0664); +MODULE_PARM_DESC(ve_dnlp_waist_h, "ve_dnlp_waist_h"); +module_param(ve_dnlp_waist_l, int, 0664); +MODULE_PARM_DESC(ve_dnlp_waist_l, "ve_dnlp_waist_l"); +module_param(ve_dnlp_ankle, int, 0664); +MODULE_PARM_DESC(ve_dnlp_ankle, "ve_dnlp_ankle"); +module_param(ve_dnlp_strength, int, 0664); +MODULE_PARM_DESC(ve_dnlp_strength, "ve_dnlp_strength"); + +static int dnlp_respond; +module_param(dnlp_respond, int, 0664); +MODULE_PARM_DESC(dnlp_respond, "dnlp_respond"); + +static int dnlp_debug; +module_param(dnlp_debug, int, 0664); +MODULE_PARM_DESC(dnlp_debug, "dnlp_debug"); + +static int ve_dnlp_method; +module_param(ve_dnlp_method, int, 0664); +MODULE_PARM_DESC(ve_dnlp_method, "ve_dnlp_method"); + +static int ve_dnlp_cliprate = 6; +module_param(ve_dnlp_cliprate, int, 0664); +MODULE_PARM_DESC(ve_dnlp_cliprate, "ve_dnlp_cliprate"); + +static int ve_dnlp_lowrange = 18; +module_param(ve_dnlp_lowrange, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lowrange, "ve_dnlp_lowrange"); + +static int ve_dnlp_hghrange = 18; +module_param(ve_dnlp_hghrange, int, 0664); +MODULE_PARM_DESC(ve_dnlp_hghrange, "ve_dnlp_hghrange"); + +static int ve_dnlp_auto_rng; +module_param(ve_dnlp_auto_rng, int, 0664); +MODULE_PARM_DESC(ve_dnlp_auto_rng, "ve_dnlp_auto_rng"); + +static int ve_dnlp_lowalpha = 24; +module_param(ve_dnlp_lowalpha, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lowalpha, "ve_dnlp_lowalpha"); + +static int ve_dnlp_midalpha = 24; +module_param(ve_dnlp_midalpha, int, 0664); +MODULE_PARM_DESC(ve_dnlp_midalpha, "ve_dnlp_midalpha"); + +static int ve_dnlp_hghalpha = 24; +module_param(ve_dnlp_hghalpha, int, 0664); +MODULE_PARM_DESC(ve_dnlp_hghalpha, "ve_dnlp_hghalpha"); + +static int dnlp_adj_level = 6; +module_param(dnlp_adj_level, int, 0664); +MODULE_PARM_DESC(dnlp_adj_level, "dnlp_adj_level"); + +int dnlp_en;/* 0:disabel;1:enable */ +module_param(dnlp_en, int, 0664); +MODULE_PARM_DESC(dnlp_en, "\n enable or disable dnlp\n"); +static int dnlp_status = 1;/* 0:done;1:todo */ + +int dnlp_en_2;/* 0:disabel;1:enable */ +module_param(dnlp_en_2, int, 0664); +MODULE_PARM_DESC(dnlp_en_2, "\n enable or disable dnlp\n"); + +static int frame_lock_freq; +module_param(frame_lock_freq, int, 0664); +MODULE_PARM_DESC(frame_lock_freq, "frame_lock_50"); + +static int video_rgb_ogo_mode_sw; +module_param(video_rgb_ogo_mode_sw, int, 0664); +MODULE_PARM_DESC(video_rgb_ogo_mode_sw, + "enable/disable video_rgb_ogo_mode_sw"); + +static int video_rgb_ogo_xvy_mtx = 1; +module_param(video_rgb_ogo_xvy_mtx, int, 0664); +MODULE_PARM_DESC(video_rgb_ogo_xvy_mtx, + "enable/disable video_rgb_ogo_xvy_mtx"); + +int video_rgb_ogo_xvy_mtx_latch = 1; + +static int ve_dnlp_adj_level = 6; +module_param(ve_dnlp_adj_level, int, 0664); +MODULE_PARM_DESC(ve_dnlp_adj_level, + "ve_dnlp_adj_level"); + +/* new dnlp start */ +/* larger -> slower */ +static int ve_dnlp_mvreflsh = 6; +module_param(ve_dnlp_mvreflsh, int, 0664); +MODULE_PARM_DESC(ve_dnlp_mvreflsh, + "ve_dnlp_mvreflsh"); + +static int ve_dnlp_gmma_rate = 82; +module_param(ve_dnlp_gmma_rate, int, 0664); +MODULE_PARM_DESC(ve_dnlp_gmma_rate, + "ve_dnlp_gmma_rate"); + +static int ve_dnlp_lowalpha_new = 40; +module_param(ve_dnlp_lowalpha_new, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lowalpha_new, + "ve_dnlp_lowalpha_new"); + +static int ve_dnlp_hghalpha_new = 28; +module_param(ve_dnlp_hghalpha_new, int, 0664); +MODULE_PARM_DESC(ve_dnlp_hghalpha_new, + "ve_dnlp_hghalpha_new"); + +static int ve_dnlp_cliprate_new = 36; +module_param(ve_dnlp_cliprate_new, int, 0664); +MODULE_PARM_DESC(ve_dnlp_cliprate_new, + "ve_dnlp_cliprate_new"); + +int ve_dnlp_sbgnbnd; +module_param(ve_dnlp_sbgnbnd, int, 0664); +MODULE_PARM_DESC(ve_dnlp_sbgnbnd, "ve_dnlp_sbgnbnd"); + +static int ve_dnlp_sendbnd; +module_param(ve_dnlp_sendbnd, int, 0664); +MODULE_PARM_DESC(ve_dnlp_sendbnd, "ve_dnlp_sendbnd"); + +int ve_dnlp_clashBgn; +module_param(ve_dnlp_clashBgn, int, 0664); +MODULE_PARM_DESC(ve_dnlp_clashBgn, "ve_dnlp_clashBgn"); + +static int ve_dnlp_clashEnd = 15; +module_param(ve_dnlp_clashEnd, int, 0664); +MODULE_PARM_DESC(ve_dnlp_clashEnd, "ve_dnlp_clashEnd"); + +static int ve_mtdbld_rate = 53; +module_param(ve_mtdbld_rate, int, 0664); +MODULE_PARM_DESC(ve_mtdbld_rate, "ve_mtdbld_rate"); + +static int ve_dnlp_pst_gmarat = 65; +module_param(ve_dnlp_pst_gmarat, int, 0664); +MODULE_PARM_DESC(ve_dnlp_pst_gmarat, "ve_dnlp_pst_gmarat"); + +/*dnlp method = 3, use this flag or no use*/ +bool ve_dnlp_respond_flag; +module_param(ve_dnlp_respond_flag, bool, 0664); +MODULE_PARM_DESC(ve_dnlp_respond_flag, + "ve_dnlp_respond_flag"); + +/*dnlp method = 3, check the same histogram*/ +bool ve_dnlp_smhist_ck; +module_param(ve_dnlp_smhist_ck, bool, 0664); +MODULE_PARM_DESC(ve_dnlp_smhist_ck, + "ve_dnlp_smhist_ck"); + +bool ve_dnlp_dbg_adjavg; +module_param(ve_dnlp_dbg_adjavg, bool, 0664); +MODULE_PARM_DESC(ve_dnlp_dbg_adjavg, + "ve_dnlp_dbg_adjavg"); + +int ve_dnlp_dbg_i2r = 255; +module_param(ve_dnlp_dbg_i2r, int, 0664); +MODULE_PARM_DESC(ve_dnlp_dbg_i2r, + "ve_dnlp_dbg_i2r"); + +/* light -pattern 1 */ +int ve_dnlp_slow_end = 2; +module_param(ve_dnlp_slow_end, int, 0664); +MODULE_PARM_DESC(ve_dnlp_slow_end, + "ve_dnlp_slow_end"); + +/*concentration*/ +static int ve_dnlp_blk_cctr = 8; +module_param(ve_dnlp_blk_cctr, int, 0664); +MODULE_PARM_DESC(ve_dnlp_blk_cctr, "dnlp low luma concenration"); + +/*the center to be brighter*/ +static int ve_dnlp_brgt_ctrl = 48; +module_param(ve_dnlp_brgt_ctrl, int, 0664); +MODULE_PARM_DESC(ve_dnlp_brgt_ctrl, "dnlp center to be brighter"); + +/*brighter range*/ +static int ve_dnlp_brgt_range = 16; +module_param(ve_dnlp_brgt_range, int, 0664); +MODULE_PARM_DESC(ve_dnlp_brgt_range, "dnlp brighter range"); + +/*yout=yin+ve_dnlp_brght_add*/ +/* 32 => 0, brght_add range = [0,64] => [-32,+32] */ +static int ve_dnlp_brght_add = 32; +module_param(ve_dnlp_brght_add, int, 0664); +MODULE_PARM_DESC(ve_dnlp_brght_add, "dnlp brightness up absolute"); + +/*yout=yin+ve_dnlp_brght_add + ve_dnlp_brght_max*rate*/ +static int ve_dnlp_brght_max; +module_param(ve_dnlp_brght_max, int, 0664); +MODULE_PARM_DESC(ve_dnlp_brght_max, "dnlp brightness up maximum"); + +/* define the black or white scence */ +static int ve_dnlp_almst_wht = 63; +module_param(ve_dnlp_almst_wht, int, 0664); +MODULE_PARM_DESC(ve_dnlp_almst_wht, "define the white scence"); + +/* global setting clip rate */ +static bool ve_dnlp_glb_crate = 1; +module_param(ve_dnlp_glb_crate, bool, 0664); +MODULE_PARM_DESC(ve_dnlp_glb_crate, "global clash rate"); + +/* define it high bins: hist > hghbin*tAvg/64 */ +static int ve_dnlp_hghbin = 51; +module_param(ve_dnlp_hghbin, int, 0664); +MODULE_PARM_DESC(ve_dnlp_hghbin, "high bins"); + +/* the number of bins with the largest histogram */ +static int ve_dnlp_hghnum = 4; +module_param(ve_dnlp_hghnum, int, 0664); +MODULE_PARM_DESC(ve_dnlp_hghnum, "the number of high bins"); + +/* define it low bins: hist < lowbin*tAvg/64 */ +static int ve_dnlp_lowbin = 4; +module_param(ve_dnlp_lowbin, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lowbin, "define it low bins"); + +/* the number of bins with the lowest histogram */ +static int ve_dnlp_lownum = 4; +module_param(ve_dnlp_lownum, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lownum, "the number of low bins"); + +/* black gamma end point setting */ +static int ve_dnlp_bkgend; +module_param(ve_dnlp_bkgend, int, 0664); +MODULE_PARM_DESC(ve_dnlp_bkgend, "black gamma end point setting"); + +/* black gamma end point rate */ +static int ve_dnlp_bkgert = 64; +module_param(ve_dnlp_bkgert, int, 0664); +MODULE_PARM_DESC(ve_dnlp_bkgert, "black gamma end point rate"); + +static int ve_dnlp_pstgma_brghtrate = 8; +module_param(ve_dnlp_pstgma_brghtrate, int, 0664); +MODULE_PARM_DESC(ve_dnlp_pstgma_brghtrate, "ve_dnlp_pstgma_brghtrate"); + +static int ve_dnlp_pstgma_brghtrat1 = 15; +module_param(ve_dnlp_pstgma_brghtrat1, int, 0664); +MODULE_PARM_DESC(ve_dnlp_pstgma_brghtrat1, "ve_dnlp_pstgma_brghtrat1"); + +/* black extension when sum(hist) < (ext*tAvg>>6) */ +static int ve_dnlp_blkext = 4; +module_param(ve_dnlp_blkext, int, 0664); +MODULE_PARM_DESC(ve_dnlp_blkext, "black extension: sum()"); + +/* white extension when sum(hist) < (ext*tAvg>>6) */ +static int ve_dnlp_whtext = 4; +module_param(ve_dnlp_whtext, int, 0664); +MODULE_PARM_DESC(ve_dnlp_whtext, "white extension: sum()"); + +/* black extension maximum bins */ +static int ve_dnlp_bextmx = 4; +module_param(ve_dnlp_bextmx, int, 0664); +MODULE_PARM_DESC(ve_dnlp_bextmx, "black extension bins"); + +/* white extension maximum bins */ +static int ve_dnlp_wextmx = 32; +module_param(ve_dnlp_wextmx, int, 0664); +MODULE_PARM_DESC(ve_dnlp_wextmx, "white extension bins"); + +static int ve_dnlp_wext_autorat = 16; +module_param(ve_dnlp_wext_autorat, int, 0664); +MODULE_PARM_DESC(ve_dnlp_wext_autorat, "ve_dnlp_wext_autorat"); + +/* adpative mtdrate low band */ +/* default=0 */ +static int ve_dnlp_adpmtd_lbnd = 19; +module_param(ve_dnlp_adpmtd_lbnd, int, 0664); +MODULE_PARM_DESC(ve_dnlp_adpmtd_lbnd, "ve_dnlp_adpmtd_lbnd"); + +/* adpative mtdrate high band */ +/* default=0 */ +static int ve_dnlp_adpmtd_hbnd = 20; +module_param(ve_dnlp_adpmtd_hbnd, int, 0664); +MODULE_PARM_DESC(ve_dnlp_adpmtd_hbnd, "ve_dnlp_adpmtd_hbnd"); + +static int ve_dnlp_adpalpha_lrate = 32; +module_param(ve_dnlp_adpalpha_lrate, int, 0664); +MODULE_PARM_DESC(ve_dnlp_adpalpha_lrate, "ve_dnlp_adpalpha_lrate"); + +static int ve_dnlp_adpalpha_hrate = 32; +module_param(ve_dnlp_adpalpha_hrate, int, 0664); +MODULE_PARM_DESC(ve_dnlp_adpalpha_hrate, "ve_dnlp_adpalpha_hrate"); + +static int ve_dnlp_set_bext; +module_param(ve_dnlp_set_bext, int, 0664); +MODULE_PARM_DESC(ve_dnlp_set_bext, "ve_dnlp_set_bext"); + +static int ve_dnlp_set_wext; +module_param(ve_dnlp_set_wext, int, 0664); +MODULE_PARM_DESC(ve_dnlp_set_wext, "ve_dnlp_set_wext"); + +static int ve_dnlp_satur_rat = 30; +module_param(ve_dnlp_satur_rat, int, 0664); +MODULE_PARM_DESC(ve_dnlp_satur_rat, "ve_dnlp_satur_rat"); + +static int ve_dnlp_satur_max = 40; +module_param(ve_dnlp_satur_max, int, 0664); +MODULE_PARM_DESC(ve_dnlp_satur_max, "ve_dnlp_satur_max"); + +static int ve_blk_prct_rng = 2; +module_param(ve_blk_prct_rng, int, 0664); +MODULE_PARM_DESC(ve_blk_prct_rng, "ve_blk_prct_rng"); + +static int ve_blk_prct_max = 16; +module_param(ve_blk_prct_max, int, 0664); +MODULE_PARM_DESC(ve_blk_prct_max, "ve_blk_prct_max"); + +static unsigned int ve_dnlp_set_saturtn; +module_param(ve_dnlp_set_saturtn, uint, 0664); +MODULE_PARM_DESC(ve_dnlp_set_saturtn, "ve_dnlp_set_saturtn"); + +static int ve_dnlp_bin0_absmax = 16; +module_param(ve_dnlp_bin0_absmax, int, 0664); +MODULE_PARM_DESC(ve_dnlp_bin0_absmax, "ve_dnlp_bin0_absmax"); + +static int ve_dnlp_bin0_sbtmax = 128; +module_param(ve_dnlp_bin0_sbtmax, int, 0664); +MODULE_PARM_DESC(ve_dnlp_bin0_sbtmax, "ve_dnlp_bin0_sbtmax"); + +static int ve_dnlp_lrate00 = 32; +module_param(ve_dnlp_lrate00, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate00, "Clash Local Clip rate 00"); + +static int ve_dnlp_lrate02 = 33; +module_param(ve_dnlp_lrate02, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate02, "Clash Local Clip rate 02"); + +static int ve_dnlp_lrate04 = 34; +module_param(ve_dnlp_lrate04, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate04, "Clash Local Clip rate 04"); + +static int ve_dnlp_lrate06 = 35; +module_param(ve_dnlp_lrate06, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate06, "Clash Local Clip rate 06"); + +static int ve_dnlp_lrate08 = 36; +module_param(ve_dnlp_lrate08, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate08, "Clash Local Clip rate 08"); + +static int ve_dnlp_lrate10 = 37; +module_param(ve_dnlp_lrate10, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate10, "Clash Local Clip rate 10"); + +static int ve_dnlp_lrate12 = 38; +module_param(ve_dnlp_lrate12, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate12, "Clash Local Clip rate 12"); + +static int ve_dnlp_lrate14 = 39; +module_param(ve_dnlp_lrate14, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate14, "Clash Local Clip rate 14"); + +static int ve_dnlp_lrate16 = 40; +module_param(ve_dnlp_lrate16, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate16, "Clash Local Clip rate 16"); + +static int ve_dnlp_lrate18 = 41; +module_param(ve_dnlp_lrate18, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate18, "Clash Local Clip rate 18"); + +static int ve_dnlp_lrate20 = 42; +module_param(ve_dnlp_lrate20, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate20, "Clash Local Clip rate 20"); + +static int ve_dnlp_lrate22 = 43; +module_param(ve_dnlp_lrate22, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate22, "Clash Local Clip rate 22"); + +static int ve_dnlp_lrate24 = 44; +module_param(ve_dnlp_lrate24, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate24, "Clash Local Clip rate 24"); + +static int ve_dnlp_lrate26 = 45; +module_param(ve_dnlp_lrate26, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate26, "Clash Local Clip rate 26"); + +static int ve_dnlp_lrate28 = 46; +module_param(ve_dnlp_lrate28, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate28, "Clash Local Clip rate 28"); + +static int ve_dnlp_lrate30 = 47; +module_param(ve_dnlp_lrate30, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate30, "Clash Local Clip rate 30"); + +static int ve_dnlp_lrate32 = 48; +module_param(ve_dnlp_lrate32, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate32, "Clash Local Clip rate 32"); + +static int ve_dnlp_lrate34 = 49; +module_param(ve_dnlp_lrate34, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate34, "Clash Local Clip rate 34"); + +static int ve_dnlp_lrate36 = 50; +module_param(ve_dnlp_lrate36, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate36, "Clash Local Clip rate 36"); + +static int ve_dnlp_lrate38 = 51; +module_param(ve_dnlp_lrate38, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate38, "Clash Local Clip rate 38"); + +static int ve_dnlp_lrate40 = 52; +module_param(ve_dnlp_lrate40, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate40, "Clash Local Clip rate 40"); + +static int ve_dnlp_lrate42 = 53; +module_param(ve_dnlp_lrate42, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate42, "Clash Local Clip rate 42"); + +static int ve_dnlp_lrate44 = 54; +module_param(ve_dnlp_lrate44, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate44, "Clash Local Clip rate 44"); + +static int ve_dnlp_lrate46 = 55; +module_param(ve_dnlp_lrate46, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate46, "Clash Local Clip rate 46"); + +static int ve_dnlp_lrate48 = 56; +module_param(ve_dnlp_lrate48, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate48, "Clash Local Clip rate 48"); + +static int ve_dnlp_lrate50 = 57; +module_param(ve_dnlp_lrate50, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate50, "Clash Local Clip rate 50"); + +static int ve_dnlp_lrate52 = 58; +module_param(ve_dnlp_lrate52, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate52, "Clash Local Clip rate 52"); + +static int ve_dnlp_lrate54 = 59; +module_param(ve_dnlp_lrate54, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate54, "Clash Local Clip rate 54"); + +static int ve_dnlp_lrate56 = 60; +module_param(ve_dnlp_lrate56, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate56, "Clash Local Clip rate 56"); + +static int ve_dnlp_lrate58 = 61; +module_param(ve_dnlp_lrate58, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate58, "Clash Local Clip rate 58"); + +static int ve_dnlp_lrate60 = 62; +module_param(ve_dnlp_lrate60, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate60, "Clash Local Clip rate 60"); + +static int ve_dnlp_lrate62 = 63; +module_param(ve_dnlp_lrate62, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lrate62, "Clash Local Clip rate 62"); +/* Local clip rate */ + +/*the maximum bins > x/256*/ +static int ve_dnlp_lgst_bin = 100; +module_param(ve_dnlp_lgst_bin, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lgst_bin, "dnlp: define it maximum bin"); + +/*two maximum bins' distance*/ +static int ve_dnlp_lgst_dst = 30; +module_param(ve_dnlp_lgst_dst, int, 0664); +MODULE_PARM_DESC(ve_dnlp_lgst_dst, "dnlp: two maximum bins' distance"); + +/* hd /fhd maybe set different value */ +static int ve_dnlp_pavg_btsft = 5; +module_param(ve_dnlp_pavg_btsft, int, 0664); +MODULE_PARM_DESC(ve_dnlp_pavg_btsft, "ve_dnlp_pavg_btsft"); + +/* limit range */ +static bool ve_dnlp_limit_rng = 1; +module_param(ve_dnlp_limit_rng, bool, 0664); +MODULE_PARM_DESC(ve_dnlp_limit_rng, "input limit range"); + +static bool ve_dnlp_range_det; +module_param(ve_dnlp_range_det, bool, 0664); +MODULE_PARM_DESC(ve_dnlp_range_det, +"input limit or full range detection"); + +/* scene change: avg - dif shif */ +static int ve_dnlp_schg_sft = 1; +module_param(ve_dnlp_schg_sft, int, 0664); +MODULE_PARM_DESC(ve_dnlp_schg_sft, + "ve_dnlp_schg_sft"); + +/* curveblend minimmum level */ +static int ve_dnlp_cuvbld_min = 2; +module_param(ve_dnlp_cuvbld_min, int, 0664); +MODULE_PARM_DESC(ve_dnlp_cuvbld_min, + "ve_dnlp_cuvbld_min"); + +/* curveblend minimmum level */ +static int ve_dnlp_cuvbld_max = 17; +module_param(ve_dnlp_cuvbld_max, int, 0664); +MODULE_PARM_DESC(ve_dnlp_cuvbld_max, + "ve_dnlp_cuvbld_max"); + +/* debug difference level */ +static int ve_dnlp_dbg_diflvl; +module_param(ve_dnlp_dbg_diflvl, int, 0664); +MODULE_PARM_DESC(ve_dnlp_dbg_diflvl, + "ve_dnlp_dbg_diflvl"); + +/* output the mapping curve */ +static int ve_dnlp_dbg_map; +module_param(ve_dnlp_dbg_map, int, 0664); +MODULE_PARM_DESC(ve_dnlp_dbg_map, + "ve_dnlp_dbg_map"); + +static int ve_dnlp_scv_dbg; +module_param(ve_dnlp_scv_dbg, int, 0664); +MODULE_PARM_DESC(ve_dnlp_scv_dbg, + "ve_dnlp_scv_dbg"); + +static int ve_dnlp_cliprate_min = 19; +module_param(ve_dnlp_cliprate_min, int, 0664); +MODULE_PARM_DESC(ve_dnlp_cliprate_min, + "ve_dnlp_cliprate_min"); + +static int ve_dnlp_adpcrat_lbnd = 10; +module_param(ve_dnlp_adpcrat_lbnd, int, 0664); +MODULE_PARM_DESC(ve_dnlp_adpcrat_lbnd, + "ve_dnlp_adpcrat_lbnd"); + +static int ve_dnlp_adpcrat_hbnd = 20; +module_param(ve_dnlp_adpcrat_hbnd, int, 0664); +MODULE_PARM_DESC(ve_dnlp_adpcrat_hbnd, + "ve_dnlp_adpcrat_hbnd"); + +/* print log once */ +static int ve_dnlp_ponce = 1; +module_param(ve_dnlp_ponce, int, 0664); +MODULE_PARM_DESC(ve_dnlp_ponce, "ve_dnlp_ponce"); + +/* global variable */ +unsigned int iRgnBgn; /* i>=iRgnBgn */ +unsigned int iRgnEnd = 64;/* ivpp , 0->vdin*/ +module_param(hist_sel, bool, 0664); +MODULE_PARM_DESC(hist_sel, "hist_sel"); + +static unsigned int assist_cnt;/* ASSIST_SPARE8_REG1; */ +static unsigned int assist_cnt2;/* ASSIST_SPARE8_REG2; */ + +/* video lock */ +#define VLOCK_MODE_ENC 0 +#define VLOCK_MODE_PLL 1 +#define VLOCK_MODE_MANUAL_PLL 2 +#define XTAL_VLOCK_CLOCK 24000000/*vlock use xtal clock*/ + +/* 0:enc;1:pll;2:manual pll */ +static unsigned int vlock_mode = VLOCK_MODE_MANUAL_PLL; +static unsigned int vlock_en = 1; + +/*0:only support 50->50;60->60;24->24;30->30;*/ +/*1:support 24/30/50/60/100/120 mix,such as 50->60;*/ +static unsigned int vlock_adapt; +static unsigned int vlock_dis_cnt_limit = 2; +/*4k@60hz test case: delta 200 is close to 500K*/ +static unsigned int vlock_delta_limit_frac = 100; +static unsigned int vlock_delta_limit_m; +/*vlock_debug:bit0:disable info;bit1:format change info;bit2:force reset*/ +static unsigned int vlock_debug; +static unsigned int vlock_dynamic_adjust = 1; + +static unsigned int vlock_sync_limit_flag; +static unsigned int vlock_state = VLOCK_STATE_NULL;/*1/2/3:vlock step*/ +static enum vmode_e pre_vmode = VMODE_INIT_NULL; +static enum vframe_source_type_e pre_source_type = + VFRAME_SOURCE_TYPE_OTHERS; +static enum vframe_source_mode_e pre_source_mode = + VFRAME_SOURCE_MODE_OTHERS; +static unsigned int pre_input_freq; +static unsigned int pre_output_freq; +static unsigned int vlock_dis_cnt; +static char pre_vout_mode[64]; +static bool vlock_vmode_changed; +static unsigned int pre_hiu_reg_m; +static unsigned int pre_hiu_reg_frac; +static unsigned int vlock_dis_cnt_step1; +static unsigned int vlock_dis_cnt_step1_limit = 300; +static unsigned int vlock_en_cnt_step1_limit = 300; + +/* 3d sync parts begin */ +unsigned int sync_3d_h_start; +unsigned int sync_3d_h_end; +unsigned int sync_3d_v_start = 10; +unsigned int sync_3d_v_end = 20; +unsigned int sync_3d_polarity; +unsigned int sync_3d_out_inv; +unsigned int sync_3d_black_color = 0x008080;/* yuv black */ +/* 3d sync to v by one enable/disable */ +unsigned int sync_3d_sync_to_vbo; +/* 3d sync parts end */ + +unsigned int contrast_adj_sel;/*0:vdj1, 1:vd1 mtx rgb contrast*/ +module_param(contrast_adj_sel, uint, 0664); +MODULE_PARM_DESC(contrast_adj_sel, "\n contrast_adj_sel\n"); + +/* *********************************************************************** */ +/* *** VPP_FIQ-oriented functions **************************************** */ +/* *********************************************************************** */ +static void ve_dnlp_add_cm(unsigned int value) +{ + unsigned int reg_value; + + VSYNC_WR_MPEG_REG(VPP_CHROMA_ADDR_PORT, 0x207); + reg_value = VSYNC_RD_MPEG_REG(VPP_CHROMA_DATA_PORT); + reg_value = (reg_value & 0xf000ffff) | (value << 16); + VSYNC_WR_MPEG_REG(VPP_CHROMA_ADDR_PORT, 0x207); + VSYNC_WR_MPEG_REG(VPP_CHROMA_DATA_PORT, reg_value); +} + +static void ve_hist_gamma_tgt(struct vframe_s *vf) +{ + int ave_luma; + struct vframe_prop_s *p = &vf->prop; + + video_ve_hist.sum = p->hist.vpp_luma_sum; + video_ve_hist.width = p->hist.vpp_width; + video_ve_hist.height = p->hist.vpp_height; + + video_ve_hist.ave = + video_ve_hist.sum/(video_ve_hist.height* + video_ve_hist.width); + if ((vf->source_type == VFRAME_SOURCE_TYPE_OTHERS) && + (is_meson_gxtvbb_cpu())) { + ave_luma = video_ve_hist.ave; + ave_luma = (ave_luma - 16) < 0 ? 0 : (ave_luma - 16); + video_ve_hist.ave = ave_luma*255/(235-16); + if (video_ve_hist.ave > 255) + video_ve_hist.ave = 255; + } +} + +static void ve_dnlp_calculate_tgt_ext(struct vframe_s *vf) +{ + struct vframe_prop_s *p = &vf->prop; + static unsigned int sum_b = 0, sum_c; + ulong i = 0, j = 0, sum = 0, ave = 0, ankle = 0, + waist = 0, peak = 0, start = 0; + ulong qty_h = 0, qty_l = 0, ratio_h = 0, ratio_l = 0; + ulong div1 = 0, div2 = 0, step_h = 0, step_l = 0; + ulong data[55]; + bool flag[55], previous_state_high = false; + /* READ_VPP_REG(ASSIST_SPARE8_REG1); */ + unsigned int cnt = assist_cnt; + /* old historic luma sum */ + sum_b = sum_c; + sum_c = ve_dnlp_luma_sum; + /* new historic luma sum */ + ve_dnlp_luma_sum = p->hist.luma_sum; + pr_amve_dbg("ve_dnlp_luma_sum=%x,sum_b=%x,sum_c=%x\n", + ve_dnlp_luma_sum, sum_b, sum_c); + /* picture mode: freeze dnlp curve */ + if (dnlp_respond) { + /* new luma sum is 0, something is wrong, freeze dnlp curve */ + if (!ve_dnlp_luma_sum) + return; + } else { + /* new luma sum is 0, something is wrong, freeze dnlp curve */ + if ((!ve_dnlp_luma_sum) || + /* new luma sum is closed to old one (1 +/- 1/64),*/ + /* picture mode, freeze curve */ + ((ve_dnlp_luma_sum < + sum_b + (sum_b >> dnlp_adj_level)) && + (ve_dnlp_luma_sum > + sum_b - (sum_b >> dnlp_adj_level)))) + return; + } + /* calculate ave (55 times of ave & data[] for accuracy) */ + /* ave 22-bit */ + /* data[] 22-bit */ + ave = 0; + for (i = 0; i < 55; i++) { + data[i] = (ulong)p->hist.gamma[i + 4]; + ave += data[i]; + data[i] *= 55; + flag[i] = false; + } + /* calculate ankle */ + /* ankle 22-bit */ + /* waist 22-bit */ + /* qty_h 6-bit */ + ankle = (ave * ve_dnlp_ankle + 128) >> 8; + /* scan data[] to find out waist pulses */ + qty_h = 0; + previous_state_high = false; + for (i = 0; i < 55; i++) { + if (data[i] >= ankle) { + /* ankle pulses start */ + if (!previous_state_high) { + previous_state_high = true; + start = i; + peak = 0; + } + /* normal maintenance */ + if (peak < data[i]) + peak = data[i]; + } else { + /* ankle pulses end + 1 */ + if (previous_state_high) { + previous_state_high = false; + /* calculate waist of high area pulses */ + if (peak >= ave) + waist = ((peak - ankle) * + ve_dnlp_waist_h + 128) >> 8; + /* calculate waist of high area pulses */ + else + waist = ((peak - ankle) * + ve_dnlp_waist_l + 128) >> 8; + /* find out waist pulses */ + for (j = start; j < i; j++) { + if (data[j] >= waist) { + flag[j] = true; + qty_h++; + } + } + } + } + } + + /* calculate ratio_h and ratio_l */ + /* (div2 = 512*H*L times of value for accuracy) */ + /* averaged duty > 1/3 */ + /* qty_l 6-bit */ + /* div1 20-bit */ + /* div2 21-bit */ + /* ratio_h 22-bit */ + /* ratio_l 21-bit */ + qty_l = 55 - qty_h; + if ((!qty_h) || (!qty_l)) { + for (i = 5; i <= 58; i++) + ve_dnlp_tgt[i] = i << 2; + } else { + div1 = 256 * qty_h * qty_l; + div2 = 512 * qty_h * qty_l; + if (qty_h > 18) { + /* [1.0 ~ 2.0) */ + ratio_h = div2 + ve_dnlp_strength * qty_l * qty_l; + /* [0.5 ~ 1.0] */ + ratio_l = div2 - ve_dnlp_strength * qty_h * qty_l; + } + /* averaged duty < 1/3 */ + /* [1.0 ~ 2.0] */ + ratio_h = div2 + (ve_dnlp_strength << 1) * qty_h * qty_l; + /* (0.5 ~ 1.0] */ + ratio_l = div2 - (ve_dnlp_strength << 1) * qty_h * qty_h; + /* distribute ratio_h & ratio_l to */ + /* ve_dnlp_tgt[5] ~ ve_dnlp_tgt[58] */ + /* sum 29-bit */ + /* step_h 24-bit */ + /* step_l 23-bit */ + sum = div2 << 4; /* start from 16 */ + step_h = ratio_h << 2; + step_l = ratio_l << 2; + for (i = 5; i <= 58; i++) { + /* high phase */ + if (flag[i - 5]) + sum += step_h; + /* low phase */ + else + sum += step_l; + ve_dnlp_tgt[i] = (sum + div1) / div2; + } + if (cnt) { + for (i = 0; i < 64; i++) + pr_amve_dbg(" ve_dnlp_tgte[%ld]=%d\n", + i, ve_dnlp_tgt[i]); + /* WRITE_VPP_REG(ASSIST_SPARE8_REG1, 0); */ + assist_cnt = 0; + } + } +} + +void GetWgtLst(ulong *iHst, ulong tAvg, ulong nLen, ulong alpha) +{ + ulong iMax = 0; + ulong iMin = 0; + ulong iPxl = 0; + ulong iT = 0; + + for (iT = 0; iT < nLen; iT++) { + iPxl = iHst[iT]; + if (iPxl > tAvg) { + iMax = iPxl; + iMin = tAvg; + } else { + iMax = tAvg; + iMin = iPxl; + } + if (alpha < 16) { + iPxl = ((16-alpha)*iMin+8)>>4; + iPxl += alpha*iMin; + } else if (alpha < 32) { + iPxl = (32-alpha)*iMin; + iPxl += (alpha-16)*iMax; + } else { + iPxl = (48-alpha)+4*(alpha-32); + iPxl *= iMax; + } + iPxl = (iPxl+8)>>4; + iHst[iT] = iPxl < 1 ? 1 : iPxl; + } +} + +static void ve_dnlp_calculate_tgtx(struct vframe_s *vf) +{ + struct vframe_prop_s *p = &vf->prop; + ulong iHst[64]; + ulong oHst[64]; + static unsigned int sum_b = 0, sum_c; + ulong i = 0, j = 0, sum = 0, max = 0; + ulong cLmt = 0, nStp = 0, stp = 0, uLmt = 0; + long nExc = 0; + unsigned int cnt = assist_cnt;/* READ_VPP_REG(ASSIST_SPARE8_REG1); */ + unsigned int cnt2 = assist_cnt2;/* READ_VPP_REG(ASSIST_SPARE8_REG2); */ + unsigned int clip_rate = ve_dnlp_cliprate; /* 8bit */ + unsigned int low_range = ve_dnlp_lowrange;/* 18; //6bit [0-54] */ + unsigned int hgh_range = ve_dnlp_hghrange;/* 18; //6bit [0-54] */ + unsigned int low_alpha = ve_dnlp_lowalpha;/* 24; //6bit [0--48] */ + unsigned int mid_alpha = ve_dnlp_midalpha;/* 24; //6bit [0--48] */ + unsigned int hgh_alpha = ve_dnlp_hghalpha;/* 24; //6bit [0--48] */ + /* ------------------------------------------------- */ + ulong tAvg = 0; + ulong nPnt = 0; + ulong mRng = 0; + /* old historic luma sum */ + sum_b = sum_c; + sum_c = ve_dnlp_luma_sum; + /* new historic luma sum */ + ve_dnlp_luma_sum = p->hist.luma_sum; + pr_amve_dbg("ve_dnlp_luma_sum=%x,sum_b=%x,sum_c=%x\n", + ve_dnlp_luma_sum, sum_b, sum_c); + /* picture mode: freeze dnlp curve */ + if (dnlp_respond) { + /* new luma sum is 0, something is wrong, freeze dnlp curve */ + if (!ve_dnlp_luma_sum) + return; + } else { + /* new luma sum is 0, something is wrong, freeze dnlp curve */ + if ((!ve_dnlp_luma_sum) || + /* new luma sum is closed to old one (1 +/- 1/64), */ + /* picture mode, freeze curve */ + ((ve_dnlp_luma_sum < + sum_b + (sum_b >> dnlp_adj_level)) && + (ve_dnlp_luma_sum > + sum_b - (sum_b >> dnlp_adj_level)))) + return; + } + /* 64 bins, max, ave */ + for (i = 0; i < 64; i++) { + iHst[i] = (ulong)p->hist.gamma[i]; + if (i >= 4 && i <= 58) { + oHst[i] = iHst[i]; + if (max < iHst[i]) + max = iHst[i]; + sum += iHst[i]; + } else { + oHst[i] = 0; + } + } + cLmt = (clip_rate*sum)>>8; + tAvg = sum/55; + /* invalid histgram: freeze dnlp curve */ + if (max <= 55) + return; + /* get 1st 4 points */ + for (i = 4; i <= 58; i++) { + if (iHst[i] > cLmt) + nExc += (iHst[i]-cLmt); + } + nStp = (nExc+28)/55; + uLmt = cLmt-nStp; + if (cnt2) { + pr_amve_dbg(" ve_dnlp_tgtx:cLmt=%ld,nStp=%ld,uLmt=%ld\n", + cLmt, nStp, uLmt); + /* WRITE_VPP_REG(ASSIST_SPARE8_REG2, 0); */ + assist_cnt2 = 0; + } + if (clip_rate <= 4 || tAvg <= 2) { + cLmt = (sum+28)/55; + sum = cLmt*55; + for (i = 4; i <= 58; i++) + oHst[i] = cLmt; + } else if (nStp != 0) { + for (i = 4; i <= 58; i++) { + if (iHst[i] >= cLmt) + oHst[i] = cLmt; + else { + if (iHst[i] > uLmt) { + oHst[i] = cLmt; + nExc -= cLmt-iHst[i]; + } else { + oHst[i] = iHst[i]+nStp; + nExc -= nStp; + } + if (nExc < 0) + nExc = 0; + } + } + j = 4; + while (nExc > 0) { + if (nExc >= 55) { + nStp = 1; + stp = nExc/55; + } else { + nStp = 55/nExc; + stp = 1; + } + for (i = j; i <= 58; i += nStp) { + if (oHst[i] < cLmt) { + oHst[i] += stp; + nExc -= stp; + } + if (nExc <= 0) + break; + } + j += 1; + if (j > 58) + break; + } + } + if (low_range == 0 && hgh_range == 0) + nPnt = 0; + else { + if (low_range == 0 || hgh_range == 0) { + nPnt = 1; + mRng = (hgh_range > low_range ? hgh_range : low_range); + } else if (low_range+hgh_range >= 54) { + nPnt = 1; + mRng = (hgh_range < low_range ? hgh_range : low_range); + } else + nPnt = 2; + } + if (nPnt == 0 && low_alpha >= 16 && low_alpha <= 32) { + sum = 0; + for (i = 5; i <= 59; i++) { + j = oHst[i]*(32-low_alpha)+tAvg*(low_alpha-16); + j = (j+8)>>4; + oHst[i] = j; + sum += j; + } + } else if (nPnt == 1) { + GetWgtLst(oHst+4, tAvg, mRng, low_alpha); + GetWgtLst(oHst+4+mRng, tAvg, 54-mRng, hgh_alpha); + } else if (nPnt == 2) { + mRng = 55-(low_range+hgh_range); + GetWgtLst(oHst+4, tAvg, low_range, low_alpha); + GetWgtLst(oHst+4+low_range, tAvg, mRng, mid_alpha); + GetWgtLst(oHst+4+mRng+low_range, tAvg, hgh_range, hgh_alpha); + } + sum = 0; + for (i = 4; i <= 58; i++) { + if (oHst[i] > cLmt) + oHst[i] = cLmt; + sum += oHst[i]; + } + nStp = 0; + /* sum -= oHst[4]; */ + for (i = 5; i <= 59; i++) { + nStp += oHst[i-1]; + /* nStp += oHst[i]; */ + j = (236-16)*nStp; + j += (sum>>1); + j /= sum; + ve_dnlp_tgt[i] = j + 16; + } + if (cnt) { + for (i = 0; i < 64; i++) + pr_amve_dbg(" ve_dnlp_tgtx[%ld]=%d\n", + i, ve_dnlp_tgt[i]); + /* WRITE_VPP_REG(ASSIST_SPARE8_REG1, 0); */ + assist_cnt = 0; + } +} + +static unsigned int pre_1_gamma[65]; +static unsigned int pre_0_gamma[65]; + +/* more 2-bit */ +static unsigned int pst_0_gamma[65]; + +bool dnlp_scn_chg; /* scene change */ +int dnlp_bld_lvl; /* blend level */ +int RBASE = 1; + +/*rGmIn[0:64] ==>0:4:256, gamma*/ +/*rGmOt[0:pwdth]==>0-0, 0~1024*/ +void GetSubCurve(unsigned int *rGmOt, + unsigned int *rGmIn, unsigned int pwdth) +{ + int nT0 = 0; + unsigned int BASE = 64; + + unsigned int plft = 0; + unsigned int prto = 0; + unsigned int rst = 0; + + unsigned int idx1 = 0; + unsigned int idx2 = 0; + + if (pwdth == 0) + pwdth = 1; + + for (nT0 = 0; nT0 <= pwdth; nT0++) { + plft = nT0*64/pwdth; + prto = (BASE*(nT0*BASE-plft*pwdth) + pwdth/2)/pwdth; + + idx1 = plft; + idx2 = plft+1; + if (idx1 > 64) + idx1 = 64; + if (idx2 > 64) + idx2 = 64; + + rst = rGmIn[idx1]*(BASE-prto) + rGmIn[idx2]*prto; + rst = (rst + BASE/2)*4*pwdth/BASE; + /* rst = ((rst + 128)>>8); */ + rst = ((rst + 32)>>6); + + if (nT0 == 0) + rst = rGmIn[0]; + if (rst > (pwdth << 4)) + rst = (pwdth << 4); + + rGmOt[nT0] = rst; + } +} + +/*rGmOt[0:64]*/ +/*rGmIn[0:64]*/ +/* 0~1024 */ +void GetGmBlkCvs(unsigned int *rGmOt, unsigned int *rGmIn, + unsigned int Bgn, unsigned int End) +{ + static unsigned int pgmma0[65]; + int nT0 = 0; + int pwdth = End - Bgn; /* 64 */ + int pLst[65]; + int i = 0; + int nTmp0 = 0; + + if (!ve_dnlp_luma_sum) { + for (nT0 = 0; nT0 < 65; nT0++) + pgmma0[nT0] = (nT0 << 4); /* 0 ~1024 */ + } + + GetSubCurve(pLst, rGmIn, pwdth); /*0~1024*/ + + for (nT0 = 0; nT0 < 65; nT0++) { + if (nT0 < Bgn) + rGmOt[nT0] = (nT0 << 4); + else if (nT0 >= End) + rGmOt[nT0] = (nT0 << 4); + else { + if (ve_dnlp_pst_gmarat > 64) + rGmOt[nT0] = (Bgn << 4) + + (1024 - pLst[64 + Bgn - nT0]); + else + rGmOt[nT0] = (Bgn << 4) + pLst[nT0 - Bgn]; + } + } + + if (!dnlp_scn_chg) + for (i = 0; i < 65; i++) { + nTmp0 = dnlp_bld_lvl * rGmOt[i] + (RBASE >> 1); + nTmp0 = nTmp0 + (RBASE - dnlp_bld_lvl) * pgmma0[i]; + nTmp0 = (nTmp0 >> ve_dnlp_mvreflsh); /* 0 ~1024 */ + + rGmOt[i] = nTmp0; + } + + for (i = 0; i < 65; i++) + pgmma0[i] = rGmOt[i]; +} + + +/*rGmOt[0:64]*/ +/*rGmIn[0:64]*/ +/* 0 ~1024 */ +void GetGmCurves2(unsigned int *rGmOt, unsigned int *rGmIn, + unsigned int pval, unsigned int BgnBnd, unsigned int EndBnd) +{ + int nT0 = 0; + /*unsigned int rst=0;*/ + int pwdth = 0; + unsigned int pLst[65]; + int nT1 = 0; + bool prt_flg = ((dnlp_printk >> 11) & 0x1); + + if (pval >= ve_dnlp_almst_wht) { + for (nT0 = 0; nT0 < 65; nT0++) + rGmOt[nT0] = rGmIn[nT0] << 2; + return; + } + + if (BgnBnd > 10) + BgnBnd = 10; + if (EndBnd > 10) + EndBnd = 10; + + if (pval < ve_dnlp_slow_end) + pval = ve_dnlp_slow_end; + + if (pval <= BgnBnd) + pval = BgnBnd + 1; + + /* fuck here */ + if (pval + EndBnd > 64) + pval = 63 - EndBnd; + + for (nT0 = 0; nT0 < 65; nT0++) + rGmOt[nT0] = (nT0<<4); /* 0~1024 */ + + if (pval > BgnBnd) { + pwdth = pval - BgnBnd; + GetSubCurve(pLst, rGmIn, pwdth); /* 0~1024 */ + for (nT0 = BgnBnd; nT0 <= pval; nT0++) { + nT1 = pLst[nT0 - BgnBnd] + (BgnBnd<<4); + rGmOt[nT0] = nT1; + } + } + + if ((pval + EndBnd) < 64) { + pwdth = 64 - pval - EndBnd; + GetSubCurve(pLst, rGmIn, pwdth); + for (nT0 = pval; nT0 <= 64 - EndBnd; nT0++) { + nT1 = (1024 - (EndBnd<<4) + - pLst[pwdth - (nT0 - pval)]); + rGmOt[nT0] = nT1; /* 0~1024 */ + } + } + + if (prt_flg) { + pr_info("#GmCvs2: %d %d %d\n", BgnBnd, pval, EndBnd); + for (nT1 = 0; nT1 < 65; nT1++) + pr_info("[%02d] => %4d\n", nT1, rGmOt[nT1]); + pr_info("\n"); + } +} + +void GetGmCurves(unsigned int *rGmOt, unsigned int *rGmIn, + unsigned int lsft_avg, unsigned int BgnBnd, unsigned int EndBnd) +{ + int pval1 = (lsft_avg >> (2 + ve_dnlp_pavg_btsft)); + int pval2 = pval1 + 1; + int BASE = (1 << (2 + ve_dnlp_pavg_btsft)); + int nRzn = lsft_avg - (pval1 << (2 + ve_dnlp_pavg_btsft)); + unsigned int pLst1[65]; + unsigned int pLst2[65]; + int i = 0; + + if (pval2 > ve_dnlp_almst_wht) + pval2 = ve_dnlp_almst_wht; + + GetGmCurves2(pLst1, rGmIn, pval1, BgnBnd, EndBnd); + GetGmCurves2(pLst2, rGmIn, pval2, BgnBnd, EndBnd); + + for (i = 0; i < 65; i++) { + pval2 = pLst1[i] * (BASE - nRzn) + pLst2[i] * nRzn; + + pval2 = (pval2 + (BASE >> 1)); + pval2 = (pval2 >> (2 + ve_dnlp_pavg_btsft)); + + if (pval2 < 0) + pval2 = 0; + else if (pval2 > 1023) + pval2 = 1023; + rGmOt[i] = pval2; + } +} + +unsigned int cal_hist_avg(unsigned int pval) +{ + static unsigned int ppval; + + if (!dnlp_scn_chg) { + pval = dnlp_bld_lvl * pval + (RBASE >> 1); + pval = pval + (RBASE - dnlp_bld_lvl) * ppval; + pval = (pval >> ve_dnlp_mvreflsh); + } + ppval = pval; + + return pval; +} + +/* history */ +unsigned int cal_hst_shft_avg(unsigned int pval) +{ + static unsigned int ppval; + + if (!dnlp_scn_chg) { + pval = dnlp_bld_lvl * pval + (RBASE >> 1); + pval = pval + (RBASE - dnlp_bld_lvl) * ppval; + pval = (pval >> ve_dnlp_mvreflsh); + } + ppval = pval; + + return pval; +} + +/* mtdrate: mtdrate in the mid-tone*/ +/* luma_avg: 0~64 */ +static int dnlp_adp_mtdrate(int mtdrate, int luma_avg) +{ + int np = 0; + int nt = mtdrate; + + if (ve_dnlp_adpmtd_lbnd > 0 && + luma_avg < ve_dnlp_adpmtd_lbnd) { + nt = mtdrate * luma_avg + (ve_dnlp_adpmtd_lbnd >> 1); + nt /= ve_dnlp_adpmtd_lbnd; + + np = 4 * (ve_dnlp_adpmtd_lbnd - luma_avg); + if (np < mtdrate) + np = mtdrate - np; + else + np = 0; + + if (np > nt) + nt = np; + } else if (ve_dnlp_adpmtd_hbnd > 0 && + (luma_avg > 64 - ve_dnlp_adpmtd_hbnd)) { + nt = mtdrate * (64 - luma_avg); + nt += (ve_dnlp_adpmtd_hbnd >> 1); + nt /= ve_dnlp_adpmtd_hbnd; + + np = luma_avg - (64 - ve_dnlp_adpmtd_hbnd); + np = 4 * np; + if (np < mtdrate) + np = mtdrate - np; + else + np = 0; + + if (np > nt) + nt = np; + } + + return nt; +} + +unsigned int AdjHistAvg(unsigned int pval, unsigned int ihstEnd) +{ + unsigned int pEXT = 224; + unsigned int pMid = 128; + unsigned int pMAX = 236; + + if (ihstEnd > 59) + pMAX = ihstEnd << 2; + + if (pval > pMid) { + pval = pMid + (pMAX - pMid)*(pval - pMid)/(pEXT - pMid); + if (pval > pMAX) + pval = pMAX; + } + + return pval; +} + +int blk_wht_extsn(int *blk_wht_ext, unsigned int *iHst, + int hstSum, unsigned int luma_avg) +{ + int tAvg = ((hstSum + 32) >> 6); + int nStp = 0; + int nT0 = 0; + int nT1 = 0; + int i = 0; + int dnlp_wextmx = ve_dnlp_wextmx; + + /* black / white extension */ + static int pblk_wht_ext[2]; + + /* black extension */ + nStp = tAvg * ve_dnlp_blkext + 32; + nStp = (nStp >> 6); + blk_wht_ext[0] = 0; + nT0 = 0; + for (i = 0; i < (iRgnBgn + ve_dnlp_bextmx); i++) { + nT0 += iHst[i]; + if (nT0 > nStp) + break; + else if (i >= iRgnBgn) + blk_wht_ext[0] = ((i + 1 - iRgnBgn) << 4); + } + + /* white extension */ + nStp = tAvg * ve_dnlp_whtext + 32; + nStp = (nStp >> 6); + + if (ve_dnlp_wext_autorat > 0) + dnlp_wextmx = iRgnEnd - 1; + else + dnlp_wextmx = ve_dnlp_wextmx; + + nT0 = 0; + nT1 = 0; + for (i = 0; i < dnlp_wextmx; i++) { + nT0 += iHst[iRgnEnd - 1 - i]; + if (nT0 > nStp) + break; + else if (i >= (64 - iRgnEnd)) + nT1 = (i + iRgnEnd - 63); + } + + if (ve_dnlp_wext_autorat > 0) { + if (luma_avg > 32) /* baby face */ + nT1 = 0; + else { + nT1 = (32 - luma_avg) * nT1 * ve_dnlp_wext_autorat; + nT1 = ((nT1 + 512) >> 10); + if (nT1 > ve_dnlp_wextmx) + nT1 = ve_dnlp_wextmx; + } + } + blk_wht_ext[1] = (nT1 << 4); + + if (!dnlp_scn_chg) { + nT0 = dnlp_bld_lvl * blk_wht_ext[0] + (RBASE >> 1); + nT0 = nT0 + (RBASE - dnlp_bld_lvl) * pblk_wht_ext[0]; + blk_wht_ext[0] = (nT0 >> ve_dnlp_mvreflsh); + + nT1 = dnlp_bld_lvl * blk_wht_ext[1] + (RBASE >> 1); + nT1 = nT1 + (RBASE - dnlp_bld_lvl) * pblk_wht_ext[1]; + blk_wht_ext[1] = (nT1 >> ve_dnlp_mvreflsh); + } + + pblk_wht_ext[0] = blk_wht_ext[0]; + pblk_wht_ext[1] = blk_wht_ext[1]; + + return 0; +} + +static unsigned int dnlp_adp_cliprate(unsigned int clip_rate, + unsigned int clip_rmin, unsigned int luma_avg) +{ + unsigned int nt = clip_rate; + + if (luma_avg < ve_dnlp_adpcrat_lbnd) { + nt = clip_rate * (ve_dnlp_adpcrat_lbnd - luma_avg) + + luma_avg * clip_rmin; + + nt = (nt << 4) + (ve_dnlp_adpcrat_lbnd >> 1); + nt /= ve_dnlp_adpcrat_lbnd; + } else if (luma_avg > 64 - ve_dnlp_adpcrat_hbnd) { + nt = clip_rmin * (64 - luma_avg) + + clip_rate * (luma_avg + ve_dnlp_adpcrat_hbnd - 64); + nt += (nt << 4) + (ve_dnlp_adpcrat_hbnd >> 1); + nt /= ve_dnlp_adpcrat_hbnd; + } else + nt = (clip_rmin << 4); + + return nt; +} + +int old_dnlp_lrate[32]; + +/*iHst[0:63]: [0,4)->iHst[0], [252,256)->iHst[63]*/ +/*oMap[0:64]:0:16:1024*/ +void clash_fun(unsigned int *oMap, unsigned int *iHst, + unsigned int hstBgn, unsigned int hstEnd) +{ + unsigned int i = 0, j = 0; + unsigned int tmax = 0; + unsigned int tsum = 0; + unsigned int oHst[64]; + unsigned int cLmt = 0; + unsigned int tLen = (hstEnd - hstBgn); + unsigned int tAvg = 0; + unsigned int lAvg4 = 0; + unsigned int lAvg1 = 0; + unsigned int nStp = 0; + /*unsigned int uLmt = 0;*/ + /*unsigned int stp = 0;*/ + unsigned int idx[64]; + unsigned int tHst[64]; + unsigned int nT0 = 0; + unsigned int clip_rate = ve_dnlp_cliprate_new; + unsigned int clip_rmin = ve_dnlp_cliprate_min; + unsigned int adp_crate = clip_rate; + + int nNum = 0; + int nExc = 0; + int tExc = 0; + bool prt_flg = 0; + + /* local limit 64-bin*/ + unsigned int lcl_lmt[64]; + + if (clip_rmin > clip_rate) + clip_rmin = clip_rate; + if (ve_dnlp_adpcrat_lbnd < 2) + ve_dnlp_adpcrat_lbnd = 2; + else if (ve_dnlp_adpcrat_lbnd > 30) + ve_dnlp_adpcrat_lbnd = 30; + + if (ve_dnlp_adpcrat_hbnd < 2) + ve_dnlp_adpcrat_hbnd = 2; + else if (ve_dnlp_adpcrat_hbnd > 30) + ve_dnlp_adpcrat_hbnd = 30; + + if (hstBgn > 16) + hstBgn = 16; + + if (hstEnd > 64) + hstEnd = 64; + else if (hstEnd < 48) + hstEnd = 48; + + oMap[64] = 1024; /* 0~1024 */ + /*64 bins, max, ave*/ + lAvg4 = 0; + lAvg1 = 0; + for (i = 0; i < 64; i++) { + oHst[i] = iHst[i]; + oMap[i] = (i << 4); /* 0~1024 */ + + tHst[i] = iHst[i]; + idx[i] = i; + + if (i >= hstBgn && i <= hstEnd-1) { + if (tmax < iHst[i]) + tmax = iHst[i]; + tsum += iHst[i]; + lAvg4 += (iHst[i] * i); + } else { + oHst[i] = 0; + } + + lcl_lmt[i] = old_dnlp_lrate[(i>>1)]; + } + lAvg4 = (lAvg4 << 2) + tsum / 2; + lAvg4 = lAvg4 / tsum; + lAvg1 = (lAvg4 + 2) >> 2; + + /* << 4 */ + adp_crate = dnlp_adp_cliprate(clip_rate, clip_rmin, lAvg1); + + prt_flg = ((dnlp_printk >> 9) & 0x1); + if (prt_flg) + pr_info("#CL: Range[%02d ~ %02d] lAvg4=%d(%d), (crate << 4)=%d\n", + hstBgn, hstEnd, lAvg4, lAvg1, adp_crate); + + for (i = 1; i <= 61; i += 2) + lcl_lmt[i] = ((lcl_lmt[i-1] + lcl_lmt[i+1] + 1)>>1); + + if (hstEnd <= hstBgn) + return; + + cLmt = (adp_crate * tsum) >> 2; + cLmt = (cLmt + 2048) >> 12; + + tAvg = (tsum + tLen/2)/tLen; + + /* sort histogram */ + for (i = hstBgn; i < hstEnd; i++) { + for (j = hstBgn; j < (hstEnd - i - 1); j++) { + if (tHst[j] < tHst[j+1]) { + nExc = tHst[j]; + tHst[j] = tHst[j+1]; + tHst[j+1] = nExc; + + nNum = idx[j]; + idx[j] = idx[j+1]; + idx[j+1] = nNum; + } + } + } + + /* local clip rate */ + if (ve_dnlp_glb_crate == 0) { + for (i = 0; i < 64; i++) + lcl_lmt[i] = ((lcl_lmt[i]*cLmt+32) >> 6); + } else { + for (i = 0; i < 64; i++) + lcl_lmt[i] = cLmt; + } + /* the largest bins should be improved */ + nStp = tAvg * ve_dnlp_hghbin + 32; + nStp = (nStp >> 6); + for (j = 0; j < ve_dnlp_hghnum; j++) { + i = idx[j]; + + if (lcl_lmt[i] < nStp) + lcl_lmt[i] = nStp; + } + + /* the lowest bins */ + nStp = tAvg * ve_dnlp_lowbin + 32; + nStp = (nStp >> 6); + for (j = 0; j < ve_dnlp_lownum; j++) { + i = idx[tLen - 1 - j]; + + /* max */ + nT0 = (nStp > tHst[i]) ? nStp : tHst[i]; + + if (lcl_lmt[i] > nT0) + lcl_lmt[i] = nT0; + } + + /* black protect */ + nStp = tAvg * ve_blk_prct_max + 4; + nStp = (nStp >> 3); + for (i = 0; i < ve_blk_prct_rng; i++) { + nT0 = (ve_blk_prct_rng - i); + if (iHst[i] > nStp) + nT0 = nT0 * (iHst[i] - nStp); + else + nT0 = 0; + + if (lcl_lmt[i] > (nT0 + tAvg)) + nT0 = lcl_lmt[i] - nT0; + else + nT0 = tAvg; + + if (nT0 < tAvg) + nT0 = tAvg; + + if (prt_flg) + pr_info("clmt[%d]: %4d -> %4d\n", + i, lcl_lmt[i], nT0); + } /* black protect */ + + nExc = 0; + nNum = 0; + for (i = hstBgn; i < hstEnd; i++) { + if (iHst[i] > lcl_lmt[i]) { + nExc += (iHst[i] - lcl_lmt[i]); + oHst[i] = lcl_lmt[i]; + } else { + nNum++; + oHst[i] = iHst[i]; + } + } + + if (clip_rate <= 8 || tAvg <= 2) { + cLmt = (tsum + tLen/2)/tLen; + tsum = cLmt*tLen; + for (i = hstBgn; i < hstEnd; i++) + oHst[i] = cLmt; + + } else { + while ((nNum > 0) && (nExc > 0)) { + nStp = (nExc+nNum/2)/nNum; + + tExc = nExc; + + for (j = 0; j < 64; j++) { + i = idx[j]; + if ((i < hstBgn) || (i > hstEnd-1)) + continue; + + if ((oHst[i] + nStp) < lcl_lmt[i]) { + oHst[i] = oHst[i] + nStp; + nExc = nExc - nStp; + } else if (lcl_lmt[i] > oHst[i]) { + oHst[i] = lcl_lmt[i]; + nExc = nExc - (lcl_lmt[i] - oHst[i]); + nNum = nNum - 1; + } + + if ((nNum <= 0) || (nExc <= 0)) + break; + } + + if (nExc == tExc) + break; + } /* end while */ + + if (nNum == 0 && tExc > 0 && nExc > tLen) { + nStp = (nExc + tLen/2)/tLen; + for (i = hstBgn; i < hstEnd; i++) + oHst[i] = oHst[i] + nStp; + } + } + + /*hstBgn:hstEnd-1*/ + tsum = 0; + for (i = hstBgn; i < hstEnd; i++) { + /*if(oHst[i]>cLmt)*/ + /*oHst[i] = cLmt;*/ + tsum += oHst[i]; + } + + nStp = 0; + /*sum -= oHst[4];*/ + for (i = hstBgn; i < hstEnd; i++) { + nStp += oHst[i]; + + j = ((hstEnd - hstBgn)*nStp << 4); + j += (tsum>>1); + j /= tsum; + oMap[i+1] = j + (hstBgn << 4); + } + + if (prt_flg) + for (i = hstBgn; i < hstEnd; i++) + pr_info("#CL: [%02d: %5d]: %4d => %4d]\n", + i, iHst[i], i<<4, oMap[i]); +} + +/*xhu*/ +int old_dnlp_mvreflsh; +int old_dnlp_gmma_rate; +int old_dnlp_lowalpha_new; +int old_dnlp_hghalpha_new; +int old_dnlp_sbgnbnd; +int old_dnlp_sendbnd; +int old_dnlp_cliprate_new; +int old_dnlp_clashBgn; +int old_dnlp_clashEnd; +int old_mtdbld_rate; +int old_dnlp_pst_gmarat; +int old_dnlp_blk_cctr; +int old_dnlp_brgt_ctrl; +int old_dnlp_brgt_range; +int old_dnlp_brght_add; +int old_dnlp_brght_max; +int old_dnlp_lgst_bin; +int old_dnlp_lgst_dst; +int old_dnlp_almst_wht; +int old_dnlp_hghbin; +int old_dnlp_hghnum; +int old_dnlp_lowbin; +int old_dnlp_lownum; +int old_dnlp_bkgend; +int old_dnlp_bkgert; +int old_dnlp_pstgma_brghtrate; +int old_dnlp_pstgma_brghtrat1; +int old_dnlp_blkext; +int old_dnlp_whtext; +int old_dnlp_bextmx; +int old_dnlp_wextmx; +int old_dnlp_wext_autorat; +int old_dnlp_lavg_cum; +int old_dnlp_schg_sft; +bool old_dnlp_smhist_ck; +bool old_dnlp_glb_crate; +int old_dnlp_cuvbld_min; +int old_dnlp_cuvbld_max; +int old_dnlp_dbg_map; +bool old_dnlp_dbg_adjavg; +int old_dnlp_dbg_i2r; +int old_dnlp_slow_end; +int old_dnlp_pavg_btsft; +int old_dnlp_dbg0331; +int old_dnlp_cliprate_min; +int old_dnlp_adpcrat_lbnd; +int old_dnlp_adpcrat_hbnd; +int old_dnlp_adpmtd_lbnd; +int old_dnlp_adpmtd_hbnd; +int old_dnlp_set_bext; +int old_dnlp_set_wext; + +int old_dnlp_satur_rat; +int old_dnlp_satur_max; +int old_blk_prct_rng; +int old_blk_prct_max; + +int old_dnlp_lowrange; +int old_dnlp_hghrange; +int old_dnlp_auto_rng; + +int old_dnlp_bin0_absmax; +int old_dnlp_bin0_sbtmax; + +int old_dnlp_adpalpha_lrate; +int old_dnlp_adpalpha_hrate; + +static int cal_brght_plus(int luma_avg4, int low_lavg4) +{ + int avg_dif = 0; + int dif_rat = 0; + + int low_rng = 0; + int low_rat = 0; + + int dnlp_brightness = 0; + static int pbrtness; + + if (luma_avg4 > low_lavg4) + avg_dif = luma_avg4 - low_lavg4; + + if (avg_dif < ve_dnlp_blk_cctr) + dif_rat = ve_dnlp_blk_cctr - avg_dif; + + if (luma_avg4 > ve_dnlp_brgt_ctrl) + low_rng = luma_avg4 - ve_dnlp_brgt_ctrl; + else + low_rng = ve_dnlp_brgt_ctrl - luma_avg4; + + if (low_rng < ve_dnlp_brgt_range) + low_rat = ve_dnlp_brgt_range - low_rng; + + /* <<2 */ + dnlp_brightness = (ve_dnlp_brght_max*dif_rat*low_rat + 16)>>5; + /* add=32 => add 0 */ + dnlp_brightness += ((ve_dnlp_brght_add - 32) << 2); + + if (!dnlp_scn_chg) { + dnlp_brightness = dnlp_bld_lvl * dnlp_brightness + (RBASE >> 1); + dnlp_brightness = dnlp_brightness + + (RBASE - dnlp_bld_lvl) * pbrtness; + dnlp_brightness = (dnlp_brightness >> ve_dnlp_mvreflsh); + } + pbrtness = dnlp_brightness; + + return dnlp_brightness; /* 0 ~ 1024 */ +} + +int gma_scurve0[65]; /* gamma0 s-curve */ +int gma_scurve1[65]; /* gamma1 s-curve */ +int gma_scurvet[65]; /* gmma0+gamm1 s-curve */ +int clash_curve[65]; /* clash curve */ +int clsh_scvbld[65]; /* clash + s-curve blend */ + +int blk_gma_crv[65]; /* black gamma curve */ +int blk_gma_bld[65]; /* blending with black gamma */ + +int blkwht_ebld[65]; /* black white extension */ + +/*xhu*/ +/* only for debug */ +static unsigned int premap0[64]; + +static int pcurves[8][64]; + +static void clash_blend(void) +{ + int i = 0; + int nTmp0 = 0; + static unsigned int pgmma[65]; + + if (!ve_dnlp_luma_sum) { + for (i = 0; i < 65; i++) + pgmma[i] = (i << 4); /* 0 ~1024 */ + } + + if (!dnlp_scn_chg && ((ve_dnlp_dbg_i2r >> 3) & 0x1)) + for (i = 0; i < 65; i++) { + nTmp0 = dnlp_bld_lvl * clash_curve[i] + (RBASE >> 1); + nTmp0 = nTmp0 + (RBASE - dnlp_bld_lvl) * pgmma[i]; + nTmp0 = (nTmp0 >> ve_dnlp_mvreflsh); + clash_curve[i] = nTmp0; + } + + for (i = 0; i < 65; i++) + pgmma[i] = clash_curve[i]; +} + +int curve_rfrsh_chk(int hstSum, int rbase) +{ + static unsigned int tLumAvg[30]; + static unsigned int tAvgDif[30]; + bool prt_flg = 0; + int lSby = 0; + int bld_lvl = 0; + int i = 0; + + for (i = 0; i < 29; i++) { + tLumAvg[i] = tLumAvg[i+1]; + tAvgDif[i] = tAvgDif[i+1]; + } + + tLumAvg[29] = (ve_dnlp_luma_sum + (hstSum >> 1)) / hstSum; + tLumAvg[29] = ((tLumAvg[29] + 4) >> 3); + tAvgDif[29] = (tLumAvg[29] > tLumAvg[28]) ? + (tLumAvg[29] - tLumAvg[28]) : (tLumAvg[28] - tLumAvg[29]); + + /* prt_flg = ((dnlp_printk >> 7) & 0x1); */ + prt_flg = (dnlp_printk & 0x1); + + lSby = 0; + for (i = 0; i < 8; i++) + lSby = lSby + tAvgDif[28 - i]; + lSby = ((lSby + 4) >> 3); + + if (tAvgDif[29] > tAvgDif[28]) + bld_lvl = tAvgDif[29] - tAvgDif[28]; + else + bld_lvl = tAvgDif[28] - tAvgDif[29]; + + bld_lvl = (bld_lvl << ve_dnlp_schg_sft); + + if (prt_flg) + pr_info("bld_lvl=%02d\n", bld_lvl); + + /* play station: return with black scene intersection */ + if (tAvgDif[29] > bld_lvl) + bld_lvl = tAvgDif[29]; + + if (bld_lvl > rbase) + bld_lvl = rbase; + else if (bld_lvl < ve_dnlp_cuvbld_min) + bld_lvl = ve_dnlp_cuvbld_min; + else if (bld_lvl > ve_dnlp_cuvbld_max) + bld_lvl = ve_dnlp_cuvbld_max; + + if (prt_flg) { + pr_info("bld_lvl=%02d, lSby=%02d\n", + bld_lvl, lSby); + + for (i = 0; i < 10; i++) + pr_info("tLumAvg[%d]: = %d\n", + i, tLumAvg[29 - i]); + + for (i = 0; i < 10; i++) + pr_info("tAvgDif[%d]: = %d\n", + i, tAvgDif[29 - i]); + } + return bld_lvl; +} + +static void dnlp3_param_refrsh(void) +{ + if (dnlp_respond) { + if ((old_dnlp_mvreflsh != ve_dnlp_mvreflsh) || + (old_dnlp_gmma_rate != ve_dnlp_gmma_rate) || + (old_dnlp_lowalpha_new != ve_dnlp_lowalpha_new) || + (old_dnlp_hghalpha_new != ve_dnlp_hghalpha_new) || + (old_dnlp_sbgnbnd != ve_dnlp_sbgnbnd) || + (old_dnlp_sendbnd != ve_dnlp_sendbnd) || + (old_dnlp_cliprate_new != ve_dnlp_cliprate_new) || + (old_dnlp_clashBgn != ve_dnlp_clashBgn) || + (old_dnlp_clashEnd != ve_dnlp_clashEnd) || + (old_mtdbld_rate != ve_mtdbld_rate) || + (old_dnlp_pst_gmarat != ve_dnlp_pst_gmarat) || + (old_dnlp_blk_cctr != ve_dnlp_blk_cctr) || + (old_dnlp_brgt_ctrl != ve_dnlp_brgt_ctrl) || + (old_dnlp_brgt_range != ve_dnlp_brgt_range) || + (old_dnlp_brght_add != ve_dnlp_brght_add) || + (old_dnlp_brght_max != ve_dnlp_brght_max) || + (old_dnlp_lgst_bin != ve_dnlp_lgst_bin) || + (old_dnlp_lgst_dst != ve_dnlp_lgst_dst) || + (old_dnlp_almst_wht != ve_dnlp_almst_wht) || + (old_dnlp_glb_crate != ve_dnlp_glb_crate) || + (old_dnlp_lrate[0] != ve_dnlp_lrate00) || + (old_dnlp_lrate[1] != ve_dnlp_lrate02) || + (old_dnlp_lrate[2] != ve_dnlp_lrate04) || + (old_dnlp_lrate[3] != ve_dnlp_lrate06) || + (old_dnlp_lrate[4] != ve_dnlp_lrate08) || + (old_dnlp_lrate[5] != ve_dnlp_lrate10) || + (old_dnlp_lrate[6] != ve_dnlp_lrate12) || + (old_dnlp_lrate[7] != ve_dnlp_lrate14) || + (old_dnlp_lrate[8] != ve_dnlp_lrate16) || + (old_dnlp_lrate[9] != ve_dnlp_lrate18) || + (old_dnlp_lrate[10] != ve_dnlp_lrate20) || + (old_dnlp_lrate[11] != ve_dnlp_lrate22) || + (old_dnlp_lrate[12] != ve_dnlp_lrate24) || + (old_dnlp_lrate[13] != ve_dnlp_lrate26) || + (old_dnlp_lrate[14] != ve_dnlp_lrate28) || + (old_dnlp_lrate[15] != ve_dnlp_lrate30) || + (old_dnlp_lrate[16] != ve_dnlp_lrate32) || + (old_dnlp_lrate[17] != ve_dnlp_lrate34) || + (old_dnlp_lrate[18] != ve_dnlp_lrate36) || + (old_dnlp_lrate[19] != ve_dnlp_lrate38) || + (old_dnlp_lrate[20] != ve_dnlp_lrate40) || + (old_dnlp_lrate[21] != ve_dnlp_lrate42) || + (old_dnlp_lrate[22] != ve_dnlp_lrate44) || + (old_dnlp_lrate[23] != ve_dnlp_lrate46) || + (old_dnlp_lrate[24] != ve_dnlp_lrate48) || + (old_dnlp_lrate[25] != ve_dnlp_lrate50) || + (old_dnlp_lrate[26] != ve_dnlp_lrate52) || + (old_dnlp_lrate[27] != ve_dnlp_lrate54) || + (old_dnlp_lrate[28] != ve_dnlp_lrate56) || + (old_dnlp_lrate[29] != ve_dnlp_lrate58) || + (old_dnlp_lrate[30] != ve_dnlp_lrate60) || + (old_dnlp_lrate[31] != ve_dnlp_lrate62) || + (old_dnlp_hghbin != ve_dnlp_hghbin) || + (old_dnlp_hghnum != ve_dnlp_hghnum) || + (old_dnlp_lowbin != ve_dnlp_lowbin) || + (old_dnlp_lownum != ve_dnlp_lownum) || + (old_dnlp_bkgend != ve_dnlp_bkgend) || + (old_dnlp_bkgert != ve_dnlp_bkgert) || + (old_dnlp_pstgma_brghtrate != + ve_dnlp_pstgma_brghtrate) || + (old_dnlp_pstgma_brghtrat1 != + ve_dnlp_pstgma_brghtrat1) || + (old_dnlp_blkext != ve_dnlp_blkext) || + (old_dnlp_whtext != ve_dnlp_whtext) || + (old_dnlp_bextmx != ve_dnlp_bextmx) || + (old_dnlp_wextmx != ve_dnlp_wextmx) || + (old_dnlp_wext_autorat != ve_dnlp_wext_autorat) || + (old_dnlp_schg_sft != ve_dnlp_schg_sft) || + (old_dnlp_smhist_ck != ve_dnlp_smhist_ck) || + (old_dnlp_cuvbld_min != ve_dnlp_cuvbld_min) || + (old_dnlp_cuvbld_max != ve_dnlp_cuvbld_max) || + (old_dnlp_dbg_map != ve_dnlp_dbg_map) || + (old_dnlp_dbg_adjavg != ve_dnlp_dbg_adjavg) || + (old_dnlp_dbg_i2r != ve_dnlp_dbg_i2r) || + (old_dnlp_slow_end != ve_dnlp_slow_end) || + (old_dnlp_pavg_btsft != ve_dnlp_pavg_btsft) || + (old_dnlp_cliprate_min != ve_dnlp_cliprate_min) || + (old_dnlp_adpcrat_lbnd != ve_dnlp_adpcrat_lbnd) || + (old_dnlp_adpcrat_hbnd != ve_dnlp_adpcrat_hbnd) || + (old_dnlp_adpmtd_lbnd != ve_dnlp_adpmtd_lbnd) || + (old_dnlp_adpmtd_hbnd != ve_dnlp_adpmtd_hbnd) || + (old_dnlp_set_bext != ve_dnlp_set_bext) || + (old_dnlp_set_wext != ve_dnlp_set_wext) || + (old_dnlp_satur_rat != ve_dnlp_satur_rat) || + (old_dnlp_satur_max != ve_dnlp_satur_max) || + (old_blk_prct_rng != ve_blk_prct_rng) || + (old_blk_prct_max != ve_blk_prct_max) || + (old_dnlp_lowrange != ve_dnlp_lowrange) || + (old_dnlp_hghrange != ve_dnlp_hghrange) || + (old_dnlp_auto_rng != ve_dnlp_auto_rng) || + (old_dnlp_bin0_absmax != ve_dnlp_bin0_absmax) || + (old_dnlp_bin0_sbtmax != ve_dnlp_bin0_sbtmax) || + (old_dnlp_adpalpha_lrate != ve_dnlp_adpalpha_lrate) || + (old_dnlp_adpalpha_hrate != ve_dnlp_adpalpha_hrate)) + ve_dnlp_respond_flag = 1; + else + ve_dnlp_respond_flag = 0; + } + + old_dnlp_mvreflsh = ve_dnlp_mvreflsh; + old_dnlp_gmma_rate = ve_dnlp_gmma_rate; + old_dnlp_lowalpha_new = ve_dnlp_lowalpha_new; + old_dnlp_hghalpha_new = ve_dnlp_hghalpha_new; + old_dnlp_sbgnbnd = ve_dnlp_sbgnbnd; + old_dnlp_sendbnd = ve_dnlp_sendbnd; + old_dnlp_cliprate_new = ve_dnlp_cliprate_new; + old_dnlp_clashBgn = ve_dnlp_clashBgn; + old_dnlp_clashEnd = ve_dnlp_clashEnd; + old_mtdbld_rate = ve_mtdbld_rate; + old_dnlp_pst_gmarat = ve_dnlp_pst_gmarat; + old_dnlp_blk_cctr = ve_dnlp_blk_cctr; + old_dnlp_brgt_ctrl = ve_dnlp_brgt_ctrl; + old_dnlp_brgt_range = ve_dnlp_brgt_range; + old_dnlp_brght_add = ve_dnlp_brght_add; + old_dnlp_brght_max = ve_dnlp_brght_max; + old_dnlp_lgst_bin = ve_dnlp_lgst_bin; + old_dnlp_lgst_dst = ve_dnlp_lgst_dst; + old_dnlp_almst_wht = ve_dnlp_almst_wht; + old_dnlp_glb_crate = ve_dnlp_glb_crate; + old_dnlp_lrate[0] = ve_dnlp_lrate00; + old_dnlp_lrate[1] = ve_dnlp_lrate02; + old_dnlp_lrate[2] = ve_dnlp_lrate04; + old_dnlp_lrate[3] = ve_dnlp_lrate06; + old_dnlp_lrate[4] = ve_dnlp_lrate08; + old_dnlp_lrate[5] = ve_dnlp_lrate10; + old_dnlp_lrate[6] = ve_dnlp_lrate12; + old_dnlp_lrate[7] = ve_dnlp_lrate14; + old_dnlp_lrate[8] = ve_dnlp_lrate16; + old_dnlp_lrate[9] = ve_dnlp_lrate18; + old_dnlp_lrate[10] = ve_dnlp_lrate20; + old_dnlp_lrate[11] = ve_dnlp_lrate22; + old_dnlp_lrate[12] = ve_dnlp_lrate24; + old_dnlp_lrate[13] = ve_dnlp_lrate26; + old_dnlp_lrate[14] = ve_dnlp_lrate28; + old_dnlp_lrate[15] = ve_dnlp_lrate30; + old_dnlp_lrate[16] = ve_dnlp_lrate32; + old_dnlp_lrate[17] = ve_dnlp_lrate34; + old_dnlp_lrate[18] = ve_dnlp_lrate36; + old_dnlp_lrate[19] = ve_dnlp_lrate38; + old_dnlp_lrate[20] = ve_dnlp_lrate40; + old_dnlp_lrate[21] = ve_dnlp_lrate42; + old_dnlp_lrate[22] = ve_dnlp_lrate44; + old_dnlp_lrate[23] = ve_dnlp_lrate46; + old_dnlp_lrate[24] = ve_dnlp_lrate48; + old_dnlp_lrate[25] = ve_dnlp_lrate50; + old_dnlp_lrate[26] = ve_dnlp_lrate52; + old_dnlp_lrate[27] = ve_dnlp_lrate54; + old_dnlp_lrate[28] = ve_dnlp_lrate56; + old_dnlp_lrate[29] = ve_dnlp_lrate58; + old_dnlp_lrate[30] = ve_dnlp_lrate60; + old_dnlp_lrate[31] = ve_dnlp_lrate62; + old_dnlp_hghbin = ve_dnlp_hghbin; + old_dnlp_hghnum = ve_dnlp_hghnum; + old_dnlp_lowbin = ve_dnlp_lowbin; + old_dnlp_lownum = ve_dnlp_lownum; + + old_dnlp_bkgend = ve_dnlp_bkgend; + old_dnlp_bkgert = ve_dnlp_bkgert; + old_dnlp_pstgma_brghtrate = ve_dnlp_pstgma_brghtrate; + old_dnlp_pstgma_brghtrat1 = ve_dnlp_pstgma_brghtrat1; + + old_dnlp_blkext = ve_dnlp_blkext; + old_dnlp_whtext = ve_dnlp_whtext; + old_dnlp_bextmx = ve_dnlp_bextmx; + old_dnlp_wextmx = ve_dnlp_wextmx; + old_dnlp_wext_autorat = ve_dnlp_wext_autorat; + + old_dnlp_schg_sft = ve_dnlp_schg_sft; + + old_dnlp_smhist_ck = ve_dnlp_smhist_ck; + old_dnlp_cuvbld_min = ve_dnlp_cuvbld_min; + old_dnlp_cuvbld_max = ve_dnlp_cuvbld_max; + old_dnlp_dbg_map = ve_dnlp_dbg_map; + old_dnlp_dbg_adjavg = ve_dnlp_dbg_adjavg; + old_dnlp_dbg_i2r = ve_dnlp_dbg_i2r; + old_dnlp_slow_end = ve_dnlp_slow_end; + old_dnlp_pavg_btsft = ve_dnlp_pavg_btsft; + old_dnlp_pavg_btsft = ve_dnlp_pavg_btsft; + old_dnlp_cliprate_min = ve_dnlp_cliprate_min; + old_dnlp_adpcrat_lbnd = ve_dnlp_adpcrat_lbnd; + old_dnlp_adpcrat_hbnd = ve_dnlp_adpcrat_hbnd; + + old_dnlp_adpmtd_lbnd = ve_dnlp_adpmtd_lbnd; + old_dnlp_adpmtd_hbnd = ve_dnlp_adpmtd_hbnd; + old_dnlp_set_bext = ve_dnlp_set_bext; + old_dnlp_set_wext = ve_dnlp_set_wext; + + old_dnlp_satur_rat = ve_dnlp_satur_rat; + old_dnlp_satur_max = ve_dnlp_satur_max; + old_blk_prct_rng = ve_blk_prct_rng; + old_blk_prct_max = ve_blk_prct_max; + + old_dnlp_lowrange = ve_dnlp_lowrange; + old_dnlp_hghrange = ve_dnlp_hghrange; + old_dnlp_auto_rng = ve_dnlp_auto_rng; + + old_dnlp_bin0_absmax = ve_dnlp_bin0_absmax; + old_dnlp_bin0_sbtmax = ve_dnlp_bin0_sbtmax; + old_dnlp_adpalpha_hrate = ve_dnlp_adpalpha_hrate; + old_dnlp_adpalpha_lrate = ve_dnlp_adpalpha_lrate; +} + +static void dnlp_rfrsh_subgmma(void) +{ + int i = 0; + static unsigned int pgmma0[65]; /* 0~4096*/ + static unsigned int pgmma1[65]; + + if (!ve_dnlp_luma_sum) { + for (i = 0; i < 65; i++) { + pgmma0[i] = (i << 6); /* 0 ~4096 */ + pgmma1[i] = (i << 6); /* 0 ~4096 */ + } + } + + if (!dnlp_scn_chg) + for (i = 0; i < 65; i++) { + gma_scurve0[i] = dnlp_bld_lvl * + (gma_scurve0[i] << 2) + (RBASE >> 1); + gma_scurve1[i] = dnlp_bld_lvl * + (gma_scurve1[i] << 2) + (RBASE >> 1); + + gma_scurve0[i] = gma_scurve0[i] + + (RBASE - dnlp_bld_lvl) * pgmma0[i]; + gma_scurve1[i] = gma_scurve1[i] + + (RBASE - dnlp_bld_lvl) * pgmma1[i]; + + gma_scurve0[i] = (gma_scurve0[i] >> ve_dnlp_mvreflsh); + gma_scurve1[i] = (gma_scurve1[i] >> ve_dnlp_mvreflsh); + + pgmma0[i] = gma_scurve0[i]; /* 0~ 4095 */ + pgmma1[i] = gma_scurve1[i]; /* 0~ 4095 */ + + gma_scurve0[i] = (gma_scurve0[i] + 2) >> 2; /* 1023 */ + gma_scurve1[i] = (gma_scurve1[i] + 2) >> 2; /* 1023 */ + } + else + for (i = 0; i < 65; i++) { + pgmma0[i] = (gma_scurve0[i] << 2); + pgmma1[i] = (gma_scurve1[i] << 2); + } +} + +static void dnlp_inhist_lpf(void) +{ + int i = 0; + int nTmp = 0; + static unsigned int pgmma0[65]; + static unsigned int luma_sum; + + if (!dnlp_scn_chg && (ve_dnlp_dbg_i2r & 0x1)) { + for (i = 0; i < 65; i++) { + nTmp = dnlp_bld_lvl * pre_0_gamma[i] + (RBASE >> 1); + nTmp = nTmp + (RBASE - dnlp_bld_lvl) * pgmma0[i]; + nTmp = (nTmp >> ve_dnlp_mvreflsh); + pre_0_gamma[i] = nTmp; + } + + nTmp = dnlp_bld_lvl * ve_dnlp_luma_sum + (RBASE >> 1); + nTmp = nTmp + (RBASE - dnlp_bld_lvl) * luma_sum; + nTmp = (nTmp >> ve_dnlp_mvreflsh); + ve_dnlp_luma_sum = nTmp; + } + + for (i = 0; i < 65; i++) + pgmma0[i] = pre_0_gamma[i]; + luma_sum = ve_dnlp_luma_sum; +} + + +/*0 ~ 65*/ +static void dnlp_gmma_cuvs(unsigned int gmma_rate, + unsigned int low_alpha, unsigned int hgh_alpha, + unsigned int lsft_avg) +{ + int i = 0; + int nTmp = 0; + unsigned int luma_avg4 = (lsft_avg >> ve_dnlp_pavg_btsft); + + static unsigned int pgmma[65]; + bool prt_flg = ((dnlp_printk >> 10) & 0x1); + + if (!ve_dnlp_luma_sum) { + for (i = 0; i < 65; i++) + pgmma[i] = (i << 6); /* 0 ~4096 */ + } + + /* refresh sub gamma */ + if ((ve_dnlp_dbg_i2r >> 1) & 0x1) + dnlp_rfrsh_subgmma(); + + if (prt_flg) + pr_info("gmma_cuvs: %3d %3d %3d %3d\n", + gmma_rate, low_alpha, hgh_alpha, luma_avg4); + + for (i = 0; i < 65; i++) { + nTmp = (((256 - gmma_rate)*gma_scurve0[i] + + gma_scurve1[i]*gmma_rate + 128) >> 8); /* 0 ~1023 */ + + if (nTmp <= (luma_avg4<<2)) + nTmp = (nTmp*(64 - low_alpha) + + (low_alpha*i<<4) + 8)>>4; /*4096*/ + else + nTmp = (nTmp*(64 - hgh_alpha) + + (hgh_alpha*i<<4) + 8)>>4; + + if (nTmp < 0) + nTmp = 0; + else if (nTmp > 4095) + nTmp = 4095; + gma_scurvet[i] = nTmp; + + if (prt_flg) + pr_info("gmma_cuvs: [%02d] %4d %4d => %4d\n", + i, gma_scurve0[i], gma_scurve1[i], + gma_scurvet[i]); + } + + if (!dnlp_scn_chg && ((ve_dnlp_dbg_i2r >> 2) & 0x1)) + for (i = 0; i < 65; i++) { + nTmp = dnlp_bld_lvl * gma_scurvet[i] + (RBASE >> 1); + nTmp = nTmp + (RBASE - dnlp_bld_lvl) * pgmma[i]; + nTmp = (nTmp >> ve_dnlp_mvreflsh); + + gma_scurvet[i] = nTmp; /* 4095 */ + } + + for (i = 0; i < 65; i++) + pgmma[i] = gma_scurvet[i]; /* 4095 */ + + for (i = 0; i < 65; i++) + gma_scurvet[i] = ((gma_scurvet[i] + 2) >> 2); /*1023*/ +} + +/* clsh_scvbld = clash_curve + gma_scurvet */ +static void dnlp_clsh_sbld(unsigned int mtdbld_rate) +{ + int i = 0; + int nTmp0 = 0; + + static unsigned int pgmma[65]; + + if (!ve_dnlp_luma_sum) { + for (i = 0; i < 65; i++) + pgmma[i] = (i << 4); /* 0 ~1024 */ + } + + for (i = 0; i < 65; i++) { + nTmp0 = gma_scurvet[i]; /* 0 ~1024 */ + nTmp0 = nTmp0*mtdbld_rate + clash_curve[i]*(64 - mtdbld_rate); + nTmp0 = (nTmp0 + 32)>>6; /* 0~1024 */ + clsh_scvbld[i] = nTmp0; + } + + if (!dnlp_scn_chg && ((ve_dnlp_dbg_i2r >> 4) & 0x1)) + for (i = 0; i < 65; i++) { + nTmp0 = dnlp_bld_lvl * clsh_scvbld[i] + (RBASE >> 1); + nTmp0 = nTmp0 + (RBASE - dnlp_bld_lvl) * pgmma[i]; + nTmp0 = (nTmp0 >> ve_dnlp_mvreflsh); + + clsh_scvbld[i] = nTmp0; + } + + for (i = 0; i < 65; i++) + pgmma[i] = clsh_scvbld[i]; /* 1023 */ +} + +/* blk_gma_rat[64] */ +/* blk_gma_bld = blk_gma_crv + clsh_scvbld */ +static void dnlp_blkgma_bld(unsigned int *blk_gma_rat) +{ + int nT1 = 0; + int nTmp0 = 0; + int i = 0; + static unsigned int pgmma[65]; + + if (!ve_dnlp_luma_sum) { + for (i = 0; i < 65; i++) + pgmma[i] = (i << 4); /* 0 ~1024 */ + } + + for (i = 0; i < 64; i++) { + nT1 = blk_gma_rat[i]; + nTmp0 = clsh_scvbld[i]; + + nTmp0 = blk_gma_crv[i]*nT1 + nTmp0*(64 - nT1); + nTmp0 = (nTmp0+32)>>6; /* 0~1024 */ + blk_gma_bld[i] = nTmp0; + + if ((dnlp_printk >> 2) & 0x1) + pr_info("sc%04d, gm%04d * rat%04d => %04d\n", + clsh_scvbld[i], blk_gma_crv[i], nT1, nTmp0); + } + blk_gma_bld[64] = 1023; + + if (!dnlp_scn_chg && ((ve_dnlp_dbg_i2r >> 5) & 0x1)) + for (i = 0; i < 65; i++) { + nTmp0 = dnlp_bld_lvl * blk_gma_bld[i] + (RBASE >> 1); + nTmp0 = nTmp0 + (RBASE - dnlp_bld_lvl) * pgmma[i]; + nTmp0 = (nTmp0 >> ve_dnlp_mvreflsh); + + blk_gma_bld[i] = nTmp0; + } + + for (i = 0; i < 65; i++) + pgmma[i] = blk_gma_bld[i]; /* 1023 */ +} + +/* blkwht_ebld = blk_gma_bld + extension */ +static void dnlp_blkwht_bld(int *blk_wht_ext, int bright, + unsigned int luma_avg4, unsigned int luma_avg, + unsigned int iRgnBgn, unsigned int iRgnEnd) +{ + int nT0 = 0; + int nT1 = 0; + int nTmp0 = 0; + int i = 0; + static unsigned int pgmma[65]; + + if (!ve_dnlp_luma_sum) { + for (i = 0; i < 65; i++) + pgmma[i] = (i << 4); /* 0 ~1024 */ + } + + /* black / white extension */ + for (i = 0; i < 64; i++) { + nTmp0 = blk_gma_bld[i]; + if ((luma_avg4 > (iRgnBgn << 2)) && (i <= luma_avg)) { + nT0 = (luma_avg4 - 4*iRgnBgn); + nT1 = blk_wht_ext[0] * (luma_avg4 - 4*i); + nT1 += (nT0 >> 1); + nT1 = nT1 / nT0; + + nT0 = nTmp0 - nT1; + } else if ((luma_avg4 < 4*(iRgnEnd - 1)) && (i >= luma_avg)) { + nT0 = 4*(iRgnEnd - 1) - luma_avg4; + nT1 = blk_wht_ext[1] * (4*i - luma_avg4) + (nT0 >> 1); + nT1 = nT1 / nT0; + + nT0 = nTmp0 + nT1; + } else + nT0 = nTmp0; + + + /* nTmp += dnlp_brightness; */ + nT0 = bright + nT0; + if (nT0 < 0) + nTmp0 = 0; + else if (nT0 > 1023) + nTmp0 = 1023; + else + nTmp0 = nT0; + + blkwht_ebld[i] = nT0; + } + blkwht_ebld[0] = 0; + blkwht_ebld[64] = 1023; + + if (!dnlp_scn_chg && ((ve_dnlp_dbg_i2r >> 6) & 0x1)) + for (i = 0; i < 65; i++) { + nTmp0 = dnlp_bld_lvl * blkwht_ebld[i] + (RBASE >> 1); + nTmp0 = nTmp0 + (RBASE - dnlp_bld_lvl) * pgmma[i]; + nTmp0 = (nTmp0 >> ve_dnlp_mvreflsh); + + blkwht_ebld[i] = nTmp0; + } + + for (i = 0; i < 65; i++) + pgmma[i] = blkwht_ebld[i]; /* 1023 */ +} + +static void dnlp_params_hist(unsigned int *gmma_rate, + unsigned int *low_alpha, unsigned int *hgh_alpha, + unsigned int *mtdbld_rate, + unsigned int luma_avg, unsigned int luma_avg4) +{ + static unsigned int pgmma0[4][7]; + int nTmp = 0; + int i = 0; + int trate = *gmma_rate; + int tlowa = *low_alpha; + int thgha = *hgh_alpha; + int tmrat = *mtdbld_rate; + + nTmp = (luma_avg > 31) ? luma_avg-31 : 31-luma_avg; + nTmp = (32 - nTmp + 2) >> 2; + + trate = trate + nTmp; + if (trate > 255) + trate = 255; + + if (luma_avg4 <= 32) + tlowa = tlowa + (32 - luma_avg4); + + if (luma_avg4 >= 224) { + if (tlowa < (luma_avg4 - 224)) + tlowa = 0; + else + tlowa = tlowa - (luma_avg4 - 224); + } + + if (!dnlp_scn_chg) { + for (i = 0; i < 7; i++) { + trate += pgmma0[0][i]; + tlowa += pgmma0[1][i]; + thgha += pgmma0[2][i]; + tmrat += pgmma0[3][i]; + } + trate = ((trate + 4)>>3); + tlowa = ((tlowa + 4)>>3); + thgha = ((thgha + 4)>>3); + tmrat = ((tmrat + 4)>>3); + + for (i = 0; i < 6; i++) { + pgmma0[0][i] = pgmma0[0][i + 1]; + pgmma0[1][i] = pgmma0[1][i + 1]; + pgmma0[2][i] = pgmma0[2][i + 1]; + pgmma0[3][i] = pgmma0[3][i + 1]; + } + pgmma0[0][6] = trate; + pgmma0[1][6] = tlowa; + pgmma0[2][6] = thgha; + pgmma0[3][6] = tmrat; + } else + for (i = 0; i < 7; i++) { + pgmma0[0][i] = trate; + pgmma0[1][i] = tlowa; + pgmma0[2][i] = thgha; + pgmma0[3][i] = tmrat; + } + *gmma_rate = trate; + *low_alpha = tlowa; + *hgh_alpha = thgha; + *mtdbld_rate = tmrat; +} + +/* black bord detection, and histogram clipping */ +static void dnlp_refine_bin0(int hstSum) +{ + static unsigned int tmp_sum[7]; + unsigned int nTmp = 0; + unsigned int nTmp0 = 0; + unsigned int nsum = 0; + int j = 0; + + nTmp = (hstSum * ve_dnlp_bin0_absmax + 128) >> 8; + nTmp0 = pre_0_gamma[1] + pre_0_gamma[2]; + if (nTmp0 > nTmp) + nTmp = nTmp0; + + if (pre_0_gamma[0] > nTmp) { + if (pre_0_gamma[1] > nTmp) + nTmp = pre_0_gamma[1]; + if (pre_0_gamma[2] > nTmp) + nTmp = pre_0_gamma[2]; + + nsum = pre_0_gamma[0] - nTmp; + + nTmp = (hstSum * ve_dnlp_bin0_sbtmax + 128) >> 8; + if (nsum > nTmp) + nsum = nTmp; + } + + if (!dnlp_scn_chg) { + for (j = 0; j < 7; j++) + nsum += tmp_sum[j]; + nsum = ((nsum + 4) >> 3); + + for (j = 0; j < 6; j++) + tmp_sum[j] = tmp_sum[j + 1]; + tmp_sum[6] = nsum; + } else { + for (j = 0; j < 7; j++) + tmp_sum[j] = nsum; + } + + if (dnlp_printk & 0x1) + pr_info("Bin0 Refine: -%4d\n", nsum); + + if (nsum >= pre_0_gamma[0]) + pre_0_gamma[0] = 0; + else + pre_0_gamma[0] = pre_0_gamma[0] - nsum; +} + +static void dnlp_adp_alpharate(unsigned int *lmh_avg, + unsigned int *low_alpha, unsigned int *hgh_alpha, + unsigned int *pst_gmarat, + unsigned int dnlp_lowrange, unsigned int dnlp_hghrange) +{ + int nTmp = 0; + int ndif = 0; + int nlap = 0; + int nbrt0 = 0; + int nbrt1 = 0; + + if ((dnlp_lowrange + lmh_avg[3]) < 64) { /* decrease low alpha */ + nTmp = 64 - (dnlp_lowrange + lmh_avg[3]); + nTmp = (ve_dnlp_adpalpha_lrate * nTmp + 16) >> 5; + if (*low_alpha < nTmp) + *low_alpha = 0; + else + *low_alpha = *low_alpha - nTmp; + + if (dnlp_printk) + pr_info("low alpha-- (%3d) -> %2d\n", nTmp, *low_alpha); + } else if (lmh_avg[3] > 64) { /* increase low alpha */ + ndif = lmh_avg[3] - 64; + nlap = (ve_dnlp_adpalpha_lrate * ndif + 16) >> 5; + if ((nlap + *low_alpha) > 64) + *low_alpha = 64; + else + *low_alpha += nlap; + + if (lmh_avg[4] < 16) { + nbrt0 = ve_dnlp_pstgma_brghtrat1 * (16 - lmh_avg[4]); + nbrt0 = (nbrt0 + 8) >> 4; + } + nbrt1 = (ve_dnlp_pstgma_brghtrate * ndif + 16) >> 6; + + nTmp = nbrt0 + nbrt1; + + if ((*pst_gmarat + nTmp) > 64) + *pst_gmarat = 64; + else + *pst_gmarat += nTmp; + + if (dnlp_printk) + pr_info("low alpha++ (%3d) -> %2d pstgma(+%2d +%2d)(%2d)\n", + nlap, *low_alpha, nbrt0, nbrt1, *pst_gmarat); + } + + if (lmh_avg[2] < 64 - dnlp_hghrange) { /* decrease hgh alpha */ + nTmp = 64 - dnlp_hghrange - lmh_avg[2]; + nTmp = (ve_dnlp_adpalpha_hrate * nTmp + 16) >> 5; + if (*hgh_alpha < nTmp) + *hgh_alpha = 0; + else + *hgh_alpha = *hgh_alpha - nTmp; + if (dnlp_printk) + pr_info("hgh alpha-- (%3d) -> %2d\n", nTmp, *hgh_alpha); + } else if (lmh_avg[2] > 63) { /* increase hgh alpha */ + nTmp = lmh_avg[2] - 63; + nTmp = (ve_dnlp_adpalpha_hrate * nTmp + 16) >> 5; + if ((nTmp + *hgh_alpha) > 64) + *hgh_alpha = 64; + else + *hgh_alpha += nTmp; + + if (dnlp_printk) + pr_info("hgh alpha++ (%3d) -> %2d\n", nTmp, *hgh_alpha); + } + +} + +static int PreTstDat[28]; +static int CrtTstDat[28]; + +static void dnlp_tgt_sort(void) +{ + int i = 0; + int j = 0; + unsigned char t = 0; + int chk = 0; + /* unsigned char ve_dnlp_tgt[64]; */ + for (j = 0; j < 63; j++) { + chk = 0; + for (i = 0; i < (63 - i); i++) { + if (ve_dnlp_tgt[i] > ve_dnlp_tgt[i+1]) { + t = ve_dnlp_tgt[i]; + ve_dnlp_tgt[i] = ve_dnlp_tgt[i+1]; + ve_dnlp_tgt[i+1] = t; + chk = chk+1; + } + } + if (chk == 0) + break; + } +} + +static void ve_dnlp_calculate_tgtx_new(struct vframe_s *vf) +{ + struct vframe_prop_s *p = &vf->prop; + + int hstSum = 0; + + /* Black gamma rate: global -> auto local */ + unsigned int blk_gma_rat[64]; + + static unsigned int nTstCnt; + + int i = 0; + /*static unsigned int sum_b;*/ + unsigned int sum = 0, max = 0; + unsigned int nTmp = 0; + int nT0 = 0, nT1 = 0; + int nTmp0 = 0; + + int dnlp_brightness = 0; + unsigned int mMaxLst[4]; + unsigned int mMaxIdx[4]; + int blk_wht_ext[2] = {0, 0}; + static unsigned int pre_stur; + unsigned int dnlp_auto_rng = 0; + + /*u4[0-8] smooth moving,reflesh the curve,0-refresh one frame*/ + /*u8larger-->near to gamma1.8, smaller->gamma1.2 [0-256]dft60*/ + unsigned int gmma_rate = (unsigned int) ve_dnlp_gmma_rate; + /* u6[0-64]dft20*/ + unsigned int low_alpha = (unsigned int) ve_dnlp_lowalpha_new; + + /* u6[0-64]dft28*/ + unsigned int hgh_alpha = (unsigned int) ve_dnlp_hghalpha_new; + + /*u4s-curve begin band [0-16]dft0*/ + unsigned int sBgnBnd = (unsigned int) ve_dnlp_sbgnbnd; + + /*u4s-curve begin band [0-16]dft5*/ + unsigned int sEndBnd = (unsigned int) ve_dnlp_sendbnd; + + /*u4clash hist begin point [0-16] dft0*/ + unsigned int clashBgn = (unsigned int) ve_dnlp_clashBgn; + + /*u4 clash hist end point [0~15] dft10*/ + unsigned int clashEnd = (unsigned int) ve_dnlp_clashEnd+49; + + /*please add the parameters*/ + /*u6method blending rate (0~64) dft32*/ + unsigned int mtdbld_rate = (unsigned int) ve_mtdbld_rate; + + /*u6 dft32*/ + unsigned int dnlp_pst_gmarat = (unsigned int) ve_dnlp_pst_gmarat; + + unsigned int dnlp_lowrange = (unsigned int) ve_dnlp_lowrange; + unsigned int dnlp_hghrange = (unsigned int) ve_dnlp_hghrange; + unsigned int dnlp_bkgert = (unsigned int) ve_dnlp_bkgert; + + /*-------------------------------------------------*/ + unsigned int lsft_avg = 0; /*luma shift average */ + unsigned int luma_avg = 0; + unsigned int luma_avg4 = 0; + unsigned int low_lavg4 = 0; /*low luma average*/ + unsigned int lmh_avg[5] = {0, 0, 0, 0, 0}; + /* low/mid/hgh tone average */ + + unsigned int ihstBgn = 0; + unsigned int ihstEnd = 0; + bool prt_flg = 0; + + unsigned int rGm1p2[] = {0, 2, 4, 7, 9, 12, 15, + 18, 21, 24, 28, 31, 34, + 38, 41, 45, 49, 52, 56, + 60, 63, 67, 71, 75, 79, + 83, 87, 91, 95, 99, 103, + 107, 111, 116, 120, 124, + 128, 133, 137, 141, 146, + 150, 154, 159, 163, 168, + 172, 177, 181, 186, 190, + 195, 200, 204, 209, 213, + 218, 223, 227, 232, 237, + 242, 246, 251, 255}; + + /* 2.0 for full range */ + unsigned int rGm1p8[] = {0, 0, 0, 1, 1, 2, 2, 3, + 4, 5, 6, 8, 9, 11, 12, 14, + 16, 18, 20, 23, 25, 28, 30, 33, + 36, 39, 42, 46, 49, 53, 56, 60, + 64, 68, 72, 77, 81, 86, 90, 95, + 100, 105, 110, 116, 121, 127, 132, 138, + 144, 150, 156, 163, + 169, 176, 182, 189, + 196, 203, 210, 218, + 225, 233, 240, 248, 255}; + + if (ve_dnlp_mvreflsh < 1) + ve_dnlp_mvreflsh = 1; + + RBASE = (1 << ve_dnlp_mvreflsh); + + /* parameters refresh */ + dnlp3_param_refrsh(); + dnlp_scn_chg = 0; + + if (low_alpha > 64) + low_alpha = 64; + if (hgh_alpha > 64) + hgh_alpha = 64; + if (clashBgn > 16) + clashBgn = 16; + if (clashEnd > 64) + clashEnd = 64; + if (clashEnd < 49) + clashEnd = 49; + + /* old historic luma sum*/ + /*sum_b = ve_dnlp_luma_sum;*/ + /* new historic luma sum*/ + if (hist_sel) + ve_dnlp_luma_sum = p->hist.vpp_luma_sum; + else + ve_dnlp_luma_sum = p->hist.luma_sum; + + /* counter the calling function */ + nTstCnt++; + if (nTstCnt > 240) + nTstCnt = 0; + + nT0 = 0; /* counter the same histogram */ + hstSum = 0; + for (i = 0; i < 64; i++) { + pre_1_gamma[i] = pre_0_gamma[i]; + if (hist_sel) + pre_0_gamma[i] = (unsigned int)p->hist.vpp_gamma[i]; + else + pre_0_gamma[i] = (unsigned int)p->hist.gamma[i]; + + /* counter the same histogram */ + if (pre_1_gamma[i] == pre_0_gamma[i]) + nT0++; + else if (pre_1_gamma[i] > pre_0_gamma[i]) + nT1 = (pre_1_gamma[i] - pre_0_gamma[i]); + else + nT1 = (pre_0_gamma[i] - pre_1_gamma[i]); + + hstSum += pre_0_gamma[i]; + } + + if (dnlp_printk) + pr_info("\nRflsh%03d: %02d same bins hstSum(%d)\n", + nTstCnt, nT0, hstSum); + + if (!ve_dnlp_luma_sum) { + /*new luma sum is 0,something is wrong,freeze dnlp curve*/ + dnlp_scn_chg = 1; + return; + } + + for (i = 0; i < 28; i++) + PreTstDat[i] = CrtTstDat[i]; + + dnlp_bld_lvl = curve_rfrsh_chk(hstSum, RBASE); + CrtTstDat[0] = dnlp_bld_lvl; + + if (ve_dnlp_respond_flag) { + dnlp_bld_lvl = RBASE; + dnlp_scn_chg = 1; + } else if (dnlp_bld_lvl >= RBASE) { + dnlp_bld_lvl = RBASE; + dnlp_scn_chg = 1; + } + + CrtTstDat[1] = dnlp_bld_lvl; + + /* black bord detection, and histogram clipping */ + dnlp_refine_bin0(hstSum); + + /* histogram and luma_sum filters */ + dnlp_inhist_lpf(); + + hstSum = 0; + for (i = 0; i < 64; i++) { + if (pre_0_gamma[i] != 0) { + if (ihstBgn == 0 && pre_0_gamma[0] == 0) + ihstBgn = i; + if (ihstEnd != 64) + ihstEnd = i+1; + } + clash_curve[i] = (i<<4); /* 0~1024 */ + + hstSum += pre_0_gamma[i]; + } + clash_curve[64] = 1024; + + if (ve_dnlp_limit_rng) { + iRgnBgn = 4; /* i=ihstBgn, i= 59) + iRgnEnd = ihstEnd; + } + CrtTstDat[8] = iRgnBgn; + CrtTstDat[9] = iRgnEnd; + + /* all the same */ + if (nT0 == 64 && ve_dnlp_smhist_ck && (!ve_dnlp_respond_flag)) + return; + + sum = 0; + max = 0; + luma_avg = 0; + + /*Get the maximum4*/ + mMaxLst[0] = 0; + mMaxLst[1] = 0; + mMaxLst[2] = 0; + mMaxLst[3] = 0; + mMaxIdx[0] = 0; + mMaxIdx[1] = 0; + mMaxIdx[2] = 0; + mMaxIdx[3] = 0; + nT0 = 0; + for (i = iRgnBgn; i < iRgnEnd; i++) { + nTmp = pre_0_gamma[i]; + + sum += nTmp; + + if (max < nTmp) + max = nTmp; + + /*lower extension [0-63]*/ + nTmp0 = nTmp*i; + luma_avg += nTmp0; + + if (i == 31) + low_lavg4 = luma_avg; /*low luma average*/ + + /*Get the maximum4*/ + for (nT0 = 0; nT0 < 4; nT0++) { + if (nTmp >= mMaxLst[nT0]) { + for (nT1 = 3; nT1 >= nT0+1; nT1--) { + mMaxLst[nT1] = mMaxLst[nT1-1]; + mMaxIdx[nT1] = mMaxIdx[nT1-1]; + } + + mMaxLst[nT0] = nTmp; + mMaxIdx[nT0] = i; + break; + } + } + } + + if (dnlp_printk & 0x1) { + pr_info("#Bins: Pre-hist => Crt-Hist\n"); + for (i = 0; i < 64; i++) + pr_info("[%03d,%03d): %05d => %05d\n", + 4*i, 4*(i+1), pre_1_gamma[i], + pre_0_gamma[i]); + /* new historic luma sum*/ + pr_info("luma s=%x, hist-sum=%d max=%d\n", + ve_dnlp_luma_sum, sum, max); + } + + /*invalid histgram: freeze dnlp curve*/ + if ((max <= 55 || sum == 0) && (!ve_dnlp_respond_flag)) + return; + + lsft_avg = (luma_avg << (2 + ve_dnlp_pavg_btsft)); + lsft_avg = (lsft_avg + (sum >> 1)) / sum; + luma_avg4 = (lsft_avg >> ve_dnlp_pavg_btsft); + luma_avg = (luma_avg4>>2); + + if (mMaxIdx[0] == 0) + nTmp = (mMaxIdx[1] * 2) + mMaxIdx[2] + mMaxIdx[3]; + else { + if (mMaxIdx[1] == 0) + nTmp = mMaxIdx[0] + mMaxIdx[2] + mMaxIdx[3]; + else if (mMaxIdx[2] == 0) + nTmp = mMaxIdx[0] + mMaxIdx[1] + mMaxIdx[3]; + else if (mMaxIdx[3] == 0) + nTmp = mMaxIdx[0] + mMaxIdx[1] + mMaxIdx[2]; + else + nTmp = mMaxIdx[1] + mMaxIdx[2] + mMaxIdx[3]; + + nTmp += mMaxIdx[0]; + } + lmh_avg[4] = nTmp; + + prt_flg = (dnlp_printk & 0x1); + if (prt_flg) { + pr_info("Max: %04d(%d) > %04d(%d) > %04d(%d) > %04d(%d) => %d\n", + mMaxLst[0], mMaxIdx[0], mMaxLst[1], mMaxIdx[1], + mMaxLst[2], mMaxIdx[2], mMaxLst[3], mMaxIdx[3], nTmp); + pr_info("%d => %d (%d)\n", luma_avg, lsft_avg, luma_avg4); + } + + CrtTstDat[10] = lsft_avg; + CrtTstDat[11] = luma_avg4; + + low_lavg4 = 4*low_lavg4/sum; + if (dnlp_printk) + pr_info("[avg1]= (%02d %02d) (%4d) (%3d, %3d)\n", + luma_avg, luma_avg4, lsft_avg, + gmma_rate, low_alpha); + + dnlp_brightness = cal_brght_plus(luma_avg4, low_lavg4); + + CrtTstDat[12] = low_lavg4; + CrtTstDat[14] = dnlp_brightness; + + /*150918 for 32-step luma pattern*/ + if (ve_dnlp_dbg_adjavg) + luma_avg4 = AdjHistAvg(luma_avg4, ihstEnd); + + luma_avg4 = cal_hist_avg(luma_avg4); + luma_avg = (luma_avg4>>2); + + if (luma_avg < ve_dnlp_auto_rng) + dnlp_auto_rng = luma_avg; + else if ((luma_avg + ve_dnlp_auto_rng) > 64) + dnlp_auto_rng = 64 - luma_avg; + else + dnlp_auto_rng = ve_dnlp_auto_rng; + + if (dnlp_auto_rng < 2) + dnlp_auto_rng = 2; + else if (dnlp_auto_rng > 10) + dnlp_auto_rng = 10; + + if (ve_dnlp_auto_rng > 0) { + if (luma_avg <= dnlp_auto_rng + 2) { + dnlp_lowrange = 2; + dnlp_hghrange = 64 - (luma_avg + dnlp_auto_rng); + } else if (luma_avg >= 61 - dnlp_auto_rng) { + dnlp_lowrange = luma_avg - dnlp_auto_rng; + dnlp_hghrange = 2; + } else { + dnlp_lowrange = luma_avg - dnlp_auto_rng; + dnlp_hghrange = (63 - (luma_avg + dnlp_auto_rng)); + } + } else { + dnlp_lowrange = ve_dnlp_lowrange; + dnlp_hghrange = ve_dnlp_hghrange; + } + if (dnlp_lowrange > 31) + dnlp_lowrange = 31; + else if (dnlp_lowrange < 2) + dnlp_lowrange = 2; + if (dnlp_hghrange > 31) + dnlp_hghrange = 31; + else if (dnlp_hghrange < 2) + dnlp_hghrange = 2; + + for (i = iRgnBgn; i < iRgnEnd; i++) { + nTmp0 = pre_0_gamma[i] * i; + + if (i < dnlp_lowrange) {/* low tone */ + lmh_avg[0] += nTmp0; + lmh_avg[3] += pre_0_gamma[i] * (64 - i); + } else if (i > (63 - dnlp_hghrange)) /* hgh tone */ + lmh_avg[2] += nTmp0; + else /* mid tone */ + lmh_avg[1] += nTmp0; + } + + /* low/mid/high tone average */ + lmh_avg[0] = (lmh_avg[0] << 6) / dnlp_lowrange; + lmh_avg[3] = (lmh_avg[3] << 6) / dnlp_lowrange; + lmh_avg[1] = (lmh_avg[1] << 6) / (64 - dnlp_lowrange - dnlp_hghrange); + lmh_avg[2] = (lmh_avg[2] << 6) / dnlp_hghrange; + + lmh_avg[0] = (lmh_avg[0] + (sum >> 1)) / (sum + 1); + lmh_avg[3] = (lmh_avg[3] + (sum >> 1)) / (sum + 1); + lmh_avg[1] = (lmh_avg[1] + (sum >> 1)) / (sum + 1); + lmh_avg[2] = (lmh_avg[2] + (sum >> 1)) / (sum + 1); + /*lmh_avg[3] = 64 - lmh_avg[3];*/ + + /* adaptive method rate */ + if (dnlp_printk) + pr_info("Adp Mtd/PostGm Rate: %d %d gm(%d)", + luma_avg, mtdbld_rate, dnlp_pst_gmarat); + + mtdbld_rate = dnlp_adp_mtdrate(mtdbld_rate, luma_avg); + + /* post gamma rate: global -> auto local */ + if (ve_dnlp_pst_gmarat > 64) + dnlp_pst_gmarat = ve_dnlp_pst_gmarat - 64; + else + dnlp_pst_gmarat = 64 - ve_dnlp_pst_gmarat; + + dnlp_adp_alpharate(lmh_avg, &low_alpha, &hgh_alpha, + &dnlp_pst_gmarat, dnlp_lowrange, dnlp_hghrange); + + if (ve_dnlp_pst_gmarat < 64) /* no adp dnlp_pst_gmarat */ + dnlp_pst_gmarat = 64 - ve_dnlp_pst_gmarat; + + if (dnlp_printk) { + pr_info("mtdbld: %2d (%2d %2d) => %2d (%2d %2d)\n", + ve_mtdbld_rate, ve_dnlp_lowalpha_new, + ve_dnlp_hghalpha_new, + mtdbld_rate, low_alpha, hgh_alpha); + pr_info("avg: l[ 0~%2d]=%2d(%2d) m=%2d h[%2d~63]=%2d\n", + dnlp_lowrange - 1, lmh_avg[0], + 64 - lmh_avg[3], lmh_avg[1], + 64 - dnlp_hghrange, lmh_avg[2]); + } + + CrtTstDat[2] = clashBgn; + CrtTstDat[3] = clashEnd; + clash_fun(clash_curve, pre_0_gamma, clashBgn, clashEnd); /* 0~1024 */ + clash_blend(); + + blk_wht_extsn(blk_wht_ext, pre_0_gamma, hstSum, luma_avg); /* 0~1024 */ + CrtTstDat[4] = blk_wht_ext[0]; + CrtTstDat[5] = blk_wht_ext[1]; + + if (dnlp_printk) + pr_info("BlkWhtExt: (%d %d), bldlvl=%02d\n", + blk_wht_ext[0], blk_wht_ext[1], dnlp_bld_lvl); + + /*patch for black+white stripe*/ + if (mMaxIdx[1] > mMaxIdx[0]) { + nT0 = mMaxIdx[0]; + nT1 = 63 - mMaxIdx[1]; + } else { + nT0 = mMaxIdx[1]; + nT1 = 63 - mMaxIdx[0]; + } + nTmp = (nT0 < nT1) ? nT0 : nT1; + nTmp = (nTmp > 16) ? 16 : nTmp; + + if ((mMaxLst[1] > (ve_dnlp_lgst_bin*sum>>8)) && + ((mMaxIdx[1] > (mMaxIdx[0] + ve_dnlp_lgst_dst)) || + (mMaxIdx[0] > (mMaxIdx[1] + ve_dnlp_lgst_dst)))) { + gmma_rate += (nTmp*(255 - gmma_rate)>>4); + low_alpha -= (low_alpha*nTmp>>4); + hgh_alpha -= (hgh_alpha*nTmp>>4); + mtdbld_rate += (nTmp*(64 - mtdbld_rate)>>4); + + if (dnlp_printk) + pr_info("special case: %d %d %d %d\n", + gmma_rate, low_alpha, hgh_alpha, mtdbld_rate); + } + /* print the parameters */ + + lsft_avg = cal_hst_shft_avg(lsft_avg); + dnlp_params_hist(&gmma_rate, &low_alpha, &hgh_alpha, + &mtdbld_rate, luma_avg, luma_avg4); + + if (dnlp_printk & 0x1) + pr_info("[avg2]= (%3d %3d) (%3d %3d) (%3d %3d)\n", + luma_avg, luma_avg4, gmma_rate, mtdbld_rate, + low_alpha, hgh_alpha); + + CrtTstDat[15] = luma_avg4; + CrtTstDat[16] = luma_avg; + CrtTstDat[17] = lsft_avg; + CrtTstDat[18] = gmma_rate; + CrtTstDat[19] = low_alpha; + + prt_flg = (dnlp_printk & 0x1); + if (prt_flg) { + pr_info("Rflsh-check: %03u\n", nTstCnt); + pr_info("BldLvl= %02d\n", dnlp_bld_lvl); + } + + if (dnlp_bkgert > dnlp_pst_gmarat) + dnlp_bkgert = dnlp_pst_gmarat; + + for (i = 0; i < 64; i++) { + nT1 = dnlp_pst_gmarat; + + if (i > ve_dnlp_bkgend) + nT1 = dnlp_bkgert; + else if (ve_dnlp_bkgend > 0) { + nT1 = dnlp_pst_gmarat - dnlp_bkgert; + nT1 = nT1 * i + (ve_dnlp_bkgend >> 1); + nT1 = nT1 / ve_dnlp_bkgend; + nT1 = dnlp_pst_gmarat - nT1; + } + + if (ve_dnlp_limit_rng && (i <= 4)) { + nT1 = i * dnlp_pst_gmarat; + nT1 = ((nT1 + 2) >> 2); + } + + if (nT1 < 0) + nT1 = 0; + else if (nT1 > 64) + nT1 = 64; + + blk_gma_rat[i] = nT1; + } + + /* 0~1024 */ + if (dnlp_printk & 0x1) + pr_info("[avg3]= %02d %02d => %4d\n", + luma_avg, luma_avg4, lsft_avg); + + if (ve_dnlp_scv_dbg != 0) { + nTmp0 = lsft_avg + 16 * ve_dnlp_scv_dbg; + if (nTmp0 < 0) + lsft_avg = 0; + else + lsft_avg = nTmp0; + } + GetGmCurves(gma_scurve0, rGm1p2, lsft_avg, sBgnBnd, sEndBnd); + GetGmCurves(gma_scurve1, rGm1p8, lsft_avg, sBgnBnd, sEndBnd); + GetGmBlkCvs(blk_gma_crv, rGm1p8, sBgnBnd, iRgnEnd); + + CrtTstDat[20] = sBgnBnd; + CrtTstDat[21] = sEndBnd; + CrtTstDat[22] = lsft_avg; + CrtTstDat[23] = iRgnEnd; + + prt_flg = (dnlp_printk & 0x1); + if (prt_flg) { + pr_info("paramets: %d %d %d %d %d\n", + luma_avg, gmma_rate, low_alpha, hgh_alpha, mtdbld_rate); + } + + /*=========================================================*/ + if (dnlp_printk & 0x1) { + pr_info("dnlp blend curve:\n"); + pr_info("[luma_sum] = %d\n", ve_dnlp_luma_sum); + } + + dnlp_gmma_cuvs(gmma_rate, low_alpha, hgh_alpha, lsft_avg); + CrtTstDat[24] = gmma_rate; + CrtTstDat[25] = low_alpha; + CrtTstDat[26] = hgh_alpha; + CrtTstDat[27] = lsft_avg; + + for (i = 0; i < 64; i++) { + pcurves[0][i] = gma_scurve0[i]; /* gamma0 s-curve */ + pcurves[1][i] = gma_scurve1[i]; /* gamma1 s-curve */ + pcurves[2][i] = gma_scurvet[i]; /* gmma0+gamm1 s-curve */ + pcurves[3][i] = clash_curve[i]; /* clash curve */ + pcurves[4][i] = clsh_scvbld[i]; /* clash + s-curve blend */ + pcurves[5][i] = blk_gma_crv[i]; /* black gamma curve */ + pcurves[6][i] = blk_gma_bld[i]; /* blending with black gamma */ + pcurves[7][i] = blkwht_ebld[i]; /* black white extension */ + } + + /* clsh_scvbld = clash_curve + gma_scurvet */ + dnlp_clsh_sbld(mtdbld_rate); /* clash + s-curve */ + + /* blk_gma_bld = blk_gma_crv + clsh_scvbld */ + dnlp_blkgma_bld(blk_gma_rat); + + /* blkwht_ebld = blk_gma_bld + extension */ + blk_wht_ext[0] += (ve_dnlp_set_bext << 4); + blk_wht_ext[1] += (ve_dnlp_set_wext << 4); + dnlp_blkwht_bld(blk_wht_ext, dnlp_brightness, + luma_avg4, luma_avg, iRgnBgn, iRgnEnd); + + if (prt_flg) { + pr_info("blk/wht ext: [%d %d] + %d\n", + blk_wht_ext[0], blk_wht_ext[1], + dnlp_brightness); + } + + prt_flg = ((dnlp_printk >> 2) & 0x1); + for (i = 0; i < 64; i++) { + premap0[i] = ve_dnlp_tgt[i]; + + if (ve_dnlp_dbg_map == 1) + nTmp0 = gma_scurve0[i]; + else if (ve_dnlp_dbg_map == 2) + nTmp0 = gma_scurve1[i]; + else if (ve_dnlp_dbg_map == 3) + nTmp0 = gma_scurvet[i]; + else if (ve_dnlp_dbg_map == 4) + nTmp0 = clash_curve[i]; + else if (ve_dnlp_dbg_map == 5) + nTmp0 = clsh_scvbld[i]; + else if (ve_dnlp_dbg_map == 6) + nTmp0 = blk_gma_crv[i]; + else if (ve_dnlp_dbg_map == 7) + nTmp0 = blk_gma_bld[i]; + else if (ve_dnlp_dbg_map == 8) + nTmp0 = blkwht_ebld[i]; /* 1023 */ + else + nTmp0 = blkwht_ebld[i]; + + nTmp0 = dnlp_bld_lvl * nTmp0 + (RBASE >> 1); /* 1024 */ + nTmp0 = nTmp0 + (RBASE - dnlp_bld_lvl) * pst_0_gamma[i]; + nTmp0 = (nTmp0 >> ve_dnlp_mvreflsh); /* 0~4096 */ + + if (nTmp0 < 0) + nTmp0 = 0; + else if (nTmp0 > 1023) + nTmp0 = 1023; + + pst_0_gamma[i] = nTmp0; + + nTmp0 = ((nTmp0 + 2) >> 2); + + if (nTmp0 > 255) + nTmp0 = 255; + else if (nTmp0 < 0) + nTmp0 = 0; + + if (prt_flg) + pr_info("[%02d]: (%4d %4d)%4d c%4d cs%4d gm%4d-%4d %4d => %3d\n", + i, gma_scurve0[i], gma_scurve1[i], + gma_scurvet[i], clash_curve[i], + clsh_scvbld[i], blk_gma_crv[i], + blk_gma_bld[i], blkwht_ebld[i], + nTmp0); + + ve_dnlp_tgt[i] = nTmp0; + } + + /* 0~255 sort */ + dnlp_tgt_sort(); + + prt_flg = ((dnlp_printk >> 3) & 0x1); + if (prt_flg) { + for (i = 0; i < 64; i++) { + nT0 = ve_dnlp_tgt[i] - 4*i; + pr_info("%02d: %03d=>%03d (%3d)\n", + i, 4*i, ve_dnlp_tgt[i], nT0); + } + pr_info("\n"); + } + + nT0 = 0; + nT1 = 0; + for (i = 1; i < 64; i++) { + if (ve_dnlp_tgt[i] > 4*i) { + nT0 += (ve_dnlp_tgt[i] - 4*i) * (65 - i); + nT1 += (65 - i); + } + } + nTmp0 = nT0 * ve_dnlp_satur_rat + (nT1 >> 1); + nTmp0 = nTmp0 / (nT1 + 1); + nTmp0 = ((nTmp0 + 4) >> 3); + + nTmp = (ve_dnlp_satur_max << 3); + if (nTmp0 < nTmp) + nTmp = nTmp0; + + if (dnlp_printk) + pr_info("#Statu: pre(%3d) => %5d / %3d => %3d cur(%3d)\n", + pre_stur, nT0, nT1, nTmp0, nTmp); + + if (ve_dnlp_set_saturtn == 0) { + if (nTmp != pre_stur) { + ve_dnlp_add_cm(nTmp + 512); + pre_stur = nTmp; + } + } else { + if (pre_stur != ve_dnlp_set_saturtn) { + if (ve_dnlp_set_saturtn < 512) + ve_dnlp_add_cm(ve_dnlp_set_saturtn + 512); + else + ve_dnlp_add_cm(ve_dnlp_set_saturtn); + pre_stur = ve_dnlp_set_saturtn; + } + } + + if (dnlp_printk) + pr_info("#Dbg: [%02d < %02d(%03d) < %02d] %03d\n", + iRgnBgn, luma_avg, luma_avg4, + iRgnEnd, dnlp_brightness); + + nT0 = 0; + prt_flg = ((dnlp_printk >> 3) & 0x1); + if (prt_flg) { + for (i = 0; i < 64; i++) + nT0 += ((premap0[i] > ve_dnlp_tgt[i]) ? + (premap0[i] - ve_dnlp_tgt[i]) : + (ve_dnlp_tgt[i] - premap0[i])); + + pr_info("map dif= %d\n", nT0); + + if (nT0 > ve_dnlp_dbg_diflvl) { + pr_info("#mrate=%02d brt=%02d\n", + mtdbld_rate, dnlp_brightness); + for (i = 0; i < 64; i++) + if (premap0[i] != ve_dnlp_tgt[i]) + pr_info("[%02d]%5d=>%5d:(%4d=>%4d)\n", + i, + pre_1_gamma[i], pre_0_gamma[i], + premap0[i], ve_dnlp_tgt[i]); + + for (i = 0; i < 28; i++) + if (PreTstDat[i] != CrtTstDat[i]) + pr_info("[%02d] %5d=>%5d\n", + i, PreTstDat[i], CrtTstDat[i]); + pr_info("\n"); + + if (ve_dnlp_ponce >= 2) + ve_dnlp_ponce--; + else + ve_dnlp_ponce = 1; + } + } + + prt_flg = ((dnlp_printk >> 8) & 0x1); + if (ve_dnlp_dbg_map && prt_flg) + for (i = 0; i < 64; i++) + pr_info("[%02d] %5d=>%5d\n", + i, pre_0_gamma[i], ve_dnlp_tgt[i]); + + /* print debug log once */ + if (ve_dnlp_ponce == 1 && dnlp_printk) + dnlp_printk = 0; +} + +static void ve_dnlp_calculate_tgt(struct vframe_s *vf) +{ + struct vframe_prop_s *p = &vf->prop; + ulong data[5]; + static unsigned int sum_b = 0, sum_c; + ulong i = 0, j = 0, ave = 0, max = 0, div = 0; + unsigned int cnt = assist_cnt;/* READ_VPP_REG(ASSIST_SPARE8_REG1); */ + /* old historic luma sum */ + sum_b = sum_c; + sum_c = ve_dnlp_luma_sum; + /* new historic luma sum */ + ve_dnlp_luma_sum = p->hist.luma_sum; + pr_amve_dbg("ve_dnlp_luma_sum=%x,sum_b=%x,sum_c=%x\n", + ve_dnlp_luma_sum, sum_b, sum_c); + /* picture mode: freeze dnlp curve */ + if (dnlp_respond) { + /* new luma sum is 0, something is wrong, freeze dnlp curve */ + if (!ve_dnlp_luma_sum) + return; + } else { + /* new luma sum is 0, something is wrong, freeze dnlp curve */ + if ((!ve_dnlp_luma_sum) || + /* new luma sum is closed to old one (1 +/- 1/64), */ + /* picture mode, freeze curve *//* 5 *//* 5 */ + ((ve_dnlp_luma_sum < + sum_b + (sum_b >> dnlp_adj_level)) && + (ve_dnlp_luma_sum > + sum_b - (sum_b >> dnlp_adj_level)))) + return; + } + /* get 5 regions */ + for (i = 0; i < 5; i++) { + j = 4 + 11 * i; + data[i] = (ulong)p->hist.gamma[j] + + (ulong)p->hist.gamma[j + 1] + + (ulong)p->hist.gamma[j + 2] + + (ulong)p->hist.gamma[j + 3] + + (ulong)p->hist.gamma[j + 4] + + (ulong)p->hist.gamma[j + 5] + + (ulong)p->hist.gamma[j + 6] + + (ulong)p->hist.gamma[j + 7] + + (ulong)p->hist.gamma[j + 8] + + (ulong)p->hist.gamma[j + 9] + + (ulong)p->hist.gamma[j + 10]; + } + /* get max, ave, div */ + for (i = 0; i < 5; i++) { + if (max < data[i]) + max = data[i]; + ave += data[i]; + data[i] *= 5; + } + max *= 5; + div = (max - ave > ave) ? max - ave : ave; + /* invalid histgram: freeze dnlp curve */ + if (!max) + return; + /* get 1st 4 points */ + for (i = 0; i < 4; i++) { + if (data[i] > ave) + data[i] = 64 + (((data[i] - ave) << 1) + div) * + ve_dnlp_rl / (div << 1); + else if (data[i] < ave) + data[i] = 64 - (((ave - data[i]) << 1) + div) * + ve_dnlp_rl / (div << 1); + else + data[i] = 64; + ve_dnlp_tgt[4 + 11 * (i + 1)] = ve_dnlp_tgt[4 + 11 * i] + + ((44 * data[i] + 32) >> 6); + } + /* fill in region 0 with black extension */ + data[0] = ve_dnlp_black; + if (data[0] > 16) + data[0] = 16; + data[0] = + (ve_dnlp_tgt[15] - ve_dnlp_tgt[4]) * (16 - data[0]); + for (j = 1; j <= 6; j++) + ve_dnlp_tgt[4 + j] = + ve_dnlp_tgt[4] + (data[0] * j + 88) / 176; + data[0] = (ve_dnlp_tgt[15] - ve_dnlp_tgt[10]) << 1; + for (j = 1; j <= 4; j++) + ve_dnlp_tgt[10 + j] = + ve_dnlp_tgt[10] + (data[0] * j + 5) / 10; + /* fill in regions 1~3 */ + for (i = 1; i <= 3; i++) { + data[i] = + (ve_dnlp_tgt[11 * i + 15] - ve_dnlp_tgt[11 * i + 4]) << 1; + for (j = 1; j <= 10; j++) + ve_dnlp_tgt[11 * i + 4 + j] = ve_dnlp_tgt[11 * i + 4] + + (data[i] * j + 11) / 22; + } + /* fill in region 4 with white extension */ + data[4] /= 20; + data[4] = (ve_dnlp_white * + ((ave << 4) - data[4] * ve_dnlp_white_factor) + + (ave << 3)) / (ave << 4); + if (data[4] > 16) + data[4] = 16; + data[4] = (ve_dnlp_tgt[59] - ve_dnlp_tgt[48]) * (16 - data[4]); + for (j = 1; j <= 6; j++) + ve_dnlp_tgt[59 - j] = ve_dnlp_tgt[59] - + (data[4] * j + 88) / 176; + data[4] = (ve_dnlp_tgt[53] - ve_dnlp_tgt[48]) << 1; + for (j = 1; j <= 4; j++) + ve_dnlp_tgt[53 - j] = ve_dnlp_tgt[53] - (data[4] * j + 5) / 10; + if (cnt) { + for (i = 0; i < 64; i++) + pr_amve_dbg(" ve_dnlp_tgt[%ld]=%d\n", + i, ve_dnlp_tgt[i]); + /* WRITE_VPP_REG(ASSIST_SPARE8_REG1, 0); */ + assist_cnt = 0; + } +} + /* lpf[0] is always 0 & no need calculation */ +static void ve_dnlp_calculate_lpf(void) +{ + ulong i = 0; + + for (i = 0; i < 64; i++) + ve_dnlp_lpf[i] = ve_dnlp_lpf[i] - + (ve_dnlp_lpf[i] >> ve_dnlp_rt) + ve_dnlp_tgt[i]; +} + +static void ve_dnlp_calculate_reg(void) +{ + ulong i = 0, j = 0, cur = 0, data = 0, + offset = ve_dnlp_rt ? (1 << (ve_dnlp_rt - 1)) : 0; + for (i = 0; i < 16; i++) { + ve_dnlp_reg[i] = 0; + cur = i << 2; + for (j = 0; j < 4; j++) { + data = (ve_dnlp_lpf[cur + j] + offset) >> ve_dnlp_rt; + if (data > 255) + data = 255; + ve_dnlp_reg[i] |= data << (j << 3); + } + } +} + +static void ve_dnlp_load_reg(void) +{ +/* #ifdef NEW_DNLP_IN_SHARPNESS */ + /* if(dnlp_sel == NEW_DNLP_IN_SHARPNESS){ */ + if (is_meson_gxtvbb_cpu() && + (dnlp_sel == NEW_DNLP_IN_SHARPNESS)) { + WRITE_VPP_REG(SRSHARP0_DNLP_00, ve_dnlp_reg[0]); + WRITE_VPP_REG(SRSHARP0_DNLP_01, ve_dnlp_reg[1]); + WRITE_VPP_REG(SRSHARP0_DNLP_02, ve_dnlp_reg[2]); + WRITE_VPP_REG(SRSHARP0_DNLP_03, ve_dnlp_reg[3]); + WRITE_VPP_REG(SRSHARP0_DNLP_04, ve_dnlp_reg[4]); + WRITE_VPP_REG(SRSHARP0_DNLP_05, ve_dnlp_reg[5]); + WRITE_VPP_REG(SRSHARP0_DNLP_06, ve_dnlp_reg[6]); + WRITE_VPP_REG(SRSHARP0_DNLP_07, ve_dnlp_reg[7]); + WRITE_VPP_REG(SRSHARP0_DNLP_08, ve_dnlp_reg[8]); + WRITE_VPP_REG(SRSHARP0_DNLP_09, ve_dnlp_reg[9]); + WRITE_VPP_REG(SRSHARP0_DNLP_10, ve_dnlp_reg[10]); + WRITE_VPP_REG(SRSHARP0_DNLP_11, ve_dnlp_reg[11]); + WRITE_VPP_REG(SRSHARP0_DNLP_12, ve_dnlp_reg[12]); + WRITE_VPP_REG(SRSHARP0_DNLP_13, ve_dnlp_reg[13]); + WRITE_VPP_REG(SRSHARP0_DNLP_14, ve_dnlp_reg[14]); + WRITE_VPP_REG(SRSHARP0_DNLP_15, ve_dnlp_reg[15]); + } else { + /* #endif */ + WRITE_VPP_REG(VPP_DNLP_CTRL_00, ve_dnlp_reg[0]); + WRITE_VPP_REG(VPP_DNLP_CTRL_01, ve_dnlp_reg[1]); + WRITE_VPP_REG(VPP_DNLP_CTRL_02, ve_dnlp_reg[2]); + WRITE_VPP_REG(VPP_DNLP_CTRL_03, ve_dnlp_reg[3]); + WRITE_VPP_REG(VPP_DNLP_CTRL_04, ve_dnlp_reg[4]); + WRITE_VPP_REG(VPP_DNLP_CTRL_05, ve_dnlp_reg[5]); + WRITE_VPP_REG(VPP_DNLP_CTRL_06, ve_dnlp_reg[6]); + WRITE_VPP_REG(VPP_DNLP_CTRL_07, ve_dnlp_reg[7]); + WRITE_VPP_REG(VPP_DNLP_CTRL_08, ve_dnlp_reg[8]); + WRITE_VPP_REG(VPP_DNLP_CTRL_09, ve_dnlp_reg[9]); + WRITE_VPP_REG(VPP_DNLP_CTRL_10, ve_dnlp_reg[10]); + WRITE_VPP_REG(VPP_DNLP_CTRL_11, ve_dnlp_reg[11]); + WRITE_VPP_REG(VPP_DNLP_CTRL_12, ve_dnlp_reg[12]); + WRITE_VPP_REG(VPP_DNLP_CTRL_13, ve_dnlp_reg[13]); + WRITE_VPP_REG(VPP_DNLP_CTRL_14, ve_dnlp_reg[14]); + WRITE_VPP_REG(VPP_DNLP_CTRL_15, ve_dnlp_reg[15]); + } +} + +static void ve_dnlp_load_def_reg(void) +{ + WRITE_VPP_REG(VPP_DNLP_CTRL_00, ve_dnlp_reg_def[0]); + WRITE_VPP_REG(VPP_DNLP_CTRL_01, ve_dnlp_reg_def[1]); + WRITE_VPP_REG(VPP_DNLP_CTRL_02, ve_dnlp_reg_def[2]); + WRITE_VPP_REG(VPP_DNLP_CTRL_03, ve_dnlp_reg_def[3]); + WRITE_VPP_REG(VPP_DNLP_CTRL_04, ve_dnlp_reg_def[4]); + WRITE_VPP_REG(VPP_DNLP_CTRL_05, ve_dnlp_reg_def[5]); + WRITE_VPP_REG(VPP_DNLP_CTRL_06, ve_dnlp_reg_def[6]); + WRITE_VPP_REG(VPP_DNLP_CTRL_07, ve_dnlp_reg_def[7]); + WRITE_VPP_REG(VPP_DNLP_CTRL_08, ve_dnlp_reg_def[8]); + WRITE_VPP_REG(VPP_DNLP_CTRL_09, ve_dnlp_reg_def[9]); + WRITE_VPP_REG(VPP_DNLP_CTRL_10, ve_dnlp_reg_def[10]); + WRITE_VPP_REG(VPP_DNLP_CTRL_11, ve_dnlp_reg_def[11]); + WRITE_VPP_REG(VPP_DNLP_CTRL_12, ve_dnlp_reg_def[12]); + WRITE_VPP_REG(VPP_DNLP_CTRL_13, ve_dnlp_reg_def[13]); + WRITE_VPP_REG(VPP_DNLP_CTRL_14, ve_dnlp_reg_def[14]); + WRITE_VPP_REG(VPP_DNLP_CTRL_15, ve_dnlp_reg_def[15]); +} + +void ve_on_vs(struct vframe_s *vf) +{ + + if (dnlp_en_2 || ve_en) { + /* calculate dnlp target data */ + if (ve_dnlp_method == 0) + ve_dnlp_calculate_tgt(vf); + else if (ve_dnlp_method == 1) + ve_dnlp_calculate_tgtx(vf); + else if (ve_dnlp_method == 2) + ve_dnlp_calculate_tgt_ext(vf); + else if (ve_dnlp_method == 3) + ve_dnlp_calculate_tgtx_new(vf); + else + ve_dnlp_calculate_tgt(vf); + /* calculate dnlp low-pass-filter data */ + ve_dnlp_calculate_lpf(); + /* calculate dnlp reg data */ + ve_dnlp_calculate_reg(); + /* load dnlp reg data */ + ve_dnlp_load_reg(); + } + ve_hist_gamma_tgt(vf); + + /* sharpness process */ + sharpness_process(vf); + + /* */ +#if 0 + /* comment for duration algorithm is not based on panel vsync */ + if (vf->prop.meas.vs_cycle && !frame_lock_nosm) { + if ((vecm_latch_flag & FLAG_LVDS_FREQ_SW1) && + (vf->duration >= 1920 - 19) && (vf->duration <= 1920 + 19)) + vpp_phase_lock_on_vs(vf->prop.meas.vs_cycle, + vf->prop.meas.vs_stamp, + true, + lock_range_50hz_fast, + lock_range_50hz_slow); + if ((!(vecm_latch_flag & FLAG_LVDS_FREQ_SW1)) && + (vf->duration >= 1600 - 5) && (vf->duration <= 1600 + 13)) + vpp_phase_lock_on_vs(vf->prop.meas.vs_cycle, + vf->prop.meas.vs_stamp, + false, + lock_range_60hz_fast, + lock_range_60hz_slow); + } +#endif +} + +/* *********************************************************************** */ +/* *** IOCTL-oriented functions ****************************************** */ +/* *********************************************************************** */ + +void vpp_enable_lcd_gamma_table(void) +{ + WRITE_VPP_REG_BITS(L_GAMMA_CNTL_PORT, 1, GAMMA_EN, 1); +} + +void vpp_disable_lcd_gamma_table(void) +{ + WRITE_VPP_REG_BITS(L_GAMMA_CNTL_PORT, 0, GAMMA_EN, 1); +} + +void vpp_set_lcd_gamma_table(u16 *data, u32 rgb_mask) +{ + int i; + int cnt = 0; + unsigned long flags = 0; + + spin_lock_irqsave(&vpp_lcd_gamma_lock, flags); + + WRITE_VPP_REG_BITS(L_GAMMA_CNTL_PORT, + 0, GAMMA_EN, 1); + + while (!(READ_VPP_REG(L_GAMMA_CNTL_PORT) & (0x1 << ADR_RDY))) { + udelay(10); + if (cnt++ > GAMMA_RETRY) + break; + } + cnt = 0; + WRITE_VPP_REG(L_GAMMA_ADDR_PORT, (0x1 << H_AUTO_INC) | + (0x1 << rgb_mask) | + (0x0 << HADR)); + for (i = 0; i < 256; i++) { + while (!(READ_VPP_REG(L_GAMMA_CNTL_PORT) & (0x1 << WR_RDY))) { + udelay(10); + if (cnt++ > GAMMA_RETRY) + break; + } + cnt = 0; + WRITE_VPP_REG(L_GAMMA_DATA_PORT, data[i]); + } + while (!(READ_VPP_REG(L_GAMMA_CNTL_PORT) & (0x1 << ADR_RDY))) { + udelay(10); + if (cnt++ > GAMMA_RETRY) + break; + } + WRITE_VPP_REG(L_GAMMA_ADDR_PORT, (0x1 << H_AUTO_INC) | + (0x1 << rgb_mask) | + (0x23 << HADR)); + + WRITE_VPP_REG_BITS(L_GAMMA_CNTL_PORT, + gamma_en, GAMMA_EN, 1); + + spin_unlock_irqrestore(&vpp_lcd_gamma_lock, flags); +} + +void init_write_gamma_table(u16 *data, u32 rgb_mask) +{ + int i; + int cnt = 0; + unsigned long flags = 0; + + spin_lock_irqsave(&vpp_lcd_gamma_lock, flags); + + while (!(READ_VPP_REG(L_GAMMA_CNTL_PORT) & (0x1 << ADR_RDY))) { + udelay(10); + if (cnt++ > GAMMA_RETRY) + break; + } + cnt = 0; + WRITE_VPP_REG(L_GAMMA_ADDR_PORT, (0x1 << H_AUTO_INC) | + (0x1 << rgb_mask) | + (0x0 << HADR)); + for (i = 0; i < 256; i++) { + while (!(READ_VPP_REG(L_GAMMA_CNTL_PORT) & (0x1 << WR_RDY))) { + udelay(10); + if (cnt++ > GAMMA_RETRY) + break; + } + cnt = 0; + WRITE_VPP_REG(L_GAMMA_DATA_PORT, data[i]); + } + while (!(READ_VPP_REG(L_GAMMA_CNTL_PORT) & (0x1 << ADR_RDY))) { + udelay(10); + if (cnt++ > GAMMA_RETRY) + break; + } + WRITE_VPP_REG(L_GAMMA_ADDR_PORT, (0x1 << H_AUTO_INC) | + (0x1 << rgb_mask) | + (0x23 << HADR)); + + spin_unlock_irqrestore(&vpp_lcd_gamma_lock, flags); +} + +#define COEFF_NORM(a) ((int)((((a) * 2048.0) + 1) / 2)) +#define MATRIX_5x3_COEF_SIZE 24 + +static int RGB709_to_YUV709l_coeff[MATRIX_5x3_COEF_SIZE] = { + 0, 0, 0, /* pre offset */ + COEFF_NORM(0.181873), COEFF_NORM(0.611831), COEFF_NORM(0.061765), + COEFF_NORM(-0.100251), COEFF_NORM(-0.337249), COEFF_NORM(0.437500), + COEFF_NORM(0.437500), COEFF_NORM(-0.397384), COEFF_NORM(-0.040116), + 0, 0, 0, /* 10'/11'/12' */ + 0, 0, 0, /* 20'/21'/22' */ + 64, 512, 512, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +static int bypass_coeff[MATRIX_5x3_COEF_SIZE] = { + 0, 0, 0, /* pre offset */ + COEFF_NORM(1.0), COEFF_NORM(0.0), COEFF_NORM(0.0), + COEFF_NORM(0.0), COEFF_NORM(1.0), COEFF_NORM(0.0), + COEFF_NORM(0.0), COEFF_NORM(0.0), COEFF_NORM(1.0), + 0, 0, 0, /* 10'/11'/12' */ + 0, 0, 0, /* 20'/21'/22' */ + 0, 0, 0, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; + +void vpp_set_rgb_ogo(struct tcon_rgb_ogo_s *p) +{ + int m[24]; + int i; + /* write to registers */ + if (video_rgb_ogo_xvy_mtx) { + if (video_rgb_ogo_xvy_mtx_latch & MTX_BYPASS_RGB_OGO) { + memcpy(m, bypass_coeff, sizeof(int) * 24); + video_rgb_ogo_xvy_mtx_latch &= ~MTX_BYPASS_RGB_OGO; + } else if (video_rgb_ogo_xvy_mtx_latch & MTX_RGB2YUVL_RGB_OGO) { + memcpy(m, RGB709_to_YUV709l_coeff, sizeof(int) * 24); + video_rgb_ogo_xvy_mtx_latch &= ~MTX_RGB2YUVL_RGB_OGO; + } else + memcpy(m, bypass_coeff, sizeof(int) * 24); + + m[3] = p->r_gain * m[3] / COEFF_NORM(1.0); + m[4] = p->r_gain * m[4] / COEFF_NORM(1.0); + m[5] = p->r_gain * m[5] / COEFF_NORM(1.0); + m[6] = p->g_gain * m[6] / COEFF_NORM(1.0); + m[7] = p->g_gain * m[7] / COEFF_NORM(1.0); + m[8] = p->g_gain * m[8] / COEFF_NORM(1.0); + m[9] = p->b_gain * m[9] / COEFF_NORM(1.0); + m[10] = p->b_gain * m[10] / COEFF_NORM(1.0); + m[11] = p->b_gain * m[11] / COEFF_NORM(1.0); + + m[18] = (p->r_pre_offset + m[18] + 1024) + * p->r_gain / COEFF_NORM(1.0) + - p->r_gain + p->r_post_offset; + m[19] = (p->g_pre_offset + m[19] + 1024) + * p->g_gain / COEFF_NORM(1.0) + - p->g_gain + p->g_post_offset; + m[20] = (p->b_pre_offset + m[20] + 1024) + * p->b_gain / COEFF_NORM(1.0) + - p->b_gain + p->b_post_offset; + + for (i = 18; i < 21; i++) { + if (m[i] > 1023) + m[i] = 1023; + if (m[i] < -1024) + m[i] = -1024; + } + + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, p->en, 6, 1); + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 3, 8, 2); + + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, + ((m[0] & 0xfff) << 16) + | (m[1] & 0xfff)); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, + m[2] & 0xfff); + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, + ((m[3] & 0x1fff) << 16) + | (m[4] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, + ((m[5] & 0x1fff) << 16) + | (m[6] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, + ((m[7] & 0x1fff) << 16) + | (m[8] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, + ((m[9] & 0x1fff) << 16) + | (m[10] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF22, + m[11] & 0x1fff); + if (m[21]) { + WRITE_VPP_REG(VPP_MATRIX_COEF13_14, + ((m[12] & 0x1fff) << 16) + | (m[13] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF15_25, + ((m[14] & 0x1fff) << 16) + | (m[17] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF23_24, + ((m[15] & 0x1fff) << 16) + | (m[16] & 0x1fff)); + } + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, + ((m[18] & 0xfff) << 16) + | (m[19] & 0xfff)); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, + m[20] & 0xfff); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, + m[21], 3, 2); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, + m[22], 5, 3); + } else { + WRITE_VPP_REG(VPP_GAINOFF_CTRL0, + ((p->en << 31) & 0x80000000) | + ((p->r_gain << 16) & 0x07ff0000) | + ((p->g_gain << 0) & 0x000007ff)); + WRITE_VPP_REG(VPP_GAINOFF_CTRL1, + ((p->b_gain << 16) & 0x07ff0000) | + ((p->r_post_offset << 0) & 0x000007ff)); + WRITE_VPP_REG(VPP_GAINOFF_CTRL2, + ((p->g_post_offset << 16) & 0x07ff0000) | + ((p->b_post_offset << 0) & 0x000007ff)); + WRITE_VPP_REG(VPP_GAINOFF_CTRL3, + ((p->r_pre_offset << 16) & 0x07ff0000) | + ((p->g_pre_offset << 0) & 0x000007ff)); + WRITE_VPP_REG(VPP_GAINOFF_CTRL4, + ((p->b_pre_offset << 0) & 0x000007ff)); + } +} + +void ve_enable_dnlp(void) +{ + ve_en = 1; +/* #ifdef NEW_DNLP_IN_SHARPNESS */ +/* if(dnlp_sel == NEW_DNLP_IN_SHARPNESS){ */ + if (is_meson_gxtvbb_cpu() && + (dnlp_sel == NEW_DNLP_IN_SHARPNESS)) + WRITE_VPP_REG_BITS(SRSHARP0_DNLP_EN, 1, 0, 1); + else + /* #endif */ + WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL, + 1, DNLP_EN_BIT, DNLP_EN_WID); +} + +void ve_disable_dnlp(void) +{ + ve_en = 0; +/* #ifdef NEW_DNLP_IN_SHARPNESS */ +/* if(dnlp_sel == NEW_DNLP_IN_SHARPNESS){ */ + if (is_meson_gxtvbb_cpu() && + (dnlp_sel == NEW_DNLP_IN_SHARPNESS)) + WRITE_VPP_REG_BITS(SRSHARP0_DNLP_EN, 0, 0, 1); + else +/* #endif */ +/* { */ + WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL, + 0, DNLP_EN_BIT, DNLP_EN_WID); +/* } */ +} + +void ve_set_dnlp(struct ve_dnlp_s *p) +{ + ulong i = 0; + /* get command parameters */ + ve_en = p->en; + ve_dnlp_white_factor = (p->rt >> 4) & 0xf; + ve_dnlp_rt = p->rt & 0xf; + ve_dnlp_rl = p->rl; + ve_dnlp_black = p->black; + ve_dnlp_white = p->white; + if (ve_en) { + /* clear historic luma sum */ + ve_dnlp_luma_sum = 0; + /* init tgt & lpf */ + for (i = 0; i < 64; i++) { + ve_dnlp_tgt[i] = i << 2; + ve_dnlp_lpf[i] = ve_dnlp_tgt[i] << ve_dnlp_rt; + } + /* calculate dnlp reg data */ + ve_dnlp_calculate_reg(); + /* load dnlp reg data */ + ve_dnlp_load_reg(); + /* enable dnlp */ + ve_enable_dnlp(); + } else { + /* disable dnlp */ + ve_disable_dnlp(); + } +} + +void ve_set_dnlp_2(void) +{ + ulong i = 0; + /* get command parameters */ + if (is_meson_gxbb_cpu()) { + ve_dnlp_method = 1; + ve_dnlp_cliprate = 6; + ve_dnlp_hghrange = 14; + ve_dnlp_lowrange = 18; + ve_dnlp_hghalpha = 26; + ve_dnlp_midalpha = 28; + ve_dnlp_lowalpha = 18; + } + /* clear historic luma sum */ + ve_dnlp_luma_sum = 0; + /* init tgt & lpf */ + for (i = 0; i < 64; i++) { + ve_dnlp_tgt[i] = i << 2; + ve_dnlp_lpf[i] = ve_dnlp_tgt[i] << ve_dnlp_rt; + } + /* calculate dnlp reg data */ + ve_dnlp_calculate_reg(); + /* load dnlp reg data */ + /*ve_dnlp_load_reg();*/ + ve_dnlp_load_def_reg(); +} + +void ve_set_new_dnlp(struct ve_dnlp_table_s *p) +{ + ulong i = 0; + /* get command parameters */ + ve_en = p->en; + ve_dnlp_method = p->method; + ve_dnlp_cliprate = p->cliprate; + ve_dnlp_hghrange = p->hghrange; + ve_dnlp_lowrange = p->lowrange; + ve_dnlp_hghalpha = p->hghalpha; + ve_dnlp_midalpha = p->midalpha; + ve_dnlp_lowalpha = p->lowalpha; + + ve_dnlp_mvreflsh = p->new_mvreflsh; + ve_dnlp_gmma_rate = p->new_gmma_rate; + ve_dnlp_lowalpha_new = p->new_lowalpha; + ve_dnlp_hghalpha_new = p->new_hghalpha; + ve_dnlp_sbgnbnd = p->new_sbgnbnd; + ve_dnlp_sendbnd = p->new_sendbnd; + ve_dnlp_cliprate_new = p->new_cliprate; + ve_dnlp_clashBgn = p->new_clashBgn; + ve_dnlp_clashEnd = p->new_clashEnd; + ve_mtdbld_rate = p->new_mtdbld_rate; + ve_dnlp_pst_gmarat = p->new_dnlp_pst_gmarat; + + dnlp_sel = p->dnlp_sel; + ve_dnlp_blk_cctr = p->dnlp_blk_cctr; + ve_dnlp_brgt_ctrl = p->dnlp_brgt_ctrl; + ve_dnlp_brgt_range = p->dnlp_brgt_range; + ve_dnlp_brght_add = p->dnlp_brght_add; + ve_dnlp_brght_max = p->dnlp_brght_max; + ve_dnlp_almst_wht = p->dnlp_almst_wht; + + ve_dnlp_hghbin = p->dnlp_hghbin; + ve_dnlp_hghnum = p->dnlp_hghnum; + ve_dnlp_lowbin = p->dnlp_lowbin; + ve_dnlp_lownum = p->dnlp_lownum; + ve_dnlp_bkgend = p->dnlp_bkgend; + ve_dnlp_bkgert = p->dnlp_bkgert; + ve_dnlp_blkext = p->dnlp_blkext; + ve_dnlp_whtext = p->dnlp_whtext; + ve_dnlp_bextmx = p->dnlp_bextmx; + ve_dnlp_wextmx = p->dnlp_wextmx; + ve_dnlp_smhist_ck = p->dnlp_smhist_ck; + ve_dnlp_glb_crate = p->dnlp_glb_crate; + + ve_dnlp_pstgma_brghtrate = p->dnlp_pstgma_brghtrate; + ve_dnlp_pstgma_brghtrat1 = p->dnlp_pstgma_brghtrat1; + ve_dnlp_wext_autorat = p->dnlp_wext_autorat; + ve_dnlp_cliprate_min = p->dnlp_cliprate_min; + ve_dnlp_adpcrat_lbnd = p->dnlp_adpcrat_lbnd; + ve_dnlp_adpcrat_hbnd = p->dnlp_adpcrat_hbnd; + ve_dnlp_adpmtd_lbnd = p->dnlp_adpmtd_lbnd; + ve_dnlp_adpmtd_hbnd = p->dnlp_adpmtd_hbnd; + ve_dnlp_set_bext = p->dnlp_set_bext; + ve_dnlp_set_wext = p->dnlp_set_wext; + ve_dnlp_satur_rat = p->dnlp_satur_rat; + ve_dnlp_satur_max = p->dnlp_satur_max; + ve_blk_prct_rng = p->blk_prct_rng; + ve_blk_prct_max = p->blk_prct_max; + ve_dnlp_lowrange = p->dnlp_lowrange; + ve_dnlp_hghrange = p->dnlp_hghrange; + ve_dnlp_auto_rng = p->dnlp_auto_rng; + ve_dnlp_bin0_absmax = p->dnlp_bin0_absmax; + ve_dnlp_bin0_sbtmax = p->dnlp_bin0_sbtmax; + ve_dnlp_adpalpha_lrate = p->dnlp_adpalpha_lrate; + ve_dnlp_adpalpha_hrate = p->dnlp_adpalpha_hrate; + + ve_dnlp_lrate00 = p->dnlp_lrate00; + ve_dnlp_lrate02 = p->dnlp_lrate02; + ve_dnlp_lrate04 = p->dnlp_lrate04; + ve_dnlp_lrate06 = p->dnlp_lrate06; + ve_dnlp_lrate08 = p->dnlp_lrate08; + ve_dnlp_lrate10 = p->dnlp_lrate10; + ve_dnlp_lrate12 = p->dnlp_lrate12; + ve_dnlp_lrate14 = p->dnlp_lrate14; + ve_dnlp_lrate16 = p->dnlp_lrate16; + ve_dnlp_lrate18 = p->dnlp_lrate18; + ve_dnlp_lrate20 = p->dnlp_lrate20; + ve_dnlp_lrate22 = p->dnlp_lrate22; + ve_dnlp_lrate24 = p->dnlp_lrate24; + ve_dnlp_lrate26 = p->dnlp_lrate26; + ve_dnlp_lrate28 = p->dnlp_lrate28; + ve_dnlp_lrate30 = p->dnlp_lrate30; + ve_dnlp_lrate32 = p->dnlp_lrate32; + ve_dnlp_lrate34 = p->dnlp_lrate34; + ve_dnlp_lrate36 = p->dnlp_lrate36; + ve_dnlp_lrate38 = p->dnlp_lrate38; + ve_dnlp_lrate40 = p->dnlp_lrate40; + ve_dnlp_lrate42 = p->dnlp_lrate42; + ve_dnlp_lrate44 = p->dnlp_lrate44; + ve_dnlp_lrate46 = p->dnlp_lrate46; + ve_dnlp_lrate48 = p->dnlp_lrate48; + ve_dnlp_lrate50 = p->dnlp_lrate50; + ve_dnlp_lrate52 = p->dnlp_lrate52; + ve_dnlp_lrate54 = p->dnlp_lrate54; + ve_dnlp_lrate56 = p->dnlp_lrate56; + ve_dnlp_lrate58 = p->dnlp_lrate58; + ve_dnlp_lrate60 = p->dnlp_lrate60; + ve_dnlp_lrate62 = p->dnlp_lrate62; + + if (ve_en) { + /* clear historic luma sum */ + ve_dnlp_luma_sum = 0; + /* init tgt & lpf */ + for (i = 0; i < 64; i++) { + ve_dnlp_tgt[i] = i << 2; + ve_dnlp_lpf[i] = ve_dnlp_tgt[i] << ve_dnlp_rt; + } + /* calculate dnlp reg data */ + ve_dnlp_calculate_reg(); + /* load dnlp reg data */ + ve_dnlp_load_reg(); + /* enable dnlp */ + ve_enable_dnlp(); + } else { + /* disable dnlp */ + ve_disable_dnlp(); + } +} + +unsigned int ve_get_vs_cnt(void) +{ + return READ_VPP_REG(VPP_VDO_MEAS_VS_COUNT_LO); +} + +void vpp_phase_lock_on_vs(unsigned int cycle, + unsigned int stamp, + bool lock50, + unsigned int range_fast, + unsigned int range_slow) +{ + unsigned int vtotal_ori = READ_VPP_REG(ENCL_VIDEO_MAX_LNCNT); + unsigned int vtotal = lock50 ? 1349 : 1124; + unsigned int stamp_in = READ_VPP_REG(VDIN_MEAS_VS_COUNT_LO); + unsigned int stamp_out = ve_get_vs_cnt(); + unsigned int phase = 0; + unsigned int cnt = assist_cnt;/* READ_VPP_REG(ASSIST_SPARE8_REG1); */ + int step = 0, i = 0; + /* get phase */ + if (stamp_out < stamp) + phase = 0xffffffff - stamp + stamp_out + 1; + else + phase = stamp_out - stamp; + while (phase >= cycle) + phase -= cycle; + /* 225~315 degree => tune fast panel output */ + if ((phase > ((cycle * 5) >> 3)) && (phase < ((cycle * 7) >> 3))) { + vtotal -= range_slow; + step = 1; + } else if ((phase > (cycle >> 3)) && (phase < ((cycle * 3) >> 3))) { + /* 45~135 degree => tune slow panel output */ + vtotal += range_slow; + step = -1; + } else if (phase >= ((cycle * 7) >> 3)) { + /* 315~360 degree => tune fast panel output */ + vtotal -= range_fast; + step = + 2; + } else if (phase <= (cycle >> 3)) { + /* 0~45 degree => tune slow panel output */ + vtotal += range_fast; + step = -2; + } else {/* 135~225 degree => keep still */ + vtotal = vtotal_ori; + step = 0; + } + if (vtotal != vtotal_ori) + WRITE_VPP_REG(ENCL_VIDEO_MAX_LNCNT, vtotal); + if (cnt) { + cnt--; + /* WRITE_VPP_REG(ASSIST_SPARE8_REG1, cnt); */ + assist_cnt = cnt; + if (cnt) { + vpp_log[cnt][0] = stamp; + vpp_log[cnt][1] = stamp_in; + vpp_log[cnt][2] = stamp_out; + vpp_log[cnt][3] = cycle; + vpp_log[cnt][4] = phase; + vpp_log[cnt][5] = vtotal; + vpp_log[cnt][6] = step; + } else { + for (i = 127; i > 0; i--) { + pr_amve_dbg("Ti=%10u Tio=%10u To=%10u CY=%6u ", + vpp_log[i][0], + vpp_log[i][1], + vpp_log[i][2], + vpp_log[i][3]); + pr_amve_dbg("PH =%10u Vt=%4u S=%2d\n", + vpp_log[i][4], + vpp_log[i][5], + vpp_log[i][6]); + } + } + } + +} + +void ve_frame_size_patch(unsigned int width, unsigned int height) +{ + unsigned int vpp_size = height|(width << 16); + + if (READ_VPP_REG(VPP_VE_H_V_SIZE) != vpp_size) + WRITE_VPP_REG(VPP_VE_H_V_SIZE, vpp_size); +} + +void ve_dnlp_latch_process(void) +{ + if (vecm_latch_flag & FLAG_VE_DNLP) { + vecm_latch_flag &= ~FLAG_VE_DNLP; + ve_set_dnlp(&am_ve_dnlp); + } + if (vecm_latch_flag & FLAG_VE_NEW_DNLP) { + vecm_latch_flag &= ~FLAG_VE_NEW_DNLP; + ve_set_new_dnlp(&am_ve_new_dnlp); + } + if (vecm_latch_flag & FLAG_VE_DNLP_EN) { + vecm_latch_flag &= ~FLAG_VE_DNLP_EN; + ve_enable_dnlp(); + pr_amve_dbg("\n[amve..] set vpp_enable_dnlp OK!!!\n"); + } + if (vecm_latch_flag & FLAG_VE_DNLP_DIS) { + vecm_latch_flag &= ~FLAG_VE_DNLP_DIS; + ve_disable_dnlp(); + pr_amve_dbg("\n[amve..] set vpp_disable_dnlp OK!!!\n"); + } + if (dnlp_en && dnlp_status) { + dnlp_status = 0; + ve_set_dnlp_2(); + ve_enable_dnlp(); + pr_amve_dbg("\n[amve..] set vpp_enable_dnlp OK!!!\n"); + } else if (dnlp_en == 0) { + dnlp_status = 1; + ve_disable_dnlp(); + pr_amve_dbg("\n[amve..] set vpp_disable_dnlp OK!!!\n"); + } +} + +void ve_lcd_gamma_process(void) +{ + if (vecm_latch_flag & FLAG_GAMMA_TABLE_EN) { + vecm_latch_flag &= ~FLAG_GAMMA_TABLE_EN; + vpp_enable_lcd_gamma_table(); + pr_amve_dbg("\n[amve..] set vpp_enable_lcd_gamma_table OK!!!\n"); + } + if (vecm_latch_flag & FLAG_GAMMA_TABLE_DIS) { + vecm_latch_flag &= ~FLAG_GAMMA_TABLE_DIS; + vpp_disable_lcd_gamma_table(); + pr_amve_dbg("\n[amve..] set vpp_disable_lcd_gamma_table OK!!!\n"); + } + if (vecm_latch_flag & FLAG_GAMMA_TABLE_R) { + vecm_latch_flag &= ~FLAG_GAMMA_TABLE_R; + vpp_set_lcd_gamma_table(video_gamma_table_r.data, H_SEL_R); + pr_amve_dbg("\n[amve..] set vpp_set_lcd_gamma_table OK!!!\n"); + } + if (vecm_latch_flag & FLAG_GAMMA_TABLE_G) { + vecm_latch_flag &= ~FLAG_GAMMA_TABLE_G; + vpp_set_lcd_gamma_table(video_gamma_table_g.data, H_SEL_G); + pr_amve_dbg("\n[amve..] set vpp_set_lcd_gamma_table OK!!!\n"); + } + if (vecm_latch_flag & FLAG_GAMMA_TABLE_B) { + vecm_latch_flag &= ~FLAG_GAMMA_TABLE_B; + vpp_set_lcd_gamma_table(video_gamma_table_b.data, H_SEL_B); + pr_amve_dbg("\n[amve..] set vpp_set_lcd_gamma_table OK!!!\n"); + } + if (vecm_latch_flag & FLAG_RGB_OGO) { + vecm_latch_flag &= ~FLAG_RGB_OGO; + if (video_rgb_ogo_mode_sw) { + if (video_rgb_ogo.en) { + vpp_set_lcd_gamma_table( + video_gamma_table_r_adj.data, + H_SEL_R); + vpp_set_lcd_gamma_table( + video_gamma_table_g_adj.data, + H_SEL_G); + vpp_set_lcd_gamma_table( + video_gamma_table_b_adj.data, + H_SEL_B); + } else { + vpp_set_lcd_gamma_table( + video_gamma_table_r.data, + H_SEL_R); + vpp_set_lcd_gamma_table( + video_gamma_table_g.data, + H_SEL_G); + vpp_set_lcd_gamma_table( + video_gamma_table_b.data, + H_SEL_B); + } + pr_amve_dbg("\n[amve..] set vpp_set_lcd_gamma_table OK!!!\n"); + } else { + vpp_set_rgb_ogo(&video_rgb_ogo); + pr_amve_dbg("\n[amve..] set vpp_set_rgb_ogo OK!!!\n"); + } + } +} +void lvds_freq_process(void) +{ +/* #if ((MESON_CPU_TYPE==MESON_CPU_TYPE_MESON6TV)|| */ +/* (MESON_CPU_TYPE==MESON_CPU_TYPE_MESON6TVD)) */ +/* lvds freq 50Hz/60Hz */ +/* if (frame_lock_freq == 1){//50 hz */ +/* // panel freq is 60Hz => change back to 50Hz */ +/* if (READ_VPP_REG(ENCP_VIDEO_MAX_LNCNT) < 1237) */ +/* (1124 + 1349 +1) / 2 */ +/* WRITE_VPP_REG(ENCP_VIDEO_MAX_LNCNT, 1349); */ +/* } */ +/* else if (frame_lock_freq == 2){//60 hz */ +/* // panel freq is 50Hz => change back to 60Hz */ +/* if(READ_VPP_REG(ENCP_VIDEO_MAX_LNCNT) >= 1237) */ +/* (1124 + 1349 + 1) / 2 */ +/* WRITE_VPP_REG(ENCP_VIDEO_MAX_LNCNT, 1124); */ +/* } */ +/* else if (frame_lock_freq == 0){ */ +/* lvds freq 50Hz/60Hz */ +/* if (vecm_latch_flag & FLAG_LVDS_FREQ_SW){ //50 hz */ +/* // panel freq is 60Hz => change back to 50Hz */ +/* if (READ_VPP_REG(ENCP_VIDEO_MAX_LNCNT) < 1237) */ +/* (1124 + 1349 +1) / 2 */ +/* WRITE_VPP_REG(ENCP_VIDEO_MAX_LNCNT, 1349); */ +/* }else{ //60 hz */ +/* // panel freq is 50Hz => change back to 60Hz */ +/* if (READ_VPP_REG(ENCP_VIDEO_MAX_LNCNT) >= 1237) */ +/* (1124 + 1349 + 1) / 2 */ +/* WRITE_VPP_REG(ENCP_VIDEO_MAX_LNCNT, 1124); */ +/* } */ +/* } */ +/* #endif */ +} + +void ve_dnlp_param_update(void) +{ + if (am_ve_dnlp.en > 1) + am_ve_dnlp.en = 1; + if (am_ve_dnlp.black > 16) + am_ve_dnlp.black = 16; + if (am_ve_dnlp.white > 16) + am_ve_dnlp.white = 16; + vecm_latch_flag |= FLAG_VE_DNLP; +} + +void ve_new_dnlp_param_update(void) +{ + if (am_ve_new_dnlp.en > 1) + am_ve_new_dnlp.en = 1; + if (am_ve_new_dnlp.cliprate > 256) + am_ve_new_dnlp.cliprate = 256; + if (am_ve_new_dnlp.lowrange > 54) + am_ve_new_dnlp.lowrange = 54; + if (am_ve_new_dnlp.hghrange > 54) + am_ve_new_dnlp.hghrange = 54; + if (am_ve_new_dnlp.lowalpha > 48) + am_ve_new_dnlp.lowalpha = 48; + if (am_ve_new_dnlp.midalpha > 48) + am_ve_new_dnlp.midalpha = 48; + if (am_ve_new_dnlp.hghalpha > 48) + am_ve_new_dnlp.hghalpha = 48; + + if (am_ve_new_dnlp.dnlp_blk_cctr > 64) + am_ve_new_dnlp.dnlp_blk_cctr = 64; + if (am_ve_new_dnlp.dnlp_brgt_ctrl > 64) + am_ve_new_dnlp.dnlp_brgt_ctrl = 64; + if (am_ve_new_dnlp.dnlp_brgt_range > 64) + am_ve_new_dnlp.dnlp_brgt_range = 64; + if (am_ve_new_dnlp.dnlp_brght_add > 64) + am_ve_new_dnlp.dnlp_brght_add = 64; + if (am_ve_new_dnlp.dnlp_brght_max > 64) + am_ve_new_dnlp.dnlp_brght_max = 64; + if (am_ve_new_dnlp.dnlp_almst_wht > 64) + am_ve_new_dnlp.dnlp_almst_wht = 64; + + if (am_ve_new_dnlp.dnlp_hghbin > 64) + am_ve_new_dnlp.dnlp_hghbin = 64; + if (am_ve_new_dnlp.dnlp_hghnum > 64) + am_ve_new_dnlp.dnlp_hghnum = 64; + if (am_ve_new_dnlp.dnlp_lowbin > 64) + am_ve_new_dnlp.dnlp_lowbin = 64; + if (am_ve_new_dnlp.dnlp_lownum > 64) + am_ve_new_dnlp.dnlp_lownum = 64; + if (am_ve_new_dnlp.dnlp_bkgend > 64) + am_ve_new_dnlp.dnlp_bkgend = 64; + if (am_ve_new_dnlp.dnlp_bkgert > 64) + am_ve_new_dnlp.dnlp_bkgert = 64; + if (am_ve_new_dnlp.dnlp_blkext > 64) + am_ve_new_dnlp.dnlp_blkext = 64; + if (am_ve_new_dnlp.dnlp_whtext > 64) + am_ve_new_dnlp.dnlp_whtext = 64; + if (am_ve_new_dnlp.dnlp_bextmx > 64) + am_ve_new_dnlp.dnlp_bextmx = 64; + if (am_ve_new_dnlp.dnlp_wextmx > 64) + am_ve_new_dnlp.dnlp_wextmx = 64; + if (am_ve_new_dnlp.dnlp_smhist_ck > 1) + am_ve_new_dnlp.dnlp_smhist_ck = 1; + if (am_ve_new_dnlp.dnlp_glb_crate > 1) + am_ve_new_dnlp.dnlp_glb_crate = 1; + + if (am_ve_new_dnlp.dnlp_lrate00 > 64) + am_ve_new_dnlp.dnlp_lrate00 = 64; + if (am_ve_new_dnlp.dnlp_lrate02 > 64) + am_ve_new_dnlp.dnlp_lrate02 = 64; + if (am_ve_new_dnlp.dnlp_lrate04 > 64) + am_ve_new_dnlp.dnlp_lrate04 = 64; + if (am_ve_new_dnlp.dnlp_lrate06 > 64) + am_ve_new_dnlp.dnlp_lrate06 = 64; + if (am_ve_new_dnlp.dnlp_lrate08 > 64) + am_ve_new_dnlp.dnlp_lrate08 = 64; + if (am_ve_new_dnlp.dnlp_lrate10 > 64) + am_ve_new_dnlp.dnlp_lrate10 = 64; + if (am_ve_new_dnlp.dnlp_lrate12 > 64) + am_ve_new_dnlp.dnlp_lrate12 = 64; + if (am_ve_new_dnlp.dnlp_lrate14 > 64) + am_ve_new_dnlp.dnlp_lrate14 = 64; + if (am_ve_new_dnlp.dnlp_lrate16 > 64) + am_ve_new_dnlp.dnlp_lrate16 = 64; + if (am_ve_new_dnlp.dnlp_lrate18 > 64) + am_ve_new_dnlp.dnlp_lrate18 = 64; + if (am_ve_new_dnlp.dnlp_lrate20 > 64) + am_ve_new_dnlp.dnlp_lrate20 = 64; + if (am_ve_new_dnlp.dnlp_lrate22 > 64) + am_ve_new_dnlp.dnlp_lrate22 = 64; + if (am_ve_new_dnlp.dnlp_lrate24 > 64) + am_ve_new_dnlp.dnlp_lrate24 = 64; + if (am_ve_new_dnlp.dnlp_lrate26 > 64) + am_ve_new_dnlp.dnlp_lrate26 = 64; + if (am_ve_new_dnlp.dnlp_lrate28 > 64) + am_ve_new_dnlp.dnlp_lrate28 = 64; + if (am_ve_new_dnlp.dnlp_lrate30 > 64) + am_ve_new_dnlp.dnlp_lrate30 = 64; + if (am_ve_new_dnlp.dnlp_lrate32 > 64) + am_ve_new_dnlp.dnlp_lrate32 = 64; + if (am_ve_new_dnlp.dnlp_lrate34 > 64) + am_ve_new_dnlp.dnlp_lrate34 = 64; + if (am_ve_new_dnlp.dnlp_lrate36 > 64) + am_ve_new_dnlp.dnlp_lrate36 = 64; + if (am_ve_new_dnlp.dnlp_lrate38 > 64) + am_ve_new_dnlp.dnlp_lrate38 = 64; + if (am_ve_new_dnlp.dnlp_lrate40 > 64) + am_ve_new_dnlp.dnlp_lrate40 = 64; + if (am_ve_new_dnlp.dnlp_lrate42 > 64) + am_ve_new_dnlp.dnlp_lrate42 = 64; + if (am_ve_new_dnlp.dnlp_lrate44 > 64) + am_ve_new_dnlp.dnlp_lrate44 = 64; + if (am_ve_new_dnlp.dnlp_lrate46 > 64) + am_ve_new_dnlp.dnlp_lrate46 = 64; + if (am_ve_new_dnlp.dnlp_lrate48 > 64) + am_ve_new_dnlp.dnlp_lrate48 = 64; + if (am_ve_new_dnlp.dnlp_lrate50 > 64) + am_ve_new_dnlp.dnlp_lrate50 = 64; + if (am_ve_new_dnlp.dnlp_lrate52 > 64) + am_ve_new_dnlp.dnlp_lrate52 = 64; + if (am_ve_new_dnlp.dnlp_lrate54 > 64) + am_ve_new_dnlp.dnlp_lrate54 = 64; + if (am_ve_new_dnlp.dnlp_lrate56 > 64) + am_ve_new_dnlp.dnlp_lrate56 = 64; + if (am_ve_new_dnlp.dnlp_lrate58 > 64) + am_ve_new_dnlp.dnlp_lrate58 = 64; + if (am_ve_new_dnlp.dnlp_lrate60 > 64) + am_ve_new_dnlp.dnlp_lrate60 = 64; + if (am_ve_new_dnlp.dnlp_lrate62 > 64) + am_ve_new_dnlp.dnlp_lrate62 = 64; + + vecm_latch_flag |= FLAG_VE_NEW_DNLP; +} + + + +static void video_data_limitation(int *val) +{ + if (*val > 1023) + *val = 1023; + if (*val < 0) + *val = 0; +} + +static void video_lookup(struct tcon_gamma_table_s *tbl, int *val) +{ + unsigned int idx = (*val) >> 2, mod = (*val) & 3; + + if (idx < 255) + *val = tbl->data[idx] + + (((tbl->data[idx + 1] - tbl->data[idx]) * mod + 2) >> 2); + else + *val = tbl->data[idx] + + (((1023 - tbl->data[idx]) * mod + 2) >> 2); +} + +static void video_set_rgb_ogo(void) +{ + int i = 0, r = 0, g = 0, b = 0; + + for (i = 0; i < 256; i++) { + r = video_curve_2d2.data[i]; + g = video_curve_2d2.data[i]; + b = video_curve_2d2.data[i]; + /* Pre_offset */ + r += video_rgb_ogo.r_pre_offset; + g += video_rgb_ogo.g_pre_offset; + b += video_rgb_ogo.b_pre_offset; + video_data_limitation(&r); + video_data_limitation(&g); + video_data_limitation(&b); + /* Gain */ + r *= video_rgb_ogo.r_gain; + r >>= 10; + g *= video_rgb_ogo.g_gain; + g >>= 10; + b *= video_rgb_ogo.b_gain; + b >>= 10; + video_data_limitation(&r); + video_data_limitation(&g); + video_data_limitation(&b); + /* Post_offset */ + r += video_rgb_ogo.r_post_offset; + g += video_rgb_ogo.g_post_offset; + b += video_rgb_ogo.b_post_offset; + video_data_limitation(&r); + video_data_limitation(&g); + video_data_limitation(&b); + video_lookup(&video_curve_2d2_inv, &r); + video_lookup(&video_curve_2d2_inv, &g); + video_lookup(&video_curve_2d2_inv, &b); + /* Get gamma_ogo = curve_2d2_inv_ogo * gamma */ + video_lookup(&video_gamma_table_r, &r); + video_lookup(&video_gamma_table_g, &g); + video_lookup(&video_gamma_table_b, &b); + /* Save gamma_ogo */ + video_gamma_table_r_adj.data[i] = r; + video_gamma_table_g_adj.data[i] = g; + video_gamma_table_b_adj.data[i] = b; + } +} + +void ve_ogo_param_update(void) +{ + if (video_rgb_ogo.en > 1) + video_rgb_ogo.en = 1; + if (video_rgb_ogo.r_pre_offset > 1023) + video_rgb_ogo.r_pre_offset = 1023; + if (video_rgb_ogo.r_pre_offset < -1024) + video_rgb_ogo.r_pre_offset = -1024; + if (video_rgb_ogo.g_pre_offset > 1023) + video_rgb_ogo.g_pre_offset = 1023; + if (video_rgb_ogo.g_pre_offset < -1024) + video_rgb_ogo.g_pre_offset = -1024; + if (video_rgb_ogo.b_pre_offset > 1023) + video_rgb_ogo.b_pre_offset = 1023; + if (video_rgb_ogo.b_pre_offset < -1024) + video_rgb_ogo.b_pre_offset = -1024; + if (video_rgb_ogo.r_gain > 2047) + video_rgb_ogo.r_gain = 2047; + if (video_rgb_ogo.r_gain < 0) + video_rgb_ogo.r_gain = 0; + if (video_rgb_ogo.g_gain > 2047) + video_rgb_ogo.g_gain = 2047; + if (video_rgb_ogo.g_gain < 0) + video_rgb_ogo.g_gain = 0; + if (video_rgb_ogo.b_gain > 2047) + video_rgb_ogo.b_gain = 2047; + if (video_rgb_ogo.b_gain < 0) + video_rgb_ogo.b_gain = 0; + if (video_rgb_ogo.r_post_offset > 1023) + video_rgb_ogo.r_post_offset = 1023; + if (video_rgb_ogo.r_post_offset < -1024) + video_rgb_ogo.r_post_offset = -1024; + if (video_rgb_ogo.g_post_offset > 1023) + video_rgb_ogo.g_post_offset = 1023; + if (video_rgb_ogo.g_post_offset < -1024) + video_rgb_ogo.g_post_offset = -1024; + if (video_rgb_ogo.b_post_offset > 1023) + video_rgb_ogo.b_post_offset = 1023; + if (video_rgb_ogo.b_post_offset < -1024) + video_rgb_ogo.b_post_offset = -1024; + if (video_rgb_ogo_mode_sw) + video_set_rgb_ogo(); + + vecm_latch_flag |= FLAG_RGB_OGO; +} + +static unsigned int vlock_check_input_hz(struct vframe_s *vf) +{ + unsigned int ret_hz = 0; + unsigned int duration = vf->duration; + + if ((vf->source_type != VFRAME_SOURCE_TYPE_CVBS) && + (vf->source_type != VFRAME_SOURCE_TYPE_HDMI)) + ret_hz = 0; + else if (vf->source_type == VFRAME_SOURCE_TYPE_HDMI) { + if (duration != 0) + ret_hz = (96000 + duration/2)/duration; + } else if (vf->source_type == VFRAME_SOURCE_TYPE_CVBS) { + if (vf->source_mode == VFRAME_SOURCE_MODE_NTSC) + ret_hz = 60; + else if ((vf->source_mode == VFRAME_SOURCE_MODE_PAL) || + (vf->source_mode == VFRAME_SOURCE_MODE_SECAM)) + ret_hz = 50; + else + ret_hz = 0; + } + return ret_hz; +} + +static unsigned int vlock_check_output_hz(unsigned int sync_duration_num) +{ + unsigned int ret_hz = 0; + + switch (sync_duration_num) { + case 24: + ret_hz = 24; + break; + case 30: + ret_hz = 30; + break; + case 50: + ret_hz = 50; + break; + case 60: + ret_hz = 60; + break; + case 100: + ret_hz = 100; + break; + case 120: + ret_hz = 120; + break; + default: + ret_hz = 0; + break; + } + return ret_hz; +} +static void vlock_enable(bool enable) +{ + if (is_meson_gxtvbb_cpu() || + is_meson_gxbb_cpu() || is_meson_txl_cpu()) { + if (vlock_mode == VLOCK_MODE_MANUAL_PLL) + amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6, 0, 20, 1); + else + amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6, + enable, 20, 1); + } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) { + if (vlock_mode == VLOCK_MODE_MANUAL_PLL) + amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL5, 0, 3, 1); + else + amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL5, + enable, 3, 1); + } +} +static void vlock_setting(struct vframe_s *vf, + unsigned int input_hz, unsigned int output_hz) +{ + unsigned int freq_hz = 0, hiu_reg_value_2_addr = HHI_HDMI_PLL_CNTL2; + unsigned int reg_value = 0, hiu_reg_value, hiu_reg_value_2; + unsigned int hiu_m_val, hiu_frac_val; + + amvecm_hiu_reg_write(HHI_VID_LOCK_CLK_CNTL, 0x80); + if (vlock_mode == VLOCK_MODE_ENC) { + am_set_regmap(&vlock_enc_lcd720x480); + /* VLOCK_CNTL_EN disable */ + vlock_enable(0); + /* disable to adjust pll */ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 29, 1); + /* CFG_VID_LOCK_ADJ_EN enable */ + WRITE_VPP_REG_BITS(ENCL_MAX_LINE_SWITCH_POINT, 1, 13, 1); + /* enable to adjust pll */ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 30, 1); + /*clear accum1 value*/ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 2, 1); + /*clear accum0 value*/ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 5, 1); + } + if ((vlock_mode == VLOCK_MODE_PLL) || + (vlock_mode == VLOCK_MODE_MANUAL_PLL)) { + /* av pal in,1080p60 hdmi out as default */ + am_set_regmap(&vlock_pll_in50hz_out60hz); + /*set input & output freq*/ + /*bit0~7:input freq*/ + /*bit8~15:output freq*/ + freq_hz = input_hz | (output_hz << 8); + WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, freq_hz, 0, 16); + /*Ifrm_cnt_mod:0x3001(bit23~16);*/ + /*(output_freq/input_freq)*Ifrm_cnt_mod must be integer*/ + if (vlock_adapt == 0) + WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, 1, 16, 8); + else + WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, + input_hz, 16, 8); + /*set PLL M_INT;PLL M_frac*/ + /* WRITE_VPP_REG_BITS(VPU_VLOCK_MX4096, */ + /* READ_CBUS_REG_BITS(HHI_HDMI_PLL_CNTL,0,9),12,9); */ + amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL, &hiu_reg_value); + amvecm_hiu_reg_read(hiu_reg_value_2_addr, + &hiu_reg_value_2); + if (is_meson_gxtvbb_cpu() || is_meson_txl_cpu()) { + hiu_m_val = hiu_reg_value & 0x1FF; + hiu_frac_val = hiu_reg_value_2 & 0x3FF; + if (hiu_reg_value_2 & 0x800) { + hiu_m_val -= 1; + if (hiu_reg_value_2 & 0x400) + hiu_m_val -= 1; + hiu_frac_val = 0x400 - + ((~(hiu_frac_val - 1)) & 0x3ff); + } else if (hiu_reg_value_2 & 0x400) { + hiu_m_val += 1; + } + reg_value = (hiu_m_val << 12) + + (hiu_frac_val << 2); + } + WRITE_VPP_REG_BITS(VPU_VLOCK_MX4096, reg_value, 0, 21); + + /* vlock module output goes to which module */ + switch (READ_VPP_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 0, 2)) { + case 0:/* ENCL */ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 26, 2); + break; + case 1:/* ENCI */ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 2, 26, 2); + break; + case 2: /* ENCP */ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 26, 2); + break; + default: + break; + } + /*enable vlock to adj pll*/ + /* CFG_VID_LOCK_ADJ_EN disable */ + WRITE_VPP_REG_BITS(ENCL_MAX_LINE_SWITCH_POINT, 0, 13, 1); + /* disable to adjust pll */ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 30, 1); + /* VLOCK_CNTL_EN enable */ + vlock_enable(1); + /* enable to adjust pll */ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 29, 1); + } + if ((vf->source_type == VFRAME_SOURCE_TYPE_TUNER) || + (vf->source_type == VFRAME_SOURCE_TYPE_CVBS)) + /* Input Vsync source select from tv-decoder */ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 2, 16, 3); + else if (vf->source_type == VFRAME_SOURCE_TYPE_HDMI) + /* Input Vsync source select from hdmi-rx */ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 16, 3); + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 31, 1); +} +void vlock_vmode_check(void) +{ + const struct vinfo_s *vinfo; + unsigned int tmp_value, hiu_reg_addr; + char cur_vout_mode[64]; + + if (vlock_en == 0) + return; + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) + hiu_reg_addr = HHI_HDMI_PLL_CNTL1; + else + hiu_reg_addr = HHI_HDMI_PLL_CNTL2; + + vinfo = get_current_vinfo(); + vlock_vmode_changed = 0; + memset(cur_vout_mode, 0, sizeof(cur_vout_mode)); + strcpy(cur_vout_mode, vinfo->name); + if (strcmp(cur_vout_mode, pre_vout_mode) != 0) { + amvecm_hiu_reg_read(hiu_reg_addr, &tmp_value); + pre_hiu_reg_frac = tmp_value & 0xfff; + amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL, &tmp_value); + pre_hiu_reg_m = tmp_value & 0x1ff; + if (vlock_debug & 0x10) + pr_info("[%s]:vout mode changed:%s==>%s\n", + __func__, pre_vout_mode, cur_vout_mode); + memset(pre_vout_mode, 0, sizeof(pre_vout_mode)); + strcpy(pre_vout_mode, cur_vout_mode); + vlock_vmode_changed = 1; + } +} +static void vlock_disable_step1(void) +{ + unsigned int m_reg_value, tmp_value; + unsigned int hiu_reg_addr; + + /* VLOCK_CNTL_EN disable */ + vlock_enable(0); + vlock_vmode_check(); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) + hiu_reg_addr = HHI_HDMI_PLL_CNTL1; + else + hiu_reg_addr = HHI_HDMI_PLL_CNTL2; + + amvecm_hiu_reg_read(hiu_reg_addr, &tmp_value); + m_reg_value = tmp_value & 0xfff; + if ((m_reg_value != pre_hiu_reg_frac) && + (pre_hiu_reg_frac != 0)) { + tmp_value = (tmp_value & 0xfffff000) | + (pre_hiu_reg_frac & 0xfff); + amvecm_hiu_reg_write(hiu_reg_addr, tmp_value); + } + amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL, &tmp_value); + m_reg_value = tmp_value & 0x1ff; + if ((m_reg_value != pre_hiu_reg_m) && + (pre_hiu_reg_m != 0)) { + tmp_value = (tmp_value & 0xfffffe00) | + (pre_hiu_reg_m & 0x1ff); + amvecm_hiu_reg_write(HHI_HDMI_PLL_CNTL, tmp_value); + } + vlock_dis_cnt = vlock_dis_cnt_limit; + pre_vmode = VMODE_INIT_NULL; + pre_source_type = VFRAME_SOURCE_TYPE_OTHERS; + pre_source_mode = VFRAME_SOURCE_MODE_OTHERS; + pre_input_freq = 0; + pre_output_freq = 0; + vlock_state = VLOCK_STATE_DISABLE_STEP1_DONE; +} + +static void vlock_disable_step2(void) +{ + /* need delay to disable follow regs(vlsi suggest!!!) */ + if (vlock_dis_cnt > 0) + vlock_dis_cnt--; + if (vlock_dis_cnt == 0) { + /* disable to adjust pll */ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 29, 1); + /* CFG_VID_LOCK_ADJ_EN disable */ + WRITE_VPP_REG_BITS(ENCL_MAX_LINE_SWITCH_POINT, + 0, 13, 1); + /* disable to adjust pll */ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 30, 1); + /* disable vid_lock_en */ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 31, 1); + vlock_state = VLOCK_STATE_DISABLE_STEP2_DONE; + } +} +static void vlock_enable_step1(struct vframe_s *vf, struct vinfo_s *vinfo, + unsigned int input_hz, unsigned int output_hz) +{ + vlock_setting(vf, input_hz, output_hz); + if (vlock_debug & 0x10) { + pr_info("%s:vmode/source_type/source_mode/input_freq/output_freq:\n", + __func__); + pr_info("\t%d/%d/%d/%d/%d=>%d/%d/%d/%d/%d\n", + pre_vmode, pre_source_type, pre_source_mode, + pre_input_freq, pre_output_freq, + vinfo->mode, vf->source_type, vf->source_mode, + input_hz, output_hz); + } + pre_vmode = vinfo->mode; + pre_source_type = vf->source_type; + pre_source_mode = vf->source_mode; + pre_input_freq = input_hz; + pre_output_freq = output_hz; + vlock_sync_limit_flag = 0; + vlock_vmode_changed = 0; + vlock_dis_cnt = 0; + vlock_state = VLOCK_STATE_ENABLE_STEP1_DONE; + +} +static void vlock_enable_step3(void) +{ + unsigned int m_reg_value, tmp_value, abs_val; + unsigned int hiu_reg_addr; + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) + hiu_reg_addr = HHI_HDMI_PLL_CNTL1; + else + hiu_reg_addr = HHI_HDMI_PLL_CNTL2; + + m_reg_value = READ_VPP_REG(VPU_VLOCK_RO_M_INT_FRAC); + if (m_reg_value == 0) { + vlock_state = VLOCK_STATE_ENABLE_FORCE_RESET; + if (vlock_debug & 0x100) + pr_info("%s:vlock work abnormal! force reset vlock\n", + __func__); + return; + } + /*frac*/ + amvecm_hiu_reg_read(hiu_reg_addr, &tmp_value); + abs_val = abs(((m_reg_value & 0xfff) >> 2) - (tmp_value & 0xfff)); + if ((abs_val < vlock_delta_limit_frac) && (abs_val > 2)) { + tmp_value = (tmp_value & 0xfffff000) | + ((m_reg_value & 0xfff) >> 2); + amvecm_hiu_reg_write(hiu_reg_addr, tmp_value); + } + /*M*/ + amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL, &tmp_value); + abs_val = abs(((m_reg_value >> 16) & 0x1ff) - (tmp_value & 0x1ff)); + if (abs_val <= vlock_delta_limit_m) { + tmp_value = (tmp_value & 0xfffffe00) | + ((m_reg_value >> 16) & 0x1ff); + amvecm_hiu_reg_write(HHI_HDMI_PLL_CNTL, tmp_value); + } +} +/* won't change this function internal seqence,*/ +/* if really need change,please be carefull */ +void amve_vlock_process(struct vframe_s *vf) +{ + struct vinfo_s *vinfo; + unsigned int input_hz, output_hz, input_vs_cnt; + + if (vecm_latch_flag & FLAG_VLOCK_DIS) { + vlock_disable_step1(); + vlock_en = 0; + vecm_latch_flag &= ~FLAG_VLOCK_DIS; + if (vlock_debug & 0x1) + pr_info("[%s]disable vlock module!!!\n", __func__); + return; + } + vinfo = get_current_vinfo(); + input_hz = vlock_check_input_hz(vf); + output_hz = vlock_check_output_hz(vinfo->sync_duration_num); + if (vecm_latch_flag & FLAG_VLOCK_EN) { + vlock_enable_step1(vf, vinfo, input_hz, output_hz); + vlock_en = 1; + vecm_latch_flag &= ~FLAG_VLOCK_EN; + } + if (vlock_state == VLOCK_STATE_DISABLE_STEP1_DONE) { + vlock_disable_step2(); + return; + } + if (vlock_en == 1) { + if (((input_hz != output_hz) && (vlock_adapt == 0)) || + (input_hz == 0) || (output_hz == 0)) { + vlock_dis_cnt_step1++; + if ((vlock_state != VLOCK_STATE_DISABLE_STEP2_DONE) && + (vlock_dis_cnt_step1 > + vlock_dis_cnt_step1_limit) && + (vlock_state != VLOCK_STATE_NULL)) { + vlock_disable_step1(); + if (vlock_debug & 0x1) + pr_info("[%s]auto disable vlock module for no support case!!!\n", + __func__); + } else + vlock_state = VLOCK_STATE_DISABLE_STEP1; + return; + } + vlock_dis_cnt_step1 = 0; + if (vlock_state == VLOCK_STATE_ENABLE_STEP1) + vlock_state = VLOCK_STATE_ENABLE_FORCE_RESET; + vlock_vmode_check(); + if ((vinfo->mode != pre_vmode) || + (vf->source_type != pre_source_type) || + (vf->source_mode != pre_source_mode) || + (input_hz != pre_input_freq) || + (output_hz != pre_output_freq) || + vlock_vmode_changed || + (vlock_state == VLOCK_STATE_ENABLE_FORCE_RESET) || + (vlock_state == VLOCK_STATE_ENABLE_STEP1)) { + if (vlock_sync_limit_flag++ > vlock_en_cnt_step1_limit) + vlock_enable_step1(vf, vinfo, + input_hz, output_hz); + else + vlock_state = VLOCK_STATE_ENABLE_STEP1; + return; + } + if (vlock_state == VLOCK_STATE_ENABLE_STEP1_DONE) { + /*input_vs_cnt =*/ + /*READ_VPP_REG_BITS(VPU_VLOCK_RO_VS_I_DIST,*/ + /* 0, 28);*/ + input_vs_cnt = XTAL_VLOCK_CLOCK/input_hz; + WRITE_VPP_REG(VPU_VLOCK_LOOP1_IMISSYNC_MAX, + input_vs_cnt*125/100); + WRITE_VPP_REG(VPU_VLOCK_LOOP1_IMISSYNC_MIN, + input_vs_cnt*70/100); + /*cal accum1 value*/ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 2, 1); + /*cal accum0 value*/ + WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 5, 1); + vlock_state = VLOCK_STATE_ENABLE_STEP2_DONE; + return; + } else if (vlock_dynamic_adjust && + (vlock_state == VLOCK_STATE_ENABLE_STEP2_DONE) && + (is_meson_gxtvbb_cpu() || is_meson_txl_cpu()) && + (vlock_mode == VLOCK_MODE_MANUAL_PLL)) { + vlock_enable_step3(); + return; + } + } +} + +void amve_vlock_resume(void) +{ + vlock_sync_limit_flag = 0; + if ((vlock_en == 0) || (vlock_state == + VLOCK_STATE_DISABLE_STEP2_DONE) || + (vlock_state == VLOCK_STATE_NULL)) + return; + if (vlock_state == VLOCK_STATE_DISABLE_STEP1_DONE) { + vlock_disable_step2(); + return; + } + vlock_dis_cnt_step1++; + if ((vlock_state != VLOCK_STATE_DISABLE_STEP2_DONE) && + (vlock_dis_cnt_step1 > vlock_dis_cnt_step1_limit)) { + vlock_disable_step1(); + vlock_dis_cnt_step1 = 0; + if (vlock_debug & 0x1) + pr_info("[%s]auto disable vlock module for no vframe & run disable step1.!!!\n", + __func__); + } + if (vlock_debug & 0x1) + pr_info("[%s]auto disable vlock module for no vframe!!!\n", + __func__); +} + +void vlock_param_set(unsigned int val, enum vlock_param_e sel) +{ + switch (sel) { + case VLOCK_EN: + vlock_en = val; + break; + case VLOCK_ADAPT: + vlock_adapt = val; + break; + case VLOCK_MODE: + vlock_mode = val; + break; + case VLOCK_DIS_CNT_LIMIT: + vlock_dis_cnt_limit = val; + break; + case VLOCK_DELTA_LIMIT_FRAC: + vlock_delta_limit_frac = val; + break; + case VLOCK_DELTA_LIMIT_M: + vlock_delta_limit_m = val; + break; + case VLOCK_DEBUG: + vlock_debug = val; + break; + case VLOCK_DYNAMIC_ADJUST: + vlock_dynamic_adjust = val; + break; + case VLOCK_DIS_CNT_STEP1_LIMIT: + vlock_dis_cnt_step1_limit = val; + break; + case VLOCK_EN_CNT_STEP1_LIMIT: + vlock_en_cnt_step1_limit = val; + break; + default: + pr_info("%s:unknown vlock param:%d\n", __func__, sel); + break; + } + +} +void vlock_status(void) +{ + pr_info("\n current vlock parameters status:\n"); + pr_info("vlock_mode:%d\n", vlock_mode); + pr_info("vlock_en:%d\n", vlock_en); + pr_info("vlock_adapt:%d\n", vlock_adapt); + pr_info("vlock_dis_cnt_limit:%d\n", vlock_dis_cnt_limit); + pr_info("vlock_delta_limit_frac:%d\n", vlock_delta_limit_frac); + pr_info("vlock_delta_limit_m:%d\n", vlock_delta_limit_m); + pr_info("vlock_debug:0x%x\n", vlock_debug); + pr_info("vlock_dynamic_adjust:%d\n", vlock_dynamic_adjust); + pr_info("vlock_state:%d\n", vlock_state); + pr_info("vlock_sync_limit_flag:%d\n", vlock_sync_limit_flag); + pr_info("pre_vmode:%d\n", pre_vmode); + pr_info("pre_hiu_reg_m:0x%x\n", pre_hiu_reg_m); + pr_info("pre_hiu_reg_frac:0x%x\n", pre_hiu_reg_frac); + pr_info("vlock_dis_cnt:%d\n", vlock_dis_cnt); + pr_info("pre_vout_mode:%s\n", pre_vout_mode); + pr_info("vlock_dis_cnt_step1:%d\n", vlock_dis_cnt_step1); + pr_info("vlock_dis_cnt_step1_limit:%d\n", vlock_dis_cnt_step1_limit); + pr_info("vlock_en_cnt_step1_limit:%d\n", vlock_en_cnt_step1_limit); +} +void vlock_reg_dump(void) +{ + unsigned int addr; + + pr_info("----dump vlock reg----\n"); + for (addr = (0x3000); addr <= (0x3020); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); +} +/*video lock end*/ + +/* sharpness process begin */ +void sharpness_process(struct vframe_s *vf) +{ +} +/* sharpness process end */ + +/*for gxbbtv rgb contrast adj in vd1 matrix */ +void vpp_vd1_mtx_rgb_contrast(signed int cont_val, struct vframe_s *vf) +{ + unsigned int vd1_contrast; + unsigned int con_minus_value, rgb_con_en; + + if ((cont_val > 1023) || (cont_val < -1024)) + return; + cont_val = cont_val + 1024; + /*close rgb contrast protect*/ + WRITE_VPP_REG_BITS(XVYCC_VD1_RGB_CTRST, 0, 0, 1); + /*VPP_VADJ_CTRL bit 1 on for rgb contrast adj*/ + rgb_con_en = READ_VPP_REG_BITS(XVYCC_VD1_RGB_CTRST, 1, 1); + if (!rgb_con_en) + WRITE_VPP_REG_BITS(XVYCC_VD1_RGB_CTRST, 1, 1, 1); + + /*select full or limit range setting*/ + con_minus_value = READ_VPP_REG_BITS(XVYCC_VD1_RGB_CTRST, 4, 10); + if (vf->source_type == VFRAME_SOURCE_TYPE_OTHERS) { + if (con_minus_value != 64) + WRITE_VPP_REG_BITS(XVYCC_VD1_RGB_CTRST, 64, 4, 10); + } else { + if (con_minus_value != 0) + WRITE_VPP_REG_BITS(XVYCC_VD1_RGB_CTRST, 0, 4, 10); + } + + vd1_contrast = (READ_VPP_REG(XVYCC_VD1_RGB_CTRST) & 0xf000ffff) | + (cont_val << 16); + + WRITE_VPP_REG(XVYCC_VD1_RGB_CTRST, vd1_contrast); +} + +/*for gxbbtv contrast adj in vadj1*/ +void vpp_vd_adj1_contrast(signed int cont_val, struct vframe_s *vf) +{ + unsigned int vd1_contrast; + unsigned int vdj1_ctl; + + if ((cont_val > 1023) || (cont_val < -1024)) + return; + cont_val = ((cont_val + 1024) >> 3); + /*VPP_VADJ_CTRL bit 1 off for contrast adj*/ + vdj1_ctl = READ_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 1); + if (is_meson_gxtvbb_cpu()) { + if (vf->source_type == VFRAME_SOURCE_TYPE_OTHERS) { + if (!vdj1_ctl) + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 1, 1); + } else { + if (vdj1_ctl) + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 0, 1, 1); + } + } + if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) { + vd1_contrast = (READ_VPP_REG(VPP_VADJ1_Y) & 0x3ff00) | + (cont_val << 0); + } else { + vd1_contrast = (READ_VPP_REG(VPP_VADJ1_Y) & 0x1ff00) | + (cont_val << 0); + } + WRITE_VPP_REG(VPP_VADJ1_Y, vd1_contrast); +} + +void vpp_vd_adj1_brightness(signed int bri_val, struct vframe_s *vf) +{ + signed int vd1_brightness; + + signed int ao0 = -64; + signed int ao1 = -512; + signed int ao2 = -512; + unsigned int a01 = 0, a_2 = 0; + /* enable vd0_csc */ + + unsigned int ori = READ_VPP_REG(VPP_MATRIX_CTRL) | 0x00000020; + /* point to vd0_csc */ + unsigned int ctl = (ori & 0xfffffcff) | 0x00000100; + + if (bri_val > 1023 || bri_val < -1024) + return; + + if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) { + bri_val = bri_val >> 1; + vd1_brightness = (READ_VPP_REG(VPP_VADJ1_Y) & 0xff) | + (bri_val << 8); + + WRITE_VPP_REG(VPP_VADJ1_Y, vd1_brightness); + } else { + if ((vf->source_type == VFRAME_SOURCE_TYPE_TUNER) || + (vf->source_type == VFRAME_SOURCE_TYPE_CVBS) || + (vf->source_type == VFRAME_SOURCE_TYPE_COMP)) + vd1_brightness = bri_val; + else if (vf->source_type == VFRAME_SOURCE_TYPE_HDMI) { + if ((((vf->signal_type >> 29) & 0x1) == 1) && + (((vf->signal_type >> 16) & 0xff) == 9)) { + bri_val += ao0; + if (bri_val < -1024) + bri_val = -1024; + vd1_brightness = bri_val; + } else + vd1_brightness = bri_val; + } else { + bri_val += ao0; + if (bri_val < -1024) + bri_val = -1024; + vd1_brightness = bri_val; + } + + a01 = ((vd1_brightness << 16) & 0x0fff0000) | + ((ao1 << 0) & 0x00000fff); + a_2 = ((ao2 << 0) & 0x00000fff); + /*p01 = ((po0 << 16) & 0x0fff0000) |*/ + /*((po1 << 0) & 0x00000fff);*/ + /*p_2 = ((po2 << 0) & 0x00000fff);*/ + + WRITE_VPP_REG(VPP_MATRIX_CTRL, ctl); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, a01); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, a_2); + WRITE_VPP_REG(VPP_MATRIX_CTRL, ori); + } +} + + +/* brightness/contrast adjust process begin */ +static void vd1_brightness_contrast(signed int brightness, + signed int contrast) +{ + signed int ao0 = -64, g00 = 1024, g01 = 0, g02 = 0, po0 = 64; + signed int ao1 = -512, g10 = 0, g11 = 1024, g12 = 0, po1 = 512; + signed int ao2 = -512, g20 = 0, g21 = 0, g22 = 1024, po2 = 512; + unsigned int gc0 = 0, gc1 = 0, gc2 = 0, gc3 = 0, gc4 = 0; + unsigned int a01 = 0, a_2 = 0, p01 = 0, p_2 = 0; + /* enable vd0_csc */ + unsigned int ori = READ_VPP_REG(VPP_MATRIX_CTRL) | 0x00000020; + /* point to vd0_csc */ + unsigned int ctl = (ori & 0xfffffcff) | 0x00000100; + + po0 += brightness >> 1; + if (po0 > 1023) + po0 = 1023; + if (po0 < -1024) + po0 = -1024; + g00 *= contrast + 2048; + g00 >>= 11; + if (g00 > 4095) + g00 = 4095; + if (g00 < -4096) + g00 = -4096; + if (contrast < 0) { + g11 *= contrast + 2048; + g11 >>= 11; + } + if (brightness < 0) { + g11 += brightness >> 1; + if (g11 > 4095) + g11 = 4095; + if (g11 < -4096) + g11 = -4096; + } + if (contrast < 0) { + g22 *= contrast + 2048; + g22 >>= 11; + } + if (brightness < 0) { + g22 += brightness >> 1; + if (g22 > 4095) + g22 = 4095; + if (g22 < -4096) + g22 = -4096; + } + gc0 = ((g00 << 16) & 0x1fff0000) | ((g01 << 0) & 0x00001fff); + gc1 = ((g02 << 16) & 0x1fff0000) | ((g10 << 0) & 0x00001fff); + gc2 = ((g11 << 16) & 0x1fff0000) | ((g12 << 0) & 0x00001fff); + gc3 = ((g20 << 16) & 0x1fff0000) | ((g21 << 0) & 0x00001fff); + gc4 = ((g22 << 0) & 0x00001fff); + /* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESONG9TV) */ + if (is_meson_gxtvbb_cpu()) { + a01 = ((ao0 << 16) & 0x0fff0000) | + ((ao1 << 0) & 0x00000fff); + a_2 = ((ao2 << 0) & 0x00000fff); + p01 = ((po0 << 16) & 0x0fff0000) | + ((po1 << 0) & 0x00000fff); + p_2 = ((po2 << 0) & 0x00000fff); + } else { + /* #else */ + a01 = ((ao0 << 16) & 0x07ff0000) | + ((ao1 << 0) & 0x000007ff); + a_2 = ((ao2 << 0) & 0x000007ff); + p01 = ((po0 << 16) & 0x07ff0000) | + ((po1 << 0) & 0x000007ff); + p_2 = ((po2 << 0) & 0x000007ff); + } + /* #endif */ + WRITE_VPP_REG(VPP_MATRIX_CTRL, ctl); + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, gc0); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, gc1); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, gc2); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, gc3); + WRITE_VPP_REG(VPP_MATRIX_COEF22, gc4); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, a01); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, a_2); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, p01); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, p_2); + WRITE_VPP_REG(VPP_MATRIX_CTRL, ori); +} + +void amvecm_bricon_process(signed int bri_val, + signed int cont_val, struct vframe_s *vf) +{ + if (vecm_latch_flag & FLAG_VADJ1_BRI) { + vecm_latch_flag &= ~FLAG_VADJ1_BRI; + vpp_vd_adj1_brightness(bri_val, vf); + pr_amve_dbg("\n[amve..] set vd1_brightness OK!!!\n"); + if (dnlp_debug&0x100) + pr_info("\n[amve..]%s :brightness:%d!!!\n", + __func__, bri_val); + } + + if (vecm_latch_flag & FLAG_VADJ1_CON) { + vecm_latch_flag &= ~FLAG_VADJ1_CON; + if (contrast_adj_sel) + vpp_vd1_mtx_rgb_contrast(cont_val, vf); + else + vpp_vd_adj1_contrast(cont_val, vf); + pr_amve_dbg("\n[amve..] set vd1_contrast OK!!!\n"); + if (dnlp_debug&0x100) + pr_info("\n[amve..]%s :contrast:%d!!!\n", + __func__, cont_val); + } + + if (0) { /* vecm_latch_flag & FLAG_BRI_CON) { */ + vecm_latch_flag &= ~FLAG_BRI_CON; + vd1_brightness_contrast(bri_val, cont_val); + pr_amve_dbg("\n[amve..] set vd1_brightness_contrast OK!!!\n"); + } +} +/* brightness/contrast adjust process end */ + +void amvecm_color_process(signed int sat_val, + signed int hue_val, struct vframe_s *vf) +{ + if (vecm_latch_flag & FLAG_VADJ1_COLOR) { + vecm_latch_flag &= ~FLAG_VADJ1_COLOR; + vpp_vd_adj1_saturation_hue(sat_val, hue_val, vf); + if (dnlp_debug&0x100) + pr_info("\n[amve..]%s :saturation:%d,hue:%d!!!\n", + __func__, sat_val, hue_val); + } +} +/* saturation/hue adjust process end */ + +/* 3d process begin */ +void amvecm_3d_black_process(void) +{ + if (vecm_latch_flag & FLAG_3D_BLACK_DIS) { + /* disable reg_3dsync_enable */ + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, 0, 31, 1); + WRITE_VPP_REG_BITS(VIU_MISC_CTRL0, 0, 8, 1); + WRITE_VPP_REG_BITS(VPP_BLEND_ONECOLOR_CTRL, 0, 26, 1); + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, 0, 13, 1); + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC2, 0, 31, 1); + vecm_latch_flag &= ~FLAG_3D_BLACK_DIS; + } + if (vecm_latch_flag & FLAG_3D_BLACK_EN) { + WRITE_VPP_REG_BITS(VIU_MISC_CTRL0, 1, 8, 1); + WRITE_VPP_REG_BITS(VPP_BLEND_ONECOLOR_CTRL, 1, 26, 1); + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC2, 1, 31, 1); + WRITE_VPP_REG_BITS(VPP_BLEND_ONECOLOR_CTRL, + sync_3d_black_color&0xffffff, 0, 24); + if (sync_3d_sync_to_vbo) + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, 1, 13, 1); + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, 1, 31, 1); + vecm_latch_flag &= ~FLAG_3D_BLACK_EN; + } +} +void amvecm_3d_sync_process(void) +{ + + if (vecm_latch_flag & FLAG_3D_SYNC_DIS) { + /* disable reg_3dsync_enable */ + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, 0, 31, 1); + vecm_latch_flag &= ~FLAG_3D_SYNC_DIS; + } + if (vecm_latch_flag & FLAG_3D_SYNC_EN) { + /*select vpu pwm source clock*/ + switch (READ_VPP_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 0, 2)) { + case 0:/* ENCL */ + WRITE_VPP_REG_BITS(VPU_VPU_PWM_V0, 0, 29, 2); + break; + case 1:/* ENCI */ + WRITE_VPP_REG_BITS(VPU_VPU_PWM_V0, 1, 29, 2); + break; + case 2:/* ENCP */ + WRITE_VPP_REG_BITS(VPU_VPU_PWM_V0, 2, 29, 2); + break; + case 3:/* ENCT */ + WRITE_VPP_REG_BITS(VPU_VPU_PWM_V0, 3, 29, 2); + break; + default: + break; + } + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC2, sync_3d_h_start, 0, 13); + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC2, sync_3d_h_end, 16, 13); + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, sync_3d_v_start, 0, 13); + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, sync_3d_v_end, 16, 13); + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, sync_3d_polarity, 29, 1); + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, sync_3d_out_inv, 15, 1); + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, 1, 31, 1); + vecm_latch_flag &= ~FLAG_3D_SYNC_EN; + } +} +/* 3d process end */ + diff --git a/drivers/amlogic/media/enhancement/amvecm/amve.h b/drivers/amlogic/media/enhancement/amvecm/amve.h new file mode 100644 index 0000000..6f7f8b5 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/amve.h @@ -0,0 +1,175 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amve.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __AM_VE_H +#define __AM_VE_H + +#include +#include + +/* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8) */ +/* #define WRITE_VPP_REG(x,val) */ +/* WRITE_VCBUS_REG(x,val) */ +/* #define WRITE_VPP_REG_BITS(x,val,start,length) */ +/* WRITE_VCBUS_REG_BITS(x,val,start,length) */ +/* #define READ_VPP_REG(x) */ +/* READ_VCBUS_REG(x) */ +/* #define READ_VPP_REG_BITS(x,start,length) */ +/* READ_VCBUS_REG_BITS(x,start,length) */ +/* #else */ +/* #define WRITE_VPP_REG(x,val) */ +/* WRITE_CBUS_REG(x,val) */ +/* #define WRITE_VPP_REG_BITS(x,val,start,length) */ +/* WRITE_CBUS_REG_BITS(x,val,start,length) */ +/* #define READ_VPP_REG(x) */ +/* READ_CBUS_REG(x) */ +/* #define READ_VPP_REG_BITS(x,start,length) */ +/* READ_CBUS_REG_BITS(x,start,length) */ +/* #endif */ + + +struct ve_regs_s { + unsigned int val:32; + unsigned int reg:14; + unsigned int port:2; + /* 0 NA NA direct access */ + /* 1 VPP_CHROMA_ADDR_PORT */ + /* VPP_CHROMA_DATA_PORT CM port registers */ + /* 2 NA NA reserved */ + /* 3 NA NA reserved */ + unsigned int bit:5; + unsigned int wid:5; + unsigned int mode:1; + unsigned int rsv:5; +}; +enum vlock_param_e { + VLOCK_EN = 0x0, + VLOCK_ADAPT, + VLOCK_MODE, + VLOCK_DIS_CNT_LIMIT, + VLOCK_DELTA_LIMIT_FRAC, + VLOCK_DELTA_LIMIT_M, + VLOCK_DEBUG, + VLOCK_DYNAMIC_ADJUST, + VLOCK_STATE, + VLOCK_SYNC_LIMIT_FLAG, + VLOCK_DIS_CNT_STEP1_LIMIT, + VLOCK_EN_CNT_STEP1_LIMIT, + VLOCK_PARAM_MAX, +}; + +extern struct ve_hist_s video_ve_hist; +extern unsigned int ve_size; +extern struct ve_dnlp_s am_ve_dnlp; +extern struct ve_dnlp_table_s am_ve_new_dnlp; +extern struct tcon_gamma_table_s video_gamma_table_r; +extern struct tcon_gamma_table_s video_gamma_table_g; +extern struct tcon_gamma_table_s video_gamma_table_b; +extern struct tcon_gamma_table_s video_gamma_table_r_adj; +extern struct tcon_gamma_table_s video_gamma_table_g_adj; +extern struct tcon_gamma_table_s video_gamma_table_b_adj; +extern struct tcon_rgb_ogo_s video_rgb_ogo; + +extern spinlock_t vpp_lcd_gamma_lock; + +void ve_on_vs(struct vframe_s *vf); + +void ve_set_bext(struct ve_bext_s *p); +void ve_set_dnlp(struct ve_dnlp_s *p); +void ve_set_new_dnlp(struct ve_dnlp_table_s *p); +void ve_set_dnlp_2(void); +void ve_set_hsvs(struct ve_hsvs_s *p); +void ve_set_ccor(struct ve_ccor_s *p); +void ve_set_benh(struct ve_benh_s *p); +void ve_set_demo(struct ve_demo_s *p); +void ve_set_regs(struct ve_regs_s *p); +void ve_set_regmap(struct ve_regmap_s *p); + +extern void ve_enable_dnlp(void); +extern void ve_disable_dnlp(void); + +extern void vpp_enable_lcd_gamma_table(void); +extern void vpp_disable_lcd_gamma_table(void); +extern void vpp_set_lcd_gamma_table(u16 *data, u32 rgb_mask); +extern void init_write_gamma_table(u16 *data, u32 rgb_mask); +extern void vpp_set_rgb_ogo(struct tcon_rgb_ogo_s *p); +extern void vpp_phase_lock_on_vs(unsigned int cycle, + unsigned int stamp, + bool lock50, + unsigned int range_fast, + unsigned int range_slow); +/* #if (MESON_CPU_TYPE>=MESON_CPU_TYPE_MESON6TVD) */ +extern void ve_frame_size_patch(unsigned int width, unsigned int height); +/* #endif */ +extern void ve_dnlp_latch_process(void); +extern void ve_lcd_gamma_process(void); +extern void lvds_freq_process(void); +extern void ve_dnlp_param_update(void); +extern void ve_new_dnlp_param_update(void); +extern void ve_ogo_param_update(void); +extern void am_set_regmap(struct am_regs_s *p); +extern void sharpness_process(struct vframe_s *vf); +extern void amvecm_bricon_process(signed int bri_val, + signed int cont_val, struct vframe_s *vf); +extern void amvecm_color_process(signed int sat_val, + signed int hue_val, struct vframe_s *vf); +extern void amvecm_3d_black_process(void); +extern void amvecm_3d_sync_process(void); +extern void amve_vlock_process(struct vframe_s *vf); +extern void amve_vlock_resume(void); +extern void vlock_param_set(unsigned int val, enum vlock_param_e sel); +extern void vlock_status(void); +extern void vlock_reg_dump(void); + +int amvecm_hiu_reg_read(unsigned int reg, unsigned int *val); +int amvecm_hiu_reg_write(unsigned int reg, unsigned int val); +extern unsigned int vecm_latch_flag; +extern unsigned int cm_size; +extern unsigned int sync_3d_h_start; +extern unsigned int sync_3d_h_end; +extern unsigned int sync_3d_v_start; +extern unsigned int sync_3d_v_end; +extern unsigned int sync_3d_polarity; +extern unsigned int sync_3d_out_inv; +extern unsigned int sync_3d_black_color; +extern unsigned int sync_3d_sync_to_vbo; + +extern void __iomem *amvecm_hiu_reg_base; + +#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA +#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val) +#define VSYNC_RD_MPEG_REG(adr) READ_VPP_REG(adr) +#else +extern u32 VSYNC_RD_MPEG_REG(u32 adr); +extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val); +#endif + +/* #if defined(CONFIG_ARCH_MESON2) */ +/* unsigned long long ve_get_vs_cnt(void); */ +/* #endif */ + +#define VLOCK_STATE_NULL 0 +#define VLOCK_STATE_ENABLE_STEP1_DONE 1 +#define VLOCK_STATE_ENABLE_STEP2_DONE 2 +#define VLOCK_STATE_DISABLE_STEP1_DONE 3 +#define VLOCK_STATE_DISABLE_STEP2_DONE 4 +#define VLOCK_STATE_ENABLE_FORCE_RESET 5 +#define VLOCK_STATE_ENABLE_STEP1 6 +#define VLOCK_STATE_DISABLE_STEP1 7 + +#endif + diff --git a/drivers/amlogic/media/enhancement/amvecm/amve_gamma_table.h b/drivers/amlogic/media/enhancement/amvecm/amve_gamma_table.h new file mode 100644 index 0000000..82897c1 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/amve_gamma_table.h @@ -0,0 +1,87 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amve_gamma_table.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __AM_VE_GAMMATABLE_H +#define __AM_VE_GAMMATABLE_H + +/* #include */ + +struct tcon_gamma_table_s video_curve_2d2_inv = { + { + 0, 82, 113, 136, 155, 171, 186, 199, 212, 223, + 234, 245, 255, 264, 273, 282, 290, 298, 306, 314, + 321, 328, 335, 342, 349, 356, 362, 368, 374, 380, + 386, 392, 398, 403, 409, 414, 420, 425, 430, 435, + 440, 445, 450, 455, 460, 464, 469, 474, 478, 483, + 487, 492, 496, 500, 505, 509, 513, 517, 521, 525, + 529, 533, 537, 541, 545, 549, 553, 556, 560, 564, + 568, 571, 575, 579, 582, 586, 589, 593, 596, 600, + 603, 607, 610, 613, 617, 620, 623, 627, 630, 633, + 636, 640, 643, 646, 649, 652, 655, 658, 661, 665, + 668, 671, 674, 677, 680, 683, 686, 688, 691, 694, + 697, 700, 703, 706, 709, 711, 714, 717, 720, 723, + 725, 728, 731, 733, 736, 739, 742, 744, 747, 750, + 752, 755, 757, 760, 763, 765, 768, 770, 773, 775, + 778, 780, 783, 785, 788, 790, 793, 795, 798, 800, + 803, 805, 808, 810, 812, 815, 817, 820, 822, 824, + 827, 829, 831, 834, 836, 838, 841, 843, 845, 847, + 850, 852, 854, 856, 859, 861, 863, 865, 868, 870, + 872, 874, 876, 879, 881, 883, 885, 887, 889, 892, + 894, 896, 898, 900, 902, 904, 906, 909, 911, 913, + 915, 917, 919, 921, 923, 925, 927, 929, 931, 933, + 935, 937, 939, 941, 943, 945, 947, 949, 951, 953, + 955, 957, 959, 961, 963, 965, 967, 969, 971, 973, + 975, 977, 979, 981, 982, 984, 986, 988, 990, 992, + 994, 996, 998, 999, 1001, 1003, 1005, 1007, 1009, 1011, + 1012, 1014, 1016, 1018, 1020, 1022, + }, +}; + +struct tcon_gamma_table_s video_curve_2d2 = { + { + 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, + 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, + 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, + 28, 29, 31, 32, 33, 35, 36, 38, 39, 41, + 42, 44, 45, 47, 49, 50, 52, 54, 55, 57, + 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, + 79, 82, 84, 86, 88, 91, 93, 95, 98, 100, + 103, 105, 108, 110, 113, 116, 118, 121, 124, 127, + 130, 132, 135, 138, 141, 144, 147, 150, 154, 157, + 160, 163, 166, 170, 173, 176, 180, 183, 187, 190, + 194, 197, 201, 204, 208, 212, 216, 219, 223, 227, + 231, 235, 239, 243, 247, 251, 255, 259, 263, 267, + 272, 276, 280, 285, 289, 294, 298, 303, 307, 312, + 316, 321, 326, 330, 335, 340, 345, 350, 355, 360, + 365, 370, 375, 380, 385, 390, 395, 401, 406, 411, + 417, 422, 427, 433, 438, 444, 450, 455, 461, 467, + 472, 478, 484, 490, 496, 502, 508, 514, 520, 526, + 532, 538, 544, 551, 557, 563, 570, 576, 583, 589, + 596, 602, 609, 615, 622, 629, 636, 642, 649, 656, + 663, 670, 677, 684, 691, 698, 705, 713, 720, 727, + 735, 742, 749, 757, 764, 772, 779, 787, 795, 802, + 810, 818, 826, 833, 841, 849, 857, 865, 873, 881, + 889, 898, 906, 914, 922, 931, 939, 948, 956, 965, + 973, 982, 990, 999, 1008, 1016, + }, +}; + + +#endif + diff --git a/drivers/amlogic/media/enhancement/amvecm/amvecm.c b/drivers/amlogic/media/enhancement/amvecm/amvecm.c new file mode 100644 index 0000000..23ea3a2 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/amvecm.c @@ -0,0 +1,3124 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amvecm.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/* Standard Linux headers */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/* #include */ +#include /* for parse_para_pq */ +#include +#include +#include +#include +#include + +#ifdef CONFIG_AML_LCD +#include +#endif + +#include "arch/vpp_regs.h" +#include "arch/ve_regs.h" +#include "arch/cm_regs.h" +#include "../../vin/tvin/tvin_global.h" + +#include "amve.h" +#include "amcm.h" +#include "amcsc.h" + +#define pr_amvecm_dbg(fmt, args...)\ + do {\ + if (debug_amvecm)\ + pr_info("AMVECM: " fmt, ## args);\ + } while (0) +#define pr_amvecm_error(fmt, args...)\ + pr_error("AMVECM: " fmt, ## args) + +#define AMVECM_NAME "amvecm" +#define AMVECM_DRIVER_NAME "amvecm" +#define AMVECM_MODULE_NAME "amvecm" +#define AMVECM_DEVICE_NAME "amvecm" +#define AMVECM_CLASS_NAME "amvecm" + +struct amvecm_dev_s { + dev_t devt; + struct cdev cdev; + dev_t devno; + struct device *dev; + struct class *clsp; +}; + +static struct amvecm_dev_s amvecm_dev; + +spinlock_t vpp_lcd_gamma_lock; + +signed int vd1_brightness = 0, vd1_contrast; + +static int hue_pre; /*-25~25*/ +static int saturation_pre; /*-128~127*/ +static int hue_post; /*-25~25*/ +static int saturation_post; /*-128~127*/ +/*contrast add saturation add*/ +static int satu_shift_by_con; /*-128~127*/ + +static s16 saturation_ma; +static s16 saturation_mb; +static s16 saturation_ma_shift; +static s16 saturation_mb_shift; + +unsigned int sr1_reg_val[101]; +unsigned int sr1_ret_val[101]; +struct vpp_hist_param_s vpp_hist_param; +static unsigned int pre_hist_height, pre_hist_width; +static unsigned int pc_mode = 0xff; +static unsigned int pc_mode_last = 0xff; +static struct hdr_metadata_info_s vpp_hdr_metadata_s; + +void __iomem *amvecm_hiu_reg_base;/* = *ioremap(0xc883c000, 0x2000); */ + +#define HIU_REG_BASE 0xc883c000 + +static bool debug_amvecm; +module_param(debug_amvecm, bool, 0664); +MODULE_PARM_DESC(debug_amvecm, "\n debug_amvecm\n"); + +unsigned int vecm_latch_flag; +module_param(vecm_latch_flag, uint, 0664); +MODULE_PARM_DESC(vecm_latch_flag, "\n vecm_latch_flag\n"); + +unsigned int vpp_demo_latch_flag; +module_param(vpp_demo_latch_flag, uint, 0664); +MODULE_PARM_DESC(vpp_demo_latch_flag, "\n vpp_demo_latch_flag\n"); + +unsigned int pq_load_en = 1;/* load pq table enable/disable */ +module_param(pq_load_en, uint, 0664); +MODULE_PARM_DESC(pq_load_en, "\n pq_load_en\n"); + +bool gamma_en; /* wb_gamma_en enable/disable */ +module_param(gamma_en, bool, 0664); +MODULE_PARM_DESC(gamma_en, "\n gamma_en\n"); + +bool wb_en; /* wb_en enable/disable */ +module_param(wb_en, bool, 0664); +MODULE_PARM_DESC(wb_en, "\n wb_en\n"); + +unsigned int probe_ok;/* probe ok or not */ +module_param(probe_ok, uint, 0664); +MODULE_PARM_DESC(probe_ok, "\n probe_ok\n"); + +static unsigned int sr1_index;/* for sr1 read */ +module_param(sr1_index, uint, 0664); +MODULE_PARM_DESC(sr1_index, "\n sr1_index\n"); + + +/* vpp brightness/contrast/saturation/hue */ +static int __init amvecm_load_pq_val(char *str) +{ + int i = 0, err = 0; + char *tk = NULL, *tmp[4]; + long val; + + if (str == NULL) { + pr_err("[amvecm] pq val error !!!\n"); + return 0; + } + + for (tk = strsep(&str, ","); tk != NULL; tk = strsep(&str, ",")) { + tmp[i] = tk; + err = kstrtol(tmp[i], 10, &val); + if (err) { + pr_err("[amvecm] pq string error !!!\n"); + break; + } + /* pr_err("[amvecm] pq[%d]: %d\n", i, (int)val[i]); */ + + /* only need to get sat/hue value,*/ + /*brightness/contrast can be got from registers */ + if (i == 2) + saturation_post = (int)val; + else if (i == 3) + hue_post = (int)val; + i++; + } + + return 0; +} +__setup("pq=", amvecm_load_pq_val); + + +static void amvecm_size_patch(void) +{ + unsigned int hs, he, vs, ve; + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + hs = READ_VPP_REG_BITS(VPP_HSC_REGION12_STARTP, 16, 13); + he = READ_VPP_REG_BITS(VPP_HSC_REGION4_ENDP, 0, 13); + + vs = READ_VPP_REG_BITS(VPP_VSC_REGION12_STARTP, 16, 13); + ve = READ_VPP_REG_BITS(VPP_VSC_REGION4_ENDP, 0, 13); + ve_frame_size_patch(he-hs+1, ve-vs+1); + } + hs = READ_VPP_REG_BITS(VPP_POSTBLEND_VD1_H_START_END, 16, 13); + he = READ_VPP_REG_BITS(VPP_POSTBLEND_VD1_H_START_END, 0, 13); + + vs = READ_VPP_REG_BITS(VPP_POSTBLEND_VD1_V_START_END, 16, 13); + ve = READ_VPP_REG_BITS(VPP_POSTBLEND_VD1_V_START_END, 0, 13); + cm2_frame_size_patch(he-hs+1, ve-vs+1); +} + +/* video adj1 */ +static ssize_t video_adj1_brightness_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + s32 val = 0; + + if (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB) { + val = (READ_VPP_REG(VPP_VADJ1_Y) >> 8) & 0x1ff; + val = (val << 23) >> 23; + + return sprintf(buf, "%d\n", val); + } + val = (READ_VPP_REG(VPP_VADJ1_Y) >> 8) & 0x3ff; + val = (val << 23) >> 23; + + return sprintf(buf, "%d\n", val >> 1); +} + +static ssize_t video_adj1_brightness_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + int val; + + r = sscanf(buf, "%d\n", &val); + if ((r != 1) || (val < -255) || (val > 255)) + return -EINVAL; + + if (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB) + WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val, 8, 9); + else + WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val << 1, 8, 10); + + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); + + return count; +} + +static ssize_t video_adj1_contrast_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", + (int)(READ_VPP_REG(VPP_VADJ1_Y) & 0xff) - 0x80); +} + +static ssize_t video_adj1_contrast_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + int val; + + r = sscanf(buf, "%d\n", &val); + if ((r != 1) || (val < -127) || (val > 127)) + return -EINVAL; + + val += 0x80; + + WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val, 0, 8); + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); + + return count; +} + +/* video adj2 */ +static ssize_t video_adj2_brightness_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + s32 val = 0; + + if (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB) { + val = (READ_VPP_REG(VPP_VADJ2_Y) >> 8) & 0x1ff; + val = (val << 23) >> 23; + + return sprintf(buf, "%d\n", val); + } + val = (READ_VPP_REG(VPP_VADJ2_Y) >> 8) & 0x3ff; + val = (val << 23) >> 23; + + return sprintf(buf, "%d\n", val >> 1); +} + +static ssize_t video_adj2_brightness_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + int val; + + r = sscanf(buf, "%d\n", &val); + if ((r != 1) || (val < -255) || (val > 255)) + return -EINVAL; + + if (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB) + WRITE_VPP_REG_BITS(VPP_VADJ2_Y, val, 8, 9); + else + WRITE_VPP_REG_BITS(VPP_VADJ2_Y, val << 1, 8, 10); + + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1); + + return count; +} + +static ssize_t video_adj2_contrast_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", + (int)(READ_VPP_REG(VPP_VADJ2_Y) & 0xff) - 0x80); +} + +static ssize_t video_adj2_contrast_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + int val; + + r = sscanf(buf, "%d\n", &val); + if ((r != 1) || (val < -127) || (val > 127)) + return -EINVAL; + + val += 0x80; + + WRITE_VPP_REG_BITS(VPP_VADJ2_Y, val, 0, 8); + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1); + + return count; +} + +static ssize_t amvecm_usage_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + pr_info("Usage:"); + pr_info("brightness_val range:-255~255\n"); + pr_info("contrast_val range:-127~127\n"); + pr_info("saturation_val range:-128~128\n"); + pr_info("hue_val range:-25~25\n"); + pr_info("************video brightness & contrast & saturation_hue adj as flow*************\n"); + pr_info("echo brightness_val > /sys/class/amvecm/brightness1\n"); + pr_info("echo contrast_val > /sys/class/amvecm/contrast1\n"); + pr_info("echo saturation_val hue_val > /sys/class/amvecm/saturation_hue_pre\n"); + pr_info("************after video+osd blender, brightness & contrast & saturation_hue adj as flow*************\n"); + pr_info("echo brightness_val > /sys/class/amvecm/brightness2\n"); + pr_info("echo contrast_val > /sys/class/amvecm/contrast2\n"); + pr_info("echo saturation_val hue_val > /sys/class/amvecm/saturation_hue_post\n"); + return 0; +} + +static void parse_param_amvecm(char *buf_orig, char **parm) +{ + char *ps, *token; + unsigned int n = 0; + char delim1[3] = " "; + char delim2[2] = "\n"; + + ps = buf_orig; + strcat(delim1, delim2); + while (1) { + token = strsep(&ps, delim1); + if (token == NULL) + break; + if (*token == '\0') + continue; + parm[n++] = token; + } +} +static void amvecm_3d_sync_status(void) +{ + unsigned int sync_h_start, sync_h_end, sync_v_start, + sync_v_end, sync_polarity, + sync_out_inv, sync_en; + if (!is_meson_gxtvbb_cpu()) { + pr_info("\n chip does not support 3D sync process!!!\n"); + return; + } + sync_h_start = READ_VPP_REG_BITS(VPU_VPU_3D_SYNC2, 0, 13); + sync_h_end = READ_VPP_REG_BITS(VPU_VPU_3D_SYNC2, 16, 13); + sync_v_start = READ_VPP_REG_BITS(VPU_VPU_3D_SYNC1, 0, 13); + sync_v_end = READ_VPP_REG_BITS(VPU_VPU_3D_SYNC1, 16, 13); + sync_polarity = READ_VPP_REG_BITS(VPU_VPU_3D_SYNC1, 29, 1); + sync_out_inv = READ_VPP_REG_BITS(VPU_VPU_3D_SYNC1, 15, 1); + sync_en = READ_VPP_REG_BITS(VPU_VPU_3D_SYNC1, 31, 1); + pr_info("\n current 3d sync state:\n"); + pr_info("sync_h_start:%d\n", sync_h_start); + pr_info("sync_h_end:%d\n", sync_h_end); + pr_info("sync_v_start:%d\n", sync_v_start); + pr_info("sync_v_end:%d\n", sync_v_end); + pr_info("sync_polarity:%d\n", sync_polarity); + pr_info("sync_out_inv:%d\n", sync_out_inv); + pr_info("sync_en:%d\n", sync_en); + pr_info("sync_3d_black_color:%d\n", sync_3d_black_color); + pr_info("sync_3d_sync_to_vbo:%d\n", sync_3d_sync_to_vbo); +} +static ssize_t amvecm_3d_sync_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + ssize_t len = 0; + + len += sprintf(buf+len, + "echo hstart val(D) > /sys/class/amvecm/sync_3d\n"); + len += sprintf(buf+len, + "echo hend val(D) > /sys/class/amvecm/sync_3d\n"); + len += sprintf(buf+len, + "echo vstart val(D) > /sys/class/amvecm/sync_3d\n"); + len += sprintf(buf+len, + "echo vend val(D) > /sys/class/amvecm/sync_3d\n"); + len += sprintf(buf+len, + "echo pola val(D) > /sys/class/amvecm/sync_3d\n"); + len += sprintf(buf+len, + "echo inv val(D) > /sys/class/amvecm/sync_3d\n"); + len += sprintf(buf+len, + "echo black_color val(Hex) > /sys/class/amvecm/sync_3d\n"); + len += sprintf(buf+len, + "echo sync_to_vx1 val(D) > /sys/class/amvecm/sync_3d\n"); + len += sprintf(buf+len, + "echo enable > /sys/class/amvecm/sync_3d\n"); + len += sprintf(buf+len, + "echo disable > /sys/class/amvecm/sync_3d\n"); + len += sprintf(buf+len, + "echo status > /sys/class/amvecm/sync_3d\n"); + return len; +} + +static ssize_t amvecm_3d_sync_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + char *buf_orig, *parm[8] = {NULL}; + long val; + + if (!buf) + return count; + + if (!is_meson_gxtvbb_cpu()) { + pr_info("\n chip does not support 3D sync process!!!\n"); + return count; + } + + buf_orig = kstrdup(buf, GFP_KERNEL); + parse_param_amvecm(buf_orig, (char **)&parm); + if (!strncmp(parm[0], "hstart", 6)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + sync_3d_h_start = val&0x1fff; + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC2, sync_3d_h_start, 0, 13); + } else if (!strncmp(parm[0], "hend", 4)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + sync_3d_h_end = val&0x1fff; + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC2, sync_3d_h_end, 16, 13); + } else if (!strncmp(parm[0], "vstart", 6)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + sync_3d_v_start = val&0x1fff; + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, sync_3d_v_start, 0, 13); + } else if (!strncmp(parm[0], "vend", 4)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + sync_3d_v_end = val&0x1fff; + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, sync_3d_v_end, 16, 13); + } else if (!strncmp(parm[0], "pola", 4)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + sync_3d_polarity = val&0x1; + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, sync_3d_polarity, 29, 1); + } else if (!strncmp(parm[0], "inv", 3)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + sync_3d_out_inv = val&0x1; + WRITE_VPP_REG_BITS(VPU_VPU_3D_SYNC1, sync_3d_out_inv, 15, 1); + } else if (!strncmp(parm[0], "black_color", 11)) { + if (kstrtol(parm[1], 16, &val) < 0) + return -EINVAL; + sync_3d_black_color = val&0xffffff; + WRITE_VPP_REG_BITS(VPP_BLEND_ONECOLOR_CTRL, + sync_3d_black_color, 0, 24); + } else if (!strncmp(parm[0], "sync_to_vx1", 11)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + sync_3d_sync_to_vbo = val&0x1; + } else if (!strncmp(parm[0], "enable", 6)) { + vecm_latch_flag |= FLAG_3D_SYNC_EN; + } else if (!strncmp(parm[0], "disable", 7)) { + vecm_latch_flag |= FLAG_3D_SYNC_DIS; + } else if (!strncmp(parm[0], "status", 7)) { + amvecm_3d_sync_status(); + } + kfree(buf_orig); + return count; +} + +static ssize_t amvecm_vlock_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + ssize_t len = 0; + + len += sprintf(buf+len, + "echo vlock_mode val(0/1/2) > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo vlock_en val(0/1) > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo vlock_adapt val(0/1) > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo vlock_dis_cnt_limit val(D) > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo vlock_delta_limit_frac val(D) > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo vlock_delta_limit_m val(D) > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo vlock_debug val(0x111) > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo vlock_dynamic_adjust val(0/1) > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo vlock_dis_cnt_step1_limit val(D) > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo vlock_cnt_step1_limit val(D) > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo enable > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo disable > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo status > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo dump_reg > /sys/class/amvecm/vlock\n"); + return len; +} + +static ssize_t amvecm_vlock_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + char *buf_orig, *parm[8] = {NULL}; + long val; + unsigned int temp_val; + enum vlock_param_e sel = VLOCK_PARAM_MAX; + + if (!buf) + return count; + if (!is_meson_gxtvbb_cpu() && + !is_meson_gxbb_cpu() && + (get_cpu_type() < MESON_CPU_MAJOR_ID_GXL)) { + pr_info("\n chip does not support vlock process!!!\n"); + return count; + } + + buf_orig = kstrdup(buf, GFP_KERNEL); + parse_param_amvecm(buf_orig, (char **)&parm); + if (!strncmp(parm[0], "vlock_mode", 10)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + temp_val = val; + sel = VLOCK_MODE; + } else if (!strncmp(parm[0], "vlock_en", 8)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + temp_val = val; + sel = VLOCK_EN; + } else if (!strncmp(parm[0], "vlock_adapt", 11)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + temp_val = val; + sel = VLOCK_ADAPT; + } else if (!strncmp(parm[0], "vlock_dis_cnt_limit", 19)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + temp_val = val; + sel = VLOCK_DIS_CNT_LIMIT; + } else if (!strncmp(parm[0], "vlock_delta_limit_frac", 22)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + temp_val = val; + sel = VLOCK_DELTA_LIMIT_FRAC; + } else if (!strncmp(parm[0], "vlock_delta_limit_m", 19)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + temp_val = val; + sel = VLOCK_DELTA_LIMIT_M; + } else if (!strncmp(parm[0], "vlock_debug", 11)) { + if (kstrtol(parm[1], 16, &val) < 0) + return -EINVAL; + temp_val = val; + sel = VLOCK_DEBUG; + } else if (!strncmp(parm[0], "vlock_dynamic_adjust", 20)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + temp_val = val; + sel = VLOCK_DYNAMIC_ADJUST; + } else if (!strncmp(parm[0], "vlock_dis_cnt_step1_limit", 25)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + temp_val = val; + sel = VLOCK_DIS_CNT_STEP1_LIMIT; + } else if (!strncmp(parm[0], "vlock_cnt_step1_limit", 21)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + temp_val = val; + sel = VLOCK_EN_CNT_STEP1_LIMIT; + } else if (!strncmp(parm[0], "enable", 6)) { + vecm_latch_flag |= FLAG_VLOCK_EN; + } else if (!strncmp(parm[0], "disable", 7)) { + vecm_latch_flag |= FLAG_VLOCK_DIS; + } else if (!strncmp(parm[0], "status", 6)) { + vlock_status(); + } else if (!strncmp(parm[0], "dump_reg", 8)) { + vlock_reg_dump(); + } else { + pr_info("unsupport cmd!!\n"); + } + if (sel < VLOCK_PARAM_MAX) + vlock_param_set(temp_val, sel); + kfree(buf_orig); + return count; +} + +/* #endif */ + +static void vpp_backup_histgram(struct vframe_s *vf) +{ + unsigned int i = 0; + + vpp_hist_param.vpp_hist_pow = vf->prop.hist.hist_pow; + vpp_hist_param.vpp_luma_sum = vf->prop.hist.vpp_luma_sum; + vpp_hist_param.vpp_pixel_sum = vf->prop.hist.vpp_pixel_sum; + for (i = 0; i < 64; i++) + vpp_hist_param.vpp_histgram[i] = vf->prop.hist.vpp_gamma[i]; +} + +static void vpp_dump_histgram(void) +{ + uint i; + + pr_info("%s:\n", __func__); + for (i = 0; i < 64; i++) { + pr_info("[%d]0x%-8x\t", i, vpp_hist_param.vpp_histgram[i]); + if ((i+1)%8 == 0) + pr_info("\n"); + } +} + +void vpp_get_hist_en(void) +{ + WRITE_VPP_REG_BITS(VI_HIST_CTRL, 0x1, 11, 3); + WRITE_VPP_REG_BITS(VI_HIST_CTRL, 0x1, 0, 1); + WRITE_VPP_REG(VI_HIST_GCLK_CTRL, 0xffffffff); + WRITE_VPP_REG_BITS(VI_HIST_CTRL, 2, VI_HIST_POW_BIT, VI_HIST_POW_WID); +} + +void vpp_get_vframe_hist_info(struct vframe_s *vf) +{ + unsigned int hist_height, hist_width; + + hist_height = READ_VPP_REG_BITS(VPP_IN_H_V_SIZE, 0, 13); + hist_width = READ_VPP_REG_BITS(VPP_IN_H_V_SIZE, 16, 13); + + if ((hist_height != pre_hist_height) || + (hist_width != pre_hist_width)) { + pre_hist_height = hist_height; + pre_hist_width = hist_width; + WRITE_VPP_REG_BITS(VI_HIST_PIC_SIZE, hist_height, 16, 13); + WRITE_VPP_REG_BITS(VI_HIST_PIC_SIZE, hist_width, 0, 13); + } + /* fetch hist info */ + /* vf->prop.hist.luma_sum = READ_CBUS_REG_BITS(VDIN_HIST_SPL_VAL,*/ + /* HIST_LUMA_SUM_BIT, HIST_LUMA_SUM_WID ); */ + vf->prop.hist.hist_pow = READ_VPP_REG_BITS(VI_HIST_CTRL, + VI_HIST_POW_BIT, VI_HIST_POW_WID); + vf->prop.hist.vpp_luma_sum = READ_VPP_REG(VI_HIST_SPL_VAL); + /* vf->prop.hist.chroma_sum = READ_CBUS_REG_BITS(VDIN_HIST_CHROMA_SUM,*/ + /* HIST_CHROMA_SUM_BIT, HIST_CHROMA_SUM_WID ); */ + vf->prop.hist.vpp_chroma_sum = READ_VPP_REG(VI_HIST_CHROMA_SUM); + vf->prop.hist.vpp_pixel_sum = READ_VPP_REG_BITS(VI_HIST_SPL_PIX_CNT, + VI_HIST_PIX_CNT_BIT, VI_HIST_PIX_CNT_WID); + vf->prop.hist.vpp_height = READ_VPP_REG_BITS(VI_HIST_PIC_SIZE, + VI_HIST_PIC_HEIGHT_BIT, VI_HIST_PIC_HEIGHT_WID); + vf->prop.hist.vpp_width = READ_VPP_REG_BITS(VI_HIST_PIC_SIZE, + VI_HIST_PIC_WIDTH_BIT, VI_HIST_PIC_WIDTH_WID); + vf->prop.hist.vpp_luma_max = READ_VPP_REG_BITS(VI_HIST_MAX_MIN, + VI_HIST_MAX_BIT, VI_HIST_MAX_WID); + vf->prop.hist.vpp_luma_min = READ_VPP_REG_BITS(VI_HIST_MAX_MIN, + VI_HIST_MIN_BIT, VI_HIST_MIN_WID); + vf->prop.hist.vpp_gamma[0] = READ_VPP_REG_BITS(VI_DNLP_HIST00, + VI_HIST_ON_BIN_00_BIT, VI_HIST_ON_BIN_00_WID); + vf->prop.hist.vpp_gamma[1] = READ_VPP_REG_BITS(VI_DNLP_HIST00, + VI_HIST_ON_BIN_01_BIT, VI_HIST_ON_BIN_01_WID); + vf->prop.hist.vpp_gamma[2] = READ_VPP_REG_BITS(VI_DNLP_HIST01, + VI_HIST_ON_BIN_02_BIT, VI_HIST_ON_BIN_02_WID); + vf->prop.hist.vpp_gamma[3] = READ_VPP_REG_BITS(VI_DNLP_HIST01, + VI_HIST_ON_BIN_03_BIT, VI_HIST_ON_BIN_03_WID); + vf->prop.hist.vpp_gamma[4] = READ_VPP_REG_BITS(VI_DNLP_HIST02, + VI_HIST_ON_BIN_04_BIT, VI_HIST_ON_BIN_04_WID); + vf->prop.hist.vpp_gamma[5] = READ_VPP_REG_BITS(VI_DNLP_HIST02, + VI_HIST_ON_BIN_05_BIT, VI_HIST_ON_BIN_05_WID); + vf->prop.hist.vpp_gamma[6] = READ_VPP_REG_BITS(VI_DNLP_HIST03, + VI_HIST_ON_BIN_06_BIT, VI_HIST_ON_BIN_06_WID); + vf->prop.hist.vpp_gamma[7] = READ_VPP_REG_BITS(VI_DNLP_HIST03, + VI_HIST_ON_BIN_07_BIT, VI_HIST_ON_BIN_07_WID); + vf->prop.hist.vpp_gamma[8] = READ_VPP_REG_BITS(VI_DNLP_HIST04, + VI_HIST_ON_BIN_08_BIT, VI_HIST_ON_BIN_08_WID); + vf->prop.hist.vpp_gamma[9] = READ_VPP_REG_BITS(VI_DNLP_HIST04, + VI_HIST_ON_BIN_09_BIT, VI_HIST_ON_BIN_09_WID); + vf->prop.hist.vpp_gamma[10] = READ_VPP_REG_BITS(VI_DNLP_HIST05, + VI_HIST_ON_BIN_10_BIT, VI_HIST_ON_BIN_10_WID); + vf->prop.hist.vpp_gamma[11] = READ_VPP_REG_BITS(VI_DNLP_HIST05, + VI_HIST_ON_BIN_11_BIT, VI_HIST_ON_BIN_11_WID); + vf->prop.hist.vpp_gamma[12] = READ_VPP_REG_BITS(VI_DNLP_HIST06, + VI_HIST_ON_BIN_12_BIT, VI_HIST_ON_BIN_12_WID); + vf->prop.hist.vpp_gamma[13] = READ_VPP_REG_BITS(VI_DNLP_HIST06, + VI_HIST_ON_BIN_13_BIT, VI_HIST_ON_BIN_13_WID); + vf->prop.hist.vpp_gamma[14] = READ_VPP_REG_BITS(VI_DNLP_HIST07, + VI_HIST_ON_BIN_14_BIT, VI_HIST_ON_BIN_14_WID); + vf->prop.hist.vpp_gamma[15] = READ_VPP_REG_BITS(VI_DNLP_HIST07, + VI_HIST_ON_BIN_15_BIT, VI_HIST_ON_BIN_15_WID); + vf->prop.hist.vpp_gamma[16] = READ_VPP_REG_BITS(VI_DNLP_HIST08, + VI_HIST_ON_BIN_16_BIT, VI_HIST_ON_BIN_16_WID); + vf->prop.hist.vpp_gamma[17] = READ_VPP_REG_BITS(VI_DNLP_HIST08, + VI_HIST_ON_BIN_17_BIT, VI_HIST_ON_BIN_17_WID); + vf->prop.hist.vpp_gamma[18] = READ_VPP_REG_BITS(VI_DNLP_HIST09, + VI_HIST_ON_BIN_18_BIT, VI_HIST_ON_BIN_18_WID); + vf->prop.hist.vpp_gamma[19] = READ_VPP_REG_BITS(VI_DNLP_HIST09, + VI_HIST_ON_BIN_19_BIT, VI_HIST_ON_BIN_19_WID); + vf->prop.hist.vpp_gamma[20] = READ_VPP_REG_BITS(VI_DNLP_HIST10, + VI_HIST_ON_BIN_20_BIT, VI_HIST_ON_BIN_20_WID); + vf->prop.hist.vpp_gamma[21] = READ_VPP_REG_BITS(VI_DNLP_HIST10, + VI_HIST_ON_BIN_21_BIT, VI_HIST_ON_BIN_21_WID); + vf->prop.hist.vpp_gamma[22] = READ_VPP_REG_BITS(VI_DNLP_HIST11, + VI_HIST_ON_BIN_22_BIT, VI_HIST_ON_BIN_22_WID); + vf->prop.hist.vpp_gamma[23] = READ_VPP_REG_BITS(VI_DNLP_HIST11, + VI_HIST_ON_BIN_23_BIT, VI_HIST_ON_BIN_23_WID); + vf->prop.hist.vpp_gamma[24] = READ_VPP_REG_BITS(VI_DNLP_HIST12, + VI_HIST_ON_BIN_24_BIT, VI_HIST_ON_BIN_24_WID); + vf->prop.hist.vpp_gamma[25] = READ_VPP_REG_BITS(VI_DNLP_HIST12, + VI_HIST_ON_BIN_25_BIT, VI_HIST_ON_BIN_25_WID); + vf->prop.hist.vpp_gamma[26] = READ_VPP_REG_BITS(VI_DNLP_HIST13, + VI_HIST_ON_BIN_26_BIT, VI_HIST_ON_BIN_26_WID); + vf->prop.hist.vpp_gamma[27] = READ_VPP_REG_BITS(VI_DNLP_HIST13, + VI_HIST_ON_BIN_27_BIT, VI_HIST_ON_BIN_27_WID); + vf->prop.hist.vpp_gamma[28] = READ_VPP_REG_BITS(VI_DNLP_HIST14, + VI_HIST_ON_BIN_28_BIT, VI_HIST_ON_BIN_28_WID); + vf->prop.hist.vpp_gamma[29] = READ_VPP_REG_BITS(VI_DNLP_HIST14, + VI_HIST_ON_BIN_29_BIT, VI_HIST_ON_BIN_29_WID); + vf->prop.hist.vpp_gamma[30] = READ_VPP_REG_BITS(VI_DNLP_HIST15, + VI_HIST_ON_BIN_30_BIT, VI_HIST_ON_BIN_30_WID); + vf->prop.hist.vpp_gamma[31] = READ_VPP_REG_BITS(VI_DNLP_HIST15, + VI_HIST_ON_BIN_31_BIT, VI_HIST_ON_BIN_31_WID); + vf->prop.hist.vpp_gamma[32] = READ_VPP_REG_BITS(VI_DNLP_HIST16, + VI_HIST_ON_BIN_32_BIT, VI_HIST_ON_BIN_32_WID); + vf->prop.hist.vpp_gamma[33] = READ_VPP_REG_BITS(VI_DNLP_HIST16, + VI_HIST_ON_BIN_33_BIT, VI_HIST_ON_BIN_33_WID); + vf->prop.hist.vpp_gamma[34] = READ_VPP_REG_BITS(VI_DNLP_HIST17, + VI_HIST_ON_BIN_34_BIT, VI_HIST_ON_BIN_34_WID); + vf->prop.hist.vpp_gamma[35] = READ_VPP_REG_BITS(VI_DNLP_HIST17, + VI_HIST_ON_BIN_35_BIT, VI_HIST_ON_BIN_35_WID); + vf->prop.hist.vpp_gamma[36] = READ_VPP_REG_BITS(VI_DNLP_HIST18, + VI_HIST_ON_BIN_36_BIT, VI_HIST_ON_BIN_36_WID); + vf->prop.hist.vpp_gamma[37] = READ_VPP_REG_BITS(VI_DNLP_HIST18, + VI_HIST_ON_BIN_37_BIT, VI_HIST_ON_BIN_37_WID); + vf->prop.hist.vpp_gamma[38] = READ_VPP_REG_BITS(VI_DNLP_HIST19, + VI_HIST_ON_BIN_38_BIT, VI_HIST_ON_BIN_38_WID); + vf->prop.hist.vpp_gamma[39] = READ_VPP_REG_BITS(VI_DNLP_HIST19, + VI_HIST_ON_BIN_39_BIT, VI_HIST_ON_BIN_39_WID); + vf->prop.hist.vpp_gamma[40] = READ_VPP_REG_BITS(VI_DNLP_HIST20, + VI_HIST_ON_BIN_40_BIT, VI_HIST_ON_BIN_40_WID); + vf->prop.hist.vpp_gamma[41] = READ_VPP_REG_BITS(VI_DNLP_HIST20, + VI_HIST_ON_BIN_41_BIT, VI_HIST_ON_BIN_41_WID); + vf->prop.hist.vpp_gamma[42] = READ_VPP_REG_BITS(VI_DNLP_HIST21, + VI_HIST_ON_BIN_42_BIT, VI_HIST_ON_BIN_42_WID); + vf->prop.hist.vpp_gamma[43] = READ_VPP_REG_BITS(VI_DNLP_HIST21, + VI_HIST_ON_BIN_43_BIT, VI_HIST_ON_BIN_43_WID); + vf->prop.hist.vpp_gamma[44] = READ_VPP_REG_BITS(VI_DNLP_HIST22, + VI_HIST_ON_BIN_44_BIT, VI_HIST_ON_BIN_44_WID); + vf->prop.hist.vpp_gamma[45] = READ_VPP_REG_BITS(VI_DNLP_HIST22, + VI_HIST_ON_BIN_45_BIT, VI_HIST_ON_BIN_45_WID); + vf->prop.hist.vpp_gamma[46] = READ_VPP_REG_BITS(VI_DNLP_HIST23, + VI_HIST_ON_BIN_46_BIT, VI_HIST_ON_BIN_46_WID); + vf->prop.hist.vpp_gamma[47] = READ_VPP_REG_BITS(VI_DNLP_HIST23, + VI_HIST_ON_BIN_47_BIT, VI_HIST_ON_BIN_47_WID); + vf->prop.hist.vpp_gamma[48] = READ_VPP_REG_BITS(VI_DNLP_HIST24, + VI_HIST_ON_BIN_48_BIT, VI_HIST_ON_BIN_48_WID); + vf->prop.hist.vpp_gamma[49] = READ_VPP_REG_BITS(VI_DNLP_HIST24, + VI_HIST_ON_BIN_49_BIT, VI_HIST_ON_BIN_49_WID); + vf->prop.hist.vpp_gamma[50] = READ_VPP_REG_BITS(VI_DNLP_HIST25, + VI_HIST_ON_BIN_50_BIT, VI_HIST_ON_BIN_50_WID); + vf->prop.hist.vpp_gamma[51] = READ_VPP_REG_BITS(VI_DNLP_HIST25, + VI_HIST_ON_BIN_51_BIT, VI_HIST_ON_BIN_51_WID); + vf->prop.hist.vpp_gamma[52] = READ_VPP_REG_BITS(VI_DNLP_HIST26, + VI_HIST_ON_BIN_52_BIT, VI_HIST_ON_BIN_52_WID); + vf->prop.hist.vpp_gamma[53] = READ_VPP_REG_BITS(VI_DNLP_HIST26, + VI_HIST_ON_BIN_53_BIT, VI_HIST_ON_BIN_53_WID); + vf->prop.hist.vpp_gamma[54] = READ_VPP_REG_BITS(VI_DNLP_HIST27, + VI_HIST_ON_BIN_54_BIT, VI_HIST_ON_BIN_54_WID); + vf->prop.hist.vpp_gamma[55] = READ_VPP_REG_BITS(VI_DNLP_HIST27, + VI_HIST_ON_BIN_55_BIT, VI_HIST_ON_BIN_55_WID); + vf->prop.hist.vpp_gamma[56] = READ_VPP_REG_BITS(VI_DNLP_HIST28, + VI_HIST_ON_BIN_56_BIT, VI_HIST_ON_BIN_56_WID); + vf->prop.hist.vpp_gamma[57] = READ_VPP_REG_BITS(VI_DNLP_HIST28, + VI_HIST_ON_BIN_57_BIT, VI_HIST_ON_BIN_57_WID); + vf->prop.hist.vpp_gamma[58] = READ_VPP_REG_BITS(VI_DNLP_HIST29, + VI_HIST_ON_BIN_58_BIT, VI_HIST_ON_BIN_58_WID); + vf->prop.hist.vpp_gamma[59] = READ_VPP_REG_BITS(VI_DNLP_HIST29, + VI_HIST_ON_BIN_59_BIT, VI_HIST_ON_BIN_59_WID); + vf->prop.hist.vpp_gamma[60] = READ_VPP_REG_BITS(VI_DNLP_HIST30, + VI_HIST_ON_BIN_60_BIT, VI_HIST_ON_BIN_60_WID); + vf->prop.hist.vpp_gamma[61] = READ_VPP_REG_BITS(VI_DNLP_HIST30, + VI_HIST_ON_BIN_61_BIT, VI_HIST_ON_BIN_61_WID); + vf->prop.hist.vpp_gamma[62] = READ_VPP_REG_BITS(VI_DNLP_HIST31, + VI_HIST_ON_BIN_62_BIT, VI_HIST_ON_BIN_62_WID); + vf->prop.hist.vpp_gamma[63] = READ_VPP_REG_BITS(VI_DNLP_HIST31, + VI_HIST_ON_BIN_63_BIT, VI_HIST_ON_BIN_63_WID); +} + +static void ioctrl_get_hdr_metadata(struct vframe_s *vf) +{ + if (((vf->signal_type >> 16) & 0xff) == 9) { + if (vf->prop.master_display_colour.present_flag) { + + memcpy(vpp_hdr_metadata_s.primaries, + vf->prop.master_display_colour.primaries, + sizeof(u32)*6); + memcpy(vpp_hdr_metadata_s.white_point, + vf->prop.master_display_colour.white_point, + sizeof(u32)*2); + vpp_hdr_metadata_s.luminance[0] = + vf->prop.master_display_colour.luminance[0]; + vpp_hdr_metadata_s.luminance[1] = + vf->prop.master_display_colour.luminance[1]; + } else + memset(vpp_hdr_metadata_s.primaries, 0, + 10 * sizeof(unsigned int)); + } else + memset(vpp_hdr_metadata_s.primaries, 0, + 10 * sizeof(unsigned int)); +} + +void vpp_demo_config(struct vframe_s *vf) +{ + unsigned int reg_value; + /*dnlp demo config*/ + if (vpp_demo_latch_flag & VPP_DEMO_DNLP_EN) { + WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL, 1, 18, 1); + /*bit14-15 left: 2 right: 3*/ + WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL, 2, 14, 2); + reg_value = READ_VPP_REG_BITS(VPP_SRSHARP1_CTRL, 0, 1); + if (((vf->height > 1080) && (vf->width > 1920)) || + (reg_value == 0)) + WRITE_VPP_REG_BITS(VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH, + 1920, 0, 12); + else + WRITE_VPP_REG_BITS(VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH, + 960, 0, 12); + vpp_demo_latch_flag &= ~VPP_DEMO_DNLP_EN; + } else if (vpp_demo_latch_flag & VPP_DEMO_DNLP_DIS) { + WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL, 0, 18, 1); + WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL, 0, 14, 2); + WRITE_VPP_REG_BITS(VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH, + 0xfff, 0, 12); + vpp_demo_latch_flag &= ~VPP_DEMO_DNLP_DIS; + } + /*cm demo config*/ + if (vpp_demo_latch_flag & VPP_DEMO_CM_EN) { + /*left: 0x1 right: 0x4*/ + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x20f); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, 0x1); + vpp_demo_latch_flag &= ~VPP_DEMO_CM_EN; + } else if (vpp_demo_latch_flag & VPP_DEMO_CM_DIS) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x20f); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, 0x0); + vpp_demo_latch_flag &= ~VPP_DEMO_CM_DIS; + } +} + +void amvecm_video_latch(void) +{ + pc_mode_process(); + cm_latch_process(); + amvecm_size_patch(); + ve_dnlp_latch_process(); + ve_lcd_gamma_process(); + lvds_freq_process(); +/* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESONG9TV) */ + if (0) { + amvecm_3d_sync_process(); + amvecm_3d_black_process(); + } +/* #endif */ +} + +void amvecm_on_vs(struct vframe_s *vf) +{ + if ((probe_ok == 0) || + (is_meson_gxm_cpu() && is_dolby_vision_on())) + return; + + if (vf != NULL) { + /* matrix ajust */ + amvecm_matrix_process(vf); + + amvecm_bricon_process( + vd1_brightness, + vd1_contrast + vd1_contrast_offset, vf); + + ioctrl_get_hdr_metadata(vf); + amvecm_color_process( + saturation_pre + saturation_offset + + satu_shift_by_con, + hue_pre, vf); + + vpp_demo_config(vf); + } else + amvecm_matrix_process(NULL); + /* vlock processs */ + if ((get_cpu_type() >= + MESON_CPU_MAJOR_ID_GXBB) && (vf != NULL)) + amve_vlock_process(vf); + else if ((get_cpu_type() >= + MESON_CPU_MAJOR_ID_GXBB) && (vf == NULL)) + amve_vlock_resume(); + + /* pq latch process */ + amvecm_video_latch(); +} +EXPORT_SYMBOL(amvecm_on_vs); + + +void refresh_on_vs(struct vframe_s *vf) +{ + if (is_meson_gxm_cpu() && is_dolby_vision_on()) + return; + if (vf != NULL) { + vpp_get_vframe_hist_info(vf); + ve_on_vs(vf); + vpp_backup_histgram(vf); + } +} +EXPORT_SYMBOL(refresh_on_vs); + +static int amvecm_open(struct inode *inode, struct file *file) +{ + struct amvecm_dev_s *devp; + /* Get the per-device structure that contains this cdev */ + devp = container_of(inode->i_cdev, struct amvecm_dev_s, cdev); + file->private_data = devp; + return 0; +} + +static int amvecm_release(struct inode *inode, struct file *file) +{ + file->private_data = NULL; + return 0; +} +static struct am_regs_s amregs_ext; + +static long amvecm_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + int ret = 0; + void __user *argp; + + pr_amvecm_dbg("[amvecm..] %s: cmd_nr = 0x%x\n", + __func__, _IOC_NR(cmd)); + + if (probe_ok == 0) + return ret; + switch (cmd) { + case AMVECM_IOC_LOAD_REG: + if (pq_load_en == 0) { + ret = -EBUSY; + pr_amvecm_dbg("[amvecm..] pq ioctl function disabled !!\n"); + return ret; + } + + if ((vecm_latch_flag & FLAG_REG_MAP0) && + (vecm_latch_flag & FLAG_REG_MAP1) && + (vecm_latch_flag & FLAG_REG_MAP2) && + (vecm_latch_flag & FLAG_REG_MAP3) && + (vecm_latch_flag & FLAG_REG_MAP4) && + (vecm_latch_flag & FLAG_REG_MAP5)) { + ret = -EBUSY; + pr_amvecm_dbg("load regs error: loading regs, please wait\n"); + break; + } + if (copy_from_user(&amregs_ext, + (void __user *)arg, sizeof(struct am_regs_s))) { + pr_amvecm_dbg("0x%x load reg errors: can't get buffer length\n", + FLAG_REG_MAP0); + ret = -EFAULT; + } else + ret = cm_load_reg(&amregs_ext); + break; + case AMVECM_IOC_VE_DNLP_EN: + vecm_latch_flag |= FLAG_VE_DNLP_EN; + break; + case AMVECM_IOC_VE_DNLP_DIS: + vecm_latch_flag |= FLAG_VE_DNLP_DIS; + break; + case AMVECM_IOC_VE_DNLP: + if (copy_from_user(&am_ve_dnlp, + (void __user *)arg, + sizeof(struct ve_dnlp_s))) + ret = -EFAULT; + else + ve_dnlp_param_update(); + break; + case AMVECM_IOC_VE_NEW_DNLP: + if (copy_from_user(&am_ve_new_dnlp, + (void __user *)arg, + sizeof(struct ve_dnlp_table_s))) + ret = -EFAULT; + else + ve_new_dnlp_param_update(); + break; + case AMVECM_IOC_G_HIST_AVG: + argp = (void __user *)arg; + if ((video_ve_hist.height == 0) || (video_ve_hist.width == 0)) + ret = -EFAULT; + else if (copy_to_user(argp, + &video_ve_hist, + sizeof(struct ve_hist_s))) + ret = -EFAULT; + break; + case AMVECM_IOC_G_HIST_BIN: + argp = (void __user *)arg; + if (vpp_hist_param.vpp_pixel_sum == 0) + ret = -EFAULT; + else if (copy_to_user(argp, &vpp_hist_param, + sizeof(struct vpp_hist_param_s))) + ret = -EFAULT; + break; + case AMVECM_IOC_G_HDR_METADATA: + argp = (void __user *)arg; + if (copy_to_user(argp, &vpp_hdr_metadata_s, + sizeof(struct hdr_metadata_info_s))) + ret = -EFAULT; + break; + /**********************************************************************/ + /*gamma ioctl*/ + /**********************************************************************/ + case AMVECM_IOC_GAMMA_TABLE_EN: + if (!gamma_en) + return -EINVAL; + + vecm_latch_flag |= FLAG_GAMMA_TABLE_EN; + break; + case AMVECM_IOC_GAMMA_TABLE_DIS: + if (!gamma_en) + return -EINVAL; + + vecm_latch_flag |= FLAG_GAMMA_TABLE_DIS; + break; + case AMVECM_IOC_GAMMA_TABLE_R: + if (!gamma_en) + return -EINVAL; + + if (copy_from_user(&video_gamma_table_r, + (void __user *)arg, + sizeof(struct tcon_gamma_table_s))) + ret = -EFAULT; + else + vecm_latch_flag |= FLAG_GAMMA_TABLE_R; + break; + case AMVECM_IOC_GAMMA_TABLE_G: + if (!gamma_en) + return -EINVAL; + + if (copy_from_user(&video_gamma_table_g, + (void __user *)arg, + sizeof(struct tcon_gamma_table_s))) + ret = -EFAULT; + else + vecm_latch_flag |= FLAG_GAMMA_TABLE_G; + break; + case AMVECM_IOC_GAMMA_TABLE_B: + if (!gamma_en) + return -EINVAL; + + if (copy_from_user(&video_gamma_table_b, + (void __user *)arg, + sizeof(struct tcon_gamma_table_s))) + ret = -EFAULT; + else + vecm_latch_flag |= FLAG_GAMMA_TABLE_B; + break; + case AMVECM_IOC_S_RGB_OGO: + if (!wb_en) + return -EINVAL; + + if (copy_from_user(&video_rgb_ogo, + (void __user *)arg, + sizeof(struct tcon_rgb_ogo_s))) + ret = -EFAULT; + else + ve_ogo_param_update(); + break; + case AMVECM_IOC_G_RGB_OGO: + if (!wb_en) + return -EINVAL; + + if (copy_to_user((void __user *)arg, + &video_rgb_ogo, sizeof(struct tcon_rgb_ogo_s))) + ret = -EFAULT; + + break; + /*VLOCK*/ + case AMVECM_IOC_VLOCK_EN: + vecm_latch_flag |= FLAG_VLOCK_EN; + break; + case AMVECM_IOC_VLOCK_DIS: + vecm_latch_flag |= FLAG_VLOCK_DIS; + break; + /*3D-SYNC*/ + case AMVECM_IOC_3D_SYNC_EN: + vecm_latch_flag |= FLAG_3D_SYNC_EN; + break; + case AMVECM_IOC_3D_SYNC_DIS: + vecm_latch_flag |= FLAG_3D_SYNC_DIS; + break; + default: + ret = -EINVAL; + break; + } + return ret; +} +#ifdef CONFIG_COMPAT +static long amvecm_compat_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + unsigned long ret; + + arg = (unsigned long)compat_ptr(arg); + ret = amvecm_ioctl(file, cmd, arg); + return ret; +} +#endif +static ssize_t amvecm_dnlp_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%x\n", + (am_ve_dnlp.en << 28) | (am_ve_dnlp.rt << 24) | + (am_ve_dnlp.rl << 16) | (am_ve_dnlp.black << 8) | + (am_ve_dnlp.white << 0)); +} +/* [ 28] en 0~1 */ +/* [27:20] rt 0~16 */ +/* [19:16] rl-1 0~15 */ +/* [15: 8] black 0~16 */ +/* [ 7: 0] white 0~16 */ +static ssize_t amvecm_dnlp_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + s32 val; + + r = sscanf(buf, "0x%x", &val); + if ((r != 1) || (vecm_latch_flag & FLAG_VE_DNLP)) + return -EINVAL; + am_ve_dnlp.en = (val & 0xf0000000) >> 28; + am_ve_dnlp.rt = (val & 0x0f000000) >> 24; + am_ve_dnlp.rl = (val & 0x00ff0000) >> 16; + am_ve_dnlp.black = (val & 0x0000ff00) >> 8; + am_ve_dnlp.white = (val & 0x000000ff) >> 0; + if (am_ve_dnlp.en > 1) + am_ve_dnlp.en = 1; + if (am_ve_dnlp.rl > 64) + am_ve_dnlp.rl = 64; + if (am_ve_dnlp.black > 16) + am_ve_dnlp.black = 16; + if (am_ve_dnlp.white > 16) + am_ve_dnlp.white = 16; + vecm_latch_flag |= FLAG_VE_DNLP; + return count; +} + +static ssize_t amvecm_brightness_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", vd1_brightness); +} + +static ssize_t amvecm_brightness_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + int val; + + r = sscanf(buf, "%d\n", &val); + if ((r != 1) || (val < -1024) || (val > 1024)) + return -EINVAL; + + vd1_brightness = val; + /*vecm_latch_flag |= FLAG_BRI_CON;*/ + vecm_latch_flag |= FLAG_VADJ1_BRI; + return count; +} + +static ssize_t amvecm_contrast_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", vd1_contrast); +} + +static ssize_t amvecm_contrast_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + int val; + + r = sscanf(buf, "%d\n", &val); + if ((r != 1) || (val < -1024) || (val > 1024)) + return -EINVAL; + + vd1_contrast = val; + /*vecm_latch_flag |= FLAG_BRI_CON;*/ + vecm_latch_flag |= FLAG_VADJ1_CON; + + if (val > 0) + satu_shift_by_con = val >> 3; + else + satu_shift_by_con = 0; + vecm_latch_flag |= FLAG_VADJ1_COLOR; + return count; +} + +static ssize_t amvecm_saturation_hue_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%x\n", READ_VPP_REG(VPP_VADJ1_MA_MB)); +} + +static ssize_t amvecm_saturation_hue_store(struct class *cla, + struct class_attribute *attr, const char *buf, size_t count) +{ + size_t r; + s32 mab = 0; + s16 mc = 0, md = 0; + s16 ma, mb; + + r = sscanf(buf, "0x%x", &mab); + if ((r != 1) || (mab&0xfc00fc00)) + return -EINVAL; + ma = (s16)((mab << 6) >> 22); + mb = (s16)((mab << 22) >> 22); + + saturation_ma = ma - 0x100; + saturation_mb = mb; + + ma += saturation_ma_shift; + mb += saturation_mb_shift; + mab = ((ma & 0x3ff) << 16) | (mb & 0x3ff); + WRITE_VPP_REG(VPP_VADJ1_MA_MB, mab); + mc = (s16)((mab<<22)>>22); /* mc = -mb */ + mc = 0 - mc; + if (mc > 511) + mc = 511; + if (mc < -512) + mc = -512; + md = (s16)((mab<<6)>>22); /* md = ma; */ + mab = ((mc&0x3ff)<<16)|(md&0x3ff); + WRITE_VPP_REG(VPP_VADJ1_MC_MD, mab); + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); + pr_amvecm_dbg("%s set video_saturation_hue OK!!!\n", __func__); + return count; +} + +static int parse_para_pq(const char *para, int para_num, int *result) +{ + char *token = NULL; + char *params, *params_base; + int *out = result; + int len = 0, count = 0; + int res = 0; + + if (!para) + return 0; + + params = kstrdup(para, GFP_KERNEL); + params_base = params; + token = params; + len = strlen(token); + do { + token = strsep(¶ms, " "); + while (token && (isspace(*token) + || !isgraph(*token)) && len) { + token++; + len--; + } + if (len == 0) + break; + if (!token || kstrtoint(token, 0, &res) < 0) + break; + len = strlen(token); + *out++ = res; + count++; + } while ((token) && (count < para_num) && (len > 0)); + + kfree(params_base); + return count; +} + +void vpp_vd_adj1_saturation_hue(signed int sat_val, + signed int hue_val, struct vframe_s *vf) +{ + int i, ma, mb, mab, mc, md; + int hue_cos[] = { + /*0~12*/ + 256, 256, 256, 255, 255, 254, 253, 252, 251, 250, 248, 247, 245, + /*13~25*/ + 243, 241, 239, 237, 234, 231, 229, 226, 223, 220, 216, 213, 209 + }; + int hue_sin[] = { + /*-25~-13*/ + -147, -142, -137, -132, -126, -121, -115, -109, -104, + -98, -92, -86, -80, -74, -68, -62, -56, -50, + -44, -38, -31, -25, -19, -13, -6, /*-12~-1*/ + 0, /*0*/ + /*1~12*/ + 6, 13, 19, 25, 31, 38, 44, 50, 56, 62, + 68, 74, 80, 86, 92, 98, 104, 109, 115, 121, + 126, 132, 137, 142, 147 /*13~25*/ + }; + + i = (hue_val > 0) ? hue_val : -hue_val; + ma = (hue_cos[i]*(sat_val + 128)) >> 7; + mb = (hue_sin[25+hue_val]*(sat_val + 128)) >> 7; + saturation_ma_shift = ma - 0x100; + saturation_mb_shift = mb; + + ma += saturation_ma; + mb += saturation_mb; + if (ma > 511) + ma = 511; + if (ma < -512) + ma = -512; + if (mb > 511) + mb = 511; + if (mb < -512) + mb = -512; + mab = ((ma & 0x3ff) << 16) | (mb & 0x3ff); + pr_info("\n[amvideo..] saturation_pre:%d hue_pre:%d mab:%x\n", + sat_val, hue_val, mab); + WRITE_VPP_REG(VPP_VADJ1_MA_MB, mab); + mc = (s16)((mab<<22)>>22); /* mc = -mb */ + mc = 0 - mc; + if (mc > 511) + mc = 511; + if (mc < -512) + mc = -512; + md = (s16)((mab<<6)>>22); /* md = ma; */ + mab = ((mc&0x3ff)<<16)|(md&0x3ff); + WRITE_VPP_REG(VPP_VADJ1_MC_MD, mab); + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); +}; + +static ssize_t amvecm_saturation_hue_pre_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return snprintf(buf, 20, "%d %d\n", saturation_pre, hue_pre); +} + +static ssize_t amvecm_saturation_hue_pre_store(struct class *cla, + struct class_attribute *attr, const char *buf, size_t count) +{ + int parsed[2]; + + if (likely(parse_para_pq(buf, 2, parsed) != 2)) + return -EINVAL; + + if ((parsed[0] < -128) || (parsed[0] > 128) || + (parsed[1] < -25) || (parsed[1] > 25)) { + return -EINVAL; + } + saturation_pre = parsed[0]; + hue_pre = parsed[1]; + vecm_latch_flag |= FLAG_VADJ1_COLOR; + + return count; +} + +static ssize_t amvecm_saturation_hue_post_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return snprintf(buf, 20, "%d %d\n", saturation_post, hue_post); +} + +static ssize_t amvecm_saturation_hue_post_store(struct class *cla, + struct class_attribute *attr, const char *buf, size_t count) +{ + int parsed[2]; + int i, ma, mb, mab, mc, md; + int hue_cos[] = { + /*0~12*/ + 256, 256, 256, 255, 255, 254, 253, 252, 251, 250, + 248, 247, 245, 243, 241, 239, 237, 234, 231, 229, + 226, 223, 220, 216, 213, 209 /*13~25*/ + }; + int hue_sin[] = { + -147, -142, -137, -132, -126, -121, -115, -109, -104, + -98, -92, -86, -80, /*-25~-13*/-74, -68, -62, -56, + -50, -44, -38, -31, -25, -19, -13, -6, /*-12~-1*/ + 0, /*0*/ + 6, 13, 19, 25, 31, 38, 44, 50, 56, + 62, 68, 74, /*1~12*/ 80, 86, 92, 98, 104, + 109, 115, 121, 126, 132, 137, 142, 147 /*13~25*/ + }; + if (likely(parse_para_pq(buf, 2, parsed) != 2)) + return -EINVAL; + + if ((parsed[0] < -128) || + (parsed[0] > 128) || + (parsed[1] < -25) || + (parsed[1] > 25)) { + return -EINVAL; + } + saturation_post = parsed[0]; + hue_post = parsed[1]; + i = (hue_post > 0) ? hue_post : -hue_post; + ma = (hue_cos[i]*(saturation_post + 128)) >> 7; + mb = (hue_sin[25+hue_post]*(saturation_post + 128)) >> 7; + if (ma > 511) + ma = 511; + if (ma < -512) + ma = -512; + if (mb > 511) + mb = 511; + if (mb < -512) + mb = -512; + mab = ((ma & 0x3ff) << 16) | (mb & 0x3ff); + pr_info("\n[amvideo..] saturation_post:%d hue_post:%d mab:%x\n", + saturation_post, hue_post, mab); + WRITE_VPP_REG(VPP_VADJ2_MA_MB, mab); + mc = (s16)((mab<<22)>>22); /* mc = -mb */ + mc = 0 - mc; + if (mc > 511) + mc = 511; + if (mc < -512) + mc = -512; + md = (s16)((mab<<6)>>22); /* md = ma; */ + mab = ((mc&0x3ff)<<16)|(md&0x3ff); + WRITE_VPP_REG(VPP_VADJ2_MC_MD, mab); + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1); + return count; +} + +static ssize_t amvecm_cm2_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + pr_info("Usage:"); + pr_info(" echo wm addr data0 data1 data2 data3 data4 "); + pr_info("> /sys/class/amvecm/cm2\n"); + pr_info(" echo rm addr > /sys/class/amvecm/cm2\n"); + return 0; +} + +static ssize_t amvecm_cm2_store(struct class *cls, + struct class_attribute *attr, + const char *buffer, size_t count) +{ + int n = 0; + char *buf_orig, *ps, *token; + char *parm[7]; + u32 addr; + int data[5] = {0}; + unsigned int addr_port = VPP_CHROMA_ADDR_PORT;/* 0x1d70; */ + unsigned int data_port = VPP_CHROMA_DATA_PORT;/* 0x1d71; */ + long val; + char delim1[3] = " "; + char delim2[2] = "\n"; + + buf_orig = kstrdup(buffer, GFP_KERNEL); + ps = buf_orig; + strcat(delim1, delim2); + while (1) { + token = strsep(&ps, delim1); + if (token == NULL) + break; + if (*token == '\0') + continue; + parm[n++] = token; + } + + if ((parm[0][0] == 'w') && parm[0][1] == 'm') { + if (n != 7) { + pr_info("read: invalid parameter\n"); + pr_info("please: cat /sys/class/amvecm/cm2\n"); + kfree(buf_orig); + return count; + } + if (kstrtol(parm[1], 16, &val) < 0) + return -EINVAL; + addr = val; + addr = addr - addr%8; + if (kstrtol(parm[2], 16, &val) < 0) + return -EINVAL; + data[0] = val; + if (kstrtol(parm[3], 16, &val) < 0) + return -EINVAL; + data[1] = val; + if (kstrtol(parm[4], 16, &val) < 0) + return -EINVAL; + data[2] = val; + if (kstrtol(parm[5], 16, &val) < 0) + return -EINVAL; + data[3] = val; + if (kstrtol(parm[6], 16, &val) < 0) + return -EINVAL; + data[4] = val; + WRITE_VPP_REG(addr_port, addr); + WRITE_VPP_REG(data_port, data[0]); + WRITE_VPP_REG(addr_port, addr + 1); + WRITE_VPP_REG(data_port, data[1]); + WRITE_VPP_REG(addr_port, addr + 2); + WRITE_VPP_REG(data_port, data[2]); + WRITE_VPP_REG(addr_port, addr + 3); + WRITE_VPP_REG(data_port, data[3]); + WRITE_VPP_REG(addr_port, addr + 4); + WRITE_VPP_REG(data_port, data[4]); + pr_info("wm: [0x%x] <-- 0x0\n", addr); + } else if ((parm[0][0] == 'r') && parm[0][1] == 'm') { + if (n != 2) { + pr_info("read: invalid parameter\n"); + pr_info("please: cat /sys/class/amvecm/cm2\n"); + kfree(buf_orig); + return count; + } + if (kstrtol(parm[1], 16, &val) < 0) + return -EINVAL; + addr = val; + addr = addr - addr%8; + WRITE_VPP_REG(addr_port, addr); + data[0] = READ_VPP_REG(data_port); + data[0] = READ_VPP_REG(data_port); + data[0] = READ_VPP_REG(data_port); + WRITE_VPP_REG(addr_port, addr+1); + data[1] = READ_VPP_REG(data_port); + data[1] = READ_VPP_REG(data_port); + data[1] = READ_VPP_REG(data_port); + WRITE_VPP_REG(addr_port, addr+2); + data[2] = READ_VPP_REG(data_port); + data[2] = READ_VPP_REG(data_port); + data[2] = READ_VPP_REG(data_port); + WRITE_VPP_REG(addr_port, addr+3); + data[3] = READ_VPP_REG(data_port); + data[3] = READ_VPP_REG(data_port); + data[3] = READ_VPP_REG(data_port); + WRITE_VPP_REG(addr_port, addr+4); + data[4] = READ_VPP_REG(data_port); + data[4] = READ_VPP_REG(data_port); + data[4] = READ_VPP_REG(data_port); + pr_info("rm:[0x%x]-->[0x%x][0x%x][0x%x][0x%x][0x%x]\n", + addr, data[0], data[1], + data[2], data[3], data[4]); + } else { + pr_info("invalid command\n"); + pr_info("please: cat /sys/class/amvecm/bit"); + } + kfree(buf_orig); + return count; +} + +static ssize_t amvecm_gamma_show(struct class *cls, + struct class_attribute *attr, + char *buf) +{ + pr_info("Usage:"); + pr_info(" echo sgr|sgg|sgb xxx...xx > /sys/class/amvecm/gamma\n"); + pr_info("Notes:"); + pr_info(" if the string xxx......xx is less than 256*3,"); + pr_info(" then the remaining will be set value 0\n"); + pr_info(" if the string xxx......xx is more than 256*3, "); + pr_info(" then the remaining will be ignored\n"); + return 0; +} + +static ssize_t amvecm_gamma_store(struct class *cls, + struct class_attribute *attr, + const char *buffer, size_t count) +{ + + int n = 0; + char *buf_orig, *ps, *token; + char *parm[4]; + unsigned short *gammaR, *gammaG, *gammaB; + unsigned int gamma_count; + char gamma[4]; + int i = 0; + long val; + char delim1[3] = " "; + char delim2[2] = "\n"; + + /* to avoid the bellow warning message while compiling: + * warning: the frame size of 1576 bytes is larger than 1024 bytes + */ + gammaR = kmalloc(256 * sizeof(unsigned short), GFP_KERNEL); + gammaG = kmalloc(256 * sizeof(unsigned short), GFP_KERNEL); + gammaB = kmalloc(256 * sizeof(unsigned short), GFP_KERNEL); + + buf_orig = kstrdup(buffer, GFP_KERNEL); + ps = buf_orig; + strcat(delim1, delim2); + while (1) { + token = strsep(&ps, delim1); + if (token == NULL) + break; + if (*token == '\0') + continue; + parm[n++] = token; + } + + if ((parm[0][0] == 's') && (parm[0][1] == 'g')) { + memset(gammaR, 0, 256 * sizeof(unsigned short)); + gamma_count = (strlen(parm[1]) + 2) / 3; + if (gamma_count > 256) + gamma_count = 256; + + for (i = 0; i < gamma_count; ++i) { + gamma[0] = parm[1][3 * i + 0]; + gamma[1] = parm[1][3 * i + 1]; + gamma[2] = parm[1][3 * i + 2]; + gamma[3] = '\0'; + if (kstrtol(gamma, 16, &val) < 0) + return -EINVAL; + gammaR[i] = val; + + } + + switch (parm[0][2]) { + case 'r': + vpp_set_lcd_gamma_table(gammaR, H_SEL_R); + break; + + case 'g': + vpp_set_lcd_gamma_table(gammaR, H_SEL_G); + break; + + case 'b': + vpp_set_lcd_gamma_table(gammaR, H_SEL_B); + break; + default: + break; + } + } else { + pr_info("invalid command\n"); + pr_info("please: cat /sys/class/amvecm/gamma"); + + } + kfree(buf_orig); + kfree(gammaR); + kfree(gammaG); + kfree(gammaB); + return count; +} + +static ssize_t set_gamma_pattern_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + pr_info(" echo r g b > /sys/class/amvecm/gamma_pattern\n"); + pr_info(" r g b should be hex\n"); + return 0; +} + +static ssize_t set_gamma_pattern_store(struct class *cls, + struct class_attribute *attr, + const char *buffer, size_t count) +{ + unsigned short r_val[256], g_val[256], b_val[256]; + int n = 0; + char *buf_orig, *ps, *token; + char *parm[3]; + unsigned int gamma[3]; + long val, i; + char deliml[3] = " "; + char delim2[2] = "\n"; + + buf_orig = kstrdup(buffer, GFP_KERNEL); + ps = buf_orig; + strcat(deliml, delim2); + while (1) { + token = strsep(&ps, deliml); + if (token == NULL) + break; + if (*token == '\0') + continue; + parm[n++] = token; + } + if (kstrtol(parm[0], 16, &val) < 0) + return -EINVAL; + gamma[0] = val << 2; + + if (kstrtol(parm[1], 16, &val) < 0) + return -EINVAL; + gamma[1] = val << 2; + + if (kstrtol(parm[2], 16, &val) < 0) + return -EINVAL; + gamma[2] = val << 2; + + for (i = 0; i < 256; i++) { + r_val[i] = gamma[0]; + g_val[i] = gamma[1]; + b_val[i] = gamma[2]; + } + + vpp_set_lcd_gamma_table(r_val, H_SEL_R); + + vpp_set_lcd_gamma_table(g_val, H_SEL_G); + + vpp_set_lcd_gamma_table(b_val, H_SEL_B); + return count; + +} + +void white_balance_adjust(int sel, int value) +{ + switch (sel) { + /*0: en*/ + /*1: pre r 2: pre g 3: pre b*/ + /*4: gain r 5: gain g 6: gain b*/ + /*7: post r 8: post g 9: post b*/ + case 0: + video_rgb_ogo.en = value; + break; + case 1: + video_rgb_ogo.r_pre_offset = value; + break; + case 2: + video_rgb_ogo.g_pre_offset = value; + break; + case 3: + video_rgb_ogo.b_pre_offset = value; + break; + case 4: + video_rgb_ogo.r_gain = value; + break; + case 5: + video_rgb_ogo.g_gain = value; + break; + case 6: + video_rgb_ogo.b_gain = value; + break; + case 7: + video_rgb_ogo.r_post_offset = value; + break; + case 8: + video_rgb_ogo.g_post_offset = value; + break; + case 9: + video_rgb_ogo.b_post_offset = value; + break; + default: + break; + } + ve_ogo_param_update(); +} + +static ssize_t amvecm_wb_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + pr_info("read: echo r gain_r > /sys/class/amvecm/wb\n"); + pr_info("read: echo r pre_r > /sys/class/amvecm/wb\n"); + pr_info("read: echo r post_r > /sys/class/amvecm/wb\n"); + pr_info("write: echo gain_r value > /sys/class/amvecm/wb\n"); + pr_info("write: echo preofst_r value > /sys/class/amvecm/wb\n"); + pr_info("write: echo postofst_r value > /sys/class/amvecm/wb\n"); + return 0; +} + +static ssize_t amvecm_wb_store(struct class *cls, + struct class_attribute *attr, + const char *buffer, size_t count) +{ + char *buf_orig, *parm[8] = {NULL}; + long value; + + if (!buffer) + return count; + buf_orig = kstrdup(buffer, GFP_KERNEL); + parse_param_amvecm(buf_orig, (char **)&parm); + + if (!strncmp(parm[0], "r", 1)) { + if (!strncmp(parm[1], "pre_r", 5)) + pr_info("\t Pre_R = %d\n", video_rgb_ogo.r_pre_offset); + else if (!strncmp(parm[1], "pre_g", 5)) + pr_info("\t Pre_G = %d\n", video_rgb_ogo.g_pre_offset); + else if (!strncmp(parm[1], "pre_b", 5)) + pr_info("\t Pre_B = %d\n", video_rgb_ogo.b_pre_offset); + else if (!strncmp(parm[1], "gain_r", 6)) + pr_info("\t Gain_R = %d\n", video_rgb_ogo.r_gain); + else if (!strncmp(parm[1], "gain_g", 6)) + pr_info("\t Gain_G = %d\n", video_rgb_ogo.g_gain); + else if (!strncmp(parm[1], "gain_b", 6)) + pr_info("\t Gain_B = %d\n", video_rgb_ogo.b_gain); + else if (!strncmp(parm[1], "post_r", 6)) + pr_info("\t Post_R = %d\n", + video_rgb_ogo.r_post_offset); + else if (!strncmp(parm[1], "post_g", 6)) + pr_info("\t Post_G = %d\n", + video_rgb_ogo.g_post_offset); + else if (!strncmp(parm[1], "post_b", 6)) + pr_info("\t Post_B = %d\n", + video_rgb_ogo.b_post_offset); + else if (!strncmp(parm[1], "en", 2)) + pr_info("\t En = %d\n", video_rgb_ogo.en); + } else { + if (kstrtol(parm[1], 10, &value) < 0) + return -EINVAL; + if (!strncmp(parm[0], "wb_en", 5)) { + white_balance_adjust(0, value); + pr_info("\t set wb en\n"); + } else if (!strncmp(parm[0], "preofst_r", 9)) { + if ((value > 1023) || (value < -1024)) + pr_info("\t preofst r over range\n"); + else { + white_balance_adjust(1, value); + pr_info("\t set wb preofst r\n"); + } + } else if (!strncmp(parm[0], "preofst_g", 9)) { + if ((value > 1023) || (value < -1024)) + pr_info("\t preofst g over range\n"); + else { + white_balance_adjust(2, value); + pr_info("\t set wb preofst g\n"); + } + } else if (!strncmp(parm[0], "preofst_b", 9)) { + if ((value > 1023) || (value < -1024)) + pr_info("\t preofst b over range\n"); + else { + white_balance_adjust(3, value); + pr_info("\t set wb preofst b\n"); + } + } else if (!strncmp(parm[0], "gain_r", 6)) { + if ((value > 2047) || (value < 0)) + pr_info("\t gain r over range\n"); + else { + white_balance_adjust(4, value); + pr_info("\t set wb gain r\n"); + } + } else if (!strncmp(parm[0], "gain_g", 6)) { + if ((value > 2047) || (value < 0)) + pr_info("\t gain g over range\n"); + else { + white_balance_adjust(5, value); + pr_info("\t set wb gain g\n"); + } + } else if (!strncmp(parm[0], "gain_b", 6)) { + if ((value > 2047) || (value < 0)) + pr_info("\t gain b over range\n"); + else { + white_balance_adjust(6, value); + pr_info("\t set wb gain b\n"); + } + } else if (!strncmp(parm[0], "postofst_r", 10)) { + if ((value > 1023) || (value < -1024)) + pr_info("\t postofst r over range\n"); + else { + white_balance_adjust(7, value); + pr_info("\t set wb postofst r\n"); + } + } else if (!strncmp(parm[0], "postofst_g", 10)) { + if ((value > 1023) || (value < -1024)) + pr_info("\t postofst g over range\n"); + else { + white_balance_adjust(8, value); + pr_info("\t set wb postofst g\n"); + } + } else if (!strncmp(parm[0], "postofst_b", 10)) { + if ((value > 1023) || (value < -1024)) + pr_info("\t postofst b over range\n"); + else { + white_balance_adjust(9, value); + pr_info("\t set wb postofst b\n"); + } + } + } + + kfree(buf_orig); + return count; +} + +static ssize_t set_hdr_289lut_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + int i; + + for (i = 0; i < 289; i++) { + pr_info("0x%-8x\t", lut_289_mapping[i]); + if ((i + 1) % 8 == 0) + pr_info("\n"); + } + return 0; +} +static ssize_t set_hdr_289lut_store(struct class *cls, + struct class_attribute *attr, + const char *buffer, size_t count) +{ + int n = 0; + char *buf_orig, *ps, *token; + char *parm[4]; + unsigned short *Hdr289lut; + unsigned int gamma_count; + char gamma[4]; + int i = 0; + long val; + char deliml[3] = " "; + char delim2[2] = "\n"; + + Hdr289lut = kmalloc(289 * sizeof(unsigned short), GFP_KERNEL); + + buf_orig = kstrdup(buffer, GFP_KERNEL); + ps = buf_orig; + strcat(deliml, delim2); + while (1) { + token = strsep(&ps, deliml); + if (token == NULL) + break; + if (*token == '\0') + continue; + parm[n++] = token; + } + + memset(Hdr289lut, 0, 289 * sizeof(unsigned short)); + gamma_count = (strlen(parm[0]) + 2) / 3; + if (gamma_count > 289) + gamma_count = 289; + + for (i = 0; i < gamma_count; ++i) { + gamma[0] = parm[0][3 * i + 0]; + gamma[1] = parm[0][3 * i + 1]; + gamma[2] = parm[0][3 * i + 2]; + gamma[3] = '\0'; + if (kstrtol(gamma, 16, &val) < 0) + return -EINVAL; + Hdr289lut[i] = val; + } + + for (i = 0; i < gamma_count; i++) + lut_289_mapping[i] = Hdr289lut[i]; + + kfree(buf_orig); + kfree(Hdr289lut); + return count; + +} + +static ssize_t amvecm_set_post_matrix_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%x\n", (int)(READ_VPP_REG(VPP_MATRIX_CTRL))); +} +static ssize_t amvecm_set_post_matrix_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + int val; + + r = sscanf(buf, "0x%x", &val); + if ((r != 1) || (val & 0xffff0000)) + return -EINVAL; + + WRITE_VPP_REG(VPP_MATRIX_CTRL, val); + return count; +} + +static ssize_t amvecm_post_matrix_pos_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%x\n", + (int)(READ_VPP_REG(VPP_MATRIX_PROBE_POS))); +} +static ssize_t amvecm_post_matrix_pos_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + int val; + + r = sscanf(buf, "0x%x", &val); + if ((r != 1) || (val & 0xf000f000)) + return -EINVAL; + + WRITE_VPP_REG(VPP_MATRIX_PROBE_POS, val); + return count; +} + +static ssize_t amvecm_post_matrix_data_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + int len = 0, val1 = 0, val2 = 0; + + val1 = READ_VPP_REG(VPP_MATRIX_PROBE_COLOR); +/* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESONG9TV) */ + val2 = READ_VPP_REG(VPP_MATRIX_PROBE_COLOR1); +/* #endif */ + len += sprintf(buf+len, "VPP_MATRIX_PROBE_COLOR %x\n", val1); + len += sprintf(buf+len, "VPP_MATRIX_PROBE_COLOR %x\n", val2); + return len; +} + +static ssize_t amvecm_post_matrix_data_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + return 0; +} + +static ssize_t amvecm_sr1_reg_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + unsigned int addr; + + addr = ((sr1_index+0x3280) << 2) | 0xd0100000; + return sprintf(buf, "0x%x = 0x%x\n", + addr, sr1_ret_val[sr1_index]); +} + +static ssize_t amvecm_sr1_reg_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + unsigned int addr, off_addr = 0; + + r = sscanf(buf, "0x%x", &addr); + addr = (addr&0xffff) >> 2; + if ((r != 1) || (addr > 0x32e4) || (addr < 0x3280)) + return -EINVAL; + off_addr = addr - 0x3280; + sr1_index = off_addr; + sr1_ret_val[off_addr] = sr1_reg_val[off_addr]; + + return count; + +} + +static ssize_t amvecm_write_sr1_reg_val_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return 0; +} + +static ssize_t amvecm_write_sr1_reg_val_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + unsigned int val; + + r = sscanf(buf, "0x%x", &val); + if (r != 1) + return -EINVAL; + sr1_reg_val[sr1_index] = val; + + return count; + +} + +static ssize_t amvecm_dump_reg_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + unsigned int addr; + unsigned int value; + + pr_info("----dump sharpness0 reg----\n"); + for (addr = 0x3200; + addr <= 0x3264; addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + if (is_meson_txl_cpu()) { + for (addr = 0x3265; + addr <= 0x3272; addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + } + pr_info("----dump sharpness1 reg----\n"); + for (addr = (0x3200+0x80); + addr <= (0x3264+0x80); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + if (is_meson_txl_cpu()) { + for (addr = (0x3265+0x80); + addr <= (0x3272+0x80); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + } + + pr_info("----dump cm reg----\n"); + for (addr = 0x200; addr <= 0x21e; addr++) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, addr); + value = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + addr, addr, + value); + } + for (addr = 0x100; addr <= 0x1fc; addr++) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, addr); + value = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + addr, addr, + value); + } + + pr_info("----dump vd1 IF0 reg----\n"); + for (addr = (0x1a50); + addr <= (0x1a69); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + pr_info("----dump vpp1 part1 reg----\n"); + for (addr = (0x1d00); + addr <= (0x1d6e); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + + pr_info("----dump vpp1 part2 reg----\n"); + for (addr = (0x1d72); + addr <= (0x1de4); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + + pr_info("----dump ndr reg----\n"); + for (addr = (0x2d00); + addr <= (0x2d78); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + pr_info("----dump nr3 reg----\n"); + for (addr = (0x2ff0); + addr <= (0x2ff6); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + pr_info("----dump vlock reg----\n"); + for (addr = (0x3000); + addr <= (0x3020); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + pr_info("----dump super scaler0 reg----\n"); + for (addr = (0x3100); + addr <= (0x3115); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + pr_info("----dump super scaler1 reg----\n"); + for (addr = (0x3118); + addr <= (0x312e); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + pr_info("----dump xvycc reg----\n"); + for (addr = (0x3158); + addr <= (0x3179); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (0xd0100000+(addr<<2)), addr, + READ_VPP_REG(addr)); + pr_info("----dump reg done----\n"); + return 0; +} +static ssize_t amvecm_dump_reg_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + return 0; +} +static ssize_t amvecm_dump_vpp_hist_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + vpp_dump_histgram(); + return 0; +} + +static ssize_t amvecm_dump_vpp_hist_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + return 0; +} + +static ssize_t amvecm_hdr_dbg_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + int ret; + + ret = amvecm_hdr_dbg(0); + + return 0; +} + +static ssize_t amvecm_hdr_dbg_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + return 0; +} + +static ssize_t amvecm_hdr_reg_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + int ret; + + ret = amvecm_hdr_dbg(1); + + return 0; +} + +static ssize_t amvecm_hdr_reg_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + return 0; +} + +static ssize_t amvecm_pc_mode_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + pr_info("pc:echo 0x0 > /sys/class/amvecm/pc_mode\n"); + pr_info("other:echo 0x1 > /sys/class/amvecm/pc_mode\n"); + pr_info("pc_mode:%d,pc_mode_last:%d\n", pc_mode, pc_mode_last); + return 0; +} + +static ssize_t amvecm_pc_mode_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + int val; + + r = sscanf(buf, "%x\n", &val); + if ((r != 1)) + return -EINVAL; + + if (val == 1) { + pc_mode = 1; + pc_mode_last = 0xff; + } else if (val == 0) { + pc_mode = 0; + pc_mode_last = 0xff; + } + + return count; +} + +void pc_mode_process(void) +{ + unsigned int reg_val; + + if ((pc_mode == 1) && (pc_mode != pc_mode_last)) { + /* open dnlp clock gate */ + dnlp_en = 1; + ve_enable_dnlp(); + /* open cm clock gate */ + cm_en = 1; + amcm_enable(); + /* sharpness on */ + WRITE_VPP_REG_BITS( + SRSHARP0_SHARP_PK_NR_ENABLE, + 1, 1, 1); + WRITE_VPP_REG_BITS( + SRSHARP1_SHARP_PK_NR_ENABLE, + 1, 1, 1); + reg_val = READ_VPP_REG(SRSHARP0_HCTI_FLT_CLP_DC); + WRITE_VPP_REG(SRSHARP0_HCTI_FLT_CLP_DC, + reg_val | 0x10000000); + WRITE_VPP_REG(SRSHARP1_HCTI_FLT_CLP_DC, + reg_val | 0x10000000); + + reg_val = READ_VPP_REG(SRSHARP0_HLTI_FLT_CLP_DC); + WRITE_VPP_REG(SRSHARP0_HLTI_FLT_CLP_DC, + reg_val | 0x10000000); + WRITE_VPP_REG(SRSHARP1_HLTI_FLT_CLP_DC, + reg_val | 0x10000000); + + reg_val = READ_VPP_REG(SRSHARP0_VLTI_FLT_CON_CLP); + WRITE_VPP_REG(SRSHARP0_VLTI_FLT_CON_CLP, + reg_val | 0x4000); + WRITE_VPP_REG(SRSHARP1_VLTI_FLT_CON_CLP, + reg_val | 0x4000); + + reg_val = READ_VPP_REG(SRSHARP0_VCTI_FLT_CON_CLP); + WRITE_VPP_REG(SRSHARP0_VCTI_FLT_CON_CLP, + reg_val | 0x4000); + WRITE_VPP_REG(SRSHARP1_VCTI_FLT_CON_CLP, + reg_val | 0x4000); + + if (is_meson_txl_cpu()) { + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 1, 28, 3); + + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 1, 28, 3); + } + WRITE_VPP_REG(VPP_VADJ_CTRL, 0xd); + pc_mode_last = pc_mode; + } else if ((pc_mode == 0) && (pc_mode != pc_mode_last)) { + dnlp_en = 0; + ve_disable_dnlp(); + cm_en = 0; + amcm_disable(); + + WRITE_VPP_REG_BITS( + SRSHARP0_SHARP_PK_NR_ENABLE, + 0, 1, 1); + WRITE_VPP_REG_BITS( + SRSHARP1_SHARP_PK_NR_ENABLE, + 0, 1, 1); + reg_val = READ_VPP_REG(SRSHARP0_HCTI_FLT_CLP_DC); + WRITE_VPP_REG(SRSHARP0_HCTI_FLT_CLP_DC, + reg_val & 0xefffffff); + WRITE_VPP_REG(SRSHARP1_HCTI_FLT_CLP_DC, + reg_val & 0xefffffff); + + reg_val = READ_VPP_REG(SRSHARP0_HLTI_FLT_CLP_DC); + WRITE_VPP_REG(SRSHARP0_HLTI_FLT_CLP_DC, + reg_val & 0xefffffff); + WRITE_VPP_REG(SRSHARP1_HLTI_FLT_CLP_DC, + reg_val & 0xefffffff); + + reg_val = READ_VPP_REG(SRSHARP0_VLTI_FLT_CON_CLP); + WRITE_VPP_REG(SRSHARP0_VLTI_FLT_CON_CLP, + reg_val & 0xffffbfff); + WRITE_VPP_REG(SRSHARP1_VLTI_FLT_CON_CLP, + reg_val & 0xffffbfff); + + reg_val = READ_VPP_REG(SRSHARP0_VCTI_FLT_CON_CLP); + WRITE_VPP_REG(SRSHARP0_VCTI_FLT_CON_CLP, + reg_val & 0xffffbfff); + WRITE_VPP_REG(SRSHARP1_VCTI_FLT_CON_CLP, + reg_val & 0xffffbfff); + + if (is_meson_txl_cpu()) { + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 0, 28, 3); + + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 0, 28, 3); + } + WRITE_VPP_REG(VPP_VADJ_CTRL, 0x0); + pc_mode_last = pc_mode; + } +} + +static ssize_t amvecm_vpp_demo_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return 0; +} + +static ssize_t amvecm_vpp_demo_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + int val; + + r = sscanf(buf, "%x\n", &val); + if ((r != 1)) + return -EINVAL; + + if (val & VPP_DEMO_CM_EN) + vpp_demo_latch_flag |= VPP_DEMO_CM_EN; + else if (val & VPP_DEMO_CM_DIS) + vpp_demo_latch_flag |= VPP_DEMO_CM_DIS; + + if (val & VPP_DEMO_DNLP_EN) + vpp_demo_latch_flag |= VPP_DEMO_DNLP_EN; + else if (val & VPP_DEMO_DNLP_DIS) + vpp_demo_latch_flag |= VPP_DEMO_DNLP_DIS; + + return count; +} + +static void dump_vpp_size_info(void) +{ + unsigned int vpp_input_h, vpp_input_v, + pps_input_length, pps_input_height, + pps_output_hs, pps_output_he, pps_output_vs, pps_output_ve, + vd1_preblend_hs, vd1_preblend_he, + vd1_preblend_vs, vd1_preblend_ve, + vd2_preblend_hs, vd2_preblend_he, + vd2_preblend_vs, vd2_preblend_ve, + prelend_input_hsize, + vd1_postblend_hs, vd1_postblend_he, + vd1_postblend_vs, vd1_postblend_ve, + postblend_hsize, + ve_hsize, ve_vsize, psr_hsize, psr_vsize, + cm_hsize, cm_vsize; + vpp_input_h = READ_VPP_REG_BITS(VPP_IN_H_V_SIZE, 16, 13); + vpp_input_v = READ_VPP_REG_BITS(VPP_IN_H_V_SIZE, 0, 13); + pps_input_length = READ_VPP_REG_BITS(VPP_LINE_IN_LENGTH, 0, 13); + pps_input_height = READ_VPP_REG_BITS(VPP_PIC_IN_HEIGHT, 0, 13); + pps_output_hs = READ_VPP_REG_BITS(VPP_HSC_REGION12_STARTP, 16, 13); + pps_output_he = READ_VPP_REG_BITS(VPP_HSC_REGION4_ENDP, 0, 13); + pps_output_vs = READ_VPP_REG_BITS(VPP_VSC_REGION12_STARTP, 16, 13); + pps_output_ve = READ_VPP_REG_BITS(VPP_VSC_REGION4_ENDP, 0, 13); + vd1_preblend_he = READ_VPP_REG_BITS(VPP_PREBLEND_VD1_H_START_END, + 0, 13); + vd1_preblend_hs = READ_VPP_REG_BITS(VPP_PREBLEND_VD1_H_START_END, + 16, 13); + vd1_preblend_ve = READ_VPP_REG_BITS(VPP_PREBLEND_VD1_V_START_END, + 0, 13); + vd1_preblend_vs = READ_VPP_REG_BITS(VPP_PREBLEND_VD1_V_START_END, + 16, 13); + vd2_preblend_he = READ_VPP_REG_BITS(VPP_BLEND_VD2_H_START_END, 0, 13); + vd2_preblend_hs = READ_VPP_REG_BITS(VPP_BLEND_VD2_H_START_END, 16, 13); + vd2_preblend_ve = READ_VPP_REG_BITS(VPP_BLEND_VD2_V_START_END, 0, 13); + vd2_preblend_vs = READ_VPP_REG_BITS(VPP_BLEND_VD2_V_START_END, 16, 13); + prelend_input_hsize = READ_VPP_REG_BITS(VPP_PREBLEND_H_SIZE, 0, 13); + vd1_postblend_he = READ_VPP_REG_BITS(VPP_POSTBLEND_VD1_H_START_END, + 0, 13); + vd1_postblend_hs = READ_VPP_REG_BITS(VPP_POSTBLEND_VD1_H_START_END, + 16, 13); + vd1_postblend_ve = READ_VPP_REG_BITS(VPP_POSTBLEND_VD1_V_START_END, + 0, 13); + vd1_postblend_vs = READ_VPP_REG_BITS(VPP_POSTBLEND_VD1_V_START_END, + 16, 13); + postblend_hsize = READ_VPP_REG_BITS(VPP_POSTBLEND_H_SIZE, 0, 13); + ve_hsize = READ_VPP_REG_BITS(VPP_VE_H_V_SIZE, 16, 13); + ve_vsize = READ_VPP_REG_BITS(VPP_VE_H_V_SIZE, 0, 13); + psr_hsize = READ_VPP_REG_BITS(VPP_PSR_H_V_SIZE, 16, 13); + psr_vsize = READ_VPP_REG_BITS(VPP_PSR_H_V_SIZE, 0, 13); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x205); + cm_hsize = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + cm_vsize = (cm_hsize >> 16) & 0xffff; + cm_hsize = cm_hsize & 0xffff; + pr_info("\n vpp size info:\n"); + pr_info("vpp_input_h:%d, vpp_input_v:%d\n" + "pps_input_length:%d, pps_input_height:%d\n" + "pps_output_hs:%d, pps_output_he:%d\n" + "pps_output_vs:%d, pps_output_ve:%d\n" + "vd1_preblend_hs:%d, vd1_preblend_he:%d\n" + "vd1_preblend_vs:%d, vd1_preblend_ve:%d\n" + "vd2_preblend_hs:%d, vd2_preblend_he:%d\n" + "vd2_preblend_vs:%d, vd2_preblend_ve:%d\n" + "prelend_input_hsize:%d\n" + "vd1_postblend_hs:%d, vd1_postblend_he:%d\n" + "vd1_postblend_vs:%d, vd1_postblend_ve:%d\n" + "postblend_hsize:%d\n" + "ve_hsize:%d, ve_vsize:%d\n" + "psr_hsize:%d, psr_vsize:%d\n" + "cm_hsize:%d, cm_vsize:%d\n", + vpp_input_h, vpp_input_v, + pps_input_length, pps_input_height, + pps_output_hs, pps_output_he, + pps_output_vs, pps_output_ve, + vd1_preblend_hs, vd1_preblend_he, + vd1_preblend_vs, vd1_preblend_ve, + vd2_preblend_hs, vd2_preblend_he, + vd2_preblend_vs, vd2_preblend_ve, + prelend_input_hsize, + vd1_postblend_hs, vd1_postblend_he, + vd1_postblend_vs, vd1_postblend_ve, + postblend_hsize, + ve_hsize, ve_vsize, + psr_hsize, psr_vsize, + cm_hsize, cm_vsize); +} + +static void vpp_sr3_enhance_enable(unsigned int enable) +{ + /*0x00: core 0 disable*/ + /*0x01: core 0 enable*/ + /*0x10: core 1 disable*/ + /*0x11: core 1 enable*/ + + if (enable == 0x00) { + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 0, 28, 3); + } else if (enable == 0x01) { + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 1, 28, 3); + } else if (enable == 0x10) { + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 0, 28, 3); + } else if (enable == 0x11) { + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 1, 28, 3); + } +} + +static void amvecm_wb_enable(int enable) +{ + if (enable) { + wb_en = 1; + WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, 1, 31, 1); + } else { + wb_en = 0; + WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, 0, 31, 1); + } +} + +static void amvecm_sharpness_debug(int enable) +{ + /*0:peaking enable 1:peaking disable*/ + /*2:lti/cti enable 3:lti/cti disable*/ + switch (enable) { + case 0: + WRITE_VPP_REG_BITS(SRSHARP0_SHARP_PK_NR_ENABLE, 1, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_SHARP_PK_NR_ENABLE, 1, 1, 1); + break; + case 1: + WRITE_VPP_REG_BITS(SRSHARP0_SHARP_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_SHARP_PK_NR_ENABLE, 0, 1, 1); + break; + case 2: + WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP, 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP, 1, 14, 1); + + WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC, 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC, 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 1, 14, 1); + break; + case 3: + WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP, 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP, 0, 14, 1); + + WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC, 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC, 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 0, 14, 1); + break; + default: + break; + } +} + +static void amvecm_pq_enable(int enable) +{ + if (enable) { + vecm_latch_flag |= FLAG_VE_DNLP_EN; + + amcm_enable(); + + WRITE_VPP_REG_BITS(SRSHARP0_SHARP_PK_NR_ENABLE, 1, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_SHARP_PK_NR_ENABLE, 1, 1, 1); + + WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP, 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP, 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC, 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC, 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 1, 14, 1); + + WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, 1, 31, 1); + + vecm_latch_flag |= FLAG_GAMMA_TABLE_EN; + + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); + } else { + vecm_latch_flag |= FLAG_VE_DNLP_DIS; + + amcm_disable(); + + WRITE_VPP_REG_BITS(SRSHARP0_SHARP_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_SHARP_PK_NR_ENABLE, 0, 1, 1); + + WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP, 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP, 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC, 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC, 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 0, 14, 1); + + WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, 0, 31, 1); + + vecm_latch_flag |= FLAG_GAMMA_TABLE_DIS; + + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 0, 0, 1); + } +} + +static const char *amvecm_debug_usage_str = { + "Usage:\n" + "echo vpp_size > /sys/class/amvecm/debug ; get vpp size config\n" +}; +static ssize_t amvecm_debug_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%s\n", amvecm_debug_usage_str); +} +static ssize_t amvecm_debug_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + char *buf_orig, *parm[8] = {NULL}; + + if (!buf) + return count; + buf_orig = kstrdup(buf, GFP_KERNEL); + parse_param_amvecm(buf_orig, (char **)&parm); + if (!strncmp(parm[0], "vpp_size", 8)) + dump_vpp_size_info(); + else if (!strncmp(parm[0], "4k_enhance", 10)) { + if (!strncmp(parm[1], "core0", 5)) { + if (!strncmp(parm[2], "00", 2)) { + vpp_sr3_enhance_enable(0x0); + pr_info("disable core0 sr3 dering/dejaggy/direction\n"); + } else if (!strncmp(parm[2], "01", 2)) { + vpp_sr3_enhance_enable(0x1); + pr_info("enable core0 sr3 dering/dejaggy/direction\n"); + } + } else if (!strncmp(parm[1], "core1", 2)) { + if (!strncmp(parm[2], "10", 2)) { + vpp_sr3_enhance_enable(0x10); + pr_info("disable core1 sr3 dering/dejaggy/direction\n"); + } else if (!strncmp(parm[2], "11", 2)) { + vpp_sr3_enhance_enable(0x11); + pr_info("enable core1 sr3 dering/dejaggy/direction\n"); + } + } + } else if (!strncmp(parm[0], "wb", 2)) { + if (!strncmp(parm[1], "enable", 6)) { + amvecm_wb_enable(1); + pr_info("enable wb\n"); + } else if (!strncmp(parm[1], "disable", 7)) { + amvecm_wb_enable(0); + pr_info("disable wb\n"); + } + } else if (!strncmp(parm[0], "gamma", 5)) { + if (!strncmp(parm[1], "enable", 6)) { + vecm_latch_flag |= FLAG_GAMMA_TABLE_EN; /* gamma off */ + pr_info("enable gamma\n"); + } else if (!strncmp(parm[1], "disable", 7)) { + vecm_latch_flag |= FLAG_GAMMA_TABLE_DIS;/* gamma off */ + pr_info("disable gamma\n"); + } + } else if (!strncmp(parm[0], "sr", 2)) { + if (!strncmp(parm[1], "peaking_en", 10)) { + amvecm_sharpness_debug(0); + pr_info("enable peaking\n"); + } else if (!strncmp(parm[1], "peaking_dis", 11)) { + amvecm_sharpness_debug(1); + pr_info("disable peaking\n"); + } else if (!strncmp(parm[1], "lcti_en", 7)) { + amvecm_sharpness_debug(2); + pr_info("enable lti cti\n"); + } else if (!strncmp(parm[1], "lcti_dis", 8)) { + amvecm_sharpness_debug(3); + pr_info("disable lti cti\n"); + } + } else if (!strncmp(parm[0], "cm", 2)) { + if (!strncmp(parm[1], "enable", 6)) { + amcm_enable(); + pr_info("enable cm\n"); + } else if (!strncmp(parm[1], "disable", 7)) { + amcm_disable(); + pr_info("disable cm\n"); + } + } else if (!strncmp(parm[0], "dnlp", 4)) { + if (!strncmp(parm[1], "enable", 6)) { + ve_enable_dnlp(); + pr_info("enable dnlp\n"); + } else if (!strncmp(parm[1], "disable", 7)) { + ve_disable_dnlp(); + pr_info("disable dnlp\n"); + } + } else if (!strncmp(parm[0], "vpp_pq", 6)) { + if (!strncmp(parm[1], "enable", 6)) { + amvecm_pq_enable(1); + pr_info("enable vpp_pq\n"); + } else if (!strncmp(parm[1], "disable", 7)) { + amvecm_pq_enable(0); + pr_info("disable vpp_pq\n"); + } + } + + kfree(buf_orig); + return count; +} + +/* supported mode: IPT_TUNNEL/HDR10/SDR10 */ +static const int dv_mode_table[6] = { + 5, /*DOLBY_VISION_OUTPUT_MODE_BYPASS*/ + 0, /*DOLBY_VISION_OUTPUT_MODE_IPT*/ + 1, /*DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL*/ + 2, /*DOLBY_VISION_OUTPUT_MODE_HDR10*/ + 3, /*DOLBY_VISION_OUTPUT_MODE_SDR10*/ + 4, /*DOLBY_VISION_OUTPUT_MODE_SDR8*/ +}; + +static const char dv_mode_str[6][12] = { + "IPT", + "IPT_TUNNEL", + "HDR10", + "SDR10", + "SDR8", + "BYPASS" +}; + +static ssize_t amvecm_dv_mode_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + pr_info("usage: echo mode > /sys/class/amvecm/dv_mode\n"); + pr_info("\tDOLBY_VISION_OUTPUT_MODE_BYPASS 0\n"); + pr_info("\tDOLBY_VISION_OUTPUT_MODE_IPT 1\n"); + pr_info("\tDOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL 2\n"); + pr_info("\tDOLBY_VISION_OUTPUT_MODE_HDR10 3\n"); + pr_info("\tDOLBY_VISION_OUTPUT_MODE_SDR10 4\n"); + pr_info("\tDOLBY_VISION_OUTPUT_MODE_SDR8 5\n"); + if (is_meson_gxm_cpu() && is_dolby_vision_enable()) + pr_info("current dv_mode = %s\n", + dv_mode_str[get_dolby_vision_mode()]); + else + pr_info("current dv_mode = off\n"); + return 0; +} + +static ssize_t amvecm_dv_mode_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + size_t r; + int val; + + if (is_meson_gxm_cpu()) { + r = sscanf(buf, "0x%x", &val); + if ((r != 1)) + return -EINVAL; + if ((val >= 0) && (val < 6)) + set_dolby_vision_mode(dv_mode_table[val]); + else if (val & 0x200) + dolby_vision_dump_struct(); + else if (val & 0x70) + dolby_vision_dump_setting(val); + } + return count; +} + +/* #if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) */ +void init_sharpness(void) +{ + /*probe close sr0 peaking for switch on video*/ + WRITE_VPP_REG_BITS(VPP_SRSHARP0_CTRL, 1, 0, 1); + /*WRITE_VPP_REG_BITS(VPP_SRSHARP1_CTRL, 1,0,1);*/ + WRITE_VPP_REG_BITS(SRSHARP0_SHARP_PK_NR_ENABLE, 0, 1, 1); + + WRITE_VPP_REG_BITS(VPP_SRSHARP1_CTRL, 1, 0, 1); + + if (is_meson_txl_cpu()) { + WRITE_VPP_REG_BITS(SRSHARP1_PK_FINALGAIN_HP_BP, 2, 16, 2); + + /*sr0 sr1 chroma filter bypass*/ + WRITE_VPP_REG(SRSHARP0_SHARP_SR2_CBIC_HCOEF0, 0x4000); + WRITE_VPP_REG(SRSHARP0_SHARP_SR2_CBIC_VCOEF0, 0x4000); + WRITE_VPP_REG(SRSHARP1_SHARP_SR2_CBIC_HCOEF0, 0x4000); + WRITE_VPP_REG(SRSHARP1_SHARP_SR2_CBIC_VCOEF0, 0x4000); + } +} +/* #endif*/ + +static void amvecm_gamma_init(bool en) +{ + unsigned int i; + unsigned short data[256]; + + if (en) { + WRITE_VPP_REG_BITS(L_GAMMA_CNTL_PORT, + 0, GAMMA_EN, 1); + + for (i = 0; i < 256; i++) + data[i] = i << 2; + init_write_gamma_table( + data, + H_SEL_R); + init_write_gamma_table( + data, + H_SEL_G); + init_write_gamma_table( + data, + H_SEL_B); + } +} +static void amvecm_wb_init(bool en) +{ + if (en) { + WRITE_VPP_REG(VPP_GAINOFF_CTRL0, + (1024 << 16) | 1024); + WRITE_VPP_REG(VPP_GAINOFF_CTRL1, + (1024 << 16)); + } + + WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, en, 31, 1); +} + +static struct class_attribute amvecm_class_attrs[] = { + __ATTR(debug, 0644, + amvecm_debug_show, amvecm_debug_store), + __ATTR(dnlp, 0644, + amvecm_dnlp_show, amvecm_dnlp_store), + __ATTR(brightness, 0644, + amvecm_brightness_show, amvecm_brightness_store), + __ATTR(contrast, 0644, + amvecm_contrast_show, amvecm_contrast_store), + __ATTR(saturation_hue, 0644, + amvecm_saturation_hue_show, + amvecm_saturation_hue_store), + __ATTR(saturation_hue_pre, 0644, + amvecm_saturation_hue_pre_show, + amvecm_saturation_hue_pre_store), + __ATTR(saturation_hue_post, 0644, + amvecm_saturation_hue_post_show, + amvecm_saturation_hue_post_store), + __ATTR(cm2, 0644, + amvecm_cm2_show, + amvecm_cm2_store), + __ATTR(gamma, 0644, + amvecm_gamma_show, + amvecm_gamma_store), + __ATTR(wb, 0644, + amvecm_wb_show, + amvecm_wb_store), + __ATTR(brightness1, 0644, + video_adj1_brightness_show, + video_adj1_brightness_store), + __ATTR(contrast1, 0644, + video_adj1_contrast_show, video_adj1_contrast_store), + __ATTR(brightness2, 0644, + video_adj2_brightness_show, video_adj2_brightness_store), + __ATTR(contrast2, 0644, + video_adj2_contrast_show, video_adj2_contrast_store), + __ATTR(help, 0644, + amvecm_usage_show, NULL), +/* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESONG9TV) */ + __ATTR(sync_3d, 0644, + amvecm_3d_sync_show, + amvecm_3d_sync_store), + __ATTR(vlock, 0644, + amvecm_vlock_show, + amvecm_vlock_store), + __ATTR(matrix_set, 0644, + amvecm_set_post_matrix_show, amvecm_set_post_matrix_store), + __ATTR(matrix_pos, 0644, + amvecm_post_matrix_pos_show, amvecm_post_matrix_pos_store), + __ATTR(matrix_data, 0644, + amvecm_post_matrix_data_show, amvecm_post_matrix_data_store), + __ATTR(dump_reg, 0644, + amvecm_dump_reg_show, amvecm_dump_reg_store), + __ATTR(sr1_reg, 0644, + amvecm_sr1_reg_show, amvecm_sr1_reg_store), + __ATTR(write_sr1_reg_val, 0644, + amvecm_write_sr1_reg_val_show, amvecm_write_sr1_reg_val_store), + __ATTR(dump_vpp_hist, 0644, + amvecm_dump_vpp_hist_show, amvecm_dump_vpp_hist_store), + __ATTR(hdr_dbg, 0644, + amvecm_hdr_dbg_show, amvecm_hdr_dbg_store), + __ATTR(hdr_reg, 0644, + amvecm_hdr_reg_show, amvecm_hdr_reg_store), + __ATTR(gamma_pattern, 0644, + set_gamma_pattern_show, set_gamma_pattern_store), + __ATTR(pc_mode, 0644, + amvecm_pc_mode_show, amvecm_pc_mode_store), + __ATTR(set_hdr_289lut, 0644, + set_hdr_289lut_show, set_hdr_289lut_store), + __ATTR(vpp_demo, 0644, + amvecm_vpp_demo_show, amvecm_vpp_demo_store), + __ATTR(dv_mode, 0644, + amvecm_dv_mode_show, amvecm_dv_mode_store), + __ATTR_NULL +}; + +static const struct file_operations amvecm_fops = { + .owner = THIS_MODULE, + .open = amvecm_open, + .release = amvecm_release, + .unlocked_ioctl = amvecm_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = amvecm_compat_ioctl, +#endif +}; +static void aml_vecm_dt_parse(struct platform_device *pdev) +{ + struct device_node *node; + unsigned int val; + int ret; + + node = pdev->dev.of_node; + /* get integer value */ + if (node) { + ret = of_property_read_u32(node, "gamma_en", &val); + if (ret) + pr_info("Can't find gamma_en.\n"); + else + gamma_en = val; + ret = of_property_read_u32(node, "wb_en", &val); + if (ret) + pr_info("Can't find wb_en.\n"); + else + wb_en = val; + ret = of_property_read_u32(node, "cm_en", &val); + if (ret) + pr_info("Can't find cm_en.\n"); + else + cm_en = val; + } + /* init module status */ + amvecm_wb_init(wb_en); + amvecm_gamma_init(gamma_en); + if (!is_dolby_vision_enable()) + WRITE_VPP_REG_BITS(VPP_MISC, 1, 28, 1); + if (cm_en) + amcm_enable(); + else + amcm_disable(); + /* WRITE_VPP_REG_BITS(VPP_MISC, cm_en, 28, 1); */ +} + +#ifdef CONFIG_AML_LCD +static int aml_lcd_gamma_notifier(struct notifier_block *nb, + unsigned long event, void *data) +{ + if ((event & LCD_EVENT_GAMMA_UPDATE) == 0) + return NOTIFY_DONE; + +#if 0 + vpp_set_lcd_gamma_table(video_gamma_table_r.data, H_SEL_R); + vpp_set_lcd_gamma_table(video_gamma_table_g.data, H_SEL_G); + vpp_set_lcd_gamma_table(video_gamma_table_b.data, H_SEL_B); +#else + vecm_latch_flag |= FLAG_GAMMA_TABLE_R; + vecm_latch_flag |= FLAG_GAMMA_TABLE_G; + vecm_latch_flag |= FLAG_GAMMA_TABLE_B; +#endif + + return NOTIFY_OK; +} + +static struct notifier_block aml_lcd_gamma_nb = { + .notifier_call = aml_lcd_gamma_notifier, +}; +#endif +static int aml_vecm_probe(struct platform_device *pdev) +{ + int ret = 0; + int i = 0; + + struct amvecm_dev_s *devp = &amvecm_dev; + + memset(devp, 0, (sizeof(struct amvecm_dev_s))); + pr_info("\n VECM probe start\n"); + ret = alloc_chrdev_region(&devp->devno, 0, 1, AMVECM_NAME); + if (ret < 0) + goto fail_alloc_region; + + devp->clsp = class_create(THIS_MODULE, AMVECM_CLASS_NAME); + if (IS_ERR(devp->clsp)) { + ret = PTR_ERR(devp->clsp); + goto fail_create_class; + } + for (i = 0; amvecm_class_attrs[i].attr.name; i++) { + if (class_create_file(devp->clsp, &amvecm_class_attrs[i]) < 0) + goto fail_class_create_file; + } + cdev_init(&devp->cdev, &amvecm_fops); + devp->cdev.owner = THIS_MODULE; + ret = cdev_add(&devp->cdev, devp->devno, 1); + if (ret) + goto fail_add_cdev; + + devp->dev = device_create(devp->clsp, NULL, devp->devno, + NULL, AMVECM_NAME); + if (IS_ERR(devp->dev)) { + ret = PTR_ERR(devp->dev); + goto fail_create_device; + } + + spin_lock_init(&vpp_lcd_gamma_lock); +#ifdef CONFIG_AML_LCD + ret = aml_lcd_notifier_register(&aml_lcd_gamma_nb); + if (ret) + pr_info("register aml_lcd_gamma_notifier failed\n"); +#endif + + amvecm_hiu_reg_base = ioremap(HIU_REG_BASE, 0x2000); + + /* #if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) */ + if (is_meson_gxtvbb_cpu() || is_meson_txl_cpu()) + init_sharpness(); + /* #endif */ + vpp_get_hist_en(); + + memset(&vpp_hist_param.vpp_histgram[0], + 0, sizeof(unsigned short) * 64); + /* box sdr_mode:auto, tv sdr_mode:off */ + /* disable contrast and saturation adjustment for HDR on TV */ + /* disable SDR to HDR convert on TV */ + if (is_meson_gxl_cpu() || is_meson_gxm_cpu()) { + sdr_mode = 0; + hdr_flag = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + } else { + sdr_mode = 0; + hdr_flag = (1 << 0) | (1 << 1) | (0 << 2) | (0 << 3); + } + aml_vecm_dt_parse(pdev); + if (is_meson_gxm_cpu()) + dolby_vision_init_receiver(); + probe_ok = 1; + pr_info("%s: ok\n", __func__); + return 0; + +fail_create_device: + pr_info("[amvecm.] : amvecm device create error.\n"); + cdev_del(&devp->cdev); +fail_add_cdev: + pr_info("[amvecm.] : amvecm add device error.\n"); + kfree(devp); +fail_class_create_file: + pr_info("[amvecm.] : amvecm class create file error.\n"); + for (i = 0; amvecm_class_attrs[i].attr.name; i++) { + class_remove_file(devp->clsp, + &amvecm_class_attrs[i]); + } + class_destroy(devp->clsp); +fail_create_class: + pr_info("[amvecm.] : amvecm class create error.\n"); + unregister_chrdev_region(devp->devno, 1); +fail_alloc_region: + pr_info("[amvecm.] : amvecm alloc error.\n"); + pr_info("[amvecm.] : amvecm_init.\n"); + return ret; +} + +static int __exit aml_vecm_remove(struct platform_device *pdev) +{ + struct amvecm_dev_s *devp = &amvecm_dev; + + device_destroy(devp->clsp, devp->devno); + cdev_del(&devp->cdev); + class_destroy(devp->clsp); + unregister_chrdev_region(devp->devno, 1); + kfree(devp); +#ifdef CONFIG_AML_LCD + aml_lcd_notifier_unregister(&aml_lcd_gamma_nb); +#endif + probe_ok = 0; + pr_info("[amvecm.] : amvecm_exit.\n"); + return 0; +} + +#ifdef CONFIG_PM +static int amvecm_drv_suspend(struct platform_device *pdev, + pm_message_t state) +{ + if (probe_ok == 1) + probe_ok = 0; + pr_info("amvecm: suspend module\n"); + return 0; +} + +static int amvecm_drv_resume(struct platform_device *pdev) +{ + if (probe_ok == 0) + probe_ok = 1; + + pr_info("amvecm: resume module\n"); + return 0; +} +#endif + + +static const struct of_device_id aml_vecm_dt_match[] = { + { + .compatible = "amlogic, vecm", + }, + {}, +}; + +static struct platform_driver aml_vecm_driver = { + .driver = { + .name = "aml_vecm", + .owner = THIS_MODULE, + .of_match_table = aml_vecm_dt_match, + }, + .probe = aml_vecm_probe, + .remove = __exit_p(aml_vecm_remove), +#ifdef CONFIG_PM + .suspend = amvecm_drv_suspend, + .resume = amvecm_drv_resume, +#endif + +}; + +static int __init aml_vecm_init(void) +{ + pr_info("module init\n"); + /* remap the hiu bus */ + if (platform_driver_register(&aml_vecm_driver)) { + pr_err("failed to register bl driver module\n"); + return -ENODEV; + } + + return 0; +} + +static void __exit aml_vecm_exit(void) +{ + pr_info("module exit\n"); + platform_driver_unregister(&aml_vecm_driver); +} + +module_init(aml_vecm_init); +module_exit(aml_vecm_exit); + +MODULE_DESCRIPTION("AMLOGIC amvecm driver"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h b/drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h new file mode 100644 index 0000000..ca433e4 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h @@ -0,0 +1,84 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __AMVECM_VLOCK_REGMAP_H +#define __AMVECM_VLOCK_REGMAP_H + +#include + +/* #if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) */ +/* TV_ENC_LCD720x480 */ +static struct am_regs_s vlock_enc_lcd720x480 = { + 20, + { + /* optimize */ + {REG_TYPE_VCBUS, 0x3000, 0xffffffff, 0xE0f50f1b }, + {REG_TYPE_VCBUS, 0x3001, 0xffffffff, 0x41E3c3c }, + {REG_TYPE_VCBUS, 0x3002, 0xffffffff, 0x6000000 }, + {REG_TYPE_VCBUS, 0x3003, 0xffffffff, 0x40280280 }, + {REG_TYPE_VCBUS, 0x3004, 0xffffffff, 0x280280 }, + {REG_TYPE_VCBUS, 0x3005, 0xffffffff, 0x8020000 }, + {REG_TYPE_VCBUS, 0x3006, 0xffffffff, 0x0008000 }, + {REG_TYPE_VCBUS, 0x3007, 0xffffffff, 0x6000000 }, + {REG_TYPE_VCBUS, 0x3008, 0xffffffff, 0x6000000 }, + {REG_TYPE_VCBUS, 0x3009, 0xffffffff, 0x0008000 }, + {REG_TYPE_VCBUS, 0x300a, 0xffffffff, 0x8000000 }, + {REG_TYPE_VCBUS, 0x300b, 0xffffffff, 0x0008000 }, + {REG_TYPE_VCBUS, 0x300c, 0xffffffff, 0xa000000 }, + {REG_TYPE_VCBUS, 0x300d, 0xffffffff, 0x0004000 }, + {REG_TYPE_VCBUS, 0x3010, 0xffffffff, 0x20001000 }, + {REG_TYPE_VCBUS, 0x3016, 0xffffffff, 0x18000 }, + {REG_TYPE_VCBUS, 0x3017, 0xffffffff, 0x01080 }, + {REG_TYPE_VCBUS, 0x301d, 0xffffffff, 0x30501080 }, + {REG_TYPE_VCBUS, 0x301e, 0xffffffff, 0x7 }, + {REG_TYPE_VCBUS, 0x301f, 0xffffffff, 0x6000000 }, + {0} + } +}; +/* out:TV_ENC_LCD1920x1080P60;in:50hz pal av */ +static struct am_regs_s vlock_pll_in50hz_out60hz = { + 20, + { + /* optimize */ + {REG_TYPE_VCBUS, 0x3000, 0xffffffff, 0x07f13f1b }, + {REG_TYPE_VCBUS, 0x3001, 0xffffffff, 0x04053c32 }, + {REG_TYPE_VCBUS, 0x3002, 0xffffffff, 0x06000000 }, + {REG_TYPE_VCBUS, 0x3003, 0xffffffff, 0x2055c55c }, + {REG_TYPE_VCBUS, 0x3004, 0xffffffff, 0x0065c65c }, + {REG_TYPE_VCBUS, 0x3005, 0xffffffff, 0x00080000 }, + {REG_TYPE_VCBUS, 0x3006, 0xffffffff, 0x00070000 }, + {REG_TYPE_VCBUS, 0x3007, 0xffffffff, 0x00000000 }, + {REG_TYPE_VCBUS, 0x3008, 0xffffffff, 0x00000000 }, + {REG_TYPE_VCBUS, 0x3009, 0xffffffff, 0x00100000 }, + {REG_TYPE_VCBUS, 0x300a, 0xffffffff, 0x00100000 }, + {REG_TYPE_VCBUS, 0x300b, 0xffffffff, 0x00100000 }, + {REG_TYPE_VCBUS, 0x300c, 0xffffffff, 0x00010000 }, + {REG_TYPE_VCBUS, 0x300d, 0xffffffff, 0x00004000 }, + {REG_TYPE_VCBUS, 0x3010, 0xffffffff, 0x20001000 }, + {REG_TYPE_VCBUS, 0x3016, 0xffffffff, 0x0003de00 }, + {REG_TYPE_VCBUS, 0x3017, 0xffffffff, 0x00001080 }, + {REG_TYPE_VCBUS, 0x301d, 0xffffffff, 0x30501080 }, + {REG_TYPE_VCBUS, 0x301e, 0xffffffff, 0x00000007 }, + {REG_TYPE_VCBUS, 0x301f, 0xffffffff, 0x06000000 }, + {0} + } +}; + +/* #endif */ + +#endif + diff --git a/drivers/amlogic/media/enhancement/amvecm/arch/cm_regs.h b/drivers/amlogic/media/enhancement/amvecm/arch/cm_regs.h new file mode 100644 index 0000000..f9cee00 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/arch/cm_regs.h @@ -0,0 +1,193 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/arch/cm_regs.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __CM_REG_H +#define __CM_REG_H + +/* ********************************************************** */ +/* ******** COLOR MANAGEMENT INDIRECT REGISTERS ******** */ +/* ******************************************************* */ + +/* #define CHROMA_GAIN_REG00 0x00 */ +/* #define CHROMA_GAIN_REG01 0x06 */ +/* #define CHROMA_GAIN_REG02 0x0C */ +/* #define CHROMA_GAIN_REG03 0x12 */ +/* #define CHROMA_GAIN_REG04 0x18 */ +/* #define CHROMA_GAIN_REG05 0x1E */ +/* #define CHROMA_GAIN_REG06 0x24 */ +/* #define CHROMA_GAIN_REG07 0x2A */ +#define SAT_EN_BIT 31 +#define SAT_EN_WID 1 +#define SAT_INC_BIT 27 +#define SAT_INC_WID 1 +#define SAT_CENTRAL_EN_BIT 25 +#define SAT_CENTRAL_EN_WID 2 +#define SAT_SHAPE_BIT 24 +#define SAT_SHAPE_WID 1 +#define SAT_GAIN_BIT 16 +#define SAT_GAIN_WID 8 +#define HUE_EN_BIT 15 +#define HUE_EN_WID 1 +#define HUE_CLOCKWISE_BIT 11 +#define HUE_CLOCKWISE_WID 1 +#define HUE_CENTRAL_EN_BIT 9 +#define HUE_CENTRAL_EN_WID 2 +#define HUE_SHAPE_BIT 8 +#define HUE_SHAPE_WID 1 +#define HUE_GAIN_BIT 0 +#define HUE_GAIN_WID 8 + +/* #define HUE_HUE_RANGE_REG00 0x01 */ +/* #define HUE_HUE_RANGE_REG01 0x07 */ +/* #define HUE_HUE_RANGE_REG02 0x0D */ +/* #define HUE_HUE_RANGE_REG03 0x13 */ +/* #define HUE_HUE_RANGE_REG04 0x19 */ +/* #define HUE_HUE_RANGE_REG05 0x1F */ +/* #define HUE_HUE_RANGE_REG06 0x25 */ +/* #define HUE_HUE_RANGE_REG07 0x2B */ +#define HUE_SHF_RAN_BIT 16 +#define HUE_SHF_RAN_WID 8 +#define SYM_EN_BIT 15 +#define SYM_EN_WID 1 +#define HUE_SHF_STA_BIT 0 +#define HUE_SHF_STA_WID 15 + +/* #define HUE_RANGE_INV_REG00 0x02 */ +/* #define HUE_RANGE_INV_REG01 0x08 */ +/* #define HUE_RANGE_INV_REG02 0x0E */ +/* #define HUE_RANGE_INV_REG03 0x14 */ +/* #define HUE_RANGE_INV_REG04 0x1A */ +/* #define HUE_RANGE_INV_REG05 0x20 */ +/* #define HUE_RANGE_INV_REG06 0x26 */ +/* #define HUE_RANGE_INV_REG07 0x2C */ +#define HUE_SHF_RAN_INV_BIT 0 +#define HUE_SHF_RAN_INV_WID 16 + +/* #define HUE_LUM_RANGE_REG00 0x03 */ +/* #define HUE_LUM_RANGE_REG01 0x09 */ +/* #define HUE_LUM_RANGE_REG02 0x0F */ +/* #define HUE_LUM_RANGE_REG03 0x15 */ +/* #define HUE_LUM_RANGE_REG04 0x1B */ +/* #define HUE_LUM_RANGE_REG05 0x21 */ +/* #define HUE_LUM_RANGE_REG06 0x27 */ +/* #define HUE_LUM_RANGE_REG07 0x2D */ +/* for belowing each low, high, low_slope, high_slope group: */ +/* a_____________b */ +/* / \ */ +/* / \ */ +/* / \ */ +/* / \ */ +/* ______/_____________________\________ */ +/* low high */ +/* a = low + 2^low_slope */ +/* low_slope <= 7; high_slope <= 7 */ +/* b >= a */ + +#define SAT_LUM_L_BIT 24 +#define SAT_LUM_L_WID 8 +#define HUE_LUM_H_SLOPE_BIT 20 +#define HUE_LUM_H_SLOPE_WID 4 +#define HUE_LUM_L_SLOPE_BIT 16 +#define HUE_LUM_L_SLOPE_WID 4 +#define HUE_LUM_H_BIT 8 +#define HUE_LUM_H_WID 8 +#define HUE_LUM_L_BIT 0 +#define HUE_LUM_L_WID 8 + +/* #define HUE_SAT_RANGE_REG00 0x04 */ +/* #define HUE_SAT_RANGE_REG01 0x0A */ +/* #define HUE_SAT_RANGE_REG02 0x10 */ +/* #define HUE_SAT_RANGE_REG03 0x16 */ +/* #define HUE_SAT_RANGE_REG04 0x1C */ +/* #define HUE_SAT_RANGE_REG05 0x22 */ +/* #define HUE_SAT_RANGE_REG06 0x28 */ +/* #define HUE_SAT_RANGE_REG07 0x2E */ +#define SAT_LUM_H_BIT 24 +#define SAT_LUM_H_WID 8 +#define HUE_SAT_H_SLOPE_BIT 20 +#define HUE_SAT_H_SLOPE_WID 4 +#define HUE_SAT_L_SLOPE_BIT 16 +#define HUE_SAT_L_SLOPE_WID 4 +#define HUE_SAT_H_BIT 8 +#define HUE_SAT_H_WID 8 +#define HUE_SAT_L_BIT 0 +#define HUE_SAT_L_WID 8 + +/* #define SAT_SAT_RANGE_REG00 0x05 */ +/* #define SAT_SAT_RANGE_REG01 0x0B */ +/* #define SAT_SAT_RANGE_REG02 0x11 */ +/* #define SAT_SAT_RANGE_REG03 0x17 */ +/* #define SAT_SAT_RANGE_REG04 0x1D */ +/* #define SAT_SAT_RANGE_REG05 0x23 */ +/* #define SAT_SAT_RANGE_REG06 0x29 */ +/* #define SAT_SAT_RANGE_REG07 0x2F */ +#define SAT_LUM_H_SLOPE_BIT 28 +#define SAT_LUM_H_SLOPE_WID 4 +#define SAT_LUM_L_SLOPE_BIT 24 +#define SAT_LUM_L_SLOPE_WID 4 +#define SAT_SAT_H_SLOPE_BIT 20 +#define SAT_SAT_H_SLOPE_WID 4 +#define SAT_SAT_L_SLOPE_BIT 16 +#define SAT_SAT_L_SLOPE_WID 4 +#define SAT_SAT_H_BIT 8 +#define SAT_SAT_H_WID 8 +#define SAT_SAT_L_BIT 0 +#define SAT_SAT_L_WID 8 + +/* #define REG_CHROMA_CONTROL 0x30 */ +#define CHROMA_EN_BIT 31 +#define CHROMA_EN_WID 1 +#if defined(CONFIG_ARCH_MESON) +/* 1'b0: demo adjust on right, 1'b1: demo adjust on left */ +#elif defined(CONFIG_ARCH_MESON2) +/* 2'b00: demo adjust on top, 2'b01: demo adjust on bottom */ +/* 2'b10: demo adjust on left,2'b11: demo adjust on right */ +#endif +#define CM_DEMO_POS_BIT 22 +#define CM_DEMO_POS_WID 2 +#define DEMO_HLIGHT_ADJ_BIT 21 +#define DEMO_HLIGHT_ADJ_WID 1 +#define DEMO_EN_BIT 20 +#define DEMO_EN_WID 1 +#define CM_DEMO_WID_BIT 8 +#define CM_DEMO_WID_WID 12 +#define SAT_SEL_BIT 6 +#define SAT_SEL_WID 1 +#define UV_ADJ_EN_BIT 5 +#define UV_ADJ_EN_WID 1 +#define RGB_TO_HUE_EN_BIT 2 +#define RGB_TO_HUE_EN_WID 1 +/* 2'b00: 601(16-235) 2'b01: 709(16-235) */ +/* 2'b10: 601(0-255) 2'b11: 709(0-255) */ +#define CSC_SEL_BIT 0 +#define CSC_SEL_WID 2 + +/* #if defined(CONFIG_ARCH_MESON2) */ +/* #define REG_DEMO_CENTER_BAR 0x31 // default 32h'0 */ +#define CM_CBAR_EN_BIT 31 /* center bar enable */ +#define CM_CBAR_EN_WID 1 +#define CM_CBAR_WID_BIT 24 /* center bar width (*2) */ +#define CM_CBAR_WID_WID 4 +#define CM_CBAR_CR_BIT 16 /* center bar Cr (*4) */ +#define CM_CBAR_CR_WID 8 +#define CM_CBAR_CB_BIT 8 /* center bar Cb (*4) */ +#define CM_CBAR_CB_WID 8 +#define CM_CBAR_Y_BIT 0 /* center bar y (*4) */ +#define CM_CBAR_Y_WID 8 +/* #endif */ + +#endif /* _CM_REG_H */ diff --git a/drivers/amlogic/media/enhancement/amvecm/arch/hdr_curve.h b/drivers/amlogic/media/enhancement/amvecm/arch/hdr_curve.h new file mode 100644 index 0000000..b5b167a --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/arch/hdr_curve.h @@ -0,0 +1,1130 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/arch/hdr_curve.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef HDR_CURVE_H +#define HDR_CURVE_H + +/*hdr eotf & oetf curve setting*/ +/*panel from 260nit to 1000nit*/ +/*matlab parameters: + *% default setting for TV: + *panel_lum_max = 260; % nits, maximum panel luminance (260~1000) + *alpha_low = 0.075; % 0: no dark boost; otherwise add dark boost + *panel_gamma = 2.2; % panel gamma 1.8, 2.0, 2.2, ... + + *osd_merge_lut = 1; % whether merge osd + eo/oe lut to solve table resolution issue + + *src_lum_max = 10000; % nits, maximum of 10000 nits + *dsp_lum_max = 10000; % nits, maximum luma of display luminance + *panel_lum_max = min(1000, panel_lum_max); + *panel_lum_max = max(100, panel_lum_max) + *panel_soft_clip_th = 912; + *hlg_lum_max = 1200; % nits, use HLG curve instead of 709 gamma + *lum_norm = 10000; % nits, 2084 maximum lum + *eotf_scl = 2^(floor(log2(10000/panel_lum_max))-1) + % to increase precision could be 1,2,4,8,16 + *eo_scale = 1; % eotf scale + *eotf_norm = (2^14)*eo_scale ; % 14bit(16384)=1.0; 15bit(32768)=1.0 + *fact_scl = 1 / eo_scale; % min(max(1,src_lum_max/dsp_lum_max),4); + % factors to be applied to linear RGB before going to LUT289 + *oetf_norm = (2^14); % oetf normalization + *oetf_scl = max(1,hlg_lum_max/100); % 1200 + *blx_soft = 0; % 0: means not black soft cliping; + otherwise soft clipping, e.g. 2*4 +*/ +unsigned int eotf_33_2084_table[][33] = { + {/*260*/ + 0, 4, 9, 16, 27, 43, 66, 101, + 149, 219, 315, 449, 644, 911, 1273, 1762, + 2418, 3297, 4468, 6028, 8100, 10851, 14501, 14938, + 15304, 15605, 15847, 16035, 16176, 16276, 16339, 16373, + 16383 + }, + {/*280*/ + 0, 4, 9, 16, 27, 43, 66, 101, + 149, 219, 315, 449, 644, 911, 1273, 1762, + 2418, 3297, 4468, 6028, 8100, 10851, 14501, 14938, + 15304, 15605, 15847, 16035, 16176, 16276, 16339, 16373, + 16383 + }, + {/*300*/ + 0, 4, 9, 16, 27, 43, 66, 101, + 149, 219, 315, 449, 644, 911, 1273, 1762, + 2418, 3297, 4468, 6028, 8100, 10851, 14501, 14938, + 15304, 15605, 15847, 16035, 16176, 16276, 16339, 16373, + 16383 + }, + {/*320*/ + 0, 3, 6, 11, 18, 27, 40, 58, + 84, 119, 169, 237, 329, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 + }, + {/*340*/ + 0, 3, 6, 11, 18, 27, 40, 58, + 84, 119, 169, 237, 329, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 + }, + {/*360*/ + 0, 3, 6, 11, 18, 27, 40, 58, + 84, 119, 169, 237, 329, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 + }, + {/*380*/ + 0, 3, 6, 11, 18, 27, 40, 58, + 84, 119, 169, 237, 329, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 + }, + {/*400*/ + 0, 3, 6, 11, 18, 27, 40, 58, + 84, 119, 169, 237, 329, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 + }, + {/*420*/ + 0, 3, 6, 11, 18, 27, 40, 58, + 84, 119, 169, 237, 329, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 + }, + {/*440*/ + 0, 3, 6, 11, 18, 27, 40, 58, + 84, 119, 169, 237, 329, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 + }, + {/*460*/ + 0, 3, 6, 11, 18, 27, 40, 58, + 84, 119, 169, 237, 329, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 + }, + {/*480*/ + 0, 3, 6, 11, 18, 27, 40, 58, + 84, 119, 169, 237, 329, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 + }, + {/*500*/ + 0, 3, 6, 11, 18, 27, 40, 58, + 84, 119, 169, 237, 329, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 + }, + {/*600*/ + 0, 3, 6, 11, 18, 27, 40, 58, + 84, 119, 169, 237, 329, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 + }, + {/*700*/ + 0, 2, 5, 8, 12, 18, 25, 35, + 49, 68, 93, 128, 175, 239, 325, 440, + 605, 824, 1117, 1507, 2025, 2713, 3625, 4836, + 6445, 8583, 11430, 15228, 15695, 16025, 16237, 16350, + 16383 + }, + {/*800*/ + 0, 2, 5, 8, 12, 18, 25, 35, + 49, 68, 93, 128, 175, 239, 325, 440, + 605, 824, 1117, 1507, 2025, 2713, 3625, 4836, + 6445, 8583, 11430, 15228, 15695, 16025, 16237, 16350, + 16383 + }, + {/*900*/ + 0, 2, 5, 8, 12, 18, 25, 35, + 49, 68, 93, 128, 175, 239, 325, 440, + 605, 824, 1117, 1507, 2025, 2713, 3625, 4836, + 6445, 8583, 11430, 15228, 15695, 16025, 16237, 16350, + 16383 + }, + {/*1000*/ + 0, 2, 5, 8, 12, 18, 25, 35, + 49, 68, 93, 128, 175, 239, 325, 440, + 605, 824, 1117, 1507, 2025, 2713, 3625, 4836, + 6445, 8583, 11430, 15228, 15695, 16025, 16237, 16350, + 16383 + } +}; + +unsigned int oetf_289_gamma22_table[][289] = { + {/*260*/ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 125, 169, 202, 230, 255, 278, 297, + 316, 333, 349, 364, 379, 393, 407, 420, + 433, 445, 457, 468, 479, 489, 500, 510, + 520, 530, 539, 549, 558, 567, 576, 585, + 593, 602, 610, 618, 626, 634, 642, 649, + 657, 664, 671, 678, 686, 693, 701, 708, + 716, 724, 732, 739, 747, 755, 762, 769, + 776, 782, 789, 794, 800, 805, 809, 813, + 816, 819, 821, 823, 826, 828, 830, 832, + 834, 836, 839, 841, 843, 845, 847, 849, + 851, 853, 855, 857, 859, 861, 863, 865, + 867, 869, 871, 873, 875, 877, 879, 880, + 882, 884, 886, 888, 890, 891, 893, 895, + 897, 898, 900, 902, 903, 905, 907, 908, + 910, 912, 913, 915, 916, 918, 920, 921, + 923, 924, 926, 927, 929, 930, 932, 933, + 935, 936, 937, 939, 940, 942, 943, 944, + 946, 947, 948, 950, 951, 952, 953, 955, + 956, 957, 958, 960, 961, 962, 963, 964, + 965, 967, 968, 969, 970, 971, 972, 973, + 974, 975, 976, 977, 978, 979, 980, 981, + 982, 983, 984, 985, 986, 987, 988, 989, + 989, 990, 991, 992, 993, 994, 994, 995, + 996, 997, 997, 998, 999, 1000, 1000, 1001, + 1002, 1002, 1003, 1004, 1004, 1005, 1006, 1006, + 1007, 1007, 1008, 1009, 1009, 1010, 1010, 1011, + 1011, 1012, 1012, 1013, 1013, 1014, 1014, 1014, + 1015, 1015, 1016, 1016, 1016, 1017, 1017, 1017, + 1018, 1018, 1018, 1019, 1019, 1019, 1020, 1020, + 1020, 1020, 1021, 1021, 1021, 1021, 1021, 1022, + 1022, 1022, 1022, 1022, 1022, 1022, 1022, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 + }, + {/*280*/ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 121, 163, 195, 222, 247, 268, 287, + 305, 322, 337, 352, 367, 380, 393, 406, + 418, 430, 441, 452, 463, 473, 483, 493, + 502, 512, 521, 530, 539, 548, 557, 565, + 573, 582, 589, 597, 605, 612, 620, 627, + 634, 641, 648, 655, 662, 669, 677, 684, + 692, 699, 707, 714, 721, 729, 736, 742, + 749, 755, 761, 767, 772, 777, 782, 786, + 789, 792, 794, 797, 799, 802, 804, 806, + 809, 811, 813, 816, 818, 820, 823, 825, + 827, 829, 832, 834, 836, 838, 841, 843, + 845, 847, 849, 851, 853, 855, 858, 860, + 862, 864, 866, 868, 870, 872, 874, 876, + 878, 880, 881, 883, 885, 887, 889, 891, + 893, 895, 896, 898, 900, 902, 903, 905, + 907, 909, 910, 912, 914, 915, 917, 919, + 920, 922, 924, 925, 927, 928, 930, 931, + 933, 934, 936, 937, 939, 940, 942, 943, + 945, 946, 947, 949, 950, 952, 953, 954, + 956, 957, 958, 959, 961, 962, 963, 964, + 966, 967, 968, 969, 970, 971, 973, 974, + 975, 976, 977, 978, 979, 980, 981, 982, + 983, 984, 985, 986, 987, 988, 989, 990, + 991, 992, 993, 993, 994, 995, 996, 997, + 998, 998, 999, 1000, 1001, 1001, 1002, 1003, + 1004, 1004, 1005, 1006, 1006, 1007, 1008, 1008, + 1009, 1009, 1010, 1011, 1011, 1012, 1012, 1013, + 1013, 1014, 1014, 1015, 1015, 1015, 1016, 1016, + 1017, 1017, 1017, 1018, 1018, 1019, 1019, 1019, + 1019, 1020, 1020, 1020, 1021, 1021, 1021, 1021, + 1021, 1022, 1022, 1022, 1022, 1022, 1022, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 + }, + {/*300*/ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 117, 158, 189, 216, 239, 260, 278, + 295, 311, 327, 341, 355, 368, 381, 393, + 405, 417, 428, 438, 449, 458, 468, 478, + 487, 496, 505, 514, 523, 531, 539, 548, + 556, 563, 571, 579, 586, 594, 601, 608, + 615, 622, 628, 635, 642, 648, 655, 661, + 667, 674, 680, 686, 692, 698, 704, 710, + 716, 722, 728, 733, 739, 745, 750, 756, + 761, 767, 772, 778, 783, 789, 795, 801, + 807, 813, 819, 825, 831, 836, 842, 848, + 854, 859, 864, 869, 874, 879, 884, 888, + 892, 895, 899, 902, 905, 907, 909, 910, + 912, 913, 915, 916, 918, 919, 921, 922, + 923, 925, 926, 927, 929, 930, 931, 933, + 934, 935, 937, 938, 939, 940, 942, 943, + 944, 945, 946, 948, 949, 950, 951, 952, + 953, 955, 956, 957, 958, 959, 960, 961, + 962, 963, 964, 965, 966, 967, 968, 969, + 970, 971, 972, 973, 974, 975, 976, 977, + 978, 979, 980, 980, 981, 982, 983, 984, + 985, 986, 986, 987, 988, 989, 990, 990, + 991, 992, 993, 993, 994, 995, 995, 996, + 997, 997, 998, 999, 999, 1000, 1001, 1001, + 1002, 1002, 1003, 1004, 1004, 1005, 1005, 1006, + 1006, 1007, 1007, 1008, 1008, 1009, 1009, 1010, + 1010, 1011, 1011, 1012, 1012, 1013, 1013, 1013, + 1014, 1014, 1015, 1015, 1015, 1016, 1016, 1016, + 1017, 1017, 1017, 1018, 1018, 1018, 1018, 1019, + 1019, 1019, 1019, 1020, 1020, 1020, 1020, 1021, + 1021, 1021, 1021, 1021, 1021, 1022, 1022, 1022, + 1022, 1022, 1022, 1022, 1022, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 + }, + {/*320*/ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 153, 209, 252, 287, 317, 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689, 696, 704, 711, 718, 725, 733, + 740, 747, 754, 762, 770, 778, 786, 794, + 801, 809, 816, 823, 830, 837, 843, 849, + 854, 858, 862, 865, 868, 870, 872, 874, + 875, 877, 879, 881, 882, 884, 886, 888, + 889, 891, 893, 894, 896, 897, 899, 901, + 902, 904, 905, 907, 909, 910, 912, 913, + 915, 916, 918, 919, 920, 922, 923, 925, + 926, 928, 929, 930, 932, 933, 934, 936, + 937, 938, 940, 941, 942, 943, 945, 946, + 947, 948, 949, 951, 952, 953, 954, 955, + 956, 958, 959, 960, 961, 962, 963, 964, + 965, 966, 967, 968, 969, 970, 971, 972, + 973, 974, 975, 976, 977, 978, 979, 980, + 980, 981, 982, 983, 984, 985, 985, 986, + 987, 988, 989, 989, 990, 991, 992, 992, + 993, 994, 995, 995, 996, 997, 997, 998, + 999, 999, 1000, 1001, 1001, 1002, 1002, 1003, + 1003, 1004, 1005, 1005, 1006, 1006, 1007, 1007, + 1008, 1008, 1009, 1009, 1010, 1010, 1011, 1011, + 1011, 1012, 1012, 1013, 1013, 1013, 1014, 1014, + 1015, 1015, 1015, 1016, 1016, 1016, 1017, 1017, + 1017, 1018, 1018, 1018, 1018, 1019, 1019, 1019, + 1019, 1020, 1020, 1020, 1020, 1020, 1021, 1021, + 1021, 1021, 1021, 1021, 1022, 1022, 1022, 1022, + 1022, 1022, 1022, 1022, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 + }, + {/*500*/ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 125, 171, 206, 235, 259, 281, 302, + 321, 339, 356, 371, 386, 401, 414, 427, + 440, 453, 465, 476, 488, 498, 509, 519, + 529, 539, 549, 558, 568, 577, 586, 595, + 603, 612, 620, 628, 637, 645, 652, 660, + 668, 675, 683, 690, 697, 705, 712, 719, + 726, 733, 740, 748, 755, 763, 771, 778, + 786, 793, 801, 808, 814, 821, 827, 832, + 837, 842, 846, 849, 852, 854, 856, 858, + 860, 862, 864, 866, 867, 869, 871, 873, + 875, 877, 879, 880, 882, 884, 886, 887, + 889, 891, 893, 894, 896, 898, 899, 901, + 902, 904, 906, 907, 909, 910, 912, 914, + 915, 917, 918, 920, 921, 923, 924, 925, + 927, 928, 930, 931, 933, 934, 935, 937, + 938, 939, 941, 942, 943, 945, 946, 947, + 948, 950, 951, 952, 953, 954, 956, 957, + 958, 959, 960, 961, 962, 963, 965, 966, + 967, 968, 969, 970, 971, 972, 973, 974, + 975, 976, 977, 978, 979, 980, 981, 981, + 982, 983, 984, 985, 986, 987, 987, 988, + 989, 990, 991, 991, 992, 993, 994, 995, + 995, 996, 997, 997, 998, 999, 999, 1000, + 1001, 1001, 1002, 1003, 1003, 1004, 1004, 1005, + 1006, 1006, 1007, 1007, 1008, 1008, 1009, 1009, + 1010, 1010, 1011, 1011, 1012, 1012, 1012, 1013, + 1013, 1014, 1014, 1015, 1015, 1015, 1016, 1016, + 1016, 1017, 1017, 1017, 1018, 1018, 1018, 1019, + 1019, 1019, 1019, 1020, 1020, 1020, 1020, 1020, + 1021, 1021, 1021, 1021, 1021, 1022, 1022, 1022, + 1022, 1022, 1022, 1022, 1022, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 + }, + {/*600*/ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 115, 157, 189, 215, 238, 259, 278, + 296, 312, 327, 342, 356, 369, 381, 394, + 405, 417, 428, 438, 449, 459, 468, 478, + 487, 496, 505, 514, 523, 531, 540, 548, + 556, 564, 571, 579, 586, 594, 601, 608, + 615, 622, 629, 636, 642, 649, 655, 662, + 668, 675, 681, 688, 695, 702, 709, 715, + 722, 729, 735, 741, 747, 753, 759, 764, + 769, 773, 777, 781, 784, 786, 789, 791, + 794, 796, 799, 801, 803, 806, 808, 811, + 813, 815, 818, 820, 822, 825, 827, 829, + 831, 834, 836, 838, 840, 842, 845, 847, + 849, 851, 853, 855, 857, 860, 862, 864, + 866, 868, 870, 872, 874, 876, 878, 880, + 882, 884, 886, 887, 889, 891, 893, 895, + 897, 899, 900, 902, 904, 906, 908, 909, + 911, 913, 915, 916, 918, 920, 921, 923, + 925, 926, 928, 929, 931, 932, 934, 936, + 937, 939, 940, 942, 943, 945, 946, 947, + 949, 950, 952, 953, 954, 956, 957, 958, + 960, 961, 962, 964, 965, 966, 967, 969, + 970, 971, 972, 973, 974, 976, 977, 978, + 979, 980, 981, 982, 983, 984, 985, 986, + 987, 988, 989, 990, 991, 992, 993, 994, + 995, 996, 996, 997, 998, 999, 1000, 1001, + 1001, 1002, 1003, 1004, 1004, 1005, 1006, 1006, + 1007, 1008, 1008, 1009, 1010, 1010, 1011, 1011, + 1012, 1012, 1013, 1014, 1014, 1015, 1015, 1015, + 1016, 1016, 1017, 1017, 1018, 1018, 1018, 1019, + 1019, 1019, 1020, 1020, 1020, 1020, 1021, 1021, + 1021, 1021, 1022, 1022, 1022, 1022, 1022, 1022, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 + }, + {/*700*/ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 146, 201, 241, 276, 306, 332, 356, + 378, 399, 419, 437, 454, 471, 487, 503, + 518, 533, 547, 560, 573, 586, 599, 611, + 623, 634, 646, 657, 668, 679, 689, 700, + 710, 720, 730, 739, 749, 758, 767, 776, + 785, 794, 803, 811, 820, 828, 837, 845, + 853, 861, 870, 880, 889, 898, 905, 908, + 909, 911, 912, 914, 915, 917, 918, 919, + 921, 922, 923, 925, 926, 927, 929, 930, + 931, 932, 934, 935, 936, 937, 939, 940, + 941, 942, 943, 944, 946, 947, 948, 949, + 950, 951, 952, 953, 954, 955, 956, 957, + 958, 959, 960, 961, 962, 963, 964, 965, + 966, 967, 968, 969, 970, 971, 972, 972, + 973, 974, 975, 976, 977, 977, 978, 979, + 980, 981, 981, 982, 983, 984, 984, 985, + 986, 987, 987, 988, 989, 989, 990, 991, + 991, 992, 993, 993, 994, 994, 995, 996, + 996, 997, 997, 998, 998, 999, 999, 1000, + 1001, 1001, 1002, 1002, 1003, 1003, 1003, 1004, + 1004, 1005, 1005, 1006, 1006, 1007, 1007, 1007, + 1008, 1008, 1009, 1009, 1009, 1010, 1010, 1011, + 1011, 1011, 1012, 1012, 1012, 1013, 1013, 1013, + 1014, 1014, 1014, 1014, 1015, 1015, 1015, 1016, + 1016, 1016, 1016, 1017, 1017, 1017, 1017, 1017, + 1018, 1018, 1018, 1018, 1018, 1019, 1019, 1019, + 1019, 1019, 1020, 1020, 1020, 1020, 1020, 1020, + 1020, 1021, 1021, 1021, 1021, 1021, 1021, 1021, + 1021, 1022, 1022, 1022, 1022, 1022, 1022, 1022, + 1022, 1022, 1022, 1022, 1022, 1022, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 + }, + {/*800*/ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 139, 189, 227, 259, 288, 312, 335, + 356, 375, 393, 411, 427, 443, 458, 473, + 487, 501, 514, 527, 539, 551, 563, 574, + 586, 597, 607, 618, 628, 639, 649, 658, + 668, 678, 687, 696, 705, 714, 722, 731, + 739, 747, 756, 764, 772, 780, 787, 795, + 803, 811, 819, 827, 836, 844, 850, 854, + 856, 858, 860, 862, 864, 866, 868, 870, + 872, 873, 875, 877, 879, 881, 883, 884, + 886, 888, 890, 891, 893, 895, 896, 898, + 900, 901, 903, 905, 906, 908, 909, 911, + 912, 914, 916, 917, 919, 920, 922, 923, + 924, 926, 927, 929, 930, 931, 933, 934, + 936, 937, 938, 939, 941, 942, 943, 945, + 946, 947, 948, 949, 951, 952, 953, 954, + 955, 956, 958, 959, 960, 961, 962, 963, + 964, 965, 966, 967, 968, 969, 970, 971, + 972, 973, 974, 975, 976, 977, 978, 979, + 980, 980, 981, 982, 983, 984, 985, 985, + 986, 987, 988, 989, 989, 990, 991, 992, + 992, 993, 994, 994, 995, 996, 996, 997, + 998, 998, 999, 1000, 1000, 1001, 1001, 1002, + 1002, 1003, 1004, 1004, 1005, 1005, 1006, 1006, + 1007, 1007, 1008, 1008, 1009, 1009, 1010, 1010, + 1010, 1011, 1011, 1012, 1012, 1012, 1013, 1013, + 1014, 1014, 1014, 1015, 1015, 1015, 1016, 1016, + 1016, 1017, 1017, 1017, 1017, 1018, 1018, 1018, + 1018, 1019, 1019, 1019, 1019, 1020, 1020, 1020, + 1020, 1020, 1020, 1021, 1021, 1021, 1021, 1021, + 1021, 1022, 1022, 1022, 1022, 1022, 1022, 1022, + 1022, 1022, 1022, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 + }, + {/*900*/ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 131, 179, 216, 246, 273, 296, 317, + 337, 355, 373, 389, 405, 420, 435, 449, + 462, 475, 488, 500, 512, 523, 534, 545, + 555, 566, 576, 586, 596, 605, 615, 624, + 633, 642, 651, 660, 668, 676, 685, 693, + 701, 709, 716, 724, 732, 739, 747, 754, + 761, 769, 776, 783, 790, 797, 804, 810, + 817, 824, 832, 839, 847, 855, 863, 870, + 877, 884, 890, 895, 900, 904, 907, 908, + 910, 911, 913, 914, 915, 917, 918, 920, + 921, 922, 924, 925, 926, 928, 929, 930, + 932, 933, 934, 935, 937, 938, 939, 940, + 941, 943, 944, 945, 946, 947, 948, 949, + 951, 952, 953, 954, 955, 956, 957, 958, + 959, 960, 961, 962, 963, 964, 965, 966, + 967, 968, 969, 970, 971, 972, 972, 973, + 974, 975, 976, 977, 978, 978, 979, 980, + 981, 982, 982, 983, 984, 985, 985, 986, + 987, 988, 988, 989, 990, 990, 991, 992, + 992, 993, 994, 994, 995, 996, 996, 997, + 997, 998, 999, 999, 1000, 1000, 1001, 1001, + 1002, 1002, 1003, 1004, 1004, 1005, 1005, 1005, + 1006, 1006, 1007, 1007, 1008, 1008, 1009, 1009, + 1009, 1010, 1010, 1011, 1011, 1011, 1012, 1012, + 1013, 1013, 1013, 1014, 1014, 1014, 1015, 1015, + 1015, 1015, 1016, 1016, 1016, 1017, 1017, 1017, + 1017, 1018, 1018, 1018, 1018, 1019, 1019, 1019, + 1019, 1019, 1020, 1020, 1020, 1020, 1020, 1020, + 1021, 1021, 1021, 1021, 1021, 1021, 1021, 1022, + 1022, 1022, 1022, 1022, 1022, 1022, 1022, 1022, + 1022, 1022, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 + }, + {/*1000*/ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 124, 171, 206, 235, 260, 281, 302, + 321, 339, 355, 371, 386, 400, 414, 428, + 441, 453, 465, 476, 487, 498, 509, 519, + 529, 539, 549, 558, 568, 577, 586, 594, + 603, 612, 620, 628, 636, 644, 652, 660, + 668, 675, 683, 690, 697, 705, 712, 719, + 726, 733, 740, 746, 753, 759, 766, 772, + 778, 785, 791, 797, 803, 809, 815, 821, + 827, 833, 839, 845, 850, 856, 862, 867, + 873, 880, 886, 893, 898, 903, 907, 909, + 911, 912, 914, 915, 917, 918, 919, 921, + 922, 924, 925, 926, 928, 929, 930, 932, + 933, 934, 936, 937, 938, 939, 941, 942, + 943, 944, 946, 947, 948, 949, 950, 951, + 952, 954, 955, 956, 957, 958, 959, 960, + 961, 962, 963, 964, 965, 966, 967, 968, + 969, 970, 971, 972, 973, 974, 975, 976, + 976, 977, 978, 979, 980, 981, 982, 982, + 983, 984, 985, 986, 986, 987, 988, 989, + 989, 990, 991, 991, 992, 993, 993, 994, + 995, 995, 996, 997, 997, 998, 999, 999, + 1000, 1000, 1001, 1001, 1002, 1003, 1003, 1004, + 1004, 1005, 1005, 1006, 1006, 1007, 1007, 1008, + 1008, 1008, 1009, 1009, 1010, 1010, 1011, 1011, + 1011, 1012, 1012, 1013, 1013, 1013, 1014, 1014, + 1014, 1015, 1015, 1015, 1016, 1016, 1016, 1016, + 1017, 1017, 1017, 1018, 1018, 1018, 1018, 1019, + 1019, 1019, 1019, 1019, 1020, 1020, 1020, 1020, + 1020, 1020, 1021, 1021, 1021, 1021, 1021, 1021, + 1022, 1022, 1022, 1022, 1022, 1022, 1022, 1022, + 1022, 1022, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 + } +}; +/*Mbox: iptv/ott hdr curve select*/ +/*600nit alpha_low = 0.12; */ +static unsigned int eotf_33_2084_mapping_box[33] = { + 0, 4, 10, 16, 24, 34, 48, 67, + 93, 129, 177, 244, 334, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 +}; + +static unsigned int oetf_289_gamma22_mapping_box[289] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 115, 157, 189, 215, 238, 259, 278, + 296, 312, 327, 342, 356, 369, 381, 394, + 405, 417, 428, 438, 449, 459, 468, 478, + 487, 496, 505, 514, 523, 531, 540, 548, + 556, 564, 571, 579, 586, 594, 601, 608, + 615, 622, 629, 636, 642, 649, 655, 662, + 668, 675, 681, 688, 695, 702, 709, 715, + 722, 729, 735, 741, 747, 753, 759, 764, + 769, 773, 777, 781, 784, 786, 789, 791, + 794, 796, 799, 801, 803, 806, 808, 811, + 813, 815, 818, 820, 822, 825, 827, 829, + 831, 834, 836, 838, 840, 842, 845, 847, + 849, 851, 853, 855, 857, 860, 862, 864, + 866, 868, 870, 872, 874, 876, 878, 880, + 882, 884, 886, 887, 889, 891, 893, 895, + 897, 899, 900, 902, 904, 906, 908, 909, + 911, 913, 915, 916, 918, 920, 921, 923, + 925, 926, 928, 929, 931, 932, 934, 936, + 937, 939, 940, 942, 943, 945, 946, 947, + 949, 950, 952, 953, 954, 956, 957, 958, + 960, 961, 962, 964, 965, 966, 967, 969, + 970, 971, 972, 973, 974, 976, 977, 978, + 979, 980, 981, 982, 983, 984, 985, 986, + 987, 988, 989, 990, 991, 992, 993, 994, + 995, 996, 996, 997, 998, 999, 1000, 1001, + 1001, 1002, 1003, 1004, 1004, 1005, 1006, 1006, + 1007, 1008, 1008, 1009, 1010, 1010, 1011, 1011, + 1012, 1012, 1013, 1014, 1014, 1015, 1015, 1015, + 1016, 1016, 1017, 1017, 1018, 1018, 1018, 1019, + 1019, 1019, 1020, 1020, 1020, 1020, 1021, 1021, + 1021, 1021, 1022, 1022, 1022, 1022, 1022, 1022, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; + +/*350nit alpha_low = 0.12; */ +static unsigned int eotf_33_2084_mapping_level1_box[33] = { + 0, 4, 10, 16, 24, 34, 48, 67, + 93, 129, 177, 244, 334, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 +}; + +static unsigned int oetf_289_gamma22_mapping_level1_box[289] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 148, 201, 242, 276, 305, 331, 355, + 378, 399, 418, 437, 454, 471, 487, 503, + 518, 532, 546, 560, 573, 586, 598, 610, + 622, 634, 645, 656, 667, 678, 689, 699, + 710, 720, 730, 741, 752, 764, 775, 786, + 797, 807, 816, 825, 832, 839, 844, 847, + 849, 851, 853, 855, 857, 859, 861, 863, + 865, 867, 869, 871, 872, 874, 876, 878, + 880, 881, 883, 885, 887, 888, 890, 892, + 893, 895, 897, 898, 900, 902, 903, 905, + 906, 908, 910, 911, 913, 914, 916, 917, + 919, 920, 921, 923, 924, 926, 927, 928, + 930, 931, 933, 934, 935, 937, 938, 939, + 940, 942, 943, 944, 945, 947, 948, 949, + 950, 951, 952, 954, 955, 956, 957, 958, + 959, 960, 961, 962, 963, 964, 965, 966, + 967, 968, 969, 970, 971, 972, 973, 974, + 975, 976, 977, 978, 979, 980, 980, 981, + 982, 983, 984, 985, 985, 986, 987, 988, + 988, 989, 990, 991, 991, 992, 993, 993, + 994, 995, 995, 996, 997, 997, 998, 999, + 999, 1000, 1000, 1001, 1002, 1002, 1003, 1003, + 1004, 1004, 1005, 1005, 1006, 1006, 1007, 1007, + 1008, 1008, 1009, 1009, 1010, 1010, 1010, 1011, + 1011, 1012, 1012, 1012, 1013, 1013, 1013, 1014, + 1014, 1014, 1015, 1015, 1015, 1016, 1016, 1016, + 1017, 1017, 1017, 1017, 1018, 1018, 1018, 1018, + 1019, 1019, 1019, 1019, 1020, 1020, 1020, 1020, + 1020, 1020, 1021, 1021, 1021, 1021, 1021, 1021, + 1022, 1022, 1022, 1022, 1022, 1022, 1022, 1022, + 1022, 1022, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; + +/*800nit alpha_low = 0.12; */ +static unsigned int eotf_33_2084_mapping_level2_box[33] = { + 0, 4, 8, 12, 18, 24, 33, 43, + 58, 77, 103, 138, 184, 246, 329, 440, + 605, 824, 1117, 1507, 2025, 2713, 3625, 4836, + 6445, 8583, 11430, 15228, 15695, 16025, 16237, 16350, + 16383 +}; + +static unsigned int oetf_289_gamma22_mapping_level2_box[289] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 139, 189, 227, 259, 288, 312, 335, + 356, 375, 393, 411, 427, 443, 458, 473, + 487, 501, 514, 527, 539, 551, 563, 574, + 586, 597, 607, 618, 628, 639, 649, 658, + 668, 678, 687, 696, 705, 714, 722, 731, + 739, 747, 756, 764, 772, 780, 787, 795, + 803, 811, 819, 827, 836, 844, 850, 854, + 856, 858, 860, 862, 864, 866, 868, 870, + 872, 873, 875, 877, 879, 881, 883, 884, + 886, 888, 890, 891, 893, 895, 896, 898, + 900, 901, 903, 905, 906, 908, 909, 911, + 912, 914, 916, 917, 919, 920, 922, 923, + 924, 926, 927, 929, 930, 931, 933, 934, + 936, 937, 938, 939, 941, 942, 943, 945, + 946, 947, 948, 949, 951, 952, 953, 954, + 955, 956, 958, 959, 960, 961, 962, 963, + 964, 965, 966, 967, 968, 969, 970, 971, + 972, 973, 974, 975, 976, 977, 978, 979, + 980, 980, 981, 982, 983, 984, 985, 985, + 986, 987, 988, 989, 989, 990, 991, 992, + 992, 993, 994, 994, 995, 996, 996, 997, + 998, 998, 999, 1000, 1000, 1001, 1001, 1002, + 1002, 1003, 1004, 1004, 1005, 1005, 1006, 1006, + 1007, 1007, 1008, 1008, 1009, 1009, 1010, 1010, + 1010, 1011, 1011, 1012, 1012, 1012, 1013, 1013, + 1014, 1014, 1014, 1015, 1015, 1015, 1016, 1016, + 1016, 1017, 1017, 1017, 1017, 1018, 1018, 1018, + 1018, 1019, 1019, 1019, 1019, 1020, 1020, 1020, + 1020, 1020, 1020, 1021, 1021, 1021, 1021, 1021, + 1021, 1022, 1022, 1022, 1022, 1022, 1022, 1022, + 1022, 1022, 1022, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; + +/*400nit alpha_low = 0.20; */ +static unsigned int eotf_33_2084_mapping_level3_box[33] = { + 0, 7, 15, 24, 34, 47, 63, 83, + 110, 146, 193, 257, 342, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 +}; + +static unsigned int oetf_289_gamma22_mapping_level3_box[289] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 139, 189, 228, 259, 287, 312, 334, + 356, 375, 394, 411, 427, 443, 458, 473, + 487, 501, 514, 527, 540, 552, 564, 575, + 586, 597, 608, 618, 629, 639, 649, 658, + 668, 677, 687, 697, 708, 718, 729, 739, + 749, 758, 767, 775, 782, 788, 793, 797, + 800, 802, 804, 807, 809, 812, 814, 816, + 819, 821, 823, 826, 828, 830, 832, 835, + 837, 839, 841, 843, 845, 848, 850, 852, + 854, 856, 858, 860, 862, 864, 866, 868, + 870, 872, 874, 876, 878, 880, 882, 883, + 885, 887, 889, 891, 892, 894, 896, 898, + 899, 901, 903, 905, 906, 908, 910, 911, + 913, 914, 916, 918, 919, 921, 922, 924, + 925, 927, 928, 930, 931, 933, 934, 935, + 937, 938, 940, 941, 942, 944, 945, 946, + 948, 949, 950, 951, 953, 954, 955, 956, + 958, 959, 960, 961, 962, 963, 964, 966, + 967, 968, 969, 970, 971, 972, 973, 974, + 975, 976, 977, 978, 979, 980, 981, 982, + 983, 984, 984, 985, 986, 987, 988, 989, + 990, 990, 991, 992, 993, 993, 994, 995, + 996, 996, 997, 998, 999, 999, 1000, 1001, + 1001, 1002, 1002, 1003, 1004, 1004, 1005, 1005, + 1006, 1007, 1007, 1008, 1008, 1009, 1009, 1010, + 1010, 1011, 1011, 1012, 1012, 1012, 1013, 1013, + 1014, 1014, 1014, 1015, 1015, 1016, 1016, 1016, + 1017, 1017, 1017, 1018, 1018, 1018, 1018, 1019, + 1019, 1019, 1019, 1020, 1020, 1020, 1020, 1021, + 1021, 1021, 1021, 1021, 1021, 1022, 1022, 1022, + 1022, 1022, 1022, 1022, 1022, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; + +/*450nit alpha_low = 0.12;*/ +static unsigned int eotf_33_2084_mapping_level4_box[33] = { + 0, 4, 10, 16, 24, 34, 48, 67, + 93, 129, 177, 244, 334, 455, 636, 881, + 1209, 1648, 2234, 3014, 4050, 5425, 7251, 9673, + 12889, 13773, 14513, 15117, 15594, 15951, 16196, 16338, + 16383 +}; + +static unsigned int oetf_289_gamma22_mapping_level4_box[289] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 131, 179, 216, 245, 272, 295, 317, + 337, 356, 374, 390, 406, 421, 435, 449, + 462, 475, 488, 500, 512, 523, 534, 545, + 556, 566, 576, 586, 596, 605, 615, 624, + 633, 642, 651, 660, 668, 676, 685, 693, + 701, 709, 717, 725, 732, 740, 747, 754, + 762, 769, 777, 785, 793, 802, 810, 818, + 826, 834, 842, 849, 856, 863, 869, 875, + 880, 885, 889, 892, 894, 896, 897, 899, + 900, 902, 904, 905, 907, 908, 909, 911, + 912, 914, 915, 917, 918, 919, 921, 922, + 924, 925, 926, 928, 929, 930, 931, 933, + 934, 935, 937, 938, 939, 940, 941, 943, + 944, 945, 946, 947, 948, 950, 951, 952, + 953, 954, 955, 956, 957, 958, 959, 960, + 961, 962, 963, 964, 965, 966, 967, 968, + 969, 970, 971, 972, 973, 974, 975, 976, + 976, 977, 978, 979, 980, 981, 981, 982, + 983, 984, 985, 985, 986, 987, 988, 988, + 989, 990, 990, 991, 992, 993, 993, 994, + 994, 995, 996, 996, 997, 998, 998, 999, + 999, 1000, 1001, 1001, 1002, 1002, 1003, 1003, + 1004, 1004, 1005, 1005, 1006, 1006, 1007, 1007, + 1008, 1008, 1009, 1009, 1009, 1010, 1010, 1011, + 1011, 1012, 1012, 1012, 1013, 1013, 1013, 1014, + 1014, 1014, 1015, 1015, 1015, 1016, 1016, 1016, + 1017, 1017, 1017, 1017, 1018, 1018, 1018, 1018, + 1019, 1019, 1019, 1019, 1019, 1020, 1020, 1020, + 1020, 1020, 1021, 1021, 1021, 1021, 1021, 1021, + 1021, 1022, 1022, 1022, 1022, 1022, 1022, 1022, + 1022, 1022, 1022, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; + +#endif + diff --git a/drivers/amlogic/media/enhancement/amvecm/arch/ve_regs.h b/drivers/amlogic/media/enhancement/amvecm/arch/ve_regs.h new file mode 100644 index 0000000..89ae0c8 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/arch/ve_regs.h @@ -0,0 +1,529 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/arch/ve_regs.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef _VE_REG_H +#define _VE_REG_H + +/* ********************************************************************* */ +/* ******** GAMMA REGISTERS ******** */ +/* ********************************************************************* */ +#define L_GAMMA_CNTL_PORT 0x1400 + #define GAMMA_VCOM_POL 7 /* RW */ + #define GAMMA_RVS_OUT 6 /* RW */ + #define ADR_RDY 5 /* Read Only */ + #define WR_RDY 4 /* Read Only */ + #define RD_RDY 3 /* Read Only */ + #define GAMMA_TR 2 /* RW */ + #define GAMMA_SET 1 /* RW */ + #define GAMMA_EN 0 /* RW */ +#define L_GAMMA_DATA_PORT 0x1401 +#define L_GAMMA_ADDR_PORT 0x1402 + #define H_RD 12 + #define H_AUTO_INC 11 + #define H_SEL_R 10 + #define H_SEL_G 9 + #define H_SEL_B 8 + #define HADR_MSB 7 /* 7:0 */ + #define HADR 0 /* 7:0 */ +/* ********************************************************************* */ +/* ******** VIDEO ENHANCEMENT REGISTERS ******** */ +/* ********************************************************************* */ + +/* #define VPP_BLACKEXT_CTRL 0x1d80 */ +#define BEXT_START_BIT 24 +#define BEXT_START_WID 8 +#define BEXT_SLOPE1_BIT 16 +#define BEXT_SLOPE1_WID 8 +#define BEXT_MIDPT_BIT 8 +#define BEXT_MIDPT_WID 8 +#define BEXT_SLOPE2_BIT 0 +#define BEXT_SLOPE2_WID 8 + +/* #define VPP_DNLP_CTRL_00 0x1d81 */ +#define DNLP_GAMMA03_BIT 24 +#define DNLP_GAMMA03_WID 8 +#define DNLP_GAMMA02_BIT 16 +#define DNLP_GAMMA02_WID 8 +#define DNLP_GAMMA01_BIT 8 +#define DNLP_GAMMA01_WID 8 +#define DNLP_GAMMA00_BIT 0 +#define DNLP_GAMMA00_WID 8 + +/* #define VPP_DNLP_CTRL_01 0x1d82 */ +#define DNLP_GAMMA07_BIT 24 +#define DNLP_GAMMA07_WID 8 +#define DNLP_GAMMA06_BIT 16 +#define DNLP_GAMMA06_WID 8 +#define DNLP_GAMMA05_BIT 8 +#define DNLP_GAMMA05_WID 8 +#define DNLP_GAMMA04_BIT 0 +#define DNLP_GAMMA04_WID 8 + +/* #define VPP_DNLP_CTRL_02 0x1d83 */ +#define DNLP_GAMMA11_BIT 24 +#define DNLP_GAMMA11_WID 8 +#define DNLP_GAMMA10_BIT 16 +#define DNLP_GAMMA10_WID 8 +#define DNLP_GAMMA09_BIT 8 +#define DNLP_GAMMA09_WID 8 +#define DNLP_GAMMA08_BIT 0 +#define DNLP_GAMMA08_WID 8 + +/* #define VPP_DNLP_CTRL_03 0x1d84 */ +#define DNLP_GAMMA15_BIT 24 +#define DNLP_GAMMA15_WID 8 +#define DNLP_GAMMA14_BIT 16 +#define DNLP_GAMMA14_WID 8 +#define DNLP_GAMMA13_BIT 8 +#define DNLP_GAMMA13_WID 8 +#define DNLP_GAMMA12_BIT 0 +#define DNLP_GAMMA12_WID 8 + +/* #define VPP_DNLP_CTRL_04 0x1d85 */ +#define DNLP_GAMMA19_BIT 24 +#define DNLP_GAMMA19_WID 8 +#define DNLP_GAMMA18_BIT 16 +#define DNLP_GAMMA18_WID 8 +#define DNLP_GAMMA17_BIT 8 +#define DNLP_GAMMA17_WID 8 +#define DNLP_GAMMA16_BIT 0 +#define DNLP_GAMMA16_WID 8 + +/* #define VPP_DNLP_CTRL_05 0x1d86 */ +#define DNLP_GAMMA23_BIT 24 +#define DNLP_GAMMA23_WID 8 +#define DNLP_GAMMA22_BIT 16 +#define DNLP_GAMMA22_WID 8 +#define DNLP_GAMMA21_BIT 8 +#define DNLP_GAMMA21_WID 8 +#define DNLP_GAMMA20_BIT 0 +#define DNLP_GAMMA20_WID 8 + +/* #define VPP_DNLP_CTRL_06 0x1d87 */ +#define DNLP_GAMMA27_BIT 24 +#define DNLP_GAMMA27_WID 8 +#define DNLP_GAMMA26_BIT 16 +#define DNLP_GAMMA26_WID 8 +#define DNLP_GAMMA25_BIT 8 +#define DNLP_GAMMA25_WID 8 +#define DNLP_GAMMA24_BIT 0 +#define DNLP_GAMMA24_WID 8 + +/* #define VPP_DNLP_CTRL_07 0x1d88 */ +#define DNLP_GAMMA31_BIT 24 +#define DNLP_GAMMA31_WID 8 +#define DNLP_GAMMA30_BIT 16 +#define DNLP_GAMMA30_WID 8 +#define DNLP_GAMMA29_BIT 8 +#define DNLP_GAMMA29_WID 8 +#define DNLP_GAMMA28_BIT 0 +#define DNLP_GAMMA28_WID 8 + +/* #define VPP_DNLP_CTRL_08 0x1d89 */ +#define DNLP_GAMMA35_BIT 24 +#define DNLP_GAMMA35_WID 8 +#define DNLP_GAMMA34_BIT 16 +#define DNLP_GAMMA34_WID 8 +#define DNLP_GAMMA33_BIT 8 +#define DNLP_GAMMA33_WID 8 +#define DNLP_GAMMA32_BIT 0 +#define DNLP_GAMMA32_WID 8 + +/* #define VPP_DNLP_CTRL_09 0x1d8a */ +#define DNLP_GAMMA39_BIT 24 +#define DNLP_GAMMA39_WID 8 +#define DNLP_GAMMA38_BIT 16 +#define DNLP_GAMMA38_WID 8 +#define DNLP_GAMMA37_BIT 8 +#define DNLP_GAMMA37_WID 8 +#define DNLP_GAMMA36_BIT 0 +#define DNLP_GAMMA36_WID 8 + +/* #define VPP_DNLP_CTRL_10 0x1d8b */ +#define DNLP_GAMMA43_BIT 24 +#define DNLP_GAMMA43_WID 8 +#define DNLP_GAMMA42_BIT 16 +#define DNLP_GAMMA42_WID 8 +#define DNLP_GAMMA41_BIT 8 +#define DNLP_GAMMA41_WID 8 +#define DNLP_GAMMA40_BIT 0 +#define DNLP_GAMMA40_WID 8 + +/* #define VPP_DNLP_CTRL_11 0x1d8c */ +#define DNLP_GAMMA47_BIT 24 +#define DNLP_GAMMA47_WID 8 +#define DNLP_GAMMA46_BIT 16 +#define DNLP_GAMMA46_WID 8 +#define DNLP_GAMMA45_BIT 8 +#define DNLP_GAMMA45_WID 8 +#define DNLP_GAMMA44_BIT 0 +#define DNLP_GAMMA44_WID 8 + +/* #define VPP_DNLP_CTRL_12 0x1d8d */ +#define DNLP_GAMMA51_BIT 24 +#define DNLP_GAMMA51_WID 8 +#define DNLP_GAMMA50_BIT 16 +#define DNLP_GAMMA50_WID 8 +#define DNLP_GAMMA49_BIT 8 +#define DNLP_GAMMA49_WID 8 +#define DNLP_GAMMA48_BIT 0 +#define DNLP_GAMMA48_WID 8 + +/* #define VPP_DNLP_CTRL_13 0x1d8e */ +#define DNLP_GAMMA55_BIT 24 +#define DNLP_GAMMA55_WID 8 +#define DNLP_GAMMA54_BIT 16 +#define DNLP_GAMMA54_WID 8 +#define DNLP_GAMMA53_BIT 8 +#define DNLP_GAMMA53_WID 8 +#define DNLP_GAMMA52_BIT 0 +#define DNLP_GAMMA52_WID 8 + +/* #define VPP_DNLP_CTRL_14 0x1d8f */ +#define DNLP_GAMMA59_BIT 24 +#define DNLP_GAMMA59_WID 8 +#define DNLP_GAMMA58_BIT 16 +#define DNLP_GAMMA58_WID 8 +#define DNLP_GAMMA57_BIT 8 +#define DNLP_GAMMA57_WID 8 +#define DNLP_GAMMA56_BIT 0 +#define DNLP_GAMMA56_WID 8 + +/* #define VPP_DNLP_CTRL_15 0x1d90 */ +#define DNLP_GAMMA63_BIT 24 +#define DNLP_GAMMA63_WID 8 +#define DNLP_GAMMA62_BIT 16 +#define DNLP_GAMMA62_WID 8 +#define DNLP_GAMMA61_BIT 8 +#define DNLP_GAMMA61_WID 8 +#define DNLP_GAMMA60_BIT 0 +#define DNLP_GAMMA60_WID 8 + +/* #define VPP_PEAKING_HGAIN 0x1d91 */ +#define VLTI_STEP_BIT 28 +#define VLTI_STEP_WID 1 +#define VLTI_STEP2_BIT 27 +#define VLTI_STEP2_WID 1 +#define HLTI_STEP_BIT 25 +#define HLTI_STEP_WID 2 +#define PEAK_GAIN_H1_BIT 20 +#define PEAK_GAIN_H1_WID 5 +#define PEAK_GAIN_H2_BIT 15 +#define PEAK_GAIN_H2_WID 5 +#define PEAK_GAIN_H3_BIT 10 +#define PEAK_GAIN_H3_WID 5 +#define PEAK_GAIN_H4_BIT 5 +#define PEAK_GAIN_H4_WID 5 +#define PEAK_GAIN_H5_BIT 0 +#define PEAK_GAIN_H5_WID 5 + +/* #define VPP_PEAKING_VGAIN 0x1d92 */ +#define VCTI_BUF_EN_BIT 31 +#define VCTI_BUF_EN_WID 1 +#define VCTI_BUF_MODE_C5L_BIT 30 +#define VCTI_BUF_MODE_C5L_WID 1 +#define PEAK_GAIN_V1_BIT 25 +#define PEAK_GAIN_V1_WID 5 +#define PEAK_GAIN_V2_BIT 20 +#define PEAK_GAIN_V2_WID 5 +#define PEAK_GAIN_V3_BIT 15 +#define PEAK_GAIN_V3_WID 5 +#define PEAK_GAIN_V4_BIT 10 +#define PEAK_GAIN_V4_WID 5 +#define PEAK_GAIN_V5_BIT 5 +#define PEAK_GAIN_V5_WID 5 +#define PEAK_GAIN_V6_BIT 0 +#define PEAK_GAIN_V6_WID 5 + +/* #define VPP_PEAKING_NLP_1 0x1d93 */ +#define HPEAK_SLOPE1_BIT 26 +#define HPEAK_SLOPE1_WID 6 +#define HPEAK_SLOPE2_BIT 20 +#define HPEAK_SLOPE2_WID 6 +#define HPEAK_THR1_BIT 12 +#define HPEAK_THR1_WID 8 +#define VPEAK_SLOPE1_BIT 6 +#define VPEAK_SLOPE1_WID 6 +#define VPEAK_SLOPE2_BIT 0 +#define VPEAK_SLOPE2_WID 6 + +/* #define VPP_PEAKING_NLP_2 0x1d94 */ +#define HPEAK_THR2_BIT 24 +#define HPEAK_THR2_WID 8 +#define HPEAK_NLP_COR_THR_BIT 16 +#define HPEAK_NLP_COR_THR_WID 8 +#define HPEAK_NLP_GAIN_POS_BIT 8 +#define HPEAK_NLP_GAIN_POS_WID 8 +#define HPEAK_NLP_GAIN_NEG_BIT 0 +#define HPEAK_NLP_GAIN_NEG_WID 8 + +/* #define VPP_PEAKING_NLP_3 0x1d95 */ +#define VPEAK_THR1_BIT 24 +#define VPEAK_THR1_WID 8 +#define SPEAK_SLOPE1_BIT 18 +#define SPEAK_SLOPE1_WID 6 +#define SPEAK_SLOPE2_BIT 12 +#define SPEAK_SLOPE2_WID 6 +#define SPEAK_THR1_BIT 4 +#define SPEAK_THR1_WID 8 +#define PEAK_COR_GAIN_BIT 0 +#define PEAK_COR_GAIN_WID 4 + +/* #define VPP_PEAKING_NLP_4 0x1d96 */ +#define VPEAK_THR2_BIT 24 +#define VPEAK_THR2_WID 8 +#define VPEAK_NLP_COR_THR_BIT 16 +#define VPEAK_NLP_COR_THR_WID 8 +#define VPEAK_NLP_GAIN_POS_BIT 8 +#define VPEAK_NLP_GAIN_POS_WID 8 +#define VPEAK_NLP_GAIN_NEG_BIT 0 +#define VPEAK_NLP_GAIN_NEG_WID 8 + +/* #define VPP_PEAKING_NLP_5 0x1d97 */ +#define SPEAK_THR2_BIT 24 +#define SPEAK_THR2_WID 8 +#define SPEAK_NLP_COR_THR_BIT 16 +#define SPEAK_NLP_COR_THR_WID 8 +#define SPEAK_NLP_GAIN_POS_BIT 8 +#define SPEAK_NLP_GAIN_POS_WID 8 +#define SPEAK_NLP_GAIN_NEG_BIT 0 +#define SPEAK_NLP_GAIN_NEG_WID 8 + +/* #define VPP_HSVS_LIMIT 0x1d98 */ +#define PEAK_COR_THR_L_BIT 24 +#define PEAK_COR_THR_L_WID 8 +#define PEAK_COR_THR_H_BIT 16 +#define PEAK_COR_THR_H_WID 8 +#define VLIMIT_COEF_H_BIT 12 +#define VLIMIT_COEF_H_WID 4 +#define VLIMIT_COEF_L_BIT 8 +#define VLIMIT_COEF_L_WID 4 +#define HLIMIT_COEF_H_BIT 4 +#define HLIMIT_COEF_H_WID 4 +#define HLIMIT_COEF_L_BIT 0 +#define HLIMIT_COEF_L_WID 4 + +/* #define VPP_VLTI_CTRL 0x1d99 */ +#define VLTI_GAIN_NEG_BIT 24 +#define VLTI_GAIN_NEG_WID 8 +#define VLTI_GAIN_POS_BIT 16 +#define VLTI_GAIN_POS_WID 8 +#define VLTI_THR_BIT 8 +#define VLTI_THR_WID 8 +#define VLTI_BLEND_FACTOR_BIT 0 +#define VLTI_BLEND_FACTOR_WID 8 + +/* #define VPP_HLTI_CTRL 0x1d9a */ +#define HLTI_GAIN_NEG_BIT 24 +#define HLTI_GAIN_NEG_WID 8 +#define HLTI_GAIN_POS_BIT 16 +#define HLTI_GAIN_POS_WID 8 +#define HLTI_THR_BIT 8 +#define HLTI_THR_WID 8 +#define HLTI_BLEND_FACTOR_BIT 0 +#define HLTI_BLEND_FACTOR_WID 8 + +/* #define VPP_CTI_CTRL 0x1d9b */ +#define CTI_C444TO422_EN_BIT 30 +#define CTI_C444TO422_EN_WID 1 +/* 2'b00: no filter, 2'b01: (1, 0, 1), */ +/* 2'b10: (1, 2, 1), 2'b11: (1, 2, 2, 2, 1), */ +#define VCTI_FILTER_BIT 28 +#define VCTI_FILTER_WID 2 +#define CTI_C422TO444_EN_BIT 27 +#define CTI_C422TO444_EN_WID 1 +#define HCTI_STEP2_BIT 24 +#define HCTI_STEP2_WID 3 +#define HCTI_STEP_BIT 21 +#define HCTI_STEP_WID 3 +#define CTI_BLEND_FACTOR_BIT 16 +#define CTI_BLEND_FACTOR_WID 5 +#define HCTI_MODE_MEDIAN_BIT 15 +#define HCTI_MODE_MEDIAN_WID 1 +#define HCTI_THR_BIT 8 +#define HCTI_THR_WID 7 +#define HCTI_GAIN_BIT 0 +#define HCTI_GAIN_WID 8 + +/* #define VPP_BLUE_STRETCH_1 0x1d9c */ +#define BENH_CB_INC_BIT 29 +#define BENH_CB_INC_WID 1 +#define BENH_CR_INC_BIT 28 +#define BENH_CR_INC_WID 1 +#define BENH_ERR_CRP_INV_H_BIT 27 +#define BENH_ERR_CRP_INV_H_WID 1 +#define BENH_ERR_CRN_INV_H_BIT 26 +#define BENH_ERR_CRN_INV_H_WID 1 +#define BENH_ERR_CBP_INV_H_BIT 25 +#define BENH_ERR_CBP_INV_H_WID 1 +#define BENH_ERR_CBN_INV_H_BIT 24 +#define BENH_ERR_CBN_INV_H_WID 1 +#define BENH_GAIN_CR_BIT 16 +#define BENH_GAIN_CR_WID 8 +#define BENH_GAIN_CB4CR_BIT 8 +#define BENH_GAIN_CB4CR_WID 8 +#define BENH_LUMA_H_BIT 0 +#define BENH_LUMA_H_WID 8 + +/* #define VPP_BLUE_STRETCH_2 0x1d9d */ +#define BENH_ERR_CRP_BIT 27 +#define BENH_ERR_CRP_WID 5 +#define BENH_ERR_CRP_INV_L_BIT 16 +#define BENH_ERR_CRP_INV_L_WID 11 +#define BENH_ERR_CRN_BIT 11 +#define BENH_ERR_CRN_WID 5 +#define BENH_ERR_CRN_INV_L_BIT 0 +#define BENH_ERR_CRN_INV_L_WID 11 + +/* #define VPP_BLUE_STRETCH_3 0x1d9e */ +#define BENH_ERR_CBP_BIT 27 +#define BENH_ERR_CBP_WID 5 +#define BENH_ERR_CBP_INV_L_BIT 16 +#define BENH_ERR_CBP_INV_L_WID 11 +#define BENH_ERR_CBN_BIT 11 +#define BENH_ERR_CBN_WID 5 +#define BENH_ERR_CBN_INV_L_BIT 0 +#define BENH_ERR_CBN_INV_L_WID 11 + +/* #define VPP_CCORING_CTRL 0x1da0 */ +#define CCOR_THR_BIT 8 +#define CCOR_THR_WID 8 +#define CCOR_SLOPE_BIT 0 +#define CCOR_SLOPE_WID 4 + +/* #define VPP_VE_ENABLE_CTRL 0x1da1 */ +#define DEMO_CCOR_BIT 20 +#define DEMO_CCOR_WID 1 +#define DEMO_BEXT_BIT 19 +#define DEMO_BEXT_WID 1 +#define DEMO_DNLP_BIT 18 +#define DEMO_DNLP_WID 1 +#define DEMO_HSVS_BIT 17 +#define DEMO_HSVS_WID 1 +#define DEMO_BENH_BIT 16 +#define DEMO_BENH_WID 1 +#if defined(CONFIG_ARCH_MESON) +/* 1'b0: demo adjust on right, 1'b1: demo adjust on left */ +#define VE_DEMO_POS_BIT 15 +#define VE_DEMO_POS_WID 1 +#elif defined(CONFIG_ARCH_MESON2) +/* 2'b00: demo adjust on top, 2'b01: demo adjust on bottom, */ +/* 2'b10: demo adjust on left, 2'b11: demo adjust on right */ +#define VE_DEMO_POS_BIT 14 +#define VE_DEMO_POS_WID 2 +#endif +#define CCOR_EN_BIT 4 +#define CCOR_EN_WID 1 +#define BEXT_EN_BIT 3 +#define BEXT_EN_WID 1 +#define DNLP_EN_BIT 2 +#define DNLP_EN_WID 1 +#define HSVS_EN_BIT 1 +#define HSVS_EN_WID 1 +#define BENH_EN_BIT 0 +#define BENH_EN_WID 1 + +#if defined(CONFIG_ARCH_MESON) +/* #define VPP_VE_DEMO_LEFT_SCREEN_WIDTH 0x1da2 */ +#elif defined(CONFIG_ARCH_MESON2) +/* #define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2 */ +#endif +#define VE_DEMO_WID_BIT 0 +#define VE_DEMO_WID_WID 12 + +#if defined(CONFIG_ARCH_MESON2) +/* #define VPP_VE_DEMO_CENTER_BAR 0x1da3 */ +#define VE_CBAR_EN_BIT 31 /* center bar enable */ +#define VE_CBAR_EN_WID 1 +#define VE_CBAR_WID_BIT 24 /* center bar width (*2) */ +#define VE_CBAR_WID_WID 4 +#define VE_CBAR_CR_BIT 16 /* center bar Cr (*4) */ +#define VE_CBAR_CR_WID 8 +#define VE_CBAR_CB_BIT 8 /* center bar Cb (*4) */ +#define VE_CBAR_CB_WID 8 +#define VE_CBAR_Y_BIT 0 /* center bar y (*4) */ +#define VE_CBAR_Y_WID 8 +#endif + +#if defined(CONFIG_ARCH_MESON2) +/* #define VPP_VDO_MEAS_CTRL 0x1da8 */ + /* reset bit, high active */ +#define VDO_MEAS_RST_BIT 10 +#define VDO_MEAS_RST_WID 1 +/* 0: rising edge, 1: falling edge */ +#define VDO_MEAS_EDGE_BIT 9 +#define VDO_MEAS_EDGE_WID 1 +/* 1: accumulate the counter number, 0: not */ +#define VDO_MEAS_ACCUM_CNT_BIT 8 +#define VDO_MEAS_ACCUM_CNT_WID 1 + /* how many vsync span need to measure */ +#define VDO_MEAS_VS_SPAN_BIT 0 +#define VDO_MEAS_VS_SPAN_WID 8 +#endif + +/* #if defined(CONFIG_ARCH_MESON2) */ +/* #define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9 //Read only */ +/* every number of sync_span vsyncs, this counter add 1 */ +#define VDO_IND_MEAS_CNT_N_BIT 16 +#define VDO_IND_MEAS_CNT_N_WID 4 + /* high bit portion of counter */ +#define VDO_MEAS_VS_CNT_HI_BIT 0 +#define VDO_MEAS_VS_CNT_HI_WID 16 +/* #endif */ + +/* #if defined(CONFIG_ARCH_MESON2) */ +/* #define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa //Read only */ +/* low bit portion of counter */ +#define VDO_MEAS_VS_CNT_LO_BIT 0 +#define VDO_MEAS_VS_CNT_LO_WID 32 +/* #endif */ +/* bit 15:8 peaking_factor */ +/* bit 5 peaking_dnlp_demo_en */ +/* bit 4 peaking_dnlp_en */ +/* bit 3:0 peaking_filter_sel */ +/* #define VPP_PEAKING_DNLP 0x1db8 */ +#define PEAKING_FACTOR_BIT 8 +#define PEAKING_FACTOR_WID 8 +#define PEAKING_DNLP_DEMO_EN_BIT 5 +#define PEAKING_DNLP_DEMO_EN_WID 1 +#define PEAKING_DNLP_EN_BIT 4 +#define PEAKING_DNLP_EN_WID 1 +#define PEAKING_FILTER_SEL_BIT 0 +#define PEAKING_FILTER_SEL_WID 4 + +#define VPP_VE_H_V_SIZE 0x1da4 + +#define SRSHARP0_DNLP_EN 0x3245 +#define SRSHARP0_DNLP_00 0x3246 +#define SRSHARP0_DNLP_01 0x3247 +#define SRSHARP0_DNLP_02 0x3248 +#define SRSHARP0_DNLP_03 0x3249 +#define SRSHARP0_DNLP_04 0x324a +#define SRSHARP0_DNLP_05 0x324b +#define SRSHARP0_DNLP_06 0x324c +#define SRSHARP0_DNLP_07 0x324d +#define SRSHARP0_DNLP_08 0x324e +#define SRSHARP0_DNLP_09 0x324f +#define SRSHARP0_DNLP_10 0x3250 +#define SRSHARP0_DNLP_11 0x3251 +#define SRSHARP0_DNLP_12 0x3252 +#define SRSHARP0_DNLP_13 0x3253 +#define SRSHARP0_DNLP_14 0x3254 +#define SRSHARP0_DNLP_15 0x3255 +#define SRSHARP0_DEMO_CRTL 0x3256 + +#endif /* _VE_REG_H */ diff --git a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h new file mode 100644 index 0000000..8d3b1ea --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h @@ -0,0 +1,206 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef VPP_DOLBYVISION_REGS_H +#define VPP_DOLBYVISION_REGS_H + +#define DOLBY_CORE1_REG_START 0x3300 +#define DOLBY_CORE1_CLKGATE_CTRL 0x33f2 +#define DOLBY_CORE1_SWAP_CTRL0 0x33f3 +#define DOLBY_CORE1_SWAP_CTRL1 0x33f4 +#define DOLBY_CORE1_SWAP_CTRL2 0x33f5 +#define DOLBY_CORE1_SWAP_CTRL3 0x33f6 +#define DOLBY_CORE1_SWAP_CTRL4 0x33f7 +#define DOLBY_CORE1_SWAP_CTRL5 0x33f8 +#define DOLBY_CORE1_DMA_CTRL 0x33f9 +#define DOLBY_CORE1_DMA_STATUS 0x33fa +#define DOLBY_CORE1_STATUS0 0x33fb +#define DOLBY_CORE1_STATUS1 0x33fc +#define DOLBY_CORE1_STATUS2 0x33fd +#define DOLBY_CORE1_STATUS3 0x33fe +#define DOLBY_CORE1_DMA_PORT 0x33ff + +#define DOLBY_CORE2A_REG_START 0x3400 +#define DOLBY_CORE2A_CTRL 0x3401 +#define DOLBY_CORE2A_CLKGATE_CTRL 0x3432 +#define DOLBY_CORE2A_SWAP_CTRL0 0x3433 +#define DOLBY_CORE2A_SWAP_CTRL1 0x3434 +#define DOLBY_CORE2A_SWAP_CTRL2 0x3435 +#define DOLBY_CORE2A_SWAP_CTRL3 0x3436 +#define DOLBY_CORE2A_SWAP_CTRL4 0x3437 +#define DOLBY_CORE2A_SWAP_CTRL5 0x3438 +#define DOLBY_CORE2A_DMA_CTRL 0x3439 +#define DOLBY_CORE2A_DMA_STATUS 0x343a +#define DOLBY_CORE2A_STATUS0 0x343b +#define DOLBY_CORE2A_STATUS1 0x343c +#define DOLBY_CORE2A_STATUS2 0x343d +#define DOLBY_CORE2A_STATUS3 0x343e +#define DOLBY_CORE2A_DMA_PORT 0x343f + +#define DOLBY_CORE3_REG_START 0x3600 +#define DOLBY_CORE3_CLKGATE_CTRL 0x36f0 +#define DOLBY_CORE3_SWAP_CTRL0 0x36f1 +#define DOLBY_CORE3_SWAP_CTRL1 0x36f2 +#define DOLBY_CORE3_SWAP_CTRL2 0x36f3 +#define DOLBY_CORE3_SWAP_CTRL3 0x36f4 +#define DOLBY_CORE3_SWAP_CTRL4 0x36f5 +#define DOLBY_CORE3_SWAP_CTRL5 0x36f6 +#define DOLBY_CORE3_SWAP_CTRL6 0x36f7 +#define DOLBY_CORE3_CRC_CTRL 0x36fb +#define DOLBY_CORE3_INPUT_CSC_CRC 0x36fc +#define DOLBY_CORE3_OUTPUT_CSC_CRC 0x36fd + +#define VIU_MISC_CTRL1 0x1a07 +#define VPP_DOLBY_CTRL 0x1d93 +#define VIU_SW_RESET 0x1a01 +#define VPU_HDMI_FMT_CTRL 0x2743 + +#if 0 +/* core 1 display manager 24 registers */ +struct dm_register_ipcore_1_s { + uint32_t SRange; + uint32_t Srange_Inverse; + uint32_t Frame_Format_1; + uint32_t Frame_Format_2; + uint32_t Frame_Pixel_Def; + uint32_t Y2RGB_Coefficient_1; + uint32_t Y2RGB_Coefficient_2; + uint32_t Y2RGB_Coefficient_3; + uint32_t Y2RGB_Coefficient_4; + uint32_t Y2RGB_Coefficient_5; + uint32_t Y2RGB_Offset_1; + uint32_t Y2RGB_Offset_2; + uint32_t Y2RGB_Offset_3; + uint32_t EOTF; + uint32_t A2B_Coefficient_1; + uint32_t A2B_Coefficient_2; + uint32_t A2B_Coefficient_3; + uint32_t A2B_Coefficient_4; + uint32_t A2B_Coefficient_5; + uint32_t C2D_Coefficient_1; + uint32_t C2D_Coefficient_2; + uint32_t C2D_Coefficient_3; + uint32_t C2D_Coefficient_4; + uint32_t C2D_Coefficient_5; +}; + +/* core 1 composer 173 registers */ +struct composer_register_ipcore_s { + uint32_t Composer_Mode; + uint32_t VDR_Resolution; + uint32_t Bit_Depth; + uint32_t Coefficient_Log2_Denominator; + uint32_t BL_Num_Pivots_Y; + uint32_t BL_Pivot[5]; + uint32_t BL_Order; + uint32_t BL_Coefficient_Y[8][3]; + uint32_t EL_NLQ_Offset_Y; + uint32_t EL_Coefficient_Y[3]; + uint32_t Mapping_IDC_U; + uint32_t BL_Num_Pivots_U; + uint32_t BL_Pivot_U[3]; + uint32_t BL_Order_U; + uint32_t BL_Coefficient_U[4][3]; + uint32_t MMR_Coefficient_U[22][2]; + uint32_t MMR_Order_U; + uint32_t EL_NLQ_Offset_U; + uint32_t EL_Coefficient_U[3]; + uint32_t Mapping_IDC_V; + uint32_t BL_Num_Pivots_V; + uint32_t BL_Pivot_V[3]; + uint32_t BL_Order_V; + uint32_t BL_Coefficient_V[4][3]; + uint32_t MMR_Coefficient_V[22][2]; + uint32_t MMR_Order_V; + uint32_t EL_NLQ_Offset_V; + uint32_t EL_Coefficient_V[3]; +}; + +/* core 2 display manager 24 registers */ +struct dm_register_ipcore_2_s { + uint32_t SRange; + uint32_t Srange_Inverse; + uint32_t Y2RGB_Coefficient_1; + uint32_t Y2RGB_Coefficient_2; + uint32_t Y2RGB_Coefficient_3; + uint32_t Y2RGB_Coefficient_4; + uint32_t Y2RGB_Coefficient_5; + uint32_t Y2RGB_Offset_1; + uint32_t Y2RGB_Offset_2; + uint32_t Y2RGB_Offset_3; + uint32_t Frame_Format; + uint32_t EOTF; + uint32_t A2B_Coefficient_1; + uint32_t A2B_Coefficient_2; + uint32_t A2B_Coefficient_3; + uint32_t A2B_Coefficient_4; + uint32_t A2B_Coefficient_5; + uint32_t C2D_Coefficient_1; + uint32_t C2D_Coefficient_2; + uint32_t C2D_Coefficient_3; + uint32_t C2D_Coefficient_4; + uint32_t C2D_Coefficient_5; + uint32_t C2D_Offset; + uint32_t VDR_Resolution; +}; + +/* core 3 display manager 26 registers */ +struct dm_register_ipcore_3_s { + uint32_t D2C_coefficient_1; + uint32_t D2C_coefficient_2; + uint32_t D2C_coefficient_3; + uint32_t D2C_coefficient_4; + uint32_t D2C_coefficient_5; + uint32_t B2A_Coefficient_1; + uint32_t B2A_Coefficient_2; + uint32_t B2A_Coefficient_3; + uint32_t B2A_Coefficient_4; + uint32_t B2A_Coefficient_5; + uint32_t Eotf_param_1; + uint32_t Eotf_param_2; + uint32_t IPT_Scale; + uint32_t IPT_Offset_1; + uint32_t IPT_Offset_2; + uint32_t IPT_Offset_3; + uint32_t Output_range_1; + uint32_t Output_range_2; + uint32_t RGB2YUV_coefficient_register1; + uint32_t RGB2YUV_coefficient_register2; + uint32_t RGB2YUV_coefficient_register3; + uint32_t RGB2YUV_coefficient_register4; + uint32_t RGB2YUV_coefficient_register5; + uint32_t RGB2YUV_offset_0; + uint32_t RGB2YUV_offset_1; + uint32_t RGB2YUV_offset_2; +}; + +/* lut 5 * 256 for core 1 and core 2 */ +struct dm_lut_ipcore_s { + uint32_t TmLutI[64*4]; + uint32_t TmLutS[64*4]; + uint32_t SmLutI[64*4]; + uint32_t SmLutS[64*4]; + uint32_t G2L[256]; +}; + +/* core 3 metadata 128 registers */ +struct md_reister_ipcore_3_s { + uint32_t raw_metadata[128]; +}; +#endif + +#endif diff --git a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_hdr_regs.h b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_hdr_regs.h new file mode 100644 index 0000000..3d97c0b --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_hdr_regs.h @@ -0,0 +1,39 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/arch/vpp_hdr_regs.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef VPP_HDR_REGS_H +#define VPP_HDR_REGS_H + +#define XVYCC_LUT_R_ADDR_PORT 0x315e +#define XVYCC_LUT_R_DATA_PORT 0x315f +#define XVYCC_LUT_G_ADDR_PORT 0x3160 +#define XVYCC_LUT_G_DATA_PORT 0x3161 +#define XVYCC_LUT_B_ADDR_PORT 0x3162 +#define XVYCC_LUT_B_DATA_PORT 0x3163 +#define XVYCC_INV_LUT_CTL 0x3164 +#define XVYCC_LUT_CTL 0x3165 + +#define XVYCC_INV_LUT_Y_ADDR_PORT 0x3158 +#define XVYCC_INV_LUT_Y_DATA_PORT 0x3159 + +extern struct am_regs_s r_lut_hdr_hdr; +extern struct am_regs_s r_lut_sdr_sdr; +extern struct am_regs_s r_lut_hdr_sdr_level1; +extern struct am_regs_s r_lut_hdr_sdr_level2; +extern struct am_regs_s r_lut_hdr_sdr_level3; + +#endif diff --git a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h new file mode 100644 index 0000000..5521250 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h @@ -0,0 +1,747 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef VPP_REGS_HEADER_ +#define VPP_REGS_HEADER_ + + +#define VPP_DUMMY_DATA 0x1d00 +#define VPP_LINE_IN_LENGTH 0x1d01 +#define VPP_PIC_IN_HEIGHT 0x1d02 +#define VPP_SCALE_COEF_IDX 0x1d03 +#define VPP_SCALE_COEF 0x1d04 +#define VPP_VSC_REGION12_STARTP 0x1d05 +#define VPP_VSC_REGION34_STARTP 0x1d06 +#define VPP_VSC_REGION4_ENDP 0x1d07 +#define VPP_VSC_START_PHASE_STEP 0x1d08 +#define VPP_VSC_REGION0_PHASE_SLOPE 0x1d09 +#define VPP_VSC_REGION1_PHASE_SLOPE 0x1d0a +#define VPP_VSC_REGION3_PHASE_SLOPE 0x1d0b +#define VPP_VSC_REGION4_PHASE_SLOPE 0x1d0c +#define VPP_VSC_PHASE_CTRL 0x1d0d +#define VPP_VSC_INI_PHASE 0x1d0e +#define VPP_HSC_REGION12_STARTP 0x1d10 +#define VPP_HSC_REGION34_STARTP 0x1d11 +#define VPP_HSC_REGION4_ENDP 0x1d12 +#define VPP_HSC_START_PHASE_STEP 0x1d13 +#define VPP_HSC_REGION0_PHASE_SLOPE 0x1d14 +#define VPP_HSC_REGION1_PHASE_SLOPE 0x1d15 +#define VPP_HSC_REGION3_PHASE_SLOPE 0x1d16 +#define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17 +#define VPP_HSC_PHASE_CTRL 0x1d18 +#define VPP_SC_MISC 0x1d19 +#define VPP_PREBLEND_VD1_H_START_END 0x1d1a +#define VPP_PREBLEND_VD1_V_START_END 0x1d1b +#define VPP_POSTBLEND_VD1_H_START_END 0x1d1c +#define VPP_POSTBLEND_VD1_V_START_END 0x1d1d +#define VPP_BLEND_VD2_H_START_END 0x1d1e +#define VPP_BLEND_VD2_V_START_END 0x1d1f +#define VPP_PREBLEND_H_SIZE 0x1d20 +#define VPP_POSTBLEND_H_SIZE 0x1d21 +#define VPP_HOLD_LINES 0x1d22 +#define VPP_BLEND_ONECOLOR_CTRL 0x1d23 +#define VPP_PREBLEND_CURRENT_XY 0x1d24 +#define VPP_POSTBLEND_CURRENT_XY 0x1d25 +#define VPP_MISC 0x1d26 +#define VPP_OFIFO_SIZE 0x1d27 +#define VPP_FIFO_STATUS 0x1d28 +#define VPP_SMOKE_CTRL 0x1d29 +#define VPP_SMOKE1_VAL 0x1d2a +#define VPP_SMOKE2_VAL 0x1d2b +#define VPP_SMOKE3_VAL 0x1d2c +#define VPP_SMOKE1_H_START_END 0x1d2d +#define VPP_SMOKE1_V_START_END 0x1d2e +#define VPP_SMOKE2_H_START_END 0x1d2f +#define VPP_SMOKE2_V_START_END 0x1d30 +#define VPP_SMOKE3_H_START_END 0x1d31 +#define VPP_SMOKE3_V_START_END 0x1d32 +#define VPP_SCO_FIFO_CTRL 0x1d33 +#define VPP_HSC_PHASE_CTRL1 0x1d34 +#define VPP_HSC_INI_PAT_CTRL 0x1d35 +#define VPP_VADJ_CTRL 0x1d40 +#define VPP_VADJ1_Y 0x1d41 +#define VPP_VADJ1_MA_MB 0x1d42 +#define VPP_VADJ1_MC_MD 0x1d43 +#define VPP_VADJ2_Y 0x1d44 +#define VPP_VADJ2_MA_MB 0x1d45 +#define VPP_VADJ2_MC_MD 0x1d46 +#define VPP_HSHARP_CTRL 0x1d50 +#define VPP_HSHARP_LUMA_THRESH01 0x1d51 +#define VPP_HSHARP_LUMA_THRESH23 0x1d52 +#define VPP_HSHARP_CHROMA_THRESH01 0x1d53 +#define VPP_HSHARP_CHROMA_THRESH23 0x1d54 +#define VPP_HSHARP_LUMA_GAIN 0x1d55 +#define VPP_HSHARP_CHROMA_GAIN 0x1d56 +#define VPP_MATRIX_PROBE_COLOR 0x1d5c +#define VPP_MATRIX_PROBE_COLOR1 0x1dd7 +#define VPP_MATRIX_HL_COLOR 0x1d5d +#define VPP_MATRIX_PROBE_POS 0x1d5e +#define VPP_MATRIX_CTRL 0x1d5f +#define VPP_MATRIX_COEF00_01 0x1d60 +#define VPP_MATRIX_COEF02_10 0x1d61 +#define VPP_MATRIX_COEF11_12 0x1d62 +#define VPP_MATRIX_COEF20_21 0x1d63 +#define VPP_MATRIX_COEF22 0x1d64 +#define VPP_MATRIX_OFFSET0_1 0x1d65 +#define VPP_MATRIX_OFFSET2 0x1d66 +#define VPP_MATRIX_PRE_OFFSET0_1 0x1d67 +#define VPP_MATRIX_PRE_OFFSET2 0x1d68 +#define VPP_DUMMY_DATA1 0x1d69 +#define VPP_GAINOFF_CTRL0 0x1d6a +#define VPP_GAINOFF_CTRL1 0x1d6b +#define VPP_GAINOFF_CTRL2 0x1d6c +#define VPP_GAINOFF_CTRL3 0x1d6d +#define VPP_GAINOFF_CTRL4 0x1d6e +#define VPP_CHROMA_ADDR_PORT 0x1d70 +#define VPP_CHROMA_DATA_PORT 0x1d71 +#define VPP_GCLK_CTRL0 0x1d72 +#define VPP_GCLK_CTRL1 0x1d73 +#define VPP_SC_GCLK_CTRL 0x1d74 +#define VPP_MISC1 0x1d76 +#define VPP_BLACKEXT_CTRL 0x1d80 +#define VPP_DNLP_CTRL_00 0x1d81 +#define VPP_DNLP_CTRL_01 0x1d82 +#define VPP_DNLP_CTRL_02 0x1d83 +#define VPP_DNLP_CTRL_03 0x1d84 +#define VPP_DNLP_CTRL_04 0x1d85 +#define VPP_DNLP_CTRL_05 0x1d86 +#define VPP_DNLP_CTRL_06 0x1d87 +#define VPP_DNLP_CTRL_07 0x1d88 +#define VPP_DNLP_CTRL_08 0x1d89 +#define VPP_DNLP_CTRL_09 0x1d8a +#define VPP_DNLP_CTRL_10 0x1d8b +#define VPP_DNLP_CTRL_11 0x1d8c +#define VPP_DNLP_CTRL_12 0x1d8d +#define VPP_DNLP_CTRL_13 0x1d8e +#define VPP_DNLP_CTRL_14 0x1d8f +#define VPP_DNLP_CTRL_15 0x1d90 +#define VPP_SRSHARP0_CTRL 0x1d91 +#define VPP_SRSHARP1_CTRL 0x1d92 +#define VPP_PEAKING_NLP_1 0x1d93 +#define VPP_PEAKING_NLP_2 0x1d94 +#define VPP_PEAKING_NLP_3 0x1d95 +#define VPP_PEAKING_NLP_4 0x1d96 +#define VPP_PEAKING_NLP_5 0x1d97 +#define VPP_SHARP_LIMIT 0x1d98 +#define VPP_VLTI_CTRL 0x1d99 +#define VPP_HLTI_CTRL 0x1d9a +#define VPP_CTI_CTRL 0x1d9b +#define VPP_BLUE_STRETCH_1 0x1d9c +#define VPP_BLUE_STRETCH_2 0x1d9d +#define VPP_BLUE_STRETCH_3 0x1d9e +#define VPP_CCORING_CTRL 0x1da0 +#define VPP_VE_ENABLE_CTRL 0x1da1 +#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2 +#define VPP_VE_DEMO_CENTER_BAR 0x1da3 +#define VPP_VE_H_V_SIZE 0x1da4 +#define VPP_PSR_H_V_SIZE 0x1da5 +#define VPP_VDO_MEAS_CTRL 0x1da8 +#define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9 +#define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa +#define VPP_INPUT_CTRL 0x1dab +#define VPP_CTI_CTRL2 0x1dac +#define VPP_PEAKING_SAT_THD1 0x1dad +#define VPP_PEAKING_SAT_THD2 0x1dae +#define VPP_PEAKING_SAT_THD3 0x1daf +#define VPP_PEAKING_SAT_THD4 0x1db0 +#define VPP_PEAKING_SAT_THD5 0x1db1 +#define VPP_PEAKING_SAT_THD6 0x1db2 +#define VPP_PEAKING_SAT_THD7 0x1db3 +#define VPP_PEAKING_SAT_THD8 0x1db4 +#define VPP_PEAKING_SAT_THD9 0x1db5 +#define VPP_PEAKING_GAIN_ADD1 0x1db6 +#define VPP_PEAKING_GAIN_ADD2 0x1db7 +#define VPP_PEAKING_DNLP 0x1db8 +#define VPP_SHARP_DEMO_WIN_CTRL1 0x1db9 +#define VPP_SHARP_DEMO_WIN_CTRL2 0x1dba +#define VPP_FRONT_HLTI_CTRL 0x1dbb +#define VPP_FRONT_CTI_CTRL 0x1dbc +#define VPP_FRONT_CTI_CTRL2 0x1dbd +#define VPP_OSD_VSC_PHASE_STEP 0x1dc0 +#define VPP_OSD_VSC_INI_PHASE 0x1dc1 +#define VPP_OSD_VSC_CTRL0 0x1dc2 +#define VPP_OSD_HSC_PHASE_STEP 0x1dc3 +#define VPP_OSD_HSC_INI_PHASE 0x1dc4 +#define VPP_OSD_HSC_CTRL0 0x1dc5 +#define VPP_OSD_HSC_INI_PAT_CTRL 0x1dc6 +#define VPP_OSD_SC_DUMMY_DATA 0x1dc7 +#define VPP_OSD_SC_CTRL0 0x1dc8 +#define VPP_OSD_SCI_WH_M1 0x1dc9 +#define VPP_OSD_SCO_H_START_END 0x1dca +#define VPP_OSD_SCO_V_START_END 0x1dcb +#define VPP_OSD_SCALE_COEF_IDX 0x1dcc +#define VPP_OSD_SCALE_COEF 0x1dcd +#define VPP_INT_LINE_NUM 0x1dce +#define VPP_XVYCC_MISC 0x1dcf + +#define VPP_CLIP_MISC0 0x1dd9 + +#define VPP_MATRIX_CLIP 0x1dde +#define VPP_CLIP_MISC1 0x1dda +#define VPP_MATRIX_COEF13_14 0x1ddb +#define VPP_MATRIX_COEF23_24 0x1ddc +#define VPP_MATRIX_COEF15_25 0x1ddd +#define VPP_MATRIX_CLIP 0x1dde +#define VPP_XVYCC_MISC0 0x1ddf +#define VPP_XVYCC_MISC1 0x1de0 +#define VPP_VD1_CLIP_MISC0 0x1de1 +#define VPP_VD1_CLIP_MISC1 0x1de2 +#define VPP_VD2_CLIP_MISC0 0x1de3 +#define VPP_VD2_CLIP_MISC1 0x1de4 + +#define VPP2_DUMMY_DATA 0x1900 +#define VPP2_LINE_IN_LENGTH 0x1901 +#define VPP2_PIC_IN_HEIGHT 0x1902 +#define VPP2_SCALE_COEF_IDX 0x1903 +#define VPP2_SCALE_COEF 0x1904 +#define VPP2_VSC_REGION12_STARTP 0x1905 +#define VPP2_VSC_REGION34_STARTP 0x1906 +#define VPP2_VSC_REGION4_ENDP 0x1907 +#define VPP2_VSC_START_PHASE_STEP 0x1908 +#define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 +#define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a +#define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b +#define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c +#define VPP2_VSC_PHASE_CTRL 0x190d +#define VPP2_VSC_INI_PHASE 0x190e +#define VPP2_HSC_REGION12_STARTP 0x1910 +#define VPP2_HSC_REGION34_STARTP 0x1911 +#define VPP2_HSC_REGION4_ENDP 0x1912 +#define VPP2_HSC_START_PHASE_STEP 0x1913 +#define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914 +#define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915 +#define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916 +#define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917 +#define VPP2_HSC_PHASE_CTRL 0x1918 +#define VPP2_SC_MISC 0x1919 +#define VPP2_PREBLEND_VD1_H_START_END 0x191a +#define VPP2_PREBLEND_VD1_V_START_END 0x191b +#define VPP2_POSTBLEND_VD1_H_START_END 0x191c +#define VPP2_POSTBLEND_VD1_V_START_END 0x191d +#define VPP2_PREBLEND_H_SIZE 0x1920 +#define VPP2_POSTBLEND_H_SIZE 0x1921 +#define VPP2_HOLD_LINES 0x1922 +#define VPP2_BLEND_ONECOLOR_CTRL 0x1923 +#define VPP2_PREBLEND_CURRENT_XY 0x1924 +#define VPP2_POSTBLEND_CURRENT_XY 0x1925 +#define VPP2_MISC 0x1926 +#define VPP2_OFIFO_SIZE 0x1927 +#define VPP2_FIFO_STATUS 0x1928 +#define VPP2_SMOKE_CTRL 0x1929 +#define VPP2_SMOKE1_VAL 0x192a +#define VPP2_SMOKE2_VAL 0x192b +#define VPP2_SMOKE1_H_START_END 0x192d +#define VPP2_SMOKE1_V_START_END 0x192e +#define VPP2_SMOKE2_H_START_END 0x192f +#define VPP2_SMOKE2_V_START_END 0x1930 +#define VPP2_SCO_FIFO_CTRL 0x1933 +#define VPP2_HSC_PHASE_CTRL1 0x1934 +#define VPP2_HSC_INI_PAT_CTRL 0x1935 +#define VPP2_VADJ_CTRL 0x1940 +#define VPP2_VADJ1_Y 0x1941 +#define VPP2_VADJ1_MA_MB 0x1942 +#define VPP2_VADJ1_MC_MD 0x1943 +#define VPP2_VADJ2_Y 0x1944 +#define VPP2_VADJ2_MA_MB 0x1945 +#define VPP2_VADJ2_MC_MD 0x1946 +#define VPP2_MATRIX_PROBE_COLOR 0x195c +#define VPP2_MATRIX_HL_COLOR 0x195d +#define VPP2_MATRIX_PROBE_POS 0x195e +#define VPP2_MATRIX_CTRL 0x195f +#define VPP2_MATRIX_COEF00_01 0x1960 +#define VPP2_MATRIX_COEF02_10 0x1961 +#define VPP2_MATRIX_COEF11_12 0x1962 +#define VPP2_MATRIX_COEF20_21 0x1963 +#define VPP2_MATRIX_COEF22 0x1964 +#define VPP2_MATRIX_OFFSET0_1 0x1965 +#define VPP2_MATRIX_OFFSET2 0x1966 +#define VPP2_MATRIX_PRE_OFFSET0_1 0x1967 +#define VPP2_MATRIX_PRE_OFFSET2 0x1968 +#define VPP2_DUMMY_DATA1 0x1969 +#define VPP2_GAINOFF_CTRL0 0x196a +#define VPP2_GAINOFF_CTRL1 0x196b +#define VPP2_GAINOFF_CTRL2 0x196c +#define VPP2_GAINOFF_CTRL3 0x196d +#define VPP2_GAINOFF_CTRL4 0x196e +#define VPP2_CHROMA_ADDR_PORT 0x1970 +#define VPP2_CHROMA_DATA_PORT 0x1971 +#define VPP2_GCLK_CTRL0 0x1972 +#define VPP2_GCLK_CTRL1 0x1973 +#define VPP2_SC_GCLK_CTRL 0x1974 +#define VPP2_MISC1 0x1976 +#define VPP2_DNLP_CTRL_00 0x1981 +#define VPP2_DNLP_CTRL_01 0x1982 +#define VPP2_DNLP_CTRL_02 0x1983 +#define VPP2_DNLP_CTRL_03 0x1984 +#define VPP2_DNLP_CTRL_04 0x1985 +#define VPP2_DNLP_CTRL_05 0x1986 +#define VPP2_DNLP_CTRL_06 0x1987 +#define VPP2_DNLP_CTRL_07 0x1988 +#define VPP2_DNLP_CTRL_08 0x1989 +#define VPP2_DNLP_CTRL_09 0x198a +#define VPP2_DNLP_CTRL_10 0x198b +#define VPP2_DNLP_CTRL_11 0x198c +#define VPP2_DNLP_CTRL_12 0x198d +#define VPP2_DNLP_CTRL_13 0x198e +#define VPP2_DNLP_CTRL_14 0x198f +#define VPP2_DNLP_CTRL_15 0x1990 +#define VPP2_VE_ENABLE_CTRL 0x19a1 +#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 +#define VPP2_VE_DEMO_CENTER_BAR 0x19a3 +#define VPP2_VE_H_V_SIZE 0x19a4 +#define VPP2_VDO_MEAS_CTRL 0x19a8 +#define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9 +#define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa +#define VPP2_OSD_VSC_PHASE_STEP 0x19c0 +#define VPP2_OSD_VSC_INI_PHASE 0x19c1 +#define VPP2_OSD_VSC_CTRL0 0x19c2 +#define VPP2_OSD_HSC_PHASE_STEP 0x19c3 +#define VPP2_OSD_HSC_INI_PHASE 0x19c4 +#define VPP2_OSD_HSC_CTRL0 0x19c5 +#define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6 +#define VPP2_OSD_SC_DUMMY_DATA 0x19c7 +#define VPP2_OSD_SC_CTRL0 0x19c8 +#define VPP2_OSD_SCI_WH_M1 0x19c9 +#define VPP2_OSD_SCO_H_START_END 0x19ca +#define VPP2_OSD_SCO_V_START_END 0x19cb +#define VPP2_OSD_SCALE_COEF_IDX 0x19cc +#define VPP2_OSD_SCALE_COEF 0x19cd +#define VPP2_INT_LINE_NUM 0x19ce + +#define VIU_OSD1_BLK0_CFG_W0 0x1a1b +#define VIU_OSD1_MATRIX_CTRL 0x1a90 +#define VIU_OSD1_MATRIX_COEF00_01 0x1a91 +#define VIU_OSD1_MATRIX_COEF02_10 0x1a92 +#define VIU_OSD1_MATRIX_COEF11_12 0x1a93 +#define VIU_OSD1_MATRIX_COEF20_21 0x1a94 +#define VIU_OSD1_MATRIX_COLMOD_COEF42 0x1a95 +#define VIU_OSD1_MATRIX_OFFSET0_1 0x1a96 +#define VIU_OSD1_MATRIX_OFFSET2 0x1a97 +#define VIU_OSD1_MATRIX_PRE_OFFSET0_1 0x1a98 +#define VIU_OSD1_MATRIX_PRE_OFFSET2 0x1a99 +#define VIU_OSD1_MATRIX_COEF22_30 0x1a9d +#define VIU_OSD1_MATRIX_COEF31_32 0x1a9e +#define VIU_OSD1_MATRIX_COEF40_41 0x1a9f +#define VIU_OSD1_EOTF_CTL 0x1ad4 +#define VIU_OSD1_EOTF_COEF00_01 0x1ad5 +#define VIU_OSD1_EOTF_COEF02_10 0x1ad6 +#define VIU_OSD1_EOTF_COEF11_12 0x1ad7 +#define VIU_OSD1_EOTF_COEF20_21 0x1ad8 +#define VIU_OSD1_EOTF_COEF22_RS 0x1ad9 +#define VIU_OSD1_EOTF_LUT_ADDR_PORT 0x1ada +#define VIU_OSD1_EOTF_LUT_DATA_PORT 0x1adb +#define VIU_OSD1_OETF_CTL 0x1adc +#define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add +#define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade + +#define VI_HIST_CTRL 0x2e00 +#define VI_HIST_H_START_END 0x2e01 +#define VI_HIST_V_START_END 0x2e02 +#define VI_HIST_MAX_MIN 0x2e03 +#define VI_HIST_SPL_VAL 0x2e04 +#define VI_HIST_SPL_PIX_CNT 0x2e05 +#define VI_HIST_CHROMA_SUM 0x2e06 +#define VI_DNLP_HIST00 0x2e07 +#define VI_DNLP_HIST01 0x2e08 +#define VI_DNLP_HIST02 0x2e09 +#define VI_DNLP_HIST03 0x2e0a +#define VI_DNLP_HIST04 0x2e0b +#define VI_DNLP_HIST05 0x2e0c +#define VI_DNLP_HIST06 0x2e0d +#define VI_DNLP_HIST07 0x2e0e +#define VI_DNLP_HIST08 0x2e0f +#define VI_DNLP_HIST09 0x2e10 +#define VI_DNLP_HIST10 0x2e11 +#define VI_DNLP_HIST11 0x2e12 +#define VI_DNLP_HIST12 0x2e13 +#define VI_DNLP_HIST13 0x2e14 +#define VI_DNLP_HIST14 0x2e15 +#define VI_DNLP_HIST15 0x2e16 +#define VI_DNLP_HIST16 0x2e17 +#define VI_DNLP_HIST17 0x2e18 +#define VI_DNLP_HIST18 0x2e19 +#define VI_DNLP_HIST19 0x2e1a +#define VI_DNLP_HIST20 0x2e1b +#define VI_DNLP_HIST21 0x2e1c +#define VI_DNLP_HIST22 0x2e1d +#define VI_DNLP_HIST23 0x2e1e +#define VI_DNLP_HIST24 0x2e1f +#define VI_DNLP_HIST25 0x2e20 +#define VI_DNLP_HIST26 0x2e21 +#define VI_DNLP_HIST27 0x2e22 +#define VI_DNLP_HIST28 0x2e23 +#define VI_DNLP_HIST29 0x2e24 +#define VI_DNLP_HIST30 0x2e25 +#define VI_DNLP_HIST31 0x2e26 +#define VI_HIST_PIC_SIZE 0x2e28 +#define VI_HIST_BLACK_WHITE_VALUE 0x2e29 +#define VI_HIST_GCLK_CTRL 0x2e2a + +#define VPP_IN_H_V_SIZE 0x1da6 + + +/* 3D process */ +#define VPU_VPU_3D_SYNC1 0x2738 +#define VPU_VPU_3D_SYNC2 0x2739 +#define VPU_VPU_PWM_V0 0x2730 +#define VPU_VIU_VENC_MUX_CTRL 0x271a +#define VIU_MISC_CTRL0 0x1a06 +#define VPU_VLOCK_CTRL 0x3000 +#define VPU_VLOCK_MISC_CTRL 0x3001 +#define VPU_VLOCK_LOOP0_ACCUM_LMT 0x3002 +#define VPU_VLOCK_LOOP0_CTRL0 0x3003 +#define VPU_VLOCK_LOOP1_CTRL0 0x3004 +#define VPU_VLOCK_LOOP1_IMISSYNC_MAX 0x3005 +#define VPU_VLOCK_LOOP1_IMISSYNC_MIN 0x3006 +#define VPU_VLOCK_OVWRITE_ACCUM0 0x3007 +#define VPU_VLOCK_OVWRITE_ACCUM1 0x3008 +#define VPU_VLOCK_OUTPUT0_CAPT_LMT 0x3009 +#define VPU_VLOCK_OUTPUT0_PLL_LMT 0x300a +#define VPU_VLOCK_OUTPUT1_CAPT_LMT 0x300b +#define VPU_VLOCK_OUTPUT1_PLL_LMT 0x300c +#define VPU_VLOCK_LOOP1_PHSDIF_TGT 0x300d +#define VPU_VLOCK_RO_LOOP0_ACCUM 0x300e +#define VPU_VLOCK_RO_LOOP1_ACCUM 0x300f +#define VPU_VLOCK_OROW_OCOL_MAX 0x3010 +#define VPU_VLOCK_RO_VS_I_DIST 0x3011 +#define VPU_VLOCK_RO_VS_O_DIST 0x3012 +#define VPU_VLOCK_RO_LINE_PIX_ADJ 0x3013 +#define VPU_VLOCK_RO_OUTPUT_00_01 0x3014 +#define VPU_VLOCK_RO_OUTPUT_10_11 0x3015 +#define VPU_VLOCK_MX4096 0x3016 +#define VPU_VLOCK_STBDET_WIN0_WIN1 0x3017 +#define VPU_VLOCK_STBDET_CLP 0x3018 +#define VPU_VLOCK_STBDET_ABS_WIN0 0x3019 +#define VPU_VLOCK_STBDET_ABS_WIN1 0x301a +#define VPU_VLOCK_STBDET_SGN_WIN0 0x301b +#define VPU_VLOCK_STBDET_SGN_WIN1 0x301c +#define VPU_VLOCK_ADJ_EN_SYNC_CTRL 0x301d +#define VPU_VLOCK_GCLK_EN 0x301e +#define VPU_VLOCK_LOOP1_ACCUM_LMT 0x301f +#define VPU_VLOCK_RO_M_INT_FRAC 0x3020 + +#define XVYCC_VD1_RGB_CTRST 0x3170 + +#define VIU_EOTF_CTL 0x31d0 +#define VIU_EOTF_COEF00_01 0x31d1 +#define VIU_EOTF_COEF02_10 0x31d2 +#define VIU_EOTF_COEF11_12 0x31d3 +#define VIU_EOTF_COEF20_21 0x31d4 +#define VIU_EOTF_COEF22_RS 0x31d5 +#define VIU_EOTF_LUT_ADDR_PORT 0x31d6 +#define VIU_EOTF_LUT_DATA_PORT 0x31d7 + +/* sharpness */ +#define SRSHARP0_PK_FINALGAIN_HP_BP 0x3222 +#define SRSHARP0_SHARP_PK_NR_ENABLE 0x3227 +#define SRSHARP0_SHARP_DNLP_EN 0x3245 +#define SRSHARP1_PK_FINALGAIN_HP_BP 0x32a2 +#define SRSHARP1_SHARP_PK_NR_ENABLE 0x32a7 +#define SRSHARP1_SHARP_DNLP_EN 0x32c5 + +/*sr0 sr1 ybic cbic*/ +#define SRSHARP0_SHARP_SR2_YBIC_HCOEF0 0x3258 +#define SRSHARP0_SHARP_SR2_CBIC_HCOEF0 0x325a +#define SRSHARP0_SHARP_SR2_YBIC_VCOEF0 0x325c +#define SRSHARP0_SHARP_SR2_CBIC_VCOEF0 0x325e + +#define SRSHARP1_SHARP_SR2_YBIC_HCOEF0 0x32d8 +#define SRSHARP1_SHARP_SR2_CBIC_HCOEF0 0x32da +#define SRSHARP1_SHARP_SR2_YBIC_VCOEF0 0x32dc +#define SRSHARP1_SHARP_SR2_CBIC_VCOEF0 0x32de + +/*sr0 sr1 lti cti*/ +#define SRSHARP0_HCTI_FLT_CLP_DC 0x322e/*bit28*/ +#define SRSHARP0_HLTI_FLT_CLP_DC 0x3234 +#define SRSHARP0_VLTI_FLT_CON_CLP 0x323a/*bit14*/ +#define SRSHARP0_VCTI_FLT_CON_CLP 0x323f + +#define SRSHARP1_HCTI_FLT_CLP_DC 0x32ae/*bit28*/ +#define SRSHARP1_HLTI_FLT_CLP_DC 0x32b4 +#define SRSHARP1_VLTI_FLT_CON_CLP 0x32ba/*bit14*/ +#define SRSHARP1_VCTI_FLT_CON_CLP 0x32bf + +/*sr0 sr1 dejaggy/direction/dering*/ +#define SRSHARP0_DEJ_CTRL 0x3264/*bit 0*/ +#define SRSHARP0_SR3_DRTLPF_EN 0x3266/*bit 0-2*/ +#define SRSHARP0_SR3_DERING_CTRL 0x326b/*bit 28-30*/ + +#define SRSHARP1_DEJ_CTRL 0x32e4/*bit 0*/ +#define SRSHARP1_SR3_DRTLPF_EN 0x32e6/*bit 0-2*/ +#define SRSHARP1_SR3_DERING_CTRL 0x32eb/*bit 28-30*/ + +/* for pll bug */ +#define HHI_HDMI_PLL_CNTL 0x10c8 +#define HHI_HDMI_PLL_CNTL2 0x10c9 +#define HHI_VID_LOCK_CLK_CNTL 0x10f2 +#define HHI_HDMI_PLL_CNTL6 0x10cd +#define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8 +/* #define P_ENCL_MAX_LINE_SWITCH_POINT */ +/* VCBUS_REG_ADDR(ENCL_MAX_LINE_SWITCH_POINT) */ +#define HHI_VID_LOCK_CLK_CNTL 0x10f2 + +#define ENCL_VIDEO_MAX_LNCNT 0x1cbb +#define VDIN_MEAS_VS_COUNT_LO 0x125c +/*after GXL new add CNTL1,same with CNTL2 on G9TV/GXTVBB*/ +#define HHI_HDMI_PLL_CNTL1 0x10c9 +/*after GXL CNTL5[bit3] is same with CNTL6[bit20] on G9TV/GXTVBB*/ +#define HHI_HDMI_PLL_CNTL5 0x10cd + + +/* #define VI_HIST_CTRL 0x2e00 */ +/* the total pixels = VDIN_HISTXX*(2^(VDIN_HIST_POW+3)) */ +#define VI_HIST_POW_BIT 5 +#define VI_HIST_POW_WID 3 +/* Histgram range: 0: full picture, 1: histgram window*/ +/* defined by VDIN_HIST_H_START_END & VDIN_HIST_V_START_END */ +#define VI_HIST_WIN_EN_BIT 1 +#define VI_HIST_WIN_EN_WID 1 +/* Histgram readback: 0: disable, 1: enable */ +#define VI_HIST_RD_EN_BIT 0 +#define VI_HIST_RD_EN_WID 1 + +/* #define VDIN_HIST_H_START_END 0x1231 */ +#define VI_HIST_HSTART_BIT 16 +#define VI_HIST_HSTART_WID 13 +#define VI_HIST_HEND_BIT 0 +#define VI_HIST_HEND_WID 13 + +/* #define VDIN_HIST_V_START_END 0x1232 */ +#define VI_HIST_VSTART_BIT 16 +#define VI_HIST_VSTART_WID 13 +#define VI_HIST_VEND_BIT 0 +#define VI_HIST_VEND_WID 13 + +/* #define VDIN_HIST_MAX_MIN 0x1233 */ +#define VI_HIST_MAX_BIT 8 +#define VI_HIST_MAX_WID 8 +#define VI_HIST_MIN_BIT 0 +#define VI_HIST_MIN_WID 8 + +/* #define VDIN_HIST_SPL_VAL 0x1234 */ +#define VI_HIST_LUMA_SUM_BIT 0 +#define VI_HIST_LUMA_SUM_WID 32 + + /* the total calculated pixels */ +/* #define VDIN_HIST_SPL_PIX_CNT 0x1235 */ +#define VI_HIST_PIX_CNT_BIT 0 +#define VI_HIST_PIX_CNT_WID 22 + +/* the total chroma value */ +/* #define VDIN_HIST_CHROMA_SUM 0x1236 */ +#define VI_HIST_CHROMA_SUM_BIT 0 +#define VI_HIST_CHROMA_SUM_WID 32 + +/* #define VDIN_DNLP_HIST00 0x1237 */ +#define VI_HIST_ON_BIN_01_BIT 16 +#define VI_HIST_ON_BIN_01_WID 16 +#define VI_HIST_ON_BIN_00_BIT 0 +#define VI_HIST_ON_BIN_00_WID 16 + +/* #define VDIN_DNLP_HIST01 0x1238 */ +#define VI_HIST_ON_BIN_03_BIT 16 +#define VI_HIST_ON_BIN_03_WID 16 +#define VI_HIST_ON_BIN_02_BIT 0 +#define VI_HIST_ON_BIN_02_WID 16 + +/* #define VDIN_DNLP_HIST02 0x1239 */ +#define VI_HIST_ON_BIN_05_BIT 16 +#define VI_HIST_ON_BIN_05_WID 16 +#define VI_HIST_ON_BIN_04_BIT 0 +#define VI_HIST_ON_BIN_04_WID 16 + +/* #define VDIN_DNLP_HIST03 0x123a */ +#define VI_HIST_ON_BIN_07_BIT 16 +#define VI_HIST_ON_BIN_07_WID 16 +#define VI_HIST_ON_BIN_06_BIT 0 +#define VI_HIST_ON_BIN_06_WID 16 + +/* #define VDIN_DNLP_HIST04 0x123b */ +#define VI_HIST_ON_BIN_09_BIT 16 +#define VI_HIST_ON_BIN_09_WID 16 +#define VI_HIST_ON_BIN_08_BIT 0 +#define VI_HIST_ON_BIN_08_WID 16 + +/* #define VDIN_DNLP_HIST05 0x123c */ +#define VI_HIST_ON_BIN_11_BIT 16 +#define VI_HIST_ON_BIN_11_WID 16 +#define VI_HIST_ON_BIN_10_BIT 0 +#define VI_HIST_ON_BIN_10_WID 16 + +/* #define VDIN_DNLP_HIST06 0x123d */ +#define VI_HIST_ON_BIN_13_BIT 16 +#define VI_HIST_ON_BIN_13_WID 16 +#define VI_HIST_ON_BIN_12_BIT 0 +#define VI_HIST_ON_BIN_12_WID 16 + +/* #define VDIN_DNLP_HIST07 0x123e */ +#define VI_HIST_ON_BIN_15_BIT 16 +#define VI_HIST_ON_BIN_15_WID 16 +#define VI_HIST_ON_BIN_14_BIT 0 +#define VI_HIST_ON_BIN_14_WID 16 + +/* #define VDIN_DNLP_HIST08 0x123f */ +#define VI_HIST_ON_BIN_17_BIT 16 +#define VI_HIST_ON_BIN_17_WID 16 +#define VI_HIST_ON_BIN_16_BIT 0 +#define VI_HIST_ON_BIN_16_WID 16 + +/* #define VDIN_DNLP_HIST09 0x1240 */ +#define VI_HIST_ON_BIN_19_BIT 16 +#define VI_HIST_ON_BIN_19_WID 16 +#define VI_HIST_ON_BIN_18_BIT 0 +#define VI_HIST_ON_BIN_18_WID 16 + +/* #define VDIN_DNLP_HIST10 0x1241 */ +#define VI_HIST_ON_BIN_21_BIT 16 +#define VI_HIST_ON_BIN_21_WID 16 +#define VI_HIST_ON_BIN_20_BIT 0 +#define VI_HIST_ON_BIN_20_WID 16 + +/* #define VDIN_DNLP_HIST11 0x1242 */ +#define VI_HIST_ON_BIN_23_BIT 16 +#define VI_HIST_ON_BIN_23_WID 16 +#define VI_HIST_ON_BIN_22_BIT 0 +#define VI_HIST_ON_BIN_22_WID 16 + +/* #define VDIN_DNLP_HIST12 0x1243 */ +#define VI_HIST_ON_BIN_25_BIT 16 +#define VI_HIST_ON_BIN_25_WID 16 +#define VI_HIST_ON_BIN_24_BIT 0 +#define VI_HIST_ON_BIN_24_WID 16 + +/* #define VDIN_DNLP_HIST13 0x1244 */ +#define VI_HIST_ON_BIN_27_BIT 16 +#define VI_HIST_ON_BIN_27_WID 16 +#define VI_HIST_ON_BIN_26_BIT 0 +#define VI_HIST_ON_BIN_26_WID 16 + +/* #define VDIN_DNLP_HIST14 0x1245 */ +#define VI_HIST_ON_BIN_29_BIT 16 +#define VI_HIST_ON_BIN_29_WID 16 +#define VI_HIST_ON_BIN_28_BIT 0 +#define VI_HIST_ON_BIN_28_WID 16 + +/* #define VDIN_DNLP_HIST15 0x1246 */ +#define VI_HIST_ON_BIN_31_BIT 16 +#define VI_HIST_ON_BIN_31_WID 16 +#define VI_HIST_ON_BIN_30_BIT 0 +#define VI_HIST_ON_BIN_30_WID 16 + +/* #define VDIN_DNLP_HIST16 0x1247 */ +#define VI_HIST_ON_BIN_33_BIT 16 +#define VI_HIST_ON_BIN_33_WID 16 +#define VI_HIST_ON_BIN_32_BIT 0 +#define VI_HIST_ON_BIN_32_WID 16 + +/* #define VDIN_DNLP_HIST17 0x1248 */ +#define VI_HIST_ON_BIN_35_BIT 16 +#define VI_HIST_ON_BIN_35_WID 16 +#define VI_HIST_ON_BIN_34_BIT 0 +#define VI_HIST_ON_BIN_34_WID 16 + +/* #define VDIN_DNLP_HIST18 0x1249 */ +#define VI_HIST_ON_BIN_37_BIT 16 +#define VI_HIST_ON_BIN_37_WID 16 +#define VI_HIST_ON_BIN_36_BIT 0 +#define VI_HIST_ON_BIN_36_WID 16 + +/* #define VDIN_DNLP_HIST19 0x124a */ +#define VI_HIST_ON_BIN_39_BIT 16 +#define VI_HIST_ON_BIN_39_WID 16 +#define VI_HIST_ON_BIN_38_BIT 0 +#define VI_HIST_ON_BIN_38_WID 16 + +/* #define VDIN_DNLP_HIST20 0x124b */ +#define VI_HIST_ON_BIN_41_BIT 16 +#define VI_HIST_ON_BIN_41_WID 16 +#define VI_HIST_ON_BIN_40_BIT 0 +#define VI_HIST_ON_BIN_40_WID 16 + +/* #define VDIN_DNLP_HIST21 0x124c */ +#define VI_HIST_ON_BIN_43_BIT 16 +#define VI_HIST_ON_BIN_43_WID 16 +#define VI_HIST_ON_BIN_42_BIT 0 +#define VI_HIST_ON_BIN_42_WID 16 + +/* #define VDIN_DNLP_HIST22 0x124d */ +#define VI_HIST_ON_BIN_45_BIT 16 +#define VI_HIST_ON_BIN_45_WID 16 +#define VI_HIST_ON_BIN_44_BIT 0 +#define VI_HIST_ON_BIN_44_WID 16 + +/* #define VDIN_DNLP_HIST23 0x124e */ +#define VI_HIST_ON_BIN_47_BIT 16 +#define VI_HIST_ON_BIN_47_WID 16 +#define VI_HIST_ON_BIN_46_BIT 0 +#define VI_HIST_ON_BIN_46_WID 16 + +/* #define VDIN_DNLP_HIST24 0x124f */ +#define VI_HIST_ON_BIN_49_BIT 16 +#define VI_HIST_ON_BIN_49_WID 16 +#define VI_HIST_ON_BIN_48_BIT 0 +#define VI_HIST_ON_BIN_48_WID 16 + +/* #define VDIN_DNLP_HIST25 0x1250 */ +#define VI_HIST_ON_BIN_51_BIT 16 +#define VI_HIST_ON_BIN_51_WID 16 +#define VI_HIST_ON_BIN_50_BIT 0 +#define VI_HIST_ON_BIN_50_WID 16 + +/* #define VDIN_DNLP_HIST26 0x1251 */ +#define VI_HIST_ON_BIN_53_BIT 16 +#define VI_HIST_ON_BIN_53_WID 16 +#define VI_HIST_ON_BIN_52_BIT 0 +#define VI_HIST_ON_BIN_52_WID 16 + +/* #define VDIN_DNLP_HIST27 0x1252 */ +#define VI_HIST_ON_BIN_55_BIT 16 +#define VI_HIST_ON_BIN_55_WID 16 +#define VI_HIST_ON_BIN_54_BIT 0 +#define VI_HIST_ON_BIN_54_WID 16 + +/* #define VDIN_DNLP_HIST28 0x1253 */ +#define VI_HIST_ON_BIN_57_BIT 16 +#define VI_HIST_ON_BIN_57_WID 16 +#define VI_HIST_ON_BIN_56_BIT 0 +#define VI_HIST_ON_BIN_56_WID 16 + +/* #define VDIN_DNLP_HIST29 0x1254 */ +#define VI_HIST_ON_BIN_59_BIT 16 +#define VI_HIST_ON_BIN_59_WID 16 +#define VI_HIST_ON_BIN_58_BIT 0 +#define VI_HIST_ON_BIN_58_WID 16 + +/* #define VDIN_DNLP_HIST30 0x1255 */ +#define VI_HIST_ON_BIN_61_BIT 16 +#define VI_HIST_ON_BIN_61_WID 16 +#define VI_HIST_ON_BIN_60_BIT 0 +#define VI_HIST_ON_BIN_60_WID 16 + +/* #define VDIN_DNLP_HIST31 0x1256 */ +#define VI_HIST_ON_BIN_63_BIT 16 +#define VI_HIST_ON_BIN_63_WID 16 +#define VI_HIST_ON_BIN_62_BIT 0 +#define VI_HIST_ON_BIN_62_WID 16 + +/* #define VDIN_HIST_PIC_SIZE 0x2e28 */ +#define VI_HIST_PIC_HEIGHT_BIT 16 +#define VI_HIST_PIC_HEIGHT_WID 13 +#define VI_HIST_PIC_WIDTH_BIT 0 +#define VI_HIST_PIC_WIDTH_WID 13 +#endif + diff --git a/drivers/amlogic/media/enhancement/amvecm/dolby_vision/dolby_vision.h b/drivers/amlogic/media/enhancement/amvecm/dolby_vision/dolby_vision.h new file mode 100644 index 0000000..d550b88 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/dolby_vision/dolby_vision.h @@ -0,0 +1,302 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/dolby_vision/dolby_vision.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef _DV_H_ +#define _DV_H_ + +#include + +#define DEF_G2L_LUT_SIZE_2P 8 +#define DEF_G2L_LUT_SIZE (1 << DEF_G2L_LUT_SIZE_2P) + +enum signal_format_e { + FORMAT_DOVI = 0, + FORMAT_HDR10 = 1, + FORMAT_SDR = 2 +}; + +enum priority_mode_e { + VIDEO_PRIORITY = 0, + GRAPHIC_PRIORITY = 1 +}; + +enum cp_signal_range_e { + SIG_RANGE_SMPTE = 0, /* head range */ + SIG_RANGE_FULL = 1, /* full range */ + SIG_RANGE_SDI = 2 /* PQ */ +}; + +struct composer_register_ipcore_s { + uint32_t Composer_Mode; + uint32_t VDR_Resolution; + uint32_t Bit_Depth; + uint32_t Coefficient_Log2_Denominator; + uint32_t BL_Num_Pivots_Y; + uint32_t BL_Pivot[5]; + uint32_t BL_Order; + uint32_t BL_Coefficient_Y[8][3]; + uint32_t EL_NLQ_Offset_Y; + uint32_t EL_Coefficient_Y[3]; + uint32_t Mapping_IDC_U; + uint32_t BL_Num_Pivots_U; + uint32_t BL_Pivot_U[3]; + uint32_t BL_Order_U; + uint32_t BL_Coefficient_U[4][3]; + uint32_t MMR_Coefficient_U[22][2]; + uint32_t MMR_Order_U; + uint32_t EL_NLQ_Offset_U; + uint32_t EL_Coefficient_U[3]; + uint32_t Mapping_IDC_V; + uint32_t BL_Num_Pivots_V; + uint32_t BL_Pivot_V[3]; + uint32_t BL_Order_V; + uint32_t BL_Coefficient_V[4][3]; + uint32_t MMR_Coefficient_V[22][2]; + uint32_t MMR_Order_V; + uint32_t EL_NLQ_Offset_V; + uint32_t EL_Coefficient_V[3]; +}; + +/** @brief DM registers for IPCORE 1 */ +struct dm_register_ipcore_1_s { + uint32_t SRange; + uint32_t Srange_Inverse; + uint32_t Frame_Format_1; + uint32_t Frame_Format_2; + uint32_t Frame_Pixel_Def; + uint32_t Y2RGB_Coefficient_1; + uint32_t Y2RGB_Coefficient_2; + uint32_t Y2RGB_Coefficient_3; + uint32_t Y2RGB_Coefficient_4; + uint32_t Y2RGB_Coefficient_5; + uint32_t Y2RGB_Offset_1; + uint32_t Y2RGB_Offset_2; + uint32_t Y2RGB_Offset_3; + uint32_t EOTF; + uint32_t A2B_Coefficient_1; + uint32_t A2B_Coefficient_2; + uint32_t A2B_Coefficient_3; + uint32_t A2B_Coefficient_4; + uint32_t A2B_Coefficient_5; + uint32_t C2D_Coefficient_1; + uint32_t C2D_Coefficient_2; + uint32_t C2D_Coefficient_3; + uint32_t C2D_Coefficient_4; + uint32_t C2D_Coefficient_5; + uint32_t C2D_Offset; + uint32_t Active_area_left_top; + uint32_t Active_area_bottom_right; +}; + +/** @brief DM registers for IPCORE 2 */ +struct dm_register_ipcore_2_s { + uint32_t SRange; + uint32_t Srange_Inverse; + uint32_t Y2RGB_Coefficient_1; + uint32_t Y2RGB_Coefficient_2; + uint32_t Y2RGB_Coefficient_3; + uint32_t Y2RGB_Coefficient_4; + uint32_t Y2RGB_Coefficient_5; + uint32_t Y2RGB_Offset_1; + uint32_t Y2RGB_Offset_2; + uint32_t Y2RGB_Offset_3; + uint32_t Frame_Format; + uint32_t EOTF; + uint32_t A2B_Coefficient_1; + uint32_t A2B_Coefficient_2; + uint32_t A2B_Coefficient_3; + uint32_t A2B_Coefficient_4; + uint32_t A2B_Coefficient_5; + uint32_t C2D_Coefficient_1; + uint32_t C2D_Coefficient_2; + uint32_t C2D_Coefficient_3; + uint32_t C2D_Coefficient_4; + uint32_t C2D_Coefficient_5; + uint32_t C2D_Offset; + uint32_t VDR_Resolution; +}; + +/** @brief DM registers for IPCORE 3 */ +struct dm_register_ipcore_3_s { + uint32_t D2C_coefficient_1; + uint32_t D2C_coefficient_2; + uint32_t D2C_coefficient_3; + uint32_t D2C_coefficient_4; + uint32_t D2C_coefficient_5; + uint32_t B2A_Coefficient_1; + uint32_t B2A_Coefficient_2; + uint32_t B2A_Coefficient_3; + uint32_t B2A_Coefficient_4; + uint32_t B2A_Coefficient_5; + uint32_t Eotf_param_1; + uint32_t Eotf_param_2; + uint32_t IPT_Scale; + uint32_t IPT_Offset_1; + uint32_t IPT_Offset_2; + uint32_t IPT_Offset_3; + uint32_t Output_range_1; + uint32_t Output_range_2; + uint32_t RGB2YUV_coefficient_register1; + uint32_t RGB2YUV_coefficient_register2; + uint32_t RGB2YUV_coefficient_register3; + uint32_t RGB2YUV_coefficient_register4; + uint32_t RGB2YUV_coefficient_register5; + uint32_t RGB2YUV_offset_0; + uint32_t RGB2YUV_offset_1; + uint32_t RGB2YUV_offset_2; +}; + +/** @brief DM luts for IPCORE 1 and 2 */ +struct dm_lut_ipcore_s { + uint32_t TmLutI[64*4]; + uint32_t TmLutS[64*4]; + uint32_t SmLutI[64*4]; + uint32_t SmLutS[64*4]; + uint32_t G2L[DEF_G2L_LUT_SIZE]; +}; + +/** @brief hdmi metadata for IPCORE 3 */ +struct md_reister_ipcore_3_s { + uint32_t raw_metadata[128]; + uint32_t size; +}; + +struct hdr_10_infoframe_s { + uint8_t infoframe_type_code; + uint8_t infoframe_version_number; + uint8_t length_of_info_frame; + uint8_t data_byte_1; + uint8_t data_byte_2; + uint8_t display_primaries_x_0_LSB; + uint8_t display_primaries_x_0_MSB; + uint8_t display_primaries_y_0_LSB; + uint8_t display_primaries_y_0_MSB; + uint8_t display_primaries_x_1_LSB; + uint8_t display_primaries_x_1_MSB; + uint8_t display_primaries_y_1_LSB; + uint8_t display_primaries_y_1_MSB; + uint8_t display_primaries_x_2_LSB; + uint8_t display_primaries_x_2_MSB; + uint8_t display_primaries_y_2_LSB; + uint8_t display_primaries_y_2_MSB; + uint8_t white_point_x_LSB; + uint8_t white_point_x_MSB; + uint8_t white_point_y_LSB; + uint8_t white_point_y_MSB; + uint8_t max_display_mastering_luminance_LSB; + uint8_t max_display_mastering_luminance_MSB; + uint8_t min_display_mastering_luminance_LSB; + uint8_t min_display_mastering_luminance_MSB; + uint8_t max_content_light_level_LSB; + uint8_t max_content_light_level_MSB; + uint8_t max_frame_average_light_level_LSB; + uint8_t max_frame_average_light_level_MSB; +}; + +struct hdr10_param_s { + uint32_t min_display_mastering_luminance; + uint32_t max_display_mastering_luminance; + uint16_t Rx; + uint16_t Ry; + uint16_t Gx; + uint16_t Gy; + uint16_t Bx; + uint16_t By; + uint16_t Wx; + uint16_t Wy; + uint16_t max_content_light_level; + uint16_t max_pic_average_light_level; +}; + +struct dovi_setting_s { + struct composer_register_ipcore_s comp_reg; + struct dm_register_ipcore_1_s dm_reg1; + struct dm_register_ipcore_2_s dm_reg2; + struct dm_register_ipcore_3_s dm_reg3; + struct dm_lut_ipcore_s dm_lut1; + struct dm_lut_ipcore_s dm_lut2; + /* for dovi output */ + struct md_reister_ipcore_3_s md_reg3; + /* for hdr10 output */ + struct hdr_10_infoframe_s hdr_info; + /* current process */ + enum signal_format_e src_format; + enum signal_format_e dst_format; + /* enhanced layer */ + bool el_flag; + bool el_halfsize_flag; + /* frame width & height */ + uint32_t video_width; + uint32_t video_height; +}; + +extern int control_path( + enum signal_format_e in_format, + enum signal_format_e out_format, + char *in_comp, int in_comp_size, + char *in_md, int in_md_size, + enum priority_mode_e set_priority, + int set_bit_depth, int set_chroma_format, int set_yuv_range, + int set_graphic_min_lum, int set_graphic_max_lum, + int set_target_min_lum, int set_target_max_lum, + int set_no_el, + struct hdr10_param_s *hdr10_param, + struct dovi_setting_s *output); +extern void *metadata_parser_init(int flag); +extern int metadata_parser_reset(int flag); +extern int metadata_parser_process( + char *src_rpu, int rpu_len, + char *dst_comp, int *comp_len, + char *dst_md, int *md_len, bool src_eos); +extern void metadata_parser_release(void); + +struct dolby_vision_func_s { + void * (*metadata_parser_init)(int); + int (*metadata_parser_reset)(int flag); + int (*metadata_parser_process)( + char *src_rpu, int rpu_len, + char *dst_comp, int *comp_len, + char *dst_md, int *md_len, bool src_eos); + void (*metadata_parser_release)(void); + int (*control_path)( + enum signal_format_e in_format, + enum signal_format_e out_format, + char *in_comp, int in_comp_size, + char *in_md, int in_md_size, + enum priority_mode_e set_priority, + int set_bit_depth, int set_chroma_format, int set_yuv_range, + int set_graphic_min_lum, int set_graphic_max_lum, + int set_target_min_lum, int set_target_max_lum, + int set_no_el, + struct hdr10_param_s *hdr10_param, + struct dovi_setting_s *output); +}; + +extern int register_dv_functions(const struct dolby_vision_func_s *func); +extern int unregister_dv_functions(void); +#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA +#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val) +#define VSYNC_RD_MPEG_REG(adr) READ_VPP_REG(adr) +#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \ + WRITE_VPP_REG_BITS(adr, val, start, len) +#else +extern int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len); +extern u32 VSYNC_RD_MPEG_REG(u32 adr); +extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val); +#endif + +#endif diff --git a/drivers/amlogic/media/video_sink/video.c b/drivers/amlogic/media/video_sink/video.c index f262d13..a65d642 100644 --- a/drivers/amlogic/media/video_sink/video.c +++ b/drivers/amlogic/media/video_sink/video.c @@ -49,7 +49,7 @@ #include #include "video_priv.h" -#if defined(CONFIG_AM_VECM) +#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) #include #endif #include @@ -3671,7 +3671,7 @@ static irqreturn_t vsync_isr(int irq, void *dev_id) } #endif -#if defined(CONFIG_AM_VECM) +#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) amvecm_on_vs(vf); #endif #ifdef CONFIG_TVIN_VDIN @@ -3876,7 +3876,7 @@ static irqreturn_t vsync_isr(int irq, void *dev_id) } #endif -#if defined(CONFIG_AM_VECM) +#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) refresh_on_vs(vf); #endif diff --git a/include/linux/amlogic/media/amvecm/amvecm.h b/include/linux/amlogic/media/amvecm/amvecm.h new file mode 100644 index 0000000..947cdf2 --- /dev/null +++ b/include/linux/amlogic/media/amvecm/amvecm.h @@ -0,0 +1,199 @@ +/* + * include/linux/amlogic/media/amvecm/amvecm.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef AMVECM_H +#define AMVECM_H + +#include "linux/amlogic/media/amvecm/ve.h" +#include "linux/amlogic/media/amvecm/cm.h" +#include +#include + +/* struct ve_dnlp_s video_ve_dnlp; */ + +#define FLAG_RSV31 (1 << 31) +#define FLAG_VADJ1_COLOR (1 << 30) +#define FLAG_VE_DNLP (1 << 29) +#define FLAG_VE_NEW_DNLP (1 << 28) +#define FLAG_RSV27 (1 << 27) +#define FLAG_RSV26 (1 << 26) +#define FLAG_3D_BLACK_DIS (1 << 25) +#define FLAG_3D_BLACK_EN (1 << 24) +#define FLAG_3D_SYNC_DIS (1 << 23) +#define FLAG_3D_SYNC_EN (1 << 22) +#define FLAG_VLOCK_DIS (1 << 21) +#define FLAG_VLOCK_EN (1 << 20) +#define FLAG_VE_DNLP_EN (1 << 19) +#define FLAG_VE_DNLP_DIS (1 << 18) +#define FLAG_VADJ1_CON (1 << 17) +#define FLAG_VADJ1_BRI (1 << 16) +#define FLAG_GAMMA_TABLE_EN (1 << 15) +#define FLAG_GAMMA_TABLE_DIS (1 << 14) +#define FLAG_GAMMA_TABLE_R (1 << 13) +#define FLAG_GAMMA_TABLE_G (1 << 12) +#define FLAG_GAMMA_TABLE_B (1 << 11) +#define FLAG_RGB_OGO (1 << 10) +#define FLAG_RSV9 (1 << 9) +#define FLAG_MATRIX_UPDATE (1 << 8) +#define FLAG_BRI_CON (1 << 7) +#define FLAG_LVDS_FREQ_SW (1 << 6) +#define FLAG_REG_MAP5 (1 << 5) +#define FLAG_REG_MAP4 (1 << 4) +#define FLAG_REG_MAP3 (1 << 3) +#define FLAG_REG_MAP2 (1 << 2) +#define FLAG_REG_MAP1 (1 << 1) +#define FLAG_REG_MAP0 (1 << 0) + +#define VPP_VADJ2_BLMINUS_EN (1 << 3) +#define VPP_VADJ2_EN (1 << 2) +#define VPP_VADJ1_BLMINUS_EN (1 << 1) +#define VPP_VADJ1_EN (1 << 0) + +#define VPP_DEMO_DNLP_DIS (1 << 3) +#define VPP_DEMO_DNLP_EN (1 << 2) +#define VPP_DEMO_CM_DIS (1 << 1) +#define VPP_DEMO_CM_EN (1 << 0) + +/*white balance latch*/ +#define MTX_BYPASS_RGB_OGO (1 << 0) +#define MTX_RGB2YUVL_RGB_OGO (1 << 1) + +#define _VE_CM 'C' + +#define AMVECM_IOC_VE_DNLP _IOW(_VE_CM, 0x21, struct ve_dnlp_s) +#define AMVECM_IOC_G_HIST_AVG _IOW(_VE_CM, 0x22, struct ve_hist_s) +#define AMVECM_IOC_VE_DNLP_EN _IO(_VE_CM, 0x23) +#define AMVECM_IOC_VE_DNLP_DIS _IO(_VE_CM, 0x24) +#define AMVECM_IOC_VE_NEW_DNLP _IOW(_VE_CM, 0x25, struct ve_dnlp_table_s) +#define AMVECM_IOC_G_HIST_BIN _IOW(_VE_CM, 0x26, struct vpp_hist_param_s) +#define AMVECM_IOC_G_HDR_METADATA _IOW(_VE_CM, 0x27, struct hdr_metadata_info_s) + + +/* VPP.CM IOCTL command list */ +#define AMVECM_IOC_LOAD_REG _IOW(_VE_CM, 0x30, struct am_regs_s) + + +/* VPP.GAMMA IOCTL command list */ +#define AMVECM_IOC_GAMMA_TABLE_EN _IO(_VE_CM, 0x40) +#define AMVECM_IOC_GAMMA_TABLE_DIS _IO(_VE_CM, 0x41) +#define AMVECM_IOC_GAMMA_TABLE_R _IOW(_VE_CM, 0x42, struct tcon_gamma_table_s) +#define AMVECM_IOC_GAMMA_TABLE_G _IOW(_VE_CM, 0x43, struct tcon_gamma_table_s) +#define AMVECM_IOC_GAMMA_TABLE_B _IOW(_VE_CM, 0x44, struct tcon_gamma_table_s) +#define AMVECM_IOC_S_RGB_OGO _IOW(_VE_CM, 0x45, struct tcon_rgb_ogo_s) +#define AMVECM_IOC_G_RGB_OGO _IOR(_VE_CM, 0x46, struct tcon_rgb_ogo_s) + +/*VPP.VLOCK IOCTL command list*/ +#define AMVECM_IOC_VLOCK_EN _IO(_VE_CM, 0x47) +#define AMVECM_IOC_VLOCK_DIS _IO(_VE_CM, 0x48) + +/*VPP.3D-SYNC IOCTL command list*/ +#define AMVECM_IOC_3D_SYNC_EN _IO(_VE_CM, 0x49) +#define AMVECM_IOC_3D_SYNC_DIS _IO(_VE_CM, 0x50) + +/* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8) */ +/* #define WRITE_VPP_REG(x,val)*/ +/* WRITE_VCBUS_REG(x,val) */ +/* #define WRITE_VPP_REG_BITS(x,val,start,length)*/ +/* WRITE_VCBUS_REG_BITS(x,val,start,length) */ +/* #define READ_VPP_REG(x)*/ +/* READ_VCBUS_REG(x) */ +/* #define READ_VPP_REG_BITS(x,start,length)*/ +/* READ_VCBUS_REG_BITS(x,start,length) */ +/* #else */ +/* #define WRITE_VPP_REG(x,val)*/ +/* WRITE_CBUS_REG(x,val) */ +/* #define WRITE_VPP_REG_BITS(x,val,start,length)*/ +/* WRITE_CBUS_REG_BITS(x,val,start,length) */ +/* #define READ_VPP_REG(x)*/ +/* READ_CBUS_REG(x) */ +/* #define READ_VPP_REG_BITS(x,start,length)*/ +/* READ_CBUS_REG_BITS(x,start,length) */ +/* #endif */ + + +static inline void WRITE_VPP_REG(uint32_t reg, + const uint32_t value) +{ + aml_write_vcbus(reg, value); +} + +static inline uint32_t READ_VPP_REG(uint32_t reg) +{ + return aml_read_vcbus(reg); +} + +static inline void WRITE_VPP_REG_BITS(uint32_t reg, + const uint32_t value, + const uint32_t start, + const uint32_t len) +{ + WRITE_VPP_REG(reg, ((READ_VPP_REG(reg) & + ~(((1L << (len)) - 1) << (start))) | + (((value) & ((1L << (len)) - 1)) << (start)))); +} + +static inline uint32_t READ_VPP_REG_BITS(uint32_t reg, + const uint32_t start, + const uint32_t len) +{ + uint32_t val; + + val = ((READ_VPP_REG(reg) >> (start)) & ((1L << (len)) - 1)); + + return val; +} + +extern signed int vd1_brightness, vd1_contrast; +extern bool gamma_en; + +extern void amvecm_on_vs(struct vframe_s *vf); +extern void refresh_on_vs(struct vframe_s *vf); +extern void pc_mode_process(void); + +/* master_display_info for display device */ +struct hdr_metadata_info_s { + u32 primaries[3][2]; /* normalized 50000 in G,B,R order */ + u32 white_point[2]; /* normalized 50000 */ + u32 luminance[2]; /* max/min lumin, normalized 10000 */ +}; + +extern void vpp_vd_adj1_saturation_hue(signed int sat_val, + signed int hue_val, struct vframe_s *vf); + +extern int metadata_read_u32(uint32_t *value); +extern int metadata_wait(struct vframe_s *vf); +extern int metadata_sync(uint32_t frame_id, uint64_t pts); + +extern void enable_dolby_vision(int enable); +extern bool is_dolby_vision_enable(void); +extern bool is_dolby_vision_on(void); +extern bool for_dolby_vision_certification(void); +extern void set_dolby_vision_mode(int mode); +extern int get_dolby_vision_mode(void); +extern void dolby_vision_set_toggle_flag(int flag); +extern int dolby_vision_wait_metadata(struct vframe_s *vf); +extern int dolby_vision_pop_metadata(void); +extern int dolby_vision_update_metadata(struct vframe_s *vf); +extern int dolby_vision_process(struct vframe_s *vf); +extern void dolby_vision_init_receiver(void); +extern void dolby_vision_vf_put(struct vframe_s *vf); +extern struct vframe_s *dolby_vision_vf_peek_el(struct vframe_s *vf); +extern void dolby_vision_dump_setting(int debug_flag); +extern void dolby_vision_dump_struct(void); +extern void enable_osd_path(int on); +#endif /* AMVECM_H */ + diff --git a/include/linux/amlogic/media/amvecm/cm.h b/include/linux/amlogic/media/amvecm/cm.h index d1ba768..8b49605 100644 --- a/include/linux/amlogic/media/amvecm/cm.h +++ b/include/linux/amlogic/media/amvecm/cm.h @@ -1,27 +1,20 @@ /* + * Color Management * include/linux/amlogic/media/amvecm/cm.h * - * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * Copyright (C) 2010 Amlogic Inc. * * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. */ + #ifndef _TVOUT_CM_H #define _TVOUT_CM_H /* ******************************************************************* */ - /* *** enum definitions ********************************************* */ - /* ******************************************************************* */ enum cm_region_idx_e { @@ -65,57 +58,55 @@ enum cm_csc_e { }; /* ******************************************************************* */ - /* *** struct definitions ********************************************* */ - /* ******************************************************************* */ struct cm_region_s { enum cm_region_idx_e region_idx; /* sym */ - unsigned char sym_en; + unsigned char sym_en; /* sat - top */ - unsigned char sat_en; - unsigned char sat_central_en; + unsigned char sat_en; + unsigned char sat_central_en; enum cm_sat_shape_e sat_shape; - unsigned char sat_gain; - unsigned char sat_inc; + unsigned char sat_gain; + unsigned char sat_inc; /* sat - lum */ - unsigned char sat_lum_h_slope; - unsigned char sat_lum_l_slope; - unsigned char sat_lum_h; - unsigned char sat_lum_l; + unsigned char sat_lum_h_slope; + unsigned char sat_lum_l_slope; + unsigned char sat_lum_h; + unsigned char sat_lum_l; /* sat - sat */ - unsigned char sat_sat_h_slope; - unsigned char sat_sat_l_slope; - unsigned char sat_sat_h; - unsigned char sat_sat_l; + unsigned char sat_sat_h_slope; + unsigned char sat_sat_l_slope; + unsigned char sat_sat_h; + unsigned char sat_sat_l; /* hue - top */ - unsigned char hue_en; - unsigned char hue_central_en; + unsigned char hue_en; + unsigned char hue_central_en; enum cm_hue_shape_e hue_shape; - unsigned char hue_gain; - unsigned char hue_clockwise; - unsigned char hue_shf_ran; - unsigned short hue_shf_sta; + unsigned char hue_gain; + unsigned char hue_clockwise; + unsigned char hue_shf_ran; + unsigned short hue_shf_sta; /* hue - lum */ - unsigned char hue_lum_h_slope; - unsigned char hue_lum_l_slope; - unsigned char hue_lum_h; - unsigned char hue_lum_l; + unsigned char hue_lum_h_slope; + unsigned char hue_lum_l_slope; + unsigned char hue_lum_h; + unsigned char hue_lum_l; /* hue - sat */ - unsigned char hue_sat_h_slope; - unsigned char hue_sat_l_slope; - unsigned char hue_sat_h; - unsigned char hue_sat_l; + unsigned char hue_sat_h_slope; + unsigned char hue_sat_l_slope; + unsigned char hue_sat_h; + unsigned char hue_sat_l; }; struct cm_top_s { - unsigned char chroma_en; - enum cm_sat_sel_e sat_sel; - unsigned char uv_adj_en; - unsigned char rgb_to_hue_en; - enum cm_csc_e csc_sel; + unsigned char chroma_en; + enum cm_sat_sel_e sat_sel; + unsigned char uv_adj_en; + unsigned char rgb_to_hue_en; + enum cm_csc_e csc_sel; }; struct cm_cbar_s { @@ -126,11 +117,11 @@ struct cm_cbar_s { unsigned char y; }; struct cm_demo_s { - unsigned char en; - enum cm_demo_pos_e pos; - unsigned char hlight_adj; - unsigned short wid; - struct cm_cbar_s cbar; + unsigned char en; + enum cm_demo_pos_e pos; + unsigned char hlight_adj; + unsigned short wid; + struct cm_cbar_s cbar; }; struct cm_regmap_s { @@ -154,15 +145,15 @@ enum reg_bus_type_e { /* Register table structure */ struct am_reg_s { - unsigned int type; /* 32-bits; 0: CBUS; 1: APB BUS... */ - unsigned int addr; /* 32-bits; Register address */ - unsigned int mask; /* 32-bits; Valid bits */ - unsigned int val; /* 32-bits; Register Value */ + unsigned int type; /* 32-bits; 0: CBUS; 1: APB BUS... */ + unsigned int addr; /* 32-bits; Register address */ + unsigned int mask; /* 32-bits; Valid bits */ + unsigned int val; /* 32-bits; Register Value */ }; #define am_reg_size 900 struct am_regs_s { - unsigned int length; /* Length of total am_reg */ + unsigned int length; /* Length of total am_reg */ struct am_reg_s am_reg[am_reg_size]; }; -#endif /* _TVOUT_CM_H */ +#endif /* _TVOUT_CM_H */ diff --git a/include/linux/amlogic/media/amvecm/ve.h b/include/linux/amlogic/media/amvecm/ve.h new file mode 100644 index 0000000..5bfd32d --- /dev/null +++ b/include/linux/amlogic/media/amvecm/ve.h @@ -0,0 +1,336 @@ +/* + * include/linux/amlogic/media/amvecm/ve.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __VE_H +#define __VE_H + +/* ******************************************************************* */ +/* *** enum definitions ********************************************* */ +/* ******************************************************************* */ + +enum ve_demo_pos_e { + VE_DEMO_POS_TOP = 0, + VE_DEMO_POS_BOTTOM, + VE_DEMO_POS_LEFT, + VE_DEMO_POS_RIGHT, +}; + +enum ve_dnlp_rt_e { + VE_DNLP_RT_0S = 0, + VE_DNLP_RT_1S = 6, + VE_DNLP_RT_2S, + VE_DNLP_RT_4S, + VE_DNLP_RT_8S, + VE_DNLP_RT_16S, + VE_DNLP_RT_32S, + VE_DNLP_RT_64S, + VE_DNLP_RT_FREEZE, +}; + +/* ******************************************************************* */ +/* *** struct definitions ********************************************* */ +/* ******************************************************************* */ + +struct ve_bext_s { + unsigned char en; + unsigned char start; + unsigned char slope1; + unsigned char midpt; + unsigned char slope2; +}; +#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) +struct ve_dnlp_s { + unsigned int en; + unsigned int rt; /* 0 ~ 255, */ + unsigned int rl; /* 0 ~ 15, 1.0000x ~ 1.9375x, step 0.0625x */ + unsigned int black; /* 0 ~ 16, weak ~ strong */ + unsigned int white; /* 0 ~ 16, weak ~ strong */ +}; +struct ve_hist_s { + ulong sum; + int width; + int height; + int ave; +}; +struct ve_dnlp_table_s { + unsigned int en; + unsigned int method; + unsigned int cliprate; + unsigned int lowrange; + unsigned int hghrange; + unsigned int lowalpha; + unsigned int midalpha; + unsigned int hghalpha; + unsigned int adj_level; + unsigned int new_adj_level; + unsigned int new_mvreflsh; + unsigned int new_gmma_rate; + unsigned int new_lowalpha; + unsigned int new_hghalpha; + unsigned int new_sbgnbnd; + unsigned int new_sendbnd; + unsigned int new_clashBgn; + unsigned int new_clashEnd; + unsigned int new_cliprate; + unsigned int new_mtdbld_rate; + unsigned int new_dnlp_pst_gmarat; + unsigned int dnlp_sel; + unsigned int dnlp_blk_cctr;/*blk signal add brightness*/ + unsigned int dnlp_brgt_ctrl; + unsigned int dnlp_brgt_range; + unsigned int dnlp_brght_add; + unsigned int dnlp_brght_max; + unsigned int dnlp_almst_wht; + unsigned int dnlp_hghbin;/*1*/ + unsigned int dnlp_hghnum; + unsigned int dnlp_lowbin; + unsigned int dnlp_lownum; + unsigned int dnlp_bkgend; + unsigned int dnlp_bkgert; + unsigned int dnlp_blkext; + unsigned int dnlp_whtext; + unsigned int dnlp_bextmx; + unsigned int dnlp_wextmx; + unsigned int dnlp_smhist_ck; + unsigned int dnlp_glb_crate;/*12*/ + unsigned int dnlp_pstgma_brghtrate; + unsigned int dnlp_pstgma_brghtrat1; + unsigned int dnlp_wext_autorat; + unsigned int dnlp_cliprate_min; + unsigned int dnlp_adpcrat_lbnd; + unsigned int dnlp_adpcrat_hbnd; + unsigned int dnlp_adpmtd_lbnd; + unsigned int dnlp_adpmtd_hbnd; + unsigned int dnlp_set_bext; + unsigned int dnlp_set_wext; + unsigned int dnlp_satur_rat; + unsigned int dnlp_satur_max; + unsigned int blk_prct_rng; + unsigned int blk_prct_max; + unsigned int dnlp_lowrange; + unsigned int dnlp_hghrange; + unsigned int dnlp_auto_rng; + unsigned int dnlp_bin0_absmax; + unsigned int dnlp_bin0_sbtmax; + unsigned int dnlp_adpalpha_lrate; + unsigned int dnlp_adpalpha_hrate; + unsigned int dnlp_lrate00;/*0-64bin curve slope*/ + unsigned int dnlp_lrate02; + unsigned int dnlp_lrate04; + unsigned int dnlp_lrate06; + unsigned int dnlp_lrate08; + unsigned int dnlp_lrate10; + unsigned int dnlp_lrate12; + unsigned int dnlp_lrate14; + unsigned int dnlp_lrate16; + unsigned int dnlp_lrate18; + unsigned int dnlp_lrate20; + unsigned int dnlp_lrate22; + unsigned int dnlp_lrate24; + unsigned int dnlp_lrate26; + unsigned int dnlp_lrate28; + unsigned int dnlp_lrate30; + unsigned int dnlp_lrate32; + unsigned int dnlp_lrate34; + unsigned int dnlp_lrate36; + unsigned int dnlp_lrate38; + unsigned int dnlp_lrate40; + unsigned int dnlp_lrate42; + unsigned int dnlp_lrate44; + unsigned int dnlp_lrate46; + unsigned int dnlp_lrate48; + unsigned int dnlp_lrate50; + unsigned int dnlp_lrate52; + unsigned int dnlp_lrate54; + unsigned int dnlp_lrate56; + unsigned int dnlp_lrate58; + unsigned int dnlp_lrate60; + unsigned int dnlp_lrate62; +}; +struct vpp_hist_param_s { + unsigned int vpp_hist_pow; + unsigned int vpp_luma_sum; + unsigned int vpp_pixel_sum; + unsigned short vpp_histgram[64]; +}; +#else +struct ve_dnlp_s { + unsigned char en; + enum ve_dnlp_rt_e rt; + unsigned char gamma[64]; +}; +#endif +struct ve_hsvs_s { + unsigned char en; + unsigned char peak_gain_h1; + unsigned char peak_gain_h2; + unsigned char peak_gain_h3; + unsigned char peak_gain_h4; + unsigned char peak_gain_h5; + unsigned char peak_gain_v1; + unsigned char peak_gain_v2; + unsigned char peak_gain_v3; + unsigned char peak_gain_v4; + unsigned char peak_gain_v5; + unsigned char peak_gain_v6; + unsigned char hpeak_slope1; + unsigned char hpeak_slope2; + unsigned char hpeak_thr1; + unsigned char hpeak_thr2; + unsigned char hpeak_nlp_cor_thr; + unsigned char hpeak_nlp_gain_pos; + unsigned char hpeak_nlp_gain_neg; + unsigned char vpeak_slope1; + unsigned char vpeak_slope2; + unsigned char vpeak_thr1; + unsigned char vpeak_thr2; + unsigned char vpeak_nlp_cor_thr; + unsigned char vpeak_nlp_gain_pos; + unsigned char vpeak_nlp_gain_neg; + unsigned char speak_slope1; + unsigned char speak_slope2; + unsigned char speak_thr1; + unsigned char speak_thr2; + unsigned char speak_nlp_cor_thr; + unsigned char speak_nlp_gain_pos; + unsigned char speak_nlp_gain_neg; + unsigned char peak_cor_gain; + unsigned char peak_cor_thr_l; + unsigned char peak_cor_thr_h; + unsigned char vlti_step; + unsigned char vlti_step2; + unsigned char vlti_thr; + unsigned char vlti_gain_pos; + unsigned char vlti_gain_neg; + unsigned char vlti_blend_factor; + unsigned char hlti_step; + unsigned char hlti_thr; + unsigned char hlti_gain_pos; + unsigned char hlti_gain_neg; + unsigned char hlti_blend_factor; + unsigned char vlimit_coef_h; + unsigned char vlimit_coef_l; + unsigned char hlimit_coef_h; + unsigned char hlimit_coef_l; + unsigned char cti_444_422_en; + unsigned char cti_422_444_en; + unsigned char cti_blend_factor; + unsigned char vcti_buf_en; + unsigned char vcti_buf_mode_c5l; + unsigned char vcti_filter; + unsigned char hcti_step; + unsigned char hcti_step2; + unsigned char hcti_thr; + unsigned char hcti_gain; + unsigned char hcti_mode_median; +}; + +struct ve_ccor_s { + unsigned char en; + unsigned char slope; + unsigned char thr; +}; + +struct ve_benh_s { + unsigned char en; + unsigned char cb_inc; + unsigned char cr_inc; + unsigned char gain_cr; + unsigned char gain_cb4cr; + unsigned char luma_h; + unsigned char err_crp; + unsigned char err_crn; + unsigned char err_cbp; + unsigned char err_cbn; +}; + +struct ve_cbar_s { + unsigned char en; + unsigned char wid; + unsigned char cr; + unsigned char cb; + unsigned char y; +}; +struct ve_demo_s { + unsigned char bext; + unsigned char dnlp; + unsigned char hsvs; + unsigned char ccor; + unsigned char benh; + enum ve_demo_pos_e pos; + unsigned long wid; + struct ve_cbar_s cbar; +}; + +struct vdo_meas_s { + /* ... */ +}; + +struct ve_regmap_s { + unsigned long reg[43]; +}; + +#define EOTF_LUT_SIZE 33 +#define OSD_OETF_LUT_SIZE 41 + +/********************OSD HDR registers backup********************************/ +struct hdr_osd_lut_s { + uint32_t r_map[33]; + uint32_t g_map[33]; + uint32_t b_map[33]; + uint32_t or_map[41]; + uint32_t og_map[41]; + uint32_t ob_map[41]; +}; + +struct hdr_osd_reg_s { + uint32_t viu_osd1_matrix_ctrl; /* 0x1a90 */ + uint32_t viu_osd1_matrix_coef00_01; /* 0x1a91 */ + uint32_t viu_osd1_matrix_coef02_10; /* 0x1a92 */ + uint32_t viu_osd1_matrix_coef11_12; /* 0x1a93 */ + uint32_t viu_osd1_matrix_coef20_21; /* 0x1a94 */ + uint32_t viu_osd1_matrix_colmod_coef42; /* 0x1a95 */ + uint32_t viu_osd1_matrix_offset0_1; /* 0x1a96 */ + uint32_t viu_osd1_matrix_offset2; /* 0x1a97 */ + uint32_t viu_osd1_matrix_pre_offset0_1; /* 0x1a98 */ + uint32_t viu_osd1_matrix_pre_offset2; /* 0x1a99 */ + uint32_t viu_osd1_matrix_coef22_30; /* 0x1a9d */ + uint32_t viu_osd1_matrix_coef31_32; /* 0x1a9e */ + uint32_t viu_osd1_matrix_coef40_41; /* 0x1a9f */ + uint32_t viu_osd1_eotf_ctl; /* 0x1ad4 */ + uint32_t viu_osd1_eotf_coef00_01; /* 0x1ad5 */ + uint32_t viu_osd1_eotf_coef02_10; /* 0x1ad6 */ + uint32_t viu_osd1_eotf_coef11_12; /* 0x1ad7 */ + uint32_t viu_osd1_eotf_coef20_21; /* 0x1ad8 */ + uint32_t viu_osd1_eotf_coef22_rs; /* 0x1ad9 */ + uint32_t viu_osd1_oetf_ctl; /* 0x1adc */ + struct hdr_osd_lut_s lut_val; +}; + +extern struct hdr_osd_reg_s hdr_osd_reg; +/***********************OSD HDR registers*******************************/ + + +/* ******************************************************************* */ +/* *** MACRO definitions ********** */ +/* ******************************************************************* */ + +/* ******************************************************************* */ +/* *** FUNCTION definitions ********** */ +/* ******************************************************************* */ + +#endif /* _VE_H */ -- 2.7.4