From 22586dcb2a25ee8f1b92833bd07f6160be14f706 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Mon, 31 Oct 2016 15:45:09 +0000
Subject: [PATCH] [Hexagon] Don't expand mux instructions with both sources
 identical

llvm-svn: 285588
---
 llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp  | 22 +++++++++++++--
 .../Hexagon/expand-condsets-same-inputs.mir        | 32 ++++++++++++++++++++++
 2 files changed, 52 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir

diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index abb7810..baa3b8b 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -614,13 +614,31 @@ bool HexagonExpandCondsets::split(MachineInstr &MI,
   bool ReadUndef = MD.isUndef();
   MachineBasicBlock::iterator At = MI;
 
+  // If this is a mux of the same register, just replace it with COPY.
+  // Ideally, this would happen earlier, so that register coalescing would
+  // see it.
+  MachineOperand &ST = MI.getOperand(2);
+  MachineOperand &SF = MI.getOperand(3);
+  if (ST.isReg() && SF.isReg()) {
+    RegisterRef RT(ST);
+    if (RT == RegisterRef(SF)) {
+      MI.setDesc(HII->get(TargetOpcode::COPY));
+      unsigned S = getRegState(ST);
+      while (MI.getNumOperands() > 1)
+        MI.RemoveOperand(MI.getNumOperands()-1);
+      MachineFunction &MF = *MI.getParent()->getParent();
+      MachineInstrBuilder(MF, MI).addReg(RT.Reg, S, RT.Sub);
+      return true;
+    }
+  }
+
   // First, create the two invididual conditional transfers, and add each
   // of them to the live intervals information. Do that first and then remove
   // the old instruction from live intervals.
   MachineInstr *TfrT =
-      genCondTfrFor(MI.getOperand(2), At, DR, DSR, MP, true, ReadUndef, false);
+      genCondTfrFor(ST, At, DR, DSR, MP, true, ReadUndef, false);
   MachineInstr *TfrF =
-      genCondTfrFor(MI.getOperand(3), At, DR, DSR, MP, false, ReadUndef, true);
+      genCondTfrFor(SF, At, DR, DSR, MP, false, ReadUndef, true);
   LIS->InsertMachineInstrInMaps(*TfrT);
   LIS->InsertMachineInstrInMaps(*TfrF);
 
diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir
new file mode 100644
index 0000000..83938d1
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir
@@ -0,0 +1,32 @@
+# RUN: llc -march=hexagon -run-pass expand-condsets -expand-condsets-coa-limit=0 -o - %s -verify-machineinstrs | FileCheck %s
+
+# CHECK-LABEL: name: fred
+
+--- |
+  define void @fred() { ret void }
+
+...
+---
+
+name: fred
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: predregs }
+  - { id: 1, class: intregs }
+  - { id: 2, class: intregs }
+  - { id: 3, class: intregs }
+
+body: |
+  bb.0:
+    liveins: %r0, %r1, %r2, %p0
+        %0 = COPY %p0
+        %0 = COPY %p0   ; Cheat: convince MIR parser that this is not SSA.
+        %1 = COPY %r1
+        ; Make sure we do not expand/predicate a mux with identical inputs.
+        ; CHECK-NOT: A2_paddit
+        %2 = A2_addi %1, 1
+        %3 = C2_mux %0, killed %2, %2
+        %r0 = COPY %3
+
+...
+
-- 
2.7.4