From 223ef402c9a38c7f3e6721445eef865aeb79e8e9 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Tue, 3 Apr 2018 18:34:56 +0000 Subject: [PATCH] [x86] add tests for convert-FP-to-integer with constants; NFC We don't constant fold any of these, but we could...but if we do, we must produce the right answer. Unlike the IR fptosi instruction or its DAG node counterpart ISD::FP_TO_SINT, these are not undef for an out-of-range input. llvm-svn: 329100 --- llvm/test/CodeGen/X86/fptosi-constant.ll | 133 +++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 llvm/test/CodeGen/X86/fptosi-constant.ll diff --git a/llvm/test/CodeGen/X86/fptosi-constant.ll b/llvm/test/CodeGen/X86/fptosi-constant.ll new file mode 100644 index 0000000..7baeff3 --- /dev/null +++ b/llvm/test/CodeGen/X86/fptosi-constant.ll @@ -0,0 +1,133 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s + +; Check constant FP to signed integer conversions that overflow the integer type. + +define i32 @constant_v2f64_to_i32() { +; CHECK-LABEL: constant_v2f64_to_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: cvtsd2si {{.*}}(%rip), %eax +; CHECK-NEXT: retq + %r = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> ) + ret i32 %r +} + +define i32 @constant_v2f64_to_i32_round_to_zero() { +; CHECK-LABEL: constant_v2f64_to_i32_round_to_zero: +; CHECK: # %bb.0: +; CHECK-NEXT: cvttsd2si {{.*}}(%rip), %eax +; CHECK-NEXT: retq + %r = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> ) + ret i32 %r +} + +define i64 @constant_v2f64_to_i64() { +; CHECK-LABEL: constant_v2f64_to_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: cvtsd2si {{.*}}(%rip), %rax +; CHECK-NEXT: retq + %r = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> ) + ret i64 %r +} + +define i64 @constant_v2f64_to_i64_round_to_zero() { +; CHECK-LABEL: constant_v2f64_to_i64_round_to_zero: +; CHECK: # %bb.0: +; CHECK-NEXT: cvttsd2si {{.*}}(%rip), %rax +; CHECK-NEXT: retq + %r = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> ) + ret i64 %r +} + +define <4 x i32> @constant_v2f64_to_v4i32() { +; CHECK-LABEL: constant_v2f64_to_v4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: cvtpd2dq {{.*}}(%rip), %xmm0 +; CHECK-NEXT: retq + %r = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> ) + ret <4 x i32> %r +} + +define <4 x i32> @constant_v2f64_to_v4i32_round_to_zero() { +; CHECK-LABEL: constant_v2f64_to_v4i32_round_to_zero: +; CHECK: # %bb.0: +; CHECK-NEXT: cvttpd2dq {{.*}}(%rip), %xmm0 +; CHECK-NEXT: retq + %r = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> ) + ret <4 x i32> %r +} + +define i32 @constant_v4f32_to_i32() { +; CHECK-LABEL: constant_v4f32_to_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: cvtss2si {{.*}}(%rip), %eax +; CHECK-NEXT: retq + %r = call i32 @llvm.x86.sse.cvtss2si(<4 x float> ) + ret i32 %r +} + +define i32 @constant_v4f32_to_i32_round_to_zero() { +; CHECK-LABEL: constant_v4f32_to_i32_round_to_zero: +; CHECK: # %bb.0: +; CHECK-NEXT: cvttss2si {{.*}}(%rip), %eax +; CHECK-NEXT: retq + %r = call i32 @llvm.x86.sse.cvttss2si(<4 x float> ) + ret i32 %r +} + +; 9223372036854775808.0 = 0x8000000000000000 + +define i64 @constant_v4f32_to_i64() { +; CHECK-LABEL: constant_v4f32_to_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: cvtss2si {{.*}}(%rip), %rax +; CHECK-NEXT: retq + %r = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> ) + ret i64 %r +} + +define i64 @constant_v4f32_to_i64_round_to_zero() { +; CHECK-LABEL: constant_v4f32_to_i64_round_to_zero: +; CHECK: # %bb.0: +; CHECK-NEXT: cvttss2si {{.*}}(%rip), %rax +; CHECK-NEXT: retq + %r = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> ) + ret i64 %r +} + +define <4 x i32> @constant_v4f32_to_v4i32() { +; CHECK-LABEL: constant_v4f32_to_v4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: cvtps2dq {{.*}}(%rip), %xmm0 +; CHECK-NEXT: retq + %r = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> ) + ret <4 x i32> %r +} + +define <4 x i32> @constant_v4f32_to_v4i32_round_to_zero() { +; CHECK-LABEL: constant_v4f32_to_v4i32_round_to_zero: +; CHECK: # %bb.0: +; CHECK-NEXT: cvttps2dq {{.*}}(%rip), %xmm0 +; CHECK-NEXT: retq + %r = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> ) + ret <4 x i32> %r +} + +declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) +declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) + +declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) +declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) + +declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>) +declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>) + +declare i32 @llvm.x86.sse.cvtss2si(<4 x float>) +declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) + +declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) +declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) + +declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>) +declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) + -- 2.7.4