From 22176a22427b32fb82e3b18a79e7b5f55f49026a Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Wed, 16 May 2018 15:45:17 +0000 Subject: [PATCH] [AArch64][SVE] Improve diagnostics for vectors with incorrect element-size. For regular SVE vector operands, this patch introduces a more sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b). For example: add z0.s, z1.s, z2.b -> invalid element width ^_____^ mismatch For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes a slightly different approach and instead returns a 'invalid operand' if the element size is not as expected. This is because the diagnostics are more specificied to suggest using the right shift/extend suffix. This is a trade-off not to introduce more operand classes and still provide useful diagnostics for LD1 and PRF instructions. For example: ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand ^________________^ mismatch For gather prefetches, both 'z0.s' and 'z0.d' would be allowed: prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' Without this change, the diagnostic would unnecessarily suggest a different element size: prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46688 llvm-svn: 332483 --- llvm/lib/Target/AArch64/AArch64RegisterInfo.td | 7 ++-- .../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 46 ++++++++++++++++++---- llvm/test/MC/AArch64/SVE/add-diagnostics.s | 2 +- llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s | 4 +- llvm/test/MC/AArch64/SVE/ld1rd-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ld1rh-diagnostics.s | 2 +- llvm/test/MC/AArch64/SVE/ld1rqb-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ld1rqd-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ld1rqh-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ld1rqw-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ld1rsb-diagnostics.s | 2 +- llvm/test/MC/AArch64/SVE/ld1rsh-diagnostics.s | 4 +- llvm/test/MC/AArch64/SVE/ld1rsw-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ld1rw-diagnostics.s | 4 +- llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s | 10 ++--- llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s | 8 ++-- llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s | 17 +++----- llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s | 4 +- llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s | 12 +++--- llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s | 8 ++-- llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s | 15 +++---- llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s | 8 ++-- llvm/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s | 4 +- llvm/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s | 4 +- llvm/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s | 4 +- llvm/test/MC/AArch64/SVE/ldnt1b-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ldnt1d-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ldnt1h-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/ldnt1w-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/prfb-diagnostics.s | 12 +++--- llvm/test/MC/AArch64/SVE/prfd-diagnostics.s | 2 +- llvm/test/MC/AArch64/SVE/prfh-diagnostics.s | 10 ++--- llvm/test/MC/AArch64/SVE/prfw-diagnostics.s | 10 ++--- llvm/test/MC/AArch64/SVE/st1b-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/st1d-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/st1h-diagnostics.s | 4 +- llvm/test/MC/AArch64/SVE/st1w-diagnostics.s | 4 +- llvm/test/MC/AArch64/SVE/stnt1b-diagnostics.s | 8 ++-- llvm/test/MC/AArch64/SVE/stnt1d-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/stnt1h-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/stnt1w-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/sub-diagnostics.s | 2 +- llvm/test/MC/AArch64/SVE/zip1-diagnostics.s | 6 +-- llvm/test/MC/AArch64/SVE/zip2-diagnostics.s | 6 +-- 49 files changed, 185 insertions(+), 164 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td index b150d55..7acdb69 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td @@ -792,7 +792,7 @@ def PPR_3b : PPRClass<7>; // Restricted 3 bit SVE predicate register class. class PPRAsmOperand : AsmOperandClass { let Name = "SVE" # name # "Reg"; - let PredicateMethod = "isSVEVectorRegOfWidth<" + let PredicateMethod = "isSVEPredicateVectorRegOfWidth<" # Width # ", " # "AArch64::" # RegClass # "RegClassID>"; let DiagnosticType = "InvalidSVE" # name # "Reg"; let RenderMethod = "addRegOperands"; @@ -837,9 +837,10 @@ def ZPR : RegisterClass<"AArch64", class ZPRAsmOperand : AsmOperandClass { let Name = "SVE" # name # "Reg"; - let PredicateMethod = "isSVEVectorRegOfWidth<" + let PredicateMethod = "isSVEDataVectorRegOfWidth<" # Width # ", AArch64::ZPRRegClassID>"; let RenderMethod = "addRegOperands"; + let DiagnosticType = "InvalidZPR" # Width; let ParserMethod = "tryParseSVEDataVector"; } @@ -958,7 +959,7 @@ class ZPRExtendAsmOperand - bool isSVEVectorRegOfWidth() const { - return isSVEVectorReg() && - (ElementWidth == 0 || Reg.ElementWidth == ElementWidth); + DiagnosticPredicate isSVEPredicateVectorRegOfWidth() const { + if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateVector) + return DiagnosticPredicateTy::NoMatch; + + if (isSVEVectorReg() && + (ElementWidth == 0 || Reg.ElementWidth == ElementWidth)) + return DiagnosticPredicateTy::Match; + + return DiagnosticPredicateTy::NearMatch; + } + + template + DiagnosticPredicate isSVEDataVectorRegOfWidth() const { + if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector) + return DiagnosticPredicateTy::NoMatch; + + if (isSVEVectorReg() && + (ElementWidth == 0 || Reg.ElementWidth == ElementWidth)) + return DiagnosticPredicateTy::Match; + + return DiagnosticPredicateTy::NearMatch; } template - DiagnosticPredicate isSVEVectorRegWithShiftExtend() const { - if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector) + DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const { + auto VectorMatch = isSVEDataVectorRegOfWidth(); + if (!VectorMatch.isMatch()) return DiagnosticPredicateTy::NoMatch; - if (!isSVEVectorRegOfWidth()) - return DiagnosticPredicateTy::NearMatch; - // Give a more specific diagnostic when the user has explicitly typed in // a shift-amount that does not match what is expected, but for which // there is also an unscaled addressing mode (e.g. sxtw/uxtw). @@ -3817,6 +3833,14 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #2'"); case Match_InvalidZPR64LSL64: return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #3'"); + case Match_InvalidZPR0: + return Error(Loc, "expected register without element width sufix"); + case Match_InvalidZPR8: + case Match_InvalidZPR16: + case Match_InvalidZPR32: + case Match_InvalidZPR64: + case Match_InvalidZPR128: + return Error(Loc, "invalid element width"); case Match_InvalidSVEPattern: return Error(Loc, "invalid predicate pattern"); case Match_InvalidSVEPredicateAnyReg: @@ -4299,6 +4323,12 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidZPR64LSL16: case Match_InvalidZPR64LSL32: case Match_InvalidZPR64LSL64: + case Match_InvalidZPR0: + case Match_InvalidZPR8: + case Match_InvalidZPR16: + case Match_InvalidZPR32: + case Match_InvalidZPR64: + case Match_InvalidZPR128: case Match_InvalidSVEPredicateAnyReg: case Match_InvalidSVEPattern: case Match_InvalidSVEPredicateBReg: diff --git a/llvm/test/MC/AArch64/SVE/add-diagnostics.s b/llvm/test/MC/AArch64/SVE/add-diagnostics.s index 797038e..45bbe1d 100644 --- a/llvm/test/MC/AArch64/SVE/add-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/add-diagnostics.s @@ -14,7 +14,7 @@ add z20.h, z2.h, z31.x // Element size specifiers should match. add z27.h, z11.h, z27.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: add z27.h, z11.h, z27.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s index c62cf1a..4d4da40 100644 --- a/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s @@ -115,17 +115,17 @@ ld1b z0.b, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ld1b z0.d, p0/z, [x0, z0.b] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.b] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s index 40c9d7d..cedb48b 100644 --- a/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s @@ -75,7 +75,7 @@ ld1d z0.d, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ld1d z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -99,12 +99,12 @@ ld1d z0.d, p0/z, [x0, z0.d, lsl] // Invalid vector + immediate addressing modes ld1d z0.s, p0/z, [z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1d z0.s, p0/z, [z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.s, p0/z, [z0.s, #8] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1d z0.s, p0/z, [z0.s, #8] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s index 5e3e69e..7c86941 100644 --- a/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s @@ -105,12 +105,12 @@ ld1h z0.h, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ld1h z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1rd-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1rd-diagnostics.s index 92f37cd..66eaa8b 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rd-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1rd-diagnostics.s @@ -33,17 +33,17 @@ ld1rd z0.d, p1/z, [x0, #3] // Invalid result vector element size ld1rd z0.b, p1/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rd z0.b, p1/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rd z0.h, p1/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rd z0.h, p1/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rd z0.s, p1/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rd z0.s, p1/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1rh-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1rh-diagnostics.s index f3af19a..bdd4b06 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rh-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1rh-diagnostics.s @@ -33,7 +33,7 @@ ld1rh z0.h, p1/z, [x0, #3] // Invalid result vector element size ld1rh z0.b, p1/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rh z0.b, p1/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1rqb-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1rqb-diagnostics.s index 6c4dca0..0a8a766 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rqb-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1rqb-diagnostics.s @@ -42,17 +42,17 @@ ld1rqb z0.b, p0/z, [x0, #16, MUL VL] // Invalid destination register width. ld1rqb z0.h, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rqb z0.h, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rqb z0.s, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rqb z0.s, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rqb z0.d, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rqb z0.d, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1rqd-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1rqd-diagnostics.s index 7bcefe6..1ea8188 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rqd-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1rqd-diagnostics.s @@ -42,17 +42,17 @@ ld1rqd z0.d, p0/z, [x0, #16, MUL VL] // Invalid destination register width. ld1rqd z0.b, p0/z, [x0, x1, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rqd z0.b, p0/z, [x0, x1, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rqd z0.h, p0/z, [x0, x1, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rqd z0.h, p0/z, [x0, x1, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rqd z0.s, p0/z, [x0, x1, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rqd z0.s, p0/z, [x0, x1, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1rqh-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1rqh-diagnostics.s index 8e21014..aecc63e 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rqh-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1rqh-diagnostics.s @@ -42,17 +42,17 @@ ld1rqh z0.h, p0/z, [x0, #16, MUL VL] // Invalid destination register width. ld1rqh z0.b, p0/z, [x0, x1, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rqh z0.b, p0/z, [x0, x1, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rqh z0.s, p0/z, [x0, x1, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rqh z0.s, p0/z, [x0, x1, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rqh z0.d, p0/z, [x0, x1, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rqh z0.d, p0/z, [x0, x1, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1rqw-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1rqw-diagnostics.s index d909629..477af42 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rqw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1rqw-diagnostics.s @@ -42,17 +42,17 @@ ld1rqw z0.s, p0/z, [x0, #16, MUL VL] // Invalid destination register width. ld1rqw z0.b, p0/z, [x0, x1, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rqw z0.b, p0/z, [x0, x1, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rqw z0.h, p0/z, [x0, x1, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rqw z0.h, p0/z, [x0, x1, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rqw z0.d, p0/z, [x0, x1, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rqw z0.d, p0/z, [x0, x1, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1rsb-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1rsb-diagnostics.s index 6de6385..7950eca 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rsb-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1rsb-diagnostics.s @@ -18,7 +18,7 @@ ld1rsb z0.h, p1/z, [x0, #64] // Invalid result vector element size ld1rsb z0.b, p1/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rsb z0.b, p1/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1rsh-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1rsh-diagnostics.s index 6dd3255b..b33c793 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rsh-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1rsh-diagnostics.s @@ -23,12 +23,12 @@ ld1rsh z0.s, p1/z, [x0, #3] // Invalid result vector element size ld1rsh z0.b, p1/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rsh z0.b, p1/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rsh z0.h, p1/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rsh z0.h, p1/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1rsw-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1rsw-diagnostics.s index 6343fc8..4d7cf63 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rsw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1rsw-diagnostics.s @@ -23,17 +23,17 @@ ld1rsw z0.d, p1/z, [x0, #3] // Invalid result vector element size ld1rsw z0.b, p1/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rsw z0.b, p1/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rsw z0.h, p1/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rsw z0.h, p1/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rsw z0.s, p1/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rsw z0.s, p1/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1rw-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1rw-diagnostics.s index a9cb22c..e5e55c9 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1rw-diagnostics.s @@ -33,12 +33,12 @@ ld1rw z0.s, p1/z, [x0, #3] // Invalid result vector element size ld1rw z0.b, p1/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rw z0.b, p1/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1rw z0.h, p1/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1rw z0.h, p1/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s index c136db1..e936f57 100644 --- a/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s @@ -4,12 +4,12 @@ // Invalid operand (.b) ld1sb z23.b, p0/z, [x13, #1, MUL VL] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1sb z23.b, p0/z, [x13, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z29.b, p0/z, [x3, #1, MUL VL] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1sb z29.b, p0/z, [x3, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -113,17 +113,17 @@ ld1sb z0.h, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ld1sb z0.d, p0/z, [x0, z0.b] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.b] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s index b550944..91fc364 100644 --- a/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s @@ -4,12 +4,12 @@ // Invalid operand (.h) ld1sh z23.h, p0/z, [x13, #1, MUL VL] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1sh z23.h, p0/z, [x13, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z29.h, p0/z, [x3, #1, MUL VL] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1sh z29.h, p0/z, [x3, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -104,12 +104,12 @@ ld1sh z0.s, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ld1sh z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s index 1b41694..2ecf3b7 100644 --- a/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s @@ -4,12 +4,12 @@ // Invalid operand (.s) ld1sw z23.s, p0/z, [x13, #1, MUL VL] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1sw z23.s, p0/z, [x13, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z29.s, p0/z, [x3, #1, MUL VL] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1sw z29.s, p0/z, [x3, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -89,17 +89,12 @@ ld1sw z0.d, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ld1sw z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' -// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -ld1sw z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -133,12 +128,12 @@ ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3] // Invalid vector + immediate addressing modes ld1sw z0.s, p0/z, [z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.s, p0/z, [z0.s, #4] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s, #4] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s index 8294e73..d1031ea 100644 --- a/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s @@ -90,12 +90,12 @@ ld1w z0.s, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ld1w z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s index 1870a3e..2ce58d8 100644 --- a/llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s @@ -50,17 +50,17 @@ ldff1b z0.b, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ldff1b z0.d, p0/z, [x0, z0.b] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.b] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1b z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1b z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s index 2bb60e0..e5aec40 100644 --- a/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s @@ -4,17 +4,17 @@ // Invalid operand (.b, .h, .s) ldff1d z4.b, p7/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1d z4.b, p7/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1d z4.h, p7/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1d z4.h, p7/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1d z4.s, p7/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1d z4.s, p7/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -54,7 +54,7 @@ ldff1d z0.d, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ldff1d z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -78,12 +78,12 @@ ldff1d z0.d, p0/z, [x0, z0.d, lsl] // Invalid vector + immediate addressing modes ldff1d z0.s, p0/z, [z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1d z0.s, p0/z, [z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1d z0.s, p0/z, [z0.s, #8] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1d z0.s, p0/z, [z0.s, #8] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s index 7dc377a..e568031 100644 --- a/llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s @@ -4,7 +4,7 @@ // Invalid operand (.b) ldff1h z9.b, p7/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1h z9.b, p7/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -54,12 +54,12 @@ ldff1h z0.h, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ldff1h z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1h z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s index 4127613..b9bd9e4 100644 --- a/llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s @@ -4,7 +4,7 @@ // Invalid operand (.b) ldff1sb z27.b, p7/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1sb z27.b, p7/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -53,17 +53,17 @@ ldff1sb z0.h, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ldff1sb z0.d, p0/z, [x0, z0.b] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1sb z0.d, p0/z, [x0, z0.b] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sb z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1sb z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sb z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1sb z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s index b3e510c..e58d915 100644 --- a/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s @@ -4,7 +4,7 @@ // Invalid operand (.h) ldff1sh z9.h, p7/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1sh z9.h, p7/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -48,12 +48,12 @@ ldff1sh z0.s, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ldff1sh z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1sh z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sh z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1sh z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s index bd196bf..4571ee6 100644 --- a/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s @@ -4,7 +4,7 @@ // Invalid operand (.s) ldff1sw z12.s, p7/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1sw z12.s, p7/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -44,17 +44,12 @@ ldff1sw z0.d, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ldff1sw z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sw z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' -// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.s] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -ldff1sw z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -88,12 +83,12 @@ ldff1sw z0.d, p0/z, [x0, z0.d, sxtw #3] // Invalid vector + immediate addressing modes ldff1sw z0.s, p0/z, [z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1sw z0.s, p0/z, [z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1sw z0.s, p0/z, [z0.s, #4] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1sw z0.s, p0/z, [z0.s, #4] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s index e666cd9..36a7eec 100644 --- a/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s @@ -4,12 +4,12 @@ // Invalid operand (.b, .h) ldff1w z12.b, p7/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1w z12.b, p7/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1w z4.h, p7/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldff1w z4.h, p7/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -54,12 +54,12 @@ ldff1w z0.s, p0/z, [x0, w0, uxtw] // Invalid scalar + vector addressing modes ldff1w z0.d, p0/z, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1w z0.d, p0/z, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldff1w z0.d, p0/z, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldff1w z0.d, p0/z, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s index f74b46f..a4d4255 100644 --- a/llvm/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s @@ -4,12 +4,12 @@ // Invalid operand (.b) ldnf1sb z23.b, p0/z, [x13, #1, MUL VL] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnf1sb z23.b, p0/z, [x13, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnf1sb z29.b, p0/z, [x3, #1, MUL VL] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnf1sb z29.b, p0/z, [x3, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s index d553ed8..7e62d79 100644 --- a/llvm/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s @@ -4,12 +4,12 @@ // Invalid operand (.h) ldnf1sh z23.h, p0/z, [x13, #1, MUL VL] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnf1sh z23.h, p0/z, [x13, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnf1sh z29.h, p0/z, [x3, #1, MUL VL] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnf1sh z29.h, p0/z, [x3, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s index e5e7cf4..0312815 100644 --- a/llvm/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s @@ -4,12 +4,12 @@ // Invalid operand (.s) ldnf1sw z23.s, p0/z, [x13, #1, MUL VL] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnf1sw z23.s, p0/z, [x13, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnf1sw z29.s, p0/z, [x3, #1, MUL VL] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnf1sw z29.s, p0/z, [x3, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldnt1b-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldnt1b-diagnostics.s index 75ae2e2..8fa065b 100644 --- a/llvm/test/MC/AArch64/SVE/ldnt1b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldnt1b-diagnostics.s @@ -18,17 +18,17 @@ ldnt1b z29.b, p0/z, [x3, #8, MUL VL] // Invalid result type. ldnt1b z0.h, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnt1b z0.h, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnt1b z0.s, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnt1b z0.s, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnt1b z0.d, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnt1b z0.d, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldnt1d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldnt1d-diagnostics.s index a53b33d..aff76a9 100644 --- a/llvm/test/MC/AArch64/SVE/ldnt1d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldnt1d-diagnostics.s @@ -18,17 +18,17 @@ ldnt1d z29.d, p0/z, [x3, #8, MUL VL] // Invalid result type. ldnt1d z0.b, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnt1d z0.b, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnt1d z0.h, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnt1d z0.h, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnt1d z0.s, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnt1d z0.s, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldnt1h-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldnt1h-diagnostics.s index fd4ac60..2af29ba 100644 --- a/llvm/test/MC/AArch64/SVE/ldnt1h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldnt1h-diagnostics.s @@ -18,17 +18,17 @@ ldnt1h z29.h, p0/z, [x3, #8, MUL VL] // Invalid result type. ldnt1h z0.b, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnt1h z0.b, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnt1h z0.s, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnt1h z0.s, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnt1h z0.d, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnt1h z0.d, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldnt1w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldnt1w-diagnostics.s index b5f4bfc..67a9644 100644 --- a/llvm/test/MC/AArch64/SVE/ldnt1w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ldnt1w-diagnostics.s @@ -18,17 +18,17 @@ ldnt1w z29.s, p0/z, [x3, #8, MUL VL] // Invalid result type. ldnt1w z0.b, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnt1w z0.b, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnt1w z0.h, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnt1w z0.h, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnt1w z0.d, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ldnt1w z0.d, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/prfb-diagnostics.s b/llvm/test/MC/AArch64/SVE/prfb-diagnostics.s index 3a4ca85..2ffdc6f 100644 --- a/llvm/test/MC/AArch64/SVE/prfb-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/prfb-diagnostics.s @@ -58,32 +58,32 @@ prfb #0, p0, [x0, x0, lsl #2] // Invalid scalar + vector addressing modes prfb #0, p0, [x0, z0.b] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: prfb #0, p0, [x0, z0.b] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfb #0, p0, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: prfb #0, p0, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfb #0, p0, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: prfb #0, p0, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfb #0, p0, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: prfb #0, p0, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfb #0, p0, [x0, z0.s, uxtw #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: prfb #0, p0, [x0, z0.s, uxtw #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfb #0, p0, [x0, z0.s, lsl #0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' // CHECK-NEXT: prfb #0, p0, [x0, z0.s, lsl #0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/prfd-diagnostics.s b/llvm/test/MC/AArch64/SVE/prfd-diagnostics.s index 1e3c681..bca2f5b 100644 --- a/llvm/test/MC/AArch64/SVE/prfd-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/prfd-diagnostics.s @@ -58,7 +58,7 @@ prfd #0, p0, [x0, x0, lsl #1] // Invalid scalar + vector addressing modes prfd #0, p0, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #3' // CHECK-NEXT: prfd #0, p0, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/prfh-diagnostics.s b/llvm/test/MC/AArch64/SVE/prfh-diagnostics.s index dbf12f8..0265c9f 100644 --- a/llvm/test/MC/AArch64/SVE/prfh-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/prfh-diagnostics.s @@ -58,27 +58,27 @@ prfh #0, p0, [x0, x0, lsl #2] // Invalid scalar + vector addressing modes prfh #0, p0, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: prfh #0, p0, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfh #0, p0, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' // CHECK-NEXT: prfh #0, p0, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfh #0, p0, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' // CHECK-NEXT: prfh #0, p0, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfh #0, p0, [x0, z0.s, uxtw #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' // CHECK-NEXT: prfh #0, p0, [x0, z0.s, uxtw #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfh #0, p0, [x0, z0.s, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' // CHECK-NEXT: prfh #0, p0, [x0, z0.s, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/prfw-diagnostics.s b/llvm/test/MC/AArch64/SVE/prfw-diagnostics.s index aa7d834..06bc54d2 100644 --- a/llvm/test/MC/AArch64/SVE/prfw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/prfw-diagnostics.s @@ -58,27 +58,27 @@ prfw #0, p0, [x0, x0, lsl #1] // Invalid scalar + vector addressing modes prfw #0, p0, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: prfw #0, p0, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfw #0, p0, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' // CHECK-NEXT: prfw #0, p0, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfw #0, p0, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' // CHECK-NEXT: prfw #0, p0, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfw #0, p0, [x0, z0.s, uxtw #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' // CHECK-NEXT: prfw #0, p0, [x0, z0.s, uxtw #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: prfw #0, p0, [x0, z0.s, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' // CHECK-NEXT: prfw #0, p0, [x0, z0.s, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st1b-diagnostics.s b/llvm/test/MC/AArch64/SVE/st1b-diagnostics.s index 0c3591e..99bbc55 100644 --- a/llvm/test/MC/AArch64/SVE/st1b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st1b-diagnostics.s @@ -113,17 +113,17 @@ st1b z0.b, p0, [x0, w0, uxtw] // Invalid scalar + vector addressing modes st1b z0.d, p0, [x0, z0.b] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st1b z0.d, p0, [x0, z0.b] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1b z0.d, p0, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st1b z0.d, p0, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1b z0.d, p0, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st1b z0.d, p0, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st1d-diagnostics.s b/llvm/test/MC/AArch64/SVE/st1d-diagnostics.s index 9445bd1..f510633 100644 --- a/llvm/test/MC/AArch64/SVE/st1d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st1d-diagnostics.s @@ -74,7 +74,7 @@ st1d z0.d, p0, [x0, w0, uxtw] // Invalid scalar + vector addressing modes st1d z0.d, p0, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st1d z0.d, p0, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -98,12 +98,12 @@ st1d z0.d, p0, [x0, z0.d, lsl] // Invalid vector + immediate addressing modes st1d z0.s, p0, [z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: st1d z0.s, p0, [z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1d z0.s, p0, [z0.s, #8] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: st1d z0.s, p0, [z0.s, #8] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st1h-diagnostics.s b/llvm/test/MC/AArch64/SVE/st1h-diagnostics.s index 60d7bae..b8b8ecd 100644 --- a/llvm/test/MC/AArch64/SVE/st1h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st1h-diagnostics.s @@ -103,12 +103,12 @@ st1h z0.h, p0, [x0, w0, uxtw] // Invalid scalar + vector addressing modes st1h z0.d, p0, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st1h z0.d, p0, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1h z0.d, p0, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st1h z0.d, p0, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st1w-diagnostics.s b/llvm/test/MC/AArch64/SVE/st1w-diagnostics.s index d9021b2..2222b06 100644 --- a/llvm/test/MC/AArch64/SVE/st1w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st1w-diagnostics.s @@ -91,12 +91,12 @@ st1w z0.s, p0, [x0, w0, uxtw] // Invalid scalar + vector addressing modes st1w z0.d, p0, [x0, z0.h] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st1w z0.d, p0, [x0, z0.h] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1w z0.d, p0, [x0, z0.s] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st1w z0.d, p0, [x0, z0.s] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/stnt1b-diagnostics.s b/llvm/test/MC/AArch64/SVE/stnt1b-diagnostics.s index 3215083..8f5a0b2 100644 --- a/llvm/test/MC/AArch64/SVE/stnt1b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/stnt1b-diagnostics.s @@ -18,17 +18,17 @@ stnt1b z29.b, p0, [x3, #8, MUL VL] // Invalid source type. stnt1b z0.h, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1b z0.h, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1b z0.s, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1b z0.s, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1b z0.d, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1b z0.d, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -42,7 +42,7 @@ stnt1b z27.b, p8, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1b z0.h, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1b z0.h, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/stnt1d-diagnostics.s b/llvm/test/MC/AArch64/SVE/stnt1d-diagnostics.s index 47c07df..9761ad9 100644 --- a/llvm/test/MC/AArch64/SVE/stnt1d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/stnt1d-diagnostics.s @@ -18,17 +18,17 @@ stnt1d z29.d, p0, [x3, #8, MUL VL] // Invalid source type. stnt1d z0.b, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1d z0.b, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1d z0.h, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1d z0.h, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1d z0.s, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1d z0.s, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/stnt1h-diagnostics.s b/llvm/test/MC/AArch64/SVE/stnt1h-diagnostics.s index cd3bc25..cf009b7 100644 --- a/llvm/test/MC/AArch64/SVE/stnt1h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/stnt1h-diagnostics.s @@ -18,17 +18,17 @@ stnt1h z29.h, p0, [x3, #8, MUL VL] // Invalid source type. stnt1h z0.b, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1h z0.b, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1h z0.s, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1h z0.s, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1h z0.d, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1h z0.d, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/stnt1w-diagnostics.s b/llvm/test/MC/AArch64/SVE/stnt1w-diagnostics.s index 4e93d89..eb38fca 100644 --- a/llvm/test/MC/AArch64/SVE/stnt1w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/stnt1w-diagnostics.s @@ -18,17 +18,17 @@ stnt1w z29.s, p0, [x3, #8, MUL VL] // Invalid source type. stnt1w z0.b, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1w z0.b, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1w z0.h, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1w z0.h, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1w z0.d, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: stnt1w z0.d, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/sub-diagnostics.s b/llvm/test/MC/AArch64/SVE/sub-diagnostics.s index 1c065aa..e27432f 100644 --- a/llvm/test/MC/AArch64/SVE/sub-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/sub-diagnostics.s @@ -14,7 +14,7 @@ sub z4.h, z27.h, z31.x // Element size specifiers should match. sub z0.h, z8.h, z8.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: sub z0.h, z8.h, z8.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/zip1-diagnostics.s b/llvm/test/MC/AArch64/SVE/zip1-diagnostics.s index f5f7cea..17670be 100644 --- a/llvm/test/MC/AArch64/SVE/zip1-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/zip1-diagnostics.s @@ -8,7 +8,7 @@ zip1 z10.h, z22.h, z31.x // Element size specifiers should match. zip1 z10.h, z3.h, z15.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: zip1 z10.h, z3.h, z15.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -26,7 +26,7 @@ zip1 z1.s, z2.s, z32.s // p16 is not a valid SVE predicate register zip1 p1.s, p2.s, p16.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: zip1 p1.s, p2.s, p16.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -38,6 +38,6 @@ zip1 z1.s, z2.s, p3.s // Combining predicate and data registers as operands zip1 p1.s, p2.s, z3.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: zip1 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/zip2-diagnostics.s b/llvm/test/MC/AArch64/SVE/zip2-diagnostics.s index 7f80ce2..3a78b94 100644 --- a/llvm/test/MC/AArch64/SVE/zip2-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/zip2-diagnostics.s @@ -8,7 +8,7 @@ zip2 z6.h, z23.h, z31.x // Element size specifiers should match. zip2 z0.h, z30.h, z24.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: zip2 z0.h, z30.h, z24.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -26,7 +26,7 @@ zip2 z1.s, z2.s, z32.s // p16 is not a valid SVE predicate register zip2 p1.s, p2.s, p16.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: zip2 p1.s, p2.s, p16.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -38,6 +38,6 @@ zip2 z1.s, z2.s, p3.s // Combining predicate and data registers as operands zip2 p1.s, p2.s, z3.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: zip2 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -- 2.7.4