From 219b8f2ff024a7f8f2cd1a9a0a1d7651c1a02737 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Thu, 10 Sep 2020 16:37:59 +0300 Subject: [PATCH] habanalabs: update firmware interface file Add new packet to fetch PLL information from firmware. This will be needed in the future when the driver won't be able to access the PLL registers directly Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/include/common/cpucp_if.h | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/misc/habanalabs/include/common/cpucp_if.h b/drivers/misc/habanalabs/include/common/cpucp_if.h index dcde440..2a5c9cb 100644 --- a/drivers/misc/habanalabs/include/common/cpucp_if.h +++ b/drivers/misc/habanalabs/include/common/cpucp_if.h @@ -213,6 +213,12 @@ enum pq_init_status { * Trigger the reset_history property of a specified current sensor. * The packet's arguments specify the desired sensor and the field to * set. + * + * CPUCP_PACKET_PLL_REG_GET + * Fetch register of PLL from the required PLL IP. + * The packet's arguments specify the PLL IP and the register to get. + * Each register is 32-bit value which is returned in result field. + * */ enum cpucp_packet_id { @@ -245,6 +251,7 @@ enum cpucp_packet_id { CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */ + CPUCP_PACKET_PLL_REG_GET, /* internal */ }; #define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5 @@ -279,6 +286,11 @@ struct cpucp_packet { __u8 pad; /* unused */ }; + struct {/* For PLL register fetch */ + __le16 pll_type; + __le16 pll_reg; + }; + /* For any general request */ __le32 index; @@ -354,6 +366,19 @@ enum cpucp_pcie_throughput_attributes { cpucp_pcie_throughput_rx }; +enum cpucp_pll_reg_attributes { + cpucp_pll_nr_reg, + cpucp_pll_nf_reg, + cpucp_pll_od_reg, + cpucp_pll_div_factor_reg, + cpucp_pll_div_sel_reg +}; + +enum cpucp_pll_type_attributes { + cpucp_pll_cpu, + cpucp_pll_pci, +}; + /* Event Queue Packets */ struct eq_generic_event { -- 2.7.4