From 218534153ec8932a873dcca48a1a2b4aba0e32b5 Mon Sep 17 00:00:00 2001 From: Yanhong Wang Date: Wed, 29 Mar 2023 11:42:08 +0800 Subject: [PATCH] riscv: cpu: jh7110: Add support for jh7110 SoC Add StarFive JH7110 SoC to support RISC-V arch. Signed-off-by: Yanhong Wang Reviewed-by: Rick Chen Tested-by: Conor Dooley --- arch/riscv/cpu/jh7110/Makefile | 10 +++++ arch/riscv/cpu/jh7110/cpu.c | 23 +++++++++++ arch/riscv/cpu/jh7110/dram.c | 38 ++++++++++++++++++ arch/riscv/cpu/jh7110/spl.c | 64 +++++++++++++++++++++++++++++++ arch/riscv/include/asm/arch-jh7110/regs.h | 19 +++++++++ arch/riscv/include/asm/arch-jh7110/spl.h | 12 ++++++ 6 files changed, 166 insertions(+) create mode 100644 arch/riscv/cpu/jh7110/Makefile create mode 100644 arch/riscv/cpu/jh7110/cpu.c create mode 100644 arch/riscv/cpu/jh7110/dram.c create mode 100644 arch/riscv/cpu/jh7110/spl.c create mode 100644 arch/riscv/include/asm/arch-jh7110/regs.h create mode 100644 arch/riscv/include/asm/arch-jh7110/spl.h diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile new file mode 100644 index 0000000..951c956 --- /dev/null +++ b/arch/riscv/cpu/jh7110/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive Technology Co., Ltd. + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y += spl.o +else +obj-y += cpu.o +obj-y += dram.o +endif diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c new file mode 100644 index 0000000..1d7c026 --- /dev/null +++ b/arch/riscv/cpu/jh7110/cpu.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + */ + +#include +#include + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c new file mode 100644 index 0000000..2ad3f20 --- /dev/null +++ b/arch/riscv/cpu/jh7110/dram.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +phys_size_t board_get_usable_ram_top(phys_size_t total_size) +{ + /* + * Ensure that we run from first 4GB so that all + * addresses used by U-Boot are 32bit addresses. + * + * This in-turn ensures that 32bit DMA capable + * devices work fine because DMA mapping APIs will + * provide 32bit DMA addresses only. + */ + if (IS_ENABLED(CONFIG_64BIT) && gd->ram_top > SZ_4G) + return SZ_4G; + + return gd->ram_top; +} diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c new file mode 100644 index 0000000..104f0fe --- /dev/null +++ b/arch/riscv/cpu/jh7110/spl.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + */ + +#include +#include +#include +#include + +#define CSR_U74_FEATURE_DISABLE 0x7c1 +#define L2_LIM_MEM_END 0x81FFFFFUL + +int spl_soc_init(void) +{ + int ret; + struct udevice *dev; + + /* DDR init */ + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + return 0; +} + +void harts_early_init(void) +{ + ulong *ptr; + u8 *tmp; + ulong len, remain; + /* + * Feature Disable CSR + * + * Clear feature disable CSR to '0' to turn on all features for + * each core. This operation must be in M-mode. + */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) + csr_write(CSR_U74_FEATURE_DISABLE, 0); + + /* clear L2 LIM memory + * set __bss_end to 0x81FFFFF region to zero + * The L2 Cache Controller supports ECC. ECC is applied to SRAM. + * If it is not cleared, the ECC part is invalid, and an ECC error + * will be reported when reading data. + */ + ptr = (ulong *)&__bss_end; + len = L2_LIM_MEM_END - (ulong)&__bss_end; + remain = len % sizeof(ulong); + len /= sizeof(ulong); + + while (len--) + *ptr++ = 0; + + /* clear the remain bytes */ + if (remain) { + tmp = (u8 *)ptr; + while (remain--) + *tmp++ = 0; + } +} diff --git a/arch/riscv/include/asm/arch-jh7110/regs.h b/arch/riscv/include/asm/arch-jh7110/regs.h new file mode 100644 index 0000000..0502687 --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7110/regs.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + */ + +#ifndef __STARFIVE_JH7110_REGS_H +#define __STARFIVE_JH7110_REGS_H + +#define JH7110_SYS_CRG 0x13020000 +#define JH7110_SYS_SYSCON 0x13030000 +#define JH7110_SYS_IOMUX 0x13040000 +#define JH7110_AON_CRG 0x17000000 +#define JH7110_AON_SYSCON 0x17010000 + +#define JH7110_BOOT_MODE_SELECT_REG 0x1702002c +#define JH7110_BOOT_MODE_SELECT_MASK GENMASK(1, 0) + +#endif /* __STARFIVE_JH7110_REGS_H */ diff --git a/arch/riscv/include/asm/arch-jh7110/spl.h b/arch/riscv/include/asm/arch-jh7110/spl.h new file mode 100644 index 0000000..23ce887 --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7110/spl.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Yanhong Wang + */ + +#ifndef _SPL_STARFIVE_H +#define _SPL_STARFIVE_H + +int spl_soc_init(void); + +#endif /* _SPL_STARFIVE_H */ -- 2.7.4