From 216bad9a64ebfac51d36210738d2b9aa3de69511 Mon Sep 17 00:00:00 2001
From: Nico Weber <thakis@chromium.org>
Date: Sun, 31 May 2020 22:04:35 -0400
Subject: [PATCH] [gn build] (semi-manually) port a8ca0ec2670

---
 llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
index f44a40f6..8f55467 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
@@ -42,6 +42,15 @@ tablegen("AMDGPUGenPostLegalizeGICombiner") {
   td_file = "AMDGPUGISel.td"
 }
 
+tablegen("AMDGPUGenRegBankGICombiner") {
+  visibility = [ ":LLVMAMDGPUCodeGen" ]
+  args = [
+    "-gen-global-isel-combiner",
+    "-combiners=AMDGPURegBankCombinerHelper",
+  ]
+  td_file = "AMDGPUGISel.td"
+}
+
 tablegen("AMDGPUGenMCPseudoLowering") {
   visibility = [ ":LLVMAMDGPUCodeGen" ]
   args = [ "-gen-pseudo-lowering" ]
@@ -81,6 +90,7 @@ static_library("LLVMAMDGPUCodeGen") {
     ":AMDGPUGenMCPseudoLowering",
     ":AMDGPUGenPostLegalizeGICombiner",
     ":AMDGPUGenPreLegalizeGICombiner",
+    ":AMDGPUGenRegBankGICombiner",
     ":AMDGPUGenRegisterBank",
     ":R600GenCallingConv",
     ":R600GenDAGISel",
@@ -141,6 +151,7 @@ static_library("LLVMAMDGPUCodeGen") {
     "AMDGPUPrintfRuntimeBinding.cpp",
     "AMDGPUPromoteAlloca.cpp",
     "AMDGPUPropagateAttributes.cpp",
+    "AMDGPURegBankCombiner.cpp",
     "AMDGPURegisterBankInfo.cpp",
     "AMDGPURewriteOutArguments.cpp",
     "AMDGPUSubtarget.cpp",
-- 
2.7.4