From 212af2c081d6a6b2af998bd20294e642396595e2 Mon Sep 17 00:00:00 2001 From: Ivan Kosarev Date: Fri, 19 May 2023 16:28:34 +0100 Subject: [PATCH] [AMDGPU][AsmParser] Refine parsing of some 32-bit instruction operands. Eliminates the need for the custom code in parseCustomOperand(). The remaining uses of NamedOperandU32 are to be addressed separately. Part of . Reviewed By: dp Differential Revision: https://reviews.llvm.org/D150204 --- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 65 ++++++++++------------ .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 17 +++--- .../Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 12 ++-- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 29 ++++------ 4 files changed, 52 insertions(+), 71 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index bf3955a..e768588 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -156,7 +156,7 @@ public: ImmTyDppRowMask, ImmTyDppBankMask, ImmTyDppBoundCtrl, - ImmTyDppFi, + ImmTyDppFI, ImmTySwizzle, ImmTyGprIdxMode, ImmTyHigh, @@ -382,10 +382,10 @@ public: bool isTFE() const { return isImmTy(ImmTyTFE); } bool isD16() const { return isImmTy(ImmTyD16); } bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); } - bool isBankMask() const { return isImmTy(ImmTyDppBankMask); } - bool isRowMask() const { return isImmTy(ImmTyDppRowMask); } + bool isDppBankMask() const { return isImmTy(ImmTyDppBankMask); } + bool isDppRowMask() const { return isImmTy(ImmTyDppRowMask); } bool isDppBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); } - bool isFI() const { return isImmTy(ImmTyDppFi); } + bool isDppFI() const { return isImmTy(ImmTyDppFI); } bool isSDWADstSel() const { return isImmTy(ImmTySDWADstSel); } bool isSDWASrc0Sel() const { return isImmTy(ImmTySDWASrc0Sel); } bool isSDWASrc1Sel() const { return isImmTy(ImmTySDWASrc1Sel); } @@ -1048,7 +1048,7 @@ public: case ImmTyDppRowMask: OS << "DppRowMask"; break; case ImmTyDppBankMask: OS << "DppBankMask"; break; case ImmTyDppBoundCtrl: OS << "DppBoundCtrl"; break; - case ImmTyDppFi: OS << "FI"; break; + case ImmTyDppFI: OS << "DppFI"; break; case ImmTySDWADstSel: OS << "SDWADstSel"; break; case ImmTySDWASrc0Sel: OS << "SDWASrc0Sel"; break; case ImmTySDWASrc1Sel: OS << "SDWASrc1Sel"; break; @@ -1592,6 +1592,7 @@ public: OperandMatchResultTy parseNumericFormat(int64_t &Format); OperandMatchResultTy parseFlatOffset(OperandVector &Operands); OperandMatchResultTy parseR128A16(OperandVector &Operands); + OperandMatchResultTy parseBLGP(OperandVector &Operands); bool tryParseFmt(const char *Pref, int64_t MaxVal, int64_t &Val); bool matchDfmtNfmt(int64_t &Dfmt, int64_t &Nfmt, StringRef FormatStr, SMLoc Loc); @@ -1791,10 +1792,10 @@ public: bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands); int64_t parseDPPCtrlSel(StringRef Ctrl); int64_t parseDPPCtrlPerm(); - AMDGPUOperand::Ptr defaultRowMask() const; - AMDGPUOperand::Ptr defaultBankMask() const; + AMDGPUOperand::Ptr defaultDppRowMask() const; + AMDGPUOperand::Ptr defaultDppBankMask() const; AMDGPUOperand::Ptr defaultDppBoundCtrl() const; - AMDGPUOperand::Ptr defaultFI() const; + AMDGPUOperand::Ptr defaultDppFI() const; void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false); void cvtDPP8(MCInst &Inst, const OperandVector &Operands) { cvtDPP(Inst, Operands, true); @@ -6390,6 +6391,16 @@ OperandMatchResultTy AMDGPUAsmParser::parseR128A16(OperandVector &Operands) { return Res; } +OperandMatchResultTy AMDGPUAsmParser::parseBLGP(OperandVector &Operands) { + OperandMatchResultTy Res = + parseIntWithPrefix("blgp", Operands, AMDGPUOperand::ImmTyBLGP); + if (Res == MatchOperand_NoMatch) { + Res = + parseOperandArrayWithPrefix("neg", Operands, AMDGPUOperand::ImmTyBLGP); + } + return Res; +} + //===----------------------------------------------------------------------===// // ds //===----------------------------------------------------------------------===// @@ -8698,7 +8709,7 @@ AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) { return MatchOperand_Success; } -AMDGPUOperand::Ptr AMDGPUAsmParser::defaultRowMask() const { +AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppRowMask() const { return AMDGPUOperand::CreateImm(this, 0xf, SMLoc(), AMDGPUOperand::ImmTyDppRowMask); } @@ -8706,7 +8717,7 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultEndpgmImmOperands() const { return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyEndpgm); } -AMDGPUOperand::Ptr AMDGPUAsmParser::defaultBankMask() const { +AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppBankMask() const { return AMDGPUOperand::CreateImm(this, 0xf, SMLoc(), AMDGPUOperand::ImmTyDppBankMask); } @@ -8714,8 +8725,8 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppBoundCtrl() const { return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDppBoundCtrl); } -AMDGPUOperand::Ptr AMDGPUAsmParser::defaultFI() const { - return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDppFi); +AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppFI() const { + return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDppFI); } void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, @@ -8762,7 +8773,7 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, } AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); // Add the register arguments - if (IsDPP8 && Op.isFI()) { + if (IsDPP8 && Op.isDppFI()) { Fi = Op.getImm(); } else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) { Op.addRegOrImmWithFPInputModsOperands(Inst, 2); @@ -8804,7 +8815,7 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi)) addOptionalImmOperand(Inst, Operands, OptionalIdx, - AMDGPUOperand::ImmTyDppFi); + AMDGPUOperand::ImmTyDppFI); } } @@ -8839,7 +8850,7 @@ void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool I Op.addImmOperands(Inst, 1); } else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) { Op.addRegWithFPInputModsOperands(Inst, 2); - } else if (Op.isFI()) { + } else if (Op.isDppFI()) { Fi = Op.getImm(); } else if (Op.isReg()) { Op.addRegOperands(Inst, 1); @@ -8870,7 +8881,8 @@ void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool I addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl); if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi)) { - addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppFi); + addOptionalImmOperand(Inst, Operands, OptionalIdx, + AMDGPUOperand::ImmTyDppFI); } } } @@ -9117,26 +9129,8 @@ AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, unsigned MCK) { return parseTokenOp("off", Operands); case MCK_row_95_en: return parseTokenOp("row_en", Operands); - case MCK_ImmABID: - return parseIntWithPrefix("abid", Operands, AMDGPUOperand::ImmTyABID); - case MCK_ImmBankMask: - return parseIntWithPrefix("bank_mask", Operands, - AMDGPUOperand::ImmTyDppBankMask); - case MCK_ImmBLGP: { - OperandMatchResultTy Res = - parseIntWithPrefix("blgp", Operands, AMDGPUOperand::ImmTyBLGP); - if (Res == MatchOperand_NoMatch) { - Res = parseOperandArrayWithPrefix("neg", Operands, - AMDGPUOperand::ImmTyBLGP); - } - return Res; - } - case MCK_ImmCBSZ: - return parseIntWithPrefix("cbsz", Operands, AMDGPUOperand::ImmTyCBSZ); case MCK_ImmCPol: return parseCPol(Operands); - case MCK_ImmFI: - return parseIntWithPrefix("fi", Operands, AMDGPUOperand::ImmTyDppFi); case MCK_gds: return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS); case MCK_ImmNegHi: @@ -9153,9 +9147,6 @@ AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, unsigned MCK) { case MCK_ImmOpSelHi: return parseOperandArrayWithPrefix("op_sel_hi", Operands, AMDGPUOperand::ImmTyOpSelHi); - case MCK_ImmRowMask: - return parseIntWithPrefix("row_mask", Operands, - AMDGPUOperand::ImmTyDppRowMask); case MCK_tfe: return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE); } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index a654686..bd0d2f8 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -1003,16 +1003,16 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo, } } -void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { +void AMDGPUInstPrinter::printDppRowMask(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { O << " row_mask:"; printU4ImmOperand(MI, OpNo, STI, O); } -void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { +void AMDGPUInstPrinter::printDppBankMask(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { O << " bank_mask:"; printU4ImmOperand(MI, OpNo, STI, O); } @@ -1026,9 +1026,8 @@ void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo, } } -void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { +void AMDGPUInstPrinter::printDppFI(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O) { using namespace llvm::AMDGPU::DPP; unsigned Imm = MI->getOperand(OpNo).getImm(); if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) { diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h index d4e007f..1a5fdb8 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -131,14 +131,14 @@ private: raw_ostream &O); void printDPPCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printRowMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printBankMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); + void printDppRowMask(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); + void printDppBankMask(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printDppBoundCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printFI(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); + void printDppFI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, + raw_ostream &O); void printSDWASel(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printSDWADstSel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index d318bed..47675a7 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -988,13 +988,6 @@ def EndpgmMatchClass : AsmOperandClass { let IsOptional = 1; } -def ExpTgtMatchClass : AsmOperandClass { - let Name = "ExpTgt"; - let PredicateMethod = "isExpTgt"; - let ParserMethod = "parseExpTgt"; - let RenderMethod = "printExpTgt"; -} - def SWaitMatchClass : AsmOperandClass { let Name = "SWaitCnt"; let RenderMethod = "addImmOperands"; @@ -1268,24 +1261,22 @@ def op_sel_hi0 : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>; def neg_lo0 : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>; def neg_hi0 : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>; -def dpp8 : NamedOperandU32<"DPP8", NamedMatchClass<"DPP8", 0>>; -def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>; +def dpp8 : CustomOperand; +def dpp_ctrl : CustomOperand; -def row_mask : NamedOperandU32<"RowMask", NamedMatchClass<"RowMask">>; -def bank_mask : NamedOperandU32<"BankMask", NamedMatchClass<"BankMask">>; +def row_mask : NamedIntOperand; +def bank_mask : NamedIntOperand; def bound_ctrl : NamedIntOperand bool { return convertDppBoundCtrl(BC); }">; -def FI : NamedOperandU32<"FI", NamedMatchClass<"FI">>; +def FI : NamedIntOperand; -def blgp : NamedOperandU32<"BLGP", NamedMatchClass<"BLGP">>; -def cbsz : NamedOperandU32<"CBSZ", NamedMatchClass<"CBSZ">>; -def abid : NamedOperandU32<"ABID", NamedMatchClass<"ABID">>; +def blgp : CustomOperand; +def cbsz : NamedIntOperand; +def abid : NamedIntOperand; -def hwreg : NamedOperandU32<"Hwreg", NamedMatchClass<"Hwreg", 0>>; +def hwreg : CustomOperand; -def exp_tgt : NamedOperandU32<"ExpTgt", NamedMatchClass<"ExpTgt", 0>> { - -} +def exp_tgt : CustomOperand; def wait_vdst : NamedIntOperand; def wait_exp : NamedIntOperand; -- 2.7.4