From 210dd1b22011f610c0e3212484650639ff5c741d Mon Sep 17 00:00:00 2001 From: Tanner Gooding Date: Wed, 6 May 2020 17:54:27 -0700 Subject: [PATCH] Ensure we account for intrinsics which have gtType=TYP_SIMD16 but gtSIMDSize=32 (#35904) --- src/coreclr/src/jit/lower.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/coreclr/src/jit/lower.cpp b/src/coreclr/src/jit/lower.cpp index 9389b21..16a0ee7 100644 --- a/src/coreclr/src/jit/lower.cpp +++ b/src/coreclr/src/jit/lower.cpp @@ -1334,7 +1334,13 @@ void Lowering::LowerArg(GenTreeCall* call, GenTree** ppArg) else if (arg->OperIs(GT_SIMD, GT_HWINTRINSIC)) { GenTreeJitIntrinsic* jitIntrinsic = reinterpret_cast(arg); - assert((jitIntrinsic->gtSIMDSize == 12) || (jitIntrinsic->gtSIMDSize == 16)); + + // For HWIntrinsic, there are some intrinsics like ExtractVector128 which have + // a gtType of TYP_SIMD16 but a gtSIMDSize of 32, so we need to include that in + // the assert below. + + assert((jitIntrinsic->gtSIMDSize == 12) || (jitIntrinsic->gtSIMDSize == 16) || + (jitIntrinsic->gtSIMDSize == 32)); if (jitIntrinsic->gtSIMDSize == 12) { -- 2.7.4