From 20c02807333a47000879e0f673cdf2d6b07148dd Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Fri, 24 Sep 2021 16:50:55 +0100 Subject: [PATCH] [LiveIntervals] Repair subreg ranges in processTiedPairs In TwoAddressInstructionPass::processTiedPairs, update subranges of the live interval for RegB as well as the main range. This is a small step towards switching TwoAddressInstructionPass over from LiveVariables to LiveIntervals. Currently this path is only tested if you explicitly enable -early-live-intervals. Differential Revision: https://reviews.llvm.org/D110526 --- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | 4 ++++ llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll | 1 + llvm/test/CodeGen/SystemZ/subregliveness-01.ll | 1 + llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll | 1 + 4 files changed, 7 insertions(+) diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 74a4f7d..a59c5b4 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -1453,6 +1453,10 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI, SlotIndex endIdx = LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber); LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI)); + for (auto &S : LI.subranges()) { + VNI = S.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator()); + S.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI)); + } } } diff --git a/llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll b/llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll index 4bd1a51..1d675c8 100644 --- a/llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll +++ b/llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll @@ -1,6 +1,7 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O2 < %s -pipeliner-experimental-cg=true | FileCheck %s ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true -early-live-intervals -verify-machineinstrs | FileCheck %s ; ; Check that we pipeline a vectorized dot product in a single packet. ; diff --git a/llvm/test/CodeGen/SystemZ/subregliveness-01.ll b/llvm/test/CodeGen/SystemZ/subregliveness-01.ll index 83a3579..7e76469 100644 --- a/llvm/test/CodeGen/SystemZ/subregliveness-01.ll +++ b/llvm/test/CodeGen/SystemZ/subregliveness-01.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs -systemz-subreg-liveness < %s | FileCheck %s +; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs -systemz-subreg-liveness -early-live-intervals < %s | FileCheck %s ; Check for successful compilation. ; CHECK: lgfrl %r0, g_399 diff --git a/llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll b/llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll index 1574263..cab8991 100644 --- a/llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll +++ b/llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -O3 -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -O3 -mattr=+mve -early-live-intervals -verify-machineinstrs %s -o - | FileCheck %s declare void @external_function() -- 2.7.4