From 209d52110a32c2069b5d870504e73fdb0e30fc51 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 25 Jan 2013 21:44:48 +0200 Subject: [PATCH] drm/i915: Set the SR01 "screen off" bit in i915_redisable_vga() too MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit From BSpec / SR01 - Clocking Mode: "The following sequence must be used when disabling the VGA plane. Write SR01 to set bit 5 = 1 to disable video output. Wait for 100us. Disable the VGA plane via Bit 31 of the MMIO VGA control." So simply call i915_disable_vga() from i915_redisable_vga(). Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 62f4590..d75c6a0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8936,8 +8936,7 @@ void i915_redisable_vga(struct drm_device *dev) if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); - I915_WRITE(vga_reg, VGA_DISP_DISABLE); - POSTING_READ(vga_reg); + i915_disable_vga(dev); } } -- 2.7.4