From 206d46a192c5134387d28d063b8b1e01882ae70a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 11 Jan 2020 09:05:27 -0500 Subject: [PATCH] AMDGPU/GlobalISel: Add some tests that used to infinite loop --- .../CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir | 15 +++++++++++++++ .../CodeGen/AMDGPU/GlobalISel/legalize-sext.mir | 18 ++++++++++++++++++ .../CodeGen/AMDGPU/GlobalISel/legalize-zext.mir | 21 +++++++++++++++++++++ 3 files changed, 54 insertions(+) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir index 15c6d3f..13fcb74 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir @@ -652,3 +652,18 @@ body: | %2:_(s112) = G_ANYEXT %1 S_ENDPGM 0, implicit %2 ... + +--- +name: test_anyext_s112_to_s128 +body: | + bb.0: + liveins: $vgpr0_vgpr1_vgpr2_vgpr3 + ; CHECK-LABEL: name: test_anyext_s112_to_s128 + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 + ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY [[COPY]](s128) + ; CHECK: S_ENDPGM 0, implicit [[COPY1]](s128) + %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 + %1:_(s112) = G_TRUNC %0 + %2:_(s128) = G_ANYEXT %1 + S_ENDPGM 0, implicit %2 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir index e384a92..4d743f55 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir @@ -716,3 +716,21 @@ body: | # %2:_(s112) = G_SEXT %1 # S_ENDPGM 0, implicit %2 # ... + +--- +name: test_sext_s112_to_s128 +body: | + bb.0: + liveins: $vgpr0_vgpr1_vgpr2_vgpr3 + ; CHECK-LABEL: name: test_sext_s112_to_s128 + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 + ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY [[COPY]](s128) + ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128) + ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[UV1]], 48 + ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV]](s64), [[SEXT_INREG]](s64) + ; CHECK: S_ENDPGM 0, implicit [[MV]](s128) + %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 + %1:_(s112) = G_TRUNC %0 + %2:_(s128) = G_SEXT %1 + S_ENDPGM 0, implicit %2 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir index 18af29f..0398945 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir @@ -716,3 +716,24 @@ body: | %2:_(s112) = G_ZEXT %1 S_ENDPGM 0, implicit %2 ... + +--- +name: test_zext_s112_to_s128 +body: | + bb.0: + liveins: $vgpr0_vgpr1_vgpr2_vgpr3 + ; CHECK-LABEL: name: test_zext_s112_to_s128 + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655 + ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY [[COPY]](s128) + ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128) + ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C]] + ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]] + ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[AND]](s64), [[AND1]](s64) + ; CHECK: S_ENDPGM 0, implicit [[MV]](s128) + %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 + %1:_(s112) = G_TRUNC %0 + %2:_(s128) = G_ZEXT %1 + S_ENDPGM 0, implicit %2 +... -- 2.7.4