From 204dfabfe68a978620258baaa0bacb55cbd6859d Mon Sep 17 00:00:00 2001 From: Puyan Lotfi Date: Mon, 16 Dec 2019 18:49:03 -0500 Subject: [PATCH] [NFC][llvm][MIRVRegNamerUtils] Moving some switch cases and altering comments. --- llvm/lib/CodeGen/MIRVRegNamerUtils.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp index 4467076..d0670dc 100644 --- a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp +++ b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp @@ -60,14 +60,14 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) { return hash_combine( MO.getType(), MO.getTargetFlags(), MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue()); - case MachineOperand::MO_Immediate: - return MO.getImm(); - case MachineOperand::MO_TargetIndex: - return MO.getOffset() | (MO.getTargetFlags() << 16); case MachineOperand::MO_Register: if (Register::isVirtualRegister(MO.getReg())) return MRI.getVRegDef(MO.getReg())->getOpcode(); return MO.getReg(); + case MachineOperand::MO_Immediate: + return MO.getImm(); + case MachineOperand::MO_TargetIndex: + return MO.getOffset() | (MO.getTargetFlags() << 16); // We could explicitly handle all the types of the MachineOperand, // here but we can just return a common number until we find a @@ -75,7 +75,7 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) { // is contributing to a hash collision but there's enough information // (Opcodes,other registers etc) that this will likely not be a problem. - // TODO: Handle the following Immediate/Index/ID/Predicate cases. They can + // TODO: Handle the following Index/ID/Predicate cases. They can // be hashed on in a stable manner. case MachineOperand::MO_FrameIndex: case MachineOperand::MO_ConstantPoolIndex: -- 2.7.4