From 1fb87ace4d097138de0027e633d9d6d83246093b Mon Sep 17 00:00:00 2001 From: LiaoChunyu Date: Fri, 19 Aug 2022 16:14:19 +0800 Subject: [PATCH] [RISCV] Optimize x > 1 ? x : 1 -> x > 0 ? x : 1 if x == 1, x > 1 ? x : 1 return x, which is also 1. x > 0 ? x : 1 return 1. Reduce the number of load 1 instructions. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D132211 --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 ++++++ llvm/test/CodeGen/RISCV/forced-atomics.ll | 12 ++++-------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index d0d48c0..800c529 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -4083,6 +4083,12 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { } translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG); + // 1 < x ? x : 1 -> 0 < x ? x : 1 + if (isOneConstant(LHS) && !isa(RHS) && + (CCVal == ISD::SETLT || CCVal == ISD::SETULT) && RHS == TrueV && + isOneConstant(FalseV)) { + LHS = DAG.getConstant(0, DL, VT); + } SDValue TargetCC = DAG.getCondCode(CCVal); SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll index fc03091..d8b33fe 100644 --- a/llvm/test/CodeGen/RISCV/forced-atomics.ll +++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll @@ -995,9 +995,8 @@ define i32 @rmw32_max_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB23_4 ; RV32-NO-ATOMIC-NEXT: .LBB23_2: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32-NO-ATOMIC-NEXT: li a0, 1 ; RV32-NO-ATOMIC-NEXT: mv a2, a1 -; RV32-NO-ATOMIC-NEXT: blt a0, a1, .LBB23_1 +; RV32-NO-ATOMIC-NEXT: bgtz a1, .LBB23_1 ; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB23_2 Depth=1 ; RV32-NO-ATOMIC-NEXT: li a2, 1 @@ -1183,9 +1182,8 @@ define i32 @rmw32_umax_seq_cst(ptr %p) nounwind { ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB25_4 ; RV32-NO-ATOMIC-NEXT: .LBB25_2: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32-NO-ATOMIC-NEXT: li a0, 1 ; RV32-NO-ATOMIC-NEXT: mv a2, a1 -; RV32-NO-ATOMIC-NEXT: bltu a0, a1, .LBB25_1 +; RV32-NO-ATOMIC-NEXT: bltu zero, a1, .LBB25_1 ; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB25_2 Depth=1 ; RV32-NO-ATOMIC-NEXT: li a2, 1 @@ -2563,9 +2561,8 @@ define i64 @rmw64_max_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB49_4 ; RV64-NO-ATOMIC-NEXT: .LBB49_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64-NO-ATOMIC-NEXT: li a0, 1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1 -; RV64-NO-ATOMIC-NEXT: blt a0, a1, .LBB49_1 +; RV64-NO-ATOMIC-NEXT: bgtz a1, .LBB49_1 ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: li a2, 1 @@ -2756,9 +2753,8 @@ define i64 @rmw64_umax_seq_cst(ptr %p) nounwind { ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB51_4 ; RV64-NO-ATOMIC-NEXT: .LBB51_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64-NO-ATOMIC-NEXT: li a0, 1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1 -; RV64-NO-ATOMIC-NEXT: bltu a0, a1, .LBB51_1 +; RV64-NO-ATOMIC-NEXT: bltu zero, a1, .LBB51_1 ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: li a2, 1 -- 2.7.4