From 1f9e23e3cca1e51c0b9a1f30477e87ddf1b764a8 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Mon, 4 Feb 2019 22:27:08 +0000
Subject: [PATCH] [CGP] add tests for usubo; NFC

llvm-svn: 353103
---
 .../CodeGenPrepare/X86/overflow-intrinsics.ll      | 155 ++++++++++++++++++++-
 1 file changed, 154 insertions(+), 1 deletion(-)

diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll b/llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll
index 9b88186..32c979c 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll
@@ -159,7 +159,7 @@ define i1 @uaddo_i16_increment_noncanonical_3(i16 %x, i16* %p) {
   ret i1 %ov
 }
 
-; TODO: Did we really intend to match this if it's not supported by the target?
+; No transform for illegal types.
 
 define i1 @uaddo_i42_increment_illegal_type(i42 %x, i42* %p) {
 ; CHECK-LABEL: @uaddo_i42_increment_illegal_type(
@@ -174,6 +174,159 @@ define i1 @uaddo_i42_increment_illegal_type(i42 %x, i42* %p) {
   ret i1 %ov
 }
 
+define i1 @usubo_ult_i64(i64 %x, i64 %y, i64* %p) {
+; CHECK-LABEL: @usubo_ult_i64(
+; CHECK-NEXT:    [[S:%.*]] = sub i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    store i64 [[S]], i64* [[P:%.*]]
+; CHECK-NEXT:    [[OV:%.*]] = icmp ult i64 [[X]], [[Y]]
+; CHECK-NEXT:    ret i1 [[OV]]
+;
+  %s = sub i64 %x, %y
+  store i64 %s, i64* %p
+  %ov = icmp ult i64 %x, %y
+  ret i1 %ov
+}
+
+; Verify insertion point for single-BB. Toggle predicate.
+
+define i1 @usubo_ugt_i32(i32 %x, i32 %y, i32* %p) {
+; CHECK-LABEL: @usubo_ugt_i32(
+; CHECK-NEXT:    [[OV:%.*]] = icmp ugt i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[S:%.*]] = sub i32 [[X]], [[Y]]
+; CHECK-NEXT:    store i32 [[S]], i32* [[P:%.*]]
+; CHECK-NEXT:    ret i1 [[OV]]
+;
+  %ov = icmp ugt i32 %y, %x
+  %s = sub i32 %x, %y
+  store i32 %s, i32* %p
+  ret i1 %ov
+}
+
+; Constant operand should match.
+
+define i1 @usubo_ugt_constant_op1_i8(i8 %x, i8* %p) {
+; CHECK-LABEL: @usubo_ugt_constant_op1_i8(
+; CHECK-NEXT:    [[S:%.*]] = sub i8 42, [[X:%.*]]
+; CHECK-NEXT:    [[OV:%.*]] = icmp ugt i8 [[X]], 42
+; CHECK-NEXT:    store i8 [[S]], i8* [[P:%.*]]
+; CHECK-NEXT:    ret i1 [[OV]]
+;
+  %s = sub i8 42, %x
+  %ov = icmp ugt i8 %x, 42
+  store i8 %s, i8* %p
+  ret i1 %ov
+}
+
+; Compare with constant operand 0 is canonicalized by commuting, but verify match for non-canonical form.
+
+define i1 @usubo_ult_constant_op1_i16(i16 %x, i16* %p) {
+; CHECK-LABEL: @usubo_ult_constant_op1_i16(
+; CHECK-NEXT:    [[S:%.*]] = sub i16 43, [[X:%.*]]
+; CHECK-NEXT:    [[OV:%.*]] = icmp ult i16 43, [[X]]
+; CHECK-NEXT:    store i16 [[S]], i16* [[P:%.*]]
+; CHECK-NEXT:    ret i1 [[OV]]
+;
+  %s = sub i16 43, %x
+  %ov = icmp ult i16 43, %x
+  store i16 %s, i16* %p
+  ret i1 %ov
+}
+
+; Subtract with constant operand 0 is canonicalized to add.
+
+define i1 @usubo_ult_constant_op0_i16(i16 %x, i16* %p) {
+; CHECK-LABEL: @usubo_ult_constant_op0_i16(
+; CHECK-NEXT:    [[S:%.*]] = add i16 [[X:%.*]], -44
+; CHECK-NEXT:    [[OV:%.*]] = icmp ult i16 [[X]], 44
+; CHECK-NEXT:    store i16 [[S]], i16* [[P:%.*]]
+; CHECK-NEXT:    ret i1 [[OV]]
+;
+  %s = add i16 %x, -44
+  %ov = icmp ult i16 %x, 44
+  store i16 %s, i16* %p
+  ret i1 %ov
+}
+
+define i1 @usubo_ugt_constant_op0_i8(i8 %x, i8* %p) {
+; CHECK-LABEL: @usubo_ugt_constant_op0_i8(
+; CHECK-NEXT:    [[S:%.*]] = add i8 [[X:%.*]], -45
+; CHECK-NEXT:    [[OV:%.*]] = icmp ugt i8 45, [[X]]
+; CHECK-NEXT:    store i8 [[S]], i8* [[P:%.*]]
+; CHECK-NEXT:    ret i1 [[OV]]
+;
+  %s = add i8 %x, -45
+  %ov = icmp ugt i8 45, %x
+  store i8 %s, i8* %p
+  ret i1 %ov
+}
+
+; Verify insertion point for multi-BB.
+
+declare void @call(i1)
+
+define i1 @usubo_ult_sub_dominates_i64(i64 %x, i64 %y, i64* %p, i1 %cond) {
+; CHECK-LABEL: @usubo_ult_sub_dominates_i64(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
+; CHECK:       t:
+; CHECK-NEXT:    [[S:%.*]] = sub i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    store i64 [[S]], i64* [[P:%.*]]
+; CHECK-NEXT:    br i1 [[COND]], label [[END:%.*]], label [[F]]
+; CHECK:       f:
+; CHECK-NEXT:    ret i1 [[COND]]
+; CHECK:       end:
+; CHECK-NEXT:    [[OV:%.*]] = icmp ult i64 [[X]], [[Y]]
+; CHECK-NEXT:    ret i1 [[OV]]
+;
+entry:
+  br i1 %cond, label %t, label %f
+
+t:
+  %s = sub i64 %x, %y
+  store i64 %s, i64* %p
+  br i1 %cond, label %end, label %f
+
+f:
+  ret i1 %cond
+
+end:
+  %ov = icmp ult i64 %x, %y
+  ret i1 %ov
+}
+
+define i1 @usubo_ult_cmp_dominates_i64(i64 %x, i64 %y, i64* %p, i1 %cond) {
+; CHECK-LABEL: @usubo_ult_cmp_dominates_i64(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]]
+; CHECK:       t:
+; CHECK-NEXT:    [[OV:%.*]] = icmp ult i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    call void @call(i1 [[OV]])
+; CHECK-NEXT:    br i1 [[OV]], label [[END:%.*]], label [[F]]
+; CHECK:       f:
+; CHECK-NEXT:    ret i1 [[COND]]
+; CHECK:       end:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i64 [[X]], [[Y]]
+; CHECK-NEXT:    [[S:%.*]] = sub i64 [[X]], [[Y]]
+; CHECK-NEXT:    store i64 [[S]], i64* [[P:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP0]]
+;
+entry:
+  br i1 %cond, label %t, label %f
+
+t:
+  %ov = icmp ult i64 %x, %y
+  call void @call(i1 %ov)
+  br i1 %ov, label %end, label %f
+
+f:
+  ret i1 %cond
+
+end:
+  %s = sub i64 %x, %y
+  store i64 %s, i64* %p
+  ret i1 %ov
+}
+
 ; Check that every instruction inserted by -codegenprepare has a debug location.
 ; DEBUG: CheckModuleDebugify: PASS
 
-- 
2.7.4