From 1f8eabf77aafb1b35f7e9aeeeb8aa67893e5473c Mon Sep 17 00:00:00 2001 From: Tanner Gooding Date: Wed, 8 Feb 2023 11:09:09 -0800 Subject: [PATCH] Ensure CNS_VEC and BLK are handled for `setLclRelatedToSIMDIntrinsic` (#81760) --- src/coreclr/jit/gentree.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp index f386a63..0edd913 100644 --- a/src/coreclr/jit/gentree.cpp +++ b/src/coreclr/jit/gentree.cpp @@ -8166,11 +8166,12 @@ GenTree* Compiler::gtNewBlkOpNode(GenTree* dst, GenTree* srcOrFillVal, bool isVo // should be labeled as simd intrinsic related struct. This is done so that // we do not promote the local, thus avoiding conflicting access methods // (fields vs. whole-register). - if (varTypeIsSIMD(srcOrFillVal) && srcOrFillVal->OperIsHWIntrinsic()) + if (varTypeIsSIMD(srcOrFillVal) && srcOrFillVal->OperIs(GT_HWINTRINSIC, GT_CNS_VEC)) { // TODO-Cleanup: similar logic already exists in "gtNewAssignNode", // however, it is not enabled for x86. Fix that and delete this code. GenTreeLclVar* dstLclNode = nullptr; + if (dst->OperIs(GT_LCL_VAR)) { dstLclNode = dst->AsLclVar(); @@ -18853,7 +18854,7 @@ void Compiler::SetOpLclRelatedToSIMDIntrinsic(GenTree* op) { setLclRelatedToSIMDIntrinsic(op); } - else if (op->OperIs(GT_OBJ) && op->AsIndir()->Addr()->OperIs(GT_LCL_VAR_ADDR)) + else if (op->OperIsBlk() && op->AsIndir()->Addr()->OperIs(GT_LCL_VAR_ADDR)) { setLclRelatedToSIMDIntrinsic(op->AsIndir()->Addr()); } -- 2.7.4