From 1f42a2c93d4ca157ba064c467b13f21283307d26 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jo=C3=A3o=20M=C3=A1rio=20Domingos?= Date: Tue, 16 Nov 2021 15:48:11 +0000 Subject: [PATCH] RISC-V: Added generic pmu-events mapfile MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The pmu-events now supports custom events for RISC-V, plus the cycle, time and instret events were defined. Signed-off-by: João Mário Domingos --- tools/perf/pmu-events/arch/riscv/mapfile.csv | 14 ++++++++++++++ tools/perf/pmu-events/arch/riscv/riscv-generic.json | 20 ++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv new file mode 100644 index 0000000..4f2aa19 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -0,0 +1,14 @@ +# Format: +# MIDR,Version,JSON/file/pathname,Type +# +# where +# MIDR Processor version +# Variant[23:20] and Revision [3:0] should be zero. +# Version could be used to track version of JSON file +# but currently unused. +# JSON/file/pathname is the path to JSON file, relative +# to tools/perf/pmu-events/arch/riscv/. +# Type is core, uncore etc +# +# +#Family-model,Version,Filename,EventType diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json b/tools/perf/pmu-events/arch/riscv/riscv-generic.json new file mode 100644 index 0000000..013e50e --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json @@ -0,0 +1,20 @@ +[ + { + "PublicDescription": "CPU Cycles", + "EventCode": "0x00", + "EventName": "riscv_cycles", + "BriefDescription": "CPU cycles RISC-V generic counter" + }, + { + "PublicDescription": "CPU Time", + "EventCode": "0x01", + "EventName": "riscv_time", + "BriefDescription": "CPU time RISC-V generic counter" + }, + { + "PublicDescription": "CPU Instructions", + "EventCode": "0x02", + "EventName": "riscv_instret", + "BriefDescription": "CPU retired instructions RISC-V generic counter" + } +] \ No newline at end of file -- 2.7.4