From 1f0fe564605b2c5ff7da6e7b4cd4f9954bad2407 Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Mon, 12 Mar 2018 13:16:12 +0000 Subject: [PATCH] [mips] Split out ASEPredicate from InsnPredicates (NFC) This simplifies tagging instructions with the correct ISA and ASE, albeit making instruction definitions a bit more verbose. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44299 llvm-svn: 327265 --- llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td | 4 +-- llvm/lib/Target/Mips/Mips.td | 5 +++- llvm/lib/Target/Mips/MipsDSPInstrFormats.td | 10 +++---- llvm/lib/Target/Mips/MipsEVAInstrInfo.td | 36 ++++++++++++------------ llvm/lib/Target/Mips/MipsInstrInfo.td | 21 ++++++-------- 5 files changed, 38 insertions(+), 38 deletions(-) diff --git a/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td index af6473c..e6fa0a4 100644 --- a/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td +++ b/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td @@ -9,7 +9,7 @@ class MMDSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl { - let InsnPredicates = [HasDSP]; + let ASEPredicate = [HasDSP]; let AdditionalPredicates = [InMicroMips]; string BaseOpcode = opstr; string Arch = "mmdsp"; @@ -18,7 +18,7 @@ class MMDSPInst class MMDSPInstAlias : InstAlias, PredicateControl { - let InsnPredicates = [HasDSP]; + let ASEPredicate = [HasDSP]; let AdditionalPredicates = [InMicroMips]; } diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td index 4a99a9f..a757f85 100644 --- a/llvm/lib/Target/Mips/Mips.td +++ b/llvm/lib/Target/Mips/Mips.td @@ -28,8 +28,10 @@ class PredicateControl { list PTRPredicates = []; // Predicates for the FGR size and layout such as IsFP64bit list FGRPredicates = []; - // Predicates for the instruction group membership such as ISA's and ASE's + // Predicates for the instruction group membership such as ISA's. list InsnPredicates = []; + // Predicate for the ASE that an instruction belongs to. + list ASEPredicate = []; // Predicate for marking the instruction as usable in hard-float mode only. list HardFloatPredicate = []; // Predicates for anything else @@ -40,6 +42,7 @@ class PredicateControl { FGRPredicates, InsnPredicates, HardFloatPredicate, + ASEPredicate, AdditionalPredicates); } diff --git a/llvm/lib/Target/Mips/MipsDSPInstrFormats.td b/llvm/lib/Target/Mips/MipsDSPInstrFormats.td index 2dcefdc..c433921 100644 --- a/llvm/lib/Target/Mips/MipsDSPInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsDSPInstrFormats.td @@ -29,11 +29,11 @@ def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">, AssemblerPredicate<"FeatureDSPR3">; class ISA_DSPR2 { - list InsnPredicates = [HasDSPR2]; + list ASEPredicate = [HasDSPR2]; } class ISA_DSPR3 { - list InsnPredicates = [HasDSPR3]; + list ASEPredicate = [HasDSPR3]; } // Fields. @@ -46,7 +46,7 @@ def REGIMM_OPCODE : Field6<0b000001>; class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl { - let InsnPredicates = [HasDSP]; + let ASEPredicate = [HasDSP]; string BaseOpcode = opstr; string Arch = "dsp"; } @@ -54,12 +54,12 @@ class DSPInst class PseudoDSP pattern, InstrItinClass itin = IIPseudo> : MipsPseudo { - let InsnPredicates = [HasDSP]; + let ASEPredicate = [HasDSP]; } class DSPInstAlias : InstAlias, PredicateControl { - let InsnPredicates = [HasDSP]; + let ASEPredicate = [HasDSP]; } // ADDU.QB sub-class format. diff --git a/llvm/lib/Target/Mips/MipsEVAInstrInfo.td b/llvm/lib/Target/Mips/MipsEVAInstrInfo.td index 41b7014..3edd494 100644 --- a/llvm/lib/Target/Mips/MipsEVAInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsEVAInstrInfo.td @@ -178,37 +178,37 @@ class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem_simm9, II_PREFE>; //===----------------------------------------------------------------------===// /// Load and Store EVA Instructions -def LBE : MMRel, LBE_ENC, LBE_DESC, INSN_EVA; -def LBuE : MMRel, LBuE_ENC, LBuE_DESC, INSN_EVA; -def LHE : MMRel, LHE_ENC, LHE_DESC, INSN_EVA; -def LHuE : MMRel, LHuE_ENC, LHuE_DESC, INSN_EVA; +def LBE : MMRel, LBE_ENC, LBE_DESC, ASE_EVA; +def LBuE : MMRel, LBuE_ENC, LBuE_DESC, ASE_EVA; +def LHE : MMRel, LHE_ENC, LHE_DESC, ASE_EVA; +def LHuE : MMRel, LHuE_ENC, LHuE_DESC, ASE_EVA; let AdditionalPredicates = [NotInMicroMips] in { -def LWE : MMRel, LWE_ENC, LWE_DESC, INSN_EVA; +def LWE : MMRel, LWE_ENC, LWE_DESC, ASE_EVA; } -def SBE : MMRel, SBE_ENC, SBE_DESC, INSN_EVA; -def SHE : MMRel, SHE_ENC, SHE_DESC, INSN_EVA; +def SBE : MMRel, SBE_ENC, SBE_DESC, ASE_EVA; +def SHE : MMRel, SHE_ENC, SHE_DESC, ASE_EVA; let AdditionalPredicates = [NotInMicroMips] in { -def SWE : MMRel, SWE_ENC, SWE_DESC, INSN_EVA; +def SWE : MMRel, SWE_ENC, SWE_DESC, ASE_EVA; } /// load/store left/right EVA let AdditionalPredicates = [NotInMicroMips] in { -def LWLE : LWLE_ENC, LWLE_DESC, INSN_EVA_NOT_32R6_64R6; -def LWRE : LWRE_ENC, LWRE_DESC, INSN_EVA_NOT_32R6_64R6; -def SWLE : SWLE_ENC, SWLE_DESC, INSN_EVA_NOT_32R6_64R6; -def SWRE : SWRE_ENC, SWRE_DESC, INSN_EVA_NOT_32R6_64R6; +def LWLE : LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; +def LWRE : LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; +def SWLE : SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; +def SWRE : SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; } /// Load-linked EVA, Store-conditional EVA let AdditionalPredicates = [NotInMicroMips] in { -def LLE : MMRel, LLE_ENC, LLE_DESC, INSN_EVA; -def SCE : MMRel, SCE_ENC, SCE_DESC, INSN_EVA; +def LLE : MMRel, LLE_ENC, LLE_DESC, ASE_EVA; +def SCE : MMRel, SCE_ENC, SCE_DESC, ASE_EVA; } let AdditionalPredicates = [NotInMicroMips] in { - def TLBINV : TLBINV_ENC, TLBINV_DESC, INSN_EVA; - def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, INSN_EVA; + def TLBINV : TLBINV_ENC, TLBINV_DESC, ASE_EVA; + def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ASE_EVA; } -def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, INSN_EVA; -def PREFE : MMRel, PREFE_ENC, PREFE_DESC, INSN_EVA; +def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, ASE_EVA; +def PREFE : MMRel, PREFE_ENC, PREFE_DESC, ASE_EVA; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 9e2db64..45ebc4e 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -361,10 +361,7 @@ class ISA_MICROMIPS32_NOT_MIPS32R6 { list InsnPredicates = [NotMips32r6]; list EncodingPredicates = [InMicroMips]; } -class INSN_EVA { list InsnPredicates = [HasEVA]; } -class INSN_EVA_NOT_32R6_64R6 { - list InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA]; -} +class ASE_EVA { list ASEPredicate = [HasEVA]; } // The portions of MIPS-III that were also added to MIPS32 class INSN_MIPS3_32 { @@ -419,31 +416,31 @@ class INSN_MIPS5_32R2_NOT_32R6_64R6 { } class ASE_CNMIPS { - list InsnPredicates = [HasCnMips]; + list ASEPredicate = [HasCnMips]; } class NOT_ASE_CNMIPS { - list InsnPredicates = [NotCnMips]; + list ASEPredicate = [NotCnMips]; } class ASE_MIPS64_CNMIPS { - list InsnPredicates = [HasMips64, HasCnMips]; + list ASEPredicate = [HasMips64, HasCnMips]; } class ASE_MSA { - list InsnPredicates = [HasMSA]; + list ASEPredicate = [HasMSA]; } class ASE_MSA_NOT_MSA64 { - list InsnPredicates = [HasMSA, NotMips64]; + list ASEPredicate = [HasMSA, NotMips64]; } class ASE_MSA64 { - list InsnPredicates = [HasMSA, HasMips64]; + list ASEPredicate = [HasMSA, HasMips64]; } class ASE_MT { - list InsnPredicates = [HasMT]; + list ASEPredicate = [HasMT]; } // Class used for separating microMIPSr6 and microMIPS (r3) instruction. @@ -454,7 +451,7 @@ class ISA_MICROMIPS_NOT_32R6 : PredicateControl { } class ASE_NOT_DSP { - list InsnPredicates = [NotDSP]; + list ASEPredicate = [NotDSP]; } class MADD4 { -- 2.7.4