From 1ed49fd384c82354856be64385b4197a8474710b Mon Sep 17 00:00:00 2001 From: Vasileios Kalintiris Date: Wed, 7 Sep 2016 10:01:18 +0000 Subject: [PATCH] [mips] Disable the TImode shift libcalls for 32-bit targets. Summary: The o32 ABI doesn't not support the TImode helpers. For the time being, disable just the shift libcalls as they break recursive builds on MIPS. Reviewers: sdardis Subscribers: llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D24259 llvm-svn: 280798 --- llvm/lib/Target/Mips/MipsISelLowering.cpp | 7 +++++++ llvm/test/CodeGen/Mips/llvm-ir/ashr.ll | 6 +++--- llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 6 +++--- llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 6 +++--- 4 files changed, 16 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index c12668b..417eb8d 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -426,6 +426,13 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, setTargetDAGCombine(ISD::ADD); setTargetDAGCombine(ISD::AssertZext); + if (ABI.IsO32()) { + // These libcalls are not available in 32-bit. + setLibcallName(RTLIB::SHL_I128, nullptr); + setLibcallName(RTLIB::SRL_I128, nullptr); + setLibcallName(RTLIB::SRA_I128, nullptr); + } + setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); // The arguments on the stack are defined in terms of 4-byte slots on O32 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll index 0621ecd..c8d0e76 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -162,7 +162,9 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: ashr_i128: - ; GP32: lw $25, %call16(__ashrti3)($gp) + ; o32 shouldn't use TImode helpers. + ; GP32-NOT: lw $25, %call16(__ashrti3)($gp) + ; MM-NOT: lw $25, %call16(__ashrti3)($2) ; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: dsrav $[[T1:[0-9]+]], $4, $7 @@ -213,8 +215,6 @@ entry: ; 64R6: jr $ra ; 64R6: or $3, $[[T13]], $[[T12]] - ; MM: lw $25, %call16(__ashrti3)($2) - %r = ashr i128 %a, %b ret i128 %r } diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll index b8d908a..09617ed 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -153,7 +153,9 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: lshr_i128: - ; GP32: lw $25, %call16(__lshrti3)($gp) + ; o32 shouldn't use TImode helpers. + ; GP32-NOT: lw $25, %call16(__lshrti3)($gp) + ; MM-NOT: lw $25, %call16(__lshrti3)($2) ; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: dsrlv $[[T1:[0-9]+]], $4, $7 @@ -200,8 +202,6 @@ entry: ; 64R6: jr $ra ; 64R6: seleqz $2, $[[T9]], $[[T7]] - ; MM: lw $25, %call16(__lshrti3)($2) - %r = lshr i128 %a, %b ret i128 %r } diff --git a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll index 6517a0f..ce3b913 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll @@ -169,7 +169,9 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: shl_i128: - ; GP32: lw $25, %call16(__ashlti3)($gp) + ; o32 shouldn't use TImode helpers. + ; GP32-NOT: lw $25, %call16(__ashlti3)($gp) + ; MM-NOT: lw $25, %call16(__ashlti3)($2) ; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: dsllv $[[T1:[0-9]+]], $5, $7 @@ -216,8 +218,6 @@ entry: ; 64R6: jr $ra ; 64R6: seleqz $3, $[[T9]], $[[T7]] - ; MM: lw $25, %call16(__ashlti3)($2) - %r = shl i128 %a, %b ret i128 %r } -- 2.7.4