From 1e43395b55bb57deaabbdc7a704aae135c1c6eee Mon Sep 17 00:00:00 2001 From: Evoke Zhang Date: Thu, 30 May 2019 16:45:03 +0800 Subject: [PATCH] tvafe: optimize display for line frequency scan range [1/1] PD#TV-5770 Problem: atv line freq offset -220hz display abnormal Solution: optimize acd_64/66 reg setting Verify: x301 Change-Id: I41fec1513a735ea6cd5975b18f01e8f80afe4f51 Signed-off-by: Evoke Zhang --- drivers/amlogic/media/vin/tvin/tvafe/tvafe_cvd.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_cvd.c b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_cvd.c index c3f7392..c0da0ca 100644 --- a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_cvd.c +++ b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_cvd.c @@ -2227,13 +2227,10 @@ inline void tvafe_cvd2_adj_hs(struct tvafe_cvd2_s *cvd2, unsigned int diff, hcnt64_ave, i; unsigned int hcnt64_standard = 0; - if (tvafe_cpu_type() >= CPU_TYPE_GXTVBB) { - if (cvd2->config_fmt == TVIN_SIG_FMT_CVBS_PAL_I) - hcnt64_standard = 0x31380; - else if (cvd2->config_fmt == TVIN_SIG_FMT_CVBS_NTSC_M) - hcnt64_standard = 0x30e0e; - } else - hcnt64_standard = 0x17a00; + if (cvd2->config_fmt == TVIN_SIG_FMT_CVBS_PAL_I) + hcnt64_standard = 0x31380; + else if (cvd2->config_fmt == TVIN_SIG_FMT_CVBS_NTSC_M) + hcnt64_standard = 0x30e0e; if ((cvd_isr_en & 0x1000) == 0) return; @@ -2296,11 +2293,20 @@ inline void tvafe_cvd2_adj_hs(struct tvafe_cvd2_s *cvd2, W_APB_BIT(CVD2_ACTIVE_VIDEO_HSTART, temp, HACTIVE_START_BIT, HACTIVE_START_WID); /* 0x12d */ + if (tvafe_cpu_type() == CPU_TYPE_TL1 || + tvafe_cpu_type() == CPU_TYPE_TM2) { + temp = 0x20 * cvd2->info.hs_adj_level; + delta = temp / 4; + } temp = delta << 16; temp = temp | delta; temp = acd_h_back - temp; W_APB_REG(ACD_REG_2D, temp); acd_h = temp; + + /*@20190530 vlsi adjust colorbar display*/ + W_APB_REG(ACD_REG_66, 0x80000f10); + W_APB_REG(ACD_REG_64, 0xff00); } else { /*0x128*/ temp = (acd_128_l1 - acd_128) * @@ -2321,6 +2327,9 @@ inline void tvafe_cvd2_adj_hs(struct tvafe_cvd2_s *cvd2, temp = acd_h_back + temp; W_APB_REG(ACD_REG_2D, temp); acd_h = temp; + + /*@20190530 vlsi adjust colorbar display*/ + W_APB_REG(ACD_REG_66, 0x0); } } else { if (R_APB_REG(CVD2_YC_SEPARATION_CONTROL) != 0x12) -- 2.7.4