From 1e3c179519b91953ad127ab558b0b9d64ead3ee4 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Fri, 30 Sep 2022 08:30:52 -0700 Subject: [PATCH] [RISCV] Address post commit review comments from D134881 --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 2282707..67e1102 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -9025,7 +9025,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, // (select (and (x , 0x1) != 0), (z ^ y) ), y -> (-(and (x , 0x1)) & z ) ^ y // (select (and (x , 0x1) == 0), y, (z | y) ) -> (-(and (x , 0x1)) & z ) | y // (select (and (x , 0x1) != 0), (z | y) ), y -> (-(and (x , 0x1)) & z ) | y - if (isNullConstant(RHS) && (CCVal == ISD::SETEQ || CCVal == ISD::SETNE) && + if (isNullConstant(RHS) && ISD::isIntEqualitySetCC(CCVal) && LHS.getOpcode() == ISD::AND && isOneConstant(LHS.getOperand(1))) { unsigned Opcode; SDValue Src1, Src2; @@ -9057,7 +9057,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, if (isOrXorPattern()) { SDValue Neg; - unsigned int CmpSz = LHS.getSimpleValueType().getSizeInBits(); + unsigned CmpSz = LHS.getSimpleValueType().getSizeInBits(); // We need mask of all zeros or ones with same size of the other // operands. if (CmpSz > VT.getSizeInBits()) -- 2.7.4