From 1e0ddf1e672ce1d44d49359042383a342eb18e4c Mon Sep 17 00:00:00 2001
From: "Kim, HeungJun" <riverful.kim@samsung.com>
Date: Fri, 22 May 2009 18:08:36 +0900
Subject: [PATCH] [S5PC100] modifiled lowlevel_init.S using s5pc1xx.h

---
 board/samsung/tt/lowlevel_init.S | 232 +++++++++++++++------------------------
 include/configs/s5pc100_tt.h     |   2 +-
 include/s5pc1xx.h                |  32 ++++--
 3 files changed, 110 insertions(+), 156 deletions(-)

diff --git a/board/samsung/tt/lowlevel_init.S b/board/samsung/tt/lowlevel_init.S
index d68b7da..7521224 100644
--- a/board/samsung/tt/lowlevel_init.S
+++ b/board/samsung/tt/lowlevel_init.S
@@ -34,16 +34,16 @@
 #include <config.h>
 #include <version.h>
 
-#include <s5pc100.h>
+#include <s5pc1xx.h>
 
 #ifdef CONFIG_SERIAL0
-#define ELFIN_UART_CONSOLE_BASE	ELFIN_UARTx_OFFSET(0)
+#define UART_CONSOLE_BASE	UARTx_OFFSET(0)
 #elif defined(CONFIG_SERIAL1)
-#define ELFIN_UART_CONSOLE_BASE ELFIN_UARTx_OFFSET(1)
+#define UART_CONSOLE_BASE	UARTx_OFFSET(1)
 #elif defined(CONFIG_SERIAL2)
-#define ELFIN_UART_CONSOLE_BASE ELFIN_UARTx_OFFSET(2)
+#define UART_CONSOLE_BASE	UARTx_OFFSET(2)
 #else
-#define ELFIN_UART_CONSOLE_BASE ELFIN_UARTx_OFFSET(3)
+#define UART_CONSOLE_BASE	UARTx_OFFSET(3)
 #endif
 
 _TEXT_BASE:
@@ -54,19 +54,20 @@ lowlevel_init:
 	mov	r12, lr
 
 	/* Disable Watchdog */
-	ldr	r0, =0xEA200000		@0xEA200000
+	ldr	r0, =S5P_WATCHDOG_BASE(0x0)		@0xEA200000
 	orr	r0, r0, #0x0
 	mov	r1, #0
 	str	r1, [r0]
 
 	/* setting SRAM */
-	ldr r0, =0xe7000000
+	ldr r0, =S5P_SROMC_BASE(0x0)
 	ldr r1, =0x9
 	str r1, [r0]
 
 	/* External interrupt pending clear : GPIO_BASE = 0xE0300000 */
-	ldr	r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET)	/*EINTPEND*/
+	ldr	r0, =S5P_GPIO_INT_PEND_REG(0x0)	/*EINTPEND*/
 	add r4, r0, #0x54
+
 interrupt_pending_loop:
 	ldr	r1, [r0]
 	str	r1, [r0]
@@ -77,28 +78,28 @@ interrupt_pending_loop:
 	bcc interrupt_pending_loop
 
 	/* s5pc100 has 3 groups of interrupt sources */
-	ldr	r0, =ELFIN_VIC0_BASE_ADDR	@0xE4000000
-	ldr	r1, =ELFIN_VIC1_BASE_ADDR	@0xE4100000
-	ldr	r2, =ELFIN_VIC2_BASE_ADDR	@0xE4200000
+	ldr	r0, =S5P_VIC0_BASE(0x0)		@0xE4000000
+	ldr	r1, =S5P_VIC1_BASE(0x0)		@0xE4000000
+	ldr	r2, =S5P_VIC2_BASE(0x0)		@0xE4000000
 
 	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
 	mvn	r3, #0x0
-	str	r3, [r0, #oINTMSK]
-	str	r3, [r1, #oINTMSK]
-	str	r3, [r2, #oINTMSK]
+	str	r3, [r0, #VIC_INTENCLEAR_OFFSET]
+	str	r3, [r1, #VIC_INTENCLEAR_OFFSET]
+	str	r3, [r2, #VIC_INTENCLEAR_OFFSET]
 
 #ifndef CONFIG_ONENAND_IPL
 	/* Set all interrupts as IRQ */
 	mov	r3, #0x0
-	str	r3, [r0, #oINTMOD]
-	str	r3, [r1, #oINTMOD]
-	str	r3, [r2, #oINTMOD]
+	str	r3, [r0, #VIC_INTSELECT_OFFSET]
+	str	r3, [r1, #VIC_INTSELECT_OFFSET]
+	str	r3, [r2, #VIC_INTSELECT_OFFSET]
 
 	/* Pending Interrupt Clear */
 	mov	r3, #0x0
-	str	r3, [r0, #oVECTADDR]
-	str	r3, [r1, #oVECTADDR]
-	str	r3, [r2, #oVECTADDR]
+	str	r3, [r0, #VIC_INTADDRESS_OFFSET]
+	str	r3, [r1, #VIC_INTADDRESS_OFFSET]
+	str	r3, [r2, #VIC_INTADDRESS_OFFSET]
 #endif
 
 	/* init system clock */
@@ -115,15 +116,14 @@ interrupt_pending_loop:
 #endif
 
 	/* Memory subsystem address 0xe0200200 */
-	ldr	r0, =ELFIN_MEM_SYS_CFG
+	ldr	r0, =S5P_MEM_SYS_CFG
 
-	/* */
 	mov	r1, #0
 	str	r1, [r0]
 
 #	bl	mem_ctrl_asm_init
 
-/* Wakeup support. Don't know if it's going to be used, untested. */
+	/* Wakeup support. Don't know if it's going to be used, untested. */
 #	ldr	r0, =(OTHERS_REGISTER_BASE)
 #	ldr	r1, [r0]
 #	bic	r1, r1, #0xfffffff7
@@ -131,16 +131,16 @@ interrupt_pending_loop:
 #	beq	wakeup_reset
 
 	/* DRAM I/O Drive-Strength */
-	ldr	r0, =ELFIN_GPIO_BASE
+	ldr	r0, =S5P_MP_0_BASE(0x0)
 	ldr	r1, =0x5555
-	str	r1, [r0, #MP_0DRV_OFFSET]
-	str	r1, [r0, #MP_1DRV_OFFSET]
-	str	r1, [r0, #MP_2DRV_OFFSET]
-	str	r1, [r0, #MP_3DRV_OFFSET]
-	str	r1, [r0, #MP_4DRV_OFFSET]
-	str	r1, [r0, #MP_5DRV_OFFSET]
-	str	r1, [r0, #MP_6DRV_OFFSET]
-	str	r1, [r0, #MP_7DRV_OFFSET]
+	str	r1, [r0, #S5P_MP_0_OFFSET]
+	str	r1, [r0, #S5P_MP_1_OFFSET]
+	str	r1, [r0, #S5P_MP_2_OFFSET]
+	str	r1, [r0, #S5P_MP_3_OFFSET]
+	str	r1, [r0, #S5P_MP_4_OFFSET]
+	str	r1, [r0, #S5P_MP_5_OFFSET]
+	str	r1, [r0, #S5P_MP_6_OFFSET]
+	str	r1, [r0, #S5P_MP_7_OFFSET]
 1:
 	mov	lr, r12
 	mov	pc, lr
@@ -148,14 +148,16 @@ interrupt_pending_loop:
 wakeup_reset:
 
 	/* Clear wakeup status register */
-	ldr	r0, =(CLOCK_REGISTER_BASE + WAKEUP_STAT_OFFSET)
+	ldr	r0, =S5P_WAKEUP_STAT
 	ldr	r1, [r0]
 	str	r1, [r0]
 
 	/* Load return address and jump to kernel */
-	ldr	r0, =(CLOCK_REGISTER_BASE + INF_REG0_OFFSET)
+	ldr	r0, =S5P_INFORM0
+
 	/* r1 = physical address of s3c6400_cpu_resume function */
 	ldr	r1, [r0]
+
 	/* Jump to kernel (sleep-s3c6400.S) */
 	mov	pc, r1
 	nop
@@ -165,31 +167,6 @@ wakeup_reset:
  * void system_clock_init(void)
  */
 system_clock_init:
-	ldr	r0, =CLOCK_REGISTER_BASE	/* 0xE0100000 */
-
-#ifdef CONFIG_SYNC_MODE
-	ldr	r1, [r0, #OTHERS_OFFSET]
-	mov	r2, #0x40
-	orr	r1, r1, r2
-	str	r1, [r0, #OTHERS_OFFSET]
-
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	ldr	r2, =0x80
-	orr	r1, r1, r2
-	str	r1, [r0, #OTHERS_OFFSET]
-
-check_syncack:
-	ldr	r1, [r0, #OTHERS_OFFSET]
-	ldr	r2, =0xf00
-	and	r1, r1, r2
-	cmp	r1, #0xf00
-	bne	check_syncack
-#else	/* ASYNC Mode */
 	nop
 	nop
 	nop
@@ -197,121 +174,85 @@ check_syncack:
 	nop
 
 	/*
-	 * This was unconditional in original Samsung sources, but it doesn't
-	 * seem to make much sense on S3C6400.
+	 * Fout = MDIV * Fin / (PDIV * (2 ^ SDIV))
 	 */
-#ifndef CONFIG_S5PC100
-	ldr	r1, [r0, #OTHERS_OFFSET]
-	bic	r1, r1, #0xC0
-	orr	r1, r1, #0x40
-	str	r1, [r0, #OTHERS_OFFSET]
-
-wait_for_async:
-	ldr	r1, [r0, #OTHERS_OFFSET]
-	and	r1, r1, #0xf00
-	cmp	r1, #0x0
-	bne	wait_for_async
-#endif
 
-	/* clock initialization */
-	ldr r0, =0xe0100304
-	ldr r1, =0x10000
+	/* Clock Divider Set */
+	ldr r0, =S5P_CLK_DIV1
+	ldr r1, =0x11110	@ MPLL, MPLL2, D1_BUS, PCLKD1 ratio set 1 -> 2
 	str r1, [r0]
 
-	ldr r1, =0x11000
-	str r1, [r0]
-
-	ldr r1, =0x11100
-	str r1, [r0]
-
-	ldr r1, =0x11110
-	str r1, [r0]
-
-	ldr r1, =0x11110
-	str r1, [r0]
-
-	ldr r0, =0xe0100308
-	ldr r1, =0x1
+	ldr r0, =S5P_CLK_DIV2
+	ldr r1, =0x1		@ UART ratio set 1 -> 2
 	str r1, [r0]
 
 	/* APLL Enable */
-	ldr r0, =0xe1000000
-	ldr r1, =0xe10
+	ldr r0, =S5P_APLL_LOCK	
+	ldr r1, =0xe10		@ Locktime : 0xe10 = 3600
 	str r1, [r0]
 
-	ldr r0, =0xe0100100
-	ldr r1, =0x81bc0400
+	ldr r0, =S5P_APLL_CON
+	ldr r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
 	str r1, [r0]
 
-ldr r3, =loop1
+	ldr r3, =loop1
 	b dummy_loop
+
 loop1:
 	/* MPLL Enable */
-	ldr r0, =0xe0100004
-	ldr r1, =0xe10
+	ldr r0, =S5P_MPLL_LOCK
+	ldr r1, =0xe10			@ Locktime : 0x310 = 3600
 	str r1, [r0]
 
-	ldr r0, =0xe0100104
-	ldr r1, =0x80590201
+	ldr r0, =S5P_MPLL_CON
+	ldr r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
 	str r1, [r0]
 
-ldr r3, =loop2
+	ldr r3, =loop2
 	b dummy_loop
+
 loop2:
 	/* EPLL Enable */
-	ldr r0, =0xe0100008
-	ldr r1, =0xe10
+	ldr r0, =S5P_EPLL_LOCK
+	ldr r1, =0xe10			@ Locktime : 0x310 = 3600
 	str r1, [r0]
 
-	ldr r0, =0xe0100108
-	ldr r1, =0x80870303
+	ldr r0, =S5P_EPLL_CON
+	ldr r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
 	str r1, [r0]
 
-ldr r3, =loop3
+	ldr r3, =loop3
 	b dummy_loop
+
 loop3:
 	/* HPLL Enable */
-	ldr r0, =0xe0100200
+	ldr r0, =S5P_CLK_SRC0
 	ldr r1, =0x0
 	str r1, [r0]
 
-	ldr r0, =0xe010000c
+	ldr r0, =S5P_HPLL_LOCK
 	ldr r1, =0xe10
 	str r1, [r0]
 
-	ldr r0, =0xe010010c
-	ldr r1, =0x80600603
+	ldr r0, =S5P_HPLL_CON
+	ldr r1, =0x80600603		@ SDIV 3, PDIV 6, MDIV 96 (54MHZ)
 	str r1, [r0]
 
-ldr r3, =loop4
+	ldr r3, =loop4
 	b dummy_loop
+
 loop4:
 	/* Set Source Clock */
-	ldr r0, =0xe0100200
-	ldr r1, =0x0
-	str r1, [r0]
-
-	ldr r1, =0x1
-	str r1, [r0]
-
-	ldr r1, =0x11
-	str r1, [r0]
-
-	ldr r1, =0x111
-	str r1, [r0]
-
-	ldr r1, =0x1111
-	str r1, [r0]
-
-	ldr r0, =0xe0100204
-	ldr r1, =0x1
+	ldr r0, =S5P_CLK_SRC0
+	ldr r1, =0x1111			@ A, M, E, HPLL Muxing
 	str r1, [r0]
 
-	ldr r1, =0x1000001
+	ldr r0, =S5P_CLK_SRC1
+	ldr r1, =0x1000001		@ Uart Clock & CLK48M Muxing
 	str r1, [r0]
 
-	ldr r0, =0xe0100400
-	ldr r1, =0x9000
+	ldr r0, =S5P_CLK_OUT
+	ldr r1, =0x9000			@ ARMCLK/4
 	str r1, [r0]
 
 	b setting_end
@@ -324,8 +265,6 @@ dummy_loop:
 	mov pc, r3
 
 setting_end:
-#endif
-
 #	/* wait at least 200us to stablize all clock */
 #	mov	r2, #0x10000
 #1:	subs	r2, r2, #1
@@ -333,14 +272,14 @@ setting_end:
 
 	/* Synchronization for VIC port */
 #if defined(CONFIG_SYNC_MODE)
-	ldr	r1, [r0, #OTHERS_OFFSET]
+	ldr	r1, [r0]
 	orr	r1, r1, #0x20
-	str	r1, [r0, #OTHERS_OFFSET]
+	str	r1, [r0]
 #elif !defined(CONFIG_S5PC100)
 	/* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
-	ldr	r1, [r0, #OTHERS_OFFSET]
+	ldr	r1, [r0]
 	bic	r1, r1, #0x20
-	str	r1, [r0, #OTHERS_OFFSET]
+	str	r1, [r0]
 #endif
 	mov	pc, lr
 
@@ -349,24 +288,27 @@ setting_end:
  */
 uart_asm_init:
 	/* set GPIO to enable UART */
-	ldr	r0, =ELFIN_GPIO_BASE
+	ldr	r0, =S5P_GPIO_A1_CON
 	ldr	r1, =0x22
-	str	r1, [r0, #GPA1CON_OFFSET]
+	str	r1, [r0]
 
 	/* uart_sel GPK0[5] */
-	ldr	r1, [r0, #GPK0CON_OFFSET]
+	ldr r0, =S5P_GPIO_K0_CON
+	ldr	r1, [r0]
 	bic	r1, r1, #0xf00000
 	orr	r1, r1, #0x100000
-	str   	r1, [r0, #GPK0CON_OFFSET]
+	str   	r1, [r0]
 
-	ldr	r1, [r0, #GPK0PUD_OFFSET]
+	ldr r0, =S5P_GPIO_K0_PULL
+	ldr	r1, [r0]
 	bic	r1, r1, #0xc00
 	orr	r1, r1, #0x800
-	str	r1, [r0, #GPK0PUD_OFFSET]
+	str	r1, [r0]
 
-	ldr	r1, [r0, #GPK0DAT_OFFSET]
+	ldr r0, =S5P_GPIO_K0_DAT
+	ldr	r1, [r0]
 	orr	r1, r1, #0x20
-	str	r1, [r0, #GPK0DAT_OFFSET]
+	str	r1, [r0]
 
 	mov	pc, lr
 
diff --git a/include/configs/s5pc100_tt.h b/include/configs/s5pc100_tt.h
index 1cd53a8..1639ee8 100644
--- a/include/configs/s5pc100_tt.h
+++ b/include/configs/s5pc100_tt.h
@@ -48,7 +48,7 @@
 
 #define CONFIG_SYS_SDRAM_BASE	0x20000000
 
-/* input clock of PLL: SMDK6400 has 12MHz input clock */
+/* input clock of PLL: TickerTape has 12MHz input clock */
 #define CONFIG_SYS_CLK_FREQ	12000000
 
 #if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
diff --git a/include/s5pc1xx.h b/include/s5pc1xx.h
index 139c5ab..8364ed8 100644
--- a/include/s5pc1xx.h
+++ b/include/s5pc1xx.h
@@ -66,7 +66,7 @@
 #define S5P_CLK_DIV1	S5P_CLKREG(0x304)
 #define S5P_CLK_DIV2	S5P_CLKREG(0x308)
 #define S5P_CLK_DIV3	S5P_CLKREG(0x30c)
-#define S5P_CLK_DIV4	S5P_CLKREG(0x300)
+#define S5P_CLK_DIV4	S5P_CLKREG(0x310)
 
 #define S5P_CLK_OUT		S5P_CLKREG(0x400)
 
@@ -523,14 +523,23 @@
 #define S5P_GPIO_L4_PDNPUL			S5P_GPIO_L4_BASE(PDNPULL_OFFSET) 
 
 /* GPIO MP Bank */ 
-#define S5P_MP_0_BASE(x)			(S5P_MP_REG(0x0) + (x))
-#define S5P_MP_1_BASE(x)			(S5P_MP_REG(0x20) + (x))
-#define S5P_MP_2_BASE(x)			(S5P_MP_REG(0x40) + (x))
-#define S5P_MP_3_BASE(x)			(S5P_MP_REG(0x60) + (x))
-#define S5P_MP_4_BASE(x)			(S5P_MP_REG(0x80) + (x))
-#define S5P_MP_5_BASE(x)			(S5P_MP_REG(0xa0) + (x))
-#define S5P_MP_6_BASE(x)			(S5P_MP_REG(0xc0) + (x))
-#define S5P_MP_7_BASE(x)			(S5P_MP_REG(0xe0) + (x))
+#define S5P_MP_0_OFFSET				0x0
+#define S5P_MP_1_OFFSET				0x20
+#define S5P_MP_2_OFFSET				0x40
+#define S5P_MP_3_OFFSET				0x60
+#define S5P_MP_4_OFFSET				0x80
+#define S5P_MP_5_OFFSET				0xa0
+#define S5P_MP_6_OFFSET				0xc0
+#define S5P_MP_7_OFFSET				0xe0
+
+#define S5P_MP_0_BASE(x)			(S5P_MP_REG(S5P_MP_0_OFFSET) + (x))
+#define S5P_MP_1_BASE(x)			(S5P_MP_REG(S5P_MP_1_OFFSET) + (x))
+#define S5P_MP_2_BASE(x)			(S5P_MP_REG(S5P_MP_2_OFFSET) + (x))
+#define S5P_MP_3_BASE(x)			(S5P_MP_REG(S5P_MP_3_OFFSET) + (x))
+#define S5P_MP_4_BASE(x)			(S5P_MP_REG(S5P_MP_4_OFFSET) + (x))
+#define S5P_MP_5_BASE(x)			(S5P_MP_REG(S5P_MP_5_OFFSET) + (x))
+#define S5P_MP_6_BASE(x)			(S5P_MP_REG(S5P_MP_6_OFFSET) + (x))
+#define S5P_MP_7_BASE(x)			(S5P_MP_REG(S5P_MP_7_OFFSET) + (x))
 
 #define S5P_MP_0PULL				S5P_MP_0_BASE(PULL_OFFSET)
 #define S5P_MP_0DRV				S5P_MP_0_BASE(DRV_OFFSET)
@@ -789,6 +798,7 @@
 #define VIC_PROTECTION_OFFSET		0x20	/* Protection Enable Register */
 #define VIC_SWPRIORITYMASK_OFFSET	0x24	/* Software Priority Mask Register */
 #define VIC_PRIORITYDAISY_OFFSET	0x28	/* Vector Priority Register for Daisy Chain */
+#define VIC_INTADDRESS_OFFSET		0xf00	/* Vector Priority Register for Daisy Chain */
 
 #define S5P_VIC0IRQSTATUS		S5P_VIC0_BASE(VIC_IRQSTATUS_OFFSET)
 #define S5P_VIC0FIQSTATUS		S5P_VIC0_BASE(VIC_FIQSTATUS_OFFSET)
@@ -1426,7 +1436,7 @@
 #define S5P_PWM_TINT_CSTAT	S5P_PWMTIMER_BASE(PWM_TINT_CSTAT_OFFSET)
 
 #define S5P_TIMER_BASE			S5P_PWMTIMER_BASE(0x0)
-#define S5P_PWMTIMER_BASE_Rget_PCLKEG	__REG(S5P_PWMTIMER_BASE(0x0))
+#define S5P_PWMTIMER_BASE_REG	__REG(S5P_PWMTIMER_BASE(0x0))
 #define S5P_PWM_TCFG0_REG		__REG(S5P_PWM_TCFG0)
 #define S5P_PWM_TCFG1_REG		__REG(S5P_PWM_TCFG1_REG)
 #define S5P_PWM_TCON_REG		__REG(S5P_PWM_TCON_REG)
@@ -1570,11 +1580,13 @@
 #define fTCFG0_PRE1		Fld(8, 8)  /* prescaler value for time 2,3,4 */
 #define fTCFG0_PRE0		Fld(8, 0)  /* prescaler value for time 0,1 */
 #define fTCFG1_MUX4		Fld(4, 16)
+
 /* bits */
 #define TCFG0_DZONE(x)		FInsrt((x), fTCFG0_DZONE)
 #define TCFG0_PRE1(x)		FInsrt((x), fTCFG0_PRE1)
 #define TCFG0_PRE0(x)		FInsrt((x), fTCFG0_PRE0)
 #define TCFG1_MUX4(x)		FInsrt((x), fTCFG1_MUX4)
+
 #define TCON_4_AUTO		(1 << 22)  /* auto reload on/off for Timer 4 */
 #define TCON_4_UPDATE		(1 << 21)  /* manual Update TCNTB4 */
 #define TCON_4_ONOFF		(1 << 20)  /* 0: Stop, 1: start Timer 4 */
-- 
2.7.4