From 1de7e0d9238a439566daa0d7f050e69a7be5e496 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Wed, 28 Jan 2015 19:39:09 +0000 Subject: [PATCH] [Hexagon] Updating many V4 intrinsic patterns. Adding missing instruction and deleting unused classes. llvm-svn: 227353 --- llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 1 + llvm/lib/Target/Hexagon/HexagonIntrinsics.td | 4 + llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td | 328 ++++++------------------ llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt | 2 + 4 files changed, 83 insertions(+), 252 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 80bf5ba..727bc2c 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -3289,6 +3289,7 @@ let Defs = [USR_OVF], isCodeGenOnly = 0 in { def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>; def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>; def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>; + def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>; } let Itinerary = S_2op_tc_2_SLOT23, isCodeGenOnly = 0 in { diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td index 229d993..b1dcf80 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td @@ -97,6 +97,10 @@ class T_PII_pat : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu), (MI DoubleRegs:$Rs, imm:$It, imm:$Iu)>; +class T_PPP_pat + : Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru), + (MI DoubleRegs:$Rs, DoubleRegs:$Rt, DoubleRegs:$Ru)>; + class T_PPR_pat : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru), (MI DoubleRegs:$Rs, DoubleRegs:$Rt, I32:$Ru)>; diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td index 95bd397..b51adac 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td @@ -42,6 +42,10 @@ def: T_RR_pat; def: T_RR_pat; def: T_RI_pat; +def : T_RP_pat ; + +def : T_PR_pat; + def : Pat <(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; @@ -54,6 +58,9 @@ def : T_RRI_pat ; def : T_RRR_pat ; def : T_RRR_pat ; +def : T_PP_pat; +def : T_PP_pat; + // Extract bitfield def : T_PP_pat ; def : T_RP_pat ; @@ -63,6 +70,9 @@ def : T_RII_pat ; // Shift an immediate left by register amount def : T_IR_pat; +// Logical xor with xor accumulation +def : T_PPP_pat; + // Shift and add/sub/and/or def : T_IRI_pat ; def : T_IRI_pat ; @@ -86,24 +96,75 @@ def: T_RI_pat; def: T_PI_pat; def: T_P_pat ; -// -// ALU 32 types. -// +/******************************************************************** +* ALU32/ALU * +*********************************************************************/ + +// ALU32 / ALU / Logical Operations. +def: T_RR_pat; +def: T_RR_pat; + +/******************************************************************** +* ALU32/PERM * +*********************************************************************/ + +// Combine Words Into Doublewords. +def: T_RI_pat; +def: T_IR_pat; + +/******************************************************************** +* ALU32/PRED * +*********************************************************************/ -class si_ALU32_sisi_not - : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), - !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")), - [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; +def: T_RR_pat; +def: T_RR_pat; -class di_ALU32_s8si - : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1, IntRegs:$src2), - !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")), - [(set DoubleRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>; +def: T_RI_pat; +def: T_RI_pat; -class di_ALU32_sis8 - : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2), - !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")), - [(set DoubleRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; +/******************************************************************** +* XTYPE/ALU * +*********************************************************************/ + +// Add And Accumulate. + +def : T_RRI_pat ; +def : T_RIR_pat ; + + +// XTYPE / ALU / Logical-logical Words. +def : T_RRR_pat ; +def : T_RRR_pat ; +def : T_RRR_pat ; +def : T_RRR_pat ; +def : T_RRR_pat ; +def : T_RRR_pat ; +def : T_RRR_pat ; +def : T_RRR_pat ; +def : T_RRR_pat ; +def : T_RRR_pat ; +def : T_RRR_pat ; + +def : T_RRI_pat ; +def : T_RRI_pat ; +def : T_RRI_pat ; + +// Modulo wrap. +def : T_RR_pat ; + +// Arithmetic/Convergent round +// Rd=[cround|round](Rs,Rt)[:sat] +// Rd=[cround|round](Rs,#u5)[:sat] +def : T_RI_pat ; +def : T_RR_pat ; + +def : T_RI_pat ; +def : T_RR_pat ; + +def : T_RI_pat ; +def : T_RR_pat ; + +def : T_P_pat ; class qi_neg_ALU32_sisi : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), @@ -120,22 +181,6 @@ class qi_neg_ALU32_siu9 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")), [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; -class si_neg_ALU32_sisi - : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), - !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")), - [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; - -class si_neg_ALU32_sis8 - : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2), - !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")), - [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; - -class si_ALU32_sis8 - : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2), - !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")), - [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; - - // // SInst Classes. // @@ -176,112 +221,6 @@ class qi_SInst_qi_orqiqi [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, IntRegs:$src3))]>; -class si_SInst_si_addsis6 - : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3), - !strconcat("$dst = ", !strconcat(opc , - "($src1, add($src2, #$src3)")), - [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, - imm:$src3))]>; - -class si_SInst_si_subs6si - : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3), - !strconcat("$dst = ", !strconcat(opc , - "($src1, sub(#$src2, $src3)")), - [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, - IntRegs:$src3))]>; - -class di_ALU64_didi_neg - : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2), - !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")), - [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>; - -class di_MInst_dididi_xacc - : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1, - DoubleRegs:$src2), - !strconcat("$dst ^= ", !strconcat(opc , "($src1, $src2)")), - [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1, - DoubleRegs:$src2))], - "$dst2 = $dst">; - -class si_MInst_sisisi_and - : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, - IntRegs:$src3), - !strconcat("$dst &= ", !strconcat(opc , "($src2, $src3)")), - [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, - IntRegs:$src3))]>; - -class si_MInst_sisisi_andn - : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, - IntRegs:$src3), - !strconcat("$dst &= ", !strconcat(opc , "($src2, ~$src3)")), - [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, - IntRegs:$src3))]>; - -class si_SInst_sisis10_andi - : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s10Imm:$src3), - !strconcat("$dst = ", !strconcat(opc , - "($src1, and($src2, #$src3))")), - [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, - imm:$src3))]>; - -class si_MInst_sisisi_xor - : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, - IntRegs:$src3), - !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")), - [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, - IntRegs:$src3))]>; - -class si_MInst_sisisi_xorn - : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, - IntRegs:$src3), - !strconcat("$dst ^= ", !strconcat(opc , "($src2, ~$src3)")), - [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, - IntRegs:$src3))]>; - -class si_SInst_sisis10_or - : SInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, s10Imm:$src3), - !strconcat("$dst |= ", !strconcat(opc , "($src2, #$src3)")), - [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, - imm:$src3))]>; - -class si_MInst_sisisi_or - : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, - IntRegs:$src3), - !strconcat("$dst |= ", !strconcat(opc , "($src2, $src3)")), - [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, - IntRegs:$src3))]>; - -class si_MInst_sisisi_orn - : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, - IntRegs:$src3), - !strconcat("$dst |= ", !strconcat(opc , "($src2, ~$src3)")), - [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, - IntRegs:$src3))]>; - -class si_SInst_siu5_sat - : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2), - !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):sat")), - [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; - - -/******************************************************************** -* ALU32/ALU * -*********************************************************************/ - -// ALU32 / ALU / Logical Operations. -def Hexagon_A4_orn : si_ALU32_sisi_not <"or", int_hexagon_A4_orn>; -def Hexagon_A4_andn : si_ALU32_sisi_not <"and", int_hexagon_A4_andn>; - - -/******************************************************************** -* ALU32/PERM * -*********************************************************************/ - -// ALU32 / PERM / Combine Words Into Doublewords. -def Hexagon_A4_combineir : di_ALU32_s8si <"combine", int_hexagon_A4_combineir>; -def Hexagon_A4_combineri : di_ALU32_sis8 <"combine", int_hexagon_A4_combineri>; - - /******************************************************************** * ALU32/PRED * *********************************************************************/ @@ -298,12 +237,6 @@ def: T_RI_pat; def: T_RI_pat; def: T_RI_pat; -// ALU32 / PRED / cmpare To General Register. -def Hexagon_A4_rcmpneq : si_neg_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpneq>; -def Hexagon_A4_rcmpneqi: si_neg_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpneqi>; -def Hexagon_A4_rcmpeq : si_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpeq>; -def Hexagon_A4_rcmpeqi : si_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpeqi>; - /******************************************************************** * CR * @@ -332,112 +265,3 @@ def Hexagon_C4_or_orn: qi_SInst_qi_orqiqi_neg <"or", int_hexagon_C4_or_orn>; def Hexagon_C4_or_or: qi_SInst_qi_orqiqi <"or", int_hexagon_C4_or_or>; - - -/******************************************************************** -* XTYPE/ALU * -*********************************************************************/ - -// XTYPE / ALU / Add And Accumulate. -def Hexagon_S4_addaddi: - si_SInst_si_addsis6 <"add", int_hexagon_S4_addaddi>; -def Hexagon_S4_subaddi: - si_SInst_si_subs6si <"add", int_hexagon_S4_subaddi>; - -// XTYPE / ALU / Logical Doublewords. -def Hexagon_S4_andnp: - di_ALU64_didi_neg <"and", int_hexagon_A4_andnp>; -def Hexagon_S4_ornp: - di_ALU64_didi_neg <"or", int_hexagon_A4_ornp>; - -// XTYPE / ALU / Logical-logical Doublewords. -def Hexagon_M4_xor_xacc: - di_MInst_dididi_xacc <"xor", int_hexagon_M4_xor_xacc>; - -// XTYPE / ALU / Logical-logical Words. -def HEXAGON_M4_and_and: - si_MInst_sisisi_and <"and", int_hexagon_M4_and_and>; -def HEXAGON_M4_and_or: - si_MInst_sisisi_and <"or", int_hexagon_M4_and_or>; -def HEXAGON_M4_and_xor: - si_MInst_sisisi_and <"xor", int_hexagon_M4_and_xor>; -def HEXAGON_M4_and_andn: - si_MInst_sisisi_andn <"and", int_hexagon_M4_and_andn>; -def HEXAGON_M4_xor_and: - si_MInst_sisisi_xor <"and", int_hexagon_M4_xor_and>; -def HEXAGON_M4_xor_or: - si_MInst_sisisi_xor <"or", int_hexagon_M4_xor_or>; -def HEXAGON_M4_xor_andn: - si_MInst_sisisi_xorn <"and", int_hexagon_M4_xor_andn>; -def HEXAGON_M4_or_and: - si_MInst_sisisi_or <"and", int_hexagon_M4_or_and>; -def HEXAGON_M4_or_or: - si_MInst_sisisi_or <"or", int_hexagon_M4_or_or>; -def HEXAGON_M4_or_xor: - si_MInst_sisisi_or <"xor", int_hexagon_M4_or_xor>; -def HEXAGON_M4_or_andn: - si_MInst_sisisi_orn <"and", int_hexagon_M4_or_andn>; -def HEXAGON_S4_or_andix: - si_SInst_sisis10_andi <"or", int_hexagon_S4_or_andix>; -def HEXAGON_S4_or_andi: - si_SInst_sisis10_or <"and", int_hexagon_S4_or_andi>; -def HEXAGON_S4_or_ori: - si_SInst_sisis10_or <"or", int_hexagon_S4_or_ori>; - -// XTYPE / ALU / Modulo wrap. -def HEXAGON_A4_modwrapu: - si_ALU64_sisi <"modwrap", int_hexagon_A4_modwrapu>; - -// XTYPE / ALU / Round. -def HEXAGON_A4_cround_ri: - si_SInst_siu5 <"cround", int_hexagon_A4_cround_ri>; -def HEXAGON_A4_cround_rr: - si_SInst_sisi <"cround", int_hexagon_A4_cround_rr>; -def HEXAGON_A4_round_ri: - si_SInst_siu5 <"round", int_hexagon_A4_round_ri>; -def HEXAGON_A4_round_rr: - si_SInst_sisi <"round", int_hexagon_A4_round_rr>; -def HEXAGON_A4_round_ri_sat: - si_SInst_siu5_sat <"round", int_hexagon_A4_round_ri_sat>; -def HEXAGON_A4_round_rr_sat: - si_SInst_sisi_sat <"round", int_hexagon_A4_round_rr_sat>; - -// XTYPE / ALU / Vector reduce add unsigned halfwords. -// XTYPE / ALU / Vector add bytes. -// XTYPE / ALU / Vector conditional negate. -// XTYPE / ALU / Vector maximum bytes. -// XTYPE / ALU / Vector reduce maximum halfwords. -// XTYPE / ALU / Vector reduce maximum words. -// XTYPE / ALU / Vector minimum bytes. -// XTYPE / ALU / Vector reduce minimum halfwords. -// XTYPE / ALU / Vector reduce minimum words. -// XTYPE / ALU / Vector subtract bytes. - - -/******************************************************************** -* XTYPE/BIT * -*********************************************************************/ - -// XTYPE / BIT / Count leading. -// XTYPE / BIT / Count trailing. -// XTYPE / BIT / Extract bitfield. -// XTYPE / BIT / Masked parity. -// XTYPE / BIT / Bit reverse. -// XTYPE / BIT / Split bitfield. - - -/******************************************************************** -* XTYPE/COMPLEX * -*********************************************************************/ - -// XTYPE / COMPLEX / Complex add/sub halfwords. -// XTYPE / COMPLEX / Complex add/sub words. -// XTYPE / COMPLEX / Complex multiply 32x16. -// XTYPE / COMPLEX / Vector reduce complex rotate. - - -/******************************************************************** -* XTYPE/MPY * -*********************************************************************/ - -// XTYPE / COMPLEX / Complex add/sub halfwords. diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt index d39260c63..bd9d2d3 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt @@ -120,6 +120,8 @@ # CHECK: r17:16 = neg(r21:20) 0xd1 0xc0 0x95 0x8c # CHECK: r17 = neg(r21):sat +0x31 0xc0 0xd4 0x88 +# CHECK: r17 = round(r21:20):sat 0x11 0xdf 0xf5 0x8c # CHECK: r17 = cround(r21, #31) 0x91 0xdf 0xf5 0x8c -- 2.7.4