From 1ddc5c95607602784950af3bc8bf6595d68bc577 Mon Sep 17 00:00:00 2001 From: MyungJoo Ham Date: Mon, 4 Oct 2010 19:40:07 +0900 Subject: [PATCH] s5pc1xx: cache: do the alignment This helps improve the stability of sleep/wakeup. --- arch/arm/cpu/armv7/s5pc1xx/cache.S | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S index 4226a39..9e64f10 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.S +++ b/arch/arm/cpu/armv7/s5pc1xx/cache.S @@ -104,17 +104,18 @@ finished_inval: @ but we compile with armv5 ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} + .align 5 l2_cache_enable: - push {r1, r2, r3, lr} - mrc 15, 0, r3, cr1, cr0, 1 - orr r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #2 + mcr p15, 0, r0, c1, c0, 1 + mov pc, lr + .align 5 l2_cache_disable: - push {r1, r2, r3, lr} - mrc 15, 0, r3, cr1, cr0, 1 - bic r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} + mrc p15, 0, r0, c1, c0, 1 + bic r0, r0, #2 + mcr p15, 0, r0, c1, c0, 1 + mov pc, lr + .align 5 -- 2.7.4