From 1dd44acfab048893b7f8028d63fe82df483bc5a8 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 7 May 2013 14:30:52 +1000 Subject: [PATCH] drm/nve4/gr: update initial register/context values Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/core/engine/graph/ctxnve0.c | 74 +--------------------- .../drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc | 31 ++------- .../nouveau/core/engine/graph/fuc/gpcnve0.fuc.h | 32 ++-------- drivers/gpu/drm/nouveau/core/engine/graph/nve0.c | 51 +++++---------- 4 files changed, 31 insertions(+), 157 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c index 574a1de..848570b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c @@ -749,38 +749,6 @@ nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv) nv_icmd(priv, 0x000841, 0x08000080); nv_icmd(priv, 0x000842, 0x00400008); nv_icmd(priv, 0x000843, 0x08000080); - switch (nv_device(priv)->chipset) { - case 0xe7: - case 0xe6: - break; - default: - nv_icmd(priv, 0x000818, 0x00000000); - nv_icmd(priv, 0x000819, 0x00000000); - nv_icmd(priv, 0x00081a, 0x00000000); - nv_icmd(priv, 0x00081b, 0x00000000); - nv_icmd(priv, 0x00081c, 0x00000000); - nv_icmd(priv, 0x00081d, 0x00000000); - nv_icmd(priv, 0x00081e, 0x00000000); - nv_icmd(priv, 0x00081f, 0x00000000); - nv_icmd(priv, 0x000848, 0x00000000); - nv_icmd(priv, 0x000849, 0x00000000); - nv_icmd(priv, 0x00084a, 0x00000000); - nv_icmd(priv, 0x00084b, 0x00000000); - nv_icmd(priv, 0x00084c, 0x00000000); - nv_icmd(priv, 0x00084d, 0x00000000); - nv_icmd(priv, 0x00084e, 0x00000000); - nv_icmd(priv, 0x00084f, 0x00000000); - nv_icmd(priv, 0x000850, 0x00000000); - nv_icmd(priv, 0x000851, 0x00000000); - nv_icmd(priv, 0x000852, 0x00000000); - nv_icmd(priv, 0x000853, 0x00000000); - nv_icmd(priv, 0x000854, 0x00000000); - nv_icmd(priv, 0x000855, 0x00000000); - nv_icmd(priv, 0x000856, 0x00000000); - nv_icmd(priv, 0x000857, 0x00000000); - nv_icmd(priv, 0x000738, 0x00000000); - break; - } nv_icmd(priv, 0x0006aa, 0x00000001); nv_icmd(priv, 0x0006ab, 0x00000002); nv_icmd(priv, 0x0006ac, 0x00000080); @@ -869,38 +837,6 @@ nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv) nv_icmd(priv, 0x000813, 0x00000006); nv_icmd(priv, 0x000814, 0x00000008); nv_icmd(priv, 0x000957, 0x00000003); - switch (nv_device(priv)->chipset) { - case 0xe7: - case 0xe6: - break; - default: - nv_icmd(priv, 0x000818, 0x00000000); - nv_icmd(priv, 0x000819, 0x00000000); - nv_icmd(priv, 0x00081a, 0x00000000); - nv_icmd(priv, 0x00081b, 0x00000000); - nv_icmd(priv, 0x00081c, 0x00000000); - nv_icmd(priv, 0x00081d, 0x00000000); - nv_icmd(priv, 0x00081e, 0x00000000); - nv_icmd(priv, 0x00081f, 0x00000000); - nv_icmd(priv, 0x000848, 0x00000000); - nv_icmd(priv, 0x000849, 0x00000000); - nv_icmd(priv, 0x00084a, 0x00000000); - nv_icmd(priv, 0x00084b, 0x00000000); - nv_icmd(priv, 0x00084c, 0x00000000); - nv_icmd(priv, 0x00084d, 0x00000000); - nv_icmd(priv, 0x00084e, 0x00000000); - nv_icmd(priv, 0x00084f, 0x00000000); - nv_icmd(priv, 0x000850, 0x00000000); - nv_icmd(priv, 0x000851, 0x00000000); - nv_icmd(priv, 0x000852, 0x00000000); - nv_icmd(priv, 0x000853, 0x00000000); - nv_icmd(priv, 0x000854, 0x00000000); - nv_icmd(priv, 0x000855, 0x00000000); - nv_icmd(priv, 0x000856, 0x00000000); - nv_icmd(priv, 0x000857, 0x00000000); - nv_icmd(priv, 0x000738, 0x00000000); - break; - } nv_icmd(priv, 0x000b07, 0x00000002); nv_icmd(priv, 0x000b08, 0x00000100); nv_icmd(priv, 0x000b09, 0x00000100); @@ -2180,6 +2116,7 @@ nve0_grctx_generate_902d(struct nvc0_graph_priv *priv) case 0xe6: nv_mthd(priv, 0x902d, 0x3410, 0x80002006); break; + case 0xe4: case 0xe7: default: nv_mthd(priv, 0x902d, 0x3410, 0x00000000); @@ -2716,6 +2653,7 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419e94, 0x0); nv_wr32(priv, 0x419e98, 0x0); switch (nv_device(priv)->chipset) { + case 0xe4: case 0xe7: case 0xe6: nv_wr32(priv, 0x419eac, 0x1f8f); @@ -2726,10 +2664,6 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419eb0, 0xdb00da0); nv_wr32(priv, 0x419eb8, 0x0); break; - default: - nv_wr32(priv, 0x419eac, 0x1fcf); - nv_wr32(priv, 0x419eb0, 0xd3f); - break; } nv_wr32(priv, 0x419ec8, 0x1304f); nv_wr32(priv, 0x419f30, 0x0); @@ -2749,6 +2683,7 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419f4c, 0x0); nv_wr32(priv, 0x419f58, 0x0); switch (nv_device(priv)->chipset) { + case 0xe4: case 0xe7: case 0xe6: nv_wr32(priv, 0x419f70, 0x0); @@ -2760,9 +2695,6 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419f78, 0xeb); nv_wr32(priv, 0x419f7c, 0x404); break; - default: - nv_wr32(priv, 0x419f78, 0xb); - break; } } diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc index e906ca6..ccaeb50 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc @@ -55,13 +55,13 @@ chipsets: .b8 0xe7 0 0 0 .b16 #nve4_gpc_mmio_head .b16 #nve4_gpc_mmio_tail -.b16 #nve6_tpc_mmio_head -.b16 #nve6_tpc_mmio_tail +.b16 #nve4_tpc_mmio_head +.b16 #nve4_tpc_mmio_tail .b8 0xe6 0 0 0 .b16 #nve4_gpc_mmio_head .b16 #nve4_gpc_mmio_tail -.b16 #nve6_tpc_mmio_head -.b16 #nve6_tpc_mmio_tail +.b16 #nve4_tpc_mmio_head +.b16 #nve4_tpc_mmio_tail .b8 0xf0 0 0 0 .b16 #nvf0_gpc_mmio_head .b16 #nvf0_gpc_mmio_tail @@ -156,30 +156,9 @@ mmctx_data(0x0006ac, 2) mmctx_data(0x0006c8, 1) mmctx_data(0x000730, 8) mmctx_data(0x000758, 1) -mmctx_data(0x000778, 1) -nve4_tpc_mmio_tail: - -nve6_tpc_mmio_head: -mmctx_data(0x000048, 1) -mmctx_data(0x000064, 1) -mmctx_data(0x000088, 1) -mmctx_data(0x000200, 6) -mmctx_data(0x00021c, 2) -mmctx_data(0x000230, 1) -mmctx_data(0x0002c4, 1) -mmctx_data(0x000400, 3) -mmctx_data(0x000420, 3) -mmctx_data(0x0004e8, 1) -mmctx_data(0x0004f4, 1) -mmctx_data(0x000604, 4) -mmctx_data(0x000644, 22) -mmctx_data(0x0006ac, 2) -mmctx_data(0x0006c8, 1) -mmctx_data(0x000730, 8) -mmctx_data(0x000758, 1) mmctx_data(0x000770, 1) mmctx_data(0x000778, 2) -nve6_tpc_mmio_tail: +nve4_tpc_mmio_tail: nvf0_tpc_mmio_head: mmctx_data(0x000048, 1) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h index 5924339..419bd5d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h @@ -35,16 +35,16 @@ uint32_t nve0_grgpc_data[] = { /* 0x0064: chipsets */ 0x000000e4, 0x011c0098, - 0x01d4018c, + 0x01d8018c, 0x000000e7, 0x011c0098, - 0x022001d4, + 0x01d8018c, 0x000000e6, 0x011c0098, - 0x022001d4, + 0x01d8018c, 0x000000f0, 0x018c011c, - 0x02700220, + 0x022801d8, 0x00000000, /* 0x0098: nve4_gpc_mmio_head */ 0x00000380, @@ -129,30 +129,10 @@ uint32_t nve0_grgpc_data[] = { 0x000006c8, 0x1c000730, 0x00000758, - 0x00000778, -/* 0x01d4: nve4_tpc_mmio_tail */ -/* 0x01d4: nve6_tpc_mmio_head */ - 0x00000048, - 0x00000064, - 0x00000088, - 0x14000200, - 0x0400021c, - 0x00000230, - 0x000002c4, - 0x08000400, - 0x08000420, - 0x000004e8, - 0x000004f4, - 0x0c000604, - 0x54000644, - 0x040006ac, - 0x000006c8, - 0x1c000730, - 0x00000758, 0x00000770, 0x04000778, -/* 0x0220: nve6_tpc_mmio_tail */ -/* 0x0220: nvf0_tpc_mmio_head */ +/* 0x01d8: nve4_tpc_mmio_tail */ +/* 0x01d8: nvf0_tpc_mmio_head */ 0x00000048, 0x00000064, 0x00000088, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c index 9a3c2a3..f4685bb 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c @@ -475,6 +475,7 @@ nve0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, case 0xe6: priv->magic_not_rop_nr = 1; break; + case 0xf0: default: break; } @@ -803,11 +804,12 @@ nve0_graph_init_units(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x409ffc, 0x00000000); nv_wr32(priv, 0x409c14, 0x00003e3e); switch (nv_device(priv)->chipset) { + case 0xe4: case 0xe7: case 0xe6: nv_wr32(priv, 0x409c24, 0x000f0001); break; - default: + case 0xf0: nv_wr32(priv, 0x409c24, 0x000f0000); break; } @@ -817,16 +819,7 @@ nve0_graph_init_units(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x408030, 0xc0000000); nv_wr32(priv, 0x404490, 0xc0000000); nv_wr32(priv, 0x406018, 0xc0000000); - switch (nv_device(priv)->chipset) { - case 0xe7: - case 0xe6: - case 0xf0: - nv_wr32(priv, 0x407020, 0x40000000); - break; - default: - nv_wr32(priv, 0x407020, 0xc0000000); - break; - } + nv_wr32(priv, 0x407020, 0x40000000); nv_wr32(priv, 0x405840, 0xc0000000); nv_wr32(priv, 0x405844, 0x00ffffff); @@ -1062,29 +1055,19 @@ nve0_graph_init(struct nouveau_object *object) nve0_graph_init_obj418880(priv); nve0_graph_init_regs(priv); - - switch (nv_device(priv)->chipset) { - case 0xe7: - case 0xe6: - case 0xf0: - nve0_graph_init_unk40xx(priv); - nve0_graph_init_unk44xx(priv); - nve0_graph_init_unk78xx(priv); - nve0_graph_init_unk60xx(priv); - nve0_graph_init_unk64xx(priv); - nve0_graph_init_unk58xx(priv); - nve0_graph_init_unk80xx(priv); - nve0_graph_init_unk70xx(priv); - nve0_graph_init_unk5bxx(priv); - nve0_graph_init_gpc(priv); - nve0_graph_init_tpc(priv); - nve0_graph_init_tpcunk(priv); - nve0_graph_init_unk88xx(priv); - break; - default: - break; - } - + nve0_graph_init_unk40xx(priv); + nve0_graph_init_unk44xx(priv); + nve0_graph_init_unk78xx(priv); + nve0_graph_init_unk60xx(priv); + nve0_graph_init_unk64xx(priv); + nve0_graph_init_unk58xx(priv); + nve0_graph_init_unk80xx(priv); + nve0_graph_init_unk70xx(priv); + nve0_graph_init_unk5bxx(priv); + nve0_graph_init_gpc(priv); + nve0_graph_init_tpc(priv); + nve0_graph_init_tpcunk(priv); + nve0_graph_init_unk88xx(priv); nve0_graph_init_gpc_0(priv); nv_wr32(priv, 0x400500, 0x00010001); -- 2.7.4