From 1db01f22f58cc01768dc921a7443a1bad4e48eb5 Mon Sep 17 00:00:00 2001 From: Yao Qi Date: Tue, 1 Jul 2014 15:36:44 +0800 Subject: [PATCH] Restrict matching add/sub sp, #imm Currently, GDB matches both add/sub sp, #imm in prologue and epilogue, which is not very precise. On the instruction level, the immediate number in both instruction can't be negative, so 'sub sp, #imm' only appears in prologue while 'add sp, #imm' only appears in epilogue. Note that on assembly level, we can write 'add sp, -8', but gas will translate to 'sub sp, 8' instruction. This patch is to only match 'sub sp, #imm' in prologue and match 'add sp, #immm' in epilogue. It paves the way for the following patch. gdb: 2014-07-11 Yao Qi * arm-tdep.c (thumb_analyze_prologue): Don't match instruction 'add sp, #imm'. (thumb_in_function_epilogue_p): Don't match 'sub sp, #imm'. --- gdb/ChangeLog | 6 ++++++ gdb/arm-tdep.c | 15 +++++---------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index afad8f3..112a869 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,9 @@ +2014-07-11 Yao Qi + + * arm-tdep.c (thumb_analyze_prologue): Don't match instruction + 'add sp, #imm'. + (thumb_in_function_epilogue_p): Don't match 'sub sp, #imm'. + 2014-07-11 Gary Benson * amd64-linux-nat.c (gdbcore.h): Remove include. diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 8cc60a4..6b1cf3c 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -737,16 +737,11 @@ thumb_analyze_prologue (struct gdbarch *gdbarch, pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); } } - else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR - sub sp, #simm */ + else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */ { offset = (insn & 0x7f) << 2; /* get scaled offset */ - if (insn & 0x80) /* Check for SUB. */ - regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], - -offset); - else - regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], - offset); + regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], + -offset); } else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */ regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM], @@ -3264,7 +3259,7 @@ thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) found_return = 1; else if (insn == 0x46bd) /* mov sp, r7 */ found_stack_adjust = 1; - else if ((insn & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */ + else if ((insn & 0xff80) == 0xb000) /* add sp, imm */ found_stack_adjust = 1; else if ((insn & 0xfe00) == 0xbc00) /* pop */ { @@ -3324,7 +3319,7 @@ thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) if (insn2 == 0x46bd) /* mov sp, r7 */ found_stack_adjust = 1; - else if ((insn2 & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */ + else if ((insn2 & 0xff80) == 0xb000) /* add sp, imm */ found_stack_adjust = 1; else if ((insn2 & 0xff00) == 0xbc00) /* pop without PC */ found_stack_adjust = 1; -- 2.7.4