From 1d8820c342560a2fbf8e1970b861193ba8137177 Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Mon, 22 May 2023 20:32:06 -0400 Subject: [PATCH] [gn] port 98e342dca2372 (RISCV MCA) --- llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn | 1 + llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn | 14 ++++++++++++++ .../gn/secondary/llvm/lib/Target/targets_with_mcas.gni | 2 +- 3 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn index 8c30924..b8ea3d1 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn @@ -105,6 +105,7 @@ group("RISCV") { ":LLVMRISCVCodeGen", "AsmParser", "Disassembler", + "MCA", "MCTargetDesc", "TargetInfo", ] diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn new file mode 100644 index 0000000..a4d95f5 --- /dev/null +++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn @@ -0,0 +1,14 @@ +static_library("MCA") { + output_name = "LLVMTargetRISCVMCA" + deps = [ + "//llvm/lib/CodeGen", + "//llvm/lib/MC", + "//llvm/lib/MC/MCParser", + "//llvm/lib/MCA", + "//llvm/lib/Support", + "//llvm/lib/Target/RISCV/MCTargetDesc", + "//llvm/lib/Target/RISCV/TargetInfo", + ] + include_dirs = [ ".." ] + sources = [ "RISCVCustomBehaviour.cpp" ] +} diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/targets_with_mcas.gni b/llvm/utils/gn/secondary/llvm/lib/Target/targets_with_mcas.gni index 950393b..bae8da1 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/targets_with_mcas.gni +++ b/llvm/utils/gn/secondary/llvm/lib/Target/targets_with_mcas.gni @@ -2,7 +2,7 @@ import("//llvm/lib/Target/targets.gni") targets_with_mcas = [] foreach(target, llvm_targets_to_build) { - if (target == "AMDGPU" || target == "X86") { + if (target == "AMDGPU" || target == "RISCV" || target == "X86") { targets_with_mcas += [ target ] } } -- 2.7.4