From 1d812728cc0ddeb69b9f0d3d2d7d29fa4295086f Mon Sep 17 00:00:00 2001
From: Rafael Espindola <rafael.espindola@gmail.com>
Date: Fri, 26 Jul 2013 13:18:16 +0000
Subject: [PATCH] Revert "Add a target legalize hook for SplitVectorOperand"

This reverts commit 187198. It broke the bots.

The soft float test probably needs a -triple because of name differences.
On the hard float test I am getting a "roundss $1, %xmm0, %xmm0", instead of
"vroundss $1, %xmm0, %xmm0, %xmm0".

llvm-svn: 187201
---
 .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp   |  4 ---
 llvm/lib/Target/X86/X86ISelLowering.cpp            |  2 +-
 llvm/test/CodeGen/NVPTX/vector-stores.ll           | 30 ----------------------
 llvm/test/CodeGen/X86/floor-soft-float.ll          | 11 --------
 4 files changed, 1 insertion(+), 46 deletions(-)
 delete mode 100644 llvm/test/CodeGen/NVPTX/vector-stores.ll
 delete mode 100644 llvm/test/CodeGen/X86/floor-soft-float.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 72c16b5..75bb609 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1031,10 +1031,6 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
         dbgs() << "\n");
   SDValue Res = SDValue();
 
-  // See if the target wants to custom split this node.
-  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
-    return false;
-
   if (Res.getNode() == 0) {
     switch (N->getOpcode()) {
     default:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index ad2d308..e75781e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -996,7 +996,7 @@ void X86TargetLowering::resetOperationActions() {
     setLoadExtAction(ISD::EXTLOAD,              MVT::v2f32, Legal);
   }
 
-  if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
+  if (Subtarget->hasSSE41()) {
     setOperationAction(ISD::FFLOOR,             MVT::f32,   Legal);
     setOperationAction(ISD::FCEIL,              MVT::f32,   Legal);
     setOperationAction(ISD::FTRUNC,             MVT::f32,   Legal);
diff --git a/llvm/test/CodeGen/NVPTX/vector-stores.ll b/llvm/test/CodeGen/NVPTX/vector-stores.ll
deleted file mode 100644
index 4941812..0000000
--- a/llvm/test/CodeGen/NVPTX/vector-stores.ll
+++ /dev/null
@@ -1,30 +0,0 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
-
-; CHECK: .visible .func foo1
-; CHECK: st.v2.f32
-define void @foo1(<2 x float> %val, <2 x float>* %ptr) {
-  store <2 x float> %val, <2 x float>* %ptr
-  ret void
-}
-
-; CHECK: .visible .func foo2
-; CHECK: st.v4.f32
-define void @foo2(<4 x float> %val, <4 x float>* %ptr) {
-  store <4 x float> %val, <4 x float>* %ptr
-  ret void
-}
-
-; CHECK: .visible .func foo3
-; CHECK: st.v2.u32
-define void @foo3(<2 x i32> %val, <2 x i32>* %ptr) {
-  store <2 x i32> %val, <2 x i32>* %ptr
-  ret void
-}
-
-; CHECK: .visible .func foo4
-; CHECK: st.v4.u32
-define void @foo4(<4 x i32> %val, <4 x i32>* %ptr) {
-  store <4 x i32> %val, <4 x i32>* %ptr
-  ret void
-}
-
diff --git a/llvm/test/CodeGen/X86/floor-soft-float.ll b/llvm/test/CodeGen/X86/floor-soft-float.ll
deleted file mode 100644
index 158a824..0000000
--- a/llvm/test/CodeGen/X86/floor-soft-float.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; RUN: llc < %s -march=x86-64 -mattr=+sse41 -soft-float=0 | FileCheck %s --check-prefix=CHECK-HARD-FLOAT
-; RUN: llc < %s -march=x86-64 -mattr=+sse41 -soft-float=1 | FileCheck %s --check-prefix=CHECK-SOFT-FLOAT
-
-declare float @llvm.floor.f32(float)
-
-; CHECK-SOFT-FLOAT: callq _floorf
-; CHECK-HARD-FLOAT: vroundss $1, %xmm0, %xmm0, %xmm0
-define float @myfloor(float %a) {
-  %val = tail call float @llvm.floor.f32(float %a)
-  ret float %val
-}
-- 
2.7.4