From 1d7b4a7037cd4773bce26906e81778b5097b09c3 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 4 Jun 2011 17:44:22 +0000 Subject: [PATCH] sim: bfin: import testsuite Now that the common sim testsuite code supports .S and .c files, we can import the Blackfin testsuite. There are about ~800 tests here, so I'm only attaching a compressed patch of them. Other than adding files to sim/testsuite/sim/bfin/, the sim/configure.tgt file was updated to mark Blackfin as having a testsuite, and sim/configure regenerated. Signed-off-by: Mike Frysinger --- sim/ChangeLog | 5 + sim/configure | 1 + sim/configure.tgt | 1 + sim/testsuite/sim/bfin/10272_small.s | 51 + sim/testsuite/sim/bfin/10436.s | 39 + sim/testsuite/sim/bfin/10622.s | 21 + sim/testsuite/sim/bfin/10742.s | 17 + sim/testsuite/sim/bfin/10799.s | 55 + sim/testsuite/sim/bfin/11080.s | 40 + sim/testsuite/sim/bfin/7641.s | 38 + sim/testsuite/sim/bfin/ChangeLog | 243 + sim/testsuite/sim/bfin/PN_generator.s | 78 + sim/testsuite/sim/bfin/a0.s | 17 + sim/testsuite/sim/bfin/a0shift.S | 169 + sim/testsuite/sim/bfin/a1.s | 29 + sim/testsuite/sim/bfin/a10.s | 176 + sim/testsuite/sim/bfin/a11.S | 386 + sim/testsuite/sim/bfin/a12.s | 40 + sim/testsuite/sim/bfin/a2.s | 179 + sim/testsuite/sim/bfin/a20.S | 68 + sim/testsuite/sim/bfin/a21.s | 83 + sim/testsuite/sim/bfin/a22.s | 83 + sim/testsuite/sim/bfin/a23.s | 84 + sim/testsuite/sim/bfin/a24.s | 12 + sim/testsuite/sim/bfin/a25.s | 28 + sim/testsuite/sim/bfin/a26.s | 72 + sim/testsuite/sim/bfin/a3.s | 313 + sim/testsuite/sim/bfin/a30.s | 55 + sim/testsuite/sim/bfin/a4.s | 36 + sim/testsuite/sim/bfin/a5.s | 140 + sim/testsuite/sim/bfin/a6.s | 132 + sim/testsuite/sim/bfin/a7.s | 179 + sim/testsuite/sim/bfin/a8.s | 41 + sim/testsuite/sim/bfin/a9.s | 219 + sim/testsuite/sim/bfin/abs-2.S | 42 + sim/testsuite/sim/bfin/abs-3.S | 42 + sim/testsuite/sim/bfin/abs-4.S | 42 + sim/testsuite/sim/bfin/abs.S | 42 + sim/testsuite/sim/bfin/abs_acc.s | 224 + sim/testsuite/sim/bfin/acc-rot.s | 129 + sim/testsuite/sim/bfin/acp5_19.s | 12 + sim/testsuite/sim/bfin/acp5_4.s | 39 + sim/testsuite/sim/bfin/add_imm7.s | 38 + sim/testsuite/sim/bfin/add_shift.S | 53 + sim/testsuite/sim/bfin/add_sub_acc.s | 123 + sim/testsuite/sim/bfin/addsub_flags.S | 107 + sim/testsuite/sim/bfin/algnbug1.s | 38 + sim/testsuite/sim/bfin/algnbug2.s | 69 + sim/testsuite/sim/bfin/allinsn.exp | 15 + sim/testsuite/sim/bfin/argc.c | 31 + sim/testsuite/sim/bfin/ashift.s | 323 + sim/testsuite/sim/bfin/ashift_flags.s | 84 + sim/testsuite/sim/bfin/b0.S | 51 + sim/testsuite/sim/bfin/b1.s | 12 + sim/testsuite/sim/bfin/b2.S | 26 + sim/testsuite/sim/bfin/brcc.s | 164 + sim/testsuite/sim/bfin/brevadd.s | 20 + sim/testsuite/sim/bfin/byteop16m.s | 76 + sim/testsuite/sim/bfin/byteop16p.s | 74 + sim/testsuite/sim/bfin/byteop1p.s | 75 + sim/testsuite/sim/bfin/byteop2p.s | 58 + sim/testsuite/sim/bfin/byteop3p.s | 119 + sim/testsuite/sim/bfin/byteunpack.s | 45 + sim/testsuite/sim/bfin/c_alu2op_arith_r_sft.s | 226 + sim/testsuite/sim/bfin/c_alu2op_conv_b.s | 211 + sim/testsuite/sim/bfin/c_alu2op_conv_h.s | 211 + sim/testsuite/sim/bfin/c_alu2op_conv_mix.s | 186 + sim/testsuite/sim/bfin/c_alu2op_conv_neg.s | 211 + sim/testsuite/sim/bfin/c_alu2op_conv_toggle.s | 211 + sim/testsuite/sim/bfin/c_alu2op_conv_xb.s | 211 + sim/testsuite/sim/bfin/c_alu2op_conv_xh.s | 212 + sim/testsuite/sim/bfin/c_alu2op_divq.s | 220 + sim/testsuite/sim/bfin/c_alu2op_divs.s | 220 + sim/testsuite/sim/bfin/c_alu2op_log_l_sft.s | 220 + sim/testsuite/sim/bfin/c_alu2op_log_r_sft.s | 217 + sim/testsuite/sim/bfin/c_alu2op_shadd_1.s | 209 + sim/testsuite/sim/bfin/c_alu2op_shadd_2.s | 209 + sim/testsuite/sim/bfin/c_br_preg_killed_ac.s | 82 + sim/testsuite/sim/bfin/c_br_preg_killed_ex1.s | 85 + sim/testsuite/sim/bfin/c_br_preg_stall_ac.s | 75 + sim/testsuite/sim/bfin/c_br_preg_stall_ex1.s | 70 + sim/testsuite/sim/bfin/c_brcc_bp1.s | 45 + sim/testsuite/sim/bfin/c_brcc_bp2.s | 45 + sim/testsuite/sim/bfin/c_brcc_bp3.s | 47 + sim/testsuite/sim/bfin/c_brcc_bp4.s | 46 + sim/testsuite/sim/bfin/c_brcc_brf_bp.s | 46 + sim/testsuite/sim/bfin/c_brcc_brf_brt_bp.s | 47 + sim/testsuite/sim/bfin/c_brcc_brf_brt_nbp.s | 46 + sim/testsuite/sim/bfin/c_brcc_brf_fbkwd.s | 46 + sim/testsuite/sim/bfin/c_brcc_brf_nbp.s | 45 + sim/testsuite/sim/bfin/c_brcc_brt_bp.s | 46 + sim/testsuite/sim/bfin/c_brcc_brt_nbp.s | 45 + sim/testsuite/sim/bfin/c_brcc_kills_dhits.s | 136 + sim/testsuite/sim/bfin/c_brcc_kills_dmiss.s | 137 + sim/testsuite/sim/bfin/c_cactrl_iflush_pr.s | 102 + sim/testsuite/sim/bfin/c_cactrl_iflush_pr_pp.s | 100 + sim/testsuite/sim/bfin/c_calla_ljump.s | 31 + sim/testsuite/sim/bfin/c_calla_subr.s | 28 + sim/testsuite/sim/bfin/c_cc2dreg.s | 56 + sim/testsuite/sim/bfin/c_cc2stat_cc_ac.S | 240 + sim/testsuite/sim/bfin/c_cc2stat_cc_an.s | 243 + sim/testsuite/sim/bfin/c_cc2stat_cc_aq.s | 243 + sim/testsuite/sim/bfin/c_cc2stat_cc_av0.S | 241 + sim/testsuite/sim/bfin/c_cc2stat_cc_av1.S | 240 + sim/testsuite/sim/bfin/c_cc2stat_cc_az.s | 243 + sim/testsuite/sim/bfin/c_cc_flag_ccmv_depend.S | 80 + sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft.s | 87 + sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_s1.s | 99 + sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_sn.s | 118 + sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft.s | 83 + sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_s1.s | 98 + sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_sn.S | 127 + sim/testsuite/sim/bfin/c_ccflag_a0a1.S | 143 + sim/testsuite/sim/bfin/c_ccflag_dr_dr.s | 299 + sim/testsuite/sim/bfin/c_ccflag_dr_dr_uu.s | 299 + sim/testsuite/sim/bfin/c_ccflag_dr_imm3.s | 224 + sim/testsuite/sim/bfin/c_ccflag_dr_imm3_uu.s | 221 + sim/testsuite/sim/bfin/c_ccflag_pr_imm3.s | 539 + sim/testsuite/sim/bfin/c_ccflag_pr_imm3_uu.s | 238 + sim/testsuite/sim/bfin/c_ccflag_pr_pr.s | 262 + sim/testsuite/sim/bfin/c_ccflag_pr_pr_uu.s | 212 + sim/testsuite/sim/bfin/c_ccmv_cc_dr_dr.s | 124 + sim/testsuite/sim/bfin/c_ccmv_cc_dr_pr.s | 61 + sim/testsuite/sim/bfin/c_ccmv_cc_pr_pr.s | 111 + sim/testsuite/sim/bfin/c_ccmv_ncc_dr_dr.s | 123 + sim/testsuite/sim/bfin/c_ccmv_ncc_dr_pr.s | 60 + sim/testsuite/sim/bfin/c_ccmv_ncc_pr_pr.s | 111 + sim/testsuite/sim/bfin/c_comp3op_dr_and_dr.s | 412 + sim/testsuite/sim/bfin/c_comp3op_dr_minus_dr.s | 412 + sim/testsuite/sim/bfin/c_comp3op_dr_mix.s | 237 + sim/testsuite/sim/bfin/c_comp3op_dr_or_dr.s | 412 + sim/testsuite/sim/bfin/c_comp3op_dr_plus_dr.s | 412 + sim/testsuite/sim/bfin/c_comp3op_dr_xor_dr.s | 412 + sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh1.s | 302 + sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh2.s | 302 + sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_n.s | 164 + sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_p.s | 147 + sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_n.s | 166 + sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_p.s | 147 + sim/testsuite/sim/bfin/c_compi2opd_flags.S | 600 + sim/testsuite/sim/bfin/c_compi2opd_flags_2.S | 600 + sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_n.s | 149 + sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_p.s | 116 + sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_n.s | 161 + sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_p.s | 131 + sim/testsuite/sim/bfin/c_dagmodik_lnz_imgebl.s | 290 + sim/testsuite/sim/bfin/c_dagmodik_lnz_imltbl.s | 289 + sim/testsuite/sim/bfin/c_dagmodik_lz_inc_dec.s | 140 + sim/testsuite/sim/bfin/c_dagmodim_lnz_imgebl.s | 108 + sim/testsuite/sim/bfin/c_dagmodim_lnz_imltbl.s | 109 + sim/testsuite/sim/bfin/c_dagmodim_lz_inc_dec.s | 98 + sim/testsuite/sim/bfin/c_dsp32alu_a0_pm_a1.s | 39 + sim/testsuite/sim/bfin/c_dsp32alu_a0a1s.s | 82 + sim/testsuite/sim/bfin/c_dsp32alu_a_abs_a.s | 34 + sim/testsuite/sim/bfin/c_dsp32alu_a_neg_a.s | 34 + sim/testsuite/sim/bfin/c_dsp32alu_aa_absabs.s | 35 + sim/testsuite/sim/bfin/c_dsp32alu_aa_negneg.s | 35 + sim/testsuite/sim/bfin/c_dsp32alu_abs.s | 62 + sim/testsuite/sim/bfin/c_dsp32alu_absabs.s | 62 + sim/testsuite/sim/bfin/c_dsp32alu_alhwx.s | 128 + sim/testsuite/sim/bfin/c_dsp32alu_awx.s | 61 + sim/testsuite/sim/bfin/c_dsp32alu_byteop1ew.s | 136 + sim/testsuite/sim/bfin/c_dsp32alu_byteop2.s | 76 + sim/testsuite/sim/bfin/c_dsp32alu_byteop3.s | 76 + sim/testsuite/sim/bfin/c_dsp32alu_bytepack.s | 77 + sim/testsuite/sim/bfin/c_dsp32alu_byteunpack.s | 113 + sim/testsuite/sim/bfin/c_dsp32alu_disalnexcpt.s | 255 + sim/testsuite/sim/bfin/c_dsp32alu_max.s | 261 + sim/testsuite/sim/bfin/c_dsp32alu_maxmax.s | 261 + sim/testsuite/sim/bfin/c_dsp32alu_min.s | 261 + sim/testsuite/sim/bfin/c_dsp32alu_minmin.s | 261 + sim/testsuite/sim/bfin/c_dsp32alu_mix.s | 137 + sim/testsuite/sim/bfin/c_dsp32alu_r_lh_a0pa1.s | 75 + sim/testsuite/sim/bfin/c_dsp32alu_r_negneg.s | 88 + sim/testsuite/sim/bfin/c_dsp32alu_rh_m.s | 263 + sim/testsuite/sim/bfin/c_dsp32alu_rh_p.s | 263 + sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_m.s | 258 + sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_p.s | 262 + sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_m.s | 258 + sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_p.s | 258 + sim/testsuite/sim/bfin/c_dsp32alu_rl_m.s | 263 + sim/testsuite/sim/bfin/c_dsp32alu_rl_p.s | 263 + sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_m.s | 261 + sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_p.s | 262 + sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_m.s | 262 + sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_p.s | 258 + sim/testsuite/sim/bfin/c_dsp32alu_rlh_rnd.s | 66 + sim/testsuite/sim/bfin/c_dsp32alu_rm.s | 262 + sim/testsuite/sim/bfin/c_dsp32alu_rmm.s | 264 + sim/testsuite/sim/bfin/c_dsp32alu_rmp.s | 264 + sim/testsuite/sim/bfin/c_dsp32alu_rp.s | 262 + sim/testsuite/sim/bfin/c_dsp32alu_rpm.s | 264 + sim/testsuite/sim/bfin/c_dsp32alu_rpp.s | 266 + sim/testsuite/sim/bfin/c_dsp32alu_rr_lph_a1a0.s | 33 + sim/testsuite/sim/bfin/c_dsp32alu_rrpm.s | 265 + sim/testsuite/sim/bfin/c_dsp32alu_rrpm_aa.s | 70 + sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp.s | 263 + sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft.s | 262 + sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft_x.s | 261 + sim/testsuite/sim/bfin/c_dsp32alu_rrppmm.s | 263 + sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft.s | 261 + sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft_x.s | 261 + sim/testsuite/sim/bfin/c_dsp32alu_saa.s | 70 + sim/testsuite/sim/bfin/c_dsp32alu_sat_aa.S | 41 + sim/testsuite/sim/bfin/c_dsp32alu_search.s | 74 + sim/testsuite/sim/bfin/c_dsp32alu_sgn.s | 39 + sim/testsuite/sim/bfin/c_dsp32mac_a1a0.s | 255 + sim/testsuite/sim/bfin/c_dsp32mac_a1a0_iuw32.s | 1014 + sim/testsuite/sim/bfin/c_dsp32mac_a1a0_m.s | 340 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a0.s | 124 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_i.s | 119 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_ih.s | 119 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_is.s | 119 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_iu.s | 119 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_m.s | 127 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_s.s | 119 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_t.s | 119 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_tu.s | 119 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_u.s | 119 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1.s | 213 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_i.s | 273 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_ih.s | 145 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_is.s | 145 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_iu.s | 145 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_m.s | 206 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_s.s | 145 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_t.s | 274 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_tu.s | 145 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_u.s | 170 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s | 157 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s | 157 + sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s | 157 + sim/testsuite/sim/bfin/c_dsp32mac_mix.s | 114 + sim/testsuite/sim/bfin/c_dsp32mac_pair_a0.s | 129 + sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_i.s | 247 + sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_is.s | 245 + sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_m.s | 129 + sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_s.s | 245 + sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_u.s | 245 + sim/testsuite/sim/bfin/c_dsp32mac_pair_a1.s | 127 + sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_i.s | 243 + sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_is.s | 243 + sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_m.s | 127 + sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_s.s | 243 + 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sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln_s.s | 423 + sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp.s | 423 + sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp_s.s | 423 + sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn.s | 423 + sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn_s.s | 424 + sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp.s | 423 + sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp_s.s | 423 + sim/testsuite/sim/bfin/c_dsp32shift_ahh.s | 430 + sim/testsuite/sim/bfin/c_dsp32shift_ahh_s.s | 430 + sim/testsuite/sim/bfin/c_dsp32shift_align16.s | 210 + sim/testsuite/sim/bfin/c_dsp32shift_align24.s | 210 + sim/testsuite/sim/bfin/c_dsp32shift_align8.s | 210 + sim/testsuite/sim/bfin/c_dsp32shift_amix.s | 142 + sim/testsuite/sim/bfin/c_dsp32shift_bitmux.s | 486 + sim/testsuite/sim/bfin/c_dsp32shift_bxor.s | 126 + sim/testsuite/sim/bfin/c_dsp32shift_expadj_h.s | 214 + sim/testsuite/sim/bfin/c_dsp32shift_expadj_l.s | 212 + sim/testsuite/sim/bfin/c_dsp32shift_expadj_r.s | 212 + sim/testsuite/sim/bfin/c_dsp32shift_expexp_r.s | 212 + sim/testsuite/sim/bfin/c_dsp32shift_fdepx.s | 210 + sim/testsuite/sim/bfin/c_dsp32shift_fextx.s | 210 + sim/testsuite/sim/bfin/c_dsp32shift_lf.s | 422 + sim/testsuite/sim/bfin/c_dsp32shift_lhalf_ln.s | 422 + sim/testsuite/sim/bfin/c_dsp32shift_lhalf_lp.s | 422 + sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rn.s | 425 + sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rp.s | 423 + sim/testsuite/sim/bfin/c_dsp32shift_lhh.s | 311 + sim/testsuite/sim/bfin/c_dsp32shift_lmix.s | 136 + sim/testsuite/sim/bfin/c_dsp32shift_ones.s | 214 + sim/testsuite/sim/bfin/c_dsp32shift_pack.s | 411 + sim/testsuite/sim/bfin/c_dsp32shift_rot.s | 427 + sim/testsuite/sim/bfin/c_dsp32shift_rot_mix.s | 437 + sim/testsuite/sim/bfin/c_dsp32shift_signbits_r.s | 214 + sim/testsuite/sim/bfin/c_dsp32shift_signbits_rh.s | 214 + sim/testsuite/sim/bfin/c_dsp32shift_signbits_rl.s | 210 + sim/testsuite/sim/bfin/c_dsp32shift_vmax.s | 113 + sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s | 113 + sim/testsuite/sim/bfin/c_dsp32shiftim_a0alr.s | 213 + sim/testsuite/sim/bfin/c_dsp32shiftim_af.s | 63 + sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s | 63 + sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln.s | 406 + sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln_s.s | 408 + sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp.s | 418 + sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp_s.s | 415 + sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn.s | 418 + sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn_s.s | 418 + sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp.s | 420 + sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp_s.s | 422 + sim/testsuite/sim/bfin/c_dsp32shiftim_ahh.s | 65 + sim/testsuite/sim/bfin/c_dsp32shiftim_ahh_s.s | 65 + sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s | 142 + sim/testsuite/sim/bfin/c_dsp32shiftim_lf.s | 63 + sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_ln.s | 401 + sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_lp.s | 418 + sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rn.s | 424 + sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rp.s | 421 + sim/testsuite/sim/bfin/c_dsp32shiftim_lhh.s | 65 + sim/testsuite/sim/bfin/c_dsp32shiftim_lmix.s | 138 + sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s | 62 + sim/testsuite/sim/bfin/c_dspldst_ld_dr_i.s | 168 + sim/testsuite/sim/bfin/c_dspldst_ld_dr_ipp.s | 348 + sim/testsuite/sim/bfin/c_dspldst_ld_dr_ippm.s | 328 + sim/testsuite/sim/bfin/c_dspldst_ld_drhi_i.s | 168 + sim/testsuite/sim/bfin/c_dspldst_ld_drhi_ipp.s | 364 + sim/testsuite/sim/bfin/c_dspldst_ld_drlo_i.s | 164 + sim/testsuite/sim/bfin/c_dspldst_ld_drlo_ipp.s | 355 + sim/testsuite/sim/bfin/c_dspldst_st_dr_i.s | 185 + sim/testsuite/sim/bfin/c_dspldst_st_dr_ipp.s | 326 + sim/testsuite/sim/bfin/c_dspldst_st_dr_ippm.s | 279 + sim/testsuite/sim/bfin/c_dspldst_st_drhi_i.s | 161 + sim/testsuite/sim/bfin/c_dspldst_st_drhi_ipp.s | 355 + sim/testsuite/sim/bfin/c_dspldst_st_drlo_i.s | 163 + sim/testsuite/sim/bfin/c_dspldst_st_drlo_ipp.s | 351 + sim/testsuite/sim/bfin/c_except_illopcode.S | 99 + sim/testsuite/sim/bfin/c_except_sys_sstep.S | 252 + sim/testsuite/sim/bfin/c_except_user_mode.S | 349 + sim/testsuite/sim/bfin/c_interr_disable.S | 323 + sim/testsuite/sim/bfin/c_interr_disable_enable.S | 344 + sim/testsuite/sim/bfin/c_interr_excpt.S | 290 + sim/testsuite/sim/bfin/c_interr_loopsetup_stld.S | 224 + sim/testsuite/sim/bfin/c_interr_nested.S | 289 + sim/testsuite/sim/bfin/c_interr_nmi.S | 318 + sim/testsuite/sim/bfin/c_interr_pending.S | 324 + sim/testsuite/sim/bfin/c_interr_pending_2.S | 268 + sim/testsuite/sim/bfin/c_interr_timer.S | 384 + sim/testsuite/sim/bfin/c_interr_timer_reload.S | 286 + sim/testsuite/sim/bfin/c_interr_timer_tcount.S | 242 + sim/testsuite/sim/bfin/c_interr_timer_tscale.S | 304 + sim/testsuite/sim/bfin/c_ldimmhalf_dreg.s | 60 + sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s | 85 + sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s | 89 + sim/testsuite/sim/bfin/c_ldimmhalf_h_dr.s | 82 + sim/testsuite/sim/bfin/c_ldimmhalf_h_ibml.s | 165 + sim/testsuite/sim/bfin/c_ldimmhalf_h_pr.s | 74 + sim/testsuite/sim/bfin/c_ldimmhalf_l_dr.s | 82 + sim/testsuite/sim/bfin/c_ldimmhalf_l_ibml.s | 165 + sim/testsuite/sim/bfin/c_ldimmhalf_l_pr.s | 76 + sim/testsuite/sim/bfin/c_ldimmhalf_lz_dr.s | 81 + sim/testsuite/sim/bfin/c_ldimmhalf_lz_ibml.s | 168 + sim/testsuite/sim/bfin/c_ldimmhalf_lz_pr.s | 72 + sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_dr.s | 113 + sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_ibml.s | 216 + sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_pr.s | 102 + sim/testsuite/sim/bfin/c_ldimmhalf_pibml.s | 212 + sim/testsuite/sim/bfin/c_ldst_ld_d_p.s | 372 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_b.s | 353 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_h.s | 351 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm.s | 417 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_b.s | 353 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_h.s | 330 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xb.s | 341 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xh.s | 355 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp.s | 371 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_b.s | 324 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_h.s | 350 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xb.s | 355 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xh.s | 333 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_ppmm_hbx.s | 656 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_xb.s | 326 + sim/testsuite/sim/bfin/c_ldst_ld_d_p_xh.s | 354 + sim/testsuite/sim/bfin/c_ldst_ld_p_p.s | 327 + sim/testsuite/sim/bfin/c_ldst_ld_p_p_mm.s | 406 + sim/testsuite/sim/bfin/c_ldst_ld_p_p_pp.s | 335 + sim/testsuite/sim/bfin/c_ldst_st_p_d.s | 299 + sim/testsuite/sim/bfin/c_ldst_st_p_d_b.s | 300 + sim/testsuite/sim/bfin/c_ldst_st_p_d_h.s | 280 + sim/testsuite/sim/bfin/c_ldst_st_p_d_mm.s | 601 + sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_b.s | 498 + sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_h.s | 554 + sim/testsuite/sim/bfin/c_ldst_st_p_d_pp.s | 804 + sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_b.s | 455 + sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_h.s | 457 + sim/testsuite/sim/bfin/c_ldst_st_p_p.s | 128 + sim/testsuite/sim/bfin/c_ldst_st_p_p_mm.s | 428 + sim/testsuite/sim/bfin/c_ldst_st_p_p_pp.s | 397 + sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_b.s | 554 + sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_h.s | 595 + sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xb.s | 594 + sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s | 595 + sim/testsuite/sim/bfin/c_ldstidxl_ld_dreg.s | 554 + sim/testsuite/sim/bfin/c_ldstidxl_ld_preg.s | 672 + sim/testsuite/sim/bfin/c_ldstidxl_st_dr_b.s | 612 + sim/testsuite/sim/bfin/c_ldstidxl_st_dr_h.s | 609 + sim/testsuite/sim/bfin/c_ldstidxl_st_dreg.s | 780 + sim/testsuite/sim/bfin/c_ldstidxl_st_preg.s | 709 + sim/testsuite/sim/bfin/c_ldstii_ld_dr_h.s | 541 + sim/testsuite/sim/bfin/c_ldstii_ld_dr_xh.s | 541 + sim/testsuite/sim/bfin/c_ldstii_ld_dreg.s | 540 + sim/testsuite/sim/bfin/c_ldstii_ld_preg.s | 564 + sim/testsuite/sim/bfin/c_ldstii_st_dr_h.s | 605 + sim/testsuite/sim/bfin/c_ldstii_st_dreg.s | 640 + sim/testsuite/sim/bfin/c_ldstii_st_preg.s | 603 + sim/testsuite/sim/bfin/c_ldstiifp_ld_dreg.s | 528 + sim/testsuite/sim/bfin/c_ldstiifp_ld_preg.s | 511 + sim/testsuite/sim/bfin/c_ldstiifp_st_dreg.s | 641 + sim/testsuite/sim/bfin/c_ldstiifp_st_preg.s | 618 + sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_hi.s | 411 + sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_lo.s | 410 + sim/testsuite/sim/bfin/c_ldstpmod_ld_dreg.s | 462 + sim/testsuite/sim/bfin/c_ldstpmod_ld_h_xh.s | 458 + sim/testsuite/sim/bfin/c_ldstpmod_ld_lohi.s | 462 + sim/testsuite/sim/bfin/c_ldstpmod_st_dr_hi.s | 400 + sim/testsuite/sim/bfin/c_ldstpmod_st_dr_lo.s | 401 + sim/testsuite/sim/bfin/c_ldstpmod_st_dreg.s | 623 + sim/testsuite/sim/bfin/c_ldstpmod_st_lohi.s | 625 + sim/testsuite/sim/bfin/c_linkage.s | 60 + sim/testsuite/sim/bfin/c_logi2op_alshft_mix.s | 143 + sim/testsuite/sim/bfin/c_logi2op_arith_shft.s | 223 + sim/testsuite/sim/bfin/c_logi2op_bitclr.s | 92 + sim/testsuite/sim/bfin/c_logi2op_bitset.s | 92 + sim/testsuite/sim/bfin/c_logi2op_bittgl.s | 165 + sim/testsuite/sim/bfin/c_logi2op_bittst.s | 583 + sim/testsuite/sim/bfin/c_logi2op_log_l_shft.s | 222 + .../sim/bfin/c_logi2op_log_l_shft_astat.S | 82 + sim/testsuite/sim/bfin/c_logi2op_log_r_shft.s | 222 + .../sim/bfin/c_logi2op_log_r_shft_astat.S | 82 + sim/testsuite/sim/bfin/c_logi2op_nbittst.s | 584 + sim/testsuite/sim/bfin/c_loopsetup_nested.s | 166 + sim/testsuite/sim/bfin/c_loopsetup_nested_bot.s | 165 + sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s | 184 + sim/testsuite/sim/bfin/c_loopsetup_nested_top.s | 166 + sim/testsuite/sim/bfin/c_loopsetup_overlap.s | 167 + sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc0.s | 95 + sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc1.s | 94 + sim/testsuite/sim/bfin/c_loopsetup_preg_lc0.s | 95 + sim/testsuite/sim/bfin/c_loopsetup_preg_lc1.s | 93 + sim/testsuite/sim/bfin/c_loopsetup_preg_stld.s | 194 + sim/testsuite/sim/bfin/c_loopsetup_prelc.s | 145 + sim/testsuite/sim/bfin/c_loopsetup_topbotcntr.s | 110 + sim/testsuite/sim/bfin/c_mmr_interr_ctl.s | 398 + sim/testsuite/sim/bfin/c_mmr_loop.S | 417 + sim/testsuite/sim/bfin/c_mmr_loop_user_except.S | 325 + sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S | 307 + sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S | 308 + sim/testsuite/sim/bfin/c_mmr_timer.S | 282 + sim/testsuite/sim/bfin/c_mode_supervisor.S | 287 + sim/testsuite/sim/bfin/c_mode_user.S | 338 + sim/testsuite/sim/bfin/c_mode_user_superivsor.S | 353 + sim/testsuite/sim/bfin/c_multi_issue_dsp_ld_ld.s | 197 + sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_1.s | 198 + sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_2.s | 198 + sim/testsuite/sim/bfin/c_progctrl_call_pcpr.s | 63 + sim/testsuite/sim/bfin/c_progctrl_call_pr.s | 32 + sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S | 330 + sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S | 280 + sim/testsuite/sim/bfin/c_progctrl_except_rtx.S | 96 + sim/testsuite/sim/bfin/c_progctrl_excpt.S | 261 + sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s | 58 + sim/testsuite/sim/bfin/c_progctrl_jump_pr.s | 56 + sim/testsuite/sim/bfin/c_progctrl_nop.s | 55 + sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S | 285 + sim/testsuite/sim/bfin/c_progctrl_rts.s | 36 + sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s | 163 + sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s | 162 + sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s | 167 + sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s | 213 + sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s | 203 + sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s | 173 + sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s | 83 + sim/testsuite/sim/bfin/c_regmv_acc_acc.s | 125 + sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s | 148 + sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s | 191 + sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s | 245 + sim/testsuite/sim/bfin/c_regmv_dr_dr.s | 209 + sim/testsuite/sim/bfin/c_regmv_dr_imlb.s | 539 + sim/testsuite/sim/bfin/c_regmv_dr_pr.s | 107 + sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s | 664 + sim/testsuite/sim/bfin/c_regmv_imlb_dep_stall.s | 335 + sim/testsuite/sim/bfin/c_regmv_imlb_dr.s | 313 + sim/testsuite/sim/bfin/c_regmv_imlb_imlb.s | 925 + sim/testsuite/sim/bfin/c_regmv_imlb_pr.s | 302 + sim/testsuite/sim/bfin/c_regmv_pr_dep_nostall.s | 280 + sim/testsuite/sim/bfin/c_regmv_pr_dep_stall.s | 237 + sim/testsuite/sim/bfin/c_regmv_pr_dr.s | 147 + sim/testsuite/sim/bfin/c_regmv_pr_imlb.s | 382 + sim/testsuite/sim/bfin/c_regmv_pr_pr.s | 95 + sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S | 342 + sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S | 359 + sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S | 359 + sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S | 341 + sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S | 377 + sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S | 393 + sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S | 375 + .../sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S | 377 + .../sim/bfin/c_seq_ex1_raise_call_mv_pop.S | 393 + sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S | 375 + sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S | 377 + sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S | 386 + sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S | 386 + sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S | 385 + .../sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S | 385 + sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S | 440 + sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S | 442 + sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S | 443 + .../sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S | 442 + sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S | 446 + .../sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S | 446 + sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S | 455 + sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S | 447 + sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S | 466 + sim/testsuite/sim/bfin/c_ujump.s | 52 + sim/testsuite/sim/bfin/cc-alu.S | 126 + sim/testsuite/sim/bfin/cc-astat-bits.s | 101 + sim/testsuite/sim/bfin/cc0.s | 30 + sim/testsuite/sim/bfin/cc1.s | 26 + sim/testsuite/sim/bfin/cc5.S | 90 + sim/testsuite/sim/bfin/cec-exact-exception.S | 54 + sim/testsuite/sim/bfin/cec-ifetch.S | 69 + sim/testsuite/sim/bfin/cec-multi-pending.S | 182 + sim/testsuite/sim/bfin/cec-no-snen-reti.S | 128 + sim/testsuite/sim/bfin/cec-non-operating-env.s | 37 + sim/testsuite/sim/bfin/cec-raise-reti.S | 111 + sim/testsuite/sim/bfin/cec-snen-reti.S | 122 + sim/testsuite/sim/bfin/cec-syscfg-ssstep.S | 72 + sim/testsuite/sim/bfin/cec-system-call.S | 64 + sim/testsuite/sim/bfin/cir.s | 20 + sim/testsuite/sim/bfin/cir1.s | 84 + sim/testsuite/sim/bfin/cli-sti.s | 25 + sim/testsuite/sim/bfin/cmpacc.s | 50 + sim/testsuite/sim/bfin/cmpdreg.S | 40 + sim/testsuite/sim/bfin/compare.s | 15 + sim/testsuite/sim/bfin/conv_enc_gen.s | 101 + sim/testsuite/sim/bfin/cycles.s | 41 + sim/testsuite/sim/bfin/d0.s | 31 + sim/testsuite/sim/bfin/d1.s | 17 + sim/testsuite/sim/bfin/d2.s | 56 + sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S | 545 + sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S | 544 + sim/testsuite/sim/bfin/dbg_jmp_src_kill.S | 543 + sim/testsuite/sim/bfin/dbg_tr_basic.S | 272 + sim/testsuite/sim/bfin/dbg_tr_simplejp.S | 267 + sim/testsuite/sim/bfin/dbg_tr_tbuf0.S | 262 + sim/testsuite/sim/bfin/dbg_tr_umode.S | 314 + sim/testsuite/sim/bfin/disalnexcpt_implicit.S | 122 + sim/testsuite/sim/bfin/div0.s | 37 + sim/testsuite/sim/bfin/divq.s | 1322 + sim/testsuite/sim/bfin/dotproduct.s | 304 + sim/testsuite/sim/bfin/dotproduct2.s | 299 + sim/testsuite/sim/bfin/double_prec_mult.s | 92 + sim/testsuite/sim/bfin/dsp_a4.s | 113 + sim/testsuite/sim/bfin/dsp_a7.s | 103 + sim/testsuite/sim/bfin/dsp_a8.s | 80 + sim/testsuite/sim/bfin/dsp_d0.s | 31 + sim/testsuite/sim/bfin/dsp_d1.s | 117 + sim/testsuite/sim/bfin/dsp_neg.S | 36 + sim/testsuite/sim/bfin/dsp_s1.s | 85 + sim/testsuite/sim/bfin/e0.s | 51 + sim/testsuite/sim/bfin/edn_snafu.s | 45 + sim/testsuite/sim/bfin/eu_dsp32mac_s.s | 38 + sim/testsuite/sim/bfin/events.s | 44 + sim/testsuite/sim/bfin/f221.s | 56 + sim/testsuite/sim/bfin/fact.s | 47 + sim/testsuite/sim/bfin/fir.s | 201 + sim/testsuite/sim/bfin/fsm.s | 57 + sim/testsuite/sim/bfin/greg2.s | 18 + sim/testsuite/sim/bfin/hwloop-bits.S | 104 + sim/testsuite/sim/bfin/hwloop-branch-in.s | 99 + sim/testsuite/sim/bfin/hwloop-branch-out.s | 129 + sim/testsuite/sim/bfin/hwloop-lt-bits.s | 25 + sim/testsuite/sim/bfin/hwloop-nested.s | 33 + sim/testsuite/sim/bfin/i0.s | 57 + sim/testsuite/sim/bfin/iir.s | 207 + sim/testsuite/sim/bfin/issue103.s | 34 + sim/testsuite/sim/bfin/issue109.s | 16 + sim/testsuite/sim/bfin/issue112.s | 38 + sim/testsuite/sim/bfin/issue113.s | 18 + sim/testsuite/sim/bfin/issue117.s | 19 + sim/testsuite/sim/bfin/issue118.s | 41 + sim/testsuite/sim/bfin/issue119.s | 26 + sim/testsuite/sim/bfin/issue121.s | 40 + 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sim/testsuite/sim/bfin/c_ccflag_dr_dr.s create mode 100644 sim/testsuite/sim/bfin/c_ccflag_dr_dr_uu.s create mode 100644 sim/testsuite/sim/bfin/c_ccflag_dr_imm3.s create mode 100644 sim/testsuite/sim/bfin/c_ccflag_dr_imm3_uu.s create mode 100644 sim/testsuite/sim/bfin/c_ccflag_pr_imm3.s create mode 100644 sim/testsuite/sim/bfin/c_ccflag_pr_imm3_uu.s create mode 100644 sim/testsuite/sim/bfin/c_ccflag_pr_pr.s create mode 100644 sim/testsuite/sim/bfin/c_ccflag_pr_pr_uu.s create mode 100644 sim/testsuite/sim/bfin/c_ccmv_cc_dr_dr.s create mode 100644 sim/testsuite/sim/bfin/c_ccmv_cc_dr_pr.s create mode 100644 sim/testsuite/sim/bfin/c_ccmv_cc_pr_pr.s create mode 100644 sim/testsuite/sim/bfin/c_ccmv_ncc_dr_dr.s create mode 100644 sim/testsuite/sim/bfin/c_ccmv_ncc_dr_pr.s create mode 100644 sim/testsuite/sim/bfin/c_ccmv_ncc_pr_pr.s create mode 100644 sim/testsuite/sim/bfin/c_comp3op_dr_and_dr.s create mode 100644 sim/testsuite/sim/bfin/c_comp3op_dr_minus_dr.s create mode 100644 sim/testsuite/sim/bfin/c_comp3op_dr_mix.s create mode 100644 sim/testsuite/sim/bfin/c_comp3op_dr_or_dr.s create mode 100644 sim/testsuite/sim/bfin/c_comp3op_dr_plus_dr.s create mode 100644 sim/testsuite/sim/bfin/c_comp3op_dr_xor_dr.s create mode 100644 sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh1.s create mode 100644 sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh2.s create mode 100644 sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_n.s create mode 100644 sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_p.s create mode 100644 sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_n.s create mode 100644 sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_p.s create mode 100644 sim/testsuite/sim/bfin/c_compi2opd_flags.S create mode 100644 sim/testsuite/sim/bfin/c_compi2opd_flags_2.S create mode 100644 sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_n.s create mode 100644 sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_p.s create mode 100644 sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_n.s create mode 100644 sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_p.s create mode 100644 sim/testsuite/sim/bfin/c_dagmodik_lnz_imgebl.s create mode 100644 sim/testsuite/sim/bfin/c_dagmodik_lnz_imltbl.s create mode 100644 sim/testsuite/sim/bfin/c_dagmodik_lz_inc_dec.s create mode 100644 sim/testsuite/sim/bfin/c_dagmodim_lnz_imgebl.s create mode 100644 sim/testsuite/sim/bfin/c_dagmodim_lnz_imltbl.s create mode 100644 sim/testsuite/sim/bfin/c_dagmodim_lz_inc_dec.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_a0_pm_a1.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_a0a1s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_a_abs_a.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_a_neg_a.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_aa_absabs.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_aa_negneg.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_abs.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_absabs.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_alhwx.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_awx.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_byteop1ew.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_byteop2.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_byteop3.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_bytepack.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_byteunpack.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_disalnexcpt.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_max.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_maxmax.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_min.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_minmin.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_mix.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_r_lh_a0pa1.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_r_negneg.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rh_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rh_p.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_p.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_p.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rl_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rl_p.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_p.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_p.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rlh_rnd.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rm.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rmm.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rmp.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rp.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rpm.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rpp.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rr_lph_a1a0.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rrpm.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rrpm_aa.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft_x.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rrppmm.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft_x.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_saa.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_sat_aa.S create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_search.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32alu_sgn.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_a1a0.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_a1a0_iuw32.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_a1a0_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a0.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_i.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_ih.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_is.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_iu.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_t.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_tu.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_u.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_i.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_ih.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_is.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_iu.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_t.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_tu.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_u.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_mix.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a0.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_i.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_is.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_u.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a1.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_i.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_is.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_u.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_i.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_is.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_u.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mac_pair_mix.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_i.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_ih.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_is.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_iu.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_m_i.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_m_iutsh.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_m_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_m_t.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_m_u.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_mix.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_t.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_tu.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_dr_u.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_pair.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_pair_i.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_pair_is.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_pair_m.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_pair_m_i.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_pair_m_is.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_pair_m_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_pair_m_u.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_pair_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32mult_pair_u.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_a0alr.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_af.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_af_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_ahh.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_ahh_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_align16.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_align24.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_align8.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_amix.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_bitmux.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_bxor.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_expadj_h.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_expadj_l.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_expadj_r.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_expexp_r.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_fdepx.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_fextx.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_lf.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_lhalf_ln.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_lhalf_lp.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rn.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rp.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_lhh.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_lmix.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_ones.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_pack.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_rot.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_rot_mix.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_signbits_r.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_signbits_rh.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_signbits_rl.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_vmax.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_a0alr.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_af.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_ahh.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_ahh_s.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_lf.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_ln.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_lp.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rn.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rp.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_lhh.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_lmix.s create mode 100644 sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_ld_dr_i.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_ld_dr_ipp.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_ld_dr_ippm.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_ld_drhi_i.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_ld_drhi_ipp.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_ld_drlo_i.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_ld_drlo_ipp.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_st_dr_i.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_st_dr_ipp.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_st_dr_ippm.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_st_drhi_i.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_st_drhi_ipp.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_st_drlo_i.s create mode 100644 sim/testsuite/sim/bfin/c_dspldst_st_drlo_ipp.s create mode 100644 sim/testsuite/sim/bfin/c_except_illopcode.S create mode 100644 sim/testsuite/sim/bfin/c_except_sys_sstep.S create mode 100644 sim/testsuite/sim/bfin/c_except_user_mode.S create mode 100644 sim/testsuite/sim/bfin/c_interr_disable.S create mode 100644 sim/testsuite/sim/bfin/c_interr_disable_enable.S create mode 100644 sim/testsuite/sim/bfin/c_interr_excpt.S create mode 100644 sim/testsuite/sim/bfin/c_interr_loopsetup_stld.S create mode 100644 sim/testsuite/sim/bfin/c_interr_nested.S create mode 100644 sim/testsuite/sim/bfin/c_interr_nmi.S create mode 100644 sim/testsuite/sim/bfin/c_interr_pending.S create mode 100644 sim/testsuite/sim/bfin/c_interr_pending_2.S create mode 100644 sim/testsuite/sim/bfin/c_interr_timer.S create mode 100644 sim/testsuite/sim/bfin/c_interr_timer_reload.S create mode 100644 sim/testsuite/sim/bfin/c_interr_timer_tcount.S create mode 100644 sim/testsuite/sim/bfin/c_interr_timer_tscale.S create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_dreg.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_h_dr.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_h_ibml.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_h_pr.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_l_dr.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_l_ibml.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_l_pr.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_lz_dr.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_lz_ibml.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_lz_pr.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_dr.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_ibml.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_pr.s create mode 100644 sim/testsuite/sim/bfin/c_ldimmhalf_pibml.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_b.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_h.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_b.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_h.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xb.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xh.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_b.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_h.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xb.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xh.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_ppmm_hbx.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_xb.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_d_p_xh.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_p_p.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_p_p_mm.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_ld_p_p_pp.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_st_p_d.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_st_p_d_b.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_st_p_d_h.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_st_p_d_mm.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_b.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_h.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_st_p_d_pp.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_b.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_h.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_st_p_p.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_st_p_p_mm.s create mode 100644 sim/testsuite/sim/bfin/c_ldst_st_p_p_pp.s create mode 100644 sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_b.s create mode 100644 sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_h.s create mode 100644 sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xb.s create mode 100644 sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s create mode 100644 sim/testsuite/sim/bfin/c_ldstidxl_ld_dreg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstidxl_ld_preg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstidxl_st_dr_b.s create mode 100644 sim/testsuite/sim/bfin/c_ldstidxl_st_dr_h.s create mode 100644 sim/testsuite/sim/bfin/c_ldstidxl_st_dreg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstidxl_st_preg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstii_ld_dr_h.s create mode 100644 sim/testsuite/sim/bfin/c_ldstii_ld_dr_xh.s create mode 100644 sim/testsuite/sim/bfin/c_ldstii_ld_dreg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstii_ld_preg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstii_st_dr_h.s create mode 100644 sim/testsuite/sim/bfin/c_ldstii_st_dreg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstii_st_preg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstiifp_ld_dreg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstiifp_ld_preg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstiifp_st_dreg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstiifp_st_preg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_hi.s create mode 100644 sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_lo.s create mode 100644 sim/testsuite/sim/bfin/c_ldstpmod_ld_dreg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstpmod_ld_h_xh.s create mode 100644 sim/testsuite/sim/bfin/c_ldstpmod_ld_lohi.s create mode 100644 sim/testsuite/sim/bfin/c_ldstpmod_st_dr_hi.s create mode 100644 sim/testsuite/sim/bfin/c_ldstpmod_st_dr_lo.s create mode 100644 sim/testsuite/sim/bfin/c_ldstpmod_st_dreg.s create mode 100644 sim/testsuite/sim/bfin/c_ldstpmod_st_lohi.s create mode 100644 sim/testsuite/sim/bfin/c_linkage.s create mode 100644 sim/testsuite/sim/bfin/c_logi2op_alshft_mix.s create mode 100644 sim/testsuite/sim/bfin/c_logi2op_arith_shft.s create mode 100644 sim/testsuite/sim/bfin/c_logi2op_bitclr.s create mode 100644 sim/testsuite/sim/bfin/c_logi2op_bitset.s create mode 100644 sim/testsuite/sim/bfin/c_logi2op_bittgl.s create mode 100644 sim/testsuite/sim/bfin/c_logi2op_bittst.s create mode 100644 sim/testsuite/sim/bfin/c_logi2op_log_l_shft.s create mode 100644 sim/testsuite/sim/bfin/c_logi2op_log_l_shft_astat.S create mode 100644 sim/testsuite/sim/bfin/c_logi2op_log_r_shft.s create mode 100644 sim/testsuite/sim/bfin/c_logi2op_log_r_shft_astat.S create mode 100644 sim/testsuite/sim/bfin/c_logi2op_nbittst.s create mode 100644 sim/testsuite/sim/bfin/c_loopsetup_nested.s create mode 100644 sim/testsuite/sim/bfin/c_loopsetup_nested_bot.s create mode 100644 sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s create mode 100644 sim/testsuite/sim/bfin/c_loopsetup_nested_top.s create mode 100644 sim/testsuite/sim/bfin/c_loopsetup_overlap.s create mode 100644 sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc0.s create mode 100644 sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc1.s create mode 100644 sim/testsuite/sim/bfin/c_loopsetup_preg_lc0.s create mode 100644 sim/testsuite/sim/bfin/c_loopsetup_preg_lc1.s create mode 100644 sim/testsuite/sim/bfin/c_loopsetup_preg_stld.s create mode 100644 sim/testsuite/sim/bfin/c_loopsetup_prelc.s create mode 100644 sim/testsuite/sim/bfin/c_loopsetup_topbotcntr.s create mode 100644 sim/testsuite/sim/bfin/c_mmr_interr_ctl.s create mode 100644 sim/testsuite/sim/bfin/c_mmr_loop.S create mode 100644 sim/testsuite/sim/bfin/c_mmr_loop_user_except.S create mode 100644 sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S create mode 100644 sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S create mode 100644 sim/testsuite/sim/bfin/c_mmr_timer.S create mode 100644 sim/testsuite/sim/bfin/c_mode_supervisor.S create mode 100644 sim/testsuite/sim/bfin/c_mode_user.S create mode 100644 sim/testsuite/sim/bfin/c_mode_user_superivsor.S create mode 100644 sim/testsuite/sim/bfin/c_multi_issue_dsp_ld_ld.s create mode 100644 sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_1.s create mode 100644 sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_2.s create mode 100644 sim/testsuite/sim/bfin/c_progctrl_call_pcpr.s create mode 100644 sim/testsuite/sim/bfin/c_progctrl_call_pr.s create mode 100644 sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S create mode 100644 sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S create mode 100644 sim/testsuite/sim/bfin/c_progctrl_except_rtx.S create mode 100644 sim/testsuite/sim/bfin/c_progctrl_excpt.S create mode 100644 sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s create mode 100644 sim/testsuite/sim/bfin/c_progctrl_jump_pr.s create mode 100644 sim/testsuite/sim/bfin/c_progctrl_nop.s create mode 100644 sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S create mode 100644 sim/testsuite/sim/bfin/c_progctrl_rts.s create mode 100644 sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s create mode 100644 sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s create mode 100644 sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s create mode 100644 sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s create mode 100644 sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s create mode 100644 sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s create mode 100644 sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_acc_acc.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_dr_dr.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_dr_imlb.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_dr_pr.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_imlb_dep_stall.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_imlb_dr.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_imlb_imlb.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_imlb_pr.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_pr_dep_nostall.s create mode 100644 sim/testsuite/sim/bfin/c_regmv_pr_dep_stall.s create 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sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S create mode 100644 sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S create mode 100644 sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S create mode 100644 sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S create mode 100644 sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S create mode 100644 sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S create mode 100644 sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S create mode 100644 sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S create mode 100644 sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S create mode 100644 sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S create mode 100644 sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S create mode 100644 sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S create mode 100644 sim/testsuite/sim/bfin/c_ujump.s create mode 100644 sim/testsuite/sim/bfin/cc-alu.S create mode 100644 sim/testsuite/sim/bfin/cc-astat-bits.s create mode 100644 sim/testsuite/sim/bfin/cc0.s create mode 100644 sim/testsuite/sim/bfin/cc1.s create mode 100644 sim/testsuite/sim/bfin/cc5.S create mode 100644 sim/testsuite/sim/bfin/cec-exact-exception.S create mode 100644 sim/testsuite/sim/bfin/cec-ifetch.S create mode 100644 sim/testsuite/sim/bfin/cec-multi-pending.S create mode 100644 sim/testsuite/sim/bfin/cec-no-snen-reti.S create mode 100644 sim/testsuite/sim/bfin/cec-non-operating-env.s create mode 100644 sim/testsuite/sim/bfin/cec-raise-reti.S create mode 100644 sim/testsuite/sim/bfin/cec-snen-reti.S create mode 100644 sim/testsuite/sim/bfin/cec-syscfg-ssstep.S create mode 100644 sim/testsuite/sim/bfin/cec-system-call.S create mode 100644 sim/testsuite/sim/bfin/cir.s create mode 100644 sim/testsuite/sim/bfin/cir1.s create mode 100644 sim/testsuite/sim/bfin/cli-sti.s create mode 100644 sim/testsuite/sim/bfin/cmpacc.s create mode 100644 sim/testsuite/sim/bfin/cmpdreg.S create mode 100644 sim/testsuite/sim/bfin/compare.s create mode 100644 sim/testsuite/sim/bfin/conv_enc_gen.s create mode 100644 sim/testsuite/sim/bfin/cycles.s create mode 100644 sim/testsuite/sim/bfin/d0.s create mode 100644 sim/testsuite/sim/bfin/d1.s create mode 100644 sim/testsuite/sim/bfin/d2.s create mode 100644 sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S create mode 100644 sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S create mode 100644 sim/testsuite/sim/bfin/dbg_jmp_src_kill.S create mode 100644 sim/testsuite/sim/bfin/dbg_tr_basic.S create mode 100644 sim/testsuite/sim/bfin/dbg_tr_simplejp.S create mode 100644 sim/testsuite/sim/bfin/dbg_tr_tbuf0.S create mode 100644 sim/testsuite/sim/bfin/dbg_tr_umode.S create mode 100644 sim/testsuite/sim/bfin/disalnexcpt_implicit.S create mode 100644 sim/testsuite/sim/bfin/div0.s create mode 100644 sim/testsuite/sim/bfin/divq.s create mode 100644 sim/testsuite/sim/bfin/dotproduct.s create mode 100644 sim/testsuite/sim/bfin/dotproduct2.s create mode 100644 sim/testsuite/sim/bfin/double_prec_mult.s create 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sim/testsuite/sim/bfin/lmu_excpt_default.S create mode 100644 sim/testsuite/sim/bfin/lmu_excpt_illaddr.S create mode 100644 sim/testsuite/sim/bfin/lmu_excpt_prot0.S create mode 100644 sim/testsuite/sim/bfin/lmu_excpt_prot1.S create mode 100644 sim/testsuite/sim/bfin/load.s create mode 100644 sim/testsuite/sim/bfin/logic.s create mode 100644 sim/testsuite/sim/bfin/loop_snafu.s create mode 100644 sim/testsuite/sim/bfin/loop_strncpy.s create mode 100644 sim/testsuite/sim/bfin/lp0.s create mode 100644 sim/testsuite/sim/bfin/lp1.s create mode 100644 sim/testsuite/sim/bfin/lsetup.s create mode 100644 sim/testsuite/sim/bfin/m0boundary.s create mode 100644 sim/testsuite/sim/bfin/m1.S create mode 100644 sim/testsuite/sim/bfin/m10.s create mode 100644 sim/testsuite/sim/bfin/m11.s create mode 100644 sim/testsuite/sim/bfin/m12.s create mode 100644 sim/testsuite/sim/bfin/m13.s create mode 100644 sim/testsuite/sim/bfin/m14.s create mode 100644 sim/testsuite/sim/bfin/m15.s create mode 100644 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sim/testsuite/sim/bfin/saatest.s create mode 100644 sim/testsuite/sim/bfin/se_all16bitopcodes.S create mode 100644 sim/testsuite/sim/bfin/se_all32bitopcodes.S create mode 100644 sim/testsuite/sim/bfin/se_all32bitopcodes.lds create mode 100644 sim/testsuite/sim/bfin/se_brtarget_stall.S create mode 100644 sim/testsuite/sim/bfin/se_bug_ui.S create mode 100644 sim/testsuite/sim/bfin/se_bug_ui2.S create mode 100644 sim/testsuite/sim/bfin/se_bug_ui3.S create mode 100644 sim/testsuite/sim/bfin/se_cc2stat_haz.S create mode 100644 sim/testsuite/sim/bfin/se_cc_kill.S create mode 100644 sim/testsuite/sim/bfin/se_cof.S create mode 100644 sim/testsuite/sim/bfin/se_event_quad.S create mode 100644 sim/testsuite/sim/bfin/se_excpt_dagprotviol.S create mode 100644 sim/testsuite/sim/bfin/se_excpt_ifprotviol.S create mode 100644 sim/testsuite/sim/bfin/se_excpt_ssstep.S create mode 100644 sim/testsuite/sim/bfin/se_illegalcombination.S create mode 100644 sim/testsuite/sim/bfin/se_kill_wbbr.S create mode 100644 sim/testsuite/sim/bfin/se_kills2.S create mode 100644 sim/testsuite/sim/bfin/se_loop_disable.S create mode 100644 sim/testsuite/sim/bfin/se_loop_kill.S create mode 100644 sim/testsuite/sim/bfin/se_loop_kill_01.S create mode 100644 sim/testsuite/sim/bfin/se_loop_kill_dcr.S create mode 100644 sim/testsuite/sim/bfin/se_loop_kill_dcr_01.S create mode 100644 sim/testsuite/sim/bfin/se_loop_lr.S create mode 100644 sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S create mode 100644 sim/testsuite/sim/bfin/se_loop_mv2lc.S create mode 100644 sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S create mode 100644 sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S create mode 100644 sim/testsuite/sim/bfin/se_loop_nest_ppm.S create mode 100644 sim/testsuite/sim/bfin/se_loop_nest_ppm_1.S create mode 100644 sim/testsuite/sim/bfin/se_loop_nest_ppm_2.S create mode 100644 sim/testsuite/sim/bfin/se_loop_ppm.S create mode 100644 sim/testsuite/sim/bfin/se_loop_ppm_1.S create mode 100644 sim/testsuite/sim/bfin/se_loop_ppm_int.S create mode 100644 sim/testsuite/sim/bfin/se_lsetup_kill.S create mode 100644 sim/testsuite/sim/bfin/se_misaligned_fetch.S create mode 100644 sim/testsuite/sim/bfin/se_more_ret_haz.S create mode 100644 sim/testsuite/sim/bfin/se_mv2lp.S create mode 100644 sim/testsuite/sim/bfin/se_oneins_zoff.S create mode 100644 sim/testsuite/sim/bfin/se_popkill.S create mode 100644 sim/testsuite/sim/bfin/se_regmv_usp_sysreg.S create mode 100644 sim/testsuite/sim/bfin/se_rets_hazard.s create mode 100644 sim/testsuite/sim/bfin/se_rts_rti.S create mode 100644 sim/testsuite/sim/bfin/se_ssstep_dagprotviol.S create mode 100644 sim/testsuite/sim/bfin/se_ssync.S create mode 100644 sim/testsuite/sim/bfin/se_stall_if2.S create mode 100644 sim/testsuite/sim/bfin/se_undefinedinstruction1.S create mode 100644 sim/testsuite/sim/bfin/se_undefinedinstruction2.S create mode 100644 sim/testsuite/sim/bfin/se_undefinedinstruction3.S create mode 100644 sim/testsuite/sim/bfin/se_undefinedinstruction4.S create mode 100644 sim/testsuite/sim/bfin/se_usermode_protviol.S create mode 100644 sim/testsuite/sim/bfin/seqstat.s create mode 100644 sim/testsuite/sim/bfin/sign.s create mode 100644 sim/testsuite/sim/bfin/simple0.s create mode 100644 sim/testsuite/sim/bfin/sri.s create mode 100644 sim/testsuite/sim/bfin/stk.s create mode 100644 sim/testsuite/sim/bfin/stk2.s create mode 100644 sim/testsuite/sim/bfin/stk3.s create mode 100644 sim/testsuite/sim/bfin/stk4.s create mode 100644 sim/testsuite/sim/bfin/stk5.s create mode 100644 sim/testsuite/sim/bfin/stk6.s create mode 100644 sim/testsuite/sim/bfin/syscfg.s create mode 100644 sim/testsuite/sim/bfin/tar10622.s create mode 100644 sim/testsuite/sim/bfin/test-dma.h create mode 100644 sim/testsuite/sim/bfin/test.h create mode 100644 sim/testsuite/sim/bfin/testset.s create mode 100644 sim/testsuite/sim/bfin/testset2.s create mode 100644 sim/testsuite/sim/bfin/testutils.inc create mode 100644 sim/testsuite/sim/bfin/unlink.S create mode 100644 sim/testsuite/sim/bfin/up0.s create mode 100644 sim/testsuite/sim/bfin/usp.S create mode 100644 sim/testsuite/sim/bfin/vec-abs-2.S create mode 100644 sim/testsuite/sim/bfin/vec-abs-3.S create mode 100644 sim/testsuite/sim/bfin/vec-abs.S create mode 100644 sim/testsuite/sim/bfin/vec-neg-2.S create mode 100644 sim/testsuite/sim/bfin/vec-neg-3.S create mode 100644 sim/testsuite/sim/bfin/vec-neg.S create mode 100644 sim/testsuite/sim/bfin/vecadd.s create mode 100644 sim/testsuite/sim/bfin/vit_max.s create mode 100644 sim/testsuite/sim/bfin/viterbi2.s create mode 100644 sim/testsuite/sim/bfin/wtf.s create mode 100644 sim/testsuite/sim/bfin/x1.s create mode 100644 sim/testsuite/sim/bfin/zcall.s create mode 100644 sim/testsuite/sim/bfin/zeroflagrnd.s diff --git a/sim/ChangeLog b/sim/ChangeLog index 02b05e1..599e9e9 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,8 @@ +2011-06-04 Mike Frysinger + + * configure.tgt (bfin-*-*): Add sim_testsuite=yes. + * configure: Regenerate. + 2011-05-04 Joseph Myers * configure.tgt (thumb*-*-* | strongarm*-*-* | xscale-*-*): Don't diff --git a/sim/configure b/sim/configure index 1cf0231..fd350d1 100755 --- a/sim/configure +++ b/sim/configure @@ -3646,6 +3646,7 @@ subdirs="$subdirs arm" subdirs="$subdirs bfin" + sim_testsuite=yes ;; cr16*-*-*) diff --git a/sim/configure.tgt b/sim/configure.tgt index bc34323..16303d5 100644 --- a/sim/configure.tgt +++ b/sim/configure.tgt @@ -25,6 +25,7 @@ case "${target}" in ;; bfin-*-*) SIM_ARCH(bfin) + sim_testsuite=yes ;; cr16*-*-*) SIM_ARCH(cr16) diff --git a/sim/testsuite/sim/bfin/10272_small.s b/sim/testsuite/sim/bfin/10272_small.s new file mode 100644 index 0000000..b260f9c --- /dev/null +++ b/sim/testsuite/sim/bfin/10272_small.s @@ -0,0 +1,51 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym P5, tmp0; + + r6=0xFF (Z); + W[p5+0x6] = r6; + + r0.l=0x0808; + r0.h=0xffff; + + R1 = W[P5 + 0x6 ] (X); + R0 = DEPOSIT(R1, R0); + W[P5+0x6] = R0; + + R5=W[P5+0x6] (X); + DBGA(r5.l,0xffff); + + /* This instruction order fails to successfully write R0 back */ + r0.l=0x0808; + r0.h=0xffff; + + loadsym P5, tmp0; + + r6=0xFF (Z); + W[p5+0x6] = r6; + R1 = W[P5 + 0x6 ] (X); + R0 = DEPOSIT(R1, R0); + W[P5+0x6] = R0; + + R5=W[P5+0x6] (X); + DBGA(r5.l,0xffff); + + r4=1; + loadsym P5, tmp0; + r6=0xFF (Z); + W[p5+0x6] = r6; + R1 = W[P5 + 0x6 ] (X); + R0 = R1+R4; + W[P5+0x6] = R0; + + R5=W[P5+0x6] (X); + DBGA(r5.l,0x100); + + pass; + + .data +tmp0: + .space (0x10); diff --git a/sim/testsuite/sim/bfin/10436.s b/sim/testsuite/sim/bfin/10436.s new file mode 100644 index 0000000..9975436 --- /dev/null +++ b/sim/testsuite/sim/bfin/10436.s @@ -0,0 +1,39 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym i0, tmp0; + + r1 = i0; + b0=i0; + r3=4; + l0=0; + m0=0; + + r5.l=0xdead; + r5.h=0xbeef; + + l0=r3; + [i0++] = r5; + l0 = 0; + r0 = i0; + + CC = R0 == R1; + if !CC JUMP _fail; + + l0=r3; + r3=[i0--]; + r0=i0; + + CC = R0 == R1; + if !CC JUMP _fail; + + pass + +_fail: + fail + + .data +tmp0: + .space (0x100); diff --git a/sim/testsuite/sim/bfin/10622.s b/sim/testsuite/sim/bfin/10622.s new file mode 100644 index 0000000..67076af --- /dev/null +++ b/sim/testsuite/sim/bfin/10622.s @@ -0,0 +1,21 @@ +# mach: bfin + +.include "testutils.inc" + start + + r2.l = 0x1234; + r2.h = 0xff90; + + r4=8; + i2=r2; + m2 = 4; + a0 = 0; + r1.l = (a0 += r4.l *r4.l) (IS) || I2 += m2 || nop; + + r0 = i2; + + dbga(r0.l, 0x1238); + dbga(r0.h, 0xff90); + +_halt0: + pass; diff --git a/sim/testsuite/sim/bfin/10742.s b/sim/testsuite/sim/bfin/10742.s new file mode 100644 index 0000000..67cb6c9 --- /dev/null +++ b/sim/testsuite/sim/bfin/10742.s @@ -0,0 +1,17 @@ +# mach: bfin + +.include "testutils.inc" + start + + + r5.h=0x1234; + r5.l=0x5678; + + p5 = r5; + p5.l = 0x1000; + + r0 = p5; + dbga(r0.h, 0x1234); + dbga(r0.l, 0x1000); + + pass diff --git a/sim/testsuite/sim/bfin/10799.s b/sim/testsuite/sim/bfin/10799.s new file mode 100644 index 0000000..76e1eb3 --- /dev/null +++ b/sim/testsuite/sim/bfin/10799.s @@ -0,0 +1,55 @@ +# mach: bfin + +.include "testutils.inc" + start + + fp = sp; + + [--SP]=RETS; + + loadsym R1, _b; + loadsym R2, _a; + R0 = R2; + + SP += -12; + R2 = 4; + + CALL _dot; + R1 = R0; + + R0 = 30; + dbga( r1.l, 0x1e); + + + pass + +_dot: + P0 = R1; + CC = R2 <= 0; + R3 = R0; + R0 = 0; + IF CC JUMP ._P1L1 (bp); + R0 = 1; + I0 = R3; + R0 = MAX (R0,R2) || R2 = [P0++] || NOP; + P1 = R0; + R0 = 0; + R1 = [I0++]; + LSETUP (._P1L4 , ._P1L5) LC0=P1; + +._P1L4: + R1 *= R2; +._P1L5: + R0= R0 + R1 (NS) || R2 = [P0++] || R1 = [I0++]; + +._P1L1: + RTS; + +.data; +_a: + .db 0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00; + .db 0x04,0x00,0x00,0x00; + +_b: + .db 0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00; + .db 0x04,0x00,0x00,0x00; diff --git a/sim/testsuite/sim/bfin/11080.s b/sim/testsuite/sim/bfin/11080.s new file mode 100644 index 0000000..c5652cc --- /dev/null +++ b/sim/testsuite/sim/bfin/11080.s @@ -0,0 +1,40 @@ +# Blackfin testcase for DISALGNEXCPT +# mach: bfin + +.include "testutils.inc" + start + + loadsym R0, foo; + R0 += 1; + I1 = R0; + + M0 = 4 (z); + + //dag0misalgn, dag1misalgn EXCAUSE value + R7 = 0x24 (z); + + // Get just the EXCAUSE field before + R5=SEQSTAT; + R5 = R5 << 26; + R5 = R5 >> 26; + + DISALGNEXCPT || R2 = [I1++M0]; // i1 = 0xff9004aa (misaligned) + + // Get just the EXCAUSE field after + R6=SEQSTAT; + R6 = R6 << 26; + R6 = R6 >> 26; + + // EXCAUSE of 0x24 == misaligned data memory access + CC = R6 == R7; + if CC jump _fail; + +_pass: + pass; + +_fail: + fail; + + .data +foo: + .space 0x10 diff --git a/sim/testsuite/sim/bfin/7641.s b/sim/testsuite/sim/bfin/7641.s new file mode 100644 index 0000000..864480c --- /dev/null +++ b/sim/testsuite/sim/bfin/7641.s @@ -0,0 +1,38 @@ +# Blackfin testcase for playing with TESTSET +# mach: bfin + + .include "testutils.inc" + + start + + loadsym P0, element1 + + loadsym P1, element2 + + R0 = B [P0]; // R0 should get 00 + R1 = B [P1]; // R1 should get 02 + + TESTSET(P0); // should set CC and MSB of memory byte + R0 = CC; + TESTSET(P1); // should clear CC and not change MSB of memory + R1 = CC; + + R2 = B [P0]; // R2 should get 80 + R3 = B [P1]; // R3 should get 02 + + dbga(R0.l,0x0001); + dbga(R0.h,0x0000); + dbga(R1.l,0x0000); + dbga(R1.h,0x0000); + dbga(R2.l,0x0080); + dbga(R2.h,0x0000); + dbga(R3.l,0x0082); + dbga(R3.h,0x0000); + + pass + +.data +.align 4; +element1: .long 0x0 +element2: .long 0x2 +element3: .long 0x4 diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog new file mode 100644 index 0000000..da2b202 --- /dev/null +++ b/sim/testsuite/sim/bfin/ChangeLog @@ -0,0 +1,243 @@ +2011-06-04 Mike Frysinger + + * .gitignore, 10272_small.s, 10436.s, 10622.s, 10742.s, 10799.s, + 11080.s, 7641.s, a0.s, a0shift.S, a10.s, a11.S, a12.s, a1.s, a20.S, + a21.s, a22.s, a23.s, a24.s, a25.s, a26.s, a2.s, a30.s, a3.s, a4.s, + a5.s, a6.s, a7.s, a8.s, a9.s, abs-2.S, abs-3.S, abs-4.S, abs_acc.s, + abs.S, acc-rot.s, acp5_19.s, acp5_4.s, add_imm7.s, add_shift.S, + add_sub_acc.s, addsub_flags.S, algnbug1.s, algnbug2.s, allinsn.exp, + argc.c, ashift_flags.s, ashift.s, b0.S, b1.s, b2.S, brcc.s, brevadd.s, + byteop16m.s, byteop16p.s, byteop1p.s, byteop2p.s, byteop3p.s, + byteunpack.s, c_alu2op_arith_r_sft.s, c_alu2op_conv_b.s, + c_alu2op_conv_h.s, c_alu2op_conv_mix.s, c_alu2op_conv_neg.s, + c_alu2op_conv_toggle.s, c_alu2op_conv_xb.s, c_alu2op_conv_xh.s, + c_alu2op_divq.s, c_alu2op_divs.s, c_alu2op_log_l_sft.s, + c_alu2op_log_r_sft.s, c_alu2op_shadd_1.s, c_alu2op_shadd_2.s, + c_brcc_bp1.s, c_brcc_bp2.s, c_brcc_bp3.s, c_brcc_bp4.s, + c_brcc_brf_bp.s, c_brcc_brf_brt_bp.s, c_brcc_brf_brt_nbp.s, + c_brcc_brf_fbkwd.s, c_brcc_brf_nbp.s, c_brcc_brt_bp.s, + c_brcc_brt_nbp.s, c_brcc_kills_dhits.s, c_brcc_kills_dmiss.s, + c_br_preg_killed_ac.s, c_br_preg_killed_ex1.s, c_br_preg_stall_ac.s, + c_br_preg_stall_ex1.s, cc0.s, cc1.s, cc5.S, c_cactrl_iflush_pr_pp.s, + c_cactrl_iflush_pr.s, c_calla_ljump.s, c_calla_subr.s, cc-alu.S, + cc-astat-bits.s, c_cc2dreg.s, c_cc2stat_cc_ac.S, c_cc2stat_cc_an.s, + c_cc2stat_cc_aq.s, c_cc2stat_cc_av0.S, c_cc2stat_cc_av1.S, + c_cc2stat_cc_az.s, c_ccflag_a0a1.S, c_cc_flag_ccmv_depend.S, + c_ccflag_dr_dr.s, c_ccflag_dr_dr_uu.s, c_cc_flagdreg_mvbrsft.s, + c_cc_flagdreg_mvbrsft_s1.s, c_cc_flagdreg_mvbrsft_sn.s, + c_ccflag_dr_imm3.s, c_ccflag_dr_imm3_uu.s, c_ccflag_pr_imm3.s, + c_ccflag_pr_imm3_uu.s, c_ccflag_pr_pr.s, c_ccflag_pr_pr_uu.s, + c_ccmv_cc_dr_dr.s, c_ccmv_cc_dr_pr.s, c_ccmv_cc_pr_pr.s, + c_ccmv_ncc_dr_dr.s, c_ccmv_ncc_dr_pr.s, c_ccmv_ncc_pr_pr.s, + c_cc_regmvlogi_mvbrsft.s, c_cc_regmvlogi_mvbrsft_s1.s, + c_cc_regmvlogi_mvbrsft_sn.S, c_comp3op_dr_and_dr.s, + c_comp3op_dr_minus_dr.s, c_comp3op_dr_mix.s, c_comp3op_dr_or_dr.s, + c_comp3op_dr_plus_dr.s, c_comp3op_dr_xor_dr.s, + c_comp3op_pr_plus_pr_sh1.s, c_comp3op_pr_plus_pr_sh2.s, + c_compi2opd_dr_add_i7_n.s, c_compi2opd_dr_add_i7_p.s, + c_compi2opd_dr_eq_i7_n.s, c_compi2opd_dr_eq_i7_p.s, + c_compi2opd_flags_2.S, c_compi2opd_flags.S, c_compi2opp_pr_add_i7_n.s, + c_compi2opp_pr_add_i7_p.s, c_compi2opp_pr_eq_i7_n.s, + c_compi2opp_pr_eq_i7_p.s, c_dagmodik_lnz_imgebl.s, + c_dagmodik_lnz_imltbl.s, c_dagmodik_lz_inc_dec.s, + c_dagmodim_lnz_imgebl.s, c_dagmodim_lnz_imltbl.s, + c_dagmodim_lz_inc_dec.s, c_dsp32alu_a0a1s.s, c_dsp32alu_a0_pm_a1.s, + c_dsp32alu_aa_absabs.s, c_dsp32alu_a_abs_a.s, c_dsp32alu_aa_negneg.s, + c_dsp32alu_absabs.s, c_dsp32alu_abs.s, c_dsp32alu_alhwx.s, + c_dsp32alu_a_neg_a.s, c_dsp32alu_awx.s, c_dsp32alu_byteop1ew.s, + c_dsp32alu_byteop2.s, c_dsp32alu_byteop3.s, c_dsp32alu_bytepack.s, + c_dsp32alu_byteunpack.s, c_dsp32alu_disalnexcpt.s, c_dsp32alu_maxmax.s, + c_dsp32alu_max.s, c_dsp32alu_minmin.s, c_dsp32alu_min.s, + c_dsp32alu_mix.s, c_dsp32alu_rh_m.s, c_dsp32alu_rh_p.s, + c_dsp32alu_rh_rnd12_m.s, c_dsp32alu_rh_rnd12_p.s, + c_dsp32alu_rh_rnd20_m.s, c_dsp32alu_rh_rnd20_p.s, + c_dsp32alu_r_lh_a0pa1.s, c_dsp32alu_rlh_rnd.s, c_dsp32alu_rl_m.s, + c_dsp32alu_rl_p.s, c_dsp32alu_rl_rnd12_m.s, c_dsp32alu_rl_rnd12_p.s, + c_dsp32alu_rl_rnd20_m.s, c_dsp32alu_rl_rnd20_p.s, c_dsp32alu_rmm.s, + c_dsp32alu_rmp.s, c_dsp32alu_rm.s, c_dsp32alu_r_negneg.s, + c_dsp32alu_rpm.s, c_dsp32alu_rpp.s, c_dsp32alu_rp.s, + c_dsp32alu_rr_lph_a1a0.s, c_dsp32alu_rrpm_aa.s, c_dsp32alu_rrpmmp.s, + c_dsp32alu_rrpmmp_sft.s, c_dsp32alu_rrpmmp_sft_x.s, c_dsp32alu_rrpm.s, + c_dsp32alu_rrppmm.s, c_dsp32alu_rrppmm_sft.s, + c_dsp32alu_rrppmm_sft_x.s, c_dsp32alu_saa.s, c_dsp32alu_sat_aa.S, + c_dsp32alu_search.s, c_dsp32alu_sgn.s, c_dsp32mac_a1a0_iuw32.s, + c_dsp32mac_a1a0_m.s, c_dsp32mac_a1a0.s, c_dsp32mac_dr_a0_ih.s, + c_dsp32mac_dr_a0_i.s, c_dsp32mac_dr_a0_is.s, c_dsp32mac_dr_a0_iu.s, + c_dsp32mac_dr_a0_m.s, c_dsp32mac_dr_a0.s, c_dsp32mac_dr_a0_s.s, + c_dsp32mac_dr_a0_t.s, c_dsp32mac_dr_a0_tu.s, c_dsp32mac_dr_a0_u.s, + c_dsp32mac_dr_a1a0_iutsh.s, c_dsp32mac_dr_a1a0_m.s, + c_dsp32mac_dr_a1a0.s, c_dsp32mac_dr_a1_ih.s, c_dsp32mac_dr_a1_i.s, + c_dsp32mac_dr_a1_is.s, c_dsp32mac_dr_a1_iu.s, c_dsp32mac_dr_a1_m.s, + c_dsp32mac_dr_a1.s, c_dsp32mac_dr_a1_s.s, c_dsp32mac_dr_a1_t.s, + c_dsp32mac_dr_a1_tu.s, c_dsp32mac_dr_a1_u.s, c_dsp32mac_mix.s, + c_dsp32mac_pair_a0_i.s, c_dsp32mac_pair_a0_is.s, + c_dsp32mac_pair_a0_m.s, c_dsp32mac_pair_a0.s, c_dsp32mac_pair_a0_s.s, + c_dsp32mac_pair_a0_u.s, c_dsp32mac_pair_a1a0_i.s, + c_dsp32mac_pair_a1a0_is.s, c_dsp32mac_pair_a1a0_m.s, + c_dsp32mac_pair_a1a0.s, c_dsp32mac_pair_a1a0_s.s, + c_dsp32mac_pair_a1a0_u.s, c_dsp32mac_pair_a1_i.s, + c_dsp32mac_pair_a1_is.s, c_dsp32mac_pair_a1_m.s, c_dsp32mac_pair_a1.s, + c_dsp32mac_pair_a1_s.s, c_dsp32mac_pair_a1_u.s, c_dsp32mac_pair_mix.s, + c_dsp32mult_dr_ih.s, c_dsp32mult_dr_i.s, c_dsp32mult_dr_is.s, + c_dsp32mult_dr_iu.s, c_dsp32mult_dr_m_i.s, c_dsp32mult_dr_m_iutsh.s, + c_dsp32mult_dr_mix.s, c_dsp32mult_dr_m.s, c_dsp32mult_dr_m_s.s, + c_dsp32mult_dr_m_t.s, c_dsp32mult_dr_m_u.s, c_dsp32mult_dr.s, + c_dsp32mult_dr_s.s, c_dsp32mult_dr_t.s, c_dsp32mult_dr_tu.s, + c_dsp32mult_dr_u.s, c_dsp32mult_pair_i.s, c_dsp32mult_pair_is.s, + c_dsp32mult_pair_m_i.s, c_dsp32mult_pair_m_is.s, c_dsp32mult_pair_m.s, + c_dsp32mult_pair_m_s.s, c_dsp32mult_pair_m_u.s, c_dsp32mult_pair.s, + c_dsp32mult_pair_s.s, c_dsp32mult_pair_u.s, c_dsp32shift_a0alr.s, + c_dsp32shift_af.s, c_dsp32shift_af_s.s, c_dsp32shift_ahalf_ln.s, + c_dsp32shift_ahalf_ln_s.s, c_dsp32shift_ahalf_lp.s, + c_dsp32shift_ahalf_lp_s.s, c_dsp32shift_ahalf_rn.s, + c_dsp32shift_ahalf_rn_s.s, c_dsp32shift_ahalf_rp.s, + c_dsp32shift_ahalf_rp_s.s, c_dsp32shift_ahh.s, c_dsp32shift_ahh_s.s, + c_dsp32shift_align16.s, c_dsp32shift_align24.s, c_dsp32shift_align8.s, + c_dsp32shift_amix.s, c_dsp32shift_bitmux.s, c_dsp32shift_bxor.s, + c_dsp32shift_expadj_h.s, c_dsp32shift_expadj_l.s, + c_dsp32shift_expadj_r.s, c_dsp32shift_expexp_r.s, c_dsp32shift_fdepx.s, + c_dsp32shift_fextx.s, c_dsp32shiftim_a0alr.s, c_dsp32shiftim_af.s, + c_dsp32shiftim_af_s.s, c_dsp32shiftim_ahalf_ln.s, + c_dsp32shiftim_ahalf_ln_s.s, c_dsp32shiftim_ahalf_lp.s, + c_dsp32shiftim_ahalf_lp_s.s, c_dsp32shiftim_ahalf_rn.s, + c_dsp32shiftim_ahalf_rn_s.s, c_dsp32shiftim_ahalf_rp.s, + c_dsp32shiftim_ahalf_rp_s.s, c_dsp32shiftim_ahh.s, + c_dsp32shiftim_ahh_s.s, c_dsp32shiftim_amix.s, c_dsp32shiftim_lf.s, + c_dsp32shiftim_lhalf_ln.s, c_dsp32shiftim_lhalf_lp.s, + c_dsp32shiftim_lhalf_rn.s, c_dsp32shiftim_lhalf_rp.s, + c_dsp32shiftim_lhh.s, c_dsp32shiftim_lmix.s, c_dsp32shiftim_rot.s, + c_dsp32shift_lf.s, c_dsp32shift_lhalf_ln.s, c_dsp32shift_lhalf_lp.s, + c_dsp32shift_lhalf_rn.s, c_dsp32shift_lhalf_rp.s, c_dsp32shift_lhh.s, + c_dsp32shift_lmix.s, c_dsp32shift_ones.s, c_dsp32shift_pack.s, + c_dsp32shift_rot_mix.s, c_dsp32shift_rot.s, c_dsp32shift_signbits_rh.s, + c_dsp32shift_signbits_rl.s, c_dsp32shift_signbits_r.s, + c_dsp32shift_vmax.s, c_dsp32shift_vmaxvmax.s, c_dspldst_ld_drhi_ipp.s, + c_dspldst_ld_drhi_i.s, c_dspldst_ld_dr_ippm.s, c_dspldst_ld_dr_ipp.s, + c_dspldst_ld_dr_i.s, c_dspldst_ld_drlo_ipp.s, c_dspldst_ld_drlo_i.s, + c_dspldst_st_drhi_ipp.s, c_dspldst_st_drhi_i.s, c_dspldst_st_dr_ippm.s, + c_dspldst_st_dr_ipp.s, c_dspldst_st_dr_i.s, c_dspldst_st_drlo_ipp.s, + c_dspldst_st_drlo_i.s, cec-exact-exception.S, cec-ifetch.S, + cec-multi-pending.S, cec-non-operating-env.s, cec-no-snen-reti.S, + cec-raise-reti.S, cec-snen-reti.S, cec-syscfg-ssstep.S, + cec-system-call.S, c_except_illopcode.S, c_except_sys_sstep.S, + c_except_user_mode.S, c_interr_disable_enable.S, c_interr_disable.S, + c_interr_excpt.S, c_interr_loopsetup_stld.S, c_interr_nested.S, + c_interr_nmi.S, c_interr_pending_2.S, c_interr_pending.S, + c_interr_timer_reload.S, c_interr_timer.S, c_interr_timer_tcount.S, + c_interr_timer_tscale.S, cir1.s, cir.s, c_ldimmhalf_dreg.s, + c_ldimmhalf_drhi.s, c_ldimmhalf_drlo.s, c_ldimmhalf_h_dr.s, + c_ldimmhalf_h_ibml.s, c_ldimmhalf_h_pr.s, c_ldimmhalf_l_dr.s, + c_ldimmhalf_l_ibml.s, c_ldimmhalf_l_pr.s, c_ldimmhalf_lz_dr.s, + c_ldimmhalf_lzhi_dr.s, c_ldimmhalf_lzhi_ibml.s, c_ldimmhalf_lzhi_pr.s, + c_ldimmhalf_lz_ibml.s, c_ldimmhalf_lz_pr.s, c_ldimmhalf_pibml.s, + c_ldstidxl_ld_dr_b.s, c_ldstidxl_ld_dreg.s, c_ldstidxl_ld_dr_h.s, + c_ldstidxl_ld_dr_xb.s, c_ldstidxl_ld_dr_xh.s, c_ldstidxl_ld_preg.s, + c_ldstidxl_st_dr_b.s, c_ldstidxl_st_dreg.s, c_ldstidxl_st_dr_h.s, + c_ldstidxl_st_preg.s, c_ldstiifp_ld_dreg.s, c_ldstiifp_ld_preg.s, + c_ldstiifp_st_dreg.s, c_ldstiifp_st_preg.s, c_ldstii_ld_dreg.s, + c_ldstii_ld_dr_h.s, c_ldstii_ld_dr_xh.s, c_ldstii_ld_preg.s, + c_ldstii_st_dreg.s, c_ldstii_st_dr_h.s, c_ldstii_st_preg.s, + c_ldst_ld_d_p_b.s, c_ldst_ld_d_p_h.s, c_ldst_ld_d_p_mm_b.s, + c_ldst_ld_d_p_mm_h.s, c_ldst_ld_d_p_mm.s, c_ldst_ld_d_p_mm_xb.s, + c_ldst_ld_d_p_mm_xh.s, c_ldst_ld_d_p_pp_b.s, c_ldst_ld_d_p_pp_h.s, + c_ldst_ld_d_p_ppmm_hbx.s, c_ldst_ld_d_p_pp.s, c_ldst_ld_d_p_pp_xb.s, + c_ldst_ld_d_p_pp_xh.s, c_ldst_ld_d_p.s, c_ldst_ld_d_p_xb.s, + c_ldst_ld_d_p_xh.s, c_ldst_ld_p_p_mm.s, c_ldst_ld_p_p_pp.s, + c_ldst_ld_p_p.s, c_ldstpmod_ld_dreg.s, c_ldstpmod_ld_dr_hi.s, + c_ldstpmod_ld_dr_lo.s, c_ldstpmod_ld_h_xh.s, c_ldstpmod_ld_lohi.s, + c_ldstpmod_st_dreg.s, c_ldstpmod_st_dr_hi.s, c_ldstpmod_st_dr_lo.s, + c_ldstpmod_st_lohi.s, c_ldst_st_p_d_b.s, c_ldst_st_p_d_h.s, + c_ldst_st_p_d_mm_b.s, c_ldst_st_p_d_mm_h.s, c_ldst_st_p_d_mm.s, + c_ldst_st_p_d_pp_b.s, c_ldst_st_p_d_pp_h.s, c_ldst_st_p_d_pp.s, + c_ldst_st_p_d.s, c_ldst_st_p_p_mm.s, c_ldst_st_p_p_pp.s, + c_ldst_st_p_p.s, c_linkage.s, cli-sti.s, c_logi2op_alshft_mix.s, + c_logi2op_arith_shft.s, c_logi2op_bitclr.s, c_logi2op_bitset.s, + c_logi2op_bittgl.s, c_logi2op_bittst.s, c_logi2op_log_l_shft_astat.S, + c_logi2op_log_l_shft.s, c_logi2op_log_r_shft_astat.S, + c_logi2op_log_r_shft.s, c_logi2op_nbittst.s, c_loopsetup_nested_bot.s, + c_loopsetup_nested_prelc.s, c_loopsetup_nested.s, + c_loopsetup_nested_top.s, c_loopsetup_overlap.s, + c_loopsetup_preg_div2_lc0.s, c_loopsetup_preg_div2_lc1.s, + c_loopsetup_preg_lc0.s, c_loopsetup_preg_lc1.s, + c_loopsetup_preg_stld.s, c_loopsetup_prelc.s, c_loopsetup_topbotcntr.s, + c_mmr_interr_ctl.s, c_mmr_loop.S, c_mmr_loop_user_except.S, + c_mmr_ppop_illegal_adr.S, c_mmr_ppopm_illegal_adr.S, c_mmr_timer.S, + c_mode_supervisor.S, c_mode_user.S, c_mode_user_superivsor.S, cmpacc.s, + cmpdreg.S, c_multi_issue_dsp_ld_ld.s, c_multi_issue_dsp_ldst_1.s, + c_multi_issue_dsp_ldst_2.s, compare.s, conv_enc_gen.s, + c_progctrl_call_pcpr.s, c_progctrl_call_pr.s, + c_progctrl_clisti_interr.S, c_progctrl_csync_mmr.S, + c_progctrl_except_rtx.S, c_progctrl_excpt.S, c_progctrl_jump_pcpr.s, + c_progctrl_jump_pr.s, c_progctrl_nop.s, c_progctrl_raise_rt_i_n.S, + c_progctrl_rts.s, c_ptr2op_pr_neg_pr.s, c_ptr2op_pr_sft_2_1.s, + c_ptr2op_pr_shadd_1_2.s, c_pushpopmultiple_dp_pair.s, + c_pushpopmultiple_dp.s, c_pushpopmultiple_dreg.s, + c_pushpopmultiple_preg.s, c_regmv_acc_acc.s, c_regmv_dag_lz_dep.s, + c_regmv_dr_acc_acc.s, c_regmv_dr_dep_nostall.s, c_regmv_dr_dr.s, + c_regmv_dr_imlb.s, c_regmv_dr_pr.s, c_regmv_imlb_dep_nostall.s, + c_regmv_imlb_dep_stall.s, c_regmv_imlb_dr.s, c_regmv_imlb_imlb.s, + c_regmv_imlb_pr.s, c_regmv_pr_dep_nostall.s, c_regmv_pr_dep_stall.s, + c_regmv_pr_dr.s, c_regmv_pr_imlb.s, c_regmv_pr_pr.s, + c_seq_ac_raise_mv_ppop.S, c_seq_ac_raise_mv.S, + c_seq_ac_regmv_pushpop.S, c_seq_dec_raise_pushpop.S, + c_seq_ex1_brcc_mv_pop.S, c_seq_ex1_call_mv_pop.S, c_seq_ex1_j_mv_pop.S, + c_seq_ex1_raise_brcc_mv_pop.S, c_seq_ex1_raise_call_mv_pop.S, + c_seq_ex1_raise_j_mv_pop.S, c_seq_ex2_brcc_mp_mv_pop.S, + c_seq_ex2_mmrj_mvpop.S, c_seq_ex2_mmr_mvpop.S, + c_seq_ex2_raise_mmrj_mvpop.S, c_seq_ex2_raise_mmr_mvpop.S, + c_seq_ex3_ls_brcc_mvp.S, c_seq_ex3_ls_mmrj_mvp.S, + c_seq_ex3_ls_mmr_mvp.S, c_seq_ex3_raise_ls_mmrj_mvp.S, + c_seq_wb_cs_lsmmrj_mvp.S, c_seq_wb_raisecs_lsmmrj_mvp.S, + c_seq_wb_rti_lsmmrj_mvp.S, c_seq_wb_rtn_lsmmrj_mvp.S, + c_seq_wb_rtx_lsmmrj_mvp.S, c_ujump.s, cycles.s, d0.s, d1.s, d2.s, + dbg_brprd_ntkn_src_kill.S, dbg_brtkn_nprd_src_kill.S, + dbg_jmp_src_kill.S, dbg_tr_basic.S, dbg_tr_simplejp.S, dbg_tr_tbuf0.S, + dbg_tr_umode.S, disalnexcpt_implicit.S, div0.s, divq.s, dotproduct2.s, + dotproduct.s, double_prec_mult.s, dsp_a4.s, dsp_a7.s, dsp_a8.s, + dsp_d0.s, dsp_d1.s, dsp_neg.S, dsp_s1.s, e0.s, edn_snafu.s, + eu_dsp32mac_s.s, events.s, f221.s, fact.s, fir.s, fsm.s, greg2.s, + hwloop-bits.S, hwloop-branch-in.s, hwloop-branch-out.s, + hwloop-lt-bits.s, hwloop-nested.s, i0.s, iir.s, issue103.s, issue109.s, + issue112.s, issue113.s, issue117.s, issue118.s, issue119.s, issue121.s, + issue123.s, issue124.s, issue125.s, issue126.s, issue127.s, issue129.s, + issue139.S, issue140.S, issue142.s, issue144.s, issue146.S, issue175.s, + issue205.s, issue257.s, issue272.S, issue83.s, issue89.s, l0.s, + l0shift.s, l2_loop.s, link-2.s, link.s, lmu_cplb_multiple0.S, + lmu_cplb_multiple1.S, lmu_excpt_align.S, lmu_excpt_default.S, + lmu_excpt_illaddr.S, lmu_excpt_prot0.S, lmu_excpt_prot1.S, load.s, + logic.s, loop_snafu.s, loop_strncpy.s, lp0.s, lp1.s, lsetup.s, + m0boundary.s, m10.s, m11.s, m12.s, m13.s, m14.s, m15.s, m16.s, m17.s, + m1.S, m2.s, m3.s, m4.s, m5.s, m6.s, m7.s, m8.s, m9.s, mac2halfreg.S, + Makefile, math.s, max_min_flags.s, mc_s2.s, mdma-32bit-1d.c, + mdma-32bit-1d-neg-count.c, mdma-8bit-1d.c, mdma-8bit-1d-neg-count.c, + mdma-skel.h, mem3.s, mmr-exception.s, move.s, msa_acp_5_10.s, + msa_acp_5.10.S, msa_acp_5.12_1.S, msa_acp_5.12_2.S, mult.s, neg-2.S, + neg-3.S, neg.S, nshift.s, PN_generator.s, pr.s, push-pop-multiple.s, + pushpopreg_1.s, push-pop.s, quadaddsub.s, random_0001.s, random_0002.S, + random_0003.S, random_0004.S, random_0005.S, random_0006.S, + random_0007.S, random_0008.S, random_0009.S, random_0010.S, + random_0011.S, random_0012.S, random_0013.S, random_0031.S, + random_0033.S, random_0034.S, run-tests.sh, s0.s, s10.s, s11.s, s12.s, + s13.s, s14.s, s15.s, s16.s, s17.s, s18.s, s19.s, s1.s, s20.s, s21.s, + s2.s, s30.s, s3.s, s4.s, s5.s, s6.s, s7.s, s8.s, s9.s, saatest.s, + se_all16bitopcodes.S, se_all32bitopcodes.lds, se_all32bitopcodes.S, + se_brtarget_stall.S, se_bug_ui2.S, se_bug_ui3.S, se_bug_ui.S, + se_cc2stat_haz.S, se_cc_kill.S, se_cof.S, se_event_quad.S, + se_excpt_dagprotviol.S, se_excpt_ifprotviol.S, se_excpt_ssstep.S, + se_illegalcombination.S, se_kills2.S, se_kill_wbbr.S, + se_loop_disable.S, se_loop_kill_01.S, se_loop_kill_dcr_01.S, + se_loop_kill_dcr.S, se_loop_kill.S, se_loop_lr.S, + se_loop_mv2lb_stall.S, se_loop_mv2lc.S, se_loop_mv2lc_stall.S, + se_loop_mv2lt_stall.S, se_loop_nest_ppm_1.S, se_loop_nest_ppm_2.S, + se_loop_nest_ppm.S, se_loop_ppm_1.S, se_loop_ppm_int.S, se_loop_ppm.S, + se_lsetup_kill.S, se_misaligned_fetch.S, se_more_ret_haz.S, se_mv2lp.S, + se_oneins_zoff.S, se_popkill.S, seqstat.s, se_regmv_usp_sysreg.S, + se_rets_hazard.s, se_rts_rti.S, se_ssstep_dagprotviol.S, se_ssync.S, + se_stall_if2.S, se_undefinedinstruction1.S, se_undefinedinstruction2.S, + se_undefinedinstruction3.S, se_undefinedinstruction4.S, + se_usermode_protviol.S, sign.s, simple0.s, sri.s, stk2.s, stk3.s, + stk4.s, stk5.s, stk6.s, stk.s, syscfg.s, tar10622.s, test-dma.h, + test.h, testset2.s, testset.s, testutils.inc, unlink.S, up0.s, usp.S, + vec-abs-2.S, vec-abs-3.S, vec-abs.S, vecadd.s, vec-neg-2.S, + vec-neg-3.S, vec-neg.S, viterbi2.s, vit_max.s, wtf.s, x1.s, zcall.s, + zeroflagrnd.s: New files. diff --git a/sim/testsuite/sim/bfin/PN_generator.s b/sim/testsuite/sim/bfin/PN_generator.s new file mode 100644 index 0000000..7d92b85 --- /dev/null +++ b/sim/testsuite/sim/bfin/PN_generator.s @@ -0,0 +1,78 @@ +# mach: bfin + +// GENERIC PN SEQUENCE GENERATOR +// Linear Feedback Shift Register +// ------------------------------- +// This solution implements an LFSR by applying an XOR reduction +// function to the 40 bit accumulator, XORing the contents of the +// CC bit, shifting by one the accumulator, and inserting the +// resulting bit on the open bit slot. +// CC --> ----- XOR-------------------------- +// | | | | | | +// | | | | | | +// +------------------------------+ v +// | b0 b1 b2 b3 b38 b39 | in <-- by one +// +------------------------------+ +// after: +// +------------------------------+ +// | b1 b2 b3 b38 b39 in | +// +------------------------------+ +// The program shown here is a PN sequence generator, and hence +// does not take any input other than the initial state. However, +// in order to accept an input, one simply needs to rotate the +// input sequence via CC prior to applying the XOR reduction. + +.include "testutils.inc" + start + + loadsym P1, output; + init_r_regs 0; + ASTAT = R0; + +// load Polynomial into A1 + A1 = A0 = 0; + R0.L = 0x1cd4; + R0.H = 0xab18; + A1.w = R0; + R0.L = 0x008d; + A1.x = R0.L; + +// load InitState into A0 + R0.L = 0x0001; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + + P4 = 4; + LSETUP ( l$0 , l$0end ) LC0 = P4; + l$0: // **** START l-LOOP ***** + + P4 = 32; + LSETUP ( m$1 , m$1 ) LC1 = P4; // **** START m-LOOP ***** + m$1: + A0 = BXORSHIFT( A0 , A1, CC ); + +// store 16 bits of outdata RL1 + R1 = A0.w; + l$0end: + [ P1 ++ ] = R1; + +// Check results + loadsym I2, output; + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5adf ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x2fc9 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0xbd91 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5520 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x80d5 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x7fef ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x34d1 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x915c ); + pass + + .data; +output: + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/a0.s b/sim/testsuite/sim/bfin/a0.s new file mode 100644 index 0000000..3bc78d6 --- /dev/null +++ b/sim/testsuite/sim/bfin/a0.s @@ -0,0 +1,17 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 1; + R0 <<= 1; + DBGA ( R0.L , 2 ); + R0 <<= 1; + DBGA ( R0.L , 4 ); + R0 <<= 3; + DBGA ( R0.L , 32 ); + R0 += 5; + DBGA ( R0.L , 37 ); + R0 += -7; + DBGA ( R0.L , 30 ); + pass diff --git a/sim/testsuite/sim/bfin/a0shift.S b/sim/testsuite/sim/bfin/a0shift.S new file mode 100644 index 0000000..18bfcbd --- /dev/null +++ b/sim/testsuite/sim/bfin/a0shift.S @@ -0,0 +1,169 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + +// 0xfffffe371c + r0 = 0; + r1 = 0; + r2 = 0; + r3 = 0; + r4 = 0; + r5 = 0; + r6 = 0; + r7 = 0; + a1 = a0 =0; + astat = R0; + + R6.L = 0x8000; + R5.H = 0x8000; + +// load acc with values; + R0.L = 0xc062; + R0.H = 0xffee; + A0.w = R0; + R0.L = 0xc52c; + A0.x = R0; + R0.L = 0x8d10; + R0.H = 0x34c; + A1.w = R0; + R0.L = 0xe10c; + A1.x = R0; +// load regs with values; + R0.L = 0xe844; + R0.H = 0x4aba; + R1.L = 0xa294; + R1.H = 0x52ea; + R2.L = 0xafda; + R2.H = 0x5c32; +// end load regs and acc; + R0.H = (A1 = R5.L * R6.H), R0.L = (A0 += R5.L * R6.H) (FU); +P0 = ASTAT; +CHECKREG P0, (_VS|_V|_V_COPY); + + CHECKREG R0, 0xffff; +R0 = A1.w +CHECKREG R0, 0; +R0 = A1.x +CHECKREG R0, 0; +R0 = A0.w +CHECKREG R0, 0xffeec062; +R0 = A0.x +CHECKREG R0, 0x2c; + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY); + R4 = R6 +|- R5 , R3 = R6 -|+ R5; + CHECKREG R3, 0x80008000; + CHECKREG R4, 0x80008000; + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN); + A1 = R7.L * R2.L (M), A0 -= R7.L * R2.H (IS); + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN); + R7.H = R1.H * R3.L (TFU); + CHECKREG R7, 0x29750000; + P0 = ASTAT; + CHECKREG P0, (_VS|_AN); + R7.H = ( A1 -= R2.L * R5.H ), A0 = R2.L * R5.H; + CHECKREG R7, 0xafda0000; +R0 = A1.w +CHECKREG R0, 0xafda0000; +R0 = A1.x +CHECKREG R0, 0xffffffff; +R0 = A0.w +CHECKREG R0, 0x50260000; +R0 = A0.x +CHECKREG R0, 0x0; + P0 = ASTAT; + CHECKREG P0, (_VS|_AN); + R3 = R7.L * R6.H, R2 = R7.L * R6.H (IS); + CHECKREG R3, 0; + CHECKREG R2, 0; + P0 = ASTAT; + CHECKREG P0, (_VS|_AN); + R1.H = (A1 += R7.L * R4.H) (M), R1.L = (A0 = R7.H * R4.H) (FU); + CHECKREG R1, 0xafda57ed; + P0 = ASTAT; +R0 = A1.w +CHECKREG R0, 0xafda0000; +R0 = A1.x +CHECKREG R0, 0xffffffff; +R0 = A0.w +CHECKREG R0, 0x57ed0000; +R0 = A0.x +CHECKREG R0, 0x0; + CHECKREG P0, (_VS|_AN); + R3 = R6.H * R5.L (FU); + CHECKREG R3, 0; + P0 = ASTAT; + CHECKREG P0, (_VS|_AN); + R5.H = ( A1 += R3.L * R1.L ) (M), A0 -= R3.H * R1.H (ISS2); + CHECKREG R5, 0x80000000; +R0 = A1.w +CHECKREG R0, 0xafda0000; +R0 = A1.x +CHECKREG R0, 0xffffffff; +R0 = A0.w +CHECKREG R0, 0x57ed0000; +R0 = A0.x +CHECKREG R0, 0x0; + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN); + R3 = R3 +|- R5 , R6 = R3 -|+ R5 (CO); + CHECKREG R3, 0x80000000; + CHECKREG R6, 0x00008000; + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); + R7 = ( A1 += R4.L * R1.L ) (M), R6 = ( A0 += R4.L * R1.H ); +R0 = A1.w +CHECKREG R0, 0x83e38000; +R0 = A1.x +CHECKREG R0, 0xffffffff; +R0 = A0.w +CHECKREG R0, 0xa8130000; +R0 = A0.x +CHECKREG R0, 0x0; + CHECKREG R6, 0x7fffffff + CHECKREG R7, 0x83e38000 + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); + IF CC P2 = R1; + R2.H = (A1 = R7.L * R5.H) (M), R2.L = (A0 = R7.L * R5.H) (ISS2); + CHECKREG R2, 0x80007fff + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); + R3.H = R4.H * R2.H, R3.L = R4.L * R2.L (T); + CHECKREG R3, 0x7fff8001 + P0 = ASTAT; + CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ); + R7 = ( A1 = R7.H * R1.H ) (M), A0 -= R7.H * R1.H (FU); + CHECKREG R7, 0xaabe7c4e + P0 = ASTAT; + CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ); + R0.H = R7.L * R4.H (M), R0.L = R7.L * R4.H (TFU); + CHECKREG R0, 0x3e273e27 + P0 = ASTAT; + CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ); + R5 = ( A1 = R7.L * R7.L ), R4 = ( A0 -= R7.H * R7.H ) (ISS2); + CHECKREG R5, 0x78b74f88 + CHECKREG R4, 0xc73635f8 +R0 = A1.w +CHECKREG R0, 0x3c5ba7c4; +R0 = A1.x +CHECKREG R0, 0x0; +R0 = A0.w +CHECKREG R0, 0xe39b1afc; +R0 = A0.x +CHECKREG R0, 0xffffffff; + R0 = ASTAT; + CHECKREG r0, (_VS|_AV0S|_AZ|_AN); + A0 = A0 >> 2; + R0 = ASTAT; + checkreg r0, (_VS|_AV0S); + R0 = A0.x; + DBGA (R0.L, 0x3f); + R0 = A0.w; + checkreg r0, 0xF8E6C6BF; + + pass diff --git a/sim/testsuite/sim/bfin/a1.s b/sim/testsuite/sim/bfin/a1.s new file mode 100644 index 0000000..40f9d40 --- /dev/null +++ b/sim/testsuite/sim/bfin/a1.s @@ -0,0 +1,29 @@ +// check the imm7 bit constants bounds +# mach: bfin + +.include "testutils.inc" + start + + R0 = 63; + DBGA ( R0.L , 63 ); + R0 = -64; + DBGA ( R0.L , 0xffc0 ); + P0 = 63; + R0 = P0; DBGA ( R0.L , 63 ); + P0 = -64; + R0 = P0; DBGA ( R0.L , 0xffc0 ); + +// check loading imm16 into h/l halves + R0.L = 0x1111; + DBGA ( R0.L , 0x1111 ); + + R0.H = 0x1111; + DBGA ( R0.H , 0x1111 ); + + P0.L = 0x2222; + R0 = P0; DBGA ( R0.L , 0x2222 ); + + P0.H = 0x2222; + R0 = P0; DBGA ( R0.H , 0x2222 ); + + pass diff --git a/sim/testsuite/sim/bfin/a10.s b/sim/testsuite/sim/bfin/a10.s new file mode 100644 index 0000000..4117e60 --- /dev/null +++ b/sim/testsuite/sim/bfin/a10.s @@ -0,0 +1,176 @@ +// ALU test program. +// Test dual 16 bit MAX, MIN, ABS instructions +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; +// MAX +// first operand is larger, so AN=0 + R0.L = 0x0001; + R0.H = 0x0002; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0002 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// second operand is larger + R0.L = 0x0000; + R0.H = 0x0000; + R1.L = 0x0001; + R1.H = 0x0022; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0022 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// one operand larger, one smaller. + R0.L = 0x000a; + R0.H = 0x0000; + R1.L = 0x0001; + R1.H = 0x0022; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x000a ); + DBGA ( R7.H , 0x0022 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x8001; + R0.H = 0xffff; + R1.L = 0x8000; + R1.H = 0x0022; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x8001 ); + DBGA ( R7.H , 0x0022 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x8000; + R0.H = 0xffff; + R1.L = 0x8000; + R1.H = 0x0022; + R7 = MAX ( R0 , R1 ) (V); + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0022 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// MIN +// second operand is smaller + R0.L = 0x0001; + R0.H = 0x0004; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MIN ( R0 , R1 ) (V); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// first operand is smaller + R0.L = 0xffff; + R0.H = 0x8001; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MIN ( R0 , R1 ) (V); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x8001 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// one of each + R0.L = 0xffff; + R0.H = 0x0034; + R1.L = 0x0999; + R1.H = 0x0010; + R7 = MIN ( R0 , R1 ) (V); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x0010 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xffff; + R0.H = 0x0010; + R1.L = 0x0999; + R1.H = 0x0010; + R7 = MIN ( R0 , R1 ) (V); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x0010 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// ABS + R0.L = 0x0001; + R0.H = 0x8001; + R7 = ABS R0 (V); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x7fff ); + _DBG ASTAT; + R6 = ASTAT; + _DBG R6; + + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = VS; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0001; + R0.H = 0x8000; + R7 = ABS R0 (V); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0000; + R0.H = 0xffff; + R7 = ABS R0 (V); + _DBG R7; + _DBG ASTAT; + R6 = ASTAT; + _DBG R6; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0001 ); + CC = VS; R6 = CC; DBGA ( R6.L, 0x1 ); + CC = AZ; R6 = CC; DBGA ( R6.L, 0x1 ); + + pass diff --git a/sim/testsuite/sim/bfin/a11.S b/sim/testsuite/sim/bfin/a11.S new file mode 100644 index 0000000..bf3723a --- /dev/null +++ b/sim/testsuite/sim/bfin/a11.S @@ -0,0 +1,386 @@ +// Test ALU RND RND12 RND20 +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + + R7 = 0; + ASTAT = R7; + +// 7ffffff0 +// + 00008000 +// -> 7fff0000 + R0 = 0xfff0 (Z); + R0.H = 0x7fff; + R7.L = R0 (RND); + R0 = ASTAT; + CHECKREG R7, 0x7fff; + CHECKREG R0, (_VS|_V|_V_COPY); + +// 7ffffff0 +// + 00008000 +// -> 7fff0000 + R0.L = 0xfff0; + R0.H = 0x7fff; + R7.H = R0 (RND); + R0 = ASTAT; + CHECKREG R7, 0x7fff7fff; + CHECKREG R0, (_VS|_V|_V_COPY); + +// 7ff0fff0 +// + 00008000 +// -> 7ff10000 + R0.L = 0xfff0; + R0.H = 0x7ff0; + R7.L = R0 (RND); + R0 = ASTAT; + CHECKREG R7, 0x7fff7ff1 + CHECKREG R0, (_VS); + +// 7ff0fff0 +// + 00008000 +// -> 7ff10000 +// 7ff0fff0 +// + 8000 +// -> 7ff1 + R0.L = 0xfff0; + R0.H = 0x7ff0; + R7.H = R0 (RND); + R0 = ASTAT; + CHECKREG R7, 0x7ff17ff1 + CHECKREG R0, (_VS); + +// fffffff0 +// + 00008000 +// -> 00000000 + R0.L = 0xfff0; + R0.H = 0xffff; + R7.L = R0 (RND); + R0 = ASTAT; + CHECKREG R7, 0x7ff10000; + CHECKREG R0, (_VS|_AZ); + +// fffffff0 +// + 00008000 +// -> 00000000 + R0.L = 0xfff0; + R0.H = 0xffff; + R7.H = R0 (RND); + R0 = ASTAT; + DBGA ( R7.H , 0 ); + CHECKREG R0, (_VS|_AZ); + +// 00fffff0 +// + 00008000 +// -> 0100 + R0.L = 0xfff0; + R0.H = 0x00ff; + R7.L = R0 (RND); + R0 = ASTAT; + DBGA ( R7.L , 0x0100 ); + CHECKREG R0, (_VS); + +// RND12 + +// 07ffe000 +// + 00000000 +// = 07ffe000 +// + 00000800 +// -> 7ffe + R0.L = 0xe000; + R0.H = 0x07ff; + R1 = 0x0000 (Z); + R1.H = 0x0000; + R7.L = R0 + R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x7ffe ); + CHECKREG R0, (_VS); + +// 07ffff00 +// + 00000000 +// = 07ffff00 +// + 00000800 +// -> 7fff + R0.L = 0xff00; + R0.H = 0x07ff; + R1.L = 0x0000; + R1.H = 0x0000; + R7.L = R0 + R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x7fff ); + CHECKREG R0, (_VS|_V|_V_COPY); + +// 07fffc00 +// + 00000f00 +// = 08000b00 +// + 00000800 +// -> 7fff + R0.L = 0xfc00; + R0.H = 0x07ff; + R1.L = 0x0f00; + R1.H = 0x0000; + R7.L = R0 + R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x7fff ); + CHECKREG R0, (_VS|_V|_V_COPY); + +// 07ff c000 +// + 0000 1000 +// = 07ff d000 +// + 0000 0800 +// -> 7ff d + R0.L = 0xc000; + R0.H = 0x07ff; + R1.L = 0x1000; + R1.H = 0x0000; + _DBG ASTAT; + R7.L = R0 + R1 (RND12); + _DBG ASTAT; + R0 = ASTAT; + _DBG R0; + DBGA ( R7.L , 0x7ffd ); + CHECKREG R0, (_VS); + +// ffff ffea +// + 07ff fe00 +// = 107ff fdea +// + 0000 0800 +// -> 7ff f + R0.L = 0xffea; + R0.H = 0xffff; + R1.L = 0xfe00; + R1.H = 0x07ff; + _DBG ASTAT; + R7.L = R0 + R1 (RND12); + _DBG ASTAT; + R0 = ASTAT; + _DBG R0; + DBGA ( R7.L , 0x7fff ); + CHECKREG R0, (_VS|_V|_V_COPY); + +// Small negative plus small negative should give zero +// ffff ffff +// + ffff ffff +// + 0000 0800 +// -> 000 0 + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0xffff; + R1.H = 0xffff; + _DBG ASTAT; + R7.L = R0 + R1 (RND12); + R0 = ASTAT; + _DBG R0; + DBGA ( R7.L , 0x0000 ); + CHECKREG R0, (_VS|_AZ); + +// Small negative minus small positive should give zero +// ffff ffff +// + 0000 0001 +// - 0000 0800 +// -> 000 0 + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x0001; + R1.H = 0x0000; + R7.L = R0 - R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x0000 ); + CHECKREG R0, (_VS|_AZ); + +// Large positive plus large positive should give maxpos +// 07ff ffff +// + 07ff ffff +// + 0000 0800 +// -> 7ff f + R0.L = 0xffff; + R0.H = 0x07ff; + R1.L = 0xffff; + R1.H = 0x07ff; + R7.L = R0 + R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x7fff ); + CHECKREG R0, (_VS|_V|_V_COPY); + +// Large negative plus large negative should give maxneg +// 0800 0000 +// + 0800 0000 +// + 0000 0800 +// -> 800 0 + R0.L = 0x0000; + R0.H = 0x0800; + R1.L = 0x0000; + R1.H = 0x0800; + R7.L = R0 + R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x7fff ); + CHECKREG R0, (_VS|_V|_V_COPY); + +// Large positive minus large negative should give maxpos +// 07ff ffff +// - 0800 0000 +// + 0000 0800 +// -> 800 0 + R0.L = 0xffff; + R0.H = 0x07ff; + R1.L = 0x0000; + R1.H = 0x0800; + R7.L = R0 - R1 (RND12); + R0 = ASTAT; + _DBG ASTAT; + DBGA ( R7.L , 0x0 ); + CHECKREG R0, (_VS|_AZ); + +// Large negative minus large positive should give maxneg +// 0800 0000 +// - 07ff ffff +// + 0000 0800 +// -> 800 0 + R0.L = 0x0000; + R0.H = 0x0800; + R1.L = 0xffff; + R1.H = 0x07ff; + R7.L = R0 - R1 (RND12); + R0 = ASTAT; + _DBG ASTAT; + DBGA ( R7.L , 0x0000 ); + CHECKREG R0, (_VS|_AZ); + +// cef4 3ed6 +// - 56f4 417a +// + 0000 0800 +// -> 800 0 + R0.L = 0x3ed6; + R0.H = 0xcef4; + R1.L = 0x417a; + R1.H = 0x56f4; + R7.L = R0 - R1 (RND12); + R0 = ASTAT; + DBGA ( R7.L , 0x8000 ); + CHECKREG R0, (_VS|_V|_V_COPY|_AN); + +// RND20 + +// 00ff 0000 +// + 0000 0000 +// + 0008 0000 +// ->0010 + R0.L = 0x0000; + R0.H = 0x00ff; + R1.L = 0x0000; + R1.H = 0x0000; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x0010 ); + CHECKREG R0, (_VS); + +// 00f0 0000 +// + 000f 0000 +// + 0008 0000 +// ->0010 + R0.L = 0x0000; + R0.H = 0x00f0; + R1.L = 0x0000; + R1.H = 0x000f; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x0010 ); + CHECKREG R0, (_VS); + +// 7ff0 0000 +// + 0000 0000 +// + 0008 0000 +// ->07ff + R0.L = 0x0000; + R0.H = 0x7ff0; + R1.L = 0x0000; + R1.H = 0x0000; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x07ff ); + CHECKREG R0, (_VS); + +// 7fff 0000 +// + 0000 0000 +// + 0008 0000 +// ->0800 + R0.L = 0x0000; + R0.H = 0x7fff; + R1.L = 0x0000; + R1.H = 0x0000; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x0800 ); + CHECKREG R0, (_VS); + +// ffff 0000 +// + 0000 0000 +// + 0008 0000 +// ->0000 + R0.L = 0x0000; + R0.H = 0xffff; + R1.L = 0x0000; + R1.H = 0x0000; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x0000 ); + DBGA ( R0.H , 0x0200 ); + DBGA ( R0.L , 0x0001 ); + +// ff00 0000 +// + 0010 0000 +// + 0008 0000 +// ->fff1 + R0.L = 0x0000; + R0.H = 0xff00; + R1.L = 0x0000; + R1.H = 0x0010; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0xfff1 ); + CHECKREG R0, (_VS|_AN); + +// ff00 0000 +// + 0018 0000 +// + 0008 0000 +// ->fff2 + R0.L = 0x0000; + R0.H = 0xff00; + R1.L = 0x0000; + R1.H = 0x0018; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0xfff2 ); + CHECKREG R0, (_VS|_AN); + +// Small negative plus small negative should give zero +// ffff ffff +// + ffff ffff +// + 0008 0000 +// ->0000 + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0xffff; + R1.H = 0xffff; + R7.L = R0 + R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x0000 ); + CHECKREG R0, (_VS|_AZ); + +// Small negative minus small positive should give zero +// ffff ffff +// + 0000 0010 +// + 0008 0000 +// ->0000 + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x0010; + R1.H = 0x0000; + R7.L = R0 - R1 (RND20); + R0 = ASTAT; + DBGA ( R7.L , 0x0000 ); + CHECKREG R0, (_VS|_AZ); + + pass diff --git a/sim/testsuite/sim/bfin/a12.s b/sim/testsuite/sim/bfin/a12.s new file mode 100644 index 0000000..ddc436e --- /dev/null +++ b/sim/testsuite/sim/bfin/a12.s @@ -0,0 +1,40 @@ +// Test SAA +# mach: bfin + +.include "testutils.inc" + start + + I0 = 0; + I1 = 0; + + imm32 R0, 0x04030201; + imm32 R2, 0x04030201; + A1 = A0 = 0; + saa(r1:0,r3:2); + R0 = A0.w; + R1 = A1.w; + CHECKREG R0, 0; + CHECKREG R1, 0; + + imm32 R0, 0x00000201; + imm32 R2, 0x00020102; + A1 = A0 = 0; + saa(r1:0,r3:2); + saa(r1:0,r3:2); + saa(r1:0,r3:2); + R0 = A0.w; + R1 = A1.w; + CHECKREG R0, 0x00030003; + CHECKREG R1, 0x00000006; + + imm32 R0, 0x000300ff; + imm32 R2, 0x0001ff00; + A1 = A0 = 0; + saa(r1:0,r3:2); + saa(r1:0,r3:2); + R0 = A0.w; + R1 = A1.w; + CHECKREG R0, 0x1fe01fe; + CHECKREG R1, 0x0000004; + + pass diff --git a/sim/testsuite/sim/bfin/a2.s b/sim/testsuite/sim/bfin/a2.s new file mode 100644 index 0000000..eb668dd --- /dev/null +++ b/sim/testsuite/sim/bfin/a2.s @@ -0,0 +1,179 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym P0, middle; + + R0 = [ P0 + 0 ]; DBGA ( R0.L , 50 ); + R0 = [ P0 + 4 ]; DBGA ( R0.L , 51 ); + R0 = [ P0 + 8 ]; DBGA ( R0.L , 52 ); + R0 = [ P0 + 12 ]; DBGA ( R0.L , 53 ); + R0 = [ P0 + 16 ]; DBGA ( R0.L , 54 ); + R0 = [ P0 + 20 ]; DBGA ( R0.L , 55 ); + R0 = [ P0 + 24 ]; DBGA ( R0.L , 56 ); + R0 = [ P0 + 28 ]; DBGA ( R0.L , 57 ); + + R0 = [ P0 + -4 ]; DBGA ( R0.L , 49 ); + R0 = [ P0 + -8 ]; DBGA ( R0.L , 48 ); + R0 = [ P0 + -12 ]; DBGA ( R0.L , 47 ); + R0 = [ P0 + -16 ]; DBGA ( R0.L , 46 ); + R0 = [ P0 + -20 ]; DBGA ( R0.L , 45 ); + R0 = [ P0 + -24 ]; DBGA ( R0.L , 44 ); + R0 = [ P0 + -28 ]; DBGA ( R0.L , 43 ); + R0 = [ P0 + -32 ]; DBGA ( R0.L , 42 ); + + FP = P0; + + R0 = [ FP + 0 ]; DBGA ( R0.L , 50 ); + R0 = [ FP + 4 ]; DBGA ( R0.L , 51 ); + R0 = [ FP + 8 ]; DBGA ( R0.L , 52 ); + R0 = [ FP + 12 ]; DBGA ( R0.L , 53 ); + R0 = [ FP + 16 ]; DBGA ( R0.L , 54 ); + R0 = [ FP + 20 ]; DBGA ( R0.L , 55 ); + R0 = [ FP + 24 ]; DBGA ( R0.L , 56 ); + R0 = [ FP + 28 ]; DBGA ( R0.L , 57 ); + R0 = [ FP + 32 ]; DBGA ( R0.L , 58 ); + R0 = [ FP + 36 ]; DBGA ( R0.L , 59 ); + R0 = [ FP + 40 ]; DBGA ( R0.L , 60 ); + R0 = [ FP + 44 ]; DBGA ( R0.L , 61 ); + R0 = [ FP + 48 ]; DBGA ( R0.L , 62 ); + R0 = [ FP + 52 ]; DBGA ( R0.L , 63 ); + R0 = [ FP + 56 ]; DBGA ( R0.L , 64 ); + R0 = [ FP + 60 ]; DBGA ( R0.L , 65 ); + + R0 = [ FP + -4 ]; DBGA ( R0.L , 49 ); + R0 = [ FP + -8 ]; DBGA ( R0.L , 48 ); + R0 = [ FP + -12 ]; DBGA ( R0.L , 47 ); + R0 = [ FP + -16 ]; DBGA ( R0.L , 46 ); + R0 = [ FP + -20 ]; DBGA ( R0.L , 45 ); + R0 = [ FP + -24 ]; DBGA ( R0.L , 44 ); + R0 = [ FP + -28 ]; DBGA ( R0.L , 43 ); + R0 = [ FP + -32 ]; DBGA ( R0.L , 42 ); + R0 = [ FP + -36 ]; DBGA ( R0.L , 41 ); + R0 = [ FP + -40 ]; DBGA ( R0.L , 40 ); + R0 = [ FP + -44 ]; DBGA ( R0.L , 39 ); + R0 = [ FP + -48 ]; DBGA ( R0.L , 38 ); + R0 = [ FP + -52 ]; DBGA ( R0.L , 37 ); + R0 = [ FP + -56 ]; DBGA ( R0.L , 36 ); + R0 = [ FP + -60 ]; DBGA ( R0.L , 35 ); + R0 = [ FP + -64 ]; DBGA ( R0.L , 34 ); + R0 = [ FP + -68 ]; DBGA ( R0.L , 33 ); + R0 = [ FP + -72 ]; DBGA ( R0.L , 32 ); + R0 = [ FP + -76 ]; DBGA ( R0.L , 31 ); + R0 = [ FP + -80 ]; DBGA ( R0.L , 30 ); + R0 = [ FP + -84 ]; DBGA ( R0.L , 29 ); + R0 = [ FP + -88 ]; DBGA ( R0.L , 28 ); + R0 = [ FP + -92 ]; DBGA ( R0.L , 27 ); + R0 = [ FP + -96 ]; DBGA ( R0.L , 26 ); + R0 = [ FP + -100 ]; DBGA ( R0.L , 25 ); + R0 = [ FP + -104 ]; DBGA ( R0.L , 24 ); + R0 = [ FP + -108 ]; DBGA ( R0.L , 23 ); + R0 = [ FP + -112 ]; DBGA ( R0.L , 22 ); + R0 = [ FP + -116 ]; DBGA ( R0.L , 21 ); + + pass + + .data +base: + .dd 0 + .dd 1 + .dd 2 + .dd 3 + .dd 4 + .dd 5 + .dd 6 + .dd 7 + .dd 8 + .dd 9 + .dd 10 + .dd 11 + .dd 12 + .dd 13 + .dd 14 + .dd 15 + .dd 16 + .dd 17 + .dd 18 + .dd 19 + .dd 20 + .dd 21 + .dd 22 + .dd 23 + .dd 24 + .dd 25 + .dd 26 + .dd 27 + .dd 28 + .dd 29 + .dd 30 + .dd 31 + .dd 32 + .dd 33 + .dd 34 + .dd 35 + .dd 36 + .dd 37 + .dd 38 + .dd 39 + .dd 40 + .dd 41 + .dd 42 + .dd 43 + .dd 44 + .dd 45 + .dd 46 + .dd 47 + .dd 48 + .dd 49 +middle: + .dd 50 + .dd 51 + .dd 52 + .dd 53 + .dd 54 + .dd 55 + .dd 56 + .dd 57 + .dd 58 + .dd 59 + .dd 60 + .dd 61 + .dd 62 + .dd 63 + .dd 64 + .dd 65 + .dd 66 + .dd 67 + .dd 68 + .dd 69 + .dd 70 + .dd 71 + .dd 72 + .dd 73 + .dd 74 + .dd 75 + .dd 76 + .dd 77 + .dd 78 + .dd 79 + .dd 80 + .dd 81 + .dd 82 + .dd 83 + .dd 84 + .dd 85 + .dd 86 + .dd 87 + .dd 88 + .dd 89 + .dd 90 + .dd 91 + .dd 92 + .dd 93 + .dd 94 + .dd 95 + .dd 96 + .dd 97 + .dd 98 + .dd 99 diff --git a/sim/testsuite/sim/bfin/a20.S b/sim/testsuite/sim/bfin/a20.S new file mode 100644 index 0000000..6245994 --- /dev/null +++ b/sim/testsuite/sim/bfin/a20.S @@ -0,0 +1,68 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R1 = 0; + ASTAT = R1; + + R1.H = -32768; + R2 = 0; + R2.H = -32768; + R3 = R1 +|+ R2; + _DBG ASTAT; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AC1|_AZ); + + R0.L = 32767; + R0.H = 32767; + R0 = R0 +|- R0; + _DBG ASTAT; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN|_AZ) + + R0 = 0; + ASTAT = R0; + _DBG ASTAT; + R7 = ASTAT; + CHECKREG R7, (_UNSET) + + R1.L = -1; + R1.H = 0x7fff; + R0 = ABS R1; + _DBG R0; + _DBG ASTAT; + R7 = ASTAT; + CHECKREG R7, (_UNSET) + + R1=0; + R1.H = 0x8000; + _DBG R1; + R0 = ABS R1; + _DBG R0; + _DBG ASTAT; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY) + + R0 = 0; + ASTAT = R0; + + R1.L = 32767; + R1.H = 32767; + R0 = R1 +|+ R1 (CO); + _DBG R0; + _DBG ASTAT; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AN) + + R0.L = -1; + R0.H = 32766; + R1.L = -1; + R1.H = -32768; + R0 = PACK( R0.H , R1.L ); + _DBG R0; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AN) + + pass diff --git a/sim/testsuite/sim/bfin/a21.s b/sim/testsuite/sim/bfin/a21.s new file mode 100644 index 0000000..c621921 --- /dev/null +++ b/sim/testsuite/sim/bfin/a21.s @@ -0,0 +1,83 @@ +// Test ALU RND RND12 RND20 +# mach: bfin + +.include "testutils.inc" + start + + +// positive saturation + R0 = 0xffffffff; + A0.w = R0; + A1.w = R0; + R0 = 0x7f (X); + A0.x = R0; + A1.x = R0; + R3 = A1 + A0, R4 = A1 - A0 (S); + DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff ); + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 ); + +// neg saturation + R0 = 0; + A0.w = R0; + A1.w = R0; + R0 = 0x80 (X); + A0.x = R0; + A1.x = R0; + R3 = A1 + A0, R4 = A1 - A0 (S); + DBGA ( R3.H , 0x8000 ); DBGA ( R3.L , 0x0000 ); + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 ); + +// positive saturation + R0 = 0xfffffff0; + A0.w = R0; + A1.w = R0; + R0 = 0x01; + A0.x = R0; + A1.x = R0; + R3 = A1 + A0, R4 = A1 - A0 (S); + DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff ); + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 ); + +// no sat + R0 = 0xfffffff0; + A0.w = R0; + A1.w = R0; + R0 = 0x01; + A0.x = R0; + A1.x = R0; + R3 = A1 + A0, R4 = A1 - A0 (NS); + DBGA ( R3.H , 0xffff ); DBGA ( R3.L , 0xffe0 ); + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 ); + +// add and sub +1 -1 + R0 = 0x00000001; + A0.w = R0; + R0 = 0xffffffff; + A1.w = R0; + R0 = 0; + A0.x = R0; + R0 = 0xff (X); + A1.x = R0; + R3 = A1 + A0, R4 = A1 - A0 (NS); + DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); // 0 + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); // -2 + +// should get the same with saturation + R3 = A1 + A0, R4 = A1 - A0 (S); + DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); // 0 + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); // -2 + +// add and sub -1 +1 but with reverse order of A0 A1 + R0 = 0x00000001; + A0.w = R0; + R0 = 0xffffffff; + A1.w = R0; + R0 = 0; + A0.x = R0; + R0 = 0xff (X); + A1.x = R0; + R3 = A0 + A1, R4 = A0 - A1 (NS); + DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0002 ); + + pass diff --git a/sim/testsuite/sim/bfin/a22.s b/sim/testsuite/sim/bfin/a22.s new file mode 100644 index 0000000..1df76df --- /dev/null +++ b/sim/testsuite/sim/bfin/a22.s @@ -0,0 +1,83 @@ +// Test ALU NEG accumulators +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0xffffffff; + A0.w = R0; + R0 = 0x7f (X); + A0.x = R0; + A0 = - A0; + _DBG A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff80 ); + + R0 = 0x1; + A0.w = R0; + R0 = 0x0; + A0.x = R0; + A0 = - A0; + R4 = A0.w; + R5 = A0.x; + _DBG A0; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); + + R0 = 0xffffffff; + A0.w = R0; + R0 = 0xff (X); + A0.x = R0; + A0 = - A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); + + R0 = 0x00000000; + A0.w = R0; + R0 = 0x80 (X); + A0.x = R0; + A0 = - A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + +// NEG NEG + R0 = 0x00000000; + A0.w = R0; + R0 = 0x80 (X); + A0.x = R0; + + R0 = 0xffffffff; + A1.w = R0; + R0 = 0x7f (X); + A1.x = R0; + + A1 = - A1, A0 = - A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + R4 = A1.w; + R5 = A1.x; + _DBG A1; + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff80 ); + +// NEG NEG register + R0.L = 0x0001; + R0.H = 0x8000; + + R3 = - R0 (V); + DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff ); + + _DBG ASTAT; + + pass diff --git a/sim/testsuite/sim/bfin/a23.s b/sim/testsuite/sim/bfin/a23.s new file mode 100644 index 0000000..d63fa0c --- /dev/null +++ b/sim/testsuite/sim/bfin/a23.s @@ -0,0 +1,84 @@ +// Test ALU ABS accumulators +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0x00000000; + A0.w = R0; + R0 = 0x80 (X); + A0.x = R0; + + A0 = ABS A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + R0 = 0x00000001; + A0.w = R0; + R0 = 0x80 (X); + A0.x = R0; + + A0 = ABS A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + R0 = 0xffffffff; + A0.w = R0; + R0 = 0xff (X); + A0.x = R0; + + A0 = ABS A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); + + R0 = 0xfffffff0; + A0.w = R0; + R0 = 0x7f (X); + A0.x = R0; + + A0 = ABS A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfff0 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + R0 = 0x00000000; + A0.w = R0; + R0 = 0x80 (X); + A0.x = R0; + + A1 = ABS A0; + R4 = A1.w; + R5 = A1.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + R0 = 0x00000000; + A0.w = R0; + R0 = 0x80 (X); + A0.x = R0; + + R0 = 0x00000002; + A1.w = R0; + R0 = 0x80 (X); + A1.x = R0; + + A1 = ABS A1, A0 = ABS A0; + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + R4 = A1.w; + R5 = A1.x; + DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f ); + + pass diff --git a/sim/testsuite/sim/bfin/a24.s b/sim/testsuite/sim/bfin/a24.s new file mode 100644 index 0000000..507350f --- /dev/null +++ b/sim/testsuite/sim/bfin/a24.s @@ -0,0 +1,12 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0x1111 (X); + R0.H = 0x1111; + A0.x = R0; + R1 = A0.x; + DBGA ( R1.L , 0x11 ); + DBGA ( R1.H , 0x0 ); + pass diff --git a/sim/testsuite/sim/bfin/a25.s b/sim/testsuite/sim/bfin/a25.s new file mode 100644 index 0000000..b5d5d7b --- /dev/null +++ b/sim/testsuite/sim/bfin/a25.s @@ -0,0 +1,28 @@ +# mach: bfin + +.include "testutils.inc" + start + + + A1 = A0 = 0; + R0.L = 0x01; + A0.x = R0; +//A0 = 0x0100000000 +//A1 = 0x0000000000 + + R4.L = 0x2d1a; + R4.H = 0x32e0; + + A1.x = R4; +//A1 = 0x1a00000000 + + A0.w = A1.x; + + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x001a ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0001 ); + + pass diff --git a/sim/testsuite/sim/bfin/a26.s b/sim/testsuite/sim/bfin/a26.s new file mode 100644 index 0000000..2e9a0b5 --- /dev/null +++ b/sim/testsuite/sim/bfin/a26.s @@ -0,0 +1,72 @@ +// Test ALU SEARCH instruction +# mach: bfin + +.include "testutils.inc" + start + + + init_r_regs 0; + ASTAT = R0; + + R0 = 4; + R1 = 5; + A1 = A0 = 0; + + R2.L = 0x0001; + R2.H = 0xffff; + + loadsym P0, foo; + + ( R1 , R0 ) = SEARCH R2 (GT); + + // R0 should be the pointer + R7 = P0; + CC = R0 == R7; + if !CC JUMP _fail; + + _DBG R1; // does not change + DBGA ( R1.H , 0 ); DBGA ( R1.L , 0x5 ); + + _DBG A0; // changes + R0 = A0.w; + DBGA ( R0.H , 0 ); DBGA ( R0.L , 0x1 ); + + _DBG A1; // does not change + R0 = A1.w; + DBGA ( R0.H , 0 ); DBGA ( R0.L , 0 ); + + R0 = 4; + R1 = 5; + A1 = A0 = 0; + + R2.L = 0x0000; + R2.H = 0xffff; + + loadsym p0, foo; + + ( R1 , R0 ) = SEARCH R2 (LT); + + _DBG R0; // no change + DBGA ( R0.H , 0 ); DBGA ( R0.L , 4 ); + + _DBG R1; // change + R7 = P0; + CC = R1 == R7; + if !CC JUMP _fail; + + _DBG A0; + R0 = A0.w; + DBGA ( R0.H , 0 ); DBGA ( R0.L , 0 ); + + _DBG A1; + R0 = A1.w; + DBGA ( R0.H , 0xffff ); DBGA ( R0.L , 0xffff ); + + pass + +_fail: + fail; + + .data +foo: + .space (0x100) diff --git a/sim/testsuite/sim/bfin/a3.s b/sim/testsuite/sim/bfin/a3.s new file mode 100644 index 0000000..c53300b --- /dev/null +++ b/sim/testsuite/sim/bfin/a3.s @@ -0,0 +1,313 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym P1, middle; + + R0 = W [ P1 + -2 ] (Z); DBGA ( R0.L , 49 ); + R0 = W [ P1 + -4 ] (Z); DBGA ( R0.L , 48 ); + R0 = W [ P1 + -6 ] (Z); DBGA ( R0.L , 47 ); + R0 = W [ P1 + -8 ] (Z); DBGA ( R0.L , 46 ); + R0 = W [ P1 + -10 ] (Z); DBGA ( R0.L , 45 ); + R0 = W [ P1 + -12 ] (Z); DBGA ( R0.L , 44 ); + R0 = W [ P1 + -14 ] (Z); DBGA ( R0.L , 43 ); + R0 = W [ P1 + -16 ] (Z); DBGA ( R0.L , 42 ); + R0 = W [ P1 + -18 ] (Z); DBGA ( R0.L , 41 ); + R0 = W [ P1 + -20 ] (Z); DBGA ( R0.L , 40 ); + R0 = W [ P1 + -22 ] (Z); DBGA ( R0.L , 39 ); + R0 = W [ P1 + -24 ] (Z); DBGA ( R0.L , 38 ); + R0 = W [ P1 + -26 ] (Z); DBGA ( R0.L , 37 ); + R0 = W [ P1 + -28 ] (Z); DBGA ( R0.L , 36 ); + R0 = W [ P1 + -30 ] (Z); DBGA ( R0.L , 35 ); + R0 = W [ P1 + -32 ] (Z); DBGA ( R0.L , 34 ); + R0 = W [ P1 + -34 ] (Z); DBGA ( R0.L , 33 ); + R0 = W [ P1 + -36 ] (Z); DBGA ( R0.L , 32 ); + R0 = W [ P1 + -38 ] (Z); DBGA ( R0.L , 31 ); + R0 = W [ P1 + -40 ] (Z); DBGA ( R0.L , 30 ); + R0 = W [ P1 + -42 ] (Z); DBGA ( R0.L , 29 ); + R0 = W [ P1 + -44 ] (Z); DBGA ( R0.L , 28 ); + R0 = W [ P1 + -46 ] (Z); DBGA ( R0.L , 27 ); + R0 = W [ P1 + -48 ] (Z); DBGA ( R0.L , 26 ); + R0 = W [ P1 + -50 ] (Z); DBGA ( R0.L , 25 ); + R0 = W [ P1 + -52 ] (Z); DBGA ( R0.L , 24 ); + R0 = W [ P1 + -54 ] (Z); DBGA ( R0.L , 23 ); + R0 = W [ P1 + -56 ] (Z); DBGA ( R0.L , 22 ); + R0 = W [ P1 + -58 ] (Z); DBGA ( R0.L , 21 ); + R0 = W [ P1 + -60 ] (Z); DBGA ( R0.L , 20 ); + R0 = W [ P1 + -62 ] (Z); DBGA ( R0.L , 19 ); + R0 = W [ P1 + -64 ] (Z); DBGA ( R0.L , 18 ); + R0 = W [ P1 + -66 ] (Z); DBGA ( R0.L , 17 ); + R0 = W [ P1 + -68 ] (Z); DBGA ( R0.L , 16 ); + R0 = W [ P1 + -70 ] (Z); DBGA ( R0.L , 15 ); + R0 = W [ P1 + -72 ] (Z); DBGA ( R0.L , 14 ); + R0 = W [ P1 + -74 ] (Z); DBGA ( R0.L , 13 ); + R0 = W [ P1 + -76 ] (Z); DBGA ( R0.L , 12 ); + R0 = W [ P1 + -78 ] (Z); DBGA ( R0.L , 11 ); + R0 = W [ P1 + -80 ] (Z); DBGA ( R0.L , 10 ); + R0 = W [ P1 + -82 ] (Z); DBGA ( R0.L , 9 ); + R0 = W [ P1 + -84 ] (Z); DBGA ( R0.L , 8 ); + R0 = W [ P1 + -86 ] (Z); DBGA ( R0.L , 7 ); + R0 = W [ P1 + -88 ] (Z); DBGA ( R0.L , 6 ); + R0 = W [ P1 + -90 ] (Z); DBGA ( R0.L , 5 ); + R0 = W [ P1 + -92 ] (Z); DBGA ( R0.L , 4 ); + R0 = W [ P1 + -94 ] (Z); DBGA ( R0.L , 3 ); + R0 = W [ P1 + -96 ] (Z); DBGA ( R0.L , 2 ); + R0 = W [ P1 + -98 ] (Z); DBGA ( R0.L , 1 ); + R0 = W [ P1 + 0 ] (Z); DBGA ( R0.L , 50 ); + R0 = W [ P1 + 2 ] (Z); DBGA ( R0.L , 51 ); + R0 = W [ P1 + 4 ] (Z); DBGA ( R0.L , 52 ); + R0 = W [ P1 + 6 ] (Z); DBGA ( R0.L , 53 ); + R0 = W [ P1 + 8 ] (Z); DBGA ( R0.L , 54 ); + R0 = W [ P1 + 10 ] (Z); DBGA ( R0.L , 55 ); + R0 = W [ P1 + 12 ] (Z); DBGA ( R0.L , 56 ); + R0 = W [ P1 + 14 ] (Z); DBGA ( R0.L , 57 ); + R0 = W [ P1 + 16 ] (Z); DBGA ( R0.L , 58 ); + R0 = W [ P1 + 18 ] (Z); DBGA ( R0.L , 59 ); + R0 = W [ P1 + 20 ] (Z); DBGA ( R0.L , 60 ); + R0 = W [ P1 + 22 ] (Z); DBGA ( R0.L , 61 ); + R0 = W [ P1 + 24 ] (Z); DBGA ( R0.L , 62 ); + R0 = W [ P1 + 26 ] (Z); DBGA ( R0.L , 63 ); + R0 = W [ P1 + 28 ] (Z); DBGA ( R0.L , 64 ); + R0 = W [ P1 + 30 ] (Z); DBGA ( R0.L , 65 ); + R0 = W [ P1 + 32 ] (Z); DBGA ( R0.L , 66 ); + R0 = W [ P1 + 34 ] (Z); DBGA ( R0.L , 67 ); + R0 = W [ P1 + 36 ] (Z); DBGA ( R0.L , 68 ); + R0 = W [ P1 + 38 ] (Z); DBGA ( R0.L , 69 ); + R0 = W [ P1 + 40 ] (Z); DBGA ( R0.L , 70 ); + R0 = W [ P1 + 42 ] (Z); DBGA ( R0.L , 71 ); + R0 = W [ P1 + 44 ] (Z); DBGA ( R0.L , 72 ); + R0 = W [ P1 + 46 ] (Z); DBGA ( R0.L , 73 ); + R0 = W [ P1 + 48 ] (Z); DBGA ( R0.L , 74 ); + R0 = W [ P1 + 50 ] (Z); DBGA ( R0.L , 75 ); + R0 = W [ P1 + 52 ] (Z); DBGA ( R0.L , 76 ); + R0 = W [ P1 + 54 ] (Z); DBGA ( R0.L , 77 ); + R0 = W [ P1 + 56 ] (Z); DBGA ( R0.L , 78 ); + R0 = W [ P1 + 58 ] (Z); DBGA ( R0.L , 79 ); + R0 = W [ P1 + 60 ] (Z); DBGA ( R0.L , 80 ); + R0 = W [ P1 + 62 ] (Z); DBGA ( R0.L , 81 ); + R0 = W [ P1 + 64 ] (Z); DBGA ( R0.L , 82 ); + R0 = W [ P1 + 66 ] (Z); DBGA ( R0.L , 83 ); + R0 = W [ P1 + 68 ] (Z); DBGA ( R0.L , 84 ); + R0 = W [ P1 + 70 ] (Z); DBGA ( R0.L , 85 ); + R0 = W [ P1 + 72 ] (Z); DBGA ( R0.L , 86 ); + R0 = W [ P1 + 74 ] (Z); DBGA ( R0.L , 87 ); + R0 = W [ P1 + 76 ] (Z); DBGA ( R0.L , 88 ); + R0 = W [ P1 + 78 ] (Z); DBGA ( R0.L , 89 ); + R0 = W [ P1 + 80 ] (Z); DBGA ( R0.L , 90 ); + R0 = W [ P1 + 82 ] (Z); DBGA ( R0.L , 91 ); + R0 = W [ P1 + 84 ] (Z); DBGA ( R0.L , 92 ); + R0 = W [ P1 + 86 ] (Z); DBGA ( R0.L , 93 ); + R0 = W [ P1 + 88 ] (Z); DBGA ( R0.L , 94 ); + R0 = W [ P1 + 90 ] (Z); DBGA ( R0.L , 95 ); + R0 = W [ P1 + 92 ] (Z); DBGA ( R0.L , 96 ); + R0 = W [ P1 + 94 ] (Z); DBGA ( R0.L , 97 ); + R0 = W [ P1 + 96 ] (Z); DBGA ( R0.L , 98 ); + R0 = W [ P1 + 98 ] (Z); DBGA ( R0.L , 99 ); + + FP = P1; + + R0 = W [ FP + -2 ] (Z); DBGA ( R0.L , 49 ); + R0 = W [ FP + -4 ] (Z); DBGA ( R0.L , 48 ); + R0 = W [ FP + -6 ] (Z); DBGA ( R0.L , 47 ); + R0 = W [ FP + -8 ] (Z); DBGA ( R0.L , 46 ); + R0 = W [ FP + -10 ] (Z); DBGA ( R0.L , 45 ); + R0 = W [ FP + -12 ] (Z); DBGA ( R0.L , 44 ); + R0 = W [ FP + -14 ] (Z); DBGA ( R0.L , 43 ); + R0 = W [ FP + -16 ] (Z); DBGA ( R0.L , 42 ); + R0 = W [ FP + -18 ] (Z); DBGA ( R0.L , 41 ); + R0 = W [ FP + -20 ] (Z); DBGA ( R0.L , 40 ); + R0 = W [ FP + -22 ] (Z); DBGA ( R0.L , 39 ); + R0 = W [ FP + -24 ] (Z); DBGA ( R0.L , 38 ); + R0 = W [ FP + -26 ] (Z); DBGA ( R0.L , 37 ); + R0 = W [ FP + -28 ] (Z); DBGA ( R0.L , 36 ); + R0 = W [ FP + -30 ] (Z); DBGA ( R0.L , 35 ); + R0 = W [ FP + -32 ] (Z); DBGA ( R0.L , 34 ); + R0 = W [ FP + -34 ] (Z); DBGA ( R0.L , 33 ); + R0 = W [ FP + -36 ] (Z); DBGA ( R0.L , 32 ); + R0 = W [ FP + -38 ] (Z); DBGA ( R0.L , 31 ); + R0 = W [ FP + -40 ] (Z); DBGA ( R0.L , 30 ); + R0 = W [ FP + -42 ] (Z); DBGA ( R0.L , 29 ); + R0 = W [ FP + -44 ] (Z); DBGA ( R0.L , 28 ); + R0 = W [ FP + -46 ] (Z); DBGA ( R0.L , 27 ); + R0 = W [ FP + -48 ] (Z); DBGA ( R0.L , 26 ); + R0 = W [ FP + -50 ] (Z); DBGA ( R0.L , 25 ); + R0 = W [ FP + -52 ] (Z); DBGA ( R0.L , 24 ); + R0 = W [ FP + -54 ] (Z); DBGA ( R0.L , 23 ); + R0 = W [ FP + -56 ] (Z); DBGA ( R0.L , 22 ); + R0 = W [ FP + -58 ] (Z); DBGA ( R0.L , 21 ); + R0 = W [ FP + -60 ] (Z); DBGA ( R0.L , 20 ); + R0 = W [ FP + -62 ] (Z); DBGA ( R0.L , 19 ); + R0 = W [ FP + -64 ] (Z); DBGA ( R0.L , 18 ); + R0 = W [ FP + -66 ] (Z); DBGA ( R0.L , 17 ); + R0 = W [ FP + -68 ] (Z); DBGA ( R0.L , 16 ); + R0 = W [ FP + -70 ] (Z); DBGA ( R0.L , 15 ); + R0 = W [ FP + -72 ] (Z); DBGA ( R0.L , 14 ); + R0 = W [ FP + -74 ] (Z); DBGA ( R0.L , 13 ); + R0 = W [ FP + -76 ] (Z); DBGA ( R0.L , 12 ); + R0 = W [ FP + -78 ] (Z); DBGA ( R0.L , 11 ); + R0 = W [ FP + -80 ] (Z); DBGA ( R0.L , 10 ); + R0 = W [ FP + -82 ] (Z); DBGA ( R0.L , 9 ); + R0 = W [ FP + -84 ] (Z); DBGA ( R0.L , 8 ); + R0 = W [ FP + -86 ] (Z); DBGA ( R0.L , 7 ); + R0 = W [ FP + -88 ] (Z); DBGA ( R0.L , 6 ); + R0 = W [ FP + -90 ] (Z); DBGA ( R0.L , 5 ); + R0 = W [ FP + -92 ] (Z); DBGA ( R0.L , 4 ); + R0 = W [ FP + -94 ] (Z); DBGA ( R0.L , 3 ); + R0 = W [ FP + -96 ] (Z); DBGA ( R0.L , 2 ); + R0 = W [ FP + -98 ] (Z); DBGA ( R0.L , 1 ); + R0 = W [ FP + 0 ] (Z); DBGA ( R0.L , 50 ); + R0 = W [ FP + 2 ] (Z); DBGA ( R0.L , 51 ); + R0 = W [ FP + 4 ] (Z); DBGA ( R0.L , 52 ); + R0 = W [ FP + 6 ] (Z); DBGA ( R0.L , 53 ); + R0 = W [ FP + 8 ] (Z); DBGA ( R0.L , 54 ); + R0 = W [ FP + 10 ] (Z); DBGA ( R0.L , 55 ); + R0 = W [ FP + 12 ] (Z); DBGA ( R0.L , 56 ); + R0 = W [ FP + 14 ] (Z); DBGA ( R0.L , 57 ); + R0 = W [ FP + 16 ] (Z); DBGA ( R0.L , 58 ); + R0 = W [ FP + 18 ] (Z); DBGA ( R0.L , 59 ); + R0 = W [ FP + 20 ] (Z); DBGA ( R0.L , 60 ); + R0 = W [ FP + 22 ] (Z); DBGA ( R0.L , 61 ); + R0 = W [ FP + 24 ] (Z); DBGA ( R0.L , 62 ); + R0 = W [ FP + 26 ] (Z); DBGA ( R0.L , 63 ); + R0 = W [ FP + 28 ] (Z); DBGA ( R0.L , 64 ); + R0 = W [ FP + 30 ] (Z); DBGA ( R0.L , 65 ); + R0 = W [ FP + 32 ] (Z); DBGA ( R0.L , 66 ); + R0 = W [ FP + 34 ] (Z); DBGA ( R0.L , 67 ); + R0 = W [ FP + 36 ] (Z); DBGA ( R0.L , 68 ); + R0 = W [ FP + 38 ] (Z); DBGA ( R0.L , 69 ); + R0 = W [ FP + 40 ] (Z); DBGA ( R0.L , 70 ); + R0 = W [ FP + 42 ] (Z); DBGA ( R0.L , 71 ); + R0 = W [ FP + 44 ] (Z); DBGA ( R0.L , 72 ); + R0 = W [ FP + 46 ] (Z); DBGA ( R0.L , 73 ); + R0 = W [ FP + 48 ] (Z); DBGA ( R0.L , 74 ); + R0 = W [ FP + 50 ] (Z); DBGA ( R0.L , 75 ); + R0 = W [ FP + 52 ] (Z); DBGA ( R0.L , 76 ); + R0 = W [ FP + 54 ] (Z); DBGA ( R0.L , 77 ); + R0 = W [ FP + 56 ] (Z); DBGA ( R0.L , 78 ); + R0 = W [ FP + 58 ] (Z); DBGA ( R0.L , 79 ); + R0 = W [ FP + 60 ] (Z); DBGA ( R0.L , 80 ); + R0 = W [ FP + 62 ] (Z); DBGA ( R0.L , 81 ); + R0 = W [ FP + 64 ] (Z); DBGA ( R0.L , 82 ); + R0 = W [ FP + 66 ] (Z); DBGA ( R0.L , 83 ); + R0 = W [ FP + 68 ] (Z); DBGA ( R0.L , 84 ); + R0 = W [ FP + 70 ] (Z); DBGA ( R0.L , 85 ); + R0 = W [ FP + 72 ] (Z); DBGA ( R0.L , 86 ); + R0 = W [ FP + 74 ] (Z); DBGA ( R0.L , 87 ); + R0 = W [ FP + 76 ] (Z); DBGA ( R0.L , 88 ); + R0 = W [ FP + 78 ] (Z); DBGA ( R0.L , 89 ); + R0 = W [ FP + 80 ] (Z); DBGA ( R0.L , 90 ); + R0 = W [ FP + 82 ] (Z); DBGA ( R0.L , 91 ); + R0 = W [ FP + 84 ] (Z); DBGA ( R0.L , 92 ); + R0 = W [ FP + 86 ] (Z); DBGA ( R0.L , 93 ); + R0 = W [ FP + 88 ] (Z); DBGA ( R0.L , 94 ); + R0 = W [ FP + 90 ] (Z); DBGA ( R0.L , 95 ); + R0 = W [ FP + 92 ] (Z); DBGA ( R0.L , 96 ); + R0 = W [ FP + 94 ] (Z); DBGA ( R0.L , 97 ); + R0 = W [ FP + 96 ] (Z); DBGA ( R0.L , 98 ); + R0 = W [ FP + 98 ] (Z); DBGA ( R0.L , 99 ); + pass + + .data + + .dw 0 + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 10 + .dw 11 + .dw 12 + .dw 13 + .dw 14 + .dw 15 + .dw 16 + .dw 17 + .dw 18 + .dw 19 + .dw 20 + .dw 21 + .dw 22 + .dw 23 + .dw 24 + .dw 25 + .dw 26 + .dw 27 + .dw 28 + .dw 29 + .dw 30 + .dw 31 + .dw 32 + .dw 33 + .dw 34 + .dw 35 + .dw 36 + .dw 37 + .dw 38 + .dw 39 + .dw 40 + .dw 41 + .dw 42 + .dw 43 + .dw 44 + .dw 45 + .dw 46 + .dw 47 + .dw 48 + .dw 49 +middle: + .dw 50 + .dw 51 + .dw 52 + .dw 53 + .dw 54 + .dw 55 + .dw 56 + .dw 57 + .dw 58 + .dw 59 + .dw 60 + .dw 61 + .dw 62 + .dw 63 + .dw 64 + .dw 65 + .dw 66 + .dw 67 + .dw 68 + .dw 69 + .dw 70 + .dw 71 + .dw 72 + .dw 73 + .dw 74 + .dw 75 + .dw 76 + .dw 77 + .dw 78 + .dw 79 + .dw 80 + .dw 81 + .dw 82 + .dw 83 + .dw 84 + .dw 85 + .dw 86 + .dw 87 + .dw 88 + .dw 89 + .dw 90 + .dw 91 + .dw 92 + .dw 93 + .dw 94 + .dw 95 + .dw 96 + .dw 97 + .dw 98 + .dw 99 diff --git a/sim/testsuite/sim/bfin/a30.s b/sim/testsuite/sim/bfin/a30.s new file mode 100644 index 0000000..38dd401 --- /dev/null +++ b/sim/testsuite/sim/bfin/a30.s @@ -0,0 +1,55 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0.L = 0.5; + R0.H = 0.5; + R1.L = 0.5; + R1.H = 0.5; + + R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); + _DBGCMPLX R2; + _DBGCMPLX R3; + + DBGA ( R2.L , 0.5 ); + DBGA ( R2.H , 0.5 ); + DBGA ( R3.L , 0 ); + DBGA ( R3.H , 0 ); + + R1.L = 0.125; + R1.H = 0.125; + + R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); + _DBGCMPLX R2; + _DBGCMPLX R3; + DBGA ( R2.L , 0.3125 ); + DBGA ( R2.H , 0.3125 ); + DBGA ( R3.L , 0.1875 ); + DBGA ( R3.H , 0.1875 ); + + R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR); + _DBGCMPLX R0; + _DBGCMPLX R1; + DBGA ( R0.L , 0.25 ); + DBGA ( R0.H , 0.25 ); + DBGA ( R1.L , 0.0625 ); + DBGA ( R1.H , 0.0625 ); + + R0 = 1; + R0 <<= 15; + R1 = R0 << 16; + r0=r0 | r1; + R1 = R0; + + R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); + + _DBGCMPLX R2; + _DBGCMPLX R3; + DBGA ( R0.L , 0x8000 ); + DBGA ( R0.H , 0x8000 ); + DBGA ( R1.L , 0x8000 ); + DBGA ( R1.H , 0x8000 ); + + pass diff --git a/sim/testsuite/sim/bfin/a4.s b/sim/testsuite/sim/bfin/a4.s new file mode 100644 index 0000000..d0f5ef5 --- /dev/null +++ b/sim/testsuite/sim/bfin/a4.s @@ -0,0 +1,36 @@ +# Blackfin testcase for signbits +# mach: bfin + + .include "testutils.inc" + + start + +xx: + R0 = 1; + CALL red; + JUMP.L aa; + + .align 16 +aa: + R0 = 2; + CALL red; + JUMP.S bb; + + .align 16 +bb: + R0 = 3; + CALL red; + JUMP.S ccd; + + .align 16 +red: + RTS; + + .align 16 +ccd: + R1 = 3 (Z); + CC = R0 == R1 + if CC jump 1f; + fail +1: + pass diff --git a/sim/testsuite/sim/bfin/a5.s b/sim/testsuite/sim/bfin/a5.s new file mode 100644 index 0000000..d0c0143 --- /dev/null +++ b/sim/testsuite/sim/bfin/a5.s @@ -0,0 +1,140 @@ +// ALU test program. +// Test instructions +// rL4= L+L (r2,r3); +// rH4= L+H (r2,r3) S; +// rL4= L-L (r2,r3); +// rH4= L-H (r2,r3) S; +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + +// overflow positive + R0.L = 0x0000; + R0.H = 0x7fff; + R1.L = 0x7fff; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R3.L = R0.H + R1.L (NS); + DBGA ( R3.L , 0xfffe ); + DBGA ( R3.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// overflow negative + R0.L = 0xffff; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x8000; + R3 = 0; + R7 = 0; + ASTAT = R7; + R3.H = R0.L + R1.H (NS); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate positive + R0.L = 0x0000; + R0.H = 0x7fff; + R1.L = 0x7fff; + R1.H = 0x0000; + R3 = 0; + R7 = 0; + ASTAT = R7; + R3.L = R0.H + R1.L (S); + DBGA ( R3.L , 0x7fff ); + DBGA ( R3.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// saturate negative + R0.L = 0xffff; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x8000; + R3 = 0; + R7 = 0; + ASTAT = R7; + R3.L = R0.L + R1.H (S); + DBGA ( R3.L , 0x8000 ); + DBGA ( R3.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// overflow positive with subtraction + R0.L = 0x0000; + R0.H = 0x7fff; + R1.L = 0xffff; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R3.L = R0.H - R1.L (NS); + DBGA ( R3.L , 0x8000 ); + DBGA ( R3.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// overflow negative with subtraction + R0.L = 0x8000; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x0001; + R3 = 0; + R7 = 0; + ASTAT = R7; + R3.H = R0.L - R1.H (NS); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate positive with subtraction + R0.L = 0x0000; + R0.H = 0x7fff; + R1.L = 0xffff; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R3.H = R0.H - R1.L (S); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// saturate negative with subtraction + R0.L = 0x8000; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x0001; + R3 = 0; + R7 = 0; + ASTAT = R7; + R3.H = R0.L - R1.H (S); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + + pass diff --git a/sim/testsuite/sim/bfin/a6.s b/sim/testsuite/sim/bfin/a6.s new file mode 100644 index 0000000..27de5d2 --- /dev/null +++ b/sim/testsuite/sim/bfin/a6.s @@ -0,0 +1,132 @@ +// ALU test program. +// Test instructions +// r7 = +/+ (r0,r1); +// r7 = +/+ (r0,r1) s; +// r7 = +/+ (r0,r1) sx; +# mach: bfin + +.include "testutils.inc" + start + + +// one result overflows positive + R0.L = 0x0001; + R0.H = 0x0010; + R1.L = 0x7fff; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1; + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// one result overflows negative + R0.L = 0xffff; + R0.H = 0x0010; + R1.L = 0x8000; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1; + DBGA ( R7.L , 0x7fff ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// one result zero + R0.L = 0x0001; + R0.H = 0xffff; + R1.L = 0x0001; + R1.H = 0x0001; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1; + DBGA ( R7.L , 0x0002 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R5 = CC; DBGA ( R5.L , 0x1 ); + CC = AN; R5 = CC; DBGA ( R5.L , 0x0 ); + CC = V; R5 = CC; DBGA ( R5.L , 0x0 ); + CC = AC0; R5 = CC; DBGA ( R5.L , 0x0 ); + +// one result saturates positive + R0.L = 0x0001; + R0.H = 0x0010; + R1.L = 0x7fff; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1 (S); + DBGA ( R7.L , 0x7fff ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// one result saturates negative + R0.L = 0xffff; + R0.H = 0x0010; + R1.L = 0x8000; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1 (S); + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// two results saturates negative + R0.L = 0xffff; + R0.H = 0xfff0; + R1.L = 0x8000; + R1.H = 0x8000; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1 (S); + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// one result overflows positive and cross + R0.L = 0x0001; + R0.H = 0x0010; + R1.L = 0x7fff; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1 (CO); + DBGA ( R7.L , 0x0020 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// one result saturates negative and cross + R0.L = 0xffff; + R0.H = 0x0010; + R1.L = 0x8000; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|+ R1 (SCO); + DBGA ( R7.L , 0x0020 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + + pass diff --git a/sim/testsuite/sim/bfin/a7.s b/sim/testsuite/sim/bfin/a7.s new file mode 100644 index 0000000..4fbc5f6 --- /dev/null +++ b/sim/testsuite/sim/bfin/a7.s @@ -0,0 +1,179 @@ +# mach: bfin + +.include "testutils.inc" + start + + R1 = 0; + R0 = 0; + R0 = R1 ^ R0; + +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 1 ); + cc = az; + r7 = cc; + dbga( r7.l, 1); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + R0 = R1 | R0; +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 1 ); + cc = az; + r7 = cc; + dbga( r7.l, 1); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + R0 = 0; + R1 = 1; + CC = R0 == R1; + +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 2 ); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + CC = BITTST ( R1 , 1 ); + +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 2 ); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + CC = ! BITTST( R1 , 1 ); +//_DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 0x22 ); + r7 = cc; + dbga( r7.l, 1); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + R0.L = 0; + R0.H = 0x8000; + R0 >>>= 1; + _DBG ASTAT; +//R7 = ASTAT; +//DBGA ( R7.L , 0x22 ); + cc = az; + r6 = cc; + dbga( r6.l, 0); + cc = an; + r6 = cc; + dbga( r6.l, 1); + cc = av0; + r6 = cc; + dbga( r6.l, 0); + cc = av0s; + r6 = cc; + dbga( r6.l, 0); + cc = av1; + r6 = cc; + dbga( r6.l, 0); + cc = av1s; + r6 = cc; + dbga( r6.l, 0); + + R0.L = 17767; R0.H = 291; + R1.L = 52719; R1.H = -30293; + R2.L = 39612; R2.H = 22136; + R3.L = 4660; R3.H = -8464; + R4.L = 26777; R4.H = 9029; + R5.L = 9029; R5.H = 30865; + R6.L = 21554; R6.H = -26506; + R7.L = 22136; R7.H = 4660; + R0 = R0 + R0; + R1 = R0 - R1; + R2 = R0 & R2; + R3 = R0 | R3; + R4 = R0 & R4; + R5 = R0 & R5; + R6 = R0 | R6; + R7 = R0 & R7; + DBGA ( R0.l , 35534 ); DBGA( R0.h , 582 ); + DBGA( R1.l , 48351 ); DBGA ( R1.h , 30874 ); + DBGA ( R2.l , 35468 ); DBGA ( R2.h , 576 ); + DBGA ( R3.l , 39678 ); DBGA ( R3.h , 0xdef6); + DBGA ( R4.l , 2184 ); DBGA ( R4.h , 580 ); + DBGA ( R5.l , 580 ); DBGA( R5.h , 0 ); + DBGA ( R6.l, 57086 ); DBGA ( R6.h , 0x9a76 ); + DBGA ( R7.l , 584 ); DBGA ( R7.h , 516 ); + pass diff --git a/sim/testsuite/sim/bfin/a8.s b/sim/testsuite/sim/bfin/a8.s new file mode 100644 index 0000000..23f3464 --- /dev/null +++ b/sim/testsuite/sim/bfin/a8.s @@ -0,0 +1,41 @@ +# mach: bfin + +.include "testutils.inc" + start + +// xh, h, xb, b + R0.L = 32898; R0.H = 1; + R1.L = 49346; R1.H = 3; + R2.L = 6; R2.H = -1; + R3.L = 129; R3.H = 7; + R4.L = 4; R4.H = 0; + R5.L = 5; R5.H = 0; + R6.L = 6; R6.H = 0; + R7.L = 7; R7.H = 0; + R4 = R0.L (X); + +// _DBG ASTAT; R7 = ASTAT;DBGA ( R7.L , 2 ); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + R5 = R0.L; + R6 = R1.B (X); + R7 = R1.B; + DBGA ( R4.l , 32898 ); DBGA ( R4.h , 0xffff); + pass diff --git a/sim/testsuite/sim/bfin/a9.s b/sim/testsuite/sim/bfin/a9.s new file mode 100644 index 0000000..525b17f --- /dev/null +++ b/sim/testsuite/sim/bfin/a9.s @@ -0,0 +1,219 @@ +// ALU test program. +// Test 32 bit MAX, MIN, ABS instructions +# mach: bfin + +.include "testutils.inc" + start + + +// MAX +// first operand is larger, so AN=0 + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// second operand is larger, so AN=1 + R0.L = 0x0000; + R0.H = 0x0000; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// first operand is larger, check correct output with overflow + R0.L = 0xffff; + R0.H = 0x7fff; + R1.L = 0xffff; + R1.H = 0xffff; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// second operand is larger, no overflow here + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0xffff; + R1.H = 0x7fff; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// second operand is larger, overflow + R0.L = 0xffff; + R0.H = 0x800f; + R1.L = 0xffff; + R1.H = 0x7fff; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0S; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1S; R7 = CC; DBGA ( R7.L , 0x0 ); + +// both operands equal + R0.L = 0x0080; + R0.H = 0x8000; + R1.L = 0x0080; + R1.H = 0x8000; + R7 = MAX ( R0 , R1 ); + DBGA ( R7.L , 0x0080 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// MIN +// second operand is smaller + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MIN ( R0 , R1 ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// first operand is smaller + R0.L = 0x0001; + R0.H = 0x8000; + R1.L = 0x0000; + R1.H = 0x0000; + R7 = MIN ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// first operand is smaller, overflow + R0.L = 0x0001; + R0.H = 0x8000; + R1.L = 0x0000; + R1.H = 0x0ff0; + R7 = MIN ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// equal operands + R0.L = 0x0001; + R0.H = 0x8000; + R1.L = 0x0001; + R1.H = 0x8000; + R7 = MIN ( R0 , R1 ); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// ABS + R0.L = 0x0001; + R0.H = 0x8000; + R7 = ABS R0; + _DBG R7; + _DBG ASTAT; + R6 = ASTAT; + + _DBG R6; + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); +//CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); +//CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); +//CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); +//CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); +//CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); +//CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0001; + R0.H = 0x0000; + R7 = ABS R0; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0000; + R0.H = 0x8000; + R7 = ABS R0; + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R7 = ABS R0; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0000; + R0.H = 0x0000; + R7 = ABS R0; + _DBG R7; + _DBG ASTAT; + R6 = ASTAT; + _DBG R6; + + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = VS; R6 = CC; DBGA (R6.L, 0x1); + CC = AZ; R6 = CC; DBGA (R6.L, 0x1); + + pass diff --git a/sim/testsuite/sim/bfin/abs-2.S b/sim/testsuite/sim/bfin/abs-2.S new file mode 100644 index 0000000..1e768b0 --- /dev/null +++ b/sim/testsuite/sim/bfin/abs-2.S @@ -0,0 +1,42 @@ +# Blackfin testcase for ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x8765; + R0.L = 0x4321; + R1 = ABS R0; + R7 = ASTAT; + R2.H = 0x789a; + R2.L = 0xbcdf; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AN V V_COPY */ + R3.H = HI(_AZ|_AN|_V|_V_COPY); + R3.L = LO(_AZ|_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: */ + R3.H = HI(0); + R3.L = LO(0); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/abs-3.S b/sim/testsuite/sim/bfin/abs-3.S new file mode 100644 index 0000000..44ba765 --- /dev/null +++ b/sim/testsuite/sim/bfin/abs-3.S @@ -0,0 +1,42 @@ +# Blackfin testcase for ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x0; + R0.L = 0x0; + R1 = ABS R0; + R7 = ASTAT; + R2.H = 0x0; + R2.L = 0x0; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN V V_COPY */ + R3.H = HI(_AN|_V|_V_COPY); + R3.L = LO(_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ */ + R3.H = HI(_AZ); + R3.L = LO(_AZ); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/abs-4.S b/sim/testsuite/sim/bfin/abs-4.S new file mode 100644 index 0000000..0e691e0 --- /dev/null +++ b/sim/testsuite/sim/bfin/abs-4.S @@ -0,0 +1,42 @@ +# Blackfin testcase for ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x8000; + R0.L = 0x0; + R1 = ABS R0; + R7 = ASTAT; + R2.H = 0x7fff; + R2.L = 0xffff; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AN V V_COPY */ + R3.H = HI(_AZ|_AN); + R3.L = LO(_AZ|_AN); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: V V_COPY VS */ + R3.H = HI(_V|_V_COPY|_VS); + R3.L = LO(_V|_V_COPY|_VS); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/abs.S b/sim/testsuite/sim/bfin/abs.S new file mode 100644 index 0000000..1425d42 --- /dev/null +++ b/sim/testsuite/sim/bfin/abs.S @@ -0,0 +1,42 @@ +# Blackfin testcase for ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x1234; + R0.L = 0x5678; + R1 = ABS R0; + R7 = ASTAT; + R2.H = 0x1234; + R2.L = 0x5678; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AN V V_COPY */ + R3.H = HI(_AZ|_AN|_V|_V_COPY); + R3.L = LO(_AZ|_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: */ + R3.H = HI(0); + R3.L = LO(0); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/abs_acc.s b/sim/testsuite/sim/bfin/abs_acc.s new file mode 100644 index 0000000..99ed052 --- /dev/null +++ b/sim/testsuite/sim/bfin/abs_acc.s @@ -0,0 +1,224 @@ +// ACP 5.7 ABS(A1) sets AV0 +# mach: bfin + +.include "testutils.inc" + start + + r1=0x80 (z); + A0=0; + A0.x=r1; + A0=abs A0; + _DBG astat; +//r7=astat; +//dbga (r7.h, 0x3); +//dbga (r7.l, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 1); + cc = av0s; + r7 = cc; + dbga( r7.l, 1); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + r6=A0.x; + dbga (r6.l, 0x7f); + + r1=0x80 (z); + A1=0; + A1.x=r1; + A1=abs A1; + _DBG astat; +//r7=astat; +//dbga (r7.h, 0xf); +//dbga (r7.l, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 1); + cc = av0s; + r7 = cc; + dbga( r7.l, 1); + cc = av1; + r7 = cc; + dbga( r7.l, 1); + cc = av1s; + r7 = cc; + dbga( r7.l, 1); + + r6=A1.x; + dbga (r6.l, 0x7f); + + r7=0; + astat=r7; + r1=0x80 (z); + A1=0; + A1.x=r1; + A0 = abs A1; + _DBG astat; +//r7=astat; +//dbga (r7.h, 0x3); +//dbga (r7.l, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 1); + cc = av0s; + r7 = cc; + dbga( r7.l, 1); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + r6=A0.x; + dbga (r6.l, 0x7f); + + r7=0; + astat=r7; + r1=0x80 (z); + A0=0; + A0.x=r1; + A1 = abs A0; + _DBG astat; +//r7=astat; +//dbga (r7.h, 0xc); +//dbga (r7.l, 0x0); + cc = az; + r3 = cc; + dbga( r3.l, 0); + cc = an; + r3 = cc; + dbga( r3.l, 0); + cc = av0; + r3 = cc; + dbga( r3.l, 0); + cc = av0s; + r3 = cc; + dbga( r3.l, 0); + cc = av1; + r3 = cc; + dbga( r3.l, 1); + cc = av1s; + r3 = cc; + dbga( r3.l, 1); + + r6=A1.x; + dbga (r6.l, 0x7f); + + r7=0; + astat=r7; + r1=0x80 (z); + A1=0; + A1.x=r1; + A0.x=r6; + _DBG A1; + _DBG A0; + A1=abs A1, A0=abs A0; + _DBG ASTAT; +//r7=astat; +//dbga (r7.h, 0xc); +//dbga (r7.l, 0x0); + cc = az; + r4 = cc; + dbga( r4.l, 0); + cc = an; + r4 = cc; + dbga( r4.l, 0); + cc = av0; + r4 = cc; + dbga( r4.l, 0); + cc = av0s; + r4 = cc; + dbga( r4.l, 0); + cc = av1; + r4 = cc; + dbga( r4.l, 1); + cc = av1s; + r4 = cc; + dbga( r4.l, 1); + + r7=0; + astat=r7; + r1=0x80 (z); + A1=0; + A1.x=r1; + A0 = A1; + A1=abs A1, A0=abs A0; + _DBG ASTAT; +//r7=astat; +//dbga (r7.h, 0xf); +//dbga (r7.l, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 1); + cc = av0s; + r7 = cc; + dbga( r7.l, 1); + cc = av1; + r7 = cc; + dbga( r7.l, 1); + cc = av1s; + r7 = cc; + dbga( r7.l, 1); + +// ACP 5.8 ABS sometimes sets AN + + r7=0; + astat=r7; + r0=1; + r1=abs r0; + _DBG r0; + _DBG r1; + _DBG astat; +//r7=astat; +//dbga (r7.h, 0x0); +//dbga (r7.l, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + + pass; diff --git a/sim/testsuite/sim/bfin/acc-rot.s b/sim/testsuite/sim/bfin/acc-rot.s new file mode 100644 index 0000000..ccf307c --- /dev/null +++ b/sim/testsuite/sim/bfin/acc-rot.s @@ -0,0 +1,129 @@ +# Blackfin testcase for Accumulator Rotates (ROT) +# mach: bfin + + .include "testutils.inc" + + .macro atest_setup acc:req, val_x:req, val_w:req, cc:req, shift:req + imm32 R0, \val_w + imm32 R1, \val_x + R2 = \cc; + R3 = \shift + \acc\().W = R0; + \acc\().X = R1; + CC = R2; + .endm + + .macro atest_check acc:req, exp_x:req, exp_w:req, expcc:req + R7 = CC; + CHECKREG R7, \expcc; + + R2 = \acc\().W; + CHECKREG R2, \exp_w; + + R6 = \acc\().X; + R6 = R6.B (z); + CHECKREG R6, \exp_x; + .endm + + .macro _atest acc:req, val_x:req, val_w:req, cc:req, shift:req, exp_x:req, exp_w:req, expcc:req + atest_setup \acc, \val_x, \val_w, \cc, \shift + _DBG \acc; + \acc = ROT \acc BY \shift; + atest_check \acc, \exp_x, \exp_w, \expcc + + atest_setup \acc, \val_x, \val_w, \cc, \shift + \acc = ROT \acc BY R3.L; + atest_check \acc, \exp_x, \exp_w, \expcc + .endm + + .macro atest val_x:req, val_w:req, cc:req, shift:req, exp_x:req, exp_w:req, expcc:req + _atest A0, \val_x, \val_w, \cc, \shift, \exp_x, \exp_w, \expcc + _atest A1, \val_x, \val_w, \cc, \shift, \exp_x, \exp_w, \expcc + .endm + + start + + atest 0x00, 0x00000000, 0, 0, 0x00, 0x00000000, 0 + atest 0xa5, 0xa5a5a5a5, 0, 0, 0xa5, 0xa5a5a5a5, 0 + atest 0x00, 0x00000000, 1, 0, 0x00, 0x00000000, 1 + atest 0xa5, 0xa5a5a5a5, 1, 0, 0xa5, 0xa5a5a5a5, 1 + atest 0x00, 0x00000000, 0, 10, 0x00, 0x00000000, 0 + + atest 0x00, 0x0000000f, 0, 4, 0x00, 0x000000f0, 0 + atest 0x00, 0x0000000f, 1, 4, 0x00, 0x000000f8, 0 + atest 0x00, 0x0000000f, 0, 20, 0x00, 0x00f00000, 0 + atest 0x00, 0x0000000f, 1, 20, 0x00, 0x00f80000, 0 + atest 0x00, 0x0000000f, 0, -5, 0xf0, 0x00000000, 0 + atest 0x00, 0x0000000f, 1, -5, 0xf8, 0x00000000, 0 + atest 0x00, 0x0000000f, 0, -1, 0x00, 0x00000007, 1 + atest 0x00, 0x0000000f, 1, -1, 0x80, 0x00000007, 1 + + atest 0xff, 0xffffffff, 1, 10, 0xff, 0xffffffff, 1 + atest 0x11, 0x11111110, 0, -5, 0x00, 0x88888888, 1 + + atest 0x1f, 0x2e3d4c5b, 1, 0, 0x1f, 0x2e3d4c5b, 1 + atest 0x1f, 0x2e3d4c5b, 1, 1, 0x3e, 0x5c7a98b7, 0 + atest 0x1f, 0x2e3d4c5b, 1, 2, 0x7c, 0xb8f5316e, 0 + atest 0x1f, 0x2e3d4c5b, 1, 3, 0xf9, 0x71ea62dc, 0 + atest 0x1f, 0x2e3d4c5b, 1, 4, 0xf2, 0xe3d4c5b8, 1 + atest 0x1f, 0x2e3d4c5b, 1, 5, 0xe5, 0xc7a98b71, 1 + atest 0x1f, 0x2e3d4c5b, 1, 6, 0xcb, 0x8f5316e3, 1 + atest 0x1f, 0x2e3d4c5b, 1, 7, 0x97, 0x1ea62dc7, 1 + atest 0x1f, 0x2e3d4c5b, 1, 8, 0x2e, 0x3d4c5b8f, 1 + atest 0x1f, 0x2e3d4c5b, 1, 9, 0x5c, 0x7a98b71f, 0 + atest 0x1f, 0x2e3d4c5b, 1, 10, 0xb8, 0xf5316e3e, 0 + atest 0x1f, 0x2e3d4c5b, 1, 11, 0x71, 0xea62dc7c, 1 + atest 0x1f, 0x2e3d4c5b, 1, 12, 0xe3, 0xd4c5b8f9, 0 + atest 0x1f, 0x2e3d4c5b, 1, 13, 0xc7, 0xa98b71f2, 1 + atest 0x1f, 0x2e3d4c5b, 1, 14, 0x8f, 0x5316e3e5, 1 + atest 0x1f, 0x2e3d4c5b, 1, 15, 0x1e, 0xa62dc7cb, 1 + atest 0x1f, 0x2e3d4c5b, 1, 16, 0x3d, 0x4c5b8f97, 0 + atest 0x1f, 0x2e3d4c5b, 1, 17, 0x7a, 0x98b71f2e, 0 + atest 0x1f, 0x2e3d4c5b, 1, 18, 0xf5, 0x316e3e5c, 0 + atest 0x1f, 0x2e3d4c5b, 1, 19, 0xea, 0x62dc7cb8, 1 + atest 0x1f, 0x2e3d4c5b, 1, 20, 0xd4, 0xc5b8f971, 1 + atest 0x1f, 0x2e3d4c5b, 1, 21, 0xa9, 0x8b71f2e3, 1 + atest 0x1f, 0x2e3d4c5b, 1, 22, 0x53, 0x16e3e5c7, 1 + atest 0x1f, 0x2e3d4c5b, 1, 23, 0xa6, 0x2dc7cb8f, 0 + atest 0x1f, 0x2e3d4c5b, 1, 24, 0x4c, 0x5b8f971e, 1 + atest 0x1f, 0x2e3d4c5b, 1, 25, 0x98, 0xb71f2e3d, 0 + atest 0x1f, 0x2e3d4c5b, 1, 26, 0x31, 0x6e3e5c7a, 1 + atest 0x1f, 0x2e3d4c5b, 1, 27, 0x62, 0xdc7cb8f5, 0 + atest 0x1f, 0x2e3d4c5b, 1, 28, 0xc5, 0xb8f971ea, 0 + atest 0x1f, 0x2e3d4c5b, 1, 29, 0x8b, 0x71f2e3d4, 1 + atest 0x1f, 0x2e3d4c5b, 1, 30, 0x16, 0xe3e5c7a9, 1 + atest 0x1f, 0x2e3d4c5b, 1, 31, 0x2d, 0xc7cb8f53, 0 + atest 0x1f, 0x2e3d4c5b, 1, -1, 0x8f, 0x971ea62d, 1 + atest 0x1f, 0x2e3d4c5b, 1, -2, 0xc7, 0xcb8f5316, 1 + atest 0x1f, 0x2e3d4c5b, 1, -3, 0xe3, 0xe5c7a98b, 0 + atest 0x1f, 0x2e3d4c5b, 1, -4, 0x71, 0xf2e3d4c5, 1 + atest 0x1f, 0x2e3d4c5b, 1, -5, 0xb8, 0xf971ea62, 1 + atest 0x1f, 0x2e3d4c5b, 1, -6, 0xdc, 0x7cb8f531, 0 + atest 0x1f, 0x2e3d4c5b, 1, -7, 0x6e, 0x3e5c7a98, 1 + atest 0x1f, 0x2e3d4c5b, 1, -8, 0xb7, 0x1f2e3d4c, 0 + atest 0x1f, 0x2e3d4c5b, 1, -9, 0x5b, 0x8f971ea6, 0 + atest 0x1f, 0x2e3d4c5b, 1, -10, 0x2d, 0xc7cb8f53, 0 + atest 0x1f, 0x2e3d4c5b, 1, -11, 0x16, 0xe3e5c7a9, 1 + atest 0x1f, 0x2e3d4c5b, 1, -12, 0x8b, 0x71f2e3d4, 1 + atest 0x1f, 0x2e3d4c5b, 1, -13, 0xc5, 0xb8f971ea, 0 + atest 0x1f, 0x2e3d4c5b, 1, -14, 0x62, 0xdc7cb8f5, 0 + atest 0x1f, 0x2e3d4c5b, 1, -15, 0x31, 0x6e3e5c7a, 1 + atest 0x1f, 0x2e3d4c5b, 1, -16, 0x98, 0xb71f2e3d, 0 + atest 0x1f, 0x2e3d4c5b, 1, -17, 0x4c, 0x5b8f971e, 1 + atest 0x1f, 0x2e3d4c5b, 1, -18, 0xa6, 0x2dc7cb8f, 0 + atest 0x1f, 0x2e3d4c5b, 1, -19, 0x53, 0x16e3e5c7, 1 + atest 0x1f, 0x2e3d4c5b, 1, -20, 0xa9, 0x8b71f2e3, 1 + atest 0x1f, 0x2e3d4c5b, 1, -21, 0xd4, 0xc5b8f971, 1 + atest 0x1f, 0x2e3d4c5b, 1, -22, 0xea, 0x62dc7cb8, 1 + atest 0x1f, 0x2e3d4c5b, 1, -23, 0xf5, 0x316e3e5c, 0 + atest 0x1f, 0x2e3d4c5b, 1, -24, 0x7a, 0x98b71f2e, 0 + atest 0x1f, 0x2e3d4c5b, 1, -25, 0x3d, 0x4c5b8f97, 0 + atest 0x1f, 0x2e3d4c5b, 1, -26, 0x1e, 0xa62dc7cb, 1 + atest 0x1f, 0x2e3d4c5b, 1, -27, 0x8f, 0x5316e3e5, 1 + atest 0x1f, 0x2e3d4c5b, 1, -28, 0xc7, 0xa98b71f2, 1 + atest 0x1f, 0x2e3d4c5b, 1, -29, 0xe3, 0xd4c5b8f9, 0 + atest 0x1f, 0x2e3d4c5b, 1, -30, 0x71, 0xea62dc7c, 1 + atest 0x1f, 0x2e3d4c5b, 1, -31, 0xb8, 0xf5316e3e, 0 + atest 0x1f, 0x2e3d4c5b, 1, -32, 0x5c, 0x7a98b71f, 0 + + pass diff --git a/sim/testsuite/sim/bfin/acp5_19.s b/sim/testsuite/sim/bfin/acp5_19.s new file mode 100644 index 0000000..74e7552 --- /dev/null +++ b/sim/testsuite/sim/bfin/acp5_19.s @@ -0,0 +1,12 @@ +# mach: bfin + +.include "testutils.inc" + start + + r0.h=0xa5a5; + r0.l=0xffff; + a0 = 0; + r0=a0.x; + dbga(r0.h, 0x0000); + dbga(r0.l, 0x0000); + pass; diff --git a/sim/testsuite/sim/bfin/acp5_4.s b/sim/testsuite/sim/bfin/acp5_4.s new file mode 100644 index 0000000..993f7ba --- /dev/null +++ b/sim/testsuite/sim/bfin/acp5_4.s @@ -0,0 +1,39 @@ +// test RND setting AZ +# mach: bfin + +.include "testutils.inc" + start + + +// result is zero with overflow ==> AZ, therefore, is not set + R0.L = 0x8000; + R0 = R0.L (X); + R1.L = R0 (RND); + CC = AZ; R7 = CC; + DBGA(R1.L, 0); + DBGA ( R7.L , 0x1 ); + +// No Overflow, result is zero, AZ is set + R0 = 1 (X); + R1.L = r0 (RND); + CC = AZ; R7 = CC; + DBGA(R1.L, 0); + DBGA ( R7.L , 0x1 ); + +// result should be 1 + R0.L = 0x8000; + R0.H = 0; + R1.L = R0 (RND); + CC = AZ; R7 = CC; + DBGA(R1.L, 1); + DBGA ( R7.L , 0x0 ); + +// Result should be non-zero + R0.H = 0x7ff0; + R0.L = 0x8000; + R1.L = R0 (RND); + CC = AZ; R7 = CC; + DBGA(R1.L, 0x7ff1); + DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/sim/bfin/add_imm7.s b/sim/testsuite/sim/bfin/add_imm7.s new file mode 100644 index 0000000..31f1538 --- /dev/null +++ b/sim/testsuite/sim/bfin/add_imm7.s @@ -0,0 +1,38 @@ +# mach: bfin + +.include "testutils.inc" + start + + r0 = 0 + ASTAT = r0; + + r2=-7; + r2+=-63; + _dbg r2; + _dbg astat; + r7=astat; + dbga ( r7.h, 0x0); + dbga ( r7.l, 0x1006); + + r7=0; + astat=r7; + r2=64; + r2+=-64; + _dbg r2; + _dbg astat; + r7=astat; + dbga ( r7.h, 0x0); + dbga ( r7.l, 0x1005); + + r7=0; + astat=r7; + r2=0; + r2.h=0x8000; + r2+=-63; + _dbg astat; + _dbg r2; + r7=astat; + dbga ( r7.h, 0x0300); + dbga ( r7.l, 0x100c); + + pass diff --git a/sim/testsuite/sim/bfin/add_shift.S b/sim/testsuite/sim/bfin/add_shift.S new file mode 100644 index 0000000..8a8bf63 --- /dev/null +++ b/sim/testsuite/sim/bfin/add_shift.S @@ -0,0 +1,53 @@ +// ACP 5.6 Flags for dreg=(dreg+dreg)<<1,2 +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + + r1=0; + ASTAT = R1; + r2=0; + r2.h=0x4000; + r2=(r2+r1)<<2; + dbga (r2.l,0x0); + dbga (r2.h,0x0); + _dbg ASTAT; + r7=ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AZ) + + r2=0; + r2.h=0x4000; + r2=(r2+r1)<<1; + dbga (r2.l,0x0); + dbga (r2.h,0x8000); + _dbg ASTAT; + r7=ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AN) + + r1=0; + r1.h=0xd300; + r2=0; + r2.h=0xb700; + r2=(r2+r1)<<1; + dbga (r2.l,0x0); + dbga (r2.h,0x1400); + _dbg ASTAT; + r7=ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY) + + r0 = 1; + r0 <<= 31; // r0 should be 0x80000000 + r7 = 0; + ASTAT = r7; + _dbg r0; + r1 = r0; + _dbg r1; + r1 = (r1 + r0) << 1; // add overflows to zero, no shift overflow + _dbg r1; + _dbg ASTAT; + r7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AZ); + + pass diff --git a/sim/testsuite/sim/bfin/add_sub_acc.s b/sim/testsuite/sim/bfin/add_sub_acc.s new file mode 100644 index 0000000..84416d0 --- /dev/null +++ b/sim/testsuite/sim/bfin/add_sub_acc.s @@ -0,0 +1,123 @@ +// ACP 5.9 A0 -= A1 doesn't set flags +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + R0 = 0x0; + astat=r0; + A0.w = R0; + R0.L = 0x0080; + A0.x = R0; + R1 = 1; + + _DBG A0; + _DBG A1; + + A0 -= A1; + _dbg A0; + _dbg ASTAT; + r7=astat; + dbga (r7.h, 0x0); + dbga (r7.l, 0x1006); + + A1 = A0 = 0; + R0 = 0x1 (z); + astat=r0; + A0.w = R0; + R0.L = 0x0080; + A0.x = R0; + R1 = 1; + + _DBG A0; + _DBG A1; + + A0 -= A1; + _dbg A0; + _dbg ASTAT; + r7=astat; + dbga (r7.h, 0x0); + dbga (r7.l, 0x1006); + + A1 = A0 = 0; + R0 = 0x0; + astat=r0; + A0.w = R0; + R0.L = 0x0080; + A0.x = R0; + R1 = 1; + A1 = R1; + + _DBG A0; + _DBG A1; + + A0 -= A1; + _dbg A0; + _dbg ASTAT; + r7=astat; + dbga (r7.h, 0x3); + dbga (r7.l, 0x1006); + + A1 = A0 = 0; + R0 = 0x1 (z); + astat=r0; + A0.w = R0; + R0.L = 0x0080; + A0.x = R0; + R1 = 2 (z); + A1 = R1; + + _DBG A0; + _DBG A1; + + A0 -= A1; + _dbg A0; + _dbg ASTAT; + r7=astat; + dbga (r7.h, 0x3); + dbga (r7.l, 0x1006); + + # + + A1 = A0 = 0; + R0 = 0x0; + astat=r0; + R0.L=0xffff; + R0.H=0xffff; + A0.w = R0; + R1=0x7f; + A0.x = R1; + A1.x = R1; + A1.w = R0; + + _DBG A0; + _DBG A1; + + A0 += A1; + _dbg A0; + _dbg ASTAT; + r7=astat; + dbga (r7.h, 0x3); + dbga (r7.l, 0x0); + + A1 = A0 = 0; + R0 = 0x0; + astat=r0; + A0.w = R0; + R1=0x80; + A0.x = R1; + A1.x = R1; + A1.w = R0; + + _DBG A0; + _DBG A1; + + A0 += A1; + _dbg A0; + _dbg ASTAT; + r7=astat; + dbga (r7.h, 0x3); + dbga (r7.l, 0x1006); + + pass; diff --git a/sim/testsuite/sim/bfin/addsub_flags.S b/sim/testsuite/sim/bfin/addsub_flags.S new file mode 100644 index 0000000..78319c5 --- /dev/null +++ b/sim/testsuite/sim/bfin/addsub_flags.S @@ -0,0 +1,107 @@ +// ACP 5.17 Dual ALU ops +// AZ, AN, AC0, AC1, V and VS are affected +// AV0, AV0S, AV1, AV1S are unaffected +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + A0 = A1 = 0; + + r0=0; + r0.h=0x7fff; + r2=0; + r2.h=0x7000; + r1=r0+r2,r3=r0-r2; + r7=astat; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); + + a1=r2; + a0=r0; + r1=a0+a1, r3=a0-a1; + r7=astat; + _dbg a0; + _dbg a1; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); + + a0=r2; + a1=r0; + r1=a1+a0, r3=a1-a0; + r7=astat; + _dbg a0; + _dbg a1; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); + + r0.h=0xafff; + r2.h=0xa000; + a1=r2; + a0=r0; + r1=a0+a1, r3=a0-a1; + r7=astat; + _dbg a0; + _dbg a1; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); + + r1=a0+a1, r3=a0-a1 (s); + r7=astat; + _dbg a0; + _dbg a1; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1|_AN); + + r0.h=0xafff; + r2.h=0xa000; + a0=r2; + a1=r0; + r1=a1+a0, r3=a1-a0; + r7=astat; + _dbg a0; + _dbg a1; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); + + r1=a1+a0, r3=a1-a0 (s); + r7=astat; + _dbg a0; + _dbg a1; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1|_AN); + + r2.h=0x8001; + r1=r0+r2,r3=r0-r2; + _dbg r1; + _dbg r3; + _dbg astat; + r7=astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); + + r2.h=0x8000; + r1=r0+r2,r3=r0-r2; + r7=astat; + _dbg r1; + _dbg r3; + _dbg astat; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); + + pass; diff --git a/sim/testsuite/sim/bfin/algnbug1.s b/sim/testsuite/sim/bfin/algnbug1.s new file mode 100644 index 0000000..be0363b --- /dev/null +++ b/sim/testsuite/sim/bfin/algnbug1.s @@ -0,0 +1,38 @@ +# mach: bfin + +.include "testutils.inc" + start + + + loadsym P0, blocka; + I0 = P0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + I0 = P0; + M0 = 1 (X); + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + pass + + .data + .align 8 +blocka: + .dw 0xfeff + .dw 0xfcfd + .dw 0xfafb + .dw 0xf8f9 diff --git a/sim/testsuite/sim/bfin/algnbug2.s b/sim/testsuite/sim/bfin/algnbug2.s new file mode 100644 index 0000000..b06d5ad --- /dev/null +++ b/sim/testsuite/sim/bfin/algnbug2.s @@ -0,0 +1,69 @@ +# mach: bfin + +.include "testutils.inc" + start + + + M0 = 1 (X); + loadsym I0, blocka; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + loadsym I0, blocka; + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + loadsym I0, blocka; + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + loadsym I0, blocka; + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.L , 0xfeff ); + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + loadsym I0, blocka; + I0 += M0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I0 ++ ]; + + DBGA ( R0.H , 0xfcfd ); + DBGA ( R1.L , 0xfafb ); + DBGA ( R1.H , 0xf8f9 ); + + pass + + .data; + .align 8 +blocka: + .dw 0xfeff + .dw 0xfcfd + .dw 0xfafb + .dw 0xf8f9 diff --git a/sim/testsuite/sim/bfin/allinsn.exp b/sim/testsuite/sim/bfin/allinsn.exp new file mode 100644 index 0000000..49c868a --- /dev/null +++ b/sim/testsuite/sim/bfin/allinsn.exp @@ -0,0 +1,15 @@ +# Analog Devices Blackfin simulator testsuite + +if [istarget bfin-*-elf] { + # all machines + set all_machs "bfin" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.\[csS\]]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/bfin/argc.c b/sim/testsuite/sim/bfin/argc.c new file mode 100644 index 0000000..21f1fef --- /dev/null +++ b/sim/testsuite/sim/bfin/argc.c @@ -0,0 +1,31 @@ +/* Basic argc/argv tests. +# mach: bfin +# cc: -msim +# progopts: a bb ccc dddd +*/ + +int streq(const char *s1, const char *s2) +{ + int i = 0; + + while (s1[i] && s2[i] && s1[i] == s2[i]) + ++i; + + return s1[i] == '\0' && s2[i] == '\0'; +} + +int main(int argc, char *argv[]) +{ + if (argc != 5) + return 1; + if (!streq(argv[1], "a")) + return 2; + if (!streq(argv[2], "bb")) + return 2; + if (!streq(argv[3], "ccc")) + return 2; + if (!streq(argv[4], "dddd")) + return 2; + puts("pass"); + return 0; +} diff --git a/sim/testsuite/sim/bfin/ashift.s b/sim/testsuite/sim/bfin/ashift.s new file mode 100644 index 0000000..de0b36e --- /dev/null +++ b/sim/testsuite/sim/bfin/ashift.s @@ -0,0 +1,323 @@ +# Blackfin testcase for ashift +# mach: bfin + + .include "testutils.inc" + + .macro ashift_test in:req, shift:req, out:req, opt + r0 = \in (Z); + r2.L = \shift; + r2.h = ASHIFT R0.L BY R2.L \opt; + DBGA (r2.h, \out); + .endm + + start + + /* + * 16-bit ashift and lshift uses a 6-bit signed magnitude, which + * gives a range from -32 to 31. In the case where the magnitude + * is -32, make sure the answer is correct. + */ + +ashift_test 0x8001, 33, 0xffff; +ashift_test 0x8001, 32, 0xffff; +ashift_test 0x8001, 31, 0x0000; +ashift_test 0x8001, 30, 0x0000; +ashift_test 0x8001, 29, 0x0000; +ashift_test 0x8001, 28, 0x0000; +ashift_test 0x8001, 27, 0x0000; +ashift_test 0x8001, 26, 0x0000; +ashift_test 0x8001, 25, 0x0000; +ashift_test 0x8001, 24, 0x0000; +ashift_test 0x8001, 23, 0x0000; +ashift_test 0x8001, 22, 0x0000; +ashift_test 0x8001, 21, 0x0000; +ashift_test 0x8001, 20, 0x0000; +ashift_test 0x8001, 19, 0x0000; +ashift_test 0x8001, 18, 0x0000; +ashift_test 0x8001, 17, 0x0000; +ashift_test 0x8001, 16, 0x0000; +ashift_test 0x8001, 15, 0x8000; +ashift_test 0x8001, 14, 0x4000; +ashift_test 0x8001, 13, 0x2000; +ashift_test 0x8001, 12, 0x1000; +ashift_test 0x8001, 11, 0x0800; +ashift_test 0x8001, 10, 0x0400; +ashift_test 0x8001, 9, 0x0200; +ashift_test 0x8001, 8, 0x0100; +ashift_test 0x8001, 7, 0x0080; +ashift_test 0x8001, 6, 0x0040; +ashift_test 0x8001, 5, 0x0020; +ashift_test 0x8001, 4, 0x0010; +ashift_test 0x8001, 3, 0x0008; +ashift_test 0x8001, 2, 0x0004; +ashift_test 0x8001, 1, 0x0002; +ashift_test 0x8001, 0, 0x8001; +ashift_test 0x8001, -1, 0xc000; +ashift_test 0x8001, -2, 0xe000; +ashift_test 0x8001, -3, 0xf000; +ashift_test 0x8001, -4, 0xf800; +ashift_test 0x8001, -5, 0xfc00; +ashift_test 0x8001, -6, 0xfe00; +ashift_test 0x8001, -7, 0xff00; +ashift_test 0x8001, -8, 0xff80; +ashift_test 0x8001, -9, 0xffc0; +ashift_test 0x8001, -10, 0xffe0; +ashift_test 0x8001, -11, 0xfff0; +ashift_test 0x8001, -12, 0xfff8; +ashift_test 0x8001, -13, 0xfffc; +ashift_test 0x8001, -14, 0xfffe; +ashift_test 0x8001, -15, 0xffff; +ashift_test 0x8001, -16, 0xffff; +ashift_test 0x8001, -17, 0xffff; +ashift_test 0x8001, -18, 0xffff; +ashift_test 0x8001, -19, 0xffff; +ashift_test 0x8001, -20, 0xffff; +ashift_test 0x8001, -21, 0xffff; +ashift_test 0x8001, -22, 0xffff; +ashift_test 0x8001, -23, 0xffff; +ashift_test 0x8001, -24, 0xffff; +ashift_test 0x8001, -25, 0xffff; +ashift_test 0x8001, -26, 0xffff; +ashift_test 0x8001, -27, 0xffff; +ashift_test 0x8001, -28, 0xffff; +ashift_test 0x8001, -29, 0xffff; +ashift_test 0x8001, -30, 0xffff; +ashift_test 0x8001, -31, 0xffff; +ashift_test 0x8001, -32, 0xffff; +ashift_test 0x8001, -33, 0x0; +ashift_test 0x8001, -34, 0x0; + +ashift_test 0x8001, 33, 0xffff, (S); +ashift_test 0x8001, 32, 0xffff, (S); +ashift_test 0x8001, 31, 0x8000, (S); +ashift_test 0x8001, 30, 0x8000, (S); +ashift_test 0x8001, 29, 0x8000, (S); +ashift_test 0x8001, 28, 0x8000, (S); +ashift_test 0x8001, 27, 0x8000, (S); +ashift_test 0x8001, 26, 0x8000, (S); +ashift_test 0x8001, 25, 0x8000, (S); +ashift_test 0x8001, 24, 0x8000, (S); +ashift_test 0x8001, 23, 0x8000, (S); +ashift_test 0x8001, 22, 0x8000, (S); +ashift_test 0x8001, 21, 0x8000, (S); +ashift_test 0x8001, 20, 0x8000, (S); +ashift_test 0x8001, 19, 0x8000, (S); +ashift_test 0x8001, 18, 0x8000, (S); +ashift_test 0x8001, 17, 0x8000, (S); +ashift_test 0x8001, 16, 0x8000, (S); +ashift_test 0x8001, 15, 0x8000, (S); +ashift_test 0x8001, 14, 0x8000, (S); +ashift_test 0x8001, 13, 0x8000, (S); +ashift_test 0x8001, 12, 0x8000, (S); +ashift_test 0x8001, 11, 0x8000, (S); +ashift_test 0x8001, 10, 0x8000, (S); +ashift_test 0x8001, 9, 0x8000, (S); +ashift_test 0x8001, 8, 0x8000, (S); +ashift_test 0x8001, 7, 0x8000, (S); +ashift_test 0x8001, 6, 0x8000, (S); +ashift_test 0x8001, 5, 0x8000, (S); +ashift_test 0x8001, 4, 0x8000, (S); +ashift_test 0x8001, 3, 0x8000, (S); +ashift_test 0x8001, 2, 0x8000, (S); +ashift_test 0x8001, 1, 0x8000, (S); +ashift_test 0x8001, 0, 0x8001, (S); +ashift_test 0x8001, -1, 0xc000, (S); +ashift_test 0x8001, -2, 0xe000, (S); +ashift_test 0x8001, -3, 0xf000, (S); +ashift_test 0x8001, -4, 0xf800, (S); +ashift_test 0x8001, -5, 0xfc00, (S); +ashift_test 0x8001, -6, 0xfe00, (S); +ashift_test 0x8001, -7, 0xff00, (S); +ashift_test 0x8001, -8, 0xff80, (S); +ashift_test 0x8001, -9, 0xffc0, (S); +ashift_test 0x8001, -10, 0xffe0, (S); +ashift_test 0x8001, -11, 0xfff0, (S); +ashift_test 0x8001, -12, 0xfff8, (S); +ashift_test 0x8001, -13, 0xfffc, (S); +ashift_test 0x8001, -14, 0xfffe, (S); +ashift_test 0x8001, -15, 0xffff, (S); +ashift_test 0x8001, -16, 0xffff, (S); +ashift_test 0x8001, -17, 0xffff, (S); +ashift_test 0x8001, -18, 0xffff, (S); +ashift_test 0x8001, -19, 0xffff, (S); +ashift_test 0x8001, -20, 0xffff, (S); +ashift_test 0x8001, -21, 0xffff, (S); +ashift_test 0x8001, -22, 0xffff, (S); +ashift_test 0x8001, -23, 0xffff, (S); +ashift_test 0x8001, -24, 0xffff, (S); +ashift_test 0x8001, -25, 0xffff, (S); +ashift_test 0x8001, -26, 0xffff, (S); +ashift_test 0x8001, -27, 0xffff, (S); +ashift_test 0x8001, -28, 0xffff, (S); +ashift_test 0x8001, -29, 0xffff, (S); +ashift_test 0x8001, -30, 0xffff, (S); +ashift_test 0x8001, -31, 0xffff, (S); +ashift_test 0x8001, -32, 0xffff, (S); +ashift_test 0x8001, -33, 0x8000, (S); +ashift_test 0x8001, -34, 0x8000, (S); + + +ashift_test 0x4002, 33, 0x0; +ashift_test 0x4002, 32, 0x0; +ashift_test 0x4002, 31, 0x0; +ashift_test 0x4002, 30, 0x0; +ashift_test 0x4002, 20, 0x0; +ashift_test 0x4002, 19, 0x0; +ashift_test 0x4002, 18, 0x0; +ashift_test 0x4002, 17, 0x0; +ashift_test 0x4002, 16, 0x0; +ashift_test 0x4002, 15, 0x0; +ashift_test 0x4002, 14, 0x8000; +ashift_test 0x4002, 13, 0x4000; +ashift_test 0x4002, 12, 0x2000; +ashift_test 0x4002, 11, 0x1000; +ashift_test 0x4002, 10, 0x0800; +ashift_test 0x4002, 9, 0x0400; +ashift_test 0x4002, 8, 0x0200; +ashift_test 0x4002, 7, 0x0100; +ashift_test 0x4002, 6, 0x0080; +ashift_test 0x4002, 5, 0x0040; +ashift_test 0x4002, 4, 0x0020; +ashift_test 0x4002, 3, 0x0010; +ashift_test 0x4002, 2, 0x0008; +ashift_test 0x4002, 1, 0x8004; +ashift_test 0x4002, 0, 0x4002; +ashift_test 0x4002, -1, 0x2001; +ashift_test 0x4002, -2, 0x1000; +ashift_test 0x4002, -3, 0x0800; +ashift_test 0x4002, -4, 0x0400; +ashift_test 0x4002, -5, 0x0200; +ashift_test 0x4002, -6, 0x0100; +ashift_test 0x4002, -7, 0x0080; +ashift_test 0x4002, -8, 0x0040; +ashift_test 0x4002, -9, 0x0020; +ashift_test 0x4002, -10, 0x0010; +ashift_test 0x4002, -11, 0x0008; +ashift_test 0x4002, -12, 0x0004; +ashift_test 0x4002, -13, 0x0002; +ashift_test 0x4002, -14, 0x0001; +ashift_test 0x4002, -15, 0x0; +ashift_test 0x4002, -16, 0x0; +ashift_test 0x4002, -17, 0x0; +ashift_test 0x4002, -31, 0x0; +ashift_test 0x4002, -32, 0x0; +ashift_test 0x4002, -33, 0x0; +ashift_test 0x4002, -34, 0x0; + +ashift_test 0x4002, 33, 0x0, (S); +ashift_test 0x4002, 32, 0x0, (S); +ashift_test 0x4002, 31, 0x7fff, (S); +ashift_test 0x4002, 30, 0x7fff, (S); +ashift_test 0x4002, 20, 0x7fff, (S); +ashift_test 0x4002, 19, 0x7fff, (S); +ashift_test 0x4002, 18, 0x7fff, (S); +ashift_test 0x4002, 17, 0x7fff, (S); +ashift_test 0x4002, 16, 0x7fff, (S); +ashift_test 0x4002, 15, 0x7fff, (S); +ashift_test 0x4002, 14, 0x7fff, (S); +ashift_test 0x4002, 13, 0x7fff, (S); +ashift_test 0x4002, 12, 0x7fff, (S); +ashift_test 0x4002, 11, 0x7fff, (S); +ashift_test 0x4002, 10, 0x7fff, (S); +ashift_test 0x4002, 9, 0x7fff, (S); +ashift_test 0x4002, 8, 0x7fff, (S); +ashift_test 0x4002, 7, 0x7fff, (S); +ashift_test 0x4002, 6, 0x7fff, (S); +ashift_test 0x4002, 5, 0x7fff, (S); +ashift_test 0x4002, 4, 0x7fff, (S); +ashift_test 0x4002, 3, 0x7fff, (S); +ashift_test 0x4002, 2, 0x7fff, (S); +ashift_test 0x4002, 1, 0x7fff, (S); +ashift_test 0x4002, 0, 0x4002, (S); +ashift_test 0x4002, -1, 0x2001, (S); +ashift_test 0x4002, -2, 0x1000, (S); +ashift_test 0x4002, -3, 0x0800, (S); +ashift_test 0x4002, -4, 0x0400, (S); +ashift_test 0x4002, -5, 0x0200, (S); +ashift_test 0x4002, -6, 0x0100, (S); +ashift_test 0x4002, -7, 0x0080, (S); +ashift_test 0x4002, -8, 0x0040, (S); +ashift_test 0x4002, -9, 0x0020, (S); +ashift_test 0x4002, -10, 0x0010, (S); +ashift_test 0x4002, -11, 0x0008, (S); +ashift_test 0x4002, -12, 0x0004, (S); +ashift_test 0x4002, -13, 0x0002, (S); +ashift_test 0x4002, -14, 0x0001, (S); +ashift_test 0x4002, -15, 0x0000, (S); +ashift_test 0x4002, -16, 0x0000, (S); +ashift_test 0x4002, -17, 0x0000, (S); +ashift_test 0x4002, -31, 0x0000, (S); +ashift_test 0x4002, -32, 0x0000, (S); +ashift_test 0x4002, -33, 0x7fff, (S); +ashift_test 0x4002, -34, 0x7fff, (S); + +ashift_test 0x0001, 33, 0x0000, (S); +ashift_test 0x0001, 32, 0x0000, (S); +ashift_test 0x0001, 31, 0x7fff, (S); +ashift_test 0x0001, 30, 0x7fff, (S); +ashift_test 0x0001, 29, 0x7fff, (S); +ashift_test 0x0001, 28, 0x7fff, (S); +ashift_test 0x0001, 27, 0x7fff, (S); +ashift_test 0x0001, 26, 0x7fff, (S); +ashift_test 0x0001, 25, 0x7fff, (S); +ashift_test 0x0001, 24, 0x7fff, (S); +ashift_test 0x0001, 23, 0x7fff, (S); +ashift_test 0x0001, 22, 0x7fff, (S); +ashift_test 0x0001, 21, 0x7fff, (S); +ashift_test 0x0001, 20, 0x7fff, (S); +ashift_test 0x0001, 19, 0x7fff, (S); +ashift_test 0x0001, 18, 0x7fff, (S); +ashift_test 0x0001, 17, 0x7fff, (S); +ashift_test 0x0001, 16, 0x7fff, (S); +ashift_test 0x0001, 15, 0x7fff, (S); +ashift_test 0x0001, 14, 0x4000, (S); +ashift_test 0x0001, 13, 0x2000, (S); +ashift_test 0x0001, 12, 0x1000, (S); +ashift_test 0x0001, 11, 0x0800, (S); +ashift_test 0x0001, 10, 0x0400, (S); +ashift_test 0x0001, 9, 0x0200, (S); +ashift_test 0x0001, 8, 0x0100, (S); +ashift_test 0x0001, 7, 0x0080, (S); +ashift_test 0x0001, 6, 0x0040, (S); +ashift_test 0x0001, 5, 0x0020, (S); +ashift_test 0x0001, 4, 0x0010, (S); +ashift_test 0x0001, 3, 0x0008, (S); +ashift_test 0x0001, 2, 0x0004, (S); +ashift_test 0x0001, 1, 0x0002, (S); +ashift_test 0x0001, 0, 0x0001, (S); +ashift_test 0x0001, -1, 0x0000, (S); +ashift_test 0x0001, -2, 0x0000, (S); +ashift_test 0x0001, -3, 0x0000, (S); +ashift_test 0x0001, -4, 0x0000, (S); +ashift_test 0x0001, -5, 0x0000, (S); +ashift_test 0x0001, -6, 0x0000, (S); +ashift_test 0x0001, -7, 0x0000, (S); +ashift_test 0x0001, -8, 0x0000, (S); +ashift_test 0x0001, -9, 0x0000, (S); +ashift_test 0x0001, -10, 0x0000, (S); +ashift_test 0x0001, -11, 0x0000, (S); +ashift_test 0x0001, -12, 0x0000, (S); +ashift_test 0x0001, -13, 0x0000, (S); +ashift_test 0x0001, -14, 0x0, (S); +ashift_test 0x0001, -15, 0x0, (S); +ashift_test 0x0001, -16, 0x0, (S); +ashift_test 0x0001, -17, 0x0, (S); +ashift_test 0x0001, -18, 0x0, (S); +ashift_test 0x0001, -19, 0x0, (S); +ashift_test 0x0001, -20, 0x0, (S); +ashift_test 0x0001, -21, 0x0, (S); +ashift_test 0x0001, -22, 0x0, (S); +ashift_test 0x0001, -23, 0x0, (S); +ashift_test 0x0001, -24, 0x0, (S); +ashift_test 0x0001, -25, 0x0, (S); +ashift_test 0x0001, -26, 0x0, (S); +ashift_test 0x0001, -27, 0x0, (S); +ashift_test 0x0001, -28, 0x0, (S); +ashift_test 0x0001, -29, 0x0, (S); +ashift_test 0x0001, -30, 0x0, (S); +ashift_test 0x0001, -31, 0x0, (S); +ashift_test 0x0001, -32, 0x0, (S); +ashift_test 0x0001, -33, 0x7fff, (S); +ashift_test 0x0001, -34, 0x7fff, (S); + + pass diff --git a/sim/testsuite/sim/bfin/ashift_flags.s b/sim/testsuite/sim/bfin/ashift_flags.s new file mode 100644 index 0000000..87f00be --- /dev/null +++ b/sim/testsuite/sim/bfin/ashift_flags.s @@ -0,0 +1,84 @@ +# mach: bfin + +.include "testutils.inc" + start + +// load r1=0x7fffffff +// load r2=0x80000000 +// load r3=0x000000ff +// load r4=0x00000000 + loadsym p0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + + _dbg r0; + _dbg r1; + _dbg r2; + _dbg r3; + _dbg r4; + + R7 = 0; + ASTAT = R7; + r5 = r1 << 0x4 (s); + _DBG ASTAT; + r7=astat; + dbga (r5.h, 0x7fff); + dbga (r5.l, 0xffff); + dbga (r7.h, 0x0300); // V=1, VS=1 + dbga (r7.l, 0x8); + + R7 = 0; + ASTAT = R7; + r5.h = r1.h << 0x4 (s); + _DBG ASTAT; + r7=astat; + dbga (r5.h, 0x7fff); + dbga (r7.h, 0x0300); // V=1, VS=1 + dbga (r7.l, 0x8); + + A0 = 0; + A0.w = r1; + A0.x = r0.l; + r6 = 0x3; + _dbg r6; + _dbg A0; + R7 = 0; + ASTAT = R7; + A0 = ASHIFT A0 BY R6.L; + _DBG ASTAT; + _DBG A0; + r7 = astat; + dbga (r7.h, 0x0); // AV0=0, AV0S=0 + dbga (r7.l, 0x2); // AN = 1 + + A1 = 0; + A1 = r1; + A1.x = r0.l; + r6 = 0x3; + _dbg A1; + R7 = 0; + ASTAT = R7; + A1 = ASHIFT A1 BY R6.L; + _DBG ASTAT; + _DBG A1; + r7 = astat; + dbga (r7.h, 0x0); // AV1=0, AV1S=0 + dbga (r7.l, 0x2); // AN = 1 + + pass + + .data 0x1000; +data0: + .dw 0x1111 + .dw 0x1111 + .dw 0xffff + .dw 0x7fff + .dw 0x0000 + .dw 0x8000 + .dw 0x00ff + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/b0.S b/sim/testsuite/sim/bfin/b0.S new file mode 100644 index 0000000..5a02092 --- /dev/null +++ b/sim/testsuite/sim/bfin/b0.S @@ -0,0 +1,51 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + CC = R0 == R0; + + AZ = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AC0|_AC0_COPY|_CC|_AZ); + R0 = R0 + R0; + R0 = ASTAT; CHECKREG R0, (_CC); + + AN = CC; + R0 = ASTAT; CHECKREG R0, (_CC|_AN); + R0 = - R0; + R0 = ASTAT; CHECKREG R0, (_CC|_AN); + + AC0 = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AC0|_CC|_AN); + + AV0 = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_CC|_AN); + + AV1 = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_CC|_AN); + + AQ = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AQ|_CC|_AN); + + CC = R0 < R0; + _DBG ASTAT; + +// When AV0 is set, AV1 is unchanged + AQ = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AC0_COPY|_AZ); + + AV1 = CC; + _DBG ASTAT; + R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_AC0_COPY|_AZ); + + pass diff --git a/sim/testsuite/sim/bfin/b1.s b/sim/testsuite/sim/bfin/b1.s new file mode 100644 index 0000000..c9eaeca --- /dev/null +++ b/sim/testsuite/sim/bfin/b1.s @@ -0,0 +1,12 @@ +# mach: bfin +.include "testutils.inc" + start + + R0 = 0; + CC = R0 == R0; + + IF CC JUMP 4; + JUMP.S LL1; + pass +LL1: + fail diff --git a/sim/testsuite/sim/bfin/b2.S b/sim/testsuite/sim/bfin/b2.S new file mode 100644 index 0000000..731f874 --- /dev/null +++ b/sim/testsuite/sim/bfin/b2.S @@ -0,0 +1,26 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + CC = BITTST ( R0 , 0x0 ); + BITSET( R0 , 0x0 ); + CC = BITTST ( R0 , 0x0 ); + CC = ! BITTST( R0 , 0x0 ); + R1.L = 1; + R1.H = 0; + CC = R0 == R1; + CC = BITTST ( R0 , 0x1 ); + R5 = ASTAT; + CHECKREG R5, (_AC0|_AC0_COPY|_AZ) + + BITSET( R0 , 0x1 ); + R5 = ASTAT; + CHECKREG R5, 0 + CC = BITTST ( R0 , 0x1 ); + CC = ! BITTST( R0 , 0x1 ); + pass diff --git a/sim/testsuite/sim/bfin/brcc.s b/sim/testsuite/sim/bfin/brcc.s new file mode 100644 index 0000000..479bf50 --- /dev/null +++ b/sim/testsuite/sim/bfin/brcc.s @@ -0,0 +1,164 @@ +# mach: bfin + +.include "testutils.inc" + start + + + /* Stall tests */ + + r0 = 0; + r1 = 1; + loadsym p0, foo; + p1 = p0; + +pass_1: + cc = r0; + nop; + nop; + + if cc jump _fail_1; + [p0++] = p0; + [p0++] = p0; + r7 = p0; + r5 = CC; + P1 += 8; + r6 = p1; + CC = R6 == R7; + if !CC jump _failure; + + cc = R5; + if !cc jump over; + +_fail_1: + [p0++] = p0; + [p0++] = p0; + +back: + if !cc jump skip(bp); + +_fail_2: + [p0++] = p0; + [p0++] = p0; + +over: + if cc jump _fail_3(bp); + [p0++] = p0; + [p0++] = p0; + r7=p0; + R5=cc; + P1 += 8; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + + CC = R5; + if !cc jump back(bp); + +_fail_3: + [p0++] = p0; + [p0++] = p0; + +skip: + [p0++] = p0; + [p0++] = p0; + [p0++] = p0; + r7=p0; + + P1 += 0xc; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + +next: + [p0++] = p0; + r7=p0; + P1 += 4; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + +pass_2: + cc = r1; + nop; + nop; + + if !cc jump _fail_4; + [p0++] = p0; + [p0++] = p0; + r7=p0; + R5 = cc; + P1 += 8; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + + cc = R5; + if cc jump over_2; + +_fail_4: + [p0++] = p0; + [p0++] = p0; + P1 += 8; + +back_2: + if cc jump skip_2 (bp); + +_fail_5: + [p0++] = p0; + [p0++] = p0; + P1 += 8; + +over_2: + if !cc jump _fail_6 (bp); + [p0++] = p0; + [p0++] = p0; + r7=p0; + R5 = cc; + P1 += 8; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + cc = R5; + + if cc jump back_2 (bp); + +_fail_6: + [p0++] = p0; + [p0++] = p0; + +skip_2: + [p0++] = p0; + [p0++] = p0; + [p0++] = p0; + r7=p0; + R5 = cc; + P1 += 0xc; + R6 = P1; + CC = R6 == R7; + if !CC jump _failure; + cc = r5; + + if cc jump next_2 (bp); + +next_2: + [p0++] = p0; + [p0++] = p0; + P1 += 8; + r7=p0; + r6 = P1; + CC = R6 == R7; + if !CC jump _failure; + + cc = r0; +_halt: + pass; + +_fail_7: + [p0++] = p0; + +_failure: + fail; + + .data +foo: + .space (0x100) diff --git a/sim/testsuite/sim/bfin/brevadd.s b/sim/testsuite/sim/bfin/brevadd.s new file mode 100644 index 0000000..56e1122 --- /dev/null +++ b/sim/testsuite/sim/bfin/brevadd.s @@ -0,0 +1,20 @@ +# Blackfin testcase for signbits +# mach: bfin + + .include "testutils.inc" + + start + + L2 = 0; + M2 = -4 (X); + I2.H = 0x9000; + I2.L = 0; + I2 += M2 (BREV); + R2 = I2; + imm32 r0, 0x10000002 + CC = R2 == R0 + if CC jump 1f; + + fail +1: + pass diff --git a/sim/testsuite/sim/bfin/byteop16m.s b/sim/testsuite/sim/bfin/byteop16m.s new file mode 100644 index 0000000..bd7478f --- /dev/null +++ b/sim/testsuite/sim/bfin/byteop16m.s @@ -0,0 +1,76 @@ +# Blackfin testcase for BYTEOP16M +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_it resL:req, resH:req + imm32 R6, \resL + CC = R4 == R6; + IF !CC JUMP 1f; +#DBG R4 + imm32 R7, \resH + CC = R5 == R7; + IF !CC JUMP 1f; +#DBG R5 + .endm + .macro test_byteop16m i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req + dmm32 I0, \i0 + dmm32 I1, \i1 + + (R4, R5) = BYTEOP16M (R1:0, R3:2); + check_it \resL, \resH + (R4, R5) = BYTEOP16M (R1:0, R3:2) (R); + check_it \resLR, \resHR + + jump 2f; +1: fail +2: + .endm + + imm32 R0, 0x01020304 + imm32 R1, 0x10203040 + imm32 R2, 0x0a0b0c0d + imm32 R3, 0xa0b0c0d0 + + test_byteop16m 0, 0, 0xfff7fff7, 0xfff7fff7, 0xff70ff70, 0xff70ff70 + test_byteop16m 0, 1, 0xff31fff8, 0xfff8fff8, 0x0003ff80, 0xff80ff80 + test_byteop16m 0, 2, 0xff41ff32, 0xfff9fff9, 0x00040013, 0xff90ff90 + test_byteop16m 0, 3, 0xff51ff42, 0xff33fffa, 0x00050014, 0x0023ffa0 + test_byteop16m 1, 0, 0x0036fff6, 0xfff6fff6, 0xff64ff60, 0xff60ff60 + test_byteop16m 1, 1, 0xff70fff7, 0xfff7fff7, 0xfff7ff70, 0xff70ff70 + test_byteop16m 1, 2, 0xff80ff31, 0xfff8fff8, 0xfff80003, 0xff80ff80 + test_byteop16m 1, 3, 0xff90ff41, 0xff32fff9, 0xfff90004, 0x0013ff90 + test_byteop16m 2, 0, 0x00260035, 0xfff5fff5, 0xff63ff54, 0xff50ff50 + test_byteop16m 2, 1, 0xff600036, 0xfff6fff6, 0xfff6ff64, 0xff60ff60 + test_byteop16m 2, 2, 0xff70ff70, 0xfff7fff7, 0xfff7fff7, 0xff70ff70 + test_byteop16m 2, 3, 0xff80ff80, 0xff31fff8, 0xfff8fff8, 0x0003ff80 + test_byteop16m 3, 0, 0x00160025, 0x0034fff4, 0xff62ff53, 0xff44ff40 + test_byteop16m 3, 1, 0xff500026, 0x0035fff5, 0xfff5ff63, 0xff54ff50 + test_byteop16m 3, 2, 0xff60ff60, 0x0036fff6, 0xfff6fff6, 0xff64ff60 + test_byteop16m 3, 3, 0xff70ff70, 0xff70fff7, 0xfff7fff7, 0xfff7ff70 + + imm32 R0, ~0x01020304 + imm32 R1, ~0x10203040 + imm32 R2, ~0x0a0b0c0d + imm32 R3, ~0xa0b0c0d0 + + test_byteop16m 0, 0, 0x00090009, 0x00090009, 0x00900090, 0x00900090 + test_byteop16m 0, 1, 0x00cf0008, 0x00080008, 0xfffd0080, 0x00800080 + test_byteop16m 0, 2, 0x00bf00ce, 0x00070007, 0xfffcffed, 0x00700070 + test_byteop16m 0, 3, 0x00af00be, 0x00cd0006, 0xfffbffec, 0xffdd0060 + test_byteop16m 1, 0, 0xffca000a, 0x000a000a, 0x009c00a0, 0x00a000a0 + test_byteop16m 1, 1, 0x00900009, 0x00090009, 0x00090090, 0x00900090 + test_byteop16m 1, 2, 0x008000cf, 0x00080008, 0x0008fffd, 0x00800080 + test_byteop16m 1, 3, 0x007000bf, 0x00ce0007, 0x0007fffc, 0xffed0070 + test_byteop16m 2, 0, 0xffdaffcb, 0x000b000b, 0x009d00ac, 0x00b000b0 + test_byteop16m 2, 1, 0x00a0ffca, 0x000a000a, 0x000a009c, 0x00a000a0 + test_byteop16m 2, 2, 0x00900090, 0x00090009, 0x00090009, 0x00900090 + test_byteop16m 2, 3, 0x00800080, 0x00cf0008, 0x00080008, 0xfffd0080 + test_byteop16m 3, 0, 0xffeaffdb, 0xffcc000c, 0x009e00ad, 0x00bc00c0 + test_byteop16m 3, 1, 0x00b0ffda, 0xffcb000b, 0x000b009d, 0x00ac00b0 + test_byteop16m 3, 2, 0x00a000a0, 0xffca000a, 0x000a000a, 0x009c00a0 + test_byteop16m 3, 3, 0x00900090, 0x00900009, 0x00090009, 0x00090090 + + pass diff --git a/sim/testsuite/sim/bfin/byteop16p.s b/sim/testsuite/sim/bfin/byteop16p.s new file mode 100644 index 0000000..fdc5d66 --- /dev/null +++ b/sim/testsuite/sim/bfin/byteop16p.s @@ -0,0 +1,74 @@ +# Blackfin testcase for BYTEOP16P +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_it resL:req, resH:req + imm32 R6, \resL + CC = R4 == R6; + IF !CC JUMP 1f; + imm32 R7, \resH + CC = R5 == R7; + IF !CC JUMP 1f; + .endm + .macro test_byteop16p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req + dmm32 I0, \i0 + dmm32 I1, \i1 + + (R4, R5) = BYTEOP16P (R1:0, R3:2); + check_it \resL, \resH + (R4, R5) = BYTEOP16P (R1:0, R3:2) (R); + check_it \resLR, \resHR + + jump 2f; +1: fail +2: + .endm + + imm32 R0, 0x01020304 + imm32 R1, 0x10203040 + imm32 R2, 0x0a0b0c0d + imm32 R3, 0xa0b0c0d0 + + test_byteop16p 0, 0, 0x000b000d, 0x000f0011, 0x00b000d0, 0x00f00110 + test_byteop16p 0, 1, 0x00d1000c, 0x000e0010, 0x001d00c0, 0x00e00100 + test_byteop16p 0, 2, 0x00c100d2, 0x000d000f, 0x001c002d, 0x00d000f0 + test_byteop16p 0, 3, 0x00b100c2, 0x00d3000e, 0x001b002c, 0x003d00e0 + test_byteop16p 1, 0, 0x004a000c, 0x000e0010, 0x00a400c0, 0x00e00100 + test_byteop16p 1, 1, 0x0110000b, 0x000d000f, 0x001100b0, 0x00d000f0 + test_byteop16p 1, 2, 0x010000d1, 0x000c000e, 0x0010001d, 0x00c000e0 + test_byteop16p 1, 3, 0x00f000c1, 0x00d2000d, 0x000f001c, 0x002d00d0 + test_byteop16p 2, 0, 0x003a004b, 0x000d000f, 0x00a300b4, 0x00d000f0 + test_byteop16p 2, 1, 0x0100004a, 0x000c000e, 0x001000a4, 0x00c000e0 + test_byteop16p 2, 2, 0x00f00110, 0x000b000d, 0x000f0011, 0x00b000d0 + test_byteop16p 2, 3, 0x00e00100, 0x00d1000c, 0x000e0010, 0x001d00c0 + test_byteop16p 3, 0, 0x002a003b, 0x004c000e, 0x00a200b3, 0x00c400e0 + test_byteop16p 3, 1, 0x00f0003a, 0x004b000d, 0x000f00a3, 0x00b400d0 + test_byteop16p 3, 2, 0x00e00100, 0x004a000c, 0x000e0010, 0x00a400c0 + test_byteop16p 3, 3, 0x00d000f0, 0x0110000b, 0x000d000f, 0x001100b0 + + imm32 R0, ~0x01020304 + imm32 R1, ~0x10203040 + imm32 R2, ~0x0a0b0c0d + imm32 R3, ~0xa0b0c0d0 + + test_byteop16p 0, 0, 0x01f301f1, 0x01ef01ed, 0x014e012e, 0x010e00ee + test_byteop16p 0, 1, 0x012d01f2, 0x01f001ee, 0x01e1013e, 0x011e00fe + test_byteop16p 0, 2, 0x013d012c, 0x01f101ef, 0x01e201d1, 0x012e010e + test_byteop16p 0, 3, 0x014d013c, 0x012b01f0, 0x01e301d2, 0x01c1011e + test_byteop16p 1, 0, 0x01b401f2, 0x01f001ee, 0x015a013e, 0x011e00fe + test_byteop16p 1, 1, 0x00ee01f3, 0x01f101ef, 0x01ed014e, 0x012e010e + test_byteop16p 1, 2, 0x00fe012d, 0x01f201f0, 0x01ee01e1, 0x013e011e + test_byteop16p 1, 3, 0x010e013d, 0x012c01f1, 0x01ef01e2, 0x01d1012e + test_byteop16p 2, 0, 0x01c401b3, 0x01f101ef, 0x015b014a, 0x012e010e + test_byteop16p 2, 1, 0x00fe01b4, 0x01f201f0, 0x01ee015a, 0x013e011e + test_byteop16p 2, 2, 0x010e00ee, 0x01f301f1, 0x01ef01ed, 0x014e012e + test_byteop16p 2, 3, 0x011e00fe, 0x012d01f2, 0x01f001ee, 0x01e1013e + test_byteop16p 3, 0, 0x01d401c3, 0x01b201f0, 0x015c014b, 0x013a011e + test_byteop16p 3, 1, 0x010e01c4, 0x01b301f1, 0x01ef015b, 0x014a012e + test_byteop16p 3, 2, 0x011e00fe, 0x01b401f2, 0x01f001ee, 0x015a013e + test_byteop16p 3, 3, 0x012e010e, 0x00ee01f3, 0x01f101ef, 0x01ed014e + + pass diff --git a/sim/testsuite/sim/bfin/byteop1p.s b/sim/testsuite/sim/bfin/byteop1p.s new file mode 100644 index 0000000..e90d790 --- /dev/null +++ b/sim/testsuite/sim/bfin/byteop1p.s @@ -0,0 +1,75 @@ +# Blackfin testcase for BYTEOP1P +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_it res:req + imm32 R7, \res + CC = R6 == R7; + IF !CC JUMP 1f; + .endm + .macro test_byteop1p i0:req, i1:req, res:req, resT:req, resR:req, resTR:req + dmm32 I0, \i0 + dmm32 I1, \i1 + + R6 = BYTEOP1P (R1:0, R3:2); + check_it \res + R6 = BYTEOP1P (R1:0, R3:2) (T); + check_it \resT + R6 = BYTEOP1P (R1:0, R3:2) (R); + check_it \resR + R6 = BYTEOP1P (R1:0, R3:2) (T, R); + check_it \resTR + + jump 2f; +1: fail +2: + .endm + + imm32 R0, 0x01020304 + imm32 R1, 0x10203040 + imm32 R2, 0x0a0b0c0d + imm32 R3, 0xa0b0c0d0 + + test_byteop1p 0, 0, 0x06070809, 0x05060708, 0x58687888, 0x58687888 + test_byteop1p 0, 1, 0x69060708, 0x68060708, 0x0f607080, 0x0e607080 + test_byteop1p 0, 2, 0x61690708, 0x60690607, 0x0e176878, 0x0e166878 + test_byteop1p 0, 3, 0x59616a07, 0x58616907, 0x0e161f70, 0x0d161e70 + test_byteop1p 1, 0, 0x25060708, 0x25060708, 0x52607080, 0x52607080 + test_byteop1p 1, 1, 0x88060708, 0x88050607, 0x09586878, 0x08586878 + test_byteop1p 1, 2, 0x80690607, 0x80680607, 0x080f6070, 0x080e6070 + test_byteop1p 1, 3, 0x78616907, 0x78606906, 0x080e1768, 0x070e1668 + test_byteop1p 2, 0, 0x1d260708, 0x1d250607, 0x525a6878, 0x515a6878 + test_byteop1p 2, 1, 0x80250607, 0x80250607, 0x08526070, 0x08526070 + test_byteop1p 2, 2, 0x78880607, 0x78880506, 0x08095868, 0x07085868 + test_byteop1p 2, 3, 0x70806906, 0x70806806, 0x07080f60, 0x07080e60 + test_byteop1p 3, 0, 0x151e2607, 0x151d2607, 0x515a6270, 0x51596270 + test_byteop1p 3, 1, 0x781d2607, 0x781d2506, 0x08525a68, 0x07515a68 + test_byteop1p 3, 2, 0x70802506, 0x70802506, 0x07085260, 0x07085260 + test_byteop1p 3, 3, 0x68788806, 0x68788805, 0x07080958, 0x06070858 + + imm32 R0, ~0x01020304 + imm32 R1, ~0x10203040 + imm32 R2, ~0x0a0b0c0d + imm32 R3, ~0xa0b0c0d0 + + test_byteop1p 0, 0, 0xfaf9f8f7, 0xf9f8f7f6, 0xa7978777, 0xa7978777 + test_byteop1p 0, 1, 0x97f9f8f7, 0x96f9f8f7, 0xf19f8f7f, 0xf09f8f7f + test_byteop1p 0, 2, 0x9f96f9f8, 0x9e96f8f7, 0xf1e99787, 0xf1e89787 + test_byteop1p 0, 3, 0xa79e96f8, 0xa69e95f8, 0xf2e9e18f, 0xf1e9e08f + test_byteop1p 1, 0, 0xdaf9f8f7, 0xdaf9f8f7, 0xad9f8f7f, 0xad9f8f7f + test_byteop1p 1, 1, 0x77faf9f8, 0x77f9f8f7, 0xf7a79787, 0xf6a79787 + test_byteop1p 1, 2, 0x7f97f9f8, 0x7f96f9f8, 0xf7f19f8f, 0xf7f09f8f + test_byteop1p 1, 3, 0x879f96f9, 0x879e96f8, 0xf8f1e997, 0xf7f1e897 + test_byteop1p 2, 0, 0xe2daf9f8, 0xe2d9f8f7, 0xaea59787, 0xada59787 + test_byteop1p 2, 1, 0x7fdaf9f8, 0x7fdaf9f8, 0xf7ad9f8f, 0xf7ad9f8f + test_byteop1p 2, 2, 0x8777faf9, 0x8777f9f8, 0xf8f7a797, 0xf7f6a797 + test_byteop1p 2, 3, 0x8f7f97f9, 0x8f7f96f9, 0xf8f7f19f, 0xf8f7f09f + test_byteop1p 3, 0, 0xeae2d9f8, 0xeae1d9f8, 0xaea69d8f, 0xaea59d8f + test_byteop1p 3, 1, 0x87e2daf9, 0x87e2d9f8, 0xf8aea597, 0xf7ada597 + test_byteop1p 3, 2, 0x8f7fdaf9, 0x8f7fdaf9, 0xf8f7ad9f, 0xf8f7ad9f + test_byteop1p 3, 3, 0x978777fa, 0x978777f9, 0xf9f8f7a7, 0xf8f7f6a7 + + pass diff --git a/sim/testsuite/sim/bfin/byteop2p.s b/sim/testsuite/sim/bfin/byteop2p.s new file mode 100644 index 0000000..e11109a --- /dev/null +++ b/sim/testsuite/sim/bfin/byteop2p.s @@ -0,0 +1,58 @@ +# Blackfin testcase for BYTEOP2P +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_it res:req + imm32 R7, \res + CC = R6 == R7; + IF !CC JUMP 1f; + .endm + .macro test_byteop2p i0:req, resRL:req, resRH:req, resTL:req, resTH:req, resRLr:req, resRHr:req, resTLr:req, resTHr:req + dmm32 I0, \i0 + + R6 = BYTEOP2P (R1:0, R3:2) (rndl); + check_it \resRL + R6 = BYTEOP2P (R1:0, R3:2) (rndh); + check_it \resRH + R6 = BYTEOP2P (R1:0, R3:2) (tl); + check_it \resTL + R6 = BYTEOP2P (R1:0, R3:2) (th); + check_it \resTH + R6 = BYTEOP2P (R1:0, R3:2) (rndl, r); + check_it \resRLr + R6 = BYTEOP2P (R1:0, R3:2) (rndh, r); + check_it \resRHr + R6 = BYTEOP2P (R1:0, R3:2) (tl, r); + check_it \resTLr + R6 = BYTEOP2P (R1:0, R3:2) (th, r); + check_it \resTHr + + jump 2f; +1: fail +2: + .endm + + imm32 R0, 0x01020304 + imm32 R1, 0x10203040 + imm32 R2, 0x0a0b0c0d + imm32 R3, 0xa0b0c0d0 + + test_byteop2p 0, 0x00060008, 0x06000800, 0x00060008, 0x06000800, 0x00600080, 0x60008000, 0x00600080, 0x60008000 + test_byteop2p 1, 0x00470007, 0x47000700, 0x00460007, 0x46000700, 0x00300070, 0x30007000, 0x00300070, 0x30007000 + test_byteop2p 2, 0x00800006, 0x80000600, 0x00800006, 0x80000600, 0x00080060, 0x08006000, 0x00080060, 0x08006000 + test_byteop2p 3, 0x00700047, 0x70004700, 0x00700046, 0x70004600, 0x00070030, 0x07003000, 0x00070030, 0x07003000 + + imm32 R0, ~0x01020304 + imm32 R1, ~0x10203040 + imm32 R2, ~0x0a0b0c0d + imm32 R3, ~0xa0b0c0d0 + + test_byteop2p 0, 0x00f900f7, 0xf900f700, 0x00f900f7, 0xf900f700, 0x009f007f, 0x9f007f00, 0x009f007f, 0x9f007f00 + test_byteop2p 1, 0x00b800f8, 0xb800f800, 0x00b800f8, 0xb800f800, 0x00cf008f, 0xcf008f00, 0x00ce008f, 0xce008f00 + test_byteop2p 2, 0x007f00f9, 0x7f00f900, 0x007f00f9, 0x7f00f900, 0x00f7009f, 0xf7009f00, 0x00f7009f, 0xf7009f00 + test_byteop2p 3, 0x008f00b8, 0x8f00b800, 0x008f00b8, 0x8f00b800, 0x00f800cf, 0xf800cf00, 0x00f800ce, 0xf800ce00 + + pass diff --git a/sim/testsuite/sim/bfin/byteop3p.s b/sim/testsuite/sim/bfin/byteop3p.s new file mode 100644 index 0000000..a5390f8 --- /dev/null +++ b/sim/testsuite/sim/bfin/byteop3p.s @@ -0,0 +1,119 @@ +# Blackfin testcase for BYTEOP3P +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_it res:req + imm32 R7, \res + CC = R6 == R7; + IF !CC JUMP 1f; + .endm + .macro test_byteop3p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req + dmm32 I0, \i0 + dmm32 I1, \i1 + + R6 = BYTEOP3P (R1:0, R3:2) (LO); + check_it \resL + R6 = BYTEOP3P (R1:0, R3:2) (HI); + check_it \resH + R6 = BYTEOP3P (R1:0, R3:2) (LO, R); + check_it \resLR + R6 = BYTEOP3P (R1:0, R3:2) (HI, R); + check_it \resHR + + jump 2f; +1: fail +2: + .endm + + imm32 R0, 0x01020304 + imm32 R1, 0x10203040 + imm32 R2, 0x0a0b0c0d + imm32 R3, 0xa0b0c0d0 + + test_byteop3p 0, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 0, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 0, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 0, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + + imm32 R0, ~0x01020304 + imm32 R1, ~0x10203040 + imm32 R2, ~0x0a0b0c0d + imm32 R3, ~0xa0b0c0d0 + + test_byteop3p 0, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 0, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 0, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 0, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 1, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 1, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 1, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 1, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 2, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 2, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 2, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 2, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 3, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 3, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 3, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + test_byteop3p 3, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + + imm32 R0, 0x00010002 + imm32 R1, 0x00030004 + imm32 R2, 0x10203040 + imm32 R3, 0x50607080 + + test_byteop3p 0, 0, 0x00110032, 0x21004200, 0x00530074, 0x63008400 + test_byteop3p 0, 1, 0x00810022, 0x11003200, 0x00430064, 0x53007400 + test_byteop3p 0, 2, 0x00710012, 0x81002200, 0x00330054, 0x43006400 + test_byteop3p 0, 3, 0x00610082, 0x71001200, 0x00230044, 0x33005400 + test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 0, 0x00140031, 0x24004100, 0x00520073, 0x62008300 + test_byteop3p 2, 1, 0x00840021, 0x14003100, 0x00420063, 0x52007300 + test_byteop3p 2, 2, 0x00740011, 0x84002100, 0x00320053, 0x42006300 + test_byteop3p 2, 3, 0x00640081, 0x74001100, 0x00220043, 0x32005300 + test_byteop3p 3, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00 + + imm32 R0, 0x00100200 + imm32 R1, 0x30000040 + imm32 R2, 0x1a2b3c4d + imm32 R3, 0x5e6f7a8b + + test_byteop3p 0, 0, 0x002a00ff, 0x3b00ff00, 0x00ff00ba, 0xff00cb00 + test_byteop3p 0, 1, 0x009b00ff, 0x2a00ff00, 0x00ff00af, 0xff00ba00 + test_byteop3p 0, 2, 0x008a00ff, 0x9b00ff00, 0x00ff009e, 0xff00af00 + test_byteop3p 0, 3, 0x007f00ff, 0x8a00ff00, 0x00ff008d, 0xff009e00 + test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x008e007a, 0x9f008b00 + test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x007d006f, 0x8e007a00 + test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x006c005e, 0x7d006f00 + test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x005b004d, 0x6c005e00 + test_byteop3p 2, 0, 0x005a004c, 0x6b005d00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 1, 0x00cb003b, 0x5a004c00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 2, 0x00ba002a, 0xcb003b00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 2, 3, 0x00af009b, 0xba002a00, 0x00ff00ff, 0xff00ff00 + test_byteop3p 3, 0, 0x001a00ff, 0x2b00ff00, 0x00ff00aa, 0xff00bb00 + test_byteop3p 3, 1, 0x008b00ff, 0x1a00ff00, 0x00ff009f, 0xff00aa00 + test_byteop3p 3, 2, 0x007a00ff, 0x8b00ff00, 0x00ff008e, 0xff009f00 + test_byteop3p 3, 3, 0x006f00ff, 0x7a00ff00, 0x00ff007d, 0xff008e00 + + pass diff --git a/sim/testsuite/sim/bfin/byteunpack.s b/sim/testsuite/sim/bfin/byteunpack.s new file mode 100644 index 0000000..883c071 --- /dev/null +++ b/sim/testsuite/sim/bfin/byteunpack.s @@ -0,0 +1,45 @@ +# Blackfin testcase for playing with BYTEUNPACK +# mach: bfin + + .include "testutils.inc" + + start + + .macro _bu_pre_test i0:req, src0:req, src1:req + dmm32 I0, \i0 + imm32 R0, \src0 + imm32 R1, \src1 + .endm + .macro _bu_chk_test dst0:req, dst1:req + imm32 R2, \dst0 + imm32 R3, \dst1 + CC = R5 == R2; + IF !CC jump 1f; + CC = R6 == R3; + IF !CC jump 1f; + .endm + .macro bu_test i0:req, dst0:req, dst1:req, src0:req, src1:req + _bu_pre_test \i0, \src0, \src1 + (R6, R5) = BYTEUNPACK R1:0; + _bu_chk_test \dst0, \dst1 + .endm + .macro bu_r_test i0:req, dst0:req, dst1:req, src0:req, src1:req + _bu_pre_test \i0, \src0, \src1 + (R6, R5) = BYTEUNPACK R1:0 (R); + _bu_chk_test \dst0, \dst1 + .endm + + # Taken from PRM + bu_test 0, 0x00BA00DD, 0x00BE00EF, 0xBEEFBADD, 0xFEEDFACE + bu_test 1, 0x00EF00BA, 0x00CE00BE, 0xBEEFBADD, 0xFEEDFACE + bu_test 2, 0x00BE00EF, 0x00FA00CE, 0xBEEFBADD, 0xFEEDFACE + bu_test 3, 0x00CE00BE, 0x00ED00FA, 0xBEEFBADD, 0xFEEDFACE + + # Taken from PRM + bu_r_test 0, 0x00FA00CE, 0x00FE00ED, 0xBEEFBADD, 0xFEEDFACE + bu_r_test 1, 0x00ED00FA, 0x00DD00FE, 0xBEEFBADD, 0xFEEDFACE + bu_r_test 2, 0x00FE00ED, 0x00BA00DD, 0xBEEFBADD, 0xFEEDFACE + bu_r_test 3, 0x00DD00FE, 0x00EF00BA, 0xBEEFBADD, 0xFEEDFACE + + pass +1: fail diff --git a/sim/testsuite/sim/bfin/c_alu2op_arith_r_sft.s b/sim/testsuite/sim/bfin/c_alu2op_arith_r_sft.s new file mode 100644 index 0000000..7ce9d4e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_arith_r_sft.s @@ -0,0 +1,226 @@ +//Original:/testcases/core/c_alu2op_arith_r_sft/c_alu2op_arith_r_sft.dsp +// Spec Reference: alu2op arith right +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R1.L = 1; +R1 >>>= R0; +R2 >>>= R0; +R3 >>>= R0; +R4 >>>= R0; +R5 >>>= R0; +R6 >>>= R0; +R7 >>>= R0; +R4 >>>= R0; +R0 >>>= R0; +CHECKREG r1, 0x12340001; +CHECKREG r2, 0x23456789; +CHECKREG r3, 0x3456789A; +CHECKREG r4, 0x856789AB; +CHECKREG r5, 0x96789ABC; +CHECKREG r6, 0xA789ABCD; +CHECKREG r7, 0xB89ABCDE; +CHECKREG r0, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R1.L = -1; +R0 >>>= R1; +R2 >>>= R1; +R3 >>>= R1; +R4 >>>= R1; +R5 >>>= R1; +R6 >>>= R1; +R7 >>>= R1; +R1 >>>= R1; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x00000000; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 31; +R0 >>>= R2; +R1 >>>= R2; +R3 >>>= R2; +R4 >>>= R2; +R5 >>>= R2; +R6 >>>= R2; +R7 >>>= R2; +R2 >>>= R2; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0x00000000; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R3.L = -31; +R0 >>>= R3; +R1 >>>= R3; +R2 >>>= R3; +R4 >>>= R3; +R5 >>>= R3; +R6 >>>= R3; +R7 >>>= R3; +R3 >>>= R3; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x00000001; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x00000000; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R4.L = 15; +R1 >>>= R4; +R2 >>>= R4; +R3 >>>= R4; +R0 >>>= R4; +R5 >>>= R4; +R6 >>>= R4; +R7 >>>= R4; +R4 >>>= R4; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00002468; +CHECKREG r2, 0x0000468A; +CHECKREG r3, 0x000068AC; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0xFFFF2CF1; +CHECKREG r6, 0xFFFF4F13; +CHECKREG r7, 0xFFFF7135; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0x00000000; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R5.L = -15; +R0 >>>= R5; +R1 >>>= R5; +R2 >>>= R5; +R3 >>>= R5; +R4 >>>= R5; +R6 >>>= R5; +R7 >>>= R5; +R5 >>>= R5; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0xb1256790; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x00000000; +imm32 r7, 0x789abcde; +R6.L = 24; +R0 >>>= R6; +R1 >>>= R6; +R2 >>>= R6; +R3 >>>= R6; +R4 >>>= R6; +R5 >>>= R6; +R7 >>>= R6; +R6 >>>= R6; +CHECKREG r0, 0x00000051; +CHECKREG r1, 0x00000012; +CHECKREG r2, 0xFFFFFFB1; +CHECKREG r3, 0x00000034; +CHECKREG r4, 0xFFFFFF95; +CHECKREG r5, 0xFFFFFF86; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000078; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0x00000000; +R7.L = -24; +R0 >>>= R7; +R1 >>>= R7; +R2 >>>= R7; +R3 >>>= R7; +R4 >>>= R7; +R5 >>>= R7; +R6 >>>= R7; +R7 >>>= R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0x00000000; + +// special case +R2.L = -1; +R2.H = 32767; +R0 = 0; +R2 >>>= R0; +CHECKREG r2, 0x7FFFFFFF; + +pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_b.s b/sim/testsuite/sim/bfin/c_alu2op_conv_b.s new file mode 100644 index 0000000..0de3b52 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_conv_b.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_b/c_alu2op_conv_b.dsp +// Spec Reference: alu2op convert b +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.B (Z); +R1 = R0.B (Z); +R2 = R0.B (Z); +R3 = R0.B (Z); +R4 = R0.B (Z); +R5 = R0.B (Z); +R6 = R0.B (Z); +R7 = R0.B (Z); +CHECKREG r0, 0x000000BC; +CHECKREG r1, 0x000000BC; +CHECKREG r2, 0x000000BC; +CHECKREG r3, 0x000000BC; +CHECKREG r4, 0x000000BC; +CHECKREG r5, 0x000000BC; +CHECKREG r6, 0x000000BC; +CHECKREG r7, 0x000000BC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.B (Z); +R2 = R1.B (Z); +R3 = R1.B (Z); +R4 = R1.B (Z); +R5 = R1.B (Z); +R6 = R1.B (Z); +R7 = R1.B (Z); +R1 = R1.B (Z); +CHECKREG r0, 0x00000059; +CHECKREG r1, 0x00000059; +CHECKREG r2, 0x00000059; +CHECKREG r3, 0x00000059; +CHECKREG r4, 0x00000059; +CHECKREG r5, 0x00000059; +CHECKREG r6, 0x00000059; +CHECKREG r7, 0x00000059; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.B (Z); +R1 = R2.B (Z); +R3 = R2.B (Z); +R4 = R2.B (Z); +R5 = R2.B (Z); +R6 = R2.B (Z); +R7 = R2.B (Z); +R2 = R2.B (Z); +CHECKREG r0, 0x00000089; +CHECKREG r1, 0x00000089; +CHECKREG r2, 0x00000089; +CHECKREG r3, 0x00000089; +CHECKREG r4, 0x00000089; +CHECKREG r5, 0x00000089; +CHECKREG r6, 0x00000089; +CHECKREG r7, 0x00000089; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.B (Z); +R1 = R3.B (Z); +R2 = R3.B (Z); +R4 = R3.B (Z); +R5 = R3.B (Z); +R6 = R3.B (Z); +R7 = R3.B (Z); +R3 = R3.B (Z); +CHECKREG r0, 0x0000009A; +CHECKREG r1, 0x0000009A; +CHECKREG r2, 0x0000009A; +CHECKREG r3, 0x0000009A; +CHECKREG r4, 0x0000009A; +CHECKREG r5, 0x0000009A; +CHECKREG r6, 0x0000009A; +CHECKREG r7, 0x0000009A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.B (Z); +R1 = R4.B (Z); +R2 = R4.B (Z); +R3 = R4.B (Z); +R4 = R4.B (Z); +R5 = R4.B (Z); +R6 = R4.B (Z); +R7 = R4.B (Z); +CHECKREG r0, 0x000000AB; +CHECKREG r1, 0x000000AB; +CHECKREG r2, 0x000000AB; +CHECKREG r3, 0x000000AB; +CHECKREG r4, 0x000000AB; +CHECKREG r5, 0x000000AB; +CHECKREG r6, 0x000000AB; +CHECKREG r7, 0x000000AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.B (Z); +R1 = R5.B (Z); +R2 = R5.B (Z); +R3 = R5.B (Z); +R4 = R5.B (Z); +R6 = R5.B (Z); +R7 = R5.B (Z); +R5 = R5.B (Z); +CHECKREG r0, 0x000000BC; +CHECKREG r1, 0x000000BC; +CHECKREG r2, 0x000000BC; +CHECKREG r3, 0x000000BC; +CHECKREG r4, 0x000000BC; +CHECKREG r5, 0x000000BC; +CHECKREG r6, 0x000000BC; +CHECKREG r7, 0x000000BC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.B (Z); +R1 = R6.B (Z); +R2 = R6.B (Z); +R3 = R6.B (Z); +R4 = R6.B (Z); +R5 = R6.B (Z); +R7 = R6.B (Z); +R6 = R6.B (Z); +CHECKREG r0, 0x000000CD; +CHECKREG r1, 0x000000CD; +CHECKREG r2, 0x000000CD; +CHECKREG r3, 0x000000CD; +CHECKREG r4, 0x000000CD; +CHECKREG r5, 0x000000CD; +CHECKREG r6, 0x000000CD; +CHECKREG r7, 0x000000CD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.B (Z); +R1 = R7.B (Z); +R2 = R7.B (Z); +R3 = R7.B (Z); +R4 = R7.B (Z); +R5 = R7.B (Z); +R6 = R7.B (Z); +R7 = R7.B (Z); +CHECKREG r0, 0x00000088; +CHECKREG r1, 0x00000088; +CHECKREG r2, 0x00000088; +CHECKREG r3, 0x00000088; +CHECKREG r4, 0x00000088; +CHECKREG r5, 0x00000088; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x00000088; + + +pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_h.s b/sim/testsuite/sim/bfin/c_alu2op_conv_h.s new file mode 100644 index 0000000..70468a6 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_conv_h.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_h/c_alu2op_conv_h.dsp +// Spec Reference: alu2op convert h +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.L (Z); +R1 = R0.L (Z); +R2 = R0.L (Z); +R3 = R0.L (Z); +R4 = R0.L (Z); +R5 = R0.L (Z); +R6 = R0.L (Z); +R7 = R0.L (Z); +CHECKREG r0, 0x00009ABC; +CHECKREG r1, 0x00009ABC; +CHECKREG r2, 0x00009ABC; +CHECKREG r3, 0x00009ABC; +CHECKREG r4, 0x00009ABC; +CHECKREG r5, 0x00009ABC; +CHECKREG r6, 0x00009ABC; +CHECKREG r7, 0x00009ABC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.L (Z); +R2 = R1.L (Z); +R3 = R1.L (Z); +R4 = R1.L (Z); +R5 = R1.L (Z); +R6 = R1.L (Z); +R7 = R1.L (Z); +R1 = R1.L (Z); +CHECKREG r0, 0x00004659; +CHECKREG r1, 0x00004659; +CHECKREG r2, 0x00004659; +CHECKREG r3, 0x00004659; +CHECKREG r4, 0x00004659; +CHECKREG r5, 0x00004659; +CHECKREG r6, 0x00004659; +CHECKREG r7, 0x00004659; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.L (Z); +R1 = R2.L (Z); +R3 = R2.L (Z); +R4 = R2.L (Z); +R5 = R2.L (Z); +R6 = R2.L (Z); +R7 = R2.L (Z); +R2 = R2.L (Z); +CHECKREG r0, 0x00006789; +CHECKREG r1, 0x00006789; +CHECKREG r2, 0x00006789; +CHECKREG r3, 0x00006789; +CHECKREG r4, 0x00006789; +CHECKREG r5, 0x00006789; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x00006789; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.L (Z); +R1 = R3.L (Z); +R2 = R3.L (Z); +R4 = R3.L (Z); +R5 = R3.L (Z); +R6 = R3.L (Z); +R7 = R3.L (Z); +R3 = R3.L (Z); +CHECKREG r0, 0x0000789A; +CHECKREG r1, 0x0000789A; +CHECKREG r2, 0x0000789A; +CHECKREG r3, 0x0000789A; +CHECKREG r4, 0x0000789A; +CHECKREG r5, 0x0000789A; +CHECKREG r6, 0x0000789A; +CHECKREG r7, 0x0000789A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.L (Z); +R1 = R4.L (Z); +R2 = R4.L (Z); +R3 = R4.L (Z); +R4 = R4.L (Z); +R5 = R4.L (Z); +R6 = R4.L (Z); +R7 = R4.L (Z); +CHECKREG r0, 0x0000A9AB; +CHECKREG r1, 0x0000A9AB; +CHECKREG r2, 0x0000A9AB; +CHECKREG r3, 0x0000A9AB; +CHECKREG r4, 0x0000A9AB; +CHECKREG r5, 0x0000A9AB; +CHECKREG r6, 0x0000A9AB; +CHECKREG r7, 0x0000A9AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.L (Z); +R1 = R5.L (Z); +R2 = R5.L (Z); +R3 = R5.L (Z); +R4 = R5.L (Z); +R6 = R5.L (Z); +R7 = R5.L (Z); +R5 = R5.L (Z); +CHECKREG r0, 0x00009FBC; +CHECKREG r1, 0x00009FBC; +CHECKREG r2, 0x00009FBC; +CHECKREG r3, 0x00009FBC; +CHECKREG r4, 0x00009FBC; +CHECKREG r5, 0x00009FBC; +CHECKREG r6, 0x00009FBC; +CHECKREG r7, 0x00009FBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.L (Z); +R1 = R6.L (Z); +R2 = R6.L (Z); +R3 = R6.L (Z); +R4 = R6.L (Z); +R5 = R6.L (Z); +R7 = R6.L (Z); +R6 = R6.L (Z); +CHECKREG r0, 0x0000AECD; +CHECKREG r1, 0x0000AECD; +CHECKREG r2, 0x0000AECD; +CHECKREG r3, 0x0000AECD; +CHECKREG r4, 0x0000AECD; +CHECKREG r5, 0x0000AECD; +CHECKREG r6, 0x0000AECD; +CHECKREG r7, 0x0000AECD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.L (Z); +R1 = R7.L (Z); +R2 = R7.L (Z); +R3 = R7.L (Z); +R4 = R7.L (Z); +R5 = R7.L (Z); +R6 = R7.L (Z); +R7 = R7.L (Z); +CHECKREG r0, 0x0000BC88; +CHECKREG r1, 0x0000BC88; +CHECKREG r2, 0x0000BC88; +CHECKREG r3, 0x0000BC88; +CHECKREG r4, 0x0000BC88; +CHECKREG r5, 0x0000BC88; +CHECKREG r6, 0x0000BC88; +CHECKREG r7, 0x0000BC88; + + +pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_mix.s b/sim/testsuite/sim/bfin/c_alu2op_conv_mix.s new file mode 100644 index 0000000..7c33c13 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_conv_mix.s @@ -0,0 +1,186 @@ +//Original:/testcases/core/c_alu2op_conv_mix/c_alu2op_conv_mix.dsp +// Spec Reference: alu2op convert mix +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.B (X); +R1 = R1.L (X); +R2 = R2.L (Z); +R3 = R3.B (X); +R4 = R4.B (Z); +R5 = - R5; +R6 = ~ R6; +R7 = R7.L (X); +CHECKREG r0, 0xFFFFFFBC; +CHECKREG r1, 0x00005678; +CHECKREG r2, 0x00006789; +CHECKREG r3, 0xFFFFFF9A; +CHECKREG r4, 0x000000AB; +CHECKREG r5, 0x69876544; +CHECKREG r6, 0x58765432; +CHECKREG r7, 0xFFFFBCDE; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R6 = R0.B (X); +R7 = R1.L (X); +R0 = R2.L (Z); +R1 = R3.B (X); +R2 = R4.B (Z); +R3 = - R5; +R4 = ~ R6; +R5 = R7.L (X); +CHECKREG r0, 0x00006789; +CHECKREG r1, 0xFFFFFF9A; +CHECKREG r2, 0x000000AB; +CHECKREG r3, 0x39876544; +CHECKREG r4, 0xFFFFFFFD; +CHECKREG r5, 0x00004659; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0x00004659; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x91203450; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0x789abcde; +R5 = R0.B (X); +R6 = R1.L (X); +R7 = R2.L (Z); +R0 = R3.B (X); +R1 = R4.B (Z); +R2 = - R5; +R3 = ~ R6; +R4 = R7.L (X); +CHECKREG r0, 0xFFFFFF9A; +CHECKREG r1, 0x000000AB; +CHECKREG r2, 0xFFFFFFFE; +CHECKREG r3, 0xFFFFA987; +CHECKREG r4, 0x00003450; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00005678; +CHECKREG r7, 0x00003450; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0x00000000; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R4 = R0.B (X); +R5 = R1.L (X); +R6 = R2.L (Z); +R7 = R3.B (X); +R0 = R4.B (Z); +R1 = - R5; +R2 = ~ R6; +R3 = R7.L (X); +CHECKREG r0, 0x00000002; +CHECKREG r1, 0xFFFFA988; +CHECKREG r2, 0xFFFF9876; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00005678; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xadf00001; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x00000000; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R3 = R0.B (X); +R4 = R1.L (X); +R5 = R2.L (Z); +R6 = R3.B (X); +R7 = R4.B (Z); +R0 = - R5; +R1 = ~ R6; +R2 = R7.L (X); +CHECKREG r0, 0xFFFF9877; +CHECKREG r1, 0xFFFFFFFE; +CHECKREG r2, 0x00000078; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00005678; +CHECKREG r5, 0x00006789; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000078; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0x54238900; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R2 = R0.B (X); +R3 = R1.L (X); +R4 = R2.L (Z); +R5 = R3.B (X); +R6 = R4.B (Z); +R7 = - R5; +R0 = ~ R6; +R1 = R7.L (X); +CHECKREG r0, 0xFFFFFFFD; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x00000000; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x00000000; +imm32 r7, 0x789abcde; +R1 = R0.B (X); +R2 = R1.L (X); +R3 = R2.L (Z); +R4 = R3.B (X); +R5 = R4.B (Z); +R6 = - R5; +R0 = ~ R6; +R7 = R7.L (X); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000002; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0xFFFFFFFE; +CHECKREG r7, 0xFFFFBCDE; + + +pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_neg.s b/sim/testsuite/sim/bfin/c_alu2op_conv_neg.s new file mode 100644 index 0000000..85314a8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_conv_neg.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_neg/c_alu2op_conv_neg.dsp +// Spec Reference: alu2op (-) negative +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = - R0; +R1 = - R0; +R2 = - R0; +R3 = - R0; +R4 = - R0; +R5 = - R0; +R6 = - R0; +R7 = - R0; +CHECKREG r0, 0xFF876544; +CHECKREG r1, 0x00789ABC; +CHECKREG r2, 0x00789ABC; +CHECKREG r3, 0x00789ABC; +CHECKREG r4, 0x00789ABC; +CHECKREG r5, 0x00789ABC; +CHECKREG r6, 0x00789ABC; +CHECKREG r7, 0x00789ABC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = - R1; +R1 = - R1; +R2 = - R1; +R3 = - R1; +R4 = - R1; +R5 = - R1; +R6 = - R1; +R7 = - R1; +CHECKREG r0, 0xFFC8B9A7; +CHECKREG r1, 0xFFC8B9A7; +CHECKREG r2, 0x00374659; +CHECKREG r3, 0x00374659; +CHECKREG r4, 0x00374659; +CHECKREG r5, 0x00374659; +CHECKREG r6, 0x00374659; +CHECKREG r7, 0x00374659; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = - R2; +R1 = - R2; +R2 = - R2; +R3 = - R2; +R4 = - R2; +R5 = - R2; +R6 = - R2; +R7 = - R2; +CHECKREG r0, 0x6CEA9877; +CHECKREG r1, 0x6CEA9877; +CHECKREG r2, 0x6CEA9877; +CHECKREG r3, 0x93156789; +CHECKREG r4, 0x93156789; +CHECKREG r5, 0x93156789; +CHECKREG r6, 0x93156789; +CHECKREG r7, 0x93156789; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = - R3; +R1 = - R3; +R2 = - R3; +R3 = - R3; +R4 = - R3; +R5 = - R3; +R6 = - R3; +R7 = - R3; +CHECKREG r0, 0x56AD8766; +CHECKREG r1, 0x56AD8766; +CHECKREG r2, 0x56AD8766; +CHECKREG r3, 0x56AD8766; +CHECKREG r4, 0xA952789A; +CHECKREG r5, 0xA952789A; +CHECKREG r6, 0xA952789A; +CHECKREG r7, 0xA952789A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = - R4; +R1 = - R4; +R2 = - R4; +R3 = - R4; +R4 = - R4; +R5 = - R4; +R6 = - R4; +R7 = - R4; +CHECKREG r0, 0x79985655; +CHECKREG r1, 0x79985655; +CHECKREG r2, 0x79985655; +CHECKREG r3, 0x79985655; +CHECKREG r4, 0x79985655; +CHECKREG r5, 0x8667A9AB; +CHECKREG r6, 0x8667A9AB; +CHECKREG r7, 0x8667A9AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = - R5; +R1 = - R5; +R2 = - R5; +R3 = - R5; +R4 = - R5; +R5 = - R5; +R6 = - R5; +R7 = - R5; +CHECKREG r0, 0x39876044; +CHECKREG r1, 0x39876044; +CHECKREG r2, 0x39876044; +CHECKREG r3, 0x39876044; +CHECKREG r4, 0x39876044; +CHECKREG r5, 0x39876044; +CHECKREG r6, 0xC6789FBC; +CHECKREG r7, 0xC6789FBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = - R6; +R1 = - R6; +R2 = - R6; +R3 = - R6; +R4 = - R6; +R5 = - R6; +R6 = - R6; +R7 = - R6; +CHECKREG r0, 0x58765133; +CHECKREG r1, 0x58765133; +CHECKREG r2, 0x58765133; +CHECKREG r3, 0x58765133; +CHECKREG r4, 0x58765133; +CHECKREG r5, 0x58765133; +CHECKREG r6, 0x58765133; +CHECKREG r7, 0xA789AECD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = - R7; +R1 = - R7; +R2 = - R7; +R3 = - R7; +R4 = - R7; +R5 = - R7; +R7 = - R7; +R6 = - R7; +CHECKREG r0, 0xA7654378; +CHECKREG r1, 0xA7654378; +CHECKREG r2, 0xA7654378; +CHECKREG r3, 0xA7654378; +CHECKREG r4, 0xA7654378; +CHECKREG r5, 0xA7654378; +CHECKREG r6, 0x589ABC88; +CHECKREG r7, 0xA7654378; + + +pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_toggle.s b/sim/testsuite/sim/bfin/c_alu2op_conv_toggle.s new file mode 100644 index 0000000..791d7a9 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_conv_toggle.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_toggle/c_alu2op_conv_toggle.dsp +// Spec Reference: alu2op (~) toggle +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = ~ R0; +R1 = ~ R0; +R2 = ~ R0; +R3 = ~ R0; +R4 = ~ R0; +R5 = ~ R0; +R6 = ~ R0; +R7 = ~ R0; +CHECKREG r0, 0xFF876543; +CHECKREG r1, 0x00789ABC; +CHECKREG r2, 0x00789ABC; +CHECKREG r3, 0x00789ABC; +CHECKREG r4, 0x00789ABC; +CHECKREG r5, 0x00789ABC; +CHECKREG r6, 0x00789ABC; +CHECKREG r7, 0x00789ABC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = ~ R1; +R1 = ~ R1; +R2 = ~ R1; +R3 = ~ R1; +R4 = ~ R1; +R5 = ~ R1; +R6 = ~ R1; +R7 = ~ R1; +CHECKREG r0, 0xFFC8B9A6; +CHECKREG r1, 0xFFC8B9A6; +CHECKREG r2, 0x00374659; +CHECKREG r3, 0x00374659; +CHECKREG r4, 0x00374659; +CHECKREG r5, 0x00374659; +CHECKREG r6, 0x00374659; +CHECKREG r7, 0x00374659; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = ~ R2; +R1 = ~ R2; +R2 = ~ R2; +R3 = ~ R2; +R4 = ~ R2; +R5 = ~ R2; +R6 = ~ R2; +R7 = ~ R2; +CHECKREG r0, 0x6CEA9876; +CHECKREG r1, 0x6CEA9876; +CHECKREG r2, 0x6CEA9876; +CHECKREG r3, 0x93156789; +CHECKREG r4, 0x93156789; +CHECKREG r5, 0x93156789; +CHECKREG r6, 0x93156789; +CHECKREG r7, 0x93156789; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = ~ R3; +R1 = ~ R3; +R2 = ~ R3; +R3 = ~ R3; +R4 = ~ R3; +R5 = ~ R3; +R6 = ~ R3; +R7 = ~ R3; +CHECKREG r0, 0x56AD8765; +CHECKREG r1, 0x56AD8765; +CHECKREG r2, 0x56AD8765; +CHECKREG r3, 0x56AD8765; +CHECKREG r4, 0xA952789A; +CHECKREG r5, 0xA952789A; +CHECKREG r6, 0xA952789A; +CHECKREG r7, 0xA952789A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = ~ R4; +R1 = ~ R4; +R2 = ~ R4; +R3 = ~ R4; +R4 = ~ R4; +R5 = ~ R4; +R6 = ~ R4; +R7 = ~ R4; +CHECKREG r0, 0x79985654; +CHECKREG r1, 0x79985654; +CHECKREG r2, 0x79985654; +CHECKREG r3, 0x79985654; +CHECKREG r4, 0x79985654; +CHECKREG r5, 0x8667A9AB; +CHECKREG r6, 0x8667A9AB; +CHECKREG r7, 0x8667A9AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = ~ R5; +R1 = ~ R5; +R2 = ~ R5; +R3 = ~ R5; +R4 = ~ R5; +R5 = ~ R5; +R6 = ~ R5; +R7 = ~ R5; +CHECKREG r0, 0x39876043; +CHECKREG r1, 0x39876043; +CHECKREG r2, 0x39876043; +CHECKREG r3, 0x39876043; +CHECKREG r4, 0x39876043; +CHECKREG r5, 0x39876043; +CHECKREG r6, 0xC6789FBC; +CHECKREG r7, 0xC6789FBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = ~ R6; +R1 = ~ R6; +R2 = ~ R6; +R3 = ~ R6; +R4 = ~ R6; +R5 = ~ R6; +R6 = ~ R6; +R7 = ~ R6; +CHECKREG r0, 0x58765132; +CHECKREG r1, 0x58765132; +CHECKREG r2, 0x58765132; +CHECKREG r3, 0x58765132; +CHECKREG r4, 0x58765132; +CHECKREG r5, 0x58765132; +CHECKREG r6, 0x58765132; +CHECKREG r7, 0xA789AECD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = ~ R7; +R1 = ~ R7; +R2 = ~ R7; +R3 = ~ R7; +R4 = ~ R7; +R5 = ~ R7; +R7 = ~ R7; +R6 = ~ R7; +CHECKREG r0, 0xA7654377; +CHECKREG r1, 0xA7654377; +CHECKREG r2, 0xA7654377; +CHECKREG r3, 0xA7654377; +CHECKREG r4, 0xA7654377; +CHECKREG r5, 0xA7654377; +CHECKREG r6, 0x589ABC88; +CHECKREG r7, 0xA7654377; + + +pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_xb.s b/sim/testsuite/sim/bfin/c_alu2op_conv_xb.s new file mode 100644 index 0000000..779a790 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_conv_xb.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_xb/c_alu2op_conv_xb.dsp +// Spec Reference: alu2op convert xb +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.B (X); +R1 = R0.B (X); +R2 = R0.B (X); +R3 = R0.B (X); +R4 = R0.B (X); +R5 = R0.B (X); +R6 = R0.B (X); +R7 = R0.B (X); +CHECKREG r0, 0xFFFFFFBC; +CHECKREG r1, 0xFFFFFFBC; +CHECKREG r2, 0xFFFFFFBC; +CHECKREG r3, 0xFFFFFFBC; +CHECKREG r4, 0xFFFFFFBC; +CHECKREG r5, 0xFFFFFFBC; +CHECKREG r6, 0xFFFFFFBC; +CHECKREG r7, 0xFFFFFFBC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.B (X); +R2 = R1.B (X); +R3 = R1.B (X); +R4 = R1.B (X); +R5 = R1.B (X); +R6 = R1.B (X); +R7 = R1.B (X); +R1 = R1.B (X); +CHECKREG r0, 0x00000059; +CHECKREG r1, 0x00000059; +CHECKREG r2, 0x00000059; +CHECKREG r3, 0x00000059; +CHECKREG r4, 0x00000059; +CHECKREG r5, 0x00000059; +CHECKREG r6, 0x00000059; +CHECKREG r7, 0x00000059; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.B (X); +R1 = R2.B (X); +R3 = R2.B (X); +R4 = R2.B (X); +R5 = R2.B (X); +R6 = R2.B (X); +R7 = R2.B (X); +R2 = R2.B (X); +CHECKREG r0, 0xFFFFFF89; +CHECKREG r1, 0xFFFFFF89; +CHECKREG r2, 0xFFFFFF89; +CHECKREG r3, 0xFFFFFF89; +CHECKREG r4, 0xFFFFFF89; +CHECKREG r5, 0xFFFFFF89; +CHECKREG r6, 0xFFFFFF89; +CHECKREG r7, 0xFFFFFF89; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.B (X); +R1 = R3.B (X); +R2 = R3.B (X); +R4 = R3.B (X); +R5 = R3.B (X); +R6 = R3.B (X); +R7 = R3.B (X); +R3 = R3.B (X); +CHECKREG r0, 0xFFFFFF9A; +CHECKREG r1, 0xFFFFFF9A; +CHECKREG r2, 0xFFFFFF9A; +CHECKREG r3, 0xFFFFFF9A; +CHECKREG r4, 0xFFFFFF9A; +CHECKREG r5, 0xFFFFFF9A; +CHECKREG r6, 0xFFFFFF9A; +CHECKREG r7, 0xFFFFFF9A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.B (X); +R1 = R4.B (X); +R2 = R4.B (X); +R3 = R4.B (X); +R4 = R4.B (X); +R5 = R4.B (X); +R6 = R4.B (X); +R7 = R4.B (X); +CHECKREG r0, 0xFFFFFFAB; +CHECKREG r1, 0xFFFFFFAB; +CHECKREG r2, 0xFFFFFFAB; +CHECKREG r3, 0xFFFFFFAB; +CHECKREG r4, 0xFFFFFFAB; +CHECKREG r5, 0xFFFFFFAB; +CHECKREG r6, 0xFFFFFFAB; +CHECKREG r7, 0xFFFFFFAB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.B (X); +R1 = R5.B (X); +R2 = R5.B (X); +R3 = R5.B (X); +R4 = R5.B (X); +R6 = R5.B (X); +R7 = R5.B (X); +R5 = R5.B (X); +CHECKREG r0, 0xFFFFFFBC; +CHECKREG r1, 0xFFFFFFBC; +CHECKREG r2, 0xFFFFFFBC; +CHECKREG r3, 0xFFFFFFBC; +CHECKREG r4, 0xFFFFFFBC; +CHECKREG r5, 0xFFFFFFBC; +CHECKREG r6, 0xFFFFFFBC; +CHECKREG r7, 0xFFFFFFBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.B (X); +R1 = R6.B (X); +R2 = R6.B (X); +R3 = R6.B (X); +R4 = R6.B (X); +R5 = R6.B (X); +R7 = R6.B (X); +R6 = R6.B (X); +CHECKREG r0, 0xFFFFFFCD; +CHECKREG r1, 0xFFFFFFCD; +CHECKREG r2, 0xFFFFFFCD; +CHECKREG r3, 0xFFFFFFCD; +CHECKREG r4, 0xFFFFFFCD; +CHECKREG r5, 0xFFFFFFCD; +CHECKREG r6, 0xFFFFFFCD; +CHECKREG r7, 0xFFFFFFCD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.B (X); +R1 = R7.B (X); +R2 = R7.B (X); +R3 = R7.B (X); +R4 = R7.B (X); +R5 = R7.B (X); +R6 = R7.B (X); +R7 = R7.B (X); +CHECKREG r0, 0xFFFFFF88; +CHECKREG r1, 0xFFFFFF88; +CHECKREG r2, 0xFFFFFF88; +CHECKREG r3, 0xFFFFFF88; +CHECKREG r4, 0xFFFFFF88; +CHECKREG r5, 0xFFFFFF88; +CHECKREG r6, 0xFFFFFF88; +CHECKREG r7, 0xFFFFFF88; + + +pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_conv_xh.s b/sim/testsuite/sim/bfin/c_alu2op_conv_xh.s new file mode 100644 index 0000000..75b06c0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_conv_xh.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_alu2op_conv_xh/c_alu2op_conv_xh.dsp +// Spec Reference: alu2op convert xh +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.L (X); +R1 = R0.L (X); +R2 = R0.L (X); +R3 = R0.L (X); +R4 = R0.L (X); +R5 = R0.L (X); +R6 = R0.L (X); +R7 = R0.L (X); +CHECKREG r0, 0xFFFF9ABC; +CHECKREG r1, 0xFFFF9ABC; +CHECKREG r2, 0xFFFF9ABC; +CHECKREG r3, 0xFFFF9ABC; +CHECKREG r4, 0xFFFF9ABC; +CHECKREG r5, 0xFFFF9ABC; +CHECKREG r6, 0xFFFF9ABC; +CHECKREG r7, 0xFFFF9ABC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.L (X); +R2 = R1.L (X); +R3 = R1.L (X); +R4 = R1.L (X); +R5 = R1.L (X); +R6 = R1.L (X); +R7 = R1.L (X); +R1 = R1.L (X); +CHECKREG r0, 0x00004659; +CHECKREG r1, 0x00004659; +CHECKREG r2, 0x00004659; +CHECKREG r3, 0x00004659; +CHECKREG r4, 0x00004659; +CHECKREG r5, 0x00004659; +CHECKREG r6, 0x00004659; +CHECKREG r7, 0x00004659; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.L (X); +R1 = R2.L (X); +R3 = R2.L (X); +R4 = R2.L (X); +R5 = R2.L (X); +R6 = R2.L (X); +R7 = R2.L (X); +R2 = R2.L (X); +CHECKREG r0, 0x00006789; +CHECKREG r1, 0x00006789; +CHECKREG r2, 0x00006789; +CHECKREG r3, 0x00006789; +CHECKREG r4, 0x00006789; +CHECKREG r5, 0x00006789; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x00006789; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.L (X); +R1 = R3.L (X); +R2 = R3.L (X); +R4 = R3.L (X); +R5 = R3.L (X); +R6 = R3.L (X); +R7 = R3.L (X); +R3 = R3.L (X); +CHECKREG r0, 0x0000789A; +CHECKREG r1, 0x0000789A; +CHECKREG r2, 0x0000789A; +CHECKREG r3, 0x0000789A; +CHECKREG r4, 0x0000789A; +CHECKREG r5, 0x0000789A; +CHECKREG r6, 0x0000789A; +CHECKREG r7, 0x0000789A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.L (X); +R1 = R4.L (X); +R2 = R4.L (X); +R3 = R4.L (X); +R4 = R4.L (X); +R5 = R4.L (X); +R6 = R4.L (X); +R7 = R4.L (X); +CHECKREG r0, 0xFFFFA9AB; +CHECKREG r1, 0xFFFFA9AB; +CHECKREG r2, 0xFFFFA9AB; +CHECKREG r3, 0xFFFFA9AB; +CHECKREG r4, 0xFFFFA9AB; +CHECKREG r5, 0xFFFFA9AB; +CHECKREG r6, 0xFFFFA9AB; +CHECKREG r7, 0xFFFFA9AB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.L (X); +R1 = R5.L (X); +R2 = R5.L (X); +R3 = R5.L (X); +R4 = R5.L (X); +R6 = R5.L (X); +R7 = R5.L (X); +R5 = R5.L (X); +CHECKREG r0, 0xFFFF9FBC; +CHECKREG r1, 0xFFFF9FBC; +CHECKREG r2, 0xFFFF9FBC; +CHECKREG r3, 0xFFFF9FBC; +CHECKREG r4, 0xFFFF9FBC; +CHECKREG r5, 0xFFFF9FBC; +CHECKREG r6, 0xFFFF9FBC; +CHECKREG r7, 0xFFFF9FBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.L (X); +R1 = R6.L (X); +R2 = R6.L (X); +R3 = R6.L (X); +R4 = R6.L (X); +R5 = R6.L (X); +R7 = R6.L (X); +R6 = R6.L (X); +CHECKREG r0, 0xFFFFAECD; +CHECKREG r1, 0xFFFFAECD; +CHECKREG r2, 0xFFFFAECD; +CHECKREG r3, 0xFFFFAECD; +CHECKREG r4, 0xFFFFAECD; +CHECKREG r5, 0xFFFFAECD; +CHECKREG r6, 0xFFFFAECD; +CHECKREG r7, 0xFFFFAECD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.L (X); +R1 = R7.L (X); +R2 = R7.L (X); +R3 = R7.L (X); +R4 = R7.L (X); +R5 = R7.L (X); +R6 = R7.L (X); +R7 = R7.L (X); +CHECKREG r0, 0xFFFFBC88; +CHECKREG r1, 0xFFFFBC88; +CHECKREG r2, 0xFFFFBC88; +CHECKREG r3, 0xFFFFBC88; +CHECKREG r4, 0xFFFFBC88; +CHECKREG r5, 0xFFFFBC88; +CHECKREG r6, 0xFFFFBC88; +CHECKREG r7, 0xFFFFBC88; + + +pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_divq.s b/sim/testsuite/sim/bfin/c_alu2op_divq.s new file mode 100644 index 0000000..2a03227 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_divq.s @@ -0,0 +1,220 @@ +//Original:/testcases/core/c_alu2op_divq/c_alu2op_divq.dsp +// Spec Reference: alu2op divide q +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0.L = 1; +DIVQ ( R1 , R0 ); +DIVQ ( R2 , R0 ); +DIVQ ( R3 , R0 ); +DIVQ ( R4 , R0 ); +DIVQ ( R5 , R0 ); +DIVQ ( R6 , R0 ); +DIVQ ( R7 , R0 ); +DIVQ ( R4 , R0 ); +DIVQ ( R0 , R0 ); +CHECKREG r1, 0x2466ACF1; +CHECKREG r2, 0x4688CF13; +CHECKREG r3, 0x68AAF135; +CHECKREG r4, 0x159C26AD; +CHECKREG r5, 0x2CF33578; +CHECKREG r6, 0x4F15579A; +CHECKREG r7, 0x713779BC; +CHECKREG r0, 0xFFFE0002; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R1.L = -1; +DIVQ ( R0 , R1 ); +DIVQ ( R2 , R1 ); +DIVQ ( R3 , R1 ); +DIVQ ( R4 , R1 ); +DIVQ ( R5 , R1 ); +DIVQ ( R6 , R1 ); +DIVQ ( R7 , R1 ); +DIVQ ( R1 , R1 ); +CHECKREG r0, 0x02440004; +CHECKREG r1, 0x0003FFFE; +CHECKREG r2, 0x2688CF13; +CHECKREG r3, 0x48AEF135; +CHECKREG r4, 0x6AD11357; +CHECKREG r5, 0x8CF33579; +CHECKREG r6, 0xAF15579B; +CHECKREG r7, 0xD13779BD; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x00000000; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 31; +DIVQ ( R0 , R2 ); +DIVQ ( R1 , R2 ); +DIVQ ( R3 , R2 ); +DIVQ ( R4 , R2 ); +DIVQ ( R5 , R2 ); +DIVQ ( R6 , R2 ); +DIVQ ( R7 , R2 ); +DIVQ ( R2 , R2 ); +CHECKREG r0, 0xA2840005; +CHECKREG r1, 0x242AACF1; +CHECKREG r2, 0xFFC2003E; +CHECKREG r3, 0x686EF135; +CHECKREG r4, 0x2A911356; +CHECKREG r5, 0x0D2F3578; +CHECKREG r6, 0xCF51579B; +CHECKREG r7, 0xF0F779BD; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0x00000000; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R3.L = -31; +DIVQ ( R0 , R3 ); +DIVQ ( R1 , R3 ); +DIVQ ( R2 , R3 ); +DIVQ ( R4 , R3 ); +DIVQ ( R5 , R3 ); +DIVQ ( R6 , R3 ); +DIVQ ( R7 , R3 ); +DIVQ ( R3 , R3 ); +CHECKREG r0, 0x02080004; +CHECKREG r1, 0x042AACF1; +CHECKREG r2, 0x26C8CF13; +CHECKREG r3, 0x003FFFC2; +CHECKREG r4, 0x6B0D1357; +CHECKREG r5, 0x8D2F3579; +CHECKREG r6, 0xAF51579B; +CHECKREG r7, 0xD17379BD; + +imm32 r0, 0x00000001; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x00000000; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R4.L = 15; +DIVQ ( R1 , R4 ); +DIVQ ( R2 , R4 ); +DIVQ ( R3 , R4 ); +DIVQ ( R0 , R4 ); +DIVQ ( R5 , R4 ); +DIVQ ( R6 , R4 ); +DIVQ ( R7 , R4 ); +DIVQ ( R4 , R4 ); +CHECKREG r0, 0xFFE20002; +CHECKREG r1, 0x2486ACF1; +CHECKREG r2, 0x466CCF13; +CHECKREG r3, 0x688EF135; +CHECKREG r4, 0x001E001F; +CHECKREG r5, 0x2D0F3578; +CHECKREG r6, 0x4F31579A; +CHECKREG r7, 0x715379BC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0x00000000; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R5.L = -15; +DIVQ ( R0 , R5 ); +DIVQ ( R1 , R5 ); +DIVQ ( R2 , R5 ); +DIVQ ( R3 , R5 ); +DIVQ ( R4 , R5 ); +DIVQ ( R6 , R5 ); +DIVQ ( R7 , R5 ); +DIVQ ( R5 , R5 ); +CHECKREG r0, 0x02640004; +CHECKREG r1, 0xFFE20001; +CHECKREG r2, 0x26A8CF13; +CHECKREG r3, 0x48CAF135; +CHECKREG r4, 0x6AED1357; +CHECKREG r5, 0x001FFFE2; +CHECKREG r6, 0xAF31579B; +CHECKREG r7, 0xD15379BD; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0xb1256790; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x00000000; +imm32 r7, 0x789abcde; +R6.L = 24; +DIVQ ( R0 , R6 ); +DIVQ ( R1 , R6 ); +DIVQ ( R2 , R6 ); +DIVQ ( R3 , R6 ); +DIVQ ( R4 , R6 ); +DIVQ ( R5 , R6 ); +DIVQ ( R7 , R6 ); +DIVQ ( R6 , R6 ); +CHECKREG r0, 0xA2760005; +CHECKREG r1, 0x2438ACF1; +CHECKREG r2, 0x621ACF20; +CHECKREG r3, 0x68DCF135; +CHECKREG r4, 0x2A9F1356; +CHECKREG r5, 0x0D213578; +CHECKREG r6, 0xFFD00030; +CHECKREG r7, 0xF16579BD; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0x00000000; +R7.L = -24; +DIVQ ( R0 , R7 ); +DIVQ ( R1 , R7 ); +DIVQ ( R2 , R7 ); +DIVQ ( R3 , R7 ); +DIVQ ( R4 , R7 ); +DIVQ ( R5 , R7 ); +DIVQ ( R6 , R7 ); +DIVQ ( R7 , R7 ); +CHECKREG r0, 0x02160004; +CHECKREG r1, 0x0438ACF1; +CHECKREG r2, 0x26BACF13; +CHECKREG r3, 0x48DCF135; +CHECKREG r4, 0x6AFF1357; +CHECKREG r5, 0x8D213579; +CHECKREG r6, 0xAF43579B; +CHECKREG r7, 0x0031FFD0; + + +pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_divs.s b/sim/testsuite/sim/bfin/c_alu2op_divs.s new file mode 100644 index 0000000..f0fc091 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_divs.s @@ -0,0 +1,220 @@ +//Original:/testcases/core/c_alu2op_divs/c_alu2op_divs.dsp +// Spec Reference: alu2op divide s +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0.L = 1; +DIVS ( R1 , R0 ); +DIVS ( R2 , R0 ); +DIVS ( R3 , R0 ); +DIVS ( R4 , R0 ); +DIVS ( R5 , R0 ); +DIVS ( R6 , R0 ); +DIVS ( R7 , R0 ); +DIVS ( R4 , R0 ); +DIVS ( R0 , R0 ); +CHECKREG r1, 0x2468ACF0; +CHECKREG r2, 0x468ACF12; +CHECKREG r3, 0x68ACF134; +CHECKREG r4, 0x159E26AE; +CHECKREG r5, 0x2CF13579; +CHECKREG r6, 0x4F13579B; +CHECKREG r7, 0x713579BD; +CHECKREG r0, 0x00000002; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R1.L = -1; +DIVS ( R0 , R1 ); +DIVS ( R2 , R1 ); +DIVS ( R3 , R1 ); +DIVS ( R4 , R1 ); +DIVS ( R5 , R1 ); +DIVS ( R6 , R1 ); +DIVS ( R7 , R1 ); +DIVS ( R1 , R1 ); +CHECKREG r0, 0x02460005; +CHECKREG r1, 0x0001FFFF; +CHECKREG r2, 0x268ACF12; +CHECKREG r3, 0x48ACF134; +CHECKREG r4, 0x6ACF1356; +CHECKREG r5, 0x8CF13578; +CHECKREG r6, 0xAF13579A; +CHECKREG r7, 0xD13579BC; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0x00000000; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 31; +DIVS ( R0 , R2 ); +DIVS ( R1 , R2 ); +DIVS ( R3 , R2 ); +DIVS ( R4 , R2 ); +DIVS ( R5 , R2 ); +DIVS ( R6 , R2 ); +DIVS ( R7 , R2 ); +DIVS ( R2 , R2 ); +CHECKREG r0, 0xA2460004; +CHECKREG r1, 0x2468ACF0; +CHECKREG r2, 0x0000003E; +CHECKREG r3, 0x68ACF134; +CHECKREG r4, 0x2ACF1357; +CHECKREG r5, 0x0CF13579; +CHECKREG r6, 0xCF13579A; +CHECKREG r7, 0xF13579BC; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0x00000000; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R3.L = -31; +DIVS ( R0 , R3 ); +DIVS ( R1 , R3 ); +DIVS ( R2 , R3 ); +DIVS ( R4 , R3 ); +DIVS ( R5 , R3 ); +DIVS ( R6 , R3 ); +DIVS ( R7 , R3 ); +DIVS ( R3 , R3 ); +CHECKREG r0, 0x02460005; +CHECKREG r1, 0x0468ACF0; +CHECKREG r2, 0x268ACF12; +CHECKREG r3, 0x0001FFC3; +CHECKREG r4, 0x6ACF1356; +CHECKREG r5, 0x8CF13578; +CHECKREG r6, 0xAF13579A; +CHECKREG r7, 0xD13579BC; + +imm32 r0, 0x00000001; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x00000000; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R4.L = 15; +DIVS ( R1 , R4 ); +DIVS ( R2 , R4 ); +DIVS ( R3 , R4 ); +DIVS ( R0 , R4 ); +DIVS ( R5 , R4 ); +DIVS ( R6 , R4 ); +DIVS ( R7 , R4 ); +DIVS ( R4 , R4 ); +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x2468ACF0; +CHECKREG r2, 0x468ACF12; +CHECKREG r3, 0x68ACF134; +CHECKREG r4, 0x0000001E; +CHECKREG r5, 0x2CF13579; +CHECKREG r6, 0x4F13579B; +CHECKREG r7, 0x713579BD; + +imm32 r0, 0x01230002; +imm32 r1, 0x00000000; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0x00000000; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R5.L = -15; +DIVS ( R0 , R5 ); +DIVS ( R1 , R5 ); +DIVS ( R2 , R5 ); +DIVS ( R3 , R5 ); +DIVS ( R4 , R5 ); +DIVS ( R6 , R5 ); +DIVS ( R7 , R5 ); +DIVS ( R5 , R5 ); +CHECKREG r0, 0x02460005; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x268ACF12; +CHECKREG r3, 0x48ACF134; +CHECKREG r4, 0x6ACF1356; +CHECKREG r5, 0x0001FFE3; +CHECKREG r6, 0xAF13579A; +CHECKREG r7, 0xD13579BC; + +imm32 r0, 0x51230002; +imm32 r1, 0x12345678; +imm32 r2, 0xb1256790; +imm32 r3, 0x3456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x00000000; +imm32 r7, 0x789abcde; +R6.L = 24; +DIVS ( R0 , R6 ); +DIVS ( R1 , R6 ); +DIVS ( R2 , R6 ); +DIVS ( R3 , R6 ); +DIVS ( R4 , R6 ); +DIVS ( R5 , R6 ); +DIVS ( R7 , R6 ); +DIVS ( R6 , R6 ); +CHECKREG r0, 0xA2460004; +CHECKREG r1, 0x2468ACF0; +CHECKREG r2, 0x624ACF21; +CHECKREG r3, 0x68ACF134; +CHECKREG r4, 0x2ACF1357; +CHECKREG r5, 0x0CF13579; +CHECKREG r6, 0x00000030; +CHECKREG r7, 0xF13579BC; + +imm32 r0, 0x01230002; +imm32 r1, 0x82345678; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0x00000000; +R7.L = -24; +DIVS ( R0 , R7 ); +DIVS ( R1 , R7 ); +DIVS ( R2 , R7 ); +DIVS ( R3 , R7 ); +DIVS ( R4 , R7 ); +DIVS ( R5 , R7 ); +DIVS ( R6 , R7 ); +DIVS ( R7 , R7 ); +CHECKREG r0, 0x02460005; +CHECKREG r1, 0x0468ACF0; +CHECKREG r2, 0x268ACF12; +CHECKREG r3, 0x48ACF134; +CHECKREG r4, 0x6ACF1356; +CHECKREG r5, 0x8CF13578; +CHECKREG r6, 0xAF13579A; +CHECKREG r7, 0x0001FFD1; + + +pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_log_l_sft.s b/sim/testsuite/sim/bfin/c_alu2op_log_l_sft.s new file mode 100644 index 0000000..06489ef --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_log_l_sft.s @@ -0,0 +1,220 @@ +//Original:/proj/frio/dv/testcases/core/c_alu2op_log_l_sft/c_alu2op_log_l_sft.dsp +// Spec Reference: alu2op logical left +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x00000000; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x856789ab; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R0.L = 1; + R1 <<= R0; + R2 <<= R0; + R3 <<= R0; + R4 <<= R0; + R5 <<= R0; + R6 <<= R0; + R7 <<= R0; + R4 <<= R0; + R0 <<= R0; + CHECKREG r1, 0x2468ACF0; + CHECKREG r2, 0x468ACF12; + CHECKREG r3, 0x68ACF134; + CHECKREG r4, 0x159E26AC; + CHECKREG r5, 0x2CF13578; + CHECKREG r6, 0x4F13579A; + CHECKREG r7, 0x713579BC; + CHECKREG r0, 0x00000002; + + imm32 r0, 0x01230002; + imm32 r1, 0x00000000; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R1.L = -1; + R0 <<= R1; + R2 <<= R1; + R3 <<= R1; + R4 <<= R1; + R5 <<= R1; + R6 <<= R1; + R7 <<= R1; + R1 <<= R1; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x51230002; + imm32 r1, 0x12345678; + imm32 r2, 0x00000000; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x86789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2.L = 31; + R0 <<= R2; + R1 <<= R2; + R3 <<= R2; + R4 <<= R2; + R5 <<= R2; + R6 <<= R2; + R7 <<= R2; + R2 <<= R2; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x80000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x80000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x80000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0x00000000; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R3.L = -31; + R0 <<= R3; + R1 <<= R3; + R2 <<= R3; + R4 <<= R3; + R5 <<= R3; + R6 <<= R3; + R7 <<= R3; + R3 <<= R3; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x00000001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x00000000; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R4.L = 15; + R1 <<= R4; + R2 <<= R4; + R3 <<= R4; + R0 <<= R4; + R5 <<= R4; + R6 <<= R4; + R7 <<= R4; + R4 <<= R4; + CHECKREG r0, 0x00008000; + CHECKREG r1, 0x2B3C0000; + CHECKREG r2, 0xB3C48000; + CHECKREG r3, 0x3C4D0000; + CHECKREG r4, 0x00078000; + CHECKREG r5, 0x4D5E0000; + CHECKREG r6, 0xD5E68000; + CHECKREG r7, 0x5E6F0000; + + imm32 r0, 0x01230002; + imm32 r1, 0x00000000; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0x00000000; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R5.L = -15; + R0 <<= R5; + R1 <<= R5; + R2 <<= R5; + R3 <<= R5; + R4 <<= R5; + R6 <<= R5; + R7 <<= R5; + R5 <<= R5; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x51230002; + imm32 r1, 0x12345678; + imm32 r2, 0xb1256790; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x86789abc; + imm32 r6, 0x00000000; + imm32 r7, 0x789abcde; + R6.L = 24; + R0 <<= R6; + R1 <<= R6; + R2 <<= R6; + R3 <<= R6; + R4 <<= R6; + R5 <<= R6; + R7 <<= R6; + R6 <<= R6; + CHECKREG r0, 0x02000000; + CHECKREG r1, 0x78000000; + CHECKREG r2, 0x90000000; + CHECKREG r3, 0x9A000000; + CHECKREG r4, 0xAB000000; + CHECKREG r5, 0xBC000000; + CHECKREG r6, 0x18000000; + CHECKREG r7, 0xDE000000; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0x00000000; + R7.L = -24; + R0 <<= R7; + R1 <<= R7; + R2 <<= R7; + R3 <<= R7; + R4 <<= R7; + R5 <<= R7; + R6 <<= R7; + R7 <<= R7; + CHECKREG r0, 0x00; + CHECKREG r1, 0x00; + CHECKREG r2, 0x00; + CHECKREG r3, 0x00; + CHECKREG r4, 0x00; + CHECKREG r5, 0x00; + CHECKREG r6, 0x00; + CHECKREG r7, 0x00; + + pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_log_r_sft.s b/sim/testsuite/sim/bfin/c_alu2op_log_r_sft.s new file mode 100644 index 0000000..fdb14fc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_log_r_sft.s @@ -0,0 +1,217 @@ +//Original:/proj/frio/dv/testcases/core/c_alu2op_log_r_sft/c_alu2op_log_r_sft.dsp +// Spec Reference: alu2op logical right +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x856789ab; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R0.L = 1; + R1 >>= R0; + R2 >>= R0; + R3 >>= R0; + R4 >>= R0; + R5 >>= R0; + R6 >>= R0; + R7 >>= R0; + R4 >>= R0; + R0 >>= R0; + CHECKREG r1, 0x091A2B3C; + CHECKREG r2, 0x11A2B3C4; + CHECKREG r3, 0x1A2B3C4D; + CHECKREG r4, 0x2159E26A; + CHECKREG r5, 0x4B3C4D5E; + CHECKREG r6, 0x53C4D5E6; + CHECKREG r7, 0x5C4D5E6F; + CHECKREG r0, 0x00000000; + + imm32 r0, 0x01230002; + imm32 r1, 0x00000000; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R1.L = -1; + R0 >>= R1; + R2 >>= R1; + R3 >>= R1; + R4 >>= R1; + R5 >>= R1; + R6 >>= R1; + R7 >>= R1; + R1 >>= R1; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x51230002; + imm32 r1, 0x12345678; + imm32 r2, 0x00000000; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x86789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2.L = 31; + R0 >>= R2; + R1 >>= R2; + R3 >>= R2; + R4 >>= R2; + R5 >>= R2; + R6 >>= R2; + R7 >>= R2; + R2 >>= R2; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000001; + CHECKREG r5, 0x00000001; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0x00000000; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R3.L = -31; + R0 >>= R3; + R1 >>= R3; + R2 >>= R3; + R4 >>= R3; + R5 >>= R3; + R6 >>= R3; + R7 >>= R3; + R3 >>= R3; + CHECKREG r0, 0x00; + CHECKREG r1, 0x0; + CHECKREG r2, 0x0; + CHECKREG r3, 0x0; + CHECKREG r4, 0x0; + CHECKREG r5, 0x0; + CHECKREG r6, 0x0; + CHECKREG r7, 0x0; + + imm32 r0, 0x00000001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x00000000; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R4.L = 15; + R1 >>= R4; + R2 >>= R4; + R3 >>= R4; + R0 >>= R4; + R5 >>= R4; + R6 >>= R4; + R7 >>= R4; + R4 >>= R4; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00002468; + CHECKREG r2, 0x0000468A; + CHECKREG r3, 0x000068AC; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00012CF1; + CHECKREG r6, 0x00014F13; + CHECKREG r7, 0x00017135; + + imm32 r0, 0x01230002; + imm32 r1, 0x00000000; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0x00000000; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R5.L = -15; + R0 >>= R5; + R1 >>= R5; + R2 >>= R5; + R3 >>= R5; + R4 >>= R5; + R6 >>= R5; + R7 >>= R5; + R5 >>= R5; + CHECKREG r0, 0x000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x0000; + CHECKREG r3, 0x0000; + CHECKREG r4, 0x0000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x0000; + CHECKREG r7, 0x0000; + + imm32 r0, 0x51230002; + imm32 r1, 0x12345678; + imm32 r2, 0xb1256790; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x86789abc; + imm32 r6, 0x00000000; + imm32 r7, 0x789abcde; + R6.L = 24; + R0 >>= R6; + R1 >>= R6; + R2 >>= R6; + R3 >>= R6; + R4 >>= R6; + R5 >>= R6; + R7 >>= R6; + R6 >>= R6; + CHECKREG r0, 0x00000051; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x000000B1; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000095; + CHECKREG r5, 0x00000086; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000078; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0x00000000; + R7.L = -24; + R0 >>= R7; + R1 >>= R7; + R2 >>= R7; + R3 >>= R7; + R4 >>= R7; + R5 >>= R7; + R6 >>= R7; + R7 >>= R7; + CHECKREG r0, 0x00; + CHECKREG r1, 0x00; + CHECKREG r2, 0x00; + CHECKREG r3, 0x00; + CHECKREG r4, 0x00; + CHECKREG r5, 0x00; + CHECKREG r6, 0x00; + CHECKREG r7, 0x00; + + pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_shadd_1.s b/sim/testsuite/sim/bfin/c_alu2op_shadd_1.s new file mode 100644 index 0000000..73e39ec --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_shadd_1.s @@ -0,0 +1,209 @@ +//Original:/testcases/core/c_alu2op_shadd_1/c_alu2op_shadd_1.dsp +// Spec Reference: alu2op shadd 1 +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x03417990; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R1 = ( R1 + R0 ) << 1; +R2 = ( R2 + R0 ) << 1; +R3 = ( R3 + R0 ) << 1; +R4 = ( R4 + R0 ) << 1; +R5 = ( R5 + R0 ) << 1; +R6 = ( R6 + R0 ) << 1; +R7 = ( R7 + R0 ) << 1; +R0 = ( R0 + R0 ) << 1; +CHECKREG r0, 0x0D05E640; +CHECKREG r1, 0x2AE5A010; +CHECKREG r2, 0x4D05C232; +CHECKREG r3, 0x6F25E454; +CHECKREG r4, 0x11460676; +CHECKREG r5, 0x33662898; +CHECKREG r6, 0x55864ABA; +CHECKREG r7, 0x77A66CDC; + +imm32 r0, 0x03457290; +imm32 r1, 0x12345278; +imm32 r2, 0x23456289; +imm32 r3, 0x3456729a; +imm32 r4, 0x856782ab; +imm32 r5, 0x967892bc; +imm32 r6, 0xa789a2cd; +imm32 r7, 0xb89ab2de; +R0 = ( R0 + R1 ) << 1; +R2 = ( R2 + R1 ) << 1; +R3 = ( R3 + R1 ) << 1; +R4 = ( R4 + R1 ) << 1; +R5 = ( R5 + R1 ) << 1; +R6 = ( R6 + R1 ) << 1; +R7 = ( R7 + R1 ) << 1; +R1 = ( R1 + R1 ) << 1; +CHECKREG r0, 0x2AF38A10; +CHECKREG r1, 0x48D149E0; +CHECKREG r2, 0x6AF36A02; +CHECKREG r3, 0x8D158A24; +CHECKREG r4, 0x2F37AA46; +CHECKREG r5, 0x5159CA68; +CHECKREG r6, 0x737BEA8A; +CHECKREG r7, 0x959E0AAC; + +imm32 r0, 0x03457930; +imm32 r1, 0x12345638; +imm32 r2, 0x23456739; +imm32 r3, 0x3456783a; +imm32 r4, 0x8567893b; +imm32 r5, 0x96789a3c; +imm32 r6, 0xa789ab3d; +imm32 r7, 0xb89abc3e; +R0 = ( R0 + R2 ) << 1; +R1 = ( R1 + R2 ) << 1; +R3 = ( R3 + R2 ) << 1; +R4 = ( R4 + R2 ) << 1; +R5 = ( R5 + R2 ) << 1; +R6 = ( R6 + R2 ) << 1; +R7 = ( R7 + R2 ) << 1; +R2 = ( R2 + R2 ) << 1; +CHECKREG r0, 0x4D15C0D2; +CHECKREG r1, 0x6AF37AE2; +CHECKREG r2, 0x8D159CE4; +CHECKREG r3, 0xAF37BEE6; +CHECKREG r4, 0x5159E0E8; +CHECKREG r5, 0x737C02EA; +CHECKREG r6, 0x959E24EC; +CHECKREG r7, 0xB7C046EE; + +imm32 r0, 0x04457990; +imm32 r1, 0x14345678; +imm32 r2, 0x24456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x846789ab; +imm32 r5, 0x94789abc; +imm32 r6, 0xa489abcd; +imm32 r7, 0xb49abcde; +R0 = ( R0 + R3 ) << 1; +R1 = ( R1 + R3 ) << 1; +R2 = ( R2 + R3 ) << 1; +R4 = ( R4 + R3 ) << 1; +R5 = ( R5 + R3 ) << 1; +R6 = ( R6 + R3 ) << 1; +R7 = ( R7 + R3 ) << 1; +R3 = ( R3 + R3 ) << 1; +CHECKREG r0, 0x7137E454; +CHECKREG r1, 0x91159E24; +CHECKREG r2, 0xB137C046; +CHECKREG r3, 0xD159E268; +CHECKREG r4, 0x717C048A; +CHECKREG r5, 0x919E26AC; +CHECKREG r6, 0xB1C048CE; +CHECKREG r7, 0xD1E26AF0; + +imm32 r0, 0x03417990; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R0 = ( R0 + R4 ) << 1; +R1 = ( R1 + R4 ) << 1; +R2 = ( R2 + R4 ) << 1; +R3 = ( R3 + R4 ) << 1; +R5 = ( R5 + R4 ) << 1; +R6 = ( R6 + R4 ) << 1; +R7 = ( R7 + R4 ) << 1; +R4 = ( R4 + R4 ) << 1; +CHECKREG r0, 0x11460676; +CHECKREG r1, 0x2F25C046; +CHECKREG r2, 0x5145E268; +CHECKREG r3, 0x7366048A; +CHECKREG r4, 0x158626AC; +CHECKREG r5, 0x37A648CE; +CHECKREG r6, 0x59C66AF0; +CHECKREG r7, 0x7BE68D12; + +imm32 r0, 0x03457290; +imm32 r1, 0x12345278; +imm32 r2, 0x23456289; +imm32 r3, 0x3456729a; +imm32 r4, 0x856782ab; +imm32 r5, 0x967892bc; +imm32 r6, 0xa789a2cd; +imm32 r7, 0xb89ab2de; +R0 = ( R0 + R5 ) << 1; +R1 = ( R1 + R5 ) << 1; +R2 = ( R2 + R5 ) << 1; +R3 = ( R3 + R5 ) << 1; +R4 = ( R4 + R5 ) << 1; +R6 = ( R6 + R5 ) << 1; +R7 = ( R7 + R5 ) << 1; +R5 = ( R5 + R5 ) << 1; +CHECKREG r0, 0x337C0A98; +CHECKREG r1, 0x5159CA68; +CHECKREG r2, 0x737BEA8A; +CHECKREG r3, 0x959E0AAC; +CHECKREG r4, 0x37C02ACE; +CHECKREG r5, 0x59E24AF0; +CHECKREG r6, 0x7C046B12; +CHECKREG r7, 0x9E268B34; + +imm32 r0, 0x03457930; +imm32 r1, 0x12345638; +imm32 r2, 0x23456739; +imm32 r3, 0x3456783a; +imm32 r4, 0x8567893b; +imm32 r5, 0x96789a3c; +imm32 r6, 0xa789ab3d; +imm32 r7, 0xb89abc3e; +R0 = ( R0 + R6 ) << 1; +R1 = ( R1 + R6 ) << 1; +R2 = ( R2 + R6 ) << 1; +R3 = ( R3 + R6 ) << 1; +R4 = ( R4 + R6 ) << 1; +R5 = ( R5 + R6 ) << 1; +R7 = ( R7 + R6 ) << 1; +R6 = ( R6 + R6 ) << 1; +CHECKREG r0, 0x559E48DA; +CHECKREG r1, 0x737C02EA; +CHECKREG r2, 0x959E24EC; +CHECKREG r3, 0xB7C046EE; +CHECKREG r4, 0x59E268F0; +CHECKREG r5, 0x7C048AF2; +CHECKREG r6, 0x9E26ACF4; +CHECKREG r7, 0xC048CEF6; + +imm32 r0, 0x04457990; +imm32 r1, 0x14345678; +imm32 r2, 0x24456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x846789ab; +imm32 r5, 0x94789abc; +imm32 r6, 0xa489abcd; +imm32 r7, 0xb49abcde; +R0 = ( R0 + R7 ) << 1; +R1 = ( R1 + R7 ) << 1; +R2 = ( R2 + R7 ) << 1; +R3 = ( R3 + R7 ) << 1; +R4 = ( R4 + R7 ) << 1; +R5 = ( R5 + R7 ) << 1; +R6 = ( R6 + R7 ) << 1; +R7 = ( R7 + R7 ) << 1; +CHECKREG r0, 0x71C06CDC; +CHECKREG r1, 0x919E26AC; +CHECKREG r2, 0xB1C048CE; +CHECKREG r3, 0xD1E26AF0; +CHECKREG r4, 0x72048D12; +CHECKREG r5, 0x9226AF34; +CHECKREG r6, 0xB248D156; +CHECKREG r7, 0xD26AF378; +pass diff --git a/sim/testsuite/sim/bfin/c_alu2op_shadd_2.s b/sim/testsuite/sim/bfin/c_alu2op_shadd_2.s new file mode 100644 index 0000000..b9812f4 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_alu2op_shadd_2.s @@ -0,0 +1,209 @@ +//Original:/testcases/core/c_alu2op_shadd_2/c_alu2op_shadd_2.dsp +// Spec Reference: alu2op shadd 2 +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x03417990; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R1 = ( R1 + R0 ) << 2; +R2 = ( R2 + R0 ) << 2; +R3 = ( R3 + R0 ) << 2; +R4 = ( R4 + R0 ) << 2; +R5 = ( R5 + R0 ) << 2; +R6 = ( R6 + R0 ) << 2; +R7 = ( R7 + R0 ) << 2; +R0 = ( R0 + R0 ) << 2; +CHECKREG r0, 0x1A0BCC80; +CHECKREG r1, 0x55CB4020; +CHECKREG r2, 0x9A0B8464; +CHECKREG r3, 0xDE4BC8A8; +CHECKREG r4, 0x228C0CEC; +CHECKREG r5, 0x66CC5130; +CHECKREG r6, 0xAB0C9574; +CHECKREG r7, 0xEF4CD9B8; + +imm32 r0, 0x03457290; +imm32 r1, 0x12345278; +imm32 r2, 0x23456289; +imm32 r3, 0x3456729a; +imm32 r4, 0x856782ab; +imm32 r5, 0x967892bc; +imm32 r6, 0xa789a2cd; +imm32 r7, 0xb89ab2de; +R0 = ( R0 + R1 ) << 2; +R2 = ( R2 + R1 ) << 2; +R3 = ( R3 + R1 ) << 2; +R4 = ( R4 + R1 ) << 2; +R5 = ( R5 + R1 ) << 2; +R6 = ( R6 + R1 ) << 2; +R7 = ( R7 + R1 ) << 2; +R1 = ( R1 + R1 ) << 2; +CHECKREG r0, 0x55E71420; +CHECKREG r1, 0x91A293C0; +CHECKREG r2, 0xD5E6D404; +CHECKREG r3, 0x1A2B1448; +CHECKREG r4, 0x5E6F548C; +CHECKREG r5, 0xA2B394D0; +CHECKREG r6, 0xE6F7D514; +CHECKREG r7, 0x2B3C1558; + +imm32 r0, 0x03457930; +imm32 r1, 0x12345638; +imm32 r2, 0x23456739; +imm32 r3, 0x3456783a; +imm32 r4, 0x8567893b; +imm32 r5, 0x96789a3c; +imm32 r6, 0xa789ab3d; +imm32 r7, 0xb89abc3e; +R0 = ( R0 + R2 ) << 2; +R1 = ( R1 + R2 ) << 2; +R3 = ( R3 + R2 ) << 2; +R4 = ( R4 + R2 ) << 2; +R5 = ( R5 + R2 ) << 2; +R6 = ( R6 + R2 ) << 2; +R7 = ( R7 + R2 ) << 2; +R2 = ( R2 + R2 ) << 2; +CHECKREG r0, 0x9A2B81A4; +CHECKREG r1, 0xD5E6F5C4; +CHECKREG r2, 0x1A2B39C8; +CHECKREG r3, 0x5E6F7DCC; +CHECKREG r4, 0xA2B3C1D0; +CHECKREG r5, 0xE6F805D4; +CHECKREG r6, 0x2B3C49D8; +CHECKREG r7, 0x6F808DDC; + +imm32 r0, 0x04457990; +imm32 r1, 0x14345678; +imm32 r2, 0x24456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x846789ab; +imm32 r5, 0x94789abc; +imm32 r6, 0xa489abcd; +imm32 r7, 0xb49abcde; +R0 = ( R0 + R3 ) << 2; +R1 = ( R1 + R3 ) << 2; +R2 = ( R2 + R3 ) << 2; +R4 = ( R4 + R3 ) << 2; +R5 = ( R5 + R3 ) << 2; +R6 = ( R6 + R3 ) << 2; +R7 = ( R7 + R3 ) << 2; +R3 = ( R3 + R3 ) << 2; +CHECKREG r0, 0xE26FC8A8; +CHECKREG r1, 0x222B3C48; +CHECKREG r2, 0x626F808C; +CHECKREG r3, 0xA2B3C4D0; +CHECKREG r4, 0xE2F80914; +CHECKREG r5, 0x233C4D58; +CHECKREG r6, 0x6380919C; +CHECKREG r7, 0xA3C4D5E0; + +imm32 r0, 0x03417990; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R0 = ( R0 + R4 ) << 2; +R1 = ( R1 + R4 ) << 2; +R2 = ( R2 + R4 ) << 2; +R3 = ( R3 + R4 ) << 2; +R5 = ( R5 + R4 ) << 2; +R6 = ( R6 + R4 ) << 2; +R7 = ( R7 + R4 ) << 2; +R4 = ( R4 + R4 ) << 2; +CHECKREG r0, 0x228C0CEC; +CHECKREG r1, 0x5E4B808C; +CHECKREG r2, 0xA28BC4D0; +CHECKREG r3, 0xE6CC0914; +CHECKREG r4, 0x2B0C4D58; +CHECKREG r5, 0x6F4C919C; +CHECKREG r6, 0xB38CD5E0; +CHECKREG r7, 0xF7CD1A24; + +imm32 r0, 0x03457290; +imm32 r1, 0x12345278; +imm32 r2, 0x23456289; +imm32 r3, 0x3456729a; +imm32 r4, 0x856782ab; +imm32 r5, 0x967892bc; +imm32 r6, 0xa789a2cd; +imm32 r7, 0xb89ab2de; +R0 = ( R0 + R5 ) << 2; +R1 = ( R1 + R5 ) << 2; +R2 = ( R2 + R5 ) << 2; +R3 = ( R3 + R5 ) << 2; +R4 = ( R4 + R5 ) << 2; +R6 = ( R6 + R5 ) << 2; +R7 = ( R7 + R5 ) << 2; +R5 = ( R5 + R5 ) << 2; +CHECKREG r0, 0x66F81530; +CHECKREG r1, 0xA2B394D0; +CHECKREG r2, 0xE6F7D514; +CHECKREG r3, 0x2B3C1558; +CHECKREG r4, 0x6F80559C; +CHECKREG r5, 0xB3C495E0; +CHECKREG r6, 0xF808D624; +CHECKREG r7, 0x3C4D1668; + +imm32 r0, 0x03457930; +imm32 r1, 0x12345638; +imm32 r2, 0x23456739; +imm32 r3, 0x3456783a; +imm32 r4, 0x8567893b; +imm32 r5, 0x96789a3c; +imm32 r6, 0xa789ab3d; +imm32 r7, 0xb89abc3e; +R0 = ( R0 + R6 ) << 2; +R1 = ( R1 + R6 ) << 2; +R2 = ( R2 + R6 ) << 2; +R3 = ( R3 + R6 ) << 2; +R4 = ( R4 + R6 ) << 2; +R5 = ( R5 + R6 ) << 2; +R7 = ( R7 + R6 ) << 2; +R6 = ( R6 + R6 ) << 2; +CHECKREG r0, 0xAB3C91B4; +CHECKREG r1, 0xE6F805D4; +CHECKREG r2, 0x2B3C49D8; +CHECKREG r3, 0x6F808DDC; +CHECKREG r4, 0xB3C4D1E0; +CHECKREG r5, 0xF80915E4; +CHECKREG r6, 0x3C4D59E8; +CHECKREG r7, 0x80919DEC; + +imm32 r0, 0x04457990; +imm32 r1, 0x14345678; +imm32 r2, 0x24456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x846789ab; +imm32 r5, 0x94789abc; +imm32 r6, 0xa489abcd; +imm32 r7, 0xb49abcde; +R0 = ( R0 + R7 ) << 2; +R1 = ( R1 + R7 ) << 2; +R2 = ( R2 + R7 ) << 2; +R3 = ( R3 + R7 ) << 2; +R4 = ( R4 + R7 ) << 2; +R5 = ( R5 + R7 ) << 2; +R6 = ( R6 + R7 ) << 2; +R7 = ( R7 + R7 ) << 2; +CHECKREG r0, 0xE380D9B8; +CHECKREG r1, 0x233C4D58; +CHECKREG r2, 0x6380919C; +CHECKREG r3, 0xA3C4D5E0; +CHECKREG r4, 0xE4091A24; +CHECKREG r5, 0x244D5E68; +CHECKREG r6, 0x6491A2AC; +CHECKREG r7, 0xA4D5E6F0; +pass diff --git a/sim/testsuite/sim/bfin/c_br_preg_killed_ac.s b/sim/testsuite/sim/bfin/c_br_preg_killed_ac.s new file mode 100644 index 0000000..67a5bdc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_br_preg_killed_ac.s @@ -0,0 +1,82 @@ +//Original:/testcases/seq/c_br_preg_killed_ac/c_br_preg_killed_ac.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; + + P4 = 4; + P2 = 2; + loadsym P5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + IF !CC JUMP LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + JUMP ( PC + P4 ); //brf LABEL2; // (bp); + CC = ! CC; +LABEL2: + JUMP ( PC + P4 ); //brf LABEL3; // (bp); + R2 = - R2; // ALU2op killed +LABEL3: + JUMP ( PC + P4 ); //brf LABEL4; + R3 <<= 2; // LOGI2op killed +LABEL4: + JUMP ( PC + P4 ); //brf LABEL5; + R0 = R1 + R2; // COMP3op killed +LABEL5: + JUMP ( PC + P4 ); //brf LABEL6; + R4 += 3; // COMPI2opD killed +LABEL6: + JUMP ( PC + P4 ); //brf LABEL7; // (bp); + R5 = 25; // LDIMMHALF killed +LABEL7: + JUMP ( PC + P4 ); //brf LABEL8; + R6 = CC; // CC2REG killed +LABEL8: + JUMP ( PC + P4 ); //brf LABEL9; + JUMP ( PC + P2 ); //BAD1; // UJUMP killed +LABEL9: + JUMP ( PC + P4 ); //brf LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/sim/testsuite/sim/bfin/c_br_preg_killed_ex1.s b/sim/testsuite/sim/bfin/c_br_preg_killed_ex1.s new file mode 100644 index 0000000..7a18f53 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_br_preg_killed_ex1.s @@ -0,0 +1,85 @@ +//Original:/testcases/seq/c_br_preg_killed_ex1/c_br_preg_killed_ex1.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + P2 = 4; + loadsym p5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + IF !CC JUMP LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + JUMP ( PC + P2 ); //brf LABEL2; // (bp); + CC = ! CC; +LABEL2: + IF !CC JUMP LABEL3; // (bp); + R2 = - R2; // ALU2op killed +LABEL3: + IF !CC JUMP LABEL4; + R3 <<= 2; // LOGI2op killed +LABEL4: + IF !CC JUMP LABEL5; + R0 = R1 + R2; // COMP3op killed +LABEL5: + IF !CC JUMP LABEL6; + R4 += 3; // COMPI2opD killed +LABEL6: + IF !CC JUMP LABEL7; // (bp); + R5 = 25; // LDIMMHALF killed +LABEL7: + IF !CC JUMP LABEL8; + R6 = CC; // CC2REG killed +LABEL8: + IF !CC JUMP LABEL9; + JUMP.S BAD1; // UJUMP killed +LABEL9: + IF !CC JUMP LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/sim/testsuite/sim/bfin/c_br_preg_stall_ac.s b/sim/testsuite/sim/bfin/c_br_preg_stall_ac.s new file mode 100644 index 0000000..7ac29e6 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_br_preg_stall_ac.s @@ -0,0 +1,75 @@ +//Original:/testcases/seq/c_br_preg_stall_ac/c_br_preg_stall_ac.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + /* This test likes to assume the current [SP] is valid */ + SP += -12; + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST; + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + P1 = 4; + P2 = 6; + loadsym P5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + R0 = CC; + IF CC R1 = R0; + [ SP ] = P2; + P2 = [ SP ]; + JUMP ( PC + P2 ); //brf LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1' + CC = ! CC; +LABEL2: + JUMP ( PC + P1 ); //brf LABEL3; + JUMP ( PC + P2 ); //BAD1; // UJUMP killed +LABEL3: + JUMP ( PC + P1 ); //brf LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/sim/testsuite/sim/bfin/c_br_preg_stall_ex1.s b/sim/testsuite/sim/bfin/c_br_preg_stall_ex1.s new file mode 100644 index 0000000..5310edf --- /dev/null +++ b/sim/testsuite/sim/bfin/c_br_preg_stall_ex1.s @@ -0,0 +1,70 @@ +//Original:/testcases/seq/c_br_preg_stall_ex1/c_br_preg_stall_ex1.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + P1 = 4; + P2 = 6; + loadsym p5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + R0 = CC; + IF CC R1 = R0; + IF !CC JUMP LABEL1; + R0 = LC0; + R2 = R1 + R0; +LABEL1: + JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1' + CC = ! CC; +LABEL2: + JUMP ( PC + P1 ); //brf LABEL3; + JUMP ( PC + P2 ); //BAD1; // UJUMP killed +LABEL3: + JUMP ( PC + P1 ); //brf LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/sim/testsuite/sim/bfin/c_brcc_bp1.s b/sim/testsuite/sim/bfin/c_brcc_bp1.s new file mode 100644 index 0000000..012d1a5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_bp1.s @@ -0,0 +1,45 @@ +//Original:/testcases/core/c_brcc_bp1/c_brcc_bp1.dsp +// Spec Reference: brcc bp +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1; // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3; // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2; // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_brcc_bp2.s b/sim/testsuite/sim/bfin/c_brcc_bp2.s new file mode 100644 index 0000000..1fc7278 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_bp2.s @@ -0,0 +1,45 @@ +//Original:/testcases/core/c_brcc_bp2/c_brcc_bp2.dsp +// Spec Reference: brcc bp +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3; // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2; // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_brcc_bp3.s b/sim/testsuite/sim/bfin/c_brcc_bp3.s new file mode 100644 index 0000000..0a21994 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_bp3.s @@ -0,0 +1,47 @@ +//Original:/testcases/core/c_brcc_bp3/c_brcc_bp3.dsp +// Spec Reference: brcc bp +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3 (BP); // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2; // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_brcc_bp4.s b/sim/testsuite/sim/bfin/c_brcc_bp4.s new file mode 100644 index 0000000..39f64b1 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_bp4.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_bp4/c_brcc_bp4.dsp +// Spec Reference: brcc bp +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3 (BP); // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2 (BP); // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_brcc_brf_bp.s b/sim/testsuite/sim/bfin/c_brcc_brf_bp.s new file mode 100644 index 0000000..7ca29c5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_brf_bp.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_brf_bp/c_brcc_brf_bp.dsp +// Spec Reference: brcc brf bp +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: +ASTAT = R0; // clear cc + IF !CC JUMP good1 (BP); // branch on false (should branch) + CC = ! CC; // set cc=1 + R1 = 1; // if go here, error +good1: IF !CC JUMP good2 (BP); // branch on false (should branch) +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // + IF !CC JUMP bad2 (BP); // branch on false (should not branch) + CC = ! CC; + IF !CC JUMP good3 (BP); // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF !CC JUMP end; // branch on true (should branch) +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_brcc_brf_brt_bp.s b/sim/testsuite/sim/bfin/c_brcc_brf_brt_bp.s new file mode 100644 index 0000000..c9f2945 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_brf_brt_bp.s @@ -0,0 +1,47 @@ +//Original:/testcases/core/c_brcc_brf_brt_bp/c_brcc_brf_brt_bp.dsp +// Spec Reference: brcc brfbrt +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000444; +imm32 r5, 0x00000555; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + CC = R4 < R5; + IF CC JUMP good1 (BP); // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch) + CC = ! CC; + IF !CC JUMP good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF CC JUMP good3 (BP); // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF !CC JUMP bad2 (BP); // branch on true (should not branch) + IF CC JUMP end; // we're done +bad2: R0 = 8; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000444; +CHECKREG r5, 0x00000555; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_brcc_brf_brt_nbp.s b/sim/testsuite/sim/bfin/c_brcc_brf_brt_nbp.s new file mode 100644 index 0000000..32b3bd0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_brf_brt_nbp.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_brf_brt_nbp/c_brcc_brf_brt_nbp.dsp +// Spec Reference: brcc brf brt no bp +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1; // branch on true (should branch) + R1 = 1; // if go here, error +good1: IF !CC JUMP bad1; // branch on false (should not branch) + JUMP.S good2; // should branch here +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // clear cc=0 + IF !CC JUMP good3; // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP bad2; // branch on true (should not branch) + JUMP.S end; // we're done +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_brcc_brf_fbkwd.s b/sim/testsuite/sim/bfin/c_brcc_brf_fbkwd.s new file mode 100644 index 0000000..371238c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_brf_fbkwd.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_brf_fbkwd/c_brcc_brf_fbkwd.dsp +// Spec Reference: brcc brf forward/backward +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +ASTAT = R0; + +IF !CC JUMP SUBR; + R1.L = 0xeeee; + R2.L = 0x2222; + R3.L = 0x3333; +JBACK: + R4.L = 0x4444; + + + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00004444; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass + +//.code 0x448 +SUBR: + R1.L = 0x1111; +IF !CC JUMP JBACK; diff --git a/sim/testsuite/sim/bfin/c_brcc_brf_nbp.s b/sim/testsuite/sim/bfin/c_brcc_brf_nbp.s new file mode 100644 index 0000000..52eb0f3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_brf_nbp.s @@ -0,0 +1,45 @@ +//Original:/testcases/core/c_brcc_brf_nbp/c_brcc_brf_nbp.dsp +// Spec Reference: brcc brf no bp +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + IF !CC JUMP good1; // branch on false (should branch) + CC = ! CC; // set cc=1 + R1 = 1; // if go here, error +good1: IF !CC JUMP good2; // branch on false (should branch) +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // + IF !CC JUMP bad2; // branch on false (should not branch) + CC = ! CC; + IF !CC JUMP good3; // branch on false (should branch) + R3 = 3; // if go here, error +good3: IF !CC JUMP end; // branch on true (should branch) +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_brcc_brt_bp.s b/sim/testsuite/sim/bfin/c_brcc_brt_bp.s new file mode 100644 index 0000000..d3ad0fc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_brt_bp.s @@ -0,0 +1,46 @@ +//Original:/testcases/core/c_brcc_brt_bp/c_brcc_brt_bp.dsp +// Spec Reference: brcc brt bp +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1 (BP); // (should branch) + R1 = 1; // if go here, error +good1: IF CC JUMP good2 (BP); // (should branch) +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // + IF CC JUMP bad2 (BP); // (should not branch) + CC = ! CC; + IF CC JUMP good3 (BP); // (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP end (BP); // (should branch) +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_brcc_brt_nbp.s b/sim/testsuite/sim/bfin/c_brcc_brt_nbp.s new file mode 100644 index 0000000..a1c5e6b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_brt_nbp.s @@ -0,0 +1,45 @@ +//Original:/testcases/core/c_brcc_brt_nbp/c_brcc_brt_nbp.dsp +// Spec Reference: brcc brt no bp +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +begin: + ASTAT = R0; // clear cc + CC = ! CC; // set cc=1 + IF CC JUMP good1; // (should branch) + R1 = 1; // if go here, error +good1: IF CC JUMP good2; // (should branch) +bad1: R2 = 2; // if go here, error +good2: CC = ! CC; // + IF CC JUMP bad2; // (should not branch) + CC = ! CC; + IF CC JUMP good3; // (should branch) + R3 = 3; // if go here, error +good3: IF CC JUMP end; // (should branch) +bad2: R4 = 4; // if go here error + +end: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_brcc_kills_dhits.s b/sim/testsuite/sim/bfin/c_brcc_kills_dhits.s new file mode 100644 index 0000000..5224554 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_kills_dhits.s @@ -0,0 +1,136 @@ +//Original:/testcases/core/c_brcc_kills_dhits/c_brcc_kills_dhits.dsp +// Spec Reference: brcc kills data cache hits +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + loadsym P5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + IF !CC JUMP LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + IF !CC JUMP LABEL2; // (bp); + CC = ! CC; +LABEL2: + IF !CC JUMP LABEL3; // (bp); + R2 = - R2; // ALU2op killed +LABEL3: + IF !CC JUMP LABEL4; + R3 <<= 2; // LOGI2op killed +LABEL4: + IF !CC JUMP LABEL5; + R0 = R1 + R2; // COMP3op killed +LABEL5: + IF !CC JUMP LABEL6; + R4 += 3; // COMPI2opD killed +LABEL6: + IF !CC JUMP LABEL7; // (bp); + R5 = 25; // LDIMMHALF killed +LABEL7: + IF !CC JUMP LABEL8; + R6 = CC; // CC2REG killed +LABEL8: + IF !CC JUMP LABEL9; + JUMP.S BAD1; // UJUMP killed +LABEL9: + IF !CC JUMP LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + +LABEL10: + IF !CC JUMP LABEL11; + R1 = ( A1 += R4.L * R5.H ), A0 += R4.H * R5.L; +// DSP32MAC killed + +LABEL11: + IF !CC JUMP LABEL12; + R2 = R2 +|+ R3; // DSP32ALU killed + +LABEL12: + IF !CC JUMP LABEL13; + R3 = LSHIFT R2 BY R3.L (V); // dsp32shift killed + +LABEL13: + IF !CC JUMP LABEL14; + R4.H = R1.L << 6; // DSP32SHIFTIMM killed + +LABEL14: + IF !CC JUMP LABEL15; + P2 = P1; // REGMV PREG-PREG killed + +LABEL15: + IF !CC JUMP LABEL16; + R5 = P1; // REGMV Pr-to-Dr killed + +LABEL16: + IF !CC JUMP LABEL17; + ASTAT = R2; // REGMV Dr-to-sys killed + +LABEL17: + IF !CC JUMP LABEL18; + R6 = ASTAT; // REGMV sys-to-Dr killed + +LABEL18: + IF !CC JUMP LABEL19; + [ I0 ] = R2; // DSPLDST store killed + +LABEL19: + IF !CC JUMP end; + R7 = [ I0 ]; // DSPLDST load killed + +end: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/sim/testsuite/sim/bfin/c_brcc_kills_dmiss.s b/sim/testsuite/sim/bfin/c_brcc_kills_dmiss.s new file mode 100644 index 0000000..62bd7e1 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_brcc_kills_dmiss.s @@ -0,0 +1,137 @@ +//Original:/testcases/core/c_brcc_kills_dmiss/c_brcc_kills_dmiss.dsp +// Spec Reference: brcc kills data cache miss +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000001; + imm32 r2, 0x00000002; + imm32 r3, 0x00000003; + imm32 r4, 0x00000004; + imm32 r5, 0x00000005; + imm32 r6, 0x00000006; + imm32 r7, 0x00000007; + imm32 p1, 0x00000011; + imm32 p2, 0x00000012; +.ifndef BFIN_HOST + imm32 p3, 0x00000013; +.endif + imm32 p4, 0x00000014; + + loadsym P5, DATA0; + loadsym I0, DATA1; + +begin: + ASTAT = R0; // clear CC + IF !CC JUMP LABEL1; // (bp); + CC = R4 < R5; // CC FLAG killed + R1 = 21; +LABEL1: + IF !CC JUMP LABEL2; // (bp); + CC = ! CC; +LABEL2: + IF !CC JUMP LABEL3; // (bp); + R2 = - R2; // ALU2op killed +LABEL3: + IF !CC JUMP LABEL4; + R3 <<= 2; // LOGI2op killed +LABEL4: + IF !CC JUMP LABEL5; + R0 = R1 + R2; // COMP3op killed +LABEL5: + IF !CC JUMP LABEL6; + R4 += 3; // COMPI2opD killed +LABEL6: + IF !CC JUMP LABEL7; // (bp); + R5 = 25; // LDIMMHALF killed +LABEL7: + IF !CC JUMP LABEL8; + R6 = CC; // CC2REG killed +LABEL8: + IF !CC JUMP LABEL9; + JUMP.S BAD1; // UJUMP killed +LABEL9: + IF !CC JUMP LABELCHK1; +BAD1: + R7 = [ P5 ]; // LDST killed + +LABELCHK1: + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + +LABEL10: + IF !CC JUMP LABEL11; + R1 = ( A1 += R4.L * R5.H ), A0 += R4.H * R5.L; +// DSP32MAC killed + +LABEL11: + IF !CC JUMP LABEL12; + R2 = R2 +|+ R3; // DSP32ALU killed + +LABEL12: + IF !CC JUMP LABEL13; + R3 = LSHIFT R2 BY R3.L (V); // dsp32shift killed + +LABEL13: + IF !CC JUMP LABEL14; + R4.H = R1.L << 6; // DSP32SHIFTIMM killed + +LABEL14: + IF !CC JUMP LABEL15; + P2 = P1; // REGMV PREG-PREG killed + +LABEL15: + IF !CC JUMP LABEL16; + R5 = P1; // REGMV Pr-to-Dr killed + +LABEL16: + IF !CC JUMP LABEL17; + ASTAT = R2; // REGMV Dr-to-sys killed + +LABEL17: + IF !CC JUMP LABEL18; + R6 = ASTAT; // REGMV sys-to-Dr killed + +LABEL18: + IF !CC JUMP LABEL19; + [ I0 ] = R2; // DSPLDST store killed + +LABEL19: + IF !CC JUMP end; + R7 = [ I0 ]; // DSPLDST load killed + +end: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000002; + CHECKREG r3, 0x00000003; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0x00000005; + CHECKREG r6, 0x00000006; + CHECKREG r7, 0x00000007; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + + .data +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 diff --git a/sim/testsuite/sim/bfin/c_cactrl_iflush_pr.s b/sim/testsuite/sim/bfin/c_cactrl_iflush_pr.s new file mode 100644 index 0000000..5d85792 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cactrl_iflush_pr.s @@ -0,0 +1,102 @@ +//Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr/c_cactrl_iflush_pr.dsp +// Spec Reference: c_cactrl iflush_pr +# mach: bfin + +.include "testutils.inc" + start + +// initial values +//p1=0x448; +//imm32 p1, CODE_ADDR_1; + loadsym p1, SUBR1; +// set all regs + + imm32 r0, 0x13545abd; + imm32 r1, 0xadbcfec7; + imm32 r2, 0xa1245679; + imm32 r3, 0x00060007; + imm32 r4, 0xefbc4569; + imm32 r5, 0x1235000b; + imm32 r6, 0x000c000d; + imm32 r7, 0x678e000f; +// The result accumulated in A0 and A1, and stored to a reg half + R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; + R3.H = A1 , A0 = R7.H * R6.L (T); +// begin of iflush + IFLUSH [ P1 ]; // p1 = 0xf00 + R7 = 0; + ASTAT = R7; + IF !CC JUMP SUBR1; +JBACK: + R6 = 0; + +//r4 = (a1 = l*h) M, a0 = h*l (r3,r2); +//r5 a1 = l*h, = (a0 = h*l) (r1,r0) IS; + CHECKREG r2, 0xFFD15679; + CHECKREG r3, 0xFFD00007; + CHECKREG r4, 0x00074569; + CHECKREG r5, 0x12358000; + + pass + +//.code 0x448 +//.code CODE_ADDR_1 +SUBR1: + R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L; + A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2); + IF !CC JUMP JBACK; + NOP; NOP; NOP; NOP; NOP; + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F diff --git a/sim/testsuite/sim/bfin/c_cactrl_iflush_pr_pp.s b/sim/testsuite/sim/bfin/c_cactrl_iflush_pr_pp.s new file mode 100644 index 0000000..96fbdc9 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cactrl_iflush_pr_pp.s @@ -0,0 +1,100 @@ +//Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr_pp/c_cactrl_iflush_pr_pp.dsp +// Spec Reference: c_cactrl iflush_pr [p++] +# mach: bfin + +.include "testutils.inc" + start + + loadsym p2, SUBR1; +// set all regs + + imm32 r0, 0x13545abd; + imm32 r1, 0xadbcfec7; + imm32 r2, 0xa1245679; + imm32 r3, 0x00060007; + imm32 r4, 0xefbc4569; + imm32 r5, 0x1235000b; + imm32 r6, 0x000c000d; + imm32 r7, 0x678e000f; +// The result accumulated in A0 and A1, and stored to a reg half + R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; + R3.H = A1 , A0 = R7.H * R6.L (T); +// begin of iflush + IFLUSH [ P2 ++ ]; // p2 = 0x448 + R7 = 0; + ASTAT = R7; + IF !CC JUMP SUBR1; +JBACK: + R6 = 0; + +//r4 = (a1 = l*h) M, a0 = h*l (r3,r2); +//r5 a1 = l*h, = (a0 = h*l) (r1,r0) IS; + CHECKREG r2, 0xFFD15679; + CHECKREG r3, 0xFFD00007; + CHECKREG r4, 0x00074569; + CHECKREG r5, 0x12358000; +//CHECKREG p2, 0x00000468; + + pass + +//.code 0x448 +//.code CODE_ADDR_1 +SUBR1: + R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L; + A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2); + IF !CC JUMP JBACK; + NOP; NOP; NOP; NOP; NOP; + +// Pre-load memory witb known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F diff --git a/sim/testsuite/sim/bfin/c_calla_ljump.s b/sim/testsuite/sim/bfin/c_calla_ljump.s new file mode 100644 index 0000000..be1e94f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_calla_ljump.s @@ -0,0 +1,31 @@ +//Original:/testcases/core/c_calla_ljump/c_calla_ljump.dsp +// Spec Reference: progctrl calla ljump +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +JUMP.L SUBR; + +JBACK: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass + +SUBR: // should jump here + R1.L = 0x1111; + JUMP.L JBACK; + R2.L = 0x2222; // should not go here + JUMP.L JBACK; +RTS; diff --git a/sim/testsuite/sim/bfin/c_calla_subr.s b/sim/testsuite/sim/bfin/c_calla_subr.s new file mode 100644 index 0000000..8c651da --- /dev/null +++ b/sim/testsuite/sim/bfin/c_calla_subr.s @@ -0,0 +1,28 @@ +//Original:/testcases/core/c_calla_subr/c_calla_subr.dsp +// Spec Reference: progctrl calla subr +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +CALL SUBR; + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass + +SUBR: // should jump here + R1.L = 0x1111; + RTS; + R2.L = 0x2222; // should not go here + RTS; diff --git a/sim/testsuite/sim/bfin/c_cc2dreg.s b/sim/testsuite/sim/bfin/c_cc2dreg.s new file mode 100644 index 0000000..38aab85 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc2dreg.s @@ -0,0 +1,56 @@ +//Original:/testcases/core/c_cc2dreg/c_cc2dreg.dsp +// Spec Reference: cc2dreg +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00120000; +imm32 r2, 0x00000003; +imm32 r3, 0x00000004; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R0; + +CC = R1; +R1 = CC; +CC = R1; +CC = ! CC; +R2 = CC; +CC = R2; +CC = ! CC; +R3 = CC; +CC = R3; +CC = ! CC; +R4 = CC; +CC = R5; +R5 = CC; +CC = R6; +R6 = CC; +CC = ! CC; +R7 = CC; +R0 = CC; + + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + + + + +pass diff --git a/sim/testsuite/sim/bfin/c_cc2stat_cc_ac.S b/sim/testsuite/sim/bfin/c_cc2stat_cc_ac.S new file mode 100644 index 0000000..964f82a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc2stat_cc_ac.S @@ -0,0 +1,240 @@ +//Original:/testcases/core/c_cc2stat_cc_ac/c_cc2stat_cc_ac.dsp +// Spec Reference: cc2stat cc ac +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + imm32 r0, _UNSET; + imm32 r1, _UNSET; + imm32 r2, _UNSET; + imm32 r3, _UNSET; + imm32 r4, _UNSET; + imm32 r5, _UNSET; + imm32 r6, _UNSET; + imm32 r7, _UNSET; + +// test CC = AC 0-0, 0-1, 1-0, 1-1 + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + CC = AC0; // + R0 = CC; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + CC = AC0; // + R1 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + CC = AC0; // + R2 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + CC = AC0; // + R3 = CC; // + +// test cc |= AC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + CC |= AC0; // + R4 = CC; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + CC |= AC0; // + R5 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 0 + CC |= AC0; // + R6 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + CC |= AC0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _SET; + +// test CC &= AC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + CC &= AC0; // + R4 = CC; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + CC &= AC0; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + CC &= AC0; // + R6 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + CC &= AC0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _UNSET; + CHECKREG r7, _SET; + +// test CC ^= AC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + CC ^= AC0; // + R4 = CC; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + CC ^= AC0; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + CC ^= AC0; // + R6 = CC; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + CC ^= AC0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _UNSET; + +// test AC0 = CC 0-0, 0-1, 1-0, 1-1 + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + AC0 = CC; // + R0 = ASTAT; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + AC0 = CC; // + R1 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + AC0 = CC; // + R2 = ASTAT; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + AC0 = CC; // + R3 = ASTAT; // + +// test AC0 |= CC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + AC0 |= CC; // + R4 = ASTAT; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + AC0 |= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + AC0 |= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + AC0 |= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_AC0|_CC); + CHECKREG r3, (_CC|_AC0); + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0); + CHECKREG r6, (_AC0|_CC); + CHECKREG r7, (_CC|_AC0); + +// test AC0 &= CC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + AC0 &= CC; // + R4 = ASTAT; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + AC0 &= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + AC0 &= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + AC0 &= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AC0); + CHECKREG r3, (_CC|_AC0); + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _CC; + CHECKREG r7, (_CC|_AC0); + +// test AC0 ^= CC (0-0, 0-1, 1-0, 1-1) + imm32 R7, 0x00; + ASTAT = R7; // cc = 0, AC0 = 0 + AC0 ^= CC; // + R4 = ASTAT; // + + imm32 R7, _AC0; + ASTAT = R7; // cc = 0, AC0 = 1 + AC0 ^= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AC0 = 0 + AC0 ^= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AC0); + ASTAT = R7; // cc = 1, AC0 = 1 + AC0 ^= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AC0); + CHECKREG r3, (_CC|_AC0); + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0); + CHECKREG r6, (_CC|_AC0); + CHECKREG r7, _CC; + + pass diff --git a/sim/testsuite/sim/bfin/c_cc2stat_cc_an.s b/sim/testsuite/sim/bfin/c_cc2stat_cc_an.s new file mode 100644 index 0000000..d93024f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc2stat_cc_an.s @@ -0,0 +1,243 @@ +//Original:/testcases/core/c_cc2stat_cc_an/c_cc2stat_cc_an.dsp +// Spec Reference: cc2stat cc an +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// test CC = AN 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +CC = AN; // +R0 = CC; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +CC = AN; // +R1 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +CC = AN; // +R2 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +CC = AN; // +R3 = CC; // + +// test cc |= AN (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +CC |= AN; // +R4 = CC; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +CC |= AN; // +R5 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 0 +CC |= AN; // +R6 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +CC |= AN; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +// test CC &= AN (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +CC &= AN; // +R4 = CC; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +CC &= AN; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +CC &= AN; // +R6 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +CC &= AN; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +// test CC ^= AN (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +CC ^= AN; // +R4 = CC; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +CC ^= AN; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +CC ^= AN; // +R6 = CC; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +CC ^= AN; // +R7 = CC; // + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +// test AN = CC 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +AN = CC; // +R0 = ASTAT; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +AN = CC; // +R1 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +AN = CC; // +R2 = ASTAT; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +AN = CC; // +R3 = ASTAT; // + +// test AN |= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +AN |= CC; // +R4 = ASTAT; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +AN |= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +AN |= CC; // +R6 = ASTAT; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +AN |= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// test AN &= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +AN &= CC; // +R4 = ASTAT; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +AN &= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +AN &= CC; // +R6 = ASTAT; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +AN &= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000022; + +// test AN ^= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AN = 0 +AN ^= CC; // +R4 = ASTAT; // + +R7 = 0x02; +ASTAT = R7; // cc = 0, AN = 1 +AN ^= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AN = 0 +AN ^= CC; // +R6 = ASTAT; // + +R7 = 0x22; +ASTAT = R7; // cc = 1, AN = 1 +AN ^= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000020; + + +pass diff --git a/sim/testsuite/sim/bfin/c_cc2stat_cc_aq.s b/sim/testsuite/sim/bfin/c_cc2stat_cc_aq.s new file mode 100644 index 0000000..e8b877e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc2stat_cc_aq.s @@ -0,0 +1,243 @@ +//Original:/testcases/core/c_cc2stat_cc_aq/c_cc2stat_cc_aq.dsp +// Spec Reference: cc2stat cc aq +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// test CC = AQ 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +CC = AQ; // +R0 = CC; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +CC = AQ; // +R1 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +CC = AQ; // +R2 = CC; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +CC = AQ; // +R3 = CC; // + +// test cc |= AQ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +CC |= AQ; // +R4 = CC; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +CC |= AQ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +CC |= AQ; // +R6 = CC; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +CC |= AQ; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +// test CC &= AQ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +CC &= AQ; // +R4 = CC; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +CC &= AQ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +CC &= AQ; // +R6 = CC; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +CC &= AQ; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +// test CC ^= AQ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +CC ^= AQ; // +R4 = CC; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +CC ^= AQ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +CC ^= AQ; // +R6 = CC; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +CC ^= AQ; // +R7 = CC; // + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +// test AQ = CC 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +AQ = CC; // +R0 = ASTAT; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +AQ = CC; // +R1 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +AQ = CC; // +R2 = ASTAT; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +AQ = CC; // +R3 = ASTAT; // + +// test AQ |= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +AQ |= CC; // +R4 = ASTAT; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +AQ |= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +AQ |= CC; // +R6 = ASTAT; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +AQ |= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000060; +CHECKREG r3, 0x00000060; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000040; +CHECKREG r6, 0x00000060; +CHECKREG r7, 0x00000060; + +// test AQ &= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +AQ &= CC; // +R4 = ASTAT; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +AQ &= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +AQ &= CC; // +R6 = ASTAT; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +AQ &= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000060; +CHECKREG r3, 0x00000060; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000060; + +// test AQ ^= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AQ = 0 +AQ ^= CC; // +R4 = ASTAT; // + +R7 = 0x40 (X); +ASTAT = R7; // cc = 0, AQ = 1 +AQ ^= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AQ = 0 +AQ ^= CC; // +R6 = ASTAT; // + +R7 = 0x60 (X); +ASTAT = R7; // cc = 1, AQ = 1 +AQ ^= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000060; +CHECKREG r3, 0x00000060; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000040; +CHECKREG r6, 0x00000060; +CHECKREG r7, 0x00000020; + + +pass diff --git a/sim/testsuite/sim/bfin/c_cc2stat_cc_av0.S b/sim/testsuite/sim/bfin/c_cc2stat_cc_av0.S new file mode 100644 index 0000000..c600902 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc2stat_cc_av0.S @@ -0,0 +1,241 @@ +//Original:/testcases/core/c_cc2stat_cc_av0/c_cc2stat_cc_av0.dsp +// Spec Reference: cc2stat cc av0 +# mach: bfin + +#include "test.h" + .include "testutils.inc" + + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000000; + imm32 r2, 0x00000000; + imm32 r3, 0x00000000; + imm32 r4, 0x00000000; + imm32 r5, 0x00000000; + imm32 r6, 0x00000000; + imm32 r7, 0x00000000; + +// test CC = AV0 0-0, 0-1, 1-0, 1-1 + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + CC = AV0; // + R0 = CC; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + CC = AV0; // + R1 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + CC = AV0; // + R2 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + CC = AV0; // + R3 = CC; // + +// test cc |= AV0 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + CC |= AV0; // + R4 = CC; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + CC |= AV0; // + R5 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 0 + CC |= AV0; // + R6 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + CC |= AV0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _SET; + +// test CC &= AV0 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + CC &= AV0; // + R4 = CC; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + CC &= AV0; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + CC &= AV0; // + R6 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + CC &= AV0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _UNSET; + CHECKREG r7, _SET; + +// test CC ^= AV0 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + CC ^= AV0; // + R4 = CC; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + CC ^= AV0; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + CC ^= AV0; // + R6 = CC; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + CC ^= AV0; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _UNSET; + +// test AV0 = CC 0-0, 0-1, 1-0, 1-1 + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + AV0 = CC; // + R0 = ASTAT; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + AV0 = CC; // + R1 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + AV0 = CC; // + R2 = ASTAT; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + AV0 = CC; // + R3 = ASTAT; // + +// test AV0 |= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + AV0 |= CC; // + R4 = ASTAT; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + AV0 |= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + AV0 |= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + AV0 |= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV0); + CHECKREG r3, (_CC|_AV0); + CHECKREG r4, _UNSET; + CHECKREG r5, _AV0; + CHECKREG r6, (_CC|_AV0); + CHECKREG r7, (_CC|_AV0); + +// test AV0 &= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + AV0 &= CC; // + R4 = ASTAT; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + AV0 &= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + AV0 &= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + AV0 &= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV0); + CHECKREG r3, (_CC|_AV0); + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, (_CC); + CHECKREG r7, (_CC|_AV0); + +// test AV0 ^= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV0 = 0 + AV0 ^= CC; // + R4 = ASTAT; // + + imm32 R7, _AV0; + ASTAT = R7; // cc = 0, AV0 = 1 + AV0 ^= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV0 = 0 + AV0 ^= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV0); + ASTAT = R7; // cc = 1, AV0 = 1 + AV0 ^= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV0); + CHECKREG r3, (_CC|_AV0); + CHECKREG r4, _UNSET; + CHECKREG r5, _AV0; + CHECKREG r6, (_CC|_AV0); + CHECKREG r7, _CC; + + pass diff --git a/sim/testsuite/sim/bfin/c_cc2stat_cc_av1.S b/sim/testsuite/sim/bfin/c_cc2stat_cc_av1.S new file mode 100644 index 0000000..2855085 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc2stat_cc_av1.S @@ -0,0 +1,240 @@ +//Original:/testcases/core/c_cc2stat_cc_av1/c_cc2stat_cc_av1.dsp +// Spec Reference: cc2stat cc av1 +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + imm32 r0, 0x00000000; + imm32 r1, 0x00000000; + imm32 r2, 0x00000000; + imm32 r3, 0x00000000; + imm32 r4, 0x00000000; + imm32 r5, 0x00000000; + imm32 r6, 0x00000000; + imm32 r7, 0x00000000; + +// test CC = AV1 0-0, 0-1, 1-0, 1-1 + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + CC = AV1; // + R0 = CC; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + CC = AV1; // + R1 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + CC = AV1; // + R2 = CC; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + CC = AV1; // + R3 = CC; // + +// test cc |= AV1 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + CC |= AV1; // + R4 = CC; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + CC |= AV1; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + CC |= AV1; // + R6 = CC; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + CC |= AV1; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _SET; + +// test CC &= AV1 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + CC &= AV1; // + R4 = CC; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + CC &= AV1; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + CC &= AV1; // + R6 = CC; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + CC &= AV1; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _UNSET; + CHECKREG r7, _SET; + +// test CC ^= AV1 (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + CC ^= AV1; // + R4 = CC; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + CC ^= AV1; // + R5 = CC; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + CC ^= AV1; // + R6 = CC; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + CC ^= AV1; // + R7 = CC; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _SET; + CHECKREG r2, _UNSET; + CHECKREG r3, _SET; + CHECKREG r4, _UNSET; + CHECKREG r5, _SET; + CHECKREG r6, _SET; + CHECKREG r7, _UNSET; + +// test AV1 = CC 0-0, 0-1, 1-0, 1-1 + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + AV1 = CC; // + R0 = ASTAT; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + AV1 = CC; // + R1 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + AV1 = CC; // + R2 = ASTAT; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + AV1 = CC; // + R3 = ASTAT; // + +// test AV1 |= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + AV1 |= CC; // + R4 = ASTAT; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + AV1 |= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + AV1 |= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + AV1 |= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV1); + CHECKREG r3, (_CC|_AV1); + CHECKREG r4, _UNSET; + CHECKREG r5, _AV1; + CHECKREG r6, (_CC|_AV1); + CHECKREG r7, (_CC|_AV1); + +// test AV1 &= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + AV1 &= CC; // + R4 = ASTAT; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + AV1 &= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + AV1 &= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + AV1 &= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV1); + CHECKREG r3, (_CC|_AV1); + CHECKREG r4, _UNSET; + CHECKREG r5, _UNSET; + CHECKREG r6, _CC; + CHECKREG r7, (_CC|_AV1); + +// test AV1 ^= CC (0-0, 0-1, 1-0, 1-1) + R7 = 0x00; + ASTAT = R7; // cc = 0, AV1 = 0 + AV1 ^= CC; // + R4 = ASTAT; // + + imm32 R7, _AV1; + ASTAT = R7; // cc = 0, AV1 = 1 + AV1 ^= CC; // + R5 = ASTAT; // + + imm32 R7, _CC; + ASTAT = R7; // cc = 1, AV1 = 0 + AV1 ^= CC; // + R6 = ASTAT; // + + imm32 R7, (_CC|_AV1); + ASTAT = R7; // cc = 1, AV1 = 1 + AV1 ^= CC; // + R7 = ASTAT; // + + CHECKREG r0, _UNSET; + CHECKREG r1, _UNSET; + CHECKREG r2, (_CC|_AV1); + CHECKREG r3, (_CC|_AV1); + CHECKREG r4, _UNSET; + CHECKREG r5, _AV1; + CHECKREG r6, (_CC|_AV1); + CHECKREG r7, _CC; + + pass diff --git a/sim/testsuite/sim/bfin/c_cc2stat_cc_az.s b/sim/testsuite/sim/bfin/c_cc2stat_cc_az.s new file mode 100644 index 0000000..0d8b05b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc2stat_cc_az.s @@ -0,0 +1,243 @@ +//Original:/testcases/core/c_cc2stat_cc_az/c_cc2stat_cc_az.dsp +// Spec Reference: cc2stat cc az +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// test CC = AZ 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +CC = AZ; // +R0 = CC; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +CC = AZ; // +R1 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +CC = AZ; // +R2 = CC; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +CC = AZ; // +R3 = CC; // + +// test cc |= AZ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +CC |= AZ; // +R4 = CC; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +CC |= AZ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +CC |= AZ; // +R6 = CC; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +CC |= AZ; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +// test CC &= AZ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +CC &= AZ; // +R4 = CC; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +CC &= AZ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +CC &= AZ; // +R6 = CC; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +CC &= AZ; // +R7 = CC; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +// test CC ^= AZ (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +CC ^= AZ; // +R4 = CC; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +CC ^= AZ; // +R5 = CC; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +CC ^= AZ; // +R6 = CC; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +CC ^= AZ; // +R7 = CC; // + + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +// test AZ = CC 0-0, 0-1, 1-0, 1-1 +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +AZ = CC; // +R0 = ASTAT; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +AZ = CC; // +R1 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +AZ = CC; // +R2 = ASTAT; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +AZ = CC; // +R3 = ASTAT; // + +// test AZ |= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +AZ |= CC; // +R4 = ASTAT; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +AZ |= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +AZ |= CC; // +R6 = ASTAT; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +AZ |= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000021; +CHECKREG r3, 0x00000021; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000021; +CHECKREG r7, 0x00000021; + +// test AZ &= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +AZ &= CC; // +R4 = ASTAT; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +AZ &= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +AZ &= CC; // +R6 = ASTAT; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +AZ &= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000021; +CHECKREG r3, 0x00000021; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000021; + +// test AZ ^= CC (0-0, 0-1, 1-0, 1-1) +R7 = 0x00; +ASTAT = R7; // cc = 0, AZ = 0 +AZ ^= CC; // +R4 = ASTAT; // + +R7 = 0x01; +ASTAT = R7; // cc = 0, AZ = 1 +AZ ^= CC; // +R5 = ASTAT; // + +R7 = 0x20; +ASTAT = R7; // cc = 1, AZ = 0 +AZ ^= CC; // +R6 = ASTAT; // + +R7 = 0x21; +ASTAT = R7; // cc = 1, AZ = 1 +AZ ^= CC; // +R7 = ASTAT; // + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000021; +CHECKREG r3, 0x00000021; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000021; +CHECKREG r7, 0x00000020; + + +pass diff --git a/sim/testsuite/sim/bfin/c_cc_flag_ccmv_depend.S b/sim/testsuite/sim/bfin/c_cc_flag_ccmv_depend.S new file mode 100644 index 0000000..807a753 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc_flag_ccmv_depend.S @@ -0,0 +1,80 @@ +//Original:/proj/frio/dv/testcases/core/c_cc_flag_ccmv_depend/c_cc_flag_ccmv_depend.dsp +// Spec Reference: ccflag followed by ccmv (# stalls) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + imm32 r0, 0xa08d2311; + imm32 r1, 0x10120040; + imm32 r2, 0x62b61557; + imm32 r3, 0x07300007; + imm32 r4, 0x00740088; + imm32 r5, 0x609950aa; + imm32 r6, 0x20bb06cc; + imm32 r7, 0xd90e108f; + + imm32 p1, 0x1401101f; + imm32 p2, 0x3204108e; + imm32 fp, 0xd93f1084; + imm32 p4, 0xeb04106f; + imm32 p5, 0xa90e5089; + + CC = R7; // cc2dreg + IF CC R0 = R3; // ccmov + R6 = R0 + R4; + + CC = ! CC; // cc2dreg + IF CC R1 = P1; // ccmov + + CC = R5 < R1; // ccflag + R1 = ASTAT; + IF !CC R2 = R5; // ccmov + + CC = R2 == R3; // ccflag + IF CC P1 = R4; // ccmov + + CC = ! CC; + CC = R7 < R5; + IF CC P2 = P5; // ccmov + + CC = P5 == 3; + IF CC FP = R2; // ccmov + + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair + + CC = A0 == A1; + IF !CC R3 = R6; // ccmov + R7 = R3 + R2; + + A0 += A1 (W32); // dsp32alu a0 + a1 + CC = A0 < A1; + IF CC R4 = P4; // ccmov + R6 = R4; + + R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac + CC = A0 <= A1; + IF CC R5 = P5; // ccmov + + A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac + CC = A0 <= A1; + IF CC P5 = R6; // ccmov + + CHECKREG r0, 0x07300007; + CHECKREG r1, (_AC0|_AC0_COPY); + CHECKREG r2, 0x00766960; + CHECKREG r3, 0x07A4008F; + CHECKREG r4, 0xEB04106F; + CHECKREG r5, 0xA90E5089; + CHECKREG r6, 0xEB04106F; + CHECKREG r7, 0x075D69EF; + CHECKREG p1, 0x1401101F; + CHECKREG p2, 0xA90E5089; + CHECKREG fp, 0xD93F1084; + CHECKREG p4, 0xEB04106F; + CHECKREG p5, 0xA90E5089; + + pass diff --git a/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft.s b/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft.s new file mode 100644 index 0000000..a36f31a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft.s @@ -0,0 +1,87 @@ +//Original:/testcases/core/c_cc_flagdreg_mvbrsft/c_cc_flagdreg_mvbrsft.dsp +// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xa08d2311; +imm32 r1, 0x10120040; +imm32 r2, 0x62b61557; +imm32 r3, 0x07300007; +imm32 r4, 0x00740088; +imm32 r5, 0x609950aa; +imm32 r6, 0x20bb06cc; +imm32 r7, 0xd90e108f; + + ASTAT = R0; + + CC = R1; // cc2dreg + IF CC R1 = R3; // ccmov + CC = ! CC; // cc2dreg + IF CC R3 = R2; // ccmov + CC = R0 < R1; // ccflag + IF CC R4 = R5; // ccmov + CC = R2 == R3; + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + IF !CC JUMP LABEL1; // branch on + CC = ! CC; + IF !CC JUMP LABEL2 (BP); // branch on +LABEL1: + R6 = R0 + R2; + JUMP.S END; +LABEL2: + R7 = R5 - R3; + CC = R0 < R1; // ccflag + IF CC JUMP END (BP); // branch on + R4 = R5 + R7; + +END: + +CHECKREG r0, 0xA08D2311; +CHECKREG r1, 0x07300007; +CHECKREG r2, 0x62B61557; +CHECKREG r3, 0x07300007; +CHECKREG r4, 0x609950AA; +CHECKREG r5, 0x609950AA; +CHECKREG r6, 0x20BB06CC; +CHECKREG r7, 0x596950A3; + +imm32 r0, 0x408d2711; +imm32 r1, 0x15124040; +imm32 r2, 0x62661557; +imm32 r3, 0x073b0007; +imm32 r4, 0x01f49088; +imm32 r5, 0x6e2959aa; +imm32 r6, 0xa0b506cc; +imm32 r7, 0x00000002; + + + CC = R1; // cc2dreg + R2 = ROT R2 BY 1; // dsp32shiftim_rot + CC = ! CC; // cc2dreg + R3 = ROT R0 BY -3; // dsp32shiftim_rot + CC = R0 < R1; // ccflag + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = R2 == R3; + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + R7 = ROT R6 BY R7.L; + +CHECKREG r0, 0x408D2711; +CHECKREG r1, 0x15124040; +CHECKREG r2, 0xC4CC2AAF; +CHECKREG r3, 0x6811A4E2; +CHECKREG r4, 0x01F49088; +CHECKREG r5, 0x6E2959AA; +CHECKREG r6, 0x3E921100; +CHECKREG r7, 0xFA484402; + + + + +pass diff --git a/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_s1.s b/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_s1.s new file mode 100644 index 0000000..24505c2 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_s1.s @@ -0,0 +1,99 @@ +//Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_s1/c_cc_flagdreg_mvbrsft_s1.dsp +// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft) +# mach: bfin + +.include "testutils.inc" + start + + INIT_P_REGS 0; + + imm32 r0, 0xa08d2311; + imm32 r1, 0x10120040; + imm32 r2, 0x62b61557; + imm32 r3, 0x07300007; + imm32 r4, 0x00740088; + imm32 r5, 0x609950aa; + imm32 r6, 0x20bb06cc; + imm32 r7, 0xd90e108f; + + ASTAT = R0; + + CC = R1; // cc2dreg + R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac + IF CC R1 = R3; // ccmov + CC = ! CC; // cc2dreg + R4.H = R1.L + R0.L (S); // dsp32alu + IF CC R3 = R2; // ccmov + CC = R0 < R1; // ccflag + R4.L = R5.L << 1; // dsp32shiftimm + IF CC R4 = R5; // ccmov + CC = R2 == R3; // ccflag + R7 = R1.L * R4.L, R6 = R1.H * R4.H; // dsp32mult + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac + IF !CC JUMP LABEL1; // branch on + CC = ! CC; // cc2dreg + P1.L = 0x3000; // ldimmhalf + IF !CC JUMP LABEL2 (BP); // branch +LABEL1: + R6 = R6 + R2; + JUMP.S END; +LABEL2: + R7 = R5 - R7; + CC = R0 < R1; // ccflag + P2 = A0.w; + IF CC JUMP END (BP); // branch + P3 = A1.w; + R5 = R5 + R7; + +END: + + CHECKREG r0, 0xA08D2311; + CHECKREG r1, 0x07300007; + CHECKREG r2, 0x00011557; + CHECKREG r3, 0x07300007; + CHECKREG r4, 0x609950AA; + CHECKREG r5, 0x609950AA; + CHECKREG r6, 0x056C9760; + CHECKREG r7, 0x6094E75E; + CHECKREG p1, 0x00003000; + CHECKREG p2, 0x01382894; + CHECKREG p3, 0x00000000; + + imm32 r0, 0x408d2711; + imm32 r1, 0x15124040; + imm32 r2, 0x62661557; + imm32 r3, 0x073b0007; + imm32 r4, 0x01f49088; + imm32 r5, 0x6e2959aa; + imm32 r6, 0xa0b506cc; + imm32 r7, 0x00000002; + + CC = R1; // cc2dreg + + R2 = ROT R2 BY 1; // dsp32shiftim_rot + CC = ! CC; // cc2dreg + R3 >>= R7; // alu2op sft + R3 = ROT R0 BY -3; // dsp32shiftim_rot + CC = R0 < R1; // ccflag + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = R2 == R3; // ccflag + P1 = R1; // regmv + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft + R7 = ROT R6 BY R7.L; // dsp32shiftim_rot + + CHECKREG r0, 0x408D2711; + CHECKREG r1, 0x2ACFF368; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0xFFFC8440; + CHECKREG r4, 0x01F49088; + CHECKREG r5, 0x6E2959AA; + CHECKREG r6, 0x15BD33A8; + CHECKREG r7, 0x56F4CEA2; + CHECKREG p1, 0x15124040; + + pass diff --git a/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_sn.s b/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_sn.s new file mode 100644 index 0000000..8002cbd --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_sn.s @@ -0,0 +1,118 @@ +//Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_sn/c_cc_flagdreg_mvbrsft_sn.dsp +// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft) +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0xa08d2311; + imm32 r1, 0x10120040; + imm32 r2, 0x62b61557; + imm32 r3, 0x07300007; + imm32 r4, 0x00740088; + imm32 r5, 0x609950aa; + imm32 r6, 0x20bb06cc; + imm32 r7, 0xd90e108f; + + imm32 p1, 0x1401101f; + imm32 p2, 0x3204108e; + imm32 p3, 0xd93f1084; + imm32 p4, 0xeb04106f; + imm32 p5, 0xa90e5089; + + ASTAT = R0; + + CC = R1; // cc2dreg + R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac + I0 = P1; // regmv + IF CC R1 = R3; // ccmov + CC = ! CC; // cc2dreg + R4.H = R1.L + R0.L (S); // dsp32alu + M0 = P2; // regmv + IF CC R3 = R2; // ccmov + CC = R0 < R1; // ccflag + R4.L = R5.L << 1; // dsp32shiftimm + I0 += M0; // dagmodim + R2 = R0 + R2; // comp3op dr plus dr + IF CC R4 = R5; // ccmov + CC = R2 == R3; // ccflag + R7 = R1.L * R4.L, R6 = R1.H * R4.H; // dsp32mult + R5 = R0 + R2; // comp3op dr plus dr + BITCLR( R6 , 1 ); + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac + IF !CC JUMP LABEL1; // branch on + CC = ! CC; // cc2dreg + P1.L = 0x3000; // ldimmhalf + A0 += A1 (W32); // dsp32alu a0 + a1 + IF !CC JUMP LABEL2 (BP); // branch +LABEL1: + R6 = R6 + R2; + JUMP.S END; +LABEL2: + R7 = R5 - R7; + CC = R0 < R1; // ccflag + P2 = A0.w; + IF CC JUMP END (BP); // branch + P3 = A1.w; + R5 = R5 + R7; + +END: + + CHECKREG r0, 0xA08D2311; + CHECKREG r1, 0x07300007; + CHECKREG r2, 0xA08E3868; + CHECKREG r3, 0x07300007; + CHECKREG r4, 0x609950AA; + CHECKREG r5, 0x411B5B79; + CHECKREG r6, 0x056C9760; + CHECKREG r7, 0x4116F22D; + CHECKREG p1, 0x14013000; + CHECKREG p2, 0x033352A4; + CHECKREG p3, 0xD93F1084; + + imm32 r0, 0x408d2711; + imm32 r1, 0x15124040; + imm32 r2, 0x62661557; + imm32 r3, 0x073b0007; + imm32 r4, 0x01f49088; + imm32 r5, 0x6e2959aa; + imm32 r6, 0xa0b506cc; + imm32 r7, 0x00000002; + + CC = R1; // cc2dreg + P1 = -15; // compi2opp_pr_eq_i7 + R2 = ROT R2 BY 1; // dsp32shiftim_rot + CC = ! CC; // cc2dreg + R3 >>= R7; // alu2op sft + R4 = ROT R0 BY -3; // dsp32shiftim_rot + CC = R0 < R1; // ccflag + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair + R5 = R0 + R2; // comp3op dr plus dr + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = R2 == R3; // ccflag + P2 = R1; // regmv + R4.H = R1.L + R3.H (S); // dsp32alu + I0 = P1; // regmv + IF CC R4 = R5; // ccmov + CC = R0; // cc2dreg + R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft + I0 += 2; + P3 = I0; + R3.L = R5.L << 1; // dsp32shiftimm + R7 = ROT R6 BY R7.L; // dsp32shiftim_rot + + CHECKREG r0, 0x408D2711; + CHECKREG r1, 0x2ACFF368; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0xFFFD4E22; + CHECKREG r4, 0x403DA4E2; + CHECKREG r5, 0x408D2711; + CHECKREG r6, 0x15BD33A8; + CHECKREG r7, 0x56F4CEA2; + CHECKREG p1, 0xFFFFFFF1; + CHECKREG p2, 0x15124040; + CHECKREG p3, 0xFFFFFFF3; + + pass diff --git a/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft.s b/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft.s new file mode 100644 index 0000000..7ad1823 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft.s @@ -0,0 +1,83 @@ +//Original:/testcases/core/c_cc_regmvlogi_mvbrsft/c_cc_regmvlogi_mvbrsft.dsp +// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000020; // cc=1 +imm32 r1, 0x00000000; // cc=0 +imm32 r2, 0x62b61557; +imm32 r3, 0x07300007; +imm32 r4, 0x00740088; +imm32 r5, 0x609950aa; +imm32 r6, 0x20bb06cc; +imm32 r7, 0xd90e108f; + + + ASTAT = R0; // cc=1 REGMV + IF CC R1 = R3; // ccmov + ASTAT = R1; // cc=0 REGMV + IF CC R3 = R2; // ccmv + CC = R0 < R1; // ccflag + IF CC R4 = R5; // ccmv + CC = ! BITTST( R0 , 4 ); // cc = 0 + IF CC R4 = R5; // ccmv + CC = BITTST ( R1 , 4 ); // cc = 0 + IF !CC JUMP LABEL1; // branch + CC = ! CC; + IF !CC JUMP LABEL2 (BP); // branch +LABEL1: + R6 = R0 + R2; + JUMP.S END; +LABEL2: + R7 = R5 - R3; + CC = R0 < R1; // ccflag + IF CC JUMP END (BP); // branch on + R4 = R5 + R7; + +END: + +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x07300007; +CHECKREG r2, 0x62B61557; +CHECKREG r3, 0x07300007; +CHECKREG r4, 0x609950AA; +CHECKREG r5, 0x609950AA; +CHECKREG r6, 0x62B61577; +CHECKREG r7, 0xD90E108F; + +imm32 r0, 0x00000020; +imm32 r1, 0x00000000; +imm32 r2, 0x62661557; +imm32 r3, 0x073b0007; +imm32 r4, 0x01f49088; +imm32 r5, 0x6e2959aa; +imm32 r6, 0xa0b506cc; +imm32 r7, 0x00000002; + + + ASTAT = R0; // cc=1 REGMV + R2 = ROT R2 BY 1; // dsp32shiftim_rot + ASTAT = R1; // cc=0 REGMV + R3 = ROT R3 BY 1; // dsp32shiftim_rot + CC = ! BITTST( R0 , 4 ); // cc = 0 + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = BITTST ( R1 , 4 ); // cc = 0 + IF CC R4 = R5; // ccmov + CC = BITTST ( R0 , 4 ); // cc = 1 + R7 = ROT R6 BY R7.L; + +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xC4CC2AAF; +CHECKREG r3, 0x0E76000E; +CHECKREG r4, 0x01F49088; +CHECKREG r5, 0x6E2959AA; +CHECKREG r6, 0x3E921110; +CHECKREG r7, 0xFA484440; + +pass diff --git a/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_s1.s b/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_s1.s new file mode 100644 index 0000000..f0306c9 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_s1.s @@ -0,0 +1,98 @@ +//Original:/testcases/core/c_cc_regmvlogi_mvbrsft_s1/c_cc_regmvlogi_mvbrsft_s1.dsp +// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft) +# mach: bfin + +.include "testutils.inc" + start + + +A0 = 0; +A1 = 0; + +imm32 r0, 0x00000020; // cc=1 +imm32 r1, 0x00000000; // cc=0 +imm32 r2, 0x62b61557; +imm32 r3, 0x07300007; +imm32 r4, 0x00740088; +imm32 r5, 0x609950aa; +imm32 r6, 0x20bb06cc; +imm32 r7, 0x00000002; + + +ASTAT = R0; // cc=1 REGMV +R5 = R0 + R2; // comp3op dr plus dr +IF CC R1 = R3; // ccmov +ASTAT = R1; // cc=0 REGMV +R4 >>= R7; // alu2op sft +IF CC R3 = R2; // ccmv +CC = R0 < R1; // ccflag +R3.H = R1.L + R3.H (S); // dsp32alu +IF CC R4 = R5; // ccmv +CC = ! BITTST( R0 , 4 ); // cc = 0 +R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft +IF CC R4 = R5; // ccmv +CC = BITTST ( R1 , 4 ); // cc = 0 +R3.L = R5.L << 1; // dsp32shiftim +IF !CC JUMP LABEL1; // branch +CC = ! CC; +R1 = ( A1 = R7.L * R4.L ), R0 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair +IF !CC JUMP LABEL2 (BP); // branch +LABEL1: + R2 = R0 + R2; +JUMP.S END; +LABEL2: + R7 = R5 - R3; +CC = R0 < R1; // ccflag +R5 = R0 + R2; // comp3op dr plus dr +IF CC JUMP END (BP); // branch on +R4 = R5 + R7; + +END: + +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x0398000C; +CHECKREG r2, 0x62B61577; +CHECKREG r3, 0x07372AEE; +CHECKREG r4, 0x62B61577; +CHECKREG r5, 0x62B61577; +CHECKREG r6, 0xFC680013; +CHECKREG r7, 0x00000002; + +imm32 r0, 0x00000020; +imm32 r1, 0x00000000; +imm32 r2, 0x62661557; +imm32 r3, 0x073b0007; +imm32 r4, 0x01f49088; +imm32 r5, 0x6e2959aa; +imm32 r6, 0xa0b506cc; +imm32 r7, 0x00000002; + + + ASTAT = R0; // cc=1 REGMV + R4.H = R1.L + R0.L (S); // dsp32alu + R2 = ROT R2 BY 1; // dsp32shiftim_rot + ASTAT = R1; // cc=0 REGMV + A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac + R3 = ROT R3 BY 1; // dsp32shiftim_rot + CC = ! BITTST( R0 , 4 ); // cc = 0 + R4.L = R5.L << 1; // dsp32shiftimm + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = BITTST ( R1 , 4 ); // cc = 0 + R7 = R0 + R2; // comp3op dr plus dr + IF CC R4 = R5; // ccmov + A0 += A1 (W32); // dsp32alu a0 + a1 + CC = BITTST ( R0 , 4 ); // cc = 1 + R5 = ROT R6 BY R7.L; + R0 = A0.w; + R1 = A1.w; + +CHECKREG r0, 0x026B943C; +CHECKREG r1, 0x00025592; +CHECKREG r2, 0xC4CC2AAF; +CHECKREG r3, 0x0E76000E; +CHECKREG r4, 0x0020B354; +CHECKREG r5, 0x35480105; +CHECKREG r6, 0x04166A90; +CHECKREG r7, 0xC4CC2ACF; + +pass diff --git a/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_sn.S b/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_sn.S new file mode 100644 index 0000000..8b04188 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_sn.S @@ -0,0 +1,127 @@ +//Original:/proj/frio/dv/testcases/core/c_cc_regmvlogi_mvbrsft_sn/c_cc_regmvlogi_mvbrsft_sn.dsp +// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + INIT_I_REGS 0; + INIT_M_REGS 0; + INIT_L_REGS 0; + INIT_B_REGS 0; + INIT_R_REGS 0; + INIT_P_REGS 0; + ASTAT = R0; + A0 = A1 = 0; + + imm32 r0, (_CC); // cc=1 + imm32 r1, 0x00000000; // cc=0 + imm32 r2, 0x62b61557; + imm32 r3, 0x07300007; + imm32 r4, 0x00740088; + imm32 r5, 0x609950aa; + imm32 r6, 0x20bb06cc; + imm32 r7, 0x00000002; + + A0 = R4; + A1 = R6; + + ASTAT = R0; // cc=1 REGMV + P2 = R2; + R2 = R0 + R2; // comp3op dr plus dr + M0 = P2; // regmv + IF CC R1 = R3; // ccmov + ASTAT = R1; // cc=0 REGMV + R3 >>= R7; // alu2op sft + R3 = R0 + R2; // comp3op dr plus dr + I0 = R5; + IF CC R3 = R2; // ccmv + CC = R0 < R1; // ccflag + R3.H = R1.L + R3.H (S); // dsp32alu + R5 = ( A1 = R7.L * R4.H ), R4 = ( A0 = R7.H * R4.L ); // dsp32mac pair + IF CC R4 = R5; // ccmv + CC = ! BITTST( R0 , 4 ); // cc = 0 + R0 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft + I0 += 2; // dagmodim + IF CC R4 = R5; // ccmv + CC = BITTST ( R1 , 4 ); // cc = 0 + R7.L = R5.L << 1; // dsp32shiftim + R1 = R0 +|- R1 , R5 = R0 -|+ R1 (ASR); // dsp32alu sft + P1 = A0.w; + IF !CC JUMP LABEL1; // branch + CC = ! CC; + R1 = ( A1 = R7.L * R4.L ), R0 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair + I0 += M0; // dagmodim + P2 = A1.w; + IF !CC JUMP LABEL2 (BP); // branch +LABEL1: + R2 = R0 + R2; + JUMP.S END; +LABEL2: + R7 = R5 - R3; + CC = R0 < R1; // ccflag + R6 = R0 + R2; // comp3op dr plus dr + P4 = I0; + IF CC JUMP END (BP); // branch on + R7 = R5 + R7; + +END: + + CHECKREG r0, 0x0398000C; + CHECKREG r1, 0x05640002; + CHECKREG r2, 0x664E1583; + CHECKREG r3, 0x62BD1597; + CHECKREG r4, 0x000001D0; + CHECKREG r5, 0xFE340009; + CHECKREG r6, 0xFC680013; + CHECKREG r7, 0x000003A0; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x62B61557; + CHECKREG p4, 0x00000000; + + imm32 r0, (_CC); + imm32 r1, 0x00000000; + imm32 r2, 0x62661557; + imm32 r3, 0x073b0007; + imm32 r4, 0x01f49088; + imm32 r5, 0x6e2959aa; + imm32 r6, 0xa0b506cc; + imm32 r7, 0xabd30002; + + A1 = A0 = 0; + ASTAT = R0; // cc=1 REGMV + R2.H = R3.L + R4.L (NS); // dsp32alu + R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac + R3 = ROT R2 BY 1; // dsp32shiftim_rot + ASTAT = R1; // cc=0 REGMV + A1 += R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac + R2.L = R5.L << 1; // dsp32shiftimm + R5 = ROT R3 BY 1; // dsp32shiftim_rot + CC = ! BITTST( R0 , 4 ); // cc = 0 + R4.L = R5.L << 1; // dsp32shiftimm + R0 >>= R7; // alu2op sft + A0 += A1; // dsp32alu a0 + a1 + R6 = ROT R4 BY 5; // dsp32shiftim_rot + CC = BITTST ( R1 , 4 ); // cc = 0 + R0 = R0 + R2; // comp3op dr plus dr + R5 = R3.L * R4.H, R4 = R3.H * R4.L; // dsp32mult + P1 = A0.w; + IF CC R4 = R5; // ccmov + P1.L = 0x3000; // ldimmhalf + P2 = A1.w; // regmv + CC = BITTST ( R0 , 4 ); // cc = 1 + R7 = ROT R6 BY R7.L; + + CHECKREG r0, 0x0001B354; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x0001B354; + CHECKREG r3, 0x00022AAF; + CHECKREG r4, 0xFFFEAAF0; + CHECKREG r5, 0x00A6BB98; + CHECKREG r6, 0x3E955790; + CHECKREG r7, 0xFA555E42; + CHECKREG p1, 0x07193000; + CHECKREG p2, 0x071EE3B4; + + pass diff --git a/sim/testsuite/sim/bfin/c_ccflag_a0a1.S b/sim/testsuite/sim/bfin/c_ccflag_a0a1.S new file mode 100644 index 0000000..8163417 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccflag_a0a1.S @@ -0,0 +1,143 @@ +//Original:/testcases/core/c_ccflag_a0a1/c_ccflag_a0a1.dsp +// Spec Reference: ccflag a0-a1 (==, <, <=) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + imm32 r0, 0x12345778; + imm32 r1, 0x12345678; + imm32 r2, 0x056789ab; + imm32 r3, 0x80231345; + + imm32 r4, 0x00770088; + imm32 r5, 0x009900aa; + imm32 r6, 0x00bb00cc; + imm32 r7, _UNSET; + + ASTAT = R7; + R4 = ASTAT; + A0 = R0; + A1 = R0; + +// positive a0 EQUAL to a1 + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0|_CC|_AC0_COPY|_AZ); + CHECKREG r6, (_AC0|_AC0_COPY|_AZ); + CC = A0 <= A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r5, (_AC0|_CC|_AC0_COPY|_AZ); + CHECKREG r6, (_AC0|_AC0_COPY|_AZ); + CHECKREG r7, (_AC0|_CC|_AC0_COPY|_AZ); + +// positive a0 GREATER than to positive a1 + A1 = R1; + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r5, (_AC0|_AC0_COPY); // carry + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AC0|_AC0_COPY); + +// positive a0 LESS than to positive a1 + A1 = R2; + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AC0|_AC0_COPY); + +// positive a0 GREATER than to neg a1 + A1 = R3; + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r5, _UNSET; + CHECKREG r6, _UNSET; + CHECKREG r7, _UNSET; + +// negative a0 and positive a1 + imm32 r0, -1; + imm32 r1, 2; + imm32 r2, -3; + imm32 r3, -4; + A0 = R0; + A1 = R1; + + R7 = 0; + ASTAT = R7; + R4 = ASTAT; + + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0|_AC0_COPY|_AN); + CHECKREG r6, (_AC0|_AC0_COPY|_CC|_AN); + CHECKREG r7, (_AC0|_AC0_COPY|_CC|_AN); + +// negative a0 LESS than neg a1 + A0 = R3; + A1 = R4; + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0|_AC0_COPY|_AN); + CHECKREG r6, (_AC0|_AC0_COPY|_CC|_AN); + CHECKREG r7, (_AC0|_AC0_COPY|_CC|_AN); + +// negative a0 GREATER neg a1 + A0 = R0; + A1 = R3; + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY); + CHECKREG r7, (_AC0|_AC0_COPY); + +// negative a0 EQUAL neg imm3 + A0 = R3; + A1 = R3; + CC = A0 == A1; + R5 = ASTAT; + CC = A0 < A1; + R6 = ASTAT; + CC = A0 <= A1; + R7 = ASTAT; + CHECKREG r4, _UNSET; + CHECKREG r5, (_AC0|_CC|_AC0_COPY|_AZ); + CHECKREG r6, (_AC0|_AC0_COPY|_AZ); + CHECKREG r7, (_AC0|_CC|_AC0_COPY|_AZ); + + pass diff --git a/sim/testsuite/sim/bfin/c_ccflag_dr_dr.s b/sim/testsuite/sim/bfin/c_ccflag_dr_dr.s new file mode 100644 index 0000000..a72cb0c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccflag_dr_dr.s @@ -0,0 +1,299 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr/c_ccflag_dr_dr.dsp +// Spec Reference: ccflags dr-dr +# mach: bfin + +.include "testutils.inc" + start + + +imm32 r0, 0x00110022; +imm32 r1, 0x00110022; +imm32 r2, 0x00330044; +imm32 r3, 0x00550066; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R7; +R4 = ASTAT; + +// positive dreg-1 EQUAL to positive dreg-2 +CC = R0 == R1; +R5 = ASTAT; +CC = R0 < R1; +R6 = ASTAT; +CC = R0 <= R1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CHECKREG r7, 0x00001025; +CC = R0 < R1; +R4 = ASTAT; +CC = R0 <= R1 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00001005; +CHECKREG r5, 0x00001025; + +// positive dreg-1 GREATER than positive dreg-2 +CC = R3 == R2; +R5 = ASTAT; +CC = R3 < R2; +R6 = ASTAT; +CC = R3 <= R2; +R7 = ASTAT; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; +CC = R3 < R2 (IU); +R4 = ASTAT; +CC = R3 <= R2 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001004; + + +// positive dreg-1 LESS than positive dreg-2 +CC = R2 == R3; +R5 = ASTAT; +CC = R2 < R3; +R6 = ASTAT; +CC = R2 <= R3; +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; +CC = R2 < R3; +R4 = ASTAT; +CC = R2 <= R3; +R5 = ASTAT; +CHECKREG r4, 0x00000022; +CHECKREG r5, 0x00000022; + +imm32 r0, 0x01230123; +imm32 r1, 0x81230123; +imm32 r2, 0x04560456; +imm32 r3, 0x87890789; +// operate on negative number +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +// positive dreg-1 GREATER than negative dreg-2 +CC = R0 == R1; +R5 = ASTAT; +CC = R0 < R1; +R6 = ASTAT; +CC = R0 <= R1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// negative dreg-1 LESS than POSITIVE dreg-2 small +CC = R3 == R2; +R5 = ASTAT; +CC = R3 < R2; +R6 = ASTAT; +CC = R3 <= R2; +R7 = ASTAT; +CHECKREG r5, 0x00001006; +CHECKREG r6, 0x00001026; +CHECKREG r7, 0x00001026; + +// negative dreg-1 GREATER than negative dreg-2 +CC = R1 == R3; +R5 = ASTAT; +CC = R1 < R3; +R6 = ASTAT; +CC = R1 <= R3; +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// negative dreg-1 LESS than negative dreg-2 +CC = R3 == R1; +R5 = ASTAT; +CC = R3 < R1; +R6 = ASTAT; +CC = R3 <= R1; +R7 = ASTAT; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + + +imm32 r0, 0x80230123; +imm32 r1, 0x00230123; +imm32 r2, 0x80560056; +imm32 r3, 0x00890089; +// operate on negative number +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +// negative dreg-1 LESS than POSITIVE dreg-2 +CC = R2 == R3; +R5 = ASTAT; +CC = R2 < R3; +R6 = ASTAT; +CC = R2 <= R3; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001006; // overflow and carry but not negative +CHECKREG r6, 0x00001026; // cc overflow, carry and negative +CHECKREG r7, 0x00001026; + + +imm32 r4, 0x44444444; +imm32 r5, 0x55555555; +imm32 r6, 0x66666666; +imm32 r7, 0x77777777; + +imm32 r0, 0x00000000; +imm32 r1, 0x11111111; +imm32 r2, 0x22222222; +imm32 r3, 0x33333333; + +ASTAT = R0; +R3 = ASTAT; +NOP; +CHECKREG r3, 0x00000000; + +// positive dreg-1 EQUAL to positive dreg-2 +CC = R4 == R5; +R0 = ASTAT; +CC = R4 < R5; +R1 = ASTAT; +CC = R4 <= R5; +R2 = ASTAT; +CC = R4 < R5; +R3 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CC = R4 <= R5; +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00000022; + +// positive dreg-1 GREATER than positive dreg-2 +CC = R7 == R6; +R0 = ASTAT; +CC = R7 < R6; +R1 = ASTAT; +CC = R7 <= R6; +R2 = ASTAT; +CC = R7 < R6; +R3 = ASTAT; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; +CC = R7 <= R6 (IU); +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00001004; + + +// positive dreg-1 LESS than positive dreg-2 +CC = R6 == R7; +R0 = ASTAT; +CC = R6 < R7; +R1 = ASTAT; +CC = R6 <= R7; +R2 = ASTAT; +CC = R6 < R7; +R3 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CC = R6 <= R7; +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00000022; + +imm32 r4, 0x01230123; +imm32 r5, 0x81230123; +imm32 r6, 0x04560456; +imm32 r7, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R3 = ASTAT; +CHECKREG r3, 0x00000000; + +// positive dreg-1 GREATER than negative dreg-2 +CC = R4 == R5; +R1 = ASTAT; +CC = R4 < R5; +R2 = ASTAT; +CC = R4 <= R5; +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + +// negative dreg-1 LESS than POSITIVE dreg-2 small +CC = R7 == R6; +R0 = ASTAT; +CC = R7 < R6; +R1 = ASTAT; +CC = R7 <= R6; +R2 = ASTAT; +CHECKREG r0, 0x00001006; +CHECKREG r1, 0x00001026; +CHECKREG r2, 0x00001026; + +// negative dreg-1 GREATER than negative dreg-2 +CC = R5 == R7; +R0 = ASTAT; +CC = R5 < R7; +R1 = ASTAT; +CC = R5 <= R7; +R2 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; + +// negative dreg-1 LESS than negative dreg-2 +CC = R7 == R5; +R1 = ASTAT; +CC = R7 < R5; +R2 = ASTAT; +CC = R7 <= R5; +R3 = ASTAT; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + + +imm32 r4, 0x80230123; +imm32 r5, 0x00230123; +imm32 r6, 0x80560056; +imm32 r7, 0x00890089; +// operate on negative number +R3 = 0; +ASTAT = R3; +R0 = ASTAT; + +// negative dreg-1 LESS than POSITIVE dreg-2 +CC = R6 == R7; +R1 = ASTAT; +CC = R6 < R7; +R2 = ASTAT; +CC = R6 <= R7; +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001006; // overflow and carry but not negative +CHECKREG r2, 0x00001026; // cc overflow, carry and negative +CHECKREG r3, 0x00001026; + + +pass; diff --git a/sim/testsuite/sim/bfin/c_ccflag_dr_dr_uu.s b/sim/testsuite/sim/bfin/c_ccflag_dr_dr_uu.s new file mode 100644 index 0000000..2709c89 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccflag_dr_dr_uu.s @@ -0,0 +1,299 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr_uu/c_ccflag_dr_dr_uu.dsp +// Spec Reference: ccflags dr-dr_uu +# mach: bfin + +.include "testutils.inc" + start + + +imm32 r0, 0x00110022; +imm32 r1, 0x00110022; +imm32 r2, 0x00330044; +imm32 r3, 0x00550066; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R7; +R4 = ASTAT; + +// positive dreg-1 EQUAL to positive dreg-2 +CC = R0 == R1; +R5 = ASTAT; +CC = R0 < R1 (IU); +R6 = ASTAT; +CC = R0 <= R1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CHECKREG r7, 0x00001025; +CC = R0 < R1 (IU); +R4 = ASTAT; +CC = R0 <= R1 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00001005; +CHECKREG r5, 0x00001025; + +// positive dreg-1 GREATER than positive dreg-2 +CC = R3 == R2; +R5 = ASTAT; +CC = R3 < R2 (IU); +R6 = ASTAT; +CC = R3 <= R2 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; +CC = R3 < R2 (IU); +R4 = ASTAT; +CC = R3 <= R2 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001004; + + +// positive dreg-1 LESS than positive dreg-2 +CC = R2 == R3; +R5 = ASTAT; +CC = R2 < R3 (IU); +R6 = ASTAT; +CC = R2 <= R3 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; +CC = R2 < R3 (IU); +R4 = ASTAT; +CC = R2 <= R3 (IU); +R5 = ASTAT; +CHECKREG r4, 0x00000022; +CHECKREG r5, 0x00000022; + +imm32 r0, 0x01230123; +imm32 r1, 0x81230123; +imm32 r2, 0x04560456; +imm32 r3, 0x87890789; +// operate on negative number +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +// positive dreg-1 GREATER than negative dreg-2 +CC = R0 == R1; +R5 = ASTAT; +CC = R0 < R1 (IU); +R6 = ASTAT; +CC = R0 <= R1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// negative dreg-1 LESS than POSITIVE dreg-2 small +CC = R3 == R2; +R5 = ASTAT; +CC = R3 < R2 (IU); +R6 = ASTAT; +CC = R3 <= R2 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001006; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + +// negative dreg-1 GREATER than negative dreg-2 +CC = R1 == R3; +R5 = ASTAT; +CC = R1 < R3 (IU); +R6 = ASTAT; +CC = R1 <= R3 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// negative dreg-1 LESS than negative dreg-2 +CC = R3 == R1; +R5 = ASTAT; +CC = R3 < R1 (IU); +R6 = ASTAT; +CC = R3 <= R1 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + + +imm32 r0, 0x80230123; +imm32 r1, 0x00230123; +imm32 r2, 0x80560056; +imm32 r3, 0x00890089; +// operate on negative number +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +// negative dreg-1 LESS than POSITIVE dreg-2 +CC = R2 == R3; +R5 = ASTAT; +CC = R2 < R3 (IU); +R6 = ASTAT; +CC = R2 <= R3 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001006; // overflow and carry but not negative +CHECKREG r6, 0x00001004; // cc overflow, carry and negative +CHECKREG r7, 0x00001004; + + +imm32 r4, 0x44444444; +imm32 r5, 0x55555555; +imm32 r6, 0x66666666; +imm32 r7, 0x77777777; + +imm32 r0, 0x00000000; +imm32 r1, 0x11111111; +imm32 r2, 0x22222222; +imm32 r3, 0x33333333; + +ASTAT = R0; +R3 = ASTAT; +NOP; +CHECKREG r3, 0x00000000; + +// positive dreg-1 EQUAL to positive dreg-2 +CC = R4 == R5; +R0 = ASTAT; +CC = R4 < R5 (IU); +R1 = ASTAT; +CC = R4 <= R5 (IU); +R2 = ASTAT; +CC = R4 < R5 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CC = R4 <= R5 (IU); +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00000022; + +// positive dreg-1 GREATER than positive dreg-2 +CC = R7 == R6; +R0 = ASTAT; +CC = R7 < R6 (IU); +R1 = ASTAT; +CC = R7 <= R6 (IU); +R2 = ASTAT; +CC = R7 < R6 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; +CC = R7 <= R6 (IU); +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00001004; + + +// positive dreg-1 LESS than positive dreg-2 +CC = R6 == R7; +R0 = ASTAT; +CC = R6 < R7 (IU); +R1 = ASTAT; +CC = R6 <= R7 (IU); +R2 = ASTAT; +CC = R6 < R7 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; +CC = R6 <= R7 (IU); +R0 = ASTAT; +NOP; +CHECKREG r0, 0x00000022; + +imm32 r4, 0x01230123; +imm32 r5, 0x81230123; +imm32 r6, 0x04560456; +imm32 r7, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R3 = ASTAT; +CHECKREG r3, 0x00000000; + +// positive dreg-1 GREATER than negative dreg-2 +CC = R4 == R5; +R1 = ASTAT; +CC = R4 < R5 (IU); +R2 = ASTAT; +CC = R4 <= R5 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; + +// negative dreg-1 LESS than POSITIVE dreg-2 small +CC = R7 == R6; +R0 = ASTAT; +CC = R7 < R6 (IU); +R1 = ASTAT; +CC = R7 <= R6 (IU); +R2 = ASTAT; +CHECKREG r0, 0x00001006; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; + +// negative dreg-1 GREATER than negative dreg-2 +CC = R5 == R7; +R0 = ASTAT; +CC = R5 < R7 (IU); +R1 = ASTAT; +CC = R5 <= R7 (IU); +R2 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; + +// negative dreg-1 LESS than negative dreg-2 +CC = R7 == R5; +R1 = ASTAT; +CC = R7 < R5 (IU); +R2 = ASTAT; +CC = R7 <= R5 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + + +imm32 r4, 0x80230123; +imm32 r5, 0x00230123; +imm32 r6, 0x80560056; +imm32 r7, 0x00890089; +// operate on negative number +R3 = 0; +ASTAT = R3; +R0 = ASTAT; + +// negative dreg-1 LESS than POSITIVE dreg-2 +CC = R6 == R7; +R1 = ASTAT; +CC = R6 < R7 (IU); +R2 = ASTAT; +CC = R6 <= R7 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001006; // overflow and carry but not negative +CHECKREG r2, 0x00001004; // cc overflow, carry and negative +CHECKREG r3, 0x00001004; + + +pass; diff --git a/sim/testsuite/sim/bfin/c_ccflag_dr_imm3.s b/sim/testsuite/sim/bfin/c_ccflag_dr_imm3.s new file mode 100644 index 0000000..e584b80 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccflag_dr_imm3.s @@ -0,0 +1,224 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3/c_ccflag_dr_imm3.dsp +// Spec Reference: ccflag dr-imm3 +# mach: bfin + +.include "testutils.inc" + start + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000002; +imm32 r2, 0x00000003; +imm32 r3, 0x00000004; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R7; +R4 = ASTAT; + +// positive dreg EQUAL to positive imm3 +CC = R0 == 1; +R5 = ASTAT; +CC = R0 < 1; +R6 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CC = R0 <= 1; +R5 = ASTAT; +CC = R0 < 1; +R6 = ASTAT; +CC = R0 <= 1; +R7 = ASTAT; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CHECKREG r7, 0x00001025; + +// positive dreg GREATER than to positive imm3 +CC = R1 == 1; +R5 = ASTAT; +CC = R1 < 1; +R6 = ASTAT; +CC = R1 <= 1; +R7 = ASTAT; +CHECKREG r5, 0x00001004; // carry +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + +// positive dreg LESS than to positive imm3 +CC = R0 == 2; +R5 = ASTAT; +CC = R0 < 2; +R6 = ASTAT; +CC = R0 <= 2; +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// positive dreg GREATER than to neg imm3 +CC = R2 == -4; +R5 = ASTAT; +CC = R2 < -4; +R6 = ASTAT; +CC = R2 <= -4; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, -1; +imm32 r1, -2; +imm32 r2, -3; +imm32 r3, -4; +// negative dreg and positive imm3 +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +CC = R3 == 1; +R5 = ASTAT; +CC = R3 < 1; +R6 = ASTAT; +CC = R3 <= 1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001006; +CHECKREG r6, 0x00001026; +CHECKREG r7, 0x00001026; + +// negative dreg LESS than neg imm3 +CC = R2 == -1; +R4 = ASTAT; +CC = R2 < -1; +R5 = ASTAT; +CC = R2 <= -1; +R6 = ASTAT; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000022; +CHECKREG r6, 0x00000022; + +// negative dreg GREATER neg imm3 +CC = R0 == -4; +R4 = ASTAT; +CC = R0 < -4; +R5 = ASTAT; +CC = R0 <= -4; +R6 = ASTAT; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; + +imm32 r4, 0x00000001; +imm32 r5, 0x00000002; +imm32 r6, 0x00000003; +imm32 r7, 0x00000004; + +ASTAT = R0; +R3 = ASTAT; + +// positive dreg EQUAL to positive imm3 +CC = R4 == 1; +R1 = ASTAT; +CC = R4 < 1; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001025; +CHECKREG r2, 0x00001005; +CC = R4 <= 1; +R1 = ASTAT; +CC = R4 < 1; +R2 = ASTAT; +CC = R4 <= 1; +R3 = ASTAT; +CHECKREG r1, 0x00001025; +CHECKREG r2, 0x00001005; +CHECKREG r3, 0x00001025; + +// positive dreg GREATER than to positive imm3 +CC = R5 == 1; +R1 = ASTAT; +CC = R5 < 1; +R2 = ASTAT; +CC = R5 <= 1; +R3 = ASTAT; +CHECKREG r1, 0x00001004; // carry +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// positive dreg LESS than to positive imm3 +CC = R6 == 2; +R1 = ASTAT; +CC = R6 < 2; +R2 = ASTAT; +CC = R6 <= 2; +R3 = ASTAT; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// positive dreg GREATER than to neg imm3 +CC = R6 == -4; +R1 = ASTAT; +CC = R6 < -4; +R2 = ASTAT; +CC = R6 <= -4; +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + +imm32 r4, -1; +imm32 r5, -2; +imm32 r6, -3; +imm32 r7, -4; +// negative dreg and positive imm3 +R3 = 0; +ASTAT = R3; +R0 = ASTAT; + +CC = R7 == 1; +R1 = ASTAT; +CC = R7 < 1; +R2 = ASTAT; +CC = R7 <= 1; +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001006; +CHECKREG r2, 0x00001026; +CHECKREG r3, 0x00001026; + +// negative dreg LESS than neg imm3 +CC = R6 == -1; +R0 = ASTAT; +CC = R6 < -1; +R1 = ASTAT; +CC = R6 <= -1; +R2 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000022; + +// negative dreg GREATER neg imm3 +CC = R4 == -4; +R0 = ASTAT; +CC = R4 < -4; +R1 = ASTAT; +CC = R4 <= -4; +R2 = ASTAT; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; + + + +pass; diff --git a/sim/testsuite/sim/bfin/c_ccflag_dr_imm3_uu.s b/sim/testsuite/sim/bfin/c_ccflag_dr_imm3_uu.s new file mode 100644 index 0000000..d4a6a48 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccflag_dr_imm3_uu.s @@ -0,0 +1,221 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3_uu/c_ccflag_dr_imm3_uu.dsp +// Spec Reference: ccflag dr-imm3 (uu) +# mach: bfin + +.include "testutils.inc" + start + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000002; +imm32 r2, 0x00000003; +imm32 r3, 0x00000004; + +imm32 r4, 0x00770088; +imm32 r5, 0x009900aa; +imm32 r6, 0x00bb00cc; +imm32 r7, 0x00000000; + +ASTAT = R7; +R4 = ASTAT; + +// positive dreg EQUAL to positive imm3 +CC = R0 == 1; +R5 = ASTAT; +CC = R0 < 1; +R6 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CC = R0 <= 1; +R5 = ASTAT; +CC = R0 < 1 (IU); +R6 = ASTAT; +CC = R0 <= 1 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001025; +CHECKREG r6, 0x00001005; +CHECKREG r7, 0x00001025; + +// positive dreg GREATER than to positive imm3 +CC = R1 == 1; +R5 = ASTAT; +CC = R1 < 1 (IU); +R6 = ASTAT; +CC = R1 <= 1 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00001004; // carry +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + +// positive dreg LESS than to positive imm3 +CC = R0 == 2; +R5 = ASTAT; +CC = R0 < 2 (IU); +R6 = ASTAT; +CC = R0 <= 2 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +// positive dreg GREATER than to neg imm3 +CC = R2 == -4; +R5 = ASTAT; +CC = R2 < 4 (IU); +R6 = ASTAT; +CC = R2 <= 4 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000022; +CHECKREG r7, 0x00000022; + +imm32 r0, -1; +imm32 r1, -2; +imm32 r2, -3; +imm32 r3, -4; +// negative dreg and positive imm3 +R7 = 0; +ASTAT = R7; +R4 = ASTAT; + +CC = R3 == 1; +R5 = ASTAT; +CC = R3 < 1 (IU); +R6 = ASTAT; +CC = R3 <= 1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00001006; +CHECKREG r6, 0x00001004; +CHECKREG r7, 0x00001004; + +// negative dreg LESS than neg imm3 +CC = R2 == -1; +R4 = ASTAT; +CC = R2 < 1 (IU); +R5 = ASTAT; +CC = R2 <= 1 (IU); +R6 = ASTAT; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; + +// negative dreg GREATER neg imm3 +CC = R0 == -2; +R4 = ASTAT; +CC = R0 < 4 (IU); +R5 = ASTAT; +CC = R0 <= 4 (IU); +R6 = ASTAT; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001004; +CHECKREG r6, 0x00001004; + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; + +imm32 r4, 0x00000001; +imm32 r5, 0x00000002; +imm32 r6, 0x00000003; +imm32 r7, 0x00000004; + +ASTAT = R0; +R3 = ASTAT; + +// positive dreg EQUAL to positive imm3 +CC = R4 == 1; +R1 = ASTAT; +CC = R4 < 1 (IU); +R2 = ASTAT; +CC = R4 <= 1 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001025; +CHECKREG r2, 0x00001005; +CHECKREG r3, 0x00001025; + +// positive dreg GREATER than to positive imm3 +CC = R5 == 1; +R1 = ASTAT; +CC = R5 < 1 (IU); +R2 = ASTAT; +CC = R5 <= 1 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00001004; // carry +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// positive dreg LESS than to positive imm3 +CC = R6 == 2; +R1 = ASTAT; +CC = R6 < 2 (IU); +R2 = ASTAT; +CC = R6 <= 2 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// positive dreg GREATER than to neg imm3 +CC = R6 == -4; +R1 = ASTAT; +CC = R6 < 4 (IU); +R2 = ASTAT; +CC = R6 <= 4 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000022; +CHECKREG r3, 0x00000022; + +imm32 r4, -1; +imm32 r5, -2; +imm32 r6, -3; +imm32 r7, -4; +// negative dreg and positive imm3 +R3 = 0; +ASTAT = R3; +R0 = ASTAT; + +CC = R7 == 1; +R1 = ASTAT; +CC = R7 < 1 (IU); +R2 = ASTAT; +CC = R7 <= 1 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001006; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001004; + +// negative dreg LESS than neg imm3 +CC = R6 == -1; +R0 = ASTAT; +CC = R6 < 1 (IU); +R1 = ASTAT; +CC = R6 <= 1 (IU); +R2 = ASTAT; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; + +// negative dreg GREATER neg imm3 +CC = R4 == -4; +R0 = ASTAT; +CC = R4 < 4 (IU); +R1 = ASTAT; +CC = R4 <= 4 (IU); +R2 = ASTAT; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001004; +CHECKREG r2, 0x00001004; + + + + + + +pass; diff --git a/sim/testsuite/sim/bfin/c_ccflag_pr_imm3.s b/sim/testsuite/sim/bfin/c_ccflag_pr_imm3.s new file mode 100644 index 0000000..aa6a0eb --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccflag_pr_imm3.s @@ -0,0 +1,539 @@ +//Original:/testcases/core/c_ccflag_pr_imm3/c_ccflag_pr_imm3.dsp +// Spec Reference: ccflag pr-imm3 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +//imm32 p0, 0x00000001; +imm32 p1, 0x00000001; +imm32 p2, 0x00000002; +imm32 p3, 0x00000003; +imm32 p4, 0x00000001; +imm32 p5, 0x00000002; +imm32 sp, 0x00000003; +imm32 fp, 0x00000003; + +R0 = 0; +ASTAT = R0; +// positive dreg EQUAL to positive imm3 +CC = P1 == 1; +R0 = ASTAT; +CC = P1 < 1; +R1 = ASTAT; +CC = P1 <= 1; +R2 = ASTAT; +CC = P2 == 2; +R3 = ASTAT; +CC = P2 < 2; +R4 = ASTAT; +CC = P2 <= 2; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P3 == 3; +R0 = ASTAT; +CC = P3 < 3; +R1 = ASTAT; +CC = P3 <= 3; +R2 = ASTAT; +CC = P4 == 1; +R3 = ASTAT; +CC = P4 < 1; +R4 = ASTAT; +CC = P4 <= 1; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P5 == 2; +R0 = ASTAT; +CC = P5 < 2; +R1 = ASTAT; +CC = P5 <= 2; +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 3; +R4 = ASTAT; +CC = SP <= 3; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 3; +R6 = ASTAT; +CC = FP <= 3; +R7 = ASTAT; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000020; + +// positive dreg GREATER than positive imm3 +imm32 p1, 0x00000002; +imm32 p2, 0x00000002; +imm32 p3, 0x00000003; +imm32 p4, 0x00000002; +imm32 p5, 0x00000002; +imm32 sp, 0x00000003; +imm32 fp, 0x00000003; +CC = P1 == 0; +R0 = ASTAT; +CC = P1 < 0; +R1 = ASTAT; +CC = P1 <= 0; +R2 = ASTAT; +CC = P2 == 1; +R3 = ASTAT; +CC = P2 < 1; +R4 = ASTAT; +CC = P2 <= 1; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P3 == 2; +R0 = ASTAT; +CC = P3 < 2; +R1 = ASTAT; +CC = P3 <= 2; +R2 = ASTAT; +CC = P4 == 0; +R3 = ASTAT; +CC = P4 < 0; +R4 = ASTAT; +CC = P4 <= 0; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P5 == 1; +R0 = ASTAT; +CC = P5 < 1; +R1 = ASTAT; +CC = P5 <= 1; +R2 = ASTAT; +CC = SP == 2; +R3 = ASTAT; +CC = SP < 2; +R4 = ASTAT; +CC = SP <= 2; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = FP == 2; +R5 = ASTAT; +CC = FP < 2; +R6 = ASTAT; +CC = FP <= 2; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// positive dreg LESS than positive imm3 +imm32 p1, 0x00000001; +imm32 p2, 0x00000002; +imm32 p3, 0x00000002; +imm32 p4, 0x00000001; +imm32 p5, 0x00000001; +imm32 sp, 0x00000002; +imm32 fp, 0x00000002; +CC = P1 == 2; +R0 = ASTAT; +CC = P1 < 2; +R1 = ASTAT; +CC = P1 <= 2; +R2 = ASTAT; +CC = P2 == 3; +R3 = ASTAT; +CC = P2 < 3; +R4 = ASTAT; +CC = P2 <= 3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P3 == 3; +R0 = ASTAT; +CC = P3 < 3; +R1 = ASTAT; +CC = P3 <= 3; +R2 = ASTAT; +CC = P4 == 3; +R3 = ASTAT; +CC = P4 < 3; +R4 = ASTAT; +CC = P4 <= 3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P5 == 3; +R0 = ASTAT; +CC = P5 < 3; +R1 = ASTAT; +CC = P5 <= 3; +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 3; +R4 = ASTAT; +CC = SP <= 3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 3; +R6 = ASTAT; +CC = FP <= 3; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + + +// positive dreg GREATER than neg imm3 +CC = P1 == -1; +R0 = ASTAT; +CC = P1 < -1; +R1 = ASTAT; +CC = P1 <= -1; +R2 = ASTAT; +CC = P2 == -2; +R3 = ASTAT; +CC = P2 < -2; +R4 = ASTAT; +CC = P2 <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P3 == -3; +R0 = ASTAT; +CC = P3 < -3; +R1 = ASTAT; +CC = P3 <= -3; +R2 = ASTAT; +CC = P4 == -4; +R3 = ASTAT; +CC = P4 < -4; +R4 = ASTAT; +CC = P4 <= -4; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P5 == -1; +R0 = ASTAT; +CC = P5 < -1; +R1 = ASTAT; +CC = P5 <= -1; +R2 = ASTAT; +CC = SP == -2; +R3 = ASTAT; +CC = SP < -2; +R4 = ASTAT; +CC = SP <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = FP == -4; +R5 = ASTAT; +CC = FP < -4; +R6 = ASTAT; +CC = FP <= -4; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + + +imm32 p1, -1; +imm32 p2, -2; +imm32 p3, -3; +imm32 p4, -4; +imm32 p5, -1; +imm32 sp, -2; +imm32 fp, -3; +// negative dreg equal negative imm3 +CC = P1 == -1; +R0 = ASTAT; +CC = P1 < -1; +R1 = ASTAT; +CC = P1 <= -1; +R2 = ASTAT; +CC = P2 == -2; +R3 = ASTAT; +CC = P2 < -2; +R4 = ASTAT; +CC = P2 <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P3 == -3; +R0 = ASTAT; +CC = P3 < -3; +R1 = ASTAT; +CC = P3 <= -3; +R2 = ASTAT; +CC = P4 == -4; +R3 = ASTAT; +CC = P4 < -4; +R4 = ASTAT; +CC = P4 <= -4; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P5 == -1; +R0 = ASTAT; +CC = P5 < -1; +R1 = ASTAT; +CC = P5 <= -1; +R2 = ASTAT; +CC = SP == -2; +R3 = ASTAT; +CC = SP < -2; +R4 = ASTAT; +CC = SP <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = FP == -3; +R5 = ASTAT; +CC = FP < -3; +R6 = ASTAT; +CC = FP <= -3; +R7 = ASTAT; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000020; + + +// negative dreg GREATER neg imm3 +imm32 p1, -1; +imm32 p2, -1; +imm32 p3, -2; +imm32 p4, -3; +imm32 p5, -1; +imm32 sp, -2; +imm32 fp, -3; +CC = P1 == -2; +R0 = ASTAT; +CC = P1 < -2; +R1 = ASTAT; +CC = P1 <= -2; +R2 = ASTAT; +CC = P2 == -3; +R3 = ASTAT; +CC = P2 < -3; +R4 = ASTAT; +CC = P2 <= -3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P3 == -4; +R0 = ASTAT; +CC = P3 < -4; +R1 = ASTAT; +CC = P3 <= -4; +R2 = ASTAT; +CC = P4 == -4; +R3 = ASTAT; +CC = P4 < -4; +R4 = ASTAT; +CC = P4 <= -4; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P5 == -2; +R0 = ASTAT; +CC = P5 < -2; +R1 = ASTAT; +CC = P5 <= -2; +R2 = ASTAT; +CC = SP == -3; +R3 = ASTAT; +CC = SP < -3; +R4 = ASTAT; +CC = SP <= -3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = FP == -4; +R5 = ASTAT; +CC = FP < -4; +R6 = ASTAT; +CC = FP <= -4; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// negative dreg LESS than neg imm3 +imm32 p1, -2; +imm32 p2, -2; +imm32 p3, -3; +imm32 p4, -3; +imm32 p5, -4; +imm32 sp, -4; +imm32 fp, -4; +imm32 p4, -4; +CC = P1 == -1; +R0 = ASTAT; +CC = P1 < -1; +R1 = ASTAT; +CC = P1 <= -1; +R2 = ASTAT; +CC = P2 == -1; +R3 = ASTAT; +CC = P2 < -1; +R4 = ASTAT; +CC = P2 <= -1; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P3 == -2; +R0 = ASTAT; +CC = P3 < -2; +R1 = ASTAT; +CC = P3 <= -2; +R2 = ASTAT; +CC = P4 == -2; +R3 = ASTAT; +CC = P4 < -2; +R4 = ASTAT; +CC = P4 <= -2; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P5 == -3; +R0 = ASTAT; +CC = P5 < -3; +R1 = ASTAT; +CC = P5 <= -3; +R2 = ASTAT; +CC = SP == -3; +R3 = ASTAT; +CC = SP < -3; +R4 = ASTAT; +CC = SP <= -3; +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = FP == -3; +R5 = ASTAT; +CC = FP < -3; +R6 = ASTAT; +CC = FP <= -3; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + + +pass diff --git a/sim/testsuite/sim/bfin/c_ccflag_pr_imm3_uu.s b/sim/testsuite/sim/bfin/c_ccflag_pr_imm3_uu.s new file mode 100644 index 0000000..6b18702 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccflag_pr_imm3_uu.s @@ -0,0 +1,238 @@ +//Original:/testcases/core/c_ccflag_pr_imm3_uu/c_ccflag_pr_imm3_uu.dsp +// Spec Reference: ccflag pr-imm3 (uu) +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS 0; + + +//imm32 p0, 0x00000001; +imm32 p1, 0x00000001; +imm32 p2, 0x00000002; +imm32 p3, 0x00000003; +imm32 p4, 0x00000004; +imm32 p5, 0x00000005; +imm32 sp, 0x00000006; +imm32 fp, 0x00000007; + +R0 = 0; +ASTAT = R0; +// positive preg EQUAL to positive imm3 +CC = P1 == 1; +R0 = ASTAT; +CC = P1 < 1 (IU); +R1 = ASTAT; +CC = P1 <= 1 (IU); +R2 = ASTAT; +CC = P2 == 2; +R3 = ASTAT; +CC = P2 < 2 (IU); +R4 = ASTAT; +CC = P2 <= 2 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P3 == 3; +R0 = ASTAT; +CC = P3 < 3 (IU); +R1 = ASTAT; +CC = P3 <= 3 (IU); +R2 = ASTAT; +CC = P4 == 3; +R3 = ASTAT; +CC = P4 < 4 (IU); +R4 = ASTAT; +CC = P4 <= 4 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000020; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = P5 == 3; +R0 = ASTAT; +CC = P5 < 5 (IU); +R1 = ASTAT; +CC = P5 <= 5 (IU); +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 6 (IU); +R4 = ASTAT; +CC = SP <= 6 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000020; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 7 (IU); +R6 = ASTAT; +CC = FP <= 7 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000020; + +// positive preg GREATER than positive imm3 +CC = P1 == 0; +R0 = ASTAT; +CC = P1 < 0 (IU); +R1 = ASTAT; +CC = P1 <= 0 (IU); +R2 = ASTAT; +CC = P2 == 1; +R3 = ASTAT; +CC = P2 < 1 (IU); +R4 = ASTAT; +CC = P2 <= 1 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P3 == 2; +R0 = ASTAT; +CC = P3 < 2 (IU); +R1 = ASTAT; +CC = P3 <= 2 (IU); +R2 = ASTAT; +CC = P4 == 3; +R3 = ASTAT; +CC = P4 < 3 (IU); +R4 = ASTAT; +CC = P4 <= 3 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = P5 == 3; +R0 = ASTAT; +CC = P5 < 4 (IU); +R1 = ASTAT; +CC = P5 <= 4 (IU); +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 5 (IU); +R4 = ASTAT; +CC = SP <= 5 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 6 (IU); +R6 = ASTAT; +CC = FP <= 6 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// positive preg LESS than positive imm3 +imm32 p1, 0x00000000; +imm32 p2, 0x00000001; +imm32 p3, 0x00000002; +imm32 p4, 0x00000003; +imm32 p5, 0x00000004; +imm32 sp, 0x00000005; +imm32 fp, 0x00000006; +CC = P1 == 2; +R0 = ASTAT; +CC = P1 < 2 (IU); +R1 = ASTAT; +CC = P1 <= 2 (IU); +R2 = ASTAT; +CC = P2 == 3; +R3 = ASTAT; +CC = P2 < 3 (IU); +R4 = ASTAT; +CC = P2 <= 3 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P3 == 3; +R0 = ASTAT; +CC = P3 < 4 (IU); +R1 = ASTAT; +CC = P3 <= 4 (IU); +R2 = ASTAT; +CC = P4 == 3; +R3 = ASTAT; +CC = P4 < 5 (IU); +R4 = ASTAT; +CC = P4 <= 5 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = P5 == 3; +R0 = ASTAT; +CC = P5 < 6 (IU); +R1 = ASTAT; +CC = P5 <= 6 (IU); +R2 = ASTAT; +CC = SP == 3; +R3 = ASTAT; +CC = SP < 7 (IU); +R4 = ASTAT; +CC = SP <= 7 (IU); +R5 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000020; +CHECKREG r5, 0x00000020; + +CC = FP == 3; +R5 = ASTAT; +CC = FP < 7 (IU); +R6 = ASTAT; +CC = FP <= 7 (IU); +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + + + + +pass diff --git a/sim/testsuite/sim/bfin/c_ccflag_pr_pr.s b/sim/testsuite/sim/bfin/c_ccflag_pr_pr.s new file mode 100644 index 0000000..ef9db52 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccflag_pr_pr.s @@ -0,0 +1,262 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr/c_ccflag_pr_pr.dsp +// Spec Reference: ccflag pr-pr +# mach: bfin + +.include "testutils.inc" + start + +INIT_P_REGS 0; +INIT_R_REGS 0; + + +//imm32 p0, 0x00110022; +imm32 p1, 0x00110022; +imm32 p2, 0x00330044; +imm32 p3, 0x00550066; + +imm32 p4, 0x00770088; +imm32 p5, 0x009900aa; +imm32 fp, 0x00bb00cc; +imm32 sp, 0x00000000; + +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// positive preg-1 EQUAL to positive preg-2 +CC = P2 == P1; +R5 = ASTAT; +P5 = R5; +CC = P2 < P1; +R6 = ASTAT; +CC = P2 <= P1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// positive preg-1 GREATER than positive preg-2 +CC = P3 == P2; +R5 = ASTAT; +CC = P3 < P2; +R6 = ASTAT; +CC = P3 <= P2; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +// positive preg-1 LESS than positive preg-2 +CC = P2 == P3; +R5 = ASTAT; +CC = P2 < P3; +R6 = ASTAT; +CC = P2 <= P3; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +//imm32 p0, 0x01230123; +imm32 p1, 0x81230123; +imm32 p2, 0x04560456; +imm32 p3, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// positive preg-1 GREATER than negative preg-2 +CC = P2 == P1; +R5 = ASTAT; +CC = P2 < P1; +R6 = ASTAT; +CC = P2 <= P1; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// negative preg-1 LESS than POSITIVE preg-2 small +CC = P3 == P2; +R5 = ASTAT; +CC = P3 < P2; +R6 = ASTAT; +CC = P3 <= P2; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +// negative preg-1 GREATER than negative preg-2 +CC = P1 == P3; +R5 = ASTAT; +CC = P1 < P3; +R6 = ASTAT; +CC = P1 <= P3; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +// negative preg-1 LESS than negative preg-2 +CC = P3 == P1; +R5 = ASTAT; +CC = P3 < P1; +R6 = ASTAT; +CC = P3 <= P1; +R7 = ASTAT; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +//imm32 p0, 0x80230123; +imm32 p1, 0x00230123; +imm32 p2, 0x80560056; +imm32 p3, 0x00890089; +// operate on negative number +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// negative preg-1 LESS than POSITIVE preg-2 +CC = P2 == P3; +R5 = ASTAT; +CC = P2 < P3; +R6 = ASTAT; +CC = P2 <= P3; +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; // overflow and carry but not negative +CHECKREG r6, 0x00000020; // cc overflow, carry and negative +CHECKREG r7, 0x00000020; + + +imm32 p4, 0x44444444; +imm32 p5, 0x55555555; +imm32 fp, 0x66666666; +imm32 sp, 0x77777777; + +//imm32 p0, 0x00000000; +imm32 p1, 0x11111111; +imm32 p2, 0x00000000; +imm32 p3, 0x33333333; + +ASTAT = R0; +R3 = ASTAT; +CHECKREG r3, 0x00000000; + +// positive preg-1 EQUAL to positive preg-2 +CC = P4 == P5; +R0 = ASTAT; +CC = P4 < P5; +R1 = ASTAT; +CC = P4 <= P5; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// positive preg-1 GREATER than positive preg-2 +CC = SP == FP; +R0 = ASTAT; +CC = SP < FP; +R1 = ASTAT; +CC = SP <= FP; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; + + +// positive preg-1 LESS than positive preg-2 +CC = FP == SP; +R0 = ASTAT; +CC = FP < SP; +R1 = ASTAT; +CC = FP <= SP; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +imm32 p4, 0x01230123; +imm32 p5, 0x81230123; +imm32 fp, 0x04560456; +imm32 sp, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R3 = ASTAT; // nop; +CHECKREG r3, 0x00000000; + +// positive preg-1 GREATER than negative preg-2 +CC = P4 == P5; +R1 = ASTAT; +CC = P4 < P5; +R2 = ASTAT; +CC = P4 <= P5; +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + +// negative preg-1 LESS than POSITIVE preg-2 small +CC = SP == FP; +R0 = ASTAT; +CC = SP < FP; +R1 = ASTAT; +CC = SP <= FP; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// negative preg-1 GREATER than negative preg-2 +CC = P5 == SP; +R0 = ASTAT; +CC = P5 < SP; +R1 = ASTAT; +CC = P5 <= SP; +R2 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// negative preg-1 LESS than negative preg-2 +CC = SP == P5; +R1 = ASTAT; +CC = SP < P5; +R2 = ASTAT; +CC = SP <= P5; +R3 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + + +imm32 p4, 0x80230123; +imm32 p5, 0x00230123; +imm32 fp, 0x80560056; +imm32 sp, 0x00890089; +// operate on negative number +P3 = 0; +ASTAT = P3; +R0 = ASTAT; + +// negative preg-1 LESS than POSITIVE preg-2 +CC = R6 == R7; +R1 = ASTAT; +CC = R6 < R7; +R2 = ASTAT; +CC = R6 <= R7; +R3 = ASTAT; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001025; // overflow and carry but not negative +CHECKREG r2, 0x00001005; // cc overflow, carry and negative +CHECKREG r3, 0x00001025; + + +pass; diff --git a/sim/testsuite/sim/bfin/c_ccflag_pr_pr_uu.s b/sim/testsuite/sim/bfin/c_ccflag_pr_pr_uu.s new file mode 100644 index 0000000..0cde8c2 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccflag_pr_pr_uu.s @@ -0,0 +1,212 @@ +//Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr_uu/c_ccflag_pr_pr_uu.dsp +// Spec Reference: ccflag pr-pr (uu) +# mach: bfin + +.include "testutils.inc" + start + +INIT_R_REGS 0; + +//imm32 p0, 0x00110022; +imm32 p1, 0x00110022; +imm32 p2, 0x00330044; +imm32 p3, 0x00550066; + +imm32 p4, 0x00770088; +imm32 p5, 0x009900aa; +imm32 fp, 0x00bb00cc; +imm32 sp, 0x00000000; + +ASTAT = R0; +R4 = ASTAT; + +// positive preg-1 EQUAL to positive preg-2 +CC = P2 < P1 (IU); +R6 = ASTAT; +CC = P2 <= P1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// positive preg-1 GREATER than positive preg-2 +CC = P3 < P2 (IU); +R6 = ASTAT; +CC = P3 <= P2 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +// positive preg-1 LESS than positive preg-2 +CC = P2 < P3 (IU); +R6 = ASTAT; +CC = P2 <= P3 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +//imm32 p0, 0x01230123; +imm32 p1, 0x81230123; +imm32 p2, 0x04560456; +imm32 p3, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// positive preg-1 GREATER than negative preg-2 +CC = P2 < P1 (IU); +R6 = ASTAT; +CC = P2 <= P1 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +// negative preg-1 LESS than POSITIVE preg-2 small +CC = P3 < P2 (IU); +R6 = ASTAT; +CC = P3 <= P2 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// negative preg-1 GREATER than negative preg-2 +CC = P1 < P3 (IU); +R6 = ASTAT; +CC = P1 <= P3 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000020; +CHECKREG r7, 0x00000020; + +// negative preg-1 LESS than negative preg-2 +CC = P3 < P1 (IU); +R6 = ASTAT; +CC = P3 <= P1 (IU); +R7 = ASTAT; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +//imm32 p0, 0x80230123; +imm32 p1, 0x00230123; +imm32 p2, 0x80560056; +imm32 p3, 0x00890089; +// operate on negative number +R0 = 0; +ASTAT = R0; +R4 = ASTAT; + +// negative preg-1 LESS than POSITIVE preg-2 +CC = P2 < P3 (IU); +R6 = ASTAT; +CC = P2 <= P3 (IU); +R7 = ASTAT; +CHECKREG r4, 0x00000000; // overflow and carry but not negative +CHECKREG r6, 0x00000000; // cc overflow, carry and negative +CHECKREG r7, 0x00000000; + + +imm32 p4, 0x44444444; +imm32 p5, 0x55555555; +imm32 fp, 0x66666666; +imm32 sp, 0x77777777; + +//imm32 p0, 0x00000000; +imm32 p1, 0x11111111; +imm32 p2, 0x00000000; +imm32 p3, 0x33333333; + +ASTAT = R0; +R3 = ASTAT; +CHECKREG r3, 0x00000000; + +// positive preg-1 EQUAL to positive preg-2 +CC = P4 < P5; +R1 = ASTAT; +CC = P4 <= P5; +R2 = ASTAT; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// positive preg-1 GREATER than positive preg-2 +CC = SP < FP (IU); +R1 = ASTAT; +CC = SP <= FP (IU); +R2 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; + + +// positive preg-1 LESS than positive preg-2 +CC = FP < SP (IU); +R1 = ASTAT; +CC = FP <= SP (IU); +R2 = ASTAT; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +imm32 p4, 0x01230123; +imm32 p5, 0x81230123; +imm32 fp, 0x04560456; +imm32 sp, 0x87890789; +// operate on negative number +R0 = 0; +ASTAT = R0; +R3 = ASTAT; // nop; +CHECKREG r3, 0x00000000; + +// positive preg-1 GREATER than negative preg-2 +CC = P4 < P5 (IU); +R2 = ASTAT; +CC = P4 <= P5 (IU); +R3 = ASTAT; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000020; + +// negative preg-1 LESS than POSITIVE preg-2 small +CC = SP < FP (IU); +R1 = ASTAT; +CC = SP <= FP (IU); +R2 = ASTAT; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; + +// negative preg-1 GREATER than negative preg-2 +CC = P5 < SP (IU); +R1 = ASTAT; +CC = P5 <= SP (IU); +R2 = ASTAT; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000020; + +// negative preg-1 LESS than negative preg-2 +CC = SP < P5 (IU); +R2 = ASTAT; +CC = SP <= P5 (IU); +R3 = ASTAT; +CHECKREG r1, 0x00000020; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; + + +imm32 p4, 0x80230123; +imm32 p5, 0x00230123; +imm32 fp, 0x80560056; +imm32 sp, 0x00890089; +// operate on negative number +R0 = 0; +ASTAT = R0; +R0 = ASTAT; + +// negative preg-1 LESS than POSITIVE preg-2 +CC = R6 < R7 (IU); +R2 = ASTAT; +CC = R6 <= R7 (IU); +R3 = ASTAT; +CHECKREG r0, 0x00000000; // overflow and carry but not negative +CHECKREG r2, 0x00001005; // cc overflow, carry and negative +CHECKREG r3, 0x00001025; + + +pass; diff --git a/sim/testsuite/sim/bfin/c_ccmv_cc_dr_dr.s b/sim/testsuite/sim/bfin/c_ccmv_cc_dr_dr.s new file mode 100644 index 0000000..b9e4fa6 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccmv_cc_dr_dr.s @@ -0,0 +1,124 @@ +//Original:/testcases/core/c_ccmv_cc_dr_dr/c_ccmv_cc_dr_dr.dsp +// Spec Reference: ccmv cc dreg = dreg +# mach: bfin + +.include "testutils.inc" + start + +R0 = 0; +ASTAT = R0; + + +imm32 r0, 0xa08d2301; +imm32 r1, 0xd0021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x60b61507; +imm32 r4, 0x50487609; +imm32 r5, 0x3005900b; +imm32 r6, 0x2a0c660d; +imm32 r7, 0xd90e108f; +IF CC R0 = R0; +IF CC R1 = R3; +IF CC R2 = R5; +IF CC R3 = R2; +CC = ! CC; +IF CC R4 = R6; +IF CC R5 = R1; +IF CC R6 = R7; +CC = ! CC; +IF CC R7 = R4; +CHECKREG r0, 0xA08D2301; +CHECKREG r1, 0xD0021053; +CHECKREG r2, 0x2F041405; +CHECKREG r3, 0x60B61507; +CHECKREG r4, 0x2A0C660D; +CHECKREG r5, 0xD0021053; +CHECKREG r6, 0xD90E108F; +CHECKREG r7, 0xD90E108F; + + +imm32 r0, 0x308d2301; +imm32 r1, 0xd4023053; +imm32 r2, 0x2f041405; +imm32 r3, 0x60f61507; +imm32 r4, 0xd0487f09; +imm32 r5, 0x300b900b; +imm32 r6, 0x2a0cd60d; +imm32 r7, 0xd90e189f; +IF CC R4 = R3; +IF CC R5 = R7; +IF CC R6 = R1; +IF CC R7 = R2; +CC = ! CC; +IF CC R0 = R6; +IF CC R1 = R5; +IF CC R2 = R4; +CC = ! CC; +IF CC R3 = R0; +CHECKREG r0, 0x2A0CD60D; +CHECKREG r1, 0x300B900B; +CHECKREG r2, 0xD0487F09; +CHECKREG r3, 0x60F61507; +CHECKREG r4, 0xD0487F09; +CHECKREG r5, 0x300B900B; +CHECKREG r6, 0x2A0CD60D; +CHECKREG r7, 0xD90E189F; + + +imm32 r0, 0x708d2301; +imm32 r1, 0xd8021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x65b61507; +imm32 r4, 0x59487609; +imm32 r5, 0x3005900b; +imm32 r6, 0x2abc660d; +imm32 r7, 0xd90e108f; +IF CC R0 = R2; +IF CC R1 = R3; +CC = ! CC; +IF CC R2 = R5; +IF CC R3 = R7; +CC = ! CC; +IF CC R4 = R1; +IF CC R5 = R4; +IF CC R6 = R7; +IF CC R7 = R6; +CHECKREG r0, 0x708D2301; +CHECKREG r1, 0xD8021053; +CHECKREG r2, 0x3005900B; +CHECKREG r3, 0xD90E108F; +CHECKREG r4, 0x59487609; +CHECKREG r5, 0x3005900B; +CHECKREG r6, 0x2ABC660D; +CHECKREG r7, 0xD90E108F; + + +imm32 r0, 0xc08d2301; +imm32 r1, 0xdb021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x64b61507; +imm32 r4, 0x50487609; +imm32 r5, 0x30f5900b; +imm32 r6, 0x2a4c660d; +imm32 r7, 0x895e108f; +IF CC R4 = R3; +IF CC R5 = R7; +CC = ! CC; +IF CC R6 = R2; +IF CC R7 = R6; +CC = ! CC; +IF CC R0 = R1; +IF CC R1 = R2; +IF CC R2 = R0; +IF CC R3 = R4; +CHECKREG r0, 0xC08D2301; +CHECKREG r1, 0xDB021053; +CHECKREG r2, 0x2F041405; +CHECKREG r3, 0x64B61507; +CHECKREG r4, 0x50487609; +CHECKREG r5, 0x30F5900B; +CHECKREG r6, 0x2F041405; +CHECKREG r7, 0x2F041405; + + +pass diff --git a/sim/testsuite/sim/bfin/c_ccmv_cc_dr_pr.s b/sim/testsuite/sim/bfin/c_ccmv_cc_dr_pr.s new file mode 100644 index 0000000..186a199 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccmv_cc_dr_pr.s @@ -0,0 +1,61 @@ +//Original:/proj/frio/dv/testcases/core/c_ccmv_cc_dr_pr/c_ccmv_cc_dr_pr.dsp +// Spec Reference: ccmv cc dpreg = dpreg +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x138d2301; + imm32 r1, 0x20421053; + imm32 r2, 0x3f051405; + imm32 r3, 0x40b66507; + imm32 r4, 0x50487709; + imm32 r5, 0x6005908b; + imm32 r6, 0x7a0c6609; + imm32 r7, 0x890e108f; + imm32 p1, 0x9d021053; + imm32 p2, 0xafb41405; + imm32 p3, 0xb0bf1507; + imm32 p4, 0xd0483609; + imm32 p5, 0xe005d00b; + imm32 sp, 0xfa0c667d; + imm32 fp, 0xc90e108f; + IF CC R0 = P0; + IF CC P1 = R3; + IF CC R2 = P5; + IF CC P2 = R2; + CC = ! CC; + IF CC P3 = R6; + IF CC R5 = P1; + IF CC P4 = R7; + CC = ! CC; + IF CC R7 = P4; + IF CC P5 = R3; + IF CC R6 = SP; + IF CC R3 = P2; + CC = ! CC; + IF CC SP = R6; + IF CC R1 = P5; + IF CC FP = R4; + CC = ! CC; + IF CC R3 = P3; + CHECKREG r0, 0x138D2301; + CHECKREG r1, 0xE005D00B; + CHECKREG r2, 0x3F051405; + CHECKREG r3, 0x40B66507; + CHECKREG r4, 0x50487709; + CHECKREG r5, 0x9D021053; + CHECKREG r6, 0x7A0C6609; + CHECKREG r7, 0x890E108F; + CHECKREG p1, 0x9D021053; + CHECKREG p2, 0xAFB41405; + CHECKREG p3, 0x7A0C6609; + CHECKREG p4, 0x890E108F; + CHECKREG p5, 0xE005D00B; + CHECKREG sp, 0x7A0C6609; + CHECKREG fp, 0x50487709; + + pass diff --git a/sim/testsuite/sim/bfin/c_ccmv_cc_pr_pr.s b/sim/testsuite/sim/bfin/c_ccmv_cc_pr_pr.s new file mode 100644 index 0000000..df93ccb --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccmv_cc_pr_pr.s @@ -0,0 +1,111 @@ +//Original:/proj/frio/dv/testcases/core/c_ccmv_cc_pr_pr/c_ccmv_cc_pr_pr.dsp +// Spec Reference: ccmv cc preg = preg +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 p1, 0xd0021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x60b61507; + imm32 p4, 0x50487609; + imm32 p5, 0x3005900b; + imm32 sp, 0x2a0c660d; + imm32 fp, 0xd90e108f; + IF CC P3 = P3; + IF CC P1 = P3; + IF CC P2 = P5; + IF CC P3 = P2; + CC = ! CC; + IF CC P4 = SP; + IF CC P5 = P1; + IF CC SP = FP; + CC = ! CC; + IF CC FP = P4; + CHECKREG p1, 0xD0021053; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x60B61507; + CHECKREG p4, 0x2A0C660D; + CHECKREG p5, 0xD0021053; + CHECKREG sp, 0xD90E108F; + CHECKREG fp, 0xD90E108F; + + imm32 p1, 0xd4023053; + imm32 p2, 0x2f041405; + imm32 p3, 0x60f61507; + imm32 p4, 0xd0487f09; + imm32 p5, 0x300b900b; + imm32 sp, 0x2a0cd60d; + imm32 fp, 0xd90e189f; + IF CC P4 = P3; + IF CC P5 = FP; + IF CC SP = P1; + IF CC FP = P2; + CC = ! CC; + IF CC P3 = SP; + IF CC P1 = P5; + IF CC P2 = P4; + CC = ! CC; + IF CC P3 = P2; + CHECKREG p1, 0x300B900B; + CHECKREG p2, 0xD0487F09; + CHECKREG p3, 0x2A0CD60D; + CHECKREG p4, 0xD0487F09; + CHECKREG p5, 0x300B900B; + CHECKREG sp, 0x2A0CD60D; + CHECKREG fp, 0xD90E189F; + + imm32 p1, 0xd8021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x65b61507; + imm32 p4, 0x59487609; + imm32 p5, 0x3005900b; + imm32 sp, 0x2abc660d; + imm32 fp, 0xd90e108f; + IF CC P3 = P2; + IF CC P1 = P3; + CC = ! CC; + IF CC P2 = P5; + IF CC P3 = FP; + CC = ! CC; + IF CC P4 = P1; + IF CC P5 = P4; + IF CC SP = FP; + IF CC FP = SP; + CHECKREG p1, 0xD8021053; + CHECKREG p2, 0x3005900B; + CHECKREG p3, 0xD90E108F; + CHECKREG p4, 0x59487609; + CHECKREG p5, 0x3005900B; + CHECKREG sp, 0x2ABC660D; + CHECKREG fp, 0xD90E108F; + + imm32 p1, 0xdb021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x64b61507; + imm32 p4, 0x50487609; + imm32 p5, 0x30f5900b; + imm32 sp, 0x2a4c660d; + imm32 fp, 0x895e108f; + IF CC P4 = P3; + IF CC P5 = FP; + CC = ! CC; + IF CC SP = P2; + IF CC FP = SP; + CC = ! CC; + IF CC P3 = P1; + IF CC P1 = P2; + IF CC P2 = P3; + IF CC P3 = P4; + CHECKREG p1, 0xDB021053; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x64B61507; + CHECKREG p4, 0x50487609; + CHECKREG p5, 0x30F5900B; + CHECKREG sp, 0x2F041405; + CHECKREG fp, 0x2F041405; + + pass diff --git a/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_dr.s b/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_dr.s new file mode 100644 index 0000000..94a6e32 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_dr.s @@ -0,0 +1,123 @@ +//Original:/testcases/core/c_ccmv_ncc_dr_dr/c_ccmv_ncc_dr_dr.dsp +// Spec Reference: ccmv !cc dreg = dreg +# mach: bfin + +.include "testutils.inc" + start +R0 = 0; +ASTAT = R0; + + +imm32 r0, 0x808d2301; +imm32 r1, 0x90021053; +imm32 r2, 0x21041405; +imm32 r3, 0x60261507; +imm32 r4, 0x50447609; +imm32 r5, 0xdfe5500b; +imm32 r6, 0x2a0c660d; +imm32 r7, 0xd90e1b8f; +IF !CC R0 = R0; +IF !CC R1 = R3; +IF !CC R2 = R5; +IF !CC R3 = R2; +CC = ! CC; +IF !CC R4 = R6; +IF !CC R5 = R1; +IF !CC R6 = R7; +CC = ! CC; +IF !CC R7 = R4; +CHECKREG r0, 0x808D2301; +CHECKREG r1, 0x60261507; +CHECKREG r2, 0xDFE5500B; +CHECKREG r3, 0xDFE5500B; +CHECKREG r4, 0x50447609; +CHECKREG r5, 0xDFE5500B; +CHECKREG r6, 0x2A0C660D; +CHECKREG r7, 0x50447609; + + +imm32 r0, 0x308d2301; +imm32 r1, 0xd4023053; +imm32 r2, 0x2f041405; +imm32 r3, 0x60f61507; +imm32 r4, 0xd0487f09; +imm32 r5, 0x300b900b; +imm32 r6, 0x2a0cd60d; +imm32 r7, 0xd90e189f; +IF !CC R4 = R3; +IF !CC R5 = R7; +IF !CC R6 = R1; +IF !CC R7 = R2; +CC = ! CC; +IF !CC R0 = R6; +IF !CC R1 = R5; +IF !CC R2 = R4; +CC = ! CC; +IF !CC R3 = R0; +CHECKREG r0, 0x308D2301; +CHECKREG r1, 0xD4023053; +CHECKREG r2, 0x2F041405; +CHECKREG r3, 0x308D2301; +CHECKREG r4, 0x60F61507; +CHECKREG r5, 0xD90E189F; +CHECKREG r6, 0xD4023053; +CHECKREG r7, 0x2F041405; + + +imm32 r0, 0x708d2301; +imm32 r1, 0xd8021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x65b61507; +imm32 r4, 0x59487609; +imm32 r5, 0x3005900b; +imm32 r6, 0x2abc660d; +imm32 r7, 0xd90e108f; +IF !CC R0 = R2; +IF !CC R1 = R3; +CC = ! CC; +IF !CC R2 = R5; +IF !CC R3 = R7; +CC = ! CC; +IF !CC R4 = R1; +IF !CC R5 = R4; +IF !CC R6 = R7; +IF !CC R7 = R6; +CHECKREG r0, 0x2F041405; +CHECKREG r1, 0x65B61507; +CHECKREG r2, 0x2F041405; +CHECKREG r3, 0x65B61507; +CHECKREG r4, 0x65B61507; +CHECKREG r5, 0x65B61507; +CHECKREG r6, 0xD90E108F; +CHECKREG r7, 0xD90E108F; + + +imm32 r0, 0xc08d2301; +imm32 r1, 0xdb021053; +imm32 r2, 0x2f041405; +imm32 r3, 0x64b61507; +imm32 r4, 0x50487609; +imm32 r5, 0x30f5900b; +imm32 r6, 0x2a4c660d; +imm32 r7, 0x895e108f; +IF !CC R4 = R3; +IF !CC R5 = R7; +CC = ! CC; +IF !CC R6 = R2; +IF !CC R7 = R6; +CC = ! CC; +IF !CC R0 = R1; +IF !CC R1 = R2; +IF !CC R2 = R0; +IF !CC R3 = R4; +CHECKREG r0, 0xDB021053; +CHECKREG r1, 0x2F041405; +CHECKREG r2, 0xDB021053; +CHECKREG r3, 0x64B61507; +CHECKREG r4, 0x64B61507; +CHECKREG r5, 0x895E108F; +CHECKREG r6, 0x2A4C660D; +CHECKREG r7, 0x895E108F; + + +pass diff --git a/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_pr.s b/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_pr.s new file mode 100644 index 0000000..1b981ac --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_pr.s @@ -0,0 +1,60 @@ +//Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_dr_pr/c_ccmv_ncc_dr_pr.dsp +// Spec Reference: ccmv !cc dpreg = dpreg +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x138d2301; + imm32 r1, 0x20421053; + imm32 r2, 0x3f051405; + imm32 r3, 0x40b66507; + imm32 r4, 0x50487709; + imm32 r5, 0x6005908b; + imm32 r6, 0x7a0c6609; + imm32 r7, 0x890e108f; + imm32 p1, 0x9d021053; + imm32 p2, 0xafb41405; + imm32 p3, 0xb0bf1507; + imm32 p4, 0xd0483609; + imm32 p5, 0xe005d00b; + imm32 sp, 0xfa0c667d; + imm32 fp, 0xc90e108f; + IF !CC R0 = P0; + CC = ! CC; + IF !CC P1 = R3; + IF !CC R2 = P5; + IF !CC P2 = R2; + IF !CC P3 = R6; + IF !CC R5 = P1; + CC = ! CC; + IF !CC P4 = R7; + IF !CC R7 = P4; + IF !CC P5 = R3; + IF !CC R6 = SP; + CC = ! CC; + IF !CC R3 = P2; + IF !CC SP = R6; + IF !CC R1 = P5; + CC = ! CC; + IF !CC FP = R4; + IF !CC R3 = P3; + CHECKREG r1, 0x20421053; + CHECKREG r2, 0x3F051405; + CHECKREG r3, 0xB0BF1507; + CHECKREG r4, 0x50487709; + CHECKREG r5, 0x6005908B; + CHECKREG r6, 0xFA0C667D; + CHECKREG r7, 0x890E108F; + CHECKREG p1, 0x9D021053; + CHECKREG p2, 0xAFB41405; + CHECKREG p3, 0xB0BF1507; + CHECKREG p4, 0x890E108F; + CHECKREG p5, 0x40B66507; + CHECKREG sp, 0xFA0C667D; + CHECKREG fp, 0x50487709; + + pass diff --git a/sim/testsuite/sim/bfin/c_ccmv_ncc_pr_pr.s b/sim/testsuite/sim/bfin/c_ccmv_ncc_pr_pr.s new file mode 100644 index 0000000..58c38ed --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ccmv_ncc_pr_pr.s @@ -0,0 +1,111 @@ +//Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_pr_pr/c_ccmv_ncc_pr_pr.dsp +// Spec Reference: ccmv !cc preg = preg +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 p1, 0xd0021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x60b61507; + imm32 p4, 0x50487609; + imm32 p5, 0x3005900b; + imm32 sp, 0x2a0c660d; + imm32 fp, 0xd90e108f; + IF !CC P3 = P3; + IF !CC P1 = P3; + CC = ! CC; + IF !CC P2 = P5; + IF !CC P3 = P2; + IF !CC P4 = SP; + IF !CC P5 = P1; + IF !CC SP = FP; + CC = ! CC; + IF !CC FP = P4; + CHECKREG p1, 0x60B61507; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x60B61507; + CHECKREG p4, 0x50487609; + CHECKREG p5, 0x3005900B; + CHECKREG sp, 0x2A0C660D; + CHECKREG fp, 0x50487609; + + imm32 p1, 0xd4023053; + imm32 p2, 0x2f041405; + imm32 p3, 0x60f61507; + imm32 p4, 0xd0487f09; + imm32 p5, 0x300b900b; + imm32 sp, 0x2a0cd60d; + imm32 fp, 0xd90e189f; + IF !CC P4 = P3; + IF !CC P5 = FP; + CC = ! CC; + IF !CC SP = P1; + IF !CC FP = P2; + IF !CC P3 = SP; + IF !CC P1 = P5; + IF !CC P2 = P4; + CC = ! CC; + IF !CC P3 = P2; + CHECKREG p1, 0xD4023053; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x2F041405; + CHECKREG p4, 0x60F61507; + CHECKREG p5, 0xD90E189F; + CHECKREG sp, 0x2A0CD60D; + CHECKREG fp, 0xD90E189F; + + imm32 p1, 0xd8021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x65b61507; + imm32 p4, 0x59487609; + imm32 p5, 0x3005900b; + imm32 sp, 0x2abc660d; + imm32 fp, 0xd90e108f; + IF !CC P3 = P2; + IF !CC P1 = P3; + CC = ! CC; + IF !CC P2 = P5; + IF !CC P3 = FP; + IF !CC P4 = P1; + IF !CC P5 = P4; + IF !CC SP = FP; + CC = ! CC; + IF !CC FP = SP; + CHECKREG p1, 0x2F041405; + CHECKREG p2, 0x2F041405; + CHECKREG p3, 0x2F041405; + CHECKREG p4, 0x59487609; + CHECKREG p5, 0x3005900B; + CHECKREG sp, 0x2ABC660D; + CHECKREG fp, 0x2ABC660D; + + imm32 p1, 0xdb021053; + imm32 p2, 0x2f041405; + imm32 p3, 0x64b61507; + imm32 p4, 0x50487609; + imm32 p5, 0x30f5900b; + imm32 sp, 0x2a4c660d; + imm32 fp, 0x895e108f; + IF !CC P4 = P3; + IF !CC P5 = FP; + IF !CC SP = P2; + IF !CC FP = SP; + CC = ! CC; + IF !CC P3 = P1; + IF !CC P1 = P2; + CC = ! CC; + IF !CC P2 = P3; + IF !CC P3 = P4; + CHECKREG p1, 0xDB021053; + CHECKREG p2, 0x64B61507; + CHECKREG p3, 0x64B61507; + CHECKREG p4, 0x64B61507; + CHECKREG p5, 0x895E108F; + CHECKREG sp, 0x2F041405; + CHECKREG fp, 0x2F041405; + + pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_dr_and_dr.s b/sim/testsuite/sim/bfin/c_comp3op_dr_and_dr.s new file mode 100644 index 0000000..567187b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_comp3op_dr_and_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_and_dr/c_comp3op_dr_and_dr.dsp +// Spec Reference: comp3op dregs & dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 & R0; +R1 = R0 & R1; +R2 = R0 & R2; +R3 = R0 & R3; +R4 = R0 & R4; +R5 = R0 & R5; +R6 = R0 & R6; +R7 = R0 & R7; +CHECKREG r0, 0x01234567; +CHECKREG r1, 0x01234567; +CHECKREG r2, 0x00200024; +CHECKREG r3, 0x00200024; +CHECKREG r4, 0x01014001; +CHECKREG r5, 0x00010145; +CHECKREG r6, 0x00224422; +CHECKREG r7, 0x00204460; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 & R0; +R1 = R1 & R1; +R2 = R1 & R2; +R3 = R1 & R3; +R4 = R1 & R4; +R5 = R1 & R5; +R6 = R1 & R6; +R7 = R1 & R7; +CHECKREG r0, 0x01231567; +CHECKREG r1, 0x89AB1DEF; +CHECKREG r2, 0x002818AC; +CHECKREG r3, 0x88A01024; +CHECKREG r4, 0x01011889; +CHECKREG r5, 0x08811145; +CHECKREG r6, 0x88221422; +CHECKREG r7, 0x00201468; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 & R0; +R1 = R2 & R1; +R2 = R2 & R2; +R3 = R2 & R3; +R4 = R2 & R4; +R5 = R2 & R5; +R6 = R2 & R6; +R7 = R2 & R7; +CHECKREG r0, 0x00200024; +CHECKREG r1, 0x0028882C; +CHECKREG r2, 0x56789A2C; +CHECKREG r3, 0x56701224; +CHECKREG r4, 0x02400828; +CHECKREG r5, 0x50100224; +CHECKREG r6, 0x10701020; +CHECKREG r7, 0x12301228; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 & R0; +R1 = R3 & R1; +R2 = R3 & R2; +R3 = R3 & R3; +R4 = R3 & R4; +R5 = R3 & R5; +R6 = R3 & R6; +R7 = R3 & R7; +CHECKREG r0, 0x00200023; +CHECKREG r1, 0x88A00023; +CHECKREG r2, 0x56701233; +CHECKREG r3, 0xDEF01233; +CHECKREG r4, 0x02400013; +CHECKREG r5, 0x58900203; +CHECKREG r6, 0x98701033; +CHECKREG r7, 0x12301233; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 & R0; +R1 = R4 & R1; +R2 = R4 & R2; +R3 = R4 & R3; +R4 = R4 & R4; +R5 = R4 & R5; +R6 = R4 & R6; +R7 = R4 & R7; +CHECKREG r0, 0x41014001; +CHECKREG r1, 0x41014889; +CHECKREG r2, 0x42400898; +CHECKREG r3, 0x42400010; +CHECKREG r4, 0x43456899; +CHECKREG r5, 0x40012001; +CHECKREG r6, 0x40444010; +CHECKREG r7, 0x42044018; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 & R0; +R1 = R5 & R1; +R2 = R5 & R2; +R3 = R5 & R3; +R4 = R5 & R4; +R5 = R5 & R5; +R6 = R5 & R6; +R7 = R5 & R7; +CHECKREG r0, 0x05010145; +CHECKREG r1, 0x05810145; +CHECKREG r2, 0x55100204; +CHECKREG r3, 0x55900204; +CHECKREG r4, 0x25012001; +CHECKREG r5, 0x75912345; +CHECKREG r6, 0x15100000; +CHECKREG r7, 0x15100240; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 & R0; +R1 = R6 & R1; +R2 = R6 & R2; +R3 = R6 & R3; +R4 = R6 & R4; +R5 = R6 & R5; +R6 = R6 & R6; +R7 = R6 & R7; +CHECKREG r0, 0x00264422; +CHECKREG r1, 0x88264422; +CHECKREG r2, 0x10761030; +CHECKREG r3, 0x98761030; +CHECKREG r4, 0x00464010; +CHECKREG r5, 0x18160000; +CHECKREG r6, 0x98765432; +CHECKREG r7, 0x10365430; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 & R0; +R1 = R7 & R1; +R2 = R7 & R2; +R3 = R7 & R3; +R4 = R7 & R4; +R5 = R7 & R5; +R6 = R7 & R6; +R7 = R7 & R7; +CHECKREG r0, 0x00205460; +CHECKREG r1, 0x00205468; +CHECKREG r2, 0x12305238; +CHECKREG r3, 0x12305230; +CHECKREG r4, 0x02045018; +CHECKREG r5, 0x10105240; +CHECKREG r6, 0x10345430; +CHECKREG r7, 0x12345678; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 & R0; +R1 = R2 & R0; +R2 = R3 & R0; +R3 = R4 & R0; +R4 = R5 & R0; +R5 = R6 & R0; +R6 = R7 & R0; +R7 = R0 & R0; +CHECKREG r0, 0x01234567; +CHECKREG r1, 0x00000024; +CHECKREG r2, 0x00210024; +CHECKREG r3, 0x01010001; +CHECKREG r4, 0x00010145; +CHECKREG r5, 0x00224402; +CHECKREG r6, 0x00204461; +CHECKREG r7, 0x01234567; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 & R1; +R1 = R3 & R1; +R2 = R4 & R1; +R3 = R5 & R1; +R4 = R6 & R1; +R5 = R7 & R1; +R6 = R0 & R1; +R7 = R1 & R1; +CHECKREG r0, 0x002818AC; +CHECKREG r1, 0x08201024; +CHECKREG r2, 0x00001000; +CHECKREG r3, 0x08000004; +CHECKREG r4, 0x08201020; +CHECKREG r5, 0x00201020; +CHECKREG r6, 0x00201024; +CHECKREG r7, 0x08201024; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R4 & R2; +R1 = R5 & R2; +R2 = R6 & R2; +R3 = R7 & R2; +R4 = R0 & R2; +R5 = R1 & R2; +R6 = R2 & R2; +R7 = R3 & R2; +CHECKREG r0, 0x02410228; +CHECKREG r1, 0x50310224; +CHECKREG r2, 0x10731020; +CHECKREG r3, 0x10301020; +CHECKREG r4, 0x00410020; +CHECKREG r5, 0x10310020; +CHECKREG r6, 0x10731020; +CHECKREG r7, 0x10301020; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R5 & R3; +R1 = R6 & R3; +R2 = R7 & R3; +R3 = R0 & R3; +R4 = R1 & R3; +R5 = R2 & R3; +R6 = R3 & R3; +R7 = R4 & R3; +CHECKREG r0, 0x48400200; +CHECKREG r1, 0x08704030; +CHECKREG r2, 0x02304233; +CHECKREG r3, 0x48400200; +CHECKREG r4, 0x08400000; +CHECKREG r5, 0x00000200; +CHECKREG r6, 0x48400200; +CHECKREG r7, 0x08400000; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R6 & R4; +R1 = R7 & R4; +R2 = R0 & R4; +R3 = R1 & R4; +R4 = R2 & R4; +R5 = R3 & R4; +R6 = R4 & R4; +R7 = R5 & R4; +CHECKREG r0, 0x40444010; +CHECKREG r1, 0x42054018; +CHECKREG r2, 0x40444010; +CHECKREG r3, 0x42054018; +CHECKREG r4, 0x40444010; +CHECKREG r5, 0x40044010; +CHECKREG r6, 0x40444010; +CHECKREG r7, 0x40044010; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R7 & R5; +R1 = R0 & R5; +R2 = R1 & R5; +R3 = R2 & R5; +R4 = R3 & R5; +R5 = R4 & R5; +R6 = R5 & R5; +R7 = R6 & R5; +CHECKREG r0, 0x15140240; +CHECKREG r1, 0x15140240; +CHECKREG r2, 0x15140240; +CHECKREG r3, 0x15140240; +CHECKREG r4, 0x15140240; +CHECKREG r5, 0x15140240; +CHECKREG r6, 0x15140240; +CHECKREG r7, 0x15140240; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 & R6; +R1 = R0 & R6; +R2 = R1 & R6; +R3 = R2 & R6; +R4 = R3 & R6; +R5 = R4 & R6; +R6 = R5 & R6; +R7 = R6 & R6; +CHECKREG r0, 0x10365430; +CHECKREG r1, 0x10365430; +CHECKREG r2, 0x10365430; +CHECKREG r3, 0x10365430; +CHECKREG r4, 0x10365430; +CHECKREG r5, 0x10365430; +CHECKREG r6, 0x10365430; +CHECKREG r7, 0x10365430; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 & R7; +R1 = R2 & R7; +R2 = R3 & R7; +R3 = R4 & R7; +R4 = R5 & R7; +R5 = R6 & R7; +R6 = R7 & R7; +R7 = R0 & R7; +CHECKREG r0, 0x00200068; +CHECKREG r1, 0x12000208; +CHECKREG r2, 0x02300238; +CHECKREG r3, 0x00048018; +CHECKREG r4, 0x10000040; +CHECKREG r5, 0x10300400; +CHECKREG r6, 0x12348678; +CHECKREG r7, 0x00200068; + + +pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_dr_minus_dr.s b/sim/testsuite/sim/bfin/c_comp3op_dr_minus_dr.s new file mode 100644 index 0000000..ebf2b0b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_comp3op_dr_minus_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_minus_dr/c_comp3op_dr_minus_dr.dsp +// Spec Reference: comp3op dregs - dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 - R0; +R1 = R0 - R1; +R2 = R0 - R2; +R3 = R0 - R3; +R4 = R0 - R4; +R5 = R0 - R5; +R6 = R0 - R6; +R7 = R0 - R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x76543211; +CHECKREG r2, 0xA9876544; +CHECKREG r3, 0x210FEDCC; +CHECKREG r4, 0xDCBA9767; +CHECKREG r5, 0x876EDCBB; +CHECKREG r6, 0x6789ABCE; +CHECKREG r7, 0xEDCBA988; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 - R0; +R1 = R1 - R1; +R2 = R1 - R2; +R3 = R1 - R3; +R4 = R1 - R4; +R5 = R1 - R5; +R6 = R1 - R6; +R7 = R1 - R7; +CHECKREG r0, 0x88880888; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xA987E544; +CHECKREG r3, 0x210FEDCC; +CHECKREG r4, 0xDCBAE767; +CHECKREG r5, 0x876EECBB; +CHECKREG r6, 0x6789EBCE; +CHECKREG r7, 0xEDCBE988; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 - R0; +R1 = R2 - R1; +R2 = R2 - R2; +R3 = R2 - R3; +R4 = R2 - R4; +R5 = R2 - R5; +R6 = R2 - R6; +R7 = R2 - R7; +CHECKREG r0, 0x55555505; +CHECKREG r1, 0xCCCCCCFD; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x210FEDDC; +CHECKREG r4, 0xDCBA97D7; +CHECKREG r5, 0x876EDCDB; +CHECKREG r6, 0x6789ABDE; +CHECKREG r7, 0xEDCBA9D8; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 - R0; +R1 = R3 - R1; +R2 = R3 - R2; +R3 = R3 - R3; +R4 = R3 - R4; +R5 = R3 - R5; +R6 = R3 - R6; +R7 = R3 - R7; +CHECKREG r0, 0xDDCCCCD0; +CHECKREG r1, 0x55444450; +CHECKREG r2, 0x88777780; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xDCBA976D; +CHECKREG r5, 0x876EDCBD; +CHECKREG r6, 0x6789ABCD; +CHECKREG r7, 0xEDCBA98D; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 - R0; +R1 = R4 - R1; +R2 = R4 - R2; +R3 = R4 - R3; +R4 = R4 - R4; +R5 = R4 - R5; +R6 = R4 - R6; +R7 = R4 - R7; +CHECKREG r0, 0x02222332; +CHECKREG r1, 0xF9999AAA; +CHECKREG r2, 0xFCCCCDDD; +CHECKREG r3, 0xF4555665; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0xB76EDCBB; +CHECKREG r6, 0xB789ABCE; +CHECKREG r7, 0xBDCBA988; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 - R0; +R1 = R5 - R1; +R2 = R5 - R2; +R3 = R5 - R3; +R4 = R5 - R4; +R5 = R5 - R5; +R6 = R5 - R6; +R7 = R5 - R7; +CHECKREG r0, 0x706DDDDE; +CHECKREG r1, 0xEFE55556; +CHECKREG r2, 0x20188889; +CHECKREG r3, 0x9FA11111; +CHECKREG r4, 0x504BBAAC; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x6A89ABCE; +CHECKREG r7, 0xEACBA988; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 - R0; +R1 = R6 - R1; +R2 = R6 - R2; +R3 = R6 - R3; +R4 = R6 - R4; +R5 = R6 - R5; +R6 = R6 - R6; +R7 = R6 - R7; +CHECKREG r0, 0x97500ECB; +CHECKREG r1, 0x0ECF8643; +CHECKREG r2, 0x41FFB976; +CHECKREG r3, 0xB98041FE; +CHECKREG r4, 0x752FEB99; +CHECKREG r5, 0x1FE030ED; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xEDC9A988; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 - R0; +R1 = R7 - R1; +R2 = R7 - R2; +R3 = R7 - R3; +R4 = R7 - R4; +R5 = R7 - R5; +R6 = R7 - R6; +R7 = R7 - R7; +CHECKREG r0, 0x1110E111; +CHECKREG r1, 0x8888D889; +CHECKREG r2, 0xBBBBDBBC; +CHECKREG r3, 0x3343E444; +CHECKREG r4, 0xEEEEDDDF; +CHECKREG r5, 0x99A2E333; +CHECKREG r6, 0x79BDE246; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 - R0; +R1 = R2 - R0; +R2 = R3 - R0; +R3 = R4 - R0; +R4 = R5 - R0; +R5 = R6 - R0; +R6 = R7 - R0; +R7 = R0 - R0; +CHECKREG r0, 0x70888888; +CHECKREG r1, 0xE5901234; +CHECKREG r2, 0x6E6889AC; +CHECKREG r3, 0xB2BC9011; +CHECKREG r4, 0x080898BD; +CHECKREG r5, 0x27EDCB8A; +CHECKREG r6, 0xA1ABCDE9; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 - R1; +R1 = R3 - R1; +R2 = R4 - R1; +R3 = R5 - R1; +R4 = R6 - R1; +R5 = R7 - R1; +R6 = R0 - R1; +R7 = R1 - R1; +CHECKREG r0, 0x28CCFCCD; +CHECKREG r1, 0xB474F445; +CHECKREG r2, 0x6ECD2454; +CHECKREG r3, 0xC41C2F00; +CHECKREG r4, 0xE4011DED; +CHECKREG r5, 0x5DBF21E3; +CHECKREG r6, 0x74580888; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R4 - R2; +R1 = R5 - R2; +R2 = R6 - R2; +R3 = R7 - R2; +R4 = R0 - R2; +R5 = R1 - R2; +R6 = R2 - R2; +R7 = R3 - R2; +CHECKREG r0, 0xCCD1C8FD; +CHECKREG r1, 0x21BD8909; +CHECKREG r2, 0x41FFB9F7; +CHECKREG r3, 0xD0347C31; +CHECKREG r4, 0x8AD20F06; +CHECKREG r5, 0xDFBDCF12; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x8E34C23A; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R5 - R3; +R1 = R6 - R3; +R2 = R7 - R3; +R3 = R0 - R3; +R4 = R1 - R3; +R5 = R2 - R3; +R6 = R3 - R3; +R7 = R4 - R3; +CHECKREG r0, 0x2950E111; +CHECKREG r1, 0x49841201; +CHECKREG r2, 0xC3440440; +CHECKREG r3, 0xDA609EDE; +CHECKREG r4, 0x6F237323; +CHECKREG r5, 0xE8E36562; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x94C2D445; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R6 - R4; +R1 = R7 - R4; +R2 = R0 - R4; +R3 = R1 - R4; +R4 = R2 - R4; +R5 = R3 - R4; +R6 = R4 - R4; +R7 = R5 - R4; +CHECKREG r0, 0xF510EB99; +CHECKREG r1, 0xEEEFEDDF; +CHECKREG r2, 0xA1CB8300; +CHECKREG r3, 0x9BAA8546; +CHECKREG r4, 0x4E861A67; +CHECKREG r5, 0x4D246ADF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFE9E5078; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R7 - R5; +R1 = R0 - R5; +R2 = R1 - R5; +R3 = R2 - R5; +R4 = R3 - R5; +R5 = R4 - R5; +R6 = R5 - R5; +R7 = R6 - R5; +CHECKREG r0, 0x9F9E3333; +CHECKREG r1, 0x2A080FEE; +CHECKREG r2, 0xB471ECA9; +CHECKREG r3, 0x3EDBC964; +CHECKREG r4, 0xC945A61F; +CHECKREG r5, 0x53AF82DA; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xAC507D26; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 - R6; +R1 = R0 - R6; +R2 = R1 - R6; +R3 = R2 - R6; +R4 = R3 - R6; +R5 = R4 - R6; +R6 = R5 - R6; +R7 = R6 - R6; +CHECKREG r0, 0x79C10246; +CHECKREG r1, 0xE14AAE14; +CHECKREG r2, 0x48D459E2; +CHECKREG r3, 0xB05E05B0; +CHECKREG r4, 0x17E7B17E; +CHECKREG r5, 0x7F715D4C; +CHECKREG r6, 0xE6FB091A; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 - R7; +R1 = R2 - R7; +R2 = R3 - R7; +R3 = R4 - R7; +R4 = R5 - R7; +R5 = R6 - R7; +R6 = R7 - R7; +R7 = R0 - R7; +CHECKREG r0, 0x7676F277; +CHECKREG r1, 0x4453F414; +CHECKREG r2, 0x7CC3EBC0; +CHECKREG r3, 0x16110221; +CHECKREG r4, 0x664CF1CD; +CHECKREG r5, 0x8643EE0A; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x64426BFF; + + +pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_dr_mix.s b/sim/testsuite/sim/bfin/c_comp3op_dr_mix.s new file mode 100644 index 0000000..4920918 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_comp3op_dr_mix.s @@ -0,0 +1,237 @@ +//Original:/testcases/core/c_comp3op_dr_mix/c_comp3op_dr_mix.dsp +// Spec Reference: comp3op dregs mix +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 + R0; +R1 = R0 - R1; +R2 = R0 & R2; +R3 = R0 | R3; +R4 = R0 & R4; +R5 = R0 & R5; +R6 = R0 | R6; +R7 = R0 & R7; +CHECKREG r0, 0x02468ACE; +CHECKREG r1, 0x789ABCDF; +CHECKREG r2, 0x02408A8C; +CHECKREG r3, 0xDEF69AFE; +CHECKREG r4, 0x02440888; +CHECKREG r5, 0x00000244; +CHECKREG r6, 0x9A76DEFE; +CHECKREG r7, 0x02040248; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 + R0; +R1 = R1 - R1; +R2 = R1 & R2; +R3 = R1 | R3; +R4 = R1 & R4; +R5 = R1 & R5; +R6 = R1 | R6; +R7 = R1 & R7; +CHECKREG r0, 0x8ACE3356; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xDEF01234; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x98761432; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 + R0; +R1 = R2 - R1; +R2 = R2 & R2; +R3 = R2 | R3; +R4 = R2 & R4; +R5 = R2 & R5; +R6 = R2 | R6; +R7 = R2 & R7; +CHECKREG r0, 0x579BDF53; +CHECKREG r1, 0xCCCCCCFD; +CHECKREG r2, 0x56789A2C; +CHECKREG r3, 0xDEF89A2C; +CHECKREG r4, 0x02400828; +CHECKREG r5, 0x50100224; +CHECKREG r6, 0xDE7EDE2E; +CHECKREG r7, 0x12301228; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 + R0; +R1 = R3 - R1; +R2 = R3 & R2; +R3 = R3 | R3; +R4 = R3 & R4; +R5 = R3 - R5; +R6 = R3 | R6; +R7 = R3 & R7; +CHECKREG r0, 0xE0135796; +CHECKREG r1, 0x55444450; +CHECKREG r2, 0x56701233; +CHECKREG r3, 0xDEF01233; +CHECKREG r4, 0x02400013; +CHECKREG r5, 0x665EEEF0; +CHECKREG r6, 0xDEF65633; +CHECKREG r7, 0x12301233; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 + R0; +R1 = R4 - R1; +R2 = R4 & R2; +R3 = R4 | R3; +R4 = R4 & R4; +R5 = R4 & R5; +R6 = R4 | R6; +R7 = R4 & R7; +CHECKREG r0, 0x8468AE00; +CHECKREG r1, 0xF9999AAA; +CHECKREG r2, 0x42400898; +CHECKREG r3, 0x4FF57ABD; +CHECKREG r4, 0x43456899; +CHECKREG r5, 0x40012001; +CHECKREG r6, 0x4B777CBB; +CHECKREG r7, 0x42044018; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 + R0; +R1 = R5 - R1; +R2 = R5 & R2; +R3 = R5 | R3; +R4 = R5 & R4; +R5 = R5 & R5; +R6 = R5 | R6; +R7 = R5 & R7; +CHECKREG r0, 0x7AB468AC; +CHECKREG r1, 0xEFE55556; +CHECKREG r2, 0x55100204; +CHECKREG r3, 0xF5F13375; +CHECKREG r4, 0x25012001; +CHECKREG r5, 0x75912345; +CHECKREG r6, 0xF5F77777; +CHECKREG r7, 0x15100240; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 + R0; +R1 = R6 - R1; +R2 = R6 & R2; +R3 = R6 | R3; +R4 = R6 & R4; +R5 = R6 & R5; +R6 = R6 | R6; +R7 = R6 & R7; +CHECKREG r0, 0x999C9999; +CHECKREG r1, 0x0ECF8643; +CHECKREG r2, 0x10761030; +CHECKREG r3, 0xDEF65636; +CHECKREG r4, 0x00464010; +CHECKREG r5, 0x18160000; +CHECKREG r6, 0x98765432; +CHECKREG r7, 0x10365430; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 + R0; +R1 = R7 - R1; +R2 = R7 & R2; +R3 = R7 | R3; +R4 = R7 & R4; +R5 = R7 - R5; +R6 = R7 | R6; +R7 = R7 & R7; +CHECKREG r0, 0x1357CBDF; +CHECKREG r1, 0x8888D889; +CHECKREG r2, 0x12305238; +CHECKREG r3, 0xDEF4767C; +CHECKREG r4, 0x02045018; +CHECKREG r5, 0x99A2E333; +CHECKREG r6, 0x9A76767A; +CHECKREG r7, 0x12345678; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; + + +R0 = R1 + R2; +R1 = R3 - R2; +R2 = R4 & R3; +R3 = R5 | R4; +R4 = R6 & R7; +CHECKREG r0, 0x00060008; +CHECKREG r1, 0x00020002; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x000A000B; +CHECKREG r4, 0x000C000D; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000e000f; + + +pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_dr_or_dr.s b/sim/testsuite/sim/bfin/c_comp3op_dr_or_dr.s new file mode 100644 index 0000000..36e6401 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_comp3op_dr_or_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_or_dr/c_comp3op_dr_or_dr.dsp +// Spec Reference: comp3op dregs | dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 | R0; +R1 = R0 | R1; +R2 = R0 | R2; +R3 = R0 | R3; +R4 = R0 | R4; +R5 = R0 | R5; +R6 = R0 | R6; +R7 = R0 | R7; +CHECKREG r0, 0x01234567; +CHECKREG r1, 0x89ABCDEF; +CHECKREG r2, 0x577BDFFF; +CHECKREG r3, 0xDFF35777; +CHECKREG r4, 0x23676DFF; +CHECKREG r5, 0x79B36767; +CHECKREG r6, 0x99775577; +CHECKREG r7, 0x1337577F; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 | R0; +R1 = R1 | R1; +R2 = R1 | R2; +R3 = R1 | R3; +R4 = R1 | R4; +R5 = R1 | R5; +R6 = R1 | R6; +R7 = R1 | R7; +CHECKREG r0, 0x89AB1DEF; +CHECKREG r1, 0x89AB1DEF; +CHECKREG r2, 0xDFFB1FFF; +CHECKREG r3, 0xDFFB1FFF; +CHECKREG r4, 0xABEF1DFF; +CHECKREG r5, 0xF9BB1FEF; +CHECKREG r6, 0x99FF1DFF; +CHECKREG r7, 0x9BBF1FFF; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 | R0; +R1 = R2 | R1; +R2 = R2 | R2; +R3 = R2 | R3; +R4 = R2 | R4; +R5 = R2 | R5; +R6 = R2 | R6; +R7 = R2 | R7; +CHECKREG r0, 0x577BDF2F; +CHECKREG r1, 0xDFFBDF2F; +CHECKREG r2, 0x56789A2C; +CHECKREG r3, 0xDEF89A2C; +CHECKREG r4, 0x777DFA2D; +CHECKREG r5, 0x7EF9BB2D; +CHECKREG r6, 0xDE7EDE2E; +CHECKREG r7, 0x567CDE2C; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 | R0; +R1 = R3 | R1; +R2 = R3 | R2; +R3 = R3 | R3; +R4 = R3 | R4; +R5 = R3 | R5; +R6 = R3 | R6; +R7 = R3 | R7; +CHECKREG r0, 0xDFF35773; +CHECKREG r1, 0xDFFBDFF3; +CHECKREG r2, 0xDEF89AB3; +CHECKREG r3, 0xDEF01233; +CHECKREG r4, 0xFFF57AB3; +CHECKREG r5, 0xFEF13373; +CHECKREG r6, 0xDEF65633; +CHECKREG r7, 0xDEF45673; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 | R0; +R1 = R4 | R1; +R2 = R4 | R2; +R3 = R4 | R3; +R4 = R4 | R4; +R5 = R4 | R5; +R6 = R4 | R6; +R7 = R4 | R7; +CHECKREG r0, 0x43676DFF; +CHECKREG r1, 0x4BEFEDFF; +CHECKREG r2, 0x477DFABD; +CHECKREG r3, 0x4FF57ABD; +CHECKREG r4, 0x43456899; +CHECKREG r5, 0x4BD56BDD; +CHECKREG r6, 0x4B777CBB; +CHECKREG r7, 0x43757EF9; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 | R0; +R1 = R5 | R1; +R2 = R5 | R2; +R3 = R5 | R3; +R4 = R5 | R4; +R5 = R5 | R5; +R6 = R5 | R6; +R7 = R5 | R7; +CHECKREG r0, 0x75B36767; +CHECKREG r1, 0xF5BBEFEF; +CHECKREG r2, 0x75F9BBFD; +CHECKREG r3, 0xF5F13375; +CHECKREG r4, 0x75D56BDD; +CHECKREG r5, 0x75912345; +CHECKREG r6, 0xF5F77777; +CHECKREG r7, 0x75B5777D; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 | R0; +R1 = R6 | R1; +R2 = R6 | R2; +R3 = R6 | R3; +R4 = R6 | R4; +R5 = R6 | R5; +R6 = R6 | R6; +R7 = R6 | R7; +CHECKREG r0, 0x99765577; +CHECKREG r1, 0x99F6DDFF; +CHECKREG r2, 0xDE76DEBE; +CHECKREG r3, 0xDEF65636; +CHECKREG r4, 0xBB767CBB; +CHECKREG r5, 0xF8F67777; +CHECKREG r6, 0x98765432; +CHECKREG r7, 0x9A76567A; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 | R0; +R1 = R7 | R1; +R2 = R7 | R2; +R3 = R7 | R3; +R4 = R7 | R4; +R5 = R7 | R5; +R6 = R7 | R6; +R7 = R7 | R7; +CHECKREG r0, 0x1337777F; +CHECKREG r1, 0x9BBF7FFF; +CHECKREG r2, 0x567C7EFC; +CHECKREG r3, 0xDEF4767C; +CHECKREG r4, 0x33757EF9; +CHECKREG r5, 0x7AB5777D; +CHECKREG r6, 0x9A76767A; +CHECKREG r7, 0x12345678; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 | R0; +R1 = R2 | R0; +R2 = R3 | R0; +R3 = R4 | R0; +R4 = R5 | R0; +R5 = R6 | R0; +R6 = R7 | R0; +R7 = R0 | R0; +CHECKREG r0, 0x91ABCDEF; +CHECKREG r1, 0xD7BBDFFF; +CHECKREG r2, 0xDFFBDFFF; +CHECKREG r3, 0xB3EFDDFF; +CHECKREG r4, 0xF9BBEDEF; +CHECKREG r5, 0x99FFDDFF; +CHECKREG r6, 0x93BFDFFF; +CHECKREG r7, 0x91ABCDEF; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 | R1; +R1 = R3 | R1; +R2 = R4 | R1; +R3 = R5 | R1; +R4 = R6 | R1; +R5 = R7 | R1; +R6 = R0 | R1; +R7 = R1 | R1; +CHECKREG r0, 0x7BFB1FFF; +CHECKREG r1, 0xFFAB1FFF; +CHECKREG r2, 0xFFEB1FFF; +CHECKREG r3, 0xFFBB3FFF; +CHECKREG r4, 0xFFFF1FFF; +CHECKREG r5, 0xFFBF1FFF; +CHECKREG r6, 0xFFFB1FFF; +CHECKREG r7, 0xFFAB1FFF; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R4 | R2; +R1 = R5 | R2; +R2 = R6 | R2; +R3 = R7 | R2; +R4 = R0 | R2; +R5 = R1 | R2; +R6 = R2 | R2; +R7 = R3 | R2; +CHECKREG r0, 0x7777FB2D; +CHECKREG r1, 0x7E73BB3D; +CHECKREG r2, 0xDE73DE2F; +CHECKREG r3, 0xDE77FE2F; +CHECKREG r4, 0xFF77FF2F; +CHECKREG r5, 0xFE73FF3F; +CHECKREG r6, 0xDE73DE2F; +CHECKREG r7, 0xDE77FE2F; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R5 | R3; +R1 = R6 | R3; +R2 = R7 | R3; +R3 = R0 | R3; +R4 = R1 | R3; +R5 = R2 | R3; +R6 = R3 | R3; +R7 = R4 | R3; +CHECKREG r0, 0x7EF16377; +CHECKREG r1, 0xDEF45637; +CHECKREG r2, 0x5EF44673; +CHECKREG r3, 0x7EF16377; +CHECKREG r4, 0xFEF57777; +CHECKREG r5, 0x7EF56777; +CHECKREG r6, 0x7EF16377; +CHECKREG r7, 0xFEF57777; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R6 | R4; +R1 = R7 | R4; +R2 = R0 | R4; +R3 = R1 | R4; +R4 = R2 | R4; +R5 = R3 | R4; +R6 = R4 | R4; +R7 = R5 | R4; +CHECKREG r0, 0x5B577CBB; +CHECKREG r1, 0x53757EF9; +CHECKREG r2, 0x5B577CBB; +CHECKREG r3, 0x53757EF9; +CHECKREG r4, 0x5B577CBB; +CHECKREG r5, 0x5B777EFB; +CHECKREG r6, 0x5B577CBB; +CHECKREG r7, 0x5B777EFB; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R7 | R5; +R1 = R0 | R5; +R2 = R1 | R5; +R3 = R2 | R5; +R4 = R3 | R5; +R5 = R4 | R5; +R6 = R5 | R5; +R7 = R6 | R5; +CHECKREG r0, 0x75B6777D; +CHECKREG r1, 0x75B6777D; +CHECKREG r2, 0x75B6777D; +CHECKREG r3, 0x75B6777D; +CHECKREG r4, 0x75B6777D; +CHECKREG r5, 0x75B6777D; +CHECKREG r6, 0x75B6777D; +CHECKREG r7, 0x75B6777D; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 | R6; +R1 = R0 | R6; +R2 = R1 | R6; +R3 = R2 | R6; +R4 = R3 | R6; +R5 = R4 | R6; +R6 = R5 | R6; +R7 = R6 | R6; +CHECKREG r0, 0x9A77567A; +CHECKREG r1, 0x9A77567A; +CHECKREG r2, 0x9A77567A; +CHECKREG r3, 0x9A77567A; +CHECKREG r4, 0x9A77567A; +CHECKREG r5, 0x9A77567A; +CHECKREG r6, 0x9A77567A; +CHECKREG r7, 0x9A77567A; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 | R7; +R1 = R2 | R7; +R2 = R3 | R7; +R3 = R4 | R7; +R4 = R5 | R7; +R5 = R6 | R7; +R6 = R7 | R7; +R7 = R0 | R7; +CHECKREG r0, 0x9ABFFEFF; +CHECKREG r1, 0x56BCFEFC; +CHECKREG r2, 0x9EFCF678; +CHECKREG r3, 0x3A758EF9; +CHECKREG r4, 0x7AB5FE7D; +CHECKREG r5, 0x9A7CF6FA; +CHECKREG r6, 0x12348678; +CHECKREG r7, 0x9ABFFEFF; + + +pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_dr_plus_dr.s b/sim/testsuite/sim/bfin/c_comp3op_dr_plus_dr.s new file mode 100644 index 0000000..fff4cb7 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_comp3op_dr_plus_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_plus_dr/c_comp3op_dr_plus_dr.dsp +// Spec Reference: comp3op dregs + dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 + R0; +R1 = R0 + R1; +R2 = R0 + R2; +R3 = R0 + R3; +R4 = R0 + R4; +R5 = R0 + R5; +R6 = R0 + R6; +R7 = R0 + R7; +CHECKREG r0, 0x02468ACE; +CHECKREG r1, 0x8BF258BD; +CHECKREG r2, 0x58BF258A; +CHECKREG r3, 0xE1369D02; +CHECKREG r4, 0x258BF367; +CHECKREG r5, 0x7AD7AE13; +CHECKREG r6, 0x9ABCDF00; +CHECKREG r7, 0x147AE146; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 + R0; +R1 = R1 + R1; +R2 = R1 + R2; +R3 = R1 + R3; +R4 = R1 + R4; +R5 = R1 + R5; +R6 = R1 + R6; +R7 = R1 + R7; +CHECKREG r0, 0x8ACE3356; +CHECKREG r1, 0x13563BDE; +CHECKREG r2, 0x69CE569A; +CHECKREG r3, 0xF2464E12; +CHECKREG r4, 0x369B5477; +CHECKREG r5, 0x8BE74F23; +CHECKREG r6, 0xABCC5010; +CHECKREG r7, 0x258A5256; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 + R0; +R1 = R2 + R1; +R2 = R2 + R2; +R3 = R2 + R3; +R4 = R2 + R4; +R5 = R2 + R5; +R6 = R2 + R6; +R7 = R2 + R7; +CHECKREG r0, 0x579BDF53; +CHECKREG r1, 0xE024675B; +CHECKREG r2, 0xACF13458; +CHECKREG r3, 0x8BE1467C; +CHECKREG r4, 0xD0369C81; +CHECKREG r5, 0x2582577D; +CHECKREG r6, 0x4567887A; +CHECKREG r7, 0xBF258A80; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 + R0; +R1 = R3 + R1; +R2 = R3 + R2; +R3 = R3 + R3; +R4 = R3 + R4; +R5 = R3 + R5; +R6 = R3 + R6; +R7 = R3 + R7; +CHECKREG r0, 0xE0135796; +CHECKREG r1, 0x689BE016; +CHECKREG r2, 0x3568ACE6; +CHECKREG r3, 0xBDE02466; +CHECKREG r4, 0xE1258CF9; +CHECKREG r5, 0x367147A9; +CHECKREG r6, 0x56567899; +CHECKREG r7, 0xD0147AD9; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 + R0; +R1 = R4 + R1; +R2 = R4 + R2; +R3 = R4 + R3; +R4 = R4 + R4; +R5 = R4 + R5; +R6 = R4 + R6; +R7 = R4 + R7; +CHECKREG r0, 0x8468AE00; +CHECKREG r1, 0x8CF13688; +CHECKREG r2, 0x89BE0355; +CHECKREG r3, 0x92357ACD; +CHECKREG r4, 0x868AD132; +CHECKREG r5, 0xCF1BF477; +CHECKREG r6, 0xCF012564; +CHECKREG r7, 0xC8BF27AA; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 + R0; +R1 = R5 + R1; +R2 = R5 + R2; +R3 = R5 + R3; +R4 = R5 + R4; +R5 = R5 + R5; +R6 = R5 + R6; +R7 = R5 + R7; +CHECKREG r0, 0x7AB468AC; +CHECKREG r1, 0xFB3CF134; +CHECKREG r2, 0xCB09BE01; +CHECKREG r3, 0x4B813579; +CHECKREG r4, 0x9AD68BDE; +CHECKREG r5, 0xEB22468A; +CHECKREG r6, 0x80989ABC; +CHECKREG r7, 0x00569D02; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 + R0; +R1 = R6 + R1; +R2 = R6 + R2; +R3 = R6 + R3; +R4 = R6 + R4; +R5 = R6 + R5; +R6 = R6 + R6; +R7 = R6 + R7; +CHECKREG r0, 0x999C9999; +CHECKREG r1, 0x221D2221; +CHECKREG r2, 0xEEECEEEE; +CHECKREG r3, 0x776C6666; +CHECKREG r4, 0xBBBCBCCB; +CHECKREG r5, 0x110C7777; +CHECKREG r6, 0x30ECA864; +CHECKREG r7, 0x4322FEDC; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 + R0; +R1 = R7 + R1; +R2 = R7 + R2; +R3 = R7 + R3; +R4 = R7 + R4; +R5 = R7 + R5; +R6 = R7 + R6; +R7 = R7 + R7; +CHECKREG r0, 0x1357CBDF; +CHECKREG r1, 0x9BDFD467; +CHECKREG r2, 0x68ACD134; +CHECKREG r3, 0xF124C8AC; +CHECKREG r4, 0x3579CF11; +CHECKREG r5, 0x8AC5C9BD; +CHECKREG r6, 0xAAAACAAA; +CHECKREG r7, 0x2468ACF0; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 + R0; +R1 = R2 + R0; +R2 = R3 + R0; +R3 = R4 + R0; +R4 = R5 + R0; +R5 = R6 + R0; +R6 = R7 + R0; +R7 = R0 + R0; +CHECKREG r0, 0x92CF1356; +CHECKREG r1, 0xE8E7AE12; +CHECKREG r2, 0x71C0258A; +CHECKREG r3, 0xB6142BEF; +CHECKREG r4, 0x0B60349B; +CHECKREG r5, 0x2B456768; +CHECKREG r6, 0xA50369C7; +CHECKREG r7, 0x259E26AC; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 + R1; +R1 = R3 + R1; +R2 = R4 + R1; +R3 = R5 + R1; +R4 = R6 + R1; +R5 = R7 + R1; +R6 = R0 + R1; +R7 = R1 + R1; +CHECKREG r0, 0x7C2338AB; +CHECKREG r1, 0x07CB3023; +CHECKREG r2, 0x2B0D48BC; +CHECKREG r3, 0x805C5368; +CHECKREG r4, 0xA0414255; +CHECKREG r5, 0x19FF464B; +CHECKREG r6, 0x83EE68CE; +CHECKREG r7, 0x0F966046; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R3 + R2; +R1 = R4 + R2; +R2 = R5 + R2; +R3 = R6 + R2; +R4 = R7 + R2; +R5 = R0 + R2; +R6 = R1 + R2; +R7 = R2 + R2; +CHECKREG r0, 0x9563CC50; +CHECKREG r1, 0x79B8FD55; +CHECKREG r2, 0xCEA4BD61; +CHECKREG r3, 0x67181184; +CHECKREG r4, 0xE0D8F389; +CHECKREG r5, 0x640889B1; +CHECKREG r6, 0x485DBAB6; +CHECKREG r7, 0x9D497AC2; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R4 + R3; +R1 = R5 + R3; +R2 = R6 + R3; +R3 = R7 + R3; +R4 = R0 + R3; +R5 = R1 + R3; +R6 = R2 + R3; +R7 = R3 + R3; +CHECKREG r0, 0x7335A6C6; +CHECKREG r1, 0xC7316577; +CHECKREG r2, 0xE7649667; +CHECKREG r3, 0x612488A6; +CHECKREG r4, 0xD45A2F6C; +CHECKREG r5, 0x2855EE1D; +CHECKREG r6, 0x48891F0D; +CHECKREG r7, 0xC249114C; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R5 + R4; +R1 = R6 + R4; +R2 = R7 + R4; +R3 = R0 + R4; +R4 = R1 + R4; +R5 = R2 + R4; +R6 = R3 + R4; +R7 = R4 + R4; +CHECKREG r0, 0x98D68BDE; +CHECKREG r1, 0x9B9BBCCB; +CHECKREG r2, 0x957ABF11; +CHECKREG r3, 0xEC1BF477; +CHECKREG r4, 0xEEE12564; +CHECKREG r5, 0x845BE475; +CHECKREG r6, 0xDAFD19DB; +CHECKREG r7, 0xDDC24AC8; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R6 + R5; +R1 = R7 + R5; +R2 = R0 + R5; +R3 = R1 + R5; +R4 = R2 + R5; +R5 = R3 + R5; +R6 = R4 + R5; +R7 = R5 + R5; +CHECKREG r0, 0x0B0C8777; +CHECKREG r1, 0x8ACA79BD; +CHECKREG r2, 0x80A2AABC; +CHECKREG r3, 0x00609D02; +CHECKREG r4, 0xF638CE01; +CHECKREG r5, 0x75F6C047; +CHECKREG r6, 0x6C2F8E48; +CHECKREG r7, 0xEBED808E; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 + R6; +R1 = R0 + R6; +R2 = R1 + R6; +R3 = R2 + R6; +R4 = R3 + R6; +R5 = R4 + R6; +R6 = R5 + R6; +R7 = R6 + R6; +CHECKREG r0, 0xAAADAAAA; +CHECKREG r1, 0x4323FEDC; +CHECKREG r2, 0xDB9A530E; +CHECKREG r3, 0x7410A740; +CHECKREG r4, 0x0C86FB72; +CHECKREG r5, 0xA4FD4FA4; +CHECKREG r6, 0x3D73A3D6; +CHECKREG r7, 0x7AE747AC; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 + R7; +R1 = R2 + R7; +R2 = R3 + R7; +R3 = R4 + R7; +R4 = R5 + R7; +R5 = R6 + R7; +R6 = R7 + R7; +R7 = R0 + R7; +CHECKREG r0, 0x9ADFFF67; +CHECKREG r1, 0x68BD0104; +CHECKREG r2, 0xA12CF8B0; +CHECKREG r3, 0x3A7A0F11; +CHECKREG r4, 0x8AB5FEBD; +CHECKREG r5, 0xAAACFAFA; +CHECKREG r6, 0x24690CF0; +CHECKREG r7, 0xAD1485DF; + + +pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_dr_xor_dr.s b/sim/testsuite/sim/bfin/c_comp3op_dr_xor_dr.s new file mode 100644 index 0000000..fa0db63 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_comp3op_dr_xor_dr.s @@ -0,0 +1,412 @@ +//Original:/testcases/core/c_comp3op_dr_xor_dr/c_comp3op_dr_xor_dr.dsp +// Spec Reference: comp3op dregs xor dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x01234567; +imm32 r1, 0x89abcdef; +imm32 r2, 0x56789abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23456899; +imm32 r5, 0x78912345; +imm32 r6, 0x98765432; +imm32 r7, 0x12345678; +R0 = R0 ^ R0; +R1 = R0 ^ R1; +R2 = R0 ^ R2; +R3 = R0 ^ R3; +R4 = R0 ^ R4; +R5 = R0 ^ R5; +R6 = R0 ^ R6; +R7 = R0 ^ R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x89ABCDEF; +CHECKREG r2, 0x56789ABC; +CHECKREG r3, 0xDEF01234; +CHECKREG r4, 0x23456899; +CHECKREG r5, 0x78912345; +CHECKREG r6, 0x98765432; +CHECKREG r7, 0x12345678; + +imm32 r0, 0x01231567; +imm32 r1, 0x89ab1def; +imm32 r2, 0x56781abc; +imm32 r3, 0xdef01234; +imm32 r4, 0x23451899; +imm32 r5, 0x78911345; +imm32 r6, 0x98761432; +imm32 r7, 0x12341678; +R0 = R1 ^ R0; +R1 = R1 ^ R1; +R2 = R1 ^ R2; +R3 = R1 ^ R3; +R4 = R1 ^ R4; +R5 = R1 ^ R5; +R6 = R1 ^ R6; +R7 = R1 ^ R7; +CHECKREG r0, 0x88880888; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x56781ABC; +CHECKREG r3, 0xDEF01234; +CHECKREG r4, 0x23451899; +CHECKREG r5, 0x78911345; +CHECKREG r6, 0x98761432; +CHECKREG r7, 0x12341678; + +imm32 r0, 0x01234527; +imm32 r1, 0x89abcd2f; +imm32 r2, 0x56789a2c; +imm32 r3, 0xdef01224; +imm32 r4, 0x23456829; +imm32 r5, 0x78912325; +imm32 r6, 0x98765422; +imm32 r7, 0x12345628; +R0 = R2 ^ R0; +R1 = R2 ^ R1; +R2 = R2 ^ R2; +R3 = R2 ^ R3; +R4 = R2 ^ R4; +R5 = R2 ^ R5; +R6 = R2 ^ R6; +R7 = R2 ^ R7; +CHECKREG r0, 0x575BDF0B; +CHECKREG r1, 0xDFD35703; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xDEF01224; +CHECKREG r4, 0x23456829; +CHECKREG r5, 0x78912325; +CHECKREG r6, 0x98765422; +CHECKREG r7, 0x12345628; + +imm32 r0, 0x01234563; +imm32 r1, 0x89abcde3; +imm32 r2, 0x56789ab3; +imm32 r3, 0xdef01233; +imm32 r4, 0x23456893; +imm32 r5, 0x78912343; +imm32 r6, 0x98765433; +imm32 r7, 0x12345673; +R0 = R3 ^ R0; +R1 = R3 ^ R1; +R2 = R3 ^ R2; +R3 = R3 ^ R3; +R4 = R3 ^ R4; +R5 = R3 ^ R5; +R6 = R3 ^ R6; +R7 = R3 ^ R7; +CHECKREG r0, 0xDFD35750; +CHECKREG r1, 0x575BDFD0; +CHECKREG r2, 0x88888880; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x23456893; +CHECKREG r5, 0x78912343; +CHECKREG r6, 0x98765433; +CHECKREG r7, 0x12345673; + +imm32 r0, 0x41234567; +imm32 r1, 0x49abcdef; +imm32 r2, 0x46789abc; +imm32 r3, 0x4ef01234; +imm32 r4, 0x43456899; +imm32 r5, 0x48912345; +imm32 r6, 0x48765432; +imm32 r7, 0x42345678; +R0 = R4 ^ R0; +R1 = R4 ^ R1; +R2 = R4 ^ R2; +R3 = R4 ^ R3; +R4 = R4 ^ R4; +R5 = R4 ^ R5; +R6 = R4 ^ R6; +R7 = R4 ^ R7; +CHECKREG r0, 0x02662DFE; +CHECKREG r1, 0x0AEEA576; +CHECKREG r2, 0x053DF225; +CHECKREG r3, 0x0DB57AAD; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x48912345; +CHECKREG r6, 0x48765432; +CHECKREG r7, 0x42345678; + +imm32 r0, 0x05234567; +imm32 r1, 0x85abcdef; +imm32 r2, 0x55789abc; +imm32 r3, 0xd5f01234; +imm32 r4, 0x25456899; +imm32 r5, 0x75912345; +imm32 r6, 0x95765432; +imm32 r7, 0x15345678; +R0 = R5 ^ R0; +R1 = R5 ^ R1; +R2 = R5 ^ R2; +R3 = R5 ^ R3; +R4 = R5 ^ R4; +R5 = R5 ^ R5; +R6 = R5 ^ R6; +R7 = R5 ^ R7; +CHECKREG r0, 0x70B26622; +CHECKREG r1, 0xF03AEEAA; +CHECKREG r2, 0x20E9B9F9; +CHECKREG r3, 0xA0613171; +CHECKREG r4, 0x50D44BDC; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x95765432; +CHECKREG r7, 0x15345678; + +imm32 r0, 0x01264567; +imm32 r1, 0x89a6cdef; +imm32 r2, 0x56769abc; +imm32 r3, 0xdef61234; +imm32 r4, 0x23466899; +imm32 r5, 0x78962345; +imm32 r6, 0x98765432; +imm32 r7, 0x12365678; +R0 = R6 ^ R0; +R1 = R6 ^ R1; +R2 = R6 ^ R2; +R3 = R6 ^ R3; +R4 = R6 ^ R4; +R5 = R6 ^ R5; +R6 = R6 ^ R6; +R7 = R6 ^ R7; +CHECKREG r0, 0x99501155; +CHECKREG r1, 0x11D099DD; +CHECKREG r2, 0xCE00CE8E; +CHECKREG r3, 0x46804606; +CHECKREG r4, 0xBB303CAB; +CHECKREG r5, 0xE0E07777; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x12365678; + +imm32 r0, 0x01237567; +imm32 r1, 0x89ab7def; +imm32 r2, 0x56787abc; +imm32 r3, 0xdef07234; +imm32 r4, 0x23457899; +imm32 r5, 0x78917345; +imm32 r6, 0x98767432; +imm32 r7, 0x12345678; +R0 = R7 ^ R0; +R1 = R7 ^ R1; +R2 = R7 ^ R2; +R3 = R7 ^ R3; +R4 = R7 ^ R4; +R5 = R7 ^ R5; +R6 = R7 ^ R6; +R7 = R7 ^ R7; +CHECKREG r0, 0x1317231F; +CHECKREG r1, 0x9B9F2B97; +CHECKREG r2, 0x444C2CC4; +CHECKREG r3, 0xCCC4244C; +CHECKREG r4, 0x31712EE1; +CHECKREG r5, 0x6AA5253D; +CHECKREG r6, 0x8A42224A; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x11234567; +imm32 r1, 0x81abcdef; +imm32 r2, 0x56189abc; +imm32 r3, 0xdef11234; +imm32 r4, 0x23451899; +imm32 r5, 0x78912145; +imm32 r6, 0x98765412; +imm32 r7, 0x12345671; +R0 = R1 ^ R0; +R1 = R2 ^ R0; +R2 = R3 ^ R0; +R3 = R4 ^ R0; +R4 = R5 ^ R0; +R5 = R6 ^ R0; +R6 = R7 ^ R0; +R7 = R0 ^ R0; +CHECKREG r0, 0x90888888; +CHECKREG r1, 0xC6901234; +CHECKREG r2, 0x4E799ABC; +CHECKREG r3, 0xB3CD9011; +CHECKREG r4, 0xE819A9CD; +CHECKREG r5, 0x08FEDC9A; +CHECKREG r6, 0x82BCDEF9; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01231567; +imm32 r1, 0x29ab1def; +imm32 r2, 0x52781abc; +imm32 r3, 0xde201234; +imm32 r4, 0x23421899; +imm32 r5, 0x78912345; +imm32 r6, 0x98761232; +imm32 r7, 0x12341628; +R0 = R2 ^ R1; +R1 = R3 ^ R1; +R2 = R4 ^ R1; +R3 = R5 ^ R1; +R4 = R6 ^ R1; +R5 = R7 ^ R1; +R6 = R0 ^ R1; +R7 = R1 ^ R1; +CHECKREG r0, 0x7BD30753; +CHECKREG r1, 0xF78B0FDB; +CHECKREG r2, 0xD4C91742; +CHECKREG r3, 0x8F1A2C9E; +CHECKREG r4, 0x6FFD1DE9; +CHECKREG r5, 0xE5BF19F3; +CHECKREG r6, 0x8C580888; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x03234527; +imm32 r1, 0x893bcd2f; +imm32 r2, 0x56739a2c; +imm32 r3, 0x3ef03224; +imm32 r4, 0x23456329; +imm32 r5, 0x78312335; +imm32 r6, 0x98735423; +imm32 r7, 0x12343628; +R0 = R4 ^ R2; +R1 = R5 ^ R2; +R2 = R6 ^ R2; +R3 = R7 ^ R2; +R4 = R0 ^ R2; +R5 = R1 ^ R2; +R6 = R2 ^ R2; +R7 = R3 ^ R2; +CHECKREG r0, 0x7536F905; +CHECKREG r1, 0x2E42B919; +CHECKREG r2, 0xCE00CE0F; +CHECKREG r3, 0xDC34F827; +CHECKREG r4, 0xBB36370A; +CHECKREG r5, 0xE0427716; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x12343628; + +imm32 r0, 0x04234563; +imm32 r1, 0x894bcde3; +imm32 r2, 0x56749ab3; +imm32 r3, 0x4ef04233; +imm32 r4, 0x24456493; +imm32 r5, 0x78412344; +imm32 r6, 0x98745434; +imm32 r7, 0x12344673; +R0 = R5 ^ R3; +R1 = R6 ^ R3; +R2 = R7 ^ R3; +R3 = R0 ^ R3; +R4 = R1 ^ R3; +R5 = R2 ^ R3; +R6 = R3 ^ R3; +R7 = R4 ^ R3; +CHECKREG r0, 0x36B16177; +CHECKREG r1, 0xD6841607; +CHECKREG r2, 0x5CC40440; +CHECKREG r3, 0x78412344; +CHECKREG r4, 0xAEC53543; +CHECKREG r5, 0x24852704; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xD6841607; + +imm32 r0, 0x41235567; +imm32 r1, 0x49abc5ef; +imm32 r2, 0x46789a5c; +imm32 r3, 0x4ef01235; +imm32 r4, 0x53456899; +imm32 r5, 0x45912345; +imm32 r6, 0x48565432; +imm32 r7, 0x42355678; +R0 = R6 ^ R4; +R1 = R7 ^ R4; +R2 = R0 ^ R4; +R3 = R1 ^ R4; +R4 = R2 ^ R4; +R5 = R3 ^ R4; +R6 = R4 ^ R4; +R7 = R5 ^ R4; +CHECKREG r0, 0x1B133CAB; +CHECKREG r1, 0x11703EE1; +CHECKREG r2, 0x48565432; +CHECKREG r3, 0x42355678; +CHECKREG r4, 0x1B133CAB; +CHECKREG r5, 0x59266AD3; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x42355678; + +imm32 r0, 0x05264567; +imm32 r1, 0x85ab6def; +imm32 r2, 0x657896bc; +imm32 r3, 0xd6f01264; +imm32 r4, 0x25656896; +imm32 r5, 0x75962345; +imm32 r6, 0x95766432; +imm32 r7, 0x15345678; +R0 = R7 ^ R5; +R1 = R0 ^ R5; +R2 = R1 ^ R5; +R3 = R2 ^ R5; +R4 = R3 ^ R5; +R5 = R4 ^ R5; +R6 = R5 ^ R5; +R7 = R6 ^ R5; +CHECKREG r0, 0x60A2753D; +CHECKREG r1, 0x15345678; +CHECKREG r2, 0x60A2753D; +CHECKREG r3, 0x15345678; +CHECKREG r4, 0x60A2753D; +CHECKREG r5, 0x15345678; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x15345678; + +imm32 r0, 0x01764567; +imm32 r1, 0x89a7cdef; +imm32 r2, 0x56767abc; +imm32 r3, 0xdef61734; +imm32 r4, 0x73466879; +imm32 r5, 0x77962347; +imm32 r6, 0x98765432; +imm32 r7, 0x12375678; +R0 = R7 ^ R6; +R1 = R0 ^ R6; +R2 = R1 ^ R6; +R3 = R2 ^ R6; +R4 = R3 ^ R6; +R5 = R4 ^ R6; +R6 = R5 ^ R6; +R7 = R6 ^ R6; +CHECKREG r0, 0x8A41024A; +CHECKREG r1, 0x12375678; +CHECKREG r2, 0x8A41024A; +CHECKREG r3, 0x12375678; +CHECKREG r4, 0x8A41024A; +CHECKREG r5, 0x12375678; +CHECKREG r6, 0x8A41024A; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x81238567; +imm32 r1, 0x88ab78ef; +imm32 r2, 0x56887a8c; +imm32 r3, 0x8ef87238; +imm32 r4, 0x28458899; +imm32 r5, 0x78817845; +imm32 r6, 0x98787482; +imm32 r7, 0x12348678; +R0 = R1 ^ R7; +R1 = R2 ^ R7; +R2 = R3 ^ R7; +R3 = R4 ^ R7; +R4 = R5 ^ R7; +R5 = R6 ^ R7; +R6 = R7 ^ R7; +R7 = R0 ^ R7; +CHECKREG r0, 0x9A9FFE97; +CHECKREG r1, 0x44BCFCF4; +CHECKREG r2, 0x9CCCF440; +CHECKREG r3, 0x3A710EE1; +CHECKREG r4, 0x6AB5FE3D; +CHECKREG r5, 0x8A4CF2FA; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x88AB78EF; + + +pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh1.s b/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh1.s new file mode 100644 index 0000000..f570a5f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh1.s @@ -0,0 +1,302 @@ +//Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh1/c_comp3op_pr_plus_pr_sh1.dsp +// Spec Reference: comp3op pregs + pregs << 1 +# mach: bfin + +.include "testutils.inc" + start + + imm32 p1, 0x89ab1def; + imm32 p2, 0x56781abc; + imm32 p3, 0xdef01234; + imm32 p4, 0x23451899; + imm32 p5, 0x78911345; + imm32 sp, 0x98761432; + imm32 fp, 0x12341678; + P1 = P1 + ( P1 << 1 ); + P2 = P1 + ( P2 << 1 ); + P3 = P1 + ( P3 << 1 ); + P4 = P1 + ( P4 << 1 ); + P5 = P1 + ( P5 << 1 ); + SP = P1 + ( SP << 1 ); + FP = P1 + FP; + CHECKREG p1, 0x9D0159CD; + CHECKREG p2, 0x49F18F45; + CHECKREG p3, 0x5AE17E35; + CHECKREG p4, 0xE38B8AFF; + CHECKREG p5, 0x8E238057; + CHECKREG sp, 0xCDED8231; + CHECKREG fp, 0xAF357045; + + imm32 p1, 0x89abcd2f; + imm32 p2, 0x56789a2c; + imm32 p3, 0xdef01224; + imm32 p4, 0x23456829; + imm32 p5, 0x78912325; + imm32 sp, 0x98765422; + imm32 fp, 0x12345628; + P1 = P2 + ( P1 << 1 ); + P2 = P2 + ( P2 << 1 ); + P3 = P2 + ( P3 << 1 ); + P4 = P2 + ( P4 << 1 ); + P5 = P2 + ( P5 << 1 ); + SP = P2 + ( SP << 1 ); + FP = P2 + ( FP << 1 ); + CHECKREG p1, 0x69D0348A; + CHECKREG p2, 0x0369CE84; + CHECKREG p3, 0xC149F2CC; + CHECKREG p4, 0x49F49ED6; + CHECKREG p5, 0xF48C14CE; + CHECKREG sp, 0x345676C8; + CHECKREG fp, 0x27D27AD4; + + imm32 p1, 0x89abcde3; + imm32 p2, 0x56789ab3; + imm32 p3, 0xdef01233; + imm32 p4, 0x23456893; + imm32 p5, 0x78912343; + imm32 sp, 0x98765433; + imm32 fp, 0x12345673; + P1 = P3 + ( P1 << 1 ); + P2 = P3 + ( P2 << 1 ); + P3 = P3 + ( P3 << 1 ); + P4 = P3 + ( P4 << 1 ); + P5 = P3 + ( P5 << 1 ); + SP = P3 + ( SP << 1 ); + FP = P3 + ( FP << 1 ); + CHECKREG p1, 0xF247ADF9; + CHECKREG p2, 0x8BE14799; + CHECKREG p3, 0x9CD03699; + CHECKREG p4, 0xE35B07BF; + CHECKREG p5, 0x8DF27D1F; + CHECKREG sp, 0xCDBCDEFF; + CHECKREG fp, 0xC138E37F; + + imm32 p1, 0x49abcdef; + imm32 p2, 0x46789abc; + imm32 p3, 0x4ef01234; + imm32 p4, 0x43456899; + imm32 p5, 0x48912345; + imm32 sp, 0x48765432; + imm32 fp, 0x42345678; + P1 = P4 + ( P1 << 1 ); + P2 = P4 + ( P2 << 1 ); + P3 = P4 + ( P3 << 1 ); + P4 = P4 + ( P4 << 1 ); + P5 = P4 + ( P5 << 1 ); + SP = P4 + ( SP << 1 ); + FP = P4 + ( FP << 1 ); + CHECKREG p1, 0xD69D0477; + CHECKREG p2, 0xD0369E11; + CHECKREG p3, 0xE1258D01; + CHECKREG p4, 0xC9D039CB; + CHECKREG p5, 0x5AF28055; + CHECKREG sp, 0x5ABCE22F; + CHECKREG fp, 0x4E38E6BB; + + imm32 p1, 0x85abcdef; + imm32 p2, 0x55789abc; + imm32 p3, 0xd5f01234; + imm32 p4, 0x25456899; + imm32 p5, 0x75912345; + imm32 sp, 0x95765432; + imm32 fp, 0x15345678; + P1 = P5 + ( P1 << 1 ); + P2 = P5 + ( P2 << 1 ); + P3 = P5 + ( P3 << 1 ); + P4 = P5 + ( P4 << 1 ); + P5 = P5 + ( P5 << 1 ); + SP = P5 + ( SP << 1 ); + FP = P5 + ( FP << 1 ); + CHECKREG p1, 0x80E8BF23; + CHECKREG p2, 0x208258BD; + CHECKREG p3, 0x217147AD; + CHECKREG p4, 0xC01BF477; + CHECKREG p5, 0x60B369CF; + CHECKREG sp, 0x8BA01233; + CHECKREG fp, 0x8B1C16BF; + + imm32 p1, 0x89a6cdef; + imm32 p2, 0x56769abc; + imm32 p3, 0xdef61234; + imm32 p4, 0x23466899; + imm32 p5, 0x78962345; + imm32 sp, 0x98765432; + imm32 fp, 0x12365678; + P1 = SP + ( P1 << 1 ); + P2 = SP + ( P2 << 1 ); + P3 = SP + ( P3 << 1 ); + P4 = SP + ( P4 << 1 ); + P5 = SP + ( P5 << 1 ); + SP = SP + ( SP << 1 ); + FP = SP + ( FP << 1 ); + CHECKREG p1, 0xABC3F010; + CHECKREG p2, 0x456389AA; + CHECKREG p3, 0x5662789A; + CHECKREG p4, 0xDF032564; + CHECKREG p5, 0x89A29ABC; + CHECKREG sp, 0xC962FC96; + CHECKREG fp, 0xEDCFA986; + + imm32 p1, 0x89ab7def; + imm32 p2, 0x56787abc; + imm32 p3, 0xdef07234; + imm32 p4, 0x23457899; + imm32 p5, 0x78917345; + imm32 sp, 0x98767432; + imm32 fp, 0x12345678; + P1 = FP + ( P1 << 1 ); + P2 = FP + ( P2 << 1 ); + P3 = FP + ( P3 << 1 ); + P4 = FP + ( P4 << 1 ); + P5 = FP + ( P5 << 1 ); + SP = FP + ( SP << 1 ); + FP = FP + ( FP << 1 ); + CHECKREG p1, 0x258B5256; + CHECKREG p2, 0xBF254BF0; + CHECKREG p3, 0xD0153AE0; + CHECKREG p4, 0x58BF47AA; + CHECKREG p5, 0x03573D02; + CHECKREG sp, 0x43213EDC; + CHECKREG fp, 0x369D0368; + + imm32 p1, 0x29ab1def; + imm32 p2, 0x52781abc; + imm32 p3, 0xde201234; + imm32 p4, 0x23421899; + imm32 p5, 0x78912345; + imm32 sp, 0x98761232; + imm32 fp, 0x12341628; + P1 = P3 + ( P1 << 1 ); + P2 = P4 + ( P1 << 1 ); + P3 = P5 + ( P1 << 1 ); + P4 = SP + ( P1 << 1 ); + P5 = FP + ( P1 << 1 ); + FP = P1 + ( P1 << 1 ); + CHECKREG p1, 0x31764E12; + CHECKREG p2, 0x862EB4BD; + CHECKREG p3, 0xDB7DBF69; + CHECKREG p4, 0xFB62AE56; + CHECKREG p5, 0x7520B24C; + CHECKREG fp, 0x9462EA36; + + imm32 p1, 0x893bcd2f; + imm32 p2, 0x56739a2c; + imm32 p3, 0x3ef03224; + imm32 p4, 0x23456329; + imm32 p5, 0x78312335; + imm32 sp, 0x98735423; + imm32 fp, 0x12343628; + P1 = P4 + ( P2 << 1 ); + P2 = P5 + ( P2 << 1 ); + P3 = SP + ( P2 << 1 ); + P4 = FP + ( P2 << 1 ); + SP = P1 + ( P2 << 1 ); + FP = P2 + ( P2 << 1 ); + CHECKREG p1, 0xD02C9781; + CHECKREG p2, 0x2518578D; + CHECKREG p3, 0xE2A4033D; + CHECKREG p4, 0x5C64E542; + CHECKREG sp, 0x1A5D469B; + CHECKREG fp, 0x6F4906A7; + + imm32 p1, 0x894bcde3; + imm32 p2, 0x56749ab3; + imm32 p3, 0x4ef04233; + imm32 p4, 0x24456493; + imm32 p5, 0x78412344; + imm32 sp, 0x98745434; + imm32 fp, 0x12344673; + P1 = P5 + ( P3 << 1 ); + P2 = SP + ( P3 << 1 ); + P3 = FP + ( P3 << 1 ); + P5 = P1 + ( P3 << 1 ); + SP = P2 + ( P3 << 1 ); + FP = P3 + ( P3 << 1 ); + CHECKREG p1, 0x1621A7AA; + CHECKREG p2, 0x3654D89A; + CHECKREG p3, 0xB014CAD9; + CHECKREG p5, 0x764B3D5C; + CHECKREG sp, 0x967E6E4C; + CHECKREG fp, 0x103E608B; + + imm32 p1, 0x49abc5ef; + imm32 p2, 0x46789a5c; + imm32 p3, 0x4ef01235; + imm32 p4, 0x53456899; + imm32 p5, 0x45912345; + imm32 sp, 0x48565432; + imm32 fp, 0x42355678; + P1 = SP + ( P4 << 1 ); + P2 = FP + ( P4 << 1 ); + P4 = P1 + ( P4 << 1 ); + P5 = P2 + ( P4 << 1 ); + SP = P3 + ( P4 << 1 ); + FP = P4 + ( P4 << 1 ); + CHECKREG p1, 0xEEE12564; + CHECKREG p2, 0xE8C027AA; + CHECKREG p4, 0x956BF696; + CHECKREG p5, 0x139814D6; + CHECKREG sp, 0x79C7FF61; + CHECKREG fp, 0xC043E3C2; + + imm32 p1, 0x85ab6def; + imm32 p2, 0x657896bc; + imm32 p3, 0xd6f01264; + imm32 p4, 0x25656896; + imm32 p5, 0x75962345; + imm32 sp, 0x95766432; + imm32 fp, 0x15345678; + P1 = FP + ( P5 << 1 ); + P3 = P1 + ( P5 << 1 ); + P4 = P2 + ( P5 << 1 ); + P5 = P3 + ( P5 << 1 ); + SP = P4 + ( P5 << 1 ); + FP = P5 + ( P5 << 1 ); + CHECKREG p1, 0x00609D02; + CHECKREG p3, 0xEB8CE38C; + CHECKREG p4, 0x50A4DD46; + CHECKREG p5, 0xD6B92A16; + CHECKREG sp, 0xFE173172; + CHECKREG fp, 0x842B7E42; + + imm32 p1, 0x89a7cdef; + imm32 p2, 0x56767abc; + imm32 p3, 0xdef61734; + imm32 p4, 0x73466879; + imm32 p5, 0x77962347; + imm32 sp, 0x98765432; + imm32 fp, 0x12375678; + P2 = P1 + ( SP << 1 ); + P3 = P2 + ( SP << 1 ); + P4 = P3 + ( SP << 1 ); + P5 = P4 + ( SP << 1 ); + SP = P5 + ( SP << 1 ); + FP = SP + ( SP << 1 ); + CHECKREG p2, 0xBA947653; + CHECKREG p3, 0xEB811EB7; + CHECKREG p4, 0x1C6DC71B; + CHECKREG p5, 0x4D5A6F7F; + CHECKREG sp, 0x7E4717E3; + CHECKREG fp, 0x7AD547A9; + + imm32 p1, 0x88ab78ef; + imm32 p2, 0x56887a8c; + imm32 p3, 0x8ef87238; + imm32 p4, 0x28458899; + imm32 p5, 0x78817845; + imm32 sp, 0x98787482; + imm32 fp, 0x12348678; + P1 = P2 + ( FP << 1 ); + P2 = P3 + ( FP << 1 ); + P3 = P4 + ( FP << 1 ); + P4 = P5 + ( FP << 1 ); + P5 = SP + ( FP << 1 ); + SP = FP + ( FP << 1 ); + CHECKREG p1, 0x7AF1877C; + CHECKREG p2, 0xB3617F28; + CHECKREG p3, 0x4CAE9589; + CHECKREG p4, 0x9CEA8535; + CHECKREG p5, 0xBCE18172; + CHECKREG sp, 0x369D9368; + + pass diff --git a/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh2.s b/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh2.s new file mode 100644 index 0000000..dd86726 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh2.s @@ -0,0 +1,302 @@ +//Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh2/c_comp3op_pr_plus_pr_sh2.dsp +// Spec Reference: comp3op pregs + pregs << 2 +# mach: bfin + +.include "testutils.inc" + start + + imm32 p1, 0x89ab1def; + imm32 p2, 0x56781abc; + imm32 p3, 0xdef01234; + imm32 p4, 0x23451899; + imm32 p5, 0x78911345; + imm32 sp, 0x98761432; + imm32 fp, 0x12341678; + P1 = P1 + ( P1 << 2 ); + P2 = P1 + ( P2 << 2 ); + P3 = P1 + ( P3 << 2 ); + P4 = P1 + ( P4 << 2 ); + P5 = P1 + ( P5 << 2 ); + SP = P1 + ( SP << 2 ); + FP = P1 + FP; + CHECKREG p1, 0xB05795AB; + CHECKREG p2, 0x0A38009B; + CHECKREG p3, 0x2C17DE7B; + CHECKREG p4, 0x3D6BF80F; + CHECKREG p5, 0x929BE2BF; + CHECKREG sp, 0x122FE673; + CHECKREG fp, 0xC28BAC23; + + imm32 p1, 0x89abcd2f; + imm32 p2, 0x56789a2c; + imm32 p3, 0xdef01224; + imm32 p4, 0x23456829; + imm32 p5, 0x78912325; + imm32 sp, 0x98765422; + imm32 fp, 0x12345628; + P1 = P2 + ( P1 << 2 ); + P2 = P2 + ( P2 << 2 ); + P3 = P2 + ( P3 << 2 ); + P4 = P2 + ( P4 << 2 ); + P5 = P2 + ( P5 << 2 ); + SP = P2 + ( SP << 2 ); + FP = P2 + ( FP << 2 ); + CHECKREG p1, 0x7D27CEE8; + CHECKREG p2, 0xB05B02DC; + CHECKREG p3, 0x2C1B4B6C; + CHECKREG p4, 0x3D70A380; + CHECKREG p5, 0x929F8F70; + CHECKREG sp, 0x12345364; + CHECKREG fp, 0xF92C5B7C; + + imm32 p1, 0x89abcde3; + imm32 p2, 0x56789ab3; + imm32 p3, 0xdef01233; + imm32 p4, 0x23456893; + imm32 p5, 0x78912343; + imm32 sp, 0x98765433; + imm32 fp, 0x12345673; + P1 = P3 + ( P1 << 2 ); + P2 = P3 + ( P2 << 2 ); + P3 = P3 + ( P3 << 2 ); + P4 = P3 + ( P4 << 2 ); + P5 = P3 + ( P5 << 2 ); + SP = P3 + ( SP << 2 ); + FP = P3 + ( FP << 2 ); + CHECKREG p1, 0x059F49BF; + CHECKREG p2, 0x38D27CFF; + CHECKREG p3, 0x5AB05AFF; + CHECKREG p4, 0xE7C5FD4B; + CHECKREG p5, 0x3CF4E80B; + CHECKREG sp, 0xBC89ABCB; + CHECKREG fp, 0xA381B4CB; + + imm32 p1, 0x49abcdef; + imm32 p2, 0x46789abc; + imm32 p3, 0x4ef01234; + imm32 p4, 0x43456899; + imm32 p5, 0x48912345; + imm32 sp, 0x48765432; + imm32 fp, 0x42345678; + P1 = P4 + ( P1 << 2 ); + P2 = P4 + ( P2 << 2 ); + P3 = P4 + ( P3 << 2 ); + P4 = P4 + ( P4 << 2 ); + P5 = P4 + ( P5 << 2 ); + SP = P4 + ( SP << 2 ); + FP = P4 + ( FP << 2 ); + CHECKREG p1, 0x69F4A055; + CHECKREG p2, 0x5D27D389; + CHECKREG p3, 0x7F05B169; + CHECKREG p4, 0x505B0AFD; + CHECKREG p5, 0x729F9811; + CHECKREG sp, 0x72345BC5; + CHECKREG fp, 0x592C64DD; + + imm32 p1, 0x85abcdef; + imm32 p2, 0x55789abc; + imm32 p3, 0xd5f01234; + imm32 p4, 0x25456899; + imm32 p5, 0x75912345; + imm32 sp, 0x95765432; + imm32 fp, 0x15345678; + P1 = P5 + ( P1 << 2 ); + P2 = P5 + ( P2 << 2 ); + P3 = P5 + ( P3 << 2 ); + P4 = P5 + ( P4 << 2 ); + P5 = P5 + ( P5 << 2 ); + SP = P5 + ( SP << 2 ); + FP = P5 + ( FP << 2 ); + CHECKREG p1, 0x8C405B01; + CHECKREG p2, 0xCB738E35; + CHECKREG p3, 0xCD516C15; + CHECKREG p4, 0x0AA6C5A9; + CHECKREG p5, 0x4BD5B059; + CHECKREG sp, 0xA1AF0121; + CHECKREG fp, 0xA0A70A39; + + imm32 p1, 0x89a6cdef; + imm32 p2, 0x56769abc; + imm32 p3, 0xdef61234; + imm32 p4, 0x23466899; + imm32 p5, 0x78962345; + imm32 sp, 0x98765432; + imm32 fp, 0x12365678; + P1 = SP + ( P1 << 2 ); + P2 = SP + ( P2 << 2 ); + P3 = SP + ( P3 << 2 ); + P4 = SP + ( P4 << 2 ); + P5 = SP + ( P5 << 2 ); + SP = SP + ( SP << 2 ); + FP = SP + ( FP << 2 ); + CHECKREG p1, 0xBF118BEE; + CHECKREG p2, 0xF250BF22; + CHECKREG p3, 0x144E9D02; + CHECKREG p4, 0x258FF696; + CHECKREG p5, 0x7ACEE146; + CHECKREG sp, 0xFA4FA4FA; + CHECKREG fp, 0x4328FEDA; + + imm32 p1, 0x89ab7def; + imm32 p2, 0x56787abc; + imm32 p3, 0xdef07234; + imm32 p4, 0x23457899; + imm32 p5, 0x78917345; + imm32 sp, 0x98767432; + imm32 fp, 0x12345678; + P1 = FP + ( P1 << 2 ); + P2 = FP + ( P2 << 2 ); + P3 = FP + ( P3 << 2 ); + P4 = FP + ( P4 << 2 ); + P5 = FP + ( P5 << 2 ); + SP = FP + ( SP << 2 ); + FP = FP + ( FP << 2 ); + CHECKREG p1, 0x38E24E34; + CHECKREG p2, 0x6C164168; + CHECKREG p3, 0x8DF61F48; + CHECKREG p4, 0x9F4A38DC; + CHECKREG p5, 0xF47A238C; + CHECKREG sp, 0x740E2740; + CHECKREG fp, 0x5B05B058; + + imm32 p1, 0x29ab1def; + imm32 p2, 0x52781abc; + imm32 p3, 0xde201234; + imm32 p4, 0x23421899; + imm32 p5, 0x78912345; + imm32 sp, 0x98761232; + imm32 fp, 0x12341628; + P1 = P3 + ( P1 << 2 ); + P2 = P4 + ( P1 << 2 ); + P3 = P5 + ( P1 << 2 ); + P4 = SP + ( P1 << 2 ); + P5 = FP + ( P1 << 2 ); + FP = P1 + ( P1 << 2 ); + CHECKREG p1, 0x84CC89F0; + CHECKREG p2, 0x36744059; + CHECKREG p3, 0x8BC34B05; + CHECKREG p4, 0xABA839F2; + CHECKREG p5, 0x25663DE8; + CHECKREG fp, 0x97FEB1B0; + + imm32 p1, 0x893bcd2f; + imm32 p2, 0x56739a2c; + imm32 p3, 0x3ef03224; + imm32 p4, 0x23456329; + imm32 p5, 0x78312335; + imm32 sp, 0x98735423; + imm32 fp, 0x12343628; + P1 = P4 + ( P2 << 2 ); + P2 = P5 + ( P2 << 2 ); + P3 = SP + ( P2 << 2 ); + P4 = FP + ( P2 << 2 ); + SP = P1 + ( P2 << 2 ); + FP = P2 + ( P2 << 2 ); + CHECKREG p1, 0x7D13CBD9; + CHECKREG p2, 0xD1FF8BE5; + CHECKREG p3, 0xE07183B7; + CHECKREG p4, 0x5A3265BC; + CHECKREG sp, 0xC511FB6D; + CHECKREG fp, 0x19FDBB79; + + imm32 p1, 0x894bcde3; + imm32 p2, 0x56749ab3; + imm32 p3, 0x4ef04233; + imm32 p4, 0x24456493; + imm32 p5, 0x78412344; + imm32 sp, 0x98745434; + imm32 fp, 0x12344673; + P1 = P5 + ( P3 << 2 ); + P2 = SP + ( P3 << 2 ); + P3 = FP + ( P3 << 2 ); + P5 = P1 + ( P3 << 2 ); + SP = P2 + ( P3 << 2 ); + FP = P3 + ( P3 << 2 ); + CHECKREG p1, 0xB4022C10; + CHECKREG p2, 0xD4355D00; + CHECKREG p3, 0x4DF54F3F; + CHECKREG p5, 0xEBD7690C; + CHECKREG sp, 0x0C0A99FC; + CHECKREG fp, 0x85CA8C3B; + + imm32 p1, 0x49abc5ef; + imm32 p2, 0x46789a5c; + imm32 p3, 0x4ef01235; + imm32 p4, 0x53456899; + imm32 p5, 0x45912345; + imm32 sp, 0x48565432; + imm32 fp, 0x42355678; + P1 = SP + ( P4 << 2 ); + P2 = FP + ( P4 << 2 ); + P4 = P1 + ( P4 << 2 ); + P5 = P2 + ( P4 << 2 ); + SP = P3 + ( P4 << 2 ); + FP = P4 + ( P4 << 2 ); + CHECKREG p1, 0x956BF696; + CHECKREG p2, 0x8F4AF8DC; + CHECKREG p4, 0xE28198FA; + CHECKREG p5, 0x19515CC4; + CHECKREG sp, 0xD8F6761D; + CHECKREG fp, 0x6C87FCE2; + + imm32 p1, 0x85ab6def; + imm32 p2, 0x657896bc; + imm32 p3, 0xd6f01264; + imm32 p4, 0x25656896; + imm32 p5, 0x75962345; + imm32 sp, 0x95766432; + imm32 fp, 0x15345678; + P1 = FP + ( P5 << 2 ); + P3 = P1 + ( P5 << 2 ); + P4 = P2 + ( P5 << 2 ); + P5 = P3 + ( P5 << 2 ); + SP = P4 + ( P5 << 2 ); + FP = P5 + ( P5 << 2 ); + CHECKREG p1, 0xEB8CE38C; + CHECKREG p3, 0xC1E570A0; + CHECKREG p4, 0x3BD123D0; + CHECKREG p5, 0x983DFDB4; + CHECKREG sp, 0x9CC91AA0; + CHECKREG fp, 0xF935F484; + + imm32 p1, 0x89a7cdef; + imm32 p2, 0x56767abc; + imm32 p3, 0xdef61734; + imm32 p4, 0x73466879; + imm32 p5, 0x77962347; + imm32 sp, 0x98765432; + imm32 fp, 0x12375678; + P2 = P1 + ( SP << 2 ); + P3 = P2 + ( SP << 2 ); + P4 = P3 + ( SP << 2 ); + P5 = P4 + ( SP << 2 ); + SP = P5 + ( SP << 2 ); + FP = SP + ( SP << 2 ); + CHECKREG p2, 0xEB811EB7; + CHECKREG p3, 0x4D5A6F7F; + CHECKREG p4, 0xAF33C047; + CHECKREG p5, 0x110D110F; + CHECKREG sp, 0x72E661D7; + CHECKREG fp, 0x3E7FE933; + + imm32 p1, 0x88ab78ef; + imm32 p2, 0x56887a8c; + imm32 p3, 0x8ef87238; + imm32 p4, 0x28458899; + imm32 p5, 0x78817845; + imm32 sp, 0x98787482; + imm32 fp, 0x12348678; + P1 = P2 + ( FP << 2 ); + P2 = P3 + ( FP << 2 ); + P3 = P4 + ( FP << 2 ); + P4 = P5 + ( FP << 2 ); + P5 = SP + ( FP << 2 ); + SP = FP + ( FP << 2 ); + CHECKREG p1, 0x9F5A946C; + CHECKREG p2, 0xD7CA8C18; + CHECKREG p3, 0x7117A279; + CHECKREG p4, 0xC1539225; + CHECKREG p5, 0xE14A8E62; + CHECKREG sp, 0x5B06A058; + + pass diff --git a/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_n.s b/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_n.s new file mode 100644 index 0000000..af3406b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_n.s @@ -0,0 +1,164 @@ +//Original:/testcases/core/c_compi2opd_dr_add_i7_n/c_compi2opd_dr_add_i7_n.dsp +// Spec Reference: compi2opd dregs += imm7 negative +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +R0 += 0; +R1 += -1; +R2 += -2; +R3 += -3; +R4 += -4; +R5 += -5; +R6 += -6; +R7 += -7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFE; +CHECKREG r3, 0xFFFFFFFD; +CHECKREG r4, 0xFFFFFFFC; +CHECKREG r5, 0xFFFFFFFB; +CHECKREG r6, 0xFFFFFFFA; +CHECKREG r7, 0xFFFFFFF9; + +R0 += -8; +R1 += -9; +R2 += -10; +R3 += -11; +R4 += -12; +R5 += -13; +R6 += -14; +R7 += -15; +CHECKREG r0, 0xFFFFFFF8; +CHECKREG r1, 0xFFFFFFF6; +CHECKREG r2, 0xFFFFFFF4; +CHECKREG r3, 0xFFFFFFF2; +CHECKREG r4, 0xFFFFFFF0; +CHECKREG r5, 0xFFFFFFEE; +CHECKREG r6, 0xFFFFFFEC; +CHECKREG r7, 0xFFFFFFEA; + +R0 += -16; +R1 += -17; +R2 += -18; +R3 += -19; +R4 += -20; +R5 += -21; +R6 += -22; +R7 += -23; +CHECKREG r0, 0xFFFFFFE8; +CHECKREG r1, 0xFFFFFFE5; +CHECKREG r2, 0xFFFFFFE2; +CHECKREG r3, 0xFFFFFFDF; +CHECKREG r4, 0xFFFFFFDC; +CHECKREG r5, 0xFFFFFFD9; +CHECKREG r6, 0xFFFFFFD6; +CHECKREG r7, 0xFFFFFFD3; + +R0 += -24; +R1 += -25; +R2 += -26; +R3 += -27; +R4 += -28; +R5 += -29; +R6 += -30; +R7 += -31; +CHECKREG r0, 0xFFFFFFD0; +CHECKREG r1, 0xFFFFFFCC; +CHECKREG r2, 0xFFFFFFC8; +CHECKREG r3, 0xFFFFFFC4; +CHECKREG r4, 0xFFFFFFC0; +CHECKREG r5, 0xFFFFFFBC; +CHECKREG r6, 0xFFFFFFB8; +CHECKREG r7, 0xFFFFFFB4; + +R0 += -32; +R1 += -33; +R2 += -34; +R3 += -35; +R4 += -36; +R5 += -37; +R6 += -38; +R7 += -39; +CHECKREG r0, 0xFFFFFFB0; +CHECKREG r1, 0xFFFFFFAB; +CHECKREG r2, 0xFFFFFFA6; +CHECKREG r3, 0xFFFFFFA1; +CHECKREG r4, 0xFFFFFF9C; +CHECKREG r5, 0xFFFFFF97; +CHECKREG r6, 0xFFFFFF92; +CHECKREG r7, 0xFFFFFF8D; + +R0 += -40; +R1 += -41; +R2 += -42; +R3 += -43; +R4 += -44; +R5 += -45; +R6 += -46; +R7 += -47; +CHECKREG r0, 0xFFFFFF88; +CHECKREG r1, 0xFFFFFF82; +CHECKREG r2, 0xFFFFFF7C; +CHECKREG r3, 0xFFFFFF76; +CHECKREG r4, 0xFFFFFF70; +CHECKREG r5, 0xFFFFFF6A; +CHECKREG r6, 0xFFFFFF64; +CHECKREG r7, 0xFFFFFF5E; + +R0 += -48; +R1 += -49; +R2 += -50; +R3 += -51; +R4 += -52; +R5 += -53; +R6 += -54; +R7 += -55; +CHECKREG r0, 0xFFFFFF58; +CHECKREG r1, 0xFFFFFF51; +CHECKREG r2, 0xFFFFFF4A; +CHECKREG r3, 0xFFFFFF43; +CHECKREG r4, 0xFFFFFF3C; +CHECKREG r5, 0xFFFFFF35; +CHECKREG r6, 0xFFFFFF2E; +CHECKREG r7, 0xFFFFFF27; + +R0 += -56; +R1 += -57; +R2 += -58; +R3 += -59; +R4 += -60; +R5 += -61; +R6 += -62; +R7 += -63; +CHECKREG r0, 0xFFFFFF20; +CHECKREG r1, 0xFFFFFF18; +CHECKREG r2, 0xFFFFFF10; +CHECKREG r3, 0xFFFFFF08; +CHECKREG r4, 0xFFFFFF00; +CHECKREG r5, 0xFFFFFEF8; +CHECKREG r6, 0xFFFFFEF0; +CHECKREG r7, 0xFFFFFEE8; + +R0 += -64; +R1 += -64; +R2 += -64; +R3 += -64; +R4 += -64; +R5 += -64; +R6 += -64; +R7 += -64; +CHECKREG r0, 0xFFFFFEE0; +CHECKREG r1, 0xFFFFFED8; +CHECKREG r2, 0xFFFFFED0; +CHECKREG r3, 0xFFFFFEC8; +CHECKREG r4, 0xFFFFFEC0; +CHECKREG r5, 0xFFFFFEB8; +CHECKREG r6, 0xFFFFFEB0; +CHECKREG r7, 0xFFFFFEA8; + +pass diff --git a/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_p.s b/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_p.s new file mode 100644 index 0000000..66b4537 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_p.s @@ -0,0 +1,147 @@ +//Original:/testcases/core/c_compi2opd_dr_add_i7_p/c_compi2opd_dr_add_i7_p.dsp +// Spec Reference: compi2opd dregs += imm7 positive +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +R0 += 0; +R1 += 1; +R2 += 2; +R3 += 3; +R4 += 4; +R5 += 5; +R6 += 6; +R7 += 7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +R0 += 8; +R1 += 9; +R2 += 10; +R3 += 11; +R4 += 12; +R5 += 13; +R6 += 14; +R7 += 15; +CHECKREG r0, 0x00000008; +CHECKREG r1, 0x0000000A; +CHECKREG r2, 0x0000000C; +CHECKREG r3, 0x0000000E; +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000012; +CHECKREG r6, 0x00000014; +CHECKREG r7, 0x00000016; + +R0 += 16; +R1 += 17; +R2 += 18; +R3 += 19; +R4 += 20; +R5 += 21; +R6 += 22; +R7 += 23; +CHECKREG r0, 0x00000018; +CHECKREG r1, 0x0000001B; +CHECKREG r2, 0x0000001E; +CHECKREG r3, 0x00000021; +CHECKREG r4, 0x00000024; +CHECKREG r5, 0x00000027; +CHECKREG r6, 0x0000002A; +CHECKREG r7, 0x0000002D; + +R0 += 24; +R1 += 25; +R2 += 26; +R3 += 27; +R4 += 28; +R5 += 29; +R6 += 30; +R7 += 31; +CHECKREG r0, 0x00000030; +CHECKREG r1, 0x00000034; +CHECKREG r2, 0x00000038; +CHECKREG r3, 0x0000003C; +CHECKREG r4, 0x00000040; +CHECKREG r5, 0x00000044; +CHECKREG r6, 0x00000048; +CHECKREG r7, 0x0000004C; + +R0 += 32; +R1 += 33; +R2 += 34; +R3 += 35; +R4 += 36; +R5 += 37; +R6 += 38; +R7 += 39; +CHECKREG r0, 0x00000050; +CHECKREG r1, 0x00000055; +CHECKREG r2, 0x0000005A; +CHECKREG r3, 0x0000005F; +CHECKREG r4, 0x00000064; +CHECKREG r5, 0x00000069; +CHECKREG r6, 0x0000006E; +CHECKREG r7, 0x00000073; + +R0 += 40; +R1 += 41; +R2 += 42; +R3 += 43; +R4 += 44; +R5 += 45; +R6 += 46; +R7 += 47; +CHECKREG r0, 0x00000078; +CHECKREG r1, 0x0000007E; +CHECKREG r2, 0x00000084; +CHECKREG r3, 0x0000008A; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0x00000096; +CHECKREG r6, 0x0000009C; +CHECKREG r7, 0x000000A2; + +R0 += 48; +R1 += 49; +R2 += 50; +R3 += 51; +R4 += 52; +R5 += 53; +R6 += 54; +R7 += 55; +CHECKREG r0, 0x000000A8; +CHECKREG r1, 0x000000AF; +CHECKREG r2, 0x000000B6; +CHECKREG r3, 0x000000BD; +CHECKREG r4, 0x000000C4; +CHECKREG r5, 0x000000CB; +CHECKREG r6, 0x000000D2; +CHECKREG r7, 0x000000D9; + +R0 += 56; +R1 += 57; +R2 += 58; +R3 += 59; +R4 += 60; +R5 += 61; +R6 += 62; +R7 += 63; +CHECKREG r0, 0x000000E0; +CHECKREG r1, 0x000000E8; +CHECKREG r2, 0x000000F0; +CHECKREG r3, 0x000000F8; +CHECKREG r4, 0x00000100; +CHECKREG r5, 0x00000108; +CHECKREG r6, 0x00000110; +CHECKREG r7, 0x00000118; + +pass diff --git a/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_n.s b/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_n.s new file mode 100644 index 0000000..509929d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_n.s @@ -0,0 +1,166 @@ +//Original:/testcases/core/c_compi2opd_dr_eq_i7_n/c_compi2opd_dr_eq_i7_n.dsp +// Spec Reference: compi2opd dregs = imm7 negative +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + + +R0 = -0; +R1 = -1; +R2 = -2; +R3 = -3; +R4 = -4; +R5 = -5; +R6 = -6; +R7 = -7; +CHECKREG r0, -0; +CHECKREG r1, -1; +CHECKREG r2, -2; +CHECKREG r3, -3; +CHECKREG r4, -4; +CHECKREG r5, -5; +CHECKREG r6, -6; +CHECKREG r7, -7; + +R0 = -8; +R1 = -9; +R2 = -10; +R3 = -11; +R4 = -12; +R5 = -13; +R6 = -14; +R7 = -15; +CHECKREG r0, -8; +CHECKREG r1, -9; +CHECKREG r2, -10; +CHECKREG r3, -11; +CHECKREG r4, -12; +CHECKREG r5, -13; +CHECKREG r6, -14; +CHECKREG r7, -15; + +R0 = -16; +R1 = -17; +R2 = -18; +R3 = -19; +R4 = -20; +R5 = -21; +R6 = -22; +R7 = -23; +CHECKREG r0, -16; +CHECKREG r1, -17; +CHECKREG r2, -18; +CHECKREG r3, -19; +CHECKREG r4, -20; +CHECKREG r5, -21; +CHECKREG r6, -22; +CHECKREG r7, -23; + +R0 = -24; +R1 = -25; +R2 = -26; +R3 = -27; +R4 = -28; +R5 = -29; +R6 = -30; +R7 = -31; +CHECKREG r0, -24; +CHECKREG r1, -25; +CHECKREG r2, -26; +CHECKREG r3, -27; +CHECKREG r4, -28; +CHECKREG r5, -29; +CHECKREG r6, -30; +CHECKREG r7, -31; + +R0 = -32; +R1 = -33; +R2 = -34; +R3 = -35; +R4 = -36; +R5 = -37; +R6 = -38; +R7 = -39; +CHECKREG r0, -32; +CHECKREG r1, -33; +CHECKREG r2, -34; +CHECKREG r3, -35; +CHECKREG r4, -36; +CHECKREG r5, -37; +CHECKREG r6, -38; +CHECKREG r7, -39; + +R0 = -40; +R1 = -41; +R2 = -42; +R3 = -43; +R4 = -44; +R5 = -45; +R6 = -46; +R7 = -47; +CHECKREG r0, -40; +CHECKREG r1, -41; +CHECKREG r2, -42; +CHECKREG r3, -43; +CHECKREG r4, -44; +CHECKREG r5, -45; +CHECKREG r6, -46; +CHECKREG r7, -47; + +R0 = -48; +R1 = -49; +R2 = -50; +R3 = -51; +R4 = -52; +R5 = -53; +R6 = -54; +R7 = -55; +CHECKREG r0, -48; +CHECKREG r1, -49; +CHECKREG r2, -50; +CHECKREG r3, -51; +CHECKREG r4, -52; +CHECKREG r5, -53; +CHECKREG r6, -54; +CHECKREG r7, -55; + +R0 = -56; +R1 = -57; +R2 = -58; +R3 = -59; +R4 = -60; +R5 = -61; +R6 = -62; +R7 = -63; +CHECKREG r0, -56; +CHECKREG r1, -57; +CHECKREG r2, -58; +CHECKREG r3, -59; +CHECKREG r4, -60; +CHECKREG r5, -61; +CHECKREG r6, -62; +CHECKREG r7, -63; + +R0 = -64; +R1 = -64; +R2 = -64; +R3 = -64; +R4 = -64; +R5 = -64; +R6 = -64; +R7 = -64; +CHECKREG r0, -64; +CHECKREG r1, -64; +CHECKREG r2, -64; +CHECKREG r3, -64; +CHECKREG r4, -64; +CHECKREG r5, -64; +CHECKREG r6, -64; +CHECKREG r7, -64; + + +pass diff --git a/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_p.s b/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_p.s new file mode 100644 index 0000000..5e792cc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_p.s @@ -0,0 +1,147 @@ +//Original:/testcases/core/c_compi2opd_dr_eq_i7_p/c_compi2opd_dr_eq_i7_p.dsp +// Spec Reference: compi2opd dregs = imm7 positive +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +R0 = 0; +R1 = 1; +R2 = 2; +R3 = 3; +R4 = 4; +R5 = 5; +R6 = 6; +R7 = 7; +CHECKREG r0, 0; +CHECKREG r1, 1; +CHECKREG r2, 2; +CHECKREG r3, 3; +CHECKREG r4, 4; +CHECKREG r5, 5; +CHECKREG r6, 6; +CHECKREG r7, 7; + +R0 = 8; +R1 = 9; +R2 = 10; +R3 = 11; +R4 = 12; +R5 = 13; +R6 = 14; +R7 = 15; +CHECKREG r0, 8; +CHECKREG r1, 9; +CHECKREG r2, 10; +CHECKREG r3, 11; +CHECKREG r4, 12; +CHECKREG r5, 13; +CHECKREG r6, 14; +CHECKREG r7, 15; + +R0 = 16; +R1 = 17; +R2 = 18; +R3 = 19; +R4 = 20; +R5 = 21; +R6 = 22; +R7 = 23; +CHECKREG r0, 16; +CHECKREG r1, 17; +CHECKREG r2, 18; +CHECKREG r3, 19; +CHECKREG r4, 20; +CHECKREG r5, 21; +CHECKREG r6, 22; +CHECKREG r7, 23; + +R0 = 24; +R1 = 25; +R2 = 26; +R3 = 27; +R4 = 28; +R5 = 29; +R6 = 30; +R7 = 31; +CHECKREG r0, 24; +CHECKREG r1, 25; +CHECKREG r2, 26; +CHECKREG r3, 27; +CHECKREG r4, 28; +CHECKREG r5, 29; +CHECKREG r6, 30; +CHECKREG r7, 31; + +R0 = 32; +R1 = 33; +R2 = 34; +R3 = 35; +R4 = 36; +R5 = 37; +R6 = 38; +R7 = 39; +CHECKREG r0, 32; +CHECKREG r1, 33; +CHECKREG r2, 34; +CHECKREG r3, 35; +CHECKREG r4, 36; +CHECKREG r5, 37; +CHECKREG r6, 38; +CHECKREG r7, 39; + +R0 = 40; +R1 = 41; +R2 = 42; +R3 = 43; +R4 = 44; +R5 = 45; +R6 = 46; +R7 = 47; +CHECKREG r0, 40; +CHECKREG r1, 41; +CHECKREG r2, 42; +CHECKREG r3, 43; +CHECKREG r4, 44; +CHECKREG r5, 45; +CHECKREG r6, 46; +CHECKREG r7, 47; + +R0 = 48; +R1 = 49; +R2 = 50; +R3 = 51; +R4 = 52; +R5 = 53; +R6 = 54; +R7 = 55; +CHECKREG r0, 48; +CHECKREG r1, 49; +CHECKREG r2, 50; +CHECKREG r3, 51; +CHECKREG r4, 52; +CHECKREG r5, 53; +CHECKREG r6, 54; +CHECKREG r7, 55; + +R0 = 56; +R1 = 57; +R2 = 58; +R3 = 59; +R4 = 60; +R5 = 61; +R6 = 62; +R7 = 63; +CHECKREG r0, 56; +CHECKREG r1, 57; +CHECKREG r2, 58; +CHECKREG r3, 59; +CHECKREG r4, 60; +CHECKREG r5, 61; +CHECKREG r6, 62; +CHECKREG r7, 63; + +pass diff --git a/sim/testsuite/sim/bfin/c_compi2opd_flags.S b/sim/testsuite/sim/bfin/c_compi2opd_flags.S new file mode 100644 index 0000000..5438e91 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_compi2opd_flags.S @@ -0,0 +1,600 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opd_flags/c_compi2opd_flags.dsp +// Spec Reference: compi2opd dregs += imm7 flags (az, an, ac, av0) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + INIT_R_REGS 0; + ASTAT = R0; // initialize astat + +// AZ for R0 + imm32 r0, 0x00000000; + R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R0 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R0 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R0; + R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R0 + imm32 r0, 0xffffffff; + R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R0; + R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0xFFFFFFFF; + CHECKREG r1, 0x00000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R0 + imm32 r0, 0x7fffffff; + R0 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R1 = R0; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R0; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFE; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); //C + CHECKREG r7, (_VS|_V|_V_COPY|_AN); // A + +// AZ, AN, AC, AV0 for R0 + R0 = 0; + ASTAT = R0; + imm32 r0, 0x80000000; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R1 = R0; + R0 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R0; + R0 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000001; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x80000000; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R0 + R1 = 0; + ASTAT = R1; + imm32 r1, 0x00000000; + R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R1 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R1 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R1; + R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R1 + imm32 r1, 0xffffffff; + R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R1; + R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R1 + imm32 r1, 0x7fffffff; + R1 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R1; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R1; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFE; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R1 + R1 = 0; + ASTAT = R1; + imm32 r1, 0x80000000; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R1; + R1 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R1; + R1 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000001; + CHECKREG r2, 0x80000000; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R2 + imm32 r2, 0x00000000; + ASTAT = R2; + R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R2 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R2 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R2; + R2 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R2 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R2 + imm32 r2, 0xffffffff; + R2 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R2; + R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R2 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r2, 0xFFFFFFFF; + CHECKREG r1, 0x00000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R2 + imm32 r2, 0x7fffffff; + R2 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R2; + R2 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R2; + R2 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x7FFFFFFE; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R2 + R2 = 0; + ASTAT = R2; + imm32 r2, 0x80000000; + R2 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R2; + R2 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R2; + R2 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x80000001; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R3 + imm32 r3, 0x00000000; + ASTAT = R3; + R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R3 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R3 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R3; + R3 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R3 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, 0x00000000; + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R3 + imm32 r3, 0xffffffff; + R3 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R3; + R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R3 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R3 + imm32 r3, 0x7fffffff; + R3 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R3; + R3 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R3; + R3 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r3, 0x7FFFFFFE; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R3 + R3 = 0; + ASTAT = R3; + imm32 r3, 0x80000000; + R3 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R3; + R3 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R3; + R3 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000000; + CHECKREG r3, 0x80000001; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R4 + imm32 r4, 0x00000000; + ASTAT = R4; + R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R4 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R4 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R4; + R4 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R3 = ASTAT; + R4 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, (_AN); + CHECKREG r4, 0x00000000; + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R4 + imm32 r4, 0xffffffff; + R4 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R4; + R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R4 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R4 + imm32 r4, 0x7fffffff; + R4 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R1 = R4; + R4 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R4; + R4 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r4, 0x7FFFFFFE; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R4 + R4 = 0; + ASTAT = R4; + imm32 r4, 0x80000000; + R4 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R1 = R4; + R4 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R4; + R4 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x80000000; + CHECKREG r4, 0x80000001; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R5 + imm32 r5, 0x00000000; + ASTAT = R5; + R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R5 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R5 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + R0 = R5; + R5 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R5 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R5 + imm32 r5, 0xffffffff; + R5 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R5; + R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R5 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r4, (_AN); + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R5 + imm32 r5, 0x7fffffff; + R5 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R5; + R5 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R5; + R5 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r4, (_VS|_AC0|_AC0_COPY); + CHECKREG r5, 0x7FFFFFFE; + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R5 + R5 = 0; + ASTAT = R5; + imm32 r5, 0x80000000; + R5 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R5; + R5 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R5; + R5 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r2, 0x80000000; + CHECKREG r4, (_VS|_AN); + CHECKREG r5, 0x80000001; + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R6 + imm32 r6, 0x00000000; + ASTAT = R6; + R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R6 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R0 = ASTAT; + R6 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R6; + R6 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R6 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R6 + imm32 r6, 0xffffffff; + R6 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R6; + R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R4 = ASTAT; + R6 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r4, (_AZ); + CHECKREG r5, (_AN); + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R6 + R6 = 0; + ASTAT = R6; + imm32 r6, 0x7fffffff; + R6 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R6; + R6 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R4 = ASTAT; + R1 = R6; + R6 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, 0x7FFFFFFE; + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R6 + R6 = 0; + ASTAT = R6; + imm32 r6, 0x80000000; + R6 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R6; + R6 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R4 = ASTAT; + R1 = R6; + R6 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000000; + CHECKREG r4, (_VS|_V|_V_COPY|_AN); + CHECKREG r5, (_VS|_AN); + CHECKREG r6, 0x80000001; + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R7 + imm32 r7, 0x00000000; + ASTAT = R7; + R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R1 = ASTAT; + R7 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R7 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R7; + R7 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R7 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, (_AZ); + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + +// AN, AC for R7 + imm32 r7, 0xffffffff; + R7 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R4 = ASTAT; + R0 = R7; + R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R7 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r4, (_AC0|_AC0_COPY|_AZ); + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, 0xFFFFFFFF; + +// AC, AV0 for R7 + R7 = 0; + ASTAT = R7; + imm32 r7, 0x7fffffff; + R7 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R4 = ASTAT; + R0 = R7; + R7 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R7; + R7 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r4, (_VS|_V|_V_COPY|_AN); + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, 0x7FFFFFFE; + +// AZ, AN, AC, AV0 for R7 + R7 = 0; + ASTAT = R7; + imm32 r7, 0x80000000; + R7 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R4 = ASTAT; + R0 = R7; + R7 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R7; + R7 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000000; + CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, 0x80000001; + + pass diff --git a/sim/testsuite/sim/bfin/c_compi2opd_flags_2.S b/sim/testsuite/sim/bfin/c_compi2opd_flags_2.S new file mode 100644 index 0000000..83bf1b0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_compi2opd_flags_2.S @@ -0,0 +1,600 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opd_flags_2/c_compi2opd_flags_2.dsp +// Spec Reference: compi2opd dregs += imm7 flags_2 (az, an, ac, av0) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = R0; // initialize astat + +// AZ for R0 + imm32 r0, 0x00000000; + R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R0 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R0 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R0; + R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R0 + imm32 r0, 0xffffffff; + R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R0; + R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0xFFFFFFFF; + CHECKREG r1, 0x00000000; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R0 + imm32 r0, 0x7fffffff; + R0 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R1 = R0; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R0; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFE; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY|_V|_V_COPY|_VS); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R0 + R0 = 0; + ASTAT = R0; + imm32 r0, 0x80000000; + R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R1 = R0; + R0 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R0; + R0 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000001; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x80000000; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V_COPY|_V|_AN); + CHECKREG r7, (_VS|_V_COPY|_V|_AC0|_AC0_COPY); + +// AZ for R0 + imm32 r1, 0x00000000; + ASTAT = R1; + R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R1 += 1; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R1 += -1; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R1; + R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R1 + r1 = 0; + ASTAT = r1; + imm32 r1, 0xffffffff; + R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R1; + R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, (_AZ); + CHECKREG r7, (_AC0|_AC0_COPY|_AZ); + +// AC, AV0 for R1 + imm32 r1, 0x7fffffff; + R1 += 1; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R1; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R1; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x7FFFFFFE; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R1 + R1 = 0; + ASTAT = R1; + imm32 r1, 0x80000000; + R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R1; + R1 += 1; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R1; + R1 += 1; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x80000001; + CHECKREG r2, 0x80000000; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R2 + imm32 r2, 0x00000000; + ASTAT = R2; + R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R2 += 2; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R2 += -2; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R2; + R2 += -2; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R2 += 2; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R2 + R2 = 0; + ASTAT = R2; + imm32 r2, 0xffffffff; + R2 += 2; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R2; + R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R2 += -2; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r2, 0xFFFFFFFF; + CHECKREG r1, (_AZ); + CHECKREG r5, (_AN); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R2 + imm32 r2, 0x7fffffff; + R2 += 2; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R2; + R2 += -2; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R2; + R2 += -2; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000001; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x7FFFFFFD; + CHECKREG r5, (_AC0|_AC0_COPY|_VS); + CHECKREG r6, (_AC0|_AC0_COPY|_VS|_V|_V_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R2 + R2 = 0; + ASTAT = R2; + imm32 r2, 0x80000000; + R2 += -2; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R2; + R2 += 2; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R2; + R2 += 2; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFE; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x80000002; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_AC0|_AC0_COPY|_VS|_V|_V_COPY); + +// AZ for R3 + imm32 r3, 0x00000000; + ASTAT = R3; + R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R3 += 3; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R3 += -3; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R3; + R3 += -3; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R3 += 3; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, 0x00000000; + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R3 + imm32 r3, 0xffffffff; + R3 += 3; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R3; + R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R3 += -3; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000002; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R3 + imm32 r3, 0x7fffffff; + R3 += 3; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R3; + R3 += -3; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R3; + R3 += -3; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000002; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r3, 0x7FFFFFFC; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_AC0|_AC0_COPY|_VS|_V|_V_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R3 + R3 = 0; + ASTAT = R3; + imm32 r3, 0x80000000; + R3 += -3; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R3; + R3 += 3; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R3; + R3 += 3; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFD; + CHECKREG r1, 0x80000000; + CHECKREG r3, 0x80000003; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R4 + imm32 r4, 0x00000000; + ASTAT = R4; + R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R4 += 4; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R4 += -4; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R4; + R4 += -4; // az = 0 an = 1 ac = 0 av0 = 0 + R3 = ASTAT; + R4 += 4; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r1, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, (_AN); + CHECKREG r4, 0x00000000; + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R4 + imm32 r4, 0xffffffff; + R4 += 4; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R4; + R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R4 += -4; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x00000003; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, (_AN); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R4 + imm32 r4, 0x7fffffff; + R4 += 4; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R1 = R4; + R4 += -4; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R4; + R4 += -4; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x80000003; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r4, 0x7FFFFFFB; + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R4 + R4 = 0; + ASTAT = R4; + imm32 r4, 0x80000000; + R4 += -4; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R1 = R4; + R4 += 4; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R4; + R4 += 4; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x7FFFFFFC; + CHECKREG r2, 0x80000000; + CHECKREG r4, 0x80000004; + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R5 + imm32 r5, 0x00000000; + ASTAT = R5; + R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R5 += 5; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R5 += -5; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + R0 = R5; + R5 += -5; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R5 += 5; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R5 + imm32 r5, 0xffffffff; + R5 += 5; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R0 = R5; + R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R5 += -5; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x00000004; + CHECKREG r4, (_AN); + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R5 + imm32 r5, 0x7fffffff; + R5 += 5; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R5; + R5 += -5; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R2 = R5; + R5 += -5; // az = 0 an = 0 ac = 1 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x80000004; + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r4, (_VS|_AC0|_AC0_COPY); + CHECKREG r5, 0x7FFFFFFA; + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R5 + R5 = 0; + ASTAT = R5; + imm32 r5, 0x80000000; + R5 += -5; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R5; + R5 += 5; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R2 = R5; + R5 += 5; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + CHECKREG r0, 0x7FFFFFFB; + CHECKREG r2, 0x80000000; + CHECKREG r4, (_VS|_AN); + CHECKREG r5, 0x80000005; + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R6 + imm32 r6, 0x00000000; + ASTAT = R6; + R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R7 = ASTAT; + R6 += 6; // az = 0 an = 0 ac = 0 av0 = 0 + R0 = ASTAT; + R6 += -6; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R1 = R6; + R6 += -6; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R6 += 6; // az = 1 an = 0 ac = 1 av0 = 0 + R3 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r3, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, (_AZ); + +// AN, AC for R6 + imm32 r6, 0xffffffff; + R6 += 6; // az = 1 an = 0 ac = 1 av0 = 0 + R7 = ASTAT; + R1 = R6; + R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R4 = ASTAT; + R6 += -6; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r1, 0x00000005; + CHECKREG r4, 0x00000000; + CHECKREG r5, (_AN); + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, (_AC0|_AC0_COPY); + +// AC, AV0 for R6 + imm32 r6, 0x7fffffff; + R6 += 6; // az = 0 an = 1 ac = 0 av0 = 1 + R7 = ASTAT; + R0 = R6; + R6 += -6; // az = 0 an = 0 ac = 1 av0 = 1 + R4 = ASTAT; + R1 = R6; + R6 += -6; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000005; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, 0x7FFFFFF9; + CHECKREG r7, (_VS|_V|_V_COPY|_AN); + +// AZ, AN, AC, AV0 for R6 + R6 = 0; + ASTAT = R6; + imm32 r6, 0x80000000; + R6 += -6; // az = 0 an = 0 ac = 1 av0 = 1 + R7 = ASTAT; + R0 = R6; + R6 += 6; // az = 1 an = 1 ac = 0 av0 = 1 + R4 = ASTAT; + R1 = R6; + R6 += 6; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFFA; + CHECKREG r1, 0x80000000; + CHECKREG r4, (_VS|_V|_V_COPY|_AN); + CHECKREG r5, (_VS|_AN); + CHECKREG r6, 0x80000006; + CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + +// AZ for R7 + imm32 r7, 0x00000000; + ASTAT = R7; + R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R1 = ASTAT; + R7 += 7; // az = 0 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R7 += -7; // az = 1 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + R0 = R7; + R7 += -7; // az = 0 an = 1 ac = 0 av0 = 0 + R4 = ASTAT; + R7 += 7; // az = 1 an = 0 ac = 1 av0 = 0 + R2 = ASTAT; + CHECKREG r0, 0x00000000; + CHECKREG r1, (_AZ); + CHECKREG r2, (_AC0|_AC0_COPY|_AZ); + CHECKREG r4, (_AN); + CHECKREG r5, (_AC0|_AC0_COPY|_AZ); + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + +// AN, AC for R7 + imm32 r7, 0xffffffff; + R7 += 7; // az = 1 an = 0 ac = 1 av0 = 0 + R4 = ASTAT; + R0 = R7; + R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 + R6 = ASTAT; + R7 += -7; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x00000006; + CHECKREG r4, (_AC0|_AC0_COPY); + CHECKREG r5, (_AN); + CHECKREG r6, 0x00000000; + CHECKREG r7, 0xFFFFFFFF; + +// AC, AV0 for R7 + imm32 r7, 0x7fffffff; + R7 += 7; // az = 0 an = 1 ac = 0 av0 = 1 + R4 = ASTAT; + R0 = R7; + R7 += -7; // az = 0 an = 0 ac = 1 av0 = 1 + R6 = ASTAT; + R1 = R7; + R7 += -7; // az = 0 an = 0 ac = 1 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x80000006; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r4, (_VS|_V|_V_COPY|_AN); + CHECKREG r5, (_VS|_AC0|_AC0_COPY); + CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r7, 0x7FFFFFF8; + +// AZ, AN, AC, AV0 for R7 + R7 = 0; + ASTAT = R7; + imm32 r7, 0x80000000; + R7 += -7; // az = 0 an = 0 ac = 1 av0 = 1 + R4 = ASTAT; + R0 = R7; + R7 += 7; // az = 1 an = 1 ac = 0 av0 = 1 + R6 = ASTAT; + R1 = R7; + R7 += 7; // az = 0 an = 1 ac = 0 av0 = 0 + R5 = ASTAT; + CHECKREG r0, 0x7FFFFFF9; + CHECKREG r1, 0x80000000; + CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); + CHECKREG r5, (_VS|_AN); + CHECKREG r6, (_VS|_V|_V_COPY|_AN); + CHECKREG r7, 0x80000007; + + pass diff --git a/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_n.s b/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_n.s new file mode 100644 index 0000000..b63cb86 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_n.s @@ -0,0 +1,149 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_n/c_compi2opp_pr_add_i7_n.dsp +// Spec Reference: compi2opp pregs += imm7 negative +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + INIT_P_REGS 0; + + imm32 sp, 0x00000000; + imm32 fp, 0x00000000; + + P1 += -1; + P2 += -2; + P3 += -3; + P4 += -4; + P5 += -5; + SP += -6; + FP += -7; + CHECKREG p1, 0xFFFFFFFF; + CHECKREG p2, 0xFFFFFFFE; + CHECKREG p3, 0xFFFFFFFD; + CHECKREG p4, 0xFFFFFFFC; + CHECKREG p5, 0xFFFFFFFB; + CHECKREG sp, 0xFFFFFFFA; + CHECKREG fp, 0xFFFFFFF9; + + P1 += -9; + P2 += -10; + P3 += -11; + P4 += -12; + P5 += -13; + SP += -14; + FP += -15; + CHECKREG p1, 0xFFFFFFF6; + CHECKREG p2, 0xFFFFFFF4; + CHECKREG p3, 0xFFFFFFF2; + CHECKREG p4, 0xFFFFFFF0; + CHECKREG p5, 0xFFFFFFEE; + CHECKREG sp, 0xFFFFFFEC; + CHECKREG fp, 0xFFFFFFEA; + + P1 += -17; + P2 += -18; + P3 += -19; + P4 += -20; + P5 += -21; + SP += -22; + FP += -23; + CHECKREG p1, 0xFFFFFFE5; + CHECKREG p2, 0xFFFFFFE2; + CHECKREG p3, 0xFFFFFFDF; + CHECKREG p4, 0xFFFFFFDC; + CHECKREG p5, 0xFFFFFFD9; + CHECKREG sp, 0xFFFFFFD6; + CHECKREG fp, 0xFFFFFFD3; + + P1 += -25; + P2 += -26; + P3 += -27; + P4 += -28; + P5 += -29; + SP += -30; + FP += -31; + CHECKREG p1, 0xFFFFFFCC; + CHECKREG p2, 0xFFFFFFC8; + CHECKREG p3, 0xFFFFFFC4; + CHECKREG p4, 0xFFFFFFC0; + CHECKREG p5, 0xFFFFFFBC; + CHECKREG sp, 0xFFFFFFB8; + CHECKREG fp, 0xFFFFFFB4; + + P1 += -33; + P2 += -34; + P3 += -35; + P4 += -36; + P5 += -37; + SP += -38; + FP += -39; + CHECKREG p1, 0xFFFFFFAB; + CHECKREG p2, 0xFFFFFFA6; + CHECKREG p3, 0xFFFFFFA1; + CHECKREG p4, 0xFFFFFF9C; + CHECKREG p5, 0xFFFFFF97; + CHECKREG sp, 0xFFFFFF92; + CHECKREG fp, 0xFFFFFF8D; + + P1 += -41; + P2 += -42; + P3 += -43; + P4 += -44; + P5 += -45; + SP += -46; + FP += -47; + CHECKREG p1, 0xFFFFFF82; + CHECKREG p2, 0xFFFFFF7C; + CHECKREG p3, 0xFFFFFF76; + CHECKREG p4, 0xFFFFFF70; + CHECKREG p5, 0xFFFFFF6A; + CHECKREG sp, 0xFFFFFF64; + CHECKREG fp, 0xFFFFFF5E; + + P1 += -49; + P2 += -50; + P3 += -51; + P4 += -52; + P5 += -53; + SP += -54; + FP += -55; + CHECKREG p1, 0xFFFFFF51; + CHECKREG p2, 0xFFFFFF4A; + CHECKREG p3, 0xFFFFFF43; + CHECKREG p4, 0xFFFFFF3C; + CHECKREG p5, 0xFFFFFF35; + CHECKREG sp, 0xFFFFFF2E; + CHECKREG fp, 0xFFFFFF27; + + P1 += -57; + P2 += -58; + P3 += -59; + P4 += -60; + P5 += -61; + SP += -62; + FP += -63; + CHECKREG p1, 0xFFFFFF18; + CHECKREG p2, 0xFFFFFF10; + CHECKREG p3, 0xFFFFFF08; + CHECKREG p4, 0xFFFFFF00; + CHECKREG p5, 0xFFFFFEF8; + CHECKREG sp, 0xFFFFFEF0; + CHECKREG fp, 0xFFFFFEE8; + + P1 += -64; + P2 += -64; + P3 += -64; + P4 += -64; + P5 += -64; + SP += -64; + FP += -64; + CHECKREG p1, 0xFFFFFED8; + CHECKREG p2, 0xFFFFFED0; + CHECKREG p3, 0xFFFFFEC8; + CHECKREG p4, 0xFFFFFEC0; + CHECKREG p5, 0xFFFFFEB8; + CHECKREG sp, 0xFFFFFEB0; + CHECKREG fp, 0xFFFFFEA8; + + pass diff --git a/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_p.s b/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_p.s new file mode 100644 index 0000000..75336a8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_p.s @@ -0,0 +1,116 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_p/c_compi2opp_pr_add_i7_p.dsp +// Spec Reference: compi2opp pregs += imm7 positive +# mach: bfin + +.include "testutils.inc" + start + + INIT_P_REGS 0; + + imm32 fp, 0x00000000; + + P1 += 1; + P2 += 2; + P3 += 3; + P4 += 4; + P5 += 5; + FP += 7; + CHECKREG p1, 0x00000001; + CHECKREG p2, 0x00000002; + CHECKREG p3, 0x00000003; + CHECKREG p4, 0x00000004; + CHECKREG p5, 0x00000005; + CHECKREG fp, 0x00000007; + + P1 += 9; + P2 += 10; + P3 += 11; + P4 += 12; + P5 += 13; + FP += 15; + CHECKREG p1, 0x0000000A; + CHECKREG p2, 0x0000000C; + CHECKREG p3, 0x0000000E; + CHECKREG p4, 0x00000010; + CHECKREG p5, 0x00000012; + CHECKREG fp, 0x00000016; + + P1 += 17; + P2 += 18; + P3 += 19; + P4 += 20; + P5 += 21; + FP += 23; + CHECKREG p1, 0x0000001B; + CHECKREG p2, 0x0000001E; + CHECKREG p3, 0x00000021; + CHECKREG p4, 0x00000024; + CHECKREG p5, 0x00000027; + CHECKREG fp, 0x0000002D; + + P1 += 25; + P2 += 26; + P3 += 27; + P4 += 28; + P5 += 29; + FP += 31; + CHECKREG p1, 0x00000034; + CHECKREG p2, 0x00000038; + CHECKREG p3, 0x0000003C; + CHECKREG p4, 0x00000040; + CHECKREG p5, 0x00000044; + CHECKREG fp, 0x0000004C; + + P1 += 33; + P2 += 34; + P3 += 35; + P4 += 36; + P5 += 37; + FP += 39; + CHECKREG p1, 0x00000055; + CHECKREG p2, 0x0000005A; + CHECKREG p3, 0x0000005F; + CHECKREG p4, 0x00000064; + CHECKREG p5, 0x00000069; + CHECKREG fp, 0x00000073; + + P1 += 41; + P2 += 42; + P3 += 43; + P4 += 44; + P5 += 45; + FP += 47; + CHECKREG p1, 0x0000007E; + CHECKREG p2, 0x00000084; + CHECKREG p3, 0x0000008A; + CHECKREG p4, 0x00000090; + CHECKREG p5, 0x00000096; + CHECKREG fp, 0x000000A2; + + P1 += 49; + P2 += 50; + P3 += 51; + P4 += 52; + P5 += 53; + FP += 55; + CHECKREG p1, 0x000000AF; + CHECKREG p2, 0x000000B6; + CHECKREG p3, 0x000000BD; + CHECKREG p4, 0x000000C4; + CHECKREG p5, 0x000000CB; + CHECKREG fp, 0x000000D9; + + P1 += 57; + P2 += 58; + P3 += 59; + P4 += 60; + P5 += 61; + FP += 63; + CHECKREG p1, 0x000000E8; + CHECKREG p2, 0x000000F0; + CHECKREG p3, 0x000000F8; + CHECKREG p4, 0x00000100; + CHECKREG p5, 0x00000108; + CHECKREG fp, 0x00000118; + + pass diff --git a/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_n.s b/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_n.s new file mode 100644 index 0000000..efeeb69 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_n.s @@ -0,0 +1,161 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_n/c_compi2opp_pr_eq_i7_n.dsp +// Spec Reference: compi2opp pregs = imm7 negative +# mach: bfin + +.include "testutils.inc" + start + + R0 = -0; + P1 = -1; + P2 = -2; + P3 = -3; + P4 = -4; + P5 = -5; + SP = -6; + FP = -7; + CHECKREG r0, -0; + CHECKREG p1, -1; + CHECKREG p2, -2; + CHECKREG p3, -3; + CHECKREG p4, -4; + CHECKREG p5, -5; + CHECKREG sp, -6; + CHECKREG fp, -7; + + R0 = -8; + P1 = -9; + P2 = -10; + P3 = -11; + P4 = -12; + P5 = -13; + SP = -14; + FP = -15; + CHECKREG r0, -8; + CHECKREG p1, -9; + CHECKREG p2, -10; + CHECKREG p3, -11; + CHECKREG p4, -12; + CHECKREG p5, -13; + CHECKREG sp, -14; + CHECKREG fp, -15; + + R0 = -16; + P1 = -17; + P2 = -18; + P3 = -19; + P4 = -20; + P5 = -21; + SP = -22; + FP = -23; + CHECKREG r0, -16; + CHECKREG p1, -17; + CHECKREG p2, -18; + CHECKREG p3, -19; + CHECKREG p4, -20; + CHECKREG p5, -21; + CHECKREG sp, -22; + CHECKREG fp, -23; + + R0 = -24; + P1 = -25; + P2 = -26; + P3 = -27; + P4 = -28; + P5 = -29; + SP = -30; + FP = -31; + CHECKREG r0, -24; + CHECKREG p1, -25; + CHECKREG p2, -26; + CHECKREG p3, -27; + CHECKREG p4, -28; + CHECKREG p5, -29; + CHECKREG sp, -30; + CHECKREG fp, -31; + + R0 = -32; + P1 = -33; + P2 = -34; + P3 = -35; + P4 = -36; + P5 = -37; + SP = -38; + FP = -39; + CHECKREG r0, -32; + CHECKREG p1, -33; + CHECKREG p2, -34; + CHECKREG p3, -35; + CHECKREG p4, -36; + CHECKREG p5, -37; + CHECKREG sp, -38; + CHECKREG fp, -39; + + R0 = -40; + P1 = -41; + P2 = -42; + P3 = -43; + P4 = -44; + P5 = -45; + SP = -46; + FP = -47; + CHECKREG r0, -40; + CHECKREG p1, -41; + CHECKREG p2, -42; + CHECKREG p3, -43; + CHECKREG p4, -44; + CHECKREG p5, -45; + CHECKREG sp, -46; + CHECKREG fp, -47; + + R0 = -48; + P1 = -49; + P2 = -50; + P3 = -51; + P4 = -52; + P5 = -53; + SP = -54; + FP = -55; + CHECKREG r0, -48; + CHECKREG p1, -49; + CHECKREG p2, -50; + CHECKREG p3, -51; + CHECKREG p4, -52; + CHECKREG p5, -53; + CHECKREG sp, -54; + CHECKREG fp, -55; + + R0 = -56; + P1 = -57; + P2 = -58; + P3 = -59; + P4 = -60; + P5 = -61; + SP = -62; + FP = -63; + CHECKREG r0, -56; + CHECKREG p1, -57; + CHECKREG p2, -58; + CHECKREG p3, -59; + CHECKREG p4, -60; + CHECKREG p5, -61; + CHECKREG sp, -62; + CHECKREG fp, -63; + + R0 = -64; + P1 = -64; + P2 = -64; + P3 = -64; + P4 = -64; + P5 = -64; + SP = -64; + FP = -64; + CHECKREG r0, -64; + CHECKREG p1, -64; + CHECKREG p2, -64; + CHECKREG p3, -64; + CHECKREG p4, -64; + CHECKREG p5, -64; + CHECKREG sp, -64; + CHECKREG fp, -64; + + pass diff --git a/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_p.s b/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_p.s new file mode 100644 index 0000000..75433bc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_p.s @@ -0,0 +1,131 @@ +//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_p/c_compi2opp_pr_eq_i7_p.dsp +// Spec Reference: compi2opd pregs = imm7 positive +# mach: bfin + +.include "testutils.inc" + start + +//R0 = 0; + P1 = 1; + P2 = 2; + P3 = 3; + P4 = 4; + P5 = 5; + SP = 6; + FP = 7; + CHECKREG p1, 1; + CHECKREG p2, 2; + CHECKREG p3, 3; + CHECKREG p4, 4; + CHECKREG p5, 5; + CHECKREG sp, 6; + CHECKREG fp, 7; + + P1 = 9; + P2 = 10; + P3 = 11; + P4 = 12; + P5 = 13; + SP = 14; + FP = 15; + CHECKREG p1, 9; + CHECKREG p2, 10; + CHECKREG p3, 11; + CHECKREG p4, 12; + CHECKREG p5, 13; + CHECKREG sp, 14; + CHECKREG fp, 15; + + P1 = 17; + P2 = 18; + P3 = 19; + P4 = 20; + P5 = 21; + SP = 22; + FP = 23; + CHECKREG p1, 17; + CHECKREG p2, 18; + CHECKREG p3, 19; + CHECKREG p4, 20; + CHECKREG p5, 21; + CHECKREG sp, 22; + CHECKREG fp, 23; + + P1 = 25; + P2 = 26; + P3 = 27; + P4 = 28; + P5 = 29; + SP = 30; + FP = 31; + CHECKREG p1, 25; + CHECKREG p2, 26; + CHECKREG p3, 27; + CHECKREG p4, 28; + CHECKREG p5, 29; + CHECKREG sp, 30; + CHECKREG fp, 31; + + R0 = 32; + P1 = 33; + P2 = 34; + P3 = 35; + P4 = 36; + P5 = 37; + SP = 38; + FP = 39; + CHECKREG r0, 32; + CHECKREG p1, 33; + CHECKREG p2, 34; + CHECKREG p3, 35; + CHECKREG p4, 36; + CHECKREG p5, 37; + CHECKREG sp, 38; + CHECKREG fp, 39; + + P1 = 41; + P2 = 42; + P3 = 43; + P4 = 44; + P5 = 45; + SP = 46; + FP = 47; + CHECKREG p1, 41; + CHECKREG p2, 42; + CHECKREG p3, 43; + CHECKREG p4, 44; + CHECKREG p5, 45; + CHECKREG sp, 46; + CHECKREG fp, 47; + + P1 = 49; + P2 = 50; + P3 = 51; + P4 = 52; + P5 = 53; + SP = 54; + FP = 55; + CHECKREG p1, 49; + CHECKREG p2, 50; + CHECKREG p3, 51; + CHECKREG p4, 52; + CHECKREG p5, 53; + CHECKREG sp, 54; + CHECKREG fp, 55; + + P1 = 57; + P2 = 58; + P3 = 59; + P4 = 60; + P5 = 61; + SP = 62; + FP = 63; + CHECKREG p1, 57; + CHECKREG p2, 58; + CHECKREG p3, 59; + CHECKREG p4, 60; + CHECKREG p5, 61; + CHECKREG sp, 62; + CHECKREG fp, 63; + + pass diff --git a/sim/testsuite/sim/bfin/c_dagmodik_lnz_imgebl.s b/sim/testsuite/sim/bfin/c_dagmodik_lnz_imgebl.s new file mode 100644 index 0000000..cea97ad --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dagmodik_lnz_imgebl.s @@ -0,0 +1,290 @@ +//Original:/testcases/core/c_dagmodik_lnz_imgebl/c_dagmodik_lnz_imgebl.dsp +// Spec Reference: dagmodik l not zero & i+m >= b+l +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x00001000; +imm32 b1, 0x00001000; +imm32 b2, 0x00001000; +imm32 b3, 0x00001000; + +imm32 l0, 0x00000001; +imm32 l1, 0x00000002; +imm32 l2, 0x00000003; +imm32 l3, 0x00000004; + +imm32 m0, 0x00000015; +imm32 m1, 0x00000016; +imm32 m2, 0x00000017; +imm32 m3, 0x00000018; + + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x0000100F; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001002; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x0000100E; +CHECKREG r7, 0x00001001; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x000010FE; +CHECKREG r2, 0x0000100C; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00000FFF; +CHECKREG r5, 0x000010FC; +CHECKREG r6, 0x0000100A; +CHECKREG r7, 0x00001001; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x000010FE; +CHECKREG r2, 0x0000100B; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x00001005; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x0000100C; +CHECKREG r7, 0x00001001; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x00000FFE; +CHECKREG r1, 0x000010F8; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x00001005; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x0000100C; +CHECKREG r7, 0x00001001; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00000FFE; +CHECKREG r1, 0x000010F8; +CHECKREG r2, 0x00001004; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x00000FF8; +CHECKREG r5, 0x000010F0; +CHECKREG r6, 0x00000FFF; +CHECKREG r7, 0x00001001; + +// i+m = b+l +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x00001000; +imm32 b1, 0x00001100; +imm32 b2, 0x00001010; +imm32 b3, 0x00001001; + +imm32 l0, 0x00000015; +imm32 l1, 0x00000016; +imm32 l2, 0x00000017; +imm32 l3, 0x00000018; + +imm32 m0, 0x00000015; +imm32 m1, 0x00000016; +imm32 m2, 0x00000017; +imm32 m3, 0x00000018; + + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001012; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001104; +CHECKREG r6, 0x00001014; +CHECKREG r7, 0x00001005; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001012; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x00001010; +CHECKREG r7, 0x00001001; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001104; +CHECKREG r2, 0x00001014; +CHECKREG r3, 0x00001005; +CHECKREG r4, 0x00001008; +CHECKREG r5, 0x00001108; +CHECKREG r6, 0x00001018; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x00001010; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x00001008; +CHECKREG r5, 0x00001108; +CHECKREG r6, 0x00001018; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x00001010; +CHECKREG r3, 0x00001001; +CHECKREG r4, 0x0000100D; +CHECKREG r5, 0x0000110E; +CHECKREG r6, 0x0000101F; +CHECKREG r7, 0x00001011; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dagmodik_lnz_imltbl.s b/sim/testsuite/sim/bfin/c_dagmodik_lnz_imltbl.s new file mode 100644 index 0000000..7142682 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dagmodik_lnz_imltbl.s @@ -0,0 +1,289 @@ +//Original:/testcases/core/c_dagmodik_lnz_imltbl/c_dagmodik_lnz_imltbl.dsp +// Spec Reference: dagmodik l not zero & i+m < b +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x0000100e; +imm32 b1, 0x0000110c; +imm32 b2, 0x0000101a; +imm32 b3, 0x00001008; + +imm32 l0, 0x000000a1; +imm32 l1, 0x000000b2; +imm32 l2, 0x000000c3; +imm32 l3, 0x000000d4; + +imm32 m0, 0x00000005; +imm32 m1, 0x00000004; +imm32 m2, 0x00000003; +imm32 m3, 0x00000002; + + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001012; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001104; +CHECKREG r6, 0x00001014; +CHECKREG r7, 0x00001005; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x000010A3; +CHECKREG r1, 0x000011B4; +CHECKREG r2, 0x000010D5; +CHECKREG r3, 0x000010D7; +CHECKREG r4, 0x000010A1; +CHECKREG r5, 0x000011B2; +CHECKREG r6, 0x000010D3; +CHECKREG r7, 0x000010D5; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x000010A5; +CHECKREG r1, 0x000011B6; +CHECKREG r2, 0x000010D7; +CHECKREG r3, 0x000010D9; +CHECKREG r4, 0x000010A9; +CHECKREG r5, 0x000011BA; +CHECKREG r6, 0x000010DB; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x000010A1; +CHECKREG r1, 0x000011B2; +CHECKREG r2, 0x000010D3; +CHECKREG r3, 0x000010D5; +CHECKREG r4, 0x000010A9; +CHECKREG r5, 0x000011BA; +CHECKREG r6, 0x000010DB; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x000010A1; +CHECKREG r1, 0x000011B2; +CHECKREG r2, 0x000010D3; +CHECKREG r3, 0x000010D5; +CHECKREG r4, 0x00001099; +CHECKREG r5, 0x000011AA; +CHECKREG r6, 0x000010CB; +CHECKREG r7, 0x000010CD; + +// i+m = b+l +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x0000100e; +imm32 b1, 0x0000110c; +imm32 b2, 0x0000101a; +imm32 b3, 0x00001008; + +imm32 l0, 0x00000011; +imm32 l1, 0x00000012; +imm32 l2, 0x00000013; +imm32 l3, 0x00000014; + +imm32 m0, 0x00000002; +imm32 m1, 0x00000003; +imm32 m2, 0x00000004; +imm32 m3, 0x00000005; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001012; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001104; +CHECKREG r6, 0x00001014; +CHECKREG r7, 0x00001005; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001013; +CHECKREG r1, 0x00001114; +CHECKREG r2, 0x00001025; +CHECKREG r3, 0x00001017; +CHECKREG r4, 0x00001011; +CHECKREG r5, 0x00001112; +CHECKREG r6, 0x00001023; +CHECKREG r7, 0x00001015; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001015; +CHECKREG r1, 0x00001116; +CHECKREG r2, 0x00001027; +CHECKREG r3, 0x00001019; +CHECKREG r4, 0x00001019; +CHECKREG r5, 0x0000111A; +CHECKREG r6, 0x0000102B; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x00001011; +CHECKREG r1, 0x00001112; +CHECKREG r2, 0x00001023; +CHECKREG r3, 0x00001015; +CHECKREG r4, 0x00001019; +CHECKREG r5, 0x0000111A; +CHECKREG r6, 0x0000102B; +CHECKREG r7, 0x00001009; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001011; +CHECKREG r1, 0x00001112; +CHECKREG r2, 0x00001023; +CHECKREG r3, 0x00001015; +CHECKREG r4, 0x0000101A; +CHECKREG r5, 0x0000111C; +CHECKREG r6, 0x0000101B; +CHECKREG r7, 0x0000100D; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dagmodik_lz_inc_dec.s b/sim/testsuite/sim/bfin/c_dagmodik_lz_inc_dec.s new file mode 100644 index 0000000..64ac946 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dagmodik_lz_inc_dec.s @@ -0,0 +1,140 @@ +//Original:/testcases/core/c_dagmodik_lz_inc_dec/c_dagmodik_lz_inc_dec.dsp +// Spec Reference: dagmodik L=0, I incremented & decremented +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001200; +imm32 i3, 0x00001300; +imm32 m0, 0x00000000; +imm32 m1, 0x00000110; +imm32 m2, 0x00000210; +imm32 m3, 0x00000310; + + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001202; +CHECKREG r3, 0x00001302; +CHECKREG r4, 0x00001004; +CHECKREG r5, 0x00001104; +CHECKREG r6, 0x00001204; +CHECKREG r7, 0x00001304; + + + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= 2; + I1 -= 2; + I2 -= 2; + I3 -= 2; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001002; +CHECKREG r1, 0x00001102; +CHECKREG r2, 0x00001202; +CHECKREG r3, 0x00001302; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00001100; +CHECKREG r6, 0x00001200; +CHECKREG r7, 0x00001300; + + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += 4; + I1 += 4; + I2 += 4; + I3 += 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001004; +CHECKREG r1, 0x00001104; +CHECKREG r2, 0x00001204; +CHECKREG r3, 0x00001304; +CHECKREG r4, 0x00001008; +CHECKREG r5, 0x00001108; +CHECKREG r6, 0x00001208; +CHECKREG r7, 0x00001308; + + I0 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x00001200; +CHECKREG r3, 0x00001300; +CHECKREG r4, 0x00001008; +CHECKREG r5, 0x00001108; +CHECKREG r6, 0x00001208; +CHECKREG r7, 0x00001308; + + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; + I0 -= 4; + I1 -= 4; + I2 -= 4; + I3 -= 4; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00001100; +CHECKREG r2, 0x00001200; +CHECKREG r3, 0x00001300; +CHECKREG r4, 0x00000FF8; +CHECKREG r5, 0x000010F8; +CHECKREG r6, 0x000011F8; +CHECKREG r7, 0x000012F8; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dagmodim_lnz_imgebl.s b/sim/testsuite/sim/bfin/c_dagmodim_lnz_imgebl.s new file mode 100644 index 0000000..4189c05 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dagmodim_lnz_imgebl.s @@ -0,0 +1,108 @@ +//Original:/testcases/core/c_dagmodim_lnz_imgebl/c_dagmodim_lnz_imgebl.dsp +// Spec Reference: dagmodim l not zero & i+m >= b+l +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x00001000; +imm32 b1, 0x00001000; +imm32 b2, 0x00001000; +imm32 b3, 0x00001000; + +imm32 l0, 0x00000001; +imm32 l1, 0x00000002; +imm32 l2, 0x00000003; +imm32 l3, 0x00000004; + +imm32 m0, 0x00000015; +imm32 m1, 0x00000016; +imm32 m2, 0x00000017; +imm32 m3, 0x00000018; + + I0 += M0; + I1 += M1; + I2 += M2; + I3 += M3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M1; + I1 += M2; + I2 += M3; + I3 += M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; + +CHECKREG r0, 0x00001014; +CHECKREG r1, 0x00001114; +CHECKREG r2, 0x00001024; +CHECKREG r3, 0x00001015; +CHECKREG r4, 0x00001029; +CHECKREG r5, 0x00001129; +CHECKREG r6, 0x00001039; +CHECKREG r7, 0x00001026; + + I0 -= M2; + I1 -= M3; + I2 -= M0; + I3 -= M1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= M3; + I1 -= M2; + I2 -= M1; + I3 -= M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001012; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00001024; +CHECKREG r3, 0x00001010; +CHECKREG r4, 0x00000FFB; +CHECKREG r5, 0x000010FA; +CHECKREG r6, 0x0000100E; +CHECKREG r7, 0x00000FFF; + + I0 += M3 (BREV); + I1 += M0 (BREV); + I2 += M1 (BREV); + I3 += M2 (BREV); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M2 (BREV); + I1 += M3 (BREV); + I2 += M0 (BREV); + I3 += M1 (BREV); +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00000FEF; +CHECKREG r1, 0x000010E0; +CHECKREG r2, 0x0000101B; +CHECKREG r3, 0x00000FE7; +CHECKREG r4, 0x00000FFB; +CHECKREG r5, 0x000010F8; +CHECKREG r6, 0x00001001; +CHECKREG r7, 0x00000FF2; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dagmodim_lnz_imltbl.s b/sim/testsuite/sim/bfin/c_dagmodim_lnz_imltbl.s new file mode 100644 index 0000000..152c94b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dagmodim_lnz_imltbl.s @@ -0,0 +1,109 @@ +//Original:/testcases/core/c_dagmodim_lnz_imltbl/c_dagmodim_lnz_imltbl.dsp +// Spec Reference: dagmodim l not zero & i+m < b +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x00001000; +imm32 i1, 0x00001100; +imm32 i2, 0x00001010; +imm32 i3, 0x00001001; + +imm32 b0, 0x0000110e; +imm32 b1, 0x0000110c; +imm32 b2, 0x0000110a; +imm32 b3, 0x00001108; + +imm32 l0, 0x000000a1; +imm32 l1, 0x000000b2; +imm32 l2, 0x000000c3; +imm32 l3, 0x000000d4; + +imm32 m0, 0x00000005; +imm32 m1, 0x00000004; +imm32 m2, 0x00000003; +imm32 m3, 0x00000002; + + I0 += M0; + I1 += M1; + I2 += M2; + I3 += M3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M1; + I1 += M2; + I2 += M3; + I3 += M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001005; +CHECKREG r1, 0x00001104; +CHECKREG r2, 0x00001013; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001009; +CHECKREG r5, 0x00001107; +CHECKREG r6, 0x00001015; +CHECKREG r7, 0x00001008; + + + I0 -= M2; + I1 -= M3; + I2 -= M0; + I3 -= M1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= M3; + I1 -= M2; + I2 -= M1; + I3 -= M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x000010A7; +CHECKREG r1, 0x000011B7; +CHECKREG r2, 0x000010D3; +CHECKREG r3, 0x000010D8; +CHECKREG r4, 0x00001146; +CHECKREG r5, 0x000011B4; +CHECKREG r6, 0x00001192; +CHECKREG r7, 0x000011A7; + + I0 += M3 (BREV); + I1 += M0 (BREV); + I2 += M1 (BREV); + I3 += M2 (BREV); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M2 (BREV); + I1 += M3 (BREV); + I2 += M0 (BREV); + I3 += M1 (BREV); +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x00001145; +CHECKREG r1, 0x000011B3; +CHECKREG r2, 0x00001196; +CHECKREG r3, 0x000011A5; +CHECKREG r4, 0x00001146; +CHECKREG r5, 0x000011B0; +CHECKREG r6, 0x00001190; +CHECKREG r7, 0x000011A3; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dagmodim_lz_inc_dec.s b/sim/testsuite/sim/bfin/c_dagmodim_lz_inc_dec.s new file mode 100644 index 0000000..094a7d8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dagmodim_lz_inc_dec.s @@ -0,0 +1,98 @@ +//Original:/testcases/core/c_dagmodim_lz_inc_dec/c_dagmodim_lz_inc_dec.dsp +// Spec Reference: dagmodim L=0, I incremented & decremented (by M) +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 i0, 0x10001000; +imm32 i1, 0x02001100; +imm32 i2, 0x00301010; +imm32 i3, 0x00041001; + +imm32 m0, 0x00000005; +imm32 m1, 0x00000006; +imm32 m2, 0x00000007; +imm32 m3, 0x00000008; + + I0 += M0; + I1 += M1; + I2 += M2; + I3 += M3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M1; + I1 += M2; + I2 += M3; + I3 += M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; + +CHECKREG r0, 0x10001005; +CHECKREG r1, 0x02001106; +CHECKREG r2, 0x00301017; +CHECKREG r3, 0x00041009; +CHECKREG r4, 0x1000100B; +CHECKREG r5, 0x0200110D; +CHECKREG r6, 0x0030101F; +CHECKREG r7, 0x0004100E; + + I0 -= M2; + I1 -= M3; + I2 -= M0; + I3 -= M1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 -= M3; + I1 -= M2; + I2 -= M1; + I3 -= M0; +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x10001004; +CHECKREG r1, 0x02001105; +CHECKREG r2, 0x0030101A; +CHECKREG r3, 0x00041008; +CHECKREG r4, 0x10000FFC; +CHECKREG r5, 0x020010FE; +CHECKREG r6, 0x00301014; +CHECKREG r7, 0x00041003; + + I0 += M3 (BREV); + I1 += M0 (BREV); + I2 += M1 (BREV); + I3 += M2 (BREV); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; + I0 += M2 (BREV); + I1 += M3 (BREV); + I2 += M0 (BREV); + I3 += M1 (BREV); +R4 = I0; +R5 = I1; +R6 = I2; +R7 = I3; +CHECKREG r0, 0x10000FF2; +CHECKREG r1, 0x020010F8; +CHECKREG r2, 0x00301011; +CHECKREG r3, 0x00041005; +CHECKREG r4, 0x10000FF4; +CHECKREG r5, 0x020010F4; +CHECKREG r6, 0x00301014; +CHECKREG r7, 0x00041000; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_a0_pm_a1.s b/sim/testsuite/sim/bfin/c_dsp32alu_a0_pm_a1.s new file mode 100644 index 0000000..dda7ddd --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_a0_pm_a1.s @@ -0,0 +1,39 @@ +//Original:/testcases/core/c_dsp32alu_a0_pm_a1/c_dsp32alu_a0_pm_a1.dsp +// Spec Reference: dsp32alu a0 += a1 +# mach: bfin + +.include "testutils.inc" + start + + + +A1 = A0 = 0; + +imm32 r0, 0x25678911; +imm32 r1, 0x0029ab2d; +imm32 r2, 0x00145535; +imm32 r3, 0xf6567747; +imm32 r4, 0xe566895b; +imm32 r5, 0x67897b6d; +imm32 r6, 0xb4445875; +imm32 r7, 0x86667797; +A0 = R0; +A1 = R1; + +A0 += A1; +A0 += A1 (W32); +A0 += A1; +A0 += A1 (W32); +R5 = A0.w; + +A1 = R2; +A0 -= A1; +A0 -= A1 (W32); +A0 -= A1; +A0 -= A1 (W32); +R6 = A0.w; +CHECKREG r5, 0x260E35C5; +CHECKREG r6, 0x25BCE0F1; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_a0a1s.s b/sim/testsuite/sim/bfin/c_dsp32alu_a0a1s.s new file mode 100644 index 0000000..ee20bb7 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_a0a1s.s @@ -0,0 +1,82 @@ +//Original:/testcases/core/c_dsp32alu_a0a1s/c_dsp32alu_a0a1s.dsp +// Spec Reference: dsp32alu a0a1s +# mach: bfin + +.include "testutils.inc" + start + + + +A1 = A0 = 0; + +imm32 r0, 0x15678911; +imm32 r1, 0xa789ab1d; +imm32 r2, 0xd4445515; +imm32 r3, 0xf6667717; +imm32 r4, 0xe567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0xb4445515; +imm32 r7, 0x86667777; +// A0 & A1 types +A0 = R0; +A1 = R1; + R6 = A0.w; + R7 = A1.w; +A0 = 0; +A1 = 0; + R0 = A0.w; + R1 = A1.w; +A0 = R2; +A1 = R3; +A0 = A0 (S); +A1 = A1 (S); + R4 = A0.w; + R5 = A1.w; +A0 = A1; + R2 = A0.w; +A0 = R3; +A1 = A0; + R3 = A1.w; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xF6667717; +CHECKREG r3, 0xF6667717; +CHECKREG r4, 0xD4445515; +CHECKREG r5, 0xF6667717; +CHECKREG r6, 0x15678911; +CHECKREG r7, 0xA789AB1D; + +A1 = A0 = 0; + R0 = A0.w; + R1 = A1.w; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; + +imm32 r0, 0xa1567891; +imm32 r1, 0xba789abd; +imm32 r2, 0xcd412355; +imm32 r3, 0xdf646777; +imm32 r4, 0xe567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0xb4445515; +imm32 r7, 0xf666aeb7; + +A0 = R4; +A1 = R5; + R0 = A0.w; + R1 = A1.w; +A0 = R6; +A1 = R7; + R2 = A0.w; + R3 = A1.w; +CHECKREG r0, 0xE567891B; +CHECKREG r1, 0x6789AB1D; +CHECKREG r2, 0xB4445515; +CHECKREG r3, 0xF666AEB7; +CHECKREG r4, 0xE567891B; +CHECKREG r5, 0x6789AB1D; +CHECKREG r6, 0xB4445515; +CHECKREG r7, 0xF666AEB7; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_a_abs_a.s b/sim/testsuite/sim/bfin/c_dsp32alu_a_abs_a.s new file mode 100644 index 0000000..3a83972 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_a_abs_a.s @@ -0,0 +1,34 @@ +//Original:/testcases/core/c_dsp32alu_a_abs_a/c_dsp32alu_a_abs_a.dsp +// Spec Reference: dsp32alu a = abs a +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +A1 = A0 = 0; +A0 = R0; + +A0 = ABS A0; +A1 = ABS A0; +A1 = ABS A1; +A0 = ABS A1; +R1 = A0.w; +R2 = A1.w; +CHECKREG r0, 0xA5678911; +CHECKREG r1, 0x5A9876EF; +CHECKREG r2, 0x5A9876EF; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_a_neg_a.s b/sim/testsuite/sim/bfin/c_dsp32alu_a_neg_a.s new file mode 100644 index 0000000..263e900 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_a_neg_a.s @@ -0,0 +1,34 @@ +//Original:/testcases/core/c_dsp32alu_a_neg_a/c_dsp32alu_a_neg_a.dsp +// Spec Reference: dsp32alu a = neg a +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +A1 = A0 = 0; +A0 = R0; + +A0 = - A0; +A1 = - A0; +A1 = - A1; +A0 = - A1; +R1 = A0.w; +R2 = A1.w; +CHECKREG r0, 0xA5678911; +CHECKREG r1, 0xA5678911; +CHECKREG r2, 0x5A9876EF; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_aa_absabs.s b/sim/testsuite/sim/bfin/c_dsp32alu_aa_absabs.s new file mode 100644 index 0000000..fd505f0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_aa_absabs.s @@ -0,0 +1,35 @@ +//Original:/testcases/core/c_dsp32alu_aa_absabs/c_dsp32alu_aa_absabs.dsp +// Spec Reference: dsp32alu a1, a0 = abs / abs a1, a0 +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +A0 = R0; +A1 = R1; + +A1 = ABS A1, A0 = ABS A0; +R2 = A0.w; +R3 = A1.w; +A1 = ABS A1, A0 = ABS A0; +R4 = A0.w; +R5 = A1.w; +CHECKREG r2, 0x5A9876EF; +CHECKREG r3, 0x2789AB1D; +CHECKREG r4, 0x5A9876EF; +CHECKREG r5, 0x2789AB1D; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_aa_negneg.s b/sim/testsuite/sim/bfin/c_dsp32alu_aa_negneg.s new file mode 100644 index 0000000..4d6f4bf --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_aa_negneg.s @@ -0,0 +1,35 @@ +//Original:/testcases/core/c_dsp32alu_aa_negneg/c_dsp32alu_aa_negneg.dsp +// Spec Reference: dsp32alu a1, a0 = neg / neg a1, a0 +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +A0 = R0; +A1 = R1; + +A1 = - A1, A0 = - A0; +R2 = A0.w; +R3 = A1.w; +A1 = - A1, A0 = - A0; +R4 = A0.w; +R5 = A1.w; +CHECKREG r2, 0x5A9876EF; +CHECKREG r3, 0xD87654E3; +CHECKREG r4, 0xA5678911; +CHECKREG r5, 0x2789AB1D; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_abs.s b/sim/testsuite/sim/bfin/c_dsp32alu_abs.s new file mode 100644 index 0000000..0504a7b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_abs.s @@ -0,0 +1,62 @@ +//Original:/testcases/core/c_dsp32alu_abs/c_dsp32alu_abs.dsp +// Spec Reference: dsp32alu dregs = abs ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = ABS R0; +R1 = ABS R1; +R2 = ABS R2; +R3 = ABS R3; +R4 = ABS R4; +R5 = ABS R5; +R6 = ABS R6; +R7 = ABS R7; +CHECKREG r0, 0x15678911; +CHECKREG r1, 0x2789AB1D; +CHECKREG r2, 0x34445515; +CHECKREG r3, 0x46667717; +CHECKREG r4, 0x5567891B; +CHECKREG r5, 0x6789AB1D; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x79998889; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = ABS R7; +R1 = ABS R6; +R2 = ABS R5; +R3 = ABS R4; +R4 = ABS R3; +R5 = ABS R2; +R6 = ABS R1; +R7 = ABS R0; +CHECKREG r0, 0x0EEEFFFF; +CHECKREG r1, 0x033322D3; +CHECKREG r2, 0x155544D5; +CHECKREG r3, 0x277766D7; +CHECKREG r4, 0x277766D7; +CHECKREG r5, 0x155544D5; +CHECKREG r6, 0x033322D3; +CHECKREG r7, 0x0EEEFFFF; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_absabs.s b/sim/testsuite/sim/bfin/c_dsp32alu_absabs.s new file mode 100644 index 0000000..bb1cafc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_absabs.s @@ -0,0 +1,62 @@ +//Original:/testcases/core/c_dsp32alu_absabs/c_dsp32alu_absabs.dsp +// Spec Reference: dsp32alu dregs = abs / abs ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = ABS R0 (V); +R1 = ABS R1 (V); +R2 = ABS R2 (V); +R3 = ABS R3 (V); +R4 = ABS R4 (V); +R5 = ABS R5 (V); +R6 = ABS R6 (V); +R7 = ABS R7 (V); +CHECKREG r0, 0x156776EF; +CHECKREG r1, 0x278954E3; +CHECKREG r2, 0x34445515; +CHECKREG r3, 0x46667717; +CHECKREG r4, 0x556776E5; +CHECKREG r5, 0x678954E3; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x799A7777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = ABS R7 (V); +R1 = ABS R6 (V); +R2 = ABS R5 (V); +R3 = ABS R4 (V); +R4 = ABS R3 (V); +R5 = ABS R2 (V); +R6 = ABS R1 (V); +R7 = ABS R0 (V); +CHECKREG r0, 0x0EEE0001; +CHECKREG r1, 0x033422D3; +CHECKREG r2, 0x155644D5; +CHECKREG r3, 0x277866D7; +CHECKREG r4, 0x277866D7; +CHECKREG r5, 0x155644D5; +CHECKREG r6, 0x033422D3; +CHECKREG r7, 0x0EEE0001; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_alhwx.s b/sim/testsuite/sim/bfin/c_dsp32alu_alhwx.s new file mode 100644 index 0000000..3ca87a7 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_alhwx.s @@ -0,0 +1,128 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_alhwx/c_dsp32alu_alhwx.dsp +// Spec Reference: dsp32alu alhwx +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + A1 = A0 = 0; + + imm32 r0, 0xa5678911; + imm32 r1, 0xaa89ab1d; + imm32 r2, 0xd4b45515; + imm32 r3, 0xf66e7717; + imm32 r4, 0xe567f91b; + imm32 r5, 0x6789ae1d; + imm32 r6, 0xb4445515; + imm32 r7, 0x8666a7d7; + A0.L = R0.L; + A0.H = R0.H; + A0.x = R1.L; + R7 = A0.w; + R6 = A0.x; + R5.L = A0.x; + A1.L = R4.L; + A1.H = R4.H; + A1.x = R3.L; + R0 = A1.w; + R1 = A1.x; + R2.L = A1.x; + CHECKREG r0, 0xE567F91B; + CHECKREG r1, 0x00000017; + CHECKREG r2, 0xD4B40017; + CHECKREG r3, 0xF66E7717; + CHECKREG r4, 0xE567F91B; + CHECKREG r5, 0x6789001D; + CHECKREG r6, 0x0000001D; + CHECKREG r7, 0xA5678911; + + imm32 r0, 0xe5678911; + imm32 r1, 0xaa89ab1d; + imm32 r2, 0xdfb45515; + imm32 r3, 0xf66e7717; + imm32 r4, 0xe5d7f91b; + imm32 r5, 0x67e9ae1d; + imm32 r6, 0xb4445515; + imm32 r7, 0x866aa7b7; + A0.L = R1.L; + A0.H = R1.H; + A0.x = R2.L; + R5 = A0.w; + R7 = A0.x; + R6.L = A0.x; + A1.L = R3.L; + A1.H = R3.H; + A1.x = R4.L; + R1 = A1.w; + R2 = A1.x; + R0.L = A1.x; + CHECKREG r0, 0xE567001B; + CHECKREG r1, 0xF66E7717; + CHECKREG r2, 0x0000001B; + CHECKREG r3, 0xF66E7717; + CHECKREG r4, 0xE5D7F91B; + CHECKREG r5, 0xAA89AB1D; + CHECKREG r6, 0xB4440015; + CHECKREG r7, 0x00000015; + + imm32 r0, 0x35678911; + imm32 r1, 0xa489ab1d; + imm32 r2, 0xd4545515; + imm32 r3, 0xf6667717; + imm32 r4, 0x9567f91b; + imm32 r5, 0x6a89ae1d; + imm32 r6, 0xb4445515; + imm32 r7, 0x8666a7d7; + A0.L = R3.L; + A0.H = R3.H; + A0.x = R4.L; + R0 = A0.w; + R1 = A0.x; + R2.L = A0.x; + A1.L = R5.L; + A1.H = R6.H; + A1.x = R7.L; + R7 = A1.w; + R5 = A1.x; + R5.L = A1.x; + CHECKREG r0, 0xF6667717; + CHECKREG r1, 0x0000001B; + CHECKREG r2, 0xD454001B; + CHECKREG r3, 0xF6667717; + CHECKREG r4, 0x9567F91B; + CHECKREG r5, 0xffffffD7; + CHECKREG r6, 0xB4445515; + CHECKREG r7, 0xB444AE1D; + + imm32 r0, 0xd5678911; + imm32 r1, 0x2a89ab1d; + imm32 r2, 0xd3b45515; + imm32 r3, 0xf66e7717; + imm32 r4, 0xe5d7f91b; + imm32 r5, 0x67e9ae1d; + imm32 r6, 0xb4445515; + imm32 r7, 0x889aa7b7; + A0.L = R4.L; + A0.H = R5.H; + A0.x = R6.L; + R1 = A0.w; + R2 = A0.x; + R3.L = A0.x; + A1.L = R0.L; + A1.H = R0.H; + A1.x = R7.L; + R4 = A1.w; + R5 = A1.x; + R6.L = A1.x; + CHECKREG r0, 0xD5678911; + CHECKREG r1, 0x67E9F91B; + CHECKREG r2, 0x00000015; + CHECKREG r3, 0xF66E0015; + CHECKREG r4, 0xD5678911; + CHECKREG r5, 0xffffffB7; + CHECKREG r6, 0xB444ffB7; + CHECKREG r7, 0x889AA7B7; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_awx.s b/sim/testsuite/sim/bfin/c_dsp32alu_awx.s new file mode 100644 index 0000000..652264c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_awx.s @@ -0,0 +1,61 @@ +//Original:/testcases/core/c_dsp32alu_awx/c_dsp32alu_awx.dsp +// Spec Reference: dsp32alu awx +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +// A0 & A1 types +A0 = 0; +A1 = 0; + +A0.L = R0.L; +A0.H = R0.H; +A0.x = R2.L; +R3 = A0.w; +R4 = A1.w; +R5.L = A0.x; +//rl6 = a1x; +CHECKREG r3, 0x15678911; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x67890015; +//CHECKREG r6, 0x74440000; + +R5 = ( A0 += A1 ); +R6.L = ( A0 += A1 ); +R7.H = ( A0 += A1 ); +CHECKREG r5, 0x7FFFFFFF; +CHECKREG r6, 0x74447FFF; +CHECKREG r7, 0x7FFF7777; + +A0 += A1; +R0 = A0.w; +CHECKREG r0, 0x15678911; + +A0 -= A1; +R1 = A0.w; +CHECKREG r1, 0x15678911; + +R2 = A1.L + A1.H, R3 = A0.L + A0.H; /* 0x */ +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xFFFF9E78; + +A0 = A1; +R4 = A0.w; +R5 = A1.w; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_byteop1ew.s b/sim/testsuite/sim/bfin/c_dsp32alu_byteop1ew.s new file mode 100644 index 0000000..ff20a19 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_byteop1ew.s @@ -0,0 +1,136 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop1ew/c_dsp32alu_byteop1ew.dsp +// Spec Reference: dsp32alu byteop1ew +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86667777; + R4 = BYTEOP1P ( R1:0 , R3:2 ); + R5 = BYTEOP1P ( R1:0 , R3:2 ) (R); + R6 = BYTEOP1P ( R1:0 , R3:2 ) (T); + R7 = BYTEOP1P ( R1:0 , R3:2 ) (T , R); + R0 = BYTEOP1P ( R1:0 , R3:2 ) (T , R); + CHECKREG r4, 0x25566F13; + CHECKREG r5, 0x3778911A; + CHECKREG r6, 0x24556F13; + CHECKREG r7, 0x3677911A; + CHECKREG r0, 0x3677911A; + + imm32 r0, 0x1567892b; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445525; + imm32 r3, 0x46667727; + imm32 r4, 0x58889929; + imm32 r5, 0x6aaabb2b; + imm32 r6, 0x7cccdd2d; + imm32 r7, 0x8eeeffff; + R0 = BYTEOP1P ( R3:2 , R1:0 ); + R1 = BYTEOP1P ( R3:2 , R1:0 ) (R); + R2 = BYTEOP1P ( R3:2 , R1:0 ) (T); + R3 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); + R4 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); + R5 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); + R6 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); + R7 = BYTEOP1P ( R3:2 , R1:0 ) (T , R); + CHECKREG r0, 0x25566F28; + CHECKREG r1, 0x3778912A; + CHECKREG r2, 0x2C4D6226; + CHECKREG r3, 0x3E6F8428; + CHECKREG r4, 0x3A738A29; + CHECKREG r5, 0x3A738A29; + CHECKREG r6, 0x3A738A29; + CHECKREG r7, 0x3A738A29; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r0, 0x456789ab; + imm32 r1, 0x6689abcd; + imm32 r2, 0x47445555; + imm32 r3, 0x68667777; + ( R1 , R2 ) = BYTEOP16P ( R1:0 , R3:2 ); + ( R0 , R3 ) = BYTEOP16P ( R1:0 , R3:2 ) (R); + ( R4 , R5 ) = BYTEOP16P ( R3:2 , R1:0 ); + ( R6 , R7 ) = BYTEOP16P ( R3:2 , R1:0 ); + CHECKREG r0, 0x006800F2; + CHECKREG r1, 0x008C00AB; + CHECKREG r2, 0x00DE0100; + CHECKREG r3, 0x00770122; + CHECKREG r4, 0x00000146; + CHECKREG r5, 0x000100F2; + CHECKREG r6, 0x00000146; + CHECKREG r7, 0x000100F2; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r0, 0x456789ab; + imm32 r1, 0x6689abcd; + imm32 r2, 0x47445555; + imm32 r3, 0x68667777; + ( R7 , R6 ) = BYTEOP16P ( R3:2 , R1:0 ); + ( R5 , R4 ) = BYTEOP16P ( R3:2 , R1:0 ) (R); + ( R2 , R3 ) = BYTEOP16P ( R3:2 , R1:0 ); + ( R1 , R0 ) = BYTEOP16P ( R3:2 , R1:0 ); + CHECKREG r0, 0x00890156; + CHECKREG r1, 0x004500F3; + CHECKREG r2, 0x008C00AB; + CHECKREG r3, 0x00DE0100; + CHECKREG r4, 0x01220144; + CHECKREG r5, 0x00CE00EF; + CHECKREG r6, 0x00DE0100; + CHECKREG r7, 0x008C00AB; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r0, 0x456789ab; + imm32 r1, 0x6689abcd; + imm32 r2, 0x47445555; + imm32 r3, 0x68667777; + ( R1 , R2 ) = BYTEOP16M ( R1:0 , R3:2 ); + ( R0 , R3 ) = BYTEOP16M ( R1:0 , R3:2 ) (R); + ( R4 , R5 ) = BYTEOP16M ( R3:2 , R1:0 ); + ( R6 , R7 ) = BYTEOP16M ( R3:2 , R1:0 ); + CHECKREG r0, 0x00970098; + CHECKREG r1, 0xFFFE0023; + CHECKREG r2, 0x00340056; + CHECKREG r3, 0xFF89FFAC; + CHECKREG r4, 0x0000FF9D; + CHECKREG r5, 0x0000FFBE; + CHECKREG r6, 0x0000FF9D; + CHECKREG r7, 0x0000FFBE; + + imm32 r0, 0x516789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x73445555; + imm32 r3, 0x84667777; + imm32 r0, 0x956789ab; + imm32 r1, 0xa689abcd; + imm32 r2, 0xb7445555; + imm32 r3, 0xc86def77; + ( R7 , R6 ) = BYTEOP16M ( R3:2 , R1:0 ); + ( R5 , R4 ) = BYTEOP16M ( R3:2 , R1:0 ) (R); + ( R2 , R3 ) = BYTEOP16M ( R3:2 , R1:0 ); + ( R1 , R0 ) = BYTEOP16M ( R3:2 , R1:0 ); + CHECKREG r0, 0x00760032; + CHECKREG r1, 0xFF6BFFBB; + CHECKREG r2, 0x0022FFDD; + CHECKREG r3, 0xFFCCFFAA; + CHECKREG r4, 0x0044FFAA; + CHECKREG r5, 0x0022FFE4; + CHECKREG r6, 0xFFCCFFAA; + CHECKREG r7, 0x0022FFDD; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_byteop2.s b/sim/testsuite/sim/bfin/c_dsp32alu_byteop2.s new file mode 100644 index 0000000..544a5bd --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_byteop2.s @@ -0,0 +1,76 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop2/c_dsp32alu_byteop2.dsp +// Spec Reference: dsp32alu byteop2 +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86667777; + R4 = BYTEOP2P ( R1:0 , R3:2 ) (RNDL); + R5 = BYTEOP2P ( R1:0 , R3:2 ) (RNDL , R); + R6 = BYTEOP2P ( R1:0 , R3:2 ) (RNDH); + R7 = BYTEOP2P ( R1:0 , R3:2 ) (RNDH , R); + CHECKREG r4, 0x003D0041; + CHECKREG r5, 0x00570056; + CHECKREG r6, 0x3D004100; + CHECKREG r7, 0x57005600; + + imm32 r0, 0x1567892b; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445525; + imm32 r3, 0x46667727; + imm32 r4, 0x58889929; + imm32 r5, 0x6aaabb2b; + imm32 r6, 0x7cccdd2d; + imm32 r7, 0x8eeeffff; + R0 = BYTEOP2P ( R3:2 , R1:0 ) (RNDL); + R1 = BYTEOP2P ( R3:2 , R1:0 ) (RNDL , R); + R2 = BYTEOP2P ( R3:2 , R1:0 ) (RNDH); + R3 = BYTEOP2P ( R3:2 , R1:0 ) (RNDH , R); + CHECKREG r0, 0x003D004C; + CHECKREG r1, 0x0057005E; + CHECKREG r2, 0x2D003200; + CHECKREG r3, 0x41003F00; + + imm32 r0, 0x716789ab; + imm32 r1, 0x8289abcd; + imm32 r2, 0x93445555; + imm32 r3, 0xa4667777; + imm32 r4, 0xb56789ab; + imm32 r5, 0xd689abcd; + imm32 r6, 0xe7445555; + imm32 r7, 0x6f661235; + R4 = BYTEOP2P ( R1:0 , R3:2 ) (TL); + R5 = BYTEOP2P ( R1:0 , R3:2 ) (TL , R); + R6 = BYTEOP2P ( R1:0 , R3:2 ) (TH); + R7 = BYTEOP2P ( R1:0 , R3:2 ) (TH , R); + CHECKREG r4, 0x006B0077; + CHECKREG r5, 0x00850099; + CHECKREG r6, 0x6B007700; + CHECKREG r7, 0x85009900; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r4, 0x456789ab; + imm32 r5, 0x6689abcd; + imm32 r6, 0x47445555; + imm32 r7, 0x68667777; + R0 = BYTEOP2P ( R3:2 , R1:0 ) (TL); + R1 = BYTEOP2P ( R3:2 , R1:0 ) (TL , R); + R2 = BYTEOP2P ( R3:2 , R1:0 ) (TH); + R3 = BYTEOP2P ( R3:2 , R1:0 ) (TH , R); + CHECKREG r0, 0x004B0077; + CHECKREG r1, 0x006D0099; + CHECKREG r2, 0x34004800; + CHECKREG r3, 0x4D006100; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_byteop3.s b/sim/testsuite/sim/bfin/c_dsp32alu_byteop3.s new file mode 100644 index 0000000..af32c06 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_byteop3.s @@ -0,0 +1,76 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop3/c_dsp32alu_byteop3.dsp +// Spec Reference: dsp32alu byteop3 +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86667777; + R4 = BYTEOP3P ( R1:0 , R3:2 ) (LO); + R5 = BYTEOP3P ( R1:0 , R3:2 ) (HI); + R6 = BYTEOP3P ( R1:0 , R3:2 ) (LO); + R7 = BYTEOP3P ( R1:0 , R3:2 ) (HI); + CHECKREG r4, 0x00FF0000; + CHECKREG r5, 0xFF000000; + CHECKREG r6, 0x00FF0000; + CHECKREG r7, 0xFF000000; + + imm32 r0, 0x1567892b; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445525; + imm32 r3, 0x46667727; + imm32 r4, 0x58889929; + imm32 r5, 0x6aaabb2b; + imm32 r6, 0x7cccdd2d; + imm32 r7, 0x8eeeffff; + R0 = BYTEOP3P ( R3:2 , R1:0 ) (LO); + R1 = BYTEOP3P ( R3:2 , R1:0 ) (LO); + R2 = BYTEOP3P ( R3:2 , R1:0 ) (HI); + R3 = BYTEOP3P ( R3:2 , R1:0 ) (HI); + CHECKREG r0, 0x00FF00FF; + CHECKREG r1, 0x00FF00FF; + CHECKREG r2, 0xFF00FF00; + CHECKREG r3, 0x00000000; + + imm32 r0, 0x716789ab; + imm32 r1, 0x8289abcd; + imm32 r2, 0x93445555; + imm32 r3, 0xa4667777; + imm32 r4, 0xb56789ab; + imm32 r5, 0xd689abcd; + imm32 r6, 0xe7445555; + imm32 r7, 0x6f661235; + R4 = BYTEOP3P ( R1:0 , R3:2 ) (LO); + R5 = BYTEOP3P ( R1:0 , R3:2 ) (LO); + R6 = BYTEOP3P ( R1:0 , R3:2 ) (HI); + R7 = BYTEOP3P ( R1:0 , R3:2 ) (HI); + CHECKREG r4, 0x00FF0000; + CHECKREG r5, 0x00FF0000; + CHECKREG r6, 0xFF000000; + CHECKREG r7, 0xFF000000; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r4, 0x456789ab; + imm32 r5, 0x6689abcd; + imm32 r6, 0x47445555; + imm32 r7, 0x68667777; + R0 = BYTEOP3P ( R3:2 , R1:0 ) (LO); + R1 = BYTEOP3P ( R3:2 , R1:0 ) (LO); + R2 = BYTEOP3P ( R3:2 , R1:0 ) (HI); + R3 = BYTEOP3P ( R3:2 , R1:0 ) (HI); + CHECKREG r0, 0x00FF00FF; + CHECKREG r1, 0x00FF00FF; + CHECKREG r2, 0xFF00FF00; + CHECKREG r3, 0x00000000; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_bytepack.s b/sim/testsuite/sim/bfin/c_dsp32alu_bytepack.s new file mode 100644 index 0000000..731a692 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_bytepack.s @@ -0,0 +1,77 @@ +//Original:/testcases/core/c_dsp32alu_bytepack/c_dsp32alu_bytepack.dsp +// Spec Reference: dsp32alu bytepack +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R4 = BYTEPACK ( R0 , R0 ); +R5 = BYTEPACK ( R0 , R1 ); +R6 = BYTEPACK ( R0 , R2 ); +R7 = BYTEPACK ( R0 , R3 ); +CHECKREG r4, 0x67116711; +CHECKREG r5, 0x891D6711; +CHECKREG r6, 0x44156711; +CHECKREG r7, 0x66176711; + +imm32 r0, 0x1567892b; +imm32 r1, 0x2789ab2d; +imm32 r2, 0x34445525; +imm32 r3, 0x46667727; +imm32 r4, 0x58889929; +imm32 r5, 0x6aaabb2b; +imm32 r6, 0x7cccdd2d; +imm32 r7, 0x8eeeffff; +R4 = BYTEPACK ( R1 , R4 ); +R5 = BYTEPACK ( R1 , R5 ); +R6 = BYTEPACK ( R1 , R6 ); +R7 = BYTEPACK ( R1 , R7 ); +CHECKREG r4, 0x8829892D; +CHECKREG r5, 0xAA2B892D; +CHECKREG r6, 0xCC2D892D; +CHECKREG r7, 0xEEFF892D; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r0, 0x456789ab; +imm32 r1, 0x6689abcd; +imm32 r2, 0x47445555; +imm32 r3, 0x68667777; +R4 = BYTEPACK ( R2 , R0 ); +R5 = BYTEPACK ( R2 , R1 ); +R6 = BYTEPACK ( R2 , R2 ); +R7 = BYTEPACK ( R2 , R3 ); +CHECKREG r4, 0x67AB4455; +CHECKREG r5, 0x89CD4455; +CHECKREG r6, 0x44554455; +CHECKREG r7, 0x66774455; + +imm32 r0, 0x496789ab; +imm32 r1, 0x6489abcd; +imm32 r2, 0x4b445555; +imm32 r3, 0x6c647777; +imm32 r4, 0x8d889999; +imm32 r5, 0xaeaa4bbb; +imm32 r6, 0xcfccd44d; +imm32 r7, 0xe1eefff4; +R4 = BYTEPACK ( R3 , R4 ); +R5 = BYTEPACK ( R3 , R5 ); +R6 = BYTEPACK ( R3 , R6 ); +R7 = BYTEPACK ( R3 , R7 ); +CHECKREG r4, 0x88996477; +CHECKREG r5, 0xAABB6477; +CHECKREG r6, 0xCC4D6477; +CHECKREG r7, 0xEEF46477; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_byteunpack.s b/sim/testsuite/sim/bfin/c_dsp32alu_byteunpack.s new file mode 100644 index 0000000..95fa30a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_byteunpack.s @@ -0,0 +1,113 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteunpack/c_dsp32alu_byteunpack.dsp +// Spec Reference: dsp32alu byteunpack +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86667777; + ( R4 , R5 ) = BYTEUNPACK R1:0; + ( R1 , R3 ) = BYTEUNPACK R1:0; + ( R0 , R7 ) = BYTEUNPACK R1:0; + ( R6 , R2 ) = BYTEUNPACK R1:0; + CHECKREG r0, 0x00150067; + CHECKREG r1, 0x00150067; + CHECKREG r2, 0x00000067; + CHECKREG r3, 0x00890011; + CHECKREG r4, 0x00150067; + CHECKREG r5, 0x00890011; + CHECKREG r6, 0x00000015; + CHECKREG r7, 0x00890011; + + imm32 r0, 0x1567892b; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445525; + imm32 r3, 0x46667727; + imm32 r4, 0x58889929; + imm32 r5, 0x6aaabb2b; + imm32 r6, 0x7cccdd2d; + imm32 r7, 0x8eeeffff; + ( R1 , R0 ) = BYTEUNPACK R3:2; + ( R3 , R4 ) = BYTEUNPACK R3:2; + ( R5 , R2 ) = BYTEUNPACK R3:2; + ( R7 , R6 ) = BYTEUNPACK R3:2; + CHECKREG r0, 0x00550025; + CHECKREG r1, 0x00340044; + CHECKREG r2, 0x00550025; + CHECKREG r3, 0x00340044; + CHECKREG r4, 0x00550025; + CHECKREG r5, 0x00340044; + CHECKREG r6, 0x00000025; + CHECKREG r7, 0x00000055; + + imm32 r0, 0x416789ab; + imm32 r1, 0x6289abcd; + imm32 r2, 0x43445555; + imm32 r3, 0x64667777; + imm32 r0, 0x456789ab; + imm32 r1, 0x6689abcd; + imm32 r2, 0x47445555; + imm32 r3, 0x68667777; + ( R1 , R2 ) = BYTEUNPACK R1:0 (R); + ( R3 , R6 ) = BYTEUNPACK R1:0 (R); + ( R4 , R0 ) = BYTEUNPACK R1:0 (R); + ( R5 , R7 ) = BYTEUNPACK R1:0 (R); + CHECKREG r0, 0x00000089; + CHECKREG r1, 0x00660089; + CHECKREG r2, 0x00AB00CD; + CHECKREG r3, 0x00000066; + CHECKREG r4, 0x00000066; + CHECKREG r5, 0x00000066; + CHECKREG r6, 0x00000089; + CHECKREG r7, 0x00000089; + + imm32 r0, 0x496789ab; + imm32 r1, 0x6489abcd; + imm32 r2, 0x4b445555; + imm32 r3, 0x6c647777; + imm32 r4, 0x8d889999; + imm32 r5, 0xaeaa4bbb; + imm32 r6, 0xcfccd44d; + imm32 r7, 0xe1eefff4; + ( R0 , R1 ) = BYTEUNPACK R3:2 (R); + ( R2 , R3 ) = BYTEUNPACK R3:2 (R); + ( R4 , R5 ) = BYTEUNPACK R3:2 (R); + ( R6 , R7 ) = BYTEUNPACK R3:2 (R); + CHECKREG r0, 0x006C0064; + CHECKREG r1, 0x00770077; + CHECKREG r2, 0x006C0064; + CHECKREG r3, 0x00770077; + CHECKREG r4, 0x00000077; + CHECKREG r5, 0x00000077; + CHECKREG r6, 0x00000077; + CHECKREG r7, 0x00000077; + + imm32 r0, 0x4537891b; + imm32 r1, 0x6759ab2d; + imm32 r2, 0x44555535; + imm32 r3, 0x66665747; + imm32 r4, 0x88789565; + imm32 r5, 0xaa8abb5b; + imm32 r6, 0xcc9cdd85; + imm32 r7, 0xeeaeff9f; + ( R0 , R1 ) = BYTEUNPACK R1:0; + ( R2 , R3 ) = BYTEUNPACK R3:2 (R); + ( R4 , R5 ) = BYTEUNPACK R1:0 (R); + ( R6 , R7 ) = BYTEUNPACK R3:2; + CHECKREG r0, 0x00450037; + CHECKREG r1, 0x0089001B; + CHECKREG r2, 0x00660066; + CHECKREG r3, 0x00570047; + CHECKREG r4, 0x00000089; + CHECKREG r5, 0x0000001B; + CHECKREG r6, 0x00000066; + CHECKREG r7, 0x00000066; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_disalnexcpt.s b/sim/testsuite/sim/bfin/c_dsp32alu_disalnexcpt.s new file mode 100644 index 0000000..ef5d916 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_disalnexcpt.s @@ -0,0 +1,255 @@ +//Original:/testcases/core/c_dsp32alu_disalnexcpt/c_dsp32alu_disalnexcpt.dsp +// Spec Reference: c_dsp32alu_disalgnexcpt +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym P0, DATA1; + P0 += 1; I0 = P0; + loadsym P0, DATA2; + P0 += 1; I1 = P0; + loadsym P0, DATA3; + P0 += 1; I2 = P0; + loadsym P0, DATA4; + P0 += 1; I3 = P0; + + DISALGNEXCPT || NOP || R0 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R1 = [ I1 ++ ]; + DISALGNEXCPT || NOP || R2 = [ I2 ++ ]; + DISALGNEXCPT || NOP || R3 = [ I3 ++ ]; + DISALGNEXCPT || NOP || R4 = [ I0 ++ ]; + DISALGNEXCPT || NOP || R5 = [ I1 ++ ]; + DISALGNEXCPT || NOP || R6 = [ I2 ++ ]; + DISALGNEXCPT || NOP || R7 = [ I3 ++ ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x04050607; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x44454647; + CHECKREG r7, 0x64656667; + +// reverse to minus mninus i-- + DISALGNEXCPT || NOP || R0 = [ I0 -- ]; + DISALGNEXCPT || NOP || R1 = [ I1 -- ]; + DISALGNEXCPT || NOP || R2 = [ I2 -- ]; + DISALGNEXCPT || NOP || R3 = [ I3 -- ]; + DISALGNEXCPT || NOP || R4 = [ I0 -- ]; + DISALGNEXCPT || NOP || R5 = [ I1 -- ]; + DISALGNEXCPT || NOP || R6 = [ I2 -- ]; + DISALGNEXCPT || NOP || R7 = [ I3 -- ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x28292A2B; + CHECKREG r2, 0x48494A4B; + CHECKREG r3, 0x68696A6B; + CHECKREG r4, 0x04050607; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x44454647; + CHECKREG r7, 0x64656667; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + +DATA2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + +DATA3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + +DATA4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + +DATA5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xBC0DBE26 + +DATA6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_max.s b/sim/testsuite/sim/bfin/c_dsp32alu_max.s new file mode 100644 index 0000000..74d36f9 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_max.s @@ -0,0 +1,261 @@ +//Original:/testcases/core/c_dsp32alu_max/c_dsp32alu_max.dsp +// Spec Reference: dsp32alu dregs = max ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x85678911; +imm32 r1, 0x9789ab1d; +imm32 r2, 0xa4445b15; +imm32 r3, 0x46667717; +imm32 r4, 0xd567f91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = MAX ( R0 , R0 ); +R1 = MAX ( R0 , R1 ); +R2 = MAX ( R0 , R2 ); +R3 = MAX ( R0 , R3 ); +R4 = MAX ( R0 , R4 ); +R5 = MAX ( R0 , R5 ); +R6 = MAX ( R0 , R6 ); +R7 = MAX ( R0 , R7 ); +CHECKREG r0, 0x85678911; +CHECKREG r1, 0x9789AB1D; +CHECKREG r2, 0xA4445B15; +CHECKREG r3, 0x46667717; +CHECKREG r4, 0xD567F91B; +CHECKREG r5, 0x6789AB1D; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x86667777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = MAX ( R1 , R0 ); +R1 = MAX ( R1 , R1 ); +R2 = MAX ( R1 , R2 ); +R3 = MAX ( R1 , R3 ); +R4 = MAX ( R1 , R4 ); +R5 = MAX ( R1 , R5 ); +R6 = MAX ( R1 , R6 ); +R7 = MAX ( R1 , R7 ); +CHECKREG r0, 0xA789AB2D; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xB4445525; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0xD8889929; +CHECKREG r5, 0xEAAABB2B; +CHECKREG r6, 0xFCCCDD2D; +CHECKREG r7, 0x0EEEFFFF; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r4, 0x456789ab; +imm32 r5, 0x6689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = MAX ( R2 , R0 ); +R1 = MAX ( R2 , R1 ); +R2 = MAX ( R2 , R2 ); +R3 = MAX ( R2 , R3 ); +R4 = MAX ( R2 , R4 ); +R5 = MAX ( R2 , R5 ); +R6 = MAX ( R2 , R6 ); +R7 = MAX ( R2 , R7 ); +CHECKREG r0, 0x43445555; +CHECKREG r1, 0x6289ABCD; +CHECKREG r2, 0x43445555; +CHECKREG r3, 0x64667777; +CHECKREG r4, 0x456789AB; +CHECKREG r5, 0x6689ABCD; +CHECKREG r6, 0x47445555; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = MAX ( R3 , R0 ); +R1 = MAX ( R3 , R1 ); +R2 = MAX ( R3 , R2 ); +R3 = MAX ( R3 , R3 ); +R4 = MAX ( R3 , R4 ); +R5 = MAX ( R3 , R5 ); +R6 = MAX ( R3 , R6 ); +R7 = MAX ( R3 , R7 ); +CHECKREG r0, 0xC6667727; +CHECKREG r1, 0xC6667727; +CHECKREG r2, 0xC6667727; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0x456789AB; +CHECKREG r5, 0x6689ABCD; +CHECKREG r6, 0x47445555; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x5537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x74555535; +imm32 r3, 0x86665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = MAX ( R4 , R0 ); +R1 = MAX ( R4 , R1 ); +R2 = MAX ( R4 , R2 ); +R3 = MAX ( R4 , R3 ); +R4 = MAX ( R4 , R4 ); +R5 = MAX ( R4 , R5 ); +R6 = MAX ( R4 , R6 ); +R7 = MAX ( R4 , R7 ); +CHECKREG r0, 0x5537891B; +CHECKREG r1, 0x6759AB2D; +CHECKREG r2, 0x74555535; +CHECKREG r3, 0x88789565; +CHECKREG r4, 0x88789565; +CHECKREG r5, 0xAA8ABB5B; +CHECKREG r6, 0xCC9CDD85; +CHECKREG r7, 0xEEAEFF9F; + +imm32 r0, 0x556b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x79736564; +imm32 r3, 0x81278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = MAX ( R5 , R0 ); +R1 = MAX ( R5 , R1 ); +R2 = MAX ( R5 , R2 ); +R3 = MAX ( R5 , R3 ); +R4 = MAX ( R5 , R4 ); +R5 = MAX ( R5 , R5 ); +R6 = MAX ( R5 , R6 ); +R7 = MAX ( R5 , R7 ); +CHECKREG r0, 0x556B89AB; +CHECKREG r1, 0x69764BCD; +CHECKREG r2, 0x79736564; +CHECKREG r3, 0xAAAA0BBB; +CHECKREG r4, 0xAAAA0BBB; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0xCCCC1DDD; +CHECKREG r7, 0x12346FFF; + +imm32 r0, 0xe56739ab; +imm32 r1, 0xf7694bcd; +imm32 r2, 0xa3456755; +imm32 r3, 0x66666777; +imm32 r4, 0x42345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = MAX ( R6 , R0 ); +R1 = MAX ( R6 , R1 ); +R2 = MAX ( R6 , R2 ); +R3 = MAX ( R6 , R3 ); +R4 = MAX ( R6 , R4 ); +R5 = MAX ( R6 , R5 ); +R6 = MAX ( R6 , R6 ); +R7 = MAX ( R6 , R7 ); +CHECKREG r0, 0x043290D6; +CHECKREG r1, 0x043290D6; +CHECKREG r2, 0x043290D6; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x42345699; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x043290D6; +CHECKREG r7, 0x1234567F; + +imm32 r0, 0x576789ab; +imm32 r1, 0xd779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xf9ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = MAX ( R7 , R0 ); +R1 = MAX ( R7 , R1 ); +R2 = MAX ( R7 , R2 ); +R3 = MAX ( R7 , R3 ); +R4 = MAX ( R7 , R4 ); +R5 = MAX ( R7 , R5 ); +R6 = MAX ( R7 , R6 ); +R7 = MAX ( R7 , R7 ); +CHECKREG r0, 0x576789AB; +CHECKREG r1, 0xD779ABCD; +CHECKREG r2, 0x23456755; +CHECKREG r3, 0x56789007; +CHECKREG r4, 0x789AB799; +CHECKREG r5, 0xABCD2FF7; +CHECKREG r6, 0xF9AB1D7D; +CHECKREG r7, 0xABCD2FF7; +imm32 r0, 0xe56739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0xd3456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = MAX ( R4 , R7 ); +R5 = MAX ( R5 , R5 ); +R2 = MAX ( R6 , R3 ); +R6 = MAX ( R0 , R4 ); +R0 = MAX ( R1 , R6 ); +R2 = MAX ( R2 , R1 ); +R1 = MAX ( R3 , R0 ); +R7 = MAX ( R7 , R4 ); +CHECKREG r0, 0x67694BCD; +CHECKREG r1, 0x67694BCD; +CHECKREG r2, 0x67694BCD; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x12345699; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x12345699; +CHECKREG r7, 0x12345699; + +imm32 r0, 0xd76789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0xe3456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = MAX ( R4 , R0 ); +R5 = MAX ( R5 , R1 ); +R2 = MAX ( R2 , R2 ); +R7 = MAX ( R7 , R3 ); +R4 = MAX ( R3 , R4 ); +R0 = MAX ( R1 , R5 ); +R1 = MAX ( R0 , R6 ); +R6 = MAX ( R6 , R7 ); +CHECKREG r0, 0x6779ABCD; +CHECKREG r1, 0x6779ABCD; +CHECKREG r2, 0xE3456755; +CHECKREG r3, 0x789AB799; +CHECKREG r4, 0x789AB799; +CHECKREG r5, 0x6779ABCD; +CHECKREG r6, 0x789AB799; +CHECKREG r7, 0x789AB799; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_maxmax.s b/sim/testsuite/sim/bfin/c_dsp32alu_maxmax.s new file mode 100644 index 0000000..8e39d22 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_maxmax.s @@ -0,0 +1,261 @@ +//Original:/testcases/core/c_dsp32alu_maxmax/c_dsp32alu_maxmax.dsp +// Spec Reference: dsp32alu dregs = max / max ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x25678911; +imm32 r1, 0x2389ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0xe6657717; +imm32 r4, 0x5a67891b; +imm32 r5, 0x67b9ab1d; +imm32 r6, 0x744d5515; +imm32 r7, 0x8666c777; +R0 = MAX ( R0 , R0 ) (V); +R1 = MAX ( R0 , R1 ) (V); +R2 = MAX ( R0 , R2 ) (V); +R3 = MAX ( R0 , R3 ) (V); +R4 = MAX ( R0 , R4 ) (V); +R5 = MAX ( R0 , R5 ) (V); +R6 = MAX ( R0 , R6 ) (V); +R7 = MAX ( R0 , R7 ) (V); +CHECKREG r0, 0x25678911; +CHECKREG r1, 0x2567AB1D; +CHECKREG r2, 0x34445515; +CHECKREG r3, 0x25677717; +CHECKREG r4, 0x5A67891B; +CHECKREG r5, 0x67B9AB1D; +CHECKREG r6, 0x744D5515; +CHECKREG r7, 0x2567C777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = MAX ( R1 , R0 ) (V); +R1 = MAX ( R1 , R1 ) (V); +R2 = MAX ( R1 , R2 ) (V); +R3 = MAX ( R1 , R3 ) (V); +R4 = MAX ( R1 , R4 ) (V); +R5 = MAX ( R1 , R5 ) (V); +R6 = MAX ( R1 , R6 ) (V); +R7 = MAX ( R1 , R7 ) (V); +CHECKREG r0, 0xA789AB2D; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xB4445525; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0xD888AB2D; +CHECKREG r5, 0xEAAABB2B; +CHECKREG r6, 0xFCCCDD2D; +CHECKREG r7, 0x0EEEFFFF; + +imm32 r0, 0x416789ab; +imm32 r1, 0x5289abcd; +imm32 r2, 0x63445555; +imm32 r3, 0xa7669777; +imm32 r4, 0x456789ab; +imm32 r5, 0xb689abcd; +imm32 r6, 0xd7445555; +imm32 r7, 0x68667777; +R0 = MAX ( R2 , R0 ) (V); +R1 = MAX ( R2 , R1 ) (V); +R2 = MAX ( R2 , R2 ) (V); +R3 = MAX ( R2 , R3 ) (V); +R4 = MAX ( R2 , R4 ) (V); +R5 = MAX ( R2 , R5 ) (V); +R6 = MAX ( R2 , R6 ) (V); +R7 = MAX ( R2 , R7 ) (V); +CHECKREG r0, 0x63445555; +CHECKREG r1, 0x63445555; +CHECKREG r2, 0x63445555; +CHECKREG r3, 0x63445555; +CHECKREG r4, 0x63445555; +CHECKREG r5, 0x63445555; +CHECKREG r6, 0x63445555; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = MAX ( R3 , R0 ) (V); +R1 = MAX ( R3 , R1 ) (V); +R2 = MAX ( R3 , R2 ) (V); +R3 = MAX ( R3 , R3 ) (V); +R4 = MAX ( R3 , R4 ) (V); +R5 = MAX ( R3 , R5 ) (V); +R6 = MAX ( R3 , R6 ) (V); +R7 = MAX ( R3 , R7 ) (V); +CHECKREG r0, 0xC6667727; +CHECKREG r1, 0xC6667727; +CHECKREG r2, 0xC6667727; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0x63447727; +CHECKREG r5, 0x63447727; +CHECKREG r6, 0x63447727; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x4537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x44555535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = MAX ( R4 , R0 ) (V); +R1 = MAX ( R4 , R1 ) (V); +R2 = MAX ( R4 , R2 ) (V); +R3 = MAX ( R4 , R3 ) (V); +R4 = MAX ( R4 , R4 ) (V); +R5 = MAX ( R4 , R5 ) (V); +R6 = MAX ( R4 , R6 ) (V); +R7 = MAX ( R4 , R7 ) (V); +CHECKREG r0, 0x45379565; +CHECKREG r1, 0x6759AB2D; +CHECKREG r2, 0x44555535; +CHECKREG r3, 0x66665747; +CHECKREG r4, 0x88789565; +CHECKREG r5, 0xAA8ABB5B; +CHECKREG r6, 0xCC9CDD85; +CHECKREG r7, 0xEEAEFF9F; + +imm32 r0, 0xa56b89ab; +imm32 r1, 0x659b4bcd; +imm32 r2, 0xd9736564; +imm32 r3, 0x61278394; +imm32 r4, 0xb8876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = MAX ( R5 , R0 ) (V); +R1 = MAX ( R5 , R1 ) (V); +R2 = MAX ( R5 , R2 ) (V); +R3 = MAX ( R5 , R3 ) (V); +R4 = MAX ( R5 , R4 ) (V); +R5 = MAX ( R5 , R5 ) (V); +R6 = MAX ( R5 , R6 ) (V); +R7 = MAX ( R5 , R7 ) (V); +CHECKREG r0, 0xAAAA0BBB; +CHECKREG r1, 0x659B4BCD; +CHECKREG r2, 0xD9736564; +CHECKREG r3, 0x61270BBB; +CHECKREG r4, 0xB8876439; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0xCCCC1DDD; +CHECKREG r7, 0x12346FFF; + +imm32 r0, 0x956739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0xd3456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = MAX ( R6 , R0 ) (V); +R1 = MAX ( R6 , R1 ) (V); +R2 = MAX ( R6 , R2 ) (V); +R3 = MAX ( R6 , R3 ) (V); +R4 = MAX ( R6 , R4 ) (V); +R5 = MAX ( R6 , R5 ) (V); +R6 = MAX ( R6 , R6 ) (V); +R7 = MAX ( R6 , R7 ) (V); +CHECKREG r0, 0x043239AB; +CHECKREG r1, 0x67694BCD; +CHECKREG r2, 0x04326755; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x12345699; +CHECKREG r5, 0x456790D6; +CHECKREG r6, 0x043290D6; +CHECKREG r7, 0x1234567F; + +imm32 r0, 0x876789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0xd3456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = MAX ( R7 , R0 ) (V); +R1 = MAX ( R7 , R1 ) (V); +R2 = MAX ( R7 , R2 ) (V); +R3 = MAX ( R7 , R3 ) (V); +R4 = MAX ( R7 , R4 ) (V); +R5 = MAX ( R7 , R5 ) (V); +R6 = MAX ( R7 , R6 ) (V); +R7 = MAX ( R7 , R7 ) (V); +CHECKREG r0, 0xABCD2FF7; +CHECKREG r1, 0x67792FF7; +CHECKREG r2, 0xD3456755; +CHECKREG r3, 0x56782FF7; +CHECKREG r4, 0x789A2FF7; +CHECKREG r5, 0xABCD2FF7; +CHECKREG r6, 0xABCD2FF7; +CHECKREG r7, 0xABCD2FF7; +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = MAX ( R4 , R7 ) (V); +R5 = MAX ( R5 , R5 ) (V); +R2 = MAX ( R6 , R3 ) (V); +R6 = MAX ( R0 , R4 ) (V); +R0 = MAX ( R1 , R6 ) (V); +R2 = MAX ( R2 , R1 ) (V); +R1 = MAX ( R3 , R0 ) (V); +R7 = MAX ( R7 , R4 ) (V); +CHECKREG r0, 0x67695699; +CHECKREG r1, 0x67696777; +CHECKREG r2, 0x67696777; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x12345699; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x45675699; +CHECKREG r7, 0x12345699; + +imm32 r0, 0x876789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x2345d755; +imm32 r3, 0x5678b007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = MAX ( R4 , R0 ) (V); +R5 = MAX ( R5 , R1 ) (V); +R2 = MAX ( R2 , R2 ) (V); +R7 = MAX ( R7 , R3 ) (V); +R4 = MAX ( R3 , R4 ) (V); +R0 = MAX ( R1 , R5 ) (V); +R1 = MAX ( R0 , R6 ) (V); +R6 = MAX ( R6 , R7 ) (V); +CHECKREG r0, 0x67790BBB; +CHECKREG r1, 0x67791D7D; +CHECKREG r2, 0x2345D755; +CHECKREG r3, 0x789AB799; +CHECKREG r4, 0x789AB799; +CHECKREG r5, 0x67790BBB; +CHECKREG r6, 0x789A2FF7; +CHECKREG r7, 0x789A2FF7; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_min.s b/sim/testsuite/sim/bfin/c_dsp32alu_min.s new file mode 100644 index 0000000..b36eaac --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_min.s @@ -0,0 +1,261 @@ +//Original:/testcases/core/c_dsp32alu_min/c_dsp32alu_min.dsp +// Spec Reference: dsp32alu dregs = min ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x35678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0xf6667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = MIN ( R0 , R0 ); +R1 = MIN ( R0 , R1 ); +R2 = MIN ( R0 , R2 ); +R3 = MIN ( R0 , R3 ); +R4 = MIN ( R0 , R4 ); +R5 = MIN ( R0 , R5 ); +R6 = MIN ( R0 , R6 ); +R7 = MIN ( R0 , R7 ); +CHECKREG r0, 0x35678911; +CHECKREG r1, 0x2789AB1D; +CHECKREG r2, 0x35678911; +CHECKREG r3, 0xF6667717; +CHECKREG r4, 0x35678911; +CHECKREG r5, 0x35678911; +CHECKREG r6, 0x35678911; +CHECKREG r7, 0x86667777; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = MIN ( R1 , R0 ); +R1 = MIN ( R1 , R1 ); +R2 = MIN ( R1 , R2 ); +R3 = MIN ( R1 , R3 ); +R4 = MIN ( R1 , R4 ); +R5 = MIN ( R1 , R5 ); +R6 = MIN ( R1 , R6 ); +R7 = MIN ( R1 , R7 ); +CHECKREG r0, 0x9567892B; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xA789AB2D; +CHECKREG r3, 0xA789AB2D; +CHECKREG r4, 0xA789AB2D; +CHECKREG r5, 0xA789AB2D; +CHECKREG r6, 0xA789AB2D; +CHECKREG r7, 0xA789AB2D; + +imm32 r0, 0x716789ab; +imm32 r1, 0x8289abcd; +imm32 r2, 0x93445555; +imm32 r3, 0xa4667777; +imm32 r4, 0x456789ab; +imm32 r5, 0xb689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = MIN ( R2 , R0 ); +R1 = MIN ( R2 , R1 ); +R2 = MIN ( R2 , R2 ); +R3 = MIN ( R2 , R3 ); +R4 = MIN ( R2 , R4 ); +R5 = MIN ( R2 , R5 ); +R6 = MIN ( R2 , R6 ); +R7 = MIN ( R2 , R7 ); +CHECKREG r0, 0x93445555; +CHECKREG r1, 0x8289ABCD; +CHECKREG r2, 0x93445555; +CHECKREG r3, 0x93445555; +CHECKREG r4, 0x93445555; +CHECKREG r5, 0x93445555; +CHECKREG r6, 0x93445555; +CHECKREG r7, 0x93445555; + +imm32 r0, 0x2567892b; +imm32 r1, 0x5789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = MIN ( R3 , R0 ); +R1 = MIN ( R3 , R1 ); +R2 = MIN ( R3 , R2 ); +R3 = MIN ( R3 , R3 ); +R4 = MIN ( R3 , R4 ); +R5 = MIN ( R3 , R5 ); +R6 = MIN ( R3 , R6 ); +R7 = MIN ( R3 , R7 ); +CHECKREG r0, 0x9567892B; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xB4445525; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0x93445555; +CHECKREG r5, 0x93445555; +CHECKREG r6, 0x93445555; +CHECKREG r7, 0x93445555; + +imm32 r0, 0xd537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0xf455b535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = MIN ( R4 , R0 ); +R1 = MIN ( R4 , R1 ); +R2 = MIN ( R4 , R2 ); +R3 = MIN ( R4 , R3 ); +R4 = MIN ( R4 , R4 ); +R5 = MIN ( R4 , R5 ); +R6 = MIN ( R4 , R6 ); +R7 = MIN ( R4 , R7 ); +CHECKREG r0, 0x88789565; +CHECKREG r1, 0x88789565; +CHECKREG r2, 0x88789565; +CHECKREG r3, 0x88789565; +CHECKREG r4, 0x88789565; +CHECKREG r5, 0x88789565; +CHECKREG r6, 0x88789565; +CHECKREG r7, 0x88789565; + +imm32 r0, 0xa56b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = MIN ( R5 , R0 ); +R1 = MIN ( R5 , R1 ); +R2 = MIN ( R5 , R2 ); +R3 = MIN ( R5 , R3 ); +R4 = MIN ( R5 , R4 ); +R5 = MIN ( R5 , R5 ); +R6 = MIN ( R5 , R6 ); +R7 = MIN ( R5 , R7 ); +CHECKREG r0, 0xA56B89AB; +CHECKREG r1, 0xAAAA0BBB; +CHECKREG r2, 0xAAAA0BBB; +CHECKREG r3, 0xAAAA0BBB; +CHECKREG r4, 0x98876439; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0xAAAA0BBB; +CHECKREG r7, 0xAAAA0BBB; + +imm32 r0, 0xe56739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0xd2345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = MIN ( R6 , R0 ); +R1 = MIN ( R6 , R1 ); +R2 = MIN ( R6 , R2 ); +R3 = MIN ( R6 , R3 ); +R4 = MIN ( R6 , R4 ); +R5 = MIN ( R6 , R5 ); +R6 = MIN ( R6 , R6 ); +R7 = MIN ( R6 , R7 ); +CHECKREG r0, 0xE56739AB; +CHECKREG r1, 0x043290D6; +CHECKREG r2, 0x03456755; +CHECKREG r3, 0x043290D6; +CHECKREG r4, 0xD2345699; +CHECKREG r5, 0x043290D6; +CHECKREG r6, 0x043290D6; +CHECKREG r7, 0x043290D6; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = MIN ( R7 , R0 ); +R1 = MIN ( R7 , R1 ); +R2 = MIN ( R7 , R2 ); +R3 = MIN ( R7 , R3 ); +R4 = MIN ( R7 , R4 ); +R5 = MIN ( R7 , R5 ); +R6 = MIN ( R7 , R6 ); +R7 = MIN ( R7 , R7 ); +CHECKREG r0, 0xABCD2FF7; +CHECKREG r1, 0xABCD2FF7; +CHECKREG r2, 0xABCD2FF7; +CHECKREG r3, 0xABCD2FF7; +CHECKREG r4, 0xABCD2FF7; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0x89AB1D7D; +CHECKREG r7, 0xABCD2FF7; +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0xd3456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0xb43290d6; +imm32 r7, 0x1234567f; +R4 = MIN ( R4 , R7 ); +R5 = MIN ( R5 , R5 ); +R2 = MIN ( R6 , R3 ); +R6 = MIN ( R0 , R4 ); +R0 = MIN ( R1 , R6 ); +R2 = MIN ( R2 , R1 ); +R1 = MIN ( R3 , R0 ); +R7 = MIN ( R7 , R4 ); +CHECKREG r0, 0x1234567F; +CHECKREG r1, 0x1234567F; +CHECKREG r2, 0xB43290D6; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x1234567F; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x1234567F; +CHECKREG r7, 0x1234567F; + +imm32 r0, 0xa76789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0xf3456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = MIN ( R4 , R0 ); +R5 = MIN ( R5 , R1 ); +R2 = MIN ( R2 , R2 ); +R7 = MIN ( R7 , R3 ); +R4 = MIN ( R3 , R4 ); +R0 = MIN ( R1 , R5 ); +R1 = MIN ( R0 , R6 ); +R6 = MIN ( R6 , R7 ); +CHECKREG r0, 0xAAAA0BBB; +CHECKREG r1, 0x89AB1D7D; +CHECKREG r2, 0xF3456755; +CHECKREG r3, 0xA76789AB; +CHECKREG r4, 0xA76789AB; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0x89AB1D7D; +CHECKREG r7, 0xA76789AB; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_minmin.s b/sim/testsuite/sim/bfin/c_dsp32alu_minmin.s new file mode 100644 index 0000000..4106245 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_minmin.s @@ -0,0 +1,261 @@ +//Original:/testcases/core/c_dsp32alu_minmin/c_dsp32alu_minmin.dsp +// Spec Reference: dsp32alu dregs = min / min ( dregs, dregs) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x25678911; +imm32 r1, 0x2389ab1d; +imm32 r2, 0x2a445345; +imm32 r3, 0x46657717; +imm32 r4, 0xd567e91b; +imm32 r5, 0x6789af1d; +imm32 r6, 0x74445d85; +imm32 r7, 0x8666a779; +R0 = MIN ( R0 , R0 ) (V); +R1 = MIN ( R0 , R1 ) (V); +R2 = MIN ( R0 , R2 ) (V); +R3 = MIN ( R0 , R3 ) (V); +R4 = MIN ( R0 , R4 ) (V); +R5 = MIN ( R0 , R5 ) (V); +R6 = MIN ( R0 , R6 ) (V); +R7 = MIN ( R0 , R7 ) (V); +CHECKREG r0, 0x25678911; +CHECKREG r1, 0x23898911; +CHECKREG r2, 0x25678911; +CHECKREG r3, 0x25678911; +CHECKREG r4, 0xD5678911; +CHECKREG r5, 0x25678911; +CHECKREG r6, 0x25678911; +CHECKREG r7, 0x86668911; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = MIN ( R1 , R0 ) (V); +R1 = MIN ( R1 , R1 ) (V); +R2 = MIN ( R1 , R2 ) (V); +R3 = MIN ( R1 , R3 ) (V); +R4 = MIN ( R1 , R4 ) (V); +R5 = MIN ( R1 , R5 ) (V); +R6 = MIN ( R1 , R6 ) (V); +R7 = MIN ( R1 , R7 ) (V); +CHECKREG r0, 0x9567892B; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xA789AB2D; +CHECKREG r3, 0xA789AB2D; +CHECKREG r4, 0xA7899929; +CHECKREG r5, 0xA789AB2D; +CHECKREG r6, 0xA789AB2D; +CHECKREG r7, 0xA789AB2D; + +imm32 r0, 0x416789ab; +imm32 r1, 0x5289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0xa466a777; +imm32 r4, 0x45678dab; +imm32 r5, 0xf689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = MIN ( R2 , R0 ) (V); +R1 = MIN ( R2 , R1 ) (V); +R2 = MIN ( R2 , R2 ) (V); +R3 = MIN ( R2 , R3 ) (V); +R4 = MIN ( R2 , R4 ) (V); +R5 = MIN ( R2 , R5 ) (V); +R6 = MIN ( R2 , R6 ) (V); +R7 = MIN ( R2 , R7 ) (V); +CHECKREG r0, 0x416789AB; +CHECKREG r1, 0x4344ABCD; +CHECKREG r2, 0x43445555; +CHECKREG r3, 0xA466A777; +CHECKREG r4, 0x43448DAB; +CHECKREG r5, 0xF689ABCD; +CHECKREG r6, 0x43445555; +CHECKREG r7, 0x43445555; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = MIN ( R3 , R0 ) (V); +R1 = MIN ( R3 , R1 ) (V); +R2 = MIN ( R3 , R2 ) (V); +R3 = MIN ( R3 , R3 ) (V); +R4 = MIN ( R3 , R4 ) (V); +R5 = MIN ( R3 , R5 ) (V); +R6 = MIN ( R3 , R6 ) (V); +R7 = MIN ( R3 , R7 ) (V); +CHECKREG r0, 0x9567892B; +CHECKREG r1, 0xA789AB2D; +CHECKREG r2, 0xB4445525; +CHECKREG r3, 0xC6667727; +CHECKREG r4, 0xC6668DAB; +CHECKREG r5, 0xC666ABCD; +CHECKREG r6, 0xC6665555; +CHECKREG r7, 0xC6665555; + +imm32 r0, 0x5537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x74555535; +imm32 r3, 0x86665747; +imm32 r4, 0x98789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = MIN ( R4 , R0 ) (V); +R1 = MIN ( R4 , R1 ) (V); +R2 = MIN ( R4 , R2 ) (V); +R3 = MIN ( R4 , R3 ) (V); +R4 = MIN ( R4 , R4 ) (V); +R5 = MIN ( R4 , R5 ) (V); +R6 = MIN ( R4 , R6 ) (V); +R7 = MIN ( R4 , R7 ) (V); +CHECKREG r0, 0x9878891B; +CHECKREG r1, 0x98789565; +CHECKREG r2, 0x98789565; +CHECKREG r3, 0x86669565; +CHECKREG r4, 0x98789565; +CHECKREG r5, 0x98789565; +CHECKREG r6, 0x98789565; +CHECKREG r7, 0x98789565; + +imm32 r0, 0x256b89ab; +imm32 r1, 0x64764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x43346fff; +R0 = MIN ( R5 , R0 ) (V); +R1 = MIN ( R5 , R1 ) (V); +R2 = MIN ( R5 , R2 ) (V); +R3 = MIN ( R5 , R3 ) (V); +R4 = MIN ( R5 , R4 ) (V); +R5 = MIN ( R5 , R5 ) (V); +R6 = MIN ( R5 , R6 ) (V); +R7 = MIN ( R5 , R7 ) (V); +CHECKREG r0, 0xAAAA89AB; +CHECKREG r1, 0xAAAA0BBB; +CHECKREG r2, 0xAAAA0BBB; +CHECKREG r3, 0xAAAA8394; +CHECKREG r4, 0x98870BBB; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0xAAAA0BBB; +CHECKREG r7, 0xAAAA0BBB; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = MIN ( R6 , R0 ) (V); +R1 = MIN ( R6 , R1 ) (V); +R2 = MIN ( R6 , R2 ) (V); +R3 = MIN ( R6 , R3 ) (V); +R4 = MIN ( R6 , R4 ) (V); +R5 = MIN ( R6 , R5 ) (V); +R6 = MIN ( R6 , R6 ) (V); +R7 = MIN ( R6 , R7 ) (V); +CHECKREG r0, 0x043290D6; +CHECKREG r1, 0x043290D6; +CHECKREG r2, 0x034590D6; +CHECKREG r3, 0x043290D6; +CHECKREG r4, 0x043290D6; +CHECKREG r5, 0x04328B6B; +CHECKREG r6, 0x043290D6; +CHECKREG r7, 0x043290D6; + +imm32 r0, 0x976789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x8345a755; +imm32 r3, 0x5678b007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = MIN ( R7 , R0 ) (V); +R1 = MIN ( R7 , R1 ) (V); +R2 = MIN ( R7 , R2 ) (V); +R3 = MIN ( R7 , R3 ) (V); +R4 = MIN ( R7 , R4 ) (V); +R5 = MIN ( R7 , R5 ) (V); +R6 = MIN ( R7 , R6 ) (V); +R7 = MIN ( R7 , R7 ) (V); +CHECKREG r0, 0x976789AB; +CHECKREG r1, 0xABCDABCD; +CHECKREG r2, 0x8345A755; +CHECKREG r3, 0xABCDB007; +CHECKREG r4, 0xABCDB799; +CHECKREG r5, 0xAAAA0BBB; +CHECKREG r6, 0x89AB1D7D; +CHECKREG r7, 0xABCD2FF7; +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = MIN ( R4 , R7 ) (V); +R5 = MIN ( R5 , R5 ) (V); +R2 = MIN ( R6 , R3 ) (V); +R6 = MIN ( R0 , R4 ) (V); +R0 = MIN ( R1 , R6 ) (V); +R2 = MIN ( R2 , R1 ) (V); +R1 = MIN ( R3 , R0 ) (V); +R7 = MIN ( R7 , R4 ) (V); +CHECKREG r0, 0x123439AB; +CHECKREG r1, 0x123439AB; +CHECKREG r2, 0x043290D6; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x1234567F; +CHECKREG r5, 0x45678B6B; +CHECKREG r6, 0x123439AB; +CHECKREG r7, 0x1234567F; + +imm32 r0, 0xa76789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0xb3456755; +imm32 r3, 0x5678d007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = MIN ( R4 , R0 ) (V); +R5 = MIN ( R5 , R1 ) (V); +R2 = MIN ( R2 , R2 ) (V); +R7 = MIN ( R7 , R3 ) (V); +R4 = MIN ( R3 , R4 ) (V); +R0 = MIN ( R1 , R5 ) (V); +R1 = MIN ( R0 , R6 ) (V); +R6 = MIN ( R6 , R7 ) (V); +CHECKREG r0, 0xAAAAABCD; +CHECKREG r1, 0x89ABABCD; +CHECKREG r2, 0xB3456755; +CHECKREG r3, 0xA76789AB; +CHECKREG r4, 0xA76789AB; +CHECKREG r5, 0xAAAAABCD; +CHECKREG r6, 0x89AB89AB; +CHECKREG r7, 0xA76789AB; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_mix.s b/sim/testsuite/sim/bfin/c_dsp32alu_mix.s new file mode 100644 index 0000000..e54523c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_mix.s @@ -0,0 +1,137 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_mix/c_dsp32alu_mix.dsp +// Spec Reference: dsp32alu mix +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + +// ALU operations include parallel addition, subtraction, MAX, MIN, ABS on 16-bit +// and 32-bit data. If an operation use a single ALU only, it uses ALU0. + + imm32 r2, 0x44445555; + imm32 r3, 0x66667777; + imm32 r4, 0x88889999; + imm32 r5, 0xaaaabbbb; + imm32 r6, 0xccccdddd; + imm32 r7, 0xeeeeffff; + + imm32 r0, 0x456789ab; + imm32 r1, 0x6789abcd; +// Use only single ALU (ALU0 only), with saturation (S) + R2 = R1 + R0 (NS); /* 0xACF13578 */ + R3 = R2 + R0 (NS); /* 0xACF13578 */ + CHECKREG r2, 0xACF13578; + CHECKREG r3, 0xF258BF23; + R2 = R1 + R0 (S); /* 0x7FFFFFFF */ + R3 = R1 - R0 (NS); /* 0x22222222 */ + R4.L = R1.L + R0.L (NS); /* 0x88883578 */ + R5.L = R1.L + R0.H (NS); /* 0xAAAAF134 */ + R6.L = R1.H + R0.L (NS); /* 0xCCCCF134 */ + R7.L = R1.H + R0.H (NS); /* 0xEEEEACF0 */ + CHECKREG r2, 0x7FFFFFFF; + CHECKREG r3, 0x22222222; + CHECKREG r4, 0x88883578; + CHECKREG r5, 0xAAAAF134; + CHECKREG r6, 0xCCCCF134; + CHECKREG r7, 0xEEEEACF0; + + R4.H = R1.L + R0.L (S); /* 0x80003578 */ + R5.H = R1.L + R0.H (S); /* 0xF134F134 */ + R6.H = R1.H + R0.L (S); /* 0xF134F134 */ + CHECKREG r4, 0x80003578; + CHECKREG r5, 0xF134F134; + CHECKREG r6, 0xF134F134; + + R4.H = R1.L + R0.L (S); /* 0x80003578 */ + R5.H = R1.L + R0.H (S); /* 0xF134F134 */ + R6.H = R1.H + R0.L (S); /* 0xF134F134 */ + CHECKREG r4, 0x80003578; /* 0x */ + CHECKREG r5, 0xF134F134; /* 0x */ + CHECKREG r6, 0xF134F134; /* 0x */ + + R4.H = R1.L + R0.L (S); /* 0x80003578 */ + R5.H = R1.L + R0.H (S); /* 0xF134F134 */ + R6.H = R1.H + R0.L (S); /* 0xF134F134 */ + R7.H = R1.H + R0.H (S); /* 0x7FFFACF0 */ + CHECKREG r4, 0x80003578; /* 0x */ + CHECKREG r5, 0xF134F134; /* 0x */ + CHECKREG r6, 0xF134F134; /* 0x */ + CHECKREG r7, 0x7FFFACF0; /* 0x */ + +// Dual + R2 = R0 +|+ R1 (SCO); /* 0x80007FFF */ + R3 = R0 +|- R1 (S); /* 0x7FFFDDDE */ + R4 = R0 -|+ R1 (SCO); /* 0x8000DDDE)*/ + R5 = R0 -|- R1 (SCO); /* 0xDDDEDDDE */ + CHECKREG r2, 0x80007FFF; + CHECKREG r3, 0x7FFFDDDE; + CHECKREG r4, 0x8000DDDE; + CHECKREG r5, 0xDDDEDDDE; + R2 = R0 +|+ R1, R3 = R0 -|- R1 (SCO); /* 0x */ +CHECKREG r2, 0x7FFF8000; + R4 = R0 +|- R1 , R5 = R0 -|+ R1 (CO); /* 0x */ + R6 = R0 + R1, R7 = R0 - R1 (S); /* 0x */ + CHECKREG r2, 0x7FFF8000; + CHECKREG r3, 0xDDDEDDDE; + CHECKREG r4, 0xACF0DDDE; + CHECKREG r5, 0x3578DDDE; + CHECKREG r6, 0x7FFFFFFF; + CHECKREG r7, 0xDDDDDDDE; + +// Max min abs types + R3 = MAX ( R0 , R1 ); /* 0x6789ABCD */ + R4 = MIN ( R0 , R1 ); /* 0x456789AB */ + R5 = ABS R0; /* 0x456789AB */ + CHECKREG r3, 0x6789ABCD; + CHECKREG r4, 0x456789AB; + CHECKREG r5, 0x456789AB; + R3 = MAX ( R0 , R1 ) (V); /* 0x6789ABCD */ + R4 = MIN ( R0 , R1 ) (V); /* 0x456789AB */ + R5 = ABS R0 (V); /* 0x45677655 */ + CHECKREG r3, 0x6789ABCD; + CHECKREG r4, 0x456789AB; + CHECKREG r5, 0x45677655; + +// RND types + R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L; + R3.L = R0 + R1 (RND12); /* 0x */ + R4.H = R0 - R1 (RND12); /* 0x */ + R5.L = R0 + R1 (RND20); /* 0x */ + R6.H = R0 - R1 (RND20); /* 0x */ + R7.H = R1 (RND); /* 0x */ + CHECKREG r2, 0xBBBCBBBC; + CHECKREG r3, 0x67897FFF; + CHECKREG r4, 0x800089AB; + CHECKREG r5, 0x45670ACF; + CHECKREG r6, 0xFDDEFFFF; + CHECKREG r7, 0x678ADDDE; + + R7 = - R0 (V); /* 0x */ + CHECKREG r7, 0xBA997655; +// A0 & A1 types + A0 = 0; + A1 = 0; + A0.L = R0.L; + A0.H = R0.H; + A0 = A1; + A0.x = R0.L; + A1.x = R0.L; + R2.L = A0.x; /* 0x */ + R3.L = A1.x; /* 0x */ + R4 = ( A0 += A1 ); /* 0x */ + R5.L = ( A0 += A1 ); /* 0x */ + R5.H = ( A0 += A1 ); /* 0x */ + CHECKREG r2, 0xBBBCffAB; /* 0x */ + CHECKREG r3, 0x6789ffAB; /* 0x */ + CHECKREG r4, 0x80000000; /* 0x */ + CHECKREG r5, 0x80008000; /* 0x */ + A0 += A1; + A0 -= A1; + R6 = A1.L + A1.H, R7 = A0.L + A0.H; /* 0x */ + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_r_lh_a0pa1.s b/sim/testsuite/sim/bfin/c_dsp32alu_r_lh_a0pa1.s new file mode 100644 index 0000000..931662b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_r_lh_a0pa1.s @@ -0,0 +1,75 @@ +//Original:/testcases/core/c_dsp32alu_r_lh_a0pa1/c_dsp32alu_r_lh_a0pa1.dsp +// Spec Reference: dsp32alu r(lh) = ( a0 += a1) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x15678911; +imm32 r1, 0x0125ab2d; +imm32 r2, 0x04445535; +imm32 r3, 0x00567747; +imm32 r4, 0x0566895b; +imm32 r5, 0x07897b6d; +imm32 r6, 0x04445875; +imm32 r7, 0x06667797; +A0 = R0; +A1 = R1; +R0 = ( A0 += A1 ); +R1 = ( A0 += A1 ); +R2 = ( A0 += A1 ); +R3 = ( A0 += A1 ); +R4 = ( A0 += A1 ); +R5 = ( A0 += A1 ); +R6 = ( A0 += A1 ); +R7 = ( A0 += A1 ); +CHECKREG r0, 0x168D343E; +CHECKREG r1, 0x17B2DF6B; +CHECKREG r2, 0x18D88A98; +CHECKREG r3, 0x19FE35C5; +CHECKREG r4, 0x1B23E0F2; +CHECKREG r5, 0x1C498C1F; +CHECKREG r6, 0x1D6F374C; +CHECKREG r7, 0x1E94E279; + +imm32 r0, 0x068D343E; +imm32 r1, 0x02B2DF6B; +imm32 r2, 0x48388A98; +imm32 r3, 0x59F435C5; +imm32 r4, 0x6B25E0F2; +imm32 r5, 0x7C496C1F; +imm32 r6, 0x886F374C; +imm32 r7, 0x9E94E279; +A0 = R0; +A1 = R1; +R0.L = ( A0 += A1 ); +R0.H = ( A0 += A1 ); +R1.L = ( A0 += A1 ); +R1.H = ( A0 += A1 ); +R2.L = ( A0 += A1 ); +R2.H = ( A0 += A1 ); +R3.L = ( A0 += A1 ); +R3.H = ( A0 += A1 ); +R4.L = ( A0 += A1 ); +R4.H = ( A0 += A1 ); +R5.L = ( A0 += A1 ); +R5.H = ( A0 += A1 ); +R6.L = ( A0 += A1 ); +R6.H = ( A0 += A1 ); +R7.L = ( A0 += A1 ); +R7.H = ( A0 += A1 ); +CHECKREG r0, 0x0BF30940; +CHECKREG r1, 0x11590EA6; +CHECKREG r2, 0x16BE140C; +CHECKREG r3, 0x1C241971; +CHECKREG r4, 0x218A1ED7; +CHECKREG r5, 0x26F0243D; +CHECKREG r6, 0x2C5529A3; +CHECKREG r7, 0x31BB2F08; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_r_negneg.s b/sim/testsuite/sim/bfin/c_dsp32alu_r_negneg.s new file mode 100644 index 0000000..9c9d60c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_r_negneg.s @@ -0,0 +1,88 @@ +//Original:/testcases/core/c_dsp32alu_r_negneg/c_dsp32alu_r_negneg.dsp +// Spec Reference: dsp32alu dregs = neg / neg dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3b44b515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = - R0 (V); +R1 = - R1 (V); +R2 = - R2 (V); +R3 = - R3 (V); +R4 = - R4 (V); +R5 = - R5 (V); +R6 = - R6 (V); +R7 = - R7 (V); +CHECKREG r0, 0x5A9976EF; +CHECKREG r1, 0xD87754E3; +CHECKREG r2, 0xC4BC4AEB; +CHECKREG r3, 0xB99A88E9; +CHECKREG r4, 0xAA9976E5; +CHECKREG r5, 0x987754E3; +CHECKREG r6, 0x8BBCAAEB; +CHECKREG r7, 0x799A8889; + +imm32 r0, 0xa567892b; +imm32 r1, 0x2789ab2d; +imm32 r2, 0x344d5525; +imm32 r3, 0xd6667727; +imm32 r4, 0x58889929; +imm32 r5, 0x6aaabb2b; +imm32 r6, 0x7ccfdd2d; +imm32 r7, 0x8eeeffff; +R1 = - R0 (V); +R2 = - R1 (V); +R3 = - R2 (V); +R4 = - R3 (V); +R5 = - R4 (V); +R6 = - R5 (V); +R7 = - R6 (V); +R0 = - R7 (V); +CHECKREG r0, 0xA567892B; +CHECKREG r1, 0x5A9976D5; +CHECKREG r2, 0xA567892B; +CHECKREG r3, 0x5A9976D5; +CHECKREG r4, 0xA567892B; +CHECKREG r5, 0x5A9976D5; +CHECKREG r6, 0xA567892B; +CHECKREG r7, 0x5A9976D5; + +imm32 r0, 0xb5678941; +imm32 r1, 0x2789ab5d; +imm32 r2, 0x34445565; +imm32 r3, 0xe6667777; +imm32 r4, 0x5567898b; +imm32 r5, 0x6789ab9d; +imm32 r6, 0xc4445505; +imm32 r7, 0x8666b777; +R2 = - R0 (V); +R3 = - R1 (V); +R4 = - R2 (V); +R5 = - R3 (V); +R6 = - R4 (V); +R7 = - R5 (V); +R0 = - R6 (V); +R1 = - R7 (V); +CHECKREG r0, 0xB5678941; +CHECKREG r1, 0x2789AB5D; +CHECKREG r2, 0x4A9976BF; +CHECKREG r3, 0xD87754A3; +CHECKREG r4, 0xB5678941; +CHECKREG r5, 0x2789AB5D; +CHECKREG r6, 0x4A9976BF; +CHECKREG r7, 0xD87754A3; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rh_m.s b/sim/testsuite/sim/bfin/c_dsp32alu_rh_m.s new file mode 100644 index 0000000..ba4dfa3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rh_m.s @@ -0,0 +1,263 @@ +//Original:/testcases/core/c_dsp32alu_rh_m/c_dsp32alu_rh_m.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x89678911; +imm32 r1, 0x2189ab1d; +imm32 r2, 0x34145515; +imm32 r3, 0x46617717; +imm32 r4, 0x5678191b; +imm32 r5, 0x6789a11d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667771; +R0.H = R0.L - R0.L (NS); +R1.H = R0.L - R1.H (NS); +R2.H = R0.H - R2.L (NS); +R3.H = R0.H - R3.H (NS); +R4.H = R0.L - R4.L (NS); +R5.H = R0.L - R5.H (NS); +R6.H = R0.H - R6.L (NS); +R7.H = R0.H - R7.H (NS); +CHECKREG r4, 0x6FF6191B; +CHECKREG r5, 0x2188A11D; +CHECKREG r6, 0xAAEB5515; +CHECKREG r7, 0x799A7771; +CHECKREG r4, 0x6FF6191B; +CHECKREG r5, 0x2188A11D; +CHECKREG r6, 0xAAEB5515; +CHECKREG r7, 0x799A7771; + +imm32 r0, 0x25678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x38445515; +imm32 r3, 0x468a7717; +imm32 r4, 0x5678e91b; +imm32 r5, 0x6789af1d; +imm32 r6, 0x744455f5; +imm32 r7, 0x8666777f; +R0.H = R1.L - R0.L (NS); +R1.H = R1.L - R1.H (NS); +R2.H = R1.H - R2.L (NS); +R3.H = R1.H - R3.H (NS); +R4.H = R1.L - R4.L (NS); +R5.H = R1.L - R5.H (NS); +R6.H = R1.H - R6.L (NS); +R7.H = R1.H - R7.H (NS); +CHECKREG r4, 0xC202E91B; +CHECKREG r5, 0x4394AF1D; +CHECKREG r6, 0x2D9F55F5; +CHECKREG r7, 0xFD2E777F; +CHECKREG r4, 0xC202E91B; +CHECKREG r5, 0x4394AF1D; +CHECKREG r6, 0x2D9F55F5; +CHECKREG r7, 0xFD2E777F; + +imm32 r0, 0x78678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34885515; +imm32 r3, 0x466aa717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789aa1d; +imm32 r6, 0x74445aa5; +imm32 r7, 0x866677a7; +R0.H = R2.L - R0.L (NS); +R1.H = R2.L - R1.H (NS); +R2.H = R2.H - R2.L (NS); +R3.H = R2.H - R3.H (NS); +R4.H = R2.L - R4.L (NS); +R5.H = R2.L - R5.H (NS); +R6.H = R2.H - R6.L (NS); +R7.H = R2.H - R7.H (NS); +CHECKREG r4, 0xCBFA891B; +CHECKREG r5, 0xED8CAA1D; +CHECKREG r6, 0x84CE5AA5; +CHECKREG r7, 0x590D77A7; +CHECKREG r4, 0xCBFA891B; +CHECKREG r5, 0xED8CAA1D; +CHECKREG r6, 0x84CE5AA5; +CHECKREG r7, 0x590D77A7; + +imm32 r0, 0xb5678911; +imm32 r1, 0xb789ab1d; +imm32 r2, 0x3b445515; +imm32 r3, 0x46b67717; +imm32 r4, 0x567b891b; +imm32 r5, 0x6789bb1d; +imm32 r6, 0x74445b15; +imm32 r7, 0x866677b7; +R0.H = R3.L - R0.L (NS); +R1.H = R3.L - R1.H (NS); +R2.H = R3.H - R2.L (NS); +R3.H = R3.H - R3.H (NS); +R4.H = R3.L - R4.L (NS); +R5.H = R3.L - R5.H (NS); +R6.H = R3.H - R6.L (NS); +R7.H = R3.H - R7.H (NS); +CHECKREG r4, 0xEDFC891B; +CHECKREG r5, 0x0F8EBB1D; +CHECKREG r6, 0xA4EB5B15; +CHECKREG r7, 0x799A77B7; +CHECKREG r4, 0xEDFC891B; +CHECKREG r5, 0x0F8EBB1D; +CHECKREG r6, 0xA4EB5B15; +CHECKREG r7, 0x799A77B7; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.H = R4.L - R0.L (NS); +R1.H = R4.L - R1.H (NS); +R2.H = R4.H - R2.L (NS); +R3.H = R4.H - R3.H (NS); +R4.H = R4.L - R4.L (NS); +R5.H = R4.L - R5.H (NS); +R6.H = R4.H - R6.L (NS); +R7.H = R4.H - R7.H (NS); +CHECKREG r4, 0x0000891B; +CHECKREG r5, 0x2192AB1D; +CHECKREG r6, 0xAAEB5515; +CHECKREG r7, 0x799A7777; +CHECKREG r4, 0x0000891B; +CHECKREG r5, 0x2192AB1D; +CHECKREG r6, 0xAAEB5515; +CHECKREG r7, 0x799A7777; + +imm32 r0, 0xcc678911; +imm32 r1, 0xc789ab1d; +imm32 r2, 0x3c445515; +imm32 r3, 0x46c67717; +imm32 r4, 0x567c891b; +imm32 r5, 0x6789cb1d; +imm32 r6, 0x74445c15; +imm32 r7, 0x866677c7; +R0.H = R5.L - R0.L (NS); +R1.H = R5.L - R1.H (NS); +R2.H = R5.H - R2.L (NS); +R3.H = R5.H - R3.H (NS); +R4.H = R5.L - R4.L (NS); +R5.H = R5.L - R5.H (NS); +R6.H = R5.H - R6.L (NS); +R7.H = R5.H - R7.H (NS); +CHECKREG r4, 0x4202891B; +CHECKREG r5, 0x6394CB1D; +CHECKREG r6, 0x077F5C15; +CHECKREG r7, 0xDD2E77C7; +CHECKREG r4, 0x4202891B; +CHECKREG r5, 0x6394CB1D; +CHECKREG r6, 0x077F5C15; +CHECKREG r7, 0xDD2E77C7; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.H = R6.L - R0.L (NS); +R1.H = R6.L - R1.H (NS); +R2.H = R6.H - R2.L (NS); +R3.H = R6.H - R3.H (NS); +R4.H = R6.L - R4.L (NS); +R5.H = R6.L - R5.H (NS); +R6.H = R6.H - R6.L (NS); +R7.H = R6.H - R7.H (NS); +CHECKREG r4, 0xCBFA891B; +CHECKREG r5, 0xED8CAB1D; +CHECKREG r6, 0x1F2F5515; +CHECKREG r7, 0x98C97777; +CHECKREG r4, 0xCBFA891B; +CHECKREG r5, 0xED8CAB1D; +CHECKREG r6, 0x1F2F5515; +CHECKREG r7, 0x98C97777; + +imm32 r0, 0xd5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667e17; +imm32 r4, 0x56e8891b; +imm32 r5, 0x678eab1d; +imm32 r6, 0x7444e515; +imm32 r7, 0x86667e77; +R0.H = R7.L - R0.L (NS); +R1.H = R7.L - R1.H (NS); +R2.H = R7.H - R2.L (NS); +R3.H = R7.H - R3.H (NS); +R4.H = R7.L - R4.L (NS); +R5.H = R7.L - R5.H (NS); +R6.H = R7.H - R6.L (NS); +R7.H = R7.H - R7.H (NS); +CHECKREG r4, 0xF55C891B; +CHECKREG r5, 0x16E9AB1D; +CHECKREG r6, 0xA151E515; +CHECKREG r7, 0x00007E77; +CHECKREG r4, 0xF55C891B; +CHECKREG r5, 0x16E9AB1D; +CHECKREG r6, 0xA151E515; +CHECKREG r7, 0x00007E77; + +imm32 r0, 0xff678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34ff5515; +imm32 r3, 0x4666f717; +imm32 r4, 0x567f891b; +imm32 r5, 0x6789fb1d; +imm32 r6, 0x74445f15; +imm32 r7, 0x866677f7; +R6.H = R2.L - R3.L (S); +R1.H = R4.L - R5.H (S); +R5.H = R7.H - R2.L (S); +R3.H = R0.H - R0.H (S); +R0.H = R3.L - R4.L (S); +R2.H = R5.L - R7.H (S); +R7.H = R6.H - R7.L (S); +R4.H = R1.H - R6.H (S); +CHECKREG r4, 0x8000891B; +CHECKREG r5, 0x8000FB1D; +CHECKREG r6, 0x5DFE5F15; +CHECKREG r7, 0xE60777F7; +CHECKREG r4, 0x8000891B; +CHECKREG r5, 0x8000FB1D; +CHECKREG r6, 0x5DFE5F15; +CHECKREG r7, 0xE60777F7; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3.H = R4.L - R0.L (S); +R1.H = R6.L - R3.H (S); +R4.H = R3.H - R2.L (S); +R6.H = R7.H - R1.H (S); +R2.H = R5.L - R4.L (S); +R7.H = R2.L - R7.H (S); +R0.H = R1.H - R6.L (S); +R5.H = R0.H - R5.H (S); +CHECKREG r4, 0xAAF5891B; +CHECKREG r5, 0x986DAB1D; +CHECKREG r6, 0x80005515; +CHECKREG r7, 0x7FFF7777; +CHECKREG r4, 0xAAF5891B; +CHECKREG r5, 0x986DAB1D; +CHECKREG r6, 0x80005515; +CHECKREG r7, 0x7FFF7777; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rh_p.s b/sim/testsuite/sim/bfin/c_dsp32alu_rh_p.s new file mode 100644 index 0000000..fb7d3fa --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rh_p.s @@ -0,0 +1,263 @@ +//Original:/testcases/core/c_dsp32alu_rh_p/c_dsp32alu_rh_p.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x34678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34645515; +imm32 r3, 0x46667717; +imm32 r4, 0xd678891b; +imm32 r5, 0x6e89ab1d; +imm32 r6, 0x74b45515; +imm32 r7, 0x866cc777; +R0.H = R0.L + R0.L (NS); +R1.H = R0.L + R1.H (NS); +R2.H = R0.H + R2.L (NS); +R3.H = R0.H + R3.H (NS); +R4.H = R0.L + R4.L (NS); +R5.H = R0.L + R5.H (NS); +R6.H = R0.H + R6.L (NS); +R7.H = R0.H + R7.H (NS); +CHECKREG r4, 0x122C891B; +CHECKREG r5, 0xF79AAB1D; +CHECKREG r6, 0x67375515; +CHECKREG r7, 0x988EC777; +CHECKREG r4, 0x122C891B; +CHECKREG r5, 0xF79AAB1D; +CHECKREG r6, 0x67375515; +CHECKREG r7, 0x988EC777; + +imm32 r0, 0x12348911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34f45515; +imm32 r3, 0x46d67717; +imm32 r4, 0x567b891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444b515; +imm32 r7, 0x86667a77; +R0.H = R1.L + R0.L (NS); +R1.H = R1.L + R1.H (NS); +R2.H = R1.H + R2.L (NS); +R3.H = R1.H + R3.H (NS); +R4.H = R1.L + R4.L (NS); +R5.H = R1.L + R5.H (NS); +R6.H = R1.H + R6.L (NS); +R7.H = R1.H + R7.H (NS); +CHECKREG r4, 0x3438891B; +CHECKREG r5, 0x12A6AB1D; +CHECKREG r6, 0x8EBBB515; +CHECKREG r7, 0x600C7A77; +CHECKREG r4, 0x3438891B; +CHECKREG r5, 0x12A6AB1D; +CHECKREG r6, 0x8EBBB515; +CHECKREG r7, 0x600C7A77; + +imm32 r0, 0x85678911; +imm32 r1, 0x3989ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x5e78891b; +imm32 r5, 0x67d9ab1d; +imm32 r6, 0x744b5515; +imm32 r7, 0x86668777; +R0.H = R2.L + R0.L (NS); +R1.H = R2.L + R1.H (NS); +R2.H = R2.H + R2.L (NS); +R3.H = R2.H + R3.H (NS); +R4.H = R2.L + R4.L (NS); +R5.H = R2.L + R5.H (NS); +R6.H = R2.H + R6.L (NS); +R7.L = R2.H + R7.H (NS); +CHECKREG r4, 0xDE30891B; +CHECKREG r5, 0xBCEEAB1D; +CHECKREG r6, 0xDE6E5515; +CHECKREG r7, 0x86660FBF; +CHECKREG r4, 0xDE30891B; +CHECKREG r5, 0xBCEEAB1D; +CHECKREG r6, 0xDE6E5515; +CHECKREG r7, 0x86660FBF; + +imm32 r0, 0x25678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3e445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x567f891b; +imm32 r5, 0x6789bb1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667b77; +R0.H = R3.L + R0.L (NS); +R1.H = R3.L + R1.H (NS); +R2.H = R3.H + R2.L (NS); +R3.H = R3.H + R3.H (NS); +R4.H = R3.L + R4.L (NS); +R5.H = R3.L + R5.H (NS); +R6.H = R3.H + R6.L (NS); +R7.H = R3.H + R7.H (NS); +CHECKREG r4, 0x0032891B; +CHECKREG r5, 0xDEA0BB1D; +CHECKREG r6, 0xE2C15515; +CHECKREG r7, 0x14127B77; +CHECKREG r4, 0x0032891B; +CHECKREG r5, 0xDEA0BB1D; +CHECKREG r6, 0xE2C15515; +CHECKREG r7, 0x14127B77; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.H = R4.L + R0.L (NS); +R1.H = R4.L + R1.H (NS); +R2.H = R4.H + R2.L (NS); +R3.H = R4.H + R3.H (NS); +R4.H = R4.L + R4.L (NS); +R5.H = R4.L + R5.H (NS); +R6.H = R4.H + R6.L (NS); +R7.H = R4.H + R7.H (NS); +CHECKREG r4, 0x1236891B; +CHECKREG r5, 0xF0A4AB1D; +CHECKREG r6, 0x674B5515; +CHECKREG r7, 0x989C7777; +CHECKREG r4, 0x1236891B; +CHECKREG r5, 0xF0A4AB1D; +CHECKREG r6, 0x674B5515; +CHECKREG r7, 0x989C7777; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34d45515; +imm32 r3, 0x466b7717; +imm32 r4, 0x5678f91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444a515; +imm32 r7, 0x86667b77; +R0.H = R5.L + R0.L (NS); +R1.H = R5.L + R1.H (NS); +R2.H = R5.H + R2.L (NS); +R3.H = R5.H + R3.H (NS); +R4.H = R5.L + R4.L (NS); +R5.H = R5.L + R5.H (NS); +R6.H = R5.H + R6.L (NS); +R7.H = R5.H + R7.H (NS); +CHECKREG r4, 0xA438F91B; +CHECKREG r5, 0x12A6AB1D; +CHECKREG r6, 0xB7BBA515; +CHECKREG r7, 0x990C7B77; +CHECKREG r4, 0xA438F91B; +CHECKREG r5, 0x12A6AB1D; +CHECKREG r6, 0xB7BBA515; +CHECKREG r7, 0x990C7B77; + +imm32 r0, 0xf5678911; +imm32 r1, 0x2f89ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46f67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678fab1d; +imm32 r6, 0x7444f515; +imm32 r7, 0x86667f77; +R0.L = R6.L + R0.L (NS); +R1.H = R6.L + R1.H (NS); +R2.H = R6.H + R2.L (NS); +R3.H = R6.H + R3.H (NS); +R4.H = R6.L + R4.L (NS); +R5.H = R6.L + R5.H (NS); +R6.H = R6.H + R6.L (NS); +R7.H = R6.H + R7.H (NS); +CHECKREG r4, 0x7E30891B; +CHECKREG r5, 0x5CA4AB1D; +CHECKREG r6, 0x6959F515; +CHECKREG r7, 0xEFBF7F77; +CHECKREG r4, 0x7E30891B; +CHECKREG r5, 0x5CA4AB1D; +CHECKREG r6, 0x6959F515; +CHECKREG r7, 0xEFBF7F77; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.H = R7.L + R0.L (NS); +R1.H = R7.L + R1.H (NS); +R2.H = R7.H + R2.L (NS); +R3.H = R7.H + R3.H (NS); +R4.H = R7.L + R4.L (NS); +R5.H = R7.L + R5.H (NS); +R6.H = R7.H + R6.L (NS); +R7.H = R7.H + R7.H (NS); +CHECKREG r4, 0x0092891B; +CHECKREG r5, 0xDF00AB1D; +CHECKREG r6, 0xDB7B5515; +CHECKREG r7, 0x0CCC7777; +CHECKREG r4, 0x0092891B; +CHECKREG r5, 0xDF00AB1D; +CHECKREG r6, 0xDB7B5515; +CHECKREG r7, 0x0CCC7777; + +imm32 r0, 0x56678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34645515; +imm32 r3, 0x466a7717; +imm32 r4, 0x5678e91b; +imm32 r5, 0x6789af1d; +imm32 r6, 0x744455f5; +imm32 r7, 0x866677b7; +R6.H = R2.L + R3.L (S); +R1.H = R4.L + R5.H (S); +R5.H = R7.H + R2.L (S); +R3.H = R0.H + R0.H (S); +R0.H = R3.L + R4.L (S); +R2.H = R5.L + R7.H (S); +R7.H = R6.H + R7.L (S); +R4.H = R1.H + R6.H (S); +CHECKREG r4, 0x7FFFE91B; +CHECKREG r5, 0xDB7BAF1D; +CHECKREG r6, 0x7FFF55F5; +CHECKREG r7, 0x7FFF77B7; +CHECKREG r4, 0x7FFFE91B; +CHECKREG r5, 0xDB7BAF1D; +CHECKREG r6, 0x7FFF55F5; +CHECKREG r7, 0x7FFF77B7; + +imm32 r0, 0x95678911; +imm32 r1, 0x2989ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46967717; +imm32 r4, 0x5679891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74449515; +imm32 r7, 0x86667977; +R3.H = R4.L + R0.L (S); +R1.H = R6.L + R3.H (S); +R4.H = R3.H + R2.L (S); +R6.H = R7.H + R1.H (S); +R2.H = R5.L + R4.L (S); +R7.H = R2.L + R7.H (S); +R0.H = R1.H + R6.L (S); +R5.H = R0.H + R5.H (S); +CHECKREG r4, 0xD515891B; +CHECKREG r5, 0xE789AB1D; +CHECKREG r6, 0x80009515; +CHECKREG r7, 0xDB7B7977; +CHECKREG r4, 0xD515891B; +CHECKREG r5, 0xE789AB1D; +CHECKREG r6, 0x80009515; +CHECKREG r7, 0xDB7B7977; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_m.s b/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_m.s new file mode 100644 index 0000000..daf114a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_m.s @@ -0,0 +1,258 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_m/c_dsp32alu_rh_rnd12_m.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x45678ad1; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xf4445545; + imm32 r3, 0x46667767; + imm32 r4, 0xe678891b; + imm32 r5, 0x6f89ab1d; + imm32 r6, 0x7444d565; + imm32 r7, 0x8666b797; + R0.H = R0 - R0 (RND12); + R1.H = R0 - R1 (RND12); + R2.H = R0 - R2 (RND12); + R3.H = R0 - R3 (RND12); + R4.H = R0 - R4 (RND12); + R5.H = R0 - R5 (RND12); + R6.H = R0 - R6 (RND12); + R7.H = R0 - R7 (RND12); + CHECKREG r0, 0x00008AD1; + CHECKREG r1, 0x8000AB1D; + CHECKREG r2, 0x7fff5545; + CHECKREG r3, 0x80007767; + CHECKREG r4, 0x7fff891B; + CHECKREG r5, 0x8000AB1D; + CHECKREG r6, 0x8000D565; + CHECKREG r7, 0x7fffB797; + + imm32 r0, 0xd5678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xa4445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5b78891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74e45515; + imm32 r7, 0x86a6b777; + R0.H = R1 - R0 (RND12); + R1.H = R1 - R1 (RND12); + R2.H = R1 - R2 (RND12); + R3.H = R1 - R3 (RND12); + R4.H = R1 - R4 (RND12); + R5.H = R1 - R5 (RND12); + R6.H = R1 - R6 (RND12); + R7.H = R1 - R7 (RND12); + CHECKREG r0, 0x7fff8911; + CHECKREG r1, 0x0000AB1D; + CHECKREG r2, 0x7fff5515; + CHECKREG r3, 0x80007717; + CHECKREG r4, 0x8000891B; + CHECKREG r5, 0x8000AB1D; + CHECKREG r6, 0x80005515; + CHECKREG r7, 0x7fffB777; + + imm32 r0, 0xa5678091; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xb4445515; + imm32 r3, 0x46667717; + imm32 r4, 0xd678891b; + imm32 r5, 0x6e89ab4d; + imm32 r6, 0x74445567; + imm32 r7, 0x86967757; + R0.H = R2 - R0 (RND12); + R1.H = R2 - R1 (RND12); + R2.H = R2 - R2 (RND12); + R3.H = R2 - R3 (RND12); + R4.H = R2 - R4 (RND12); + R5.H = R2 - R5 (RND12); + R6.H = R2 - R6 (RND12); + R7.H = R2 - R7 (RND12); + CHECKREG r0, 0x7fff8091; + CHECKREG r1, 0x8000AB1D; + CHECKREG r2, 0x00005515; + CHECKREG r3, 0x80007717; + CHECKREG r4, 0x7fff891B; + CHECKREG r5, 0x8000AB4D; + CHECKREG r6, 0x80005567; + CHECKREG r7, 0x7fff7757; + + imm32 r0, 0x35678991; + imm32 r1, 0x2789ab8d; + imm32 r2, 0xd4445515; + imm32 r3, 0x46667737; + imm32 r4, 0x5678891b; + imm32 r5, 0xeab9ab4d; + imm32 r6, 0x744e5515; + imm32 r7, 0x866e747f; + R0.H = R3 - R0 (RND12); + R1.H = R3 - R1 (RND12); + R2.H = R3 - R2 (RND12); + R3.H = R3 - R3 (RND12); + R4.H = R3 - R4 (RND12); + R5.H = R3 - R5 (RND12); + R6.H = R3 - R6 (RND12); + R7.H = R3 - R7 (RND12); + CHECKREG r0, 0x7fff8991; + CHECKREG r1, 0x7fffAB8D; + CHECKREG r2, 0x7fff5515; + CHECKREG r3, 0x00007737; + CHECKREG r4, 0x8000891B; + CHECKREG r5, 0x7fffAB4D; + CHECKREG r6, 0x80005515; + CHECKREG r7, 0x7fff747F; + + imm32 r0, 0xe5678931; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34e45555; + imm32 r3, 0xd6667767; + imm32 r4, 0x5675891b; + imm32 r5, 0x6789abfd; + imm32 r6, 0xa4465515; + imm32 r7, 0x8b66e7b7; + R0.H = R4 - R0 (RND12); + R1.H = R4 - R1 (RND12); + R2.H = R4 - R2 (RND12); + R3.H = R4 - R3 (RND12); + R4.H = R4 - R4 (RND12); + R5.H = R4 - R5 (RND12); + R6.H = R4 - R6 (RND12); + R7.H = R4 - R7 (RND12); + CHECKREG r0, 0x7fff8931; + CHECKREG r1, 0x7fffAB1D; + CHECKREG r2, 0x7fff5555; + CHECKREG r3, 0x7fff7767; + CHECKREG r4, 0x0000891B; + CHECKREG r5, 0x8000ABFD; + CHECKREG r6, 0x7fff5515; + CHECKREG r7, 0x7fffE7B7; + + imm32 r0, 0x35678931; + imm32 r1, 0x2789ab4d; + imm32 r2, 0x3e445585; + imm32 r3, 0x46667717; + imm32 r4, 0xe6f8899b; + imm32 r5, 0x6789db1d; + imm32 r6, 0xf44a5515; + imm32 r7, 0x866b77b7; + R0.H = R5 - R0 (RND12); + R1.H = R5 - R1 (RND12); + R2.H = R5 - R2 (RND12); + R3.H = R5 - R3 (RND12); + R4.H = R5 - R4 (RND12); + R5.H = R5 - R5 (RND12); + R6.H = R5 - R6 (RND12); + R7.H = R5 - R7 (RND12); + CHECKREG r0, 0x7fff8931; + CHECKREG r1, 0x7fffAB4D; + CHECKREG r2, 0x7fff5585; + CHECKREG r3, 0x7fff7717; + CHECKREG r4, 0x7fff899B; + CHECKREG r5, 0x0000DB1D; + CHECKREG r6, 0x7fff5515; + CHECKREG r7, 0x7fff77B7; + + imm32 r0, 0xb5678911; + imm32 r1, 0xc789ab1d; + imm32 r2, 0x3ab45515; + imm32 r3, 0x466b7717; + imm32 r4, 0x4678e91b; + imm32 r5, 0x6789af1d; + imm32 r6, 0xf4445515; + imm32 r7, 0x86e6f777; + R0.H = R6 - R0 (RND12); + R1.H = R6 - R1 (RND12); + R2.H = R6 - R2 (RND12); + R3.H = R6 - R3 (RND12); + R4.H = R6 - R4 (RND12); + R5.H = R6 - R5 (RND12); + R6.H = R6 - R6 (RND12); + R7.H = R6 - R7 (RND12); + CHECKREG r0, 0x7fff8911; + CHECKREG r1, 0x7fffAB1D; + CHECKREG r2, 0x80005515; + CHECKREG r3, 0x80007717; + CHECKREG r4, 0x8000E91B; + CHECKREG r5, 0x8000AF1D; + CHECKREG r6, 0x00005515; + CHECKREG r7, 0x7fffF777; + + imm32 r0, 0xab678051; + imm32 r1, 0x2c89a26d; + imm32 r2, 0x34d455f5; + imm32 r3, 0x466e7717; + imm32 r4, 0x567f89bb; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x744e55a5; + imm32 r7, 0x8666ab77; + R0.H = R7 - R0 (RND12); + R1.H = R7 - R1 (RND12); + R2.H = R7 - R2 (RND12); + R3.H = R7 - R3 (RND12); + R4.H = R7 - R4 (RND12); + R5.H = R7 - R5 (RND12); + R6.H = R7 - R6 (RND12); + R7.H = R7 - R7 (RND12); + CHECKREG r0, 0x80008051; + CHECKREG r1, 0x8000A26D; + CHECKREG r2, 0x800055F5; + CHECKREG r3, 0x80007717; + CHECKREG r4, 0x800089BB; + CHECKREG r5, 0x8000AB1D; + CHECKREG r6, 0x800055A5; + CHECKREG r7, 0x0000AB77; + + imm32 r0, 0x15678901; + imm32 r1, 0x2789abad; + imm32 r2, 0x34445515; + imm32 r3, 0x466677d7; + imm32 r4, 0x5678891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445535; + imm32 r7, 0x86667747; + R6.H = R2 - R3 (RND12); + R1.H = R4 - R5 (RND12); + R5.H = R7 - R2 (RND12); + R3.H = R0 - R0 (RND12); + R0.H = R3 - R4 (RND12); + R2.H = R5 - R7 (RND12); + R7.H = R6 - R7 (RND12); + R4.H = R1 - R6 (RND12); + CHECKREG r0, 0x80008901; + CHECKREG r1, 0x8000ABAD; + CHECKREG r2, 0x99a35515; + CHECKREG r3, 0x000077D7; + CHECKREG r4, 0x0005891B; + CHECKREG r5, 0x8000AB1D; + CHECKREG r6, 0x80005535; + CHECKREG r7, 0x999e7747; + + imm32 r0, 0x15678121; + imm32 r1, 0x2789ab3d; + imm32 r2, 0x34445565; + imm32 r3, 0x4d667797; + imm32 r4, 0x567889ab; + imm32 r5, 0x67beabbd; + imm32 r6, 0x7b445515; + imm32 r7, 0x86d6e777; + R3.H = R4 - R0 (RND12); + R1.H = R6 - R3 (RND12); + R4.H = R3 - R2 (RND12); + R6.H = R7 - R1 (RND12); + R2.H = R5 - R4 (RND12); + R7.H = R2 - R7 (RND12); + R0.H = R1 - R6 (RND12); + R5.H = R0 - R5 (RND12); + CHECKREG r0, 0x7fff8121; + CHECKREG r1, 0xb44eAB3D; + CHECKREG r2, 0x80005565; + CHECKREG r3, 0x7fff7797; + CHECKREG r4, 0x7fff89AB; + CHECKREG r5, 0x7fffABBD; + CHECKREG r6, 0x80005515; + CHECKREG r7, 0x9297E777; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_p.s b/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_p.s new file mode 100644 index 0000000..fe54a86 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_p.s @@ -0,0 +1,262 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_p/c_dsp32alu_rh_rnd12_p.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + + imm32 r0, 0x45678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xf4445515; + imm32 r3, 0x46667717; + imm32 r4, 0xe678891b; + imm32 r5, 0x6f89ab1d; + imm32 r6, 0x7444d515; + imm32 r7, 0x8666b777; + R0.H = R0 + R0 (RND12); + R1.H = R0 + R1 (RND12); + R2.H = R0 + R2 (RND12); + R3.H = R0 + R3 (RND12); + R4.H = R0 + R4 (RND12); + R5.H = R0 + R5 (RND12); + R6.H = R0 + R6 (RND12); + R7.H = R0 + R7 (RND12); + CHECKREG r0, 0x7FFF8911; + CHECKREG r1, 0x7fffAB1D; + CHECKREG r2, 0x7fff5515; + CHECKREG r3, 0x7fff7717; + CHECKREG r4, 0x7fff891B; + CHECKREG r5, 0x7fffAB1D; + CHECKREG r6, 0x7fffD515; + CHECKREG r7, 0x6664B777; + + imm32 r0, 0xd5678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xa4445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5b78891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74e45515; + imm32 r7, 0x86a6b777; + R0.H = R1 + R0 (RND12); + R1.H = R1 + R1 (RND12); + R2.H = R1 + R2 (RND12); + R3.H = R1 + R3 (RND12); + R4.H = R1 + R4 (RND12); + R5.H = R1 + R5 (RND12); + R6.H = R1 + R6 (RND12); + R7.H = R1 + R7 (RND12); + CHECKREG r0, 0xcf138911; + CHECKREG r1, 0x7FFFAB1D; + CHECKREG r2, 0x7fff5515; + CHECKREG r3, 0x7fff7717; + CHECKREG r4, 0x7fff891B; + CHECKREG r5, 0x7fffAB1D; + CHECKREG r6, 0x7fff5515; + CHECKREG r7, 0x6A66B777; + + imm32 r0, 0xa5678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xb4445515; + imm32 r3, 0x46667717; + imm32 r4, 0xd678891b; + imm32 r5, 0x6e89ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86967777; + R0.H = R2 + R0 (RND12); + R1.H = R2 + R1 (RND12); + R2.H = R2 + R2 (RND12); + R3.H = R2 + R3 (RND12); + R4.H = R2 + R4 (RND12); + R5.H = R2 + R5 (RND12); + R6.H = R2 + R6 (RND12); + R7.H = R2 + R7 (RND12); + CHECKREG r4, 0x8000891B; + CHECKREG r5, 0x8000AB1D; + CHECKREG r6, 0x80005515; + CHECKREG r7, 0x80007777; + CHECKREG r4, 0x8000891B; + CHECKREG r5, 0x8000AB1D; + CHECKREG r6, 0x80005515; + CHECKREG r7, 0x80007777; + + imm32 r0, 0x35678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0xd4445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5678891b; + imm32 r5, 0xeab9ab1d; + imm32 r6, 0x744e5515; + imm32 r7, 0x866e777f; + R0.H = R3 + R0 (RND12); + R1.H = R3 + R1 (RND12); + R2.H = R3 + R2 (RND12); + R3.H = R3 + R3 (RND12); + R4.H = R3 + R4 (RND12); + R5.H = R3 + R5 (RND12); + R6.H = R3 + R6 (RND12); + R7.H = R3 + R7 (RND12); + CHECKREG r0, 0x7FFF8911; + CHECKREG r1, 0x7FFFAB1D; + CHECKREG r2, 0x7FFF5515; + CHECKREG r3, 0x7FFF7717; + CHECKREG r4, 0x7fff891B; + CHECKREG r5, 0x7fffAB1D; + CHECKREG r6, 0x7fff5515; + CHECKREG r7, 0x66df777F; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34e45515; + imm32 r3, 0xd6667717; + imm32 r4, 0x5675891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0xa4465515; + imm32 r7, 0x8b66e777; + R0.H = R4 + R0 (RND12); + R1.H = R4 + R1 (RND12); + R2.H = R4 + R2 (RND12); + R3.H = R4 + R3 (RND12); + R4.H = R4 + R4 (RND12); + R5.H = R4 + R5 (RND12); + R6.H = R4 + R6 (RND12); + R7.H = R4 + R7 (RND12); + CHECKREG r0, 0x7FFF8911; + CHECKREG r1, 0x7FFFAB1D; + CHECKREG r2, 0x7FFF5515; + CHECKREG r3, 0x7FFF7717; + CHECKREG r4, 0x7FFF891B; + CHECKREG r5, 0x7fffAB1D; + CHECKREG r6, 0x7fff5515; + CHECKREG r7, 0x7fffE777; + + imm32 r0, 0x35678111; + imm32 r1, 0x2789a21d; + imm32 r2, 0x3e445535; + imm32 r3, 0x46667757; + imm32 r4, 0xe6f8891b; + imm32 r5, 0x6789db7d; + imm32 r6, 0xf44a5595; + imm32 r7, 0x866b7770; + R0.H = R5 + R0 (RND12); + R1.H = R5 + R1 (RND12); + R2.H = R5 + R2 (RND12); + R3.H = R5 + R3 (RND12); + R4.H = R5 + R4 (RND12); + R5.H = R5 + R5 (RND12); + R6.H = R5 + R6 (RND12); + R7.H = R5 + R7 (RND12); + CHECKREG r0, 0x7FFF8111; + CHECKREG r1, 0x7FFFA21D; + CHECKREG r2, 0x7fff5535; + CHECKREG r3, 0x7FFF7757; + CHECKREG r4, 0x7FFF891B; + CHECKREG r5, 0x7FFFDB7D; + CHECKREG r6, 0x7fff5595; + CHECKREG r7, 0x66b57770; + + imm32 r0, 0xb5678911; + imm32 r1, 0xc789ab1d; + imm32 r2, 0x3ab45515; + imm32 r3, 0x466b7717; + imm32 r4, 0x4678e91b; + imm32 r5, 0x6789af1d; + imm32 r6, 0xf4445515; + imm32 r7, 0x86e6f777; + R0.H = R6 + R0 (RND12); + R1.H = R6 + R1 (RND12); + R2.H = R6 + R2 (RND12); + R3.H = R6 + R3 (RND12); + R4.H = R6 + R4 (RND12); + R5.H = R6 + R5 (RND12); + R6.H = R6 + R6 (RND12); + R7.H = R6 + R7 (RND12); + CHECKREG r0, 0x80008911; + CHECKREG r1, 0x8000AB1D; + CHECKREG r2, 0x7fff5515; + CHECKREG r3, 0x7FFF7717; + CHECKREG r4, 0x7FFFE91B; + CHECKREG r5, 0x7FFFAF1D; + CHECKREG r6, 0x80005515; + CHECKREG r7, 0x8000F777; + + imm32 r0, 0xab678021; + imm32 r1, 0x2c89a33d; + imm32 r2, 0x34d45575; + imm32 r3, 0x466e7797; + imm32 r4, 0x567f89fb; + imm32 r5, 0x6789abdd; + imm32 r6, 0x744e5515; + imm32 r7, 0x8666ab87; + R0.H = R7 + R0 (RND12); + R1.H = R7 + R1 (RND12); + R2.H = R7 + R2 (RND12); + R3.H = R7 + R3 (RND12); + R4.H = R7 + R4 (RND12); + R5.H = R7 + R5 (RND12); + R6.H = R7 + R6 (RND12); + R7.H = R7 + R7 (RND12); + CHECKREG r0, 0x80008021; + CHECKREG r1, 0x8000A33D; + CHECKREG r2, 0x80005575; + CHECKREG r3, 0x80007797; + CHECKREG r4, 0x800089FB; + CHECKREG r5, 0x8000ABDD; + CHECKREG r6, 0xab505515; + CHECKREG r7, 0x8000AB87; + + imm32 r0, 0x15678901; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445535; + imm32 r3, 0x46667747; + imm32 r4, 0x56788915; + imm32 r5, 0x6789ab6d; + imm32 r6, 0x74445518; + imm32 r7, 0x86667797; + R6.H = R2 + R3 (RND12); + R1.H = R4 + R5 (RND12); + R5.H = R7 + R2 (RND12); + R3.H = R0 + R0 (RND12); + R0.H = R3 + R4 (RND12); + R2.H = R5 + R7 (RND12); + R7.H = R6 + R7 (RND12); + R4.H = R1 + R6 (RND12); + CHECKREG r0, 0x7fff8901; + CHECKREG r1, 0x7FFFAB2D; + CHECKREG r2, 0x80005535; + CHECKREG r3, 0x7FFF7747; + CHECKREG r4, 0x7fff8915; + CHECKREG r5, 0x8000AB6D; + CHECKREG r6, 0x7FFF5518; + CHECKREG r7, 0x665D7797; + + imm32 r0, 0x35678911; + imm32 r1, 0x2489ab1d; + imm32 r2, 0x34545565; + imm32 r3, 0x4d6677b7; + imm32 r4, 0x567889db; + imm32 r5, 0x67beab1d; + imm32 r6, 0x7b445595; + imm32 r7, 0x86d6e707; + R3.H = R4 + R0 (RND12); + R1.H = R6 + R3 (RND12); + R4.H = R3 + R2 (RND12); + R6.H = R7 + R1 (RND12); + R2.H = R5 + R4 (RND12); + R7.H = R2 + R7 (RND12); + R0.H = R1 + R6 (RND12); + R5.H = R0 + R5 (RND12); + CHECKREG r0, 0x7fff8911; + CHECKREG r1, 0x7fffAB1D; + CHECKREG r2, 0x7FFF5565; + CHECKREG r3, 0x7FFF77B7; + CHECKREG r4, 0x7fff89DB; + CHECKREG r5, 0x7FFFAB1D; + CHECKREG r6, 0x6d695595; + CHECKREG r7, 0x6D64E707; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_m.s b/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_m.s new file mode 100644 index 0000000..8283394 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_m.s @@ -0,0 +1,258 @@ +//Original:/testcases/core/c_dsp32alu_rh_rnd20_m/c_dsp32alu_rh_rnd20_m.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34a45515; +imm32 r3, 0x46a67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678aab1d; +imm32 r6, 0x7444a515; +imm32 r7, 0x86667a77; +R0.H = R0 - R0 (RND20); +R1.H = R0 - R1 (RND20); +R2.H = R0 - R2 (RND20); +R3.H = R0 - R3 (RND20); +R4.H = R0 - R4 (RND20); +R5.H = R0 - R5 (RND20); +R6.H = R0 - R6 (RND20); +R7.H = R0 - R7 (RND20); +CHECKREG r0, 0x00008911; +CHECKREG r1, 0xFD57AB1D; +CHECKREG r2, 0xFCB65515; +CHECKREG r3, 0xFB967717; +CHECKREG r4, 0xFA98891B; +CHECKREG r5, 0xF987AB1D; +CHECKREG r6, 0xF8BCA515; +CHECKREG r7, 0x079A7A77; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0xb4445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5b78891b; +imm32 r5, 0x67bbab1d; +imm32 r6, 0x7444b515; +imm32 r7, 0x86667b77; +R0.H = R1 - R0 (RND20); +R1.H = R1 - R1 (RND20); +R2.H = R1 - R2 (RND20); +R3.H = R1 - R3 (RND20); +R4.H = R1 - R4 (RND20); +R5.H = R1 - R5 (RND20); +R6.H = R1 - R6 (RND20); +R7.H = R1 - R7 (RND20); +CHECKREG r0, 0x08228911; +CHECKREG r1, 0x0000AB1D; +CHECKREG r2, 0x04BC5515; +CHECKREG r3, 0xFB9A7717; +CHECKREG r4, 0xFA49891B; +CHECKREG r5, 0xF984AB1D; +CHECKREG r6, 0xF8BCB515; +CHECKREG r7, 0x079A7B77; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x3a445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x567a891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445a15; +imm32 r7, 0x866677a7; +R0.H = R2 - R0 (RND20); +R1.H = R2 - R1 (RND20); +R2.H = R2 - R2 (RND20); +R3.H = R2 - R3 (RND20); +R4.H = R2 - R4 (RND20); +R5.H = R2 - R5 (RND20); +R6.H = R2 - R6 (RND20); +R7.H = R2 - R7 (RND20); +CHECKREG r0, 0x094E8911; +CHECKREG r1, 0x00FCAB1D; +CHECKREG r2, 0x00005515; +CHECKREG r3, 0xFB967717; +CHECKREG r4, 0xFA98891B; +CHECKREG r5, 0xF987AB1D; +CHECKREG r6, 0xF8BC5A15; +CHECKREG r7, 0x079A77A7; + +imm32 r0, 0xb5678911; +imm32 r1, 0xb789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678ddb1d; +imm32 r6, 0x74445d15; +imm32 r7, 0x866677d7; +R0.H = R3 - R0 (RND20); +R1.H = R3 - R1 (RND20); +R2.H = R3 - R2 (RND20); +R3.H = R3 - R3 (RND20); +R4.H = R3 - R4 (RND20); +R5.H = R3 - R5 (RND20); +R6.H = R3 - R6 (RND20); +R7.H = R3 - R7 (RND20); +CHECKREG r0, 0x09178911; +CHECKREG r1, 0x08F5AB1D; +CHECKREG r2, 0x00995515; +CHECKREG r3, 0x00007717; +CHECKREG r4, 0xFA98891B; +CHECKREG r5, 0xF987DB1D; +CHECKREG r6, 0xF8BC5D15; +CHECKREG r7, 0x079A77D7; + +imm32 r0, 0xd5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0xd4445515; +imm32 r3, 0xd6667717; +imm32 r4, 0x5d78891b; +imm32 r5, 0x67d9ab1d; +imm32 r6, 0x744d5515; +imm32 r7, 0x8666dd77; +R0.H = R4 - R0 (RND20); +R1.H = R4 - R1 (RND20); +R2.H = R4 - R2 (RND20); +R3.H = R4 - R3 (RND20); +R4.H = R4 - R4 (RND20); +R5.H = R4 - R5 (RND20); +R6.H = R4 - R6 (RND20); +R7.H = R4 - R7 (RND20); +CHECKREG r0, 0x08818911; +CHECKREG r1, 0x035FAB1D; +CHECKREG r2, 0x08935515; +CHECKREG r3, 0x08717717; +CHECKREG r4, 0x0000891B; +CHECKREG r5, 0xF982AB1D; +CHECKREG r6, 0xF8BB5515; +CHECKREG r7, 0x079ADD77; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34d45515; +imm32 r3, 0x46667717; +imm32 r4, 0x567d891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x74445d15; +imm32 r7, 0x866677d7; +R0.H = R5 - R0 (RND20); +R1.H = R5 - R1 (RND20); +R2.H = R5 - R2 (RND20); +R3.H = R5 - R3 (RND20); +R4.H = R5 - R4 (RND20); +R5.H = R5 - R5 (RND20); +R6.H = R5 - R6 (RND20); +R7.H = R5 - R7 (RND20); +CHECKREG r0, 0x08228911; +CHECKREG r1, 0x0390AB1D; +CHECKREG r2, 0x032B5515; +CHECKREG r3, 0x02127717; +CHECKREG r4, 0x0111891B; +CHECKREG r5, 0x0000DB1D; +CHECKREG r6, 0xF8BC5D15; +CHECKREG r7, 0x079A77D7; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34a45515; +imm32 r3, 0x46a67717; +imm32 r4, 0x56a8891b; +imm32 r5, 0x678aab1d; +imm32 r6, 0x7444a515; +imm32 r7, 0x86667a77; +R0.H = R6 - R0 (RND20); +R1.H = R6 - R1 (RND20); +R2.H = R6 - R2 (RND20); +R3.H = R6 - R3 (RND20); +R4.H = R6 - R4 (RND20); +R5.H = R6 - R5 (RND20); +R6.H = R6 - R6 (RND20); +R7.H = R6 - R7 (RND20); +CHECKREG r0, 0x0CEE8911; +CHECKREG r1, 0x049CAB1D; +CHECKREG r2, 0x03FA5515; +CHECKREG r3, 0x02DA7717; +CHECKREG r4, 0x01DA891B; +CHECKREG r5, 0x00CCAB1D; +CHECKREG r6, 0x0000A515; +CHECKREG r7, 0x079A7A77; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.H = R7 - R0 (RND20); +R1.H = R7 - R1 (RND20); +R2.H = R7 - R2 (RND20); +R3.H = R7 - R3 (RND20); +R4.H = R7 - R4 (RND20); +R5.H = R7 - R5 (RND20); +R6.H = R7 - R6 (RND20); +R7.H = R7 - R7 (RND20); +CHECKREG r0, 0xF7108911; +CHECKREG r1, 0xF5EEAB1D; +CHECKREG r2, 0xF5225515; +CHECKREG r3, 0xF4007717; +CHECKREG r4, 0xF2FF891B; +CHECKREG r5, 0xF1EEAB1D; +CHECKREG r6, 0xF1225515; +CHECKREG r7, 0x00007777; + +imm32 r0, 0xe5678911; +imm32 r1, 0xe789ab1d; +imm32 r2, 0xe4445515; +imm32 r3, 0x4ee67717; +imm32 r4, 0x567e891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444e515; +imm32 r7, 0x86667e77; +R6.H = R2 - R3 (RND20); +R1.H = R4 - R5 (RND20); +R5.H = R7 - R2 (RND20); +R3.H = R0 - R0 (RND20); +R0.H = R3 - R4 (RND20); +R2.H = R5 - R7 (RND20); +R7.H = R6 - R7 (RND20); +R4.H = R1 - R6 (RND20); +CHECKREG r0, 0xFA988911; +CHECKREG r1, 0xFEEFAB1D; +CHECKREG r2, 0x073C5515; +CHECKREG r3, 0x00007717; +CHECKREG r4, 0x005A891B; +CHECKREG r5, 0xFA22AB1D; +CHECKREG r6, 0xF956E515; +CHECKREG r7, 0x072F7E77; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x567d891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R3.H = R4 - R0 (RND20); +R1.H = R6 - R3 (RND20); +R4.H = R3 - R2 (RND20); +R6.H = R7 - R1 (RND20); +R2.H = R5 - R4 (RND20); +R7.H = R2 - R7 (RND20); +R0.H = R1 - R6 (RND20); +R5.H = R0 - R5 (RND20); +CHECKREG r0, 0x00EE8911; +CHECKREG r1, 0x06D3AB1D; +CHECKREG r2, 0x06AF5515; +CHECKREG r3, 0x07117717; +CHECKREG r4, 0xFC9D891B; +CHECKREG r5, 0xF996DB1D; +CHECKREG r6, 0xF7F9D515; +CHECKREG r7, 0x08057D77; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_p.s b/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_p.s new file mode 100644 index 0000000..231db02 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_p.s @@ -0,0 +1,258 @@ +//Original:/testcases/core/c_dsp32alu_rh_rnd20_p/c_dsp32alu_rh_rnd20_p.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34a45515; +imm32 r3, 0x46a67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678aab1d; +imm32 r6, 0x7444a515; +imm32 r7, 0x86667a77; +R0.H = R0 + R0 (RND20); +R1.H = R0 + R1 (RND20); +R2.H = R0 + R2 (RND20); +R3.H = R0 + R3 (RND20); +R4.H = R0 + R4 (RND20); +R5.H = R0 + R5 (RND20); +R6.H = R0 + R6 (RND20); +R7.H = R0 + R7 (RND20); +CHECKREG r0, 0xF4AD8911; +CHECKREG r1, 0x01F3AB1D; +CHECKREG r2, 0x02955515; +CHECKREG r3, 0x03B57717; +CHECKREG r4, 0x04B2891B; +CHECKREG r5, 0x05C4AB1D; +CHECKREG r6, 0x068FA515; +CHECKREG r7, 0xF7B17A77; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0xb4445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5b78891b; +imm32 r5, 0x67bbab1d; +imm32 r6, 0x7444b515; +imm32 r7, 0x86667b77; +R0.H = R1 + R0 (RND20); +R1.H = R1 + R1 (RND20); +R2.H = R1 + R2 (RND20); +R3.H = R1 + R3 (RND20); +R4.H = R1 + R4 (RND20); +R5.H = R1 + R5 (RND20); +R6.H = R1 + R6 (RND20); +R7.H = R1 + R7 (RND20); +CHECKREG r0, 0xFCCF8911; +CHECKREG r1, 0x04F1AB1D; +CHECKREG r2, 0xFB935515; +CHECKREG r3, 0x04B67717; +CHECKREG r4, 0x0607891B; +CHECKREG r5, 0x06CBAB1D; +CHECKREG r6, 0x0793B515; +CHECKREG r7, 0xF8B67B77; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x3a445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x567a891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445a15; +imm32 r7, 0x866677a7; +R0.H = R2 + R0 (RND20); +R1.H = R2 + R1 (RND20); +R2.H = R2 + R2 (RND20); +R3.H = R2 + R3 (RND20); +R4.H = R2 + R4 (RND20); +R5.H = R2 + R5 (RND20); +R6.H = R2 + R6 (RND20); +R7.H = R2 + R7 (RND20); +CHECKREG r0, 0xFDFB8911; +CHECKREG r1, 0x064DAB1D; +CHECKREG r2, 0x07495515; +CHECKREG r3, 0x04DF7717; +CHECKREG r4, 0x05DC891B; +CHECKREG r5, 0x06EDAB1D; +CHECKREG r6, 0x07B95A15; +CHECKREG r7, 0xF8DB77A7; + +imm32 r0, 0xb5678911; +imm32 r1, 0xb789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678ddb1d; +imm32 r6, 0x74445d15; +imm32 r7, 0x866677d7; +R0.H = R3 + R0 (RND20); +R1.H = R3 + R1 (RND20); +R2.H = R3 + R2 (RND20); +R3.H = R3 + R3 (RND20); +R4.H = R3 + R4 (RND20); +R5.H = R3 + R5 (RND20); +R6.H = R3 + R6 (RND20); +R7.H = R3 + R7 (RND20); +CHECKREG r0, 0xFFC48911; +CHECKREG r1, 0xFFE6AB1D; +CHECKREG r2, 0x08425515; +CHECKREG r3, 0x08DB7717; +CHECKREG r4, 0x05F5891B; +CHECKREG r5, 0x0707DB1D; +CHECKREG r6, 0x07D25D15; +CHECKREG r7, 0xF8F477D7; + +imm32 r0, 0xd5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0xd4445515; +imm32 r3, 0xd6667717; +imm32 r4, 0x5d78891b; +imm32 r5, 0x67d9ab1d; +imm32 r6, 0x744d5515; +imm32 r7, 0x8666dd77; +R0.H = R4 + R0 (RND20); +R1.H = R4 + R1 (RND20); +R2.H = R4 + R2 (RND20); +R3.H = R4 + R3 (RND20); +R4.H = R4 + R4 (RND20); +R5.H = R4 + R5 (RND20); +R6.H = R4 + R6 (RND20); +R7.H = R4 + R7 (RND20); +CHECKREG r0, 0x032E8911; +CHECKREG r1, 0x0850AB1D; +CHECKREG r2, 0x031C5515; +CHECKREG r3, 0x033E7717; +CHECKREG r4, 0x0BAF891B; +CHECKREG r5, 0x0739AB1D; +CHECKREG r6, 0x08005515; +CHECKREG r7, 0xF921DD77; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34d45515; +imm32 r3, 0x46667717; +imm32 r4, 0x567d891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x74445d15; +imm32 r7, 0x866677d7; +R0.H = R5 + R0 (RND20); +R1.H = R5 + R1 (RND20); +R2.H = R5 + R2 (RND20); +R3.H = R5 + R3 (RND20); +R4.H = R5 + R4 (RND20); +R5.H = R5 + R5 (RND20); +R6.H = R5 + R6 (RND20); +R7.H = R5 + R7 (RND20); +CHECKREG r0, 0x04CF8911; +CHECKREG r1, 0x0961AB1D; +CHECKREG r2, 0x09C65515; +CHECKREG r3, 0x0ADF7717; +CHECKREG r4, 0x0BE0891B; +CHECKREG r5, 0x0CF1DB1D; +CHECKREG r6, 0x08135D15; +CHECKREG r7, 0xF93677D7; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34a45515; +imm32 r3, 0x46a67717; +imm32 r4, 0x56a8891b; +imm32 r5, 0x678aab1d; +imm32 r6, 0x7444a515; +imm32 r7, 0x86667a77; +R0.H = R6 + R0 (RND20); +R1.H = R6 + R1 (RND20); +R2.H = R6 + R2 (RND20); +R3.H = R6 + R3 (RND20); +R4.H = R6 + R4 (RND20); +R5.H = R6 + R5 (RND20); +R6.H = R6 + R6 (RND20); +R7.H = R6 + R7 (RND20); +CHECKREG r0, 0x019B8911; +CHECKREG r1, 0x09EDAB1D; +CHECKREG r2, 0x0A8F5515; +CHECKREG r3, 0x0BAF7717; +CHECKREG r4, 0x0CAF891B; +CHECKREG r5, 0x0DBDAB1D; +CHECKREG r6, 0x0E89A515; +CHECKREG r7, 0xF94F7A77; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.H = R7 + R0 (RND20); +R1.H = R7 + R1 (RND20); +R2.H = R7 + R2 (RND20); +R3.H = R7 + R3 (RND20); +R4.H = R7 + R4 (RND20); +R5.H = R7 + R5 (RND20); +R6.H = R7 + R6 (RND20); +R7.H = R7 + R7 (RND20); +CHECKREG r0, 0xF9BD8911; +CHECKREG r1, 0xFADFAB1D; +CHECKREG r2, 0xFBAB5515; +CHECKREG r3, 0xFCCD7717; +CHECKREG r4, 0xFDCE891B; +CHECKREG r5, 0xFEDFAB1D; +CHECKREG r6, 0xFFAB5515; +CHECKREG r7, 0xF0CD7777; + +imm32 r0, 0xe5678911; +imm32 r1, 0xe789ab1d; +imm32 r2, 0xe4445515; +imm32 r3, 0x4ee67717; +imm32 r4, 0x567e891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444e515; +imm32 r7, 0x86667e77; +R6.H = R2 + R3 (RND20); +R1.H = R4 + R5 (RND20); +R5.H = R7 + R2 (RND20); +R3.H = R0 + R0 (RND20); +R0.H = R3 + R4 (RND20); +R2.H = R5 + R7 (RND20); +R7.H = R6 + R7 (RND20); +R4.H = R1 + R6 (RND20); +CHECKREG r0, 0x05338911; +CHECKREG r1, 0x0BE1AB1D; +CHECKREG r2, 0xF7D15515; +CHECKREG r3, 0xFCAD7717; +CHECKREG r4, 0x00F1891B; +CHECKREG r5, 0xF6ABAB1D; +CHECKREG r6, 0x0333E515; +CHECKREG r7, 0xF89A7E77; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x567d891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R3.H = R4 + R0 (RND20); +R1.H = R6 + R3 (RND20); +R4.H = R3 + R2 (RND20); +R6.H = R7 + R1 (RND20); +R2.H = R5 + R4 (RND20); +R7.H = R2 + R7 (RND20); +R0.H = R1 + R6 (RND20); +R5.H = R0 + R5 (RND20); +CHECKREG r0, 0x00068911; +CHECKREG r1, 0x0780AB1D; +CHECKREG r2, 0x06BA5515; +CHECKREG r3, 0x03BE7717; +CHECKREG r4, 0x0410891B; +CHECKREG r5, 0x0679DB1D; +CHECKREG r6, 0xF8DED515; +CHECKREG r7, 0xF8D27D77; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rl_m.s b/sim/testsuite/sim/bfin/c_dsp32alu_rl_m.s new file mode 100644 index 0000000..d942d91 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rl_m.s @@ -0,0 +1,263 @@ +//Original:/testcases/core/c_dsp32alu_rl_m/c_dsp32alu_rl_m.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x55678911; +imm32 r1, 0x2759ab1d; +imm32 r2, 0x34455515; +imm32 r3, 0x46665717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789a51d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R0.L - R0.L (NS); +R1.L = R0.L - R1.H (NS); +R2.L = R0.H - R2.L (NS); +R3.L = R0.H - R3.H (NS); +R4.L = R0.L - R4.L (NS); +R5.L = R0.L - R5.H (NS); +R6.L = R0.H - R6.L (NS); +R7.L = R0.H - R7.H (NS); +CHECKREG r4, 0x567876E5; +CHECKREG r5, 0x67899877; +CHECKREG r6, 0x74440052; +CHECKREG r7, 0x8666CF01; +CHECKREG r4, 0x567876E5; +CHECKREG r5, 0x67899877; +CHECKREG r6, 0x74440052; +CHECKREG r7, 0x8666CF01; + +imm32 r0, 0x44678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x344d5515; +imm32 r3, 0x4666d717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789cc1d; +imm32 r6, 0x74445c15; +imm32 r7, 0x86667c77; +R0.L = R1.L - R0.L (NS); +R1.L = R1.L - R1.H (NS); +R2.L = R1.H - R2.L (NS); +R3.L = R1.H - R3.H (NS); +R4.L = R1.L - R4.L (NS); +R5.L = R1.L - R5.H (NS); +R6.L = R1.H - R6.L (NS); +R7.L = R1.H - R7.H (NS); +CHECKREG r4, 0x5678FA79; +CHECKREG r5, 0x67891C0B; +CHECKREG r6, 0x7444CB74; +CHECKREG r7, 0x8666A123; +CHECKREG r4, 0x5678FA79; +CHECKREG r5, 0x67891C0B; +CHECKREG r6, 0x7444CB74; +CHECKREG r7, 0x8666A123; + +imm32 r0, 0xcc678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34c45515; +imm32 r3, 0x466c7717; +imm32 r4, 0x5678c91b; +imm32 r5, 0x6789ac1d; +imm32 r6, 0x74445515; +imm32 r7, 0x866677c7; +R0.L = R2.L - R0.L (NS); +R1.L = R2.L - R1.H (NS); +R2.L = R2.H - R2.L (NS); +R3.L = R2.H - R3.H (NS); +R4.L = R2.L - R4.L (NS); +R5.L = R2.L - R5.H (NS); +R6.L = R2.H - R6.L (NS); +R7.L = R2.H - R7.H (NS); +CHECKREG r4, 0x56781694; +CHECKREG r5, 0x67897826; +CHECKREG r6, 0x7444DFAF; +CHECKREG r7, 0x8666AE5E; +CHECKREG r4, 0x56781694; +CHECKREG r5, 0x67897826; +CHECKREG r6, 0x7444DFAF; +CHECKREG r7, 0x8666AE5E; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R3.L - R0.L (NS); +R1.L = R3.L - R1.H (NS); +R2.L = R3.H - R2.L (NS); +R3.L = R3.H - R3.H (NS); +R4.L = R3.L - R4.L (NS); +R5.L = R3.L - R5.H (NS); +R6.L = R3.H - R6.L (NS); +R7.L = R3.H - R7.H (NS); +CHECKREG r4, 0x567876E5; +CHECKREG r5, 0x67899877; +CHECKREG r6, 0x7444F151; +CHECKREG r7, 0x8666C000; +CHECKREG r4, 0x567876E5; +CHECKREG r5, 0x67899877; +CHECKREG r6, 0x7444F151; +CHECKREG r7, 0x8666C000; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34e45515; +imm32 r3, 0x466e7717; +imm32 r4, 0x5678e91b; +imm32 r5, 0x6789ae1d; +imm32 r6, 0x744455e5; +imm32 r7, 0x8666777e; +R0.L = R4.L - R0.L (NS); +R1.L = R4.L - R1.H (NS); +R2.L = R4.H - R2.L (NS); +R3.L = R4.H - R3.H (NS); +R4.L = R4.L - R4.L (NS); +R5.L = R4.L - R5.H (NS); +R6.L = R4.H - R6.L (NS); +R7.L = R4.H - R7.H (NS); +CHECKREG r4, 0x56780000; +CHECKREG r5, 0x67899877; +CHECKREG r6, 0x74440093; +CHECKREG r7, 0x8666D012; +CHECKREG r4, 0x56780000; +CHECKREG r5, 0x67899877; +CHECKREG r6, 0x74440093; +CHECKREG r7, 0x8666D012; + +imm32 r0, 0xdd678911; +imm32 r1, 0xd789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x567d891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x74445d15; +imm32 r7, 0x866677d7; +R0.L = R5.L - R0.L (NS); +R1.L = R5.L - R1.H (NS); +R2.L = R5.H - R2.L (NS); +R3.L = R5.H - R3.H (NS); +R4.L = R5.L - R4.L (NS); +R5.L = R5.L - R5.H (NS); +R6.L = R5.H - R6.L (NS); +R7.L = R5.H - R7.H (NS); +CHECKREG r4, 0x567D5202; +CHECKREG r5, 0x67897394; +CHECKREG r6, 0x74440A74; +CHECKREG r7, 0x8666E123; +CHECKREG r4, 0x567D5202; +CHECKREG r5, 0x67897394; +CHECKREG r6, 0x74440A74; +CHECKREG r7, 0x8666E123; + +imm32 r0, 0x85678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x38445515; +imm32 r3, 0x46667717; +imm32 r4, 0x568a891b; +imm32 r5, 0x67a9ab1d; +imm32 r6, 0x744a5515; +imm32 r7, 0x8666aa77; +R0.L = R6.L - R0.L (NS); +R1.L = R6.L - R1.H (NS); +R2.L = R6.H - R2.L (NS); +R3.L = R6.H - R3.H (NS); +R4.L = R6.L - R4.L (NS); +R5.L = R6.L - R5.H (NS); +R6.L = R6.H - R6.L (NS); +R7.L = R6.H - R7.H (NS); +CHECKREG r4, 0x568ACBFA; +CHECKREG r5, 0x67A9ED6C; +CHECKREG r6, 0x744A1F35; +CHECKREG r7, 0x8666EDE4; +CHECKREG r4, 0x568ACBFA; +CHECKREG r5, 0x67A9ED6C; +CHECKREG r6, 0x744A1F35; +CHECKREG r7, 0x8666EDE4; + +imm32 r0, 0x35678911; +imm32 r1, 0x2389ab1d; +imm32 r2, 0x34845515; +imm32 r3, 0x466a7717; +imm32 r4, 0x5678a91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445b15; +imm32 r7, 0x866677b7; +R0.L = R7.L - R0.L (NS); +R1.L = R7.L - R1.H (NS); +R2.L = R7.H - R2.L (NS); +R3.L = R7.H - R3.H (NS); +R4.L = R7.L - R4.L (NS); +R5.L = R7.L - R5.H (NS); +R6.L = R7.H - R6.L (NS); +R7.L = R7.H - R7.H (NS); +CHECKREG r4, 0x5678CE9C; +CHECKREG r5, 0x6789102E; +CHECKREG r6, 0x74442B51; +CHECKREG r7, 0x86660000; +CHECKREG r4, 0x5678CE9C; +CHECKREG r5, 0x6789102E; +CHECKREG r6, 0x74442B51; +CHECKREG r7, 0x86660000; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R6.L = R2.L - R3.L (S); +R1.L = R4.L - R5.H (S); +R5.L = R7.H - R2.L (S); +R3.L = R0.H - R0.H (S); +R0.L = R3.L - R4.L (S); +R2.L = R5.L - R7.H (S); +R7.L = R6.H - R7.L (S); +R4.L = R1.H - R6.H (S); +CHECKREG r4, 0x5678B345; +CHECKREG r5, 0x67898000; +CHECKREG r6, 0x7444DDFE; +CHECKREG r7, 0x8666FCCD; +CHECKREG r4, 0x5678B345; +CHECKREG r5, 0x67898000; +CHECKREG r6, 0x7444DDFE; +CHECKREG r7, 0x8666FCCD; + +imm32 r0, 0x1d678911; +imm32 r1, 0x27d9ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x466d7717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789dd1d; +imm32 r6, 0x74445515; +imm32 r7, 0x866677d7; +R3.L = R4.L - R0.L (S); +R1.L = R6.L - R3.H (S); +R4.L = R3.H - R2.L (S); +R6.L = R7.H - R1.H (S); +R2.L = R5.L - R4.L (S); +R7.L = R2.L - R7.H (S); +R0.L = R1.H - R6.L (S); +R5.L = R0.H - R5.H (S); +CHECKREG r4, 0x5678F158; +CHECKREG r5, 0x6789B5DE; +CHECKREG r6, 0x74448000; +CHECKREG r7, 0x8666655F; +CHECKREG r4, 0x5678F158; +CHECKREG r5, 0x6789B5DE; +CHECKREG r6, 0x74448000; +CHECKREG r7, 0x8666655F; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rl_p.s b/sim/testsuite/sim/bfin/c_dsp32alu_rl_p.s new file mode 100644 index 0000000..3c037bd --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rl_p.s @@ -0,0 +1,263 @@ +//Original:/testcases/core/c_dsp32alu_rl_p/c_dsp32alu_rl_p.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x19678911; +imm32 r1, 0x2799ab1d; +imm32 r2, 0x34945515; +imm32 r3, 0x46967717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86669977; +R0.L = R0.L + R0.L (NS); +R1.L = R0.L + R1.H (NS); +R2.L = R0.H + R2.L (NS); +R3.L = R0.H + R3.H (NS); +R4.L = R0.L + R4.L (NS); +R5.L = R0.L + R5.H (NS); +R6.L = R0.H + R6.L (NS); +R7.L = R0.H + R7.H (NS); +CHECKREG r4, 0x56789B3D; +CHECKREG r5, 0x678979AB; +CHECKREG r6, 0x74446E7C; +CHECKREG r7, 0x86669FCD; +CHECKREG r4, 0x56789B3D; +CHECKREG r5, 0x678979AB; +CHECKREG r6, 0x74446E7C; +CHECKREG r7, 0x86669FCD; + +imm32 r0, 0x15678911; +imm32 r1, 0xaa89ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x567a891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445a15; +imm32 r7, 0x866677a7; +R0.L = R1.L + R0.L (NS); +R1.L = R1.L + R1.H (NS); +R2.L = R1.H + R2.L (NS); +R3.L = R1.H + R3.H (NS); +R4.L = R1.L + R4.L (NS); +R5.L = R1.L + R5.H (NS); +R6.L = R1.H + R6.L (NS); +R7.L = R1.H + R7.H (NS); +CHECKREG r4, 0x567ADEC1; +CHECKREG r5, 0x6789BD2F; +CHECKREG r6, 0x7444049E; +CHECKREG r7, 0x866630EF; +CHECKREG r4, 0x567ADEC1; +CHECKREG r5, 0x6789BD2F; +CHECKREG r6, 0x7444049E; +CHECKREG r7, 0x866630EF; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R2.L + R0.L (NS); +R1.L = R2.L + R1.H (NS); +R2.L = R2.H + R2.L (NS); +R3.L = R2.H + R3.H (NS); +R4.L = R2.L + R4.L (NS); +R5.L = R2.L + R5.H (NS); +R6.L = R2.H + R6.L (NS); +R7.L = R2.H + R7.H (NS); +CHECKREG r4, 0x56781274; +CHECKREG r5, 0x6789F0E2; +CHECKREG r6, 0x74448959; +CHECKREG r7, 0x8666BAAA; +CHECKREG r4, 0x56781274; +CHECKREG r5, 0x6789F0E2; +CHECKREG r6, 0x74448959; +CHECKREG r7, 0x8666BAAA; + +imm32 r0, 0xb5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3bb45515; +imm32 r3, 0x46667717; +imm32 r4, 0x567b891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444b515; +imm32 r7, 0x86667b77; +R0.L = R3.L + R0.L (NS); +R1.L = R3.L + R1.H (NS); +R2.L = R3.H + R2.L (NS); +R3.L = R3.H + R3.H (NS); +R4.L = R3.L + R4.L (NS); +R5.L = R3.L + R5.H (NS); +R6.L = R3.H + R6.L (NS); +R7.L = R3.H + R7.H (NS); +CHECKREG r4, 0x567B15E7; +CHECKREG r5, 0x6789F455; +CHECKREG r6, 0x7444FB7B; +CHECKREG r7, 0x8666CCCC; +CHECKREG r4, 0x567B15E7; +CHECKREG r5, 0x6789F455; +CHECKREG r6, 0x7444FB7B; +CHECKREG r7, 0x8666CCCC; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R4.L + R0.L (NS); +R1.L = R4.L + R1.H (NS); +R2.L = R4.H + R2.L (NS); +R3.L = R4.H + R3.H (NS); +R4.L = R4.L + R4.L (NS); +R5.L = R4.L + R5.H (NS); +R6.L = R4.H + R6.L (NS); +R7.L = R4.H + R7.H (NS); +CHECKREG r4, 0x56781236; +CHECKREG r5, 0x678979BF; +CHECKREG r6, 0x7444AB8D; +CHECKREG r7, 0x8666DCDE; +CHECKREG r4, 0x56781236; +CHECKREG r5, 0x678979BF; +CHECKREG r6, 0x7444AB8D; +CHECKREG r7, 0x8666DCDE; + +imm32 r0, 0xcc678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3c445515; +imm32 r3, 0x46c67717; +imm32 r4, 0x567c891b; +imm32 r5, 0x6789cb1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667c77; +R0.L = R5.L + R0.L (NS); +R1.L = R5.L + R1.H (NS); +R2.L = R5.H + R2.L (NS); +R3.L = R5.H + R3.H (NS); +R4.L = R5.L + R4.L (NS); +R5.L = R5.L + R5.H (NS); +R6.L = R5.H + R6.L (NS); +R7.L = R5.H + R7.H (NS); +CHECKREG r4, 0x567C5438; +CHECKREG r5, 0x678932A6; +CHECKREG r6, 0x7444BC9E; +CHECKREG r7, 0x8666EDEF; +CHECKREG r4, 0x567C5438; +CHECKREG r5, 0x678932A6; +CHECKREG r6, 0x7444BC9E; +CHECKREG r7, 0x8666EDEF; + +imm32 r0, 0xd5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R0.L = R6.L + R0.L (NS); +R1.L = R6.L + R1.H (NS); +R2.L = R6.H + R2.L (NS); +R3.L = R6.H + R3.H (NS); +R4.L = R6.L + R4.L (NS); +R5.L = R6.L + R5.H (NS); +R6.L = R6.H + R6.L (NS); +R7.L = R6.H + R7.H (NS); +CHECKREG r4, 0x56785E30; +CHECKREG r5, 0x678D3CA2; +CHECKREG r6, 0x74444959; +CHECKREG r7, 0x8666FAAA; +CHECKREG r4, 0x56785E30; +CHECKREG r5, 0x678D3CA2; +CHECKREG r6, 0x74444959; +CHECKREG r7, 0x8666FAAA; + +imm32 r0, 0xf5678911; +imm32 r1, 0x2f89ab1d; +imm32 r2, 0x34f45515; +imm32 r3, 0x466f7717; +imm32 r4, 0x5678f91b; +imm32 r5, 0x6789af1d; +imm32 r6, 0x744455f5; +imm32 r7, 0x8666777f; +R0.L = R7.L + R0.L (NS); +R1.L = R7.L + R1.H (NS); +R2.L = R7.H + R2.L (NS); +R3.L = R7.H + R3.H (NS); +R4.L = R7.L + R4.L (NS); +R5.L = R7.L + R5.H (NS); +R6.L = R7.H + R6.L (NS); +R7.L = R7.H + R7.H (NS); +CHECKREG r4, 0x5678709A; +CHECKREG r5, 0x6789DF08; +CHECKREG r6, 0x7444DC5B; +CHECKREG r7, 0x86660CCC; +CHECKREG r4, 0x5678709A; +CHECKREG r5, 0x6789DF08; +CHECKREG r6, 0x7444DC5B; +CHECKREG r7, 0x86660CCC; + +imm32 r0, 0x55678911; +imm32 r1, 0x2589ab1d; +imm32 r2, 0x35545515; +imm32 r3, 0x46d67717; +imm32 r4, 0x5678891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R6.L = R2.L + R3.L (S); +R1.L = R4.L + R5.H (S); +R5.L = R7.H + R2.L (S); +R3.L = R0.H + R0.H (S); +R0.L = R3.L + R4.L (S); +R2.L = R5.L + R7.H (S); +R7.L = R6.H + R7.L (S); +R4.L = R1.H + R6.H (S); +CHECKREG r4, 0x56787FFF; +CHECKREG r5, 0x678DDB7B; +CHECKREG r6, 0x74447FFF; +CHECKREG r7, 0x86667FFF; +CHECKREG r4, 0x56787FFF; +CHECKREG r5, 0x678DDB7B; +CHECKREG r6, 0x74447FFF; +CHECKREG r7, 0x86667FFF; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3.L = R4.L + R0.L (S); +R1.L = R6.L + R3.H (S); +R4.L = R3.H + R2.L (S); +R6.L = R7.H + R1.H (S); +R2.L = R5.L + R4.L (S); +R7.L = R2.L + R7.H (S); +R0.L = R1.H + R6.L (S); +R5.L = R0.H + R5.H (S); +CHECKREG r4, 0x56787FFF; +CHECKREG r5, 0x67897CF0; +CHECKREG r6, 0x7444ADEF; +CHECKREG r7, 0x8666B182; +CHECKREG r4, 0x56787FFF; +CHECKREG r5, 0x67897CF0; +CHECKREG r6, 0x7444ADEF; +CHECKREG r7, 0x8666B182; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_m.s b/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_m.s new file mode 100644 index 0000000..3beee88 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_m.s @@ -0,0 +1,261 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_m/c_dsp32alu_rl_rnd12_m.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x85678911; + imm32 r1, 0x9189ab1d; + imm32 r2, 0xa4245515; + imm32 r3, 0xb6637717; + imm32 r4, 0xc678491b; + imm32 r5, 0x6789a51d; + imm32 r6, 0xe4445565; + imm32 r7, 0x86667777; + R0.L = R0 - R0 (RND12); + R1.L = R0 - R1 (RND12); + R2.L = R0 - R2 (RND12); + R3.L = R0 - R3 (RND12); + R4.L = R0 - R4 (RND12); + R5.L = R0 - R5 (RND12); + R6.L = R0 - R6 (RND12); + R7.L = R0 - R7 (RND12); + CHECKREG r0, 0x85670000; + CHECKREG r1, 0x91898000; + CHECKREG r2, 0xA4248000; + CHECKREG r3, 0xB6638000; + CHECKREG r4, 0xC6788000; + CHECKREG r5, 0x67898000; + CHECKREG r6, 0xE4448000; + CHECKREG r7, 0x8666F009; + + imm32 r0, 0x75678921; + imm32 r1, 0x2789ab14; + imm32 r2, 0xd4745515; + imm32 r3, 0x4d677767; + imm32 r4, 0x56d8791b; + imm32 r5, 0x678dab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86a6d777; + R0.L = R1 - R0 (RND12); + R1.L = R1 - R1 (RND12); + R2.L = R1 - R2 (RND12); + R3.L = R1 - R3 (RND12); + R4.L = R1 - R4 (RND12); + R5.L = R1 - R5 (RND12); + R6.L = R1 - R6 (RND12); + R7.L = R1 - R7 (RND12); + CHECKREG r0, 0x75678000; + CHECKREG r1, 0x27890000; + CHECKREG r2, 0xD4747FFF; + CHECKREG r3, 0x4D678000; + CHECKREG r4, 0x56D88000; + CHECKREG r5, 0x678D8000; + CHECKREG r6, 0x74448000; + CHECKREG r7, 0x86A67fff; + + imm32 r0, 0x55678911; + imm32 r1, 0x2689ab1d; + imm32 r2, 0x3d445515; + imm32 r3, 0x46967717; + imm32 r4, 0xa67a891b; + imm32 r5, 0x6789bb1d; + imm32 r6, 0x7444d515; + imm32 r7, 0x8666c777; + R0.L = R2 - R0 (RND12); + R1.L = R2 - R1 (RND12); + R2.L = R2 - R2 (RND12); + R3.L = R2 - R3 (RND12); + R4.L = R2 - R4 (RND12); + R5.L = R2 - R5 (RND12); + R6.L = R2 - R6 (RND12); + R7.L = R2 - R7 (RND12); + CHECKREG r0, 0x55678000; + CHECKREG r1, 0x26897fff; + CHECKREG r2, 0x3D440000; + CHECKREG r3, 0x46968000; + CHECKREG r4, 0xA67A7fff; + CHECKREG r5, 0x67898000; + CHECKREG r6, 0x74448000; + CHECKREG r7, 0x86667fff; + + imm32 r0, 0xf5678911; + imm32 r1, 0xd789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0xe6667717; + imm32 r4, 0x5678891b; + imm32 r5, 0x6d89ab1d; + imm32 r6, 0x7444d515; + imm32 r7, 0xe6667b77; + R0.L = R3 - R0 (RND12); + R1.L = R3 - R1 (RND12); + R2.L = R3 - R2 (RND12); + R3.L = R3 - R3 (RND12); + R4.L = R3 - R4 (RND12); + R5.L = R3 - R5 (RND12); + R6.L = R3 - R6 (RND12); + R7.L = R3 - R7 (RND12); + CHECKREG r0, 0xF5678000; + CHECKREG r1, 0xD7897fff; + CHECKREG r2, 0x34448000; + CHECKREG r3, 0xE6660000; + CHECKREG r4, 0x56788000; + CHECKREG r5, 0x6D898000; + CHECKREG r6, 0x74448000; + CHECKREG r7, 0xE666FFF8; + + imm32 r0, 0xa5678911; + imm32 r1, 0x2b89ab1d; + imm32 r2, 0x34c45515; + imm32 r3, 0x46d67717; + imm32 r4, 0x56e8891b; + imm32 r5, 0x67f9ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86687777; + R0.L = R4 - R0 (RND12); + R1.L = R4 - R1 (RND12); + R2.L = R4 - R2 (RND12); + R3.L = R4 - R3 (RND12); + R4.L = R4 - R4 (RND12); + R5.L = R4 - R5 (RND12); + R6.L = R4 - R6 (RND12); + R7.L = R4 - R7 (RND12); + CHECKREG r0, 0xa5677fff; + CHECKREG r1, 0x2b897fff; + CHECKREG r2, 0x34c47fff; + CHECKREG r3, 0x46d67fff; + CHECKREG r4, 0x56E80000; + CHECKREG r5, 0x67F98000; + CHECKREG r6, 0x74448000; + CHECKREG r7, 0x86687fff; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0xd6667717; + imm32 r4, 0x5ff8891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x744e5515; + imm32 r7, 0x8666a7b7; + R0.L = R5 - R0 (RND12); + R1.L = R5 - R1 (RND12); + R2.L = R5 - R2 (RND12); + R3.L = R5 - R3 (RND12); + R4.L = R5 - R4 (RND12); + R5.L = R5 - R5 (RND12); + R6.L = R5 - R6 (RND12); + R7.L = R5 - R7 (RND12); + CHECKREG r0, 0xE5677fff; + CHECKREG r1, 0x27897fff; + CHECKREG r2, 0x34447fff; + CHECKREG r3, 0xD6667fff; + CHECKREG r4, 0x5FF87912; + CHECKREG r5, 0x67890000; + CHECKREG r6, 0x744E8000; + CHECKREG r7, 0x86667fff; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ae1d; + imm32 r2, 0x344455e5; + imm32 r3, 0x4666771d; + imm32 r4, 0x5678891b; + imm32 r5, 0x6789abdd; + imm32 r6, 0x74a45515; + imm32 r7, 0x866c77b7; + R0.L = R6 - R0 (RND12); + R1.L = R6 - R1 (RND12); + R2.L = R6 - R2 (RND12); + R3.L = R6 - R3 (RND12); + R4.L = R6 - R4 (RND12); + R5.L = R6 - R5 (RND12); + R6.L = R6 - R6 (RND12); + R7.L = R6 - R7 (RND12); + CHECKREG r0, 0x15677fff; + CHECKREG r1, 0x27897fff; + CHECKREG r2, 0x34447fff; + CHECKREG r3, 0x46667fff; + CHECKREG r4, 0x56787fff; + CHECKREG r5, 0x67897fff; + CHECKREG r6, 0x74A40000; + CHECKREG r7, 0x866C7fff; + + imm32 r0, 0x25678911; + imm32 r1, 0x2389ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46567717; + imm32 r4, 0x5678891b; + imm32 r5, 0x678dab1d; + imm32 r6, 0x7444b515; + imm32 r7, 0xb666a777; + R0.L = R7 - R0 (RND12); + R1.L = R7 - R1 (RND12); + R2.L = R7 - R2 (RND12); + R3.L = R7 - R3 (RND12); + R4.L = R7 - R4 (RND12); + R5.L = R7 - R5 (RND12); + R6.L = R7 - R6 (RND12); + R7.L = R7 - R7 (RND12); + CHECKREG r0, 0x25678000; + CHECKREG r1, 0x23898000; + CHECKREG r2, 0x34448000; + CHECKREG r3, 0x46568000; + CHECKREG r4, 0x56788000; + CHECKREG r5, 0x678D8000; + CHECKREG r6, 0x74448000; + CHECKREG r7, 0xB6660000; + + imm32 r0, 0xaa678911; + imm32 r1, 0x27ddab1d; + imm32 r2, 0x344bb515; + imm32 r3, 0x46667717; + imm32 r4, 0x56dd891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x7444bb15; + imm32 r7, 0x86ff7777; + R6.L = R2 - R3 (RND12); + R1.L = R4 - R5 (RND12); + R5.L = R7 - R2 (RND12); + R3.L = R0 - R0 (RND12); + R0.L = R3 - R4 (RND12); + R2.L = R5 - R7 (RND12); + R7.L = R6 - R7 (RND12); + R4.L = R1 - R6 (RND12); + CHECKREG r0, 0xAA678000; + CHECKREG r1, 0x27DD8000; + CHECKREG r2, 0x344B7fff; + CHECKREG r3, 0x46660000; + CHECKREG r4, 0x56DD8000; + CHECKREG r5, 0x67898000; + CHECKREG r6, 0x74448000; + CHECKREG r7, 0x86FF7fff; + + imm32 r0, 0x95678911; + imm32 r1, 0x2d89ab1d; + imm32 r2, 0x34b45515; + imm32 r3, 0x46c67717; + imm32 r4, 0x567e891b; + imm32 r5, 0x678fab1d; + imm32 r6, 0x744e5515; + imm32 r7, 0x8b66a777; + R3.L = R4 - R0 (RND12); + R1.L = R6 - R3 (RND12); + R4.L = R3 - R2 (RND12); + R6.L = R7 - R1 (RND12); + R2.L = R5 - R4 (RND12); + R7.L = R2 - R7 (RND12); + R0.L = R1 - R6 (RND12); + R5.L = R0 - R5 (RND12); + CHECKREG r0, 0x95678000; + CHECKREG r1, 0x2D897fff; + CHECKREG r2, 0x34B47fff; + CHECKREG r3, 0x46C67fff; + CHECKREG r4, 0x567E7fff; + CHECKREG r5, 0x678F8000; + CHECKREG r6, 0x744E8000; + CHECKREG r7, 0x8B667FFF; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_p.s b/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_p.s new file mode 100644 index 0000000..bc159a2 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_p.s @@ -0,0 +1,262 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_p/c_dsp32alu_rl_rnd12_p.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + + imm32 r0, 0x85678011; + imm32 r1, 0x9189a11d; + imm32 r2, 0xa4245235; + imm32 r3, 0xb6637747; + imm32 r4, 0xc67849db; + imm32 r5, 0x6789a5fd; + imm32 r6, 0xe4445565; + imm32 r7, 0x86667707; + R0.L = R0 + R0 (RND12); + R1.L = R0 + R1 (RND12); + R2.L = R0 + R2 (RND12); + R3.L = R0 + R3 (RND12); + R4.L = R0 + R4 (RND12); + R5.L = R0 + R5 (RND12); + R6.L = R0 + R6 (RND12); + R7.L = R0 + R7 (RND12); + CHECKREG r0, 0x85678000; + CHECKREG r1, 0x91898000; + CHECKREG r2, 0xA4248000; + CHECKREG r3, 0xB6638000; + CHECKREG r4, 0xC6788000; + CHECKREG r5, 0x67898000; + CHECKREG r6, 0xE4448000; + CHECKREG r7, 0x86668000; + + imm32 r0, 0x75678921; + imm32 r1, 0x2789ab14; + imm32 r2, 0xd4745515; + imm32 r3, 0x4d677767; + imm32 r4, 0x56d8791b; + imm32 r5, 0x678dab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86a6d777; + R0.L = R1 + R0 (RND12); + R1.L = R1 + R1 (RND12); + R2.L = R1 + R2 (RND12); + R3.L = R1 + R3 (RND12); + R4.L = R1 + R4 (RND12); + R5.L = R1 + R5 (RND12); + R6.L = R1 + R6 (RND12); + R7.L = R1 + R7 (RND12); + CHECKREG r0, 0x75677FFF; + CHECKREG r1, 0x27897FFF; + CHECKREG r2, 0xD474bfdd; + CHECKREG r3, 0x4D677fff; + CHECKREG r4, 0x56D87FFF; + CHECKREG r5, 0x678D7FFF; + CHECKREG r6, 0x74447FFF; + CHECKREG r7, 0x86A68000; + + imm32 r0, 0x55678911; + imm32 r1, 0x2689ab2d; + imm32 r2, 0x3d44551a; + imm32 r3, 0x469677cd; + imm32 r4, 0xa67a89bb; + imm32 r5, 0x6789bb1d; + imm32 r6, 0x7444d525; + imm32 r7, 0x8666c747; + R0.L = R2 + R0 (RND12); + R1.L = R2 + R1 (RND12); + R2.L = R2 + R2 (RND12); + R3.L = R2 + R3 (RND12); + R4.L = R2 + R4 (RND12); + R5.L = R2 + R5 (RND12); + R6.L = R2 + R6 (RND12); + R7.L = R2 + R7 (RND12); + CHECKREG r0, 0x55677fff; + CHECKREG r1, 0x26897fff; + CHECKREG r2, 0x3D447fff; + CHECKREG r3, 0x46967fff; + CHECKREG r4, 0xA67A8000; + CHECKREG r5, 0x67897fff; + CHECKREG r6, 0x74447fff; + CHECKREG r7, 0x86668000; + + imm32 r0, 0xf5678901; + imm32 r1, 0xd789ab7d; + imm32 r2, 0x34445565; + imm32 r3, 0xe6667757; + imm32 r4, 0x5678894b; + imm32 r5, 0x6d89ab3d; + imm32 r6, 0x7444d525; + imm32 r7, 0xe6667b77; + R0.L = R3 + R0 (RND12); + R1.L = R3 + R1 (RND12); + R2.L = R3 + R2 (RND12); + R3.L = R3 + R3 (RND12); + R4.L = R3 + R4 (RND12); + R5.L = R3 + R5 (RND12); + R6.L = R3 + R6 (RND12); + R7.L = R3 + R7 (RND12); + CHECKREG r0, 0xF5678000; + CHECKREG r1, 0xD7898000; + CHECKREG r2, 0x34447FFF; + CHECKREG r3, 0xE6668000; + CHECKREG r4, 0x56787FFF; + CHECKREG r5, 0x6D897FFF; + CHECKREG r6, 0x74447FFF; + CHECKREG r7, 0xE6668000; + + imm32 r0, 0xa5678911; + imm32 r1, 0x2b89ab1d; + imm32 r2, 0x34c45515; + imm32 r3, 0x46d67717; + imm32 r4, 0x56e8891b; + imm32 r5, 0x67f9ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86687777; + R0.L = R4 + R0 (RND12); + R1.L = R4 + R1 (RND12); + R2.L = R4 + R2 (RND12); + R3.L = R4 + R3 (RND12); + R4.L = R4 + R4 (RND12); + R5.L = R4 + R5 (RND12); + R6.L = R4 + R6 (RND12); + R7.L = R4 + R7 (RND12); + CHECKREG r0, 0xA567c501; + CHECKREG r1, 0x2B897fff; + CHECKREG r2, 0x34C47FFF; + CHECKREG r3, 0x46D67FFF; + CHECKREG r4, 0x56E87FFF; + CHECKREG r5, 0x67F97FFF; + CHECKREG r6, 0x74447FFF; + CHECKREG r7, 0x86688000; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445535; + imm32 r3, 0xd6667747; + imm32 r4, 0x5ff8895b; + imm32 r5, 0x6789ab8d; + imm32 r6, 0x744e5515; + imm32 r7, 0x8666a7b7; + R0.L = R5 + R0 (RND12); + R1.L = R5 + R1 (RND12); + R2.L = R5 + R2 (RND12); + R3.L = R5 + R3 (RND12); + R4.L = R5 + R4 (RND12); + R5.L = R5 + R5 (RND12); + R6.L = R5 + R6 (RND12); + R7.L = R5 + R7 (RND12); + CHECKREG r0, 0xE5677FFF; + CHECKREG r1, 0x27897FFF; + CHECKREG r2, 0x34447FFF; + CHECKREG r3, 0xD6667FFF; + CHECKREG r4, 0x5FF87fff; + CHECKREG r5, 0x67897FFF; + CHECKREG r6, 0x744E7FFF; + CHECKREG r7, 0x86668000; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ae1d; + imm32 r2, 0x344455e5; + imm32 r3, 0x4666771d; + imm32 r4, 0x5678891b; + imm32 r5, 0x6789abdd; + imm32 r6, 0x74a45515; + imm32 r7, 0x866c77b7; + R0.L = R6 + R0 (RND12); + R1.L = R6 + R1 (RND12); + R2.L = R6 + R2 (RND12); + R3.L = R6 + R3 (RND12); + R4.L = R6 + R4 (RND12); + R5.L = R6 + R5 (RND12); + R6.L = R6 + R6 (RND12); + R7.L = R6 + R7 (RND12); + CHECKREG r0, 0x15677FFF; + CHECKREG r1, 0x27897FFF; + CHECKREG r2, 0x34447FFF; + CHECKREG r3, 0x46667FFF; + CHECKREG r4, 0x56787FFF; + CHECKREG r5, 0x67897FFF; + CHECKREG r6, 0x74A47FFF; + CHECKREG r7, 0x866Cb10f; + + imm32 r0, 0x25678931; + imm32 r1, 0x2389ab14; + imm32 r2, 0x34445576; + imm32 r3, 0x46567787; + imm32 r4, 0x5678899b; + imm32 r5, 0x678dab1d; + imm32 r6, 0x7444b515; + imm32 r7, 0xb666a777; + R0.L = R7 + R0 (RND12); + R1.L = R7 + R1 (RND12); + R2.L = R7 + R2 (RND12); + R3.L = R7 + R3 (RND12); + R4.L = R7 + R4 (RND12); + R5.L = R7 + R5 (RND12); + R6.L = R7 + R6 (RND12); + R7.L = R7 + R7 (RND12); + CHECKREG r0, 0x25678000; + CHECKREG r1, 0x23898000; + CHECKREG r2, 0x34448000; + CHECKREG r3, 0x4656cbd2; + CHECKREG r4, 0x56787FFF; + CHECKREG r5, 0x678D7FFF; + CHECKREG r6, 0x74447FFF; + CHECKREG r7, 0xB6668000; + + imm32 r0, 0xaa678911; + imm32 r1, 0x27ddab1d; + imm32 r2, 0x344bb515; + imm32 r3, 0x46667717; + imm32 r4, 0x56dd891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x7444bb15; + imm32 r7, 0x86ff7777; + R6.L = R2 + R3 (RND12); + R1.L = R4 + R5 (RND12); + R5.L = R7 + R2 (RND12); + R3.L = R0 + R0 (RND12); + R0.L = R3 + R4 (RND12); + R2.L = R5 + R7 (RND12); + R7.L = R6 + R7 (RND12); + R4.L = R1 + R6 (RND12); + CHECKREG r0, 0xAA677FFF; + CHECKREG r1, 0x27DD7FFF; + CHECKREG r2, 0x344B8000; + CHECKREG r3, 0x46668000; + CHECKREG r4, 0x56DD7FFF; + CHECKREG r5, 0x67898000; + CHECKREG r6, 0x74447FFF; + CHECKREG r7, 0x86FFb43f; + + imm32 r0, 0x95678911; + imm32 r1, 0x2d89ab1d; + imm32 r2, 0x34b45515; + imm32 r3, 0x46c67717; + imm32 r4, 0x567e891b; + imm32 r5, 0x678fab1d; + imm32 r6, 0x744e5515; + imm32 r7, 0x8b66a777; + R3.L = R4 + R0 (RND12); + R1.L = R6 + R3 (RND12); + R4.L = R3 + R2 (RND12); + R6.L = R7 + R1 (RND12); + R2.L = R5 + R4 (RND12); + R7.L = R2 + R7 (RND12); + R0.L = R1 + R6 (RND12); + R5.L = R0 + R5 (RND12); + CHECKREG r0, 0x95677fff; + CHECKREG r1, 0x2D897FFF; + CHECKREG r2, 0x34B47FFF; + CHECKREG r3, 0x46C68000; + CHECKREG r4, 0x567E7FFF; + CHECKREG r5, 0x678Fcf73; + CHECKREG r6, 0x744E8000; + CHECKREG r7, 0x8B668000; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_m.s b/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_m.s new file mode 100644 index 0000000..4916fd0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_m.s @@ -0,0 +1,262 @@ +//Original:/testcases/core/c_dsp32alu_rl_rnd20_m/c_dsp32alu_rl_rnd20_m.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x75678911; +imm32 r1, 0xa789ab1d; +imm32 r2, 0x34745515; +imm32 r3, 0x4b677717; +imm32 r4, 0x5678791b; +imm32 r5, 0xc789a71d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R0 - R0 (RND20); +R1.L = R0 - R1 (RND20); +R2.L = R0 - R2 (RND20); +R3.L = R0 - R3 (RND20); +R4.L = R0 - R4 (RND20); +R5.L = R0 - R5 (RND20); +R6.L = R0 - R6 (RND20); +R7.L = R0 - R7 (RND20); +CHECKREG r0, 0x75670000; +CHECKREG r1, 0xA7890CDE; +CHECKREG r2, 0x3474040F; +CHECKREG r3, 0x4B6702A0; +CHECKREG r4, 0x567801EF; +CHECKREG r5, 0xC7890ADE; +CHECKREG r6, 0x74440012; +CHECKREG r7, 0x86660EF0; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3e445515; +imm32 r3, 0x46667717; +imm32 r4, 0x56e8891b; +imm32 r5, 0x678eab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86e67e77; +R0.L = R1 - R0 (RND20); +CHECKREG r0, 0xE5670422; +R1.L = R1 - R1 (RND20); +CHECKREG r1, 0x27890000; +R2.L = R1 - R2 (RND20); +CHECKREG r2, 0x3E44FE94; +R3.L = R1 - R3 (RND20); +CHECKREG r3, 0x4666FE12; +R4.L = R1 - R4 (RND20); +R5.L = R1 - R5 (RND20); +R6.L = R1 - R6 (RND20); +R7.L = R1 - R7 (RND20); +CHECKREG r0, 0xE5670422; +CHECKREG r1, 0x27890000; +CHECKREG r2, 0x3E44FE94; +CHECKREG r3, 0x4666FE12; +CHECKREG r4, 0x56E8FD0A; +CHECKREG r5, 0x678EFC00; +CHECKREG r6, 0x7444FB34; +CHECKREG r7, 0x86E60A0A; + +imm32 r0, 0xdd678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46667717; +imm32 r4, 0x56d8891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R0.L = R2 - R0 (RND20); +R1.L = R2 - R1 (RND20); +R2.L = R2 - R2 (RND20); +R3.L = R2 - R3 (RND20); +R4.L = R2 - R4 (RND20); +R5.L = R2 - R5 (RND20); +R6.L = R2 - R6 (RND20); +R7.L = R2 - R7 (RND20); +CHECKREG r0, 0xDD6705FE; +CHECKREG r1, 0x2789015C; +CHECKREG r2, 0x3D440000; +CHECKREG r3, 0x4666FF6E; +CHECKREG r4, 0x56D8FE67; +CHECKREG r5, 0x678DFD5B; +CHECKREG r6, 0x7444FC90; +CHECKREG r7, 0x86660B6E; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x567a891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444c515; +imm32 r7, 0x86667c77; +R0.L = R3 - R0 (RND20); +R1.L = R3 - R1 (RND20); +R2.L = R3 - R2 (RND20); +R3.L = R3 - R3 (RND20); +R4.L = R3 - R4 (RND20); +R5.L = R3 - R5 (RND20); +R6.L = R3 - R6 (RND20); +R7.L = R3 - R7 (RND20); +CHECKREG r0, 0xA5670A14; +CHECKREG r1, 0x2A8901C2; +CHECKREG r2, 0x34440126; +CHECKREG r3, 0x46A60000; +CHECKREG r4, 0x567AFF03; +CHECKREG r5, 0x6789FDF2; +CHECKREG r6, 0x7444FD26; +CHECKREG r7, 0x86660C04; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R4 - R0 (RND20); +R1.L = R4 - R1 (RND20); +R2.L = R4 - R2 (RND20); +R3.L = R4 - R3 (RND20); +R4.L = R4 - R4 (RND20); +R5.L = R4 - R5 (RND20); +R6.L = R4 - R6 (RND20); +R7.L = R4 - R7 (RND20); +CHECKREG r0, 0x15670411; +CHECKREG r1, 0x278902EF; +CHECKREG r2, 0x34440223; +CHECKREG r3, 0x46660101; +CHECKREG r4, 0x56780000; +CHECKREG r5, 0x6789FEEF; +CHECKREG r6, 0x7444FE23; +CHECKREG r7, 0x86660D01; + +imm32 r0, 0x95678911; +imm32 r1, 0x8789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0x4a667717; +imm32 r4, 0x56b8891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444e515; +imm32 r7, 0x86667d77; +R0.L = R5 - R0 (RND20); +R1.L = R5 - R1 (RND20); +R2.L = R5 - R2 (RND20); +R3.L = R5 - R3 (RND20); +R4.L = R5 - R4 (RND20); +R5.L = R5 - R5 (RND20); +R6.L = R5 - R6 (RND20); +R7.L = R5 - R7 (RND20); +CHECKREG r0, 0x95670D22; +CHECKREG r1, 0x87890E00; +CHECKREG r2, 0x7444FF35; +CHECKREG r3, 0x4A6601D2; +CHECKREG r4, 0x56B8010D; +CHECKREG r5, 0x678D0000; +CHECKREG r6, 0x7444FF35; +CHECKREG r7, 0x86660E12; + +imm32 r0, 0x35678911; +imm32 r1, 0x2459ab1d; +imm32 r2, 0x34465515; +imm32 r3, 0xe6667717; +imm32 r4, 0x5d78891b; +imm32 r5, 0x67b9ab1d; +imm32 r6, 0x744a5515; +imm32 r7, 0x8666c777; +R0.L = R6 - R0 (RND20); +R1.L = R6 - R1 (RND20); +R2.L = R6 - R2 (RND20); +R3.L = R6 - R3 (RND20); +R4.L = R6 - R4 (RND20); +R5.L = R6 - R5 (RND20); +R6.L = R6 - R6 (RND20); +R7.L = R6 - R7 (RND20); +CHECKREG r0, 0x356703EE; +CHECKREG r1, 0x245904FF; +CHECKREG r2, 0x34460400; +CHECKREG r3, 0xE66608DE; +CHECKREG r4, 0x5D78016D; +CHECKREG r5, 0x67B900C9; +CHECKREG r6, 0x744A0000; +CHECKREG r7, 0x86660EDE; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3a445515; +imm32 r3, 0x4c667717; +imm32 r4, 0x56b8891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x8666d777; +R0.L = R7 - R0 (RND20); +R1.L = R7 - R1 (RND20); +R2.L = R7 - R2 (RND20); +R3.L = R7 - R3 (RND20); +R4.L = R7 - R4 (RND20); +R5.L = R7 - R5 (RND20); +R6.L = R7 - R6 (RND20); +R7.L = R7 - R7 (RND20); +CHECKREG r0, 0xA567FE10; +CHECKREG r1, 0x2789F5EE; +CHECKREG r2, 0x3A44F4C2; +CHECKREG r3, 0x4C66F3A0; +CHECKREG r4, 0x56B8F2FB; +CHECKREG r5, 0x678DF1EE; +CHECKREG r6, 0x7444F122; +CHECKREG r7, 0x86660000; + +imm32 r0, 0xabd78911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0xd4445515; +imm32 r3, 0x4e667717; +imm32 r4, 0x56f8891b; +imm32 r5, 0x678aab1d; +imm32 r6, 0x7444b515; +imm32 r7, 0x86667d77; +R6.L = R2 - R3 (RND20); +R1.L = R4 - R5 (RND20); +R5.L = R7 - R2 (RND20); +R3.L = R0 - R0 (RND20); +R0.L = R3 - R4 (RND20); +R2.L = R5 - R7 (RND20); +R7.L = R6 - R7 (RND20); +R4.L = R1 - R6 (RND20); +CHECKREG r0, 0xABD7FF77; +CHECKREG r1, 0x2789FEF7; +CHECKREG r2, 0xD4440E12; +CHECKREG r3, 0x4E660000; +CHECKREG r4, 0x56F8FB34; +CHECKREG r5, 0x678AFB22; +CHECKREG r6, 0x7444F85E; +CHECKREG r7, 0x86660EDE; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3.L = R4 - R0 (RND20); +R1.L = R6 - R3 (RND20); +R4.L = R3 - R2 (RND20); +R6.L = R7 - R1 (RND20); +R2.L = R5 - R4 (RND20); +R7.L = R2 - R7 (RND20); +R0.L = R1 - R6 (RND20); +R5.L = R0 - R5 (RND20); +CHECKREG r0, 0x1567FB34; +CHECKREG r1, 0x278902DE; +CHECKREG r2, 0x34440111; +CHECKREG r3, 0x46660411; +CHECKREG r4, 0x56780122; +CHECKREG r5, 0x6789FADE; +CHECKREG r6, 0x7444F5EE; +CHECKREG r7, 0x86660ADE; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_p.s b/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_p.s new file mode 100644 index 0000000..ced4fcc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_p.s @@ -0,0 +1,258 @@ +//Original:/testcases/core/c_dsp32alu_rl_rnd20_p/c_dsp32alu_rl_rnd20_p.dsp +// Spec Reference: dsp32alu dreg (half) +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x75678911; +imm32 r1, 0xa789ab1d; +imm32 r2, 0x34745515; +imm32 r3, 0x4b677717; +imm32 r4, 0x5678791b; +imm32 r5, 0xc789a71d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R0 + R0 (RND20); +R1.L = R0 + R1 (RND20); +R2.L = R0 + R2 (RND20); +R3.L = R0 + R3 (RND20); +R4.L = R0 + R4 (RND20); +R5.L = R0 + R5 (RND20); +R6.L = R0 + R6 (RND20); +R7.L = R0 + R7 (RND20); +CHECKREG r0, 0x75670EAD; +CHECKREG r1, 0xA78901CF; +CHECKREG r2, 0x34740A9E; +CHECKREG r3, 0x4B670C0D; +CHECKREG r4, 0x56780CBE; +CHECKREG r5, 0xC78903CF; +CHECKREG r6, 0x74440E9B; +CHECKREG r7, 0x8666FFBD; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3e445515; +imm32 r3, 0x46667717; +imm32 r4, 0x56e8891b; +imm32 r5, 0x678eab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86e67e77; +R0.L = R1 + R0 (RND20); +R1.L = R1 + R1 (RND20); +R2.L = R1 + R2 (RND20); +R3.L = R1 + R3 (RND20); +R4.L = R1 + R4 (RND20); +R5.L = R1 + R5 (RND20); +R6.L = R1 + R6 (RND20); +R7.L = R1 + R7 (RND20); +CHECKREG r0, 0xE56700CF; +CHECKREG r1, 0x278904F1; +CHECKREG r2, 0x3E44065D; +CHECKREG r3, 0x466606DF; +CHECKREG r4, 0x56E807E7; +CHECKREG r5, 0x678E08F1; +CHECKREG r6, 0x744409BD; +CHECKREG r7, 0x86E6FAE7; + +imm32 r0, 0xdd678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3d445515; +imm32 r3, 0x46667717; +imm32 r4, 0x56d8891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R0.L = R2 + R0 (RND20); +R1.L = R2 + R1 (RND20); +R2.L = R2 + R2 (RND20); +R3.L = R2 + R3 (RND20); +R4.L = R2 + R4 (RND20); +R5.L = R2 + R5 (RND20); +R6.L = R2 + R6 (RND20); +R7.L = R2 + R7 (RND20); +CHECKREG r0, 0xDD6701AB; +CHECKREG r1, 0x2789064D; +CHECKREG r2, 0x3D4407A9; +CHECKREG r3, 0x4666083B; +CHECKREG r4, 0x56D80942; +CHECKREG r5, 0x678D0A4D; +CHECKREG r6, 0x74440B19; +CHECKREG r7, 0x8666FC3B; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x567a891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444c515; +imm32 r7, 0x86667c77; +R0.L = R3 + R0 (RND20); +R1.L = R3 + R1 (RND20); +R2.L = R3 + R2 (RND20); +R3.L = R3 + R3 (RND20); +R4.L = R3 + R4 (RND20); +R5.L = R3 + R5 (RND20); +R6.L = R3 + R6 (RND20); +R7.L = R3 + R7 (RND20); +CHECKREG r0, 0xA567FEC1; +CHECKREG r1, 0x2A890713; +CHECKREG r2, 0x344407AF; +CHECKREG r3, 0x46A608D5; +CHECKREG r4, 0x567A09D2; +CHECKREG r5, 0x67890AE3; +CHECKREG r6, 0x74440BAF; +CHECKREG r7, 0x8666FCD1; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0.L = R4 + R0 (RND20); +R1.L = R4 + R1 (RND20); +R2.L = R4 + R2 (RND20); +R3.L = R4 + R3 (RND20); +R4.L = R4 + R4 (RND20); +R5.L = R4 + R5 (RND20); +R6.L = R4 + R6 (RND20); +R7.L = R4 + R7 (RND20); +CHECKREG r0, 0x156706BE; +CHECKREG r1, 0x278907E0; +CHECKREG r2, 0x344408AC; +CHECKREG r3, 0x466609CE; +CHECKREG r4, 0x56780ACF; +CHECKREG r5, 0x67890BE0; +CHECKREG r6, 0x74440CAC; +CHECKREG r7, 0x8666FDCE; + +imm32 r0, 0x95678911; +imm32 r1, 0x8789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0x4a667717; +imm32 r4, 0x56b8891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444e515; +imm32 r7, 0x86667d77; +R0.L = R5 + R0 (RND20); +R1.L = R5 + R1 (RND20); +R2.L = R5 + R2 (RND20); +R3.L = R5 + R3 (RND20); +R4.L = R5 + R4 (RND20); +R5.L = R5 + R5 (RND20); +R6.L = R5 + R6 (RND20); +R7.L = R5 + R7 (RND20); +CHECKREG r0, 0x9567FFCF; +CHECKREG r1, 0x8789FEF1; +CHECKREG r2, 0x74440DBD; +CHECKREG r3, 0x4A660B1F; +CHECKREG r4, 0x56B80BE4; +CHECKREG r5, 0x678D0CF2; +CHECKREG r6, 0x74440DBD; +CHECKREG r7, 0x8666FEDF; + +imm32 r0, 0x35678911; +imm32 r1, 0x2459ab1d; +imm32 r2, 0x34465515; +imm32 r3, 0xe6667717; +imm32 r4, 0x5d78891b; +imm32 r5, 0x67b9ab1d; +imm32 r6, 0x744a5515; +imm32 r7, 0x8666c777; +R0.L = R6 + R0 (RND20); +R1.L = R6 + R1 (RND20); +R2.L = R6 + R2 (RND20); +R3.L = R6 + R3 (RND20); +R4.L = R6 + R4 (RND20); +R5.L = R6 + R5 (RND20); +R6.L = R6 + R6 (RND20); +R7.L = R6 + R7 (RND20); +CHECKREG r0, 0x35670A9B; +CHECKREG r1, 0x2459098A; +CHECKREG r2, 0x34460A89; +CHECKREG r3, 0xE66605AB; +CHECKREG r4, 0x5D780D1C; +CHECKREG r5, 0x67B90DC0; +CHECKREG r6, 0x744A0E89; +CHECKREG r7, 0x8666FFAB; + +imm32 r0, 0xa5678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3a445515; +imm32 r3, 0x4c667717; +imm32 r4, 0x56b8891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x8666d777; +R0.L = R7 + R0 (RND20); +R1.L = R7 + R1 (RND20); +R2.L = R7 + R2 (RND20); +R3.L = R7 + R3 (RND20); +R4.L = R7 + R4 (RND20); +R5.L = R7 + R5 (RND20); +R6.L = R7 + R6 (RND20); +R7.L = R7 + R7 (RND20); +CHECKREG r0, 0xA567F2BD; +CHECKREG r1, 0x2789FADF; +CHECKREG r2, 0x3A44FC0B; +CHECKREG r3, 0x4C66FD2D; +CHECKREG r4, 0x56B8FDD2; +CHECKREG r5, 0x678DFEDF; +CHECKREG r6, 0x7444FFAB; +CHECKREG r7, 0x8666F0CD; + +imm32 r0, 0xabd78911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0xd4445515; +imm32 r3, 0x4e667717; +imm32 r4, 0x56f8891b; +imm32 r5, 0x678aab1d; +imm32 r6, 0x7444b515; +imm32 r7, 0x86667d77; +R6.L = R2 + R3 (RND20); +R1.L = R4 + R5 (RND20); +R5.L = R7 + R2 (RND20); +R3.L = R0 + R0 (RND20); +R0.L = R3 + R4 (RND20); +R2.L = R5 + R7 (RND20); +R7.L = R6 + R7 (RND20); +R4.L = R1 + R6 (RND20); +CHECKREG r0, 0xABD70A56; +CHECKREG r1, 0x27890BE8; +CHECKREG r2, 0xD444FEDF; +CHECKREG r3, 0x4E66F57B; +CHECKREG r4, 0x56F809BD; +CHECKREG r5, 0x678AF5AB; +CHECKREG r6, 0x7444022B; +CHECKREG r7, 0x8666FFAB; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5678891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3.L = R4 + R0 (RND20); +R1.L = R6 + R3 (RND20); +R4.L = R3 + R2 (RND20); +R6.L = R7 + R1 (RND20); +R2.L = R5 + R4 (RND20); +R7.L = R2 + R7 (RND20); +R0.L = R1 + R6 (RND20); +R5.L = R0 + R5 (RND20); +CHECKREG r0, 0x156709BD; +CHECKREG r1, 0x27890BAB; +CHECKREG r2, 0x34440BE0; +CHECKREG r3, 0x466606BE; +CHECKREG r4, 0x567807AB; +CHECKREG r5, 0x678907CF; +CHECKREG r6, 0x7444FADF; +CHECKREG r7, 0x8666FBAB; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rlh_rnd.s b/sim/testsuite/sim/bfin/c_dsp32alu_rlh_rnd.s new file mode 100644 index 0000000..b7f0c2a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rlh_rnd.s @@ -0,0 +1,66 @@ +//Original:/testcases/core/c_dsp32alu_rlh_rnd/c_dsp32alu_rlh_rnd.dsp +// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x4537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x44555535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0.L = R1 (RND); +R0.H = R2 (RND); +R1.L = R3 (RND); +R1.H = R4 (RND); +R2.L = R5 (RND); +R2.H = R6 (RND); +CHECKREG r0, 0x4455675A; +CHECKREG r1, 0x88796666; +CHECKREG r2, 0xCC9DAA8B; + + +imm32 r0, 0xe537891b; +imm32 r1, 0xf759ab2d; +imm32 r2, 0x4ef55535; +imm32 r3, 0x666b5747; +imm32 r4, 0xc8789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0x8c9cdd85; +imm32 r7, 0x9eaeff9f; +R3.L = R0 (RND); +R3.H = R1 (RND); +R4.L = R2 (RND); +R4.H = R5 (RND); +R5.L = R6 (RND); +R5.H = R7 (RND); +CHECKREG r3, 0xF75AE538; +CHECKREG r4, 0xAA8B4EF5; +CHECKREG r5, 0x9EAF8C9D; + +imm32 r0, 0x5537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x8ef55535; +imm32 r3, 0x666b5747; +imm32 r4, 0xc8789565; +imm32 r5, 0xea8abb5b; +imm32 r6, 0xfc9cdd85; +imm32 r7, 0x9eaeff9f; +R6.L = R0 (RND); +R6.H = R1 (RND); +R7.L = R2 (RND); +R7.H = R3 (RND); +R5.L = R4 (RND); +R5.H = R5 (RND); +CHECKREG r5, 0xEA8BC879; +CHECKREG r6, 0x675A5538; +CHECKREG r7, 0x666B8EF5; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rm.s b/sim/testsuite/sim/bfin/c_dsp32alu_rm.s new file mode 100644 index 0000000..f8c1407 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rm.s @@ -0,0 +1,262 @@ +//Original:/testcases/core/c_dsp32alu_rm/c_dsp32alu_rm.dsp +// Spec Reference: dsp32alu +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x35678911; +imm32 r1, 0x2389ab1d; +imm32 r2, 0x34345515; +imm32 r3, 0x46637717; +imm32 r4, 0x5567391b; +imm32 r5, 0x6789a31d; +imm32 r6, 0x744455a5; +imm32 r7, 0x866677a7; +R0 = R0 - R0 (NS); +R1 = R0 - R1 (NS); +R2 = R0 - R2 (NS); +R3 = R0 - R3 (NS); +R4 = R0 - R4 (NS); +R5 = R0 - R5 (NS); +R6 = R0 - R6 (NS); +R7 = R0 - R7 (NS); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xDC7654E3; +CHECKREG r2, 0xCBCBAAEB; +CHECKREG r3, 0xB99C88E9; +CHECKREG r4, 0xAA98C6E5; +CHECKREG r5, 0x98765CE3; +CHECKREG r6, 0x8BBBAA5B; +CHECKREG r7, 0x79998859; + +imm32 r0, 0xa5678911; +imm32 r1, 0x4a89ab1d; +imm32 r2, 0x54a45515; +imm32 r3, 0x466a7717; +imm32 r4, 0x5567a91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445a15; +imm32 r7, 0x866677a7; +R0 = R1 - R0 (NS); +R1 = R1 - R1 (NS); +R2 = R1 - R2 (NS); +R3 = R1 - R3 (NS); +R4 = R1 - R4 (NS); +R5 = R1 - R5 (NS); +R6 = R1 - R6 (NS); +R7 = R1 - R7 (NS); +CHECKREG r0, 0xA522220C; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xAB5BAAEB; +CHECKREG r3, 0xB99588E9; +CHECKREG r4, 0xAA9856E5; +CHECKREG r5, 0x987654E3; +CHECKREG r6, 0x8BBBA5EB; +CHECKREG r7, 0x79998859; + +imm32 r0, 0xda678911; +imm32 r1, 0x27c9ab1d; +imm32 r2, 0x344c5515; +imm32 r3, 0x4666c717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x744455b5; +imm32 r7, 0x8666777b; +R0 = R2 - R0 (NS); +R1 = R2 - R1 (NS); +R2 = R2 - R2 (NS); +R3 = R2 - R3 (NS); +R4 = R2 - R4 (NS); +R5 = R2 - R5 (NS); +R6 = R2 - R6 (NS); +R7 = R2 - R7 (NS); +CHECKREG r0, 0x59E4CC04; +CHECKREG r1, 0x0C82A9F8; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xB99938E9; +CHECKREG r4, 0xAA9876E5; +CHECKREG r5, 0x987654E3; +CHECKREG r6, 0x8BBBAA4B; +CHECKREG r7, 0x79998885; + +imm32 r0, 0x65678911; +imm32 r1, 0x7289ab1d; +imm32 r2, 0x84345515; +imm32 r3, 0x96647717; +imm32 r4, 0x5567591b; +imm32 r5, 0x6789a61d; +imm32 r6, 0x744d5515; +imm32 r7, 0x8666b777; +R0 = R3 - R0 (NS); +R1 = R3 - R1 (NS); +R2 = R3 - R2 (NS); +R3 = R3 - R3 (NS); +R4 = R3 - R4 (NS); +R5 = R3 - R5 (NS); +R6 = R3 - R6 (NS); +R7 = R3 - R7 (NS); +CHECKREG r0, 0x30FCEE06; +CHECKREG r1, 0x23DACBFA; +CHECKREG r2, 0x12302202; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xAA98A6E5; +CHECKREG r5, 0x987659E3; +CHECKREG r6, 0x8BB2AAEB; +CHECKREG r7, 0x79994889; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R4 - R0 (NS); +R1 = R4 - R1 (NS); +R2 = R4 - R2 (NS); +R3 = R4 - R3 (NS); +R4 = R4 - R4 (NS); +R5 = R4 - R5 (NS); +R6 = R4 - R6 (NS); +R7 = R4 - R7 (NS); +CHECKREG r0, 0x4000000A; +CHECKREG r1, 0x2DDDDDFE; +CHECKREG r2, 0x21233406; +CHECKREG r3, 0x0F011204; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x987654E3; +CHECKREG r6, 0x8BBBAAEB; +CHECKREG r7, 0x79998889; + +imm32 r0, 0x95678911; +imm32 r1, 0x8789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0x36667717; +imm32 r4, 0x3567891b; +imm32 r5, 0x6e89ab1d; +imm32 r6, 0x74e45515; +imm32 r7, 0x866e7777; +R0 = R5 - R0 (NS); +R1 = R5 - R1 (NS); +R2 = R5 - R2 (NS); +R3 = R5 - R3 (NS); +R4 = R5 - R4 (NS); +R5 = R5 - R5 (NS); +R6 = R5 - R6 (NS); +R7 = R5 - R7 (NS); +CHECKREG r0, 0xD922220C; +CHECKREG r1, 0xE7000000; +CHECKREG r2, 0xFA455608; +CHECKREG r3, 0x38233406; +CHECKREG r4, 0x39222202; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x8B1BAAEB; +CHECKREG r7, 0x79918889; + +imm32 r0, 0x5a678911; +imm32 r1, 0x67c9ab1d; +imm32 r2, 0x744d5515; +imm32 r3, 0x8666b717; +imm32 r4, 0x9567891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x74445f15; +imm32 r7, 0x866677f7; +R0 = R6 - R0 (NS); +R1 = R6 - R1 (NS); +R2 = R6 - R2 (NS); +R3 = R6 - R3 (NS); +R4 = R6 - R4 (NS); +R5 = R6 - R5 (NS); +R6 = R6 - R6 (NS); +R7 = R6 - R7 (NS); +CHECKREG r0, 0x19DCD604; +CHECKREG r1, 0x0C7AB3F8; +CHECKREG r2, 0xFFF70A00; +CHECKREG r3, 0xEDDDA7FE; +CHECKREG r4, 0xDEDCD5FA; +CHECKREG r5, 0x0CBA83F8; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x79998809; + +imm32 r0, 0x25678911; +imm32 r1, 0x2389ab1d; +imm32 r2, 0x3a455515; +imm32 r3, 0x46d66717; +imm32 r4, 0x556b891b; +imm32 r5, 0x6789cb1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R7 - R0 (NS); +R1 = R7 - R1 (NS); +R2 = R7 - R2 (NS); +R3 = R7 - R3 (NS); +R4 = R7 - R4 (NS); +R5 = R7 - R5 (NS); +R6 = R7 - R6 (NS); +R7 = R7 - R7 (NS); +CHECKREG r0, 0x60FEEE66; +CHECKREG r1, 0x62DCCC5A; +CHECKREG r2, 0x4C212262; +CHECKREG r3, 0x3F901060; +CHECKREG r4, 0x30FAEE5C; +CHECKREG r5, 0x1EDCAC5A; +CHECKREG r6, 0x12222262; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xd5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34f45515; +imm32 r3, 0x466b7717; +imm32 r4, 0x5567c91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445115; +imm32 r7, 0x866a7d77; +R3 = R1 - R4 (S); +R7 = R4 - R6 (S); +R2 = R7 - R7 (S); +R4 = R5 - R0 (S); +R5 = R3 - R1 (S); +R6 = R2 - R3 (S); +R0 = R0 - R2 (S); +R1 = R6 - R5 (S); +CHECKREG r0, 0xD5678911; +CHECKREG r1, 0x7C45E719; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xD921E202; +CHECKREG r4, 0x7FFFFFFF; +CHECKREG r5, 0xAA9836E5; +CHECKREG r6, 0x26DE1DFE; +CHECKREG r7, 0xE1237806; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3 = R3 - R3 (S); +R1 = R7 - R6 (S); +R4 = R1 - R2 (S); +R7 = R4 - R0 (S); +R5 = R6 - R4 (S); +R2 = R5 - R5 (S); +R6 = R2 - R1 (S); +R0 = R0 - R7 (S); +CHECKREG r0, 0x7FFFFFFF; +CHECKREG r1, 0x80000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x7FFFFFFF; +CHECKREG r6, 0x7FFFFFFF; +CHECKREG r7, 0x80000000; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rmm.s b/sim/testsuite/sim/bfin/c_dsp32alu_rmm.s new file mode 100644 index 0000000..85170a8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rmm.s @@ -0,0 +1,264 @@ +//Original:/testcases/core/c_dsp32alu_rmm/c_dsp32alu_rmm.dsp +// Spec Reference: dsp32alu dreg = -/- ( dreg, dreg) +# mach: bfin + +.include "testutils.inc" + start + + + + +// ALU operations include parallel addition, subtraction +// and 32-bit data. If an operation use a single ALU only, it uses ALU0. + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R0 -|- R0; +R1 = R0 -|- R1; +R2 = R0 -|- R2; +R3 = R0 -|- R3; +R4 = R0 -|- R4; +R5 = R0 -|- R5; +R6 = R0 -|- R6; +R7 = R0 -|- R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xD87754E3; +CHECKREG r2, 0xCBBCAAEB; +CHECKREG r3, 0xB99A88E9; +CHECKREG r4, 0xAA9976E5; +CHECKREG r5, 0x987754E3; +CHECKREG r6, 0x8BBCAAEB; +CHECKREG r7, 0x799A8889; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = R1 -|- R0; +R1 = R1 -|- R1; +R2 = R1 -|- R2; +R3 = R1 -|- R3; +R4 = R1 -|- R4; +R5 = R1 -|- R5; +R6 = R1 -|- R6; +R7 = R1 -|- R7; +CHECKREG r0, 0x12222202; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x4BBCAADB; +CHECKREG r3, 0x399A88D9; +CHECKREG r4, 0x277866D7; +CHECKREG r5, 0x155644D5; +CHECKREG r6, 0x033422D3; +CHECKREG r7, 0xF1120001; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r4, 0x456789ab; +imm32 r5, 0x6689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = R2 -|- R0; +R1 = R2 -|- R1; +R2 = R2 -|- R2; +R3 = R2 -|- R3; +R4 = R2 -|- R4; +R5 = R2 -|- R5; +R6 = R2 -|- R6; +R7 = R2 -|- R7; +CHECKREG r0, 0x01DDCBAA; +CHECKREG r1, 0xE0BBA988; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x9B9A8889; +CHECKREG r4, 0xBA997655; +CHECKREG r5, 0x99775433; +CHECKREG r6, 0xB8BCAAAB; +CHECKREG r7, 0x979A8889; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = R3 -|- R0; +R1 = R3 -|- R1; +R2 = R3 -|- R2; +R3 = R3 -|- R3; +R4 = R3 -|- R4; +R5 = R3 -|- R5; +R6 = R3 -|- R6; +R7 = R3 -|- R7; +CHECKREG r0, 0x30FFEDFC; +CHECKREG r1, 0x1EDDCBFA; +CHECKREG r2, 0x12222202; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x456789AB; +CHECKREG r5, 0x6689ABCD; +CHECKREG r6, 0x47445555; +CHECKREG r7, 0x68667777; + +imm32 r0, 0x4537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x44555535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = R4 -|- R0; +R1 = R4 -|- R1; +R2 = R4 -|- R2; +R3 = R4 -|- R3; +R4 = R4 -|- R4; +R5 = R4 -|- R5; +R6 = R4 -|- R6; +R7 = R4 -|- R7; +CHECKREG r0, 0x43410C4A; +CHECKREG r1, 0x211FEA38; +CHECKREG r2, 0x44234030; +CHECKREG r3, 0x22123E1E; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x557644A5; +CHECKREG r6, 0x3364227B; +CHECKREG r7, 0x11520061; + +imm32 r0, 0x456b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = R5 -|- R0; +R1 = R5 -|- R1; +R2 = R5 -|- R2; +R3 = R5 -|- R3; +R4 = R5 -|- R4; +R5 = R5 -|- R5; +R6 = R5 -|- R6; +R7 = R5 -|- R7; +CHECKREG r0, 0x653F8210; +CHECKREG r1, 0x4134BFEE; +CHECKREG r2, 0x6137A657; +CHECKREG r3, 0x49838827; +CHECKREG r4, 0x1223A782; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x3334E223; +CHECKREG r7, 0xEDCC9001; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = R6 -|- R0; +R1 = R6 -|- R1; +R2 = R6 -|- R2; +R3 = R6 -|- R3; +R4 = R6 -|- R4; +R5 = R6 -|- R5; +R6 = R6 -|- R6; +R7 = R6 -|- R7; +CHECKREG r0, 0xBECB572B; +CHECKREG r1, 0x9CC94509; +CHECKREG r2, 0x00ED2981; +CHECKREG r3, 0x9DCC295F; +CHECKREG r4, 0xF1FE3A3D; +CHECKREG r5, 0xBECB056B; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xEDCCA981; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = R7 -|- R0; +R1 = R7 -|- R1; +R2 = R7 -|- R2; +R3 = R7 -|- R3; +R4 = R7 -|- R4; +R5 = R7 -|- R5; +R6 = R7 -|- R6; +R7 = R7 -|- R7; +CHECKREG r0, 0x6466A64C; +CHECKREG r1, 0x4454842A; +CHECKREG r2, 0x8888C8A2; +CHECKREG r3, 0x55559FF0; +CHECKREG r4, 0x3333785E; +CHECKREG r5, 0x0123243C; +CHECKREG r6, 0x2222127A; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = R4 -|- R7 (S); +R5 = R5 -|- R5 (CO); +R2 = R6 -|- R3 (SCO); +R6 = R0 -|- R4 (S); +R0 = R1 -|- R6 (S); +R2 = R2 -|- R1 (CO); +R1 = R3 -|- R0 (CO); +R7 = R7 -|- R4 (SCO); +CHECKREG r0, 0x2202123C; +CHECKREG r1, 0x553B4464; +CHECKREG r2, 0x51FF1897; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x0000001A; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x45673991; +CHECKREG r7, 0x56651234; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = R4 -|- R0 (S); +R5 = R5 -|- R1 (SCO); +R2 = R2 -|- R2 (S); +R7 = R7 -|- R3 (CO); +R4 = R3 -|- R4 (CO); +R0 = R1 -|- R5 (S); +R1 = R0 -|- R6 (SCO); +R6 = R6 -|- R7 (SCO); +CHECKREG r0, 0x078B2BCD; +CHECKREG r1, 0x0E507DE0; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x31332DEE; +CHECKREG r4, 0x7655B899; +CHECKREG r5, 0x5FEE8000; +CHECKREG r6, 0xA2E387A2; +CHECKREG r7, 0x02097A9A; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rmp.s b/sim/testsuite/sim/bfin/c_dsp32alu_rmp.s new file mode 100644 index 0000000..b15397d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rmp.s @@ -0,0 +1,264 @@ +//Original:/testcases/core/c_dsp32alu_rmp/c_dsp32alu_rmp.dsp +// Spec Reference: dsp32alu dreg = -/+ ( dreg, dreg) +# mach: bfin + +.include "testutils.inc" + start + + + + +// ALU operations include parallel addition, subtraction +// and 32-bit data. If an operation use a single ALU only, it uses ALU0. + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R0 -|+ R0; +R1 = R0 -|+ R1; +R2 = R0 -|+ R2; +R3 = R0 -|+ R3; +R4 = R0 -|+ R4; +R5 = R0 -|+ R5; +R6 = R0 -|+ R6; +R7 = R0 -|+ R7; +CHECKREG r0, 0x00001222; +CHECKREG r1, 0xD877BD3F; +CHECKREG r2, 0xCBBC6737; +CHECKREG r3, 0xB99A8939; +CHECKREG r4, 0xAA999B3D; +CHECKREG r5, 0x9877BD3F; +CHECKREG r6, 0x8BBC6737; +CHECKREG r7, 0x799A8999; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = R1 -|+ R0; +R1 = R1 -|+ R1; +R2 = R1 -|+ R2; +R3 = R1 -|+ R3; +R4 = R1 -|+ R4; +R5 = R1 -|+ R5; +R6 = R1 -|+ R6; +R7 = R1 -|+ R7; +CHECKREG r0, 0x12223458; +CHECKREG r1, 0x0000565A; +CHECKREG r2, 0x4BBCAB7F; +CHECKREG r3, 0x399ACD81; +CHECKREG r4, 0x2778EF83; +CHECKREG r5, 0x15561185; +CHECKREG r6, 0x03343387; +CHECKREG r7, 0xF1125659; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r4, 0x456789ab; +imm32 r5, 0x6689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = R2 -|+ R0; +R1 = R2 -|+ R1; +R2 = R2 -|+ R2; +R3 = R2 -|+ R3; +R4 = R2 -|+ R4; +R5 = R2 -|+ R5; +R6 = R2 -|+ R6; +R7 = R2 -|+ R7; +CHECKREG r0, 0x01DDDF00; +CHECKREG r1, 0xE0BB0122; +CHECKREG r2, 0x0000AAAA; +CHECKREG r3, 0x9B9A2221; +CHECKREG r4, 0xBA993455; +CHECKREG r5, 0x99775677; +CHECKREG r6, 0xB8BCFFFF; +CHECKREG r7, 0x979A2221; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +R0 = R3 -|+ R0; +R1 = R3 -|+ R1; +R2 = R3 -|+ R2; +R3 = R3 -|+ R3; +R4 = R3 -|+ R4; +R5 = R3 -|+ R5; +R6 = R3 -|+ R6; +R7 = R3 -|+ R7; +CHECKREG r4, 0x456722A3; +CHECKREG r5, 0x668944C5; +CHECKREG r6, 0x4744EE4D; +CHECKREG r7, 0x6866106F; +CHECKREG r4, 0x456722A3; +CHECKREG r5, 0x668944C5; +CHECKREG r6, 0x4744EE4D; +CHECKREG r7, 0x6866106F; + +imm32 r0, 0x4537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x44555535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = R4 -|+ R0; +R1 = R4 -|+ R1; +R2 = R4 -|+ R2; +R3 = R4 -|+ R3; +R4 = R4 -|+ R4; +R5 = R4 -|+ R5; +R6 = R4 -|+ R6; +R7 = R4 -|+ R7; +CHECKREG r0, 0x43411E80; +CHECKREG r1, 0x211F4092; +CHECKREG r2, 0x4423EA9A; +CHECKREG r3, 0x2212ECAC; +CHECKREG r4, 0x00002ACA; +CHECKREG r5, 0x5576E625; +CHECKREG r6, 0x3364084F; +CHECKREG r7, 0x11522A69; + +imm32 r0, 0x456b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = R5 -|+ R0; +R1 = R5 -|+ R1; +R2 = R5 -|+ R2; +R3 = R5 -|+ R3; +R4 = R5 -|+ R4; +R5 = R5 -|+ R5; +R6 = R5 -|+ R6; +R7 = R5 -|+ R7; +CHECKREG r0, 0x653F9566; +CHECKREG r1, 0x41345788; +CHECKREG r2, 0x6137711F; +CHECKREG r3, 0x49838F4F; +CHECKREG r4, 0x12236FF4; +CHECKREG r5, 0x00001776; +CHECKREG r6, 0x33343553; +CHECKREG r7, 0xEDCC8775; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = R6 -|+ R0; +R1 = R6 -|+ R1; +R2 = R6 -|+ R2; +R3 = R6 -|+ R3; +R4 = R6 -|+ R4; +R5 = R6 -|+ R5; +R6 = R6 -|+ R6; +R7 = R6 -|+ R7; +CHECKREG r0, 0xBECBCA81; +CHECKREG r1, 0x9CC9DCA3; +CHECKREG r2, 0x00EDF82B; +CHECKREG r3, 0x9DCCF84D; +CHECKREG r4, 0xF1FEE76F; +CHECKREG r5, 0xBECB1C41; +CHECKREG r6, 0x000021AC; +CHECKREG r7, 0xEDCC782B; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R0 = R7 -|+ R0; +R1 = R7 -|+ R1; +R2 = R7 -|+ R2; +R3 = R7 -|+ R3; +R4 = R7 -|+ R4; +R5 = R7 -|+ R5; +R6 = R7 -|+ R6; +R7 = R7 -|+ R7; +CHECKREG r0, 0x6466B9A2; +CHECKREG r1, 0x4454DBC4; +CHECKREG r2, 0x8888974C; +CHECKREG r3, 0x5555BFFE; +CHECKREG r4, 0x3333E790; +CHECKREG r5, 0x01233BB2; +CHECKREG r6, 0x22224D74; +CHECKREG r7, 0x00005FEE; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = R4 -|+ R7 (S); +R5 = R5 -|+ R5 (CO); +R2 = R6 -|+ R3 (SCO); +R6 = R0 -|+ R4 (S); +R0 = R1 -|+ R6 (S); +R2 = R2 -|+ R1 (CO); +R1 = R3 -|+ R0 (CO); +R7 = R7 -|+ R4 (SCO); +CHECKREG r0, 0x22027FFF; +CHECKREG r1, 0xE7764464; +CHECKREG r2, 0xE99990E4; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x00007FFF; +CHECKREG r5, 0x16D60000; +CHECKREG r6, 0x45677FFF; +CHECKREG r7, 0x7FFF1234; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = R4 -|+ R0 (S); +R5 = R5 -|+ R1 (SCO); +R2 = R2 -|+ R2 (S); +R7 = R7 -|+ R3 (CO); +R4 = R3 -|+ R4 (CO); +R0 = R1 -|+ R5 (S); +R1 = R0 -|+ R6 (SCO); +R6 = R6 -|+ R7 (SCO); +CHECKREG r0, 0x7FFF8000; +CHECKREG r1, 0x9D7D7FFF; +CHECKREG r2, 0x00007FFF; +CHECKREG r3, 0x31338000; +CHECKREG r4, 0x3799B899; +CHECKREG r5, 0xB7888000; +CHECKREG r6, 0x7FFFD9B4; +CHECKREG r7, 0xAFF77A9A; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rp.s b/sim/testsuite/sim/bfin/c_dsp32alu_rp.s new file mode 100644 index 0000000..6984bc4 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rp.s @@ -0,0 +1,262 @@ +//Original:/testcases/core/c_dsp32alu_rp/c_dsp32alu_rp.dsp +// Spec Reference: dsp32alu +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xa5678911; +imm32 r1, 0x2a89ab1d; +imm32 r2, 0x34a45515; +imm32 r3, 0x466a7717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445a15; +imm32 r7, 0x866677a7; +R0 = R0 + R0 (NS); +R1 = R0 + R1 (NS); +R2 = R0 + R2 (NS); +R3 = R0 + R3 (NS); +R4 = R0 + R4 (NS); +R5 = R0 + R5 (NS); +R6 = R0 + R6 (NS); +R7 = R0 + R7 (NS); +CHECKREG r0, 0x4ACF1222; +CHECKREG r1, 0x7558BD3F; +CHECKREG r2, 0x7F736737; +CHECKREG r3, 0x91398939; +CHECKREG r4, 0xA0369B3D; +CHECKREG r5, 0xB258BD3F; +CHECKREG r6, 0xBF136C37; +CHECKREG r7, 0xD13589C9; + +imm32 r0, 0xabc78911; +imm32 r1, 0x27c9ab1d; +imm32 r2, 0x344c5515; +imm32 r3, 0x4666c717; +imm32 r4, 0x5567c91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445c15; +imm32 r7, 0x866677c7; +R0 = R1 + R0 (NS); +R1 = R1 + R1 (NS); +R2 = R1 + R2 (NS); +R3 = R1 + R3 (NS); +R4 = R1 + R4 (NS); +R5 = R1 + R5 (NS); +R6 = R1 + R6 (NS); +R7 = R1 + R7 (NS); +CHECKREG r0, 0xD391342E; +CHECKREG r1, 0x4F93563A; +CHECKREG r2, 0x83DFAB4F; +CHECKREG r3, 0x95FA1D51; +CHECKREG r4, 0xA4FB1F55; +CHECKREG r5, 0xB71D0157; +CHECKREG r6, 0xC3D7B24F; +CHECKREG r7, 0xD5F9CE01; + +imm32 r0, 0xdd678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46d67717; +imm32 r4, 0x5567891b; +imm32 r5, 0x678dab1d; +imm32 r6, 0x7444d515; +imm32 r7, 0x86667d77; +R0 = R2 + R0 (NS); +R1 = R2 + R1 (NS); +R2 = R2 + R2 (NS); +R3 = R2 + R3 (NS); +R4 = R2 + R4 (NS); +R5 = R2 + R5 (NS); +R6 = R2 + R6 (NS); +R7 = R2 + R7 (NS); +CHECKREG r0, 0x11ABDE26; +CHECKREG r1, 0x5BCE0032; +CHECKREG r2, 0x6888AA2A; +CHECKREG r3, 0xAF5F2141; +CHECKREG r4, 0xBDF03345; +CHECKREG r5, 0xD0165547; +CHECKREG r6, 0xDCCD7F3F; +CHECKREG r7, 0xEEEF27A1; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R3 + R0 (NS); +R1 = R3 + R1 (NS); +R2 = R3 + R2 (NS); +R3 = R3 + R3 (NS); +R4 = R3 + R4 (NS); +R5 = R3 + R5 (NS); +R6 = R3 + R6 (NS); +R7 = R3 + R7 (NS); +CHECKREG r0, 0x5BCE0028; +CHECKREG r1, 0x6DF02234; +CHECKREG r2, 0x7AAACC2C; +CHECKREG r3, 0x8CCCEE2E; +CHECKREG r4, 0xE2347749; +CHECKREG r5, 0xF456994B; +CHECKREG r6, 0x01114343; +CHECKREG r7, 0x133365A5; + +imm32 r0, 0xee678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34e45515; +imm32 r3, 0x46667717; +imm32 r4, 0x556e891b; +imm32 r5, 0x6789eb1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667e77; +R0 = R4 + R0 (NS); +R1 = R4 + R1 (NS); +R2 = R4 + R2 (NS); +R3 = R4 + R3 (NS); +R4 = R4 + R4 (NS); +R5 = R4 + R5 (NS); +R6 = R4 + R6 (NS); +R7 = R4 + R7 (NS); +CHECKREG r0, 0x43D6122C; +CHECKREG r1, 0x7CF83438; +CHECKREG r2, 0x8A52DE30; +CHECKREG r3, 0x9BD50032; +CHECKREG r4, 0xAADD1236; +CHECKREG r5, 0x1266FD53; +CHECKREG r6, 0x1F21674B; +CHECKREG r7, 0x314390AD; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R5 + R0 (NS); +R1 = R5 + R1 (NS); +R2 = R5 + R2 (NS); +R3 = R5 + R3 (NS); +R4 = R5 + R4 (NS); +R5 = R5 + R5 (NS); +R6 = R5 + R6 (NS); +R7 = R5 + R7 (NS); +CHECKREG r0, 0x7CF1342E; +CHECKREG r1, 0x8F13563A; +CHECKREG r2, 0x9BCE0032; +CHECKREG r3, 0xADF02234; +CHECKREG r4, 0xBCF13438; +CHECKREG r5, 0xCF13563A; +CHECKREG r6, 0x4357AB4F; +CHECKREG r7, 0x5579CDB1; + +imm32 r0, 0xff678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34f45515; +imm32 r3, 0x46667717; +imm32 r4, 0x556f891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444f515; +imm32 r7, 0x86667f77; +R0 = R6 + R0 (NS); +R1 = R6 + R1 (NS); +R2 = R6 + R2 (NS); +R3 = R6 + R3 (NS); +R4 = R6 + R4 (NS); +R5 = R6 + R5 (NS); +R6 = R6 + R6 (NS); +R7 = R6 + R7 (NS); +CHECKREG r0, 0x73AC7E26; +CHECKREG r1, 0x9BCEA032; +CHECKREG r2, 0xA9394A2A; +CHECKREG r3, 0xBAAB6C2C; +CHECKREG r4, 0xC9B47E30; +CHECKREG r5, 0xDBCEA032; +CHECKREG r6, 0xE889EA2A; +CHECKREG r7, 0x6EF069A1; + +imm32 r0, 0xed678911; +imm32 r1, 0x27d9ab1d; +imm32 r2, 0x344d5515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567c91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445c15; +imm32 r7, 0x866677c7; +R0 = R7 + R0 (NS); +R1 = R7 + R1 (NS); +R2 = R7 + R2 (NS); +R3 = R7 + R3 (NS); +R4 = R7 + R4 (NS); +R5 = R7 + R5 (NS); +R6 = R7 + R6 (NS); +R7 = R7 + R7 (NS); +CHECKREG r0, 0x73CE00D8; +CHECKREG r1, 0xAE4022E4; +CHECKREG r2, 0xBAB3CCDC; +CHECKREG r3, 0xCCCCEEDE; +CHECKREG r4, 0xDBCE40E2; +CHECKREG r5, 0xEDF022E4; +CHECKREG r6, 0xFAAAD3DC; +CHECKREG r7, 0x0CCCEF8E; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3 = R1 + R4 (S); +R7 = R4 + R6 (S); +R2 = R7 + R7 (S); +R4 = R5 + R0 (S); +R5 = R3 + R1 (S); +R6 = R2 + R3 (S); +R0 = R0 + R2 (S); +R1 = R6 + R5 (S); +CHECKREG r0, 0x7FFFFFFF; +CHECKREG r1, 0x7FFFFFFF; +CHECKREG r2, 0x7FFFFFFF; +CHECKREG r3, 0x7CF13438; +CHECKREG r4, 0x7CF1342E; +CHECKREG r5, 0x7FFFFFFF; +CHECKREG r6, 0x7FFFFFFF; +CHECKREG r7, 0x7FFFFFFF; + +imm32 r0, 0x55678911; +imm32 r1, 0x6a89ab1d; +imm32 r2, 0x74d45515; +imm32 r3, 0x866f7717; +imm32 r4, 0x5567c91b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R3 = R3 + R3 (S); +R1 = R7 + R6 (S); +R4 = R1 + R2 (S); +R7 = R4 + R0 (S); +R5 = R6 + R4 (S); +R2 = R5 + R5 (S); +R6 = R2 + R1 (S); +R0 = R0 + R7 (S); +CHECKREG r0, 0x7FFFFFFF; +CHECKREG r1, 0xFAAACC8C; +CHECKREG r2, 0x7FFFFFFF; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x6F7F21A1; +CHECKREG r5, 0x7FFFFFFF; +CHECKREG r6, 0x7AAACC8B; +CHECKREG r7, 0x7FFFFFFF; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rpm.s b/sim/testsuite/sim/bfin/c_dsp32alu_rpm.s new file mode 100644 index 0000000..ebdec07 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rpm.s @@ -0,0 +1,264 @@ +//Original:/testcases/core/c_dsp32alu_rpm/c_dsp32alu_rpm.dsp +// Spec Reference: dsp32alu dreg = +/- ( dreg, dreg) +# mach: bfin + +.include "testutils.inc" + start + + + + +// ALU operations include parallel addition, subtraction +// and 32-bit data. If an operation use a single ALU only, it uses ALU0. + +imm32 r0, 0x65678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34845515; +imm32 r3, 0x46697717; +imm32 r4, 0x5567191b; +imm32 r5, 0x6789a31d; +imm32 r6, 0x74445545; +imm32 r7, 0x86667779; +R0 = R0 +|- R0; +R1 = R0 +|- R1; +R2 = R0 +|- R2; +R3 = R0 +|- R3; +R4 = R0 +|- R4; +R5 = R0 +|- R5; +R6 = R0 +|- R6; +R7 = R0 +|- R7; +CHECKREG r0, 0xCACE0000; +CHECKREG r1, 0xF25754E3; +CHECKREG r2, 0xFF52AAEB; +CHECKREG r3, 0x113788E9; +CHECKREG r4, 0x2035E6E5; +CHECKREG r5, 0x32575CE3; +CHECKREG r6, 0x3F12AABB; +CHECKREG r7, 0x51348887; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = R1 +|- R0; +R1 = R1 +|- R1; +R2 = R1 +|- R2; +R3 = R1 +|- R3; +R4 = R1 +|- R4; +R5 = R1 +|- R5; +R6 = R1 +|- R6; +R7 = R1 +|- R7; +CHECKREG r0, 0x3CF02202; +CHECKREG r1, 0x4F120000; +CHECKREG r2, 0x0356AADB; +CHECKREG r3, 0x157888D9; +CHECKREG r4, 0x279A66D7; +CHECKREG r5, 0x39BC44D5; +CHECKREG r6, 0x4BDE22D3; +CHECKREG r7, 0x5E000001; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r4, 0x456789ab; +imm32 r5, 0x6689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = R2 +|- R0; +R1 = R2 +|- R1; +R2 = R2 +|- R2; +R3 = R2 +|- R3; +R4 = R2 +|- R4; +R5 = R2 +|- R5; +R6 = R2 +|- R6; +R7 = R2 +|- R7; +CHECKREG r0, 0x84ABCBAA; +CHECKREG r1, 0xA5CDA988; +CHECKREG r2, 0x86880000; +CHECKREG r3, 0xEAEE8889; +CHECKREG r4, 0xCBEF7655; +CHECKREG r5, 0xED115433; +CHECKREG r6, 0xCDCCAAAB; +CHECKREG r7, 0xEEEE8889; + +imm32 r0, 0xa567892b; +imm32 r1, 0xaa89ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6a67727; +imm32 r0, 0x9a67892b; +imm32 r1, 0xa7a9ab2d; +imm32 r2, 0xb44a5525; +imm32 r3, 0xc666a727; +R0 = R3 +|- R0; +R1 = R3 +|- R1; +R2 = R3 +|- R2; +R3 = R3 +|- R3; +R4 = R3 +|- R4; +R5 = R3 +|- R5; +R6 = R3 +|- R6; +R7 = R3 +|- R7; +CHECKREG r0, 0x60CD1DFC; +CHECKREG r1, 0x6E0FFBFA; +CHECKREG r2, 0x7AB05202; +CHECKREG r3, 0x8CCC0000; +CHECKREG r4, 0x58BB89AB; +CHECKREG r5, 0x79DDABCD; +CHECKREG r6, 0x5A985555; +CHECKREG r7, 0x7BBA7777; + +imm32 r0, 0x4537891b; +imm32 r1, 0x6759ab2d; +imm32 r2, 0x44555535; +imm32 r3, 0x66665747; +imm32 r4, 0x88789565; +imm32 r5, 0xaa8abb5b; +imm32 r6, 0xcc9cdd85; +imm32 r7, 0xeeaeff9f; +R0 = R4 +|- R0; +R1 = R4 +|- R1; +R2 = R4 +|- R2; +R3 = R4 +|- R3; +R4 = R4 +|- R4; +R5 = R4 +|- R5; +R6 = R4 +|- R6; +R7 = R4 +|- R7; +CHECKREG r0, 0xCDAF0C4A; +CHECKREG r1, 0xEFD1EA38; +CHECKREG r2, 0xCCCD4030; +CHECKREG r3, 0xEEDE3E1E; +CHECKREG r4, 0x10F00000; +CHECKREG r5, 0xBB7A44A5; +CHECKREG r6, 0xDD8C227B; +CHECKREG r7, 0xFF9E0061; + +imm32 r0, 0x456b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = R5 +|- R0; +R1 = R5 +|- R1; +R2 = R5 +|- R2; +R3 = R5 +|- R3; +R4 = R5 +|- R4; +R5 = R5 +|- R5; +R6 = R5 +|- R6; +R7 = R5 +|- R7; +CHECKREG r0, 0xF0158210; +CHECKREG r1, 0x1420BFEE; +CHECKREG r2, 0xF41DA657; +CHECKREG r3, 0x0BD18827; +CHECKREG r4, 0x4331A782; +CHECKREG r5, 0x55540000; +CHECKREG r6, 0x2220E223; +CHECKREG r7, 0x67889001; + +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R0 = R6 +|- R0; +R1 = R6 +|- R1; +R2 = R6 +|- R2; +R3 = R6 +|- R3; +R4 = R6 +|- R4; +R5 = R6 +|- R5; +R6 = R6 +|- R6; +R7 = R6 +|- R7; +CHECKREG r0, 0x4999572B; +CHECKREG r1, 0x6B9B4509; +CHECKREG r2, 0x07772981; +CHECKREG r3, 0x6A98295F; +CHECKREG r4, 0x16663A3D; +CHECKREG r5, 0x4999056B; +CHECKREG r6, 0x08640000; +CHECKREG r7, 0x1A98A981; + +imm32 r0, 0xb76789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x2b456755; +imm32 r3, 0x56789007; +imm32 r4, 0x78bab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcdbff7; +R0 = R7 +|- R0; +R1 = R7 +|- R1; +R2 = R7 +|- R2; +R3 = R7 +|- R3; +R4 = R7 +|- R4; +R5 = R7 +|- R5; +R6 = R7 +|- R6; +R7 = R7 +|- R7; +CHECKREG r0, 0x6334364C; +CHECKREG r1, 0x1346142A; +CHECKREG r2, 0xD71258A2; +CHECKREG r3, 0x02452FF0; +CHECKREG r4, 0x2487085E; +CHECKREG r5, 0x5677B43C; +CHECKREG r6, 0x3578A27A; +CHECKREG r7, 0x579A0000; +imm32 r0, 0x456739ab; +imm32 r1, 0x67694bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x66666777; +imm32 r4, 0x12345699; +imm32 r5, 0x45678b6b; +imm32 r6, 0x043290d6; +imm32 r7, 0x1234567f; +R4 = R4 +|- R7 (S); +R5 = R5 +|- R5 (CO); +R2 = R6 +|- R3 (SCO); +R6 = R0 +|- R4 (S); +R0 = R1 +|- R6 (S); +R2 = R2 +|- R1 (CO); +R1 = R3 +|- R0 (CO); +R7 = R7 +|- R4 (SCO); +CHECKREG r0, 0x7FFF123C; +CHECKREG r1, 0x553BE665; +CHECKREG r2, 0x1ECBE769; +CHECKREG r3, 0x66666777; +CHECKREG r4, 0x2468001A; +CHECKREG r5, 0x00008ACE; +CHECKREG r6, 0x69CF3991; +CHECKREG r7, 0x5665369C; + +imm32 r0, 0xb76789ab; +imm32 r1, 0x6b79abcd; +imm32 r2, 0x2b456755; +imm32 r3, 0x56b89007; +imm32 r4, 0x78bab799; +imm32 r5, 0xaaab0bbb; +imm32 r6, 0x89abbd7d; +imm32 r7, 0xabcd2bf7; +R3 = R4 +|- R0 (S); +R5 = R5 +|- R1 (SCO); +R2 = R2 +|- R2 (S); +R7 = R7 +|- R3 (CO); +R4 = R3 +|- R4 (CO); +R0 = R1 +|- R5 (S); +R1 = R0 +|- R6 (SCO); +R6 = R6 +|- R7 (SCO); +CHECKREG r0, 0x7FFF95A9; +CHECKREG r1, 0xD82C09AA; +CHECKREG r2, 0x568A0000; +CHECKREG r3, 0x30212DEE; +CHECKREG r4, 0x7655A8DB; +CHECKREG r5, 0x5FEE1624; +CHECKREG r6, 0xE18F87B4; +CHECKREG r7, 0xFE09DBEE; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rpp.s b/sim/testsuite/sim/bfin/c_dsp32alu_rpp.s new file mode 100644 index 0000000..5a69267 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rpp.s @@ -0,0 +1,266 @@ +//Original:/testcases/core/c_dsp32alu_rpp/c_dsp32alu_rpp.dsp +// Spec Reference: dsp32alu dreg = +/+ ( dreg, dreg) +# mach: bfin + +.include "testutils.inc" + start + + + + +// ALU operations include parallel addition, subtraction +// and 32-bit data. If an operation use a single ALU only, it uses ALU0. + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +R0 = R0 +|+ R0; +R1 = R0 +|+ R1; +R2 = R0 +|+ R2; +R3 = R0 +|+ R3; +R4 = R0 +|+ R4; +R5 = R0 +|+ R5; +R6 = R0 +|+ R6; +R7 = R0 +|+ R7; +CHECKREG r0, 0x2ACE1222; +CHECKREG r1, 0x5257BD3F; +CHECKREG r2, 0x5F126737; +CHECKREG r3, 0x71348939; +CHECKREG r4, 0x80359B3D; +CHECKREG r5, 0x9257BD3F; +CHECKREG r6, 0x9F126737; +CHECKREG r7, 0xB1348999; + +imm32 r0, 0x9567892b; +imm32 r1, 0xa789ab2d; +imm32 r2, 0xb4445525; +imm32 r3, 0xc6667727; +imm32 r4, 0xd8889929; +imm32 r5, 0xeaaabb2b; +imm32 r6, 0xfcccdd2d; +imm32 r7, 0x0eeeffff; +R0 = R1 +|+ R0; +R1 = R1 +|+ R1; +R2 = R1 +|+ R2; +R3 = R1 +|+ R3; +R4 = R1 +|+ R4; +R5 = R1 +|+ R5; +R6 = R1 +|+ R6; +R7 = R1 +|+ R7; +CHECKREG r0, 0x3CF03458; +CHECKREG r1, 0x4F12565A; +CHECKREG r2, 0x0356AB7F; +CHECKREG r3, 0x1578CD81; +CHECKREG r4, 0x279AEF83; +CHECKREG r5, 0x39BC1185; +CHECKREG r6, 0x4BDE3387; +CHECKREG r7, 0x5E005659; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r4, 0x456789ab; +imm32 r5, 0x6689abcd; +imm32 r6, 0x47445555; +imm32 r7, 0x68667777; +R0 = R2 +|+ R0; +R1 = R2 +|+ R1; +R2 = R2 +|+ R2; +R3 = R2 +|+ R3; +R4 = R2 +|+ R4; +R5 = R2 +|+ R5; +R6 = R2 +|+ R6; +R7 = R2 +|+ R7; +CHECKREG r0, 0x84ABDF00; +CHECKREG r1, 0xA5CD0122; +CHECKREG r2, 0x8688AAAA; +CHECKREG r3, 0xEAEE2221; +CHECKREG r4, 0xCBEF3455; +CHECKREG r5, 0xED115677; +CHECKREG r6, 0xCDCCFFFF; +CHECKREG r7, 0xEEEE2221; + +imm32 r0, 0xd567892b; +imm32 r1, 0xad89ab2d; +imm32 r2, 0xb4d45525; +imm32 r3, 0xc66d7727; +imm32 r0, 0x9567d92b; +imm32 r1, 0xa789ad2d; +imm32 r2, 0xb44455d5; +imm32 r3, 0xc666772d; +R0 = R3 +|+ R0; +R1 = R3 +|+ R1; +R2 = R3 +|+ R2; +R3 = R3 +|+ R3; +R4 = R3 +|+ R4; +R5 = R3 +|+ R5; +R6 = R3 +|+ R6; +R7 = R3 +|+ R7; +CHECKREG r0, 0x5BCD5058; +CHECKREG r1, 0x6DEF245A; +CHECKREG r2, 0x7AAACD02; +CHECKREG r3, 0x8CCCEE5A; +CHECKREG r4, 0x58BB22AF; +CHECKREG r5, 0x79DD44D1; +CHECKREG r6, 0x5A98EE59; +CHECKREG r7, 0x7BBA107B; + +imm32 r0, 0x4577891b; +imm32 r1, 0x6779ab2d; +imm32 r2, 0x44755535; +imm32 r3, 0x66765747; +imm32 r4, 0x88779565; +imm32 r5, 0xaa7abb5b; +imm32 r6, 0xcc97dd85; +imm32 r7, 0xeeae7f9f; +R0 = R4 +|+ R0; +R1 = R4 +|+ R1; +R2 = R4 +|+ R2; +R3 = R4 +|+ R3; +R4 = R4 +|+ R4; +R5 = R4 +|+ R5; +R6 = R4 +|+ R6; +R7 = R4 +|+ R7; +CHECKREG r0, 0xCDEE1E80; +CHECKREG r1, 0xEFF04092; +CHECKREG r2, 0xCCECEA9A; +CHECKREG r3, 0xEEEDECAC; +CHECKREG r4, 0x10EE2ACA; +CHECKREG r5, 0xBB68E625; +CHECKREG r6, 0xDD85084F; +CHECKREG r7, 0xFF9CAA69; + +imm32 r0, 0x456b89ab; +imm32 r1, 0x69764bcd; +imm32 r2, 0x49736564; +imm32 r3, 0x61278394; +imm32 r4, 0x98876439; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0xcccc1ddd; +imm32 r7, 0x12346fff; +R0 = R5 +|+ R0; +R1 = R5 +|+ R1; +R2 = R5 +|+ R2; +R3 = R5 +|+ R3; +R4 = R5 +|+ R4; +R5 = R5 +|+ R5; +R6 = R5 +|+ R6; +R7 = R5 +|+ R7; +CHECKREG r0, 0xF0159566; +CHECKREG r1, 0x14205788; +CHECKREG r2, 0xF41D711F; +CHECKREG r3, 0x0BD18F4F; +CHECKREG r4, 0x43316FF4; +CHECKREG r5, 0x55541776; +CHECKREG r6, 0x22203553; +CHECKREG r7, 0x67888775; + +imm32 r0, 0xaa6739ab; +imm32 r1, 0x67dd4bcd; +imm32 r2, 0x03456755; +imm32 r3, 0x6b66bb77; +imm32 r4, 0x12345699; +imm32 r5, 0x45b78b6b; +imm32 r6, 0x043b90d6; +imm32 r7, 0x12b4bb7f; +R0 = R6 +|+ R0; +R1 = R6 +|+ R1; +R2 = R6 +|+ R2; +R3 = R6 +|+ R3; +R4 = R6 +|+ R4; +R5 = R6 +|+ R5; +R6 = R6 +|+ R6; +R7 = R6 +|+ R7; +CHECKREG r0, 0xAEA2CA81; +CHECKREG r1, 0x6C18DCA3; +CHECKREG r2, 0x0780F82B; +CHECKREG r3, 0x6FA14C4D; +CHECKREG r4, 0x166FE76F; +CHECKREG r5, 0x49F21C41; +CHECKREG r6, 0x087621AC; +CHECKREG r7, 0x1B2ADD2B; + +imm32 r0, 0x976789ab; +imm32 r1, 0x6979abcd; +imm32 r2, 0x23956755; +imm32 r3, 0x56799007; +imm32 r4, 0x789a9799; +imm32 r5, 0xaaaa09bb; +imm32 r6, 0x89ab1d9d; +imm32 r7, 0xabcd2ff9; +R0 = R7 +|+ R0; +R1 = R7 +|+ R1; +R2 = R7 +|+ R2; +R3 = R7 +|+ R3; +R4 = R7 +|+ R4; +R5 = R7 +|+ R5; +R6 = R7 +|+ R6; +R7 = R7 +|+ R7; +CHECKREG r0, 0x4334B9A4; +CHECKREG r1, 0x1546DBC6; +CHECKREG r2, 0xCF62974E; +CHECKREG r3, 0x0246C000; +CHECKREG r4, 0x2467C792; +CHECKREG r5, 0x567739B4; +CHECKREG r6, 0x35784D96; +CHECKREG r7, 0x579A5FF2; + +imm32 r0, 0x856739ab; +imm32 r1, 0x87694bcd; +imm32 r2, 0x08856755; +imm32 r3, 0x66686777; +imm32 r4, 0x12385699; +imm32 r5, 0x4567886b; +imm32 r6, 0x04329086; +imm32 r7, 0x12345678; +R4 = R4 +|+ R7 (S); +R5 = R5 +|+ R5 (CO); +R2 = R6 +|+ R3 (SCO); +R6 = R0 +|+ R4 (S); +R0 = R1 +|+ R6 (S); +R2 = R2 +|+ R1 (CO); +R1 = R3 +|+ R0 (CO); +R7 = R7 +|+ R4 (SCO); +CHECKREG r0, 0x80007FFF; +CHECKREG r1, 0xE776E668; +CHECKREG r2, 0xB6677F66; +CHECKREG r3, 0x66686777; +CHECKREG r4, 0x246C7FFF; +CHECKREG r5, 0x10D68ACE; +CHECKREG r6, 0xA9D37FFF; +CHECKREG r7, 0x7FFF36A0; + +imm32 r0, 0x476789ab; +imm32 r1, 0x6779abcd; +imm32 r2, 0x23456755; +imm32 r3, 0x56789007; +imm32 r4, 0x789ab799; +imm32 r5, 0xaaaa0bbb; +imm32 r6, 0x89ab1d7d; +imm32 r7, 0xabcd2ff7; +R3 = R4 +|+ R0 (S); +R5 = R5 +|+ R1 (SCO); +R2 = R2 +|+ R2 (S); +R7 = R7 +|+ R3 (CO); +R4 = R3 +|+ R4 (CO); +R0 = R1 +|+ R5 (S); +R1 = R0 +|+ R6 (SCO); +R6 = R6 +|+ R7 (SCO); +CHECKREG r0, 0x1F01BDF0; +CHECKREG r1, 0xDB6DA8AC; +CHECKREG r2, 0x468A7FFF; +CHECKREG r3, 0x7FFF8000; +CHECKREG r4, 0x3799F899; +CHECKREG r5, 0xB7881223; +CHECKREG r6, 0x49498000; +CHECKREG r7, 0xAFF72BCC; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rr_lph_a1a0.s b/sim/testsuite/sim/bfin/c_dsp32alu_rr_lph_a1a0.s new file mode 100644 index 0000000..5ce3598 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rr_lph_a1a0.s @@ -0,0 +1,33 @@ +//Original:/testcases/core/c_dsp32alu_rr_lph_a1a0/c_dsp32alu_rr_lph_a1a0.dsp +// Spec Reference: dsp32alu (dregs, dregs) = L + H, L + H (a1, a0) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x25678911; +imm32 r1, 0x0029ab2d; +imm32 r2, 0x00145535; +imm32 r3, 0xf6567747; +imm32 r4, 0xe566895b; +imm32 r5, 0x67897b6d; +imm32 r6, 0xb4445875; +imm32 r7, 0x86667797; +A1 = R1; +A0 = R0; + +R2 = A1.L + A1.H, R3 = A0.L + A0.H; +R4 = A1.L + A1.H, R5 = A0.L + A0.H; +R6 = A1.L + A1.H, R7 = A0.L + A0.H; +CHECKREG r2, 0xFFFFAB56; +CHECKREG r3, 0xFFFFAE78; +CHECKREG r4, 0xFFFFAB56; +CHECKREG r5, 0xFFFFAE78; +CHECKREG r6, 0xFFFFAB56; +CHECKREG r7, 0xFFFFAE78; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrpm.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrpm.s new file mode 100644 index 0000000..2ced758 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rrpm.s @@ -0,0 +1,265 @@ +//Original:/testcases/core/c_dsp32alu_rrpm/c_dsp32alu_rrpm.dsp +// Spec Reference: dsp32alu (dreg, dreg) +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x75678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34745515; +imm32 r3, 0x46677717; +imm32 r0, 0x5567a91b; +imm32 r1, 0x6789aa1d; +imm32 r2, 0x744455a5; +imm32 r3, 0x8666777a; +R0 = R0 + R0, R7 = R0 - R0 (NS); +R1 = R0 + R1, R6 = R0 - R1 (NS); +R2 = R0 + R2, R5 = R0 - R2 (NS); +R3 = R0 + R3, R4 = R0 - R3 (NS); +R4 = R0 + R4, R3 = R0 - R4 (NS); +R5 = R0 + R5, R2 = R0 - R5 (NS); +R6 = R0 + R6, R1 = R0 - R6 (NS); +R7 = R0 + R7, R0 = R0 - R7 (NS); +CHECKREG r0, 0xAACF5236; +CHECKREG r1, 0x6789AA1D; +CHECKREG r2, 0x744455A5; +CHECKREG r3, 0x8666777A; +CHECKREG r4, 0xCF382CF2; +CHECKREG r5, 0xE15A4EC7; +CHECKREG r6, 0xEE14FA4F; +CHECKREG r7, 0xAACF5236; + +imm32 r0, 0x4567892b; +imm32 r1, 0x4489ab2d; +imm32 r2, 0x54445525; +imm32 r3, 0x66645727; +imm32 r4, 0x78889629; +imm32 r5, 0x8aaabb6b; +imm32 r6, 0x9cccdd2d; +imm32 r7, 0x0eee3fff; +R0 = R1 + R0, R7 = R1 - R0 (NS); +R1 = R1 + R1, R6 = R1 - R1 (NS); +R2 = R1 + R2, R5 = R1 - R2 (NS); +R3 = R1 + R3, R4 = R1 - R3 (NS); +R4 = R1 + R4, R3 = R1 - R4 (NS); +R5 = R1 + R5, R2 = R1 - R5 (NS); +R6 = R1 + R6, R1 = R1 - R6 (NS); +R7 = R1 + R7, R0 = R1 - R7 (NS); +CHECKREG r0, 0x89F13458; +CHECKREG r1, 0x8913565A; +CHECKREG r2, 0x54445525; +CHECKREG r3, 0x66645727; +CHECKREG r4, 0xABC2558D; +CHECKREG r5, 0xBDE2578F; +CHECKREG r6, 0x8913565A; +CHECKREG r7, 0x8835785C; + + +imm32 r0, 0x496789ab; +imm32 r1, 0x6489abcd; +imm32 r2, 0x4b445555; +imm32 r3, 0x6c647777; +imm32 r4, 0x8d889999; +imm32 r5, 0x1eaa4bbb; +imm32 r6, 0x2fccd44d; +imm32 r7, 0x31eefff4; +R0 = R2 + R0, R7 = R2 - R0 (NS); +R1 = R2 + R1, R6 = R2 - R1 (NS); +R2 = R2 + R2, R5 = R2 - R2 (NS); +R3 = R2 + R3, R4 = R2 - R3 (NS); +R4 = R2 + R4, R3 = R2 - R4 (NS); +R5 = R2 + R5, R2 = R2 - R5 (NS); +R6 = R2 + R6, R1 = R2 - R6 (NS); +R7 = R2 + R7, R0 = R2 - R7 (NS); +CHECKREG r0, 0x94ABDF00; +CHECKREG r1, 0xAFCE0122; +CHECKREG r2, 0x9688AAAA; +CHECKREG r3, 0x6C647777; +CHECKREG r4, 0xC0ACDDDD; +CHECKREG r5, 0x9688AAAA; +CHECKREG r6, 0x7D435432; +CHECKREG r7, 0x98657654; + +imm32 r0, 0xa537891b; +imm32 r1, 0x6a59ab2d; +imm32 r2, 0x44a55535; +imm32 r3, 0x166a5747; +imm32 r4, 0x6878a565; +imm32 r5, 0x7a8aba5b; +imm32 r6, 0x8c9cdd85; +imm32 r7, 0x9eaeffaf; +R0 = R3 + R0, R7 = R3 - R0 (NS); +R1 = R3 + R1, R6 = R3 - R1 (NS); +R2 = R3 + R2, R5 = R3 - R2 (NS); +R3 = R3 + R3, R4 = R3 - R3 (NS); +R4 = R3 + R4, R3 = R3 - R4 (NS); +R5 = R3 + R5, R2 = R3 - R5 (NS); +R6 = R3 + R6, R1 = R3 - R6 (NS); +R7 = R3 + R7, R0 = R3 - R7 (NS); +CHECKREG r0, 0xBBA1E062; +CHECKREG r1, 0x80C40274; +CHECKREG r2, 0x5B0FAC7C; +CHECKREG r3, 0x2CD4AE8E; +CHECKREG r4, 0x2CD4AE8E; +CHECKREG r5, 0xFE99B0A0; +CHECKREG r6, 0xD8E55AA8; +CHECKREG r7, 0x9E077CBA; + +imm32 r0, 0x15678911; +imm32 r1, 0x9789ab1d; +imm32 r2, 0x94445515; +imm32 r3, 0x96667717; +imm32 r0, 0x5267891b; +imm32 r1, 0x67a9ab1d; +imm32 r2, 0x744c5515; +imm32 r3, 0x8666d777; +R0 = R4 + R0, R7 = R4 - R0 (NS); +R1 = R4 + R1, R6 = R4 - R1 (NS); +R2 = R4 + R2, R5 = R4 - R2 (NS); +R3 = R4 + R3, R4 = R4 - R3 (NS); +R4 = R4 + R4, R3 = R4 - R4 (NS); +R5 = R4 + R5, R2 = R4 - R5 (NS); +R6 = R4 + R6, R1 = R4 - R6 (NS); +R7 = R4 + R7, R0 = R4 - R7 (NS); +CHECKREG r0, 0x726E88BB; +CHECKREG r1, 0x87B0AABD; +CHECKREG r2, 0x945354B5; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x4CDBAE2E; +CHECKREG r5, 0x056407A7; +CHECKREG r6, 0x1206B19F; +CHECKREG r7, 0x2748D3A1; + +imm32 r0, 0xa567892b; +imm32 r1, 0x4a89ab2d; +imm32 r2, 0x54a45525; +imm32 r3, 0x666d7727; +imm32 r4, 0x7888d929; +imm32 r5, 0x8aaabe2b; +imm32 r6, 0x9cccdd2d; +imm32 r7, 0x0eeeffef; +R0 = R5 + R0, R7 = R5 - R0 (NS); +R1 = R5 + R1, R6 = R5 - R1 (NS); +R2 = R5 + R2, R5 = R5 - R2 (NS); +R3 = R5 + R3, R4 = R5 - R3 (NS); +R4 = R5 + R4, R3 = R5 - R4 (NS); +R5 = R5 + R5, R2 = R5 - R5 (NS); +R6 = R5 + R6, R1 = R5 - R6 (NS); +R7 = R5 + R7, R0 = R5 - R7 (NS); +CHECKREG r0, 0x86C99D0C; +CHECKREG r1, 0x2BEBBF0E; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x666D7727; +CHECKREG r4, 0x059F5AE5; +CHECKREG r5, 0x6C0CD20C; +CHECKREG r6, 0xAC2DE50A; +CHECKREG r7, 0x5150070C; + + +imm32 r0, 0x496789ab; +imm32 r1, 0x6489abcd; +imm32 r2, 0x4b445555; +imm32 r3, 0x6c647777; +imm32 r4, 0x8d889999; +imm32 r5, 0x1eaa4bbb; +imm32 r6, 0x2fccd44d; +imm32 r7, 0x31eefff4; +R0 = R6 + R0, R7 = R6 - R0 (NS); +R1 = R6 + R1, R6 = R6 - R1 (NS); +R2 = R6 + R2, R5 = R6 - R2 (NS); +R3 = R6 + R3, R4 = R6 - R3 (NS); +R4 = R6 + R4, R3 = R6 - R4 (NS); +R5 = R6 + R5, R2 = R6 - R5 (NS); +R6 = R6 + R6, R1 = R6 - R6 (NS); +R7 = R6 + R7, R0 = R6 - R7 (NS); +CHECKREG r0, 0xB021065E; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x4B445555; +CHECKREG r3, 0x6C647777; +CHECKREG r4, 0x2A21D989; +CHECKREG r5, 0x4B41FBAB; +CHECKREG r6, 0x96865100; +CHECKREG r7, 0x7CEB9BA2; + +imm32 r0, 0xe537891b; +imm32 r1, 0xe759ab2d; +imm32 r2, 0x4e555535; +imm32 r3, 0x16e65747; +imm32 r4, 0x687e9565; +imm32 r5, 0x7a8aeb5b; +imm32 r6, 0x8c9cdd85; +imm32 r7, 0x9eaefe9f; +R0 = R7 + R0, R7 = R7 - R0 (NS); +R1 = R7 + R1, R6 = R7 - R1 (NS); +R2 = R7 + R2, R5 = R7 - R2 (NS); +R3 = R7 + R3, R4 = R7 - R3 (NS); +R4 = R7 + R4, R3 = R7 - R4 (NS); +R5 = R7 + R5, R2 = R7 - R5 (NS); +R6 = R7 + R6, R1 = R7 - R6 (NS); +R7 = R7 + R7, R0 = R7 - R7 (NS); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xE759AB2D; +CHECKREG r2, 0x4E555535; +CHECKREG r3, 0x16E65747; +CHECKREG r4, 0x5C0893C1; +CHECKREG r5, 0x249995D3; +CHECKREG r6, 0x8B953FDB; +CHECKREG r7, 0x72EEEB08; + +imm32 r0, 0x496789ab; +imm32 r1, 0x6489abcd; +imm32 r2, 0x4b445555; +imm32 r3, 0x6c647777; +imm32 r4, 0x8d889999; +imm32 r5, 0x1eaa4bbb; +imm32 r6, 0x2fccd44d; +imm32 r7, 0x31eefff4; +R2 = R4 + R0, R7 = R4 - R0 (S); +R3 = R7 + R1, R6 = R7 - R1 (NS); +R4 = R0 + R2, R5 = R0 - R2 (S); +R5 = R4 + R3, R4 = R4 - R3 (NS); +R6 = R2 + R4, R3 = R2 - R4 (S); +R7 = R3 + R5, R2 = R3 - R5 (NS); +R0 = R1 + R6, R1 = R1 - R6 (S); +R1 = R5 + R7, R0 = R5 - R7 (S); +CHECKREG r0, 0x64DDDDDE; +CHECKREG r1, 0xA4E4D39A; +CHECKREG r2, 0x9640C966; +CHECKREG r3, 0x9B222222; +CHECKREG r4, 0x3BCE0122; +CHECKREG r5, 0x04E158BC; +CHECKREG r6, 0x12BE2466; +CHECKREG r7, 0xA0037ADE; + +imm32 r0, 0xa537891b; +imm32 r1, 0x6d59ab2d; +imm32 r2, 0x4f555535; +imm32 r3, 0x16c65747; +imm32 r4, 0x687c9565; +imm32 r5, 0x7a8acb5b; +imm32 r6, 0x8c9cdc85; +imm32 r7, 0x9eaefb9f; +R4 = R3 + R0, R1 = R3 - R0 (S); +R5 = R6 + R1, R2 = R6 - R1 (S); +R6 = R7 + R2, R3 = R7 - R2 (S); +R7 = R0 + R3, R4 = R0 - R3 (NS); +R0 = R2 + R4, R5 = R2 - R4 (S); +R1 = R1 + R5, R6 = R1 - R5 (S); +R2 = R5 + R6, R7 = R5 - R6 (NS); +R3 = R4 + R7, R0 = R4 - R7 (S); +CHECKREG r0, 0x052876A0; +CHECKREG r1, 0x6B0640B0; +CHECKREG r2, 0x718ECE2C; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x86888D7C; +CHECKREG r5, 0xF9777284; +CHECKREG r6, 0x78175BA8; +CHECKREG r7, 0x816016DC; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrpm_aa.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrpm_aa.s new file mode 100644 index 0000000..7c1e3a3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rrpm_aa.s @@ -0,0 +1,70 @@ +//Original:/testcases/core/c_dsp32alu_rrpm_aa/c_dsp32alu_rrpm_aa.dsp +// Spec Reference: dsp32alu (dregs, dregs) = +/- (a, a) amod1 +# mach: bfin + +.include "testutils.inc" + start + + + +A1 = A0 = 0; + +imm32 r0, 0x75678911; +imm32 r1, 0xa789ab2d; +imm32 r2, 0x34745515; +imm32 r3, 0x46677757; +imm32 r4, 0xb567a96b; +imm32 r5, 0x6789aa1d; +imm32 r6, 0x744455a5; +imm32 r7, 0x8666777a; +A0 = R0; +A1 = R1; + +R0 = A1 + A0, R7 = A1 - A0 (NS); +R1 = A0 + A1, R6 = A0 - A1 (NS); +R2 = A1 + A0, R5 = A1 - A0 (NS); +R3 = A0 + A1, R4 = A0 - A1 (NS); +R4 = A1 + A0, R0 = A1 - A0 (NS); +R5 = A0 + A1, R1 = A0 - A1 (NS); +R6 = A0 + A1, R2 = A0 - A1 (NS); +R7 = A1 + A0, R3 = A1 - A0 (NS); +CHECKREG r0, 0x3222221C; +CHECKREG r1, 0xCDDDDDE4; +CHECKREG r2, 0xCDDDDDE4; +CHECKREG r3, 0x3222221C; +CHECKREG r4, 0x1CF1343E; +CHECKREG r5, 0x1CF1343E; +CHECKREG r6, 0x1CF1343E; +CHECKREG r7, 0x1CF1343E; + +imm32 r0, 0x8537891b; +imm32 r1, 0x3759ab2d; +imm32 r2, 0x4e555535; +imm32 r3, 0x16e65747; +imm32 r4, 0x687e9565; +imm32 r5, 0x7a8aeb5b; +imm32 r6, 0x8c9cdd85; +imm32 r7, 0x9eaefe9f; +A0 = R0; +A1 = R1; +R3 = A1 + A0, R7 = A1 - A0 (S); +R4 = A0 + A1, R6 = A0 - A1 (S); +R5 = A1 + A0, R4 = A1 - A0 (S); +R6 = A0 + A1, R5 = A0 - A1 (S); +R7 = A1 + A0, R3 = A1 - A0 (S); +R0 = A0 + A1, R2 = A0 - A1 (S); +R1 = A0 + A1, R0 = A0 - A1 (S); +R2 = A1 + A0, R1 = A1 - A0 (S); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x7FFFFFFF; +CHECKREG r2, 0xBC913448; +CHECKREG r3, 0x7FFFFFFF; +CHECKREG r4, 0x7FFFFFFF; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0xBC913448; +CHECKREG r7, 0xBC913448; + + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp.s new file mode 100644 index 0000000..6951a9f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp.s @@ -0,0 +1,263 @@ +//Original:/testcases/core/c_dsp32alu_rrpmmp/c_dsp32alu_rrpmmp.dsp +// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) amod0 +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x35678911; +imm32 r1, 0x2489ab1d; +imm32 r2, 0x34545515; +imm32 r3, 0x46667717; +imm32 r0, 0x5567891b; +imm32 r1, 0x67889b1d; +imm32 r2, 0x74445915; +imm32 r3, 0x86667797; +R0 = R0 +|- R0 , R7 = R0 -|+ R0; +R1 = R0 +|- R1 , R6 = R0 -|+ R1; +R2 = R0 +|- R2 , R5 = R0 -|+ R2; +R3 = R0 +|- R3 , R4 = R0 -|+ R3; +R4 = R0 +|- R4 , R3 = R0 -|+ R4; +R5 = R0 +|- R5 , R2 = R0 -|+ R5; +R6 = R0 +|- R6 , R1 = R0 -|+ R6; +R7 = R0 +|- R7 , R0 = R0 -|+ R7; +CHECKREG r0, 0xAACE1236; +CHECKREG r1, 0x67889B1D; +CHECKREG r2, 0x74445915; +CHECKREG r3, 0x86667797; +CHECKREG r4, 0xCF368869; +CHECKREG r5, 0xE158A6EB; +CHECKREG r6, 0xEE1464E3; +CHECKREG r7, 0xAACEEDCA; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34e45515; +imm32 r3, 0x466e7717; +imm32 r0, 0x5567ee1b; +imm32 r1, 0x6789abed; +imm32 r2, 0x7444551e; +imm32 r3, 0x86e67777; +R0 = R1 +|- R0 , R7 = R1 -|+ R0; +R1 = R1 +|- R1 , R6 = R1 -|+ R1; +R2 = R1 +|- R2 , R5 = R1 -|+ R2; +R3 = R1 +|- R3 , R4 = R1 -|+ R3; +R4 = R1 +|- R4 , R3 = R1 -|+ R4; +R5 = R1 +|- R5 , R2 = R1 -|+ R5; +R6 = R1 +|- R6 , R1 = R1 -|+ R6; +R7 = R1 +|- R7 , R0 = R1 -|+ R7; +CHECKREG r0, 0xBCF0F1E2; +CHECKREG r1, 0xCF1257DA; +CHECKREG r2, 0x7444551E; +CHECKREG r3, 0x86E67777; +CHECKREG r4, 0x173E8889; +CHECKREG r5, 0x29E0AAE2; +CHECKREG r6, 0xCF12A826; +CHECKREG r7, 0xE134BDD2; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r0, 0x5567891b; +imm32 r1, 0x6789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0x86667777; +R0 = R2 +|- R0 , R7 = R2 -|+ R0; +R1 = R2 +|- R1 , R6 = R2 -|+ R1; +R2 = R2 +|- R2 , R5 = R2 -|+ R2; +R3 = R2 +|- R3 , R4 = R2 -|+ R3; +R4 = R2 +|- R4 , R3 = R2 -|+ R4; +R5 = R2 +|- R5 , R2 = R2 -|+ R5; +R6 = R2 +|- R6 , R1 = R2 -|+ R6; +R7 = R2 +|- R7 , R0 = R2 -|+ R7; +CHECKREG r0, 0xC9AB885A; +CHECKREG r1, 0xDBCDAA5C; +CHECKREG r2, 0xE888AA2A; +CHECKREG r3, 0x86667777; +CHECKREG r4, 0x4AAA8889; +CHECKREG r5, 0xE88855D6; +CHECKREG r6, 0xF543A9F8; +CHECKREG r7, 0x0765CBFA; + +imm32 r0, 0x85678911; +imm32 r1, 0x2889ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r0, 0x5587891b; +imm32 r1, 0x6788ab1d; +imm32 r2, 0x74448515; +imm32 r3, 0x86667877; +R0 = R3 +|- R0 , R7 = R3 -|+ R0; +R1 = R3 +|- R1 , R6 = R3 -|+ R1; +R2 = R3 +|- R2 , R5 = R3 -|+ R2; +R3 = R3 +|- R3 , R4 = R3 -|+ R3; +R4 = R3 +|- R4 , R3 = R3 -|+ R4; +R5 = R3 +|- R5 , R2 = R3 -|+ R5; +R6 = R3 +|- R6 , R1 = R3 -|+ R6; +R7 = R3 +|- R7 , R0 = R3 -|+ R7; +CHECKREG r0, 0xDBEDF280; +CHECKREG r1, 0xEDEE1482; +CHECKREG r2, 0xFAAAEE7A; +CHECKREG r3, 0x0CCCF0EE; +CHECKREG r4, 0x0CCC0F12; +CHECKREG r5, 0x1EEEF362; +CHECKREG r6, 0x2BAACD5A; +CHECKREG r7, 0x3DABEF5C; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r0, 0x5567891b; +imm32 r1, 0x6789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0x86667777; +R0 = R4 +|- R0 , R7 = R4 -|+ R0; +R1 = R4 +|- R1 , R6 = R4 -|+ R1; +R2 = R4 +|- R2 , R5 = R4 -|+ R2; +R3 = R4 +|- R3 , R4 = R4 -|+ R3; +R4 = R4 +|- R4 , R3 = R4 -|+ R4; +R5 = R4 +|- R5 , R2 = R4 -|+ R5; +R6 = R4 +|- R6 , R1 = R4 -|+ R6; +R7 = R4 +|- R7 , R0 = R4 -|+ R7; +CHECKREG r0, 0x5567982D; +CHECKREG r1, 0x6789BA2F; +CHECKREG r2, 0x74446427; +CHECKREG r3, 0x00000D12; +CHECKREG r4, 0x0CCC0000; +CHECKREG r5, 0xA5549BD9; +CHECKREG r6, 0xB20F45D1; +CHECKREG r7, 0xC43167D3; + +imm32 r0, 0x95678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x39445515; +imm32 r3, 0x46967717; +imm32 r0, 0x5567891b; +imm32 r1, 0x6789ab1d; +imm32 r2, 0x74495515; +imm32 r3, 0x86669777; +R0 = R5 +|- R0 , R7 = R5 -|+ R0; +R1 = R5 +|- R1 , R6 = R5 -|+ R1; +R2 = R5 +|- R2 , R5 = R5 -|+ R2; +R3 = R5 +|- R3 , R4 = R5 -|+ R3; +R4 = R5 +|- R4 , R3 = R5 -|+ R4; +R5 = R5 +|- R5 , R2 = R5 -|+ R5; +R6 = R5 +|- R6 , R1 = R5 -|+ R6; +R7 = R5 +|- R7 , R0 = R5 -|+ R7; +CHECKREG r0, 0x122924F4; +CHECKREG r1, 0x244B46F6; +CHECKREG r2, 0x0000E1DC; +CHECKREG r3, 0x86667953; +CHECKREG r4, 0xDBB06889; +CHECKREG r5, 0x62160000; +CHECKREG r6, 0x9FE1B90A; +CHECKREG r7, 0xB203DB0C; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r0, 0x5567891b; +imm32 r1, 0x6789ab1d; +imm32 r2, 0x74445515; +imm32 r3, 0x86667777; +R0 = R6 +|- R0 , R7 = R6 -|+ R0; +R1 = R6 +|- R1 , R6 = R6 -|+ R1; +R2 = R6 +|- R2 , R5 = R6 -|+ R2; +R3 = R6 +|- R3 , R4 = R6 -|+ R3; +R4 = R6 +|- R4 , R3 = R6 -|+ R4; +R5 = R6 +|- R5 , R2 = R6 -|+ R5; +R6 = R6 +|- R6 , R1 = R6 -|+ R6; +R7 = R6 +|- R7 , R0 = R6 -|+ R7; +CHECKREG r0, 0x26364225; +CHECKREG r1, 0x0000C84E; +CHECKREG r2, 0x74441D63; +CHECKREG r3, 0x86663FC5; +CHECKREG r4, 0xEA4A8889; +CHECKREG r5, 0xFC6CAAEB; +CHECKREG r6, 0x70B00000; +CHECKREG r7, 0xBB2ABDDB; + +imm32 r0, 0x67898911; +imm32 r1, 0xb789ab1d; +imm32 r2, 0x3b445515; +imm32 r3, 0x46b67717; +imm32 r0, 0x5567891b; +imm32 r1, 0x678bab1d; +imm32 r2, 0x7444b515; +imm32 r3, 0x86667b77; +R0 = R7 +|- R0 , R7 = R7 -|+ R0; +R1 = R7 +|- R1 , R6 = R7 -|+ R1; +R2 = R7 +|- R2 , R5 = R7 -|+ R2; +R3 = R7 +|- R3 , R4 = R7 -|+ R3; +R4 = R7 +|- R4 , R3 = R7 -|+ R4; +R5 = R7 +|- R5 , R2 = R7 -|+ R5; +R6 = R7 +|- R6 , R1 = R7 -|+ R6; +R7 = R7 +|- R7 , R0 = R7 -|+ R7; +CHECKREG r0, 0x00008DEC; +CHECKREG r1, 0x678B3909; +CHECKREG r2, 0x74444301; +CHECKREG r3, 0x86660963; +CHECKREG r4, 0x45208489; +CHECKREG r5, 0x57424AEB; +CHECKREG r6, 0x63FB54E3; +CHECKREG r7, 0xCB860000; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34ee5515; +imm32 r3, 0x4666e717; +imm32 r0, 0x5567891b; +imm32 r1, 0x6789ae1d; +imm32 r2, 0x744455e5; +imm32 r3, 0x8666777e; +R4 = R2 +|- R5 , R3 = R2 -|+ R5 (S); +R0 = R5 +|- R3 , R5 = R5 -|+ R3 (CO); +R2 = R6 +|- R2 , R0 = R6 -|+ R2 (SCO); +R3 = R4 +|- R0 , R2 = R4 -|+ R0 (S); +R7 = R7 +|- R6 , R6 = R7 -|+ R6 (CO); +R6 = R1 +|- R7 , R1 = R1 -|+ R7 (SCO); +R5 = R0 +|- R4 , R7 = R0 -|+ R4 (S); +R1 = R3 +|- R1 , R4 = R3 -|+ R1 (CO); +CHECKREG r0, 0x7FFFEFB7; +CHECKREG r1, 0xFFFFE33B; +CHECKREG r2, 0x0000FAB1; +CHECKREG r3, 0x7FFF1B43; +CHECKREG r4, 0x534BFFFF; +CHECKREG r5, 0x7FFFE4BD; +CHECKREG r6, 0x7FFF0300; +CHECKREG r7, 0x0000FAB1; + +imm32 r0, 0xff678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x3f445515; +imm32 r3, 0x46f67717; +imm32 r0, 0x556f891b; +imm32 r1, 0x6789fb1d; +imm32 r2, 0x74445f15; +imm32 r3, 0x866677f7; +R4 = R3 +|- R3 , R5 = R3 -|+ R3 (SCO); +R1 = R6 +|- R1 , R6 = R6 -|+ R1 (SCO); +R6 = R1 +|- R4 , R4 = R1 -|+ R4 (S); +R7 = R4 +|- R2 , R0 = R4 -|+ R2 (S); +R2 = R2 +|- R6 , R1 = R2 -|+ R6 (CO); +R3 = R5 +|- R5 , R7 = R5 -|+ R5 (CO); +R5 = R7 +|- R7 , R3 = R7 -|+ R7 (SCO); +R0 = R0 +|- R0 , R2 = R0 -|+ R0 (SCO); +CHECKREG r0, 0x17760000; +CHECKREG r1, 0x66F87445; +CHECKREG r2, 0x7FFF0000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x7FFF07E3; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xFFFF07E3; +CHECKREG r7, 0x00000000; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft.s new file mode 100644 index 0000000..bd48482 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft.s @@ -0,0 +1,262 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft/c_dsp32alu_rrpmmp_sft.dsp +// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, << +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + + imm32 r0, 0x35678911; + imm32 r1, 0x2489ab1d; + imm32 r2, 0x34545515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x67889b1d; + imm32 r2, 0x74445915; + imm32 r3, 0x86667797; + R0 = R0 +|- R0 , R7 = R0 -|+ R0 (ASR); + R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); + R2 = R0 +|- R2 , R5 = R0 -|+ R2 (ASR); + R3 = R0 +|- R3 , R4 = R0 -|+ R3 (ASR); + R4 = R0 +|- R4 , R3 = R0 -|+ R4 (ASR); + R5 = R0 +|- R5 , R2 = R0 -|+ R5 (ASR); + R6 = R0 +|- R6 , R1 = R0 -|+ R6 (ASR); + R7 = R0 +|- R7 , R0 = R0 -|+ R7 (ASR); + CHECKREG r0, 0x2AB3c48D; + CHECKREG r1, 0x2F3CE6C7; + CHECKREG r2, 0x326B1645; + CHECKREG r3, 0xf6F31DE5; + CHECKREG r4, 0x5E73E21A; + CHECKREG r5, 0x22FCE9BB; + CHECKREG r6, 0x262B1939; + CHECKREG r7, 0x2AB33B72; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2e89ab1d; + imm32 r2, 0x34e45515; + imm32 r3, 0x466e7717; + imm32 r0, 0x5567ee1b; + imm32 r1, 0x6789abed; + imm32 r2, 0x7444551e; + imm32 r3, 0x86e67777; + R0 = R1 +|- R0 , R7 = R1 -|+ R0 (ASR); + R1 = R1 +|- R1 , R6 = R1 -|+ R1 (ASR); + R2 = R1 +|- R2 , R5 = R1 -|+ R2 (ASR); + R3 = R1 +|- R3 , R4 = R1 -|+ R3 (ASR); + R4 = R1 +|- R4 , R3 = R1 -|+ R4 (ASR); + R5 = R1 +|- R5 , R2 = R1 -|+ R5 (ASR); + R6 = R1 +|- R6 , R1 = R1 -|+ R6 (ASR); + R7 = R1 +|- R7 , R0 = R1 -|+ R7 (ASR); + CHECKREG r0, 0x1559d17D; + CHECKREG r1, 0x33C4d5F6; + CHECKREG r2, 0x36F31547; + CHECKREG r3, 0xfB9C1DDD; + CHECKREG r4, 0x6BEDE222; + CHECKREG r5, 0x3095eAB8; + CHECKREG r6, 0x33C42A09; + CHECKREG r7, 0x1E6A0479; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74445515; + imm32 r3, 0x86667777; + R0 = R2 +|- R0 , R7 = R2 -|+ R0 (ASR); + R1 = R2 +|- R1 , R6 = R2 -|+ R1 (ASR); + R2 = R2 +|- R2 , R5 = R2 -|+ R2 (ASR); + R3 = R2 +|- R3 , R4 = R2 -|+ R3 (ASR); + R4 = R2 +|- R4 , R3 = R2 -|+ R4 (ASR); + R5 = R2 +|- R5 , R2 = R2 -|+ R5 (ASR); + R6 = R2 +|- R6 , R1 = R2 -|+ R6 (ASR); + R7 = R2 +|- R7 , R0 = R2 -|+ R7 (ASR); + CHECKREG r0, 0x155A0CD1; + CHECKREG r1, 0x19E21551; + CHECKREG r2, 0x3A222A8A; + CHECKREG r3, 0xfEAA1DDD; + CHECKREG r4, 0x7599e222; + CHECKREG r5, 0x3A22d575; + CHECKREG r6, 0x203F1538; + CHECKREG r7, 0x24C81DB9; + + imm32 r0, 0x85678911; + imm32 r1, 0x2889ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5587891b; + imm32 r1, 0x6788ab1d; + imm32 r2, 0x74448515; + imm32 r3, 0x86667877; + R0 = R3 +|- R0 , R7 = R3 -|+ R0 (ASR); + R1 = R3 +|- R1 , R6 = R3 -|+ R1 (ASR); + R2 = R3 +|- R2 , R5 = R3 -|+ R2 (ASR); + R3 = R3 +|- R3 , R4 = R3 -|+ R3 (ASR); + R4 = R3 +|- R4 , R3 = R3 -|+ R4 (ASR); + R5 = R3 +|- R5 , R2 = R3 -|+ R5 (ASR); + R6 = R3 +|- R6 , R1 = R3 -|+ R6 (ASR); + R7 = R3 +|- R7 , R0 = R3 -|+ R7 (ASR); + CHECKREG r0, 0x15621E82; + CHECKREG r1, 0x19E22702; + CHECKREG r2, 0x1D111D80; + CHECKREG r3, 0xc3333C3B; + CHECKREG r4, 0xc333c3C4; + CHECKREG r5, 0xa6221EBA; + CHECKREG r6, 0xa9511538; + CHECKREG r7, 0xaDD11DB9; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74445515; + imm32 r3, 0x86667777; + R0 = R4 +|- R0 , R7 = R4 -|+ R0 (ASR); + R1 = R4 +|- R1 , R6 = R4 -|+ R1 (ASR); + R2 = R4 +|- R2 , R5 = R4 -|+ R2 (ASR); + R3 = R4 +|- R3 , R4 = R4 -|+ R3 (ASR); + R4 = R4 +|- R4 , R3 = R4 -|+ R4 (ASR); + R5 = R4 +|- R5 , R2 = R4 -|+ R5 (ASR); + R6 = R4 +|- R6 , R1 = R4 -|+ R6 (ASR); + R7 = R4 +|- R7 , R0 = R4 -|+ R7 (ASR); + CHECKREG r0, 0x33C0d337; + CHECKREG r1, 0x3848dBB8; + CHECKREG r2, 0x3B770636; + CHECKREG r3, 0x00001D9D; + CHECKREG r4, 0x1E660000; + CHECKREG r5, 0xe2EEf9CA; + CHECKREG r6, 0xe61D2448; + CHECKREG r7, 0xeAA62CC8; + + imm32 r0, 0x95678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x39445515; + imm32 r3, 0x46967717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74495515; + imm32 r3, 0x86669777; + R0 = R5 +|- R0 , R7 = R5 -|+ R0 (ASR); + R1 = R5 +|- R1 , R6 = R5 -|+ R1 (ASL); + R2 = R5 +|- R2 , R5 = R5 -|+ R2 (ASR); + R3 = R5 +|- R3 , R4 = R5 -|+ R3 (ASL); + R4 = R5 +|- R4 , R3 = R5 -|+ R4 (ASR); + R5 = R5 +|- R5 , R2 = R5 -|+ R5 (ASR); + R6 = R5 +|- R6 , R1 = R5 -|+ R6 (ASR); + R7 = R5 +|- R7 , R0 = R5 -|+ R7 (ASL); + CHECKREG r0, 0xE11E82E4; + CHECKREG r1, 0xe04424E7; + CHECKREG r2, 0x0000276F; + CHECKREG r3, 0xaaBD529D; + CHECKREG r4, 0x0c95D4D1; + CHECKREG r5, 0xb7520000; + CHECKREG r6, 0xd70EdB19; + CHECKREG r7, 0xfC2A7D1C; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74445515; + imm32 r3, 0x86667777; + R0 = R6 +|- R0 , R7 = R6 -|+ R0 (ASR); + R1 = R6 +|- R1 , R6 = R6 -|+ R1 (ASL); + R2 = R6 +|- R2 , R5 = R6 -|+ R2 (ASL); + R3 = R6 +|- R3 , R4 = R6 -|+ R3 (ASR); + R4 = R6 +|- R4 , R3 = R6 -|+ R4 (ASR); + R5 = R6 +|- R5 , R2 = R6 -|+ R5 (ASR); + R6 = R6 +|- R6 , R1 = R6 -|+ R6 (ASL); + R7 = R6 +|- R7 , R0 = R6 -|+ R7 (ASR); + CHECKREG r0, 0x5dAAd90D; + CHECKREG r1, 0x000031B0; + CHECKREG r2, 0x04BFe7B7; + CHECKREG r3, 0xd95C272E; + CHECKREG r4, 0x05AEe53D; + CHECKREG r5, 0xDa4B24B5; + CHECKREG r6, 0x7C280000; + CHECKREG r7, 0x1e7D26F3; + + imm32 r0, 0x67898911; + imm32 r1, 0xb789ab1d; + imm32 r2, 0x3b445515; + imm32 r3, 0x46b67717; + imm32 r0, 0x5567891b; + imm32 r1, 0x678bab1d; + imm32 r2, 0x7444b515; + imm32 r3, 0x86667b77; + R0 = R7 +|- R0 , R7 = R7 -|+ R0 (ASR); + R1 = R7 +|- R1 , R6 = R7 -|+ R1 (ASR); + R2 = R7 +|- R2 , R5 = R7 -|+ R2 (ASL); + R3 = R7 +|- R3 , R4 = R7 -|+ R3 (ASR); + R4 = R7 +|- R4 , R3 = R7 -|+ R4 (ASL); + R5 = R7 +|- R5 , R2 = R7 -|+ R5 (ASL); + R6 = R7 +|- R6 , R1 = R7 -|+ R6 (ASL); + R7 = R7 +|- R7 , R0 = R7 -|+ R7 (ASR); + CHECKREG r0, 0x0000d807; + CHECKREG r1, 0x4c163332; + CHECKREG r2, 0x07FAe47E; + CHECKREG r3, 0x6aF2038C; + CHECKREG r4, 0x273A5c90; + CHECKREG r5, 0x8a327b9E; + CHECKREG r6, 0x46162cEA; + CHECKREG r7, 0xe48B0000; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2e89ab1d; + imm32 r2, 0x34ee5515; + imm32 r3, 0x4666e717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ae1d; + imm32 r2, 0x744455e5; + imm32 r3, 0x8666777e; + R4 = R2 +|- R5 , R3 = R2 -|+ R5 (ASR); + R0 = R5 +|- R3 , R5 = R5 -|+ R3 (ASL); + R2 = R6 +|- R2 , R0 = R6 -|+ R2 (ASR); + R3 = R4 +|- R0 , R2 = R4 -|+ R0 (ASR); + R7 = R7 +|- R6 , R6 = R7 -|+ R6 (ASR); + R6 = R1 +|- R7 , R1 = R1 -|+ R7 (ASL); + R5 = R0 +|- R4 , R7 = R0 -|+ R4 (ASR); + R1 = R3 +|- R1 , R4 = R3 -|+ R1 (ASL); + CHECKREG r0, 0xE8e94167; + CHECKREG r1, 0x31084d1C; + CHECKREG r2, 0x0b291745; + CHECKREG r3, 0xF412d5de; + CHECKREG r4, 0x9f400a5C; + CHECKREG r5, 0xF4122a22; + CHECKREG r6, 0xf9B28924; + CHECKREG r7, 0xF4D71745; + + imm32 r0, 0xff678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x3f445515; + imm32 r3, 0x46f67717; + imm32 r0, 0x556f891b; + imm32 r1, 0x6789fb1d; + imm32 r2, 0x74445f15; + imm32 r3, 0x866677f7; + R4 = R3 +|- R3 , R5 = R3 -|+ R3 (ASR); + R1 = R6 +|- R1 , R6 = R6 -|+ R1 (ASL); + R6 = R1 +|- R4 , R4 = R1 -|+ R4 (ASR); + R7 = R4 +|- R2 , R0 = R4 -|+ R2 (ASL); + R2 = R2 +|- R6 , R1 = R2 -|+ R6 (ASR); + R3 = R5 +|- R5 , R7 = R5 -|+ R5 (ASL); + R5 = R7 +|- R7 , R3 = R7 -|+ R7 (ASR); + R0 = R0 +|- R0 , R2 = R0 -|+ R0 (ASR); + CHECKREG r0, 0x53880000; + CHECKREG r1, 0x67eb368e; + CHECKREG r2, 0x0000da38; + CHECKREG r3, 0x0000dfdc; + CHECKREG r4, 0x1e080e07; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0xa46e0e07; + CHECKREG r7, 0x0000dfdc; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft_x.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft_x.s new file mode 100644 index 0000000..f8711a5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft_x.s @@ -0,0 +1,261 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft_x/c_dsp32alu_rrpmmp_sft_x.dsp +// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, << +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x35678911; + imm32 r1, 0x2489ab1d; + imm32 r2, 0x34545515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x67889b1d; + imm32 r2, 0x74445915; + imm32 r3, 0x86667797; + R0 = R0 +|- R0 , R7 = R0 -|+ R0 (CO , ASR); + R1 = R0 +|- R1 , R6 = R0 -|+ R1 (CO , ASR); + R2 = R0 +|- R2 , R5 = R0 -|+ R2 (CO , ASR); + R3 = R0 +|- R3 , R4 = R0 -|+ R3 (CO , ASR); + R4 = R0 +|- R4 , R3 = R0 -|+ R4 (CO , ASR); + R5 = R0 +|- R5 , R2 = R0 -|+ R5 (CO , ASR); + R6 = R0 +|- R6 , R1 = R0 -|+ R6 (CO , ASR); + R7 = R0 +|- R7 , R0 = R0 -|+ R7 (CO , ASR); + CHECKREG r0, 0x00006626; + CHECKREG r1, 0xfb7743ec; + CHECKREG r2, 0xf848146e; + CHECKREG r3, 0x33c00cce; + CHECKREG r4, 0x4899cc40; + CHECKREG r5, 0x40f807b7; + CHECKREG r6, 0x117a0488; + CHECKREG r7, 0xef410000; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2e89ab1d; + imm32 r2, 0x34e45515; + imm32 r3, 0x466e7717; + imm32 r0, 0x5567ee1b; + imm32 r1, 0x6789abed; + imm32 r2, 0x7444551e; + imm32 r3, 0x86e67777; + R0 = R1 +|- R0 , R7 = R1 -|+ R0 (CO , ASR); + R1 = R1 +|- R1 , R6 = R1 -|+ R1 (CO , ASR); + R2 = R1 +|- R2 , R5 = R1 -|+ R2 (CO , ASR); + R3 = R1 +|- R3 , R4 = R1 -|+ R3 (CO , ASR); + R4 = R1 +|- R4 , R3 = R1 -|+ R4 (CO , ASR); + R5 = R1 +|- R5 , R2 = R1 -|+ R5 (CO , ASR); + R6 = R1 +|- R6 , R1 = R1 -|+ R6 (CO , ASR); + R7 = R1 +|- R7 , R0 = R1 -|+ R7 (CO , ASR); + CHECKREG r0, 0x336f197e; + CHECKREG r1, 0x00005dce; + CHECKREG r2, 0xfcd11e7d; + CHECKREG r3, 0x382815e7; + CHECKREG r4, 0x51a2c7d7; + CHECKREG r5, 0x490c032f; + CHECKREG r6, 0x09bb0000; + CHECKREG r7, 0xe6822a5e; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74445515; + imm32 r3, 0x86667777; + R0 = R2 +|- R0 , R7 = R2 -|+ R0 (CO , ASR); + R1 = R2 +|- R1 , R6 = R2 -|+ R1 (CO , ASR); + R2 = R2 +|- R2 , R5 = R2 -|+ R2 (CO , ASR); + R3 = R2 +|- R3 , R4 = R2 -|+ R3 (CO , ASR); + R4 = R2 +|- R4 , R3 = R2 -|+ R4 (CO , ASR); + R5 = R2 +|- R5 , R2 = R2 -|+ R5 (CO , ASR); + R6 = R2 +|- R6 , R1 = R2 -|+ R6 (CO , ASR); + R7 = R2 +|- R7 , R0 = R2 -|+ R7 (CO , ASR); + CHECKREG r0, 0x0f820874; + CHECKREG r1, 0x0afafff3; + CHECKREG r2, 0x00000f97; + CHECKREG r3, 0x3b771c44; + CHECKREG r4, 0x57ffc488; + CHECKREG r5, 0x64ac0000; + CHECKREG r6, 0x000c049d; + CHECKREG r7, 0xf78c0014; + + imm32 r0, 0x85678911; + imm32 r1, 0x2889ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5587891b; + imm32 r1, 0x6788ab1d; + imm32 r2, 0x74448515; + imm32 r3, 0x86667877; + R0 = R3 +|- R0 , R7 = R3 -|+ R0 (CO , ASR); + R1 = R3 +|- R1 , R6 = R3 -|+ R1 (CO , ASR); + R2 = R3 +|- R2 , R5 = R3 -|+ R2 (CO , ASR); + R3 = R3 +|- R3 , R4 = R3 -|+ R3 (CO , ASR); + R4 = R3 +|- R4 , R3 = R3 -|+ R4 (CO , ASR); + R5 = R3 +|- R5 , R2 = R3 -|+ R5 (CO , ASR); + R6 = R3 +|- R6 , R1 = R3 -|+ R6 (CO , ASR); + R7 = R3 +|- R7 , R0 = R3 -|+ R7 (CO , ASR); + CHECKREG r0, 0x8fb3ff9b; + CHECKREG r1, 0x8b33f71b; + CHECKREG r2, 0x8804009d; + CHECKREG r3, 0x000086f7; + CHECKREG r4, 0xff6e0000; + CHECKREG r5, 0xff63fef3; + CHECKREG r6, 0x08e5fbc4; + CHECKREG r7, 0x0064f744; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74445515; + imm32 r3, 0x86667777; + R0 = R4 +|- R0 , R7 = R4 -|+ R0 (CO , ASR); + R1 = R4 +|- R1 , R6 = R4 -|+ R1 (CO , ASR); + R2 = R4 +|- R2 , R5 = R4 -|+ R2 (CO , ASR); + R3 = R4 +|- R3 , R4 = R4 -|+ R3 (CO , ASR); + R4 = R4 +|- R4 , R3 = R4 -|+ R4 (CO , ASR); + R5 = R4 +|- R5 , R2 = R4 -|+ R5 (CO , ASR); + R6 = R4 +|- R6 , R1 = R4 -|+ R6 (CO , ASR); + R7 = R4 +|- R7 , R0 = R4 -|+ R7 (CO , ASR); + CHECKREG r0, 0xEA813B97; + CHECKREG r1, 0xE5F93316; + CHECKREG r2, 0xe2ca0898; + CHECKREG r3, 0x3C840000; + CHECKREG r4, 0x3BBB0000; + CHECKREG r5, 0x33221D35; + CHECKREG r6, 0x08A41A07; + CHECKREG r7, 0x0024157E; + + imm32 r0, 0x95678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x39445515; + imm32 r3, 0x46967717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74495515; + imm32 r3, 0x86669777; + R0 = R5 +|- R0 , R7 = R5 -|+ R0 (CO , ASR); + R1 = R5 +|- R1 , R6 = R5 -|+ R1 (CO , ASL); + R2 = R5 +|- R2 , R5 = R5 -|+ R2 (CO , ASR); + R3 = R5 +|- R3 , R4 = R5 -|+ R3 (CO , ASL); + R4 = R5 +|- R4 , R3 = R5 -|+ R4 (CO , ASR); + R5 = R5 +|- R5 , R2 = R5 -|+ R5 (CO , ASR); + R6 = R5 +|- R6 , R1 = R5 -|+ R6 (CO , ASR); + R7 = R5 +|- R7 , R0 = R5 -|+ R7 (CO , ASL); + CHECKREG r0, 0xDDBACBFA; + CHECKREG r1, 0xCB995440; + CHECKREG r2, 0xDF6C0000; + CHECKREG r3, 0x227525AF; + CHECKREG r4, 0x1375bCF7; + CHECKREG r5, 0x39250000; + CHECKREG r6, 0xE4E43467; + CHECKREG r7, 0x189A2246; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ab1d; + imm32 r2, 0x74445515; + imm32 r3, 0x86667777; + R0 = R6 +|- R0 , R7 = R6 -|+ R0 (CO , ASR); + R1 = R6 +|- R1 , R6 = R6 -|+ R1 (CO , ASL); + R2 = R6 +|- R2 , R5 = R6 -|+ R2 (CO , ASL); + R3 = R6 +|- R3 , R4 = R6 -|+ R3 (CO , ASR); + R4 = R6 +|- R4 , R3 = R6 -|+ R4 (CO , ASR); + R5 = R6 +|- R5 , R2 = R6 -|+ R5 (CO , ASR); + R6 = R6 +|- R6 , R1 = R6 -|+ R6 (CO , ASL); + R7 = R6 +|- R7 , R0 = R6 -|+ R7 (CO , ASR); + CHECKREG r0, 0xE3DF0EAF; + CHECKREG r1, 0xEAD80000; + CHECKREG r2, 0xC81F0FB9; + CHECKREG r3, 0x0B83C2F9; + CHECKREG r4, 0xFC0FEF32; + CHECKREG r5, 0xaF4F3297; + CHECKREG r6, 0xFC200000; + CHECKREG r7, 0xED701C21; + + imm32 r0, 0x67898911; + imm32 r1, 0xb789ab1d; + imm32 r2, 0x3b445515; + imm32 r3, 0x46b67717; + imm32 r0, 0x5567891b; + imm32 r1, 0x678bab1d; + imm32 r2, 0x7444b515; + imm32 r3, 0x86667b77; + R0 = R7 +|- R0 , R7 = R7 -|+ R0 (CO , ASR); + R1 = R7 +|- R1 , R6 = R7 -|+ R1 (CO , ASR); + R2 = R7 +|- R2 , R5 = R7 -|+ R2 (CO , ASL); + R3 = R7 +|- R3 , R4 = R7 -|+ R3 (CO , ASR); + R4 = R7 +|- R4 , R3 = R7 -|+ R4 (CO , ASL); + R5 = R7 +|- R5 , R2 = R7 -|+ R5 (CO , ASL); + R6 = R7 +|- R6 , R1 = R7 -|+ R6 (CO , ASL); + R7 = R7 +|- R7 , R0 = R7 -|+ R7 (CO , ASR); + CHECKREG r0, 0xCC040000; + CHECKREG r1, 0x031A2E1C; + CHECKREG r2, 0x1170A0D8; + CHECKREG r3, 0xE4405DC2; + CHECKREG r4, 0xECB64BD0; + CHECKREG r5, 0xA9A01EA0; + CHECKREG r6, 0x1C5C2CF6; + CHECKREG r7, 0xD29E0000; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2e89ab1d; + imm32 r2, 0x34ee5515; + imm32 r3, 0x4666e717; + imm32 r0, 0x5567891b; + imm32 r1, 0x6789ae1d; + imm32 r2, 0x744455e5; + imm32 r3, 0x8666777e; + R4 = R2 +|- R5 , R3 = R2 -|+ R5 (CO , ASR); + R0 = R5 +|- R3 , R5 = R5 -|+ R3 (CO , ASL); + R2 = R6 +|- R2 , R0 = R6 -|+ R2 (CO , ASR); + R3 = R4 +|- R0 , R2 = R4 -|+ R0 (CO , ASR); + R7 = R7 +|- R6 , R6 = R7 -|+ R6 (CO , ASR); + R6 = R1 +|- R7 , R1 = R1 -|+ R7 (CO , ASL); + R5 = R0 +|- R4 , R7 = R0 -|+ R4 (CO , ASR); + R1 = R3 +|- R1 , R4 = R3 -|+ R1 (CO , ASL); + CHECKREG r0, 0x416dd40c; + CHECKREG r1, 0xaEE68766; + CHECKREG r2, 0xF7D7e6C2; + CHECKREG r3, 0x282F23CB; + CHECKREG r4, 0x07C6f1D6; + CHECKREG r5, 0x282FDC35; + CHECKREG r6, 0xBE0C8930; + CHECKREG r7, 0xF7D7193D; + + imm32 r0, 0xff678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x3f445515; + imm32 r3, 0x46f67717; + imm32 r0, 0x556f891b; + imm32 r1, 0x6789fb1d; + imm32 r2, 0x74445f15; + imm32 r3, 0x866677f7; + R4 = R3 +|- R3 , R5 = R3 -|+ R3 (CO , ASR); + R1 = R6 +|- R1 , R6 = R6 -|+ R1 (CO , ASL); + R6 = R1 +|- R4 , R4 = R1 -|+ R4 (CO , ASR); + R7 = R4 +|- R2 , R0 = R4 -|+ R2 (CO , ASL); + R2 = R2 +|- R6 , R1 = R2 -|+ R6 (CO , ASR); + R3 = R5 +|- R5 , R7 = R5 -|+ R5 (CO , ASL); + R5 = R7 +|- R7 , R3 = R7 -|+ R7 (CO , ASR); + R0 = R0 +|- R0 , R2 = R0 -|+ R0 (CO , ASR); + CHECKREG r0, 0x82EE0000; + CHECKREG r1, 0x369445BE; + CHECKREG r2, 0x339E0000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x0E136262; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0xe8C80E13; + CHECKREG r7, 0x00000000; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm.s new file mode 100644 index 0000000..3d62e56 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm.s @@ -0,0 +1,263 @@ +//Original:/testcases/core/c_dsp32alu_rrppmm/c_dsp32alu_rrppmm.dsp +// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) amod0 +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x95679911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34945515; +imm32 r3, 0x46967717; +imm32 r4, 0x5597891b; +imm32 r5, 0x6989ab1d; +imm32 r6, 0x94445515; +imm32 r7, 0x96667777; +R0 = R0 +|+ R0, R7 = R0 -|- R0; +R1 = R0 +|+ R1, R6 = R0 -|- R1; +R2 = R0 +|+ R2, R5 = R0 -|- R2; +R3 = R0 +|+ R3, R4 = R0 -|- R3; +R4 = R0 +|+ R4, R3 = R0 -|- R4; +R5 = R0 +|+ R5, R2 = R0 -|- R5; +R6 = R0 +|+ R6, R1 = R0 -|- R6; +R7 = R0 +|+ R7, R0 = R0 -|- R7; +CHECKREG r0, 0x2ACE3222; +CHECKREG r1, 0x2789AB1D; +CHECKREG r2, 0x34945515; +CHECKREG r3, 0x46967717; +CHECKREG r4, 0x0F06ED2D; +CHECKREG r5, 0x21080F2F; +CHECKREG r6, 0x2E13B927; +CHECKREG r7, 0x2ACE3222; + +imm32 r0, 0x11678911; +imm32 r1, 0xa719ab1d; +imm32 r2, 0x3a415515; +imm32 r3, 0x46a67717; +imm32 r4, 0x556a891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445a15; +imm32 r7, 0x866677a7; +R0 = R1 +|+ R0, R7 = R1 -|- R0; +R1 = R1 +|+ R1, R6 = R1 -|- R1; +R2 = R1 +|+ R2, R5 = R1 -|- R2; +R3 = R1 +|+ R3, R4 = R1 -|- R3; +R4 = R1 +|+ R4, R3 = R1 -|- R4; +R5 = R1 +|+ R5, R2 = R1 -|- R5; +R6 = R1 +|+ R6, R1 = R1 -|- R6; +R7 = R1 +|+ R7, R0 = R1 -|- R7; +CHECKREG r0, 0xB880342E; +CHECKREG r1, 0x4E32563A; +CHECKREG r2, 0x3A415515; +CHECKREG r3, 0x46A67717; +CHECKREG r4, 0x55BE355D; +CHECKREG r5, 0x6223575F; +CHECKREG r6, 0x4E32563A; +CHECKREG r7, 0xE3E47846; + +imm32 r0, 0xb567891b; +imm32 r1, 0x2b89abbd; +imm32 r2, 0x34b45b15; +imm32 r3, 0x466bb717; +imm32 r4, 0x556bb91b; +imm32 r5, 0x67b9ab1d; +imm32 r6, 0x7b4455b5; +imm32 r7, 0xb666777b; +R0 = R2 +|+ R0, R7 = R2 -|- R0; +R1 = R2 +|+ R1, R6 = R2 -|- R1; +R2 = R2 +|+ R2, R5 = R2 -|- R2; +R3 = R2 +|+ R3, R4 = R2 -|- R3; +R4 = R2 +|+ R4, R3 = R2 -|- R4; +R5 = R2 +|+ R5, R2 = R2 -|- R5; +R6 = R2 +|+ R6, R1 = R2 -|- R6; +R7 = R2 +|+ R7, R0 = R2 -|- R7; +CHECKREG r0, 0xEA1BE430; +CHECKREG r1, 0x603D06D2; +CHECKREG r2, 0x6968B62A; +CHECKREG r3, 0x466BB717; +CHECKREG r4, 0x8C65B53D; +CHECKREG r5, 0x6968B62A; +CHECKREG r6, 0x72936582; +CHECKREG r7, 0xE8B58824; + +imm32 r0, 0xbc678c11; +imm32 r1, 0x27c9cb1d; +imm32 r2, 0x344c5515; +imm32 r3, 0x46c6c717; +imm32 r4, 0x55678c1b; +imm32 r5, 0x6c89abcd; +imm32 r6, 0x7444551c; +imm32 r7, 0x8c667777; +R0 = R3 +|+ R0, R7 = R3 -|- R0; +R1 = R3 +|+ R1, R6 = R3 -|- R1; +R2 = R3 +|+ R2, R5 = R3 -|- R2; +R3 = R3 +|+ R3, R4 = R3 -|- R3; +R4 = R3 +|+ R4, R3 = R3 -|- R4; +R5 = R3 +|+ R5, R2 = R3 -|- R5; +R6 = R3 +|+ R6, R1 = R3 -|- R6; +R7 = R3 +|+ R7, R0 = R3 -|- R7; +CHECKREG r0, 0x032D5328; +CHECKREG r1, 0x6E8F9234; +CHECKREG r2, 0x7B121C2C; +CHECKREG r3, 0x8D8C8E2E; +CHECKREG r4, 0x8D8C8E2E; +CHECKREG r5, 0xA0060030; +CHECKREG r6, 0xAC898A28; +CHECKREG r7, 0x17EBC934; + +imm32 r0, 0xd56789d1; +imm32 r1, 0x2d89abdd; +imm32 r2, 0x34d455d5; +imm32 r3, 0x4d667717; +imm32 r4, 0x5dd7891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0xd44d5515; +imm32 r7, 0xd666d777; +R0 = R4 +|+ R0, R7 = R4 -|- R0; +R1 = R4 +|+ R1, R6 = R4 -|- R1; +R2 = R4 +|+ R2, R5 = R4 -|- R2; +R3 = R4 +|+ R3, R4 = R4 -|- R3; +R4 = R4 +|+ R4, R3 = R4 -|- R4; +R5 = R4 +|+ R5, R2 = R4 -|- R5; +R6 = R4 +|+ R6, R1 = R4 -|- R6; +R7 = R4 +|+ R7, R0 = R4 -|- R7; +CHECKREG r0, 0x987224BE; +CHECKREG r1, 0xF09446CA; +CHECKREG r2, 0xF7DFF0C2; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x20E22408; +CHECKREG r5, 0x49E5574E; +CHECKREG r6, 0x51300146; +CHECKREG r7, 0xA9522352; + +imm32 r0, 0xc567a911; +imm32 r1, 0x278aab1d; +imm32 r2, 0x3c445515; +imm32 r3, 0x46a67717; +imm32 r4, 0x55c7891b; +imm32 r5, 0x6a8cab1d; +imm32 r6, 0x7444c515; +imm32 r7, 0xa6667c77; +R0 = R5 +|+ R0, R7 = R5 -|- R0; +R1 = R5 +|+ R1, R6 = R5 -|- R1; +R2 = R5 +|+ R2, R5 = R5 -|- R2; +R3 = R5 +|+ R3, R4 = R5 -|- R3; +R4 = R5 +|+ R4, R3 = R5 -|- R4; +R5 = R5 +|+ R5, R2 = R5 -|- R5; +R6 = R5 +|+ R6, R1 = R5 -|- R6; +R7 = R5 +|+ R7, R0 = R5 -|- R7; +CHECKREG r0, 0xB76BAA04; +CHECKREG r1, 0x198EAC10; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x46A67717; +CHECKREG r4, 0x15EA34F9; +CHECKREG r5, 0x5C90AC10; +CHECKREG r6, 0x9F92AC10; +CHECKREG r7, 0x01B5AE1C; + +imm32 r0, 0xd5678911; +imm32 r1, 0x2ddddd1d; +imm32 r2, 0x34ddd515; +imm32 r3, 0x46d67717; +imm32 r4, 0x5d6d891b; +imm32 r5, 0x6789db1d; +imm32 r6, 0x74445d15; +imm32 r7, 0xd66677d7; +R0 = R6 +|+ R0, R7 = R6 -|- R0; +R1 = R6 +|+ R1, R6 = R6 -|- R1; +R2 = R6 +|+ R2, R5 = R6 -|- R2; +R3 = R6 +|+ R3, R4 = R6 -|- R3; +R4 = R6 +|+ R4, R3 = R6 -|- R4; +R5 = R6 +|+ R5, R2 = R6 -|- R5; +R6 = R6 +|+ R6, R1 = R6 -|- R6; +R7 = R6 +|+ R7, R0 = R6 -|- R7; +CHECKREG r0, 0xEDF12BEC; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x34DDD515; +CHECKREG r3, 0x46D67717; +CHECKREG r4, 0x45F888D9; +CHECKREG r5, 0x57F12ADB; +CHECKREG r6, 0x8CCEFFF0; +CHECKREG r7, 0x2BABD3F4; + +imm32 r0, 0xf567a911; +imm32 r1, 0x2f8aab1d; +imm32 r2, 0x34a45515; +imm32 r3, 0x4a6f7717; +imm32 r4, 0x5567f91b; +imm32 r5, 0xa789af1d; +imm32 r6, 0x74445515; +imm32 r7, 0x866677f7; +R0 = R7 +|+ R0, R7 = R7 -|- R0; +R1 = R7 +|+ R1, R6 = R7 -|- R1; +R2 = R7 +|+ R2, R5 = R7 -|- R2; +R3 = R7 +|+ R3, R4 = R7 -|- R3; +R4 = R7 +|+ R4, R3 = R7 -|- R4; +R5 = R7 +|+ R5, R2 = R7 -|- R5; +R6 = R7 +|+ R6, R1 = R7 -|- R6; +R7 = R7 +|+ R7, R0 = R7 -|- R7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x2F8AAB1D; +CHECKREG r2, 0x34A45515; +CHECKREG r3, 0x4A6F7717; +CHECKREG r4, 0xD78F26B5; +CHECKREG r5, 0xED5A48B7; +CHECKREG r6, 0xF274F2AF; +CHECKREG r7, 0x21FE9DCC; + +imm32 r0, 0xe5678911; +imm32 r1, 0x2e89ab1d; +imm32 r2, 0x34e45515; +imm32 r3, 0x46667717; +imm32 r4, 0x556e891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x7444e515; +imm32 r7, 0x86667e77; +R4 = R2 +|+ R5, R3 = R2 -|- R5 (S); +R0 = R5 +|+ R3, R5 = R5 -|- R3 (CO); +R2 = R6 +|+ R2, R0 = R6 -|- R2 (SCO); +R3 = R4 +|+ R0, R2 = R4 -|- R0 (S); +R7 = R7 +|+ R6, R6 = R7 -|- R6 (CO); +R6 = R1 +|+ R7, R1 = R1 -|- R7 (SCO); +R5 = R0 +|+ R4, R7 = R0 -|- R4 (S); +R1 = R3 +|+ R1, R4 = R3 -|- R1 (CO); +CHECKREG r0, 0x90003F60; +CHECKREG r1, 0x8FFF7371; +CHECKREG r2, 0x7FFFC0D2; +CHECKREG r3, 0x0FFF3F92; +CHECKREG r4, 0x0BB38FFF; +CHECKREG r5, 0x0FFF3F92; +CHECKREG r6, 0x29330EA9; +CHECKREG r7, 0x80003F2E; + +imm32 r0, 0xd5678911; +imm32 r1, 0xff89ab1d; +imm32 r2, 0x34f45515; +imm32 r3, 0x46667717; +imm32 r4, 0x556f891b; +imm32 r5, 0x6789fb1d; +imm32 r6, 0x74445f15; +imm32 r7, 0x866677f7; +R4 = R3 +|+ R3, R5 = R3 -|- R3 (SCO); +R1 = R6 +|+ R1, R6 = R6 -|- R1 (SCO); +R6 = R1 +|+ R4, R4 = R1 -|- R4 (S); +R7 = R4 +|+ R2, R0 = R4 -|- R2 (S); +R2 = R2 +|+ R6, R1 = R2 -|- R6 (CO); +R3 = R5 +|+ R5, R7 = R5 -|- R5 (CO); +R5 = R7 +|+ R7, R3 = R7 -|- R7 (SCO); +R0 = R0 +|+ R0, R2 = R0 -|- R0 (SCO); +CHECKREG r0, 0x80008000; +CHECKREG r1, 0xD516B4F5; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xF3CE8A33; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x00000000; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft.s new file mode 100644 index 0000000..027f516 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft.s @@ -0,0 +1,261 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft/c_dsp32alu_rrppmm_sft.dsp +// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, << +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x95679911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34945515; + imm32 r3, 0x46967717; + imm32 r4, 0x5597891b; + imm32 r5, 0x6989ab1d; + imm32 r6, 0x94445515; + imm32 r7, 0x96667777; + R0 = R0 +|+ R0, R7 = R0 -|- R0 (ASR); + R1 = R0 +|+ R1, R6 = R0 -|- R1 (ASL); + R2 = R0 +|+ R2, R5 = R0 -|- R2 (ASR); + R3 = R0 +|+ R3, R4 = R0 -|- R3 (ASR); + R4 = R0 +|+ R4, R3 = R0 -|- R4 (ASL); + R5 = R0 +|+ R5, R2 = R0 -|- R5 (ASR); + R6 = R0 +|+ R6, R1 = R0 -|- R6 (ASL); + R7 = R0 +|+ R7, R0 = R0 -|- R7 (ASR); + CHECKREG r0, 0xcAB3cC88; + CHECKREG r1, 0x73567A52; + CHECKREG r2, 0xf27FfB89; + CHECKREG r3, 0xdBFE1028; + CHECKREG r4, 0x799E541C; + CHECKREG r5, 0xa2E89D87; + CHECKREG r6, 0xE246e9F2; + CHECKREG r7, 0xcAB3cC88; + + imm32 r0, 0x11678911; + imm32 r1, 0xa719ab1d; + imm32 r2, 0x3a415515; + imm32 r3, 0x46a67717; + imm32 r4, 0x556a891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445a15; + imm32 r7, 0x866677a7; + R0 = R1 +|+ R0, R7 = R1 -|- R0 (ASR); + R1 = R1 +|+ R1, R6 = R1 -|- R1 (ASR); + R2 = R1 +|+ R2, R5 = R1 -|- R2 (ASL); + R3 = R1 +|+ R3, R4 = R1 -|- R3 (ASR); + R4 = R1 +|+ R4, R3 = R1 -|- R4 (ASR); + R5 = R1 +|+ R5, R2 = R1 -|- R5 (ASR); + R6 = R1 +|+ R6, R1 = R1 -|- R6 (ASL); + R7 = R1 +|+ R7, R0 = R1 -|- R7 (ASR); + CHECKREG r0, 0x41AC229A; + CHECKREG r1, 0x4E32563A; + CHECKREG r2, 0xe6B4fF86; + CHECKREG r3, 0xfB70088D; + CHECKREG r4, 0xaBA9a290; + CHECKREG r5, 0xc064aB96; + CHECKREG r6, 0x4E32563A; + CHECKREG r7, 0x0C8533A0; + + imm32 r0, 0xb567891b; + imm32 r1, 0x2b89abbd; + imm32 r2, 0x34b45b15; + imm32 r3, 0x466bb717; + imm32 r4, 0x556bb91b; + imm32 r5, 0x67b9ab1d; + imm32 r6, 0x7b4455b5; + imm32 r7, 0xb666777b; + R0 = R2 +|+ R0, R7 = R2 -|- R0 (ASR); + R1 = R2 +|+ R1, R6 = R2 -|- R1 (ASR); + R2 = R2 +|+ R2, R5 = R2 -|- R2 (ASR); + R3 = R2 +|+ R3, R4 = R2 -|- R3 (ASL); + R4 = R2 +|+ R4, R3 = R2 -|- R4 (ASR); + R5 = R2 +|+ R5, R2 = R2 -|- R5 (ASR); + R6 = R2 +|+ R6, R1 = R2 -|- R6 (ASL); + R7 = R2 +|+ R7, R0 = R2 -|- R7 (ASR); + CHECKREG r0, 0xED5Ae246; + CHECKREG r1, 0x2B8AaBBC; + CHECKREG r2, 0x1A5A2D8A; + CHECKREG r3, 0x2C11098C; + CHECKREG r4, 0x08A35188; + CHECKREG r5, 0x1A5A2D8A; + CHECKREG r6, 0x3DDE0A6C; + CHECKREG r7, 0x2D004B43; + + imm32 r0, 0xbc678c11; + imm32 r1, 0x27c9cb1d; + imm32 r2, 0x344c5515; + imm32 r3, 0x46c6c717; + imm32 r4, 0x55678c1b; + imm32 r5, 0x6c89abcd; + imm32 r6, 0x7444551c; + imm32 r7, 0x8c667777; + R0 = R3 +|+ R0, R7 = R3 -|- R0 (ASL); + R1 = R3 +|+ R1, R6 = R3 -|- R1 (ASR); + R2 = R3 +|+ R2, R5 = R3 -|- R2 (ASR); + R3 = R3 +|+ R3, R4 = R3 -|- R3 (ASR); + R4 = R3 +|+ R4, R3 = R3 -|- R4 (ASL); + R5 = R3 +|+ R5, R2 = R3 -|- R5 (ASR); + R6 = R3 +|+ R6, R1 = R3 -|- R6 (ASR); + R7 = R3 +|+ R7, R0 = R3 -|- R7 (ASL); + CHECKREG r0, 0xF19C3044; + CHECKREG r1, 0xbF07C818; + CHECKREG r2, 0xC227eA96; + CHECKREG r3, 0x8D8C8E2E; + CHECKREG r4, 0x8D8C8E2E; + CHECKREG r5, 0xCB64a397; + CHECKREG r6, 0xCE85C615; + CHECKREG r7, 0x44940874; + + imm32 r0, 0xd56789d1; + imm32 r1, 0x2d89abdd; + imm32 r2, 0x34d455d5; + imm32 r3, 0x4d667717; + imm32 r4, 0x5dd7891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0xd44d5515; + imm32 r7, 0xd666d777; + R0 = R4 +|+ R0, R7 = R4 -|- R0 (ASR); + R1 = R4 +|+ R1, R6 = R4 -|- R1 (ASR); + R2 = R4 +|+ R2, R5 = R4 -|- R2 (ASR); + R3 = R4 +|+ R3, R4 = R4 -|- R3 (ASL); + R4 = R4 +|+ R4, R3 = R4 -|- R4 (ASR); + R5 = R4 +|+ R5, R2 = R4 -|- R5 (ASL); + R6 = R4 +|+ R6, R1 = R4 -|- R6 (ASR); + R7 = R4 +|+ R7, R0 = R4 -|- R7 (ASR); + CHECKREG r0, 0xeE551231; + CHECKREG r1, 0x045D1AB4; + CHECKREG r2, 0x18C214CA; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x20E22408; + CHECKREG r5, 0x6AC67B56; + CHECKREG r6, 0x1C840953; + CHECKREG r7, 0x328D11D6; + + imm32 r0, 0xc567a911; + imm32 r1, 0x278aab1d; + imm32 r2, 0x3c445515; + imm32 r3, 0x46a67717; + imm32 r4, 0x55c7891b; + imm32 r5, 0x6a8cab1d; + imm32 r6, 0x7444c515; + imm32 r7, 0xa6667c77; + R0 = R5 +|+ R0, R7 = R5 -|- R0 (ASR); + R1 = R5 +|+ R1, R6 = R5 -|- R1 (ASL); + R2 = R5 +|+ R2, R5 = R5 -|- R2 (ASR); + R3 = R5 +|+ R3, R4 = R5 -|- R3 (ASR); + R4 = R5 +|+ R4, R3 = R5 -|- R4 (ASR); + R5 = R5 +|+ R5, R2 = R5 -|- R5 (ASL); + R6 = R5 +|+ R6, R1 = R5 -|- R6 (ASR); + R7 = R5 +|+ R7, R0 = R5 -|- R7 (ASR); + CHECKREG r0, 0x04FFD585; + CHECKREG r1, 0x6B46D608; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x17720887; + CHECKREG r4, 0xFFB1a27D; + CHECKREG r5, 0x5C90AC10; + CHECKREG r6, 0xF14AD608; + CHECKREG r7, 0x5791D68B; + + imm32 r0, 0xd5678911; + imm32 r1, 0x2ddddd1d; + imm32 r2, 0x34ddd515; + imm32 r3, 0x46d67717; + imm32 r4, 0x5d6d891b; + imm32 r5, 0x6789db1d; + imm32 r6, 0x74445d15; + imm32 r7, 0xd66677d7; + R0 = R6 +|+ R0, R7 = R6 -|- R0 (ASR); + R1 = R6 +|+ R1, R6 = R6 -|- R1 (ASR); + R2 = R6 +|+ R2, R5 = R6 -|- R2 (ASR); + R3 = R6 +|+ R3, R4 = R6 -|- R3 (ASL); + R4 = R6 +|+ R4, R3 = R6 -|- R4 (ASR); + R5 = R6 +|+ R5, R2 = R6 -|- R5 (ASR); + R6 = R6 +|+ R6, R1 = R6 -|- R6 (ASL); + R7 = R6 +|+ R7, R0 = R6 -|- R7 (ASR); + CHECKREG r0, 0x9EAFcAF7; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x16040544; + CHECKREG r3, 0x353C5719; + CHECKREG r4, 0xEDF6E8E3; + CHECKREG r5, 0x0D2F3AB7; + CHECKREG r6, 0x8CCCFFF0; + CHECKREG r7, 0xeE1D34F9; + + imm32 r0, 0xf567a911; + imm32 r1, 0x2f8aab1d; + imm32 r2, 0x34a45515; + imm32 r3, 0x4a6f7717; + imm32 r4, 0x5567f91b; + imm32 r5, 0xa789af1d; + imm32 r6, 0x74445515; + imm32 r7, 0x866677f7; + R0 = R7 +|+ R0, R7 = R7 -|- R0 (ASR); + R1 = R7 +|+ R1, R6 = R7 -|- R1 (ASL); + R2 = R7 +|+ R2, R5 = R7 -|- R2 (ASR); + R3 = R7 +|+ R3, R4 = R7 -|- R3 (ASR); + R4 = R7 +|+ R4, R3 = R7 -|- R4 (ASL); + R5 = R7 +|+ R5, R2 = R7 -|- R5 (ASL); + R6 = R7 +|+ R6, R1 = R7 -|- R6 (ASR); + R7 = R7 +|+ R7, R0 = R7 -|- R7 (ASL); + CHECKREG r0, 0x00000000; + CHECKREG r1, 0xCB4Af763; + CHECKREG r2, 0xFD24bC88; + CHECKREG r3, 0x12EEdE8A; + CHECKREG r4, 0x0F0EbF42; + CHECKREG r5, 0x24D8e144; + CHECKREG r6, 0xFD34700F; + CHECKREG r7, 0x21FC9DCC; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2e89ab1d; + imm32 r2, 0x34e45515; + imm32 r3, 0x46667717; + imm32 r4, 0x556e891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x7444e515; + imm32 r7, 0x86667e77; + R4 = R2 +|+ R5, R3 = R2 -|- R5 (ASR); + R0 = R5 +|+ R3, R5 = R5 -|- R3 (ASL); + R2 = R6 +|+ R2, R0 = R6 -|- R2 (ASL); + R3 = R4 +|+ R0, R2 = R4 -|- R0 (ASR); + R7 = R7 +|+ R6, R6 = R7 -|- R6 (ASL); + R6 = R1 +|+ R7, R1 = R1 -|- R7 (ASL); + R5 = R0 +|+ R4, R7 = R0 -|- R4 (ASR); + R1 = R3 +|+ R1, R4 = R3 -|- R1 (ASR); + CHECKREG r0, 0x7EC02000; + CHECKREG r1, 0x6C72EC0B; + CHECKREG r2, 0xe7BBF00C; + CHECKREG r3, 0x667B100C; + CHECKREG r4, 0xfA082401; + CHECKREG r5, 0x667B100C; + CHECKREG r6, 0x47BAE46A; + CHECKREG r7, 0x18450FF3; + + imm32 r0, 0xd5678911; + imm32 r1, 0xff89ab1d; + imm32 r2, 0x34f45515; + imm32 r3, 0x46667717; + imm32 r4, 0x556f891b; + imm32 r5, 0x6789fb1d; + imm32 r6, 0x74445f15; + imm32 r7, 0x866677f7; + R4 = R3 +|+ R3, R5 = R3 -|- R3 (ASR); + R1 = R6 +|+ R1, R6 = R6 -|- R1 (ASL); + R6 = R1 +|+ R4, R4 = R1 -|- R4 (ASL); + R7 = R4 +|+ R2, R0 = R4 -|- R2 (ASR); + R2 = R2 +|+ R6, R1 = R2 -|- R6 (ASR); + R3 = R5 +|+ R5, R7 = R5 -|- R5 (ASL); + R5 = R7 +|+ R7, R3 = R7 -|- R7 (ASL); + R0 = R0 +|+ R0, R2 = R0 -|- R0 (ASR); + CHECKREG r0, 0x06BAF2C2; + CHECKREG r1, 0xEC7A1F0F; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x42683A9A; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x5C0016F6; + CHECKREG r7, 0x00000000; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft_x.s b/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft_x.s new file mode 100644 index 0000000..32913f6 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft_x.s @@ -0,0 +1,261 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft_x/c_dsp32alu_rrppmm_sft_x.dsp +// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, << X +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x95679911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34945515; + imm32 r3, 0x46967717; + imm32 r4, 0x5597891b; + imm32 r5, 0x6989ab1d; + imm32 r6, 0x94445515; + imm32 r7, 0x96667777; + R0 = R0 +|+ R0, R7 = R0 -|- R0 (CO , ASR); + R1 = R0 +|+ R1, R6 = R0 -|- R1 (CO , ASL); + R2 = R0 +|+ R2, R5 = R0 -|- R2 (CO , ASR); + R3 = R0 +|+ R3, R4 = R0 -|- R3 (CO , ASR); + R4 = R0 +|+ R4, R3 = R0 -|- R4 (CO , ASL); + R5 = R0 +|+ R5, R2 = R0 -|- R5 (CO , ASR); + R6 = R0 +|+ R6, R1 = R0 -|- R6 (CO , ASL); + R7 = R0 +|+ R7, R0 = R0 -|- R7 (CO , ASR); + CHECKREG r0, 0xcC88cAB3; + CHECKREG r1, 0x7AAA72FE; + CHECKREG r2, 0xf454f9B4; + CHECKREG r3, 0xe35208D4; + CHECKREG r4, 0x4CC880F2; + CHECKREG r5, 0x9BB2a4BD; + CHECKREG r6, 0xE29EE99A; + CHECKREG r7, 0xcAB3cC88; + + imm32 r0, 0x11678911; + imm32 r1, 0xa719ab1d; + imm32 r2, 0x3a415515; + imm32 r3, 0x46a67717; + imm32 r4, 0x556a891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445a15; + imm32 r7, 0x866677a7; + R0 = R1 +|+ R0, R7 = R1 -|- R0 (CO , ASR); + R1 = R1 +|+ R1, R6 = R1 -|- R1 (CO , ASR); + R2 = R1 +|+ R2, R5 = R1 -|- R2 (CO , ASL); + R3 = R1 +|+ R3, R4 = R1 -|- R3 (CO , ASR); + R4 = R1 +|+ R4, R3 = R1 -|- R4 (CO , ASR); + R5 = R1 +|+ R5, R2 = R1 -|- R5 (CO , ASR); + R6 = R1 +|+ R6, R1 = R1 -|- R6 (CO , ASL); + R7 = R1 +|+ R7, R0 = R1 -|- R7 (CO , ASR); + CHECKREG r0, 0x41AC229A; + CHECKREG r1, 0x563A4E32; + CHECKREG r2, 0xe8B6fD84; + CHECKREG r3, 0xfD72068B; + CHECKREG r4, 0xa08EaDAB; + CHECKREG r5, 0xa994c266; + CHECKREG r6, 0x4E32563A; + CHECKREG r7, 0x33A00C85; + + imm32 r0, 0xb567891b; + imm32 r1, 0x2b89abbd; + imm32 r2, 0x34b45b15; + imm32 r3, 0x466bb717; + imm32 r4, 0x556bb91b; + imm32 r5, 0x67b9ab1d; + imm32 r6, 0x7b4455b5; + imm32 r7, 0xb666777b; + R0 = R2 +|+ R0, R7 = R2 -|- R0 (CO , ASR); + R1 = R2 +|+ R1, R6 = R2 -|- R1 (CO , ASR); + R2 = R2 +|+ R2, R5 = R2 -|- R2 (CO , ASR); + R3 = R2 +|+ R3, R4 = R2 -|- R3 (CO , ASL); + R4 = R2 +|+ R4, R3 = R2 -|- R4 (CO , ASR); + R5 = R2 +|+ R5, R2 = R2 -|- R5 (CO , ASR); + R6 = R2 +|+ R6, R1 = R2 -|- R6 (CO , ASL); + R7 = R2 +|+ R7, R0 = R2 -|- R7 (CO , ASR); + CHECKREG r0, 0xED5Ae246; + CHECKREG r1, 0x2B8AaBBC; + CHECKREG r2, 0x2D8A1A5A; + CHECKREG r3, 0x3F41F65C; + CHECKREG r4, 0x3E581BD3; + CHECKREG r5, 0x1A5A2D8A; + CHECKREG r6, 0x0A6C3DDE; + CHECKREG r7, 0x4B432D00; + + imm32 r0, 0xbc678c11; + imm32 r1, 0x27c9cb1d; + imm32 r2, 0x344c5515; + imm32 r3, 0x46c6c717; + imm32 r4, 0x55678c1b; + imm32 r5, 0x6c89abcd; + imm32 r6, 0x7444551c; + imm32 r7, 0x8c667777; + R0 = R3 +|+ R0, R7 = R3 -|- R0 (CO , ASL); + R1 = R3 +|+ R1, R6 = R3 -|- R1 (CO , ASR); + R2 = R3 +|+ R2, R5 = R3 -|- R2 (CO , ASR); + R3 = R3 +|+ R3, R4 = R3 -|- R3 (CO , ASR); + R4 = R3 +|+ R4, R3 = R3 -|- R4 (CO , ASL); + R5 = R3 +|+ R5, R2 = R3 -|- R5 (CO , ASR); + R6 = R3 +|+ R6, R1 = R3 -|- R6 (CO , ASR); + R7 = R3 +|+ R7, R0 = R3 -|- R7 (CO , ASL); + CHECKREG r0, 0xF19C3044; + CHECKREG r1, 0xbF07C818; + CHECKREG r2, 0xC227eA96; + CHECKREG r3, 0x8E2E8D8C; + CHECKREG r4, 0x8D8C8E2E; + CHECKREG r5, 0xa397CB64; + CHECKREG r6, 0xC615CE85; + CHECKREG r7, 0x08744494; + + imm32 r0, 0xd56789d1; + imm32 r1, 0x2d89abdd; + imm32 r2, 0x34d455d5; + imm32 r3, 0x4d667717; + imm32 r4, 0x5dd7891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0xd44d5515; + imm32 r7, 0xd666d777; + R0 = R4 +|+ R0, R7 = R4 -|- R0 (CO , ASR); + R1 = R4 +|+ R1, R6 = R4 -|- R1 (CO , ASR); + R2 = R4 +|+ R2, R5 = R4 -|- R2 (CO , ASR); + R3 = R4 +|+ R3, R4 = R4 -|- R3 (CO , ASL); + R4 = R4 +|+ R4, R3 = R4 -|- R4 (CO , ASR); + R5 = R4 +|+ R5, R2 = R4 -|- R5 (CO , ASL); + R6 = R4 +|+ R6, R1 = R4 -|- R6 (CO , ASR); + R7 = R4 +|+ R7, R0 = R4 -|- R7 (CO , ASR); + CHECKREG r0, 0xeE551231; + CHECKREG r1, 0x045D1AB4; + CHECKREG r2, 0x18C214CA; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x240820E2; + CHECKREG r5, 0x7B566AC6; + CHECKREG r6, 0x09531C84; + CHECKREG r7, 0x11D6328D; + + imm32 r0, 0xc567a911; + imm32 r1, 0x278aab1d; + imm32 r2, 0x3c445515; + imm32 r3, 0x46a67717; + imm32 r4, 0x55c7891b; + imm32 r5, 0x6a8cab1d; + imm32 r6, 0x7444c515; + imm32 r7, 0xa6667c77; + R0 = R5 +|+ R0, R7 = R5 -|- R0 (CO , ASR); + R1 = R5 +|+ R1, R6 = R5 -|- R1 (CO , ASL); + R2 = R5 +|+ R2, R5 = R5 -|- R2 (CO , ASR); + R3 = R5 +|+ R3, R4 = R5 -|- R3 (CO , ASR); + R4 = R5 +|+ R4, R3 = R5 -|- R4 (CO , ASR); + R5 = R5 +|+ R5, R2 = R5 -|- R5 (CO , ASL); + R6 = R5 +|+ R6, R1 = R5 -|- R6 (CO , ASR); + R7 = R5 +|+ R7, R0 = R5 -|- R7 (CO , ASR); + CHECKREG r0, 0x04FFD585; + CHECKREG r1, 0x6B46D608; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x327AeD7F; + CHECKREG r4, 0xbD85e4A9; + CHECKREG r5, 0xAC105C90; + CHECKREG r6, 0xD608F14A; + CHECKREG r7, 0xD68B5791; + + imm32 r0, 0xd5678911; + imm32 r1, 0x2ddddd1d; + imm32 r2, 0x34ddd515; + imm32 r3, 0x46d67717; + imm32 r4, 0x5d6d891b; + imm32 r5, 0x6789db1d; + imm32 r6, 0x74445d15; + imm32 r7, 0xd66677d7; + R0 = R6 +|+ R0, R7 = R6 -|- R0 (CO , ASR); + R1 = R6 +|+ R1, R6 = R6 -|- R1 (CO , ASR); + R2 = R6 +|+ R2, R5 = R6 -|- R2 (CO , ASR); + R3 = R6 +|+ R3, R4 = R6 -|- R3 (CO , ASL); + R4 = R6 +|+ R4, R3 = R6 -|- R4 (CO , ASR); + R5 = R6 +|+ R5, R2 = R6 -|- R5 (CO , ASR); + R6 = R6 +|+ R6, R1 = R6 -|- R6 (CO , ASL); + R7 = R6 +|+ R7, R0 = R6 -|- R7 (CO , ASR); + CHECKREG r0, 0x9EAFcAF7; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x0ED20C76; + CHECKREG r3, 0x1873F3E2; + CHECKREG r4, 0x4C1A0ABF; + CHECKREG r5, 0x33851461; + CHECKREG r6, 0xFFF08CCC; + CHECKREG r7, 0x34F9eE1D; + + imm32 r0, 0xf567a911; + imm32 r1, 0x2f8aab1d; + imm32 r2, 0x34a45515; + imm32 r3, 0x4a6f7717; + imm32 r4, 0x5567f91b; + imm32 r5, 0xa789af1d; + imm32 r6, 0x74445515; + imm32 r7, 0x866677f7; + R0 = R7 +|+ R0, R7 = R7 -|- R0 (CO , ASR); + R1 = R7 +|+ R1, R6 = R7 -|- R1 (CO , ASL); + R2 = R7 +|+ R2, R5 = R7 -|- R2 (CO , ASR); + R3 = R7 +|+ R3, R4 = R7 -|- R3 (CO , ASR); + R4 = R7 +|+ R4, R3 = R7 -|- R4 (CO , ASL); + R5 = R7 +|+ R5, R2 = R7 -|- R5 (CO , ASL); + R6 = R7 +|+ R6, R1 = R7 -|- R6 (CO , ASR); + R7 = R7 +|+ R7, R0 = R7 -|- R7 (CO , ASL); + CHECKREG r0, 0x00000000; + CHECKREG r1, 0xaC561657; + CHECKREG r2, 0x5E305B7C; + CHECKREG r3, 0x73FA7D7E; + CHECKREG r4, 0x204EaE02; + CHECKREG r5, 0x4250c3CC; + CHECKREG r6, 0x511B1C28; + CHECKREG r7, 0x9DCC21FC; + + imm32 r0, 0xe5678911; + imm32 r1, 0x2e89ab1d; + imm32 r2, 0x34e45515; + imm32 r3, 0x46667717; + imm32 r4, 0x556e891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x7444e515; + imm32 r7, 0x86667e77; + R4 = R2 +|+ R5, R3 = R2 -|- R5 (CO , ASR); + R0 = R5 +|+ R3, R5 = R5 -|- R3 (CO , ASL); + R2 = R6 +|+ R2, R0 = R6 -|- R2 (CO , ASL); + R3 = R4 +|+ R0, R2 = R4 -|- R0 (CO , ASR); + R7 = R7 +|+ R6, R6 = R7 -|- R6 (CO , ASL); + R6 = R1 +|+ R7, R1 = R1 -|- R7 (CO , ASL); + R5 = R0 +|+ R4, R7 = R0 -|- R4 (CO , ASR); + R1 = R3 +|+ R1, R4 = R3 -|- R1 (CO , ASR); + CHECKREG r0, 0x20007EC0; + CHECKREG r1, 0xfF9258EB; + CHECKREG r2, 0xC0AC171B; + CHECKREG r3, 0x371B3F6C; + CHECKREG r4, 0xE6813788; + CHECKREG r5, 0x371B3F6C; + CHECKREG r6, 0x47BAE46A; + CHECKREG r7, 0x3F53e8E5; + + imm32 r0, 0xd5678911; + imm32 r1, 0xff89ab1d; + imm32 r2, 0x34f45515; + imm32 r3, 0x46667717; + imm32 r4, 0x556f891b; + imm32 r5, 0x6789fb1d; + imm32 r6, 0x74445f15; + imm32 r7, 0x866677f7; + R4 = R3 +|+ R3, R5 = R3 -|- R3 (CO , ASR); + R1 = R6 +|+ R1, R6 = R6 -|- R1 (CO , ASL); + R6 = R1 +|+ R4, R4 = R1 -|- R4 (CO , ASL); + R7 = R4 +|+ R2, R0 = R4 -|- R2 (CO , ASR); + R2 = R2 +|+ R6, R1 = R2 -|- R6 (CO , ASR); + R3 = R5 +|+ R5, R7 = R5 -|- R5 (CO , ASL); + R5 = R7 +|+ R7, R3 = R7 -|- R7 (CO , ASL); + R0 = R0 +|+ R0, R2 = R0 -|- R0 (CO , ASR); + CHECKREG r0, 0xF6A902D3; + CHECKREG r1, 0x1F0FEC7A; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x3A9A4268; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x5C0016F6; + CHECKREG r7, 0x00000000; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_saa.s b/sim/testsuite/sim/bfin/c_dsp32alu_saa.s new file mode 100644 index 0000000..6cb577e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_saa.s @@ -0,0 +1,70 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_saa/c_dsp32alu_saa.dsp +// Spec Reference: dsp32alu saa +# mach: bfin + +.include "testutils.inc" + start + + A1 = 0; + A0 = 0; + + imm32 r0, 0x15678911; + imm32 r1, 0x2789ab1d; + imm32 r2, 0x34445515; + imm32 r3, 0x46667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0x74445515; + imm32 r7, 0x86667777; + A0 = 0; + A1 = 0; + SAA ( R1:0 , R3:2 ); + R4 = A0.w; + R5 = A1.w; + CHECKREG r4, 0x00340004; + CHECKREG r5, 0x001F0023; + SAA ( R3:2 , R1:0 ); + R6 = A0.w; + R7 = A1.w; + CHECKREG r6, 0x00680008; + CHECKREG r7, 0x003E0046; + + imm32 r0, 0x1567892b; + imm32 r1, 0x2789ab2d; + imm32 r2, 0x34445525; + imm32 r3, 0x46667727; + imm32 r4, 0x00340004; + imm32 r5, 0x001F0023; + imm32 r6, 0x00680008; + imm32 r7, 0x003E0046; + SAA ( R1:0 , R3:2 ); + R0 = A0.w; + R1 = A1.w; + CHECKREG r0, 0x009C000E; + CHECKREG r1, 0x005D0069; + SAA ( R3:2 , R1:0 ); + R2 = A0.w; + R3 = A1.w; + CHECKREG r2, 0x00F10025; + CHECKREG r3, 0x009100C1; + + imm32 r0, 0x496789ab; + imm32 r1, 0x6489abcd; + imm32 r2, 0x4b445555; + imm32 r3, 0x6c647777; + imm32 r4, 0x8d889999; + imm32 r5, 0xaeaa4bbb; + imm32 r6, 0xcfccd44d; + imm32 r7, 0xe1eefff4; + SAA ( R3:2 , R1:0 ) (R); + R0 = A0.w; + R1 = A1.w; + CHECKREG r0, 0x0125007B; + CHECKREG r1, 0x009900E6; + SAA ( R1:0 , R3:2 ) (R); + R6 = A0.w; + R7 = A1.w; + CHECKREG r6, 0x019C00EA; + CHECKREG r7, 0x0105011B; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_sat_aa.S b/sim/testsuite/sim/bfin/c_dsp32alu_sat_aa.S new file mode 100644 index 0000000..981de01 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_sat_aa.S @@ -0,0 +1,41 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32alu_sat_aa/c_dsp32alu_sat_aa.dsp +// Spec Reference: dsp32alu sat ( a1, a0) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + A0 = A1 = 0; + + imm32 r0, 0xabefda8f; + imm32 r1, 0x789abced; + imm32 r2, 0x3b44b515; + imm32 r3, 0x96667717; + imm32 r4, 0x5567891b; + imm32 r5, 0x6789ab1d; + imm32 r6, 0xabcdef89; + imm32 r7, 0xefadbc8a; + A0 = R0; + A1 = R1; + A1 = A1 (S), A0 = A0 (S); + R0 = ASTAT; + R2 = A0.w; + R3 = A1.w; + + A0 = R6; + A1 = R7; + A1 = A1 (S), A0 = A0 (S); + R1 = ASTAT; + R4 = A0.w; + R5 = A1.w; + CHECKREG r0, _AN; + CHECKREG r1, _AN; + CHECKREG r2, 0xABEFDA8F; + CHECKREG r3, 0x789ABCED; + CHECKREG r4, 0xABCDEF89; + CHECKREG r5, 0xEFADBC8A; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_search.s b/sim/testsuite/sim/bfin/c_dsp32alu_search.s new file mode 100644 index 0000000..68b3d32 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_search.s @@ -0,0 +1,74 @@ +//Original:/testcases/core/c_dsp32alu_search/c_dsp32alu_search.dsp +// Spec Reference: dsp32alu search +# mach: bfin + +.include "testutils.inc" + start + +imm32 p0, 0x11234556; + +imm32 r0, 0x15678911; +imm32 r1, 0x2789ab1d; +imm32 r2, 0x34445515; +imm32 r3, 0x46667717; +imm32 r4, 0x5567891b; +imm32 r5, 0x6789ab1d; +imm32 r6, 0x74445515; +imm32 r7, 0x86667777; +( R0 , R1 ) = SEARCH R2 (GE); +( R2 , R3 ) = SEARCH R4 (GT); +( R4 , R5 ) = SEARCH R0 (LE); +( R7 , R6 ) = SEARCH R1 (LT); +CHECKREG r0, 0x11234556; +CHECKREG r1, 0x11234556; +CHECKREG r2, 0x11234556; +CHECKREG r3, 0x46667717; +CHECKREG r4, 0x11234556; +CHECKREG r5, 0x11234556; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x86667777; + +imm32 r0, 0x416789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x43445555; +imm32 r3, 0x64667777; +imm32 r0, 0x456789ab; +imm32 r1, 0x6689abcd; +imm32 r2, 0x47445555; +imm32 r3, 0x68667777; +( R2 , R1 ) = SEARCH R3 (LE); +( R6 , R3 ) = SEARCH R5 (GT); +( R4 , R7 ) = SEARCH R2 (GE); +( R0 , R5 ) = SEARCH R4 (LT); +CHECKREG r0, 0x11234556; +CHECKREG r1, 0x6689ABCD; +CHECKREG r2, 0x47445555; +CHECKREG r3, 0x68667777; +CHECKREG r4, 0x11234556; +CHECKREG r5, 0x11234556; +CHECKREG r6, 0x74445515; +CHECKREG r7, 0x11234556; + +imm32 r0, 0x516789ab; +imm32 r1, 0x6289abcd; +imm32 r2, 0x73445555; +imm32 r3, 0x84667777; +imm32 r0, 0x956789ab; +imm32 r1, 0xa689abcd; +imm32 r2, 0xb7445555; +imm32 r3, 0xc86def77; +( R3 , R4 ) = SEARCH R5 (GT); +( R0 , R7 ) = SEARCH R6 (GE); +( R6 , R1 ) = SEARCH R2 (LT); +( R2 , R5 ) = SEARCH R4 (LE); +CHECKREG r0, 0x11234556; +CHECKREG r1, 0xA689ABCD; +CHECKREG r2, 0xB7445555; +CHECKREG r3, 0xC86DEF77; +CHECKREG r4, 0x11234556; +CHECKREG r5, 0x11234556; +CHECKREG r6, 0x11234556; +CHECKREG r7, 0x11234556; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32alu_sgn.s b/sim/testsuite/sim/bfin/c_dsp32alu_sgn.s new file mode 100644 index 0000000..de36c20 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32alu_sgn.s @@ -0,0 +1,39 @@ +//Original:/testcases/core/c_dsp32alu_sgn/c_dsp32alu_sgn.dsp +// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x456789ab; +imm32 r1, 0x6689abcd; +imm32 r2, 0x47445555; +imm32 r3, 0x68667777; +R4.H = R4.L = SIGN(R2.H) * R0.H + SIGN(R2.L) * R0.L; +R5.H = R5.L = SIGN(R2.H) * R1.H + SIGN(R2.L) * R1.L; +R6.H = R6.L = SIGN(R2.H) * R2.H + SIGN(R2.L) * R2.L; +R7.H = R7.L = SIGN(R2.H) * R3.H + SIGN(R2.L) * R3.L; +CHECKREG r4, 0xCF12CF12; +CHECKREG r5, 0x12561256; +CHECKREG r6, 0x9C999C99; +CHECKREG r7, 0xDFDDDFDD; + +imm32 r0, 0x496789ab; +imm32 r1, 0x6489abcd; +imm32 r2, 0x4b445555; +imm32 r3, 0x6c647777; +imm32 r4, 0x8d889999; +imm32 r5, 0xaeaa4bbb; +imm32 r6, 0xcfccd44d; +imm32 r7, 0xe1eefff4; +R0.H = R0.L = SIGN(R3.H) * R4.H + SIGN(R3.L) * R4.L; +R1.H = R1.L = SIGN(R3.H) * R5.H + SIGN(R3.L) * R5.L; +R2.H = R2.L = SIGN(R3.H) * R6.H + SIGN(R3.L) * R6.L; +R3.H = R3.L = SIGN(R3.H) * R7.H + SIGN(R3.L) * R7.L; +CHECKREG r0, 0x27212721; +CHECKREG r1, 0xFA65FA65; +CHECKREG r2, 0xA419A419; +CHECKREG r3, 0xE1E2E1E2; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_a1a0.s b/sim/testsuite/sim/bfin/c_dsp32mac_a1a0.s new file mode 100644 index 0000000..25c2a2d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_a1a0.s @@ -0,0 +1,255 @@ +//Original:/testcases/core/c_dsp32mac_a1a0/c_dsp32mac_a1a0.dsp +// Spec Reference: dsp32mac a1 a0 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 r0, 0x00000000; +A0 = 0; +A1 = 0; +ASTAT = r0; + + +// test the default (signed fraction : left ) +imm32 r0, 0x12345678; +imm32 r1, 0x33456789; +imm32 r2, 0x5556789a; +imm32 r3, 0x75678912; +imm32 r4, 0x86789123; +imm32 r5, 0xa7891234; +imm32 r6, 0xc1234567; +imm32 r7, 0xf1234567; +A1 = R0.L * R1.L, A0 = R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 = R2.L * R3.L, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 += R4.L * R5.L, A0 = R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.L * R7.L, A0 += R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x45F11C70; +CHECKREG r1, 0x45F11C70; +CHECKREG r2, 0xB48EEC5C; +CHECKREG r3, 0x8FF1C9A8; +CHECKREG r4, 0xEEB780C0; +CHECKREG r5, 0x802DABE0; +CHECKREG r6, 0xF6043652; +CHECKREG r7, 0xA5CF0AC2; + +imm32 r0, 0x12245618; +imm32 r1, 0x23256719; +imm32 r2, 0x3426781a; +imm32 r3, 0x45278912; +imm32 r4, 0x56289113; +imm32 r5, 0x67291214; +imm32 r6, 0xa1234517; +imm32 r7, 0xc1234517; +A1 = R0.L * R1.H, A0 += R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 = R2.L * R3.H, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 = R4.L * R5.H, A0 += R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 = R6.L * R7.H, A0 += R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x3B5C5702; +CHECKREG r1, 0x17A372F0; +CHECKREG r2, 0x7C3EF2EE; +CHECKREG r3, 0x40E29BEC; +CHECKREG r4, 0x886A092E; +CHECKREG r5, 0xA699C216; +CHECKREG r6, 0xB700DEC0; +CHECKREG r7, 0xDE11924A; + +imm32 r0, 0x15245648; +imm32 r1, 0x25256749; +imm32 r2, 0x3526784a; +imm32 r3, 0x45278942; +imm32 r4, 0x55389143; +imm32 r5, 0x65391244; +imm32 r6, 0xa5334547; +imm32 r7, 0xc5334547; +A1 += R0.H * R1.H, A0 = R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 += R2.H * R3.H, A0 = R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 += R4.H * R5.H, A0 = R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.H * R7.H, A0 = R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x459F2510; +CHECKREG r1, 0xE43416B2; +CHECKREG r2, 0x40FC8A8C; +CHECKREG r3, 0x00EAC446; +CHECKREG r4, 0x0C2925C0; +CHECKREG r5, 0x444EE736; +CHECKREG r6, 0x29B65052; +CHECKREG r7, 0x6E053788; + + +imm32 r0, 0x13245628; +imm32 r1, 0x23256729; +imm32 r2, 0x3326782a; +imm32 r3, 0x43278922; +imm32 r4, 0x56389123; +imm32 r5, 0x67391224; +imm32 r6, 0xa1334527; +imm32 r7, 0xc1334527; +A1 += R0.H * R1.L, A0 += R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 = R2.H * R3.L, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 = R4.H * R5.L, A0 += R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 = R6.H * R7.L, A0 += R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x6F261922; +CHECKREG r1, 0x7D725110; +CHECKREG r2, 0xAE30B1EE; +CHECKREG r3, 0xD0804218; +CHECKREG r4, 0xBA68D1AE; +CHECKREG r5, 0x0C381FC0; +CHECKREG r6, 0xE8EBF200; +CHECKREG r7, 0xCCC89B8A; + + +imm32 r0, 0x01340678; +imm32 r1, 0x02450789; +imm32 r2, 0x0356089a; +imm32 r3, 0x04670912; +imm32 r4, 0x05780123; +imm32 r5, 0x06890234; +imm32 r6, 0x07230567; +imm32 r7, 0x00230567; +A1 -= R0.L * R1.L, A0 = R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 = R2.L * R3.L, A0 -= R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 -= R4.L * R5.L, A0 -= R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 -= R6.L * R7.L, A0 += R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x00617C70; +CHECKREG r1, 0xCC671F1A; +CHECKREG r2, 0x0015C084; +CHECKREG r3, 0x009C09A8; +CHECKREG r4, 0xFFFDA7C4; +CHECKREG r5, 0x00970770; +CHECKREG r6, 0xFFFF9B56; +CHECKREG r7, 0x005CA88E; + +imm32 r0, 0x00245618; +imm32 r1, 0x01256719; +imm32 r2, 0x0226781a; +imm32 r3, 0x03278912; +imm32 r4, 0x06489113; +imm32 r5, 0x05291214; +imm32 r6, 0x01634517; +imm32 r7, 0x02234517; +A1 += R0.L * R1.H, A0 -= R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 -= R2.L * R3.H, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 -= R4.L * R5.H, A0 -= R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.L * R7.H, A0 -= R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0xBAA77AA6; +CHECKREG r1, 0x0121BB7E; +CHECKREG r2, 0xBD9CAE92; +CHECKREG r3, 0xFE2C8792; +CHECKREG r4, 0xBCB99352; +CHECKREG r5, 0x02A5517C; +CHECKREG r6, 0xBCB3A640; +CHECKREG r7, 0x03CC91C6; + +imm32 r0, 0x10240648; +imm32 r1, 0x25156749; +imm32 r2, 0x3526084a; +imm32 r3, 0x45238942; +imm32 r4, 0x51381143; +imm32 r5, 0x62392244; +imm32 r6, 0xa3333547; +imm32 r7, 0xc4334547; +A1 += R0.H * R1.H, A0 -= R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 -= R2.H * R3.H, A0 -= R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 -= R4.H * R5.H, A0 += R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.H * R7.H, A0 -= R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0xB7A22130; +CHECKREG r1, 0x08799FAE; +CHECKREG r2, 0xB327F8F4; +CHECKREG r3, 0xEBC49B4A; +CHECKREG r4, 0xC8E5FEB4; +CHECKREG r5, 0xAD71905A; +CHECKREG r6, 0x9D8AE062; +CHECKREG r7, 0xD8CCAEAC; + + +imm32 r0, 0x10245628; +imm32 r1, 0x23056729; +imm32 r2, 0x3320782a; +imm32 r3, 0x43270922; +imm32 r4, 0x56389023; +imm32 r5, 0x67391024; +imm32 r6, 0x21334507; +imm32 r7, 0x11334520; +A1 += R0.H * R1.L, A0 -= R0.L * R1.L; +R0 = A0.w; +R1 = A1.w; +A1 -= R2.H * R3.L, A0 += R2.L * R3.H; +R2 = A0.w; +R3 = A1.w; +A1 -= R4.H * R5.L, A0 -= R4.H * R5.L; +R4 = A0.w; +R5 = A1.w; +A1 += R6.H * R7.L, A0 -= R6.H * R7.H; +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x581B1792; +CHECKREG r1, 0xE5CED234; +CHECKREG r2, 0x9725B05E; +CHECKREG r3, 0xE228FDB4; +CHECKREG r4, 0x8C46709E; +CHECKREG r5, 0xD749BDF4; +CHECKREG r6, 0x87D0704C; +CHECKREG r7, 0xE93788B4; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_iuw32.s b/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_iuw32.s new file mode 100644 index 0000000..16910ff --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_iuw32.s @@ -0,0 +1,1014 @@ +//Original:/testcases/core/c_dsp32mac_a1a0_iuw32/c_dsp32mac_a1a0_iuw32.dsp +// Spec Reference: dsp32mac a1 a0 iuw32 MNOP +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 r0, 0x00000000; +A0 = 0; +A1 = 0; +ASTAT = r0; + + +// test the (signed integer: no ) I=1 +imm32 r0, 0x22345628; +imm32 r1, 0x23456729; +imm32 r2, 0x3456782a; +imm32 r3, 0x45678922; +imm32 r4, 0x56789123; +imm32 r5, 0x67891224; +imm32 r6, 0xa1234527; +imm32 r7, 0xc1234567; +A1 = R0.L * R7.L, A0 = R0.L * R7.L (IS); +R0 = A0.w; +R7 = A1.w; +A1 = R6.L * R1.L, A0 += R6.L * R1.H (IS); +R6 = A0.w; +R1 = A1.w; +A1 += R2.L * R3.L, A0 = R2.H * R3.L (IS); +R2 = A0.w; +R3 = A1.w; +A1 += R5.L * R4.L, A0 += R5.H * R4.H (IS); +R5 = A0.w; +R4 = A1.w; +CHECKREG r0, 0x175B7218; +CHECKREG r1, 0x1BDDC43F; +CHECKREG r2, 0xE7B2F96C; +CHECKREG r3, 0xE41233D3; +CHECKREG r4, 0xDC3712BF; +CHECKREG r5, 0x0AAB87A4; +CHECKREG r6, 0x20E26A9B; +CHECKREG r7, 0x175B7218; + +imm32 r0, 0x13335678; +imm32 r1, 0x23436789; +imm32 r2, 0x3353789a; +imm32 r3, 0xa3638912; +imm32 r4, 0x53739123; +imm32 r5, 0x63831234; +imm32 r6, 0xa1234567; +imm32 r7, 0xc1234567; +A1 = R2.L * R7.H, A0 += R2.L * R7.L (IS); +R2 = A0.w; +R7 = A1.w; +A1 = R6.L * R1.H, A0 += R6.L * R1.H (IS); +R6 = A0.w; +R1 = A1.w; +A1 += R0.L * R5.H, A0 = R0.H * R5.L (IS); +R0 = A0.w; +R5 = A1.w; +A1 += R4.L * R3.H, A0 = R4.H * R3.H (IS); +R4 = A0.w; +R3 = A1.w; +CHECKREG r0, 0x015D7C5C; +CHECKREG r1, 0x098F3EF5; +CHECKREG r2, 0x2B5D8F9A; +CHECKREG r3, 0x53474FE6; +CHECKREG r4, 0xE1CF7E79; +CHECKREG r5, 0x2B2BE65D; +CHECKREG r6, 0x34ECCE8F; +CHECKREG r7, 0xE262970E; + +imm32 r0, 0x14345678; +imm32 r1, 0x24456789; +imm32 r2, 0x3456789a; +imm32 r3, 0x44678912; +imm32 r4, 0x54789123; +imm32 r5, 0x67891244; +imm32 r6, 0xa1234547; +imm32 r7, 0xc1234547; +A1 += R4.H * R0.L, A0 = R4.L * R0.L (IS); +R4 = A0.w; +R0 = A1.w; +A1 = R3.H * R1.L, A0 += R3.L * R1.H (IS); +R3 = A0.w; +R1 = A1.w; +A1 = R2.H * R6.L, A0 = R2.H * R6.L (IS); +R2 = A0.w; +R6 = A1.w; +A1 += R7.H * R5.L, A0 += R7.H * R5.H (IS); +R7 = A0.w; +R5 = A1.w; +CHECKREG r0, 0x6FCF3826; +CHECKREG r1, 0x1BAA0C1F; +CHECKREG r2, 0x0E29B1DA; +CHECKREG r3, 0xC9B44442; +CHECKREG r4, 0xDA8DCA68; +CHECKREG r5, 0x09AD7526; +CHECKREG r6, 0x0E29B1DA; +CHECKREG r7, 0xF4BD2295; + +imm32 r0, 0x15345678; +imm32 r1, 0x23556789; +imm32 r2, 0x3455789a; +imm32 r3, 0x45675912; +imm32 r4, 0x56789523; +imm32 r5, 0x67891234; +imm32 r6, 0xa1234557; +imm32 r7, 0xc1234565; +A1 += R0.H * R1.H, A0 = R0.L * R1.L (IS); +R0 = A0.w; +R1 = A1.w; +A1 = R5.H * R6.H, A0 = R5.L * R6.H (IS); +R5 = A0.w; +R6 = A1.w; +A1 = R4.H * R3.H, A0 += R4.H * R3.L (IS); +R4 = A0.w; +R3 = A1.w; +A1 = R2.H * R7.H, A0 = R2.H * R7.H (IS); +R2 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x22F88E38; +CHECKREG r1, 0x0C9A9B6A; +CHECKREG r2, 0xF3263C9F; +CHECKREG r3, 0x17712248; +CHECKREG r4, 0x1756FD8C; +CHECKREG r5, 0xF941311C; +CHECKREG r6, 0xD9A250BB; +CHECKREG r7, 0xF3263C9F; + +// test the (unsigned or integer :no ) U=1 +imm32 r0, 0x62345678; +imm32 r1, 0x26456789; +imm32 r2, 0x3466789a; +imm32 r3, 0x45668912; +imm32 r4, 0x56786123; +imm32 r5, 0x67891634; +imm32 r6, 0xa1234567; +imm32 r7, 0xc1234566; +A1 = R0.L * R2.L, A0 = R0.L * R2.L (FU); +R0 = A0.w; +R2 = A1.w; +A1 = R1.L * R3.L, A0 += R1.L * R3.H (FU); +R1 = A0.w; +R3 = A1.w; +A1 += R4.L * R6.L, A0 = R4.H * R6.L (FU); +R4 = A0.w; +R6 = A1.w; +A1 += R5.L * R7.L, A0 += R5.H * R7.H (FU); +R5 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x28BC4430; +CHECKREG r1, 0x44CD71C6; +CHECKREG r2, 0x28BC4430; +CHECKREG r3, 0x376F98A2; +CHECKREG r4, 0x17712248; +CHECKREG r5, 0x658D9303; +CHECKREG r6, 0x51C51CB7; +CHECKREG r7, 0x57C9F96F; + +imm32 r0, 0x12345678; +imm32 r1, 0x73456789; +imm32 r2, 0x8456789a; +imm32 r3, 0x49998912; +imm32 r4, 0x56782123; +imm32 r5, 0x67891234; +imm32 r6, 0xa1234577; +imm32 r7, 0xc1234567; +A1 = R2.L * R3.H, A0 = R2.L * R3.L (FU); +R2 = A0.w; +R3 = A1.w; +A1 = R0.L * R1.H, A0 = R0.L * R1.H (FU); +R0 = A0.w; +R1 = A1.w; +A1 += R4.L * R5.H, A0 = R4.H * R5.L (FU); +R4 = A0.w; +R5 = A1.w; +A1 = R7.L * R6.H, A0 += R7.H * R6.H (FU); +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x26EF3658; +CHECKREG r1, 0x26EF3658; +CHECKREG r2, 0x4092E4D4; +CHECKREG r3, 0x22ABFE0A; +CHECKREG r4, 0x06260060; +CHECKREG r5, 0x34560713; +CHECKREG r6, 0x7FB76B29; +CHECKREG r7, 0x2BAF4415; + +imm32 r0, 0x1234567a; +imm32 r1, 0x2345678a; +imm32 r2, 0x3456a89a; +imm32 r3, 0x4a678912; +imm32 r4, 0xa6789123; +imm32 r5, 0xc7891234; +imm32 r6, 0xa1234567; +imm32 r7, 0xc1234567; +A1 = R5.H * R4.L, A0 = R5.L * R4.L (FU); +R4 = A0.w; +R5 = A1.w; +A1 = R3.H * R2.L, A0 = R3.L * R2.H (FU); +R2 = A0.w; +R3 = A1.w; +A1 = R1.H * R0.L, A0 = R1.H * R0.L (FU); +R0 = A0.w; +R1 = A1.w; +A1 = R7.H * R6.L, A0 = R7.H * R6.H (FU); +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x0BE9FCE2; +CHECKREG r1, 0x0BE9FCE2; +CHECKREG r2, 0x1C05B40C; +CHECKREG r3, 0x310059F6; +CHECKREG r4, 0x0A51F11C; +CHECKREG r5, 0x711FE0BB; +CHECKREG r6, 0x79916AC9; +CHECKREG r7, 0x345C2415; + +imm32 r0, 0xb2345678; +imm32 r1, 0x2b456789; +imm32 r2, 0x34b6789a; +imm32 r3, 0xc56b8912; +imm32 r4, 0x5c78b123; +imm32 r5, 0x67c91b34; +imm32 r6, 0xa12345b7; +imm32 r7, 0xc123456b; +A1 = R6.H * R7.H, A0 = R6.L * R7.L (FU); +R6 = A0.w; +R7 = A1.w; +A1 = R5.H * R4.H, A0 = R5.L * R4.H (FU); +R4 = A0.w; +R5 = A1.w; +A1 = R2.H * R3.H, A0 = R2.H * R3.L (FU); +R2 = A0.w; +R3 = A1.w; +A1 = R0.H * R1.H, A0 = R0.H * R1.H (FU); +R0 = A0.w; +R1 = A1.w; +CHECKREG r0, 0x1E1EC404; +CHECKREG r1, 0x1E1EC404; +CHECKREG r2, 0x1C391ACC; +CHECKREG r3, 0x28A61612; +CHECKREG r4, 0x09D37060; +CHECKREG r5, 0x257CE238; +CHECKREG r6, 0x12E7767D; +CHECKREG r7, 0x79916AC9; + +// Test w32 +imm32 r0, 0x123df178; +imm32 r1, 0x2245e189; +imm32 r2, 0x3256719a; +imm32 r3, 0x42678112; +imm32 r4, 0xa2789123; +imm32 r5, 0x62891134; +imm32 r6, 0xa2b34167; +imm32 r7, 0xc22d4167; +A1 = R0.L * R4.L, A0 += R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.L * R5.L, A0 += R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 = R2.L * R6.L, A0 += R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.L * R4.L, A0 += R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0x2AB4BAD4; +CHECKREG r1, 0x13410376; +CHECKREG r2, 0x2CF930AA; +CHECKREG r3, 0x33802490; +CHECKREG r4, 0x091C5540; +CHECKREG r5, 0xFBE7D1A8; +CHECKREG r6, 0x3A0B9DEC; +CHECKREG r7, 0xC22D4167; + +imm32 r0, 0x553df344; +imm32 r1, 0x2525e349; +imm32 r2, 0x3252734a; +imm32 r3, 0x42658342; +imm32 r4, 0xa5789343; +imm32 r5, 0x63591344; +imm32 r6, 0xa3b54347; +imm32 r7, 0xc32d4347; +A1 += R0.L * R4.H, A0 = R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 += R1.L * R5.H, A0 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.L * R6.H, A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 += R3.L * R4.H, A0 = R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0x0AD16D98; +CHECKREG r1, 0xE9B67EC2; +CHECKREG r2, 0x1A72D57C; +CHECKREG r3, 0x0965C3AC; +CHECKREG r4, 0x970BD9DE; +CHECKREG r5, 0xFBD48BC2; +CHECKREG r6, 0xA8B3CE66; +CHECKREG r7, 0xC32D4347; + +imm32 r0, 0x163df678; +imm32 r1, 0x2625e689; +imm32 r2, 0x3652769a; +imm32 r3, 0x46628612; +imm32 r4, 0xa6789623; +imm32 r5, 0x63691634; +imm32 r6, 0xa3634367; +imm32 r7, 0xc3264667; +A1 += R0.H * R4.L, A0 = R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.H * R5.L, A0 += R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.L, A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 += R3.H * R4.L, A0 += R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0x07E204D0; +CHECKREG r1, 0xF41B1732; +CHECKREG r2, 0x1C9AA1FC; +CHECKREG r3, 0xD8C785D8; +CHECKREG r4, 0x5DCEA034; +CHECKREG r5, 0x069DDB08; +CHECKREG r6, 0x23387D04; +CHECKREG r7, 0xC3264667; + +imm32 r0, 0x123df378; +imm32 r1, 0x2225e389; +imm32 r2, 0x3252739a; +imm32 r3, 0x42628312; +imm32 r4, 0xa3789323; +imm32 r5, 0x63891334; +imm32 r6, 0xa3b34367; +imm32 r7, 0xc32d4367; +A1 += R0.H * R4.H, A0 = R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.H * R5.H, A0 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.H, A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.H * R4.H, A0 = R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0x0AA862D0; +CHECKREG r1, 0xE9DD7EA2; +CHECKREG r2, 0x1A7F69FC; +CHECKREG r3, 0x29CFB5BC; +CHECKREG r4, 0x29CFB5BC; +CHECKREG r5, 0x1A8D299A; +CHECKREG r6, 0xF643F446; +CHECKREG r7, 0xC32D4367; + +imm32 r0, 0x123df678; +imm32 r1, 0x2345e789; +imm32 r2, 0x34567b9a; +imm32 r3, 0x45678c12; +imm32 r4, 0xa6789123; +imm32 r5, 0x6c891234; +imm32 r6, 0xa1b34567; +imm32 r7, 0xc12d4567; +A1 = R0.H * R4.L, A0 = R0.H * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.H * R5.L, A0 = R1.H * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 = R2.H * R6.H, A0 = R2.L * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.H * R4.H, A0 = R3.L * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xF03416AE; +CHECKREG r1, 0x1DE7F7DA; +CHECKREG r2, 0x430479EC; +CHECKREG r3, 0x0E4EA750; +CHECKREG r4, 0xF76F51D8; +CHECKREG r5, 0x05040808; +CHECKREG r6, 0xD9715C44; +CHECKREG r7, 0xC12D4567; + +// MNOP & w32 +imm32 r0, 0x623df17a; +imm32 r1, 0x7245e18b; +imm32 r2, 0x8256719a; +imm32 r3, 0x92678112; +imm32 r4, 0xa2789123; +imm32 r5, 0xb2891134; +imm32 r6, 0xc2b34167; +imm32 r7, 0xd22d4167; +A0 += R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A0 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A0 += R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A0 = R3.H * R7.H (W32); +R3 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x1AE2E2AC; +CHECKREG r1, 0x126EB2C6; +CHECKREG r2, 0xD2393FFA; +CHECKREG r3, 0x273C7436; +CHECKREG r4, 0xF76F51D8; +CHECKREG r5, 0xF76F51D8; +CHECKREG r6, 0xF76F51D8; +CHECKREG r7, 0xF76F51D8; + +imm32 r0, 0xa23df17a; +imm32 r1, 0x7b45e18b; +imm32 r2, 0x82c6719a; +imm32 r3, 0x126d8112; +imm32 r4, 0xc278e123; +imm32 r5, 0xb2491f34; +imm32 r6, 0x89b54167; +imm32 r7, 0xd25d6767; +A1 += R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.H * R7.H (W32); +R3 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x273C7436; +CHECKREG r1, 0x273C7436; +CHECKREG r2, 0x273C7436; +CHECKREG r3, 0x273C7436; +CHECKREG r4, 0xFAEFCD34; +CHECKREG r5, 0x127DED46; +CHECKREG r6, 0xD281B49A; +CHECKREG r7, 0xF96E3732; + +// test MM=1(Mix mode), MAC1 executes a mixed mode multiplication: (one input is +// signed, the other input is unsigned +imm32 r0, 0x22345628; +imm32 r1, 0x23456729; +imm32 r2, 0x3456782a; +imm32 r3, 0x45678922; +imm32 r4, 0x56789123; +imm32 r5, 0x67891224; +imm32 r6, 0xa1234527; +imm32 r7, 0xc1234567; +A1 += R0.L * R7.L (M), A0 = R0.L * R7.L (IS); +R0 = A0.w; +R7 = A1.w; +A1 = R6.L * R1.L (M), A0 += R6.L * R1.H (IS); +R6 = A0.w; +R1 = A1.w; +A1 = R2.L * R3.L (M), A0 = R2.H * R3.L (IS); +R2 = A0.w; +R3 = A1.w; +A1 += R5.L * R4.L (M), A0 += R5.H * R4.H (IS); +R5 = A0.w; +R4 = A1.w; +CHECKREG r0, 0x175B7218; +CHECKREG r1, 0x1BDDC43F; +CHECKREG r2, 0xE7B2F96C; +CHECKREG r3, 0x405E6F94; +CHECKREG r4, 0x4AA74E80; +CHECKREG r5, 0x0AAB87A4; +CHECKREG r6, 0x20E26A9B; +CHECKREG r7, 0x10C9A94A; + +imm32 r0, 0x13335678; +imm32 r1, 0x23436789; +imm32 r2, 0x3353789a; +imm32 r3, 0xa3638912; +imm32 r4, 0x53739123; +imm32 r5, 0x63831234; +imm32 r6, 0xa1234567; +imm32 r7, 0xc1234567; +A1 += R2.L * R7.H (M), A0 = R2.L * R7.L (IS); +R2 = A0.w; +R7 = A1.w; +A1 = R6.L * R1.H (M), A0 = R6.L * R1.H (IS); +R6 = A0.w; +R1 = A1.w; +A1 += R0.L * R5.H (M), A0 = R0.H * R5.L (IS); +R0 = A0.w; +R5 = A1.w; +A1 = R4.L * R3.H (M), A0 += R4.H * R3.H (IS); +R4 = A0.w; +R3 = A1.w; +CHECKREG r0, 0x015D7C5C; +CHECKREG r1, 0x098F3EF5; +CHECKREG r2, 0x20B207F6; +CHECKREG r3, 0xB93E6989; +CHECKREG r4, 0xE32CFAD5; +CHECKREG r5, 0x2B2BE65D; +CHECKREG r6, 0x098F3EF5; +CHECKREG r7, 0xA5A3E58E; + +imm32 r0, 0x14345678; +imm32 r1, 0x24456789; +imm32 r2, 0x3456789a; +imm32 r3, 0x44678912; +imm32 r4, 0x54789123; +imm32 r5, 0x67891244; +imm32 r6, 0xa1234547; +imm32 r7, 0xc1234547; +A1 = R4.H * R0.L (M), A0 = R4.L * R0.L (IS); +R4 = A0.w; +R0 = A1.w; +A1 = R3.H * R1.L (M), A0 = R3.L * R1.H (IS); +R3 = A0.w; +R1 = A1.w; +A1 = R2.H * R6.L (M), A0 = R2.H * R6.L (IS); +R2 = A0.w; +R6 = A1.w; +A1 = R7.H * R5.L (M), A0 = R7.H * R5.H (IS); +R7 = A0.w; +R5 = A1.w; +CHECKREG r0, 0x1C87E840; +CHECKREG r1, 0x1BAA0C1F; +CHECKREG r2, 0x0E29B1DA; +CHECKREG r3, 0xEF2679DA; +CHECKREG r4, 0xDA8DCA68; +CHECKREG r5, 0xFB83C34C; +CHECKREG r6, 0x0E29B1DA; +CHECKREG r7, 0xE69370BB; + +imm32 r0, 0x15345678; +imm32 r1, 0x23556789; +imm32 r2, 0x3455789a; +imm32 r3, 0x45675912; +imm32 r4, 0x56789523; +imm32 r5, 0x67891234; +imm32 r6, 0xa1234557; +imm32 r7, 0xc1234565; +A1 = R0.H * R1.H (M), A0 = R0.L * R1.L (IS); +R0 = A0.w; +R1 = A1.w; +A1 = R5.H * R6.H (M), A0 = R5.L * R6.H (IS); +R5 = A0.w; +R6 = A1.w; +A1 += R4.H * R3.H (M), A0 = R4.H * R3.L (IS); +R4 = A0.w; +R3 = A1.w; +A1 += R2.H * R7.H (M), A0 = R2.H * R7.H (IS); +R2 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x22F88E38; +CHECKREG r1, 0x02ED2644; +CHECKREG r2, 0xF3263C9F; +CHECKREG r3, 0x589C7303; +CHECKREG r4, 0x1E15CC70; +CHECKREG r5, 0xF941311C; +CHECKREG r6, 0x412B50BB; +CHECKREG r7, 0x8017AFA2; + +// test the (unsigned or integer :no ) U=1 +imm32 r0, 0x62345678; +imm32 r1, 0x26456789; +imm32 r2, 0x3466789a; +imm32 r3, 0x45668912; +imm32 r4, 0x56786123; +imm32 r5, 0x67891634; +imm32 r6, 0xa1234567; +imm32 r7, 0xc1234566; +A1 = R0.L * R2.L (M), A0 = R0.L * R2.L (FU); +R0 = A0.w; +R2 = A1.w; +A1 += R1.L * R3.L (M), A0 = R1.L * R3.H (FU); +R1 = A0.w; +R3 = A1.w; +A1 = R4.L * R6.L (M), A0 = R4.H * R6.L (FU); +R4 = A0.w; +R6 = A1.w; +A1 += R5.L * R7.L (M), A0 = R5.H * R7.H (FU); +R5 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x28BC4430; +CHECKREG r1, 0x1C112D96; +CHECKREG r2, 0x28BC4430; +CHECKREG r3, 0x602BDCD2; +CHECKREG r4, 0x17712248; +CHECKREG r5, 0x4E1C70BB; +CHECKREG r6, 0x1A558415; +CHECKREG r7, 0x205A60CD; + +imm32 r0, 0x12345678; +imm32 r1, 0x73456789; +imm32 r2, 0x8456789a; +imm32 r3, 0x49998912; +imm32 r4, 0x56782123; +imm32 r5, 0x67891234; +imm32 r6, 0xa1234577; +imm32 r7, 0xc1234567; +A1 = R2.L * R3.H (M), A0 = R2.L * R3.L (FU); +R2 = A0.w; +R3 = A1.w; +A1 = R0.L * R1.H (M), A0 = R0.L * R1.H (FU); +R0 = A0.w; +R1 = A1.w; +A1 = R4.L * R5.H (M), A0 = R4.H * R5.L (FU); +R4 = A0.w; +R5 = A1.w; +A1 = R7.L * R6.H (M), A0 = R7.H * R6.H (FU); +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x26EF3658; +CHECKREG r1, 0x26EF3658; +CHECKREG r2, 0x4092E4D4; +CHECKREG r3, 0x22ABFE0A; +CHECKREG r4, 0x06260060; +CHECKREG r5, 0x0D66D0BB; +CHECKREG r6, 0x79916AC9; +CHECKREG r7, 0x2BAF4415; + +imm32 r0, 0x1234567a; +imm32 r1, 0x2345678a; +imm32 r2, 0x3456a89a; +imm32 r3, 0x4a678912; +imm32 r4, 0xa6789123; +imm32 r5, 0xc7891234; +imm32 r6, 0xa1234567; +imm32 r7, 0xc1234567; +A1 = R5.H * R4.L (M), A0 += R5.L * R4.L (FU); +R4 = A0.w; +R5 = A1.w; +A1 = R3.H * R2.L (M), A0 = R3.L * R2.H (FU); +R2 = A0.w; +R3 = A1.w; +A1 = R1.H * R0.L (M), A0 += R1.H * R0.L (FU); +R0 = A0.w; +R1 = A1.w; +A1 = R7.H * R6.L (M), A0 = R7.H * R6.H (FU); +R6 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x27EFB0EE; +CHECKREG r1, 0x0BE9FCE2; +CHECKREG r2, 0x1C05B40C; +CHECKREG r3, 0x310059F6; +CHECKREG r4, 0x83E35BE5; +CHECKREG r5, 0xDFFCE0BB; +CHECKREG r6, 0x79916AC9; +CHECKREG r7, 0xEEF52415; + +imm32 r0, 0xb2345678; +imm32 r1, 0x2b456789; +imm32 r2, 0x34b6789a; +imm32 r3, 0xc56b8912; +imm32 r4, 0x5c78b123; +imm32 r5, 0x67c91b34; +imm32 r6, 0xa12345b7; +imm32 r7, 0xc123456b; +A1 += R6.H * R7.H (M), A0 = R6.L * R7.L (FU); +R6 = A0.w; +R7 = A1.w; +A1 += R5.H * R4.H (M), A0 = R5.L * R4.H (FU); +R4 = A0.w; +R5 = A1.w; +A1 = R2.H * R3.H (M), A0 += R2.H * R3.L (FU); +R2 = A0.w; +R3 = A1.w; +A1 = R0.H * R1.H (M), A0 += R0.H * R1.H (FU); +R0 = A0.w; +R1 = A1.w; +CHECKREG r0, 0x442B4F30; +CHECKREG r1, 0xF2D9C404; +CHECKREG r2, 0x260C8B2C; +CHECKREG r3, 0x28A61612; +CHECKREG r4, 0x09D37060; +CHECKREG r5, 0xCCE07116; +CHECKREG r6, 0x12E7767D; +CHECKREG r7, 0xA7638EDE; + +// Test w32 +imm32 r0, 0x123df178; +imm32 r1, 0x2245e189; +imm32 r2, 0x3256719a; +imm32 r3, 0x42678112; +imm32 r4, 0xa2789123; +imm32 r5, 0x62891134; +imm32 r6, 0xa2b34167; +imm32 r7, 0xc22d4167; +A1 = R0.L * R7.L (M), A0 = R0.L * R7.L (W32); +R0 = A0.w; +R7 = A1.w; +A1 += R1.L * R5.L (M), A0 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 = R2.L * R6.L (M), A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 += R3.L * R4.L (M), A0 = R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xF8933E90; +CHECKREG r1, 0xE88C48A2; +CHECKREG r2, 0x19B82D34; +CHECKREG r3, 0xCF7A9C90; +CHECKREG r4, 0xD50FA66C; +CHECKREG r5, 0xFA3D881C; +CHECKREG r6, 0x1D05CEF6; +CHECKREG r7, 0xFC499F48; + +imm32 r0, 0x553df344; +imm32 r1, 0x2525e349; +imm32 r2, 0x3252734a; +imm32 r3, 0x42658342; +imm32 r4, 0xa5789343; +imm32 r5, 0x63591344; +imm32 r6, 0xa3b54347; +imm32 r7, 0xc32d4347; +A1 = R0.L * R7.H (M), A0 = R0.L * R7.L (W32); +R0 = A0.w; +R7 = A1.w; +A1 = R1.L * R5.H (M), A0 += R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 = R2.L * R6.H (M), A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.L * R4.H (M), A0 += R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xF94E87B8; +CHECKREG r1, 0xE305067A; +CHECKREG r2, 0x1A72D57C; +CHECKREG r3, 0xEB7D462C; +CHECKREG r4, 0xAF5F10F0; +CHECKREG r5, 0xF4DB3F61; +CHECKREG r6, 0x49B9A152; +CHECKREG r7, 0xF64A8EF4; + +imm32 r0, 0x163df678; +imm32 r1, 0x2625e689; +imm32 r2, 0x3652769a; +imm32 r3, 0x46628612; +imm32 r4, 0xa6789623; +imm32 r5, 0x63691634; +imm32 r6, 0xa3634367; +imm32 r7, 0xc3264667; +A1 = R0.H * R7.L (M), A0 = R0.L * R7.L (W32); +R0 = A0.w; +R7 = A1.w; +A1 = R1.H * R5.L (M), A0 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.L (M), A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.H * R4.L (M), A0 = R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xFAC1F490; +CHECKREG r1, 0xEC391262; +CHECKREG r2, 0x1C9AA1FC; +CHECKREG r3, 0xCEC513E0; +CHECKREG r4, 0x29470B66; +CHECKREG r5, 0x034EED84; +CHECKREG r6, 0x119C3E82; +CHECKREG r7, 0x061DA08B; + +imm32 r0, 0x123df378; +imm32 r1, 0x2225e389; +imm32 r2, 0x3252739a; +imm32 r3, 0x42628312; +imm32 r4, 0xa3789323; +imm32 r5, 0x63891334; +imm32 r6, 0xa3b34367; +imm32 r7, 0xc32d4367; +A1 = R0.H * R7.H (M), A0 = R0.L * R7.L (W32); +R0 = A0.w; +R7 = A1.w; +A1 = R1.H * R5.H (M), A0 = R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.H (M), A0 += R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 += R3.H * R4.H (M), A0 += R3.H * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xF966BA90; +CHECKREG r1, 0xE9DD7EA2; +CHECKREG r2, 0x045CE89E; +CHECKREG r3, 0xD45FF07E; +CHECKREG r4, 0x57D77E13; +CHECKREG r5, 0x0D4694CD; +CHECKREG r6, 0x2D73FA23; +CHECKREG r7, 0x0DE7ABB9; + +imm32 r0, 0x123df678; +imm32 r1, 0x2345e789; +imm32 r2, 0x34567b9a; +imm32 r3, 0x45678c12; +imm32 r4, 0xa6789123; +imm32 r5, 0x6c891234; +imm32 r6, 0xa1b34567; +imm32 r7, 0xc12d4567; +A1 = R0.H * R4.L (M), A0 = R0.H * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.H * R5.L (M), A0 = R1.H * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A1 = R2.H * R6.H (M), A0 = R2.L * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.H * R4.H (M), A0 = R3.L * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xF03416AE; +CHECKREG r1, 0x1DE7F7DA; +CHECKREG r2, 0x430479EC; +CHECKREG r3, 0xF6A29C3C; +CHECKREG r4, 0x02CD9C01; +CHECKREG r5, 0x02820404; +CHECKREG r6, 0x210EAE22; +CHECKREG r7, 0xC12D4567; + +// MNOP & w32 +imm32 r0, 0x623df17a; +imm32 r1, 0x7245e18b; +imm32 r2, 0x8256719a; +imm32 r3, 0x92678112; +imm32 r4, 0xa2789123; +imm32 r5, 0xb2891134; +imm32 r6, 0xc2b34167; +imm32 r7, 0xd22d4167; +A0 = R0.L * R4.L (W32); +R0 = A0.w; +R4 = A1.w; +A0 += R1.L * R5.H (W32); +R1 = A0.w; +R5 = A1.w; +A0 = R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A0 += R3.H * R7.H (W32); +R3 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x0C943B5C; +CHECKREG r1, 0x1F02EE22; +CHECKREG r2, 0xBFCA8D34; +CHECKREG r3, 0xE707016A; +CHECKREG r4, 0x02CD9C01; +CHECKREG r5, 0x02CD9C01; +CHECKREG r6, 0x02CD9C01; +CHECKREG r7, 0x02CD9C01; + +imm32 r0, 0xa23df17a; +imm32 r1, 0x7b45e18b; +imm32 r2, 0x82c6719a; +imm32 r3, 0x126d8112; +imm32 r4, 0xc278e123; +imm32 r5, 0xb2491f34; +imm32 r6, 0x89b54167; +imm32 r7, 0xd25d6767; +A1 += R0.L * R4.L (M,W32); +R0 = A0.w; +R4 = A1.w; +A1 = R1.L * R5.H (M,W32); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.L (M,W32); +R2 = A0.w; +R6 = A1.w; +A1 = R3.H * R7.H (M,W32); +R3 = A0.w; +R7 = A1.w; +CHECKREG r0, 0xE707016A; +CHECKREG r1, 0xE707016A; +CHECKREG r2, 0xE707016A; +CHECKREG r3, 0xE707016A; +CHECKREG r4, 0xF607D9AF; +CHECKREG r5, 0xEAC9F6A3; +CHECKREG r6, 0xCACBDA4D; +CHECKREG r7, 0x0F241B99; + +imm32 r0, 0x123df678; +imm32 r1, 0x2345e789; +imm32 r2, 0x34567b9a; +imm32 r3, 0x45678c12; +imm32 r4, 0xa6789123; +imm32 r5, 0x6c891234; +imm32 r6, 0xa1b34567; +imm32 r7, 0xc12d4567; +A1 -= R0.H * R4.L (M), A0 += R0.H * R4.L (IS); +R0 = A0.w; +R4 = A1.w; +A1 -= R1.H * R5.L (M), A0 -= R1.H * R5.H (FU); +R1 = A0.w; +R5 = A1.w; +A1 += R2.H * R6.H (M), A0 -= R2.L * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 -= R3.H * R4.H (M), A0 -= R3.L * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xDF210CC1; +CHECKREG r1, 0xD02D10D4; +CHECKREG r2, 0x8D2896E8; +CHECKREG r3, 0x9181B214; +CHECKREG r4, 0x220C8AE5; +CHECKREG r5, 0x024B0C3E; +CHECKREG r6, 0x2359BA60; +CHECKREG r7, 0xC12D4567; + +imm32 r0, 0x123df678; +imm32 r1, 0x2345e789; +imm32 r2, 0x34567b9a; +imm32 r3, 0x45678c12; +imm32 r4, 0xa6789123; +imm32 r5, 0x6c891234; +imm32 r6, 0xa1b34567; +imm32 r7, 0xc12d4567; +A1 -= R0.H * R4.L (M), A0 = R0.H * R4.L (IS); +R0 = A0.w; +R4 = A1.w; +A1 -= R1.H * R5.L (M), A0 = R1.H * R5.H (FU); +R1 = A0.w; +R5 = A1.w; +A1 -= R2.H * R6.H (M), A0 = R2.L * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A1 -= R3.H * R4.H (M), A0 = R3.L * R4.H (W32); +R3 = A0.w; +R4 = A1.w; +CHECKREG r0, 0xF81A0B57; +CHECKREG r1, 0x0EF3FBED; +CHECKREG r2, 0x430479EC; +CHECKREG r3, 0xEA874D74; +CHECKREG r4, 0xEDB77A95; +CHECKREG r5, 0x15337B8A; +CHECKREG r6, 0xF424CD68; +CHECKREG r7, 0xC12D4567; + +// MNOP & w32 +imm32 r0, 0x623df17a; +imm32 r1, 0x7245e18b; +imm32 r2, 0x8256719a; +imm32 r3, 0x92678112; +imm32 r4, 0xa2789123; +imm32 r5, 0xb2891134; +imm32 r6, 0xc2b34167; +imm32 r7, 0xd22d4167; +A0 -= R0.L * R4.L (IS); +R0 = A0.w; +R4 = A1.w; +A0 -= R1.L * R5.H (FU); +R1 = A0.w; +R5 = A1.w; +A0 -= R2.H * R6.L (W32); +R2 = A0.w; +R6 = A1.w; +A0 -= R3.H * R7.H (W32); +R3 = A0.w; +R7 = A1.w; +CHECKREG r0, 0xE43D2FC6; +CHECKREG r1, 0x46F1D663; +CHECKREG r2, 0x8727492F; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0xEDB77A95; +CHECKREG r5, 0xEDB77A95; +CHECKREG r6, 0xEDB77A95; +CHECKREG r7, 0xEDB77A95; + +imm32 r0, 0xa23df17a; +imm32 r1, 0x7b45e18b; +imm32 r2, 0x82c6719a; +imm32 r3, 0x126d8112; +imm32 r4, 0xc278e123; +imm32 r5, 0xb2491f34; +imm32 r6, 0x89b54167; +imm32 r7, 0xd25d6767; +A1 -= R0.L * R4.L (M,IS); +R0 = A0.w; +R4 = A1.w; +A1 -= R1.L * R5.H (M,FU); +R1 = A0.w; +R5 = A1.w; +A1 -= R2.H * R6.L (M,W32); +R2 = A0.w; +R6 = A1.w; +A1 -= R3.H * R7.H (M,FU); +R3 = A0.w; +R7 = A1.w; +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x80000000; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0xFA7D3CE7; +CHECKREG r5, 0x0FB34644; +CHECKREG r6, 0x2FB1629A; +CHECKREG r7, 0x208D4701; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_m.s new file mode 100644 index 0000000..69d54d3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_m.s @@ -0,0 +1,340 @@ +//Original:/testcases/core/c_dsp32mac_a1a0_m/c_dsp32mac_a1a0_m.dsp +// Spec Reference: dsp32mac a1 a0 m MNOP +# mach: bfin + +.include "testutils.inc" + start + + + INIT_R_REGS 0; + + + imm32 r0, 0x00000000; + A0 = 0; + A1 = 0; + ASTAT = r0; + +// test the MNOP default (signed fraction : left ) rounding U=0 I=0 T=0 w32=1 + imm32 r0, 0x123c5678; + imm32 r1, 0x2345c789; + imm32 r2, 0x34567c9a; + imm32 r3, 0x456789c2; + imm32 r4, 0xc678912c; + imm32 r5, 0x6c891234; + imm32 r6, 0xa1c34567; + imm32 r7, 0xc12c4567; + + A0 = 0; + A1 = 0; + + A1 = R0.L * R1.L (M); + R0 = A0.w; + R1 = A1.w; + A0 += R2.H * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 += R4.L * R5.H; + R4 = A0.w; + R5 = A1.w; + A0 += R6.L * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x43658E38; + CHECKREG r2, 0x1C607934; + CHECKREG r3, 0x43658E38; + CHECKREG r4, 0x1C607934; + CHECKREG r5, 0xE56C0F50; + CHECKREG r6, 0xFA4FA29C; + CHECKREG r7, 0xE56C0F50; + + imm32 r0, 0xd2345678; + imm32 r1, 0x2d456789; + imm32 r2, 0x34d6789a; + imm32 r3, 0x456d8912; + imm32 r4, 0x5678d123; + imm32 r5, 0x67891d34; + imm32 r6, 0xa12345d7; + imm32 r7, 0xc123456d; + A0 += R6.H * R7.L; + R6 = A0.w; + R7 = A1.w; + A1 += R4.L * R5.H; + R4 = A0.w; + R5 = A1.w; + A0 += R2.L * R3.L; + R2 = A0.w; + R3 = A1.w; + A1 += R0.H * R1.L; + R0 = A0.w; + R1 = A1.w; + CHECKREG r0, 0x56CD8212; + CHECKREG r1, 0x9A78E46E; + CHECKREG r2, 0x56CD8212; + CHECKREG r3, 0xBF8410C6; + CHECKREG r4, 0xC6DBB86A; + CHECKREG r5, 0xBF8410C6; + CHECKREG r6, 0xC6DBB86A; + CHECKREG r7, 0xE56C0F50; + +// test MM=1(Mix mode), MAC1 executes a mixed mode multiplication: (one input is +// signed, the other input is unsigned + imm32 r0, 0x12345678; + imm32 r1, 0x33456789; + imm32 r2, 0x5556789a; + imm32 r3, 0x75678912; + imm32 r4, 0x86789123; + imm32 r5, 0xa7891234; + imm32 r6, 0xc1234567; + imm32 r7, 0xf1234567; + A1 += R0.L * R1.L (M), A0 = R0.L * R1.L; + R0 = A0.w; + R1 = A1.w; + A1 = R2.L * R3.L (M), A0 += R2.L * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 += R4.L * R5.L (M), A0 = R4.H * R5.L; + R4 = A0.w; + R5 = A1.w; + A1 = R6.L * R7.L (M), A0 = R6.H * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x45F11C70; + CHECKREG r1, 0xBD7172A6; + CHECKREG r2, 0xB48EEC5C; + CHECKREG r3, 0x4092E4D4; + CHECKREG r4, 0xEEB780C0; + CHECKREG r5, 0x38B0D5F0; + CHECKREG r6, 0x074CB592; + CHECKREG r7, 0x12D0AF71; + + imm32 r0, 0x12245618; + imm32 r1, 0x23256719; + imm32 r2, 0x3426781a; + imm32 r3, 0x45278912; + imm32 r4, 0x56289113; + imm32 r5, 0x67291214; + imm32 r6, 0xa1234517; + imm32 r7, 0xc1234517; + A1 += R0.L * R1.H (M), A0 = R0.L * R1.L; + R0 = A0.w; + R1 = A1.w; + A1 += R2.L * R3.H (M), A0 = R2.L * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 += R4.L * R5.H (M), A0 = R4.H * R5.L; + R4 = A0.w; + R5 = A1.w; + A1 += R6.L * R7.H (M), A0 += R6.H * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x455820B0; + CHECKREG r1, 0x1EA268E9; + CHECKREG r2, 0x40E29BEC; + CHECKREG r3, 0x3F13B6DF; + CHECKREG r4, 0x0C2B1640; + CHECKREG r5, 0x126097EA; + CHECKREG r6, 0x3AC1EBD2; + CHECKREG r7, 0x4680610F; + + imm32 r0, 0x15245648; + imm32 r1, 0x25256749; + imm32 r2, 0x3526784a; + imm32 r3, 0x45278942; + imm32 r4, 0x55389143; + imm32 r5, 0x65391244; + imm32 r6, 0xa5334547; + imm32 r7, 0xc5334547; + A1 = R0.H * R1.H (M), A0 = R0.L * R1.L; + R0 = A0.w; + R1 = A1.w; + A1 += R2.H * R3.H (M), A0 += R2.L * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 = R4.H * R5.H (M), A0 = R4.H * R5.L; + R4 = A0.w; + R5 = A1.w; + A1 = R6.H * R7.H (M), A0 = R6.H * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x459F2510; + CHECKREG r1, 0x03114234; + CHECKREG r2, 0x869BAF9C; + CHECKREG r3, 0x116C98FE; + CHECKREG r4, 0x0C2925C0; + CHECKREG r5, 0x21B21178; + CHECKREG r6, 0x29B65052; + CHECKREG r7, 0xBA0E2829; + + imm32 r0, 0x13245628; + imm32 r1, 0x23256729; + imm32 r2, 0x3326782a; + imm32 r3, 0x43278922; + imm32 r4, 0x56389123; + imm32 r5, 0x67391224; + imm32 r6, 0xa1334527; + imm32 r7, 0xc1334527; + A1 = R0.H * R1.L (M), A0 = R0.L * R1.L; + R0 = A0.w; + R1 = A1.w; + A1 += R2.H * R3.L (M), A0 = R2.L * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 = R4.H * R5.L (M), A0 = R4.H * R5.L; + R4 = A0.w; + R5 = A1.w; + A1 += R6.H * R7.L (M), A0 = R6.H * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x456FC8D0; + CHECKREG r1, 0x07B68CC4; + CHECKREG r2, 0x3F0A98CC; + CHECKREG r3, 0x231CADD0; + CHECKREG r4, 0x0C381FC0; + CHECKREG r5, 0x061C0FE0; + CHECKREG r6, 0x2E832052; + CHECKREG r7, 0xEC805DA5; + +// test the MNOP default (signed fraction : left ) rounding U=0 I=0 T=0 w32=1 + imm32 r0, 0x123c5678; + imm32 r1, 0x2345c789; + imm32 r2, 0x34567c9a; + imm32 r3, 0x456789c2; + imm32 r4, 0xc678912c; + imm32 r5, 0x6c891234; + imm32 r6, 0xa1c34567; + imm32 r7, 0xc12c4567; + + A0 = 0; + A1 = 0; + + A1 += R0.L * R1.L (M); + R0 = A0.w; + R1 = A1.w; + A0 += R2.H * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 = R4.L * R5.H (M); + R4 = A0.w; + R5 = A1.w; + A0 += R6.L * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x43658E38; + CHECKREG r2, 0x1C607934; + CHECKREG r3, 0x43658E38; + CHECKREG r4, 0x1C607934; + CHECKREG r5, 0xD103408C; + CHECKREG r6, 0xFA4FA29C; + CHECKREG r7, 0xD103408C; + + imm32 r0, 0xd2345678; + imm32 r1, 0x2d456789; + imm32 r2, 0x34d6789a; + imm32 r3, 0x456d8912; + imm32 r4, 0x5678d123; + imm32 r5, 0x67891d34; + imm32 r6, 0xa12345d7; + imm32 r7, 0xc123456d; + A0 = R6.H * R7.L; + R6 = A0.w; + R7 = A1.w; + A1 = R4.L * R5.H (M); + R4 = A0.w; + R5 = A1.w; + A0 = R2.L * R3.L; + R2 = A0.w; + R3 = A1.w; + A1 += R0.H * R1.L (M); + R0 = A0.w; + R1 = A1.w; + CHECKREG r0, 0x8FF1C9A8; + CHECKREG r1, 0xDA866A8F; + CHECKREG r2, 0x8FF1C9A8; + CHECKREG r3, 0xED0C00BB; + CHECKREG r4, 0xCC8C15CE; + CHECKREG r5, 0xED0C00BB; + CHECKREG r6, 0xCC8C15CE; + CHECKREG r7, 0xD103408C; + + imm32 r0, 0x123c5678; + imm32 r1, 0x2345c789; + imm32 r2, 0x34567c9a; + imm32 r3, 0x456789c2; + imm32 r4, 0xc678912c; + imm32 r5, 0x6c891234; + imm32 r6, 0xa1c34567; + imm32 r7, 0xc12c4567; + + A0 = 0; + A1 = 0; + + A1 -= R0.L * R1.L (M); + R0 = A0.w; + R1 = A1.w; + A0 -= R2.H * R3.H; + R2 = A0.w; + R3 = A1.w; + A1 -= R4.L * R5.H (M); + R4 = A0.w; + R5 = A1.w; + A0 -= R6.L * R7.H; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0xBC9A71C8; + CHECKREG r2, 0xE39F86CC; + CHECKREG r3, 0xBC9A71C8; + CHECKREG r4, 0xE39F86CC; + CHECKREG r5, 0xEB97313C; + CHECKREG r6, 0x05B05D64; + CHECKREG r7, 0xEB97313C; + + imm32 r0, 0xd2345678; + imm32 r1, 0x2d456789; + imm32 r2, 0x34d6789a; + imm32 r3, 0x456d8912; + imm32 r4, 0x5678d123; + imm32 r5, 0x67891d34; + imm32 r6, 0xa12345d7; + imm32 r7, 0xc123456d; + A0 -= R6.H * R7.L; + R6 = A0.w; + R7 = A1.w; + A1 -= R4.L * R5.H (M); + R4 = A0.w; + R5 = A1.w; + A0 -= R2.L * R3.L; + R2 = A0.w; + R3 = A1.w; + A1 -= R0.H * R1.L (M); + R0 = A0.w; + R1 = A1.w; + CHECKREG r0, 0xA9327DEE; + CHECKREG r1, 0x1110C6AD; + CHECKREG r2, 0xA9327DEE; + CHECKREG r3, 0xFE8B3081; + CHECKREG r4, 0x39244796; + CHECKREG r5, 0xFE8B3081; + CHECKREG r6, 0x39244796; + CHECKREG r7, 0xEB97313C; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + .dd 0x000f0005 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 + .dd 0x00b00104 + .dd 0x00a00105 diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0.s new file mode 100644 index 0000000..71bd916 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0.s @@ -0,0 +1,124 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0/c_dsp32mac_dr_a0.dsp +// Spec Reference: dsp32mac dr_a0 +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xab235675; +imm32 r1, 0xcaba5127; +imm32 r2, 0x13a46705; +imm32 r3, 0x000a0007; +imm32 r4, 0x90abad09; +imm32 r5, 0x10aceadb; +imm32 r6, 0x000c00ad; +imm32 r7, 0x1246700a; + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0xb3545abd; +imm32 r1, 0xabbcfec7; +imm32 r2, 0xa1b45679; +imm32 r3, 0x000b0007; +imm32 r4, 0xefbcb569; +imm32 r5, 0x12350b0b; +imm32 r6, 0x000c00bd; +imm32 r7, 0x678e000b; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +A1 -= R2.L * R3.L, R2.L = ( A0 = R2.H * R3.L ); +R3 = A0.w; +A1 = R4.L * R5.L, R4.L = ( A0 += R4.H * R5.H ); +R5 = A0.w; +A1 = R6.L * R7.L, R6.L = ( A0 = R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0xB354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xA1B4FFFB; +CHECKREG r3, 0xFFFAD7D8; +CHECKREG r4, 0xEFBCFDAB; +CHECKREG r5, 0xFDAA8BB0; +CHECKREG r6, 0x000C0099; +CHECKREG r7, 0x0098E7AC; + +imm32 r0, 0xc3545abd; +imm32 r1, 0xacbcfec7; +imm32 r2, 0xa1c45679; +imm32 r3, 0x000c0007; +imm32 r4, 0xefbcc569; +imm32 r5, 0x12350c0b; +imm32 r6, 0x000c00cd; +imm32 r7, 0x678e000c; +A1 = R1.L * R0.H, R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +A1 -= R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ); +R3 = A0.w; +A1 = R4.H * R5.H, R4.L = ( A0 += R4.H * R5.H ); +R5 = A0.w; +A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0xC354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xA1C4FF27; +CHECKREG r3, 0xFF27451E; +CHECKREG r4, 0xEFBCFCD7; +CHECKREG r5, 0xFCD6F8F6; +CHECKREG r6, 0x000CFD7D; +CHECKREG r7, 0xFD7CD262; + +imm32 r0, 0xd3545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1d45679; +imm32 r3, 0x000d0007; +imm32 r4, 0xefbcd569; +imm32 r5, 0x12350d0b; +imm32 r6, 0x000c00dd; +imm32 r7, 0x678e000d; +A1 += R1.H * R0.L, R0.L = ( A0 -= R1.L * R0.L ); +R1 = A0.w; +A1 = R2.H * R3.H, R2.L = ( A0 -= R2.H * R3.L ); +R3 = A0.w; +A1 -= R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ); +R5 = A0.w; +A1 += R6.H * R7.L, R6.L = ( A0 = R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0xD354FE5B; +CHECKREG r1, 0xFE5AB48C; +CHECKREG r2, 0xA1D4FE60; +CHECKREG r3, 0xFE5FDAF4; +CHECKREG r4, 0xEFBC00B0; +CHECKREG r5, 0x00B0271C; +CHECKREG r6, 0x000C00B3; +CHECKREG r7, 0x00B2CB2C; + +imm32 r0, 0xe3545abd; +imm32 r1, 0xaebcfec7; +imm32 r2, 0xa1e45679; +imm32 r3, 0x000e0007; +imm32 r4, 0xefbce569; +imm32 r5, 0x12350e0b; +imm32 r6, 0x000c00ed; +imm32 r7, 0x678e000e; +A1 = R1.H * R0.H, R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +A1 += R2.H * R3.H, R2.L = ( A0 += R2.H * R3.L ); +R3 = A0.w; +A1 = R4.H * R5.H, R4.L = ( A0 = R4.H * R5.H ); +R5 = A0.w; +A1 = R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0xE354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xA1E4FF1D; +CHECKREG r3, 0xFF1CF84E; +CHECKREG r4, 0xEFBCFDB0; +CHECKREG r5, 0xFDAFB3D8; +CHECKREG r6, 0x000CFCF0; +CHECKREG r7, 0xFCEFF6EC; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_i.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_i.s new file mode 100644 index 0000000..4696075 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_i.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_i/c_dsp32mac_dr_a0_i.dsp +// Spec Reference: dsp32mac dr a0 i (signed int) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0x9dbcfec7; +imm32 r2, 0xc9248679; +imm32 r3, 0xd0969007; +imm32 r4, 0xefb94569; +imm32 r5, 0xcd35900b; +imm32 r6, 0xe00c890d; +imm32 r7, 0xf78e909f; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (IS); +R1 = A0.w; +A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IS); +R3 = A0.w; +A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IS); +R5 = A0.w; +A1 += R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H ) (IS); +R7 = A0.w; +CHECKREG r0, 0xA3548000; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0xC9247FFF; +CHECKREG r3, 0x17FEBFFC; +CHECKREG r4, 0xEFB97FFF; +CHECKREG r5, 0x1B398649; +CHECKREG r6, 0xE00C7FFF; +CHECKREG r7, 0x174CF613; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x68548abd; +imm32 r1, 0x7d8cfec7; +imm32 r2, 0xa1285679; +imm32 r3, 0xb0068007; +imm32 r4, 0xcfbc4869; +imm32 r5, 0xd235c08b; +imm32 r6, 0xe00ca008; +imm32 r7, 0x678e700f; +R0.L = ( A0 -= R1.L * R0.L ) (IS); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (IS); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.L ) (IS); +R5 = A0.w; +R6.L = ( A0 -= R6.H * R7.H ) (IS); +R7 = A0.w; +CHECKREG r0, 0x68547FFF; +CHECKREG r1, 0x16BD9728; +CHECKREG r2, 0xA1288000; +CHECKREG r3, 0xFBB9CDFE; +CHECKREG r4, 0xCFBC7FFF; +CHECKREG r5, 0x0BF6CB14; +CHECKREG r6, 0xE00C7FFF; +CHECKREG r7, 0x18E3B06C; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x7b54babd; +imm32 r1, 0xb7bcdec7; +imm32 r2, 0x7b7be679; +imm32 r3, 0x80b77007; +imm32 r4, 0x9fbb7569; +imm32 r5, 0xa235b70b; +imm32 r6, 0xb00c3b7d; +imm32 r7, 0xc78ea0b7; +R0.L = ( A0 = R1.L * R0.L ) (IS); +R1 = A0.w; +R2.L = ( A0 -= R2.H * R3.L ) (IS); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.H ) (IS); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (IS); +R7 = A0.w; +CHECKREG r0, 0x7B547FFF; +CHECKREG r1, 0x08FD0EEB; +CHECKREG r2, 0x7B7B8000; +CHECKREG r3, 0xD2F3DE8E; +CHECKREG r4, 0x9FBB7FFF; +CHECKREG r5, 0x234567B7; +CHECKREG r6, 0xB00C7FFF; +CHECKREG r7, 0x1627920D; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xe3545abd; +imm32 r1, 0x5ebcfec7; +imm32 r2, 0x71e45679; +imm32 r3, 0x900e0007; +imm32 r4, 0xafbce569; +imm32 r5, 0xd2359e0b; +imm32 r6, 0xc00ca0ed; +imm32 r7, 0x678ed00e; +A1 -= R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (IS); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ) (IS); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (IS); +R5 = A0.w; +A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (IS); +R1 = A0.w; +CHECKREG r0, 0xE3547FFF; +CHECKREG r1, 0x2E5AD9ED; +CHECKREG r2, 0x71E47FFF; +CHECKREG r3, 0x15B8A0F8; +CHECKREG r4, 0xAFBC7FFF; +CHECKREG r5, 0x0E5B99EC; +CHECKREG r6, 0xC00C7FFF; +CHECKREG r7, 0x3FFFCC18; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_ih.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_ih.s new file mode 100644 index 0000000..3735995 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_ih.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_ih/c_dsp32mac_dr_a0_ih.dsp +// Spec Reference: dsp32mac dr a0 ih (integer mutiplication with high word extraction) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xf3545abd; +imm32 r1, 0x7fbcfec7; +imm32 r2, 0xc7fff679; +imm32 r3, 0xd0799007; +imm32 r4, 0xefb79f69; +imm32 r5, 0xcd35700b; +imm32 r6, 0xe00c87fd; +imm32 r7, 0xf78e909f; +A1 = R1.L * R0.L, R0.L = ( A0 -= R1.L * R0.L ) (IH); +R1 = A0.w; +A1 = R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IH); +R3 = A0.w; +A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IH); +R5 = A0.w; +A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (IH); +R7 = A0.w; +CHECKREG r0, 0xF354006F; +CHECKREG r1, 0x006EF115; +CHECKREG r2, 0xC7FF187F; +CHECKREG r3, 0x187EE7F9; +CHECKREG r4, 0xEFB71BBA; +CHECKREG r5, 0x1BBA13DC; +CHECKREG r6, 0xE00C1FB0; +CHECKREG r7, 0x1FAF9D32; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0xc5548abd; +imm32 r1, 0x9b5cfec7; +imm32 r2, 0xa9b55679; +imm32 r3, 0xb09b5007; +imm32 r4, 0xcfb9b5c9; +imm32 r5, 0x52359b5c; +imm32 r6, 0xe50c5098; +imm32 r7, 0x675e7509; +R0.L = ( A0 = R1.L * R0.L ) (IH); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (IH); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.L ) (IH); +R5 = A0.w; +R6.L = ( A0 -= R6.H * R7.H ) (IH); +R7 = A0.w; +CHECKREG r0, 0xC554008F; +CHECKREG r1, 0x008F5EEB; +CHECKREG r2, 0xA9B5E5BE; +CHECKREG r3, 0xE5BDEA2E; +CHECKREG r4, 0xCFB912FB; +CHECKREG r5, 0x12FAA97C; +CHECKREG r6, 0xE50C1DDD; +CHECKREG r7, 0x1DDCBB14; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x4b54babd; +imm32 r1, 0x12346ec7; +imm32 r2, 0xa4bbe679; +imm32 r3, 0x8abdb707; +imm32 r4, 0x9f4b7b69; +imm32 r5, 0xa234877b; +imm32 r6, 0xb00c4887; +imm32 r7, 0xc78ea4b8; +R0.L = ( A0 = R1.L * R0.L ) (IH); +R1 = A0.w; +R2.L = ( A0 -= R2.H * R3.L ) (IH); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.H ) (IH); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (IH); +R7 = A0.w; +CHECKREG r0, 0x4B54E207; +CHECKREG r1, 0xE2075EEB; +CHECKREG r2, 0xA4BBC803; +CHECKREG r3, 0xC80330CE; +CHECKREG r4, 0x9F4B236F; +CHECKREG r5, 0x236ED13C; +CHECKREG r6, 0xB00C1371; +CHECKREG r7, 0x1370FD1E; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x1a545abd; +imm32 r1, 0x42fcfec7; +imm32 r2, 0xc53f5679; +imm32 r3, 0x9c64f007; +imm32 r4, 0xafc7ec69; +imm32 r5, 0xd23c891b; +imm32 r6, 0xc00cc602; +imm32 r7, 0x678edc7e; +A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (IH); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (IH); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (IH); +R5 = A0.w; +A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (IH); +R1 = A0.w; +CHECKREG r0, 0x1A54EEED; +CHECKREG r1, 0xEEED15DF; +CHECKREG r2, 0xC53F1302; +CHECKREG r3, 0x13020C09; +CHECKREG r4, 0xAFC7EEE5; +CHECKREG r5, 0xEEE57293; +CHECKREG r6, 0xC00CFD3D; +CHECKREG r7, 0xFD3CE337; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_is.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_is.s new file mode 100644 index 0000000..9c10949 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_is.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_is/c_dsp32mac_dr_a0_is.dsp +// Spec Reference: dsp32mac dr a0 is (scale by 2.0 signed fraction with round) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xf3545abd; +imm32 r1, 0x7fbcfec7; +imm32 r2, 0xc7fff679; +imm32 r3, 0xd0799007; +imm32 r4, 0xefb79f69; +imm32 r5, 0xcd35700b; +imm32 r6, 0xe00c87fd; +imm32 r7, 0xf78e909f; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (ISS2); +R1 = A0.w; +A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (ISS2); +R3 = A0.w; +A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (ISS2); +R5 = A0.w; +A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (ISS2); +R7 = A0.w; +CHECKREG r0, 0xF3548000; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0xC7FF8000; +CHECKREG r3, 0xE71226F2; +CHECKREG r4, 0xEFB78000; +CHECKREG r5, 0xEA4D52D5; +CHECKREG r6, 0xE00C8000; +CHECKREG r7, 0xEE42DC2B; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0xc5548abd; +imm32 r1, 0x9b5cfec7; +imm32 r2, 0xa9b55679; +imm32 r3, 0xb09b5007; +imm32 r4, 0xcfb9b5c9; +imm32 r5, 0x52359b5c; +imm32 r6, 0xe50c5098; +imm32 r7, 0x675e7509; +R0.L = ( A0 -= R1.L * R0.L ) (ISS2); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (ISS2); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.L ) (ISS2); +R5 = A0.w; +R6.L = ( A0 -= R6.H * R7.H ) (ISS2); +R7 = A0.w; +CHECKREG r0, 0xC5548000; +CHECKREG r1, 0xEDB37D40; +CHECKREG r2, 0xA9B58000; +CHECKREG r3, 0xD2E20883; +CHECKREG r4, 0xCFB97FFF; +CHECKREG r5, 0x12FAA97C; +CHECKREG r6, 0xE50C7FFF; +CHECKREG r7, 0x1DDCBB14; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x4b54babd; +imm32 r1, 0x12346ec7; +imm32 r2, 0xa4bbe679; +imm32 r3, 0x8abdb707; +imm32 r4, 0x9f4b7b69; +imm32 r5, 0xa234877b; +imm32 r6, 0xb00c4887; +imm32 r7, 0xc78ea4b8; +R0.L = ( A0 = R1.L * R0.L ) (ISS2); +R1 = A0.w; +R2.L = ( A0 -= R2.H * R3.L ) (ISS2); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.H ) (ISS2); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (ISS2); +R7 = A0.w; +CHECKREG r0, 0x4B548000; +CHECKREG r1, 0xE2075EEB; +CHECKREG r2, 0xA4BB8000; +CHECKREG r3, 0xC80330CE; +CHECKREG r4, 0x9F4B7FFF; +CHECKREG r5, 0x236ED13C; +CHECKREG r6, 0xB00C7FFF; +CHECKREG r7, 0x1370FD1E; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x1a545abd; +imm32 r1, 0x42fcfec7; +imm32 r2, 0xc53f5679; +imm32 r3, 0x9c64f007; +imm32 r4, 0xafc7ec69; +imm32 r5, 0xd23c891b; +imm32 r6, 0xc00cc602; +imm32 r7, 0x678edc7e; +A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (ISS2); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (ISS2); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (ISS2); +R5 = A0.w; +A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (ISS2); +R1 = A0.w; +CHECKREG r0, 0x1A548000; +CHECKREG r1, 0xF0477293; +CHECKREG r2, 0xC53F7FFF; +CHECKREG r3, 0x13020C09; +CHECKREG r4, 0xAFC78000; +CHECKREG r5, 0xEEE57293; +CHECKREG r6, 0xC00C8000; +CHECKREG r7, 0xFD3CE337; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_iu.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_iu.s new file mode 100644 index 0000000..2017459 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_iu.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_iu/c_dsp32mac_dr_a0_iu.dsp +// Spec Reference: dsp32mac dr a0 iu (unsigned int) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x83545abd; +imm32 r1, 0x78bcfec7; +imm32 r2, 0xc7948679; +imm32 r3, 0xd0799007; +imm32 r4, 0xefb79569; +imm32 r5, 0xcd35700b; +imm32 r6, 0xe00c877d; +imm32 r7, 0xf78e9097; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ); +R3 = A0.w; +A1 = R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ); +R5 = A0.w; +A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0x8354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xC794315B; +CHECKREG r3, 0x315B6A18; +CHECKREG r4, 0xEFB72AE5; +CHECKREG r5, 0x2AE51252; +CHECKREG r6, 0xE00C32D9; +CHECKREG r7, 0x32D896FE; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0xc5548abd; +imm32 r1, 0x7b5cfec7; +imm32 r2, 0xa1b55679; +imm32 r3, 0xb00b5007; +imm32 r4, 0xcfbcb5c9; +imm32 r5, 0x5235cb5c; +imm32 r6, 0xe50c50b8; +imm32 r7, 0x675e750b; +R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ); +R3 = A0.w; +R4.L = ( A0 -= R4.H * R5.L ); +R5 = A0.w; +R6.L = ( A0 = R6.H * R7.H ); +R7 = A0.w; +CHECKREG r0, 0xC554011F; +CHECKREG r1, 0x011EBDD6; +CHECKREG r2, 0xA1B5CB1B; +CHECKREG r3, 0xCB1A8C3C; +CHECKREG r4, 0xCFBCB741; +CHECKREG r5, 0xB741151C; +CHECKREG r6, 0xE50CEA3C; +CHECKREG r7, 0xEA3BDCD0; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x4b54babd; +imm32 r1, 0xbabcdec7; +imm32 r2, 0xa4bbe679; +imm32 r3, 0x8abdb007; +imm32 r4, 0x9f4b7b69; +imm32 r5, 0xa23487bb; +imm32 r6, 0xb00c488b; +imm32 r7, 0xc78ea4b8; +R0.L = ( A0 -= R1.L * R0.L ); +R1 = A0.w; +R2.L = ( A0 = R2.H * R3.L ); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.H ); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0x4B54D842; +CHECKREG r1, 0xD841BEFA; +CHECKREG r2, 0xA4BB3906; +CHECKREG r3, 0x3906223A; +CHECKREG r4, 0x9F4B46DE; +CHECKREG r5, 0x46DDA278; +CHECKREG r6, 0xB00C26E0; +CHECKREG r7, 0x26E036AC; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x1a545abd; +imm32 r1, 0x52fcfec7; +imm32 r2, 0xc13f5679; +imm32 r3, 0x9c04f007; +imm32 r4, 0xafccec69; +imm32 r5, 0xd23c5e1b; +imm32 r6, 0xc00cc6e2; +imm32 r7, 0x678edc7e; +A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ); +R5 = A0.w; +A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ); +R1 = A0.w; +CHECKREG r0, 0x1A544DFA; +CHECKREG r1, 0x4DFA5880; +CHECKREG r2, 0xC13F2602; +CHECKREG r3, 0x26025482; +CHECKREG r4, 0xAFCC1CAD; +CHECKREG r5, 0x1CAD17A0; +CHECKREG r6, 0xC00C4F71; +CHECKREG r7, 0x4F70B886; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_m.s new file mode 100644 index 0000000..dcdbae0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_m.s @@ -0,0 +1,127 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_m/c_dsp32mac_dr_a0_m.dsp +// Spec Reference: dsp32mac dr_a0 m +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xab235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246700f; + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +A1 -= R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ); +R3 = A0.w; +A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ); +R5 = A0.w; +A1 = R6.H * R7.H, R6.L = ( A0 = R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0x1354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xA124FF27; +CHECKREG r3, 0xFF274DDE; +CHECKREG r4, 0xEFBCFCD7; +CHECKREG r5, 0xFCD701B6; +CHECKREG r6, 0x000C000B; +CHECKREG r7, 0x000A846C; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R0.L = ( A0 += R6.L * R7.L ); +R1 = A0.w; +R2.L = ( A0 -= R2.L * R3.H ); +R3 = A0.w; +R4.L = ( A0 += R4.H * R5.L ); +R5 = A0.w; +R6.L = ( A0 = R0.H * R1.H ); +R7 = A0.w; +CHECKREG r0, 0x1354000B; +CHECKREG r1, 0x000A85F2; +CHECKREG r2, 0xA1240006; +CHECKREG r3, 0x00067846; +CHECKREG r4, 0xEFBC0005; +CHECKREG r5, 0x0005126E; +CHECKREG r6, 0x000C0002; +CHECKREG r7, 0x00018290; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R0.L = ( A0 = R1.L * R0.L ); +R1 = A0.w; +R2.L = ( A0 += R2.H * R3.L ); +R3 = A0.w; +R4.L = ( A0 += R4.H * R5.H ); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ); +R7 = A0.w; +CHECKREG r0, 0x1354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xA124FF1D; +CHECKREG r3, 0xFF1CEDCE; +CHECKREG r4, 0xEFBCFCCD; +CHECKREG r5, 0xFCCCA1A6; +CHECKREG r6, 0x000CFCD7; +CHECKREG r7, 0xFCD72612; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +A1 = R1.L * R0.L (M), R6.L = ( A0 -= R1.L * R0.L ); +R7 = A0.w; +A1 -= R2.L * R3.H (M), R2.L = ( A0 += R2.H * R3.L ); +R3 = A0.w; +A1 = R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ); +R5 = A0.w; +A1 -= R6.H * R7.H (M), R0.L = ( A0 = R6.L * R7.H ); +R1 = A0.w; +CHECKREG r0, 0x1354000B; +CHECKREG r1, 0x000A83F2; +CHECKREG r2, 0xA124FDB0; +CHECKREG r3, 0xFDAFD834; +CHECKREG r4, 0xEFBCFDB0; +CHECKREG r5, 0xFDAFB3D8; +CHECKREG r6, 0x000CFDB5; +CHECKREG r7, 0xFDB5083C; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_s.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_s.s new file mode 100644 index 0000000..2288130 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_s.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_s/c_dsp32mac_dr_a0_s.dsp +// Spec Reference: dsp32mac dr a0 s (scale by 2.0 signed fraction with round) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x83545abd; +imm32 r1, 0x98bcfec7; +imm32 r2, 0xc9948679; +imm32 r3, 0xd0999007; +imm32 r4, 0xefb99569; +imm32 r5, 0xcd35900b; +imm32 r6, 0xe00c89ad; +imm32 r7, 0xf78e909a; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (S2RND); +R1 = A0.w; +A1 = R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (S2RND); +R3 = A0.w; +A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (S2RND); +R5 = A0.w; +A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (S2RND); +R7 = A0.w; +CHECKREG r0, 0x8354FE44; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xC9945F37; +CHECKREG r3, 0x2F9B8618; +CHECKREG r4, 0xEFB96C22; +CHECKREG r5, 0x361112B2; +CHECKREG r6, 0xE00C7BBF; +CHECKREG r7, 0x3DDFA49E; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0xc8548abd; +imm32 r1, 0x7bccfec7; +imm32 r2, 0xa1bc5679; +imm32 r3, 0xb00bc007; +imm32 r4, 0xcfbcb8c9; +imm32 r5, 0x5235cb8c; +imm32 r6, 0xe50ca0b8; +imm32 r7, 0x675e700b; +R0.L = ( A0 = R1.L * R0.L ) (S2RND); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (S2RND); +R3 = A0.w; +R4.L = ( A0 -= R4.H * R5.L ) (S2RND); +R5 = A0.w; +R6.L = ( A0 = R6.H * R7.H ) (S2RND); +R7 = A0.w; +CHECKREG r0, 0xC854023D; +CHECKREG r1, 0x011EBDD6; +CHECKREG r2, 0xA1BC9635; +CHECKREG r3, 0xCB1A8C3C; +CHECKREG r4, 0xCFBC8000; +CHECKREG r5, 0xB7532E9C; +CHECKREG r6, 0xE50CD478; +CHECKREG r7, 0xEA3BDCD0; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x7b54babd; +imm32 r1, 0xbabcdec7; +imm32 r2, 0xabbbe679; +imm32 r3, 0x8abdb007; +imm32 r4, 0x9fab7b69; +imm32 r5, 0xa23a87bb; +imm32 r6, 0xb00ca88b; +imm32 r7, 0xc78eaab8; +R0.L = ( A0 = R1.L * R0.L ) (S2RND); +R1 = A0.w; +R2.L = ( A0 -= R2.H * R3.L ) (S2RND); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.H ) (S2RND); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (S2RND); +R7 = A0.w; +CHECKREG r0, 0x7B5423F4; +CHECKREG r1, 0x11FA1DD6; +CHECKREG r2, 0xABBBBAA7; +CHECKREG r3, 0xDD53999C; +CHECKREG r4, 0x9FAB7FFF; +CHECKREG r5, 0x4692C57C; +CHECKREG r6, 0xB00C7FFF; +CHECKREG r7, 0x6D23D9B0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xfa545abd; +imm32 r1, 0x5ffcfec7; +imm32 r2, 0xc1ef5679; +imm32 r3, 0x9c0ef007; +imm32 r4, 0xafccec69; +imm32 r5, 0xd23c9e1b; +imm32 r6, 0xc00cc0e2; +imm32 r7, 0x678edc0e; +A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (S2RND); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (S2RND); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (S2RND); +R5 = A0.w; +A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (S2RND); +R1 = A0.w; +CHECKREG r0, 0xFA54CF65; +CHECKREG r1, 0xE7B2ACD4; +CHECKREG r2, 0xC1EF7FFF; +CHECKREG r3, 0x6C45F786; +CHECKREG r4, 0xAFCCCEDE; +CHECKREG r5, 0xE76F2094; +CHECKREG r6, 0xC00C0838; +CHECKREG r7, 0x041C3834; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_t.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_t.s new file mode 100644 index 0000000..f72f8cc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_t.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_t/c_dsp32mac_dr_a0_t.dsp +// Spec Reference: dsp32mac dr a0 t (truncation) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbdbcfec7; +imm32 r2, 0xc1248679; +imm32 r3, 0xd0069007; +imm32 r4, 0xefbc4569; +imm32 r5, 0xcd35500b; +imm32 r6, 0xe00c800d; +imm32 r7, 0xf78e900f; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (T); +R1 = A0.w; +A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (T); +R3 = A0.w; +A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (T); +R5 = A0.w; +A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (T); +R7 = A0.w; +CHECKREG r0, 0xA354FF22; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0xC12436FD; +CHECKREG r3, 0x36FD0FF8; +CHECKREG r4, 0xEFBC3D71; +CHECKREG r5, 0x3D716BD0; +CHECKREG r6, 0xE00C45E2; +CHECKREG r7, 0x45E2903C; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x63548abd; +imm32 r1, 0x7dbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0xb0069007; +imm32 r4, 0xcfbc4569; +imm32 r5, 0xd235c00b; +imm32 r6, 0xe00ca00d; +imm32 r7, 0x678e700f; +R0.L = ( A0 = R1.L * R0.L ) (T); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (T); +R3 = A0.w; +R4.L = ( A0 -= R4.H * R5.L ) (T); +R5 = A0.w; +R6.L = ( A0 = R6.H * R7.H ) (T); +R7 = A0.w; +CHECKREG r0, 0x6354011E; +CHECKREG r1, 0x011EBDD6; +CHECKREG r2, 0xA124CB17; +CHECKREG r3, 0xCB172B82; +CHECKREG r4, 0xCFBCB2F9; +CHECKREG r5, 0xB2F9515A; +CHECKREG r6, 0xE00CE626; +CHECKREG r7, 0xE6263550; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x6dbcdec7; +imm32 r2, 0x7124e679; +imm32 r3, 0x80067007; +imm32 r4, 0x9fbc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb00c300d; +imm32 r7, 0xc78ea00f; +R0.L = ( A0 -= R1.L * R0.L ) (T); +R1 = A0.w; +R2.L = ( A0 = R2.H * R3.L ) (T); +R3 = A0.w; +R4.L = ( A0 -= R4.H * R5.H ) (T); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (T); +R7 = A0.w; +CHECKREG r0, 0x5354D42C; +CHECKREG r1, 0xD42C177A; +CHECKREG r2, 0x71246305; +CHECKREG r3, 0x6305AFF8; +CHECKREG r4, 0x9FBC1C7B; +CHECKREG r5, 0x1C7B9C20; +CHECKREG r6, 0xB00C074B; +CHECKREG r7, 0x074B208C; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +A1 = R1.L * R0.L (M), R0.L = ( A0 += R1.L * R0.L ) (T); +R1 = A0.w; +A1 += R2.L * R3.H (M), R2.L = ( A0 -= R2.H * R3.L ) (T); +R3 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (T); +R5 = A0.w; +A1 -= R6.H * R7.H (M), R6.L = ( A0 += R6.L * R7.H ) (T); +R7 = A0.w; +CHECKREG r0, 0x3354066D; +CHECKREG r1, 0x066D3E62; +CHECKREG r2, 0x71240667; +CHECKREG r3, 0x06670E6A; +CHECKREG r4, 0xAFBC1CB7; +CHECKREG r5, 0x1CB733D8; +CHECKREG r6, 0xC00CCF17; +CHECKREG r7, 0xCF173844; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_tu.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_tu.s new file mode 100644 index 0000000..61c4670 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_tu.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_tu/c_dsp32mac_dr_a0_tu.dsp +// Spec Reference: dsp32mac dr a0 tu (truncate unsigned fraction) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xf3545abd; +imm32 r1, 0x7fbcfec7; +imm32 r2, 0xc7fff679; +imm32 r3, 0xd0799007; +imm32 r4, 0xefb79f69; +imm32 r5, 0xcd35700b; +imm32 r6, 0xe00c87fd; +imm32 r7, 0xf78e909f; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (TFU); +R1 = A0.w; +A1 -= R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (TFU); +R3 = A0.w; +A1 += R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ) (TFU); +R5 = A0.w; +A1 += R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (TFU); +R7 = A0.w; +CHECKREG r0, 0xF3545A4E; +CHECKREG r1, 0x5A4E0EEB; +CHECKREG r2, 0xC7FF0000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xEFB70000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xE00C8380; +CHECKREG r7, 0x83808956; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0xc5548abd; +imm32 r1, 0x9b5cfec7; +imm32 r2, 0xa9b55679; +imm32 r3, 0xb09b5007; +imm32 r4, 0xcfb9b5c9; +imm32 r5, 0x52359b5c; +imm32 r6, 0xe50c5098; +imm32 r7, 0x675e7509; +R0.L = ( A0 = R1.L * R0.L ) (TFU); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (TFU); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.L ) (TFU); +R5 = A0.w; +R6.L = ( A0 -= R6.H * R7.H ) (TFU); +R7 = A0.w; +CHECKREG r0, 0xC5548A13; +CHECKREG r1, 0x8A135EEB; +CHECKREG r2, 0xA9B5C5BA; +CHECKREG r3, 0xC5BAEA2E; +CHECKREG r4, 0xCFB97E0F; +CHECKREG r5, 0x7E0FA97C; +CHECKREG r6, 0xE50C2193; +CHECKREG r7, 0x2193BB14; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x4b54babd; +imm32 r1, 0x12346ec7; +imm32 r2, 0xa4bbe679; +imm32 r3, 0x8abdb707; +imm32 r4, 0x9f4b7b69; +imm32 r5, 0xa234877b; +imm32 r6, 0xb00c4887; +imm32 r7, 0xc78ea4b8; +R0.L = ( A0 -= R1.L * R0.L ) (TFU); +R1 = A0.w; +R2.L = ( A0 = R2.H * R3.L ) (TFU); +R3 = A0.w; +R4.L = ( A0 -= R4.H * R5.H ) (TFU); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (TFU); +R7 = A0.w; +CHECKREG r0, 0x4B540000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xA4BB75C6; +CHECKREG r3, 0x75C62E1D; +CHECKREG r4, 0x9F4B10D8; +CHECKREG r5, 0x10D85CE1; +CHECKREG r6, 0xB00C4961; +CHECKREG r7, 0x496188C3; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x1a545abd; +imm32 r1, 0x42fcfec7; +imm32 r2, 0xc53f5679; +imm32 r3, 0x9c64f007; +imm32 r4, 0xafc7ec69; +imm32 r5, 0xd23c891b; +imm32 r6, 0xc00cc602; +imm32 r7, 0x678edc7e; +A1 -= R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (TFU); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ) (TFU); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (TFU); +R5 = A0.w; +A1 -= R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (TFU); +R1 = A0.w; +CHECKREG r0, 0x1A5498EA; +CHECKREG r1, 0x98EA3745; +CHECKREG r2, 0xC53FA3AF; +CHECKREG r3, 0xA3AF97AE; +CHECKREG r4, 0xAFC7905A; +CHECKREG r5, 0x905A70A4; +CHECKREG r6, 0xC00C2ED1; +CHECKREG r7, 0x2ED15DDC; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_u.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_u.s new file mode 100644 index 0000000..5ca5cac --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_u.s @@ -0,0 +1,119 @@ +//Original:/testcases/core/c_dsp32mac_dr_a0_u/c_dsp32mac_dr_a0_u.dsp +// Spec Reference: dsp32mac dr a0 u (unsigned fraction and unsigned int) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0x9abcfec7; +imm32 r2, 0xc9a48679; +imm32 r3, 0xd09a9007; +imm32 r4, 0xefb9a569; +imm32 r5, 0xcd359a0b; +imm32 r6, 0xe00c89ad; +imm32 r7, 0xf78e909a; +A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (FU); +R1 = A0.w; +A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (FU); +R3 = A0.w; +A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (FU); +R5 = A0.w; +A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (FU); +R7 = A0.w; +CHECKREG r0, 0xA3545A4E; +CHECKREG r1, 0x5A4E0EEB; +CHECKREG r2, 0xC9A40000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xEFB9C029; +CHECKREG r5, 0xC028C64D; +CHECKREG r6, 0xE00CFFFF; +CHECKREG r7, 0x454B0F43; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0xb8548abd; +imm32 r1, 0x7b8cfec7; +imm32 r2, 0xa1b85679; +imm32 r3, 0xb00b8007; +imm32 r4, 0xcfbcb869; +imm32 r5, 0xd235cb8b; +imm32 r6, 0xe00ca0b8; +imm32 r7, 0x678e700b; +R0.L = ( A0 = R1.L * R0.L ) (FU); +R1 = A0.w; +R2.L = ( A0 += R2.L * R3.H ) (FU); +R3 = A0.w; +R4.L = ( A0 -= R4.H * R5.L ) (FU); +R5 = A0.w; +R6.L = ( A0 = R6.H * R7.H ) (FU); +R7 = A0.w; +CHECKREG r0, 0xB8548A13; +CHECKREG r1, 0x8A135EEB; +CHECKREG r2, 0xA1B8C58A; +CHECKREG r3, 0xC58A461E; +CHECKREG r4, 0xCFBC205F; +CHECKREG r5, 0x205F670A; +CHECKREG r6, 0xE00C5AA1; +CHECKREG r7, 0x5AA11AA8; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x7b54babd; +imm32 r1, 0xb7bcdec7; +imm32 r2, 0xab7be679; +imm32 r3, 0x8ab7b007; +imm32 r4, 0x9fab7b69; +imm32 r5, 0xa23ab7bb; +imm32 r6, 0xb00cab7b; +imm32 r7, 0xc78eaab7; +R0.L = ( A0 = R1.L * R0.L ) (FU); +R1 = A0.w; +R2.L = ( A0 -= R2.H * R3.L ) (FU); +R3 = A0.w; +R4.L = ( A0 = R4.H * R5.H ) (FU); +R5 = A0.w; +R6.L = ( A0 += R6.L * R7.H ) (FU); +R7 = A0.w; +CHECKREG r0, 0x7B54A281; +CHECKREG r1, 0xA2810EEB; +CHECKREG r2, 0xAB7B2C98; +CHECKREG r3, 0x2C97CE8E; +CHECKREG r4, 0x9FAB652E; +CHECKREG r5, 0x652E62BE; +CHECKREG r6, 0xB00CEADA; +CHECKREG r7, 0xEADA1DF8; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xea545abd; +imm32 r1, 0x5eacfec7; +imm32 r2, 0xc1ea5679; +imm32 r3, 0x9c0ea007; +imm32 r4, 0xafccea69; +imm32 r5, 0xd23c9eab; +imm32 r6, 0xc00cc0ea; +imm32 r7, 0x678edc0e; +A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (FU); +R3 = A0.w; +A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (FU); +R7 = A0.w; +A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (FU); +R5 = A0.w; +A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (FU); +R1 = A0.w; +CHECKREG r0, 0xEA540484; +CHECKREG r1, 0x04840000; +CHECKREG r2, 0xC1EAFFFF; +CHECKREG r3, 0x45282CE3; +CHECKREG r4, 0xAFCC0000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xC00C2200; +CHECKREG r7, 0x22002A7E; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1.s new file mode 100644 index 0000000..33c5981 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1.s @@ -0,0 +1,213 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1/c_dsp32mac_dr_a1.dsp +// Spec Reference: dsp32mac dr_a1 +# mach: bfin + +.include "testutils.inc" + start + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R0.H = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L; +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; +R3 = A1.w; +R4.H = ( A1 = R4.L * R5.L ), A0 += R4.H * R5.H; +R5 = A1.w; +R6.H = ( A1 += R6.L * R7.L ), A0 += R6.L * R7.H; +R7 = A1.w; +CHECKREG r0, 0xFF225ABD; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0x00055679; +CHECKREG r3, 0x0004BA9E; +CHECKREG r4, 0x00064569; +CHECKREG r5, 0x0005F706; +CHECKREG r6, 0x0006000D; +CHECKREG r7, 0x0005F88C; + +imm32 r0, 0x13545abd; +imm32 r1, 0xa1bcfec7; +imm32 r2, 0xa1145679; +imm32 r3, 0x00010007; +imm32 r4, 0xefbc1569; +imm32 r5, 0x1235010b; +imm32 r6, 0x000c001d; +imm32 r7, 0x678e0001; +R4.H = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L; +R5 = A1.w; +R0.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L; +R1 = A1.w; +R2.H = ( A1 = R4.L * R5.H ), A0 += R4.H * R5.H; +R3 = A1.w; +R6.H = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H; +R7 = A1.w; +CHECKREG r0, 0x00015ABD; +CHECKREG r1, 0x0000ACF2; +CHECKREG r2, 0xFFF95679; +CHECKREG r3, 0xFFF8F98C; +CHECKREG r4, 0xFFD71569; +CHECKREG r5, 0xFFD6B524; +CHECKREG r6, 0x0010001D; +CHECKREG r7, 0x00106FB8; + +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xa1845679; +imm32 r3, 0x00080007; +imm32 r4, 0xefbc8569; +imm32 r5, 0x1235080b; +imm32 r6, 0x000c008d; +imm32 r7, 0x678e0008; +R6.H = ( A1 += R1.H * R0.L ), A0 = R1.L * R0.L; +R7 = A1.w; +R2.H = ( A1 = R2.H * R3.L ), A0 = R2.H * R3.L; +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H; +R5 = A1.w; +R0.H = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H; +R1 = A1.w; +CHECKREG r0, 0x1B505ABD; +CHECKREG r1, 0x1B4FC2A8; +CHECKREG r2, 0xFFFB5679; +CHECKREG r3, 0xFFFAD538; +CHECKREG r4, 0xFEFA8569; +CHECKREG r5, 0xFEFA5A28; +CHECKREG r6, 0xC234008D; +CHECKREG r7, 0xC233C550; + +imm32 r0, 0xc3545abd; +imm32 r1, 0xacbcfec7; +imm32 r2, 0xa1c45679; +imm32 r3, 0x000c0007; +imm32 r4, 0xefbcc569; +imm32 r5, 0x12350c0b; +imm32 r6, 0x000c00cd; +imm32 r7, 0x678e000c; +R6.H = ( A1 += R1.H * R0.H ), A0 = R1.L * R0.L; +R7 = A1.w; +R0.H = ( A1 = R2.H * R3.H ), A0 = R2.H * R3.L; +R1 = A1.w; +R4.H = ( A1 = R4.H * R5.H ), A0 += R4.H * R5.H; +R5 = A1.w; +R2.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H; +R3 = A1.w; +CHECKREG r0, 0xFFF75ABD; +CHECKREG r1, 0xFFF72A60; +CHECKREG r2, 0x20875679; +CHECKREG r3, 0x2086A6C8; +CHECKREG r4, 0xFDB0C569; +CHECKREG r5, 0xFDAFB3D8; +CHECKREG r6, 0x42C800CD; +CHECKREG r7, 0x42C78608; + +imm32 r0, 0x01542abd; +imm32 r1, 0x02bc4ec7; +imm32 r2, 0x03240679; +imm32 r3, 0x04061007; +imm32 r4, 0x05bc2569; +imm32 r5, 0x0635300b; +imm32 r6, 0x070c200d; +imm32 r7, 0x088e100f; +R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L; +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.L ), A0 -= R2.H * R3.L; +R3 = A1.w; +R4.H = ( A1 -= R4.L * R5.L ), A0 += R4.H * R5.H; +R5 = A1.w; +R6.H = ( A1 += R6.L * R7.L ), A0 -= R6.L * R7.H; +R7 = A1.w; +CHECKREG r0, 0x06392ABD; +CHECKREG r1, 0x063908F2; +CHECKREG r2, 0x056A0679; +CHECKREG r3, 0x05698E54; +CHECKREG r4, 0xF75F2569; +CHECKREG r5, 0xF75EF74E; +CHECKREG r6, 0xFB64200D; +CHECKREG r7, 0xFB6458D4; + +imm32 r0, 0x03545abd; +imm32 r1, 0x31bcfec7; +imm32 r2, 0x11145679; +imm32 r3, 0x00010007; +imm32 r4, 0xefbc1569; +imm32 r5, 0x1235010b; +imm32 r6, 0x000c001d; +imm32 r7, 0x678e0001; +R4.H = ( A1 += R1.L * R0.H ), A0 -= R1.L * R0.L; +R5 = A1.w; +R0.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L; +R1 = A1.w; +R2.H = ( A1 -= R4.L * R5.H ), A0 += R4.H * R5.H; +R3 = A1.w; +R6.H = ( A1 += R6.L * R7.H ), A0 -= R6.L * R7.H; +R7 = A1.w; +CHECKREG r0, 0xFB5C5ABD; +CHECKREG r1, 0xFB5B887A; +CHECKREG r2, 0xFC225679; +CHECKREG r3, 0xFC223F02; +CHECKREG r4, 0xFB5C1569; +CHECKREG r5, 0xFB5C356C; +CHECKREG r6, 0xFC3A001D; +CHECKREG r7, 0xFC39B52E; + +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xa1845679; +imm32 r3, 0x00080007; +imm32 r4, 0xefbc8569; +imm32 r5, 0x1235080b; +imm32 r6, 0x000c008d; +imm32 r7, 0x678e0008; +R6.H = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L; +R7 = A1.w; +R2.H = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L; +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ), A0 -= R4.H * R5.H; +R5 = A1.w; +R0.H = ( A1 += R6.H * R7.L ), A0 -= R6.L * R7.H; +R1 = A1.w; +CHECKREG r0, 0xF9745ABD; +CHECKREG r1, 0xF9741604; +CHECKREG r2, 0xBE625679; +CHECKREG r3, 0xBE62358E; +CHECKREG r4, 0xFEFA8569; +CHECKREG r5, 0xFEFA5A28; +CHECKREG r6, 0xBE5D008D; +CHECKREG r7, 0xBE5D0AC6; + +imm32 r0, 0xc3545abd; +imm32 r1, 0xacbcfec7; +imm32 r2, 0xa1c45679; +imm32 r3, 0x000c0007; +imm32 r4, 0xefbcc569; +imm32 r5, 0x12350c0b; +imm32 r6, 0x000c00cd; +imm32 r7, 0x678e000c; +R6.H = ( A1 += R1.H * R0.H ), A0 -= R1.L * R0.L; +R7 = A1.w; +R0.H = ( A1 = R2.H * R3.H ), A0 -= R2.H * R3.L; +R1 = A1.w; +R4.H = ( A1 -= R4.H * R5.H ), A0 += R4.H * R5.H; +R5 = A1.w; +R2.H = ( A1 -= R6.H * R7.H ), A0 += R6.L * R7.H; +R3 = A1.w; +CHECKREG r0, 0xFFF75ABD; +CHECKREG r1, 0xFFF72A60; +CHECKREG r2, 0xF9D05679; +CHECKREG r3, 0xF9D00540; +CHECKREG r4, 0x0247C569; +CHECKREG r5, 0x02477688; +CHECKREG r6, 0x20EC00CD; +CHECKREG r7, 0x20EBD964; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_i.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_i.s new file mode 100644 index 0000000..de42387 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_i.s @@ -0,0 +1,273 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_i/c_dsp32mac_dr_a1_i.dsp +// Spec Reference: dsp32mac dr a1 i (signed int) +# mach: bfin + +.include "testutils.inc" + start + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbdbcfec7; +imm32 r2, 0xc1248679; +imm32 r3, 0xd0069007; +imm32 r4, 0xefbc4569; +imm32 r5, 0xcd35500b; +imm32 r6, 0xe00c800d; +imm32 r7, 0xf78e900f; +R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (IS); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (IS); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (IS); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x7FFF8679; +CHECKREG r3, 0x16C676D6; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0xFAEA0D14; +CHECKREG r6, 0x7FFF800D; +CHECKREG r7, 0x010DDAA8; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x63548abd; +imm32 r1, 0x7dbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0xb0069007; +imm32 r4, 0xcfbc4569; +imm32 r5, 0xFFFF8000; +imm32 r6, 0x7FFF800D; +imm32 r7, 0x00007FFF; +R0.H = ( A1 = R1.L * R0.L ) (IS); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (IS); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (IS); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (IS); +R7 = A1.w; +CHECKREG r0, 0x7FFF8ABD; +CHECKREG r1, 0x008F5EEB; +CHECKREG r2, 0x80005679; +CHECKREG r3, 0xE58B95C1; +CHECKREG r4, 0x7FFF4569; +CHECKREG r5, 0x18220000; +CHECKREG r6, 0x0000800D; +CHECKREG r7, 0x00000000; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x6dbcdec7; +imm32 r2, 0x7124e679; +imm32 r3, 0x80067007; +imm32 r4, 0x9fbc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb00c300d; +imm32 r7, 0xc78ea00f; + R0.H = A1 , A0 = R1.L * R0.L (IS); +R1 = A1.w; + R2.H = A1 , A0 = R2.H * R3.L (IS); +R3 = A1.w; + R4.H = A1 , A0 = R4.H * R5.H (IS); +R5 = A1.w; + R6.H = A1 , A0 += R6.L * R7.H (IS); +R7 = A1.w; +CHECKREG r0, 0x0000BABD; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x0000E679; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00004569; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x0000300D; +CHECKREG r7, 0x00000000; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (IS); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M), A0 = R2.H * R3.L (IS); +R3 = A0.w; +R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (IS); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H (IS); +R7 = A0.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x7FFF5679; +CHECKREG r3, 0x000317FC; +CHECKREG r4, 0x7FFF4569; +CHECKREG r5, 0x030D72D5; +CHECKREG r6, 0x8000A00D; +CHECKREG r7, 0xE78B9C22; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xc1845679; +imm32 r3, 0x1c080007; +imm32 r4, 0xe1cc8569; +imm32 r5, 0x921c080b; +imm32 r6, 0x7901908d; +imm32 r7, 0x679e9008; +R0.H = ( A1 += R1.L * R0.L ) (M,IS); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ) (M,IS); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ) (M,IS); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M,IS); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xE5B26993; +CHECKREG r2, 0x7FFF5679; +CHECKREG r3, 0x0977EFC8; +CHECKREG r4, 0x7FFF8569; +CHECKREG r5, 0x0885038C; +CHECKREG r6, 0x7FFF908D; +CHECKREG r7, 0x30FA159E; + +imm32 r0, 0x03545abd; +imm32 r1, 0x1dbcfec7; +imm32 r2, 0x21248679; +imm32 r3, 0x30069007; +imm32 r4, 0x4fbc4569; +imm32 r5, 0x5d35500b; +imm32 r6, 0x600c800d; +imm32 r7, 0x778e900f; +R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L (IS); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L (IS); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IS); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ), A0 -= R6.L * R7.H (IS); +R7 = A1.w; +CHECKREG r0, 0x7FFF5ABD; +CHECKREG r1, 0x316906B3; +CHECKREG r2, 0x80008679; +CHECKREG r3, 0xE933D6D6; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0xD045A9C2; +CHECKREG r6, 0x8000800D; +CHECKREG r7, 0xA36ACF1A; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x63540abd; +imm32 r1, 0x7dbc1ec7; +imm32 r2, 0xa1242679; +imm32 r3, 0x40063007; +imm32 r4, 0x1fbc4569; +imm32 r5, 0x2FFF4000; +imm32 r6, 0x7FFF800D; +imm32 r7, 0x10007FFF; +R0.H = ( A1 -= R1.L * R0.L ) (IS); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (IS); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (IS); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (IS); +R7 = A1.w; +CHECKREG r0, 0x80000ABD; +CHECKREG r1, 0xA220502F; +CHECKREG r2, 0x80002679; +CHECKREG r3, 0x98812959; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0x90922959; +CHECKREG r6, 0x8000800D; +CHECKREG r7, 0x88923959; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x2354babd; +imm32 r1, 0x3dbcdec7; +imm32 r2, 0x7424e679; +imm32 r3, 0x80067007; +imm32 r4, 0x95bc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb06c300d; +imm32 r7, 0xc787a00f; + R0.H = A1 , A0 -= R1.L * R0.L (IS); +R1 = A1.w; + R2.H = A1 , A0 -= R2.H * R3.L (IS); +R3 = A1.w; + R4.H = A1 , A0 -= R4.H * R5.H (IS); +R5 = A1.w; + R6.H = A1 , A0 -= R6.L * R7.H (IS); +R7 = A1.w; +CHECKREG r0, 0x8000BABD; +CHECKREG r1, 0x88923959; +CHECKREG r2, 0x8000E679; +CHECKREG r3, 0x88923959; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0x88923959; +CHECKREG r6, 0x8000300D; +CHECKREG r7, 0x88923959; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +R0.H = ( A1 -= R1.L * R0.L ) (M), A0 += R1.L * R0.L (IS); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (IS); +R3 = A0.w; +R4.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H (IS); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (M), A0 += R6.L * R7.H (IS); +R7 = A0.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0x89012A6E; +CHECKREG r2, 0x80005679; +CHECKREG r3, 0x000317FC; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0x2B3160AC; +CHECKREG r6, 0x8000A00D; +CHECKREG r7, 0xCAD78046; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xc1845679; +imm32 r3, 0x1c080007; +imm32 r4, 0xe1cc8569; +imm32 r5, 0x921c080b; +imm32 r6, 0x7901908d; +imm32 r7, 0x679e9008; +R0.H = ( A1 -= R1.L * R0.L ) (M,IS); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M,IS); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (M,IS); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (M,IS); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0x457EF719; +CHECKREG r2, 0x80005679; +CHECKREG r3, 0x3C070751; +CHECKREG r4, 0x80008569; +CHECKREG r5, 0x3CF9F38D; +CHECKREG r6, 0x8000908D; +CHECKREG r7, 0x0BFFDDEF; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_ih.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_ih.s new file mode 100644 index 0000000..ae20990 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_ih.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_ih/c_dsp32mac_dr_a1_ih.dsp +// Spec Reference: dsp32mac dr_a1 ih (int multiplication with word extraction) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x93545abd; +imm32 r1, 0x1dbcfec7; +imm32 r2, 0x52248679; +imm32 r3, 0xd6069007; +imm32 r4, 0xef7c4569; +imm32 r5, 0xcd38500b; +imm32 r6, 0xe00c900d; +imm32 r7, 0xf78e990f; +R0.H = ( A1 = R1.L * R0.L ), A0 -= R1.L * R0.L (IH); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ), A0 -= R2.H * R3.L (IH); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IH); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ), A0 = R6.L * R7.H (IH); +R7 = A1.w; +CHECKREG r0, 0xFF915ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x137E8679; +CHECKREG r3, 0x137E5BC1; +CHECKREG r4, 0x18A84569; +CHECKREG r5, 0x18A8516D; +CHECKREG r6, 0x010E900D; +CHECKREG r7, 0x010DDAA8; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0x83548abd; +imm32 r1, 0x76bcfec7; +imm32 r2, 0xa1745679; +imm32 r3, 0xb0269007; +imm32 r4, 0xcfb34569; +imm32 r5, 0xd235600b; +imm32 r6, 0xe00ca70d; +imm32 r7, 0x678e708f; +R0.H = ( A1 -= R1.L * R0.L ) (IH); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (IH); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (IH); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (IH); +R7 = A1.w; +CHECKREG r0, 0x007E8ABD; +CHECKREG r1, 0x007E7BBD; +CHECKREG r2, 0xE5865679; +CHECKREG r3, 0xE58581B3; +CHECKREG r4, 0xEDE14569; +CHECKREG r5, 0xEDE10CB1; +CHECKREG r6, 0xFACEA70D; +CHECKREG r7, 0xFACDF209; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x9dbcdec7; +imm32 r2, 0x7724e679; +imm32 r3, 0x80567007; +imm32 r4, 0x9fb34569; +imm32 r5, 0xa235200b; +imm32 r6, 0xb00c100d; +imm32 r7, 0x9876a10f; + R0.H = A1 , A0 = R1.L * R0.L (IH); +R1 = A1.w; + R2.H = A1 , A0 += R2.H * R3.L (IH); +R3 = A1.w; + R4.H = A1 , A0 -= R4.H * R5.H (IH); +R5 = A1.w; + R6.H = A1 , A0 += R6.L * R7.H (IH); +R7 = A1.w; +CHECKREG r0, 0xFACEBABD; +CHECKREG r1, 0xFACDF209; +CHECKREG r2, 0xFACEE679; +CHECKREG r3, 0xFACDF209; +CHECKREG r4, 0xFACE4569; +CHECKREG r5, 0xFACDF209; +CHECKREG r6, 0xFACE100D; +CHECKREG r7, 0xFACDF209; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x9dbcfec7; +imm32 r2, 0x81245679; +imm32 r3, 0x97060007; +imm32 r4, 0xaf6c4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00c400d; +imm32 r7, 0x678ed30f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 -= R1.L * R0.L (IH); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M), A0 += R2.H * R3.L (IH); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (M), A0 += R4.H * R5.H (IH); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M), A0 -= R6.L * R7.H (IH); +R7 = A1.w; +CHECKREG r0, 0xFF915ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x32945679; +CHECKREG r3, 0x329474C1; +CHECKREG r4, 0xD2A94569; +CHECKREG r5, 0xD2A949A4; +CHECKREG r6, 0xE621400D; +CHECKREG r7, 0xE6215AA8; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x92005ABD; +imm32 r1, 0x09300000; +imm32 r2, 0x56749679; +imm32 r3, 0x30A95000; +imm32 r4, 0xa0009669; +imm32 r5, 0x01000970; +imm32 r6, 0xdf45609D; +imm32 r7, 0x12345679; +R0.H = ( A1 -= R1.L * R0.L ) (M,IH); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M,IH); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (M,IH); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ) (M,IH); +R7 = A1.w; +CHECKREG r0, 0xE6215ABD; +CHECKREG r1, 0xE6215AA8; +CHECKREG r2, 0xD2129679; +CHECKREG r3, 0xD2126089; +CHECKREG r4, 0xFC769669; +CHECKREG r5, 0xFC760000; +CHECKREG r6, 0xFA22609D; +CHECKREG r7, 0xFA223404; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_is.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_is.s new file mode 100644 index 0000000..2d97468 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_is.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_is/c_dsp32mac_dr_a1_is.dsp +// Spec Reference: dsp32mac dr_a1 is ((scale by 2 signed int) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbdbcfec7; +imm32 r2, 0xc1248679; +imm32 r3, 0xd0069007; +imm32 r4, 0xefbc4569; +imm32 r5, 0xcd35500b; +imm32 r6, 0xe00c800d; +imm32 r7, 0xf78e900f; +R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (ISS2); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (ISS2); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (ISS2); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (ISS2); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x80008679; +CHECKREG r3, 0xE8CA9815; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0xE3B4A529; +CHECKREG r6, 0x8000800D; +CHECKREG r7, 0xE4C27FD1; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0x63548abd; +imm32 r1, 0x7dbcfec7; +imm32 r2, 0xC5885679; +imm32 r3, 0xC5880000; +imm32 r4, 0xcfbc4569; +imm32 r5, 0xd235c00b; +imm32 r6, 0xe00ca00d; +imm32 r7, 0x678e700f; +R0.H = ( A1 = R1.L * R0.L ) (ISS2); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (ISS2); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (ISS2); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (ISS2); +R7 = A1.w; +CHECKREG r0, 0x7FFF8ABD; +CHECKREG r1, 0x008F5EEB; +CHECKREG r2, 0x80005679; +CHECKREG r3, 0xECCF6C33; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0xE0C07F1F; +CHECKREG r6, 0x8000A00D; +CHECKREG r7, 0xEDAD6477; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x6dbcdec7; +imm32 r2, 0x7124e679; +imm32 r3, 0x80067007; +imm32 r4, 0x9fbc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb00c300d; +imm32 r7, 0xc78ea00f; + R0.H = A1 , A0 -= R1.L * R0.L (ISS2); +R1 = A1.w; + R2.H = A1 , A0 += R2.H * R3.L (ISS2); +R3 = A1.w; + R4.H = A1 , A0 -= R4.H * R5.H (ISS2); +R5 = A1.w; + R6.H = A1 , A0 = R6.L * R7.H (ISS2); +R7 = A1.w; +CHECKREG r0, 0x8000BABD; +CHECKREG r1, 0xEDAD6477; +CHECKREG r2, 0x8000E679; +CHECKREG r3, 0xEDAD6477; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0xEDAD6477; +CHECKREG r6, 0x8000300D; +CHECKREG r7, 0xEDAD6477; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (ISS2); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (ISS2); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (ISS2); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (ISS2); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x7FFF5679; +CHECKREG r3, 0x303725C1; +CHECKREG r4, 0x7FFF4569; +CHECKREG r5, 0x5D60D8AD; +CHECKREG r6, 0x7FFFA00D; +CHECKREG r7, 0x43823355; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x92005ABD; +imm32 r1, 0x09300000; +imm32 r2, 0x56749679; +imm32 r3, 0x30A95000; +imm32 r4, 0xa0009669; +imm32 r5, 0x01000970; +imm32 r6, 0xdf45609D; +imm32 r7, 0x12345679; +R0.H = ( A1 += R1.L * R0.L ) (M,ISS2); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M,ISS2); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (M,ISS2); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M,ISS2); +R7 = A1.w; +CHECKREG r0, 0x7FFF5ABD; +CHECKREG r1, 0x43823355; +CHECKREG r2, 0x7FFF9679; +CHECKREG r3, 0x57912D74; +CHECKREG r4, 0x7FFF9669; +CHECKREG r5, 0x5B1B2D74; +CHECKREG r6, 0x8000609D; +CHECKREG r7, 0xFDAC3404; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_iu.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_iu.s new file mode 100644 index 0000000..8f36ac3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_iu.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_iu/c_dsp32mac_dr_a1_iu.dsp +// Spec Reference: dsp32mac dr_a1 iu (unsigned integer) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x93545abd; +imm32 r1, 0x7890afc7; +imm32 r2, 0x52248679; +imm32 r3, 0xd5069007; +imm32 r4, 0xef5c4569; +imm32 r5, 0xcd35500b; +imm32 r6, 0xe00c500d; +imm32 r7, 0xf78e950f; +R0.H = ( A1 = R1.L * R0.L ), A0 += R1.L * R0.L (IU); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ), A0 = R2.H * R3.L (IU); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ), A0 += R4.H * R5.H (IU); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ), A0 -= R6.L * R7.H (IU); +R7 = A1.w; +CHECKREG r0, 0xFFFF5ABD; +CHECKREG r1, 0x3E4DBBEB; +CHECKREG r2, 0xFFFF8679; +CHECKREG r3, 0xAE338FC1; +CHECKREG r4, 0xFFFF4569; +CHECKREG r5, 0xF90A98B5; +CHECKREG r6, 0xFFFF500D; +CHECKREG r7, 0x2062BE0D; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0xd3548abd; +imm32 r1, 0x9dbcfec7; +imm32 r2, 0xa9d45679; +imm32 r3, 0xb09d9007; +imm32 r4, 0xcfb9d569; +imm32 r5, 0xd2359d0b; +imm32 r6, 0xe00ca90d; +imm32 r7, 0x678e709f; +R0.H = ( A1 += R1.L * R0.L ) (IU); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (IU); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (IU); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (IU); +R7 = A1.w; +CHECKREG r0, 0xFFFF8ABD; +CHECKREG r1, 0xAA761CF8; +CHECKREG r2, 0xFFFF5679; +CHECKREG r3, 0x6ECDE4C3; +CHECKREG r4, 0xFFFFD569; +CHECKREG r5, 0x7F6D61F3; +CHECKREG r6, 0xFFFFA90D; +CHECKREG r7, 0x24CC474B; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0xa354babd; +imm32 r1, 0x9abcdec7; +imm32 r2, 0x77a4e679; +imm32 r3, 0x805a7007; +imm32 r4, 0x9fb3a569; +imm32 r5, 0xa2352a0b; +imm32 r6, 0xb00c10ad; +imm32 r7, 0x9876a10a; + R0.H = A1 , A0 -= R1.L * R0.L (IU); +R1 = A1.w; + R2.H = A1 , A0 += R2.H * R3.L (IU); +R3 = A1.w; + R4.H = A1 , A0 = R4.H * R5.H (IU); +R5 = A1.w; + R6.H = A1 , A0 -= R6.L * R7.H (IU); +R7 = A1.w; +CHECKREG r0, 0xFFFFBABD; +CHECKREG r1, 0x24CC474B; +CHECKREG r2, 0xFFFFE679; +CHECKREG r3, 0x24CC474B; +CHECKREG r4, 0xFFFFA569; +CHECKREG r5, 0x24CC474B; +CHECKREG r6, 0xFFFF10AD; +CHECKREG r7, 0x24CC474B; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x9dbcfec7; +imm32 r2, 0x81245679; +imm32 r3, 0x97060007; +imm32 r4, 0xaf6c4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00c400d; +imm32 r7, 0x678ed30f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (IU); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (IU); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (M), A0 -= R4.H * R5.H (IU); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (IU); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x80005679; +CHECKREG r3, 0xCC8DA915; +CHECKREG r4, 0x80004569; +CHECKREG r5, 0xD2A949A4; +CHECKREG r6, 0x8000400D; +CHECKREG r7, 0xB8CAA44C; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0xe2005ABD; +imm32 r1, 0x0e300000; +imm32 r2, 0x56e49679; +imm32 r3, 0x30Ae5000; +imm32 r4, 0xa000e669; +imm32 r5, 0x01000e70; +imm32 r6, 0xdf4560eD; +imm32 r7, 0x1234567e; +R0.H = ( A1 -= R1.L * R0.L ) (M,IU); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M,IU); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (M,IU); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (M,IU); +R7 = A1.w; +CHECKREG r0, 0x80005ABD; +CHECKREG r1, 0xB8CAA44C; +CHECKREG r2, 0x80009679; +CHECKREG r3, 0xA4B99A8A; +CHECKREG r4, 0x8000E669; +CHECKREG r5, 0xAA239A8A; +CHECKREG r6, 0x800060ED; +CHECKREG r7, 0xAC776686; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_m.s new file mode 100644 index 0000000..b44d5e6 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_m.s @@ -0,0 +1,206 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_m/c_dsp32mac_dr_a1_m.dsp +// Spec Reference: dsp32mac dr a1 m +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xab235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246700f; + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R0.H = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L; +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L; +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H; +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H; +R7 = A1.w; +CHECKREG r0, 0xFF225ABD; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0x00045679; +CHECKREG r3, 0x00040DAC; +CHECKREG r4, 0xFFFF4569; +CHECKREG r5, 0xFFFE9A28; +CHECKREG r6, 0x0008000D; +CHECKREG r7, 0x00084F78; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R0.H = ( A1 += R1.L * R0.L ); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ); +R7 = A1.w; +CHECKREG r0, 0xFF2A5ABD; +CHECKREG r1, 0xFF2A6D4E; +CHECKREG r2, 0x00045679; +CHECKREG r3, 0x00040DAC; +CHECKREG r4, 0x00034569; +CHECKREG r5, 0x0002A7D4; +CHECKREG r6, 0x000A000D; +CHECKREG r7, 0x0009B550; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; + R0.H = A1 , A0 += R1.L * R0.L; +R1 = A1.w; + R2.H = A1 , A0 = R2.H * R3.L; +R3 = A1.w; + R4.H = A1 , A0 = R4.H * R5.H; +R5 = A1.w; + R6.H = A1 , A0 += R6.L * R7.H; +R7 = A1.w; +CHECKREG r0, 0x000A5ABD; +CHECKREG r1, 0x0009B550; +CHECKREG r2, 0x000A5679; +CHECKREG r3, 0x0009B550; +CHECKREG r4, 0x000A4569; +CHECKREG r5, 0x0009B550; +CHECKREG r6, 0x000A000D; +CHECKREG r7, 0x0009B550; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R4.H = ( A1 += R1.L * R0.L ) (M), A0 = R1.L * R0.L; +R5 = A1.w; +R6.H = ( A1 = R2.L * R3.H ) (M), A0 += R2.H * R3.L; +R7 = A1.w; +R0.H = ( A1 = R4.H * R5.L ) (M), A0 = R4.H * R5.H; +R1 = A1.w; +R2.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H; +R3 = A1.w; +CHECKREG r0, 0xFFB35ABD; +CHECKREG r1, 0xFFB294B9; +CHECKREG r2, 0x00005679; +CHECKREG r3, 0x00000004; +CHECKREG r4, 0xFF9B4569; +CHECKREG r5, 0xFF9AC43B; +CHECKREG r6, 0x0002000D; + +CHECKREG r7, 0x000206D6; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xc1845679; +imm32 r3, 0x1c080007; +imm32 r4, 0xe1cc8569; +imm32 r5, 0x121c080b; +imm32 r6, 0x7001008d; +imm32 r7, 0x678e1008; +R6.H = ( A1 += R1.L * R0.L ) (M); +R7 = A1.w; +R2.H = ( A1 = R2.L * R3.H ) (M); +R3 = A1.w; +R0.H = ( A1 += R4.H * R5.L ) (M); +R1 = A1.w; +R4.H = ( A1 = R6.H * R7.H ) (M); +R5 = A1.w; +CHECKREG r0, 0x08855ABD; +CHECKREG r1, 0x0885038C; +CHECKREG r2, 0x09785679; +CHECKREG r3, 0x0977EFC8; +CHECKREG r4, 0xFF918569; +CHECKREG r5, 0xFF913021; +CHECKREG r6, 0xFF91008D; +CHECKREG r7, 0xFF910EEF; + +imm32 r0, 0x03545abd; +imm32 r1, 0xa0bcfec7; +imm32 r2, 0xa1045679; +imm32 r3, 0x00000007; +imm32 r4, 0xefbc0569; +imm32 r5, 0x1235100b; +imm32 r6, 0x000c020d; +imm32 r7, 0x678e003f; +R4.H = ( A1 -= R1.L * R0.L ) (M), A0 -= R1.L * R0.L; +R5 = A1.w; +R6.H = ( A1 -= R2.L * R3.H ) (M), A0 += R2.H * R3.L; +R7 = A1.w; +R0.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H; +R1 = A1.w; +R2.H = ( A1 -= R6.H * R7.H ) (M), A0 -= R6.L * R7.H; +R3 = A1.w; +CHECKREG r0, 0x00005ABD; +CHECKREG r1, 0x00002136; +CHECKREG r2, 0x00005679; +CHECKREG r3, 0x00002136; +CHECKREG r4, 0x00000569; +CHECKREG r5, 0x00002136; +CHECKREG r6, 0x0000020D; +CHECKREG r7, 0x00002136; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xc1845679; +imm32 r3, 0x1c080007; +imm32 r4, 0xe1cc8569; +imm32 r5, 0x121c080b; +imm32 r6, 0x7001008d; +imm32 r7, 0x678e1008; +R6.H = ( A1 -= R1.L * R0.L ) (M); +R7 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M); +R3 = A1.w; +R0.H = ( A1 -= R4.H * R5.L ) (M); +R1 = A1.w; +R4.H = ( A1 -= R6.H * R7.H ) (M); +R5 = A1.w; +CHECKREG r0, 0xF7EA5ABD; +CHECKREG r1, 0xF7EA0EBF; +CHECKREG r2, 0xF6F75679; +CHECKREG r3, 0xF6F72283; +CHECKREG r4, 0xF7EA8569; +CHECKREG r5, 0xF7E9DE9E; +CHECKREG r6, 0x006F008D; +CHECKREG r7, 0x006F124B; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_s.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_s.s new file mode 100644 index 0000000..1059673 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_s.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_s/c_dsp32mac_dr_a1_s.dsp +// Spec Reference: dsp32mac dr_a1 s (scale by 2 signed fraction with round) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbabcfec7; +imm32 r2, 0xc1a48679; +imm32 r3, 0xd00a9007; +imm32 r4, 0xefbca569; +imm32 r5, 0xcd355a0b; +imm32 r6, 0xe00c80ad; +imm32 r7, 0xf78e900a; +R0.H = ( A1 -= R1.L * R0.L ), A0 += R1.L * R0.L (S2RND); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ), A0 -= R2.H * R3.L (S2RND); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ), A0 = R4.H * R5.H (S2RND); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ), A0 -= R6.L * R7.H (S2RND); +R7 = A1.w; +CHECKREG r0, 0x01BC5ABD; +CHECKREG r1, 0x00DDE22A; +CHECKREG r2, 0x5CCE8679; +CHECKREG r3, 0x2E67039E; +CHECKREG r4, 0xE91EA569; +CHECKREG r5, 0xF48ECA28; +CHECKREG r6, 0xED5580AD; +CHECKREG r7, 0xF6AA7F78; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0x63bb8abd; +imm32 r1, 0xbdbcfec7; +imm32 r2, 0xab245679; +imm32 r3, 0xb0b69007; +imm32 r4, 0xcfbb4569; +imm32 r5, 0xd235b00b; +imm32 r6, 0xe00cab0d; +imm32 r7, 0x678e70bf; +R0.H = ( A1 += R1.L * R0.L ) (S2RND); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (S2RND); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ) (S2RND); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (S2RND); +R7 = A1.w; +CHECKREG r0, 0xEF928ABD; +CHECKREG r1, 0xF7C93D4E; +CHECKREG r2, 0x5AB45679; +CHECKREG r3, 0x2D59E942; +CHECKREG r4, 0x7FFF4569; +CHECKREG r5, 0x4B80E354; +CHECKREG r6, 0xCC4CAB0D; +CHECKREG r7, 0xE6263550; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0x5c54babd; +imm32 r1, 0x6dccdec7; +imm32 r2, 0xc12ce679; +imm32 r3, 0x8c06c007; +imm32 r4, 0x9fcc4c69; +imm32 r5, 0xa23c90cb; +imm32 r6, 0xb00cc00c; +imm32 r7, 0xc78eac0f; + R0.H = A1 , A0 -= R1.L * R0.L (S2RND); +R1 = A1.w; + R2.H = A1 , A0 += R2.H * R3.L (S2RND); +R3 = A1.w; + R4.H = A1 , A0 = R4.H * R5.H (S2RND); +R5 = A1.w; + R6.H = A1 , A0 += R6.L * R7.H (S2RND); +R7 = A1.w; +CHECKREG r0, 0xCC4CBABD; +CHECKREG r1, 0xE6263550; +CHECKREG r2, 0xCC4CE679; +CHECKREG r3, 0xE6263550; +CHECKREG r4, 0xCC4C4C69; +CHECKREG r5, 0xE6263550; +CHECKREG r6, 0xCC4CC00C; +CHECKREG r7, 0xE6263550; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x3d545abd; +imm32 r1, 0x5ddcfec7; +imm32 r2, 0x712d5679; +imm32 r3, 0x9006d007; +imm32 r4, 0xafbc4d69; +imm32 r5, 0xd23590db; +imm32 r6, 0xd00ca00d; +imm32 r7, 0x6d8ed00f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (S2RND); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ) (M), A0 -= R2.H * R3.L (S2RND); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (S2RND); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (S2RND); +R7 = A1.w; +CHECKREG r0, 0xFF225ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x614C5679; +CHECKREG r3, 0x30A616D6; +CHECKREG r4, 0x06764D69; +CHECKREG r5, 0x033B2CAA; +CHECKREG r6, 0xDD6BA00D; +CHECKREG r7, 0xEEB5AF52; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83e45abd; +imm32 r1, 0xe8befec7; +imm32 r2, 0xce84e679; +imm32 r3, 0x1ce80e07; +imm32 r4, 0xe1ce85e9; +imm32 r5, 0x921ce80e; +imm32 r6, 0x79019e8d; +imm32 r7, 0x679e90e8; +R0.H = ( A1 += R1.L * R0.L ) (M,S2RND); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ) (M,S2RND); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ) (M,S2RND); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (M,S2RND); +R7 = A1.w; +CHECKREG r0, 0xDC8D5ABD; +CHECKREG r1, 0xEE46BE3D; +CHECKREG r2, 0xFA3CE679; +CHECKREG r3, 0xFD1E19A8; +CHECKREG r4, 0xC37E85E9; +CHECKREG r5, 0xE1BF22EC; +CHECKREG r6, 0x80009E8D; +CHECKREG r7, 0xB0C50D4E; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_t.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_t.s new file mode 100644 index 0000000..7dc3925 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_t.s @@ -0,0 +1,274 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_t/c_dsp32mac_dr_a1_t.dsp +// Spec Reference: dsp32mac dr a1 t (truncation) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbdbcfec7; +imm32 r2, 0xc1248679; +imm32 r3, 0xd0069007; +imm32 r4, 0xefbc4569; +imm32 r5, 0xcd35500b; +imm32 r6, 0xe00c800d; +imm32 r7, 0xf78e900f; +R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (T); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (T); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (T); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (T); +R7 = A1.w; +CHECKREG r0, 0xFF225ABD; +CHECKREG r1, 0xFF221DD6; +CHECKREG r2, 0x2D8C8679; +CHECKREG r3, 0x2D8CEDAC; +CHECKREG r4, 0xF5D44569; +CHECKREG r5, 0xF5D41A28; +CHECKREG r6, 0x021B800D; +CHECKREG r7, 0x021BB550; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x63548abd; +imm32 r1, 0x7dbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0xb0069007; +imm32 r4, 0xcfbc4569; +imm32 r5, 0xd235c00b; +imm32 r6, 0xe00ca00d; +imm32 r7, 0x678e700f; +R0.H = ( A1 = R1.L * R0.L ) (T); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (T); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (T); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (T); +R7 = A1.w; +CHECKREG r0, 0x011E8ABD; +CHECKREG r1, 0x011EBDD6; +CHECKREG r2, 0xCB175679; +CHECKREG r3, 0xCB172B82; +CHECKREG r4, 0x181D4569; +CHECKREG r5, 0x181DDA28; +CHECKREG r6, 0xE626A00D; +CHECKREG r7, 0xE6263550; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x6dbcdec7; +imm32 r2, 0x7124e679; +imm32 r3, 0x80067007; +imm32 r4, 0x9fbc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb00c300d; +imm32 r7, 0xc78ea00f; + R0.H = A1 , A0 = R1.L * R0.L (T); +R1 = A1.w; + R2.H = A1 , A0 = R2.H * R3.L (T); +R3 = A1.w; + R4.H = A1 , A0 = R4.H * R5.H (T); +R5 = A1.w; + R6.H = A1 , A0 += R6.L * R7.H (T); +R7 = A1.w; +CHECKREG r0, 0xE626BABD; +CHECKREG r1, 0xE6263550; +CHECKREG r2, 0xE626E679; +CHECKREG r3, 0xE6263550; +CHECKREG r4, 0xE6264569; +CHECKREG r5, 0xE6263550; +CHECKREG r6, 0xE626300D; +CHECKREG r7, 0xE6263550; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (T); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M), A0 = R2.H * R3.L (T); +R3 = A0.w; +R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (T); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H (T); +R7 = A0.w; +CHECKREG r0, 0xFF915ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x30375679; +CHECKREG r3, 0x00062FF8; +CHECKREG r4, 0x030D4569; +CHECKREG r5, 0x030D72D5; +CHECKREG r6, 0xE621A00D; +CHECKREG r7, 0xCF173844; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xc1845679; +imm32 r3, 0x1c080007; +imm32 r4, 0xe1cc8569; +imm32 r5, 0x921c080b; +imm32 r6, 0x7901908d; +imm32 r7, 0x679e9008; +R0.H = ( A1 += R1.L * R0.L ) (M,T); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ) (M,T); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ) (M,T); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M,T); +R7 = A1.w; +CHECKREG r0, 0xE5B25ABD; +CHECKREG r1, 0xE5B26993; +CHECKREG r2, 0x09775679; +CHECKREG r3, 0x0977EFC8; +CHECKREG r4, 0x08858569; +CHECKREG r5, 0x0885038C; +CHECKREG r6, 0x30FA908D; +CHECKREG r7, 0x30FA159E; + +imm32 r0, 0x03545abd; +imm32 r1, 0xb0bcfec7; +imm32 r2, 0xc1048679; +imm32 r3, 0xd0009007; +imm32 r4, 0xefbc0569; +imm32 r5, 0xcd35510b; +imm32 r6, 0xe00c802d; +imm32 r7, 0xf78e9003; +R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L (T); +R1 = A1.w; +R2.H = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L (T); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (T); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ), A0 -= R6.L * R7.H (T); +R7 = A1.w; +CHECKREG r0, 0x31D75ABD; +CHECKREG r1, 0x31D7F7C8; +CHECKREG r2, 0x2D928679; +CHECKREG r3, 0x2D92A000; +CHECKREG r4, 0x37DF0569; +CHECKREG r5, 0x37DF0DD8; +CHECKREG r6, 0x39FA802D; +CHECKREG r7, 0x39FAC328; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x63548abd; +imm32 r1, 0x7dbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0xb0069007; +imm32 r4, 0xcfbc4569; +imm32 r5, 0xd235c00b; +imm32 r6, 0xe00ca00d; +imm32 r7, 0x678e700f; +R0.H = ( A1 -= R1.L * R0.L ) (T); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (T); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (T); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (T); +R7 = A1.w; +CHECKREG r0, 0x38DC8ABD; +CHECKREG r1, 0x38DC0552; +CHECKREG r2, 0x6EE35679; +CHECKREG r3, 0x6EE397A6; +CHECKREG r4, 0x56C54569; +CHECKREG r5, 0x56C5BD7E; +CHECKREG r6, 0x709FA00D; +CHECKREG r7, 0x709F882E; + +// The result accumulated in A , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x6dbcdec7; +imm32 r2, 0x7124e679; +imm32 r3, 0x80067007; +imm32 r4, 0x9fbc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb00c300d; +imm32 r7, 0xc78ea00f; + R0.H = A1 , A0 -= R1.L * R0.L (T); +R1 = A1.w; + R2.H = A1 , A0 -= R2.H * R3.L (T); +R3 = A1.w; + R4.H = A1 , A0 -= R4.H * R5.H (T); +R5 = A1.w; + R6.H = A1 , A0 -= R6.L * R7.H (T); +R7 = A1.w; +CHECKREG r0, 0x709FBABD; +CHECKREG r1, 0x709F882E; +CHECKREG r2, 0x709FE679; +CHECKREG r3, 0x709F882E; +CHECKREG r4, 0x709F4569; +CHECKREG r5, 0x709F882E; +CHECKREG r6, 0x709F300D; +CHECKREG r7, 0x709F882E; + +// The result accumulated in A , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +R0.H = ( A1 -= R1.L * R0.L ) (M), A0 += R1.L * R0.L (T); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M), A0 -= R2.H * R3.L (T); +R3 = A0.w; +R4.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H (T); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (T); +R7 = A0.w; +CHECKREG r0, 0x710E5ABD; +CHECKREG r1, 0x710E7943; +CHECKREG r2, 0x40685679; +CHECKREG r3, 0x1ED0EB56; +CHECKREG r4, 0x133E4569; +CHECKREG r5, 0x133EAF81; +CHECKREG r6, 0xF960A00D; +CHECKREG r7, 0x4FB9B312; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x83545abd; +imm32 r1, 0xa8bcfec7; +imm32 r2, 0xc1845679; +imm32 r3, 0x1c080007; +imm32 r4, 0xe1cc8569; +imm32 r5, 0x921c080b; +imm32 r6, 0x7901908d; +imm32 r7, 0x679e9008; +R0.H = ( A1 -= R1.L * R0.L ) (M,T); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M,T); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (M,T); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (M,T); +R7 = A1.w; +CHECKREG r0, 0xF9CE5ABD; +CHECKREG r1, 0xF9CEFB3E; +CHECKREG r2, 0xF0575679; +CHECKREG r3, 0xF0570B76; +CHECKREG r4, 0xF1498569; +CHECKREG r5, 0xF149F7B2; +CHECKREG r6, 0xC04F908D; +CHECKREG r7, 0xC04FE214; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_tu.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_tu.s new file mode 100644 index 0000000..259def7 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_tu.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_tu/c_dsp32mac_dr_a1_tu.dsp +// Spec Reference: dsp32mac dr_a1 tu (truncate signed fraction) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbdbcfec7; +imm32 r2, 0xc1248679; +imm32 r3, 0xd0069007; +imm32 r4, 0xefbc4569; +imm32 r5, 0xcd35500b; +imm32 r6, 0xe00c800d; +imm32 r7, 0xf78e900f; +R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (TFU); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (TFU); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (TFU); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (TFU); +R7 = A1.w; +CHECKREG r0, 0x5A4E5ABD; +CHECKREG r1, 0x5A4E0EEB; +CHECKREG r2, 0x00008679; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x4AF54569; +CHECKREG r5, 0x4AF50D14; +CHECKREG r6, 0xFFFF800D; +CHECKREG r7, 0x239CE7BC; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0x63548abd; +imm32 r1, 0x7dbcfec7; +imm32 r2, 0xC5885679; +imm32 r3, 0xC5880000; +imm32 r4, 0xcfbc4569; +imm32 r5, 0xd235c00b; +imm32 r6, 0xe00ca00d; +imm32 r7, 0x678e700f; +R0.H = ( A1 = R1.L * R0.L ) (TFU); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (TFU); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (TFU); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (TFU); +R7 = A1.w; +CHECKREG r0, 0x8A138ABD; +CHECKREG r1, 0x8A135EEB; +CHECKREG r2, 0xCCCC5679; +CHECKREG r3, 0xCCCC6C33; +CHECKREG r4, 0x30F64569; +CHECKREG r5, 0x30F67F1F; +CHECKREG r6, 0x5AA1A00D; +CHECKREG r7, 0x5AA11AA8; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0x5354babd; +imm32 r1, 0x6dbcdec7; +imm32 r2, 0x7124e679; +imm32 r3, 0x80067007; +imm32 r4, 0x9fbc4569; +imm32 r5, 0xa235900b; +imm32 r6, 0xb00c300d; +imm32 r7, 0xc78ea00f; + R0.H = A1 , A0 -= R1.L * R0.L (TFU); +R1 = A1.w; + R2.H = A1 , A0 += R2.H * R3.L (TFU); +R3 = A1.w; + R4.H = A1 , A0 -= R4.H * R5.H (TFU); +R5 = A1.w; + R6.H = A1 , A0 = R6.L * R7.H (TFU); +R7 = A1.w; +CHECKREG r0, 0x5AA1BABD; +CHECKREG r1, 0x5AA11AA8; +CHECKREG r2, 0x5AA1E679; +CHECKREG r3, 0x5AA11AA8; +CHECKREG r4, 0x5AA14569; +CHECKREG r5, 0x5AA11AA8; +CHECKREG r6, 0x5AA1300D; +CHECKREG r7, 0x5AA11AA8; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0x33545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71245679; +imm32 r3, 0x90060007; +imm32 r4, 0xafbc4569; +imm32 r5, 0xd235900b; +imm32 r6, 0xc00ca00d; +imm32 r7, 0x678ed00f; +R0.H = ( A1 = R1.L * R0.L ) (M), A0 -= R1.L * R0.L (TFU); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (TFU); +R3 = A1.w; +R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (TFU); +R5 = A1.w; +R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (TFU); +R7 = A1.w; +CHECKREG r0, 0xFF915ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x30375679; +CHECKREG r3, 0x303725C1; +CHECKREG r4, 0x5D604569; +CHECKREG r5, 0x5D60D8AD; +CHECKREG r6, 0x4382A00D; +CHECKREG r7, 0x43823355; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0x92005ABD; +imm32 r1, 0x09300000; +imm32 r2, 0x56749679; +imm32 r3, 0x30A95000; +imm32 r4, 0xa0009669; +imm32 r5, 0x01000970; +imm32 r6, 0xdf45609D; +imm32 r7, 0x12345679; +R0.H = ( A1 += R1.L * R0.L ) (M,TFU); +R1 = A1.w; +R2.H = ( A1 -= R2.L * R3.H ) (M,TFU); +R3 = A1.w; +R4.H = ( A1 = R4.H * R5.L ) (M,TFU); +R5 = A1.w; +R6.H = ( A1 -= R6.H * R7.H ) (M,TFU); +R7 = A1.w; +CHECKREG r0, 0x43825ABD; +CHECKREG r1, 0x43823355; +CHECKREG r2, 0x57919679; +CHECKREG r3, 0x57912D74; +CHECKREG r4, 0xFC769669; +CHECKREG r5, 0xFC760000; +CHECKREG r6, 0xFEC9609D; +CHECKREG r7, 0xFEC9CBFC; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_u.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_u.s new file mode 100644 index 0000000..1f78e34 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_u.s @@ -0,0 +1,170 @@ +//Original:/testcases/core/c_dsp32mac_dr_a1_u/c_dsp32mac_dr_a1_u.dsp +// Spec Reference: dsp32mac dr_a1 u (unsigned fraction & unsigned int) +# mach: bfin + +.include "testutils.inc" + start + + + + +A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0xa3545abd; +imm32 r1, 0xbabcfec7; +imm32 r2, 0xc1a48679; +imm32 r3, 0xd00a9007; +imm32 r4, 0xefbca569; +imm32 r5, 0xcd355a0b; +imm32 r6, 0xe00c80ad; +imm32 r7, 0xf78e900a; +R0.H = ( A1 = R6.L * R7.L ), A0 += R6.L * R7.L (FU); +R1 = A1.w; +R2.H = ( A1 = R3.L * R4.H ), A0 = R3.H * R4.L (FU); +R3 = A1.w; +R4.H = ( A1 += R2.H * R5.L ), A0 = R2.H * R5.H (FU); +R5 = A1.w; +R6.H = ( A1 += R0.H * R1.H ), A0 += R0.L * R1.H (FU); +R7 = A1.w; +CHECKREG r0, 0x48665ABD; +CHECKREG r1, 0x486656C2; +CHECKREG r2, 0x86E08679; +CHECKREG r3, 0x86E04E24; +CHECKREG r4, 0xB651A569; +CHECKREG r5, 0xB650D9C4; +CHECKREG r6, 0xCACA80AD; +CHECKREG r7, 0xCACA6268; + +imm32 r0, 0x03545abd; +imm32 r1, 0x1abcfec7; +imm32 r2, 0xc2a48679; +imm32 r3, 0x300a9007; +imm32 r4, 0x54bca569; +imm32 r5, 0x6d355a0b; +imm32 r6, 0x700c80ad; +imm32 r7, 0x878e900a; +R0.H = ( A1 -= R6.L * R7.L ), A0 += R6.L * R7.L (FU); +R1 = A1.w; +R2.H = ( A1 -= R3.L * R4.H ), A0 = R3.H * R4.L (FU); +R3 = A1.w; +R4.H = ( A1 += R2.H * R5.L ), A0 -= R2.H * R5.H (FU); +R5 = A1.w; +R6.H = ( A1 -= R0.H * R1.H ), A0 += R0.L * R1.H (FU); +R7 = A1.w; +CHECKREG r0, 0x82645ABD; +CHECKREG r1, 0x82640BA6; +CHECKREG r2, 0x52B88679; +CHECKREG r3, 0x52B7FA82; +CHECKREG r4, 0x6FD0A569; +CHECKREG r5, 0x6FD0386A; +CHECKREG r6, 0x2D6780AD; +CHECKREG r7, 0x2D66815A; + +// The result accumulated in A1, and stored to a reg half (MNOP) +imm32 r0, 0xb3548abd; +imm32 r1, 0x7bbcfec7; +imm32 r2, 0xa1b45679; +imm32 r3, 0xb00b9007; +imm32 r4, 0xcfbcb569; +imm32 r5, 0xd235c00b; +imm32 r6, 0xe00cabbd; +imm32 r7, 0x678e700b; +R0.H = ( A1 = R1.L * R0.L ) (FU); +R1 = A1.w; +R2.H = ( A1 = R2.L * R6.H ) (FU); +R3 = A1.w; +R4.H = ( A1 += R3.H * R5.L ) (FU); +R5 = A1.w; +R6.H = ( A1 = R4.H * R7.H ) (FU); +R7 = A1.w; +CHECKREG r0, 0x8A138ABD; +CHECKREG r1, 0x8A135EEB; +CHECKREG r2, 0x4BAE5679; +CHECKREG r3, 0x4BADEDAC; +CHECKREG r4, 0x8473B569; +CHECKREG r5, 0x8472EE1B; +CHECKREG r6, 0x3594ABBD; +CHECKREG r7, 0x3593BCCA; + +// The result accumulated in A1 , and stored to a reg half (MNOP) +imm32 r0, 0xc354babd; +imm32 r1, 0x6cbcdec7; +imm32 r2, 0x71c4e679; +imm32 r3, 0x800c7007; +imm32 r4, 0x9fbcc569; +imm32 r5, 0xa2359c0b; +imm32 r6, 0xb00c30cd; +imm32 r7, 0xc78ea00c; + R0.H = A1 , A0 = R1.L * R0.L (FU); +R1 = A1.w; + R2.H = A1 , A0 = R2.H * R3.L (FU); +R3 = A1.w; + R4.H = A1 , A0 = R4.H * R5.H (FU); +R5 = A1.w; + R6.H = A1 , A0 = R6.L * R7.H (FU); +R7 = A1.w; +CHECKREG r0, 0x3594BABD; +CHECKREG r1, 0x3593BCCA; +CHECKREG r2, 0x3594E679; +CHECKREG r3, 0x3593BCCA; +CHECKREG r4, 0x3594C569; +CHECKREG r5, 0x3593BCCA; +CHECKREG r6, 0x359430CD; +CHECKREG r7, 0x3593BCCA; + +// The result accumulated in A1 , and stored to a reg half +imm32 r0, 0xd3545abd; +imm32 r1, 0x5dbcfec7; +imm32 r2, 0x71d45679; +imm32 r3, 0x900d0007; +imm32 r4, 0xafbcd569; +imm32 r5, 0xd2359d0b; +imm32 r6, 0xc00ca0dd; +imm32 r7, 0x678ed00d; +R0.H = ( A1 = R1.L * R2.L ) (M), A0 += R1.L * R2.L (FU); +R1 = A1.w; +R2.H = ( A1 = R3.L * R4.H ) (M), A0 = R3.H * R4.L (FU); +R3 = A1.w; +R4.H = ( A1 = R5.H * R6.L ) (M), A0 += R5.H * R6.H (FU); +R5 = A1.w; +R6.H = ( A1 += R7.H * R0.H ) (M), A0 += R7.L * R0.H (FU); +R7 = A1.w; +CHECKREG r0, 0xFF965ABD; +CHECKREG r1, 0xFF96460F; +CHECKREG r2, 0x00055679; +CHECKREG r3, 0x0004CE24; +CHECKREG r4, 0xE33AD569; +CHECKREG r5, 0xE33997C1; +CHECKREG r6, 0x4A9DA0DD; +CHECKREG r7, 0x4A9CB6F5; + +// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) +imm32 r0, 0xe3545abd; +imm32 r1, 0xaebcfec7; +imm32 r2, 0xc1e45679; +imm32 r3, 0x1c0e0007; +imm32 r4, 0xe1cce569; +imm32 r5, 0x921c0e0b; +imm32 r6, 0x790190ed; +imm32 r7, 0x679e900e; +R0.H = ( A1 = R1.L * R0.L ) (M,FU); +R1 = A1.w; +R2.H = ( A1 += R2.L * R3.H ) (M,FU); +R3 = A1.w; +R4.H = ( A1 += R4.H * R5.L ) (M,FU); +R5 = A1.w; +R6.H = ( A1 = R6.H * R7.H ) (M,FU); +R7 = A1.w; +CHECKREG r0, 0xFF915ABD; +CHECKREG r1, 0xFF910EEB; +CHECKREG r2, 0x090B5679; +CHECKREG r3, 0x090B0589; +CHECKREG r4, 0x0763E569; +CHECKREG r5, 0x0762E14D; +CHECKREG r6, 0x30FA90ED; +CHECKREG r7, 0x30FA159E; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s new file mode 100644 index 0000000..700cbdf --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s @@ -0,0 +1,157 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0/c_dsp32mac_dr_a1a0.dsp +// Spec Reference: dsp32mac dr_a1a0 +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + R0 = 0; + ASTAT = R0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x13545abd; + imm32 r1, 0xb2bcfec7; + imm32 r2, 0xc1348679; + imm32 r3, 0xd0049007; + imm32 r4, 0x12efbc5569; + imm32 r5, 0xcd35560b; + imm32 r6, 0xe00c807d; + imm32 r7, 0xf78e9008; + A1 = A0 = 0; + R6.H = (A1 += R0.L * R0.L), R6.L = (A0 = R0.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 += R2.L * R3.L), R1.L = (A0 -= R2.H * R3.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 -= R4.L * R5.L), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R0.L * R7.L), R3.L = (A0 += R0.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0x13545ABD; + CHECKREG r1, 0x7FFF0964; + CHECKREG r2, 0x71380FD8; + CHECKREG r3, 0x21D909DC; + CHECKREG r4, 0x21D8C27A; + CHECKREG r5, 0x09DB89BE; + CHECKREG r6, 0x40534053; + CHECKREG r7, 0xF78E9008; + CHECKREG p1, 0x4052DF12; + CHECKREG p2, 0x4052DF12; + CHECKREG p3, 0xAAA259B0; + CHECKREG p4, 0x0963CE3A; + CHECKREG p5, 0x713876AA; + CHECKREG fp, 0x0FD82A12; + + imm32 r0, 0x13545abd; + imm32 r1, 0x22bcfec7; + imm32 r2, 0x43348679; + imm32 r3, 0x50049007; + imm32 r4, 0x6fbc5569; + imm32 r5, 0x7d35560b; + imm32 r6, 0x800c807d; + imm32 r7, 0xf98e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.L * R0.H), R0.L = (A0 = R1.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R6.H = (A1 += R2.L * R2.H), R6.L = (A0 -= R2.H * R2.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 -= R4.L * R5.H), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R3.L * R7.H), R3.L = (A0 -= R3.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0xFFD1FF22; + CHECKREG r1, 0x22BCFEC7; + CHECKREG r2, 0x80007FFF; + CHECKREG r3, 0x80007FFF; + CHECKREG r4, 0x721A320A; + CHECKREG r5, 0xA6989CC2; + CHECKREG r6, 0xC0033EF0; + CHECKREG r7, 0xF98E9008; + CHECKREG p1, 0xFFD0BC98; + CHECKREG p2, 0xFF221DD6; + CHECKREG p3, 0xC002B3C0; + CHECKREG p4, 0x3EF026AE; + CHECKREG p5, 0x6C76CC46; + CHECKREG fp, 0xAC3C0286; + + imm32 r0, 0x13545abd; + imm32 r1, 0x42bcfec7; + imm32 r2, 0x51348679; + imm32 r3, 0x60049007; + imm32 r4, 0x7fbc5569; + imm32 r5, 0x8d35560b; + imm32 r6, 0x900c807d; + imm32 r7, 0xa78e9008; + A1 = A0 = 0; + R0.H = (A1 -= R1.H * R0.L), R0.L = (A0 = R1.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 += R2.H * R3.L), R1.L = (A0 -= R2.H * R3.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 = R4.H * R5.L), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 -= R6.H * R7.L), R3.L = (A0 += R6.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0xD0B1FF22; + CHECKREG r1, 0x89A8462B; + CHECKREG r2, 0x55DDD39D; + CHECKREG r3, 0xF3EF2BB9; + CHECKREG r4, 0xF3EEC968; + CHECKREG r5, 0x2BB8C982; + CHECKREG r6, 0x900C807D; + CHECKREG r7, 0xA78E9008; + CHECKREG p1, 0xD0B14668; + CHECKREG p2, 0xFF221DD6; + CHECKREG p3, 0x89A83740; + CHECKREG p4, 0x462B2CFE; + CHECKREG p5, 0x55DD4A28; + CHECKREG fp, 0xD39D28D6; + + imm32 r0, 0x03545abd; + imm32 r1, 0xb3bcfec7; + imm32 r2, 0x24348679; + imm32 r3, 0x60049007; + imm32 r4, 0x7fbc5569; + imm32 r5, 0x9d35560b; + imm32 r6, 0xa00c807d; + imm32 r7, 0x078e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.H * R0.H), R0.L = (A0 -= R1.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 -= R2.H * R3.H), R1.L = (A0 = R2.H * R3.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 = R4.H * R5.H), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R6.H * R7.H), R3.L = (A0 -= R6.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0xFE0400DE; + CHECKREG r1, 0xE2DCE054; + CHECKREG r2, 0x9D698000; + CHECKREG r3, 0x97C08545; + CHECKREG r4, 0x97BFB128; + CHECKREG r5, 0x85449604; + CHECKREG r6, 0xA00C807D; + CHECKREG r7, 0x078E9008; + CHECKREG p1, 0xFE045B60; + CHECKREG p2, 0x00DDE22A; + CHECKREG p3, 0xE2DC39C0; + CHECKREG p4, 0xE0547AD8; + CHECKREG p5, 0x9D697BD8; + CHECKREG fp, 0x7DBDF6B0; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s new file mode 100644 index 0000000..8d4232e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s @@ -0,0 +1,157 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_iutsh/c_dsp32mac_dr_a1a0_iutsh.dsp +// Spec Reference: dsp32mac dr_a1a0 iutsh +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + R0 = 0; + ASTAT = R0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x13545abd; + imm32 r1, 0xb2bcfec7; + imm32 r2, 0xc1348679; + imm32 r3, 0xd0049007; + imm32 r4, 0x12efbc556; + imm32 r5, 0xcd35560b; + imm32 r6, 0xe00c807d; + imm32 r7, 0xf78e9008; + A1 = A0 = 0; + R6.H = (A1 += R0.L * R0.L), R6.L = (A0 = R0.L * R0.L) (IS); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 += R2.L * R3.L), R1.L = (A0 -= R2.H * R3.L) (FU); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 = R4.L * R5.L) (M), R2.L = (A0 += R4.H * R5.H) (T); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R0.L * R7.L), R3.L = (A0 += R0.L * R7.H) (S2RND); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0x13545ABD; + CHECKREG r1, 0x6BD10000; + CHECKREG r2, 0xEC48ED5B; + CHECKREG r3, 0x8000CEBE; + CHECKREG r4, 0x9CE8AA82; + CHECKREG r5, 0xE75ED19A; + CHECKREG r6, 0x7FFF7FFF; + CHECKREG r7, 0xF78E9008; + CHECKREG p1, 0x20296F89; + CHECKREG p2, 0x20296F89; + CHECKREG p3, 0x6BD12CD8; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0xEC485EB2; + CHECKREG fp, 0xED5B71EE; + + imm32 r0, 0x13545abd; + imm32 r1, 0x22bcfec7; + imm32 r2, 0x43348679; + imm32 r3, 0x50049007; + imm32 r4, 0x6fbc5569; + imm32 r5, 0x7d35560b; + imm32 r6, 0x800c807d; + imm32 r7, 0xf98e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.L * R0.H), R0.L = (A0 = R1.L * R0.L) (IU); + P1 = A1.w; + P2 = A0.w; + R6.H = (A1 += R2.L * R2.H), R6.L = (A0 = R2.H * R2.L) (TFU); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 -= R4.L * R5.H), R2.L = (A0 += R4.H * R5.H) (ISS2); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R3.L * R7.H), R3.L = (A0 -= R3.L * R7.H) (IH); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0xFFFFFFFF; + CHECKREG r1, 0x22BCFEC7; + CHECKREG r2, 0x7FFF7FFF; + CHECKREG r3, 0x0F955721; + CHECKREG r4, 0x0F951905; + CHECKREG r5, 0x5721369E; + CHECKREG r6, 0x3689234C; + CHECKREG r7, 0xF98E9008; + CHECKREG p1, 0x133C5E4C; + CHECKREG p2, 0x5A4E0EEB; + CHECKREG p3, 0x368959E0; + CHECKREG p4, 0x234CFB94; + CHECKREG p5, 0x0CC36623; + CHECKREG fp, 0x59F2E980; + + imm32 r0, 0x13545abd; + imm32 r1, 0x42bcfec7; + imm32 r2, 0x51348679; + imm32 r3, 0x60049007; + imm32 r4, 0x7fbc5569; + imm32 r5, 0x8d35560b; + imm32 r6, 0x900c807d; + imm32 r7, 0xa78e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.H * R0.L), R0.L = (A0 = R1.L * R0.L) (IS); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 += R2.H * R3.L) (M), R1.L = (A0 -= R2.H * R3.L) (IU); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 = R4.H * R5.L), R2.L = (A0 += R4.H * R5.H) (ISS2); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 -= R6.H * R7.L) (M), R3.L = (A0 += R6.L * R7.H) (IH); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0x7FFF8000; + CHECKREG r1, 0x7FFFFFFF; + CHECKREG r2, 0x7FFF8000; + CHECKREG r3, 0x69EBC4A8; + CHECKREG r4, 0x69EB64B4; + CHECKREG r5, 0xC4A864C1; + CHECKREG r6, 0x900C807D; + CHECKREG r7, 0xA78E9008; + CHECKREG p1, 0x17A75CCC; + CHECKREG p2, 0xFF910EEB; + CHECKREG p3, 0x4556D538; + CHECKREG p4, 0xD1E1967F; + CHECKREG p5, 0x2AEEA514; + CHECKREG fp, 0x989A946B; + + imm32 r0, 0x03545abd; + imm32 r1, 0xb3bcfec7; + imm32 r2, 0x24348679; + imm32 r3, 0x60049007; + imm32 r4, 0x7fbc5569; + imm32 r5, 0x9d35560b; + imm32 r6, 0xa00c807d; + imm32 r7, 0x078e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.H * R0.H), R0.L = (A0 -= R1.L * R0.L) (FU); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 += R2.H * R3.H), R1.L = (A0 = R2.H * R3.L) (TFU); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 = R4.H * R5.H), R2.L = (A0 += R4.H * R5.H) (IU); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 -= R6.H * R7.H) (M), R3.L = (A0 += R6.L * R7.H) (S2RND); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0x02560000; + CHECKREG r1, 0x0FEA145E; + CHECKREG r2, 0xFFFFFFFF; + CHECKREG r3, 0x7FFF7FFF; + CHECKREG r4, 0x5145A344; + CHECKREG r5, 0x5B485C04; + CHECKREG r6, 0xA00C807D; + CHECKREG r7, 0x078E9008; + CHECKREG p1, 0x02562DB0; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x0FEA3E80; + CHECKREG p4, 0x145E3D6C; + CHECKREG p5, 0x4E70BDEC; + CHECKREG fp, 0x62CEFB58; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s new file mode 100644 index 0000000..75fcc43 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s @@ -0,0 +1,157 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_m/c_dsp32mac_dr_a1a0_m.dsp +// Spec Reference: dsp32mac dr_a1a0 m +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + R0 = 0; + ASTAT = R0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x13545abd; + imm32 r1, 0xb2bcfec7; + imm32 r2, 0xc1348679; + imm32 r3, 0xd0049007; + imm32 r4, 0x12efbc5569; + imm32 r5, 0xcd35560b; + imm32 r6, 0xe00c807d; + imm32 r7, 0xf78e9008; + A1 = A0 = 0; + R6.H = (A1 += R0.L * R0.L) (M), R6.L = (A0 = R0.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 += R2.L * R3.L) (M), R1.L = (A0 -= R2.H * R3.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 -= R4.L * R5.L) (M), R2.L = (A0 -= R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R0.L * R7.L) (M), R3.L = (A0 += R0.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0x13545ABD; + CHECKREG r1, 0xDBCA0964; + CHECKREG r2, 0xBF1502EF; + CHECKREG r3, 0xF222FCF3; + CHECKREG r4, 0xF222613D; + CHECKREG r5, 0xFCF2D20E; + CHECKREG r6, 0x20294053; + CHECKREG r7, 0xF78E9008; + CHECKREG p1, 0x20296F89; + CHECKREG p2, 0x4052DF12; + CHECKREG p3, 0xDBCA2CD8; + CHECKREG p4, 0x0963CE3A; + CHECKREG p5, 0xBF153B55; + CHECKREG fp, 0x02EF7262; + + imm32 r0, 0x13545abd; + imm32 r1, 0x22bcfec7; + imm32 r2, 0x43348679; + imm32 r3, 0x50049007; + imm32 r4, 0x6fbc5569; + imm32 r5, 0x7d35560b; + imm32 r6, 0x800c807d; + imm32 r7, 0xf98e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.L * R0.H) (M), R0.L = (A0 -= R1.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R6.H = (A1 += R2.L * R2.H) (M), R6.L = (A0 = R2.H * R2.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 -= R4.L * R5.H) (M), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R3.L * R7.H) (M), R3.L = (A0 -= R3.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0xFFE800DE; + CHECKREG r1, 0x22BCFEC7; + CHECKREG r2, 0xB63B2D7E; + CHECKREG r3, 0x800027DA; + CHECKREG r4, 0x49141905; + CHECKREG r5, 0x27DA6D3C; + CHECKREG r6, 0xE001C032; + CHECKREG r7, 0xF98E9008; + CHECKREG p1, 0xFFE85E4C; + CHECKREG p2, 0x00DDE22A; + CHECKREG p3, 0xE00159E0; + CHECKREG p4, 0xC031F728; + CHECKREG p5, 0xB63B6623; + CHECKREG fp, 0x2D7DD300; + + imm32 r0, 0x13545abd; + imm32 r1, 0x42bcfec7; + imm32 r2, 0x51348679; + imm32 r3, 0x60049007; + imm32 r4, 0x7fbc5569; + imm32 r5, 0x8d35560b; + imm32 r6, 0x900c807d; + imm32 r7, 0xa78e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.H * R0.L) (M), R0.L = (A0 = R1.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 -= R2.H * R3.L) (M), R1.L = (A0 -= R2.H * R3.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 -= R4.H * R5.L) (M), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R6.H * R7.L) (M), R3.L = (A0 += R6.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0x17A7FF22; + CHECKREG r1, 0xE9F8462B; + CHECKREG r2, 0xBF09D39D; + CHECKREG r3, 0x800C2BB9; + CHECKREG r4, 0x800C7FAC; + CHECKREG r5, 0x2BB8C982; + CHECKREG r6, 0x900C807D; + CHECKREG r7, 0xA78E9008; + CHECKREG p1, 0x17A75CCC; + CHECKREG p2, 0xFF221DD6; + CHECKREG p3, 0xE9F7E460; + CHECKREG p4, 0x462B2CFE; + CHECKREG p5, 0xBF093F4C; + CHECKREG fp, 0xD39D28D6; + + imm32 r0, 0x03545abd; + imm32 r1, 0xb3bcfec7; + imm32 r2, 0x24348679; + imm32 r3, 0x60049007; + imm32 r4, 0x7fbc5569; + imm32 r5, 0x9d35560b; + imm32 r6, 0xa00c807d; + imm32 r7, 0x078e9008; + A1 = A0 = 0; + R0.H = (A1 += R1.H * R0.H) (M), R0.L = (A0 -= R1.L * R0.L); + P1 = A1.w; + P2 = A0.w; + R1.H = (A1 -= R2.H * R3.H) (M), R1.L = (A0 = R2.H * R3.L); + P3 = A1.w; + P4 = A0.w; + R2.H = (A1 = R4.H * R5.H) (M), R2.L = (A0 += R4.H * R5.H); + P5 = A1.w; + FP = A0.w; + R3.H = (A1 += R6.H * R7.H) (M), R3.L = (A0 += R6.L * R7.H); + R4 = A1.w; + R5 = A0.w; + CHECKREG r0, 0xFF0200DE; + CHECKREG r1, 0xF16EE054; + CHECKREG r2, 0x4E718000; + CHECKREG r3, 0x4B9C8000; + CHECKREG r4, 0x4B9BD894; + CHECKREG r5, 0x7637575C; + CHECKREG r6, 0xA00C807D; + CHECKREG r7, 0x078E9008; + CHECKREG p1, 0xFF022DB0; + CHECKREG p2, 0x00DDE22A; + CHECKREG p3, 0xF16E1CE0; + CHECKREG p4, 0xE0547AD8; + CHECKREG p5, 0x4E70BDEC; + CHECKREG fp, 0x7DBDF6B0; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_mix.s b/sim/testsuite/sim/bfin/c_dsp32mac_mix.s new file mode 100644 index 0000000..a5a28c7 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_mix.s @@ -0,0 +1,114 @@ +//Original:/testcases/core/c_dsp32mac_mix/c_dsp32mac_mix.dsp +// Spec Reference: dsp32mac mix +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xab235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246700f; + +A1 = A0 = 0; +A0.L = R0.L; +A0.H = R0.H; + +// test the ROUNDING only on signed fraction T=1 +R0.H = (A1 = R4.L * R5.L), R0.L = (A0 = R4.L * R5.H) (T); +R1.H = (A1 = R4.H * R5.L), R1.L = (A0 = R4.H * R5.H) (T); +R2.H = (A1 = R6.L * R7.L), R2.L = (A0 = R6.H * R7.H) (T); +R3.H = (A1 = R6.L * R7.H), R3.L = (A0 = R6.L * R7.L) (T); +CHECKREG r0, 0x066DF95C; +CHECKREG r1, 0x0E0AF17F; +CHECKREG r2, 0x000B0001; +CHECKREG r3, 0x0001000B; + +// When two results are stored to a single register, they must be rounded +// or truncated and stored to the 2 halves of a single destination reg dst + +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; + +// The result accumulated in A0 and A1, and stored to a reg half +R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; +R3.H = A1 , A0 = R7.H * R6.L (T); +R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L; +A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2); + +CHECKREG r2, 0xFFD15679; +CHECKREG r3, 0xFFD00007; +CHECKREG r4, 0x00074569; +CHECKREG r5, 0x12358000; + +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +// The result accumulated in A0 and A1, and stored to a reg +R5.H = (A1 = R1.L * R0.H), R5.L = (A0 = R1.H * R0.L) (TFU); +R6.H = (A1 = R3.L * R2.H) (M), R6.L = (A0 = R3.H * R2.L) (TFU); +R7.H = (A1 = R1.L * R0.H) (M), R7.L = (A0 = R1.H * R0.L) (IH); // hi-word extraction +CHECKREG r5, 0x133C3D94; +CHECKREG r6, 0x00040002; +CHECKREG r7, 0xFFE8E2D7; + + +// The result accumulated in A0 and A1, and stored to a reg pair +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; + +R3 = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; +R5 = ( A1 = R1.L * R0.H ); +R7 = ( A1 += R1.L * R0.H ) (M), A0 -= R1.H * R0.L; +CHECKREG r2, 0xA1245679; +CHECKREG r3, 0xFFD0BC98; +CHECKREG r4, 0xEFBC4569; +CHECKREG r5, 0xFFD0BC98; +CHECKREG r6, 0x000C000D; +CHECKREG r7, 0xFFB91AE4; +A1 = R1.L * R0.H, R2 = ( A0 = R1.H * R0.L ); +A1 = R1.L * R0.H (M), R6 = ( A0 -= R1.H * R0.L ); +CHECKREG r2, 0xC5AEB798; +CHECKREG r3, 0xFFD0BC98; +CHECKREG r4, 0xEFBC4569; +CHECKREG r5, 0xFFD0BC98; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFFB91AE4; + +imm32 r0, 0x13545abd; +imm32 r1, 0xadbcfec7; +imm32 r2, 0xa1245679; +imm32 r3, 0x00060007; +imm32 r4, 0xefbc4569; +imm32 r5, 0x1235000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x678e000f; +R3 = ( A1 -= R5.L * R4.H ), R2 = ( A0 -= R5.H * R4.L ) (S2RND); +R3 = ( A1 -= R1.L * R0.H ) (M), R2 = ( A0 += R1.H * R0.L ) (S2RND); +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x0002CBB0; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0.s new file mode 100644 index 0000000..e47600e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0.s @@ -0,0 +1,129 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0/c_dsp32mac_pair_a0.dsp +// Spec Reference: dsp32mac pair a0 +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L, R6 = ( A0 = R1.L * R0.L ); + P1 = A1.w; + P5 = A0.w; + A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ); + P2 = A1.w; + A1 -= R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ); + P3 = A0.w; + A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ); + P4 = A0.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF2CF3598; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF70DA834; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xFF221DD6; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0x0004BA9E; + CHECKREG p3, 0xF2CF3598; + CHECKREG p4, 0xF70DA834; + CHECKREG p5, 0xFF221DD6; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A1 += R1.L * R0.H, R4 = ( A0 -= R1.L * R0.L ); + P1 = A0.w; + A1 = R2.L * R3.H, R0 = ( A0 = R2.H * R3.L ); + P2 = A0.w; + A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ); + P3 = A0.w; + A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ); + P4 = A0.w; + CHECKREG r0, 0xFFBC8F22; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFFA518F6; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xFD9B2E5E; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFD9B2E5E; + CHECKREG p2, 0xFFFC4AC8; + CHECKREG p3, 0xFFA518F6; + CHECKREG p4, 0xFFBC8F22; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ); + P1 = A0.w; + A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ); + P2 = A0.w; + A1 -= R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ); + P3 = A0.w; + A1 += R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ); + P4 = A0.w; + CHECKREG r0, 0xF8876658; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x1EA0F4F8; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x00062F18; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xCB200616; + CHECKREG p2, 0x00062F18; + CHECKREG p3, 0xF8876658; + CHECKREG p4, 0x1EA0F4F8; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ); + P1 = A0.w; + A1 -= R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ); + P2 = A0.w; + A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ); + P3 = A0.w; + A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ); + P4 = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0xFF256182; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0xFF1FB35E; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0xF750102E; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFF9EE9A; + CHECKREG p2, 0xFF256182; + CHECKREG p3, 0xFF1FB35E; + CHECKREG p4, 0xF750102E; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_i.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_i.s new file mode 100644 index 0000000..75782f8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_i.s @@ -0,0 +1,247 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_i/c_dsp32mac_pair_a0_i.dsp +// Spec Reference: dsp32mac pair a0 I +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (IS); + P1 = A0.w; + A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (IS); + P5 = A1.w; + P2 = A0.w; + A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (IS); + P3 = A0.w; + A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFFD9ABC; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF9679ACC; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF857FE25; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0x006EF115; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0x006EF115; + CHECKREG p2, 0xFFFD9ABC; + CHECKREG p3, 0xF9679ACC; + CHECKREG p4, 0xF857FE25; + CHECKREG p5, 0x00025D4F; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A0.w; + A1 -= R2.L * R3.H, R0 = ( A0 -= R2.H * R3.L ) (IS); + P2 = A0.w; + A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (IS); + P3 = A0.w; + A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFC8B26EA; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFC7F6BD4; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xFCB93CEB; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFCB93CEB; + CHECKREG p2, 0xFCBB1787; + CHECKREG p3, 0xFC7F6BD4; + CHECKREG p4, 0xFC8B26EA; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L, R4 = ( A0 -= R1.L * R0.L ) (IS); + P1 = A0.w; + A1 -= R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (IS); + P2 = A0.w; + A1 = R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (IS); + P3 = A0.w; + A1 -= R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0x01A40FD3; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x0B2A737B; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0x16FB23DF; + CHECKREG p2, 0x0003178C; + CHECKREG p3, 0x01A40FD3; + CHECKREG p4, 0x0B2A737B; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (IS); + P1 = A0.w; + A1 = R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ) (IS); + P2 = A0.w; + A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (IS); + P3 = A0.w; + A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFFCF74D; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0xFF92B0C1; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0xFF911149; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0x007295B5; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFFCF74D; + CHECKREG p2, 0xFF92B0C1; + CHECKREG p3, 0xFF911149; + CHECKREG p4, 0x007295B5; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (IS); + P5 = A1.w; + P1 = A0.w; + A1 -= R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (IS); + P2 = A0.w; + A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (IS); + P3 = A0.w; + A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFFD9ABC; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF9679ACC; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xFA773773; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xFF910EEB; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF910EEB; + CHECKREG p2, 0xFFFD9ABC; + CHECKREG p3, 0xF9679ACC; + CHECKREG p4, 0xFA773773; + CHECKREG p5, 0xFF89C73F; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R4 = ( A0 -= R1.L * R0.L ) (IS); + P1 = A0.w; + R0 = ( A0 = R2.H * R3.L ) (IS); + P2 = A0.w; + R2 = ( A0 += R4.H * R5.H ) (IS); + P3 = A0.w; + R0 = ( A0 += R6.L * R7.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFE0B29B; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFFD4F785; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xFDBDFA88; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFDBDFA88; + CHECKREG p2, 0xFFFE2564; + CHECKREG p3, 0xFFD4F785; + CHECKREG p4, 0xFFE0B29B; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A0.w; + R6 = ( A0 -= R2.H * R3.L ) (IS); + P2 = A0.w; + A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (IS); + P3 = A0.w; + R4 = ( A0 += R6.L * R7.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xE3AD394F; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xDB61F2C1; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0xE58CEB7F; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xE590030B; + CHECKREG p2, 0xE58CEB7F; + CHECKREG p3, 0xE3AD394F; + CHECKREG p4, 0xDB61F2C1; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R0 = ( A0 = R5.L * R3.L ) (IS); + P1 = A0.w; + A1 -= R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (IS); + P2 = A0.w; + A1 = R7.H * R0.H (M), R4 = ( A0 += R7.H * R0.H ) (IS); + P3 = A0.w; + R6 = ( A0 += R4.L * R6.H ) (IS); + P4 = A0.w; + CHECKREG r0, 0xFFFCF74D; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0x006A468C; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0x0068A714; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0xFBE08004; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFFCF74D; + CHECKREG p2, 0x006A468C; + CHECKREG p3, 0x0068A714; + CHECKREG p4, 0xFBE08004; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_is.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_is.s new file mode 100644 index 0000000..55f6c05 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_is.s @@ -0,0 +1,245 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_is/c_dsp32mac_pair_a0_is.dsp +// Spec Reference: dsp32mac pair a0 IS +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (ISS2); + P1 = A1.w; + A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (ISS2); + P2 = A1.w; + A1 -= R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (ISS2); + P3 = A1.w; + A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (ISS2); + P4 = A1.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF2CF3598; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xEE90C2FC; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0x00DDE22A; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF910EEB; + CHECKREG p2, 0x00025D4F; + CHECKREG p3, 0xFFCD4859; + CHECKREG p4, 0x0E03FC27; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A0.w; + A1 -= R2.L * R3.H, R0 = ( A0 -= R2.H * R3.L ) (ISS2); + P2 = A0.w; + A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (ISS2); + P3 = A0.w; + A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xF89EF66E; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xF8878042; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xF97279D6; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFCB93CEB; + CHECKREG p2, 0xFCBB1787; + CHECKREG p3, 0xFC43C021; + CHECKREG p4, 0xFC4F7B37; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A0.w; + A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (ISS2); + P2 = A0.w; + A1 -= R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (ISS2); + P3 = A0.w; + A1 += R6.H * R7.L, R4 = ( A0 -= R6.L * R7.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xF8876658; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xD26DD7B8; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x00062F18; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xE590030B; + CHECKREG p2, 0x0003178C; + CHECKREG p3, 0xFC43B32C; + CHECKREG p4, 0xE936EBDC; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (ISS2); + P1 = A0.w; + A1 -= R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ) (ISS2); + P2 = A0.w; + A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (ISS2); + P3 = A0.w; + A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0xFF256182; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0xFF1FB35E; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0xF750102E; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFFCF74D; + CHECKREG p2, 0xFF92B0C1; + CHECKREG p3, 0xFF8FD9AF; + CHECKREG p4, 0xFBA80817; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L (M), R6 = ( A0 -= R1.L * R0.L ) (ISS2); + P5 = A1.w; + P1 = A0.w; + A1 = R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (ISS2); + P2 = A0.w; + A1 -= R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (ISS2); + P3 = A0.w; + A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF2CF3598; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF0DDEE08; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xF82DF258; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFC16F92C; + CHECKREG p2, 0xFFFD9ABC; + CHECKREG p3, 0xF9679ACC; + CHECKREG p4, 0xF86EF704; + CHECKREG p5, 0xFF82C04D; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A0.w; + R0 = ( A0 -= R2.H * R3.L ) (ISS2); + P2 = A0.w; + R2 = ( A0 += R4.H * R5.H ) (ISS2); + P3 = A0.w; + R0 = ( A0 += R6.L * R7.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xF89EF66E; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xF8878042; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xF97279D6; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFCB93CEB; + CHECKREG p2, 0xFCBB1787; + CHECKREG p3, 0xFC43C021; + CHECKREG p4, 0xFC4F7B37; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A0.w; + R6 = ( A0 = R2.H * R3.L ) (ISS2); + P2 = A0.w; + A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (ISS2); + P3 = A0.w; + R4 = ( A0 += R6.L * R7.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xF8876658; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x1EA0F4F8; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x00062F18; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xE590030B; + CHECKREG p2, 0x0003178C; + CHECKREG p3, 0xFC43B32C; + CHECKREG p4, 0x0F507A7C; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R0 = ( A0 = R5.L * R3.L ) (ISS2); + P1 = A0.w; + A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (ISS2); + P2 = A0.w; + A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (ISS2); + P3 = A0.w; + R6 = ( A0 += R4.L * R6.H ) (ISS2); + P4 = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0x00D48D18; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0x00DA3B3C; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0x06E3E0DC; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFFCF74D; + CHECKREG p2, 0x006A468C; + CHECKREG p3, 0x006D1D9E; + CHECKREG p4, 0x0371F06E; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_m.s new file mode 100644 index 0000000..075704f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_m.s @@ -0,0 +1,129 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_m/c_dsp32mac_pair_a0_m.dsp +// Spec Reference: dsp32mac pair a0 m (M, MNOP) +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ); + P5 = A1.w; + P1 = A0.w; + A1 = R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ); + P2 = A0.w; + A1 -= R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ); + P3 = A0.w; + A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ); + P4 = A0.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xF2CF3598; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF70DA834; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xFF221DD6; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0xFFFB3578; + CHECKREG p3, 0xF2CF3598; + CHECKREG p4, 0xF70DA834; + CHECKREG p5, 0xFF910EEB; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R4 = ( A0 -= R1.L * R0.L ); + P1 = A0.w; + R0 = ( A0 = R2.H * R3.L ); + P2 = A0.w; + R2 = ( A0 += R4.H * R5.H ); + P3 = A0.w; + R0 = ( A0 += R6.L * R7.H ); + P4 = A0.w; + CHECKREG r0, 0xFFBC8F22; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFFA518F6; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xFD9B2E5E; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xFD9B2E5E; + CHECKREG p2, 0xFFFC4AC8; + CHECKREG p3, 0xFFA518F6; + CHECKREG p4, 0xFFBC8F22; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ); + P1 = A0.w; + R6 = ( A0 -= R2.H * R3.L ); + P2 = A0.w; + A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ); + P3 = A0.w; + R4 = ( A0 += R6.L * R7.H ); + P4 = A0.w; + CHECKREG r0, 0xC39B0E3E; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xA26DF406; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0xCB19D6FE; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xCB200616; + CHECKREG p2, 0xCB19D6FE; + CHECKREG p3, 0xC39B0E3E; + CHECKREG p4, 0xA26DF406; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R0 = ( A0 = R5.L * R3.L ); + P1 = A0.w; + A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ); + P2 = A0.w; + A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ); + P3 = A0.w; + R6 = ( A0 += R4.L * R6.H ); + P4 = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0x00D48D18; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0x00DA3B3C; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0x06E3E0DC; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFF9EE9A; + CHECKREG p2, 0x00D48D18; + CHECKREG p3, 0x00DA3B3C; + CHECKREG p4, 0x06E3E0DC; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_s.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_s.s new file mode 100644 index 0000000..77e36d8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_s.s @@ -0,0 +1,245 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_s/c_dsp32mac_pair_a0_s.dsp +// Spec Reference: dsp32mac pair a0 S +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (S2RND); + P1 = A0.w; + A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (S2RND); + P3 = A0.w; + A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0xFFF66AF0; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xE59E6B30; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xD4A4A0C0; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0x01BBC454; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0x00DDE22A; + CHECKREG p2, 0xFFFB3578; + CHECKREG p3, 0xF2CF3598; + CHECKREG p4, 0xEA525060; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A0.w; + A1 = R2.L * R3.H, R0 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (S2RND); + P3 = A0.w; + A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0xFC6CC6B8; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0xFC3DDA60; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xF2E4F3AC; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xF97279D6; + CHECKREG p2, 0xFFFC4AC8; + CHECKREG p3, 0xFE1EED30; + CHECKREG p4, 0xFE36635C; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L, R4 = ( A0 -= R1.L * R0.L ) (S2RND); + P1 = A0.w; + A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + A1 = R4.H * R5.L, R0 = ( A0 -= R4.H * R5.H ) (S2RND); + P3 = A0.w; + A1 += R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0xE314ECC0; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x7B7B2740; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x000C5E30; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0x33165D46; + CHECKREG p2, 0x00062F18; + CHECKREG p3, 0xF18A7660; + CHECKREG p4, 0x3DBD93A0; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (S2RND); + P1 = A0.w; + A1 -= R2.H * R1.H, R2 = ( A0 = R2.H * R1.L ) (S2RND); + P2 = A0.w; + A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (S2RND); + P3 = A0.w; + A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0xFFF3DD34; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0x01A91A30; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0x01940118; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0x01CD1598; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0xFFF9EE9A; + CHECKREG p2, 0x00D48D18; + CHECKREG p3, 0x00CA008C; + CHECKREG p4, 0x00E68ACC; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (S2RND); + P5 = A1.w; + P1 = A0.w; + A1 -= R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (S2RND); + P3 = A0.w; + A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0xFFF66AF0; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xE59E6B30; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xF69835A0; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0xFE443BAC; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0xFFFB3578; + CHECKREG p3, 0xF2CF3598; + CHECKREG p4, 0xFB4C1AD0; + CHECKREG p5, 0xFFAFB03F; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R4 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A0.w; + R0 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + R2 = ( A0 -= R4.H * R5.H ) (S2RND); + P3 = A0.w; + R0 = ( A0 += R6.L * R7.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0x03E23D18; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0x03B350C0; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0xF2E4F3AC; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xF97279D6; + CHECKREG p2, 0xFFFC4AC8; + CHECKREG p3, 0x01D9A860; + CHECKREG p4, 0x01F11E8C; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A0.w; + R6 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (S2RND); + P3 = A0.w; + R4 = ( A0 += R6.L * R7.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0xE2113B30; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x7A7775B0; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x000C5E30; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0xCB200616; + CHECKREG p2, 0x00062F18; + CHECKREG p3, 0xF1089D98; + CHECKREG p4, 0x3D3BBAD8; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R0 = ( A0 -= R5.L * R3.L ) (S2RND); + P1 = A0.w; + A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (S2RND); + P2 = A0.w; + A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (S2RND); + P3 = A0.w; + R6 = ( A0 += R4.L * R6.H ) (S2RND); + P4 = A0.w; + CHECKREG r0, 0x7A83987C; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0x01A91A30; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0x80000000; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0x80000000; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0x3D41CC3E; + CHECKREG p2, 0x00D48D18; + CHECKREG p3, 0x9D6AA7E4; + CHECKREG p4, 0x9D6AA7E4; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_u.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_u.s new file mode 100644 index 0000000..000fe6b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_u.s @@ -0,0 +1,245 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_u/c_dsp32mac_pair_a0_u.dsp +// Spec Reference: dsp32mac pair a0 U +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (FU); + P1 = A0.w; + A1 -= R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (FU); + P2 = A0.w; + A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (FU); + P3 = A0.w; + A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x00049ABC; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0x60FC9ACC; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0x60FC9ACC; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00049ABC; + CHECKREG p3, 0x60FC9ACC; + CHECKREG p4, 0x60FC9ACC; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (FU); + P1 = A0.w; + A1 -= R2.L * R3.H, R0 = ( A0 = R2.H * R3.L ) (FU); + P2 = A0.w; + A1 = R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (FU); + P3 = A0.w; + A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x0523F7E8; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0x05183CD2; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0x47763CEB; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x47763CEB; + CHECKREG p2, 0x00032564; + CHECKREG p3, 0x05183CD2; + CHECKREG p4, 0x0523F7E8; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ) (FU); + P1 = A0.w; + A1 -= R2.H * R3.L, R6 = ( A0 -= R2.H * R3.L ) (FU); + P2 = A0.w; + A1 = R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (FU); + P3 = A0.w; + A1 += R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x2E395300; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x8D7C0C72; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x2B29EB7F; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0x2B2D030B; + CHECKREG p2, 0x2B29EB7F; + CHECKREG p3, 0x2E395300; + CHECKREG p4, 0x8D7C0C72; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (FU); + P1 = A0.w; + A1 = R2.H * R1.H, R2 = ( A0 = R2.H * R1.L ) (FU); + P2 = A0.w; + A1 -= R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (FU); + P3 = A0.w; + A1 -= R4.H * R6.H, R6 = ( A0 -= R4.L * R6.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x0003F74D; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0xA845468C; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0xA8467E26; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0xA1D8A65E; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0x0003F74D; + CHECKREG p2, 0xA845468C; + CHECKREG p3, 0xA8467E26; + CHECKREG p4, 0xA1D8A65E; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (FU); + P5 = A1.w; + P1 = A0.w; + A1 = R2.L * R3.L (M), R0 = ( A0 -= R2.H * R3.L ) (FU); + P2 = A0.w; + A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (FU); + P3 = A0.w; + A1 -= R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x5A49742F; + CHECKREG r1, 0x86BCFEC7; + CHECKREG r2, 0xBB41743F; + CHECKREG r3, 0x00860007; + CHECKREG r4, 0xBC5110E6; + CHECKREG r5, 0x1235860B; + CHECKREG r6, 0x5A4E0EEB; + CHECKREG r7, 0x678E0086; + CHECKREG p1, 0x5A4E0EEB; + CHECKREG p2, 0x5A49742F; + CHECKREG p3, 0xBB41743F; + CHECKREG p4, 0xBC5110E6; + CHECKREG p5, 0x573CE4B9; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R4 = ( A0 -= R1.L * R0.L ) (FU); + P1 = A0.w; + R0 = ( A0 = R2.H * R3.L ) (FU); + P2 = A0.w; + R2 = ( A0 += R4.H * R5.H ) (FU); + P3 = A0.w; + R0 = ( A0 -= R6.L * R7.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x0846EF70; + CHECKREG r1, 0xA1BCF4C7; + CHECKREG r2, 0x0852AA86; + CHECKREG r3, 0x00010005; + CHECKREG r4, 0x74DAD3FB; + CHECKREG r5, 0x1235010B; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x74DAD3FB; + CHECKREG p2, 0x00032564; + CHECKREG p3, 0x0852AA86; + CHECKREG p4, 0x0846EF70; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (FU); + P1 = A0.w; + R6 = ( A0 = R2.H * R3.L ) (FU); + P2 = A0.w; + A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (FU); + P3 = A0.w; + R4 = ( A0 += R6.L * R7.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x03127F0D; + CHECKREG r1, 0xABD69EC7; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x0C98E2B5; + CHECKREG r5, 0x1225010B; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x678E0561; + CHECKREG p1, 0x2B2D030B; + CHECKREG p2, 0x0003178C; + CHECKREG p3, 0x03127F0D; + CHECKREG p4, 0x0C98E2B5; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R0 = ( A0 = R5.L * R3.L ) (FU); + P1 = A0.w; + A1 -= R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (FU); + P2 = A0.w; + A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (FU); + P3 = A0.w; + R6 = ( A0 += R4.L * R6.H ) (FU); + P4 = A0.w; + CHECKREG r0, 0x0003F74D; + CHECKREG r1, 0x91BCFEC7; + CHECKREG r2, 0xA845468C; + CHECKREG r3, 0xD0910007; + CHECKREG r4, 0xA8440EF2; + CHECKREG r5, 0xD235910B; + CHECKREG r6, 0xA9070C4A; + CHECKREG r7, 0x67DE0009; + CHECKREG p1, 0x0003F74D; + CHECKREG p2, 0xA845468C; + CHECKREG p3, 0xA8440EF2; + CHECKREG p4, 0xA9070C4A; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1.s new file mode 100644 index 0000000..36d8e2a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1.s @@ -0,0 +1,127 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1/c_dsp32mac_pair_a1.dsp +// Spec Reference: dsp32mac pair a1 +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L; + P1 = A1.w; + R1 = ( A1 = R2.L * R3.L ), A0 += R2.H * R3.L; + P2 = A1.w; + R3 = ( A1 -= R7.L * R4.L ), A0 += R7.H * R4.H; + P3 = A1.w; + R5 = ( A1 -= R6.L * R5.L ), A0 -= R6.L * R5.H; + P4 = A1.w; + CHECKREG r0, 0x63545ABD; + CHECKREG r1, 0x0004BA9E; + CHECKREG r2, 0xA8645679; + CHECKREG r3, 0xE8616512; + CHECKREG r4, 0xEFB86569; + CHECKREG r5, 0xF0688FB4; + CHECKREG r6, 0x000C086D; + CHECKREG r7, 0xFF221DD6; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0x0004BA9E; + CHECKREG p3, 0xE8616512; + CHECKREG p4, 0xF0688FB4; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = ( A1 += R1.L * R0.H ), A0 -= R1.L * R0.L; + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L; + P2 = A1.w; + R3 = ( A1 -= R4.L * R5.H ), A0 += R4.H * R5.H; + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H; + P4 = A1.w; + CHECKREG r0, 0x98764ABD; + CHECKREG r1, 0x012F2306; + CHECKREG r2, 0xA1145649; + CHECKREG r3, 0x0117ACDA; + CHECKREG r4, 0xEFBC1569; + CHECKREG r5, 0xF97C8728; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xF97C8728; + CHECKREG p2, 0x0000AC92; + CHECKREG p3, 0x0117ACDA; + CHECKREG p4, 0x012F2306; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ), A0 = R1.L * R0.L; + P1 = A1.w; + R7 = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L; + P2 = A1.w; + R1 = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H; + P3 = A1.w; + R5 = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H; + P4 = A1.w; + CHECKREG r0, 0x7136459D; + CHECKREG r1, 0xCABE16DA; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xEF9C1569; + CHECKREG r5, 0xCABE9156; + CHECKREG r6, 0x0003401D; + CHECKREG r7, 0xD363146A; + CHECKREG p1, 0xD3694382; + CHECKREG p2, 0xD363146A; + CHECKREG p3, 0xCABE16DA; + CHECKREG p4, 0xCABE9156; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L; + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ), A0 -= R2.H * R1.L; + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H; + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H; + P4 = A1.w; + CHECKREG r0, 0x123489BD; + CHECKREG r1, 0xDBB6D160; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0x18A4A070; + CHECKREG r4, 0xEDB91569; + CHECKREG r5, 0x09DF3640; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0x08024998; + CHECKREG p1, 0xDBB6D160; + CHECKREG p2, 0x18A4A070; + CHECKREG p3, 0x09DF3640; + CHECKREG p4, 0x08024998; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_i.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_i.s new file mode 100644 index 0000000..8ac571d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_i.s @@ -0,0 +1,243 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_i/c_dsp32mac_pair_a1_i.dsp +// Spec Reference: dsp32mac pair a1 I +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x93545abd; + imm32 r1, 0x89bcfec7; + imm32 r2, 0xa8945679; + imm32 r3, 0x00890007; + imm32 r4, 0xefb89569; + imm32 r5, 0x1235890b; + imm32 r6, 0x000c089d; + imm32 r7, 0x678e0089; + R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L (IS); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.L ), A0 -= R2.H * R3.L (IS); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.L ), A0 += R7.H * R4.H (IS); + P3 = A1.w; + R5 = ( A1 += R6.L * R5.L ), A0 += R6.L * R5.H (IS); + P4 = A1.w; + CHECKREG r0, 0x93545ABD; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0xA8945679; + CHECKREG r3, 0xF9C9E563; + CHECKREG r4, 0xEFB89569; + CHECKREG r5, 0xF5C94922; + CHECKREG r6, 0x000C089D; + CHECKREG r7, 0xFF910EEB; + CHECKREG p1, 0xFF910EEB; + CHECKREG p2, 0x00025D4F; + CHECKREG p3, 0xF9C9E563; + CHECKREG p4, 0xF5C94922; + + imm32 r0, 0x98464abd; + imm32 r1, 0xa1b5f4c7; + imm32 r2, 0xa1146649; + imm32 r3, 0x00010805; + imm32 r4, 0xefbc1599; + imm32 r5, 0x12350100; + imm32 r6, 0x200c001d; + imm32 r7, 0x628e0001; + R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (IS); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS); + P2 = A1.w; + R3 = ( A1 = R4.L * R5.H ), A0 -= R4.H * R5.H (IS); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (IS); + P4 = A1.w; + CHECKREG r0, 0x98464ABD; + CHECKREG r1, 0xFF90BFE3; + CHECKREG r2, 0xA1146649; + CHECKREG r3, 0xFF8595CD; + CHECKREG r4, 0xEFBC1599; + CHECKREG r5, 0xFA555F8C; + CHECKREG r6, 0x200C001D; + CHECKREG r7, 0x628E0001; + CHECKREG p1, 0xFA555F8C; + CHECKREG p2, 0x00006649; + CHECKREG p3, 0xFF8595CD; + CHECKREG p4, 0xFF90BFE3; + + imm32 r0, 0x713a459d; + imm32 r1, 0xabd6aec7; + imm32 r2, 0x7a145a79; + imm32 r3, 0x08a100a7; + imm32 r4, 0xef9a156a; + imm32 r5, 0x1225a10b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0a61; + R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (IS); + P1 = A1.w; + R7 = ( A1 -= R2.H * R3.L ), A0 = R2.H * R3.L (IS); + P2 = A1.w; + R1 = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IS); + P3 = A1.w; + R5 = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H (IS); + P4 = A1.w; + CHECKREG r0, 0x713A459D; + CHECKREG r1, 0xE54D2A3B; + CHECKREG r2, 0x7A145A79; + CHECKREG r3, 0x08A100A7; + CHECKREG r4, 0xEF9A156A; + CHECKREG r5, 0xE54DB17A; + CHECKREG r6, 0x0003401D; + CHECKREG r7, 0xE85E2D15; + CHECKREG p1, 0xE8ADD021; + CHECKREG p2, 0xE85E2D15; + CHECKREG p3, 0xE54D2A3B; + CHECKREG p4, 0xE54DB17A; + + imm32 r0, 0x773489bd; + imm32 r1, 0x917cfec7; + imm32 r2, 0xa9177679; + imm32 r3, 0xd0910777; + imm32 r4, 0xedb91579; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d077999; + imm32 r7, 0x677e0709; + R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (IS); + P1 = A1.w; + R3 = ( A1 -= R2.H * R1.H ), A0 = R2.H * R1.L (IS); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H (IS); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ), A0 -= R4.L * R6.H (IS); + P4 = A1.w; + CHECKREG r0, 0x773489BD; + CHECKREG r1, 0xEDC9D17F; + CHECKREG r2, 0xA9177679; + CHECKREG r3, 0xE79AC370; + CHECKREG r4, 0xEDB91579; + CHECKREG r5, 0xB76A2BD8; + CHECKREG r6, 0x0D077999; + CHECKREG r7, 0xB67C10E7; + CHECKREG p1, 0xEDC9D17F; + CHECKREG p2, 0xE79AC370; + CHECKREG p3, 0xB76A2BD8; + CHECKREG p4, 0xB67C10E7; + + imm32 r0, 0x83547abd; + imm32 r1, 0x88bc8ec7; + imm32 r2, 0xa8895679; + imm32 r3, 0x00080007; + imm32 r4, 0xe6b86569; + imm32 r5, 0x1A35860b; + imm32 r6, 0x000c896d; + imm32 r7, 0x67Be0096; + R7 = ( A1 += R1.L * R0.L ) (IS); + P1 = A1.w; + R1 = ( A1 = R2.H * R3.L ) (IS); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.H ) (IS); + P3 = A1.w; + R5 = ( A1 += R6.H * R5.H ) (IS); + P4 = A1.w; + CHECKREG r0, 0x83547ABD; + CHECKREG r1, 0xFFFD9BBF; + CHECKREG r2, 0xA8895679; + CHECKREG r3, 0xF81E0AF0; + CHECKREG r4, 0xE6B86569; + CHECKREG r5, 0xF81F456C; + CHECKREG r6, 0x000C896D; + CHECKREG r7, 0x80334FD2; + CHECKREG p1, 0x80334FD2; + CHECKREG p2, 0xFFFD9BBF; + CHECKREG p3, 0xF81E0AF0; + CHECKREG p4, 0xF81F456C; + + imm32 r0, 0x9aa64abd; + imm32 r1, 0xa1baf4c7; + imm32 r2, 0xb114a649; + imm32 r3, 0x0b010005; + imm32 r4, 0xefbcdb69; + imm32 r5, 0x123501bb; + imm32 r6, 0x000c0d1b; + imm32 r7, 0x678e0d01; + R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (IS); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ) (M), A0 -= R2.H * R3.L (IS); + P2 = A1.w; + R3 = ( A1 -= R4.L * R5.H ) (M), A0 += R4.H * R5.H (IS); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (IS); + P4 = A1.w; + CHECKREG r0, 0x9AA64ABD; + CHECKREG r1, 0x23F08194; + CHECKREG r2, 0xB114A649; + CHECKREG r3, 0x1EA35F9A; + CHECKREG r4, 0xEFBCDB69; + CHECKREG r5, 0xF157B476; + CHECKREG r6, 0x000C0D1B; + CHECKREG r7, 0x678E0D01; + CHECKREG p1, 0xF157B476; + CHECKREG p2, 0xFC24C949; + CHECKREG p3, 0x1EA35F9A; + CHECKREG p4, 0x23F08194; + + imm32 r0, 0xd136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0xdd010007; + imm32 r4, 0xeddc1569; + imm32 r5, 0x122d010b; + imm32 r6, 0x00e3d01d; + imm32 r7, 0x678e0d61; + R5 = A1 , A0 -= R1.L * R0.L (IS); + P1 = A1.w; + R7 = A1 , A0 = R2.H * R3.L (IS); + P2 = A1.w; + R1 = A1 , A0 += R4.H * R5.H (IS); + P3 = A1.w; + R5 = A1 , A0 += R6.L * R7.H (IS); + P4 = A1.w; + CHECKREG r0, 0xD136459D; + CHECKREG r1, 0x23F08194; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0xDD010007; + CHECKREG r4, 0xEDDC1569; + CHECKREG r5, 0x23F08194; + CHECKREG r6, 0x00E3D01D; + CHECKREG r7, 0x23F08194; + CHECKREG p1, 0x23F08194; + CHECKREG p2, 0x23F08194; + CHECKREG p3, 0x23F08194; + CHECKREG p4, 0x23F08194; + + imm32 r0, 0x125489bd; + imm32 r1, 0x91b5fec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910507; + imm32 r4, 0x34567859; + imm32 r5, 0xd2359105; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ) (M,IS); + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ) (M,IS); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ) (M,IS); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ) (M,IS); + P4 = A1.w; + CHECKREG r0, 0x125489BD; + CHECKREG r1, 0xFEA1A199; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0xA98B2D94; + CHECKREG r4, 0x34567859; + CHECKREG r5, 0xA21B7CBC; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0xA4C64EC4; + CHECKREG p1, 0xFEA1A199; + CHECKREG p2, 0xA98B2D94; + CHECKREG p3, 0xA21B7CBC; + CHECKREG p4, 0xA4C64EC4; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_is.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_is.s new file mode 100644 index 0000000..58d9735 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_is.s @@ -0,0 +1,243 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_is/c_dsp32mac_pair_a1_is.dsp +// Spec Reference: dsp32mac pair a1 IS +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x93545abd; + imm32 r1, 0x89bcfec7; + imm32 r2, 0xa8945679; + imm32 r3, 0x00890007; + imm32 r4, 0xefb89569; + imm32 r5, 0x1235890b; + imm32 r6, 0x000c089d; + imm32 r7, 0x678e0089; + R7 = ( A1 += R5.L * R0.L ), A0 = R5.L * R0.L (ISS2); + P1 = A1.w; + R1 = ( A1 = R4.L * R3.L ), A0 = R4.H * R3.L (ISS2); + P2 = A1.w; + R3 = ( A1 = R7.L * R2.L ), A0 += R7.H * R2.H (ISS2); + P3 = A1.w; + R5 = ( A1 += R6.L * R1.L ), A0 += R6.L * R1.H (ISS2); + P4 = A1.w; + CHECKREG r0, 0x93545ABD; + CHECKREG r1, 0xFFFA2BBE; + CHECKREG r2, 0xA8945679; + CHECKREG r3, 0x0F06AE9C; + CHECKREG r4, 0xEFB89569; + CHECKREG r5, 0x11F835A8; + CHECKREG r6, 0x000C089D; + CHECKREG r7, 0xABAC163E; + CHECKREG p1, 0xD5D60B1F; + CHECKREG p2, 0xFFFD15DF; + CHECKREG p3, 0x0783574E; + CHECKREG p4, 0x08FC1AD4; + + imm32 r0, 0x98464abd; + imm32 r1, 0xa1b5f4c7; + imm32 r2, 0xa1146649; + imm32 r3, 0x00010805; + imm32 r4, 0xefbc1599; + imm32 r5, 0x12350100; + imm32 r6, 0x200c001d; + imm32 r7, 0x628e0001; + R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (ISS2); + P1 = A1.w; + R1 = ( A1 -= R5.L * R3.H ), A0 = R5.H * R3.L (ISS2); + P2 = A1.w; + R3 = ( A1 -= R4.L * R2.H ), A0 += R4.H * R2.H (ISS2); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (ISS2); + P4 = A1.w; + CHECKREG r0, 0x98464ABD; + CHECKREG r1, 0x2B2A1FC8; + CHECKREG r2, 0xA1146649; + CHECKREG r3, 0x2B13CB9C; + CHECKREG r4, 0xEFBC1599; + CHECKREG r5, 0x1B10627C; + CHECKREG r6, 0x200C001D; + CHECKREG r7, 0x628E0001; + CHECKREG p1, 0x0D88313E; + CHECKREG p2, 0x0D87CEC2; + CHECKREG p3, 0x1589E5CE; + CHECKREG p4, 0x15950FE4; + + imm32 r0, 0x713a459d; + imm32 r1, 0xabd6aec7; + imm32 r2, 0x7a145a79; + imm32 r3, 0x08a100a7; + imm32 r4, 0xef9a156a; + imm32 r5, 0x1225a10b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0a61; + R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (ISS2); + P1 = A1.w; + R7 = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L (ISS2); + P2 = A1.w; + R1 = ( A1 = R7.H * R5.L ), A0 += R7.H * R5.H (ISS2); + P3 = A1.w; + R5 = ( A1 += R6.H * R4.L ), A0 += R6.L * R4.H (ISS2); + P4 = A1.w; + CHECKREG r0, 0x713A459D; + CHECKREG r1, 0xFE604820; + CHECKREG r2, 0x7A145A79; + CHECKREG r3, 0x08A100A7; + CHECKREG r4, 0xEF9A156A; + CHECKREG r5, 0xFE60C89C; + CHECKREG r6, 0x0003401D; + CHECKREG r7, 0xFCC4FA2C; + CHECKREG p1, 0xFEB22022; + CHECKREG p2, 0xFE627D16; + CHECKREG p3, 0xFF302410; + CHECKREG p4, 0xFF30644E; + + imm32 r0, 0x773489bd; + imm32 r1, 0x917cfec7; + imm32 r2, 0xa9177679; + imm32 r3, 0xd0910777; + imm32 r4, 0xedb91579; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d077999; + imm32 r7, 0x677e0709; + R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (ISS2); + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ), A0 = R2.H * R1.L (ISS2); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H (ISS2); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (ISS2); + P4 = A1.w; + CHECKREG r0, 0x773489BD; + CHECKREG r1, 0x0F5908A6; + CHECKREG r2, 0xA9177679; + CHECKREG r3, 0xF59443FE; + CHECKREG r4, 0xEDB91579; + CHECKREG r5, 0x953314CE; + CHECKREG r6, 0x0D077999; + CHECKREG r7, 0x9356DEEC; + CHECKREG p1, 0x07AC8453; + CHECKREG p2, 0xFACA21FF; + CHECKREG p3, 0xCA998A67; + CHECKREG p4, 0xC9AB6F76; + + imm32 r0, 0x83547abd; + imm32 r1, 0x88bc8ec7; + imm32 r2, 0xa8895679; + imm32 r3, 0x00080007; + imm32 r4, 0xe6b86569; + imm32 r5, 0x1A35860b; + imm32 r6, 0x000c896d; + imm32 r7, 0x67Be0096; + R7 = ( A1 += R1.L * R0.L ) (ISS2); + P1 = A1.w; + R1 = ( A1 = R2.H * R3.L ) (ISS2); + P2 = A1.w; + R3 = ( A1 -= R7.L * R4.H ) (ISS2); + P3 = A1.w; + R5 = ( A1 += R6.H * R5.H ) (ISS2); + P4 = A1.w; + CHECKREG r0, 0x83547ABD; + CHECKREG r1, 0xFFFB377E; + CHECKREG r2, 0xA8895679; + CHECKREG r3, 0xFFFB377E; + CHECKREG r4, 0xE6B86569; + CHECKREG r5, 0xFFFDAC76; + CHECKREG r6, 0x000C896D; + CHECKREG r7, 0x80000000; + CHECKREG p1, 0x9362AE61; + CHECKREG p2, 0xFFFD9BBF; + CHECKREG p3, 0xFFFD9BBF; + CHECKREG p4, 0xFFFED63B; + + imm32 r0, 0x9aa64abd; + imm32 r1, 0xa1baf4c7; + imm32 r2, 0xb114a649; + imm32 r3, 0x0b010005; + imm32 r4, 0xefbcdb69; + imm32 r5, 0x123501bb; + imm32 r6, 0x000c0d1b; + imm32 r7, 0x678e0d01; + R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (ISS2); + P1 = A1.w; + R1 = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (ISS2); + P2 = A1.w; + R3 = ( A1 = R4.L * R5.H ) (M), A0 += R4.H * R5.H (ISS2); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (ISS2); + P4 = A1.w; + CHECKREG r0, 0x9AA64ABD; + CHECKREG r1, 0xC54D5630; + CHECKREG r2, 0xB114A649; + CHECKREG r3, 0xBAB3123C; + CHECKREG r4, 0xEFBCDB69; + CHECKREG r5, 0xF26E8A8A; + CHECKREG r6, 0x000C0D1B; + CHECKREG r7, 0x678E0D01; + CHECKREG p1, 0xF9374545; + CHECKREG p2, 0xFD127BFC; + CHECKREG p3, 0xDD59891E; + CHECKREG p4, 0xE2A6AB18; + + imm32 r0, 0xd136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0xdd010007; + imm32 r4, 0xeddc1569; + imm32 r5, 0x122d010b; + imm32 r6, 0x00e3d01d; + imm32 r7, 0x678e0d61; + R5 = A1 , A0 -= R1.L * R0.L (ISS2); + P1 = A1.w; + R7 = A1 , A0 = R2.H * R3.L (ISS2); + P2 = A1.w; + R1 = A1 , A0 += R4.H * R5.H (ISS2); + P3 = A1.w; + R5 = A1 , A0 += R6.L * R7.H (ISS2); + P4 = A1.w; + CHECKREG r0, 0xD136459D; + CHECKREG r1, 0xC54D5630; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0xDD010007; + CHECKREG r4, 0xEDDC1569; + CHECKREG r5, 0xC54D5630; + CHECKREG r6, 0x00E3D01D; + CHECKREG r7, 0xC54D5630; + CHECKREG p1, 0xE2A6AB18; + CHECKREG p2, 0xE2A6AB18; + CHECKREG p3, 0xE2A6AB18; + CHECKREG p4, 0xE2A6AB18; + + imm32 r0, 0x125489bd; + imm32 r1, 0x91b5fec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910507; + imm32 r4, 0x34567859; + imm32 r5, 0xd2359105; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ) (M,ISS2); + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ) (M,ISS2); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ) (M,ISS2); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ) (M,ISS2); + P4 = A1.w; + CHECKREG r0, 0x125489BD; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0xA9140000; + CHECKREG r4, 0x34567859; + CHECKREG r5, 0x9A349E50; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0x9F8A4260; + CHECKREG p1, 0xBD57CB1D; + CHECKREG p2, 0xD48A0000; + CHECKREG p3, 0xCD1A4F28; + CHECKREG p4, 0xCFC52130; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_m.s new file mode 100644 index 0000000..f93e7a5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_m.s @@ -0,0 +1,127 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_m/c_dsp32mac_pair_a1_m.dsp +// Spec Reference: dsp32mac pair a1 M MNOP +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x63547abd; + imm32 r1, 0x86bc8ec7; + imm32 r2, 0xa8695679; + imm32 r3, 0x00060007; + imm32 r4, 0xe6b86569; + imm32 r5, 0x1A35860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x67Be0086; + R7 = ( A1 += R1.L * R0.L ); + P1 = A1.w; + R1 = ( A1 -= R2.H * R3.L ); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.H ); + P3 = A1.w; + R5 = ( A1 += R6.H * R5.H ); + P4 = A1.w; + CHECKREG r0, 0x63547ABD; + CHECKREG r1, 0x93734818; + CHECKREG r2, 0xA8695679; + CHECKREG r3, 0xE7256BA0; + CHECKREG r4, 0xE6B86569; + CHECKREG r5, 0xE727E098; + CHECKREG r6, 0x000C086D; + CHECKREG r7, 0x936E7DD6; + CHECKREG p1, 0x936E7DD6; + CHECKREG p2, 0x93734818; + CHECKREG p3, 0xE7256BA0; + CHECKREG p4, 0xE727E098; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xb1145649; + imm32 r3, 0x0b010005; + imm32 r4, 0xefbcbb69; + imm32 r5, 0x123501bb; + imm32 r6, 0x000c001b; + imm32 r7, 0x678e0001; + R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L; + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ) (M), A0 = R2.H * R3.L; + P2 = A1.w; + R3 = ( A1 -= R4.L * R5.H ) (M), A0 += R4.H * R5.H; + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H; + P4 = A1.w; + CHECKREG r0, 0x98764ABD; + CHECKREG r1, 0x3FE4AC0B; + CHECKREG r2, 0xB1145649; + CHECKREG r3, 0x3FD9C011; + CHECKREG r4, 0xEFBCBB69; + CHECKREG r5, 0xE078DC52; + CHECKREG r6, 0x000C001B; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xE078DC52; + CHECKREG p2, 0x03B57949; + CHECKREG p3, 0x3FD9C011; + CHECKREG p4, 0x3FE4AC0B; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0xd8010007; + imm32 r4, 0xeddc1569; + imm32 r5, 0x122d010b; + imm32 r6, 0x0003d01d; + imm32 r7, 0x678e0d61; + R5 = A1 , A0 = R1.L * R0.L; + P1 = A1.w; + R7 = A1 , A0 -= R2.H * R3.L; + P2 = A1.w; + R1 = A1 , A0 += R4.H * R5.H; + P3 = A1.w; + R5 = A1 , A0 += R6.L * R7.H; + P4 = A1.w; + CHECKREG r0, 0x7136459D; + CHECKREG r1, 0x3FE4AC0B; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0xD8010007; + CHECKREG r4, 0xEDDC1569; + CHECKREG r5, 0x3FE4AC0B; + CHECKREG r6, 0x0003D01D; + CHECKREG r7, 0x3FE4AC0B; + CHECKREG p1, 0x3FE4AC0B; + CHECKREG p2, 0x3FE4AC0B; + CHECKREG p3, 0x3FE4AC0B; + CHECKREG p4, 0x3FE4AC0B; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0x34567899; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ) (M); + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ) (M); + P2 = A1.w; + R5 = ( A1 -= R7.H * R0.H ) (M); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ) (M); + P4 = A1.w; + CHECKREG r0, 0x123489BD; + CHECKREG r1, 0x1A95CC10; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0xF6F970A4; + CHECKREG r4, 0x34567899; + CHECKREG r5, 0xEF96BB8C; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0xF2418D94; + CHECKREG p1, 0x1A95CC10; + CHECKREG p2, 0xF6F970A4; + CHECKREG p3, 0xEF96BB8C; + CHECKREG p4, 0xF2418D94; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_s.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_s.s new file mode 100644 index 0000000..2cc1ec6 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_s.s @@ -0,0 +1,243 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_s/c_dsp32mac_pair_a1_s.dsp +// Spec Reference: dsp32mac pair a1 S +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x93545abd; + imm32 r1, 0x89bcfec7; + imm32 r2, 0xa8945679; + imm32 r3, 0x00890007; + imm32 r4, 0xefb89569; + imm32 r5, 0x1235890b; + imm32 r6, 0x000c089d; + imm32 r7, 0x678e0089; + R7 = ( A1 += R5.L * R0.L ), A0 = R5.L * R0.L (S2RND); + P1 = A1.w; + R1 = ( A1 -= R4.L * R3.L ), A0 = R4.H * R3.L (S2RND); + P2 = A1.w; + R3 = ( A1 -= R7.L * R2.L ), A0 += R7.H * R2.H (S2RND); + P3 = A1.w; + R5 = ( A1 += R6.L * R1.L ), A0 += R6.L * R1.H (S2RND); + P4 = A1.w; + CHECKREG r0, 0x93545ABD; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0xA8945679; + CHECKREG r3, 0x80000000; + CHECKREG r4, 0xEFB89569; + CHECKREG r5, 0x80000000; + CHECKREG r6, 0x000C089D; + CHECKREG r7, 0x80000000; + CHECKREG p1, 0xABAC163E; + CHECKREG p2, 0xABB1EA80; + CHECKREG p3, 0xABB1EA80; + CHECKREG p4, 0xABB1EA80; + + imm32 r0, 0x98464abd; + imm32 r1, 0xa1b5f4c7; + imm32 r2, 0xa1146649; + imm32 r3, 0x00010805; + imm32 r4, 0xefbc1599; + imm32 r5, 0x12350100; + imm32 r6, 0x200c001d; + imm32 r7, 0x628e0001; + R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (S2RND); + P1 = A1.w; + R1 = ( A1 = R5.L * R3.H ), A0 -= R5.H * R3.L (S2RND); + P2 = A1.w; + R3 = ( A1 = R4.L * R2.H ), A0 += R4.H * R2.H (S2RND); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (S2RND); + P4 = A1.w; + CHECKREG r0, 0x98464ABD; + CHECKREG r1, 0xE0244C28; + CHECKREG r2, 0xA1146649; + CHECKREG r3, 0xDFF7A3D0; + CHECKREG r4, 0xEFBC1599; + CHECKREG r5, 0x80000000; + CHECKREG r6, 0x200C001D; + CHECKREG r7, 0x628E0001; + CHECKREG p1, 0xB4CA1754; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0xEFFBD1E8; + CHECKREG p4, 0xF0122614; + + imm32 r0, 0x713a459d; + imm32 r1, 0xabd6aec7; + imm32 r2, 0x7a145a79; + imm32 r3, 0x08a100a7; + imm32 r4, 0xef9a156a; + imm32 r5, 0x1225a10b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0a61; + R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (S2RND); + P1 = A1.w; + R7 = ( A1 = R2.H * R3.L ), A0 -= R2.H * R3.L (S2RND); + P2 = A1.w; + R1 = ( A1 = R7.H * R5.L ), A0 += R7.H * R5.H (S2RND); + P3 = A1.w; + R5 = ( A1 += R6.H * R4.L ), A0 += R6.L * R4.H (S2RND); + P4 = A1.w; + CHECKREG r0, 0x713A459D; + CHECKREG r1, 0xFDC53700; + CHECKREG r2, 0x7A145A79; + CHECKREG r3, 0x08A100A7; + CHECKREG r4, 0xEF9A156A; + CHECKREG r5, 0xFDC637F8; + CHECKREG r6, 0x0003401D; + CHECKREG r7, 0x013E8C30; + CHECKREG p1, 0xC24C4690; + CHECKREG p2, 0x009F4618; + CHECKREG p3, 0xFEE29B80; + CHECKREG p4, 0xFEE31BFC; + + imm32 r0, 0x773489bd; + imm32 r1, 0x917cfec7; + imm32 r2, 0xa9177679; + imm32 r3, 0xd0910777; + imm32 r4, 0xedb91579; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d077999; + imm32 r7, 0x677e0709; + R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (S2RND); + P1 = A1.w; + R3 = ( A1 -= R2.H * R1.H ), A0 = R2.H * R1.L (S2RND); + P2 = A1.w; + R5 = ( A1 = R7.H * R0.H ), A0 += R7.H * R0.H (S2RND); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (S2RND); + P4 = A1.w; + CHECKREG r0, 0x773489BD; + CHECKREG r1, 0x1FB6B80C; + CHECKREG r2, 0xA9177679; + CHECKREG r3, 0x4AC6BAA4; + CHECKREG r4, 0xEDB91579; + CHECKREG r5, 0x7FFFFFFF; + CHECKREG r6, 0x0D077999; + CHECKREG r7, 0x7FFFFFFF; + CHECKREG p1, 0x0FDB5C06; + CHECKREG p2, 0x25635D52; + CHECKREG p3, 0x60612F30; + CHECKREG p4, 0x5E84F94E; + + imm32 r0, 0x83547abd; + imm32 r1, 0x88bc8ec7; + imm32 r2, 0xa8895679; + imm32 r3, 0x00080007; + imm32 r4, 0xe6b86569; + imm32 r5, 0x1A35860b; + imm32 r6, 0x000c896d; + imm32 r7, 0x67Be0096; + R7 = ( A1 += R1.L * R0.L ) (S2RND); + P1 = A1.w; + R1 = ( A1 -= R2.H * R3.L ) (S2RND); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.H ) (S2RND); + P3 = A1.w; + R5 = ( A1 += R6.H * R5.H ) (S2RND); + P4 = A1.w; + CHECKREG r0, 0x83547ABD; + CHECKREG r1, 0xE3F07F4C; + CHECKREG r2, 0xA8895679; + CHECKREG r3, 0x06FFCF00; + CHECKREG r4, 0xE6B86569; + CHECKREG r5, 0x0704B8F0; + CHECKREG r6, 0x000C896D; + CHECKREG r7, 0xE3E6EE48; + CHECKREG p1, 0xF1F37724; + CHECKREG p2, 0xF1F83FA6; + CHECKREG p3, 0x037FE780; + CHECKREG p4, 0x03825C78; + + imm32 r0, 0x9aa64abd; + imm32 r1, 0xa1baf4c7; + imm32 r2, 0xb114a649; + imm32 r3, 0x0b010005; + imm32 r4, 0xefbcdb69; + imm32 r5, 0x123501bb; + imm32 r6, 0x000c0d1b; + imm32 r7, 0x678e0d01; + R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (S2RND); + P1 = A1.w; + R1 = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (S2RND); + P2 = A1.w; + R3 = ( A1 -= R4.L * R5.H ) (M), A0 -= R4.H * R5.H (S2RND); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (S2RND); + P4 = A1.w; + CHECKREG r0, 0x9AA64ABD; + CHECKREG r1, 0x5315786C; + CHECKREG r2, 0xB114A649; + CHECKREG r3, 0x487B3478; + CHECKREG r4, 0xEFBCDB69; + CHECKREG r5, 0xF9759704; + CHECKREG r6, 0x000C0D1B; + CHECKREG r7, 0x678E0D01; + CHECKREG p1, 0xFCBACB82; + CHECKREG p2, 0x00960239; + CHECKREG p3, 0x243D9A3C; + CHECKREG p4, 0x298ABC36; + + imm32 r0, 0xd136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0xdd010007; + imm32 r4, 0xeddc1569; + imm32 r5, 0x122d010b; + imm32 r6, 0x00e3d01d; + imm32 r7, 0x678e0d61; + R5 = A1 , A0 -= R1.L * R0.L (S2RND); + P1 = A1.w; + R7 = A1 , A0 = R2.H * R3.L (S2RND); + P2 = A1.w; + R1 = A1 , A0 -= R4.H * R5.H (S2RND); + P3 = A1.w; + R5 = A1 , A0 += R6.L * R7.H (S2RND); + P4 = A1.w; + CHECKREG r0, 0xD136459D; + CHECKREG r1, 0x5315786C; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0xDD010007; + CHECKREG r4, 0xEDDC1569; + CHECKREG r5, 0x5315786C; + CHECKREG r6, 0x00E3D01D; + CHECKREG r7, 0x5315786C; + CHECKREG p1, 0x298ABC36; + CHECKREG p2, 0x298ABC36; + CHECKREG p3, 0x298ABC36; + CHECKREG p4, 0x298ABC36; + + imm32 r0, 0x125489bd; + imm32 r1, 0x91b5fec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910507; + imm32 r4, 0x34567859; + imm32 r5, 0xd2359105; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ) (M,S2RND); + P1 = A1.w; + R3 = ( A1 -= R2.H * R1.H ) (M,S2RND); + P2 = A1.w; + R5 = ( A1 = R7.H * R0.H ) (M,S2RND); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ) (M,S2RND); + P4 = A1.w; + CHECKREG r0, 0x125489BD; + CHECKREG r1, 0x0877B876; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0x0E3747DE; + CHECKREG r4, 0x34567859; + CHECKREG r5, 0x0EDF61B0; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0x143505C0; + CHECKREG p1, 0x043BDC3B; + CHECKREG p2, 0x071BA3EF; + CHECKREG p3, 0x076FB0D8; + CHECKREG p4, 0x0A1A82E0; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_u.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_u.s new file mode 100644 index 0000000..26cfbd5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_u.s @@ -0,0 +1,243 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_u/c_dsp32mac_pair_a1_u.dsp +// Spec Reference: dsp32mac pair a1 U +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A1 , and stored to a reg half + imm32 r0, 0x93545abd; + imm32 r1, 0x89bcfec7; + imm32 r2, 0xa8945679; + imm32 r3, 0x00890007; + imm32 r4, 0xefb89569; + imm32 r5, 0x1235890b; + imm32 r6, 0x000c089d; + imm32 r7, 0x678e0089; + R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L (FU); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L (FU); + P2 = A1.w; + R3 = ( A1 = R7.L * R4.L ), A0 += R7.H * R4.H (FU); + P3 = A1.w; + R5 = ( A1 += R6.L * R5.L ), A0 += R6.L * R5.H (FU); + P4 = A1.w; + CHECKREG r0, 0x93545ABD; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0xA8945679; + CHECKREG r3, 0x08B4E563; + CHECKREG r4, 0xEFB89569; + CHECKREG r5, 0x0D514922; + CHECKREG r6, 0x000C089D; + CHECKREG r7, 0x5A4E0EEB; + CHECKREG p1, 0x5A4E0EEB; + CHECKREG p2, 0x00025D4F; + CHECKREG p3, 0x08B4E563; + CHECKREG p4, 0x0D514922; + + imm32 r0, 0x98464abd; + imm32 r1, 0xa1b5f4c7; + imm32 r2, 0xa1146649; + imm32 r3, 0x00010805; + imm32 r4, 0xefbc1599; + imm32 r5, 0x12350100; + imm32 r6, 0x200c001d; + imm32 r7, 0x628e0001; + R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (FU); + P1 = A1.w; + R1 = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (FU); + P2 = A1.w; + R3 = ( A1 = R4.L * R5.H ), A0 += R4.H * R5.H (FU); + P3 = A1.w; + R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (FU); + P4 = A1.w; + CHECKREG r0, 0x98464ABD; + CHECKREG r1, 0x0D7355F0; + CHECKREG r2, 0xA1146649; + CHECKREG r3, 0x0D682BDA; + CHECKREG r4, 0xEFBC1599; + CHECKREG r5, 0x9EEA5F8C; + CHECKREG r6, 0x200C001D; + CHECKREG r7, 0x628E0001; + CHECKREG p1, 0x9EEA5F8C; + CHECKREG p2, 0x00006649; + CHECKREG p3, 0x0D682BDA; + CHECKREG p4, 0x0D7355F0; + + imm32 r0, 0x713a459d; + imm32 r1, 0xabd6aec7; + imm32 r2, 0x7a145a79; + imm32 r3, 0x08a100a7; + imm32 r4, 0xef9a156a; + imm32 r5, 0x1225a10b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0a61; + R5 = ( A1 += R7.H * R3.L ), A0 = R7.L * R3.L (FU); + P1 = A1.w; + R7 = ( A1 = R2.H * R4.L ), A0 -= R2.H * R4.L (FU); + P2 = A1.w; + R1 = ( A1 -= R0.H * R5.L ), A0 += R0.H * R5.H (FU); + P3 = A1.w; + R5 = ( A1 += R6.H * R1.L ), A0 += R6.L * R1.H (FU); + P4 = A1.w; + CHECKREG r0, 0x713A459D; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x7A145A79; + CHECKREG r3, 0x08A100A7; + CHECKREG r4, 0xEF9A156A; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x0003401D; + CHECKREG r7, 0x0A363048; + CHECKREG p1, 0x0DB6E392; + CHECKREG p2, 0x0A363048; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x00000000; + + imm32 r0, 0x773489bd; + imm32 r1, 0x917cfec7; + imm32 r2, 0xa9177679; + imm32 r3, 0xd0910777; + imm32 r4, 0xedb91579; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d077999; + imm32 r7, 0x677e0709; + R1 = ( A1 += R5.H * R3.H ), A0 -= R5.L * R3.L (FU); + P1 = A1.w; + R3 = ( A1 = R2.H * R1.H ), A0 -= R2.H * R1.L (FU); + P2 = A1.w; + R5 = ( A1 = R7.H * R0.H ), A0 += R7.H * R0.H (FU); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (FU); + P4 = A1.w; + CHECKREG r0, 0x773489BD; + CHECKREG r1, 0xAB422005; + CHECKREG r2, 0xA9177679; + CHECKREG r3, 0x711DF4EE; + CHECKREG r4, 0xEDB91579; + CHECKREG r5, 0x30309798; + CHECKREG r6, 0x0D077999; + CHECKREG r7, 0x3C497CA7; + CHECKREG p1, 0xAB422005; + CHECKREG p2, 0x711DF4EE; + CHECKREG p3, 0x30309798; + CHECKREG p4, 0x3C497CA7; + + imm32 r0, 0x83547abd; + imm32 r1, 0x88bc8ec7; + imm32 r2, 0xa8895679; + imm32 r3, 0x00080007; + imm32 r4, 0xe6b86569; + imm32 r5, 0x1A35860b; + imm32 r6, 0x000c896d; + imm32 r7, 0x67Be0096; + R7 = ( A1 += R1.L * R0.L ) (FU); + P1 = A1.w; + R1 = ( A1 = R2.H * R3.L ) (FU); + P2 = A1.w; + R3 = ( A1 -= R7.L * R4.H ) (FU); + P3 = A1.w; + R5 = ( A1 += R6.H * R5.H ) (FU); + P4 = A1.w; + CHECKREG r0, 0x83547ABD; + CHECKREG r1, 0x00049BBF; + CHECKREG r2, 0xA8895679; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0xE6B86569; + CHECKREG r5, 0x00013A7C; + CHECKREG r6, 0x000C896D; + CHECKREG r7, 0x80BDBB92; + CHECKREG p1, 0x80BDBB92; + CHECKREG p2, 0x00049BBF; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x00013A7C; + + imm32 r0, 0x9aa64abd; + imm32 r1, 0xa1baf4c7; + imm32 r2, 0xb114a649; + imm32 r3, 0x0b010005; + imm32 r4, 0xefbcdb69; + imm32 r5, 0x123501bb; + imm32 r6, 0x000c0d1b; + imm32 r7, 0x678e0d01; + R5 = ( A1 += R5.L * R0.H ) (M), A0 = R5.L * R0.L (FU); + P1 = A1.w; + R1 = ( A1 = R1.L * R3.H ) (M), A0 = R1.H * R3.L (FU); + P2 = A1.w; + R3 = ( A1 -= R2.L * R6.H ) (M), A0 += R2.H * R6.H (FU); + P3 = A1.w; + R1 = ( A1 += R4.L * R7.H ) (M), A0 += R4.L * R7.H (FU); + P4 = A1.w; + CHECKREG r0, 0x9AA64ABD; + CHECKREG r1, 0xF0BBA999; + CHECKREG r2, 0xB114A649; + CHECKREG r3, 0xFF88B65B; + CHECKREG r4, 0xEFBCDB69; + CHECKREG r5, 0x010CD7BE; + CHECKREG r6, 0x000C0D1B; + CHECKREG r7, 0x678E0D01; + CHECKREG p1, 0x010CD7BE; + CHECKREG p2, 0xFF8481C7; + CHECKREG p3, 0xFF88B65B; + CHECKREG p4, 0xF0BBA999; + + imm32 r0, 0xd136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0xdd010007; + imm32 r4, 0xeddc1569; + imm32 r5, 0x122d010b; + imm32 r6, 0x00e3d01d; + imm32 r7, 0x678e0d61; + R5 = A1 , A0 = R1.L * R0.L (FU); + P1 = A1.w; + R7 = A1 , A0 = R2.H * R3.L (FU); + P2 = A1.w; + R1 = A1 , A0 += R4.H * R5.H (FU); + P3 = A1.w; + R5 = A1 , A0 += R6.L * R7.H (FU); + P4 = A1.w; + CHECKREG r0, 0xD136459D; + CHECKREG r1, 0xFFFFFFFF; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0xDD010007; + CHECKREG r4, 0xEDDC1569; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0x00E3D01D; + CHECKREG r7, 0xFFFFFFFF; + CHECKREG p1, 0xF0BBA999; + CHECKREG p2, 0xF0BBA999; + CHECKREG p3, 0xF0BBA999; + CHECKREG p4, 0xF0BBA999; + + imm32 r0, 0x125489bd; + imm32 r1, 0x91b5fec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910507; + imm32 r4, 0x34567859; + imm32 r5, 0xd2359105; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ) (M,FU); + P1 = A1.w; + R3 = ( A1 -= R2.H * R1.H ) (M,FU); + P2 = A1.w; + R5 = ( A1 = R7.H * R0.H ) (M,FU); + P3 = A1.w; + R7 = ( A1 += R4.H * R6.H ) (M,FU); + P4 = A1.w; + CHECKREG r0, 0x125489BD; + CHECKREG r1, 0xCB6CC99E; + CHECKREG r2, 0xA9145679; + CHECKREG r3, 0x107E992E; + CHECKREG r4, 0x34567859; + CHECKREG r5, 0x076FB0D8; + CHECKREG r6, 0x0D0C0999; + CHECKREG r7, 0x0A1A82E0; + CHECKREG p1, 0xCB6CC99E; + CHECKREG p2, 0x107E992E; + CHECKREG p3, 0x076FB0D8; + CHECKREG p4, 0x0A1A82E0; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0.s new file mode 100644 index 0000000..d7bd4b4 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0.s @@ -0,0 +1,152 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0/c_dsp32mac_pair_a1a0.dsp +// Spec Reference: dsp32mac pair a1a0 +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ); + FP = A1.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x0004BA9E; + CHECKREG r2, 0x00177258; + CHECKREG r3, 0x17A3558C; + CHECKREG r4, 0x0455E4F4; + CHECKREG r5, 0xFB35EDF0; + CHECKREG r6, 0xFF221DD6; + CHECKREG r7, 0xFF221DD6; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0xFF221DD6; + CHECKREG p3, 0x0004BA9E; + CHECKREG p4, 0xFFFB3578; + CHECKREG p5, 0x17A3558C; + CHECKREG sp, 0x00177258; + CHECKREG fp, 0xFB35EDF0; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 -= R2.H * R3.L ); + P2 = A0.w; + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ); + P5 = A1.w; + SP = A0.w; + R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ); + FP = A0.w; + CHECKREG r0, 0xF955783E; + CHECKREG r1, 0xFC03F6B2; + CHECKREG r2, 0xF93E0212; + CHECKREG r3, 0xFBEC8086; + CHECKREG r4, 0xF97279D6; + CHECKREG r5, 0x0449E564; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x0449E564; + CHECKREG p2, 0xF9762F0E; + CHECKREG p3, 0x0000AC92; + CHECKREG p4, 0xF9762F0E; + CHECKREG p5, 0xFBEC8086; + CHECKREG sp, 0xF93E0212; + CHECKREG fp, 0xF955783E; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ); + P1 = A1.w; + P2 = A0.w; + R7 = ( A1 -= R2.H * R3.L ), R6 = ( A0 -= R2.H * R3.L ); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H ); + FP = A0.w; + CHECKREG r0, 0xDFA7BA7E; + CHECKREG r1, 0xF66CBF80; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xEF9AE3A2; + CHECKREG r5, 0x004EF7CC; + CHECKREG r6, 0xCB19D6FE; + CHECKREG r7, 0xCE37E816; + CHECKREG p1, 0xCE3E172E; + CHECKREG p2, 0xCB200616; + CHECKREG p3, 0xCE37E816; + CHECKREG p5, 0xF66CBF80; + CHECKREG p4, 0xCB19D6FE; + CHECKREG sp, 0xDFA7BA7E; + CHECKREG fp, 0xEF9AE3A2; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 -= R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ); + P5 = A1.w; + SP = A0.w; + R7 = ( A1 -= R4.H * R6.H ), R6 = ( A0 -= R4.L * R6.H ); + FP = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0x114737D6; + CHECKREG r2, 0xDA154570; + CHECKREG r3, 0xF4447118; + CHECKREG r4, 0xDA0F974C; + CHECKREG r5, 0xF44A1F3C; + CHECKREG r6, 0xE4BBB02C; + CHECKREG r7, 0xF82827D4; + CHECKREG p1, 0x114737D6; + CHECKREG p2, 0xFFF9EE9A; + CHECKREG p3, 0xF4447118; + CHECKREG p4, 0xDA154570; + CHECKREG p5, 0xF44A1F3C; + CHECKREG sp, 0xDA0F974C; + CHECKREG fp, 0xE4BBB02C; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_i.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_i.s new file mode 100644 index 0000000..24d66fb --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_i.s @@ -0,0 +1,292 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_i/c_dsp32mac_pair_a1a0_i.dsp +// Spec Reference: dsp32mac pair a1a0 I +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (IS); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (IS); + FP = A1.w; + CHECKREG r0, 0xFFFD9ABC; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0x0004A9F4; + CHECKREG r3, 0x05E8D563; + CHECKREG r4, 0x0114469B; + CHECKREG r5, 0xFECD7B7C; + CHECKREG r6, 0xFF910EEB; + CHECKREG r7, 0xFF910EEB; + CHECKREG p1, 0xFF910EEB; + CHECKREG p2, 0xFF910EEB; + CHECKREG p3, 0x00025D4F; + CHECKREG p4, 0xFFFD9ABC; + CHECKREG p5, 0x05E8D563; + CHECKREG sp, 0x0004A9F4; + CHECKREG fp, 0xFECD7B7C; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 -= R2.H * R3.L ) (IS); + P2 = A0.w; + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (IS); + P5 = A1.w; + SP = A0.w; + R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (IS); + FP = A0.w; + CHECKREG r0, 0xFCBBE07C; + CHECKREG r1, 0xFF409C82; + CHECKREG r2, 0xFCB02566; + CHECKREG r3, 0xFF34E16C; + CHECKREG r4, 0xFCB93CEB; + CHECKREG r5, 0x03577736; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x03577736; + CHECKREG p2, 0xFCBB1787; + CHECKREG p3, 0x00005649; + CHECKREG p4, 0xFCBB1787; + CHECKREG p5, 0xFF34E16C; + CHECKREG sp, 0xFCB02566; + CHECKREG fp, 0xFCBBE07C; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R7 = ( A1 = R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 -= R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (IS); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H ) (IS); + FP = A0.w; + CHECKREG r0, 0x0273FCDC; + CHECKREG r1, 0xF76A2B8C; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x02744380; + CHECKREG r5, 0xF76A7230; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x0003178C; + CHECKREG p1, 0xE85DACC0; + CHECKREG p2, 0xE590030B; + CHECKREG p3, 0x0003178C; + CHECKREG p5, 0xF76A2B8C; + CHECKREG p4, 0x0003178C; + CHECKREG sp, 0x0273FCDC; + CHECKREG fp, 0x02744380; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 -= R2.H * R1.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (IS); + P5 = A1.w; + SP = A0.w; + R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (IS); + FP = A0.w; + CHECKREG r0, 0xFFFCF74D; + CHECKREG r1, 0xFFE69235; + CHECKREG r2, 0xDAB58E29; + CHECKREG r3, 0x0008D3F8; + CHECKREG r4, 0xDAB3EEB1; + CHECKREG r5, 0xFFFE6088; + CHECKREG r6, 0xD9D21BFD; + CHECKREG r7, 0xFE17B7EC; + CHECKREG p1, 0xFFE69235; + CHECKREG p2, 0xFFFCF74D; + CHECKREG p3, 0x0008D3F8; + CHECKREG p4, 0xDAB58E29; + CHECKREG p5, 0xFFFE6088; + CHECKREG sp, 0xDAB3EEB1; + CHECKREG fp, 0xD9D21BFD; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 -= R7.H * R4.H ) (IS); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (IS); + FP = A0.w; + CHECKREG r0, 0xFFFD9ABC; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0xFFD771FC; + CHECKREG r3, 0x16A6FC20; + CHECKREG r4, 0x00E70EA3; + CHECKREG r5, 0x1E76A239; + CHECKREG r6, 0xFF910EEB; + CHECKREG r7, 0xFDA8C6D7; + CHECKREG p1, 0xFDA8C6D7; + CHECKREG p2, 0xFF910EEB; + CHECKREG p3, 0x00025D4F; + CHECKREG p4, 0xFFFD9ABC; + CHECKREG p5, 0x16A6FC20; + CHECKREG sp, 0xFFD771FC; + CHECKREG fp, 0x00E70EA3; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = A1, R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R1 = A1, R0 = ( A0 = R2.H * R3.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R3 = A1, R2 = ( A0 -= R4.H * R5.H ) (IS); + P5 = A1.w; + SP = A0.w; + R1 = A1, R0 = ( A0 += R6.L * R7.H ) (IS); + FP = A1.w; + CHECKREG r0, 0x006DB534; + CHECKREG r1, 0x1E76A239; + CHECKREG r2, 0x0061FA1E; + CHECKREG r3, 0x1E76A239; + CHECKREG r4, 0xFCB93CEB; + CHECKREG r5, 0x1E76A239; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x1E76A239; + CHECKREG p2, 0xFCB93CEB; + CHECKREG p3, 0x1E76A239; + CHECKREG p4, 0xFFFE2564; + CHECKREG p5, 0x1E76A239; + CHECKREG sp, 0x0061FA1E; + CHECKREG fp, 0x1E76A239; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R7 = A1, R6 = ( A0 = R2.H * R3.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 += R4.H * R5.H ) (IS); + P5 = A1.w; + SP = A0.w; + R5 = A1, R4 = ( A0 -= R6.L * R7.H ) (IS); + FP = A1.w; + CHECKREG r0, 0xFF3AD93C; + CHECKREG r1, 0xED91D5F0; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xFE887FD8; + CHECKREG r5, 0xED91D5F0; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x0793B277; + CHECKREG p1, 0x0793B277; + CHECKREG p2, 0xE590030B; + CHECKREG p3, 0x0793B277; + CHECKREG p4, 0x0003178C; + CHECKREG p5, 0xED91D5F0; + CHECKREG sp, 0xFF3AD93C; + CHECKREG fp, 0xED91D5F0; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = A1, R0 = ( A0 = R5.L * R3.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (IS); + P5 = A0.w; + SP = A1.w; + R7 = A1, R6 = ( A0 += R4.L * R6.H ) (IS); + FP = A0.w; + CHECKREG r0, 0xFFFCF74D; + CHECKREG r1, 0xED91D5F0; + CHECKREG r2, 0x0E4826C0; + CHECKREG r3, 0xAF564854; + CHECKREG r4, 0x0E468748; + CHECKREG r5, 0x67DC6088; + CHECKREG r6, 0x081F86A8; + CHECKREG r7, 0x67DC6088; + CHECKREG p1, 0xED91D5F0; + CHECKREG p2, 0xFFFCF74D; + CHECKREG p3, 0xAF564854; + CHECKREG p4, 0x0E4826C0; + CHECKREG p5, 0x0E468748; + CHECKREG sp, 0x67DC6088; + CHECKREG fp, 0x081F86A8; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_is.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_is.s new file mode 100644 index 0000000..b719318 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_is.s @@ -0,0 +1,292 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_is/c_dsp32mac_pair_a1a0_is.dsp +// Spec Reference: dsp32mac pair a1a0 IS +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R4.L * R0.L ), R6 = ( A0 = R4.L * R0.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R3.L * R1.L ), R0 = ( A0 = R3.H * R1.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R7.L * R2.L ), R2 = ( A0 += R7.H * R2.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R5.L * R6.L ), R4 = ( A0 += R5.L * R6.H ) (ISS2); + FP = A1.w; + CHECKREG r0, 0xFFFEB854; + CHECKREG r1, 0xFFFFEEE2; + CHECKREG r2, 0xCECAD1AC; + CHECKREG r3, 0xB509D374; + CHECKREG r4, 0x8A4CA32E; + CHECKREG r5, 0x1EC2C250; + CHECKREG r6, 0x47E3910A; + CHECKREG r7, 0x47E3910A; + CHECKREG p1, 0x23F1C885; + CHECKREG p2, 0x23F1C885; + CHECKREG p3, 0xFFFFF771; + CHECKREG p4, 0xFFFF5C2A; + CHECKREG p5, 0xDA84E9BA; + CHECKREG sp, 0xE76568D6; + CHECKREG fp, 0x0F616128; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = ( A1 += R4.L * R0.H ), R4 = ( A0 = R4.L * R0.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (ISS2); + P2 = A0.w; + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R7.L * R5.H ), R2 = ( A0 += R7.H * R5.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R1 = ( A1 += R6.L * R1.H ), R0 = ( A0 += R6.L * R1.H ) (ISS2); + FP = A0.w; + CHECKREG r0, 0x0ADC2224; + CHECKREG r1, 0x00001AE2; + CHECKREG r2, 0x0ADC2224; + CHECKREG r3, 0x00001AE2; + CHECKREG r4, 0x0C80510A; + CHECKREG r5, 0x0D712F1C; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x06B8978E; + CHECKREG p2, 0xFFFE2564; + CHECKREG p3, 0x00005649; + CHECKREG p4, 0xFFFE2564; + CHECKREG p5, 0x00000D71; + CHECKREG sp, 0x056E1112; + CHECKREG fp, 0x056E1112; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R7 = ( A1 = R6.H * R3.L ), R6 = ( A0 = R6.H * R3.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R2.H * R7.L ), R4 = ( A0 += R2.L * R7.H ) (ISS2); + FP = A0.w; + CHECKREG r0, 0x12E88AAA; + CHECKREG r1, 0xE779EB80; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x12E88AAA; + CHECKREG r5, 0xE79F0610; + CHECKREG r6, 0x0000002A; + CHECKREG r7, 0x0000002A; + CHECKREG p1, 0xE91D1DAF; + CHECKREG p2, 0xE590030B; + CHECKREG p3, 0x00000015; + CHECKREG p5, 0xF3BCF5C0; + CHECKREG p4, 0x00000015; + CHECKREG sp, 0x09744555; + CHECKREG fp, 0x09744555; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (ISS2); + FP = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0xF897461A; + CHECKREG r2, 0xD0654810; + CHECKREG r3, 0x05083598; + CHECKREG r4, 0xD05F99EC; + CHECKREG r5, 0xFFFA51DC; + CHECKREG r6, 0xC5F8000C; + CHECKREG r7, 0xFB1F80C4; + CHECKREG p1, 0xFC4BA30D; + CHECKREG p2, 0xFFFCF74D; + CHECKREG p3, 0x02841ACC; + CHECKREG p4, 0xE832A408; + CHECKREG p5, 0xFFFD28EE; + CHECKREG sp, 0xE82FCCF6; + CHECKREG fp, 0xE2FC0006; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (ISS2); + FP = A0.w; + CHECKREG r0, 0xFFFB3578; + CHECKREG r1, 0x0004BA9E; + CHECKREG r2, 0x00B650E8; + CHECKREG r3, 0xB2D59E54; + CHECKREG r4, 0x04F4C384; + CHECKREG r5, 0xD21436B8; + CHECKREG r6, 0xFF221DD6; + CHECKREG r7, 0xFA419E9A; + CHECKREG p1, 0xFD20CF4D; + CHECKREG p2, 0xFF910EEB; + CHECKREG p3, 0x00025D4F; + CHECKREG p4, 0xFFFD9ABC; + CHECKREG p5, 0xD96ACF2A; + CHECKREG sp, 0x005B2874; + CHECKREG fp, 0x027A61C2; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = A1, R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R1 = A1, R0 = ( A0 = R4.H * R3.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R3 = A1, R2 = ( A0 += R2.H * R5.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R1 = A1, R0 = ( A0 += R6.L * R7.H ) (ISS2); + FP = A1.w; + CHECKREG r0, 0x22252FC0; + CHECKREG r1, 0xD21436B8; + CHECKREG r2, 0x220DB994; + CHECKREG r3, 0xD21436B8; + CHECKREG r4, 0xF97279D6; + CHECKREG r5, 0xD21436B8; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xE90A1B5C; + CHECKREG p2, 0xFCB93CEB; + CHECKREG p3, 0xE90A1B5C; + CHECKREG p4, 0xFFFFDF3A; + CHECKREG p5, 0xE90A1B5C; + CHECKREG sp, 0x1106DCCA; + CHECKREG fp, 0xE90A1B5C; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R7 = A1, R6 = ( A0 = R2.H * R3.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 += R4.H * R5.H ) (ISS2); + P5 = A1.w; + SP = A0.w; + R5 = A1, R4 = ( A0 += R6.L * R7.H ) (ISS2); + FP = A1.w; + CHECKREG r0, 0x25E6F698; + CHECKREG r1, 0xDBFA4500; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x042A6938; + CHECKREG r5, 0xDBFA4500; + CHECKREG r6, 0x00062F18; + CHECKREG r7, 0xA44E5734; + CHECKREG p1, 0xD2272B9A; + CHECKREG p2, 0xE590030B; + CHECKREG p3, 0xD2272B9A; + CHECKREG p4, 0x0003178C; + CHECKREG p5, 0xEDFD2280; + CHECKREG sp, 0x12F37B4C; + CHECKREG fp, 0xEDFD2280; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = A1, R0 = ( A0 = R5.L * R3.L ) (ISS2); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (ISS2); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (ISS2); + P5 = A0.w; + SP = A1.w; + R7 = A1, R6 = ( A0 += R4.L * R6.H ) (ISS2); + FP = A0.w; + CHECKREG r0, 0xFFF9EE9A; + CHECKREG r1, 0xDBFA4500; + CHECKREG r2, 0xD124C800; + CHECKREG r3, 0x80000000; + CHECKREG r4, 0xD11F19DC; + CHECKREG r5, 0x7FFFFFFF; + CHECKREG r6, 0xD3C1DE7C; + CHECKREG r7, 0x7FFFFFFF; + CHECKREG p1, 0xEDFD2280; + CHECKREG p2, 0xFFFCF74D; + CHECKREG p3, 0xB54F3988; + CHECKREG p4, 0xE8926400; + CHECKREG p5, 0xE88F8CEE; + CHECKREG sp, 0x67DB28EE; + CHECKREG fp, 0xE9E0EF3E; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_m.s new file mode 100644 index 0000000..2725fa9 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_m.s @@ -0,0 +1,152 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_m/c_dsp32mac_pair_a1a0_m.dsp +// Spec Reference: dsp32mac pair a1a0 M MNOP +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R0.L * R1.L ) (M), R6 = ( A0 = R0.L * R1.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R3.L * R2.L ) (M), R0 = ( A0 = R3.H * R2.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R7.L * R6.L ) (M), R2 = ( A0 += R7.H * R6.H ) (IS); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R5.L * R4.L ) (M), R4 = ( A0 += R5.L * R4.H ) (IS); + FP = A0.w; + CHECKREG r0, 0x002D4356; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0x00061B84; + CHECKREG r3, 0xFF23D196; + CHECKREG r4, 0x07C7B86C; + CHECKREG r5, 0xCED42319; + CHECKREG r6, 0xFF910EEB; + CHECKREG r7, 0x5A4E0EEB; + CHECKREG p1, 0x5A4E0EEB; + CHECKREG p2, 0xFF910EEB; + CHECKREG p3, 0x00025D4F; + CHECKREG p4, 0x002D4356; + CHECKREG p5, 0xFF23D196; + CHECKREG sp, 0x00061B84; + CHECKREG fp, 0x07C7B86C; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = A1, R4 = ( A0 = R3.L * R1.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R1 = A1, R0 = ( A0 -= R0.H * R5.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R3 = A1, R2 = ( A0 += R2.H * R7.H ) (IS); + P5 = A1.w; + SP = A0.w; + R1 = A1, R0 = ( A0 -= R4.L * R6.H ) (IS); + FP = A1.w; + CHECKREG r0, 0xE7CEC8D1; + CHECKREG r1, 0xCED42319; + CHECKREG r2, 0xE7CC2775; + CHECKREG r3, 0xCED42319; + CHECKREG r4, 0xFFFFC7E3; + CHECKREG r5, 0xCED42319; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xCED42319; + CHECKREG p2, 0xFFFFC7E3; + CHECKREG p3, 0xCED42319; + CHECKREG p4, 0x0E31C25D; + CHECKREG p5, 0xCED42319; + CHECKREG sp, 0xE7CC2775; + CHECKREG fp, 0xCED42319; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R4.H * R3.L ) (M), R4 = ( A0 = R4.L * R3.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R7 = A1, R6 = ( A0 = R5.H * R0.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R2.H * R6.L ) (M), R0 = ( A0 += R2.H * R6.H ) (IS); + P5 = A1.w; + SP = A0.w; + R5 = A1, R4 = ( A0 += R7.L * R1.H ) (IS); + FP = A1.w; + CHECKREG r0, 0xECB84AE7; + CHECKREG r1, 0x5091B70C; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0xD3A83F94; + CHECKREG r5, 0x5091B70C; + CHECKREG r6, 0xF2A0B667; + CHECKREG r7, 0xCED3B05D; + CHECKREG p1, 0xCED3B05D; + CHECKREG p2, 0x000095DF; + CHECKREG p3, 0xCED3B05D; + CHECKREG p4, 0xF2A0B667; + CHECKREG p5, 0x5091B70C; + CHECKREG sp, 0xECB84AE7; + CHECKREG fp, 0x5091B70C; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = A1, R0 = ( A0 = R5.L * R2.L ) (IS); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R3.H * R1.H ) (M), R2 = ( A0 -= R3.H * R1.L ) (IS); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (IS); + P5 = A0.w; + SP = A1.w; + R7 = A1, R6 = ( A0 += R4.L * R6.H ) (IS); + FP = A0.w; + CHECKREG r0, 0xDA854033; + CHECKREG r1, 0x5091B70C; + CHECKREG r2, 0xCD00D267; + CHECKREG r3, 0xF1127221; + CHECKREG r4, 0xBDCBD4BD; + CHECKREG r5, 0x58A90256; + CHECKREG r6, 0xBB976699; + CHECKREG r7, 0x58A90256; + CHECKREG p1, 0x5091B70C; + CHECKREG p2, 0xDA854033; + CHECKREG p3, 0xF1127221; + CHECKREG p4, 0xCD00D267; + CHECKREG p5, 0xBDCBD4BD; + CHECKREG sp, 0x58A90256; + CHECKREG fp, 0xBB976699; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_s.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_s.s new file mode 100644 index 0000000..ce66ae0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_s.s @@ -0,0 +1,306 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_s/c_dsp32mac_pair_a1a0_s.dsp +// Spec Reference: dsp32mac pair a1a0 S +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (S2RND); + FP = A1.w; + CHECKREG r0, 0xFFF66AF0; + CHECKREG r1, 0x0009753C; + CHECKREG r2, 0x00675E70; + CHECKREG r3, 0x5E8D5630; + CHECKREG r4, 0x116128E0; + CHECKREG r5, 0xECD7B7C0; + CHECKREG r6, 0xFE443BAC; + CHECKREG r7, 0xFE443BAC; + CHECKREG p1, 0xFF221DD6; + CHECKREG p2, 0xFF221DD6; + CHECKREG p3, 0x0004BA9E; + CHECKREG p4, 0xFFFB3578; + CHECKREG p5, 0x2F46AB18; + CHECKREG sp, 0x0033AF38; + CHECKREG fp, 0xF66BDBE0; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A0 = R2; + A1 = R3; + R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (S2RND); + P2 = A0.w; + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (S2RND); + FP = A0.w; + CHECKREG r0, 0xFC6F3BF8; + CHECKREG r1, 0xFCAF6688; + CHECKREG r2, 0xFC404FA0; + CHECKREG r3, 0xFC807A30; + CHECKREG r4, 0xF2E4F3AC; + CHECKREG r5, 0x1229EEF2; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x0914F779; + CHECKREG p2, 0xFFFC4AC8; + CHECKREG p3, 0x0000AC92; + CHECKREG p4, 0xFFFC4AC8; + CHECKREG p5, 0xFE403D18; + CHECKREG sp, 0xFE2027D0; + CHECKREG fp, 0xFE379DFC; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A0 = R0; + A1 = R1; + R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R7 = ( A1 = R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H ) (S2RND); + FP = A0.w; + CHECKREG r0, 0x7FFFFFFF; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x7FFFFFFF; + CHECKREG r5, 0x0011A900; + CHECKREG r6, 0x000C5E30; + CHECKREG r7, 0x000C5E30; + CHECKREG p1, 0x7E10BF43; + CHECKREG p2, 0xCB200616; + CHECKREG p3, 0x00062F18; + CHECKREG p5, 0x00000000; + CHECKREG p4, 0x00062F18; + CHECKREG sp, 0x69C62F18; + CHECKREG fp, 0x69CF0398; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A0 = R0; + A1 = R1; + R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (S2RND); + FP = A0.w; + CHECKREG r0, 0xFFF3DD34; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x7FFFFFFF; + CHECKREG r4, 0xFFEAE6E8; + CHECKREG r5, 0xFFEAE6E8; + CHECKREG r6, 0xFACD5268; + CHECKREG r7, 0xFFE66AC8; + CHECKREG p1, 0xA2B53ED1; + CHECKREG p2, 0xFFF9EE9A; + CHECKREG p3, 0x56EC0000; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0xFFF57374; + CHECKREG sp, 0xFFF57374; + CHECKREG fp, 0xFD66A934; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + A0 = R0; + A1 = R1; + R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 -= R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (S2RND); + FP = A0.w; + CHECKREG r0, 0xFFF66AF0; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x20866AF0; + CHECKREG r3, 0x80000000; + CHECKREG r4, 0x31803560; + CHECKREG r5, 0x80000000; + CHECKREG r6, 0xFE443BAC; + CHECKREG r7, 0x80000000; + CHECKREG p1, 0x864E0DB2; + CHECKREG p2, 0xFF221DD6; + CHECKREG p3, 0x864BB063; + CHECKREG p4, 0xFFFB3578; + CHECKREG p5, 0x864BB063; + CHECKREG sp, 0x10433578; + CHECKREG fp, 0x18C01AB0; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + A0 = R0; + A1 = R1; + R5 = A1, R4 = ( A0 = R3.L * R0.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R1 = A1, R0 = ( A0 = R2.H * R1.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R3 = A1, R2 = ( A0 += R7.H * R5.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R1 = A1, R0 = ( A0 += R4.L * R6.H ) (S2RND); + FP = A1.w; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x80000000; + CHECKREG r3, 0x80000000; + CHECKREG r4, 0x0005D6C4; + CHECKREG r5, 0x80000000; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0xA1BCF4C7; + CHECKREG p2, 0x0002EB62; + CHECKREG p3, 0xA1BCF4C7; + CHECKREG p4, 0x08528D18; + CHECKREG p5, 0xA1BCF4C7; + CHECKREG sp, 0xA0C48D18; + CHECKREG fp, 0xA1BCF4C7; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + A0 = R0; + A1 = R1; + R5 = ( A1 += R1.H * R6.L ) (M), R4 = ( A0 = R1.L * R6.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R7 = A1, R6 = ( A0 -= R4.H * R3.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R2.H * R5.L ) (M), R0 = ( A0 += R2.H * R5.H ) (S2RND); + P5 = A1.w; + SP = A0.w; + R5 = A1, R4 = ( A0 += R0.L * R7.H ) (S2RND); + FP = A1.w; + CHECKREG r0, 0x80000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x80000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x9EA59954; + CHECKREG r7, 0x80000000; + CHECKREG p1, 0x96C29605; + CHECKREG p2, 0xCF4D7916; + CHECKREG p3, 0x96C29605; + CHECKREG p4, 0xCF52CCAA; + CHECKREG p5, 0x00000000; + CHECKREG sp, 0x5E3ECCAA; + CHECKREG fp, 0x00000000; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + A0 = R0; + A1 = R1; + R1 = A1, R0 = ( A0 -= R5.L * R3.L ) (S2RND); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 -= R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (S2RND); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 -= R7.H * R0.H ) (S2RND); + P5 = A0.w; + SP = A1.w; + R7 = A1, R6 = ( A0 += R4.L * R6.H ) (S2RND); + FP = A0.w; + CHECKREG r0, 0x24753646; + CHECKREG r1, 0x80000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x80000000; + CHECKREG r4, 0xC4D53E28; + CHECKREG r5, 0x1D9560EC; + CHECKREG r6, 0xD18105A8; + CHECKREG r7, 0x1D9560EC; + CHECKREG p1, 0x91BCFEC7; + CHECKREG p2, 0x123A9B23; + CHECKREG p3, 0xBD32FEC7; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0xE26A9F14; + CHECKREG sp, 0x0ECAB076; + CHECKREG fp, 0xE8C082D4; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_u.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_u.s new file mode 100644 index 0000000..1b2707e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_u.s @@ -0,0 +1,292 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_u/c_dsp32mac_pair_a1a0_u.dsp +// Spec Reference: dsp32mac pair a1a0 U +# mach: bfin + +.include "testutils.inc" + start + + A1 = A0 = 0; + +// The result accumulated in A , and stored to a reg half + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (FU); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (FU); + FP = A1.w; + CHECKREG r0, 0x00049ABC; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0x549454CC; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x55A3F173; + CHECKREG r5, 0x07CFA619; + CHECKREG r6, 0x5A4E0EEB; + CHECKREG r7, 0x5A4E0EEB; + CHECKREG p1, 0x5A4E0EEB; + CHECKREG p2, 0x5A4E0EEB; + CHECKREG p3, 0x00025D4F; + CHECKREG p4, 0x00049ABC; + CHECKREG p5, 0x00000000; + CHECKREG sp, 0x549454CC; + CHECKREG fp, 0x07CFA619; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 -= R1.L * R0.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 -= R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (FU); + P2 = A0.w; + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 = R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (FU); + P5 = A1.w; + SP = A0.w; + R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (FU); + FP = A0.w; + CHECKREG r0, 0x089013D8; + CHECKREG r1, 0x6C5ACAC6; + CHECKREG r2, 0x088458C2; + CHECKREG r3, 0x6C4F0FB0; + CHECKREG r4, 0x0E2DB488; + CHECKREG r5, 0x9996A1D3; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x9996A1D3; + CHECKREG p2, 0x00032564; + CHECKREG p3, 0x99964B8A; + CHECKREG p4, 0x00032564; + CHECKREG p5, 0x6C4F0FB0; + CHECKREG sp, 0x088458C2; + CHECKREG fp, 0x089013D8; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R7 = ( A1 -= R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (FU); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 -= R6.L * R7.H ) (FU); + FP = A0.w; + CHECKREG r0, 0x1A2AB610; + CHECKREG r1, 0x24F02BB4; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x0BE761C4; + CHECKREG r5, 0x24F2761C; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x9B11C378; + CHECKREG p1, 0x9B14DB04; + CHECKREG p2, 0x2B2D030B; + CHECKREG p3, 0x9B11C378; + CHECKREG p5, 0x24F02BB4; + CHECKREG p4, 0x0003178C; + CHECKREG sp, 0x1A2AB610; + CHECKREG fp, 0x0BE761C4; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 -= R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 -= R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (FU); + P5 = A1.w; + SP = A0.w; + R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (FU); + FP = A0.w; + CHECKREG r0, 0x0003F74D; + CHECKREG r1, 0xD0349621; + CHECKREG r2, 0x63278394; + CHECKREG r3, 0x46B1FE11; + CHECKREG r4, 0x6328BB2E; + CHECKREG r5, 0x46B0C677; + CHECKREG r6, 0x6CB2D756; + CHECKREG r7, 0x4BBE7457; + CHECKREG p1, 0xD0349621; + CHECKREG p2, 0x0003F74D; + CHECKREG p3, 0x46B1FE11; + CHECKREG p4, 0x63278394; + CHECKREG p5, 0x46B0C677; + CHECKREG sp, 0x6328BB2E; + CHECKREG fp, 0x6CB2D756; + + imm32 r0, 0x63545abd; + imm32 r1, 0x86bcfec7; + imm32 r2, 0xa8645679; + imm32 r3, 0x00860007; + imm32 r4, 0xefb86569; + imm32 r5, 0x1235860b; + imm32 r6, 0x000c086d; + imm32 r7, 0x678e0086; + R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (FU); + P5 = A1.w; + SP = A0.w; + R5 = ( A1 -= R6.L * R5.L ) (M), R4 = ( A0 -= R6.L * R5.H ) (FU); + FP = A0.w; + CHECKREG r0, 0x00049ABC; + CHECKREG r1, 0x00025D4F; + CHECKREG r2, 0x46897C84; + CHECKREG r3, 0x316C7D3D; + CHECKREG r4, 0x4579DFDD; + CHECKREG r5, 0x299CD724; + CHECKREG r6, 0x5A4E0EEB; + CHECKREG r7, 0x4B4F8342; + CHECKREG p1, 0x4B4F8342; + CHECKREG p2, 0x5A4E0EEB; + CHECKREG p3, 0x00025D4F; + CHECKREG p4, 0x00049ABC; + CHECKREG p5, 0x316C7D3D; + CHECKREG sp, 0x46897C84; + CHECKREG fp, 0x4579DFDD; + + imm32 r0, 0x98764abd; + imm32 r1, 0xa1bcf4c7; + imm32 r2, 0xa1145649; + imm32 r3, 0x00010005; + imm32 r4, 0xefbc1569; + imm32 r5, 0x1235010b; + imm32 r6, 0x000c001d; + imm32 r7, 0x678e0001; + R5 = A1, R4 = ( A0 = R1.L * R0.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R1 = A1, R0 = ( A0 -= R2.H * R3.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R3 = A1, R2 = ( A0 += R4.H * R5.H ) (FU); + P5 = A1.w; + SP = A0.w; + R1 = A1, R0 = ( A0 -= R6.L * R7.H ) (FU); + FP = A1.w; + CHECKREG r0, 0x5304CE59; + CHECKREG r1, 0x299CD724; + CHECKREG r2, 0x5310896F; + CHECKREG r3, 0x299CD724; + CHECKREG r4, 0x47763CEB; + CHECKREG r5, 0x299CD724; + CHECKREG r6, 0x000C001D; + CHECKREG r7, 0x678E0001; + CHECKREG p1, 0x299CD724; + CHECKREG p2, 0x47763CEB; + CHECKREG p3, 0x299CD724; + CHECKREG p4, 0x47731787; + CHECKREG p5, 0x299CD724; + CHECKREG sp, 0x5310896F; + CHECKREG fp, 0x299CD724; + + imm32 r0, 0x7136459d; + imm32 r1, 0xabd69ec7; + imm32 r2, 0x71145679; + imm32 r3, 0x08010007; + imm32 r4, 0xef9c1569; + imm32 r5, 0x1225010b; + imm32 r6, 0x0003401d; + imm32 r7, 0x678e0561; + R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R7 = A1, R6 = ( A0 = R2.H * R3.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 -= R4.H * R5.H ) (FU); + P5 = A1.w; + SP = A0.w; + R5 = A1, R4 = ( A0 += R6.L * R7.H ) (FU); + FP = A1.w; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x2706223A; + CHECKREG r2, 0x71145679; + CHECKREG r3, 0x08010007; + CHECKREG r4, 0x01B8DC2C; + CHECKREG r5, 0x2706223A; + CHECKREG r6, 0x0003178C; + CHECKREG r7, 0x12B9E762; + CHECKREG p1, 0x12B9E762; + CHECKREG p2, 0x2B2D030B; + CHECKREG p3, 0x12B9E762; + CHECKREG p4, 0x0003178C; + CHECKREG p5, 0x2706223A; + CHECKREG sp, 0x00000000; + CHECKREG fp, 0x2706223A; + + imm32 r0, 0x123489bd; + imm32 r1, 0x91bcfec7; + imm32 r2, 0xa9145679; + imm32 r3, 0xd0910007; + imm32 r4, 0xedb91569; + imm32 r5, 0xd235910b; + imm32 r6, 0x0d0c0999; + imm32 r7, 0x67de0009; + R1 = A1, R0 = ( A0 -= R5.L * R3.L ) (FU); + P1 = A1.w; + P2 = A0.w; + R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (FU); + P3 = A1.w; + P4 = A0.w; + R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (FU); + P5 = A0.w; + SP = A1.w; + R7 = A1, R6 = ( A0 += R4.L * R6.H ) (FU); + FP = A0.w; + CHECKREG r0, 0x01B4E4DF; + CHECKREG r1, 0x2706223A; + CHECKREG r2, 0x169AF688; + CHECKREG r3, 0xF2C00278; + CHECKREG r4, 0x174BDCA0; + CHECKREG r5, 0x00B0E618; + CHECKREG r6, 0x228A5420; + CHECKREG r7, 0x00B0E618; + CHECKREG p1, 0x2706223A; + CHECKREG p2, 0x01B4E4DF; + CHECKREG p3, 0xF2C00278; + CHECKREG p4, 0x169AF688; + CHECKREG p5, 0x174BDCA0; + CHECKREG sp, 0x00B0E618; + CHECKREG fp, 0x228A5420; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_pair_mix.s b/sim/testsuite/sim/bfin/c_dsp32mac_pair_mix.s new file mode 100644 index 0000000..714fedd --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mac_pair_mix.s @@ -0,0 +1,69 @@ +//Original:/testcases/core/c_dsp32mac_pair_mix/c_dsp32mac_pair_mix.dsp +// Spec Reference: dsp32mac pair mix +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00060007; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; + +A0 = 0; +ASTAT = R0; +// The result accumulated in A0 and A1, and stored to a reg pair +imm32 r0, 0x00120034; +imm32 r1, 0x00050006; + +R3 = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L; +R5 = ( A1 = R1.L * R0.H ); +R7 = ( A1 = R1.L * R0.H ) (M), A0 = R1.H * R0.L; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x000000d8; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x000000d8; +CHECKREG r6, 0x000C000D; +CHECKREG r7, 0x0000006c; +A1 = R1.L * R0.H, R2 = ( A0 += R1.H * R0.L ); +A1 = R1.L * R0.H (M), R6 = ( A0 -= R1.H * R0.L ); +CHECKREG r2, 0x00000410; +CHECKREG r3, 0x000000d8; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x000000d8; +CHECKREG r6, 0x00000208; +CHECKREG r7, 0x0000006c; +R3 = ( A1 = R1.L * R0.H ), R2 = ( A0 += R1.H * R0.L ) (S2RND); +R5 = ( A1 = R1.L * R0.H ) (M), R4 = ( A0 -= R1.H * R0.L ) (S2RND); +CHECKREG r2, 0x00000820; +CHECKREG r3, 0x000001B0; +CHECKREG r4, 0x00000410; +CHECKREG r5, 0x000000D8; + +imm32 r0, 0x12345678; +imm32 r1, 0x34567897; +imm32 r2, 0x0acb1234; +imm32 r3, 0x456acb07; +imm32 r4, 0x421dbc09; +imm32 r5, 0x89acbd0b; +imm32 r6, 0x5adbcd0d; +imm32 r7, 0x9abc230f; +A1 += R7.L * R5.H, R2 = ( A0 = R7.H * R5.L ); +A1 -= R1.H * R2.L (M), R6 = ( A0 += R1.L * R2.H ) (S2RND); +CHECKREG r0, 0x12345678; +CHECKREG r1, 0x34567897; +CHECKREG r2, 0x34F8E428; +CHECKREG r3, 0x456ACB07; +CHECKREG r4, 0x421DBC09; +CHECKREG r5, 0x89ACBD0B; +CHECKREG r6, 0x7FFFFFFF; +CHECKREG r7, 0x9ABC230F; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr.s new file mode 100644 index 0000000..5ae44cb --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr/c_dsp32mult_dr.dsp +// Spec Reference: dsp32mult single dr +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x93ba5127; +imm32 r2, 0xa3446725; +imm32 r3, 0x00050027; +imm32 r4, 0xb0ab6d29; +imm32 r5, 0x10ace72b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467029; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L; +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H; +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L; +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H; +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L; +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H; +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L; +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H; +CHECKREG r0, 0x39FA39FA; +CHECKREG r1, 0x24C2CEF5; +CHECKREG r2, 0xE9C910A6; +CHECKREG r3, 0x12CA0A8E; +CHECKREG r4, 0x39FA39FA; +CHECKREG r5, 0x369EB722; +CHECKREG r6, 0x369EB722; +CHECKREG r7, 0x33735B96; + +imm32 r0, 0x5b33a635; +imm32 r1, 0x6fbe5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x9006d037; +imm32 r4, 0x80abcb39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c00dd; +imm32 r7, 0x12469003; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L; +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H; +R6.H = R3.L * R2.H, R6.L = R3.L * R2.L; +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H; +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L; +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H; +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L; +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H; +CHECKREG r0, 0xFF31FF31; +CHECKREG r1, 0x00B500B5; +CHECKREG r2, 0xF51DF51D; +CHECKREG r3, 0x09860986; +CHECKREG r4, 0xF51DF51D; +CHECKREG r5, 0x3FAEEF41; +CHECKREG r6, 0xF8DB1B2D; +CHECKREG r7, 0x29CE29CE; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L; +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H; +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L; +R3.H = R5.H * R5.L, R3.L = R5.H * R5.H; +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L; +R5.H = R4.H * R5.L, R5.L = R4.L * R5.H; +R6.H = R5.H * R4.L, R6.L = R5.H * R4.L; +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H; +CHECKREG r0, 0x33491B2A; +CHECKREG r1, 0x0E7AF852; +CHECKREG r2, 0xF852F852; +CHECKREG r3, 0xFDD5022C; +CHECKREG r4, 0x33491B2A; +CHECKREG r5, 0xF955038A; +CHECKREG r6, 0xFE96FE96; +CHECKREG r7, 0xFFD10059; + +imm32 r0, 0xab235666; +imm32 r1, 0xeaba5166; +imm32 r2, 0x13d48766; +imm32 r3, 0xf00b0066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10ac5f6b; +imm32 r6, 0x800cb66d; +imm32 r7, 0x1246707f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L; +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H; +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L; +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H; +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L; +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H; +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L; +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H; +CHECKREG r0, 0x7FE82A4A; +CHECKREG r1, 0xEDBCF57F; +CHECKREG r2, 0xEDBCF57F; +CHECKREG r3, 0x029C029C; +CHECKREG r4, 0x12400609; +CHECKREG r5, 0x029B029B; +CHECKREG r6, 0x7FE82A4A; +CHECKREG r7, 0x1243060A; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0.H = R0.L * R7.H (M), R0.L = R0.H * R7.L; +R1.H = R1.H * R6.H, R1.L = R1.H * R6.H; +R2.H = R2.H * R5.L, R2.L = R2.L * R5.L; +R3.H = R3.H * R4.L (M), R3.L = R3.H * R4.L; +R4.H = R4.L * R3.L, R4.L = R4.L * R3.H; +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L; +R6.H = R6.L * R1.H, R6.L = R6.L * R1.L; +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H; +CHECKREG r0, 0xF99C0A92; +CHECKREG r1, 0xFFFBFFFB; +CHECKREG r2, 0xFB31E621; +CHECKREG r3, 0x0005FFFE; +CHECKREG r4, 0x0001FFFE; +CHECKREG r5, 0xFCA1FCA1; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x0182FF16; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946905; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d9d; +imm32 r7, 0x12467009; +R0.H = R7.H * R0.H, R0.L = R7.L * R0.L; +R1.H = R6.H * R1.L (M), R1.L = R6.H * R1.L; +R2.H = R5.H * R2.H, R2.L = R5.L * R2.L; +R3.H = R4.L * R3.H, R3.L = R4.H * R3.L; +R4.H = R3.H * R4.H, R4.L = R3.L * R4.L; +R5.H = R2.H * R5.L (M), R5.L = R2.H * R5.L; +R6.H = R1.L * R6.L, R6.L = R1.L * R6.H; +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H; +CHECKREG r0, 0xF19A4F2D; +CHECKREG r1, 0x00040008; +CHECKREG r2, 0x028DEDD5; +CHECKREG r3, 0xFFF9FFFA; +CHECKREG r4, 0x00060005; +CHECKREG r5, 0x0255FF8F; +CHECKREG r6, 0x00010000; +CHECKREG r7, 0x0B4EFDF2; + +imm32 r0, 0x8b235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0x00080007; +imm32 r4, 0x90ab8d09; +imm32 r5, 0x10ace8db; +imm32 r6, 0x000c008d; +imm32 r7, 0x12467008; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H; +R3.H = R1.H * R7.H (M), R3.L = R1.L * R7.L; +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H; +R1.H = R3.H * R1.L, R1.L = R3.L * R1.H; +R4.H = R4.L * R2.L, R4.L = R4.L * R2.H; +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L; +R6.H = R6.H * R4.L (M), R6.L = R6.L * R4.H; +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H; +CHECKREG r0, 0x0005FFA9; +CHECKREG r1, 0xFD80E154; +CHECKREG r2, 0x005F0008; +CHECKREG r3, 0xFC0E4707; +CHECKREG r4, 0xFFF9FFAB; +CHECKREG r5, 0x00B70940; +CHECKREG r6, 0x000C0000; +CHECKREG r7, 0x0819001A; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H; +R6.H = R6.H * R3.L (M), R6.L = R6.L * R3.H; +R0.H = R7.L * R4.H, R0.L = R7.H * R4.H; +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L; +R2.H = R1.H * R6.L (M), R2.L = R1.L * R6.H; +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L; +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H; +R7.H = R4.L * R1.L, R7.L = R4.L * R1.H; +CHECKREG r0, 0xF3ECFE08; +CHECKREG r1, 0xFFBE0044; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x0000FFFF; +CHECKREG r4, 0xF234FD56; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFFFF0001; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_i.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_i.s new file mode 100644 index 0000000..b0b34d5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_i.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_i/c_dsp32mult_dr_i.dsp +// Spec Reference: dsp32mult single dr i +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IS); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IS); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IS); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IS); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IS); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IS); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IS); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IS); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF8000; +CHECKREG r2, 0x80007FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0x8923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1824b735; +imm32 r3, 0x99860037; +imm32 r4, 0x8098cd39; +imm32 r5, 0xb0a98f3b; +imm32 r6, 0xa00c083d; +imm32 r7, 0x12467083; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IS); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IS); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IS); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IS); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IS); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IS); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IS); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IS); +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x80007FFF; +CHECKREG r7, 0x80008000; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IS); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IS); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IS); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IS); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IS); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IS); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IS); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IS); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF8000; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x80008000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xe0060066; +imm32 r4, 0x9eab9d69; +imm32 r5, 0x10ecef6b; +imm32 r6, 0x800ee06d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IS); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IS); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IS); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IS); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IS); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IS); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IS); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IS); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x80008000; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x7FFF7FFF; + +// mix order +imm32 r0, 0xac23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13c46705; +imm32 r3, 0xf0060007; +imm32 r4, 0x9faccd09; +imm32 r5, 0x10fcdfdb; +imm32 r6, 0x000fc00d; +imm32 r7, 0x1246ff0f; +R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (IS); +R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IS); +R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IS); +R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IS); +R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IS); +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IS); +R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IS); +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IS); +CHECKREG r0, 0x7FFF8000; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x80008000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x80007FFF; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R5.H * R0.H, R0.L = R5.H * R0.L (IS); +R1.H = R6.H * R1.L, R1.L = R6.L * R1.L (IS); +R2.H = R7.H * R2.H, R2.L = R7.H * R2.H (IS); +R3.H = R0.L * R3.H, R3.L = R0.H * R3.L (IS); +R4.H = R1.H * R4.H, R4.L = R1.L * R4.L (IS); +R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (IS); +R6.H = R3.H * R6.H, R6.L = R3.L * R6.L (IS); +R7.H = R4.L * R7.H, R7.L = R4.H * R7.H (IS); +CHECKREG r0, 0x80007FFF; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x80007FFF; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x80008000; + +imm32 r0, 0xfb235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13f46705; +imm32 r3, 0x000f0007; +imm32 r4, 0x90abfd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IS); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IS); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IS); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IS); +R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IS); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IS); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IS); +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IS); +CHECKREG r0, 0x7FFF8000; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x80007FFF; + +imm32 r0, 0xab2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13246d05; +imm32 r3, 0x000600d7; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c500d; +imm32 r7, 0x1246760f; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (IS); +R6.H = R6.H * R3.L, R6.L = R6.H * R3.H (IS); +R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (IS); +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (IS); +R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (IS); +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (IS); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (IS); +R7.H = R4.H * R1.L, R7.L = R4.H * R1.H (IS); +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x0A140048; +CHECKREG r7, 0x80007FFF; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_ih.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_ih.s new file mode 100644 index 0000000..5236375 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_ih.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_ih/c_dsp32mult_dr_ih.dsp +// Spec Reference: dsp32mult single dr ih +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IH); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IH); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IH); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IH); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IH); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IH); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IH); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IH); +CHECKREG r0, 0x1CFD1CFD; +CHECKREG r1, 0x0930F44E; +CHECKREG r2, 0xFEAD010A; +CHECKREG r3, 0x00890054; +CHECKREG r4, 0x1CFD1CFD; +CHECKREG r5, 0x1B4FDD40; +CHECKREG r6, 0x1B4FDD40; +CHECKREG r7, 0x19BA29A9; + +imm32 r0, 0x9923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1324b735; +imm32 r3, 0x99060037; +imm32 r4, 0x809bcd39; +imm32 r5, 0xb0a99f3b; +imm32 r6, 0xa00c093d; +imm32 r7, 0x12467093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IH); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IH); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IH); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IH); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IH); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IH); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IH); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IH); +CHECKREG r0, 0xFFF4FFF4; +CHECKREG r1, 0x00050005; +CHECKREG r2, 0xFA8FFA8F; +CHECKREG r3, 0x02300230; +CHECKREG r4, 0xFA8FFA8F; +CHECKREG r5, 0x1D48F84D; +CHECKREG r6, 0xFFF00004; +CHECKREG r7, 0xFFEAFFEA; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IH); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IH); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IH); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IH); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IH); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IH); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IH); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IH); +CHECKREG r0, 0x19A50D95; +CHECKREG r1, 0x073DFC29; +CHECKREG r2, 0xFC29FC29; +CHECKREG r3, 0x01150116; +CHECKREG r4, 0x19A50D95; +CHECKREG r5, 0xFE55FF1E; +CHECKREG r6, 0xFFF4FFE9; +CHECKREG r7, 0x00010003; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xe0060066; +imm32 r4, 0x9eab9d69; +imm32 r5, 0x10ecef6b; +imm32 r6, 0x800ee06d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IH); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IH); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IH); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IH); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IH); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IH); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IH); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IH); +CHECKREG r0, 0x3FF203E5; +CHECKREG r1, 0xF6DEFDBF; +CHECKREG r2, 0xF6DEFDBF; +CHECKREG r3, 0x014E014E; +CHECKREG r4, 0x01240012; +CHECKREG r5, 0x00150015; +CHECKREG r6, 0x3FF203E5; +CHECKREG r7, 0x04910047; + +// mix order +imm32 r0, 0xac23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13c46705; +imm32 r3, 0x00060007; +imm32 r4, 0x90accd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000cc00d; +imm32 r7, 0x1246fc0f; +R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (IH); +R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IH); +R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IH); +R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IH); +R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IH); +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IH); +R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IH); +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IH); +CHECKREG r0, 0x0161FA04; +CHECKREG r1, 0xEBBA0004; +CHECKREG r2, 0xFD85FD85; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0xFFD7FFD7; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFF930019; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (IH); +R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (IH); +R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (IH); +R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (IH); +R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (IH); +R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (IH); +R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (IH); +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (IH); +CHECKREG r0, 0xF9F10675; +CHECKREG r1, 0xFFFE0423; +CHECKREG r2, 0xFDBB06D7; +CHECKREG r3, 0xFFA314DD; +CHECKREG r4, 0x00280013; +CHECKREG r5, 0xFFDA0029; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x0076FF91; + +imm32 r0, 0xfb235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13f46705; +imm32 r3, 0x000f0007; +imm32 r4, 0x90abfd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IH); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IH); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IH); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IH); +R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IH); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IH); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IH); +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IH); +CHECKREG r0, 0x0001FFFE; +CHECKREG r1, 0xF94D00A6; +CHECKREG r2, 0x00550004; +CHECKREG r3, 0xFC8EEADF; +CHECKREG r4, 0x0000FFDB; +CHECKREG r5, 0x0038FEA0; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFF660004; + +imm32 r0, 0xab2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13246d05; +imm32 r3, 0x000600d7; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c500d; +imm32 r7, 0x1246760f; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (IH); +R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (IH); +R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (IH); +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (IH); +R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (IH); +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (IH); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (IH); +R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (IH); +CHECKREG r0, 0xFF71FCD4; +CHECKREG r1, 0xFFCB0033; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0xFFFD0000; +CHECKREG r4, 0xF920FECB; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0xFFFF0000; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_is.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_is.s new file mode 100644 index 0000000..f081342 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_is.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_is/c_dsp32mult_dr_is.dsp +// Spec Reference: dsp32mult single dr is +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (ISS2); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (ISS2); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (ISS2); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (ISS2); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (ISS2); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (ISS2); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (ISS2); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (ISS2); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF8000; +CHECKREG r2, 0x80007FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0x9923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1324b735; +imm32 r3, 0x99060037; +imm32 r4, 0x809bcd39; +imm32 r5, 0xb0a99f3b; +imm32 r6, 0xa00c093d; +imm32 r7, 0x12467093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (ISS2); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (ISS2); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (ISS2); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (ISS2); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (ISS2); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (ISS2); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (ISS2); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (ISS2); +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x80007FFF; +CHECKREG r7, 0x80008000; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (ISS2); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (ISS2); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (ISS2); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (ISS2); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (ISS2); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (ISS2); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (ISS2); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (ISS2); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF8000; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x80008000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xe0060066; +imm32 r4, 0x9eab9d69; +imm32 r5, 0x10ecef6b; +imm32 r6, 0x800ee06d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (ISS2); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (ISS2); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (ISS2); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (ISS2); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (ISS2); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (ISS2); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (ISS2); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (ISS2); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x80008000; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x7FFF7FFF; + +// mix order +imm32 r0, 0xac23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13c46705; +imm32 r3, 0x00060007; +imm32 r4, 0x90accd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000cc00d; +imm32 r7, 0x1246fc0f; +R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (ISS2); +R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (ISS2); +R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (ISS2); +R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (ISS2); +R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (ISS2); +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (ISS2); +R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (ISS2); +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (ISS2); +CHECKREG r0, 0x7FFF8000; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x80008000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x80007FFF; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (ISS2); +R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (ISS2); +R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (ISS2); +R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (ISS2); +R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (ISS2); +R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (ISS2); +R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (ISS2); +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (ISS2); +CHECKREG r0, 0x80007FFF; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x80007FFF; +CHECKREG r3, 0x80007FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x80007FFF; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x7FFF8000; + +imm32 r0, 0xfb235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13f46705; +imm32 r3, 0x000f0007; +imm32 r4, 0x90abfd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (ISS2); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (ISS2); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (ISS2); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (ISS2); +R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (ISS2); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (ISS2); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (ISS2); +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (ISS2); +CHECKREG r0, 0x7FFF8000; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x80007FFF; + +imm32 r0, 0xab2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13246d05; +imm32 r3, 0x000600d7; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c500d; +imm32 r7, 0x1246760f; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (ISS2); +R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (ISS2); +R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (ISS2); +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (ISS2); +R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (ISS2); +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (ISS2); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (ISS2); +R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (ISS2); +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x14287FFF; +CHECKREG r7, 0x80007FFF; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_iu.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_iu.s new file mode 100644 index 0000000..83b1bc0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_iu.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_iu/c_dsp32mult_dr_iu.dsp +// Spec Reference: dsp32mult single dr iu +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00010002; +imm32 r1, 0x00023004; +imm32 r2, 0x03843725; +imm32 r3, 0x00084027; +imm32 r4, 0x00ab5d29; +imm32 r5, 0x00ac682b; +imm32 r6, 0x000c708d; +imm32 r7, 0x02462028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IU); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IU); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IU); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IU); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IU); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IU); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IU); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IU); +CHECKREG r0, 0x00040004; +CHECKREG r1, 0xC0100008; +CHECKREG r2, 0x0020FFFF; +CHECKREG r3, 0x0040FFFF; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x60080004; +CHECKREG r6, 0x60080004; +CHECKREG r7, 0xFFFF0004; + +imm32 r0, 0x00230635; +imm32 r1, 0x00995137; +imm32 r2, 0x00240735; +imm32 r3, 0x00060037; +imm32 r4, 0x009b0239; +imm32 r5, 0x00a9933b; +imm32 r6, 0x000c093d; +imm32 r7, 0x12407093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IU); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IU); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IU); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IU); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IU); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IU); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IU); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IU); +CHECKREG r0, 0xFFFFFFFF; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0x2B3E00D8; +CHECKREG r6, 0xFFFF07BC; +CHECKREG r7, 0x014A014A; + +imm32 r0, 0x09235655; +imm32 r1, 0x09ba5157; +imm32 r2, 0x03246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x00ab6509; +imm32 r5, 0x00ac7f5b; +imm32 r6, 0x000a005d; +imm32 r7, 0x0246405f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IU); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IU); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IU); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IU); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IU); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IU); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IU); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IU); +CHECKREG r0, 0xFFFFFFFF; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFF7390; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x00230666; +imm32 r1, 0x00ba0166; +imm32 r2, 0x00240766; +imm32 r3, 0x00060066; +imm32 r4, 0x03ab0d69; +imm32 r5, 0x10ec3f6b; +imm32 r6, 0x000e206d; +imm32 r7, 0x00460e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IU); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IU); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IU); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IU); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IU); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IU); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IU); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IU); +CHECKREG r0, 0x00C4FFFF; +CHECKREG r1, 0x03D4FFFF; +CHECKREG r2, 0x03D4FFFF; +CHECKREG r3, 0x13241324; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x00C4FFFF; +CHECKREG r7, 0x3598FFFF; + +// mix order +imm32 r0, 0x0023a675; +imm32 r1, 0x00ba5127; +imm32 r2, 0x00c46705; +imm32 r3, 0x00060007; +imm32 r4, 0x00accd09; +imm32 r5, 0x00acdfdb; +imm32 r6, 0x000cc00d; +imm32 r7, 0x0246fc0f; +R0.H = R0.L * R7.H, R0.L = R0.H * R7.H (IU); +R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IU); +R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IU); +R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IU); +R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IU); +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IU); +R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IU); +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IU); +CHECKREG r0, 0xFFFF4F92; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0xFFFFFFFF; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x00230a75; +imm32 r1, 0x00ba0127; +imm32 r2, 0x00240905; +imm32 r3, 0x00d60007; +imm32 r4, 0x00ab0d09; +imm32 r5, 0x00ac0ddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x0046000f; +R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (IU); +R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (IU); +R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (IU); +R3.H = R4.L * R3.H, R3.L = R4.H * R3.H (IU); +R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (IU); +R5.H = R2.H * R5.L, R5.L = R2.L * R5.H (IU); +R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (IU); +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (IU); +CHECKREG r0, 0x0992FFFF; +CHECKREG r1, 0x08B8FFFF; +CHECKREG r2, 0x1830FFFF; +CHECKREG r3, 0xFFFF8EF2; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x68A0FFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x0b230675; +imm32 r1, 0x00ba0127; +imm32 r2, 0x03f40705; +imm32 r3, 0x000f0007; +imm32 r4, 0x00ab0d09; +imm32 r5, 0x10ac0fdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246000f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IU); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IU); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IU); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IU); +R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IU); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IU); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IU); +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IU); +CHECKREG r0, 0xFFFFFFFF; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFF4D7C; +CHECKREG r3, 0xFFFF0AE6; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x002d0675; +imm32 r1, 0x001a0027; +imm32 r2, 0x00240005; +imm32 r3, 0x000600d7; +imm32 r4, 0x008b0d09; +imm32 r5, 0x00a0000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x0006060f; +R3.H = R0.L * R2.L, R3.L = R0.L * R2.H (IU); +R4.H = R1.H * R3.L, R4.L = R1.H * R3.H (IU); +R5.H = R2.L * R4.L, R5.L = R2.L * R4.H (IU); +R6.H = R3.L * R5.H, R6.L = R3.L * R5.L (IU); +R0.H = R4.H * R6.L, R0.L = R4.H * R6.L (IU); +R1.H = R5.L * R7.H, R1.L = R5.H * R7.L (IU); +R2.H = R6.L * R0.L, R2.L = R6.L * R0.H (IU); +R7.H = R7.H * R1.L, R7.L = R7.L * R1.H (IU); +CHECKREG r0, 0xFFFFFFFF; +CHECKREG r1, 0xFFFFFFFF; +CHECKREG r2, 0xFFFFFFFF; +CHECKREG r3, 0x2049E874; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFFFFFFFF; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m.s new file mode 100644 index 0000000..3e42cae --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_dsp32mult_dr_m/c_dsp32mult_dr_m.dsp +// Spec Reference: dsp32mult single dr (mix) MUNOP +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R4.L = R0.L * R0.L; +R5.L = R0.L * R1.H; +R6.L = R1.H * R0.L; +R7.L = R1.H * R1.H; +R0.L = R0.L * R0.L; +R1.L = R0.L * R1.H; +R2.L = R1.H * R0.L; +R3.L = R1.H * R1.H; +CHECKREG r0, 0x342339FA; +CHECKREG r1, 0x9F7AD448; +CHECKREG r2, 0xA328D448; +CHECKREG r3, 0x000648CA; +CHECKREG r4, 0xB0AB39FA; +CHECKREG r5, 0x10ACBF0A; +CHECKREG r6, 0xC00CBF0A; +CHECKREG r7, 0xD24648CA; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R4.L = R2.H * R2.L; +R5.L = R2.H * R3.H; +R6.L = R3.L * R2.L; +R7.L = R3.L * R3.H; +R0.L = R2.H * R2.L; +R1.L = R2.H * R3.H; +R2.L = R3.L * R2.L; +R3.L = R3.L * R3.H; +CHECKREG r0, 0x5B23F51D; +CHECKREG r1, 0x6FBAEF41; +CHECKREG r2, 0x1324FFE1; +CHECKREG r3, 0x9006FFD0; +CHECKREG r4, 0x80ABF51D; +CHECKREG r5, 0xB0ACEF41; +CHECKREG r6, 0xA00CFFE1; +CHECKREG r7, 0x1246FFD0; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0.L = R4.L * R4.L; +R1.L = R4.L * R5.H; +R2.L = R5.H * R4.L; +R3.L = R5.H * R5.H; +R4.L = R4.L * R4.L; +R5.L = R4.L * R5.H; +R6.L = R5.H * R4.L; +R7.L = R5.H * R5.H; +CHECKREG r0, 0x1B231B2A; +CHECKREG r1, 0xC4BAF854; +CHECKREG r2, 0x4324F854; +CHECKREG r3, 0x0506022B; +CHECKREG r4, 0x906B1B2A; +CHECKREG r5, 0x10A70389; +CHECKREG r6, 0xB00C0389; +CHECKREG r7, 0x1246022B; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +// test the unsigned U=1 +R0.L = R6.L * R6.L; +R1.L = R6.L * R7.H; +R2.L = R7.H * R6.L; +R3.L = R7.H * R7.H; +R4.L = R6.L * R6.L; +R5.L = R6.L * R7.H; +R6.L = R7.H * R6.L; +R7.L = R7.H * R7.H; +CHECKREG r0, 0xBB233178; +CHECKREG r1, 0xEFBAF4A4; +CHECKREG r2, 0x1324F4A4; +CHECKREG r3, 0xF006029C; +CHECKREG r4, 0x90AB3178; +CHECKREG r5, 0x10ACF4A4; +CHECKREG r6, 0x800CF4A4; +CHECKREG r7, 0x1246029C; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0.L = R0.H * R7.L; +R1.L = R1.H * R6.H; +R2.L = R2.L * R5.L; +R3.L = R3.H * R4.H; +R4.L = R4.L * R3.H; +R5.L = R5.H * R2.L; +R6.L = R6.L * R1.L; +R7.L = R7.H * R0.L; +CHECKREG r0, 0xAB230A92; +CHECKREG r1, 0xCFBAFFFB; +CHECKREG r2, 0x1324E621; +CHECKREG r3, 0x0006FFFB; +CHECKREG r4, 0x90ABFFFE; +CHECKREG r5, 0x10ACFCA1; +CHECKREG r6, 0x000C0000; +CHECKREG r7, 0x12460182; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R7.H * R0.H; +R1.H = R6.H * R1.H; +R2.H = R5.H * R2.L; +R3.H = R4.H * R3.H; +R4.H = R3.L * R4.H; +R5.H = R2.H * R5.L; +R6.H = R1.H * R6.H; +R7.H = R0.L * R7.H; +CHECKREG r0, 0xF3E35A75; +CHECKREG r1, 0xFFFB5127; +CHECKREG r2, 0x0DAE6905; +CHECKREG r3, 0xFFFB0007; +CHECKREG r4, 0xFFFACD09; +CHECKREG r5, 0xFDA2E9DB; +CHECKREG r6, 0x00000D0D; +CHECKREG r7, 0x0CEA700F; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R2.H = R0.L * R6.L; +R3.H = R1.H * R7.L; +R0.H = R2.L * R0.L; +R1.H = R3.L * R1.H; +R4.H = R4.H * R2.H; +R5.H = R5.L * R3.H; +R6.H = R6.H * R4.L; +R7.H = R7.L * R5.H; +CHECKREG r0, 0x45965675; +CHECKREG r1, 0xFFFD5127; +CHECKREG r2, 0x006A6705; +CHECKREG r3, 0xD07F0007; +CHECKREG r4, 0xFFA49D09; +CHECKREG r5, 0x0838E9DB; +CHECKREG r6, 0xFFF7009D; +CHECKREG r7, 0x07327009; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R4.H = R5.L * R2.L; +R6.H = R6.H * R3.H; +R0.H = R7.H * R4.L; +R1.H = R0.H * R5.L; +R2.H = R1.H * R6.H; +R5.H = R2.H * R7.L; +R3.H = R3.H * R0.L; +R7.H = R4.L * R1.H; +CHECKREG r0, 0xFD4B5675; +CHECKREG r1, 0x005D5127; +CHECKREG r2, 0x00006705; +CHECKREG r3, 0x00090007; +CHECKREG r4, 0xF234ED09; +CHECKREG r5, 0x0000EEDB; +CHECKREG r6, 0x000000ED; +CHECKREG r7, 0xFFF2700E; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_i.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_i.s new file mode 100644 index 0000000..6860a13 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_i.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_m_i/c_dsp32mult_dr_m_i.dsp +// Spec Reference: dsp32mult single dr munop i +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xfb235625; +imm32 r1, 0x9fba5127; +imm32 r2, 0xa3ff6725; +imm32 r3, 0x0006f027; +imm32 r4, 0xb0abcd29; +imm32 r5, 0x1facef2b; +imm32 r6, 0xc0fc002d; +imm32 r7, 0xd24f702f; +R4.L = R0.H * R0.L (IS); +R5.H = R0.L * R1.L (IS); +R6.L = R1.L * R0.H (IS); +R7.L = R1.L * R1.L (IS); +R0.H = R0.L * R0.L (IS); +R1.L = R0.L * R1.L (IS); +R2.L = R1.H * R0.L (IS); +R3.H = R1.L * R1.L (IS); +CHECKREG r0, 0x7FFF5625; +CHECKREG r1, 0x9FBA7FFF; +CHECKREG r2, 0xA3FF8000; +CHECKREG r3, 0x7FFFF027; +CHECKREG r4, 0xB0AB8000; +CHECKREG r5, 0x7FFFEF2B; +CHECKREG r6, 0xC0FC8000; +CHECKREG r7, 0xD24F7FFF; + +imm32 r0, 0xeb23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b7e5; +imm32 r3, 0x9e060037; +imm32 r4, 0x80ebcd39; +imm32 r5, 0xb0aeef3b; +imm32 r6, 0xa00ce03d; +imm32 r7, 0x12467e03; +R5.H = R2.L * R2.L (IS); +R6.L = R2.L * R3.H (IS); +R7.L = R3.H * R2.L (IS); +R0.H = R3.L * R3.L (IS); +R1.H = R2.L * R2.H (IS); +R2.L = R2.H * R3.H (IS); +R3.H = R3.L * R2.L (IS); +R4.L = R3.L * R3.L (IS); +CHECKREG r0, 0x0BD1A635; +CHECKREG r1, 0x80005137; +CHECKREG r2, 0x13248000; +CHECKREG r3, 0x80000037; +CHECKREG r4, 0x80EB0BD1; +CHECKREG r5, 0x7FFFEF3B; +CHECKREG r6, 0xA00C7FFF; +CHECKREG r7, 0x12467FFF; + +imm32 r0, 0xdd235655; +imm32 r1, 0xc4dd5157; +imm32 r2, 0x6324d755; +imm32 r3, 0x00060055; +imm32 r4, 0x90dbc509; +imm32 r5, 0x10adef5b; +imm32 r6, 0xb00cd05d; +imm32 r7, 0x12467d5f; +R0.L = R4.L * R4.H (IS); +R1.H = R4.H * R5.L (IS); +R2.L = R5.H * R4.L (IS); +R3.L = R5.L * R5.L (IS); +R4.H = R4.L * R4.H (IS); +R5.L = R4.L * R5.H (IS); +R6.H = R5.H * R4.H (IS); +R7.L = R5.H * R5.H (IS); +CHECKREG r0, 0xDD237FFF; +CHECKREG r1, 0x7FFF5157; +CHECKREG r2, 0x63248000; +CHECKREG r3, 0x00067FFF; +CHECKREG r4, 0x7FFFC509; +CHECKREG r5, 0x10AD8000; +CHECKREG r6, 0x7FFFD05D; +CHECKREG r7, 0x12467FFF; + +imm32 r0, 0xcb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x1c248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90cb9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cc06d; +imm32 r7, 0x12467c6f; +// test the unsigned U=1 +R0.L = R6.L * R6.L (IS); +R1.H = R6.H * R7.L (IS); +R2.L = R7.L * R6.L (IS); +R3.L = R7.L * R7.L (IS); +R6.H = R6.H * R6.H (IS); +R7.L = R6.L * R7.L (IS); +R4.H = R7.H * R6.H (IS); +R5.L = R7.L * R7.L (IS); +CHECKREG r0, 0xCB237FFF; +CHECKREG r1, 0x80005166; +CHECKREG r2, 0x1C248000; +CHECKREG r3, 0xF0067FFF; +CHECKREG r4, 0x7FFF9D69; +CHECKREG r5, 0x10AC7FFF; +CHECKREG r6, 0x7FFFC06D; +CHECKREG r7, 0x12468000; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0xe0060007; +imm32 r4, 0x9eabcd09; +imm32 r5, 0x10ecdfdb; +imm32 r6, 0x000e000d; +imm32 r7, 0x1246e00f; +R0.H = R0.L * R7.H (IS); +R1.L = R1.H * R6.H (IS); +R2.L = R2.L * R5.L (IS); +R3.H = R3.H * R4.H (IS); +R4.L = R4.L * R3.H (IS); +R5.L = R5.H * R2.H (IS); +R6.H = R6.H * R1.L (IS); +R7.L = R7.L * R0.H (IS); +CHECKREG r0, 0x8000A675; +CHECKREG r1, 0xCFBA8000; +CHECKREG r2, 0x13248000; +CHECKREG r3, 0x7FFF0007; +CHECKREG r4, 0x9EAB8000; +CHECKREG r5, 0x10EC7FFF; +CHECKREG r6, 0x8000000D; +CHECKREG r7, 0x12467FFF; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x93246905; +imm32 r3, 0x09060007; +imm32 r4, 0x909bcd09; +imm32 r5, 0x10a9e9db; +imm32 r6, 0x000c9d0d; +imm32 r7, 0x1246790f; +R0.L = R7.L * R0.H (IS); +R1.L = R6.L * R1.L (IS); +R2.H = R5.L * R2.L (IS); +R3.L = R4.H * R3.L (IS); +R4.L = R3.H * R4.H (IS); +R5.H = R2.H * R5.L (IS); +R6.L = R1.H * R6.L (IS); +R7.L = R0.L * R7.L (IS); +CHECKREG r0, 0x9B238000; +CHECKREG r1, 0xCFBA8000; +CHECKREG r2, 0x80006905; +CHECKREG r3, 0x09068000; +CHECKREG r4, 0x909B8000; +CHECKREG r5, 0x7FFFE9DB; +CHECKREG r6, 0x000C7FFF; +CHECKREG r7, 0x12468000; + +imm32 r0, 0xa9235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x08060007; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a88fdb; +imm32 r6, 0x000c080d; +imm32 r7, 0x1246708f; +R2.L = R0.L * R6.L (IS); +R3.L = R1.H * R7.L (IS); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IS); +R1.H = R3.L * R1.L (IS); +R4.L = R4.H * R2.L (IS); +R5.L = R5.L * R3.L (IS); +R6.L = R6.L * R4.L (IS); +R7.H = R7.H * R5.L (IS); +CHECKREG r0, 0x7FFF8000; +CHECKREG r1, 0x80005127; +CHECKREG r2, 0x13247FFF; +CHECKREG r3, 0x08068000; +CHECKREG r4, 0x908B8000; +CHECKREG r5, 0x10A87FFF; +CHECKREG r6, 0x000C8000; +CHECKREG r7, 0x7FFF708F; + +imm32 r0, 0x7b235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x17246705; +imm32 r3, 0x00760007; +imm32 r4, 0x907bcd09; +imm32 r5, 0x10a7efdb; +imm32 r6, 0x000c700d; +imm32 r7, 0x1246770f; +R4.L = R5.L * R2.L (IS); +R6.L = R6.L * R3.H (IS); +R0.H = R7.L * R4.H (IS); +R1.L = R0.H * R5.L (IS); +R2.L = R1.L * R6.L (IS); +R5.L = R2.L * R7.H (IS); +R3.H = R3.H * R0.L (IS); +R7.L = R4.H * R1.H (IS); +CHECKREG r0, 0x80005675; +CHECKREG r1, 0xCFBA7FFF; +CHECKREG r2, 0x17247FFF; +CHECKREG r3, 0x7FFF0007; +CHECKREG r4, 0x907B8000; +CHECKREG r5, 0x10A77FFF; +CHECKREG r6, 0x000C7FFF; +CHECKREG r7, 0x12467FFF; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_iutsh.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_iutsh.s new file mode 100644 index 0000000..4f38460 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_iutsh.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_m_iutsh/c_dsp32mult_dr_m_iutsh.dsp +// Spec Reference: dsp32mult single dr munop iu tu is ih +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xfb235625; +imm32 r1, 0x9fba5127; +imm32 r2, 0xa3ff6725; +imm32 r3, 0x0006f027; +imm32 r4, 0xb0abcd29; +imm32 r5, 0x1facef2b; +imm32 r6, 0xc0fc002d; +imm32 r7, 0xd24f702f; +R4.L = R0.H * R0.L (TFU); +R5.H = R0.L * R1.L (IU); +R6.L = R1.L * R0.H (TFU); +R7.L = R1.L * R1.L (TFU); +R0.H = R0.L * R0.L (IU); +R1.L = R0.L * R1.L (TFU); +R2.L = R1.H * R0.L (IU); +R3.H = R1.L * R1.L (TFU); +CHECKREG r0, 0xFFFF5625; +CHECKREG r1, 0x9FBA1B4E; +CHECKREG r2, 0xA3FFFFFF; +CHECKREG r3, 0x02E9F027; +CHECKREG r4, 0xB0AB5482; +CHECKREG r5, 0xFFFFEF2B; +CHECKREG r6, 0xC0FC4F9C; +CHECKREG r7, 0xD24F19B9; + +imm32 r0, 0xeb23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b7e5; +imm32 r3, 0x9e060037; +imm32 r4, 0x80ebcd39; +imm32 r5, 0xb0aeef3b; +imm32 r6, 0xa00ce03d; +imm32 r7, 0x12467e03; +R4.H = R2.L * R2.L (ISS2); +R5.L = R2.L * R3.H (IH); +R6.L = R3.H * R2.L (ISS2); +R7.H = R3.L * R3.L (ISS2); +R2.H = R2.L * R2.H (IH); +R3.L = R2.H * R3.H (ISS2); +R0.H = R3.L * R2.L (IH); +R1.L = R3.L * R3.L (ISS2); +CHECKREG r0, 0xDBF3A635; +CHECKREG r1, 0x6FBA7FFF; +CHECKREG r2, 0xFA9CB7E5; +CHECKREG r3, 0x9E067FFF; +CHECKREG r4, 0x7FFFCD39; +CHECKREG r5, 0xB0AE1B99; +CHECKREG r6, 0xA00C7FFF; +CHECKREG r7, 0x17A27E03; + +imm32 r0, 0xdd235655; +imm32 r1, 0xc4dd5157; +imm32 r2, 0x6324d755; +imm32 r3, 0x00060055; +imm32 r4, 0x90dbc509; +imm32 r5, 0x10adef5b; +imm32 r6, 0xb00cd05d; +imm32 r7, 0x12467d5f; +R0.L = R4.L * R4.H (IU); +R1.H = R4.H * R5.L (TFU); +R2.L = R5.H * R4.L (ISS2); +R3.L = R5.L * R5.L (IH); +R4.H = R4.L * R4.H (ISS2); +R5.L = R4.L * R5.H (TFU); +R6.H = R5.H * R4.H (IU); +R7.L = R5.H * R5.H (ISS2); +CHECKREG r0, 0xDD23FFFF; +CHECKREG r1, 0x876F5157; +CHECKREG r2, 0x63248000; +CHECKREG r3, 0x00060115; +CHECKREG r4, 0x7FFFC509; +CHECKREG r5, 0x10AD0CD5; +CHECKREG r6, 0xFFFFD05D; +CHECKREG r7, 0x12467FFF; + +imm32 r0, 0xcb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x1c248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90cb9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cc06d; +imm32 r7, 0x12467c6f; +// test the unsigned U=1 +R0.L = R6.L * R6.L (TFU); +R1.H = R6.H * R7.L (IH); +R2.L = R7.L * R6.L (ISS2); +R3.L = R7.L * R7.L (IH); +R6.L = R6.L * R6.L (TFU); +R7.L = R6.L * R7.L (IH); +R4.L = R7.L * R6.L (TFU); +R5.L = R7.L * R7.L (ISS2); +CHECKREG r0, 0xCB2390A3; +CHECKREG r1, 0xC1CE5166; +CHECKREG r2, 0x1C248000; +CHECKREG r3, 0xF0063C7C; +CHECKREG r4, 0x90CB720D; +CHECKREG r5, 0x10AC7FFF; +CHECKREG r6, 0x800C90A3; +CHECKREG r7, 0x1246C9DF; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0xe0060007; +imm32 r4, 0x9eabcd09; +imm32 r5, 0x10ecdfdb; +imm32 r6, 0x000e000d; +imm32 r7, 0x1246e00f; +R0.H = R0.L * R7.H (IU); +R1.L = R1.H * R6.H (ISS2); +R2.L = R2.L * R5.L (IU); +R3.H = R3.H * R4.H (ISS2); +R4.L = R4.L * R3.H (IU); +R5.L = R5.H * R2.H (ISS2); +R6.H = R6.H * R1.L (IH); +R7.L = R7.L * R0.H (IU); +CHECKREG r0, 0xFFFFA675; +CHECKREG r1, 0xCFBA8000; +CHECKREG r2, 0x1324FFFF; +CHECKREG r3, 0x7FFF0007; +CHECKREG r4, 0x9EABFFFF; +CHECKREG r5, 0x10EC7FFF; +CHECKREG r6, 0xFFF9000D; +CHECKREG r7, 0x1246FFFF; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x93246905; +imm32 r3, 0x09060007; +imm32 r4, 0x909bcd09; +imm32 r5, 0x10a9e9db; +imm32 r6, 0x000c9d0d; +imm32 r7, 0x1246790f; +R0.L = R7.L * R0.H (TFU); +R1.L = R6.L * R1.L (TFU); +R2.H = R5.L * R2.L (TFU); +R3.L = R4.H * R3.L (TFU); +R4.L = R3.H * R4.H (TFU); +R5.H = R2.H * R5.L (TFU); +R6.L = R1.H * R6.L (TFU); +R7.L = R0.L * R7.L (TFU); +CHECKREG r0, 0x9B23495C; +CHECKREG r1, 0xCFBA31C9; +CHECKREG r2, 0x5FEF6905; +CHECKREG r3, 0x09060003; +CHECKREG r4, 0x909B0518; +CHECKREG r5, 0x57A2E9DB; +CHECKREG r6, 0x000C7F6F; +CHECKREG r7, 0x124622B0; + +imm32 r0, 0xa9235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x08060007; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a88fdb; +imm32 r6, 0x000c080d; +imm32 r7, 0x1246708f; +R2.L = R0.L * R6.L (IU); +R3.L = R1.H * R7.L (IH); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IU); +R1.H = R3.L * R1.L (IH); +R4.L = R4.H * R2.L (IU); +R5.L = R5.L * R3.L (ISS2); +R6.L = R6.L * R4.L (IH); +R7.H = R7.H * R5.L (IU); +CHECKREG r0, 0xFFFFFFFF; +CHECKREG r1, 0xF84C5127; +CHECKREG r2, 0x1324FFFF; +CHECKREG r3, 0x0806E7B2; +CHECKREG r4, 0x908BFFFF; +CHECKREG r5, 0x10A87FFF; +CHECKREG r6, 0x000C0000; +CHECKREG r7, 0xFFFF708F; + +imm32 r0, 0x7b235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x17246705; +imm32 r3, 0x00760007; +imm32 r4, 0x907bcd09; +imm32 r5, 0x10a7efdb; +imm32 r6, 0x000c700d; +imm32 r7, 0x1246770f; +R4.L = R5.L * R2.L (TFU); +R6.L = R6.L * R3.H (ISS2); +R0.H = R7.L * R4.H (ISS2); +R1.L = R0.H * R5.L (ISS2); +R2.L = R1.L * R6.L (IH); +R5.L = R2.L * R7.H (TFU); +R3.H = R3.H * R0.L (IH); +R7.L = R4.H * R1.H (IU); +CHECKREG r0, 0x80005675; +CHECKREG r1, 0xCFBA7FFF; +CHECKREG r2, 0x17243FFF; +CHECKREG r3, 0x00280007; +CHECKREG r4, 0x907B6085; +CHECKREG r5, 0x10A70491; +CHECKREG r6, 0x000C7FFF; +CHECKREG r7, 0x1246FFFF; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_s.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_s.s new file mode 100644 index 0000000..670d9d3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_s.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_m_s/c_dsp32mult_dr_m_s.dsp +// Spec Reference: dsp32mult single dr munop s +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xfb235625; +imm32 r1, 0x9fba5127; +imm32 r2, 0xa3ff6725; +imm32 r3, 0x0006f027; +imm32 r4, 0xb0abcd29; +imm32 r5, 0x1facef2b; +imm32 r6, 0xc0fc002d; +imm32 r7, 0xd24f702f; +R4.L = R0.H * R0.L (S2RND); +R5.H = R0.L * R1.L (S2RND); +R6.L = R1.L * R0.H (S2RND); +R7.L = R1.L * R1.L (S2RND); +R0.H = R0.L * R0.L (S2RND); +R1.L = R0.L * R1.L (S2RND); +R2.L = R1.H * R0.L (S2RND); +R3.H = R1.L * R1.L (S2RND); +CHECKREG r0, 0x73F45625; +CHECKREG r1, 0x9FBA6D3B; +CHECKREG r2, 0xA3FF8000; +CHECKREG r3, 0x7FFFF027; +CHECKREG r4, 0xB0ABF974; +CHECKREG r5, 0x6D3BEF2B; +CHECKREG r6, 0xC0FCF9D5; +CHECKREG r7, 0xD24F66E7; + +imm32 r0, 0xeb23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b7e5; +imm32 r3, 0x9e060037; +imm32 r4, 0x80ebcd39; +imm32 r5, 0xb0aeef3b; +imm32 r6, 0xa00ce03d; +imm32 r7, 0x12467e03; +R4.H = R2.L * R2.L (S2RND); +R5.L = R2.L * R3.H (S2RND); +R6.L = R3.H * R2.L (S2RND); +R7.H = R3.L * R3.L (S2RND); +R2.H = R2.L * R2.H (S2RND); +R3.L = R2.H * R3.H (S2RND); +R0.H = R3.L * R2.L (S2RND); +R1.L = R3.L * R3.L (S2RND); +CHECKREG r0, 0xDACEA635; +CHECKREG r1, 0x6FBA1108; +CHECKREG r2, 0xEA6FB7E5; +CHECKREG r3, 0x9E062104; +CHECKREG r4, 0x513DCD39; +CHECKREG r5, 0xB0AE6E63; +CHECKREG r6, 0xA00C6E63; +CHECKREG r7, 0x00007E03; + +imm32 r0, 0xdd235655; +imm32 r1, 0xc4dd5157; +imm32 r2, 0x6324d755; +imm32 r3, 0x00060055; +imm32 r4, 0x90dbc509; +imm32 r5, 0x10adef5b; +imm32 r6, 0xb00cd05d; +imm32 r7, 0x12467d5f; +R0.L = R4.L * R4.H (S2RND); +R1.H = R4.H * R5.L (S2RND); +R2.L = R5.H * R4.L (S2RND); +R3.L = R5.L * R5.L (S2RND); +R4.H = R4.L * R4.H (S2RND); +R5.L = R4.L * R5.H (S2RND); +R6.H = R5.H * R4.H (S2RND); +R7.L = R5.H * R5.H (S2RND); +CHECKREG r0, 0xDD236666; +CHECKREG r1, 0x1CE85157; +CHECKREG r2, 0x6324F0A3; +CHECKREG r3, 0x00060454; +CHECKREG r4, 0x6666C509; +CHECKREG r5, 0x10ADF0A3; +CHECKREG r6, 0x1AAED05D; +CHECKREG r7, 0x12460458; + +imm32 r0, 0xcb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x1c248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90cb9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cc06d; +imm32 r7, 0x12467c6f; +// test the unsigned U=1 +R0.L = R6.L * R6.L (S2RND); +R1.H = R6.H * R7.L (S2RND); +R2.L = R7.L * R6.L (S2RND); +R3.L = R7.L * R7.L (S2RND); +R6.L = R6.L * R6.L (S2RND); +R7.L = R6.L * R7.L (S2RND); +R4.L = R7.L * R6.L (S2RND); +R5.L = R7.L * R7.L (S2RND); +CHECKREG r0, 0xCB233F27; +CHECKREG r1, 0x80005166; +CHECKREG r2, 0x1C248465; +CHECKREG r3, 0xF0067FFF; +CHECKREG r4, 0x90CB7929; +CHECKREG r5, 0x10AC7FFF; +CHECKREG r6, 0x800C3F27; +CHECKREG r7, 0x12467AC9; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0xe0060007; +imm32 r4, 0x9eabcd09; +imm32 r5, 0x10ecdfdb; +imm32 r6, 0x000e000d; +imm32 r7, 0x1246e00f; +R0.H = R0.L * R7.H (S2RND); +R1.L = R1.H * R6.H (S2RND); +R2.L = R2.L * R5.L (S2RND); +R3.H = R3.H * R4.H (S2RND); +R4.L = R4.L * R3.H (S2RND); +R5.L = R5.H * R2.H (S2RND); +R6.H = R6.H * R1.L (S2RND); +R7.L = R7.L * R0.H (S2RND); +CHECKREG r0, 0xE66FA675; +CHECKREG r1, 0xCFBAFFF5; +CHECKREG r2, 0x1324CC42; +CHECKREG r3, 0x30A10007; +CHECKREG r4, 0x9EABD947; +CHECKREG r5, 0x10EC0510; +CHECKREG r6, 0x0000000D; +CHECKREG r7, 0x12460CC3; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x93246905; +imm32 r3, 0x09060007; +imm32 r4, 0x909bcd09; +imm32 r5, 0x10a9e9db; +imm32 r6, 0x000c9d0d; +imm32 r7, 0x1246790f; +R0.L = R7.L * R0.H (S2RND); +R1.L = R6.L * R1.L (S2RND); +R2.H = R5.L * R2.L (S2RND); +R3.L = R4.H * R3.L (S2RND); +R4.L = R3.H * R4.H (S2RND); +R5.H = R2.H * R5.L (S2RND); +R6.L = R1.H * R6.L (S2RND); +R7.L = R0.L * R7.L (S2RND); +CHECKREG r0, 0x9B238000; +CHECKREG r1, 0xCFBA8288; +CHECKREG r2, 0xDBAA6905; +CHECKREG r3, 0x0906FFF4; +CHECKREG r4, 0x909BF04B; +CHECKREG r5, 0x0C93E9DB; +CHECKREG r6, 0x000C4AA2; +CHECKREG r7, 0x12468000; + +imm32 r0, 0xa9235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x08060007; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a88fdb; +imm32 r6, 0x000c080d; +imm32 r7, 0x1246708f; +R2.L = R4.L * R6.L (S2RND); +R3.L = R2.H * R2.L (S2RND); +R0.H = R2.L * R3.L, R0.L = R2.H * R3.H (S2RND); +R1.H = R3.L * R1.L (S2RND); +R4.L = R4.H * R0.L (S2RND); +R5.L = R5.L * R5.L (S2RND); +R6.L = R6.L * R5.H (S2RND); +R7.H = R6.H * R7.L (S2RND); +CHECKREG r0, 0x00310266; +CHECKREG r1, 0xFD915127; +CHECKREG r2, 0x1324F997; +CHECKREG r3, 0x0806FE15; +CHECKREG r4, 0x908BFBD3; +CHECKREG r5, 0x10A87FFF; +CHECKREG r6, 0x000C0218; +CHECKREG r7, 0x0015708F; + +imm32 r0, 0x7b235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x17246705; +imm32 r3, 0x00760007; +imm32 r4, 0x907bcd09; +imm32 r5, 0x10a7efdb; +imm32 r6, 0x000c700d; +imm32 r7, 0x1246770f; +R4.L = R5.L * R2.L (S2RND); +R6.L = R6.L * R3.H (S2RND); +R0.H = R7.L * R4.H (S2RND); +R1.L = R0.H * R5.L (S2RND); +R2.L = R1.L * R6.L (S2RND); +R5.L = R2.L * R7.H (S2RND); +R3.H = R3.H * R0.L (S2RND); +R7.L = R4.H * R1.H (S2RND); +CHECKREG r0, 0x80005675; +CHECKREG r1, 0xCFBA204A; +CHECKREG r2, 0x17240068; +CHECKREG r3, 0x009F0007; +CHECKREG r4, 0x907BE603; +CHECKREG r5, 0x10A7001E; +CHECKREG r6, 0x000C00CF; +CHECKREG r7, 0x1246541E; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_t.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_t.s new file mode 100644 index 0000000..4dc42e8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_t.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_m_t/c_dsp32mult_dr_m_t.dsp +// Spec Reference: dsp32mult single dr munop t +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xfb235625; +imm32 r1, 0x9fba5127; +imm32 r2, 0xa3ff6725; +imm32 r3, 0x0006f027; +imm32 r4, 0xb0abcd29; +imm32 r5, 0x1facef2b; +imm32 r6, 0xc0fc002d; +imm32 r7, 0xd24f702f; +R4.L = R0.H * R0.L (T); +R5.H = R0.L * R1.L (T); +R6.L = R1.L * R0.H (T); +R7.L = R1.L * R1.L (T); +R0.H = R0.L * R0.L (T); +R1.L = R0.L * R1.L (T); +R2.L = R1.H * R0.L (T); +R3.H = R1.L * R1.L (T); +CHECKREG r0, 0x39F95625; +CHECKREG r1, 0x9FBA369D; +CHECKREG r2, 0xA3FFBF35; +CHECKREG r3, 0x174DF027; +CHECKREG r4, 0xB0ABFCBA; +CHECKREG r5, 0x369DEF2B; +CHECKREG r6, 0xC0FCFCEA; +CHECKREG r7, 0xD24F3373; + +imm32 r0, 0xeb23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b7e5; +imm32 r3, 0x9e060037; +imm32 r4, 0x80ebcd39; +imm32 r5, 0xb0aeef3b; +imm32 r6, 0xa00ce03d; +imm32 r7, 0x12467e03; +R4.H = R2.L * R2.L (T); +R5.L = R2.L * R3.H (T); +R6.L = R3.H * R2.L (T); +R7.H = R3.L * R3.L (T); +R2.H = R2.L * R2.H (T); +R3.L = R2.H * R3.H (T); +R0.H = R3.L * R2.L (T); +R1.L = R3.L * R3.L (T); +CHECKREG r0, 0xFB59A635; +CHECKREG r1, 0x6FBA0088; +CHECKREG r2, 0xF537B7E5; +CHECKREG r3, 0x9E060841; +CHECKREG r4, 0x289ECD39; +CHECKREG r5, 0xB0AE3731; +CHECKREG r6, 0xA00C3731; +CHECKREG r7, 0x00007E03; + +imm32 r0, 0xdd235655; +imm32 r1, 0xc4dd5157; +imm32 r2, 0x6324d755; +imm32 r3, 0x00060055; +imm32 r4, 0x90dbc509; +imm32 r5, 0x10adef5b; +imm32 r6, 0xb00cd05d; +imm32 r7, 0x12467d5f; +R0.L = R4.L * R4.H (T); +R1.H = R4.H * R5.L (T); +R2.L = R5.H * R4.L (T); +R3.L = R5.L * R5.L (T); +R4.H = R4.L * R4.H (T); +R5.L = R4.L * R5.H (T); +R6.H = R5.H * R4.H (T); +R7.L = R5.H * R5.H (T); +CHECKREG r0, 0xDD233333; +CHECKREG r1, 0x0E735157; +CHECKREG r2, 0x6324F851; +CHECKREG r3, 0x0006022A; +CHECKREG r4, 0x3333C509; +CHECKREG r5, 0x10ADF851; +CHECKREG r6, 0x06ABD05D; +CHECKREG r7, 0x1246022C; + +imm32 r0, 0xcb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x1c248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90cb9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cc06d; +imm32 r7, 0x12467c6f; +// test the unsigned U=1 +R0.L = R6.L * R6.L (T); +R1.H = R6.H * R7.L (T); +R2.L = R7.L * R6.L (T); +R3.L = R7.L * R7.L (T); +R6.L = R6.L * R6.L (T); +R7.L = R6.L * R7.L (T); +R4.L = R7.L * R6.L (T); +R5.L = R7.L * R7.L (T); +CHECKREG r0, 0xCB231F93; +CHECKREG r1, 0x839C5166; +CHECKREG r2, 0x1C24C232; +CHECKREG r3, 0xF00678F7; +CHECKREG r4, 0x90CB0792; +CHECKREG r5, 0x10AC075B; +CHECKREG r6, 0x800C1F93; +CHECKREG r7, 0x12461EB1; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0xe0060007; +imm32 r4, 0x9eabcd09; +imm32 r5, 0x10ecdfdb; +imm32 r6, 0x000e000d; +imm32 r7, 0x1246e00f; +R0.H = R0.L * R7.H (T); +R1.L = R1.H * R6.H (T); +R2.L = R2.L * R5.L (T); +R3.H = R3.H * R4.H (T); +R4.L = R4.L * R3.H (T); +R5.L = R5.H * R2.H (T); +R6.H = R6.H * R1.L (T); +R7.L = R7.L * R0.H (T); +CHECKREG r0, 0xF337A675; +CHECKREG r1, 0xCFBAFFFA; +CHECKREG r2, 0x1324E620; +CHECKREG r3, 0x18500007; +CHECKREG r4, 0x9EABF651; +CHECKREG r5, 0x10EC0287; +CHECKREG r6, 0xFFFF000D; +CHECKREG r7, 0x12460330; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x93246905; +imm32 r3, 0x09060007; +imm32 r4, 0x909bcd09; +imm32 r5, 0x10a9e9db; +imm32 r6, 0x000c9d0d; +imm32 r7, 0x1246790f; +R0.L = R7.L * R0.H (T); +R1.L = R6.L * R1.L (T); +R2.H = R5.L * R2.L (T); +R3.L = R4.H * R3.L (T); +R4.L = R3.H * R4.H (T); +R5.H = R2.H * R5.L (T); +R6.L = R1.H * R6.L (T); +R7.L = R0.L * R7.L (T); +CHECKREG r0, 0x9B23A09B; +CHECKREG r1, 0xCFBAC144; +CHECKREG r2, 0xEDD46905; +CHECKREG r3, 0x0906FFF9; +CHECKREG r4, 0x909BF825; +CHECKREG r5, 0x0324E9DB; +CHECKREG r6, 0x000C2551; +CHECKREG r7, 0x1246A5C7; + +imm32 r0, 0xa9235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x08060007; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a88fdb; +imm32 r6, 0x000c080d; +imm32 r7, 0x1246708f; +R2.L = R3.L * R6.L (T); +R3.L = R4.H * R7.L (T); +R0.H = R7.L * R0.L, R0.L = R7.H * R0.H (T); +R1.H = R6.L * R1.L (T); +R4.L = R5.H * R2.L (T); +R5.L = R2.L * R3.L (T); +R6.L = R0.L * R4.L (T); +R7.H = R1.H * R5.L (T); +CHECKREG r0, 0x4C06F399; +CHECKREG r1, 0x051A5127; +CHECKREG r2, 0x13240000; +CHECKREG r3, 0x08069DFD; +CHECKREG r4, 0x908B0000; +CHECKREG r5, 0x10A80000; +CHECKREG r6, 0x000C0000; +CHECKREG r7, 0x0000708F; + +imm32 r0, 0x7b235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x17246705; +imm32 r3, 0x00760007; +imm32 r4, 0x907bcd09; +imm32 r5, 0x10a7efdb; +imm32 r6, 0x000c700d; +imm32 r7, 0x1246770f; +R4.L = R5.L * R3.L (T); +R6.L = R6.L * R4.H (T); +R0.H = R7.L * R5.H (T); +R1.L = R0.L * R6.L (T); +R2.L = R1.L * R7.H (T); +R5.L = R2.L * R2.H (T); +R3.H = R3.H * R0.L (T); +R7.L = R4.H * R1.H (T); +CHECKREG r0, 0x0F7D5675; +CHECKREG r1, 0xCFBABE0F; +CHECKREG r2, 0x1724F696; +CHECKREG r3, 0x004F0007; +CHECKREG r4, 0x907BFFFF; +CHECKREG r5, 0x10A7FE4C; +CHECKREG r6, 0x000C9E60; +CHECKREG r7, 0x12462A0E; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_u.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_u.s new file mode 100644 index 0000000..c07b136 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_u.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_m_u/c_dsp32mult_dr_m_u.dsp +// Spec Reference: dsp32mult single dr munop u +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0xfb235625; +imm32 r1, 0x9fba5127; +imm32 r2, 0xa3ff6725; +imm32 r3, 0x0006f027; +imm32 r4, 0xb0abcd29; +imm32 r5, 0x1facef2b; +imm32 r6, 0xc0fc002d; +imm32 r7, 0xd24f702f; +R4.L = R0.H * R0.L (FU); +R5.H = R0.L * R1.L (FU); +R6.L = R1.L * R0.H (FU); +R7.L = R1.L * R1.L (FU); +R0.H = R0.L * R0.L (FU); +R1.L = R0.L * R1.L (FU); +R2.L = R1.H * R0.L (FU); +R3.H = R1.L * R1.L (FU); +CHECKREG r0, 0x1CFD5625; +CHECKREG r1, 0x9FBA1B4F; +CHECKREG r2, 0xA3FF35C0; +CHECKREG r3, 0x02EAF027; +CHECKREG r4, 0xB0AB5482; +CHECKREG r5, 0x1B4FEF2B; +CHECKREG r6, 0xC0FC4F9C; +CHECKREG r7, 0xD24F19BA; + +imm32 r0, 0xbb23a635; +imm32 r1, 0x6bba5137; +imm32 r2, 0x13b4b7e5; +imm32 r3, 0x9e0b0037; +imm32 r4, 0x80ebbd39; +imm32 r5, 0xb0aeef3b; +imm32 r6, 0xa00ceb3d; +imm32 r7, 0x12467eb3; +R4.H = R2.L * R2.L (FU); +R5.L = R2.L * R3.H (FU); +R6.L = R3.H * R2.L (FU); +R7.H = R3.L * R3.L (FU); +R2.H = R2.L * R2.H (FU); +R3.L = R2.H * R3.H (FU); +R0.H = R3.L * R2.L (FU); +R1.L = R3.L * R3.L (FU); +CHECKREG r0, 0x0647A635; +CHECKREG r1, 0x6BBA004C; +CHECKREG r2, 0x0E27B7E5; +CHECKREG r3, 0x9E0B08BD; +CHECKREG r4, 0x8419BD39; +CHECKREG r5, 0xB0AE7187; +CHECKREG r6, 0xA00C7187; +CHECKREG r7, 0x00007EB3; + +imm32 r0, 0xbd235655; +imm32 r1, 0xc4dd5157; +imm32 r2, 0x6b24d755; +imm32 r3, 0x00b60055; +imm32 r4, 0x90dbc509; +imm32 r5, 0x10adbf5b; +imm32 r6, 0xb00cdb5d; +imm32 r7, 0x12467dbf; +R0.L = R4.L * R4.H (FU); +R1.H = R4.H * R5.L (FU); +R2.L = R5.H * R4.L (FU); +R3.L = R5.L * R5.L (FU); +R4.H = R4.L * R4.H (FU); +R5.L = R4.L * R5.H (FU); +R6.H = R5.H * R4.H (FU); +R7.L = R5.H * R5.H (FU); +CHECKREG r0, 0xBD236F7E; +CHECKREG r1, 0x6C475157; +CHECKREG r2, 0x6B240CD6; +CHECKREG r3, 0x00B68F09; +CHECKREG r4, 0x6F7EC509; +CHECKREG r5, 0x10AD0CD6; +CHECKREG r6, 0x0743DB5D; +CHECKREG r7, 0x12460116; + +imm32 r0, 0xcb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x1c248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90cb9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cc06d; +imm32 r7, 0x12467c6f; +// test the unsigned U=1 +R0.L = R6.L * R6.L (FU); +R1.H = R6.H * R7.L (FU); +R2.L = R7.L * R6.L (FU); +R3.L = R7.L * R7.L (FU); +R6.L = R6.L * R6.L (FU); +R7.L = R6.L * R7.L (FU); +R4.L = R7.L * R6.L (FU); +R5.L = R7.L * R7.L (FU); +CHECKREG r0, 0xCB2390A4; +CHECKREG r1, 0x3E3D5166; +CHECKREG r2, 0x1C245D88; +CHECKREG r3, 0xF0063C7C; +CHECKREG r4, 0x90CB27B9; +CHECKREG r5, 0x10AC134F; +CHECKREG r6, 0x800C90A4; +CHECKREG r7, 0x1246464E; + +// mix order +imm32 r0, 0x8b23a675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0xe0088807; +imm32 r4, 0x9eabcd09; +imm32 r5, 0x10ecdfdb; +imm32 r6, 0x000e008d; +imm32 r7, 0x1246e008; +R0.H = R0.L * R7.H (FU); +R1.L = R1.H * R6.H (FU); +R2.L = R2.L * R5.L (FU); +R3.H = R3.H * R4.H (FU); +R4.L = R4.L * R3.H (FU); +R5.L = R5.H * R2.H (FU); +R6.H = R6.H * R1.L (FU); +R7.L = R7.L * R0.H (FU); +CHECKREG r0, 0x0BE2A675; +CHECKREG r1, 0xC8BA000B; +CHECKREG r2, 0x13845A15; +CHECKREG r3, 0x8ADB8807; +CHECKREG r4, 0x9EAB6F36; +CHECKREG r5, 0x10EC014A; +CHECKREG r6, 0x0000008D; +CHECKREG r7, 0x12460A66; + +imm32 r0, 0x9b235a75; +imm32 r1, 0x7fba5127; +imm32 r2, 0x97246905; +imm32 r3, 0x09777007; +imm32 r4, 0x909bc779; +imm32 r5, 0x10a9e9d7; +imm32 r6, 0x000c9d0d; +imm32 r7, 0x1246790f; +R0.L = R7.L * R0.H (FU); +R1.L = R6.L * R1.L (FU); +R2.H = R5.L * R2.L (FU); +R3.L = R4.H * R3.L (FU); +R4.L = R3.H * R4.H (FU); +R5.H = R2.H * R5.L (FU); +R6.L = R1.H * R6.L (FU); +R7.L = R0.L * R7.L (FU); +CHECKREG r0, 0x9B23495D; +CHECKREG r1, 0x7FBA31C9; +CHECKREG r2, 0x5FEE6905; +CHECKREG r3, 0x09773F48; +CHECKREG r4, 0x909B0559; +CHECKREG r5, 0x57A0E9D7; +CHECKREG r6, 0x000C4E5C; +CHECKREG r7, 0x124622B1; + +imm32 r0, 0xa9235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x08060007; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a88fdb; +imm32 r6, 0x000c080d; +imm32 r7, 0x1246708f; +R2.L = R0.L * R6.L (FU); +R3.L = R1.H * R7.H (FU); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.L (FU); +R1.H = R3.L * R4.L (FU); +R4.L = R1.H * R2.L (FU); +R5.L = R5.L * R3.L (FU); +R6.L = R6.L * R4.L (FU); +R7.H = R7.H * R5.L (FU); +CHECKREG r0, 0x00EB0677; +CHECKREG r1, 0x0B7A5127; +CHECKREG r2, 0x132402B8; +CHECKREG r3, 0x08060E54; +CHECKREG r4, 0x908B001F; +CHECKREG r5, 0x10A8080D; +CHECKREG r6, 0x000C0001; +CHECKREG r7, 0x0093708F; + +imm32 r0, 0x7b235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x17246705; +imm32 r3, 0x00760007; +imm32 r4, 0x907bcd09; +imm32 r5, 0x10a7efdb; +imm32 r6, 0x000c700d; +imm32 r7, 0x1246770f; +R4.L = R5.L * R2.L (FU); +R6.L = R6.L * R3.H (FU); +R0.H = R7.L * R4.H (FU); +R1.L = R0.H * R5.L (FU); +R2.L = R1.L * R6.L (FU); +R5.L = R2.L * R7.H (FU); +R3.H = R3.H * R0.L (FU); +R7.L = R4.H * R1.H (FU); +CHECKREG r0, 0x43325675; +CHECKREG r1, 0xCFBA3EF5; +CHECKREG r2, 0x1724000D; +CHECKREG r3, 0x00280007; +CHECKREG r4, 0x907B6086; +CHECKREG r5, 0x10A70001; +CHECKREG r6, 0x000C0034; +CHECKREG r7, 0x1246753C; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_mix.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_mix.s new file mode 100644 index 0000000..794cbfc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_mix.s @@ -0,0 +1,196 @@ +//Original:/testcases/core/c_dsp32mult_dr_mix/c_dsp32mult_dr_mix.dsp +// Spec Reference: dsp32mult single dr (mix) u i t is tu ih +# mach: bfin + +.include "testutils.inc" + start + +// test the default (signed fraction) rounding U=0 I=0 T=0 +imm32 r0, 0xab235615; +imm32 r1, 0xcfba5117; +imm32 r2, 0x13246715; +imm32 r3, 0x00060017; +imm32 r4, 0x90abcd19; +imm32 r5, 0x10acef1b; +imm32 r6, 0x000c001d; +imm32 r7, 0x1246701f; +R2.H = R1.L * R0.L, R2.L = R1.L * R0.L; +R3.L = R1.L * R0.H (ISS2); +R4.H = R1.H * R0.L; +R5.H = R1.L * R0.H (M), R5.L = R1.H * R0.H; +R6.H = R1.H * R0.L, R6.L = R1.L * R0.L; +R7.H = R1.H * R0.H (M), R7.L = R1.H * R0.H; +CHECKREG r2, 0x36893689; +CHECKREG r3, 0x00068000; +CHECKREG r4, 0xDF89CD19; +CHECKREG r5, 0x36352001; +CHECKREG r6, 0xDF893689; +CHECKREG r7, 0xDFBB2001; + +// test the signed integer U=0 I=1 +imm32 r0, 0x8b235625; +imm32 r1, 0x9fba5127; +imm32 r2, 0xa3246725; +imm32 r3, 0x00060027; +imm32 r4, 0xb0abcd29; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c002d; +imm32 r7, 0xd246702f; +R2.H = R1.L * R0.L, R2.L = R1.L * R0.L (TFU); +R3.H = R1.L * R0.L, R3.L = R1.L * R0.H (IS); +R4.H = R1.L * R0.L, R4.L = R1.H * R0.L (ISS2); +R5.H = R1.L * R0.L, R5.L = R1.H * R0.H (IS); +R6.H = R1.L * R0.H, R6.L = R1.L * R0.L (IS); +R7.H = R1.L * R0.H, R7.L = R1.L * R0.H (IH); +CHECKREG r0, 0x8B235625; +CHECKREG r1, 0x9FBA5127; +CHECKREG r2, 0x1B4E1B4E; +CHECKREG r3, 0x7FFF8000; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x80007FFF; +CHECKREG r7, 0xDAF4DAF4; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0.H = R3.L * R2.H, R0.L = R3.H * R2.L (IS); +R1.H = R3.L * R2.H, R1.L = R3.H * R2.H (ISS2); +R4.H = R3.H * R2.L, R4.L = R3.L * R2.L (IS); +R5.H = R3.H * R2.L, R5.L = R3.L * R2.H (IS); +R6.H = R3.H * R2.L, R6.L = R3.H * R2.L (IH); +R7.H = R3.H * R2.L, R7.L = R3.H * R2.H (IS); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF8000; +CHECKREG r2, 0x1324B735; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x1FD71FD7; +CHECKREG r7, 0x7FFF8000; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R0.H = R5.H * R4.H, R0.L = R5.L * R4.L (IS); +R1.H = R5.H * R4.H, R1.L = R5.L * R4.H (ISS2); +R2.H = R5.H * R4.H, R2.L = R5.H * R4.L (IS); +R3.H = R5.H * R4.H, R3.L = R5.H * R4.H (IS); +R4.H = R6.H * R7.L, R4.L = R6.H * R7.L (IH); +R5.H = R6.L * R7.H, R5.L = R6.H * R7.H (IS); +CHECKREG r0, 0x80007FFF; +CHECKREG r1, 0x80007FFF; +CHECKREG r2, 0x80008000; +CHECKREG r3, 0x80008000; +CHECKREG r4, 0xDCE8DCE8; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0xB00C005D; +CHECKREG r7, 0x1246705F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +// test the unsigned U=1 +R2.H = R1.L * R0.L, R2.L = R1.L * R0.L (FU); +R3.H = R1.L * R0.L, R3.L = R1.L * R0.H (ISS2); +R4.H = R7.L * R6.L, R4.L = R7.H * R6.L (FU); +R5.H = R3.L * R2.L (M), R5.L = R3.H * R2.H (FU); +R6.H = R5.L * R4.H, R6.L = R5.L * R4.L (TFU); +R7.H = R5.L * R4.H, R7.L = R5.L * R4.H (FU); +CHECKREG r0, 0xBB235666; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0x1B791B79; +CHECKREG r3, 0x7FFF8000; +CHECKREG r4, 0x4D7C0C98; +CHECKREG r5, 0xF2440DBC; +CHECKREG r6, 0x042800AC; +CHECKREG r7, 0x04280428; + +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0.H = R5.L * R4.H, R0.L = R5.H * R4.L (FU); +R1.H = R3.L * R2.H, R1.L = R3.H * R2.H (IU); +R2.H = R7.H * R6.L, R2.L = R7.L * R6.L (TFU); +R3.H = R5.H * R4.L, R3.L = R5.L * R4.H (FU); +R6.H = R1.H * R0.L, R6.L = R1.H * R0.L (IH); +R7.H = R3.H * R2.L, R7.L = R3.H * R2.H (FU); +CHECKREG r0, 0x7E810D5A; +CHECKREG r1, 0x85FC72D8; +CHECKREG r2, 0x0000000C; +CHECKREG r3, 0x0D5A7E81; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0xF9A3F9A3; +CHECKREG r7, 0x00010000; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R2.H = R1.H * R0.H, R2.L = R1.L * R0.L (TFU); +R3.H = R1.H * R0.L, R3.L = R1.L * R0.H (FU); +R4.H = R6.H * R7.H, R4.L = R6.H * R7.L (ISS2); +R5.H = R6.L * R7.H, R5.L = R6.H * R7.H (FU); +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x8ADD1CAC; +CHECKREG r3, 0x49663640; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x00EE0001; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x1246700F; + +// test the ROUNDING only on signed fraction T=1 +imm32 r0, 0xab235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246700f; +R2.H = R1.L * R0.L (M), R2.L = R1.L * R0.H (IS); +R3.H = R1.H * R0.L (M), R3.L = R1.H * R0.H (FU); +R0.H = R3.L * R2.L (M), R0.L = R3.H * R2.H (T); +R1.H = R5.L * R4.H (M), R1.L = R5.L * R4.L (S2RND); +R4.H = R7.H * R6.H (M), R4.L = R7.L * R6.L (IU); +R5.H = R7.L * R6.H (M), R5.L = R7.H * R6.L (TFU); +R6.H = R5.H * R4.L (M), R6.L = R5.L * R4.H (ISS2); +R7.H = R3.L * R2.H (M), R7.L = R3.L * R2.L (IH); +CHECKREG r0, 0xC56FEFB2; +CHECKREG r1, 0xEDC10CDB; +CHECKREG r2, 0x7FFF8000; +CHECKREG r3, 0xEFB28ADE; +CHECKREG r4, 0x7FFFFFFF; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x7FFF0000; +CHECKREG r7, 0xC56F3A91; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_s.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_s.s new file mode 100644 index 0000000..1f3f967 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_s.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_s/c_dsp32mult_dr_s.dsp +// Spec Reference: dsp32mult single dr s +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (S2RND); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (S2RND); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (S2RND); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (S2RND); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (S2RND); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (S2RND); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (S2RND); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (S2RND); +CHECKREG r0, 0x73F473F4; +CHECKREG r1, 0x7FFF8000; +CHECKREG r2, 0x80007FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x73F473F4; +CHECKREG r5, 0x6D3B8000; +CHECKREG r6, 0x6D3B8000; +CHECKREG r7, 0x66E77FFF; + +imm32 r0, 0x9923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1324b735; +imm32 r3, 0x99060037; +imm32 r4, 0x809bcd39; +imm32 r5, 0xb0a99f3b; +imm32 r6, 0xa00c093d; +imm32 r7, 0x12467093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (S2RND); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (S2RND); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (S2RND); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (S2RND); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (S2RND); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (S2RND); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (S2RND); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (S2RND); +CHECKREG r0, 0xF416F416; +CHECKREG r1, 0x132C132C; +CHECKREG r2, 0xEA3BEA3B; +CHECKREG r3, 0x23072307; +CHECKREG r4, 0xEA3BEA3B; +CHECKREG r5, 0x7520E134; +CHECKREG r6, 0xFFC10010; +CHECKREG r7, 0xFFA8FFA8; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (S2RND); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (S2RND); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (S2RND); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (S2RND); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (S2RND); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (S2RND); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (S2RND); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (S2RND); +CHECKREG r0, 0x66933653; +CHECKREG r1, 0x1CF4F0A4; +CHECKREG r2, 0xF0A4F0A4; +CHECKREG r3, 0x04540458; +CHECKREG r4, 0x66933653; +CHECKREG r5, 0xE553F1DF; +CHECKREG r6, 0xF402E95B; +CHECKREG r7, 0x05E40B1E; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xe0060066; +imm32 r4, 0x9eab9d69; +imm32 r5, 0x10ecef6b; +imm32 r6, 0x800ee06d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (S2RND); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (S2RND); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (S2RND); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (S2RND); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (S2RND); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (S2RND); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (S2RND); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (S2RND); +CHECKREG r0, 0x7FFF0F94; +CHECKREG r1, 0xDB78F6FC; +CHECKREG r2, 0xDB78F6FC; +CHECKREG r3, 0x05380538; +CHECKREG r4, 0x491708E5; +CHECKREG r5, 0x14DF14DF; +CHECKREG r6, 0x7FFF0F94; +CHECKREG r7, 0x248C0473; + +// mix order +imm32 r0, 0xac23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13c46705; +imm32 r3, 0x00060007; +imm32 r4, 0x90accd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000cc00d; +imm32 r7, 0x1246fc0f; +R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (S2RND); +R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (S2RND); +R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (S2RND); +R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (S2RND); +R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (S2RND); +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (S2RND); +R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (S2RND); +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (S2RND); +CHECKREG r0, 0x0584E80E; +CHECKREG r1, 0xAEE9000F; +CHECKREG r2, 0xF613F613; +CHECKREG r3, 0xFFFAFFFA; +CHECKREG r4, 0x00050005; +CHECKREG r5, 0xFD6AFD6A; +CHECKREG r6, 0xFFF1FFF1; +CHECKREG r7, 0xF92A0193; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (S2RND); +R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (S2RND); +R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (S2RND); +R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (S2RND); +R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (S2RND); +R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (S2RND); +R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (S2RND); +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (S2RND); +CHECKREG r0, 0xE7C519D4; +CHECKREG r1, 0xFFF7108C; +CHECKREG r2, 0xF6EB1B5B; +CHECKREG r3, 0xFE8C5374; +CHECKREG r4, 0x02870128; +CHECKREG r5, 0xFDA20293; +CHECKREG r6, 0x0000FFFE; +CHECKREG r7, 0x0760F915; + +imm32 r0, 0xfb235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13f46705; +imm32 r3, 0x000f0007; +imm32 r4, 0x90abfd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (S2RND); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (S2RND); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (S2RND); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (S2RND); +R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (S2RND); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (S2RND); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (S2RND); +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (S2RND); +CHECKREG r0, 0x0016FFE6; +CHECKREG r1, 0x94D30A65; +CHECKREG r2, 0x01560010; +CHECKREG r3, 0xF238AB7A; +CHECKREG r4, 0xFFFFFDAD; +CHECKREG r5, 0x037AE9FB; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xD97200FE; + +imm32 r0, 0xab2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13246d05; +imm32 r3, 0x000600d7; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c500d; +imm32 r7, 0x1246760f; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (S2RND); +R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (S2RND); +R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (S2RND); +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (S2RND); +R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (S2RND); +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (S2RND); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (S2RND); +R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (S2RND); +CHECKREG r0, 0xF718CD46; +CHECKREG r1, 0xF2CC0CCC; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0xFF56FFE2; +CHECKREG r4, 0xE480FB2C; +CHECKREG r5, 0x00000004; +CHECKREG r6, 0x00000008; +CHECKREG r7, 0xFA8000FF; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_t.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_t.s new file mode 100644 index 0000000..fd2fe02 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_t.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_t/c_dsp32mult_dr_t.dsp +// Spec Reference: dsp32mult single dr t +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (T); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (T); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (T); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (T); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (T); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (T); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (T); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (T); +CHECKREG r0, 0x39F939F9; +CHECKREG r1, 0x24C1D139; +CHECKREG r2, 0xEAD010A5; +CHECKREG r3, 0x11180A8D; +CHECKREG r4, 0x39F939F9; +CHECKREG r5, 0x369DBA7F; +CHECKREG r6, 0x369DBA7F; +CHECKREG r7, 0x33735352; + +imm32 r0, 0x9923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1324b735; +imm32 r3, 0x99060037; +imm32 r4, 0x809bcd39; +imm32 r5, 0xb0a99f3b; +imm32 r6, 0xa00c093d; +imm32 r7, 0x12467093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (T); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (T); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (T); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (T); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (T); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (T); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (T); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (T); +CHECKREG r0, 0xFF41FF41; +CHECKREG r1, 0x00990099; +CHECKREG r2, 0xF51DF51D; +CHECKREG r3, 0x08C208C2; +CHECKREG r4, 0xF51DF51D; +CHECKREG r5, 0x3A8FF099; +CHECKREG r6, 0xFFE00008; +CHECKREG r7, 0xFFD3FFD3; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (T); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (T); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (T); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (T); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (T); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (T); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (T); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (T); +CHECKREG r0, 0x33491B29; +CHECKREG r1, 0x0E7AF851; +CHECKREG r2, 0xF851F851; +CHECKREG r3, 0x022A022B; +CHECKREG r4, 0x33491B29; +CHECKREG r5, 0xF954FC77; +CHECKREG r6, 0xFF3FFE95; +CHECKREG r7, 0x002F0059; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xe0060066; +imm32 r4, 0x9eab9d69; +imm32 r5, 0x10ecef6b; +imm32 r6, 0x800ee06d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (T); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (T); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (T); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (T); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (T); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (T); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (T); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (T); +CHECKREG r0, 0x7FE407C9; +CHECKREG r1, 0xEDBBFB7E; +CHECKREG r2, 0xEDBBFB7E; +CHECKREG r3, 0x029B029B; +CHECKREG r4, 0x123E011C; +CHECKREG r5, 0x029A029A; +CHECKREG r6, 0x7FE407C9; +CHECKREG r7, 0x1242011C; + +// mix order +imm32 r0, 0xac23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13c46705; +imm32 r3, 0x00060007; +imm32 r4, 0x90accd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000cc00d; +imm32 r7, 0x1246fc0f; +R0.H = R5.L * R7.L, R0.L = R5.H * R7.H (T); +R1.H = R7.L * R6.L, R1.L = R7.L * R6.H (T); +R2.H = R6.H * R5.H, R2.L = R6.H * R5.L (T); +R3.H = R0.L * R4.L, R3.L = R0.L * R4.L (T); +R4.H = R1.L * R5.H, R4.L = R1.L * R5.L (T); +R5.H = R3.H * R4.L, R5.L = R3.H * R4.L (T); +R6.H = R2.L * R5.L, R6.L = R2.L * R5.L (T); +R7.H = R4.H * R0.L, R7.L = R4.H * R0.H (T); +CHECKREG r0, 0x00FD0261; +CHECKREG r1, 0x01F8FFFF; +CHECKREG r2, 0x0001FFFC; +CHECKREG r3, 0xFF0DFF0D; +CHECKREG r4, 0xFFFF0000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R4.H = R7.H * R0.H, R4.L = R7.H * R0.L (T); +R5.H = R6.H * R1.H, R5.L = R6.L * R1.L (T); +R6.H = R5.H * R2.H, R6.L = R5.H * R2.L (T); +R7.H = R4.H * R3.H, R7.L = R4.H * R3.L (T); +R0.H = R3.H * R4.H, R0.L = R3.H * R4.L (T); +R2.H = R2.H * R5.H, R2.L = R2.H * R5.L (T); +R1.H = R1.H * R6.H, R1.L = R1.H * R6.L (T); +R3.H = R0.L * R7.H, R3.L = R0.H * R7.H (T); +CHECKREG r0, 0xFFEB0015; +CHECKREG r1, 0xFFFF0001; +CHECKREG r2, 0x0001FDBF; +CHECKREG r3, 0xFFFF0000; +CHECKREG r4, 0xF3E20CE9; +CHECKREG r5, 0xFFFB0846; +CHECKREG r6, 0x0001FFFB; +CHECKREG r7, 0xFFEB048A; + +imm32 r0, 0xfb235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13f46705; +imm32 r3, 0x000f0007; +imm32 r4, 0x90abfd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (T); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (T); +R0.H = R2.L * R0.L, R0.L = R2.L * R0.H (T); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (T); +R4.H = R4.L * R2.L, R4.L = R4.L * R2.H (T); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (T); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (T); +R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (T); +CHECKREG r0, 0x0005FFFF; +CHECKREG r1, 0xE5340299; +CHECKREG r2, 0x00AA0008; +CHECKREG r3, 0xF91BD5BD; +CHECKREG r4, 0xFFFFFFFC; +CHECKREG r5, 0x00DEFA7E; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xFB2D001F; + +imm32 r0, 0xab2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13246d05; +imm32 r3, 0x000600d7; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c500d; +imm32 r7, 0x1246760f; +R5.H = R5.L * R2.L, R5.L = R5.L * R2.H (T); +R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (T); +R1.H = R7.L * R4.L, R1.L = R7.L * R4.H (T); +R0.H = R1.L * R5.H, R0.L = R1.L * R5.L (T); +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (T); +R4.H = R2.L * R7.H, R4.L = R2.H * R7.L (T); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (T); +R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (T); +CHECKREG r0, 0x0B0B01F1; +CHECKREG r1, 0xD0FE9933; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00030012; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0xF23FFD95; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000000; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_tu.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_tu.s new file mode 100644 index 0000000..81ad933 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_tu.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_tu/c_dsp32mult_dr_tu.dsp +// Spec Reference: dsp32mult single dr tu +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (TFU); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (TFU); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (TFU); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (TFU); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (TFU); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (TFU); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (TFU); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (TFU); +CHECKREG r0, 0x1CFC1CFC; +CHECKREG r1, 0x0930114A; +CHECKREG r2, 0x01F5010A; +CHECKREG r3, 0x012A0054; +CHECKREG r4, 0x1CFC1CFC; +CHECKREG r5, 0x1B4E3364; +CHECKREG r6, 0x1B4E3364; +CHECKREG r7, 0x19B95B1D; + +imm32 r0, 0x9923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1324b735; +imm32 r3, 0x99060037; +imm32 r4, 0x809bcd39; +imm32 r5, 0xb0a99f3b; +imm32 r6, 0xa00c093d; +imm32 r7, 0x12467093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (TFU); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (TFU); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (TFU); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (TFU); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (TFU); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (TFU); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (TFU); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (TFU); +CHECKREG r0, 0x00700070; +CHECKREG r1, 0x00420042; +CHECKREG r2, 0x0DB20DB2; +CHECKREG r3, 0x082F082F; +CHECKREG r4, 0x0DB20DB2; +CHECKREG r5, 0x6D820B70; +CHECKREG r6, 0x00270004; +CHECKREG r7, 0x00200020; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (TFU); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (TFU); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (TFU); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (TFU); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (TFU); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (TFU); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (TFU); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (TFU); +CHECKREG r0, 0x6F5897A6; +CHECKREG r1, 0x87430CD4; +CHECKREG r2, 0x0CD40CD4; +CHECKREG r3, 0xDFCB0115; +CHECKREG r4, 0x6F5897A6; +CHECKREG r5, 0x681A8DC9; +CHECKREG r6, 0x53FD3DAA; +CHECKREG r7, 0x39A82A55; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xe0060066; +imm32 r4, 0x9eab9d69; +imm32 r5, 0x10ecef6b; +imm32 r6, 0x800ee06d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (TFU); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (TFU); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (TFU); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (TFU); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (TFU); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (TFU); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (TFU); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (TFU); +CHECKREG r0, 0x400EC4BE; +CHECKREG r1, 0x09231005; +CHECKREG r2, 0x09231005; +CHECKREG r3, 0x014D014D; +CHECKREG r4, 0x01240383; +CHECKREG r5, 0x00140014; +CHECKREG r6, 0x400EC4BE; +CHECKREG r7, 0x04920E0B; + +// mix order +imm32 r0, 0xac23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13c46705; +imm32 r3, 0x00060007; +imm32 r4, 0x90accd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000cc00d; +imm32 r7, 0x1246fc0f; +R2.H = R0.L * R7.L, R2.L = R0.H * R7.H (TFU); +R5.H = R1.L * R6.L, R5.L = R1.L * R6.H (TFU); +R6.H = R2.H * R5.L, R6.L = R2.H * R5.L (TFU); +R7.H = R3.L * R4.L, R7.L = R3.L * R4.L (TFU); +R0.H = R4.L * R3.L, R0.L = R4.L * R3.L (TFU); +R1.H = R5.H * R2.L, R1.L = R5.H * R2.L (TFU); +R3.H = R6.L * R1.L, R3.L = R6.L * R1.L (TFU); +R4.H = R7.H * R0.L, R4.L = R7.H * R0.H (TFU); +CHECKREG r0, 0x00050005; +CHECKREG r1, 0x02EB02EB; +CHECKREG r2, 0xA3E40C49; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x3CE10003; +CHECKREG r6, 0x00010001; +CHECKREG r7, 0x00050005; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (TFU); +R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (TFU); +R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (TFU); +R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (TFU); +R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (TFU); +R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (TFU); +R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (TFU); +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (TFU); +CHECKREG r0, 0x0C370674; +CHECKREG r1, 0x00090423; +CHECKREG r2, 0x0E6606D6; +CHECKREG r3, 0x0078758E; +CHECKREG r4, 0x00430060; +CHECKREG r5, 0x00F00D60; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x007500DF; + +imm32 r0, 0xfb235675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13f46705; +imm32 r3, 0x000f0007; +imm32 r4, 0x90abfd09; +imm32 r5, 0x10acefdb; +imm32 r6, 0x000c00fd; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (TFU); +R3.H = R2.H * R7.H, R3.L = R2.H * R7.L (TFU); +R0.H = R1.L * R0.L, R0.L = R1.H * R0.H (TFU); +R1.H = R3.L * R0.L, R1.L = R3.H * R0.H (TFU); +R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (TFU); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (TFU); +R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (TFU); +R7.H = R7.L * R6.L, R7.L = R7.H * R6.H (TFU); +CHECKREG r0, 0x1B68CBC7; +CHECKREG r1, 0x001D0000; +CHECKREG r2, 0x00550004; +CHECKREG r3, 0x00060025; +CHECKREG r4, 0x00030030; +CHECKREG r5, 0x00050002; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xab2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13246d05; +imm32 r3, 0x000600d7; +imm32 r4, 0x908bcd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c500d; +imm32 r7, 0x1246760f; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (TFU); +R6.H = R6.H * R3.L, R6.L = R6.H * R3.L (TFU); +R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (TFU); +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (TFU); +R2.H = R1.L * R6.L, R2.L = R1.H * R6.H (TFU); +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (TFU); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.L (TFU); +R7.H = R4.H * R1.L, R7.L = R4.H * R1.L (TFU); +CHECKREG r0, 0x08442F1A; +CHECKREG r1, 0x03102C21; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00270027; +CHECKREG r4, 0x662411EE; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x119B119B; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_dr_u.s b/sim/testsuite/sim/bfin/c_dsp32mult_dr_u.s new file mode 100644 index 0000000..47ae1b9 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_dr_u.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32mult_dr_u/c_dsp32mult_dr_u.dsp +// Spec Reference: dsp32mult single dr u +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x98ba5127; +imm32 r2, 0xa3846725; +imm32 r3, 0x00080027; +imm32 r4, 0xb0ab8d29; +imm32 r5, 0x10ace82b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467028; +R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (FU); +R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (FU); +R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (FU); +R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (FU); +R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (FU); +R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (FU); +R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (FU); +R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (FU); +CHECKREG r0, 0x1CFD1CFD; +CHECKREG r1, 0x0930114B; +CHECKREG r2, 0x01F5010A; +CHECKREG r3, 0x012B0054; +CHECKREG r4, 0x1CFD1CFD; +CHECKREG r5, 0x1B4F3365; +CHECKREG r6, 0x1B4F3365; +CHECKREG r7, 0x19BA5B1D; + +imm32 r0, 0x9923a635; +imm32 r1, 0x6f995137; +imm32 r2, 0x1324b735; +imm32 r3, 0x99060037; +imm32 r4, 0x809bcd39; +imm32 r5, 0xb0a99f3b; +imm32 r6, 0xa00c093d; +imm32 r7, 0x12467093; +R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (FU); +R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (FU); +R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (FU); +R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (FU); +R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (FU); +R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (FU); +R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (FU); +R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (FU); +CHECKREG r0, 0x00700070; +CHECKREG r1, 0x00430043; +CHECKREG r2, 0x0DB30DB3; +CHECKREG r3, 0x08300830; +CHECKREG r4, 0x0DB30DB3; +CHECKREG r5, 0x6D830B71; +CHECKREG r6, 0x00270004; +CHECKREG r7, 0x00210021; + +imm32 r0, 0x19235655; +imm32 r1, 0xc9ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x0a060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00a005d; +imm32 r7, 0x1246a05f; +R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (FU); +R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (FU); +R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (FU); +R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (FU); +R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (FU); +R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (FU); +R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (FU); +R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (FU); +CHECKREG r0, 0x6F5997A7; +CHECKREG r1, 0x87430CD5; +CHECKREG r2, 0x0CD50CD5; +CHECKREG r3, 0xDFCB0116; +CHECKREG r4, 0x6F5997A7; +CHECKREG r5, 0x681C8DCB; +CHECKREG r6, 0x53FF3DAC; +CHECKREG r7, 0x39AA2A57; + +imm32 r0, 0xb9235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x19248766; +imm32 r3, 0xe0960066; +imm32 r4, 0x9ea99d69; +imm32 r5, 0x10ec9f6b; +imm32 r6, 0x800e906d; +imm32 r7, 0x12467e6f; +// test the unsigned U=1 +R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (FU); +R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (FU); +R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (FU); +R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (FU); +R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (FU); +R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (FU); +R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (FU); +R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (FU); +CHECKREG r0, 0x400E517B; +CHECKREG r1, 0x09240A4F; +CHECKREG r2, 0x09240A4F; +CHECKREG r3, 0x014E014E; +CHECKREG r4, 0x01250174; +CHECKREG r5, 0x00150015; +CHECKREG r6, 0x400E517B; +CHECKREG r7, 0x049205D1; + +// mix order +imm32 r0, 0x9923a675; +imm32 r1, 0xcf995127; +imm32 r2, 0x13c49705; +imm32 r3, 0x05069007; +imm32 r4, 0x90accd09; +imm32 r5, 0x10ac9fdb; +imm32 r6, 0x000cc90d; +imm32 r7, 0x1246fc9f; +R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (FU); +R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (FU); +R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (FU); +R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (FU); +R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (FU); +R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (FU); +R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (FU); +R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (FU); +CHECKREG r0, 0xA4430AEE; +CHECKREG r1, 0x3FBC0004; +CHECKREG r2, 0x0C580C58; +CHECKREG r3, 0x735B735B; +CHECKREG r4, 0x5C645C64; +CHECKREG r5, 0x00CE00CE; +CHECKREG r6, 0x00030003; +CHECKREG r7, 0x00C80BBA; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0xdd246905; +imm32 r3, 0x00d6d007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10aceddb; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (FU); +R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (FU); +R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (FU); +R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (FU); +R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (FU); +R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (FU); +R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (FU); +R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (FU); +CHECKREG r0, 0x0C370675; +CHECKREG r1, 0x000A0423; +CHECKREG r2, 0x0E6706D7; +CHECKREG r3, 0x0079758F; +CHECKREG r4, 0x00440061; +CHECKREG r5, 0x00F00D62; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x007600DF; + +imm32 r0, 0xee235675; +imm32 r1, 0xcfea5127; +imm32 r2, 0x13fe6705; +imm32 r3, 0x000fe007; +imm32 r4, 0x90abfe09; +imm32 r5, 0x10acefeb; +imm32 r6, 0x000c00fe; +imm32 r7, 0x1246700f; +R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (FU); +R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (FU); +R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (FU); +R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (FU); +R4.H = R4.L * R2.L, R4.L = R4.L * R2.H (FU); +R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (FU); +R6.H = R6.H * R5.L, R6.L = R6.L * R5.H (FU); +R7.H = R7.L * R4.L, R7.L = R7.H * R4.H (FU); +CHECKREG r0, 0x00010050; +CHECKREG r1, 0x1CDA0C0D; +CHECKREG r2, 0x00560004; +CHECKREG r3, 0x0ED75B03; +CHECKREG r4, 0x00040055; +CHECKREG r5, 0x0DE805ED; +CHECKREG r6, 0x0000000E; +CHECKREG r7, 0x00250000; + +imm32 r0, 0xfb2d5675; +imm32 r1, 0xcfbad127; +imm32 r2, 0x13f46d05; +imm32 r3, 0x000f00d7; +imm32 r4, 0x908bfd09; +imm32 r5, 0x10a9efdb; +imm32 r6, 0x000c5f0d; +imm32 r7, 0x124676ff; +R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (FU); +R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (FU); +R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (FU); +R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (FU); +R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (FU); +R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (FU); +R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (FU); +R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (FU); +CHECKREG r0, 0x08B12F7B; +CHECKREG r1, 0x03172C7C; +CHECKREG r2, 0x00010000; +CHECKREG r3, 0x00280007; +CHECKREG r4, 0x662512B2; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x11C0003A; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair.s new file mode 100644 index 0000000..99d3504 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_pair.s @@ -0,0 +1,179 @@ +//Original:/testcases/core/c_dsp32mult_pair/c_dsp32mult_pair.dsp +// Spec Reference: dsp32mult pair +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x93ba5127; +imm32 r2, 0xa3446725; +imm32 r3, 0x00050027; +imm32 r4, 0xb0ab6d29; +imm32 r5, 0x10ace72b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467029; +R1 = R0.L * R0.L, R0 = R0.L * R0.L; +R3 = R0.L * R1.L, R2 = R0.L * R1.H; +R5 = R1.L * R0.L, R4 = R1.H * R0.L; +R7 = R1.L * R1.L, R6 = R1.H * R1.H; +CHECKREG r0, 0x39F9C2B2; +CHECKREG r1, 0x39F9C2B2; +CHECKREG r2, 0xE43C0244; +CHECKREG r3, 0x1D5C8788; +CHECKREG r4, 0xE43C0244; +CHECKREG r5, 0x1D5C8788; +CHECKREG r6, 0x1A41A862; +CHECKREG r7, 0x1D5C8788; + +imm32 r0, 0x5b33a635; +imm32 r1, 0x6fbe5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x9006d037; +imm32 r4, 0x80abcb39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c00dd; +imm32 r7, 0x12469003; +R1 = R2.L * R2.L, R0 = R2.L * R2.L; +R3 = R2.L * R3.L, R2 = R2.L * R3.H; +R5 = R3.L * R2.L, R4 = R3.H * R2.L; +R7 = R3.L * R3.L, R6 = R3.H * R3.H; +CHECKREG r0, 0x2965A1F2; +CHECKREG r1, 0x2965A1F2; +CHECKREG r2, 0x3FAE367C; +CHECKREG r3, 0x1B2CD8C6; +CHECKREG r4, 0x0B90E2A0; +CHECKREG r5, 0xEF4D87D0; +CHECKREG r6, 0x05C49F20; +CHECKREG r7, 0x0C057248; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R1 = R4.L * R4.L, R0 = R4.L * R4.L; +R3 = R4.L * R5.L, R2 = R4.L * R5.H; +R5 = R5.L * R4.L, R4 = R5.H * R4.L; +R7 = R5.L * R5.L, R6 = R5.H * R5.H; +CHECKREG r0, 0x1B29B4A2; +CHECKREG r1, 0x1B29B4A2; +CHECKREG r2, 0xF851E418; +CHECKREG r3, 0x07AAE266; +CHECKREG r4, 0xF851E418; +CHECKREG r5, 0x07AAE266; +CHECKREG r6, 0x007579C8; +CHECKREG r7, 0x06D88148; + +imm32 r0, 0xab235666; +imm32 r1, 0xeaba5166; +imm32 r2, 0x13d48766; +imm32 r3, 0xf00b0066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10ac5f6b; +imm32 r6, 0x800cb66d; +imm32 r7, 0x1246707f; +R1 = R6.L * R6.L, R0 = R6.L * R6.L; +R3 = R6.L * R7.L, R2 = R6.L * R7.H; +R5 = R7.L * R6.L, R4 = R7.H * R6.L; +R7 = R7.L * R7.L, R6 = R7.H * R7.H; +CHECKREG r0, 0x2A4A54D2; +CHECKREG r1, 0x2A4A54D2; +CHECKREG r2, 0xF57F179C; +CHECKREG r3, 0xBF566026; +CHECKREG r4, 0xF57F179C; +CHECKREG r5, 0xBF566026; +CHECKREG r6, 0x029BD648; +CHECKREG r7, 0x62DEBE02; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R1 = R3.L * R2.L (M), R0 = R3.L * R2.H; +R3 = R1.L * R0.H, R2 = R1.H * R0.L; +R5 = R7.H * R4.L, R4 = R7.H * R4.L; +R7 = R5.L * R6.L (M), R6 = R5.H * R6.L; +CHECKREG r0, 0x00010BF8; +CHECKREG r1, 0x0002D123; +CHECKREG r2, 0x00002FE0; +CHECKREG r3, 0xFFFFA246; +CHECKREG r4, 0xF8B964EC; +CHECKREG r5, 0xF8B964EC; +CHECKREG r6, 0xFFFF42CA; +CHECKREG r7, 0x00051FFC; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946905; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d9d; +imm32 r7, 0x12467009; +R3 = R6.L * R5.L, R2 = R6.L * R5.H; +R1 = R3.L * R0.H (M), R0 = R3.H * R0.L; +R5 = R1.L * R4.L (M), R4 = R1.H * R4.L; +R7 = R2.H * R7.L, R6 = R2.H * R7.L; +CHECKREG r0, 0xFE55DCD2; +CHECKREG r1, 0x0C7E7B9A; +CHECKREG r2, 0x01C5EAF8; +CHECKREG r3, 0xFDA5149E; +CHECKREG r4, 0xF6576CDC; +CHECKREG r5, 0x4BD1CA6A; +CHECKREG r6, 0x018C7FDA; +CHECKREG r7, 0x018C7FDA; + +imm32 r0, 0x8b235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0x00080007; +imm32 r4, 0x90ab8d09; +imm32 r5, 0x10ace8db; +imm32 r6, 0x000c008d; +imm32 r7, 0x12467008; +R3 = R6.H * R5.L, R2 = R6.L * R5.H; +R7 = R2.L * R0.H (M), R6 = R2.H * R0.L; +R5 = R1.L * R3.L (M), R4 = R1.H * R3.L; +R1 = R2.H * R7.L, R0 = R2.L * R7.H; +CHECKREG r0, 0x2517D740; +CHECKREG r1, 0xFFFDAAA0; +CHECKREG r2, 0x00125D78; +CHECKREG r3, 0xFFFDD488; +CHECKREG r4, 0x12C555A0; +CHECKREG r5, 0x435F68B8; +CHECKREG r6, 0x000C2874; +CHECKREG r7, 0x32CCEF68; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R1.H * R4.L, R0 = R1.H * R4.L; +R3 = R2.L * R5.L, R2 = R2.L * R5.H; +R5 = R3.H * R6.L, R4 = R3.L * R6.L; +R7 = R4.L * R0.H, R6 = R4.H * R0.L; +CHECKREG r0, 0x074CED14; +CHECKREG r1, 0x074CED14; +CHECKREG r2, 0x0D6B0EB8; +CHECKREG r3, 0xF2338E8E; +CHECKREG r4, 0xFF2DF2EC; +CHECKREG r5, 0xFFE6726E; +CHECKREG r6, 0x001F3108; +CHECKREG r7, 0xFF412420; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_i.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_i.s new file mode 100644 index 0000000..2d0d320 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_pair_i.s @@ -0,0 +1,179 @@ +//Original:/testcases/core/c_dsp32mult_pair_i/c_dsp32mult_pair_i.dsp +// Spec Reference: dsp32mult pair i +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x93ba5127; +imm32 r2, 0xa3446725; +imm32 r3, 0x00050027; +imm32 r4, 0xb0ab6d29; +imm32 r5, 0x10ace72b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467029; +R1 = R0.L * R0.L, R0 = R0.L * R0.L (IS); +R3 = R0.L * R1.L, R2 = R0.L * R1.H (IS); +R5 = R1.L * R0.L, R4 = R1.H * R0.L (IS); +R7 = R1.L * R1.L, R6 = R1.H * R1.H (IS); +CHECKREG r0, 0x1CFCE159; +CHECKREG r1, 0x1CFCE159; +CHECKREG r2, 0xFC878F9C; +CHECKREG r3, 0x03AB90F1; +CHECKREG r4, 0xFC878F9C; +CHECKREG r5, 0x03AB90F1; +CHECKREG r6, 0x03481810; +CHECKREG r7, 0x03AB90F1; + +imm32 r0, 0x5b33a635; +imm32 r1, 0x6fbe5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x9006d037; +imm32 r4, 0x80abcb39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c00dd; +imm32 r7, 0x12469003; +R1 = R2.L * R2.L, R0 = R2.L * R2.L (IS); +R3 = R2.L * R3.L, R2 = R2.L * R3.H (IS); +R5 = R3.L * R2.L, R4 = R3.H * R2.L (IS); +R7 = R3.L * R3.L, R6 = R3.H * R3.H (IS); +CHECKREG r0, 0x14B2D0F9; +CHECKREG r1, 0x14B2D0F9; +CHECKREG r2, 0x1FD71B3E; +CHECKREG r3, 0x0D966C63; +CHECKREG r4, 0x01721C54; +CHECKREG r5, 0x0B88B0FA; +CHECKREG r6, 0x00B893E4; +CHECKREG r7, 0x2DE3AE49; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R1 = R4.L * R4.L, R0 = R4.L * R4.L (IS); +R3 = R4.L * R5.L, R2 = R4.L * R5.H (IS); +R5 = R5.L * R4.L, R4 = R5.H * R4.L (IS); +R7 = R5.L * R5.L, R6 = R5.H * R5.H (IS); +CHECKREG r0, 0x0D94DA51; +CHECKREG r1, 0x0D94DA51; +CHECKREG r2, 0xFC28F20C; +CHECKREG r3, 0x03D57133; +CHECKREG r4, 0xFC28F20C; +CHECKREG r5, 0x03D57133; +CHECKREG r6, 0x000EAF39; +CHECKREG r7, 0x320E1029; + +imm32 r0, 0xab235666; +imm32 r1, 0xeaba5166; +imm32 r2, 0x13d48766; +imm32 r3, 0xf00b0066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10ac5f6b; +imm32 r6, 0x800cb66d; +imm32 r7, 0x1246707f; +R1 = R6.L * R6.L, R0 = R6.L * R6.L (IS); +R3 = R6.L * R7.L, R2 = R6.L * R7.H (IS); +R5 = R7.L * R6.L, R4 = R7.H * R6.L (IS); +R7 = R7.L * R7.L, R6 = R7.H * R7.H (IS); +CHECKREG r0, 0x15252A69; +CHECKREG r1, 0x15252A69; +CHECKREG r2, 0xFABF8BCE; +CHECKREG r3, 0xDFAB3013; +CHECKREG r4, 0xFABF8BCE; +CHECKREG r5, 0xDFAB3013; +CHECKREG r6, 0x014DEB24; +CHECKREG r7, 0x316F5F01; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (IS); +R3 = R1.L * R0.H, R2 = R1.H * R0.L (IS); +R5 = R7.H * R4.L, R4 = R7.H * R4.L (IS); +R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (IS); +CHECKREG r0, 0x000085FC; +CHECKREG r1, 0x0002D123; +CHECKREG r2, 0xFFFF0BF8; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0xFC5CB276; +CHECKREG r5, 0xFC5CB276; +CHECKREG r6, 0xFFFFD0AC; +CHECKREG r7, 0xFFFC0FFE; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946905; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d9d; +imm32 r7, 0x12467009; +R3 = R6.L * R5.L, R2 = R6.L * R5.H (IS); +R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (IS); +R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (IS); +R7 = R2.H * R7.L, R6 = R2.H * R7.L (IS); +CHECKREG r0, 0xFF9549FA; +CHECKREG r1, 0xB8ADBDCD; +CHECKREG r2, 0x00E2F57C; +CHECKREG r3, 0xFED28A4F; +CHECKREG r4, 0x1B929715; +CHECKREG r5, 0xD7646535; +CHECKREG r6, 0x0062E7F2; +CHECKREG r7, 0x0062E7F2; + +imm32 r0, 0x8b235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0x00080007; +imm32 r4, 0x90ab8d09; +imm32 r5, 0x10ace8db; +imm32 r6, 0x000c008d; +imm32 r7, 0x12467008; +R3 = R6.H * R5.L, R2 = R6.L * R5.H (IS); +R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (IS); +R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (IS); +R1 = R2.H * R7.L, R0 = R2.L * R7.H (IS); +CHECKREG r0, 0x04A2FAE8; +CHECKREG r1, 0x00043554; +CHECKREG r2, 0x00092EBC; +CHECKREG r3, 0xFFFEEA44; +CHECKREG r4, 0x04B15568; +CHECKREG r5, 0x4A43345C; +CHECKREG r6, 0x00030A1D; +CHECKREG r7, 0x196677B4; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R1.H * R4.L, R0 = R1.H * R4.L (IS); +R3 = R2.L * R5.L, R2 = R2.L * R5.H (IS); +R5 = R3.H * R6.L, R4 = R3.L * R6.L (IS); +R7 = R4.L * R0.H, R6 = R4.H * R0.L (IS); +CHECKREG r0, 0x03A6768A; +CHECKREG r1, 0x03A6768A; +CHECKREG r2, 0x06B5875C; +CHECKREG r3, 0xF919C747; +CHECKREG r4, 0xFFCB7CBB; +CHECKREG r5, 0xFFF99C25; +CHECKREG r6, 0xFFE7756E; +CHECKREG r7, 0x01C71242; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_is.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_is.s new file mode 100644 index 0000000..d4a7d88 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_pair_is.s @@ -0,0 +1,179 @@ +//Original:/testcases/core/c_dsp32mult_pair_is/c_dsp32mult_pair_is.dsp +// Spec Reference: dsp32mult pair is +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x93ba5127; +imm32 r2, 0xa3446725; +imm32 r3, 0x00050027; +imm32 r4, 0xb0ab6d29; +imm32 r5, 0x10ace72b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467029; +R1 = R0.L * R0.L, R0 = R0.L * R0.L (ISS2); +R3 = R0.L * R1.L, R2 = R0.L * R1.H (ISS2); +R5 = R1.L * R0.L, R4 = R1.H * R0.L (ISS2); +R7 = R1.L * R1.L, R6 = R1.H * R1.H (ISS2); +CHECKREG r0, 0x39F9C2B2; +CHECKREG r1, 0x39F9C2B2; +CHECKREG r2, 0xE43C0244; +CHECKREG r3, 0x1D5C8788; +CHECKREG r4, 0xE43C0244; +CHECKREG r5, 0x1D5C8788; +CHECKREG r6, 0x1A41A862; +CHECKREG r7, 0x1D5C8788; + +imm32 r0, 0x5b33a635; +imm32 r1, 0x6fbe5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x9006d037; +imm32 r4, 0x80abcb39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c00dd; +imm32 r7, 0x12469003; +R1 = R2.L * R2.L, R0 = R2.L * R2.L (ISS2); +R3 = R2.L * R3.L, R2 = R2.L * R3.H (ISS2); +R5 = R3.L * R2.L, R4 = R3.H * R2.L (ISS2); +R7 = R3.L * R3.L, R6 = R3.H * R3.H (ISS2); +CHECKREG r0, 0x2965A1F2; +CHECKREG r1, 0x2965A1F2; +CHECKREG r2, 0x3FAE367C; +CHECKREG r3, 0x1B2CD8C6; +CHECKREG r4, 0x0B90E2A0; +CHECKREG r5, 0xEF4D87D0; +CHECKREG r6, 0x05C49F20; +CHECKREG r7, 0x0C057248; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R1 = R4.L * R4.L, R0 = R4.L * R4.L (ISS2); +R3 = R4.L * R5.L, R2 = R4.L * R5.H (ISS2); +R5 = R5.L * R4.L, R4 = R5.H * R4.L (ISS2); +R7 = R5.L * R5.L, R6 = R5.H * R5.H (ISS2); +CHECKREG r0, 0x1B29B4A2; +CHECKREG r1, 0x1B29B4A2; +CHECKREG r2, 0xF851E418; +CHECKREG r3, 0x07AAE266; +CHECKREG r4, 0xF851E418; +CHECKREG r5, 0x07AAE266; +CHECKREG r6, 0x007579C8; +CHECKREG r7, 0x06D88148; + +imm32 r0, 0xab235666; +imm32 r1, 0xeaba5166; +imm32 r2, 0x13d48766; +imm32 r3, 0xf00b0066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10ac5f6b; +imm32 r6, 0x800cb66d; +imm32 r7, 0x1246707f; +R1 = R6.L * R6.L, R0 = R6.L * R6.L (ISS2); +R3 = R6.L * R7.L, R2 = R6.L * R7.H (ISS2); +R5 = R7.L * R6.L, R4 = R7.H * R6.L (ISS2); +R7 = R7.L * R7.L, R6 = R7.H * R7.H (ISS2); +CHECKREG r0, 0x2A4A54D2; +CHECKREG r1, 0x2A4A54D2; +CHECKREG r2, 0xF57F179C; +CHECKREG r3, 0xBF566026; +CHECKREG r4, 0xF57F179C; +CHECKREG r5, 0xBF566026; +CHECKREG r6, 0x029BD648; +CHECKREG r7, 0x62DEBE02; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (ISS2); +R3 = R1.L * R0.H, R2 = R1.H * R0.L (ISS2); +R5 = R7.H * R4.L, R4 = R7.H * R4.L (ISS2); +R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (ISS2); +CHECKREG r0, 0x00010BF8; +CHECKREG r1, 0x0005A246; +CHECKREG r2, 0x000077B0; +CHECKREG r3, 0xFFFF448C; +CHECKREG r4, 0xF8B964EC; +CHECKREG r5, 0xF8B964EC; +CHECKREG r6, 0xFFFF42CA; +CHECKREG r7, 0x000A3FF8; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946905; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d9d; +imm32 r7, 0x12467009; +R3 = R6.L * R5.L, R2 = R6.L * R5.H (ISS2); +R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (ISS2); +R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (ISS2); +R7 = R2.H * R7.L, R6 = R2.H * R7.L (ISS2); +CHECKREG r0, 0xFE55DCD2; +CHECKREG r1, 0x18FCF734; +CHECKREG r2, 0x01C5EAF8; +CHECKREG r3, 0xFDA5149E; +CHECKREG r4, 0xECAED9B8; +CHECKREG r5, 0xF53529A8; +CHECKREG r6, 0x018C7FDA; +CHECKREG r7, 0x018C7FDA; + +imm32 r0, 0x8b235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0x00080007; +imm32 r4, 0x90ab8d09; +imm32 r5, 0x10ace8db; +imm32 r6, 0x000c008d; +imm32 r7, 0x12467008; +R3 = R6.H * R5.L, R2 = R6.L * R5.H (ISS2); +R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (ISS2); +R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (ISS2); +R1 = R2.H * R7.L, R0 = R2.L * R7.H (ISS2); +CHECKREG r0, 0x4A306970; +CHECKREG r1, 0xFFFB5540; +CHECKREG r2, 0x00125D78; +CHECKREG r3, 0xFFFDD488; +CHECKREG r4, 0x12C555A0; +CHECKREG r5, 0x7FFFFFFF; +CHECKREG r6, 0x000C2874; +CHECKREG r7, 0x6599DED0; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R1.H * R4.L, R0 = R1.H * R4.L (ISS2); +R3 = R2.L * R5.L, R2 = R2.L * R5.H (ISS2); +R5 = R3.H * R6.L, R4 = R3.L * R6.L (ISS2); +R7 = R4.L * R0.H, R6 = R4.H * R0.L (ISS2); +CHECKREG r0, 0x074CED14; +CHECKREG r1, 0x074CED14; +CHECKREG r2, 0x0D6B0EB8; +CHECKREG r3, 0xF2338E8E; +CHECKREG r4, 0xFF2DF2EC; +CHECKREG r5, 0xFFE6726E; +CHECKREG r6, 0x001F3108; +CHECKREG r7, 0xFF412420; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m.s new file mode 100644 index 0000000..73ab875 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m/c_dsp32mult_pair_m.dsp +// Spec Reference: dsp32mult pair MUNOP +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L; +R2 = R0.L * R1.H; +R4 = R1.H * R1.H; +R6 = R0.L * R0.L; +CHECKREG r0, 0x39F9C2B2; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x2E3AADA8; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x48C98C48; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0x1D5C8788; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L; +R2 = R2.L * R3.H; +R4 = R3.H * R2.H; +R6 = R2.L * R3.L; +CHECKREG r0, 0x2965A1F2; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x3FAE367C; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0xC84ABC28; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x00176948; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L; +R2 = R4.L * R5.H; +R4 = R5.H * R5.H; +R6 = R4.L * R5.L; +CHECKREG r0, 0x1B29B4A2; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0xF85431BE; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x022A99E2; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0x0D4762AC; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L; +R2 = R6.L * R7.H; +R4 = R7.H * R7.H; +R6 = R6.L * R7.L; +CHECKREG r0, 0x31781CD2; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0xF4A3CF9C; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x029BD648; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0xBA1A5E86; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L; +R2 = R1.L * R6.H; +R4 = R3.H * R4.H; +R6 = R4.L * R3.L; +CHECKREG r0, 0x0B26E1B6; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x00079BA8; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0xFFFAC804; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0xFFFCF038; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H; +R3 = R6.H * R1.H; +R5 = R5.H * R2.L; +R7 = R4.L * R3.H; +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0xF3E28324; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0xFFFEDD30; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x0DADBEB8; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x0000CBDC; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L; +R3 = R5.L * R3.H; +R5 = R3.H * R1.L; +R7 = R1.H * R2.H; +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0xFFF6B8D8; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0xFFFE7166; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0x00011CA0; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0xFFFE7870; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H; +R3 = R6.H * R1.H; +R5 = R1.L * R2.L; +R7 = R4.H * R2.L; +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0x03175676; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x00004A28; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0x4596549C; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0xA66540AE; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_i.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_i.s new file mode 100644 index 0000000..b865be0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_i.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m_i/c_dsp32mult_pair_m_i.dsp +// Spec Reference: dsp32mult pair MUNOP i +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L (IS); +R2 = R0.L * R1.H (IS); +R4 = R1.H * R1.H (IS); +R6 = R0.L * R0.L (IS); +CHECKREG r0, 0x1CFCE159; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x0B8EAB6A; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x2464C624; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0x03AB90F1; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L (IS); +R2 = R2.L * R3.H (IS); +R4 = R3.H * R2.H (IS); +R6 = R2.L * R3.L (IS); +CHECKREG r0, 0x14B2D0F9; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x1FD71B3E; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0xF212AF0A; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x0005DA52; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L (IS); +R2 = R4.L * R5.H (IS); +R4 = R5.H * R5.H (IS); +R6 = R4.L * R5.L (IS); +CHECKREG r0, 0x0D94DA51; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0xFC2A18DF; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x01154CF1; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0xFAFF58AB; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L (IS); +R2 = R6.L * R7.H (IS); +R4 = R7.H * R7.H (IS); +R6 = R6.L * R7.L (IS); +CHECKREG r0, 0x18BC0E69; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0xFA51E7CE; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x014DEB24; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0xDD0D2F43; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L (IS); +R2 = R1.L * R6.H (IS); +R4 = R3.H * R4.H (IS); +R6 = R4.L * R3.L (IS); +CHECKREG r0, 0x059370DB; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x0003CDD4; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0xFFFD6402; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0x0002BC0E; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H (IS); +R3 = R6.H * R1.H (IS); +R5 = R5.H * R2.L (IS); +R7 = R4.L * R3.H (IS); +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0xF9F14192; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0xFFFFB74C; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x06D6DF5C; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x000032F7; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L (IS); +R3 = R5.L * R3.H (IS); +R5 = R3.H * R1.L (IS); +R7 = R1.H * R2.H (IS); +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0xFFFB5C6C; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0xFFFF38B3; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0xFFFFA394; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0xFFFF9E1C; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H (IS); +R3 = R6.H * R1.H (IS); +R5 = R1.L * R2.L (IS); +R7 = R4.H * R2.L (IS); +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0x018BAB3B; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x00001284; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0xDDE31527; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0xD332A057; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_is.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_is.s new file mode 100644 index 0000000..073b7f3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_is.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m_is/c_dsp32mult_pair_m_is.dsp +// Spec Reference: dsp32mult pair MUNOP is +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L (ISS2); +R2 = R0.L * R1.H (ISS2); +R4 = R1.H * R1.H (ISS2); +R6 = R0.L * R0.L (ISS2); +CHECKREG r0, 0x39F9C2B2; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x2E3AADA8; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x48C98C48; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0x1D5C8788; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L (ISS2); +R2 = R2.L * R3.H (ISS2); +R4 = R3.H * R2.H (ISS2); +R6 = R2.L * R3.L (ISS2); +CHECKREG r0, 0x2965A1F2; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x3FAE367C; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0xC84ABC28; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x00176948; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L (ISS2); +R2 = R4.L * R5.H (ISS2); +R4 = R5.H * R5.H (ISS2); +R6 = R4.L * R5.L (ISS2); +CHECKREG r0, 0x1B29B4A2; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0xF85431BE; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x022A99E2; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0x0D4762AC; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L (ISS2); +R2 = R6.L * R7.H (ISS2); +R4 = R7.H * R7.H (ISS2); +R6 = R6.L * R7.L (ISS2); +CHECKREG r0, 0x31781CD2; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0xF4A3CF9C; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x029BD648; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0xBA1A5E86; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L (ISS2); +R2 = R1.L * R6.H (ISS2); +R4 = R3.H * R4.H (ISS2); +R6 = R4.L * R3.L (ISS2); +CHECKREG r0, 0x0B26E1B6; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x00079BA8; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0xFFFAC804; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0xFFFCF038; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H (ISS2); +R3 = R6.H * R1.H (ISS2); +R5 = R5.H * R2.L (ISS2); +R7 = R4.L * R3.H (ISS2); +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0xF3E28324; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0xFFFEDD30; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x0DADBEB8; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x0000CBDC; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L (ISS2); +R3 = R5.L * R3.H (ISS2); +R5 = R3.H * R1.L (ISS2); +R7 = R1.H * R2.H (ISS2); +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0xFFF6B8D8; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0xFFFE7166; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0x00011CA0; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0xFFFE7870; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H (ISS2); +R3 = R6.H * R1.H (ISS2); +R5 = R1.L * R2.L (ISS2); +R7 = R4.H * R2.L (ISS2); +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0x03175676; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x00004A28; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0x4596549C; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0xA66540AE; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_s.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_s.s new file mode 100644 index 0000000..71b95eb --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_s.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m_s/c_dsp32mult_pair_m_s.dsp +// Spec Reference: dsp32mult pair MUNOP s +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L (S2RND); +R2 = R0.L * R1.H (S2RND); +R4 = R1.H * R1.H (S2RND); +R6 = R0.L * R0.L (S2RND); +CHECKREG r0, 0x73F38564; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x7FFFFFFF; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x7FFFFFFF; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0x7FFFFFFF; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L (S2RND); +R2 = R2.L * R3.H (S2RND); +R4 = R3.H * R2.H (S2RND); +R6 = R2.L * R3.L (S2RND); +CHECKREG r0, 0x52CB43E4; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x7F5C6CF8; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x005DA520; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L (S2RND); +R2 = R4.L * R5.H (S2RND); +R4 = R5.H * R5.H (S2RND); +R6 = R4.L * R5.L (S2RND); +CHECKREG r0, 0x36536944; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0xF0A8637C; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x045533C4; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0xF2898AB0; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L (S2RND); +R2 = R6.L * R7.H (S2RND); +R4 = R7.H * R7.H (S2RND); +R6 = R6.L * R7.L (S2RND); +CHECKREG r0, 0x62F039A4; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0xE9479F38; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x0537AC90; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L (S2RND); +R2 = R1.L * R6.H (S2RND); +R4 = R3.H * R4.H (S2RND); +R6 = R4.L * R3.L (S2RND); +CHECKREG r0, 0x164DC36C; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x000F3750; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0xFFF59008; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0xFFF3C0E0; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H (S2RND); +R3 = R6.H * R1.H (S2RND); +R5 = R5.H * R2.L (S2RND); +R7 = R4.L * R3.H (S2RND); +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0xE7C50648; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0xFFFB74F0; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x1B5B7D70; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x0003FB4C; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L (S2RND); +R3 = R5.L * R3.H (S2RND); +R5 = R3.H * R1.L (S2RND); +R7 = R1.H * R2.H (S2RND); +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0xFFED71B0; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0xFFFCE2CC; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0xFFF8E500; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0xFFFA3010; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H (S2RND); +R3 = R6.H * R1.H (S2RND); +R5 = R1.L * R2.L (S2RND); +R7 = R4.H * R2.L (S2RND); +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0x062EACEC; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x000128A0; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0x80000000; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_u.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_u.s new file mode 100644 index 0000000..d7f6633 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_pair_m_u.s @@ -0,0 +1,178 @@ +//Original:/testcases/core/c_dsp32mult_pair_m_u/c_dsp32mult_pair_m_u.dsp +// Spec Reference: dsp32mult pair MUNOP u +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x34235625; +imm32 r1, 0x9f7a5127; +imm32 r2, 0xa3286725; +imm32 r3, 0x00069027; +imm32 r4, 0xb0abc029; +imm32 r5, 0x10acef2b; +imm32 r6, 0xc00c00de; +imm32 r7, 0xd246712f; +R0 = R0.L * R0.L (FU); +R2 = R0.L * R1.H (FU); +R4 = R1.H * R1.H (FU); +R6 = R0.L * R0.L (FU); +CHECKREG r0, 0x1CFCE159; +CHECKREG r1, 0x9F7A5127; +CHECKREG r2, 0x8C61AB6A; +CHECKREG r3, 0x00069027; +CHECKREG r4, 0x6358C624; +CHECKREG r5, 0x10ACEF2B; +CHECKREG r6, 0xC65D90F1; +CHECKREG r7, 0xD246712F; + +imm32 r0, 0x5b23a635; +imm32 r1, 0x6fba5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x90060037; +imm32 r4, 0x80abcd39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c003d; +imm32 r7, 0x12467003; +R0 = R2.L * R2.L (FU); +R2 = R2.L * R3.H (FU); +R4 = R3.H * R2.H (FU); +R6 = R2.L * R3.L (FU); +CHECKREG r0, 0x831CD0F9; +CHECKREG r1, 0x6FBA5137; +CHECKREG r2, 0x67121B3E; +CHECKREG r3, 0x90060037; +CHECKREG r4, 0x39FC8A6C; +CHECKREG r5, 0xB0ACEF3B; +CHECKREG r6, 0x0005DA52; +CHECKREG r7, 0x12467003; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x43246755; +imm32 r3, 0x05060055; +imm32 r4, 0x906bc509; +imm32 r5, 0x10a7ef5b; +imm32 r6, 0xb00c805d; +imm32 r7, 0x1246795f; +R0 = R4.L * R4.L (FU); +R2 = R4.L * R5.H (FU); +R4 = R5.H * R5.H (FU); +R6 = R4.L * R5.L (FU); +CHECKREG r0, 0x97A6DA51; +CHECKREG r1, 0xC4BA5157; +CHECKREG r2, 0x0CD118DF; +CHECKREG r3, 0x05060055; +CHECKREG r4, 0x01154CF1; +CHECKREG r5, 0x10A7EF5B; +CHECKREG r6, 0x47F058AB; +CHECKREG r7, 0x1246795F; + +imm32 r0, 0xbb235666; +imm32 r1, 0xefba5166; +imm32 r2, 0x13248766; +imm32 r3, 0xf0060066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10acef6b; +imm32 r6, 0x800cb06d; +imm32 r7, 0x1246706f; +R0 = R6.L * R6.L (FU); +R2 = R6.L * R7.H (FU); +R4 = R7.H * R7.H (FU); +R6 = R6.L * R7.L (FU); +CHECKREG r0, 0x79960E69; +CHECKREG r1, 0xEFBA5166; +CHECKREG r2, 0x0C97E7CE; +CHECKREG r3, 0xF0060066; +CHECKREG r4, 0x014DEB24; +CHECKREG r5, 0x10ACEF6B; +CHECKREG r6, 0x4D7C2F43; +CHECKREG r7, 0x1246706F; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R0 = R0.L * R7.L (FU); +R2 = R1.L * R6.H (FU); +R4 = R3.H * R4.H (FU); +R6 = R4.L * R3.L (FU); +CHECKREG r0, 0x9C1770DB; +CHECKREG r1, 0xCFBA5127; +CHECKREG r2, 0x0003CDD4; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00036402; +CHECKREG r5, 0x10ACDFDB; +CHECKREG r6, 0x0002BC0E; +CHECKREG r7, 0x1246F00F; + +imm32 r0, 0xab235a75; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246905; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d0d; +imm32 r7, 0x1246700f; +R1 = R7.H * R0.H (FU); +R3 = R6.H * R1.H (FU); +R5 = R5.H * R2.L (FU); +R7 = R4.L * R3.H (FU); +CHECKREG r0, 0xAB235A75; +CHECKREG r1, 0x0C374192; +CHECKREG r2, 0x13246905; +CHECKREG r3, 0x00009294; +CHECKREG r4, 0x90ABCD09; +CHECKREG r5, 0x06D6DF5C; +CHECKREG r6, 0x000C0D0D; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x9b235675; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946705; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c009d; +imm32 r7, 0x12467009; +R1 = R6.H * R4.L (FU); +R3 = R5.L * R3.H (FU); +R5 = R3.H * R1.L (FU); +R7 = R1.H * R2.H (FU); +CHECKREG r0, 0x9B235675; +CHECKREG r1, 0x00075C6C; +CHECKREG r2, 0x13946705; +CHECKREG r3, 0x000838B3; +CHECKREG r4, 0x90AB9D09; +CHECKREG r5, 0x0002E360; +CHECKREG r6, 0x000C009D; +CHECKREG r7, 0x0000890C; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R4.L * R0.H (FU); +R3 = R6.H * R1.H (FU); +R5 = R1.L * R2.L (FU); +R7 = R4.H * R2.L (FU); +CHECKREG r0, 0xEB235675; +CHECKREG r1, 0xD9B7AB3B; +CHECKREG r2, 0x13E46705; +CHECKREG r3, 0x000A3494; +CHECKREG r4, 0x90ABED09; +CHECKREG r5, 0x44E81527; +CHECKREG r6, 0x000C00ED; +CHECKREG r7, 0x3A37A057; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_s.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_s.s new file mode 100644 index 0000000..dae1552 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_pair_s.s @@ -0,0 +1,180 @@ +//Original:/testcases/core/c_dsp32mult_pair_s/c_dsp32mult_pair_s.dsp +// Spec Reference: dsp32mult pair s +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x93ba5127; +imm32 r2, 0xa3446725; +imm32 r3, 0x00050027; +imm32 r4, 0xb0ab6d29; +imm32 r5, 0x10ace72b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467029; +R1 = R0.L * R0.L, R0 = R0.L * R0.L (S2RND); +R3 = R0.L * R1.L, R2 = R0.L * R1.H (S2RND); +R5 = R1.L * R0.L, R4 = R1.H * R0.L (S2RND); +R7 = R1.L * R1.L, R6 = R1.H * R1.H (S2RND); +CHECKREG r0, 0x73F38564; +CHECKREG r1, 0x73F38564; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x7FFFFFFF; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x7FFFFFFF; +CHECKREG r6, 0x7FFFFFFF; +CHECKREG r7, 0x7FFFFFFF; + +imm32 r0, 0x5b33a635; +imm32 r1, 0x6fbe5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x9006d037; +imm32 r4, 0x80abcb39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c00dd; +imm32 r7, 0x12469003; +R1 = R2.L * R2.L, R0 = R2.L * R2.L (S2RND); +R3 = R2.L * R3.L, R2 = R2.L * R3.H (S2RND); +R5 = R3.L * R2.L, R4 = R3.H * R2.L (S2RND); +R7 = R3.L * R3.L, R6 = R3.H * R3.H (S2RND); +CHECKREG r0, 0x52CB43E4; +CHECKREG r1, 0x52CB43E4; +CHECKREG r2, 0x7F5C6CF8; +CHECKREG r3, 0x3659B18C; +CHECKREG r4, 0x5C88C8E0; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x2E26ABC4; +CHECKREG r7, 0x602B9240; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R1 = R4.L * R4.L, R0 = R4.L * R4.L (S2RND); +R3 = R4.L * R5.L, R2 = R4.L * R5.H (S2RND); +R5 = R5.L * R4.L, R4 = R5.H * R4.L (S2RND); +R7 = R5.L * R5.L, R6 = R5.H * R5.H (S2RND); +CHECKREG r0, 0x36536944; +CHECKREG r1, 0x36536944; +CHECKREG r2, 0xF0A3C830; +CHECKREG r3, 0x0F55C4CC; +CHECKREG r4, 0xF0A3C830; +CHECKREG r5, 0x0F55C4CC; +CHECKREG r6, 0x03AC48E4; +CHECKREG r7, 0x36C40A40; + +imm32 r0, 0xab235666; +imm32 r1, 0xeaba5166; +imm32 r2, 0x13d48766; +imm32 r3, 0xf00b0066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10ac5f6b; +imm32 r6, 0x800cb66d; +imm32 r7, 0x1246707f; +R1 = R6.L * R6.L, R0 = R6.L * R6.L (S2RND); +R3 = R6.L * R7.L, R2 = R6.L * R7.H (S2RND); +R5 = R7.L * R6.L, R4 = R7.H * R6.L (S2RND); +R7 = R7.L * R7.L, R6 = R7.H * R7.H (S2RND); +CHECKREG r0, 0x5494A9A4; +CHECKREG r1, 0x5494A9A4; +CHECKREG r2, 0xEAFE2F38; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0xEAFE2F38; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x0537AC90; +CHECKREG r7, 0x7FFFFFFF; + + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (S2RND); +R3 = R1.L * R0.H, R2 = R1.H * R0.L (S2RND); +R5 = R7.H * R4.L, R4 = R7.H * R4.L (S2RND); +R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (S2RND); +CHECKREG r0, 0x000217F0; +CHECKREG r1, 0x0005A246; +CHECKREG r2, 0x0001DEC0; +CHECKREG r3, 0xFFFD1230; +CHECKREG r4, 0xF172C9D8; +CHECKREG r5, 0xF172C9D8; +CHECKREG r6, 0xFFFD0B28; +CHECKREG r7, 0xFFFA7FF0; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946905; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d9d; +imm32 r7, 0x12467009; +R3 = R6.L * R5.L, R2 = R6.L * R5.H (S2RND); +R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (S2RND); +R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (S2RND); +R7 = R2.H * R7.L, R6 = R2.H * R7.L (S2RND); +CHECKREG r0, 0xF9577348; +CHECKREG r1, 0x31F9EE68; +CHECKREG r2, 0x038BD5F0; +CHECKREG r3, 0xFB4A293C; +CHECKREG r4, 0xB2B9DB04; +CHECKREG r5, 0xEA6A5350; +CHECKREG r6, 0x0633BF8C; +CHECKREG r7, 0x0633BF8C; + +imm32 r0, 0x8b235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0x00080007; +imm32 r4, 0x90ab8d09; +imm32 r5, 0x10ace8db; +imm32 r6, 0x000c008d; +imm32 r7, 0x12467008; +R3 = R6.H * R5.L, R2 = R6.L * R5.H (S2RND); +R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (S2RND); +R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (S2RND); +R1 = R2.H * R7.L, R0 = R2.L * R7.H (S2RND); +CHECKREG r0, 0x510340C0; +CHECKREG r1, 0xFFDAAA00; +CHECKREG r2, 0x0024BAF0; +CHECKREG r3, 0xFFFBA910; +CHECKREG r4, 0x4B155680; +CHECKREG r5, 0x6B2FA2E0; +CHECKREG r6, 0x0030A1D0; +CHECKREG r7, 0xB4EDBDA0; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R1.H * R4.L, R0 = R1.H * R4.L (S2RND); +R3 = R2.L * R5.L, R2 = R2.L * R5.H (S2RND); +R5 = R3.H * R6.L, R4 = R3.L * R6.L (S2RND); +R7 = R4.L * R0.H, R6 = R4.H * R0.L (S2RND); +CHECKREG r0, 0x0E99DA28; +CHECKREG r1, 0x0E99DA28; +CHECKREG r2, 0x1AD61D70; +CHECKREG r3, 0xE4671D1C; +CHECKREG r4, 0x006BCBB0; +CHECKREG r5, 0xFF99CD6C; +CHECKREG r6, 0xFFC0BAE0; +CHECKREG r7, 0xF41170C0; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32mult_pair_u.s b/sim/testsuite/sim/bfin/c_dsp32mult_pair_u.s new file mode 100644 index 0000000..0c570b2 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32mult_pair_u.s @@ -0,0 +1,179 @@ +//Original:/testcases/core/c_dsp32mult_pair_u/c_dsp32mult_pair_u.dsp +// Spec Reference: dsp32mult pair u +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x8b235625; +imm32 r1, 0x93ba5127; +imm32 r2, 0xa3446725; +imm32 r3, 0x00050027; +imm32 r4, 0xb0ab6d29; +imm32 r5, 0x10ace72b; +imm32 r6, 0xc00c008d; +imm32 r7, 0xd2467029; +R1 = R0.L * R0.L, R0 = R0.L * R0.L (FU); +R3 = R0.L * R1.L, R2 = R0.L * R1.H (FU); +R5 = R1.L * R0.L, R4 = R1.H * R0.L (FU); +R7 = R1.L * R1.L, R6 = R1.H * R1.H (FU); +CHECKREG r0, 0x1CFCE159; +CHECKREG r1, 0x1CFCE159; +CHECKREG r2, 0x19838F9C; +CHECKREG r3, 0xC65D90F1; +CHECKREG r4, 0x19838F9C; +CHECKREG r5, 0xC65D90F1; +CHECKREG r6, 0x03481810; +CHECKREG r7, 0xC65D90F1; + +imm32 r0, 0x5b33a635; +imm32 r1, 0x6fbe5137; +imm32 r2, 0x1324b735; +imm32 r3, 0x9006d037; +imm32 r4, 0x80abcb39; +imm32 r5, 0xb0acef3b; +imm32 r6, 0xa00c00dd; +imm32 r7, 0x12469003; +R1 = R2.L * R2.L, R0 = R2.L * R2.L (FU); +R3 = R2.L * R3.L, R2 = R2.L * R3.H (FU); +R5 = R3.L * R2.L, R4 = R3.H * R2.L (FU); +R7 = R3.L * R3.L, R6 = R3.H * R3.H (FU); +CHECKREG r0, 0x831CD0F9; +CHECKREG r1, 0x831CD0F9; +CHECKREG r2, 0x67121B3E; +CHECKREG r3, 0x95026C63; +CHECKREG r4, 0x0FDB4C7C; +CHECKREG r5, 0x0B88B0FA; +CHECKREG r6, 0x56BB5404; +CHECKREG r7, 0x2DE3AE49; + +imm32 r0, 0x1b235655; +imm32 r1, 0xc4ba5157; +imm32 r2, 0x63246755; +imm32 r3, 0x00060055; +imm32 r4, 0x90abc509; +imm32 r5, 0x10acef5b; +imm32 r6, 0xb00c005d; +imm32 r7, 0x1246705f; +R1 = R4.L * R4.L, R0 = R4.L * R4.L (FU); +R3 = R4.L * R5.L, R2 = R4.L * R5.H (FU); +R5 = R5.L * R4.L, R4 = R5.H * R4.L (FU); +R7 = R5.L * R5.L, R6 = R5.H * R5.H (FU); +CHECKREG r0, 0x97A6DA51; +CHECKREG r1, 0x97A6DA51; +CHECKREG r2, 0x0CD4F20C; +CHECKREG r3, 0xB8397133; +CHECKREG r4, 0x0CD4F20C; +CHECKREG r5, 0xB8397133; +CHECKREG r6, 0x8491FCB1; +CHECKREG r7, 0x320E1029; + +imm32 r0, 0xab235666; +imm32 r1, 0xeaba5166; +imm32 r2, 0x13d48766; +imm32 r3, 0xf00b0066; +imm32 r4, 0x90ab9d69; +imm32 r5, 0x10ac5f6b; +imm32 r6, 0x800cb66d; +imm32 r7, 0x1246707f; +R1 = R6.L * R6.L, R0 = R6.L * R6.L (FU); +R3 = R6.L * R7.L, R2 = R6.L * R7.H (FU); +R5 = R7.L * R6.L, R4 = R7.H * R6.L (FU); +R7 = R7.L * R7.L, R6 = R7.H * R7.H (FU); +CHECKREG r0, 0x81FF2A69; +CHECKREG r1, 0x81FF2A69; +CHECKREG r2, 0x0D058BCE; +CHECKREG r3, 0x502A3013; +CHECKREG r4, 0x0D058BCE; +CHECKREG r5, 0x502A3013; +CHECKREG r6, 0x014DEB24; +CHECKREG r7, 0x316F5F01; + +// mix order +imm32 r0, 0xab23a675; +imm32 r1, 0xcfba5127; +imm32 r2, 0x13246705; +imm32 r3, 0x00060007; +imm32 r4, 0x90abcd09; +imm32 r5, 0x10acdfdb; +imm32 r6, 0x000c000d; +imm32 r7, 0x1246f00f; +R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (FU); +R3 = R1.L * R0.H, R2 = R1.H * R0.L (FU); +R5 = R7.H * R4.L, R4 = R7.H * R4.L (FU); +R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (FU); +CHECKREG r0, 0x000085FC; +CHECKREG r1, 0x0002D123; +CHECKREG r2, 0x00010BF8; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0EA2B276; +CHECKREG r5, 0x0EA2B276; +CHECKREG r6, 0x0000BE3A; +CHECKREG r7, 0xFFFC0FFE; + +imm32 r0, 0x9b235a75; +imm32 r1, 0xc9ba5127; +imm32 r2, 0x13946905; +imm32 r3, 0x00090007; +imm32 r4, 0x90ab9d09; +imm32 r5, 0x10ace9db; +imm32 r6, 0x000c0d9d; +imm32 r7, 0x12467009; +R3 = R6.L * R5.L, R2 = R6.L * R5.H (FU); +R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (FU); +R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (FU); +R7 = R2.H * R7.L, R6 = R2.H * R7.L (FU); +CHECKREG r0, 0x0464B4BB; +CHECKREG r1, 0xB8ADBDCD; +CHECKREG r2, 0x00E2F57C; +CHECKREG r3, 0x0C6F8A4F; +CHECKREG r4, 0x71489715; +CHECKREG r5, 0xD7646535; +CHECKREG r6, 0x0062E7F2; +CHECKREG r7, 0x0062E7F2; + +imm32 r0, 0x8b235675; +imm32 r1, 0xc8ba5127; +imm32 r2, 0x13846705; +imm32 r3, 0x00080007; +imm32 r4, 0x90ab8d09; +imm32 r5, 0x10ace8db; +imm32 r6, 0x000c008d; +imm32 r7, 0x12467008; +R3 = R6.H * R5.L, R2 = R6.L * R5.H (FU); +R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (FU); +R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (FU); +R1 = R2.H * R7.L, R0 = R2.L * R7.H (FU); +CHECKREG r0, 0x04A2FAE8; +CHECKREG r1, 0x00043554; +CHECKREG r2, 0x00092EBC; +CHECKREG r3, 0x000AEA44; +CHECKREG r4, 0xB7AF5568; +CHECKREG r5, 0x4A43345C; +CHECKREG r6, 0x00030A1D; +CHECKREG r7, 0x196677B4; + +imm32 r0, 0xeb235675; +imm32 r1, 0xceba5127; +imm32 r2, 0x13e46705; +imm32 r3, 0x000e0007; +imm32 r4, 0x90abed09; +imm32 r5, 0x10aceedb; +imm32 r6, 0x000c00ed; +imm32 r7, 0x1246700e; +R1 = R1.H * R4.L, R0 = R1.H * R4.L (FU); +R3 = R2.L * R5.L, R2 = R2.L * R5.H (FU); +R5 = R3.H * R6.L, R4 = R3.L * R6.L (FU); +R7 = R4.L * R0.H, R6 = R4.H * R0.L (FU); +CHECKREG r0, 0xBF69768A; +CHECKREG r1, 0xBF69768A; +CHECKREG r2, 0x06B5875C; +CHECKREG r3, 0x601EC747; +CHECKREG r4, 0x00B87CBB; +CHECKREG r5, 0x0058FBC6; +CHECKREG r6, 0x00553330; +CHECKREG r7, 0x5D42ADB3; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_a0alr.s b/sim/testsuite/sim/bfin/c_dsp32shift_a0alr.s new file mode 100644 index 0000000..4b625aa --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_a0alr.s @@ -0,0 +1,211 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_a0alr/c_dsp32shift_a0alr.dsp +// Spec Reference: dsp32shift a0 ashift, lshift, rot +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x11140000; + imm32 r1, 0x012C003E; + imm32 r2, 0x81359E24; + imm32 r3, 0x81459E24; + imm32 r4, 0xD159E268; + imm32 r5, 0x51626AF2; + imm32 r6, 0x9176AF36; + imm32 r7, 0xE18BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = ASHIFT A0 BY R0.L; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x012C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0x0258007C; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = ASHIFT A0 BY R2.L; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x003E0000; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = ASHIFT A0 BY R3.L; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x00000000; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = ASHIFT A0 BY R4.L; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x00000000; + + R5.L = -16; + A0 = 0; + A0.L = R6.L; + A0.H = R6.H; + A0 = ASHIFT A0 BY R5.L; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x00000000; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = ASHIFT A0 BY R6.L; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x00000000; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + A0 = ASHIFT A0 BY R7.L; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x00000000; + + imm32 r0, 0x12340000; + imm32 r1, 0x028C003E; + imm32 r2, 0x82159E24; + imm32 r3, 0x82159E24; + imm32 r4, 0xD259E268; + imm32 r5, 0x52E26AF2; + imm32 r6, 0x9226AF36; + imm32 r7, 0xE26BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = LSHIFT A0 BY R0.L; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x028C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0x0518007C; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = LSHIFT A0 BY R2.L; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x003E0000; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = LSHIFT A0 BY R3.L; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x00000000; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = LSHIFT A0 BY R4.L; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x00000000; + + R5.L = -16; + A0 = 0; + A0.L = R6.L; + A0.H = R6.H; + A0 = LSHIFT A0 BY R5.L; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x00000000; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = LSHIFT A0 BY R6.L; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x00000000; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + A0 = LSHIFT A0 BY R7.L; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x00000000; + + imm32 r0, 0x13340000; + imm32 r1, 0x038C003E; + imm32 r2, 0x83159E24; + imm32 r3, 0x83159E24; + imm32 r4, 0xD359E268; + imm32 r5, 0x53E26AF2; + imm32 r6, 0x9326AF36; + imm32 r7, 0xE36BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = ROT A0 BY R0.L; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x038C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = ROT A0 BY R1.L; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0x0718007C; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = ROT A0 BY R2.L; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x003E0001; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = ROT A0 BY R3.L; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0xE3000F80; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = ROT A0 BY R4.L; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x718007C0; + + R5.L = -16; + A0.L = R6.L; + A0.H = R6.H; + A0 = ROT A0 BY R5.L; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x80007180; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = ROT A0 BY R6.L; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x01C6001F; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + A0 = ROT A0 BY R7.L; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x8C003E00; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_af.s b/sim/testsuite/sim/bfin/c_dsp32shift_af.s new file mode 100644 index 0000000..c93587b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_af.s @@ -0,0 +1,186 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_af/c_dsp32shift_af.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + +// ashift : mix data, count (+)= (half reg) +// d_reg = ashift (d BY d_lo) +// Rx by RLx + imm32 r0, 0x01230001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x856789ab; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R4 = ASHIFT R0 BY R0.L; + R5 = ASHIFT R1 BY R0.L; + R6 = ASHIFT R2 BY R0.L; + R7 = ASHIFT R3 BY R0.L; + CHECKREG r4, 0x02460002; + CHECKREG r5, 0x2468ACF0; + CHECKREG r6, 0x468ACF12; + CHECKREG r7, 0x68ACF134; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0xa6789abc; + imm32 r6, 0xb789abcd; + imm32 r7, 0xc89abcde; + R1.L = 5; + R5 = ASHIFT R0 BY R1.L; + R6 = ASHIFT R1 BY R1.L; + R7 = ASHIFT R2 BY R1.L; + R4 = ASHIFT R3 BY R1.L; + CHECKREG r4, 0x8ACF1340; + CHECKREG r5, 0x24600040; + CHECKREG r6, 0x468000A0; + CHECKREG r7, 0x68ACF120; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2 = 15; + R6 = ASHIFT R0 BY R2.L; + R7 = ASHIFT R1 BY R2.L; + R4 = ASHIFT R2 BY R2.L; + R5 = ASHIFT R3 BY R2.L; + CHECKREG r4, 0x00078000; + CHECKREG r5, 0x3C4D0000; + CHECKREG r6, 0x80010000; + CHECKREG r7, 0x2B3C0000; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0xa56789ab; + imm32 r5, 0xb6789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0xd89abcde; + R3.L = 16; + R7 = ASHIFT R0 BY R3.L; + R6 = ASHIFT R1 BY R3.L; + R5 = ASHIFT R2 BY R3.L; + R4 = ASHIFT R3 BY R3.L; + CHECKREG r4, 0x00100000; + CHECKREG r5, 0x67890000; + CHECKREG r6, 0x56780000; + CHECKREG r7, 0x00020000; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -1; + R7 = ASHIFT R0 BY R4.L; + R0 = ASHIFT R1 BY R4.L; + R1 = ASHIFT R2 BY R4.L; + R2 = ASHIFT R3 BY R4.L; + R3 = ASHIFT R4 BY R4.L; + R4 = ASHIFT R5 BY R4.L; + R5 = ASHIFT R6 BY R4.L; + R6 = ASHIFT R7 BY R4.L; + CHECKREG r0, 0x091A2B3C; + CHECKREG r1, 0x11A2B3C4; + CHECKREG r2, 0x1A2B3C4D; + CHECKREG r3, 0x22B3FFFF; + CHECKREG r4, 0x2B3C4D5E; + CHECKREG r5, 0x40000000; + CHECKREG r6, 0x40000000; + CHECKREG r7, 0x00918001; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R5.L = -6; + R6 = ASHIFT R0 BY R5.L; + R7 = ASHIFT R1 BY R5.L; + R0 = ASHIFT R2 BY R5.L; + R1 = ASHIFT R3 BY R5.L; + R2 = ASHIFT R4 BY R5.L; + R3 = ASHIFT R5 BY R5.L; + R4 = ASHIFT R6 BY R5.L; + R5 = ASHIFT R7 BY R5.L; + CHECKREG r0, 0xFE4D159E; + CHECKREG r1, 0xFE9159E2; + CHECKREG r2, 0xFED59E26; + CHECKREG r3, 0xFF19E3FF; + CHECKREG r4, 0x00001230; + CHECKREG r5, 0xFFF82345; + CHECKREG r6, 0x00048C00; + CHECKREG r7, 0xFE08D159; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -15; + R5 = ASHIFT R0 BY R6.L; + R0 = ASHIFT R1 BY R6.L; + R7 = ASHIFT R2 BY R6.L; + R0 = ASHIFT R3 BY R6.L; + R1 = ASHIFT R4 BY R6.L; + R2 = ASHIFT R5 BY R6.L; + R3 = ASHIFT R6 BY R6.L; + R6 = ASHIFT R7 BY R6.L; + CHECKREG r0, 0x000068AC; + CHECKREG r1, 0x00008ACF; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x0000CF13; + CHECKREG r4, 0x456789AB; + CHECKREG r5, 0x00000246; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x0000468A; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R7.L = -14; + R0 = ASHIFT R0 BY R7.L; + R1 = ASHIFT R1 BY R7.L; + R2 = ASHIFT R2 BY R7.L; + R3 = ASHIFT R3 BY R7.L; + R4 = ASHIFT R4 BY R7.L; + R5 = ASHIFT R5 BY R7.L; + R6 = ASHIFT R6 BY R7.L; + R7 = ASHIFT R7 BY R7.L; + CHECKREG r0, 0x0000048C; + CHECKREG r1, 0xFFFE08D1; + CHECKREG r2, 0xFFFE4D15; + CHECKREG r3, 0xFFFE9159; + CHECKREG r4, 0xFFFED59E; + CHECKREG r5, 0xFFFF19E2; + CHECKREG r6, 0xFFFF5E26; + CHECKREG r7, 0xFFFFA26B; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_af_s.s b/sim/testsuite/sim/bfin/c_dsp32shift_af_s.s new file mode 100644 index 0000000..e94f7cb --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_af_s.s @@ -0,0 +1,186 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_af_s/c_dsp32shift_af_s.dsp +// Spec Reference: dsp32shift ashift s +# mach: bfin + +.include "testutils.inc" + start + +// ashift : mix data, count (+)= (half reg) +// d_reg = ashift (d BY d_lo) +// Rx by RLx + imm32 r0, 0x01230001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x856789ab; + imm32 r5, 0x96789abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb89abcde; + R4 = ASHIFT R0 BY R0.L (S); + R5 = ASHIFT R1 BY R0.L (S); + R6 = ASHIFT R2 BY R0.L (S); + R7 = ASHIFT R3 BY R0.L (S); + CHECKREG r4, 0x02460002; + CHECKREG r5, 0x2468ACF0; + CHECKREG r6, 0x468ACF12; + CHECKREG r7, 0x68ACF134; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0xa6789abc; + imm32 r6, 0xb789abcd; + imm32 r7, 0xc89abcde; + R1.L = 5; + R5 = ASHIFT R0 BY R1.L (S); + R6 = ASHIFT R1 BY R1.L (S); + R7 = ASHIFT R2 BY R1.L (S); + R4 = ASHIFT R3 BY R1.L (S); + CHECKREG r4, 0x7FFFFFFF; + CHECKREG r5, 0x24600040; + CHECKREG r6, 0x7FFFFFFF; + CHECKREG r7, 0x7FFFFFFF; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2 = 14; + R6 = ASHIFT R0 BY R2.L (S); + R7 = ASHIFT R1 BY R2.L (S); + R4 = ASHIFT R2 BY R2.L (S); + R5 = ASHIFT R3 BY R2.L (S); + CHECKREG r4, 0x00038000; + CHECKREG r5, 0x7FFFFFFF; + CHECKREG r6, 0x7FFFFFFF; + CHECKREG r7, 0x7FFFFFFF; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0xa56789ab; + imm32 r5, 0xb6789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0xd89abcde; + R3.L = 15; + R7 = ASHIFT R0 BY R3.L (S); + R6 = ASHIFT R1 BY R3.L (S); + R5 = ASHIFT R2 BY R3.L (S); + R4 = ASHIFT R3 BY R3.L (S); + CHECKREG r4, 0x7FFFFFFF; + CHECKREG r5, 0x7FFFFFFF; + CHECKREG r6, 0x7FFFFFFF; + CHECKREG r7, 0x7FFFFFFF; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -1; + R7 = ASHIFT R0 BY R4.L; + R0 = ASHIFT R1 BY R4.L; + R1 = ASHIFT R2 BY R4.L; + R2 = ASHIFT R3 BY R4.L; + R3 = ASHIFT R4 BY R4.L; + R4 = ASHIFT R5 BY R4.L; + R5 = ASHIFT R6 BY R4.L; + R6 = ASHIFT R7 BY R4.L; + CHECKREG r0, 0x091A2B3C; + CHECKREG r1, 0x11A2B3C4; + CHECKREG r2, 0x1A2B3C4D; + CHECKREG r3, 0x22B3FFFF; + CHECKREG r4, 0x2B3C4D5E; + CHECKREG r5, 0x40000000; + CHECKREG r6, 0x40000000; + CHECKREG r7, 0x00918001; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R5.L = -6; + R6 = ASHIFT R0 BY R5.L (S); + R7 = ASHIFT R1 BY R5.L (S); + R0 = ASHIFT R2 BY R5.L (S); + R1 = ASHIFT R3 BY R5.L (S); + R2 = ASHIFT R4 BY R5.L (S); + R3 = ASHIFT R5 BY R5.L (S); + R4 = ASHIFT R6 BY R5.L (S); + R5 = ASHIFT R7 BY R5.L (S); + CHECKREG r0, 0xFE4D159E; + CHECKREG r1, 0xFE9159E2; + CHECKREG r2, 0xFED59E26; + CHECKREG r3, 0xFF19E3FF; + CHECKREG r4, 0x00001230; + CHECKREG r5, 0xFFF82345; + CHECKREG r6, 0x00048C00; + CHECKREG r7, 0xFE08D159; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -15; + R5 = ASHIFT R0 BY R6.L (S); + R0 = ASHIFT R1 BY R6.L (S); + R7 = ASHIFT R2 BY R6.L (S); + R0 = ASHIFT R3 BY R6.L (S); + R1 = ASHIFT R4 BY R6.L (S); + R2 = ASHIFT R5 BY R6.L (S); + R3 = ASHIFT R6 BY R6.L (S); + R6 = ASHIFT R7 BY R6.L (S); + CHECKREG r0, 0x000068AC; + CHECKREG r1, 0x00008ACF; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x0000CF13; + CHECKREG r4, 0x456789AB; + CHECKREG r5, 0x00000246; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x0000468A; + + imm32 r0, 0x01230002; + imm32 r1, 0x82345678; + imm32 r2, 0x93456789; + imm32 r3, 0xa456789a; + imm32 r4, 0xb56789ab; + imm32 r5, 0xc6789abc; + imm32 r6, 0xd789abcd; + imm32 r7, 0xe89abcde; + R7.L = -14; + R0 = ASHIFT R0 BY R7.L (S); + R1 = ASHIFT R1 BY R7.L (S); + R2 = ASHIFT R2 BY R7.L (S); + R3 = ASHIFT R3 BY R7.L (S); + R4 = ASHIFT R4 BY R7.L (S); + R5 = ASHIFT R5 BY R7.L (S); + R6 = ASHIFT R6 BY R7.L (S); + R7 = ASHIFT R7 BY R7.L (S); + CHECKREG r0, 0x0000048C; + CHECKREG r1, 0xFFFE08D1; + CHECKREG r2, 0xFFFE4D15; + CHECKREG r3, 0xFFFE9159; + CHECKREG r4, 0xFFFED59E; + CHECKREG r5, 0xFFFF19E2; + CHECKREG r6, 0xFFFF5E26; + CHECKREG r7, 0xFFFFA26B; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln.s new file mode 100644 index 0000000..9a37aef --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_ln/c_dsp32shift_ahalf_ln.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + + +// Ashift : neg data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R0.L = ASHIFT R0.L BY R0.L; +R1.L = ASHIFT R1.L BY R0.L; +R2.L = ASHIFT R2.L BY R0.L; +R3.L = ASHIFT R3.L BY R0.L; +R4.L = ASHIFT R4.L BY R0.L; +R5.L = ASHIFT R5.L BY R0.L; +R6.L = ASHIFT R6.L BY R0.L; +R7.L = ASHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c001; +CHECKREG r2, 0x0000c002; +CHECKREG r3, 0x0000c003; +CHECKREG r4, 0x0000c004; +CHECKREG r5, 0x0000c005; +CHECKREG r6, 0x0000c006; +CHECKREG r7, 0x0000c007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R0.L = ASHIFT R0.L BY R1.L; +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L; +R3.L = ASHIFT R3.L BY R1.L; +R4.L = ASHIFT R4.L BY R1.L; +R5.L = ASHIFT R5.L BY R1.L; +R6.L = ASHIFT R6.L BY R1.L; +R7.L = ASHIFT R7.L BY R1.L; +//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */ +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000a004; +CHECKREG r3, 0x0000c006; +CHECKREG r4, 0x0000e008; +CHECKREG r5, 0x0000800a; +CHECKREG r6, 0x0000a00c; +CHECKREG r7, 0x0000c00e; + + +imm32 r0, 0x0000c001; +imm32 r1, 0x0000d001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = ASHIFT R0.L BY R2.L; +R1.L = ASHIFT R1.L BY R2.L; +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L; +R4.L = ASHIFT R4.L BY R2.L; +R5.L = ASHIFT R5.L BY R2.L; +R6.L = ASHIFT R6.L BY R2.L; +R7.L = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00009001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000b002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000f007; +R0.L = ASHIFT R0.L BY R3.L; +R1.L = ASHIFT R1.L BY R3.L; +R2.L = ASHIFT R2.L BY R3.L; +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L; +R5.L = ASHIFT R5.L BY R3.L; +R6.L = ASHIFT R6.L BY R3.L; +R7.L = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L; +R1.L = ASHIFT R1.H BY R0.L; +R2.L = ASHIFT R2.H BY R0.L; +R3.L = ASHIFT R3.H BY R0.L; +R4.L = ASHIFT R4.H BY R0.L; +R5.L = ASHIFT R5.H BY R0.L; +R6.L = ASHIFT R6.H BY R0.L; +R7.L = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R0.L = ASHIFT R0.H BY R1.L; +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L; +R3.L = ASHIFT R3.H BY R1.L; +R4.L = ASHIFT R4.H BY R1.L; +R5.L = ASHIFT R5.H BY R1.L; +R6.L = ASHIFT R6.H BY R1.L; +R7.L = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x90012002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x90022004; +CHECKREG r3, 0x90032006; +CHECKREG r4, 0x90042008; +CHECKREG r5, 0x9005200a; +CHECKREG r6, 0x9006200c; +CHECKREG r7, 0x9007200e; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0xa0018000; +CHECKREG r1, 0xa0018000; +CHECKREG r2, 0xa002000f; +CHECKREG r3, 0xa0038000; +CHECKREG r4, 0xa0040000; +CHECKREG r5, 0xa0058000; +CHECKREG r6, 0xa0060000; +CHECKREG r7, 0xa0078000; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc0070007; +R0.L = ASHIFT R0.H BY R3.L; +R1.L = ASHIFT R1.H BY R3.L; +R2.L = ASHIFT R2.H BY R3.L; +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L; +R5.L = ASHIFT R5.H BY R3.L; +R6.L = ASHIFT R6.H BY R3.L; +R7.L = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0xc0010000; +CHECKREG r1, 0xc0010000; +CHECKREG r2, 0xc0020000; +CHECKREG r3, 0xc0030010; +CHECKREG r4, 0xc0040000; +CHECKREG r5, 0xc0050000; +CHECKREG r6, 0xc0060000; +CHECKREG r7, 0xc0070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R0.L; +R1.H = ASHIFT R1.L BY R0.L; +R2.H = ASHIFT R2.L BY R0.L; +R3.H = ASHIFT R3.L BY R0.L; +R4.H = ASHIFT R4.L BY R0.L; +R5.H = ASHIFT R5.L BY R0.L; +R6.H = ASHIFT R6.L BY R0.L; +R7.H = ASHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R0.H = ASHIFT R0.L BY R1.L; +R1.H = ASHIFT R1.L BY R1.L; +R2.H = ASHIFT R2.L BY R1.L; +R3.H = ASHIFT R3.L BY R1.L; +R4.H = ASHIFT R4.L BY R1.L; +R5.H = ASHIFT R5.L BY R1.L; +R6.H = ASHIFT R6.L BY R1.L; +R7.H = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0xa002d001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0xa004d002; +CHECKREG r3, 0xa006d003; +CHECKREG r4, 0xa008d004; +CHECKREG r5, 0xa00ad005; +CHECKREG r6, 0xa00cd006; +CHECKREG r7, 0xa00ed007; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = ASHIFT R0.L BY R2.L; +R1.H = ASHIFT R1.L BY R2.L; +//rh2 = ashift (rl2 by rl2); +R3.H = ASHIFT R3.L BY R2.L; +R4.H = ASHIFT R4.L BY R2.L; +R5.H = ASHIFT R5.L BY R2.L; +R6.H = ASHIFT R6.L BY R2.L; +R7.H = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x8000e001; +CHECKREG r1, 0x8000e001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x8000e003; +CHECKREG r4, 0x0000e004; +CHECKREG r5, 0x8000e005; +CHECKREG r6, 0x0000e006; +CHECKREG r7, 0x8000e007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.H = ASHIFT R0.L BY R3.L; +R1.H = ASHIFT R1.L BY R3.L; +R2.H = ASHIFT R2.L BY R3.L; +R3.H = ASHIFT R3.L BY R3.L; +R4.H = ASHIFT R4.L BY R3.L; +R5.H = ASHIFT R5.L BY R3.L; +R6.H = ASHIFT R6.L BY R3.L; +R7.H = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x0000f001; +CHECKREG r1, 0x0000f001; +CHECKREG r2, 0x0000f002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000f004; +CHECKREG r5, 0x0000f005; +CHECKREG r6, 0x0000f006; +CHECKREG r7, 0x0000f007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R0.L; +R1.H = ASHIFT R1.H BY R0.L; +R2.H = ASHIFT R2.H BY R0.L; +R3.H = ASHIFT R3.H BY R0.L; +R4.H = ASHIFT R4.H BY R0.L; +R5.H = ASHIFT R5.H BY R0.L; +R6.H = ASHIFT R6.H BY R0.L; +R7.H = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.H = ASHIFT R0.H BY R1.L; +R1.H = ASHIFT R1.H BY R1.L; +R2.H = ASHIFT R2.H BY R1.L; +R3.H = ASHIFT R3.H BY R1.L; +R4.H = ASHIFT R4.H BY R1.L; +R5.H = ASHIFT R5.H BY R1.L; +R6.H = ASHIFT R6.H BY R1.L; +R7.H = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x40020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x40040000; +CHECKREG r3, 0x40060000; +CHECKREG r4, 0x40080000; +CHECKREG r5, 0x400a0000; +CHECKREG r6, 0x400c0000; +CHECKREG r7, 0x400e0000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0xb0018000; +CHECKREG r1, 0xb0018000; +CHECKREG r2, 0xb002000f; +CHECKREG r3, 0xb0038000; +CHECKREG r4, 0xb0040000; +CHECKREG r5, 0xb0058000; +CHECKREG r6, 0xb0060000; +CHECKREG r7, 0xb0078000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R0.H = ASHIFT R0.H BY R3.L; +R1.H = ASHIFT R1.H BY R3.L; +R2.H = ASHIFT R2.H BY R3.L; +R3.H = ASHIFT R3.H BY R3.L; +R4.H = ASHIFT R4.H BY R3.L; +R5.H = ASHIFT R5.H BY R3.L; +R6.H = ASHIFT R6.H BY R3.L; +R7.H = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln_s.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln_s.s new file mode 100644 index 0000000..dd6b8d4 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_ln_s.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_ln_s/c_dsp32shift_ahalf_ln_s.dsp +// Spec Reference: +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : neg data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R0.L = ASHIFT R0.L BY R0.L (S); +R1.L = ASHIFT R1.L BY R0.L (S); +R2.L = ASHIFT R2.L BY R0.L (S); +R3.L = ASHIFT R3.L BY R0.L (S); +R4.L = ASHIFT R4.L BY R0.L (S); +R5.L = ASHIFT R5.L BY R0.L (S); +R6.L = ASHIFT R6.L BY R0.L (S); +R7.L = ASHIFT R7.L BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c001; +CHECKREG r2, 0x0000c002; +CHECKREG r3, 0x0000c003; +CHECKREG r4, 0x0000c004; +CHECKREG r5, 0x0000c005; +CHECKREG r6, 0x0000c006; +CHECKREG r7, 0x0000c007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R0.L = ASHIFT R0.L BY R1.L (S); +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L (S); +R3.L = ASHIFT R3.L BY R1.L (S); +R4.L = ASHIFT R4.L BY R1.L (S); +R5.L = ASHIFT R5.L BY R1.L (S); +R6.L = ASHIFT R6.L BY R1.L (S); +R7.L = ASHIFT R7.L BY R1.L (S); +//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */ +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000a004; +CHECKREG r3, 0x0000c006; +CHECKREG r4, 0x0000e008; +CHECKREG r5, 0x0000800a; +CHECKREG r6, 0x0000a00c; +CHECKREG r7, 0x0000c00e; + + +imm32 r0, 0x0000c001; +imm32 r1, 0x0000d001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = ASHIFT R0.L BY R2.L (S); +R1.L = ASHIFT R1.L BY R2.L (S); +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L (S); +R4.L = ASHIFT R4.L BY R2.L (S); +R5.L = ASHIFT R5.L BY R2.L (S); +R6.L = ASHIFT R6.L BY R2.L (S); +R7.L = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00008000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00008000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00009001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000b002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000f007; +R0.L = ASHIFT R0.L BY R3.L (S); +R1.L = ASHIFT R1.L BY R3.L (S); +R2.L = ASHIFT R2.L BY R3.L (S); +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L (S); +R5.L = ASHIFT R5.L BY R3.L (S); +R6.L = ASHIFT R6.L BY R3.L (S); +R7.L = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x00008000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00008000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00008000; +CHECKREG r7, 0x00008000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L (S); +R1.L = ASHIFT R1.H BY R0.L (S); +R2.L = ASHIFT R2.H BY R0.L (S); +R3.L = ASHIFT R3.H BY R0.L (S); +R4.L = ASHIFT R4.H BY R0.L (S); +R5.L = ASHIFT R5.H BY R0.L (S); +R6.L = ASHIFT R6.H BY R0.L (S); +R7.L = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R0.L = ASHIFT R0.H BY R1.L (S); +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L (S); +R3.L = ASHIFT R3.H BY R1.L (S); +R4.L = ASHIFT R4.H BY R1.L (S); +R5.L = ASHIFT R5.H BY R1.L (S); +R6.L = ASHIFT R6.H BY R1.L (S); +R7.L = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x90018000; +//CHECKREG r1, 0x00018000; +CHECKREG r2, 0x90028000; +CHECKREG r3, 0x90038000; +CHECKREG r4, 0x90048000; +CHECKREG r5, 0x90058000; +CHECKREG r6, 0x90068000; +CHECKREG r7, 0x90078000; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0xa0018000; +CHECKREG r1, 0xa0018000; +//CHECKREG r2, 0xa002000f; +CHECKREG r3, 0xa0038000; +CHECKREG r4, 0xa0048000; +CHECKREG r5, 0xa0058000; +CHECKREG r6, 0xa0068000; +CHECKREG r7, 0xa0078000; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc0070007; +R0.L = ASHIFT R0.H BY R3.L (S); +R1.L = ASHIFT R1.H BY R3.L (S); +R2.L = ASHIFT R2.H BY R3.L (S); +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L (S); +R5.L = ASHIFT R5.H BY R3.L (S); +R6.L = ASHIFT R6.H BY R3.L (S); +R7.L = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0xc0018000; +CHECKREG r1, 0xc0018000; +CHECKREG r2, 0xc0028000; +CHECKREG r3, 0xc0030010; +CHECKREG r4, 0xc0048000; +CHECKREG r5, 0xc0058000; +CHECKREG r6, 0xc0068000; +CHECKREG r7, 0xc0078000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R0.L (S); +R1.H = ASHIFT R1.L BY R0.L (S); +R2.H = ASHIFT R2.L BY R0.L (S); +R3.H = ASHIFT R3.L BY R0.L (S); +R4.H = ASHIFT R4.L BY R0.L (S); +R5.H = ASHIFT R5.L BY R0.L (S); +R6.H = ASHIFT R6.L BY R0.L (S); +R7.H = ASHIFT R7.L BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R0.H = ASHIFT R0.L BY R1.L (S); +R1.H = ASHIFT R1.L BY R1.L (S); +R2.H = ASHIFT R2.L BY R1.L (S); +R3.H = ASHIFT R3.L BY R1.L (S); +R4.H = ASHIFT R4.L BY R1.L (S); +R5.H = ASHIFT R5.L BY R1.L (S); +R6.H = ASHIFT R6.L BY R1.L (S); +R7.H = ASHIFT R7.L BY R1.L (S); +CHECKREG r0, 0xa002d001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0xa004d002; +CHECKREG r3, 0xa006d003; +CHECKREG r4, 0xa008d004; +CHECKREG r5, 0xa00ad005; +CHECKREG r6, 0xa00cd006; +CHECKREG r7, 0xa00ed007; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = ASHIFT R0.L BY R2.L (S); +R1.H = ASHIFT R1.L BY R2.L (S); +//rh2 = ashift (rl2 by rl2); +R3.H = ASHIFT R3.L BY R2.L (S); +R4.H = ASHIFT R4.L BY R2.L (S); +R5.H = ASHIFT R5.L BY R2.L (S); +R6.H = ASHIFT R6.L BY R2.L (S); +R7.H = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x8000e001; +CHECKREG r1, 0x8000e001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x8000e003; +CHECKREG r4, 0x8000e004; +CHECKREG r5, 0x8000e005; +CHECKREG r6, 0x8000e006; +CHECKREG r7, 0x8000e007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.H = ASHIFT R0.L BY R3.L (S); +R1.H = ASHIFT R1.L BY R3.L (S); +R2.H = ASHIFT R2.L BY R3.L (S); +//rh3 = ashift (rl3 by rl3) s; +R4.H = ASHIFT R4.L BY R3.L (S); +R5.H = ASHIFT R5.L BY R3.L (S); +R6.H = ASHIFT R6.L BY R3.L (S); +R7.H = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x8000f001; +CHECKREG r1, 0x8000f001; +CHECKREG r2, 0x8000f002; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x8000f004; +CHECKREG r5, 0x8000f005; +CHECKREG r6, 0x8000f006; +CHECKREG r7, 0x8000f007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R0.L (S); +R1.H = ASHIFT R1.H BY R0.L (S); +R2.H = ASHIFT R2.H BY R0.L (S); +R3.H = ASHIFT R3.H BY R0.L (S); +R4.H = ASHIFT R4.H BY R0.L (S); +R5.H = ASHIFT R5.H BY R0.L (S); +R6.H = ASHIFT R6.H BY R0.L (S); +R7.H = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.H = ASHIFT R0.H BY R1.L (S); +R1.H = ASHIFT R1.H BY R1.L (S); +R2.H = ASHIFT R2.H BY R1.L (S); +R3.H = ASHIFT R3.H BY R1.L (S); +R4.H = ASHIFT R4.H BY R1.L (S); +R5.H = ASHIFT R5.H BY R1.L (S); +R6.H = ASHIFT R6.H BY R1.L (S); +R7.H = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x80000000; +//CHECKREG r1, 0x80000000; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0xb0018000; +CHECKREG r1, 0xb0018000; +//CHECKREG r2, 0xb002000f; +CHECKREG r3, 0xb0038000; +CHECKREG r4, 0xb0048000; +CHECKREG r5, 0xb0058000; +CHECKREG r6, 0xb0068000; +CHECKREG r7, 0xb0078000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R0.H = ASHIFT R0.H BY R3.L (S); +R1.H = ASHIFT R1.H BY R3.L (S); +R2.H = ASHIFT R2.H BY R3.L (S); +R3.H = ASHIFT R3.H BY R3.L (S); +R4.H = ASHIFT R4.H BY R3.L (S); +R5.H = ASHIFT R5.H BY R3.L (S); +R6.H = ASHIFT R6.H BY R3.L (S); +R7.H = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x80000000; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x80000010; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp.s new file mode 100644 index 0000000..ecfa5f6 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_lp/c_dsp32shift_ahalf_lp.dsp +// Spec Reference: dsp32shift ashift half reg left positive +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R0.L; +R1.L = ASHIFT R1.L BY R0.L; +R2.L = ASHIFT R2.L BY R0.L; +R3.L = ASHIFT R3.L BY R0.L; +R4.L = ASHIFT R4.L BY R0.L; +R5.L = ASHIFT R5.L BY R0.L; +R6.L = ASHIFT R6.L BY R0.L; +R7.L = ASHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R1.L; +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L; +R3.L = ASHIFT R3.L BY R1.L; +R4.L = ASHIFT R4.L BY R1.L; +R5.L = ASHIFT R5.L BY R1.L; +R6.L = ASHIFT R6.L BY R1.L; +R7.L = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000006; +CHECKREG r4, 0x00000008; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x0000000c; +CHECKREG r7, 0x0000000e; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R2.L; +R1.L = ASHIFT R1.L BY R2.L; +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L; +R4.L = ASHIFT R4.L BY R2.L; +R5.L = ASHIFT R5.L BY R2.L; +R6.L = ASHIFT R6.L BY R2.L; +R7.L = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R3.L; +R1.L = ASHIFT R1.L BY R3.L; +R2.L = ASHIFT R2.L BY R3.L; +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L; +R5.L = ASHIFT R5.L BY R3.L; +R6.L = ASHIFT R6.L BY R3.L; +R7.L = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L; +R1.L = ASHIFT R1.H BY R0.L; +R2.L = ASHIFT R2.H BY R0.L; +R3.L = ASHIFT R3.H BY R0.L; +R4.L = ASHIFT R4.H BY R0.L; +R5.L = ASHIFT R5.H BY R0.L; +R6.L = ASHIFT R6.H BY R0.L; +R7.L = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R1.L; +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L; +R3.L = ASHIFT R3.H BY R1.L; +R4.L = ASHIFT R4.H BY R1.L; +R5.L = ASHIFT R5.H BY R1.L; +R6.L = ASHIFT R6.H BY R1.L; +R7.L = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x00010002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020004; +CHECKREG r3, 0x00030006; +CHECKREG r4, 0x00040008; +CHECKREG r5, 0x0005000a; +CHECKREG r6, 0x0006000c; +CHECKREG r7, 0x0007000e; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0x00018000; +CHECKREG r1, 0x00018000; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00038000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00058000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x00010001; +imm32 r1, 0x00010001; +imm32 r2, 0x00020002; +imm32 r3, 0x00030010; +imm32 r4, 0x00040004; +imm32 r5, 0x00050005; +imm32 r6, 0x00060006; +imm32 r7, 0x00070007; +R0.L = ASHIFT R0.H BY R3.L; +R1.L = ASHIFT R1.H BY R3.L; +R2.L = ASHIFT R2.H BY R3.L; +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L; +R5.L = ASHIFT R5.H BY R3.L; +R6.L = ASHIFT R6.H BY R3.L; +R7.L = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030010; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R0.L; +R1.H = ASHIFT R1.L BY R0.L; +R2.H = ASHIFT R2.L BY R0.L; +R3.H = ASHIFT R3.L BY R0.L; +R4.H = ASHIFT R4.L BY R0.L; +R5.H = ASHIFT R5.L BY R0.L; +R6.H = ASHIFT R6.L BY R0.L; +R7.H = ASHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R1.L; +R1.H = ASHIFT R1.L BY R1.L; +R2.H = ASHIFT R2.L BY R1.L; +R3.H = ASHIFT R3.L BY R1.L; +R4.H = ASHIFT R4.L BY R1.L; +R5.H = ASHIFT R5.L BY R1.L; +R6.H = ASHIFT R6.L BY R1.L; +R7.H = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0x00020001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040002; +CHECKREG r3, 0x00060003; +CHECKREG r4, 0x00080004; +CHECKREG r5, 0x000a0005; +CHECKREG r6, 0x000c0006; +CHECKREG r7, 0x000e0007; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R2.L; +R1.H = ASHIFT R1.L BY R2.L; +//rh2 = ashift (rl2 by rl2); +R3.H = ASHIFT R3.L BY R2.L; +R4.H = ASHIFT R4.L BY R2.L; +R5.H = ASHIFT R5.L BY R2.L; +R6.H = ASHIFT R6.L BY R2.L; +R7.H = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x80000001; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x80000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x80000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x80000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R3.L; +R1.H = ASHIFT R1.L BY R3.L; +R2.H = ASHIFT R2.L BY R3.L; +R3.H = ASHIFT R3.L BY R3.L; +R4.H = ASHIFT R4.L BY R3.L; +R5.H = ASHIFT R5.L BY R3.L; +R6.H = ASHIFT R6.L BY R3.L; +R7.H = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R0.L; +R1.H = ASHIFT R1.H BY R0.L; +R2.H = ASHIFT R2.H BY R0.L; +R3.H = ASHIFT R3.H BY R0.L; +R4.H = ASHIFT R4.H BY R0.L; +R5.H = ASHIFT R5.H BY R0.L; +R6.H = ASHIFT R6.H BY R0.L; +R7.H = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R1.L; +R1.H = ASHIFT R1.H BY R1.L; +R2.H = ASHIFT R2.H BY R1.L; +R3.H = ASHIFT R3.H BY R1.L; +R4.H = ASHIFT R4.H BY R1.L; +R5.H = ASHIFT R5.H BY R1.L; +R6.H = ASHIFT R6.H BY R1.L; +R7.H = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x00020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040000; +CHECKREG r3, 0x00060000; +CHECKREG r4, 0x00080000; +CHECKREG r5, 0x000a0000; +CHECKREG r6, 0x000c0000; +CHECKREG r7, 0x000e0000; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0x00018000; +CHECKREG r1, 0x00018000; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00038000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00058000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030010; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R3.L; +R1.H = ASHIFT R1.H BY R3.L; +R2.H = ASHIFT R2.H BY R3.L; +R3.H = ASHIFT R3.H BY R3.L; +R4.H = ASHIFT R4.H BY R3.L; +R5.H = ASHIFT R5.H BY R3.L; +R6.H = ASHIFT R6.H BY R3.L; +R7.H = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp_s.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp_s.s new file mode 100644 index 0000000..b07eed8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_lp_s.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_lp_s/c_dsp32shift_ahalf_lp_s.dsp +// Spec Reference: dsp32shift ashift s +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R0.L (S); +R1.L = ASHIFT R1.L BY R0.L (S); +R2.L = ASHIFT R2.L BY R0.L (S); +R3.L = ASHIFT R3.L BY R0.L (S); +R4.L = ASHIFT R4.L BY R0.L (S); +R5.L = ASHIFT R5.L BY R0.L (S); +R6.L = ASHIFT R6.L BY R0.L (S); +R7.L = ASHIFT R7.L BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R1.L (S); +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L (S); +R3.L = ASHIFT R3.L BY R1.L (S); +R4.L = ASHIFT R4.L BY R1.L (S); +R5.L = ASHIFT R5.L BY R1.L (S); +R6.L = ASHIFT R6.L BY R1.L (S); +R7.L = ASHIFT R7.L BY R1.L (S); +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000006; +CHECKREG r4, 0x00000008; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x0000000c; +CHECKREG r7, 0x0000000e; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R2.L (S); +R1.L = ASHIFT R1.L BY R2.L (S); +//rl2 = ashift (rl2 by rl2) s; +R3.L = ASHIFT R3.L BY R2.L (S); +R4.L = ASHIFT R4.L BY R2.L (S); +R5.L = ASHIFT R5.L BY R2.L (S); +R6.L = ASHIFT R6.L BY R2.L (S); +R7.L = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x00007fff; +CHECKREG r1, 0x00007fff; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00007fff; +CHECKREG r4, 0x00007fff; +CHECKREG r5, 0x00007fff; +CHECKREG r6, 0x00007fff; +CHECKREG r7, 0x00007fff; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = ASHIFT R0.L BY R3.L (S); +R1.L = ASHIFT R1.L BY R3.L (S); +R2.L = ASHIFT R2.L BY R3.L (S); +//rl3 = ashift (rl3 by rl3) s; +R4.L = ASHIFT R4.L BY R3.L (S); +R5.L = ASHIFT R5.L BY R3.L (S); +R6.L = ASHIFT R6.L BY R3.L (S); +R7.L = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x00007fff; +CHECKREG r1, 0x00007fff; +CHECKREG r2, 0x00007fff; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00007fff; +CHECKREG r5, 0x00007fff; +CHECKREG r6, 0x00007fff; +CHECKREG r7, 0x00007fff; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L (S); +R1.L = ASHIFT R1.H BY R0.L (S); +R2.L = ASHIFT R2.H BY R0.L (S); +R3.L = ASHIFT R3.H BY R0.L (S); +R4.L = ASHIFT R4.H BY R0.L (S); +R5.L = ASHIFT R5.H BY R0.L (S); +R6.L = ASHIFT R6.H BY R0.L (S); +R7.L = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R1.L (S); +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L (S); +R3.L = ASHIFT R3.H BY R1.L (S); +R4.L = ASHIFT R4.H BY R1.L (S); +R5.L = ASHIFT R5.H BY R1.L (S); +R6.L = ASHIFT R6.H BY R1.L (S); +R7.L = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x00010002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020004; +CHECKREG r3, 0x00030006; +CHECKREG r4, 0x00040008; +CHECKREG r5, 0x0005000a; +CHECKREG r6, 0x0006000c; +CHECKREG r7, 0x0007000e; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0x00017fff; +CHECKREG r1, 0x00017fff; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00037fff; +CHECKREG r4, 0x00047fff; +CHECKREG r5, 0x00057fff; +CHECKREG r6, 0x00067fff; +CHECKREG r7, 0x00077fff; + +imm32 r0, 0x00010001; +imm32 r1, 0x00010001; +imm32 r2, 0x00020002; +imm32 r3, 0x00030010; +imm32 r4, 0x00040004; +imm32 r5, 0x00050005; +imm32 r6, 0x00060006; +imm32 r7, 0x00070007; +R0.L = ASHIFT R0.H BY R3.L (S); +R1.L = ASHIFT R1.H BY R3.L (S); +R2.L = ASHIFT R2.H BY R3.L (S); +//rl3 = ashift (rh3 by rl3) s; +R4.L = ASHIFT R4.H BY R3.L (S); +R5.L = ASHIFT R5.H BY R3.L (S); +R6.L = ASHIFT R6.H BY R3.L (S); +R7.L = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0x00017fff; +CHECKREG r1, 0x00017fff; +CHECKREG r2, 0x00027fff; +CHECKREG r3, 0x00030010; +CHECKREG r4, 0x00047fff; +CHECKREG r5, 0x00057fff; +CHECKREG r6, 0x00067fff; +CHECKREG r7, 0x00077fff; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R0.L (S); +R1.H = ASHIFT R1.L BY R0.L (S); +R2.H = ASHIFT R2.L BY R0.L (S); +R3.H = ASHIFT R3.L BY R0.L (S); +R4.H = ASHIFT R4.L BY R0.L (S); +R5.H = ASHIFT R5.L BY R0.L (S); +R6.H = ASHIFT R6.L BY R0.L (S); +R7.H = ASHIFT R7.L BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R1.L (S); +R1.H = ASHIFT R1.L BY R1.L (S); +R2.H = ASHIFT R2.L BY R1.L (S); +R3.H = ASHIFT R3.L BY R1.L (S); +R4.H = ASHIFT R4.L BY R1.L (S); +R5.H = ASHIFT R5.L BY R1.L (S); +R6.H = ASHIFT R6.L BY R1.L (S); +R7.H = ASHIFT R7.L BY R1.L (S); +CHECKREG r0, 0x00020001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040002; +CHECKREG r3, 0x00060003; +CHECKREG r4, 0x00080004; +CHECKREG r5, 0x000a0005; +CHECKREG r6, 0x000c0006; +CHECKREG r7, 0x000e0007; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R2.L (S); +R1.H = ASHIFT R1.L BY R2.L (S); +//rh2 = ashift (rl2 by rl2) s; +R3.H = ASHIFT R3.L BY R2.L (S); +R4.H = ASHIFT R4.L BY R2.L (S); +R5.H = ASHIFT R5.L BY R2.L (S); +R6.H = ASHIFT R6.L BY R2.L (S); +R7.H = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x7fff0001; +CHECKREG r1, 0x7fff0001; +//ECKREG(r2, 0x7fff000f); +CHECKREG r3, 0x7fff0003; +CHECKREG r4, 0x7fff0004; +CHECKREG r5, 0x7fff0005; +CHECKREG r6, 0x7fff0006; +CHECKREG r7, 0x7fff0007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R3.L (S); +R1.H = ASHIFT R1.L BY R3.L (S); +R2.H = ASHIFT R2.L BY R3.L (S); +R3.H = ASHIFT R3.L BY R3.L (S); +R4.H = ASHIFT R4.L BY R3.L (S); +R5.H = ASHIFT R5.L BY R3.L (S); +R6.H = ASHIFT R6.L BY R3.L (S); +R7.H = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x7fff0001; +CHECKREG r1, 0x7fff0001; +CHECKREG r2, 0x7fff0002; +CHECKREG r3, 0x7fff0010; +CHECKREG r4, 0x7fff0004; +CHECKREG r5, 0x7fff0005; +CHECKREG r6, 0x7fff0006; +CHECKREG r7, 0x7fff0007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R0.L (S); +R1.H = ASHIFT R1.H BY R0.L (S); +R2.H = ASHIFT R2.H BY R0.L (S); +R3.H = ASHIFT R3.H BY R0.L (S); +R4.H = ASHIFT R4.H BY R0.L (S); +R5.H = ASHIFT R5.H BY R0.L (S); +R6.H = ASHIFT R6.H BY R0.L (S); +R7.H = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R1.L (S); +R1.H = ASHIFT R1.H BY R1.L (S); +R2.H = ASHIFT R2.H BY R1.L (S); +R3.H = ASHIFT R3.H BY R1.L (S); +R4.H = ASHIFT R4.H BY R1.L (S); +R5.H = ASHIFT R5.H BY R1.L (S); +R6.H = ASHIFT R6.H BY R1.L (S); +R7.H = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x00020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040000; +CHECKREG r3, 0x00060000; +CHECKREG r4, 0x00080000; +CHECKREG r5, 0x000a0000; +CHECKREG r6, 0x000c0000; +CHECKREG r7, 0x000e0000; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0x00017fff; +CHECKREG r1, 0x00017fff; +//CHECKREG r2, 0x00027fff; +CHECKREG r3, 0x00037fff; +CHECKREG r4, 0x00047fff; +CHECKREG r5, 0x00057fff; +CHECKREG r6, 0x00067fff; +CHECKREG r7, 0x00077fff; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030010; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R3.L (S); +R1.H = ASHIFT R1.H BY R3.L (S); +R2.H = ASHIFT R2.H BY R3.L (S); +R3.H = ASHIFT R3.H BY R3.L (S); +R4.H = ASHIFT R4.H BY R3.L (S); +R5.H = ASHIFT R5.H BY R3.L (S); +R6.H = ASHIFT R6.H BY R3.L (S); +R7.H = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0x7fff0000; +CHECKREG r1, 0x7fff0000; +CHECKREG r2, 0x7fff0000; +CHECKREG r3, 0x7fff0010; +CHECKREG r4, 0x7fff0000; +CHECKREG r5, 0x7fff0000; +CHECKREG r6, 0x7fff0000; +CHECKREG r7, 0x7fff0000; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn.s new file mode 100644 index 0000000..aaa282c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_rn/c_dsp32shift_ahalf_rn.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=right (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +//rl0 = ashift (rl0 by rl0); +R1.L = ASHIFT R1.L BY R0.L; +R2.L = ASHIFT R2.L BY R0.L; +R3.L = ASHIFT R3.L BY R0.L; +R4.L = ASHIFT R4.L BY R0.L; +R5.L = ASHIFT R5.L BY R0.L; +R6.L = ASHIFT R6.L BY R0.L; +R7.L = ASHIFT R7.L BY R0.L; +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c000; +CHECKREG r2, 0x0000c001; +CHECKREG r3, 0x0000c001; +CHECKREG r4, 0x0000c002; +CHECKREG r5, 0x0000c002; +CHECKREG r6, 0x0000c003; +CHECKREG r7, 0x0000c003; + +imm32 r0, 0x00008001; +R1.L = -1; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R1.L; +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L; +R3.L = ASHIFT R3.L BY R1.L; +R4.L = ASHIFT R4.L BY R1.L; +R5.L = ASHIFT R5.L BY R1.L; +R6.L = ASHIFT R6.L BY R1.L; +R7.L = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0x0000c000; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000c001; +CHECKREG r3, 0x0000c001; +CHECKREG r4, 0x0000c002; +CHECKREG r5, 0x0000c002; +CHECKREG r6, 0x0000c003; +CHECKREG r7, 0x0000c003; + + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +R2.L = -15; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R2.L; +R1.L = ASHIFT R1.L BY R2.L; +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L; +R4.L = ASHIFT R4.L BY R2.L; +R5.L = ASHIFT R5.L BY R2.L; +R6.L = ASHIFT R6.L BY R2.L; +R7.L = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0000ffff; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x0000ffff; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +R3.L = -16; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R3.L; +R1.L = ASHIFT R1.L BY R3.L; +R2.L = ASHIFT R2.L BY R3.L; +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L; +R5.L = ASHIFT R5.L BY R3.L; +R6.L = ASHIFT R6.L BY R3.L; +R7.L = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0000ffff; +CHECKREG r2, 0x0000ffff; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = ASHIFT R0.H BY R0.L; +R1.L = ASHIFT R1.H BY R0.L; +R2.L = ASHIFT R2.H BY R0.L; +R3.L = ASHIFT R3.H BY R0.L; +R4.L = ASHIFT R4.H BY R0.L; +R5.L = ASHIFT R5.H BY R0.L; +R6.L = ASHIFT R6.H BY R0.L; +R7.L = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x80018001; +CHECKREG r2, 0x80028002; +CHECKREG r3, 0x80038003; +CHECKREG r4, 0x80048004; +CHECKREG r5, 0x80058005; +CHECKREG r6, 0x80068006; +CHECKREG r7, 0x80078007; + +imm32 r0, 0x80010000; +R1.L = -1; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = ASHIFT R0.H BY R1.L; +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L; +R3.L = ASHIFT R3.H BY R1.L; +R4.L = ASHIFT R4.H BY R1.L; +R5.L = ASHIFT R5.H BY R1.L; +R6.L = ASHIFT R6.H BY R1.L; +R7.L = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x8001c000; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x8002c001; +CHECKREG r3, 0x8003c001; +CHECKREG r4, 0x8004c002; +CHECKREG r5, 0x8005c002; +CHECKREG r6, 0x8006c003; +CHECKREG r7, 0x8007c003; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +R2.L = -15; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0xa001ffff; +CHECKREG r1, 0xa001ffff; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0xa003ffff; +CHECKREG r4, 0xa004ffff; +CHECKREG r5, 0xa005ffff; +CHECKREG r6, 0xa006ffff; +CHECKREG r7, 0xa007ffff; + +imm32 r0, 0xb0010001; +imm32 r1, 0xb0010001; +imm32 r2, 0xb0020002; +R3.L = -16; +imm32 r4, 0xb0040004; +imm32 r5, 0xb0050005; +imm32 r6, 0xb0060006; +imm32 r7, 0xb0070007; +R0.L = ASHIFT R0.H BY R3.L; +R1.L = ASHIFT R1.H BY R3.L; +R2.L = ASHIFT R2.H BY R3.L; +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L; +R5.L = ASHIFT R5.H BY R3.L; +R6.L = ASHIFT R6.H BY R3.L; +R7.L = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0xb001ffff; +CHECKREG r1, 0xb001ffff; +CHECKREG r2, 0xb002ffff; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0xb004ffff; +CHECKREG r5, 0xb005ffff; +CHECKREG r6, 0xb006ffff; +CHECKREG r7, 0xb007ffff; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R4.L; +R1.H = ASHIFT R1.L BY R4.L; +R2.H = ASHIFT R2.L BY R4.L; +R3.H = ASHIFT R3.L BY R4.L; +//rh4 = ashift (rl4 by rl4); +R5.H = ASHIFT R5.L BY R4.L; +R6.H = ASHIFT R6.L BY R4.L; +R7.H = ASHIFT R7.L BY R4.L; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +R5.L = -1; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = ASHIFT R0.L BY R5.L; +R1.H = ASHIFT R1.L BY R5.L; +R2.H = ASHIFT R2.L BY R5.L; +R3.H = ASHIFT R3.L BY R5.L; +R4.H = ASHIFT R4.L BY R5.L; +//rh5 = ashift (rl5 by rl5); +R6.H = ASHIFT R6.L BY R5.L; +R7.H = ASHIFT R7.L BY R5.L; +CHECKREG r0, 0xc0008001; +CHECKREG r1, 0xc0008001; +CHECKREG r2, 0xc0018002; +CHECKREG r3, 0xc0018003; +CHECKREG r4, 0xc0028004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0xc0038006; +CHECKREG r7, 0xc0038007; + + +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009004; +imm32 r5, 0x00009005; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = ASHIFT R0.L BY R6.L; +R1.H = ASHIFT R1.L BY R6.L; +R2.H = ASHIFT R2.L BY R6.L; +R3.H = ASHIFT R3.L BY R6.L; +R4.H = ASHIFT R4.L BY R6.L; +R5.H = ASHIFT R5.L BY R6.L; +//rh6 = ashift (rl6 by rl6); +R7.H = ASHIFT R7.L BY R6.L; +CHECKREG r0, 0xffff9001; +CHECKREG r1, 0xffff9001; +CHECKREG r2, 0xffff9002; +CHECKREG r3, 0xffff9003; +CHECKREG r4, 0xffff9004; +CHECKREG r5, 0xffff9005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0xffff9007; + +imm32 r0, 0x0000a001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000a002; +imm32 r3, 0x0000a003; +imm32 r4, 0x0000a004; +imm32 r5, 0x0000a005; +imm32 r6, 0x0000a006; +R7.L = -16; +R0.H = ASHIFT R0.L BY R7.L; +R1.H = ASHIFT R1.L BY R7.L; +R2.H = ASHIFT R2.L BY R7.L; +R3.H = ASHIFT R3.L BY R7.L; +R4.H = ASHIFT R4.L BY R7.L; +R5.H = ASHIFT R5.L BY R7.L; +R6.H = ASHIFT R6.L BY R7.L; +R7.H = ASHIFT R7.L BY R7.L; +CHECKREG r0, 0xffffa001; +CHECKREG r1, 0xffffa001; +CHECKREG r2, 0xffffa002; +CHECKREG r3, 0xffffa003; +CHECKREG r4, 0xffffa004; +CHECKREG r5, 0xffffa005; +CHECKREG r6, 0xffffa006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +R4.L = -1; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = ASHIFT R0.H BY R4.L; +R1.H = ASHIFT R1.H BY R4.L; +R2.H = ASHIFT R2.H BY R4.L; +R3.H = ASHIFT R3.H BY R4.L; +//rh4 = ashift (rh4 by rl4); +R5.H = ASHIFT R5.H BY R4.L; +R6.H = ASHIFT R6.H BY R4.L; +R7.H = ASHIFT R7.H BY R4.L; +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xc0010000; +CHECKREG r3, 0xc0010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0xc0020000; +CHECKREG r6, 0xc0030000; +CHECKREG r7, 0xc0030000; + +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +R5.L = -1; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = ASHIFT R0.H BY R5.L; +R1.H = ASHIFT R1.H BY R5.L; +R2.H = ASHIFT R2.H BY R5.L; +R3.H = ASHIFT R3.H BY R5.L; +R4.H = ASHIFT R4.H BY R5.L; +//rh5 = ashift (rh5 by rl5); +R6.H = ASHIFT R6.H BY R5.L; +R7.H = ASHIFT R7.H BY R5.L; +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xc0010000; +CHECKREG r3, 0xc0010000; +CHECKREG r4, 0xc0020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0xc0030000; +CHECKREG r7, 0xc0030000; + + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030000; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = ASHIFT R0.H BY R6.L; +R1.L = ASHIFT R1.H BY R6.L; +R2.L = ASHIFT R2.H BY R6.L; +R3.L = ASHIFT R3.H BY R6.L; +R4.L = ASHIFT R4.H BY R6.L; +R5.L = ASHIFT R5.H BY R6.L; +//rl6 = ashift (rh6 by rl6); +R7.L = ASHIFT R7.H BY R6.L; +CHECKREG r0, 0xd001ffff; +CHECKREG r1, 0xd001ffff; +CHECKREG r2, 0xd002ffff; +CHECKREG r3, 0xd003ffff; +CHECKREG r4, 0xd004ffff; +CHECKREG r5, 0xd005ffff; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0xd007ffff; + +imm32 r0, 0xe0010000; +imm32 r1, 0xe0010000; +imm32 r2, 0xe0020000; +imm32 r3, 0xe0030000; +imm32 r4, 0xe0040000; +imm32 r5, 0xe0050000; +imm32 r6, 0xe0060000; +R7.L = -16; +R0.H = ASHIFT R0.H BY R7.L; +R1.H = ASHIFT R1.H BY R7.L; +R2.H = ASHIFT R2.H BY R7.L; +R3.H = ASHIFT R3.H BY R7.L; +R4.H = ASHIFT R4.H BY R7.L; +R5.H = ASHIFT R5.H BY R7.L; +R6.H = ASHIFT R6.H BY R7.L; +//rh7 = ashift (rh7 by rl7); +CHECKREG r0, 0xffff0000; +CHECKREG r1, 0xffff0000; +CHECKREG r2, 0xffff0000; +CHECKREG r3, 0xffff0000; +CHECKREG r4, 0xffff0000; +CHECKREG r5, 0xffff0000; +CHECKREG r6, 0xffff0000; +//CHECKREG r7, -16; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn_s.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn_s.s new file mode 100644 index 0000000..503671e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rn_s.s @@ -0,0 +1,424 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_rn_s/c_dsp32shift_ahalf_rn_s.dsp +// Spec Reference: dsp32shift ashift s +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +//rl0 = ashift (rl0 by rl0); +R1.L = ASHIFT R1.L BY R0.L (S); +R2.L = ASHIFT R2.L BY R0.L (S); +R3.L = ASHIFT R3.L BY R0.L (S); +R4.L = ASHIFT R4.L BY R0.L (S); +R5.L = ASHIFT R5.L BY R0.L (S); +R6.L = ASHIFT R6.L BY R0.L (S); +R7.L = ASHIFT R7.L BY R0.L (S); +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c000; +CHECKREG r2, 0x0000c001; +CHECKREG r3, 0x0000c001; +CHECKREG r4, 0x0000c002; +CHECKREG r5, 0x0000c002; +CHECKREG r6, 0x0000c003; +CHECKREG r7, 0x0000c003; + +imm32 r0, 0x00008001; +R1.L = -1; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R1.L (S); +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L (S); +R3.L = ASHIFT R3.L BY R1.L (S); +R4.L = ASHIFT R4.L BY R1.L (S); +R5.L = ASHIFT R5.L BY R1.L (S); +R6.L = ASHIFT R6.L BY R1.L (S); +R7.L = ASHIFT R7.L BY R1.L (S); +CHECKREG r0, 0x0000c000; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000c001; +CHECKREG r3, 0x0000c001; +CHECKREG r4, 0x0000c002; +CHECKREG r5, 0x0000c002; +CHECKREG r6, 0x0000c003; +CHECKREG r7, 0x0000c003; + + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +R2.L = -15; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R2.L (S); +R1.L = ASHIFT R1.L BY R2.L (S); +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L (S); +R4.L = ASHIFT R4.L BY R2.L (S); +R5.L = ASHIFT R5.L BY R2.L (S); +R6.L = ASHIFT R6.L BY R2.L (S); +R7.L = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0000ffff; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x0000ffff; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +R3.L = -16; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = ASHIFT R0.L BY R3.L (S); +R1.L = ASHIFT R1.L BY R3.L (S); +R2.L = ASHIFT R2.L BY R3.L (S); +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L (S); +R5.L = ASHIFT R5.L BY R3.L (S); +R6.L = ASHIFT R6.L BY R3.L (S); +R7.L = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0000ffff; +CHECKREG r2, 0x0000ffff; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = ASHIFT R0.H BY R0.L (S); +R1.L = ASHIFT R1.H BY R0.L (S); +R2.L = ASHIFT R2.H BY R0.L (S); +R3.L = ASHIFT R3.H BY R0.L (S); +R4.L = ASHIFT R4.H BY R0.L (S); +R5.L = ASHIFT R5.H BY R0.L (S); +R6.L = ASHIFT R6.H BY R0.L (S); +R7.L = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x80018001; +CHECKREG r2, 0x80028002; +CHECKREG r3, 0x80038003; +CHECKREG r4, 0x80048004; +CHECKREG r5, 0x80058005; +CHECKREG r6, 0x80068006; +CHECKREG r7, 0x80078007; + +imm32 r0, 0x80010000; +R1.L = -1; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = ASHIFT R0.H BY R1.L (S); +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L (S); +R3.L = ASHIFT R3.H BY R1.L (S); +R4.L = ASHIFT R4.H BY R1.L (S); +R5.L = ASHIFT R5.H BY R1.L (S); +R6.L = ASHIFT R6.H BY R1.L (S); +R7.L = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x8001c000; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x8002c001; +CHECKREG r3, 0x8003c001; +CHECKREG r4, 0x8004c002; +CHECKREG r5, 0x8005c002; +CHECKREG r6, 0x8006c003; +CHECKREG r7, 0x8007c003; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +R2.L = -15; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0xa001ffff; +CHECKREG r1, 0xa001ffff; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0xa003ffff; +CHECKREG r4, 0xa004ffff; +CHECKREG r5, 0xa005ffff; +CHECKREG r6, 0xa006ffff; +CHECKREG r7, 0xa007ffff; + +imm32 r0, 0xb0010001; +imm32 r1, 0xb0010001; +imm32 r2, 0xb0020002; +R3.L = -16; +imm32 r4, 0xb0040004; +imm32 r5, 0xb0050005; +imm32 r6, 0xb0060006; +imm32 r7, 0xb0070007; +R0.L = ASHIFT R0.H BY R3.L (S); +R1.L = ASHIFT R1.H BY R3.L (S); +R2.L = ASHIFT R2.H BY R3.L (S); +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L (S); +R5.L = ASHIFT R5.H BY R3.L (S); +R6.L = ASHIFT R6.H BY R3.L (S); +R7.L = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0xb001ffff; +CHECKREG r1, 0xb001ffff; +CHECKREG r2, 0xb002ffff; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0xb004ffff; +CHECKREG r5, 0xb005ffff; +CHECKREG r6, 0xb006ffff; +CHECKREG r7, 0xb007ffff; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R4.L (S); +R1.H = ASHIFT R1.L BY R4.L (S); +R2.H = ASHIFT R2.L BY R4.L (S); +R3.H = ASHIFT R3.L BY R4.L (S); +//rh4 = ashift (rl4 by rl4); +R5.H = ASHIFT R5.L BY R4.L (S); +R6.H = ASHIFT R6.L BY R4.L (S); +R7.H = ASHIFT R7.L BY R4.L (S); +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +R5.L = -1; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = ASHIFT R0.L BY R5.L (S); +R1.H = ASHIFT R1.L BY R5.L (S); +R2.H = ASHIFT R2.L BY R5.L (S); +R3.H = ASHIFT R3.L BY R5.L (S); +R4.H = ASHIFT R4.L BY R5.L (S); +//rh5 = ashift (rl5 by rl5); +R6.H = ASHIFT R6.L BY R5.L (S); +R7.H = ASHIFT R7.L BY R5.L (S); +CHECKREG r0, 0xc0008001; +CHECKREG r1, 0xc0008001; +CHECKREG r2, 0xc0018002; +CHECKREG r3, 0xc0018003; +CHECKREG r4, 0xc0028004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0xc0038006; +CHECKREG r7, 0xc0038007; + + +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009004; +imm32 r5, 0x00009005; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = ASHIFT R0.L BY R6.L (S); +R1.H = ASHIFT R1.L BY R6.L (S); +R2.H = ASHIFT R2.L BY R6.L (S); +R3.H = ASHIFT R3.L BY R6.L (S); +R4.H = ASHIFT R4.L BY R6.L (S); +R5.H = ASHIFT R5.L BY R6.L (S); +//rh6 = ashift (rl6 by rl6); +R7.H = ASHIFT R7.L BY R6.L; +CHECKREG r0, 0xffff9001; +CHECKREG r1, 0xffff9001; +CHECKREG r2, 0xffff9002; +CHECKREG r3, 0xffff9003; +CHECKREG r4, 0xffff9004; +CHECKREG r5, 0xffff9005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0xffff9007; + +imm32 r0, 0x0000a001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000a002; +imm32 r3, 0x0000a003; +imm32 r4, 0x0000a004; +imm32 r5, 0x0000a005; +imm32 r6, 0x0000a006; +R7.L = -16; +R0.H = ASHIFT R0.L BY R7.L (S); +R1.H = ASHIFT R1.L BY R7.L (S); +R2.H = ASHIFT R2.L BY R7.L (S); +R3.H = ASHIFT R3.L BY R7.L (S); +R4.H = ASHIFT R4.L BY R7.L (S); +R5.H = ASHIFT R5.L BY R7.L (S); +R6.H = ASHIFT R6.L BY R7.L (S); +R7.H = ASHIFT R7.L BY R7.L (S); +CHECKREG r0, 0xffffa001; +CHECKREG r1, 0xffffa001; +CHECKREG r2, 0xffffa002; +CHECKREG r3, 0xffffa003; +CHECKREG r4, 0xffffa004; +CHECKREG r5, 0xffffa005; +CHECKREG r6, 0xffffa006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +R4.L = -1; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = ASHIFT R0.H BY R4.L (S); +R1.H = ASHIFT R1.H BY R4.L (S); +R2.H = ASHIFT R2.H BY R4.L (S); +R3.H = ASHIFT R3.H BY R4.L (S); +//rh4 = ashift (rh4 by rl4); +R5.H = ASHIFT R5.H BY R4.L (S); +R6.H = ASHIFT R6.H BY R4.L (S); +R7.H = ASHIFT R7.H BY R4.L (S); +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xc0010000; +CHECKREG r3, 0xc0010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0xc0020000; +CHECKREG r6, 0xc0030000; +CHECKREG r7, 0xc0030000; + +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +R5.L = -1; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = ASHIFT R0.H BY R5.L (S); +R1.H = ASHIFT R1.H BY R5.L (S); +R2.H = ASHIFT R2.H BY R5.L (S); +R3.H = ASHIFT R3.H BY R5.L (S); +R4.H = ASHIFT R4.H BY R5.L (S); +//rh5 = ashift (rh5 by rl5); +R6.H = ASHIFT R6.H BY R5.L (S); +R7.H = ASHIFT R7.H BY R5.L (S); +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xc0010000; +CHECKREG r3, 0xc0010000; +CHECKREG r4, 0xc0020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0xc0030000; +CHECKREG r7, 0xc0030000; + + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030000; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = ASHIFT R0.H BY R6.L (S); +R1.L = ASHIFT R1.H BY R6.L (S); +R2.L = ASHIFT R2.H BY R6.L (S); +R3.L = ASHIFT R3.H BY R6.L (S); +R4.L = ASHIFT R4.H BY R6.L (S); +R5.L = ASHIFT R5.H BY R6.L (S); +//rl6 = ashift (rh6 by rl6); +R7.L = ASHIFT R7.H BY R6.L; +CHECKREG r0, 0xd001ffff; +CHECKREG r1, 0xd001ffff; +CHECKREG r2, 0xd002ffff; +CHECKREG r3, 0xd003ffff; +CHECKREG r4, 0xd004ffff; +CHECKREG r5, 0xd005ffff; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0xd007ffff; + +imm32 r0, 0xe0010000; +imm32 r1, 0xe0010000; +imm32 r2, 0xe0020000; +imm32 r3, 0xe0030000; +imm32 r4, 0xe0040000; +imm32 r5, 0xe0050000; +imm32 r6, 0xe0060000; +R7.L = -16; +R0.H = ASHIFT R0.H BY R7.L (S); +R1.H = ASHIFT R1.H BY R7.L (S); +R2.H = ASHIFT R2.H BY R7.L (S); +R3.H = ASHIFT R3.H BY R7.L (S); +R4.H = ASHIFT R4.H BY R7.L (S); +R5.H = ASHIFT R5.H BY R7.L (S); +R6.H = ASHIFT R6.H BY R7.L (S); +//rh7 = ashift (rh7 by rl7); +CHECKREG r0, 0xffff0000; +CHECKREG r1, 0xffff0000; +CHECKREG r2, 0xffff0000; +CHECKREG r3, 0xffff0000; +CHECKREG r4, 0xffff0000; +CHECKREG r5, 0xffff0000; +CHECKREG r6, 0xffff0000; +//CHECKREG r7, -16; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp.s new file mode 100644 index 0000000..e3480d5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_rp/c_dsp32shift_ahalf_rp.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=right (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +//rl0 = ashift (rl0 by rl0); +R1.L = ASHIFT R1.L BY R0.L; +R2.L = ASHIFT R2.L BY R0.L; +R3.L = ASHIFT R3.L BY R0.L; +R4.L = ASHIFT R4.L BY R0.L; +R5.L = ASHIFT R5.L BY R0.L; +R6.L = ASHIFT R6.L BY R0.L; +R7.L = ASHIFT R7.L BY R0.L; +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x00001001; +R1.L = -1; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R1.L; +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L; +R3.L = ASHIFT R3.L BY R1.L; +R4.L = ASHIFT R4.L BY R1.L; +R5.L = ASHIFT R5.L BY R1.L; +R6.L = ASHIFT R6.L BY R1.L; +R7.L = ASHIFT R7.L BY R1.L; +CHECKREG r0, 0x00000800; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00001001; +CHECKREG r3, 0x00001801; +CHECKREG r4, 0x00002002; +CHECKREG r5, 0x00002802; +CHECKREG r6, 0x00003003; +CHECKREG r7, 0x00003803; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +R2.L = -15; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R2.L; +R1.L = ASHIFT R1.L BY R2.L; +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L; +R4.L = ASHIFT R4.L BY R2.L; +R5.L = ASHIFT R5.L BY R2.L; +R6.L = ASHIFT R6.L BY R2.L; +R7.L = ASHIFT R7.L BY R2.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r2, 0x00002002; +R3.L = -16; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R3.L; +R1.L = ASHIFT R1.L BY R3.L; +R2.L = ASHIFT R2.L BY R3.L; +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L; +R5.L = ASHIFT R5.L BY R3.L; +R6.L = ASHIFT R6.L BY R3.L; +R7.L = ASHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L; +R1.L = ASHIFT R1.H BY R0.L; +R2.L = ASHIFT R2.H BY R0.L; +R3.L = ASHIFT R3.H BY R0.L; +R4.L = ASHIFT R4.H BY R0.L; +R5.L = ASHIFT R5.H BY R0.L; +R6.L = ASHIFT R6.H BY R0.L; +R7.L = ASHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x10010000; +R1.L = -1; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R1.L; +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L; +R3.L = ASHIFT R3.H BY R1.L; +R4.L = ASHIFT R4.H BY R1.L; +R5.L = ASHIFT R5.H BY R1.L; +R6.L = ASHIFT R6.H BY R1.L; +R7.L = ASHIFT R7.H BY R1.L; +CHECKREG r0, 0x10010800; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x20021001; +CHECKREG r3, 0x30031801; +CHECKREG r4, 0x40042002; +CHECKREG r5, 0x50052802; +CHECKREG r6, 0x60063003; +CHECKREG r7, 0x70073803; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +R2.L = -15; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R2.L; +R1.L = ASHIFT R1.H BY R2.L; +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L; +R4.L = ASHIFT R4.H BY R2.L; +R5.L = ASHIFT R5.H BY R2.L; +R6.L = ASHIFT R6.H BY R2.L; +R7.L = ASHIFT R7.H BY R2.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010001; +imm32 r1, 0x10010001; +imm32 r2, 0x20020002; +R3.L = -16; +imm32 r4, 0x40040004; +imm32 r5, 0x50050005; +imm32 r6, 0x60060006; +imm32 r7, 0x70070007; +R0.L = ASHIFT R0.H BY R3.L; +R1.L = ASHIFT R1.H BY R3.L; +R2.L = ASHIFT R2.H BY R3.L; +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L; +R5.L = ASHIFT R5.H BY R3.L; +R6.L = ASHIFT R6.H BY R3.L; +R7.L = ASHIFT R7.H BY R3.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R4.L; +R1.H = ASHIFT R1.L BY R4.L; +R2.H = ASHIFT R2.L BY R4.L; +R3.H = ASHIFT R3.L BY R4.L; +//rh4 = ashift (rl4 by rl4); +R5.H = ASHIFT R5.L BY R4.L; +R6.H = ASHIFT R6.L BY R4.L; +R7.H = ASHIFT R7.L BY R4.L; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +R5.L = -1; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R5.L; +R1.H = ASHIFT R1.L BY R5.L; +R2.H = ASHIFT R2.L BY R5.L; +R3.H = ASHIFT R3.L BY R5.L; +R4.H = ASHIFT R4.L BY R5.L; +//rh5 = ashift (rl5 by rl5); +R6.H = ASHIFT R6.L BY R5.L; +R7.H = ASHIFT R7.L BY R5.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00010002; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0x00030006; +CHECKREG r7, 0x00030007; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r1, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +R6.L = -15; +imm32 r7, 0x00007007; +R0.H = ASHIFT R0.L BY R6.L; +R1.H = ASHIFT R1.L BY R6.L; +R2.H = ASHIFT R2.L BY R6.L; +R3.H = ASHIFT R3.L BY R6.L; +R4.H = ASHIFT R4.L BY R6.L; +R5.H = ASHIFT R5.L BY R6.L; +//rh6 = ashift (rl6 by rl6); +R7.H = ASHIFT R7.L BY R6.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00007007; + +imm32 r0, 0x00001001; +imm32 r1, 0x00002001; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +R7.L = -16; +R0.H = ASHIFT R0.L BY R7.L; +R1.H = ASHIFT R1.L BY R7.L; +R2.H = ASHIFT R2.L BY R7.L; +R3.H = ASHIFT R3.L BY R7.L; +R4.H = ASHIFT R4.L BY R7.L; +R5.H = ASHIFT R5.L BY R7.L; +R6.H = ASHIFT R6.L BY R7.L; +R7.H = ASHIFT R7.L BY R7.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002001; +CHECKREG r2, 0x00002002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +CHECKREG r6, 0x00006006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +R4.L = -1; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R4.L; +R1.H = ASHIFT R1.H BY R4.L; +R2.H = ASHIFT R2.H BY R4.L; +R3.H = ASHIFT R3.H BY R4.L; +//rh4 = ashift (rh4 by rl4); +R5.H = ASHIFT R5.H BY R4.L; +R6.H = ASHIFT R6.H BY R4.L; +R7.H = ASHIFT R7.H BY R4.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00010000; +CHECKREG r3, 0x00010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0x00020000; +CHECKREG r6, 0x00030000; +CHECKREG r7, 0x00030000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +R5.L = -1; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.H = ASHIFT R0.H BY R5.L; +R1.H = ASHIFT R1.H BY R5.L; +R2.H = ASHIFT R2.H BY R5.L; +R3.H = ASHIFT R3.H BY R5.L; +R4.H = ASHIFT R4.H BY R5.L; +//rh5 = ashift (rh5 by rl5); +R6.H = ASHIFT R6.H BY R5.L; +R7.H = ASHIFT R7.H BY R5.L; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x08000000; +CHECKREG r2, 0x10010000; +CHECKREG r3, 0x18010000; +CHECKREG r4, 0x20020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0x30030000; +CHECKREG r7, 0x38030000; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +R6.L = -15; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R6.L; +R1.L = ASHIFT R1.H BY R6.L; +R2.L = ASHIFT R2.H BY R6.L; +R3.L = ASHIFT R3.H BY R6.L; +R4.L = ASHIFT R4.H BY R6.L; +R5.L = ASHIFT R5.H BY R6.L; +//rl6 = ashift (rh6 by rl6); +R7.L = ASHIFT R7.H BY R6.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r2, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +R7.L = -16; +R0.H = ASHIFT R0.H BY R7.L; +R1.H = ASHIFT R1.H BY R7.L; +R2.H = ASHIFT R2.H BY R7.L; +R3.H = ASHIFT R3.H BY R7.L; +R4.H = ASHIFT R4.H BY R7.L; +R5.H = ASHIFT R5.H BY R7.L; +R6.H = ASHIFT R6.H BY R7.L; +//rh7 = ashift (rh7 by rl7); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +//CHECKREG r7, -16; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp_s.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp_s.s new file mode 100644 index 0000000..3e467f2 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_ahalf_rp_s.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_ahalf_rp_s/c_dsp32shift_ahalf_rp_s.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +//rl0 = ashift (rl0 by rl0); +R1.L = ASHIFT R1.L BY R0.L (S); +R2.L = ASHIFT R2.L BY R0.L (S); +R3.L = ASHIFT R3.L BY R0.L (S); +R4.L = ASHIFT R4.L BY R0.L (S); +R5.L = ASHIFT R5.L BY R0.L (S); +R6.L = ASHIFT R6.L BY R0.L (S); +R7.L = ASHIFT R7.L BY R0.L (S); +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x00001001; +R1.L = -1; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R1.L (S); +//rl1 = ashift (rl1 by rl1); +R2.L = ASHIFT R2.L BY R1.L (S); +R3.L = ASHIFT R3.L BY R1.L (S); +R4.L = ASHIFT R4.L BY R1.L (S); +R5.L = ASHIFT R5.L BY R1.L (S); +R6.L = ASHIFT R6.L BY R1.L (S); +R7.L = ASHIFT R7.L BY R1.L (S); +CHECKREG r0, 0x00000800; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00001001; +CHECKREG r3, 0x00001801; +CHECKREG r4, 0x00002002; +CHECKREG r5, 0x00002802; +CHECKREG r6, 0x00003003; +CHECKREG r7, 0x00003803; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +R2.L = -15; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R2.L (S); +R1.L = ASHIFT R1.L BY R2.L (S); +//rl2 = ashift (rl2 by rl2); +R3.L = ASHIFT R3.L BY R2.L (S); +R4.L = ASHIFT R4.L BY R2.L (S); +R5.L = ASHIFT R5.L BY R2.L (S); +R6.L = ASHIFT R6.L BY R2.L (S); +R7.L = ASHIFT R7.L BY R2.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r2, 0x00002002; +R3.L = -16; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = ASHIFT R0.L BY R3.L (S); +R1.L = ASHIFT R1.L BY R3.L (S); +R2.L = ASHIFT R2.L BY R3.L (S); +//rl3 = ashift (rl3 by rl3); +R4.L = ASHIFT R4.L BY R3.L (S); +R5.L = ASHIFT R5.L BY R3.L (S); +R6.L = ASHIFT R6.L BY R3.L (S); +R7.L = ASHIFT R7.L BY R3.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ASHIFT R0.H BY R0.L (S); +R1.L = ASHIFT R1.H BY R0.L (S); +R2.L = ASHIFT R2.H BY R0.L (S); +R3.L = ASHIFT R3.H BY R0.L (S); +R4.L = ASHIFT R4.H BY R0.L (S); +R5.L = ASHIFT R5.H BY R0.L (S); +R6.L = ASHIFT R6.H BY R0.L (S); +R7.L = ASHIFT R7.H BY R0.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x10010000; +R1.L = -1; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R1.L (S); +//rl1 = ashift (rh1 by rl1); +R2.L = ASHIFT R2.H BY R1.L (S); +R3.L = ASHIFT R3.H BY R1.L (S); +R4.L = ASHIFT R4.H BY R1.L (S); +R5.L = ASHIFT R5.H BY R1.L (S); +R6.L = ASHIFT R6.H BY R1.L (S); +R7.L = ASHIFT R7.H BY R1.L (S); +CHECKREG r0, 0x10010800; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x20021001; +CHECKREG r3, 0x30031801; +CHECKREG r4, 0x40042002; +CHECKREG r5, 0x50052802; +CHECKREG r6, 0x60063003; +CHECKREG r7, 0x70073803; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +R2.L = -15; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R2.L (S); +R1.L = ASHIFT R1.H BY R2.L (S); +//rl2 = ashift (rh2 by rl2); +R3.L = ASHIFT R3.H BY R2.L (S); +R4.L = ASHIFT R4.H BY R2.L (S); +R5.L = ASHIFT R5.H BY R2.L (S); +R6.L = ASHIFT R6.H BY R2.L (S); +R7.L = ASHIFT R7.H BY R2.L (S); +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010001; +imm32 r1, 0x10010001; +imm32 r2, 0x20020002; +R3.L = -16; +imm32 r4, 0x40040004; +imm32 r5, 0x50050005; +imm32 r6, 0x60060006; +imm32 r7, 0x70070007; +R0.L = ASHIFT R0.H BY R3.L (S); +R1.L = ASHIFT R1.H BY R3.L (S); +R2.L = ASHIFT R2.H BY R3.L (S); +//rl3 = ashift (rh3 by rl3); +R4.L = ASHIFT R4.H BY R3.L (S); +R5.L = ASHIFT R5.H BY R3.L (S); +R6.L = ASHIFT R6.H BY R3.L (S); +R7.L = ASHIFT R7.H BY R3.L (S); +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +// d_hi = ashift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R4.L (S); +R1.H = ASHIFT R1.L BY R4.L (S); +R2.H = ASHIFT R2.L BY R4.L (S); +R3.H = ASHIFT R3.L BY R4.L (S); +//rh4 = ashift (rl4 by rl4); +R5.H = ASHIFT R5.L BY R4.L (S); +R6.H = ASHIFT R6.L BY R4.L (S); +R7.H = ASHIFT R7.L BY R4.L (S); +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +R5.L = -1; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = ASHIFT R0.L BY R5.L (S); +R1.H = ASHIFT R1.L BY R5.L (S); +R2.H = ASHIFT R2.L BY R5.L (S); +R3.H = ASHIFT R3.L BY R5.L (S); +R4.H = ASHIFT R4.L BY R5.L (S); +//rh5 = ashift (rl5 by rl5); +R6.H = ASHIFT R6.L BY R5.L (S); +R7.H = ASHIFT R7.L BY R5.L (S); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00010002; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0x00030006; +CHECKREG r7, 0x00030007; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r1, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +R6.L = -15; +imm32 r7, 0x00007007; +R0.H = ASHIFT R0.L BY R6.L (S); +R1.H = ASHIFT R1.L BY R6.L (S); +R2.H = ASHIFT R2.L BY R6.L (S); +R3.H = ASHIFT R3.L BY R6.L (S); +R4.H = ASHIFT R4.L BY R6.L (S); +R5.H = ASHIFT R5.L BY R6.L (S); +//rh6 = ashift (rl6 by rl6); +R7.H = ASHIFT R7.L BY R6.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00007007; + +imm32 r0, 0x00001001; +imm32 r1, 0x00002001; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +R7.L = -16; +R0.H = ASHIFT R0.L BY R7.L (S); +R1.H = ASHIFT R1.L BY R7.L (S); +R2.H = ASHIFT R2.L BY R7.L (S); +R3.H = ASHIFT R3.L BY R7.L (S); +R4.H = ASHIFT R4.L BY R7.L (S); +R5.H = ASHIFT R5.L BY R7.L (S); +R6.H = ASHIFT R6.L BY R7.L (S); +R7.H = ASHIFT R7.L BY R7.L (S); +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002001; +CHECKREG r2, 0x00002002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +CHECKREG r6, 0x00006006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +R4.L = -1; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = ASHIFT R0.H BY R4.L (S); +R1.H = ASHIFT R1.H BY R4.L (S); +R2.H = ASHIFT R2.H BY R4.L (S); +R3.H = ASHIFT R3.H BY R4.L (S); +//rh4 = ashift (rh4 by rl4); +R5.H = ASHIFT R5.H BY R4.L (S); +R6.H = ASHIFT R6.H BY R4.L (S); +R7.H = ASHIFT R7.H BY R4.L (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00010000; +CHECKREG r3, 0x00010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0x00020000; +CHECKREG r6, 0x00030000; +CHECKREG r7, 0x00030000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +R5.L = -1; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.H = ASHIFT R0.H BY R5.L (S); +R1.H = ASHIFT R1.H BY R5.L (S); +R2.H = ASHIFT R2.H BY R5.L (S); +R3.H = ASHIFT R3.H BY R5.L (S); +R4.H = ASHIFT R4.H BY R5.L (S); +//rh5 = ashift (rh5 by rl5); +R6.H = ASHIFT R6.H BY R5.L (S); +R7.H = ASHIFT R7.H BY R5.L (S); +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x08000000; +CHECKREG r2, 0x10010000; +CHECKREG r3, 0x18010000; +CHECKREG r4, 0x20020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0x30030000; +CHECKREG r7, 0x38030000; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +R6.L = -15; +imm32 r7, 0x70070000; +R0.L = ASHIFT R0.H BY R6.L (S); +R1.L = ASHIFT R1.H BY R6.L (S); +R2.L = ASHIFT R2.H BY R6.L (S); +R3.L = ASHIFT R3.H BY R6.L (S); +R4.L = ASHIFT R4.H BY R6.L (S); +R5.L = ASHIFT R5.H BY R6.L (S); +//rl6 = ashift (rh6 by rl6); +R7.L = ASHIFT R7.H BY R6.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r2, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +R7.L = -16; +R0.H = ASHIFT R0.H BY R7.L (S); +R1.H = ASHIFT R1.H BY R7.L (S); +R2.H = ASHIFT R2.H BY R7.L (S); +R3.H = ASHIFT R3.H BY R7.L (S); +R4.H = ASHIFT R4.H BY R7.L (S); +R5.H = ASHIFT R5.H BY R7.L (S); +R6.H = ASHIFT R6.H BY R7.L (S); +//rh7 = ashift (rh7 by rl7); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +//CHECKREG r7, -16; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahh.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahh.s new file mode 100644 index 0000000..2051cf9 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_ahh.s @@ -0,0 +1,430 @@ +//Original:/testcases/core/c_dsp32shift_ahh/c_dsp32shift_ahh.dsp +// Spec Reference: dsp32shift ashift/ashift +# mach: bfin + +.include "testutils.inc" + start + + + +// ashift/ashift : positive data, count (+)=left (half reg) +// d_reg = ashift/ashift (d BY d_lo) +// Rx by RLx +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5 = ASHIFT R0 BY R0.L (V); +R0 = ASHIFT R1 BY R0.L (V); +R1 = ASHIFT R2 BY R0.L (V); +R2 = ASHIFT R3 BY R0.L (V); +R3 = ASHIFT R4 BY R0.L (V); +R4 = ASHIFT R5 BY R0.L (V); +R7 = ASHIFT R6 BY R0.L (V); +R6 = ASHIFT R7 BY R0.L (V); +CHECKREG r0, 0x12345678; +CHECKREG r1, 0x00230067; +CHECKREG r2, 0x00340078; +CHECKREG r3, 0x0045FF89; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x01230000; +CHECKREG r6, 0x0000FFFF; +CHECKREG r7, 0x0067FFAB; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1.L = 5; +R2 = ASHIFT R0 BY R1.L (V); +R3 = ASHIFT R1 BY R1.L (V); +R4 = ASHIFT R2 BY R1.L (V); +R5 = ASHIFT R3 BY R1.L (V); +R6 = ASHIFT R4 BY R1.L (V); +R7 = ASHIFT R5 BY R1.L (V); +R0 = ASHIFT R6 BY R1.L (V); +R1 = ASHIFT R7 BY R1.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x24600040; +CHECKREG r3, 0x468000A0; +CHECKREG r4, 0x8C000800; +CHECKREG r5, 0xD0001400; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2 = 15; +R3 = ASHIFT R0 BY R2.L (V); +R4 = ASHIFT R1 BY R2.L (V); +R5 = ASHIFT R2 BY R2.L (V); +R6 = ASHIFT R3 BY R2.L (V); +R7 = ASHIFT R4 BY R2.L (V); +R0 = ASHIFT R5 BY R2.L (V); +R1 = ASHIFT R6 BY R2.L (V); +R2 = ASHIFT R7 BY R2.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R3.L = 16; +R4 = ASHIFT R0 BY R3.L (V); +R5 = ASHIFT R1 BY R3.L (V); +R6 = ASHIFT R2 BY R3.L (V); +R7 = ASHIFT R3 BY R3.L (V); +R0 = ASHIFT R4 BY R3.L (V); +R1 = ASHIFT R5 BY R3.L (V); +R2 = ASHIFT R6 BY R3.L (V); +R3 = ASHIFT R7 BY R3.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R4.L = -1; +R0 = ASHIFT R0 BY R4.L (V); +R1 = ASHIFT R1 BY R4.L (V); +R2 = ASHIFT R2 BY R4.L (V); +R3 = ASHIFT R3 BY R4.L (V); +R4 = ASHIFT R4 BY R4.L (V); +R5 = ASHIFT R5 BY R4.L (V); +R6 = ASHIFT R6 BY R4.L (V); +R7 = ASHIFT R7 BY R4.L (V); +CHECKREG r0, 0x00910001; +CHECKREG r1, 0x091A2B3C; +CHECKREG r2, 0x11A233C4; +CHECKREG r3, 0x1A2B3C4D; +CHECKREG r4, 0x22B3FFFF; +CHECKREG r5, 0x2B3CCD5E; +CHECKREG r6, 0x33C4D5E6; +CHECKREG r7, 0x3C4DDE6F; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5.L = -6; +R6 = ASHIFT R0 BY R5.L (V); +R7 = ASHIFT R1 BY R5.L (V); +R0 = ASHIFT R2 BY R5.L (V); +R1 = ASHIFT R3 BY R5.L (V); +R2 = ASHIFT R4 BY R5.L (V); +R3 = ASHIFT R5 BY R5.L (V); +R4 = ASHIFT R6 BY R5.L (V); +R5 = ASHIFT R7 BY R5.L (V); +CHECKREG r0, 0x008D019E; +CHECKREG r1, 0x00D101E2; +CHECKREG r2, 0x0115FE26; +CHECKREG r3, 0x0159FFFF; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00010005; +CHECKREG r6, 0x00040000; +CHECKREG r7, 0x00480159; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R6.L = -15; +R7 = ASHIFT R0 BY R6.L (V); +R0 = ASHIFT R1 BY R6.L (V); +R1 = ASHIFT R2 BY R6.L (V); +R2 = ASHIFT R3 BY R6.L (V); +R3 = ASHIFT R4 BY R6.L (V); +R4 = ASHIFT R5 BY R6.L (V); +R5 = ASHIFT R6 BY R6.L (V); +R6 = ASHIFT R7 BY R6.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x0000FFFF; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7.L = -16; +R0 = ASHIFT R0 BY R7.L (V); +R1 = ASHIFT R1 BY R7.L (V); +R2 = ASHIFT R2 BY R7.L (V); +R3 = ASHIFT R3 BY R7.L (V); +R4 = ASHIFT R4 BY R7.L (V); +R5 = ASHIFT R5 BY R7.L (V); +R6 = ASHIFT R6 BY R7.L (V); +R7 = ASHIFT R7 BY R7.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x0000FFFF; +CHECKREG r7, 0x0000FFFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0.L = 4; +//r0 = ashift/ashift (r0 by rl0); +R1 = ASHIFT R1 BY R0.L (V); +R2 = ASHIFT R2 BY R0.L (V); +R3 = ASHIFT R3 BY R0.L (V); +R4 = ASHIFT R4 BY R0.L (V); +R5 = ASHIFT R5 BY R0.L (V); +R6 = ASHIFT R6 BY R0.L (V); +R7 = ASHIFT R7 BY R0.L (V); +CHECKREG r0, 0x01230004; +CHECKREG r1, 0x23406780; +CHECKREG r2, 0x34507890; +CHECKREG r3, 0x456089A0; +CHECKREG r4, 0x56709AB0; +CHECKREG r5, 0x6780ABC0; +CHECKREG r6, 0x7890BCD0; +CHECKREG r7, 0x89A0CDE0; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1.L = 6; +R0 = ASHIFT R0 BY R1.L (V); +//r1 = ashift/ashift (r1 by rl1); +R2 = ASHIFT R2 BY R1.L (V); +R3 = ASHIFT R3 BY R1.L (V); +R4 = ASHIFT R4 BY R1.L (V); +R5 = ASHIFT R5 BY R1.L (V); +R6 = ASHIFT R6 BY R1.L (V); +R7 = ASHIFT R7 BY R1.L (V); +CHECKREG r0, 0x48C00080; +CHECKREG r1, 0x12340006; +CHECKREG r2, 0xD140E240; +CHECKREG r3, 0x15802680; +CHECKREG r4, 0x59C06AC0; +CHECKREG r5, 0x9E00AF00; +CHECKREG r6, 0xE240F340; +CHECKREG r7, 0x26803780; + + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 15; +R0 = ASHIFT R0 BY R2.L (V); +R1 = ASHIFT R1 BY R2.L (V); +//r2 = ashift/ashift (r2 by rl2); +R3 = ASHIFT R3 BY R2.L (V); +R4 = ASHIFT R4 BY R2.L (V); +R5 = ASHIFT R5 BY R2.L (V); +R6 = ASHIFT R6 BY R2.L (V); +R7 = ASHIFT R7 BY R2.L (V); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x2345000F; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x80008000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x80008000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R3.L = 16; +R0 = ASHIFT R0 BY R3.L (V); +R1 = ASHIFT R1 BY R3.L (V); +R2 = ASHIFT R2 BY R3.L (V); +//r3 = ashift/ashift (r3 by rl3); +R4 = ASHIFT R4 BY R3.L (V); +R5 = ASHIFT R5 BY R3.L (V); +R6 = ASHIFT R6 BY R3.L (V); +R7 = ASHIFT R7 BY R3.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x34560010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R4.L = -9; +R0 = ASHIFT R0 BY R4.L (V); +R1 = ASHIFT R1 BY R4.L (V); +R2 = ASHIFT R2 BY R4.L (V); +R3 = ASHIFT R3 BY R4.L (V); +//r4 = ashift/ashift (r4 by rl4); +R5 = ASHIFT R5 BY R4.L (V); +R6 = ASHIFT R6 BY R4.L (V); +R7 = ASHIFT R7 BY R4.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0009002B; +CHECKREG r2, 0x00110033; +CHECKREG r3, 0x001A003C; +CHECKREG r4, 0x4567FFF7; +CHECKREG r5, 0x002BFFCD; +CHECKREG r6, 0x0033FFD5; +CHECKREG r7, 0x003CFFDE; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5.L = -14; +R0 = ASHIFT R0 BY R5.L (V); +R1 = ASHIFT R1 BY R5.L (V); +R2 = ASHIFT R2 BY R5.L (V); +R3 = ASHIFT R3 BY R5.L (V); +R4 = ASHIFT R4 BY R5.L (V); +//r5 = ashift/ashift (r5 by rl5); +R6 = ASHIFT R6 BY R5.L (V); +R7 = ASHIFT R7 BY R5.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x0001FFFE; +CHECKREG r5, 0x5678FFF2; +CHECKREG r6, 0x0001FFFE; +CHECKREG r7, 0x0001FFFE; + + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R6.L = -15; +R0 = ASHIFT R0 BY R6.L (V); +R1 = ASHIFT R1 BY R6.L (V); +R2 = ASHIFT R2 BY R6.L (V); +R3 = ASHIFT R3 BY R6.L (V); +R4 = ASHIFT R4 BY R6.L (V); +R5 = ASHIFT R5 BY R6.L (V); +//r6 = ashift/ashift (r6 by rl6); +R7 = ASHIFT R7 BY R6.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x6789FFF1; +CHECKREG r7, 0x0000FFFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7.L = -16; +R0 = ASHIFT R0 BY R7.L (V); +R1 = ASHIFT R1 BY R7.L (V); +R2 = ASHIFT R2 BY R7.L (V); +R3 = ASHIFT R3 BY R7.L (V); +R4 = ASHIFT R4 BY R7.L (V); +R5 = ASHIFT R5 BY R7.L (V); +R6 = ASHIFT R6 BY R7.L (V); +R7 = ASHIFT R7 BY R7.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ahh_s.s b/sim/testsuite/sim/bfin/c_dsp32shift_ahh_s.s new file mode 100644 index 0000000..b948e90 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_ahh_s.s @@ -0,0 +1,430 @@ +//Original:/testcases/core/c_dsp32shift_ahh_s/c_dsp32shift_ahh_s.dsp +// Spec Reference: dsp32shift ashift/ashift s +# mach: bfin + +.include "testutils.inc" + start + + + +// ashift/ashift s : positive data, count (+)=left (half reg) +// d_reg = ashift/ashift (d BY d_lo) saturation +// Rx by RLx +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5 = ASHIFT R0 BY R0.L (V , S); +R0 = ASHIFT R1 BY R0.L (V , S); +R1 = ASHIFT R2 BY R0.L (V , S); +R2 = ASHIFT R3 BY R0.L (V , S); +R3 = ASHIFT R4 BY R0.L (V , S); +R4 = ASHIFT R5 BY R0.L (V , S); +R7 = ASHIFT R6 BY R0.L (V , S); +R6 = ASHIFT R7 BY R0.L (V , S); +CHECKREG r0, 0x12345678; +CHECKREG r1, 0x00230067; +CHECKREG r2, 0x00340078; +CHECKREG r3, 0x0045FF89; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x01230000; +CHECKREG r6, 0x0000FFFF; +CHECKREG r7, 0x0067FFAB; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1.L = 5; +R2 = ASHIFT R0 BY R1.L (V , S); +R3 = ASHIFT R1 BY R1.L (V , S); +R4 = ASHIFT R2 BY R1.L (V , S); +R5 = ASHIFT R3 BY R1.L (V , S); +R6 = ASHIFT R4 BY R1.L (V , S); +R7 = ASHIFT R5 BY R1.L (V , S); +R0 = ASHIFT R6 BY R1.L (V , S); +R1 = ASHIFT R7 BY R1.L (V , S); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x24600040; +CHECKREG r3, 0x7FFF00A0; +CHECKREG r4, 0x7FFF0800; +CHECKREG r5, 0x7FFF1400; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2 = 15; +R3 = ASHIFT R0 BY R2.L (V , S); +R4 = ASHIFT R1 BY R2.L (V , S); +R5 = ASHIFT R2 BY R2.L (V , S); +R6 = ASHIFT R3 BY R2.L (V , S); +R7 = ASHIFT R4 BY R2.L (V , S); +R0 = ASHIFT R5 BY R2.L (V , S); +R1 = ASHIFT R6 BY R2.L (V , S); +R2 = ASHIFT R7 BY R2.L (V , S); +CHECKREG r0, 0x00007FFF; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x00007FFF; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R3.L = 16; +R4 = ASHIFT R0 BY R3.L (V , S); +R5 = ASHIFT R1 BY R3.L (V , S); +R6 = ASHIFT R2 BY R3.L (V , S); +R7 = ASHIFT R3 BY R3.L (V , S); +R0 = ASHIFT R4 BY R3.L (V , S); +R1 = ASHIFT R5 BY R3.L (V , S); +R2 = ASHIFT R6 BY R3.L (V , S); +R3 = ASHIFT R7 BY R3.L (V , S); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF7FFF; +CHECKREG r5, 0x7FFF7FFF; +CHECKREG r6, 0x7FFF7FFF; +CHECKREG r7, 0x7FFF7FFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R4.L = -1; +R0 = ASHIFT R0 BY R4.L (V , S); +R1 = ASHIFT R1 BY R4.L (V , S); +R2 = ASHIFT R2 BY R4.L (V , S); +R3 = ASHIFT R3 BY R4.L (V , S); +R4 = ASHIFT R4 BY R4.L (V , S); +R5 = ASHIFT R5 BY R4.L (V , S); +R6 = ASHIFT R6 BY R4.L (V , S); +R7 = ASHIFT R7 BY R4.L (V , S); +CHECKREG r0, 0x00910001; +CHECKREG r1, 0x091A2B3C; +CHECKREG r2, 0x11A233C4; +CHECKREG r3, 0x1A2B3C4D; +CHECKREG r4, 0x22B3FFFF; +CHECKREG r5, 0x2B3CCD5E; +CHECKREG r6, 0x33C4D5E6; +CHECKREG r7, 0x3C4DDE6F; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5.L = -6; +R6 = ASHIFT R0 BY R5.L (V , S); +R7 = ASHIFT R1 BY R5.L (V , S); +R0 = ASHIFT R2 BY R5.L (V , S); +R1 = ASHIFT R3 BY R5.L (V , S); +R2 = ASHIFT R4 BY R5.L (V , S); +R3 = ASHIFT R5 BY R5.L (V , S); +R4 = ASHIFT R6 BY R5.L (V , S); +R5 = ASHIFT R7 BY R5.L (V , S); +CHECKREG r0, 0x008D019E; +CHECKREG r1, 0x00D101E2; +CHECKREG r2, 0x0115FE26; +CHECKREG r3, 0x0159FFFF; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00010005; +CHECKREG r6, 0x00040000; +CHECKREG r7, 0x00480159; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R6.L = -15; +R7 = ASHIFT R0 BY R6.L (V , S); +R0 = ASHIFT R1 BY R6.L (V , S); +R1 = ASHIFT R2 BY R6.L (V , S); +R2 = ASHIFT R3 BY R6.L (V , S); +R3 = ASHIFT R4 BY R6.L (V , S); +R4 = ASHIFT R5 BY R6.L (V , S); +R5 = ASHIFT R6 BY R6.L (V , S); +R6 = ASHIFT R7 BY R6.L (V , S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x0000FFFF; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7.L = -16; +R0 = ASHIFT R0 BY R7.L (V , S); +R1 = ASHIFT R1 BY R7.L (V , S); +R2 = ASHIFT R2 BY R7.L (V , S); +R3 = ASHIFT R3 BY R7.L (V , S); +R4 = ASHIFT R4 BY R7.L (V , S); +R5 = ASHIFT R5 BY R7.L (V , S); +R6 = ASHIFT R6 BY R7.L (V , S); +R7 = ASHIFT R7 BY R7.L (V , S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x0000FFFF; +CHECKREG r7, 0x0000FFFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0.L = 4; +//r0 = ashift/ashift (r0 by rl0); +R1 = ASHIFT R1 BY R0.L (V , S); +R2 = ASHIFT R2 BY R0.L (V , S); +R3 = ASHIFT R3 BY R0.L (V , S); +R4 = ASHIFT R4 BY R0.L (V , S); +R5 = ASHIFT R5 BY R0.L (V , S); +R6 = ASHIFT R6 BY R0.L (V , S); +R7 = ASHIFT R7 BY R0.L (V , S); +CHECKREG r0, 0x01230004; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF8000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1.L = 6; +R0 = ASHIFT R0 BY R1.L (V , S); +//r1 = ashift/ashift (r1 by rl1); +R2 = ASHIFT R2 BY R1.L (V , S); +R3 = ASHIFT R3 BY R1.L (V , S); +R4 = ASHIFT R4 BY R1.L (V , S); +R5 = ASHIFT R5 BY R1.L (V , S); +R6 = ASHIFT R6 BY R1.L (V , S); +R7 = ASHIFT R7 BY R1.L (V , S); +CHECKREG r0, 0x48C00080; +CHECKREG r1, 0x12340006; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF8000; + + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 15; +R0 = ASHIFT R0 BY R2.L (V , S); +R1 = ASHIFT R1 BY R2.L (V , S); +//r2 = ashift/ashift (r2 by rl2) s; +R3 = ASHIFT R3 BY R2.L (V , S); +R4 = ASHIFT R4 BY R2.L (V , S); +R5 = ASHIFT R5 BY R2.L (V , S); +R6 = ASHIFT R6 BY R2.L (V , S); +R7 = ASHIFT R7 BY R2.L (V , S); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x2345000F; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF8000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R3.L = 16; +R0 = ASHIFT R0 BY R3.L (V , S); +R1 = ASHIFT R1 BY R3.L (V , S); +R2 = ASHIFT R2 BY R3.L (V , S); +//r3 = ashift/ashift (r3 by rl3) s; +R4 = ASHIFT R4 BY R3.L (V , S); +R5 = ASHIFT R5 BY R3.L (V , S); +R6 = ASHIFT R6 BY R3.L (V , S); +R7 = ASHIFT R7 BY R3.L (V , S); +CHECKREG r0, 0x7FFF7FFF; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x34560010; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF8000; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R4.L = -9; +R0 = ASHIFT R0 BY R4.L (V , S); +R1 = ASHIFT R1 BY R4.L (V , S); +R2 = ASHIFT R2 BY R4.L (V , S); +R3 = ASHIFT R3 BY R4.L (V , S); +//r4 = ashift/ashift (r4 by rl4) s; +R5 = ASHIFT R5 BY R4.L (V , S); +R6 = ASHIFT R6 BY R4.L (V , S); +R7 = ASHIFT R7 BY R4.L (V , S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0009002B; +CHECKREG r2, 0x00110033; +CHECKREG r3, 0x001A003C; +CHECKREG r4, 0x4567FFF7; +CHECKREG r5, 0x002BFFCD; +CHECKREG r6, 0x0033FFD5; +CHECKREG r7, 0x003CFFDE; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5.L = -14; +R0 = ASHIFT R0 BY R5.L (V , S); +R1 = ASHIFT R1 BY R5.L (V , S); +R2 = ASHIFT R2 BY R5.L (V , S); +R3 = ASHIFT R3 BY R5.L (V , S); +R4 = ASHIFT R4 BY R5.L (V , S); +//r5 = ashift/ashift (r5 by rl5) s; +R6 = ASHIFT R6 BY R5.L (V , S); +R7 = ASHIFT R7 BY R5.L (V , S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x0001FFFE; +CHECKREG r5, 0x5678FFF2; +CHECKREG r6, 0x0001FFFE; +CHECKREG r7, 0x0001FFFE; + + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R6.L = -15; +R0 = ASHIFT R0 BY R6.L (V , S); +R1 = ASHIFT R1 BY R6.L (V , S); +R2 = ASHIFT R2 BY R6.L (V , S); +R3 = ASHIFT R3 BY R6.L (V , S); +R4 = ASHIFT R4 BY R6.L (V , S); +R5 = ASHIFT R5 BY R6.L (V , S); +//r6 = ashift/ashift (r6 by rl6) s; +R7 = ASHIFT R7 BY R6.L (V , S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x6789FFF1; +CHECKREG r7, 0x0000FFFF; + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7.L = -16; +R0 = ASHIFT R0 BY R7.L (V , S); +R1 = ASHIFT R1 BY R7.L (V , S); +R2 = ASHIFT R2 BY R7.L (V , S); +R3 = ASHIFT R3 BY R7.L (V , S); +R4 = ASHIFT R4 BY R7.L (V , S); +R5 = ASHIFT R5 BY R7.L (V , S); +R6 = ASHIFT R6 BY R7.L (V , S); +R7 = ASHIFT R7 BY R7.L (V , S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x0000ffff; +CHECKREG r5, 0x0000ffff; +CHECKREG r6, 0x0000ffff; +CHECKREG r7, 0x0000ffff; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_align16.s b/sim/testsuite/sim/bfin/c_dsp32shift_align16.s new file mode 100644 index 0000000..a6fd284 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_align16.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_align16/c_dsp32shift_align16.dsp +// Spec Reference: dsp32shift align16 +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = ALIGN16 ( R1 , R0 ); +R2 = ALIGN16 ( R2 , R0 ); +R3 = ALIGN16 ( R3 , R0 ); +R4 = ALIGN16 ( R4 , R0 ); +R5 = ALIGN16 ( R5 , R0 ); +R6 = ALIGN16 ( R6 , R0 ); +R7 = ALIGN16 ( R7 , R0 ); +R0 = ALIGN16 ( R0 , R0 ); +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x08010000; +CHECKREG r2, 0x08020000; +CHECKREG r3, 0x08030000; +CHECKREG r4, 0x48040000; +CHECKREG r5, 0x05050000; +CHECKREG r6, 0x08660000; +CHECKREG r7, 0x08070000; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09400002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = ALIGN16 ( R0 , R1 ); +R2 = ALIGN16 ( R2 , R1 ); +R3 = ALIGN16 ( R3 , R1 ); +R4 = ALIGN16 ( R4 , R1 ); +R5 = ALIGN16 ( R5 , R1 ); +R6 = ALIGN16 ( R6 , R1 ); +R7 = ALIGN16 ( R7 , R1 ); +R1 = ALIGN16 ( R1 , R1 ); +CHECKREG r0, 0xD0010900; +CHECKREG r1, 0x00020900; +CHECKREG r2, 0x00020900; +CHECKREG r3, 0x00030900; +CHECKREG r4, 0x00040900; +CHECKREG r5, 0x30050900; +CHECKREG r6, 0x04060900; +CHECKREG r7, 0x00570900; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a400010; +imm32 r4, 0x0a05e004; +imm32 r5, 0x0a006005; +imm32 r6, 0x0a00e706; +imm32 r7, 0x0a00e087; +R0 = ALIGN16 ( R0 , R2 ); +R1 = ALIGN16 ( R1 , R2 ); +R3 = ALIGN16 ( R3 , R2 ); +R4 = ALIGN16 ( R4 , R2 ); +R5 = ALIGN16 ( R5 , R2 ); +R6 = ALIGN16 ( R6 , R2 ); +R7 = ALIGN16 ( R7 , R2 ); +R2 = ALIGN16 ( R2 , R2 ); +CHECKREG r0, 0xE0010A00; +CHECKREG r1, 0xE0010A00; +CHECKREG r2, 0x000F0A00; +CHECKREG r3, 0x00100A00; +CHECKREG r4, 0xE0040A00; +CHECKREG r5, 0x60050A00; +CHECKREG r6, 0xE7060A00; +CHECKREG r7, 0xE0870A00; + +imm32 r0, 0x2b00f001; +imm32 r1, 0x0300f001; +imm32 r2, 0x0b40f002; +imm32 r3, 0x0b050010; +imm32 r4, 0x0b006004; +imm32 r5, 0x0b00f705; +imm32 r6, 0x0b00f086; +imm32 r7, 0x0b00f009; +R0 = ALIGN16 ( R0 , R3 ); +R1 = ALIGN16 ( R1 , R3 ); +R2 = ALIGN16 ( R2 , R3 ); +R4 = ALIGN16 ( R4 , R3 ); +R5 = ALIGN16 ( R5 , R3 ); +R6 = ALIGN16 ( R6 , R3 ); +R7 = ALIGN16 ( R7 , R3 ); +R3 = ALIGN16 ( R3 , R3 ); +CHECKREG r0, 0xF0010B05; +CHECKREG r1, 0xF0010B05; +CHECKREG r2, 0xF0020B05; +CHECKREG r3, 0x00100B05; +CHECKREG r4, 0x60040B05; +CHECKREG r5, 0xF7050B05; +CHECKREG r6, 0xF0860B05; +CHECKREG r7, 0xF0090B05; + +imm32 r0, 0x4c0000c0; +imm32 r1, 0x050100c0; +imm32 r2, 0x0c6200c0; +imm32 r3, 0x0c0700c0; +imm32 r4, 0x0c04800c; +imm32 r5, 0x0c0509c0; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c0700ca; +R0 = ALIGN16 ( R0 , R4 ); +R1 = ALIGN16 ( R1 , R4 ); +R2 = ALIGN16 ( R2 , R4 ); +R3 = ALIGN16 ( R3 , R4 ); +R5 = ALIGN16 ( R5 , R4 ); +R6 = ALIGN16 ( R6 , R4 ); +R7 = ALIGN16 ( R7 , R4 ); +R4 = ALIGN16 ( R4 , R4 ); +CHECKREG r0, 0x00C00C04; +CHECKREG r1, 0x00C00C04; +CHECKREG r2, 0x00C00C04; +CHECKREG r3, 0x00C00C04; +CHECKREG r4, 0x800C0C04; +CHECKREG r5, 0x09C00C04; +CHECKREG r6, 0x00000C04; +CHECKREG r7, 0x00CA0C04; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = ALIGN16 ( R0 , R5 ); +R1 = ALIGN16 ( R1 , R5 ); +R2 = ALIGN16 ( R2 , R5 ); +R3 = ALIGN16 ( R3 , R5 ); +R4 = ALIGN16 ( R4 , R5 ); +R6 = ALIGN16 ( R6 , R5 ); +R7 = ALIGN16 ( R7 , R5 ); +R5 = ALIGN16 ( R5 , R5 ); +CHECKREG r0, 0x00D0A005; +CHECKREG r1, 0x00D1A005; +CHECKREG r2, 0x00D0A005; +CHECKREG r3, 0x00D0A005; +CHECKREG r4, 0x00D0A005; +CHECKREG r5, 0x0007A005; +CHECKREG r6, 0x00D0A005; +CHECKREG r7, 0x00D0A005; + +imm32 r0, 0xb2010000; +imm32 r1, 0xb0310000; +imm32 r2, 0xb042000f; +imm32 r3, 0xbf030000; +imm32 r4, 0xba040000; +imm32 r5, 0xbb050000; +imm32 r6, 0xbc060009; +imm32 r7, 0xb0e70000; +R0 = ALIGN16 ( R0 , R6 ); +R1 = ALIGN16 ( R1 , R6 ); +R2 = ALIGN16 ( R2 , R6 ); +R3 = ALIGN16 ( R3 , R6 ); +R4 = ALIGN16 ( R4 , R6 ); +R5 = ALIGN16 ( R5 , R6 ); +R6 = ALIGN16 ( R6 , R6 ); +R7 = ALIGN16 ( R7 , R6 ); +CHECKREG r0, 0x0000BC06; +CHECKREG r1, 0x0000BC06; +CHECKREG r2, 0x000FBC06; +CHECKREG r3, 0x0000BC06; +CHECKREG r4, 0x0000BC06; +CHECKREG r5, 0x0000BC06; +CHECKREG r6, 0x0009BC06; +CHECKREG r7, 0x00000009; + +imm32 r0, 0xd23100e0; +imm32 r1, 0xd04500e0; +imm32 r2, 0xde32f0e0; +imm32 r3, 0xd90300e0; +imm32 r4, 0xd07400e0; +imm32 r5, 0xdef500e0; +imm32 r6, 0xd06600e0; +imm32 r7, 0xd0080023; +R1 = ALIGN16 ( R0 , R7 ); +R2 = ALIGN16 ( R1 , R7 ); +R3 = ALIGN16 ( R2 , R7 ); +R4 = ALIGN16 ( R3 , R7 ); +R5 = ALIGN16 ( R4 , R7 ); +R6 = ALIGN16 ( R5 , R7 ); +R7 = ALIGN16 ( R6 , R7 ); +R0 = ALIGN16 ( R7 , R7 ); +CHECKREG r0, 0xD008D008; +CHECKREG r1, 0x00E0D008; +CHECKREG r2, 0xD008D008; +CHECKREG r3, 0xD008D008; +CHECKREG r4, 0xD008D008; +CHECKREG r5, 0xD008D008; +CHECKREG r6, 0xD008D008; +CHECKREG r7, 0xD008D008; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_align24.s b/sim/testsuite/sim/bfin/c_dsp32shift_align24.s new file mode 100644 index 0000000..bc33c58 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_align24.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_align24/c_dsp32shift_align24.dsp +// Spec Reference: dsp32shift align24 +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = ALIGN24 ( R1 , R0 ); +R2 = ALIGN24 ( R2 , R0 ); +R3 = ALIGN24 ( R3 , R0 ); +R4 = ALIGN24 ( R4 , R0 ); +R5 = ALIGN24 ( R5 , R0 ); +R6 = ALIGN24 ( R6 , R0 ); +R7 = ALIGN24 ( R7 , R0 ); +R0 = ALIGN24 ( R0 , R0 ); +CHECKREG r0, 0x00000100; +CHECKREG r1, 0x00080100; +CHECKREG r2, 0x20080200; +CHECKREG r3, 0x03080300; +CHECKREG r4, 0x00480400; +CHECKREG r5, 0x00050500; +CHECKREG r6, 0x00086600; +CHECKREG r7, 0x00080700; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09400002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = ALIGN24 ( R0 , R1 ); +R2 = ALIGN24 ( R2 , R1 ); +R3 = ALIGN24 ( R3 , R1 ); +R4 = ALIGN24 ( R4 , R1 ); +R5 = ALIGN24 ( R5 , R1 ); +R6 = ALIGN24 ( R6 , R1 ); +R7 = ALIGN24 ( R7 , R1 ); +R1 = ALIGN24 ( R1 , R1 ); +CHECKREG r0, 0x00D00109; +CHECKREG r1, 0x00000209; +CHECKREG r2, 0x40000209; +CHECKREG r3, 0x10000309; +CHECKREG r4, 0x02000409; +CHECKREG r5, 0x00300509; +CHECKREG r6, 0x00040609; +CHECKREG r7, 0x00005709; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a400010; +imm32 r4, 0x0a05e004; +imm32 r5, 0x0a006005; +imm32 r6, 0x0a00e706; +imm32 r7, 0x0a00e087; +R0 = ALIGN24 ( R0 , R2 ); +R1 = ALIGN24 ( R1 , R2 ); +R3 = ALIGN24 ( R3 , R2 ); +R4 = ALIGN24 ( R4 , R2 ); +R5 = ALIGN24 ( R5 , R2 ); +R6 = ALIGN24 ( R6 , R2 ); +R7 = ALIGN24 ( R7 , R2 ); +R2 = ALIGN24 ( R2 , R2 ); +CHECKREG r0, 0x00E0010A; +CHECKREG r1, 0x00E0010A; +CHECKREG r2, 0x00000F0A; +CHECKREG r3, 0x4000100A; +CHECKREG r4, 0x05E0040A; +CHECKREG r5, 0x0060050A; +CHECKREG r6, 0x00E7060A; +CHECKREG r7, 0x00E0870A; + +imm32 r0, 0x2b00f001; +imm32 r1, 0x0300f001; +imm32 r2, 0x0b40f002; +imm32 r3, 0x0b050010; +imm32 r4, 0x0b006004; +imm32 r5, 0x0b00f705; +imm32 r6, 0x0b00f086; +imm32 r7, 0x0b00f009; +R0 = ALIGN24 ( R0 , R3 ); +R1 = ALIGN24 ( R1 , R3 ); +R2 = ALIGN24 ( R2 , R3 ); +R4 = ALIGN24 ( R4 , R3 ); +R5 = ALIGN24 ( R5 , R3 ); +R6 = ALIGN24 ( R6 , R3 ); +R7 = ALIGN24 ( R7 , R3 ); +R3 = ALIGN24 ( R3 , R3 ); +CHECKREG r0, 0x00F0010B; +CHECKREG r1, 0x00F0010B; +CHECKREG r2, 0x40F0020B; +CHECKREG r3, 0x0500100B; +CHECKREG r4, 0x0060040B; +CHECKREG r5, 0x00F7050B; +CHECKREG r6, 0x00F0860B; +CHECKREG r7, 0x00F0090B; + +imm32 r0, 0x4c0000c0; +imm32 r1, 0x050100c0; +imm32 r2, 0x0c6200c0; +imm32 r3, 0x0c0700c0; +imm32 r4, 0x0c04800c; +imm32 r5, 0x0c0509c0; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c0700ca; +R0 = ALIGN24 ( R0 , R4 ); +R1 = ALIGN24 ( R1 , R4 ); +R2 = ALIGN24 ( R2 , R4 ); +R3 = ALIGN24 ( R3 , R4 ); +R5 = ALIGN24 ( R5 , R4 ); +R6 = ALIGN24 ( R6 , R4 ); +R7 = ALIGN24 ( R7 , R4 ); +R4 = ALIGN24 ( R4 , R4 ); +CHECKREG r0, 0x0000C00C; +CHECKREG r1, 0x0100C00C; +CHECKREG r2, 0x6200C00C; +CHECKREG r3, 0x0700C00C; +CHECKREG r4, 0x04800C0C; +CHECKREG r5, 0x0509C00C; +CHECKREG r6, 0x0600000C; +CHECKREG r7, 0x0700CA0C; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = ALIGN24 ( R0 , R5 ); +R1 = ALIGN24 ( R1 , R5 ); +R2 = ALIGN24 ( R2 , R5 ); +R3 = ALIGN24 ( R3 , R5 ); +R4 = ALIGN24 ( R4 , R5 ); +R6 = ALIGN24 ( R6 , R5 ); +R7 = ALIGN24 ( R7 , R5 ); +R5 = ALIGN24 ( R5 , R5 ); +CHECKREG r0, 0x0100D0A0; +CHECKREG r1, 0x0100D1A0; +CHECKREG r2, 0x0200D0A0; +CHECKREG r3, 0x0300D0A0; +CHECKREG r4, 0x0400D0A0; +CHECKREG r5, 0x050007A0; +CHECKREG r6, 0x0600D0A0; +CHECKREG r7, 0x0700D0A0; + +imm32 r0, 0xb2010000; +imm32 r1, 0xb0310000; +imm32 r2, 0xb042000f; +imm32 r3, 0xbf030000; +imm32 r4, 0xba040000; +imm32 r5, 0xbb050000; +imm32 r6, 0xbc060009; +imm32 r7, 0xb0e70000; +R0 = ALIGN24 ( R0 , R6 ); +R1 = ALIGN24 ( R1 , R6 ); +R2 = ALIGN24 ( R2 , R6 ); +R3 = ALIGN24 ( R3 , R6 ); +R4 = ALIGN24 ( R4 , R6 ); +R5 = ALIGN24 ( R5 , R6 ); +R6 = ALIGN24 ( R6 , R6 ); +R7 = ALIGN24 ( R7 , R6 ); +CHECKREG r0, 0x010000BC; +CHECKREG r1, 0x310000BC; +CHECKREG r2, 0x42000FBC; +CHECKREG r3, 0x030000BC; +CHECKREG r4, 0x040000BC; +CHECKREG r5, 0x050000BC; +CHECKREG r6, 0x060009BC; +CHECKREG r7, 0xE7000006; + +imm32 r0, 0xd23100e0; +imm32 r1, 0xd04500e0; +imm32 r2, 0xde32f0e0; +imm32 r3, 0xd90300e0; +imm32 r4, 0xd07400e0; +imm32 r5, 0xdef500e0; +imm32 r6, 0xd06600e0; +imm32 r7, 0xd0080023; +R1 = ALIGN24 ( R0 , R7 ); +R2 = ALIGN24 ( R1 , R7 ); +R3 = ALIGN24 ( R2 , R7 ); +R4 = ALIGN24 ( R3 , R7 ); +R5 = ALIGN24 ( R4 , R7 ); +R6 = ALIGN24 ( R5 , R7 ); +R7 = ALIGN24 ( R6 , R7 ); +R0 = ALIGN24 ( R7 , R7 ); +CHECKREG r0, 0xD0D0D0D0; +CHECKREG r1, 0x3100E0D0; +CHECKREG r2, 0x00E0D0D0; +CHECKREG r3, 0xE0D0D0D0; +CHECKREG r4, 0xD0D0D0D0; +CHECKREG r5, 0xD0D0D0D0; +CHECKREG r6, 0xD0D0D0D0; +CHECKREG r7, 0xD0D0D0D0; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_align8.s b/sim/testsuite/sim/bfin/c_dsp32shift_align8.s new file mode 100644 index 0000000..ce1f82b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_align8.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_align8/c_dsp32shift_align8.dsp +// Spec Reference: dsp32shift align8 +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = ALIGN8 ( R1 , R0 ); +R2 = ALIGN8 ( R2 , R0 ); +R3 = ALIGN8 ( R3 , R0 ); +R4 = ALIGN8 ( R4 , R0 ); +R5 = ALIGN8 ( R5 , R0 ); +R6 = ALIGN8 ( R6 , R0 ); +R7 = ALIGN8 ( R7 , R0 ); +R0 = ALIGN8 ( R0 , R0 ); +CHECKREG r0, 0x01000000; +CHECKREG r1, 0x01000000; +CHECKREG r2, 0x02000000; +CHECKREG r3, 0x03000000; +CHECKREG r4, 0x04000000; +CHECKREG r5, 0x05000000; +CHECKREG r6, 0x66000000; +CHECKREG r7, 0x07000000; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09400002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = ALIGN8 ( R0 , R1 ); +R2 = ALIGN8 ( R2 , R1 ); +R3 = ALIGN8 ( R3 , R1 ); +R4 = ALIGN8 ( R4 , R1 ); +R5 = ALIGN8 ( R5 , R1 ); +R6 = ALIGN8 ( R6 , R1 ); +R7 = ALIGN8 ( R7 , R1 ); +R1 = ALIGN8 ( R1 , R1 ); +CHECKREG r0, 0x01090000; +CHECKREG r1, 0x02090000; +CHECKREG r2, 0x02090000; +CHECKREG r3, 0x03090000; +CHECKREG r4, 0x04090000; +CHECKREG r5, 0x05090000; +CHECKREG r6, 0x06090000; +CHECKREG r7, 0x57090000; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a400010; +imm32 r4, 0x0a05e004; +imm32 r5, 0x0a006005; +imm32 r6, 0x0a00e706; +imm32 r7, 0x0a00e087; +R0 = ALIGN8 ( R0 , R2 ); +R1 = ALIGN8 ( R1 , R2 ); +R3 = ALIGN8 ( R3 , R2 ); +R4 = ALIGN8 ( R4 , R2 ); +R5 = ALIGN8 ( R5 , R2 ); +R6 = ALIGN8 ( R6 , R2 ); +R7 = ALIGN8 ( R7 , R2 ); +R2 = ALIGN8 ( R2 , R2 ); +CHECKREG r0, 0x010A0000; +CHECKREG r1, 0x010A0000; +CHECKREG r2, 0x0F0A0000; +CHECKREG r3, 0x100A0000; +CHECKREG r4, 0x040A0000; +CHECKREG r5, 0x050A0000; +CHECKREG r6, 0x060A0000; +CHECKREG r7, 0x870A0000; + +imm32 r0, 0x2b00f001; +imm32 r1, 0x0300f001; +imm32 r2, 0x0b40f002; +imm32 r3, 0x0b050010; +imm32 r4, 0x0b006004; +imm32 r5, 0x0b00f705; +imm32 r6, 0x0b00f086; +imm32 r7, 0x0b00f009; +R0 = ALIGN8 ( R0 , R3 ); +R1 = ALIGN8 ( R1 , R3 ); +R2 = ALIGN8 ( R2 , R3 ); +R4 = ALIGN8 ( R4 , R3 ); +R5 = ALIGN8 ( R5 , R3 ); +R6 = ALIGN8 ( R6 , R3 ); +R7 = ALIGN8 ( R7 , R3 ); +R3 = ALIGN8 ( R3 , R3 ); +CHECKREG r0, 0x010B0500; +CHECKREG r1, 0x010B0500; +CHECKREG r2, 0x020B0500; +CHECKREG r3, 0x100B0500; +CHECKREG r4, 0x040B0500; +CHECKREG r5, 0x050B0500; +CHECKREG r6, 0x860B0500; +CHECKREG r7, 0x090B0500; + +imm32 r0, 0x4c0000c0; +imm32 r1, 0x050100c0; +imm32 r2, 0x0c6200c0; +imm32 r3, 0x0c0700c0; +imm32 r4, 0x0c04800c; +imm32 r5, 0x0c0509c0; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c0700ca; +R0 = ALIGN8 ( R0 , R4 ); +R1 = ALIGN8 ( R1 , R4 ); +R2 = ALIGN8 ( R2 , R4 ); +R3 = ALIGN8 ( R3 , R4 ); +R5 = ALIGN8 ( R5 , R4 ); +R6 = ALIGN8 ( R6 , R4 ); +R7 = ALIGN8 ( R7 , R4 ); +R4 = ALIGN8 ( R4 , R4 ); +CHECKREG r0, 0xC00C0480; +CHECKREG r1, 0xC00C0480; +CHECKREG r2, 0xC00C0480; +CHECKREG r3, 0xC00C0480; +CHECKREG r4, 0x0C0C0480; +CHECKREG r5, 0xC00C0480; +CHECKREG r6, 0x000C0480; +CHECKREG r7, 0xCA0C0480; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = ALIGN8 ( R0 , R5 ); +R1 = ALIGN8 ( R1 , R5 ); +R2 = ALIGN8 ( R2 , R5 ); +R3 = ALIGN8 ( R3 , R5 ); +R4 = ALIGN8 ( R4 , R5 ); +R6 = ALIGN8 ( R6 , R5 ); +R7 = ALIGN8 ( R7 , R5 ); +R5 = ALIGN8 ( R5 , R5 ); +CHECKREG r0, 0xD0A00500; +CHECKREG r1, 0xD1A00500; +CHECKREG r2, 0xD0A00500; +CHECKREG r3, 0xD0A00500; +CHECKREG r4, 0xD0A00500; +CHECKREG r5, 0x07A00500; +CHECKREG r6, 0xD0A00500; +CHECKREG r7, 0xD0A00500; + +imm32 r0, 0xb2010000; +imm32 r1, 0xb0310000; +imm32 r2, 0xb042000f; +imm32 r3, 0xbf030000; +imm32 r4, 0xba040000; +imm32 r5, 0xbb050000; +imm32 r6, 0xbc060009; +imm32 r7, 0xb0e70000; +R0 = ALIGN8 ( R0 , R6 ); +R1 = ALIGN8 ( R1 , R6 ); +R2 = ALIGN8 ( R2 , R6 ); +R3 = ALIGN8 ( R3 , R6 ); +R4 = ALIGN8 ( R4 , R6 ); +R5 = ALIGN8 ( R5 , R6 ); +R6 = ALIGN8 ( R6 , R6 ); +R7 = ALIGN8 ( R7 , R6 ); +CHECKREG r0, 0x00BC0600; +CHECKREG r1, 0x00BC0600; +CHECKREG r2, 0x0FBC0600; +CHECKREG r3, 0x00BC0600; +CHECKREG r4, 0x00BC0600; +CHECKREG r5, 0x00BC0600; +CHECKREG r6, 0x09BC0600; +CHECKREG r7, 0x0009BC06; + +imm32 r0, 0xd23100e0; +imm32 r1, 0xd04500e0; +imm32 r2, 0xde32f0e0; +imm32 r3, 0xd90300e0; +imm32 r4, 0xd07400e0; +imm32 r5, 0xdef500e0; +imm32 r6, 0xd06600e0; +imm32 r7, 0xd0080023; +R1 = ALIGN8 ( R0 , R7 ); +R2 = ALIGN8 ( R1 , R7 ); +R3 = ALIGN8 ( R2 , R7 ); +R4 = ALIGN8 ( R3 , R7 ); +R5 = ALIGN8 ( R4 , R7 ); +R6 = ALIGN8 ( R5 , R7 ); +R7 = ALIGN8 ( R6 , R7 ); +R0 = ALIGN8 ( R7 , R7 ); +CHECKREG r0, 0x0000D008; +CHECKREG r1, 0xE0D00800; +CHECKREG r2, 0x00D00800; +CHECKREG r3, 0x00D00800; +CHECKREG r4, 0x00D00800; +CHECKREG r5, 0x00D00800; +CHECKREG r6, 0x00D00800; +CHECKREG r7, 0x00D00800; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_amix.s b/sim/testsuite/sim/bfin/c_dsp32shift_amix.s new file mode 100644 index 0000000..af59e3f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_amix.s @@ -0,0 +1,142 @@ +//Original:/testcases/core/c_dsp32shift_amix/c_dsp32shift_amix.dsp +// Spec Reference: dsp32shift ashift mix +# mach: bfin + +.include "testutils.inc" + start + +// Ashift (Arithmetic ) retain the sign bit (0-->0, 1-->1) + +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// Ashift : positive data, count (+)=left (half reg) +imm32 r0, 0x00010001; +imm32 r1, 1; +imm32 r2, 0x00020002; +imm32 r3, 2; +R4.H = ASHIFT R0.H BY R1.L; +R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x00020002 */ +R5.H = ASHIFT R2.H BY R3.L; +R5.L = ASHIFT R2.L BY R3.L; /* r5 = 0x00080008 */ +R6 = ASHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */ +R7 = ASHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */ +CHECKREG r4, 0x00020002; +CHECKREG r5, 0x00080008; +CHECKREG r6, 0x00020002; +CHECKREG r7, 0x00080008; + +// Ashift : (full reg) +imm32 r1, 3; +imm32 r3, 4; +R6 = ASHIFT R0 BY R1.L; /* r6 = 0x00080010 */ +R7 = ASHIFT R2 BY R3.L; +CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ +CHECKREG r7, 0x00200020; + +A0 = 0; +A0.L = R0.L; +A0.H = R0.H; +A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00080008 */ +R5 = A0.w; /* r5 = 0x00080008 */ + +CHECKREG r5, 0x00080008; +imm32 r4, 0x30000003; +imm32 r1, 1; +R5 = ASHIFT R4 BY R1.L; /* r5 = 0x60000006 */ +CHECKREG r5, 0x60000006; +imm32 r1, 2; +R5 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */ +CHECKREG r5, 0xc000000c; + + +// Ashift : count (-)=right (half reg) +imm32 r0, 0x10001000; +imm32 r1, -1; +imm32 r2, 0x10001000; +imm32 r3, -2; +R4.H = ASHIFT R0.H BY R1.L; +R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x08000800 */ +R5.H = ASHIFT R2.H BY R3.L; +R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0x04000400 */ +R6 = ASHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */ +R7 = ASHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */ +CHECKREG r4, 0x08000800; +CHECKREG r5, 0x04000400; +CHECKREG r6, 0x08000800; +CHECKREG r7, 0x04000400; + +// Ashift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = ASHIFT R0 BY R1.L; /* r6 = 0x02000200 */ +R7 = ASHIFT R2 BY R3.L; /* r7 = 0x01000100 */ +CHECKREG r6, 0x02000200; +CHECKREG r7, 0x01000100; + +// NEGATIVE +// Ashift : NEGATIVE data, count (+)=left (half reg) +imm32 r0, 0xc00f800f; +imm32 r1, 1; +imm32 r2, 0xe00fe00f; +imm32 r3, 2; +R4.H = ASHIFT R0.H BY R1.L; +R4.L = ASHIFT R0.L BY R1.L (S); /* r4 = 0x801e801e */ +R5.H = ASHIFT R2.H BY R3.L; +R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0x803c803c */ +CHECKREG r4, 0x801e8000; +CHECKREG r5, 0x803c803c; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +imm32 r1, 4; +imm32 r3, 5; +R6 = ASHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */ +R7 = ASHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xf80fe00f; +imm32 r2, 0xfc0fe00f; +R6 = ASHIFT R0 BY R1.L (S); /* r6 = 0x80fe00f0 */ +R7 = ASHIFT R2 BY R3.L (S); /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +R6 = ASHIFT R0 BY R1.L (S); /* r6 = 0x80000000 zero bubble tru MSB */ +R7 = ASHIFT R2 BY R3.L (S); /* r7 = 0x80000000 */ +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + + +// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok +imm32 r0, 0x80f080f0; +imm32 r1, -1; +imm32 r2, 0x80f080f0; +imm32 r3, -2; +R4.H = ASHIFT R0.H BY R1.L; +R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0xc078c078 */ +R5.H = ASHIFT R2.H BY R3.L; +R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0xe03ce03c */ +CHECKREG r4, 0xc078c078; +CHECKREG r5, 0xe03ce03c; +R6 = ASHIFT R0 BY R1.L (V); /* r6 = 0xc078c078 */ +R7 = ASHIFT R2 BY R3.L (V); /* r7 = 0xe03ce03c */ +CHECKREG r6, 0xc078c078; +CHECKREG r7, 0xe03ce03c; + +// Ashift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = ASHIFT R0 BY R1.L; /* r6 = 0xf01e101e */ +R7 = ASHIFT R2 BY R3.L; /* r7 = 0xf80f080f */ +CHECKREG r6, 0xf01e101e; +CHECKREG r7, 0xf80f080f; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_bitmux.s b/sim/testsuite/sim/bfin/c_dsp32shift_bitmux.s new file mode 100644 index 0000000..d962b27 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_bitmux.s @@ -0,0 +1,486 @@ +//Original:/testcases/core/c_dsp32shift_bitmux/c_dsp32shift_bitmux.dsp +// Spec Reference: dsp32shift bitmux +# mach: bfin + + .include "testutils.inc" + + start + + A0 = 0; + imm32 r0, 0x01230000; + imm32 r1, 0x12340678; + imm32 r2, 0x23450089; + imm32 r3, 0x3456089a; + imm32 r4, 0x456709ab; + imm32 r5, 0x56780abc; + imm32 r6, 0x67890bcd; + imm32 r7, 0x789a0cde; +//r0, r0, a0 >>= bitmux; invalid now + BITMUX( R0 , R1, A0) (ASR); + BITMUX( R0 , R2, A0) (ASR); + BITMUX( R0 , R3, A0) (ASR); + BITMUX( R0 , R4, A0) (ASR); + BITMUX( R0 , R5, A0) (ASR); + BITMUX( R0 , R6, A0) (ASR); + BITMUX( R0 , R7, A0) (ASR); + CHECKREG r1, 0x091A033C; + CHECKREG r0, 0x00024600; + CHECKREG r2, 0x11A28044; + CHECKREG r3, 0x1A2B044D; + CHECKREG r4, 0x22B384D5; + CHECKREG r5, 0x2B3C055E; + CHECKREG r6, 0x33C485E6; + CHECKREG r7, 0x3C4D066F; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x20000000; + CHECKREG r1, 0x00000022; + + imm32 r0, 0x01231001; + imm32 r1, 0x12341678; + imm32 r2, 0x13451789; + imm32 r3, 0x1456189a; + imm32 r4, 0x156711ab; + imm32 r5, 0x16781abc; + imm32 r6, 0x17891bcd; + imm32 r7, 0x189a1cde; + BITMUX( R1 , R0, A0) (ASR); +//r1, r1, a0 >>= bitmux; + BITMUX( R1 , R2, A0) (ASR); + BITMUX( R1 , R3, A0) (ASR); + BITMUX( R1 , R4, A0) (ASR); + BITMUX( R1 , R5, A0) (ASR); + BITMUX( R1 , R6, A0) (ASR); + BITMUX( R1 , R7, A0) (ASR); + CHECKREG r0, 0x00918800; + CHECKREG r1, 0x0024682C; + CHECKREG r2, 0x09A28BC4; + CHECKREG r3, 0x0A2B0C4D; + CHECKREG r4, 0x0AB388D5; + CHECKREG r5, 0x0B3C0D5E; + CHECKREG r6, 0x0BC48DE6; + CHECKREG r7, 0x0C4D0E6F; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x28888000; + CHECKREG r1, 0x00000077; + + imm32 r0, 0x31232002; + imm32 r1, 0x22342678; + imm32 r2, 0x23452789; + imm32 r3, 0x2456289a; + imm32 r4, 0x256729ab; + imm32 r5, 0x26782abc; + imm32 r6, 0x27892bcd; + imm32 r7, 0x289a2cde; + BITMUX( R2 , R0, A0) (ASR); + BITMUX( R2 , R1, A0) (ASR); +//r2, r2, a0 >>= bitmux; + BITMUX( R2 , R3, A0) (ASR); + BITMUX( R2 , R4, A0) (ASR); + BITMUX( R2 , R5, A0) (ASR); + BITMUX( R2 , R6, A0) (ASR); + BITMUX( R2 , R7, A0) (ASR); + CHECKREG r0, 0x18919001; + CHECKREG r1, 0x111A133C; + CHECKREG r2, 0x00468A4F; + CHECKREG r3, 0x122B144D; + CHECKREG r4, 0x12B394D5; + CHECKREG r5, 0x133C155E; + CHECKREG r6, 0x13C495E6; + CHECKREG r7, 0x144D166F; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x05DCA222; + CHECKREG r1, 0x00000023; + + imm32 r0, 0x31230003; + imm32 r1, 0x32345378; + imm32 r2, 0x33456389; + imm32 r3, 0x3456739a; + imm32 r4, 0x356783ab; + imm32 r5, 0x367893bc; + imm32 r6, 0x3789a3cd; + imm32 r7, 0x389ab3de; + BITMUX( R3 , R0, A0) (ASR); + BITMUX( R3 , R1, A0) (ASR); + BITMUX( R3 , R2, A0) (ASR); +//r3, r3, a0 >>= bitmux; + BITMUX( R3 , R4, A0) (ASR); + BITMUX( R3 , R5, A0) (ASR); + BITMUX( R3 , R6, A0) (ASR); + BITMUX( R3 , R7, A0) (ASR); + CHECKREG r0, 0x18918001; + CHECKREG r1, 0x191A29BC; + CHECKREG r2, 0x19A2B1C4; + CHECKREG r3, 0x0068ACE7; + CHECKREG r4, 0x1AB3C1D5; + CHECKREG r5, 0x1B3C49DE; + CHECKREG r6, 0x1BC4D1E6; + CHECKREG r7, 0x1C4D59EF; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x988C1772; + CHECKREG r1, 0x00000027; + + imm32 r0, 0x41230044; + imm32 r1, 0x42345648; + imm32 r2, 0x43456749; + imm32 r3, 0x4456784a; + imm32 r4, 0x4567894b; + imm32 r5, 0x46789a4c; + imm32 r6, 0x4789ab4d; + imm32 r7, 0x489abc44; + BITMUX( R4 , R0, A0) (ASR); + BITMUX( R4 , R1, A0) (ASR); + BITMUX( R4 , R2, A0) (ASR); + BITMUX( R4 , R3, A0) (ASR); +//r4, r4, a0 >>= bitmux; + BITMUX( R4 , R5, A0) (ASR); + BITMUX( R4 , R6, A0) (ASR); + BITMUX( R4 , R7, A0) (ASR); + CHECKREG r0, 0x20918022; + CHECKREG r1, 0x211A2B24; + CHECKREG r2, 0x21A2B3A4; + CHECKREG r3, 0x222B3C25; + CHECKREG r4, 0x008ACF12; + CHECKREG r5, 0x233C4D26; + CHECKREG r6, 0x23C4D5A6; + CHECKREG r7, 0x244D5E22; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x949E6230; + CHECKREG r1, 0x00000061; + + imm32 r0, 0x51235005; + imm32 r1, 0x52345678; + imm32 r2, 0x53455789; + imm32 r3, 0x5456589a; + imm32 r4, 0x556759ab; + imm32 r5, 0x56785abc; + imm32 r6, 0x57895bcd; + imm32 r7, 0x589a5cde; + BITMUX( R5 , R0, A0) (ASR); + BITMUX( R5 , R1, A0) (ASR); + BITMUX( R5 , R2, A0) (ASR); + BITMUX( R5 , R3, A0) (ASR); + BITMUX( R5 , R4, A0) (ASR); +//r5, r5, a0 >>= bitmux; + BITMUX( R5 , R6, A0) (ASR); + BITMUX( R5 , R7, A0) (ASR); + CHECKREG r0, 0x2891A802; + CHECKREG r1, 0x291A2B3C; + CHECKREG r2, 0x29A2ABC4; + CHECKREG r3, 0x2A2B2C4D; + CHECKREG r4, 0x2AB3ACD5; + CHECKREG r5, 0x00ACF0B5; + CHECKREG r6, 0x2BC4ADE6; + CHECKREG r7, 0x2C4D2E6F; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0xC9865279; + CHECKREG r1, 0x0000003D; + + imm32 r0, 0x61260006; + imm32 r1, 0x62365678; + imm32 r2, 0x63466789; + imm32 r3, 0x6456789a; + imm32 r4, 0x656689ab; + imm32 r5, 0x66786abc; + imm32 r6, 0x6786abcd; + imm32 r7, 0x6896bcde; + BITMUX( R6 , R0, A0) (ASR); + BITMUX( R6 , R1, A0) (ASR); + BITMUX( R6 , R2, A0) (ASR); + BITMUX( R6 , R3, A0) (ASR); + BITMUX( R6 , R4, A0) (ASR); + BITMUX( R6 , R5, A0) (ASR); +//r6, r6, a0 >>= bitmux; + BITMUX( R6 , R7, A0) (ASR); + CHECKREG r0, 0x30930003; + CHECKREG r1, 0x311B2B3C; + CHECKREG r2, 0x31A333C4; + CHECKREG r3, 0x322B3C4D; + CHECKREG r4, 0x32B344D5; + CHECKREG r5, 0x333C355E; + CHECKREG r6, 0x00CF0D57; + CHECKREG r7, 0x344B5E6F; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0xC4F72619; + CHECKREG r1, 0x00000049; + + imm32 r0, 0x71730007; + imm32 r1, 0x72745678; + imm32 r2, 0x73756789; + imm32 r3, 0x7476789a; + imm32 r4, 0x757789ab; + imm32 r5, 0x76789abc; + imm32 r6, 0x7779abcd; + imm32 r7, 0x777abcde; + BITMUX( R7 , R0, A0) (ASR); + BITMUX( R7 , R1, A0) (ASR); + BITMUX( R7 , R2, A0) (ASR); + BITMUX( R7 , R3, A0) (ASR); + BITMUX( R7 , R4, A0) (ASR); + BITMUX( R7 , R5, A0) (ASR); + BITMUX( R7 , R6, A0) (ASR); +//r7, r7, a0 >>= bitmux; + CHECKREG r0, 0x38B98003; + CHECKREG r1, 0x393A2B3C; + CHECKREG r2, 0x39BAB3C4; + CHECKREG r3, 0x3A3B3C4D; + CHECKREG r4, 0x3ABBC4D5; + CHECKREG r5, 0x3B3C4D5E; + CHECKREG r6, 0x3BBCD5E6; + CHECKREG r7, 0x00EEF579; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0xD92713DC; + CHECKREG r1, 0xFFFFFFCD; + + imm32 r0, 0x08230080; + imm32 r1, 0x18345688; + imm32 r2, 0x28456789; + imm32 r3, 0x3856788a; + imm32 r4, 0x4867898b; + imm32 r5, 0x58789a8c; + imm32 r6, 0x6889ab8d; + imm32 r7, 0x789abc8e; +//r0, r0, a0 <<= bitmux; + BITMUX( R0 , R1, A0) (ASL); + BITMUX( R0 , R2, A0) (ASL); + BITMUX( R0 , R3, A0) (ASL); + BITMUX( R0 , R4, A0) (ASL); + BITMUX( R0 , R5, A0) (ASL); + BITMUX( R0 , R6, A0) (ASL); + BITMUX( R0 , R7, A0) (ASL); + CHECKREG r1, 0x3068AD10; + CHECKREG r0, 0x11804000; + CHECKREG r2, 0x508ACF12; + CHECKREG r3, 0x70ACF114; + CHECKREG r4, 0x90CF1316; + CHECKREG r5, 0xB0F13518; + CHECKREG r6, 0xD113571A; + CHECKREG r7, 0xF135791C; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0xC4F70010; + CHECKREG r1, 0x00000049; + + imm32 r0, 0x09230009; + imm32 r1, 0x19345679; + imm32 r2, 0x29456789; + imm32 r3, 0x39567899; + imm32 r4, 0x496789a9; + imm32 r5, 0x59789ab9; + imm32 r6, 0x6989abc9; + imm32 r7, 0x799abcd9; + BITMUX( R1 , R0, A0) (ASL); +//r1, r1, a0 <<= bitmux; + BITMUX( R1 , R2, A0) (ASL); + BITMUX( R1 , R3, A0) (ASL); + BITMUX( R1 , R4, A0) (ASL); + BITMUX( R1 , R5, A0) (ASL); + BITMUX( R1 , R6, A0) (ASL); + BITMUX( R1 , R7, A0) (ASL); + CHECKREG r0, 0x12460012; + CHECKREG r1, 0x9A2B3C80; + CHECKREG r2, 0x528ACF12; + CHECKREG r3, 0x72ACF132; + CHECKREG r4, 0x92CF1352; + CHECKREG r5, 0xB2F13572; + CHECKREG r6, 0xD3135792; + CHECKREG r7, 0xF33579B2; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0xC0040050; + CHECKREG r1, 0x0000003D; + + imm32 r0, 0x0a23000a; + imm32 r1, 0x1a34567a; + imm32 r2, 0x2a45678a; + imm32 r3, 0x3a56789a; + imm32 r4, 0x4a6789aa; + imm32 r5, 0x5aa89aba; + imm32 r6, 0x6a89abca; + imm32 r7, 0x7a9abcda; + BITMUX( R2 , R0, A0) (ASL); + BITMUX( R2 , R1, A0) (ASL); +//r2, r2, a0 <<= bitmux; + BITMUX( R2 , R3, A0) (ASL); + BITMUX( R2 , R4, A0) (ASL); + BITMUX( R2 , R5, A0) (ASL); + BITMUX( R2 , R6, A0) (ASL); + BITMUX( R2 , R7, A0) (ASL); + CHECKREG r0, 0x14460014; + CHECKREG r1, 0x3468ACF4; + CHECKREG r2, 0x22B3C500; + CHECKREG r3, 0x74ACF134; + CHECKREG r4, 0x94CF1354; + CHECKREG r5, 0xB5513574; + CHECKREG r6, 0xD5135794; + CHECKREG r7, 0xF53579B4; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x00140111; + CHECKREG r1, 0x00000001; + + imm32 r0, 0x01b300b3; + imm32 r1, 0x12b456b8; + imm32 r2, 0x23b567b9; + imm32 r3, 0x34b678ba; + imm32 r4, 0x45b789bb; + imm32 r5, 0x56b89abc; + imm32 r6, 0x67b9abbd; + imm32 r7, 0x78babcbe; + BITMUX( R3 , R0, A0) (ASL); + BITMUX( R3 , R1, A0) (ASL); + BITMUX( R3 , R2, A0) (ASL); +//r3, r3, a0 <<= bitmux; + BITMUX( R3 , R4, A0) (ASL); + BITMUX( R3 , R5, A0) (ASL); + BITMUX( R3 , R6, A0) (ASL); + BITMUX( R3 , R7, A0) (ASL); + CHECKREG r0, 0x03660166; + CHECKREG r1, 0x2568AD70; + CHECKREG r2, 0x476ACF72; + CHECKREG r3, 0x5B3C5D00; + CHECKREG r4, 0x8B6F1376; + CHECKREG r5, 0xAD713578; + CHECKREG r6, 0xCF73577A; + CHECKREG r7, 0xF175797C; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x00444144; + CHECKREG r1, 0x00000005; + + imm32 r0, 0x012300c4; + imm32 r1, 0x123456c8; + imm32 r2, 0x234567c9; + imm32 r3, 0x345678ca; + imm32 r4, 0x456789cb; + imm32 r5, 0x56789acc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcce; + BITMUX( R4 , R0, A0) (ASL); + BITMUX( R4 , R1, A0) (ASL); + BITMUX( R4 , R2, A0) (ASL); + BITMUX( R4 , R3, A0) (ASL); +//r4, r4, a0 <<= bitmux; + BITMUX( R4 , R5, A0) (ASL); + BITMUX( R4 , R6, A0) (ASL); + BITMUX( R4 , R7, A0) (ASL); + CHECKREG r0, 0x02460188; + CHECKREG r1, 0x2468AD90; + CHECKREG r2, 0x468ACF92; + CHECKREG r3, 0x68ACF194; + CHECKREG r4, 0xB3C4E580; + CHECKREG r5, 0xACF13598; + CHECKREG r6, 0xCF13579A; + CHECKREG r7, 0xF135799C; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x10510404; + CHECKREG r1, 0x00000011; + + imm32 r0, 0x0c230d05; + imm32 r1, 0x1c345d78; + imm32 r2, 0x2c456d89; + imm32 r3, 0x3c567d9a; + imm32 r4, 0x4c678dab; + imm32 r5, 0x5c789dbc; + imm32 r6, 0x6c89adcd; + imm32 r7, 0x7c9abdde; + BITMUX( R5 , R0, A0) (ASL); + BITMUX( R5 , R1, A0) (ASL); + BITMUX( R5 , R2, A0) (ASL); + BITMUX( R5 , R3, A0) (ASL); + BITMUX( R5 , R4, A0) (ASL); +//r5, r5, a0 <<= bitmux; + BITMUX( R5 , R6, A0) (ASL); + BITMUX( R5 , R7, A0) (ASL); + CHECKREG r0, 0x18461A0A; + CHECKREG r1, 0x3868BAF0; + CHECKREG r2, 0x588ADB12; + CHECKREG r3, 0x78ACFB34; + CHECKREG r4, 0x98CF1B56; + CHECKREG r5, 0x3C4EDE00; + CHECKREG r6, 0xD9135B9A; + CHECKREG r7, 0xF9357BBC; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x41010454; + CHECKREG r1, 0x00000014; + + imm32 r0, 0x0d230e06; + imm32 r1, 0x1d345e78; + imm32 r2, 0x2d456e89; + imm32 r3, 0x3d567e9a; + imm32 r4, 0x4d678eab; + imm32 r5, 0x5d789ebc; + imm32 r6, 0x6d89aecd; + imm32 r7, 0x7d9abede; + BITMUX( R6 , R0, A0) (ASL); + BITMUX( R6 , R1, A0) (ASL); + BITMUX( R6 , R2, A0) (ASL); + BITMUX( R6 , R3, A0) (ASL); + BITMUX( R6 , R4, A0) (ASL); + BITMUX( R6 , R5, A0) (ASL); +//r6, r6, a0 <<= bitmux; + BITMUX( R6 , R7, A0) (ASL); + CHECKREG r0, 0x1A461C0C; + CHECKREG r1, 0x3A68BCF0; + CHECKREG r2, 0x5A8ADD12; + CHECKREG r3, 0x7AACFD34; + CHECKREG r4, 0x9ACF1D56; + CHECKREG r5, 0xBAF13D78; + CHECKREG r6, 0xC4D76680; + CHECKREG r7, 0xFB357DBC; + + R0 = A0.w; + R1 = A0.x; + CHECKREG r0, 0x41150514; + CHECKREG r1, 0x00000040; + + imm32 r0, 0x01230007; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + BITMUX( R7 , R0, A0) (ASL); + BITMUX( R7 , R1, A0) (ASL); + BITMUX( R7 , R2, A0) (ASL); + BITMUX( R7 , R3, A0) (ASL); + BITMUX( R7 , R4, A0) (ASL); + BITMUX( R7 , R5, A0) (ASL); + BITMUX( R7 , R6, A0) (ASL); +//r7, r7, a0 <<= bitmux; + + CHECKREG r0, 0x0246000E; + CHECKREG r1, 0x2468ACF0; + CHECKREG r2, 0x468ACF12; + CHECKREG r3, 0x68ACF134; + CHECKREG r4, 0x8ACF1356; + CHECKREG r5, 0xACF13578; + CHECKREG r6, 0xCF13579A; + CHECKREG r7, 0x4D5E6F00; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_bxor.s b/sim/testsuite/sim/bfin/c_dsp32shift_bxor.s new file mode 100644 index 0000000..18b148b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_bxor.s @@ -0,0 +1,126 @@ +//Original:/testcases/core/c_dsp32shift_bxor/c_dsp32shift_bxor.dsp +// Spec Reference: dsp32shift bxor +# mach: bfin + +.include "testutils.inc" + start + +R0 = 0; +R1 = 58; +A0 = R1; +ASTAT = R0; + + +imm32 r0, 0x12345678; +imm32 r1, 0x22334455; +imm32 r2, 0x66778890; +imm32 r3, 0xaabbccdd; +imm32 r4, 0x34567890; +imm32 r5, 0xa2d3d5f6; +imm32 r6, 0x456bda06; +imm32 r7, 0x56789abc; +R0.L = CC = BXORSHIFT( A0 , R0 ); +R1.L = CC = BXORSHIFT( A0 , R1 ); +R2.L = CC = BXORSHIFT( A0 , R2 ); +R3.L = CC = BXORSHIFT( A0 , R3 ); +R4.L = CC = BXORSHIFT( A0 , R4 ); +R5.L = CC = BXORSHIFT( A0 , R5 ); +R6.L = CC = BXORSHIFT( A0 , R6 ); +R7.L = CC = BXORSHIFT( A0 , R7 ); +CHECKREG r0, 0x12340001; +CHECKREG r1, 0x22330001; +CHECKREG r2, 0x66770000; +CHECKREG r3, 0xAABB0001; +CHECKREG r4, 0x34560000; +CHECKREG r5, 0xA2D30000; +CHECKREG r6, 0x456B0000; +CHECKREG r7, 0x56780001; + +imm32 r0, 0xa1001001; +imm32 r1, 0x1b001001; +imm32 r2, 0x11c01002; +imm32 r3, 0x110d1003; +imm32 r4, 0x1100e004; +imm32 r5, 0x11001f05; +imm32 r6, 0x11001006; +imm32 r7, 0x11001001; +R5.L = CC = BXORSHIFT( A0 , R0 ); +R4.L = CC = BXORSHIFT( A0 , R1 ); +R2.L = CC = BXORSHIFT( A0 , R2 ); +R7.L = CC = BXORSHIFT( A0 , R3 ); +R0.L = CC = BXORSHIFT( A0 , R4 ); +R1.L = CC = BXORSHIFT( A0 , R5 ); +R3.L = CC = BXORSHIFT( A0 , R6 ); +R6.L = CC = BXORSHIFT( A0 , R7 ); +CHECKREG r0, 0xA1000000; +CHECKREG r1, 0x1B000000; +CHECKREG r2, 0x11C00001; +CHECKREG r3, 0x110D0000; +CHECKREG r4, 0x11000000; +CHECKREG r5, 0x11000001; +CHECKREG r6, 0x11000000; +CHECKREG r7, 0x11000001; + +imm32 r0, 0xa2001001; +imm32 r1, 0x1b341001; +imm32 r2, 0x71c01002; +imm32 r3, 0x810d1003; +imm32 r4, 0x1600e004; +imm32 r5, 0x41001405; +imm32 r6, 0x31003006; +imm32 r7, 0x21004671; +R2.L = CC = BXOR( A0 , R0 ); +R3.L = CC = BXOR( A0 , R1 ); +R5.L = CC = BXOR( A0 , R2 ); +R6.L = CC = BXOR( A0 , R3 ); +R0.L = CC = BXOR( A0 , R4 ); +R1.L = CC = BXOR( A0 , R5 ); +R7.L = CC = BXOR( A0 , R6 ); +R4.L = CC = BXOR( A0 , R7 ); +CHECKREG r0, 0xA2000000; +CHECKREG r1, 0x1B340000; +CHECKREG r2, 0x71C00000; +CHECKREG r3, 0x810D0000; +CHECKREG r4, 0x16000000; +CHECKREG r5, 0x41000000; +CHECKREG r6, 0x31000001; +CHECKREG r7, 0x21000000; + +imm32 r0, 0x4a502001; +imm32 r1, 0x6b343001; +imm32 r2, 0x71c04002; +imm32 r3, 0x810d5003; +imm32 r4, 0x5600e004; +imm32 r5, 0x47001405; +imm32 r6, 0x91003006; +imm32 r7, 0xa1004671; +A1 = R3; +R0.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R1.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R2.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R3.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R4.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R5.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R6.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +R7.L = CC = BXOR( A0 , A1, CC ); +A0 = BXORSHIFT( A0 , A1, CC ); +CHECKREG r0, 0x4A500001; +CHECKREG r1, 0x6B340000; +CHECKREG r2, 0x71C00000; +CHECKREG r3, 0x810D0000; +CHECKREG r4, 0x56000001; +CHECKREG r5, 0x47000000; +CHECKREG r6, 0x91000001; +CHECKREG r7, 0xA1000001; + + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_expadj_h.s b/sim/testsuite/sim/bfin/c_dsp32shift_expadj_h.s new file mode 100644 index 0000000..30ecd61 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_expadj_h.s @@ -0,0 +1,214 @@ +//Original:/testcases/core/c_dsp32shift_expadj_h/c_dsp32shift_expadj_h.dsp +// Spec Reference: dsp32shift expadj rh +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x80000008; +imm32 r1, 0x80010008; +imm32 r2, 0x80020008; +imm32 r3, 0x80030008; +imm32 r4, 0x80040008; +imm32 r5, 0x80050008; +imm32 r6, 0x80060008; +imm32 r7, 0x80070008; +R1.L = EXPADJ( R1.H , R0.L ); +R2.L = EXPADJ( R2.H , R0.L ); +R3.L = EXPADJ( R3.H , R0.L ); +R4.L = EXPADJ( R4.H , R0.L ); +R5.L = EXPADJ( R5.H , R0.L ); +R6.L = EXPADJ( R6.H , R0.L ); +R7.L = EXPADJ( R7.H , R0.L ); +R0.L = EXPADJ( R0.H , R0.L ); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x80010000; +CHECKREG r2, 0x80020000; +CHECKREG r3, 0x80030000; +CHECKREG r4, 0x80040000; +CHECKREG r5, 0x80050000; +CHECKREG r6, 0x80060000; +CHECKREG r7, 0x80070000; + +imm32 r0, 0x90010009; +imm32 r1, 0x00010009; +imm32 r2, 0x90020009; +imm32 r3, 0x90030009; +imm32 r4, 0x90040009; +imm32 r5, 0x90050009; +imm32 r6, 0x90060009; +imm32 r7, 0x90070009; +R0.L = EXPADJ( R0.H , R1.L ); +R2.L = EXPADJ( R2.H , R1.L ); +R3.L = EXPADJ( R3.H , R1.L ); +R4.L = EXPADJ( R4.H , R1.L ); +R5.L = EXPADJ( R5.H , R1.L ); +R6.L = EXPADJ( R6.H , R1.L ); +R7.L = EXPADJ( R7.H , R1.L ); +R1.L = EXPADJ( R1.H , R1.L ); +CHECKREG r0, 0x90010000; +CHECKREG r1, 0x00010009; +CHECKREG r2, 0x90020000; +CHECKREG r3, 0x90030000; +CHECKREG r4, 0x90040000; +CHECKREG r5, 0x90050000; +CHECKREG r6, 0x90060000; +CHECKREG r7, 0x90070000; + + +imm32 r0, 0xa001000a; +imm32 r1, 0xa001000a; +imm32 r2, 0xa002000a; +imm32 r3, 0xa003000a; +imm32 r4, 0xa004000a; +imm32 r5, 0xa005000a; +imm32 r6, 0xa006000a; +imm32 r7, 0xa007000a; +R0.L = EXPADJ( R0.H , R2.L ); +R1.L = EXPADJ( R1.H , R2.L ); +R3.L = EXPADJ( R3.H , R2.L ); +R4.L = EXPADJ( R4.H , R2.L ); +R5.L = EXPADJ( R5.H , R2.L ); +R6.L = EXPADJ( R6.H , R2.L ); +R7.L = EXPADJ( R7.H , R2.L ); +R2.L = EXPADJ( R2.H , R2.L ); +CHECKREG r0, 0xA0010000; +CHECKREG r1, 0xA0010000; +CHECKREG r2, 0xA0020000; +CHECKREG r3, 0xA0030000; +CHECKREG r4, 0xA0040000; +CHECKREG r5, 0xA0050000; +CHECKREG r6, 0xA0060000; +CHECKREG r7, 0xA0070000; + +imm32 r0, 0xc001000c; +imm32 r1, 0xc001000c; +imm32 r2, 0xc002000c; +imm32 r3, 0xc003001c; +imm32 r4, 0xc004000c; +imm32 r5, 0xc005000c; +imm32 r6, 0xc006000c; +imm32 r7, 0xc007000c; +R0.L = EXPADJ( R0.H , R3.L ); +R1.L = EXPADJ( R1.H , R3.L ); +R2.L = EXPADJ( R2.H , R3.L ); +R4.L = EXPADJ( R4.H , R3.L ); +R5.L = EXPADJ( R5.H , R3.L ); +R6.L = EXPADJ( R6.H , R3.L ); +R7.L = EXPADJ( R7.H , R3.L ); +R3.L = EXPADJ( R3.H , R3.L ); +CHECKREG r0, 0xC0010001; +CHECKREG r1, 0xC0010001; +CHECKREG r2, 0xC0020001; +CHECKREG r3, 0xC0030001; +CHECKREG r4, 0xC0040001; +CHECKREG r5, 0xC0050001; +CHECKREG r6, 0xC0060001; +CHECKREG r7, 0xC0070001; + +imm32 r0, 0xb0000008; +imm32 r1, 0xb0010008; +imm32 r2, 0xb0020008; +imm32 r3, 0xb0030008; +imm32 r4, 0xb0040008; +imm32 r5, 0xb0050008; +imm32 r6, 0xb0060008; +imm32 r7, 0xb0070008; +R0.L = EXPADJ( R1.H , R4.L ); +R1.L = EXPADJ( R2.H , R4.L ); +R2.L = EXPADJ( R3.H , R4.L ); +R3.L = EXPADJ( R4.H , R4.L ); +R5.L = EXPADJ( R5.H , R4.L ); +R6.L = EXPADJ( R6.H , R4.L ); +R7.L = EXPADJ( R7.H , R4.L ); +R4.L = EXPADJ( R0.H , R4.L ); +CHECKREG r0, 0xB0000000; +CHECKREG r1, 0xB0010000; +CHECKREG r2, 0xB0020000; +CHECKREG r3, 0xB0030000; +CHECKREG r4, 0xB0040000; +CHECKREG r5, 0xB0050000; +CHECKREG r6, 0xB0060000; +CHECKREG r7, 0xB0070000; + +imm32 r0, 0xc0010009; +imm32 r1, 0xc0010009; +imm32 r2, 0xc0020009; +imm32 r3, 0xc0030009; +imm32 r4, 0xc0040009; +imm32 r5, 0xc0050009; +imm32 r6, 0xc0060009; +imm32 r7, 0xc0070009; +R0.L = EXPADJ( R0.H , R5.L ); +R1.L = EXPADJ( R2.H , R5.L ); +R2.L = EXPADJ( R3.H , R5.L ); +R3.L = EXPADJ( R4.H , R5.L ); +R4.L = EXPADJ( R5.H , R5.L ); +R6.L = EXPADJ( R6.H , R5.L ); +R7.L = EXPADJ( R7.H , R5.L ); +R5.L = EXPADJ( R1.H , R5.L ); +CHECKREG r0, 0xC0010001; +CHECKREG r1, 0xC0010001; +CHECKREG r2, 0xC0020001; +CHECKREG r3, 0xC0030001; +CHECKREG r4, 0xC0040001; +CHECKREG r5, 0xC0050001; +CHECKREG r6, 0xC0060001; +CHECKREG r7, 0xC0070001; + + +imm32 r0, 0xe001000a; +imm32 r1, 0xe001000a; +imm32 r2, 0xe002000a; +imm32 r3, 0xe003000a; +imm32 r4, 0xe004000a; +imm32 r5, 0xe005000a; +imm32 r6, 0xe006000a; +imm32 r7, 0xe007000a; +R0.L = EXPADJ( R0.H , R6.L ); +R1.L = EXPADJ( R1.H , R6.L ); +R2.L = EXPADJ( R3.H , R6.L ); +R3.L = EXPADJ( R4.H , R6.L ); +R4.L = EXPADJ( R5.H , R6.L ); +R5.L = EXPADJ( R6.H , R6.L ); +R6.L = EXPADJ( R7.H , R6.L ); +R7.L = EXPADJ( R2.H , R6.L ); +CHECKREG r0, 0xE0010002; +CHECKREG r1, 0xE0010002; +CHECKREG r2, 0xE0020002; +CHECKREG r3, 0xE0030002; +CHECKREG r4, 0xE0040002; +CHECKREG r5, 0xE0050002; +CHECKREG r6, 0xE0060002; +CHECKREG r7, 0xE0070002; + +imm32 r0, 0xd001000c; +imm32 r1, 0xd001000c; +imm32 r2, 0xd002000c; +imm32 r3, 0xd003001c; +imm32 r4, 0xd004000c; +imm32 r5, 0xd005000c; +imm32 r6, 0xd006000c; +imm32 r7, 0xd007000c; +R0.L = EXPADJ( R0.H , R7.L ); +R1.L = EXPADJ( R1.H , R7.L ); +R2.L = EXPADJ( R2.H , R7.L ); +R3.L = EXPADJ( R4.H , R7.L ); +R4.L = EXPADJ( R5.H , R7.L ); +R5.L = EXPADJ( R6.H , R7.L ); +R6.L = EXPADJ( R7.H , R7.L ); +R7.L = EXPADJ( R3.H , R7.L ); +CHECKREG r0, 0xD0010001; +CHECKREG r1, 0xD0010001; +CHECKREG r2, 0xD0020001; +CHECKREG r3, 0xD0030001; +CHECKREG r4, 0xD0040001; +CHECKREG r5, 0xD0050001; +CHECKREG r6, 0xD0060001; +CHECKREG r7, 0xD0070001; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_expadj_l.s b/sim/testsuite/sim/bfin/c_dsp32shift_expadj_l.s new file mode 100644 index 0000000..237850b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_expadj_l.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32shift_expadj_l/c_dsp32shift_expadj_l.dsp +// Spec Reference: dsp32shift expadj rl +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R1.L = EXPADJ( R1.L , R0.L ); +R2.L = EXPADJ( R2.L , R0.L ); +R3.L = EXPADJ( R3.L , R0.L ); +R4.L = EXPADJ( R4.L , R0.L ); +R5.L = EXPADJ( R5.L , R0.L ); +R6.L = EXPADJ( R6.L , R0.L ); +R7.L = EXPADJ( R7.L , R0.L ); +R0.L = EXPADJ( R0.L , R0.L ); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x11001001; +imm32 r1, 0x11001001; +imm32 r2, 0x11001002; +imm32 r3, 0x11001003; +imm32 r4, 0x11001004; +imm32 r5, 0x11001005; +imm32 r6, 0x11001006; +imm32 r7, 0x11001007; +R0.L = EXPADJ( R0.L , R1.L ); +R2.L = EXPADJ( R2.L , R1.L ); +R3.L = EXPADJ( R3.L , R1.L ); +R4.L = EXPADJ( R4.L , R1.L ); +R5.L = EXPADJ( R5.L , R1.L ); +R6.L = EXPADJ( R6.L , R1.L ); +R7.L = EXPADJ( R7.L , R1.L ); +R1.L = EXPADJ( R1.L , R1.L ); +CHECKREG r0, 0x11001001; +CHECKREG r1, 0x11001001; +CHECKREG r2, 0x11001001; +CHECKREG r3, 0x11001001; +CHECKREG r4, 0x11001001; +CHECKREG r5, 0x11001001; +CHECKREG r6, 0x11001001; +CHECKREG r7, 0x11001001; + +imm32 r0, 0x2000c001; +imm32 r1, 0x2000d001; +imm32 r2, 0x2000000f; +imm32 r3, 0x2000e003; +imm32 r4, 0x2000f004; +imm32 r5, 0x2000f005; +imm32 r6, 0x2000f006; +imm32 r7, 0x2000f007; +R0.L = EXPADJ( R0.L , R2.L ); +R1.L = EXPADJ( R1.L , R2.L ); +R3.L = EXPADJ( R3.L , R2.L ); +R4.L = EXPADJ( R4.L , R2.L ); +R5.L = EXPADJ( R5.L , R2.L ); +R6.L = EXPADJ( R6.L , R2.L ); +R7.L = EXPADJ( R7.L , R2.L ); +R2.L = EXPADJ( R2.L , R2.L ); +CHECKREG r0, 0x20000001; +CHECKREG r1, 0x20000001; +CHECKREG r2, 0x2000000B; +CHECKREG r3, 0x20000002; +CHECKREG r4, 0x20000003; +CHECKREG r5, 0x20000003; +CHECKREG r6, 0x20000003; +CHECKREG r7, 0x20000003; + +imm32 r0, 0x30009001; +imm32 r1, 0x3000a001; +imm32 r2, 0x3000b002; +imm32 r3, 0x30000010; +imm32 r4, 0x3000c004; +imm32 r5, 0x3000d005; +imm32 r6, 0x3000e006; +imm32 r7, 0x3000f007; +R0.L = EXPADJ( R0.L , R3.L ); +R1.L = EXPADJ( R1.L , R3.L ); +R2.L = EXPADJ( R2.L , R3.L ); +R4.L = EXPADJ( R4.L , R3.L ); +R5.L = EXPADJ( R5.L , R3.L ); +R6.L = EXPADJ( R6.L , R3.L ); +R7.L = EXPADJ( R7.L , R3.L ); +R3.L = EXPADJ( R3.L , R3.L ); +CHECKREG r0, 0x30000010; +CHECKREG r1, 0x30000010; +CHECKREG r2, 0x30000010; +CHECKREG r3, 0x30000010; +CHECKREG r4, 0x30000010; +CHECKREG r5, 0x30000010; +CHECKREG r6, 0x30000010; +CHECKREG r7, 0x30000010; + +imm32 r0, 0x40000000; +imm32 r1, 0x4000c001; +imm32 r2, 0x4000c002; +imm32 r3, 0x4000c003; +imm32 r4, 0x4000c004; +imm32 r5, 0x4000c005; +imm32 r6, 0x4000c006; +imm32 r7, 0x4000c007; +R0.L = EXPADJ( R1.L , R4.L ); +R1.L = EXPADJ( R2.L , R4.L ); +R2.L = EXPADJ( R3.L , R4.L ); +R3.L = EXPADJ( R4.L , R4.L ); +R5.L = EXPADJ( R5.L , R4.L ); +R6.L = EXPADJ( R6.L , R4.L ); +R7.L = EXPADJ( R7.L , R4.L ); +R4.L = EXPADJ( R0.L , R4.L ); +CHECKREG r0, 0x40000001; +CHECKREG r1, 0x40000001; +CHECKREG r2, 0x40000001; +CHECKREG r3, 0x40000001; +CHECKREG r4, 0x4000C004; +CHECKREG r5, 0x40000001; +CHECKREG r6, 0x40000001; +CHECKREG r7, 0x40000001; + +imm32 r0, 0x51001001; +imm32 r1, 0x51001001; +imm32 r2, 0x51001002; +imm32 r3, 0x51001003; +imm32 r4, 0x51001004; +imm32 r5, 0x51001005; +imm32 r6, 0x51001006; +imm32 r7, 0x51001007; +R0.L = EXPADJ( R0.L , R5.L ); +R1.L = EXPADJ( R2.L , R5.L ); +R2.L = EXPADJ( R3.L , R5.L ); +R3.L = EXPADJ( R4.L , R5.L ); +R4.L = EXPADJ( R5.L , R5.L ); +R6.L = EXPADJ( R6.L , R5.L ); +R7.L = EXPADJ( R7.L , R5.L ); +R5.L = EXPADJ( R1.L , R5.L ); +CHECKREG r0, 0x51000002; +CHECKREG r1, 0x51000002; +CHECKREG r2, 0x51000002; +CHECKREG r3, 0x51000002; +CHECKREG r4, 0x51000002; +CHECKREG r5, 0x51001005; +CHECKREG r6, 0x51000002; +CHECKREG r7, 0x51000002; + +imm32 r0, 0x6000c001; +imm32 r1, 0x6000d001; +imm32 r2, 0x6000000f; +imm32 r3, 0x6000e003; +imm32 r4, 0x6000f004; +imm32 r5, 0x6000f005; +imm32 r6, 0x6000f006; +imm32 r7, 0x6000f007; +R0.L = EXPADJ( R0.L , R6.L ); +R1.L = EXPADJ( R1.L , R6.L ); +R2.L = EXPADJ( R3.L , R6.L ); +R3.L = EXPADJ( R4.L , R6.L ); +R4.L = EXPADJ( R5.L , R6.L ); +R5.L = EXPADJ( R6.L , R6.L ); +R7.L = EXPADJ( R7.L , R6.L ); +R6.L = EXPADJ( R2.L , R6.L ); +CHECKREG r0, 0x60000001; +CHECKREG r1, 0x60000001; +CHECKREG r2, 0x60000002; +CHECKREG r3, 0x60000003; +CHECKREG r4, 0x60000003; +CHECKREG r5, 0x60000003; +CHECKREG r6, 0x6000F006; +CHECKREG r7, 0x60000003; + +imm32 r0, 0x70009001; +imm32 r1, 0x7000a001; +imm32 r2, 0x7000b002; +imm32 r3, 0x70000010; +imm32 r4, 0x7000c004; +imm32 r5, 0x7000d005; +imm32 r6, 0x7000e006; +imm32 r7, 0x7000f007; +R0.L = EXPADJ( R0.L , R7.L ); +R1.L = EXPADJ( R1.L , R7.L ); +R2.L = EXPADJ( R2.L , R7.L ); +R3.L = EXPADJ( R4.L , R7.L ); +R4.L = EXPADJ( R5.L , R7.L ); +R5.L = EXPADJ( R6.L , R7.L ); +R6.L = EXPADJ( R7.L , R7.L ); +R7.L = EXPADJ( R3.L , R7.L ); +CHECKREG r0, 0x70000000; +CHECKREG r1, 0x70000000; +CHECKREG r2, 0x70000000; +CHECKREG r3, 0x70000001; +CHECKREG r4, 0x70000001; +CHECKREG r5, 0x70000002; +CHECKREG r6, 0x70000003; +CHECKREG r7, 0x7000F007; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_expadj_r.s b/sim/testsuite/sim/bfin/c_dsp32shift_expadj_r.s new file mode 100644 index 0000000..c557cbf --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_expadj_r.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32shift_expadj_r/c_dsp32shift_expadj_r.dsp +// Spec Reference: dsp32shift expadj r +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x08000800; +imm32 r1, 0x08000801; +imm32 r2, 0x08000802; +imm32 r3, 0x08000803; +imm32 r4, 0x08000804; +imm32 r5, 0x08000805; +imm32 r6, 0x08000806; +imm32 r7, 0x08000807; +//rl0 = expadj r0 by rl0; +R1.L = EXPADJ( R1 , R0.L ); +R2.L = EXPADJ( R2 , R0.L ); +R3.L = EXPADJ( R3 , R0.L ); +R4.L = EXPADJ( R4 , R0.L ); +R5.L = EXPADJ( R5 , R0.L ); +R6.L = EXPADJ( R6 , R0.L ); +R7.L = EXPADJ( R7 , R0.L ); +CHECKREG r0, 0x08000800; +CHECKREG r1, 0x08000800; +CHECKREG r2, 0x08000800; +CHECKREG r3, 0x08000800; +CHECKREG r4, 0x08000800; +CHECKREG r5, 0x08000800; +CHECKREG r6, 0x08000800; +CHECKREG r7, 0x08000800; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000001; +imm32 r2, 0x0900d002; +imm32 r3, 0x0900d003; +imm32 r4, 0x0900d004; +imm32 r5, 0x0900d005; +imm32 r6, 0x0900d006; +imm32 r7, 0x0900d007; +R0.L = EXPADJ( R0 , R1.L ); +R1.L = EXPADJ( R1 , R1.L ); +R2.L = EXPADJ( R2 , R1.L ); +R3.L = EXPADJ( R3 , R1.L ); +R4.L = EXPADJ( R4 , R1.L ); +R5.L = EXPADJ( R5 , R1.L ); +R6.L = EXPADJ( R6 , R1.L ); +R7.L = EXPADJ( R7 , R1.L ); +CHECKREG r0, 0x09000001; +CHECKREG r1, 0x09000001; +CHECKREG r2, 0x09000001; +CHECKREG r3, 0x09000001; +CHECKREG r4, 0x09000001; +CHECKREG r5, 0x09000001; +CHECKREG r6, 0x09000001; +CHECKREG r7, 0x09000001; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a00e003; +imm32 r4, 0x0a00e004; +imm32 r5, 0x0a00e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0a00e007; +R0.L = EXPADJ( R0 , R2.L ); +R1.L = EXPADJ( R1 , R2.L ); +//rl2 = expadj r2 by rl2; +R3.L = EXPADJ( R3 , R2.L ); +R4.L = EXPADJ( R4 , R2.L ); +R5.L = EXPADJ( R5 , R2.L ); +R6.L = EXPADJ( R6 , R2.L ); +R7.L = EXPADJ( R7 , R2.L ); +CHECKREG r0, 0x0A000003; +CHECKREG r1, 0x0A000003; +CHECKREG r2, 0x0A00000F; +CHECKREG r3, 0x0A000003; +CHECKREG r4, 0x0A000003; +CHECKREG r5, 0x0A000003; +CHECKREG r6, 0x0A000003; +CHECKREG r7, 0x0A000003; + +imm32 r0, 0x0b00f001; +imm32 r1, 0x0b00f001; +imm32 r2, 0x0b00f002; +imm32 r3, 0x0b000010; +imm32 r4, 0x0b00f004; +imm32 r5, 0x0b00f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x0b00f007; +R0.L = EXPADJ( R0 , R3.L ); +R1.L = EXPADJ( R1 , R3.L ); +R2.L = EXPADJ( R2 , R3.L ); +R3.L = EXPADJ( R3 , R3.L ); +R4.L = EXPADJ( R4 , R3.L ); +R5.L = EXPADJ( R5 , R3.L ); +R6.L = EXPADJ( R6 , R3.L ); +R7.L = EXPADJ( R7 , R3.L ); +CHECKREG r0, 0x0B000003; +CHECKREG r1, 0x0B000003; +CHECKREG r2, 0x0B000003; +CHECKREG r3, 0x0B000003; +CHECKREG r4, 0x0B000003; +CHECKREG r5, 0x0B000003; +CHECKREG r6, 0x0B000003; +CHECKREG r7, 0x0B000003; + +imm32 r0, 0x0c0000c0; +imm32 r1, 0x0c0100c0; +imm32 r2, 0x0c0200c0; +imm32 r3, 0x0c0300c0; +imm32 r4, 0x0c0400c0; +imm32 r5, 0x0c0500c0; +imm32 r6, 0x0c0600c0; +imm32 r7, 0x0c0700c0; +R0.L = EXPADJ( R0 , R4.L ); +R1.L = EXPADJ( R1 , R4.L ); +R2.L = EXPADJ( R2 , R4.L ); +R3.L = EXPADJ( R3 , R4.L ); +R4.L = EXPADJ( R4 , R4.L ); +R5.L = EXPADJ( R5 , R4.L ); +R6.L = EXPADJ( R6 , R4.L ); +R7.L = EXPADJ( R7 , R4.L ); +CHECKREG r0, 0x0C0000C0; +CHECKREG r1, 0x0C0100C0; +CHECKREG r2, 0x0C0200C0; +CHECKREG r3, 0x0C0300C0; +CHECKREG r4, 0x0C0400C0; +CHECKREG r5, 0x0C0500C0; +CHECKREG r6, 0x0C0600C0; +CHECKREG r7, 0x0C0700C0; + +imm32 r0, 0xa00100d0; +imm32 r1, 0x000100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa00500d0; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0.L = EXPADJ( R0 , R5.L ); +R1.L = EXPADJ( R1 , R5.L ); +R2.L = EXPADJ( R2 , R5.L ); +R3.L = EXPADJ( R3 , R5.L ); +R4.L = EXPADJ( R4 , R5.L ); +R5.L = EXPADJ( R5 , R5.L ); +R6.L = EXPADJ( R6 , R5.L ); +R7.L = EXPADJ( R7 , R5.L ); +CHECKREG r0, 0xA0010000; +CHECKREG r1, 0x0001000E; +CHECKREG r2, 0xA0020000; +CHECKREG r3, 0xA0030000; +CHECKREG r4, 0xA0040000; +CHECKREG r5, 0xA0050000; +CHECKREG r6, 0xA0060000; +CHECKREG r7, 0xA0070000; + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R0.L = EXPADJ( R0 , R6.L ); +R1.L = EXPADJ( R1 , R6.L ); +R2.L = EXPADJ( R2 , R6.L ); +R3.L = EXPADJ( R3 , R6.L ); +R4.L = EXPADJ( R4 , R6.L ); +R5.L = EXPADJ( R5 , R6.L ); +R6.L = EXPADJ( R6 , R6.L ); +R7.L = EXPADJ( R7 , R6.L ); +CHECKREG r0, 0xB0010000; +CHECKREG r1, 0xB0010000; +CHECKREG r2, 0xB0020000; +CHECKREG r3, 0xB0030000; +CHECKREG r4, 0xB0040000; +CHECKREG r5, 0xB0050000; +CHECKREG r6, 0xB0060000; +CHECKREG r7, 0xB0070000; + +imm32 r0, 0xd00100e0; +imm32 r1, 0xd00100e0; +imm32 r2, 0xd00200e0; +imm32 r3, 0xd00300e0; +imm32 r4, 0xd00400e0; +imm32 r5, 0xd00500e0; +imm32 r6, 0xd00600e0; +imm32 r7, 0xd00700e0; +R0.L = EXPADJ( R0 , R7.L ); +R1.L = EXPADJ( R1 , R7.L ); +R2.L = EXPADJ( R2 , R7.L ); +R3.L = EXPADJ( R3 , R7.L ); +R4.L = EXPADJ( R4 , R7.L ); +R5.L = EXPADJ( R5 , R7.L ); +R6.L = EXPADJ( R6 , R7.L ); +R7.L = EXPADJ( R7 , R7.L ); +CHECKREG r0, 0xD00100E0; +CHECKREG r1, 0xD00100E0; +CHECKREG r2, 0xD00200E0; +CHECKREG r3, 0xD00300E0; +CHECKREG r4, 0xD00400E0; +CHECKREG r5, 0xD00500E0; +CHECKREG r6, 0xD00600E0; +CHECKREG r7, 0xD00700E0; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_expexp_r.s b/sim/testsuite/sim/bfin/c_dsp32shift_expexp_r.s new file mode 100644 index 0000000..4e9186b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_expexp_r.s @@ -0,0 +1,212 @@ +//Original:/testcases/core/c_dsp32shift_expexp_r/c_dsp32shift_expexp_r.dsp +// Spec Reference: dsp32shift expadj / expadj r +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x0800d001; +imm32 r1, 0x08000001; +imm32 r2, 0x0800d002; +imm32 r3, 0x0800d003; +imm32 r4, 0x0800d004; +imm32 r5, 0x0800d005; +imm32 r6, 0x0800d006; +imm32 r7, 0x0800d007; +R1.L = EXPADJ( R1 , R0.L ) (V); +R2.L = EXPADJ( R2 , R0.L ) (V); +R3.L = EXPADJ( R3 , R0.L ) (V); +R4.L = EXPADJ( R4 , R0.L ) (V); +R5.L = EXPADJ( R5 , R0.L ) (V); +R6.L = EXPADJ( R6 , R0.L ) (V); +R7.L = EXPADJ( R7 , R0.L ) (V); +R0.L = EXPADJ( R0 , R0.L ) (V); +CHECKREG r0, 0x0800D001; +CHECKREG r1, 0x0800D001; +CHECKREG r2, 0x0800D001; +CHECKREG r3, 0x0800D001; +CHECKREG r4, 0x0800D001; +CHECKREG r5, 0x0800D001; +CHECKREG r6, 0x0800D001; +CHECKREG r7, 0x0800D001; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000001; +imm32 r2, 0x0900d002; +imm32 r3, 0x0900d003; +imm32 r4, 0x0900d004; +imm32 r5, 0x0900d005; +imm32 r6, 0x0900d006; +imm32 r7, 0x0900d007; +R0.L = EXPADJ( R0 , R1.L ) (V); +R1.L = EXPADJ( R1 , R1.L ) (V); +R2.L = EXPADJ( R2 , R1.L ) (V); +R3.L = EXPADJ( R3 , R1.L ) (V); +R4.L = EXPADJ( R4 , R1.L ) (V); +R5.L = EXPADJ( R5 , R1.L ) (V); +R6.L = EXPADJ( R6 , R1.L ) (V); +R7.L = EXPADJ( R7 , R1.L ) (V); +CHECKREG r0, 0x09000001; +CHECKREG r1, 0x09000001; +CHECKREG r2, 0x09000001; +CHECKREG r3, 0x09000001; +CHECKREG r4, 0x09000001; +CHECKREG r5, 0x09000001; +CHECKREG r6, 0x09000001; +CHECKREG r7, 0x09000001; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a00e003; +imm32 r4, 0x0a00e004; +imm32 r5, 0x0a00e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0a00e007; +R0.L = EXPADJ( R0 , R2.L ) (V); +R1.L = EXPADJ( R1 , R2.L ) (V); +R3.L = EXPADJ( R3 , R2.L ) (V); +R4.L = EXPADJ( R4 , R2.L ) (V); +R5.L = EXPADJ( R5 , R2.L ) (V); +R6.L = EXPADJ( R6 , R2.L ) (V); +R7.L = EXPADJ( R7 , R2.L ) (V); +R2.L = EXPADJ( R2 , R2.L ) (V); +CHECKREG r0, 0x0A000002; +CHECKREG r1, 0x0A000002; +CHECKREG r2, 0x0A000003; +CHECKREG r3, 0x0A000002; +CHECKREG r4, 0x0A000002; +CHECKREG r5, 0x0A000002; +CHECKREG r6, 0x0A000002; +CHECKREG r7, 0x0A000002; + +imm32 r0, 0x0b00f001; +imm32 r1, 0x0b00f001; +imm32 r2, 0x0b00f002; +imm32 r3, 0x0b000010; +imm32 r4, 0x0b00f004; +imm32 r5, 0x0b00f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x0b00f007; +R0.L = EXPADJ( R0 , R3.L ) (V); +R1.L = EXPADJ( R1 , R3.L ) (V); +R2.L = EXPADJ( R2 , R3.L ) (V); +R3.L = EXPADJ( R3 , R3.L ) (V); +R4.L = EXPADJ( R4 , R3.L ) (V); +R5.L = EXPADJ( R5 , R3.L ) (V); +R6.L = EXPADJ( R6 , R3.L ) (V); +R7.L = EXPADJ( R7 , R3.L ) (V); +CHECKREG r0, 0x0B000010; +CHECKREG r1, 0x0B000010; +CHECKREG r2, 0x0B000010; +CHECKREG r3, 0x0B000010; +CHECKREG r4, 0x0B000010; +CHECKREG r5, 0x0B000010; +CHECKREG r6, 0x0B000010; +CHECKREG r7, 0x0B000010; + +imm32 r0, 0x0c0000c0; +imm32 r1, 0x0c0100c0; +imm32 r2, 0x0c0200c0; +imm32 r3, 0x0c0300c0; +imm32 r4, 0x0c0400c0; +imm32 r5, 0x0c0500c0; +imm32 r6, 0x0c0600c0; +imm32 r7, 0x0c0700c0; +R0.L = EXPADJ( R0 , R4.L ) (V); +R1.L = EXPADJ( R1 , R4.L ) (V); +R2.L = EXPADJ( R2 , R4.L ) (V); +R3.L = EXPADJ( R3 , R4.L ) (V); +R4.L = EXPADJ( R4 , R4.L ) (V); +R5.L = EXPADJ( R5 , R4.L ) (V); +R6.L = EXPADJ( R6 , R4.L ) (V); +R7.L = EXPADJ( R7 , R4.L ) (V); +CHECKREG r0, 0x0C0000C0; +CHECKREG r1, 0x0C0100C0; +CHECKREG r2, 0x0C0200C0; +CHECKREG r3, 0x0C0300C0; +CHECKREG r4, 0x0C0400C0; +CHECKREG r5, 0x0C0500C0; +CHECKREG r6, 0x0C0600C0; +CHECKREG r7, 0x0C0700C0; + +imm32 r0, 0xa00100d0; +imm32 r1, 0x000100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa00500d0; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0.L = EXPADJ( R0 , R5.L ) (V); +R1.L = EXPADJ( R1 , R5.L ) (V); +R2.L = EXPADJ( R2 , R5.L ) (V); +R3.L = EXPADJ( R3 , R5.L ) (V); +R4.L = EXPADJ( R4 , R5.L ) (V); +R5.L = EXPADJ( R5 , R5.L ) (V); +R6.L = EXPADJ( R6 , R5.L ) (V); +R7.L = EXPADJ( R7 , R5.L ) (V); +CHECKREG r0, 0xA00100D0; +CHECKREG r1, 0x000100D0; +CHECKREG r2, 0xA00200D0; +CHECKREG r3, 0xA00300D0; +CHECKREG r4, 0xA00400D0; +CHECKREG r5, 0xA00500D0; +CHECKREG r6, 0xA00600D0; +CHECKREG r7, 0xA00700D0; + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R0.L = EXPADJ( R0 , R6.L ) (V); +R1.L = EXPADJ( R1 , R6.L ) (V); +R2.L = EXPADJ( R2 , R6.L ) (V); +R3.L = EXPADJ( R3 , R6.L ) (V); +R4.L = EXPADJ( R4 , R6.L ) (V); +R5.L = EXPADJ( R5 , R6.L ) (V); +R6.L = EXPADJ( R6 , R6.L ) (V); +R7.L = EXPADJ( R7 , R6.L ) (V); +CHECKREG r0, 0xB0010000; +CHECKREG r1, 0xB0010000; +CHECKREG r2, 0xB0020000; +CHECKREG r3, 0xB0030000; +CHECKREG r4, 0xB0040000; +CHECKREG r5, 0xB0050000; +CHECKREG r6, 0xB0060000; +CHECKREG r7, 0xB0070000; + +imm32 r0, 0xd00102e7; +imm32 r1, 0xd00104e7; +imm32 r2, 0xd00206e7; +imm32 r3, 0xd00308e7; +imm32 r4, 0xd0040ae7; +imm32 r5, 0xd0050ce7; +imm32 r6, 0xd0060ee7; +imm32 r7, 0xd00707e7; +R0.L = EXPADJ( R0 , R7.L ) (V); +R1.L = EXPADJ( R1 , R7.L ) (V); +R2.L = EXPADJ( R2 , R7.L ) (V); +R3.L = EXPADJ( R3 , R7.L ) (V); +R4.L = EXPADJ( R4 , R7.L ) (V); +R5.L = EXPADJ( R5 , R7.L ) (V); +R6.L = EXPADJ( R6 , R7.L ) (V); +R7.L = EXPADJ( R7 , R7.L ) (V); +CHECKREG r0, 0xD0010001; +CHECKREG r1, 0xD0010001; +CHECKREG r2, 0xD0020001; +CHECKREG r3, 0xD0030001; +CHECKREG r4, 0xD0040001; +CHECKREG r5, 0xD0050001; +CHECKREG r6, 0xD0060001; +CHECKREG r7, 0xD0070001; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_fdepx.s b/sim/testsuite/sim/bfin/c_dsp32shift_fdepx.s new file mode 100644 index 0000000..5e843fe --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_fdepx.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_fdepx/c_dsp32shift_fdepx.dsp +// Spec Reference: dsp32shift fdep x +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = DEPOSIT( R1, R0 ); +R2 = DEPOSIT( R2, R0 ); +R3 = DEPOSIT( R3, R0 ); +R4 = DEPOSIT( R4, R0 ) (X); +R5 = DEPOSIT( R5, R0 ); +R6 = DEPOSIT( R6, R0 ); +R7 = DEPOSIT( R7, R0 ) (X); +R0 = DEPOSIT( R0, R0 ); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x01000800; +CHECKREG r2, 0x08200802; +CHECKREG r3, 0x08030802; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x08000504; +CHECKREG r6, 0x08000866; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09000002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = DEPOSIT( R0, R1 ); +R2 = DEPOSIT( R2, R1 ); +R3 = DEPOSIT( R3, R1 ); +R4 = DEPOSIT( R4, R1 ); +R5 = DEPOSIT( R5, R1 ) (X); +R6 = DEPOSIT( R6, R1 ); +R7 = DEPOSIT( R7, R1 ) (X); +R1 = DEPOSIT( R1, R1 ); +CHECKREG r0, 0x0900D000; +CHECKREG r1, 0x09000000; +CHECKREG r2, 0x09000000; +CHECKREG r3, 0x09100000; +CHECKREG r4, 0x09020004; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x09000404; +CHECKREG r7, 0x00000000; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a000010; +imm32 r4, 0x0a00e004; +imm32 r5, 0x0a00e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0a00e007; +R0 = DEPOSIT( R0, R2 ); +R1 = DEPOSIT( R1, R2 ); +R3 = DEPOSIT( R3, R2 ); +R4 = DEPOSIT( R4, R2 ); +R5 = DEPOSIT( R5, R2 ); +R6 = DEPOSIT( R6, R2 ); +R7 = DEPOSIT( R7, R2 ); +R2 = DEPOSIT( R2, R2 ); +CHECKREG r0, 0x0A008A00; +CHECKREG r1, 0x0A008A00; +CHECKREG r2, 0x0A000A00; +CHECKREG r3, 0x0A000A00; +CHECKREG r4, 0x0A008A00; +CHECKREG r5, 0x0A008A00; +CHECKREG r6, 0x0A008A00; +CHECKREG r7, 0x0A008A00; + +imm32 r0, 0x4b00f001; +imm32 r1, 0x5b00f001; +imm32 r2, 0x6b00f002; +imm32 r3, 0x9f000010; +imm32 r4, 0x8b00f004; +imm32 r5, 0x0900f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x0b0af007; +R0 = DEPOSIT( R0, R3 ); +R1 = DEPOSIT( R1, R3 ); +R2 = DEPOSIT( R2, R3 ) (X); +R4 = DEPOSIT( R4, R3 ); +R5 = DEPOSIT( R5, R3 ); +R6 = DEPOSIT( R6, R3 ) (X); +R7 = DEPOSIT( R7, R3 ); +R3 = DEPOSIT( R3, R3 ); +CHECKREG r0, 0x4B009F00; +CHECKREG r1, 0x5B009F00; +CHECKREG r2, 0xFFFF9F00; +CHECKREG r3, 0x9F009F00; +CHECKREG r4, 0x8B009F00; +CHECKREG r5, 0x09009F00; +CHECKREG r6, 0xFFFF9F00; +CHECKREG r7, 0x0B0A9F00; + +imm32 r0, 0x0c0000c0; +imm32 r1, 0x0c0100c0; +imm32 r2, 0x0c0200c0; +imm32 r3, 0x0c0300c0; +imm32 r4, 0x0c04000c; +imm32 r5, 0x0c0500c0; +imm32 r6, 0x0c0600c0; +imm32 r7, 0x0c0700c0; +R0 = DEPOSIT( R0, R4 ); +R1 = DEPOSIT( R1, R4 ); +R2 = DEPOSIT( R2, R4 ); +R3 = DEPOSIT( R3, R4 ); +R5 = DEPOSIT( R5, R4 ) (X); +R6 = DEPOSIT( R6, R4 ); +R7 = DEPOSIT( R7, R4 ); +R4 = DEPOSIT( R4, R4 ); +CHECKREG r0, 0x0C000C04; +CHECKREG r1, 0x0C010C04; +CHECKREG r2, 0x0C020C04; +CHECKREG r3, 0x0C030C04; +CHECKREG r4, 0x0C040C04; +CHECKREG r5, 0xFFFFFC04; +CHECKREG r6, 0x0C060C04; +CHECKREG r7, 0x0C070C04; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R5 = DEPOSIT( R0, R5 ); +R6 = DEPOSIT( R1, R5 ) (X); +R7 = DEPOSIT( R2, R5 ); +R0 = DEPOSIT( R3, R5 ); +R1 = DEPOSIT( R4, R5 ) (X); +R2 = DEPOSIT( R6, R5 ); +R3 = DEPOSIT( R7, R5 ); +R4 = DEPOSIT( R5, R5 ); +CHECKREG r0, 0xA00300C1; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0xA00200C1; +CHECKREG r4, 0xA0010081; +CHECKREG r5, 0xA0010085; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0xA00200C1; + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0x00237809; +imm32 r7, 0xb0070000; +R0 = DEPOSIT( R0, R6 ); +R1 = DEPOSIT( R1, R6 ); +R2 = DEPOSIT( R2, R6 ); +R3 = DEPOSIT( R3, R6 ) (X); +R4 = DEPOSIT( R4, R6 ); +R5 = DEPOSIT( R5, R6 ); +R6 = DEPOSIT( R6, R6 ); +R7 = DEPOSIT( R7, R6 ); +CHECKREG r0, 0x23010000; +CHECKREG r1, 0x23010000; +CHECKREG r2, 0x2302000F; +CHECKREG r3, 0x23030000; +CHECKREG r4, 0x23040000; +CHECKREG r5, 0x23050000; +CHECKREG r6, 0x23237809; +CHECKREG r7, 0x23070000; + +imm32 r0, 0xd00100e0; +imm32 r1, 0xd00100e0; +imm32 r2, 0xd00200e0; +imm32 r3, 0xd00300e0; +imm32 r4, 0xd00400e0; +imm32 r5, 0xd00500e0; +imm32 r6, 0xd00600e0; +imm32 r7, 0x00012345; +R1 = DEPOSIT( R0, R7 ); +R2 = DEPOSIT( R1, R7 ); +R3 = DEPOSIT( R2, R7 ); +R4 = DEPOSIT( R3, R7 ); +R5 = DEPOSIT( R4, R7 ) (X); +R6 = DEPOSIT( R5, R7 ); +R7 = DEPOSIT( R6, R7 ) (X); +R0 = DEPOSIT( R7, R7 ); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0xD0010008; +CHECKREG r2, 0xD0010008; +CHECKREG r3, 0xD0010008; +CHECKREG r4, 0xD0010008; +CHECKREG r5, 0x00000008; +CHECKREG r6, 0x00000008; +CHECKREG r7, 0x00000008; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_fextx.s b/sim/testsuite/sim/bfin/c_dsp32shift_fextx.s new file mode 100644 index 0000000..13ba90c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_fextx.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_fextx/c_dsp32shift_fextx.dsp +// Spec Reference: dsp32shift fext x +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = EXTRACT( R1, R0.L ) (Z); +R2 = EXTRACT( R2, R0.L ) (Z); +R3 = EXTRACT( R3, R0.L ) (Z); +R4 = EXTRACT( R4, R0.L ) (X); +R5 = EXTRACT( R5, R0.L ) (Z); +R6 = EXTRACT( R6, R0.L ) (Z); +R7 = EXTRACT( R7, R0.L ) (X); +R0 = EXTRACT( R0, R0.L ) (Z); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0xFFFFFFFF; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09000002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = EXTRACT( R0, R1.L ) (Z); +R2 = EXTRACT( R2, R1.L ) (Z); +R3 = EXTRACT( R3, R1.L ) (Z); +R4 = EXTRACT( R4, R1.L ) (Z); +R5 = EXTRACT( R5, R1.L ) (X); +R6 = EXTRACT( R6, R1.L ) (Z); +R7 = EXTRACT( R7, R1.L ) (X); +R1 = EXTRACT( R1, R1.L ) (Z); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0xFFFFFFFF; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a000010; +imm32 r4, 0x0a00e004; +imm32 r5, 0x0a00e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0a00e007; +R0 = EXTRACT( R0, R2.L ) (Z); +R1 = EXTRACT( R1, R2.L ) (Z); +R3 = EXTRACT( R3, R2.L ) (Z); +R4 = EXTRACT( R4, R2.L ) (Z); +R5 = EXTRACT( R5, R2.L ) (Z); +R6 = EXTRACT( R6, R2.L ) (Z); +R7 = EXTRACT( R7, R2.L ) (Z); +R2 = EXTRACT( R2, R2.L ) (Z); +CHECKREG r0, 0x00006001; +CHECKREG r1, 0x00006001; +CHECKREG r2, 0x0000000F; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00006004; +CHECKREG r5, 0x00006005; +CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00006007; + +imm32 r0, 0x0b00f001; +imm32 r1, 0x0b00f001; +imm32 r2, 0x0b00f002; +imm32 r3, 0x0b000010; +imm32 r4, 0x0b00f004; +imm32 r5, 0x0b00f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x0b00f007; +R0 = EXTRACT( R0, R3.L ) (Z); +R1 = EXTRACT( R1, R3.L ) (Z); +R2 = EXTRACT( R2, R3.L ) (X); +R4 = EXTRACT( R4, R3.L ) (Z); +R5 = EXTRACT( R5, R3.L ) (Z); +R6 = EXTRACT( R6, R3.L ) (X); +R7 = EXTRACT( R7, R3.L ) (Z); +R3 = EXTRACT( R3, R3.L ) (Z); +CHECKREG r0, 0x0000F001; +CHECKREG r1, 0x0000F001; +CHECKREG r2, 0xFFFFF002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000F004; +CHECKREG r5, 0x0000F005; +CHECKREG r6, 0xFFFFF006; +CHECKREG r7, 0x0000F007; + +imm32 r0, 0x0c0000c0; +imm32 r1, 0x0c0100c0; +imm32 r2, 0x0c0200c0; +imm32 r3, 0x0c0300c0; +imm32 r4, 0x0c04000c; +imm32 r5, 0x0c0500c0; +imm32 r6, 0x0c0600c0; +imm32 r7, 0x0c0700c0; +R0 = EXTRACT( R0, R4.L ) (Z); +R1 = EXTRACT( R1, R4.L ) (Z); +R2 = EXTRACT( R2, R4.L ) (Z); +R3 = EXTRACT( R3, R4.L ) (Z); +R5 = EXTRACT( R5, R4.L ) (X); +R6 = EXTRACT( R6, R4.L ) (Z); +R7 = EXTRACT( R7, R4.L ) (Z); +R4 = EXTRACT( R4, R4.L ) (Z); +CHECKREG r0, 0x000000C0; +CHECKREG r1, 0x000000C0; +CHECKREG r2, 0x000000C0; +CHECKREG r3, 0x000000C0; +CHECKREG r4, 0x0000000C; +CHECKREG r5, 0x000000C0; +CHECKREG r6, 0x000000C0; +CHECKREG r7, 0x000000C0; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = EXTRACT( R0, R5.L ) (Z); +R1 = EXTRACT( R1, R5.L ) (X); +R2 = EXTRACT( R2, R5.L ) (Z); +R3 = EXTRACT( R3, R5.L ) (Z); +R4 = EXTRACT( R4, R5.L ) (X); +R6 = EXTRACT( R6, R5.L ) (Z); +R7 = EXTRACT( R7, R5.L ) (Z); +R5 = EXTRACT( R5, R5.L ) (Z); +CHECKREG r0, 0x00000050; +CHECKREG r1, 0xFFFFFFD1; +CHECKREG r2, 0x00000050; +CHECKREG r3, 0x00000050; +CHECKREG r4, 0xFFFFFFD0; +CHECKREG r5, 0x00000007; +CHECKREG r6, 0x00000050; +CHECKREG r7, 0x00000050; + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060009; +imm32 r7, 0xb0070000; +R0 = EXTRACT( R0, R6.L ) (Z); +R1 = EXTRACT( R1, R6.L ) (Z); +R2 = EXTRACT( R2, R6.L ) (Z); +R3 = EXTRACT( R3, R6.L ) (X); +R4 = EXTRACT( R4, R6.L ) (Z); +R5 = EXTRACT( R5, R6.L ) (Z); +R6 = EXTRACT( R6, R6.L ) (Z); +R7 = EXTRACT( R7, R6.L ) (Z); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x0000000F; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000009; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xd00100e0; +imm32 r1, 0xd00100e0; +imm32 r2, 0xd00200e0; +imm32 r3, 0xd00300e0; +imm32 r4, 0xd00400e0; +imm32 r5, 0xd00500e0; +imm32 r6, 0xd00600e0; +imm32 r7, 0xd0070023; +R1 = EXTRACT( R0, R7.L ) (Z); +R2 = EXTRACT( R1, R7.L ) (Z); +R3 = EXTRACT( R2, R7.L ) (Z); +R4 = EXTRACT( R3, R7.L ) (Z); +R5 = EXTRACT( R4, R7.L ) (X); +R6 = EXTRACT( R5, R7.L ) (Z); +R7 = EXTRACT( R6, R7.L ) (X); +R0 = EXTRACT( R7, R7.L ) (Z); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lf.s b/sim/testsuite/sim/bfin/c_dsp32shift_lf.s new file mode 100644 index 0000000..88ee774 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_lf.s @@ -0,0 +1,422 @@ +//Original:/testcases/core/c_dsp32shift_lf/c_dsp32shift_lf.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : mix data, count (+)= (half reg) +// d_reg = lshift (d BY d_lo) +// Rx by RLx +imm32 r0, 0x01210001; +imm32 r1, 0x12315678; +imm32 r2, 0x23416789; +imm32 r3, 0x3451789a; +imm32 r4, 0x856189ab; +imm32 r5, 0x96719abc; +imm32 r6, 0xa781abcd; +imm32 r7, 0xb891bcde; +R7 = LSHIFT R0 BY R0.L; +R6 = LSHIFT R1 BY R0.L; +R0 = LSHIFT R2 BY R0.L; +R1 = LSHIFT R3 BY R0.L; +R2 = LSHIFT R4 BY R0.L; +R3 = LSHIFT R5 BY R0.L; +R4 = LSHIFT R6 BY R0.L; +R5 = LSHIFT R7 BY R0.L; +CHECKREG r0, 0x4682CF12; +CHECKREG r1, 0xE2680000; +CHECKREG r2, 0x26AC0000; +CHECKREG r3, 0x6AF00000; +CHECKREG r4, 0xB3C00000; +CHECKREG r5, 0x00080000; +CHECKREG r6, 0x2462ACF0; +CHECKREG r7, 0x02420002; + +imm32 r0, 0x01220002; +imm32 r1, 0x12325678; +imm32 r2, 0x23426789; +imm32 r3, 0x3452789a; +imm32 r4, 0x956289ab; +imm32 r5, 0xa6729abc; +imm32 r6, 0xb782abcd; +imm32 r7, 0xc892bcde; +R1.L = 2; +R3 = LSHIFT R0 BY R1.L; +R4 = LSHIFT R1 BY R1.L; +R5 = LSHIFT R2 BY R1.L; +R6 = LSHIFT R3 BY R1.L; +R7 = LSHIFT R4 BY R1.L; +R0 = LSHIFT R5 BY R1.L; +R1 = LSHIFT R6 BY R1.L; +R2 = LSHIFT R7 BY R1.L; +CHECKREG r0, 0x34267890; +CHECKREG r1, 0x48800080; +CHECKREG r2, 0x23200020; +CHECKREG r3, 0x04880008; +CHECKREG r4, 0x48C80008; +CHECKREG r5, 0x8D099E24; +CHECKREG r6, 0x12200020; +CHECKREG r7, 0x23200020; + +imm32 r0, 0x01230002; +imm32 r1, 0x12335678; +imm32 r2, 0x23436789; +imm32 r3, 0x3453789a; +imm32 r4, 0x456389ab; +imm32 r5, 0x56739abc; +imm32 r6, 0x6783abcd; +imm32 r7, 0x789abcde; +R2 = 14; +R0 = LSHIFT R4 BY R2.L; +R1 = LSHIFT R5 BY R2.L; +R2 = LSHIFT R6 BY R2.L; +R3 = LSHIFT R7 BY R2.L; +CHECKREG r0, 0xE26AC000; +CHECKREG r1, 0xE6AF0000; +CHECKREG r2, 0xEAF34000; +CHECKREG r3, 0x789ABCDE; + +imm32 r0, 0x01240002; +imm32 r1, 0x12345678; +imm32 r2, 0x23446789; +imm32 r3, 0x3454789a; +imm32 r4, 0xa56489ab; +imm32 r5, 0xb6749abc; +imm32 r6, 0xc784abcd; +imm32 r7, 0xd894bcde; +R3.L = 15; +R4 = LSHIFT R0 BY R3.L; +R5 = LSHIFT R1 BY R3.L; +R6 = LSHIFT R2 BY R3.L; +R7 = LSHIFT R3 BY R3.L; +R0 = LSHIFT R4 BY R3.L; +R1 = LSHIFT R5 BY R3.L; +R2 = LSHIFT R6 BY R3.L; +R3 = LSHIFT R7 BY R3.L; +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0xC0000000; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x2B3C0000; +CHECKREG r6, 0x33C48000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x01250002; +imm32 r1, 0x12355678; +imm32 r2, 0x23456789; +imm32 r3, 0x3455789a; +imm32 r4, 0x456589ab; +imm32 r5, 0x56759abc; +imm32 r6, 0x6785abcd; +imm32 r7, 0x7895bcde; +R4.L = -1; +R7 = LSHIFT R0 BY R4.L; +R6 = LSHIFT R1 BY R4.L; +R5 = LSHIFT R2 BY R4.L; +R3 = LSHIFT R4 BY R4.L; +R2 = LSHIFT R5 BY R4.L; +R1 = LSHIFT R6 BY R4.L; +R0 = LSHIFT R7 BY R4.L; +R4 = LSHIFT R3 BY R4.L; +CHECKREG r0, 0x00494000; +CHECKREG r1, 0x048D559E; +CHECKREG r2, 0x08D159E2; +CHECKREG r3, 0x22B2FFFF; +CHECKREG r4, 0x11597FFF; +CHECKREG r5, 0x11A2B3C4; +CHECKREG r6, 0x091AAB3C; +CHECKREG r7, 0x00928001; + +imm32 r0, 0x01260002; +imm32 r1, 0x82365678; +imm32 r2, 0x93466789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56689ab; +imm32 r5, 0xc6769abc; +imm32 r6, 0xd786abcd; +imm32 r7, 0xe896bcde; +R5.L = -8; +R6 = LSHIFT R0 BY R5.L; +R7 = LSHIFT R1 BY R5.L; +R0 = LSHIFT R2 BY R5.L; +R1 = LSHIFT R3 BY R5.L; +R2 = LSHIFT R4 BY R5.L; +R3 = LSHIFT R5 BY R5.L; +R4 = LSHIFT R6 BY R5.L; +R5 = LSHIFT R7 BY R5.L; +CHECKREG r0, 0x00934667; +CHECKREG r1, 0x00A45678; +CHECKREG r2, 0x00B56689; +CHECKREG r3, 0x00C676FF; +CHECKREG r4, 0x00000126; +CHECKREG r5, 0x00008236; +CHECKREG r6, 0x00012600; +CHECKREG r7, 0x00823656; + +imm32 r0, 0x01270002; +imm32 r1, 0x12375678; +imm32 r2, 0x23476789; +imm32 r3, 0x3457789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56779abc; +imm32 r6, 0x6787abcd; +imm32 r7, 0x7897bcde; +R6.L = -15; +R7 = LSHIFT R0 BY R6.L; +R0 = LSHIFT R1 BY R6.L; +R1 = LSHIFT R2 BY R6.L; +R2 = LSHIFT R3 BY R6.L; +R3 = LSHIFT R4 BY R6.L; +R4 = LSHIFT R5 BY R6.L; +R5 = LSHIFT R6 BY R6.L; +R6 = LSHIFT R7 BY R6.L; +CHECKREG r0, 0x0000246E; +CHECKREG r1, 0x0000468E; +CHECKREG r2, 0x000068AE; +CHECKREG r3, 0x00008ACF; +CHECKREG r4, 0x0000ACEF; +CHECKREG r5, 0x0000CF0F; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x0000024E; + +imm32 r0, 0x01280002; +imm32 r1, 0x82385678; +imm32 r2, 0x93486789; +imm32 r3, 0xa458789a; +imm32 r4, 0xb56889ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd788abcd; +imm32 r7, 0xe898bcde; +R7.L = -16; +R0 = LSHIFT R0 BY R7.L; +R1 = LSHIFT R1 BY R7.L; +R2 = LSHIFT R2 BY R7.L; +R3 = LSHIFT R3 BY R7.L; +R4 = LSHIFT R4 BY R7.L; +R5 = LSHIFT R5 BY R7.L; +R6 = LSHIFT R6 BY R7.L; +R7 = LSHIFT R7 BY R7.L; +CHECKREG r0, 0x00000128; +CHECKREG r1, 0x00008238; +CHECKREG r2, 0x00009348; +CHECKREG r3, 0x0000A458; +CHECKREG r4, 0x0000B568; +CHECKREG r5, 0x0000C678; +CHECKREG r6, 0x0000D788; +CHECKREG r7, 0x0000E898; + +imm32 r0, 0x81290002; +imm32 r1, 0x92395678; +imm32 r2, 0xa3496789; +imm32 r3, 0xb459789a; +imm32 r4, 0xc56989ab; +imm32 r5, 0xd6799abc; +imm32 r6, 0xe789abcd; +imm32 r7, 0xf899bcde; +R0.L = 4; +//r0 = lshift (r0 by rl0); +R1 = LSHIFT R1 BY R0.L; +R2 = LSHIFT R2 BY R0.L; +R3 = LSHIFT R3 BY R0.L; +R4 = LSHIFT R4 BY R0.L; +R5 = LSHIFT R5 BY R0.L; +R6 = LSHIFT R6 BY R0.L; +R7 = LSHIFT R7 BY R0.L; +CHECKREG r1, 0x23956780; +CHECKREG r2, 0x34967890; +CHECKREG r3, 0x459789A0; +CHECKREG r4, 0x56989AB0; +CHECKREG r5, 0x6799ABC0; +CHECKREG r6, 0x789ABCD0; +CHECKREG r7, 0x899BCDE0; + +imm32 r0, 0x012a0002; +imm32 r1, 0x123a5678; +imm32 r2, 0x234a6789; +imm32 r3, 0x345a789a; +imm32 r4, 0x456a89ab; +imm32 r5, 0x567a9abc; +imm32 r6, 0x678aabcd; +imm32 r7, 0xf89abcde; +R1.L = 2; +R7 = LSHIFT R0 BY R1.L; +R6 = LSHIFT R1 BY R1.L; +R5 = LSHIFT R2 BY R1.L; +R4 = LSHIFT R3 BY R1.L; +R3 = LSHIFT R4 BY R1.L; +R2 = LSHIFT R5 BY R1.L; +R0 = LSHIFT R6 BY R1.L; +R1 = LSHIFT R7 BY R1.L; +CHECKREG r0, 0x23A00020; +CHECKREG r1, 0x12A00020; +CHECKREG r2, 0x34A67890; +CHECKREG r3, 0x45A789A0; +CHECKREG r4, 0xD169E268; +CHECKREG r5, 0x8D299E24; +CHECKREG r6, 0x48E80008; +CHECKREG r7, 0x04A80008; + + +imm32 r0, 0x012b0002; +imm32 r1, 0x123b5678; +imm32 r2, 0x234b6789; +imm32 r3, 0x345b789a; +imm32 r4, 0x456b89ab; +imm32 r5, 0x567b9abc; +imm32 r6, 0x678babcd; +imm32 r7, 0x789bbcde; +R2.L = 15; +R0 = LSHIFT R0 BY R2.L; +R1 = LSHIFT R1 BY R2.L; +R3 = LSHIFT R3 BY R2.L; +R4 = LSHIFT R4 BY R2.L; +R5 = LSHIFT R5 BY R2.L; +R6 = LSHIFT R6 BY R2.L; +R7 = LSHIFT R7 BY R2.L; +R2 = LSHIFT R2 BY R2.L; +CHECKREG r0, 0x80010000; +CHECKREG r1, 0xAB3C0000; +CHECKREG r2, 0x80078000; +CHECKREG r3, 0xBC4D0000; +CHECKREG r4, 0xC4D58000; +CHECKREG r5, 0xCD5E0000; +CHECKREG r6, 0xD5E68000; +CHECKREG r7, 0xDE6F0000; + +imm32 r0, 0x012c0002; +imm32 r1, 0x123c5678; +imm32 r2, 0x234c6789; +imm32 r3, 0x345c789a; +imm32 r4, 0x456c89ab; +imm32 r5, 0x567c9abc; +imm32 r6, 0x678cabcd; +imm32 r7, 0x789cbcde; +R3.L = 16; +R0 = LSHIFT R0 BY R3.L; +R1 = LSHIFT R1 BY R3.L; +R2 = LSHIFT R2 BY R3.L; +R4 = LSHIFT R4 BY R3.L; +R5 = LSHIFT R5 BY R3.L; +R6 = LSHIFT R6 BY R3.L; +R7 = LSHIFT R7 BY R3.L; +R3 = LSHIFT R3 BY R3.L; +CHECKREG r0, 0x00020000; +CHECKREG r1, 0x56780000; +CHECKREG r2, 0x67890000; +CHECKREG r3, 0x00100000; +CHECKREG r4, 0x89AB0000; +CHECKREG r5, 0x9ABC0000; +CHECKREG r6, 0xABCD0000; +CHECKREG r7, 0xBCDE0000; + +imm32 r0, 0x012d0002; +imm32 r1, 0x123d5678; +imm32 r2, 0x234d6789; +imm32 r3, 0x345d789a; +imm32 r4, 0x456d89ab; +imm32 r5, 0x567d9abc; +imm32 r6, 0x678dabcd; +imm32 r7, 0x789dbcde; +R4.L = -9; +R7 = LSHIFT R0 BY R4.L; +R0 = LSHIFT R1 BY R4.L; +R1 = LSHIFT R2 BY R4.L; +R2 = LSHIFT R3 BY R4.L; +//r4 = lshift (r4 by rl4); +R3 = LSHIFT R5 BY R4.L; +R5 = LSHIFT R6 BY R4.L; +R6 = LSHIFT R7 BY R4.L; +CHECKREG r0, 0x00091EAB; +CHECKREG r1, 0x0011A6B3; +CHECKREG r2, 0x001A2EBC; +CHECKREG r3, 0x002B3ECD; +CHECKREG r4, 0x456DFFF7; +CHECKREG r5, 0x0033C6D5; +CHECKREG r6, 0x0000004B; +CHECKREG r7, 0x00009680; + +imm32 r0, 0x012e0002; +imm32 r1, 0x123e5678; +imm32 r2, 0x234e6789; +imm32 r3, 0x345e789a; +imm32 r4, 0x456e89ab; +imm32 r5, 0x567e9abc; +imm32 r6, 0x678eabcd; +imm32 r7, 0x789ebcde; +R5.L = -14; +R0 = LSHIFT R0 BY R5.L; +R1 = LSHIFT R1 BY R5.L; +R2 = LSHIFT R2 BY R5.L; +R3 = LSHIFT R3 BY R5.L; +R4 = LSHIFT R4 BY R5.L; +//r5 = lshift (r5 by rl5); +R6 = LSHIFT R6 BY R5.L; +R7 = LSHIFT R7 BY R5.L; +CHECKREG r0, 0x000004B8; +CHECKREG r1, 0x000048F9; +CHECKREG r2, 0x00008D39; +CHECKREG r3, 0x0000D179; +CHECKREG r4, 0x000115BA; +CHECKREG r5, 0x567EFFF2; +CHECKREG r6, 0x00019E3A; +CHECKREG r7, 0x0001E27A; + + +imm32 r0, 0x012f0002; +imm32 r1, 0x623f5678; +imm32 r2, 0x734f6789; +imm32 r3, 0x845f789a; +imm32 r4, 0x956f89ab; +imm32 r5, 0xa67f9abc; +imm32 r6, 0xc78fabcd; +imm32 r7, 0xd89fbcde; +R6.L = -15; +R0 = LSHIFT R0 BY R6.L; +R1 = LSHIFT R1 BY R6.L; +R2 = LSHIFT R2 BY R6.L; +R3 = LSHIFT R3 BY R6.L; +R4 = LSHIFT R4 BY R6.L; +R5 = LSHIFT R5 BY R6.L; +//r6 = lshift (r6 by rl6); +R7 = LSHIFT R7 BY R6.L; +CHECKREG r0, 0x0000025E; +CHECKREG r1, 0x0000C47E; +CHECKREG r2, 0x0000E69E; +CHECKREG r3, 0x000108BE; +CHECKREG r4, 0x00012ADF; +CHECKREG r5, 0x00014CFF; +CHECKREG r6, 0xC78FFFF1; +CHECKREG r7, 0x0001B13F; + +imm32 r0, 0x71230072; +imm32 r1, 0x82345678; +imm32 r2, 0x93456779; +imm32 r3, 0xa456787a; +imm32 r4, 0xb567897b; +imm32 r5, 0xc6789a7c; +imm32 r6, 0x6789ab7d; +imm32 r7, 0x789abc7e; +R7.L = -16; +R0 = LSHIFT R0 BY R7.L; +R1 = LSHIFT R1 BY R7.L; +R2 = LSHIFT R2 BY R7.L; +R3 = LSHIFT R3 BY R7.L; +R4 = LSHIFT R4 BY R7.L; +R5 = LSHIFT R5 BY R7.L; +R6 = LSHIFT R6 BY R7.L; +R7 = LSHIFT R7 BY R7.L; +CHECKREG r0, 0x00007123; +CHECKREG r1, 0x00008234; +CHECKREG r2, 0x00009345; +CHECKREG r3, 0x0000A456; +CHECKREG r4, 0x0000B567; +CHECKREG r5, 0x0000C678; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x0000789A; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_ln.s b/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_ln.s new file mode 100644 index 0000000..df47e33 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_ln.s @@ -0,0 +1,422 @@ +//Original:/testcases/core/c_dsp32shift_lhalf_ln/c_dsp32shift_lhalf_ln.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : neg data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R0.L = LSHIFT R0.L BY R0.L; +R1.L = LSHIFT R1.L BY R0.L; +R2.L = LSHIFT R2.L BY R0.L; +R3.L = LSHIFT R3.L BY R0.L; +R4.L = LSHIFT R4.L BY R0.L; +R5.L = LSHIFT R5.L BY R0.L; +R6.L = LSHIFT R6.L BY R0.L; +R7.L = LSHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000c001; +CHECKREG r2, 0x0000c002; +CHECKREG r3, 0x0000c003; +CHECKREG r4, 0x0000c004; +CHECKREG r5, 0x0000c005; +CHECKREG r6, 0x0000c006; +CHECKREG r7, 0x0000c007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R0.L = LSHIFT R0.L BY R1.L; +//rl1 = lshift (rl1 by rl1); +R2.L = LSHIFT R2.L BY R1.L; +R3.L = LSHIFT R3.L BY R1.L; +R4.L = LSHIFT R4.L BY R1.L; +R5.L = LSHIFT R5.L BY R1.L; +R6.L = LSHIFT R6.L BY R1.L; +R7.L = LSHIFT R7.L BY R1.L; +//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */ +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x0000a004; +CHECKREG r3, 0x0000c006; +CHECKREG r4, 0x0000e008; +CHECKREG r5, 0x0000800a; +CHECKREG r6, 0x0000a00c; +CHECKREG r7, 0x0000c00e; + + +imm32 r0, 0x0000c001; +imm32 r1, 0x0000d001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = LSHIFT R0.L BY R2.L; +R1.L = LSHIFT R1.L BY R2.L; +//rl2 = lshift (rl2 by rl2); +R3.L = LSHIFT R3.L BY R2.L; +R4.L = LSHIFT R4.L BY R2.L; +R5.L = LSHIFT R5.L BY R2.L; +R6.L = LSHIFT R6.L BY R2.L; +R7.L = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00009001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000b002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000f007; +R0.L = LSHIFT R0.L BY R3.L; +R1.L = LSHIFT R1.L BY R3.L; +R2.L = LSHIFT R2.L BY R3.L; +//rl3 = lshift (rl3 by rl3); +R4.L = LSHIFT R4.L BY R3.L; +R5.L = LSHIFT R5.L BY R3.L; +R6.L = LSHIFT R6.L BY R3.L; +R7.L = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = lshft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R0.L; +R1.L = LSHIFT R1.H BY R0.L; +R2.L = LSHIFT R2.H BY R0.L; +R3.L = LSHIFT R3.H BY R0.L; +R4.L = LSHIFT R4.H BY R0.L; +R5.L = LSHIFT R5.H BY R0.L; +R6.L = LSHIFT R6.H BY R0.L; +R7.L = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R0.L = LSHIFT R0.H BY R1.L; +//rl1 = lshift (rh1 by rl1); +R2.L = LSHIFT R2.H BY R1.L; +R3.L = LSHIFT R3.H BY R1.L; +R4.L = LSHIFT R4.H BY R1.L; +R5.L = LSHIFT R5.H BY R1.L; +R6.L = LSHIFT R6.H BY R1.L; +R7.L = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x90012002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x90022004; +CHECKREG r3, 0x90032006; +CHECKREG r4, 0x90042008; +CHECKREG r5, 0x9005200a; +CHECKREG r6, 0x9006200c; +CHECKREG r7, 0x9007200e; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0xa0018000; +CHECKREG r1, 0xa0018000; +CHECKREG r2, 0xa002000f; +CHECKREG r3, 0xa0038000; +CHECKREG r4, 0xa0040000; +CHECKREG r5, 0xa0058000; +CHECKREG r6, 0xa0060000; +CHECKREG r7, 0xa0078000; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc0070007; +R0.L = LSHIFT R0.H BY R3.L; +R1.L = LSHIFT R1.H BY R3.L; +R2.L = LSHIFT R2.H BY R3.L; +//rl3 = lshift (rh3 by rl3); +R4.L = LSHIFT R4.H BY R3.L; +R5.L = LSHIFT R5.H BY R3.L; +R6.L = LSHIFT R6.H BY R3.L; +R7.L = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0xc0010000; +CHECKREG r1, 0xc0010000; +CHECKREG r2, 0xc0020000; +CHECKREG r3, 0xc0030010; +CHECKREG r4, 0xc0040000; +CHECKREG r5, 0xc0050000; +CHECKREG r6, 0xc0060000; +CHECKREG r7, 0xc0070000; + +// d_hi = lshft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R0.L; +R1.H = LSHIFT R1.L BY R0.L; +R2.H = LSHIFT R2.L BY R0.L; +R3.H = LSHIFT R3.L BY R0.L; +R4.H = LSHIFT R4.L BY R0.L; +R5.H = LSHIFT R5.L BY R0.L; +R6.H = LSHIFT R6.L BY R0.L; +R7.H = LSHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R0.H = LSHIFT R0.L BY R1.L; +R1.H = LSHIFT R1.L BY R1.L; +R2.H = LSHIFT R2.L BY R1.L; +R3.H = LSHIFT R3.L BY R1.L; +R4.H = LSHIFT R4.L BY R1.L; +R5.H = LSHIFT R5.L BY R1.L; +R6.H = LSHIFT R6.L BY R1.L; +R7.H = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0xa002d001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0xa004d002; +CHECKREG r3, 0xa006d003; +CHECKREG r4, 0xa008d004; +CHECKREG r5, 0xa00ad005; +CHECKREG r6, 0xa00cd006; +CHECKREG r7, 0xa00ed007; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = LSHIFT R0.L BY R2.L; +R1.H = LSHIFT R1.L BY R2.L; +//rh2 = lshift (rl2 by rl2); +R3.H = LSHIFT R3.L BY R2.L; +R4.H = LSHIFT R4.L BY R2.L; +R5.H = LSHIFT R5.L BY R2.L; +R6.H = LSHIFT R6.L BY R2.L; +R7.H = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x8000e001; +CHECKREG r1, 0x8000e001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x8000e003; +CHECKREG r4, 0x0000e004; +CHECKREG r5, 0x8000e005; +CHECKREG r6, 0x0000e006; +CHECKREG r7, 0x8000e007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.H = LSHIFT R0.L BY R3.L; +R1.H = LSHIFT R1.L BY R3.L; +R2.H = LSHIFT R2.L BY R3.L; +R3.H = LSHIFT R3.L BY R3.L; +R4.H = LSHIFT R4.L BY R3.L; +R5.H = LSHIFT R5.L BY R3.L; +R6.H = LSHIFT R6.L BY R3.L; +R7.H = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x0000f001; +CHECKREG r1, 0x0000f001; +CHECKREG r2, 0x0000f002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x0000f004; +CHECKREG r5, 0x0000f005; +CHECKREG r6, 0x0000f006; +CHECKREG r7, 0x0000f007; + +// d_lo = lshft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R0.L; +R1.H = LSHIFT R1.H BY R0.L; +R2.H = LSHIFT R2.H BY R0.L; +R3.H = LSHIFT R3.H BY R0.L; +R4.H = LSHIFT R4.H BY R0.L; +R5.H = LSHIFT R5.H BY R0.L; +R6.H = LSHIFT R6.H BY R0.L; +R7.H = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.H = LSHIFT R0.H BY R1.L; +R1.H = LSHIFT R1.H BY R1.L; +R2.H = LSHIFT R2.H BY R1.L; +R3.H = LSHIFT R3.H BY R1.L; +R4.H = LSHIFT R4.H BY R1.L; +R5.H = LSHIFT R5.H BY R1.L; +R6.H = LSHIFT R6.H BY R1.L; +R7.H = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x40020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x40040000; +CHECKREG r3, 0x40060000; +CHECKREG r4, 0x40080000; +CHECKREG r5, 0x400a0000; +CHECKREG r6, 0x400c0000; +CHECKREG r7, 0x400e0000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0xb0018000; +CHECKREG r1, 0xb0018000; +CHECKREG r2, 0xb002000f; +CHECKREG r3, 0xb0038000; +CHECKREG r4, 0xb0040000; +CHECKREG r5, 0xb0058000; +CHECKREG r6, 0xb0060000; +CHECKREG r7, 0xb0078000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R0.H = LSHIFT R0.H BY R3.L; +R1.H = LSHIFT R1.H BY R3.L; +R2.H = LSHIFT R2.H BY R3.L; +R3.H = LSHIFT R3.H BY R3.L; +R4.H = LSHIFT R4.H BY R3.L; +R5.H = LSHIFT R5.H BY R3.L; +R6.H = LSHIFT R6.H BY R3.L; +R7.H = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_lp.s b/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_lp.s new file mode 100644 index 0000000..6000715 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_lp.s @@ -0,0 +1,422 @@ +//Original:/testcases/core/c_dsp32shift_lhalf_lp/c_dsp32shift_lhalf_lp.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = LSHIFT R0.L BY R0.L; +R1.L = LSHIFT R1.L BY R0.L; +R2.L = LSHIFT R2.L BY R0.L; +R3.L = LSHIFT R3.L BY R0.L; +R4.L = LSHIFT R4.L BY R0.L; +R5.L = LSHIFT R5.L BY R0.L; +R6.L = LSHIFT R6.L BY R0.L; +R7.L = LSHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = LSHIFT R0.L BY R1.L; +//rl1 = lshift (rl1 by rl1); +R2.L = LSHIFT R2.L BY R1.L; +R3.L = LSHIFT R3.L BY R1.L; +R4.L = LSHIFT R4.L BY R1.L; +R5.L = LSHIFT R5.L BY R1.L; +R6.L = LSHIFT R6.L BY R1.L; +R7.L = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0x00000002; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000006; +CHECKREG r4, 0x00000008; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x0000000c; +CHECKREG r7, 0x0000000e; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = LSHIFT R0.L BY R2.L; +R1.L = LSHIFT R1.L BY R2.L; +//rl2 = lshift (rl2 by rl2); +R3.L = LSHIFT R3.L BY R2.L; +R4.L = LSHIFT R4.L BY R2.L; +R5.L = LSHIFT R5.L BY R2.L; +R6.L = LSHIFT R6.L BY R2.L; +R7.L = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x00008000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00008000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00008000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00008000; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.L = LSHIFT R0.L BY R3.L; +R1.L = LSHIFT R1.L BY R3.L; +R2.L = LSHIFT R2.L BY R3.L; +//rl3 = lshift (rl3 by rl3); +R4.L = LSHIFT R4.L BY R3.L; +R5.L = LSHIFT R5.L BY R3.L; +R6.L = LSHIFT R6.L BY R3.L; +R7.L = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R0.L; +R1.L = LSHIFT R1.H BY R0.L; +R2.L = LSHIFT R2.H BY R0.L; +R3.L = LSHIFT R3.H BY R0.L; +R4.L = LSHIFT R4.H BY R0.L; +R5.L = LSHIFT R5.H BY R0.L; +R6.L = LSHIFT R6.H BY R0.L; +R7.L = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R1.L; +//rl1 = lshift (rh1 by rl1); +R2.L = LSHIFT R2.H BY R1.L; +R3.L = LSHIFT R3.H BY R1.L; +R4.L = LSHIFT R4.H BY R1.L; +R5.L = LSHIFT R5.H BY R1.L; +R6.L = LSHIFT R6.H BY R1.L; +R7.L = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x00010002; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020004; +CHECKREG r3, 0x00030006; +CHECKREG r4, 0x00040008; +CHECKREG r5, 0x0005000a; +CHECKREG r6, 0x0006000c; +CHECKREG r7, 0x0007000e; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0x00018000; +CHECKREG r1, 0x00018000; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00038000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00058000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x00010001; +imm32 r1, 0x00010001; +imm32 r2, 0x00020002; +imm32 r3, 0x00030010; +imm32 r4, 0x00040004; +imm32 r5, 0x00050005; +imm32 r6, 0x00060006; +imm32 r7, 0x00070007; +R0.L = LSHIFT R0.H BY R3.L; +R1.L = LSHIFT R1.H BY R3.L; +R2.L = LSHIFT R2.H BY R3.L; +//rl3 = lshift (rh3 by rl3); +R4.L = LSHIFT R4.H BY R3.L; +R5.L = LSHIFT R5.H BY R3.L; +R6.L = LSHIFT R6.H BY R3.L; +R7.L = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030010; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R0.L; +R1.H = LSHIFT R1.L BY R0.L; +R2.H = LSHIFT R2.L BY R0.L; +R3.H = LSHIFT R3.L BY R0.L; +R4.H = LSHIFT R4.L BY R0.L; +R5.H = LSHIFT R5.L BY R0.L; +R6.H = LSHIFT R6.L BY R0.L; +R7.H = LSHIFT R7.L BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R1.L; +R1.H = LSHIFT R1.L BY R1.L; +R2.H = LSHIFT R2.L BY R1.L; +R3.H = LSHIFT R3.L BY R1.L; +R4.H = LSHIFT R4.L BY R1.L; +R5.H = LSHIFT R5.L BY R1.L; +R6.H = LSHIFT R6.L BY R1.L; +R7.H = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0x00020001; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040002; +CHECKREG r3, 0x00060003; +CHECKREG r4, 0x00080004; +CHECKREG r5, 0x000a0005; +CHECKREG r6, 0x000c0006; +CHECKREG r7, 0x000e0007; + + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000000f; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R2.L; +R1.H = LSHIFT R1.L BY R2.L; +//rh2 = lshift (rl2 by rl2); +R3.H = LSHIFT R3.L BY R2.L; +R4.H = LSHIFT R4.L BY R2.L; +R5.H = LSHIFT R5.L BY R2.L; +R6.H = LSHIFT R6.L BY R2.L; +R7.H = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x80000001; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x80000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x80000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x80000007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000010; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R3.L; +R1.H = LSHIFT R1.L BY R3.L; +R2.H = LSHIFT R2.L BY R3.L; +R3.H = LSHIFT R3.L BY R3.L; +R4.H = LSHIFT R4.L BY R3.L; +R5.H = LSHIFT R5.L BY R3.L; +R6.H = LSHIFT R6.L BY R3.L; +R7.H = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R0.L; +R1.H = LSHIFT R1.H BY R0.L; +R2.H = LSHIFT R2.H BY R0.L; +R3.H = LSHIFT R3.H BY R0.L; +R4.H = LSHIFT R4.H BY R0.L; +R5.H = LSHIFT R5.H BY R0.L; +R6.H = LSHIFT R6.H BY R0.L; +R7.H = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R1.L; +R1.H = LSHIFT R1.H BY R1.L; +R2.H = LSHIFT R2.H BY R1.L; +R3.H = LSHIFT R3.H BY R1.L; +R4.H = LSHIFT R4.H BY R1.L; +R5.H = LSHIFT R5.H BY R1.L; +R6.H = LSHIFT R6.H BY R1.L; +R7.H = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x00020000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00040000; +CHECKREG r3, 0x00060000; +CHECKREG r4, 0x00080000; +CHECKREG r5, 0x000a0000; +CHECKREG r6, 0x000c0000; +CHECKREG r7, 0x000e0000; + + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x0002000f; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0x00018000; +CHECKREG r1, 0x00018000; +CHECKREG r2, 0x0002000f; +CHECKREG r3, 0x00038000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00058000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00078000; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030010; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R3.L; +R1.H = LSHIFT R1.H BY R3.L; +R2.H = LSHIFT R2.H BY R3.L; +R3.H = LSHIFT R3.H BY R3.L; +R4.H = LSHIFT R4.H BY R3.L; +R5.H = LSHIFT R5.H BY R3.L; +R6.H = LSHIFT R6.H BY R3.L; +R7.H = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rn.s b/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rn.s new file mode 100644 index 0000000..a5b6563 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rn.s @@ -0,0 +1,425 @@ +//Original:/testcases/core/c_dsp32shift_lhalf_rn/c_dsp32shift_lhalf_rn.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +//rl0 = lshift (rl0 by rl0); +R1.L = LSHIFT R1.L BY R0.L; +R2.L = LSHIFT R2.L BY R0.L; +R3.L = LSHIFT R3.L BY R0.L; +R4.L = LSHIFT R4.L BY R0.L; +R5.L = LSHIFT R5.L BY R0.L; +R6.L = LSHIFT R6.L BY R0.L; +R7.L = LSHIFT R7.L BY R0.L; +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00004000; +CHECKREG r2, 0x00004001; +CHECKREG r3, 0x00004001; +CHECKREG r4, 0x00004002; +CHECKREG r5, 0x00004002; +CHECKREG r6, 0x00004003; +CHECKREG r7, 0x00004003; + +imm32 r0, 0x00008001; +R1.L = -1; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = LSHIFT R0.L BY R1.L; +//rl1 = lshift (rl1 by rl1); +R2.L = LSHIFT R2.L BY R1.L; +R3.L = LSHIFT R3.L BY R1.L; +R4.L = LSHIFT R4.L BY R1.L; +R5.L = LSHIFT R5.L BY R1.L; +R6.L = LSHIFT R6.L BY R1.L; +R7.L = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0x00004000; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00004001; +CHECKREG r3, 0x00004001; +CHECKREG r4, 0x00004002; +CHECKREG r5, 0x00004002; +CHECKREG r6, 0x00004003; +CHECKREG r7, 0x00004003; + + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +R2.L = -15; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = LSHIFT R0.L BY R2.L; +R1.L = LSHIFT R1.L BY R2.L; +//rl2 = lshift (rl2 by rl2); +R3.L = LSHIFT R3.L BY R2.L; +R4.L = LSHIFT R4.L BY R2.L; +R5.L = LSHIFT R5.L BY R2.L; +R6.L = LSHIFT R6.L BY R2.L; +R7.L = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +R3.L = -16; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = LSHIFT R0.L BY R3.L; +R1.L = LSHIFT R1.L BY R3.L; +R2.L = LSHIFT R2.L BY R3.L; +//rl3 = lshift (rl3 by rl3); +R4.L = LSHIFT R4.L BY R3.L; +R5.L = LSHIFT R5.L BY R3.L; +R6.L = LSHIFT R6.L BY R3.L; +R7.L = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = LSHIFT R0.H BY R0.L; +R1.L = LSHIFT R1.H BY R0.L; +R2.L = LSHIFT R2.H BY R0.L; +R3.L = LSHIFT R3.H BY R0.L; +R4.L = LSHIFT R4.H BY R0.L; +R5.L = LSHIFT R5.H BY R0.L; +R6.L = LSHIFT R6.H BY R0.L; +R7.L = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x80018001; +CHECKREG r2, 0x80028002; +CHECKREG r3, 0x80038003; +CHECKREG r4, 0x80048004; +CHECKREG r5, 0x80058005; +CHECKREG r6, 0x80068006; +CHECKREG r7, 0x80078007; + +imm32 r0, 0x80010000; +R1.L = -1; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = LSHIFT R0.H BY R1.L; +//rl1 = lshift (rh1 by rl1); +R2.L = LSHIFT R2.H BY R1.L; +R3.L = LSHIFT R3.H BY R1.L; +R4.L = LSHIFT R4.H BY R1.L; +R5.L = LSHIFT R5.H BY R1.L; +R6.L = LSHIFT R6.H BY R1.L; +R7.L = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x80014000; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x80024001; +CHECKREG r3, 0x80034001; +CHECKREG r4, 0x80044002; +CHECKREG r5, 0x80054002; +CHECKREG r6, 0x80064003; +CHECKREG r7, 0x80074003; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +R2.L = -15; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0xa0010001; +CHECKREG r1, 0xa0010001; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0xa0030001; +CHECKREG r4, 0xa0040001; +CHECKREG r5, 0xa0050001; +CHECKREG r6, 0xa0060001; +CHECKREG r7, 0xa0070001; + +imm32 r0, 0xb0010001; +imm32 r1, 0xb0010001; +imm32 r2, 0xb0020002; +R3.L = -16; +imm32 r4, 0xb0040004; +imm32 r5, 0xb0050005; +imm32 r6, 0xb0060006; +imm32 r7, 0xb0070007; +R0.L = LSHIFT R0.H BY R3.L; +R1.L = LSHIFT R1.H BY R3.L; +R2.L = LSHIFT R2.H BY R3.L; +//rl3 = lshift (rh3 by rl3); +R4.L = LSHIFT R4.H BY R3.L; +R5.L = LSHIFT R5.H BY R3.L; +R6.L = LSHIFT R6.H BY R3.L; +R7.L = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0xb0010000; +CHECKREG r1, 0xb0010000; +CHECKREG r2, 0xb0020000; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0xb0040000; +CHECKREG r5, 0xb0050000; +CHECKREG r6, 0xb0060000; +CHECKREG r7, 0xb0070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R4.L; +R1.H = LSHIFT R1.L BY R4.L; +R2.H = LSHIFT R2.L BY R4.L; +R3.H = LSHIFT R3.L BY R4.L; +//rh4 = lshift (rl4 by rl4); +R5.H = LSHIFT R5.L BY R4.L; +R6.H = LSHIFT R6.L BY R4.L; +R7.H = LSHIFT R7.L BY R4.L; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +R5.L = -1; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = LSHIFT R0.L BY R5.L; +R1.H = LSHIFT R1.L BY R5.L; +R2.H = LSHIFT R2.L BY R5.L; +R3.H = LSHIFT R3.L BY R5.L; +R4.H = LSHIFT R4.L BY R5.L; +//rh5 = lshift (rl5 by rl5); +R6.H = LSHIFT R6.L BY R5.L; +R7.H = LSHIFT R7.L BY R5.L; +CHECKREG r0, 0x40008001; +CHECKREG r1, 0x40008001; +CHECKREG r2, 0x40018002; +CHECKREG r3, 0x40018003; +CHECKREG r4, 0x40028004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0x40038006; +CHECKREG r7, 0x40038007; + + +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009004; +imm32 r5, 0x00009005; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = LSHIFT R0.L BY R6.L; +R1.H = LSHIFT R1.L BY R6.L; +R2.H = LSHIFT R2.L BY R6.L; +R3.H = LSHIFT R3.L BY R6.L; +R4.H = LSHIFT R4.L BY R6.L; +R5.H = LSHIFT R5.L BY R6.L; +//rh6 = lshift (rl6 by rl6); +R7.H = LSHIFT R7.L BY R6.L; +CHECKREG r0, 0x00019001; +CHECKREG r1, 0x00019001; +CHECKREG r2, 0x00019002; +CHECKREG r3, 0x00019003; +CHECKREG r4, 0x00019004; +CHECKREG r5, 0x00019005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00019007; + +imm32 r0, 0x0000a001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000a002; +imm32 r3, 0x0000a003; +imm32 r4, 0x0000a004; +imm32 r5, 0x0000a005; +imm32 r6, 0x0000a006; +R7.L = -16; +R0.H = LSHIFT R0.L BY R7.L; +R1.H = LSHIFT R1.L BY R7.L; +R2.H = LSHIFT R2.L BY R7.L; +R3.H = LSHIFT R3.L BY R7.L; +R4.H = LSHIFT R4.L BY R7.L; +R5.H = LSHIFT R5.L BY R7.L; +R6.H = LSHIFT R6.L BY R7.L; +R7.H = LSHIFT R7.L BY R7.L; +CHECKREG r0, 0x0000a001; +CHECKREG r1, 0x0000a001; +CHECKREG r2, 0x0000a002; +CHECKREG r3, 0x0000a003; +CHECKREG r4, 0x0000a004; +CHECKREG r5, 0x0000a005; +CHECKREG r6, 0x0000a006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +R4.L = -1; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = LSHIFT R0.H BY R4.L; +R1.H = LSHIFT R1.H BY R4.L; +R2.H = LSHIFT R2.H BY R4.L; +R3.H = LSHIFT R3.H BY R4.L; +//rh4 = lshift (rh4 by rl4); +R5.H = LSHIFT R5.H BY R4.L; +R6.H = LSHIFT R6.H BY R4.L; +R7.H = LSHIFT R7.H BY R4.L; +CHECKREG r0, 0x40000000; +CHECKREG r1, 0x40000000; +CHECKREG r2, 0x40010000; +CHECKREG r3, 0x40010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0x40020000; +CHECKREG r6, 0x40030000; +CHECKREG r7, 0x40030000; + +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +R5.L = -1; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = LSHIFT R0.H BY R5.L; +R1.H = LSHIFT R1.H BY R5.L; +R2.H = LSHIFT R2.H BY R5.L; +R3.H = LSHIFT R3.H BY R5.L; +R4.H = LSHIFT R4.H BY R5.L; +//rh5 = lshift (rh5 by rl5); +R6.H = LSHIFT R6.H BY R5.L; +R7.H = LSHIFT R7.H BY R5.L; +CHECKREG r0, 0x40000000; +CHECKREG r1, 0x40000000; +CHECKREG r2, 0x40010000; +CHECKREG r3, 0x40010000; +CHECKREG r4, 0x40020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0x40030000; +CHECKREG r7, 0x40030000; + + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030000; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = LSHIFT R0.H BY R6.L; +R1.L = LSHIFT R1.H BY R6.L; +R2.L = LSHIFT R2.H BY R6.L; +R3.L = LSHIFT R3.H BY R6.L; +R4.L = LSHIFT R4.H BY R6.L; +R5.L = LSHIFT R5.H BY R6.L; +//rl6 = lshift (rh6 by rl6); +R7.L = LSHIFT R7.H BY R6.L; +CHECKREG r0, 0xd0010001; +CHECKREG r1, 0xd0010001; +CHECKREG r2, 0xd0020001; +CHECKREG r3, 0xd0030001; +CHECKREG r4, 0xd0040001; +CHECKREG r5, 0xd0050001; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0xd0070001; + +imm32 r0, 0xe0010000; +imm32 r1, 0xe0010000; +imm32 r2, 0xe0020000; +imm32 r3, 0xe0030000; +imm32 r4, 0xe0040000; +imm32 r5, 0xe0050000; +imm32 r6, 0xe0060000; +R7.L = -16; +R0.H = LSHIFT R0.H BY R7.L; +R1.H = LSHIFT R1.H BY R7.L; +R2.H = LSHIFT R2.H BY R7.L; +R3.H = LSHIFT R3.H BY R7.L; +R4.H = LSHIFT R4.H BY R7.L; +R5.H = LSHIFT R5.H BY R7.L; +R6.H = LSHIFT R6.H BY R7.L; +//rh7 = lshift (rh7 by rl7); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +//CHECKREG r7, -16; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rp.s b/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rp.s new file mode 100644 index 0000000..45fa6a0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_lhalf_rp.s @@ -0,0 +1,423 @@ +//Original:/testcases/core/c_dsp32shift_lhalf_rp/c_dsp32shift_lhalf_rp.dsp +// Spec Reference: dsp32shift lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +//rl0 = lshift (rl0 by rl0); +R1.L = LSHIFT R1.L BY R0.L; +R2.L = LSHIFT R2.L BY R0.L; +R3.L = LSHIFT R3.L BY R0.L; +R4.L = LSHIFT R4.L BY R0.L; +R5.L = LSHIFT R5.L BY R0.L; +R6.L = LSHIFT R6.L BY R0.L; +R7.L = LSHIFT R7.L BY R0.L; +//CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000002; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x00001001; +R1.L = -1; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = LSHIFT R0.L BY R1.L; +//rl1 = lshift (rl1 by rl1); +R2.L = LSHIFT R2.L BY R1.L; +R3.L = LSHIFT R3.L BY R1.L; +R4.L = LSHIFT R4.L BY R1.L; +R5.L = LSHIFT R5.L BY R1.L; +R6.L = LSHIFT R6.L BY R1.L; +R7.L = LSHIFT R7.L BY R1.L; +CHECKREG r0, 0x00000800; +//CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00001001; +CHECKREG r3, 0x00001801; +CHECKREG r4, 0x00002002; +CHECKREG r5, 0x00002802; +CHECKREG r6, 0x00003003; +CHECKREG r7, 0x00003803; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +R2.L = -15; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = LSHIFT R0.L BY R2.L; +R1.L = LSHIFT R1.L BY R2.L; +//rl2 = lshift (rl2 by rl2); +R3.L = LSHIFT R3.L BY R2.L; +R4.L = LSHIFT R4.L BY R2.L; +R5.L = LSHIFT R5.L BY R2.L; +R6.L = LSHIFT R6.L BY R2.L; +R7.L = LSHIFT R7.L BY R2.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +//CHECKREG r2, 0x0000000f; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r2, 0x00002002; +R3.L = -16; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +imm32 r7, 0x00007007; +R0.L = LSHIFT R0.L BY R3.L; +R1.L = LSHIFT R1.L BY R3.L; +R2.L = LSHIFT R2.L BY R3.L; +//rl3 = lshift (rl3 by rl3); +R4.L = LSHIFT R4.L BY R3.L; +R5.L = LSHIFT R5.L BY R3.L; +R6.L = LSHIFT R6.L BY R3.L; +R7.L = LSHIFT R7.L BY R3.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +//CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = LSHIFT R0.H BY R0.L; +R1.L = LSHIFT R1.H BY R0.L; +R2.L = LSHIFT R2.H BY R0.L; +R3.L = LSHIFT R3.H BY R0.L; +R4.L = LSHIFT R4.H BY R0.L; +R5.L = LSHIFT R5.H BY R0.L; +R6.L = LSHIFT R6.H BY R0.L; +R7.L = LSHIFT R7.H BY R0.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x10010000; +R1.L = -1; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = LSHIFT R0.H BY R1.L; +//rl1 = lshift (rh1 by rl1); +R2.L = LSHIFT R2.H BY R1.L; +R3.L = LSHIFT R3.H BY R1.L; +R4.L = LSHIFT R4.H BY R1.L; +R5.L = LSHIFT R5.H BY R1.L; +R6.L = LSHIFT R6.H BY R1.L; +R7.L = LSHIFT R7.H BY R1.L; +CHECKREG r0, 0x10010800; +//CHECKREG r1, 0x00010001; +CHECKREG r2, 0x20021001; +CHECKREG r3, 0x30031801; +CHECKREG r4, 0x40042002; +CHECKREG r5, 0x50052802; +CHECKREG r6, 0x60063003; +CHECKREG r7, 0x70073803; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +R2.L = -15; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = LSHIFT R0.H BY R2.L; +R1.L = LSHIFT R1.H BY R2.L; +//rl2 = lshift (rh2 by rl2); +R3.L = LSHIFT R3.H BY R2.L; +R4.L = LSHIFT R4.H BY R2.L; +R5.L = LSHIFT R5.H BY R2.L; +R6.L = LSHIFT R6.H BY R2.L; +R7.L = LSHIFT R7.H BY R2.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +//CHECKREG r2, 0x2002000f; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010001; +imm32 r1, 0x10010001; +imm32 r2, 0x20020002; +R3.L = -16; +imm32 r4, 0x40040004; +imm32 r5, 0x50050005; +imm32 r6, 0x60060006; +imm32 r7, 0x70070007; +R0.L = LSHIFT R0.H BY R3.L; +R1.L = LSHIFT R1.H BY R3.L; +R2.L = LSHIFT R2.H BY R3.L; +//rl3 = lshift (rh3 by rl3); +R4.L = LSHIFT R4.H BY R3.L; +R5.L = LSHIFT R5.H BY R3.L; +R6.L = LSHIFT R6.H BY R3.L; +R7.L = LSHIFT R7.H BY R3.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +//CHECKREG r3, 0x30030010; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000000; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R4.L; +R1.H = LSHIFT R1.L BY R4.L; +R2.H = LSHIFT R2.L BY R4.L; +R3.H = LSHIFT R3.L BY R4.L; +//rh4 = lshift (rl4 by rl4); +R5.H = LSHIFT R5.L BY R4.L; +R6.H = LSHIFT R6.L BY R4.L; +R7.H = LSHIFT R7.L BY R4.L; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +//CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +R5.L = -1; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = LSHIFT R0.L BY R5.L; +R1.H = LSHIFT R1.L BY R5.L; +R2.H = LSHIFT R2.L BY R5.L; +R3.H = LSHIFT R3.L BY R5.L; +R4.H = LSHIFT R4.L BY R5.L; +//rh5 = lshift (rl5 by rl5); +R6.H = LSHIFT R6.L BY R5.L; +R7.H = LSHIFT R7.L BY R5.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00010002; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +//CHECKREG r5, 0x00020005; +CHECKREG r6, 0x00030006; +CHECKREG r7, 0x00030007; + + +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r1, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +R6.L = -15; +imm32 r7, 0x00007007; +R0.H = LSHIFT R0.L BY R6.L; +R1.H = LSHIFT R1.L BY R6.L; +R2.H = LSHIFT R2.L BY R6.L; +R3.H = LSHIFT R3.L BY R6.L; +R4.H = LSHIFT R4.L BY R6.L; +R5.H = LSHIFT R5.L BY R6.L; +//rh6 = lshift (rl6 by rl6); +R7.H = LSHIFT R7.L BY R6.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +//CHECKREG r6, 0x00006006; +CHECKREG r7, 0x00007007; + +imm32 r0, 0x00001001; +imm32 r1, 0x00002001; +imm32 r2, 0x00002002; +imm32 r3, 0x00003003; +imm32 r4, 0x00004004; +imm32 r5, 0x00005005; +imm32 r6, 0x00006006; +R7.L = -16; +R0.H = LSHIFT R0.L BY R7.L; +R1.H = LSHIFT R1.L BY R7.L; +R2.H = LSHIFT R2.L BY R7.L; +R3.H = LSHIFT R3.L BY R7.L; +R4.H = LSHIFT R4.L BY R7.L; +R5.H = LSHIFT R5.L BY R7.L; +R6.H = LSHIFT R6.L BY R7.L; +R7.H = LSHIFT R7.L BY R7.L; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002001; +CHECKREG r2, 0x00002002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +CHECKREG r6, 0x00006006; +//CHECKREG r7, 0x00007007; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00010000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +R4.L = -1; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = LSHIFT R0.H BY R4.L; +R1.H = LSHIFT R1.H BY R4.L; +R2.H = LSHIFT R2.H BY R4.L; +R3.H = LSHIFT R3.H BY R4.L; +//rh4 = lshift (rh4 by rl4); +R5.H = LSHIFT R5.H BY R4.L; +R6.H = LSHIFT R6.H BY R4.L; +R7.H = LSHIFT R7.H BY R4.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00010000; +CHECKREG r3, 0x00010000; +//CHECKREG r4, 0x00020000; +CHECKREG r5, 0x00020000; +CHECKREG r6, 0x00030000; +CHECKREG r7, 0x00030000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +R5.L = -1; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.H = LSHIFT R0.H BY R5.L; +R1.H = LSHIFT R1.H BY R5.L; +R2.H = LSHIFT R2.H BY R5.L; +R3.H = LSHIFT R3.H BY R5.L; +R4.H = LSHIFT R4.H BY R5.L; +//rh5 = lshift (rh5 by rl5); +R6.H = LSHIFT R6.H BY R5.L; +R7.H = LSHIFT R7.H BY R5.L; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x08000000; +CHECKREG r2, 0x10010000; +CHECKREG r3, 0x18010000; +CHECKREG r4, 0x20020000; +//CHECKREG r5, 0x28020000; +CHECKREG r6, 0x30030000; +CHECKREG r7, 0x38030000; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +R6.L = -15; +imm32 r7, 0x70070000; +R0.L = LSHIFT R0.H BY R6.L; +R1.L = LSHIFT R1.H BY R6.L; +R2.L = LSHIFT R2.H BY R6.L; +R3.L = LSHIFT R3.H BY R6.L; +R4.L = LSHIFT R4.H BY R6.L; +R5.L = LSHIFT R5.H BY R6.L; +//rl6 = lshift (rh6 by rl6); +R7.L = LSHIFT R7.H BY R6.L; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +//CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r2, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +R7.L = -16; +R0.H = LSHIFT R0.H BY R7.L; +R1.H = LSHIFT R1.H BY R7.L; +R2.H = LSHIFT R2.H BY R7.L; +R3.H = LSHIFT R3.H BY R7.L; +R4.H = LSHIFT R4.H BY R7.L; +R5.H = LSHIFT R5.H BY R7.L; +R6.H = LSHIFT R6.H BY R7.L; +//rh7 = lshift (rh7 by rl7); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +//CHECKREG r7, -16; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lhh.s b/sim/testsuite/sim/bfin/c_dsp32shift_lhh.s new file mode 100644 index 0000000..4722987 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_lhh.s @@ -0,0 +1,311 @@ +//Original:/testcases/core/c_dsp32shift_lhh/c_dsp32shift_lhh.dsp +// Spec Reference: dsp32shift lshift/lshift +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift/lshift : = (half reg) +// d_reg = lshift/lshift (d BY d_lo) +// Rx by RLx +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1 = LSHIFT R0 BY R0.L (V); +R2 = LSHIFT R1 BY R0.L (V); +R3 = LSHIFT R2 BY R0.L (V); +R4 = LSHIFT R3 BY R0.L (V); +R5 = LSHIFT R4 BY R0.L (V); +R6 = LSHIFT R5 BY R0.L (V); +R7 = LSHIFT R6 BY R0.L (V); +R0 = LSHIFT R7 BY R0.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1.L = 5; +R2 = LSHIFT R0 BY R1.L (V); +R3 = LSHIFT R1 BY R1.L (V); +R4 = LSHIFT R2 BY R1.L (V); +R5 = LSHIFT R3 BY R1.L (V); +R6 = LSHIFT R4 BY R1.L (V); +R7 = LSHIFT R5 BY R1.L (V); +R0 = LSHIFT R6 BY R1.L (V); +R1 = LSHIFT R7 BY R1.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2 = 15; +R3 = LSHIFT R0 BY R2.L (V); +R4 = LSHIFT R1 BY R2.L (V); +R5 = LSHIFT R2 BY R2.L (V); +R6 = LSHIFT R3 BY R2.L (V); +R7 = LSHIFT R4 BY R2.L (V); +R0 = LSHIFT R5 BY R2.L (V); +R1 = LSHIFT R6 BY R2.L (V); +R2 = LSHIFT R7 BY R2.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R3.L = 16; +R4 = LSHIFT R0 BY R3.L (V); +R5 = LSHIFT R1 BY R3.L (V); +R6 = LSHIFT R2 BY R3.L (V); +R7 = LSHIFT R3 BY R3.L (V); +R0 = LSHIFT R4 BY R3.L (V); +R1 = LSHIFT R5 BY R3.L (V); +R2 = LSHIFT R6 BY R3.L (V); +R3 = LSHIFT R7 BY R3.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R4.L = -1; +R0 = LSHIFT R0 BY R4.L (V); +R1 = LSHIFT R1 BY R4.L (V); +R2 = LSHIFT R2 BY R4.L (V); +R3 = LSHIFT R3 BY R4.L (V); +R4 = LSHIFT R4 BY R4.L (V); +R5 = LSHIFT R5 BY R4.L (V); +R6 = LSHIFT R6 BY R4.L (V); +R7 = LSHIFT R7 BY R4.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5.L = -6; +R6 = LSHIFT R0 BY R5.L (V); +R7 = LSHIFT R1 BY R5.L (V); +R0 = LSHIFT R2 BY R5.L (V); +R1 = LSHIFT R3 BY R5.L (V); +R2 = LSHIFT R4 BY R5.L (V); +R3 = LSHIFT R5 BY R5.L (V); +R4 = LSHIFT R6 BY R5.L (V); +R5 = LSHIFT R7 BY R5.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R6.L = -15; +R7 = LSHIFT R0 BY R6.L (V); +R0 = LSHIFT R1 BY R6.L (V); +R1 = LSHIFT R2 BY R6.L (V); +R2 = LSHIFT R3 BY R6.L (V); +R3 = LSHIFT R4 BY R6.L (V); +R4 = LSHIFT R5 BY R6.L (V); +R5 = LSHIFT R6 BY R6.L (V); +R6 = LSHIFT R7 BY R6.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7.L = -16; +R0 = LSHIFT R0 BY R7.L (V); +R1 = LSHIFT R1 BY R7.L (V); +R2 = LSHIFT R2 BY R7.L (V); +R3 = LSHIFT R3 BY R7.L (V); +R4 = LSHIFT R4 BY R7.L (V); +R5 = LSHIFT R5 BY R7.L (V); +R6 = LSHIFT R6 BY R7.L (V); +R7 = LSHIFT R7 BY R7.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0.L = 4; +//r0 = lshift/lshift (r0 by rl0); +R1 = LSHIFT R1 BY R0.L (V); +R2 = LSHIFT R2 BY R0.L (V); +R3 = LSHIFT R3 BY R0.L (V); +R4 = LSHIFT R4 BY R0.L (V); +R5 = LSHIFT R5 BY R0.L (V); +R6 = LSHIFT R6 BY R0.L (V); +R7 = LSHIFT R7 BY R0.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R1.L = 6; +R0 = LSHIFT R0 BY R1.L (V); +//r1 = lshift/lshift (r1 by rl1); +R2 = LSHIFT R2 BY R1.L (V); +R3 = LSHIFT R3 BY R1.L (V); +R4 = LSHIFT R4 BY R1.L (V); +R5 = LSHIFT R5 BY R1.L (V); +R6 = LSHIFT R6 BY R1.L (V); +R7 = LSHIFT R7 BY R1.L (V); + + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R2.L = 15; +R0 = LSHIFT R0 BY R2.L (V); +R1 = LSHIFT R1 BY R2.L (V); +//r2 = lshift/lshift (r2 by rl2); +R3 = LSHIFT R3 BY R2.L (V); +R4 = LSHIFT R4 BY R2.L (V); +R5 = LSHIFT R5 BY R2.L (V); +R6 = LSHIFT R6 BY R2.L (V); +R7 = LSHIFT R7 BY R2.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R3.L = 16; +R0 = LSHIFT R0 BY R3.L (V); +R1 = LSHIFT R1 BY R3.L (V); +R2 = LSHIFT R2 BY R3.L (V); +//r3 = lshift/lshift (r3 by rl3); +R4 = LSHIFT R4 BY R3.L (V); +R5 = LSHIFT R5 BY R3.L (V); +R6 = LSHIFT R6 BY R3.L (V); +R7 = LSHIFT R7 BY R3.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R4.L = -9; +R0 = LSHIFT R0 BY R4.L (V); +R1 = LSHIFT R1 BY R4.L (V); +R2 = LSHIFT R2 BY R4.L (V); +R3 = LSHIFT R3 BY R4.L (V); +//r4 = lshift/lshift (r4 by rl4); +R5 = LSHIFT R5 BY R4.L (V); +R6 = LSHIFT R6 BY R4.L (V); +R7 = LSHIFT R7 BY R4.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R5.L = -14; +R0 = LSHIFT R0 BY R5.L (V); +R1 = LSHIFT R1 BY R5.L (V); +R2 = LSHIFT R2 BY R5.L (V); +R3 = LSHIFT R3 BY R5.L (V); +R4 = LSHIFT R4 BY R5.L (V); +//r5 = lshift/lshift (r5 by rl5); +R6 = LSHIFT R6 BY R5.L (V); +R7 = LSHIFT R7 BY R5.L (V); + + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R6.L = -15; +R0 = LSHIFT R0 BY R6.L (V); +R1 = LSHIFT R1 BY R6.L (V); +R2 = LSHIFT R2 BY R6.L (V); +R3 = LSHIFT R3 BY R6.L (V); +R4 = LSHIFT R4 BY R6.L (V); +R5 = LSHIFT R5 BY R6.L (V); +//r6 = lshift/lshift (r6 by rl6); +R7 = LSHIFT R7 BY R6.L (V); + +imm32 r0, 0x01230002; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7.L = -16; +R0 = LSHIFT R0 BY R7.L (V); +R1 = LSHIFT R1 BY R7.L (V); +R2 = LSHIFT R2 BY R7.L (V); +R3 = LSHIFT R3 BY R7.L (V); +R4 = LSHIFT R4 BY R7.L (V); +R5 = LSHIFT R5 BY R7.L (V); +R6 = LSHIFT R6 BY R7.L (V); +R7 = LSHIFT R7 BY R7.L (V); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_lmix.s b/sim/testsuite/sim/bfin/c_dsp32shift_lmix.s new file mode 100644 index 0000000..2a3c360 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_lmix.s @@ -0,0 +1,136 @@ +//Original:/testcases/core/c_dsp32shift_lmix/c_dsp32shift_lmix.dsp +// Spec Reference: dsp32shift lshift: mix +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// lshift : positive data, count (+)=left (half reg) +imm32 r0, 0x00010001; +imm32 r1, 1; +imm32 r2, 0x00020002; +imm32 r3, 2; +R4.H = LSHIFT R0.H BY R1.L; +R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x00020002 */ +R5.H = LSHIFT R2.H BY R3.L; +R5.L = LSHIFT R2.L BY R3.L; /* r5 = 0x00080008 */ +R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */ +R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */ +CHECKREG r4, 0x00020002; +CHECKREG r5, 0x00080008; +CHECKREG r6, 0x00020002; +CHECKREG r7, 0x00080008; + +// lshift : (full reg) +imm32 r1, 3; +imm32 r3, 4; +R6 = LSHIFT R0 BY R1.L; /* r6 = 0x00080010 */ +R7 = LSHIFT R2 BY R3.L; +CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ +CHECKREG r7, 0x00200020; + +A0 = 0; +A0.L = R0.L; +A0.H = R0.H; +A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00080008 */ +R5 = A0.w; /* r5 = 0x00080008 */ +CHECKREG r5, 0x00080008; + +imm32 r4, 0x30000003; +imm32 r1, 1; +R6 = LSHIFT R4 BY R1.L; /* r5 = 0x60000006 */ +imm32 r1, 2; +R7 = LSHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */ +CHECKREG r6, 0x60000006; +CHECKREG r7, 0xc000000c; + + +// lshift : count (-)=right (half reg) +imm32 r0, 0x10001000; +imm32 r1, -1; +imm32 r2, 0x10001000; +imm32 r3, -2; +R4.H = LSHIFT R0.H BY R1.L; +R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x08000800 */ +R5.H = LSHIFT R2.H BY R3.L; +R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x04000400 */ +R6 = LSHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */ +R7 = LSHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */ +CHECKREG r4, 0x08000800; +CHECKREG r5, 0x04000400; +CHECKREG r6, 0x08000800; +CHECKREG r7, 0x04000400; + +// lshift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = LSHIFT R0 BY R1.L; /* r6 = 0x02000200 */ +R7 = LSHIFT R2 BY R3.L; /* r7 = 0x01000100 */ +CHECKREG r6, 0x02000200; +CHECKREG r7, 0x01000100; + +// NEGATIVE +// lshift : NEGATIVE data, count (+)=left (half reg) +imm32 r0, 0xc00f800f; +imm32 r1, 1; +imm32 r2, 0xe00fe00f; +imm32 r3, 2; +R4.H = LSHIFT R0.H BY R1.L; +R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x801e001e */ +R5.H = LSHIFT R2.H BY R3.L; +R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x803c803c */ +CHECKREG r4, 0x801e001e; +CHECKREG r5, 0x803c803c; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +imm32 r1, 4; +imm32 r3, 5; +R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */ +R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xf80fe00f; +imm32 r2, 0xfc0fe00f; +R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */ +R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + + + +// lshift : NEGATIVE data, count (-)=right (half reg) Working ok +imm32 r0, 0x80f080f0; +imm32 r1, -1; +imm32 r2, 0x80f080f0; +imm32 r3, -2; +R4.H = LSHIFT R0.H BY R1.L; +R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x40784078 */ +R5.H = LSHIFT R2.H BY R3.L; +R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x203c203c */ +CHECKREG r4, 0x40784078; +CHECKREG r5, 0x203c203c; +R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x40784078 */ +R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x203c203c */ +CHECKREG r6, 0x40784078; +CHECKREG r7, 0x203c203c; + +// lshift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = LSHIFT R0 BY R1.L; /* r6 = 0x101e101e */ +R7 = LSHIFT R2 BY R3.L; /* r7 = 0x080f080f */ +CHECKREG r6, 0x101e101e; +CHECKREG r7, 0x080f080f; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_ones.s b/sim/testsuite/sim/bfin/c_dsp32shift_ones.s new file mode 100644 index 0000000..4097777 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_ones.s @@ -0,0 +1,214 @@ +//Original:/testcases/core/c_dsp32shift_ones/c_dsp32shift_ones.dsp +// Spec Reference: dsp32shift ones +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x88880000; +imm32 r1, 0x34560001; +imm32 r2, 0x08000002; +imm32 r3, 0x08000003; +imm32 r4, 0x08000004; +imm32 r5, 0x08000005; +imm32 r6, 0x08000006; +imm32 r7, 0x08000007; +R7.L = ONES R0; +R1.L = ONES R0; +R2.L = ONES R0; +R3.L = ONES R0; +R4.L = ONES R0; +R5.L = ONES R0; +R6.L = ONES R0; +R0.L = ONES R0; +CHECKREG r1, 0x34560004; +CHECKREG r0, 0x88880004; +CHECKREG r2, 0x08000004; +CHECKREG r3, 0x08000004; +CHECKREG r4, 0x08000004; +CHECKREG r5, 0x08000004; +CHECKREG r6, 0x08000004; +CHECKREG r7, 0x08000004; + +imm32 r0, 0x9999d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R0.L = ONES R1; +R7.L = ONES R1; +R2.L = ONES R1; +R3.L = ONES R1; +R4.L = ONES R1; +R5.L = ONES R1; +R6.L = ONES R1; +R1.L = ONES R1; +CHECKREG r0, 0x99990001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + + +imm32 r0, 0xaaaae001; +imm32 r1, 0x0000e001; +imm32 r2, 0xaaaa000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.L = ONES R2; +R1.L = ONES R2; +R7.L = ONES R2; +R3.L = ONES R2; +R4.L = ONES R2; +R5.L = ONES R2; +R6.L = ONES R2; +R2.L = ONES R2; +CHECKREG r0, 0xAAAA000C; +CHECKREG r1, 0x0000000C; +CHECKREG r2, 0xAAAA000C; +CHECKREG r3, 0x0000000C; +CHECKREG r4, 0x0000000C; +CHECKREG r5, 0x0000000C; +CHECKREG r6, 0x0000000C; +CHECKREG r7, 0x0000000C; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0xbbbb0010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = ONES R3; +R1.L = ONES R3; +R2.L = ONES R3; +R7.L = ONES R3; +R4.L = ONES R3; +R5.L = ONES R3; +R6.L = ONES R3; +R3.L = ONES R3; +CHECKREG r0, 0x0000000D; +CHECKREG r1, 0x0000000D; +CHECKREG r2, 0x0000000D; +CHECKREG r3, 0xBBBB000D; +CHECKREG r4, 0x0000000D; +CHECKREG r5, 0x0000000D; +CHECKREG r6, 0x0000000D; +CHECKREG r7, 0x0000000D; + +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0xcccc0000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = ONES R4; +R1.L = ONES R4; +R2.L = ONES R4; +R3.L = ONES R4; +R7.L = ONES R4; +R5.L = ONES R4; +R6.L = ONES R4; +R4.L = ONES R4; +CHECKREG r0, 0x00000008; +CHECKREG r1, 0x00010008; +CHECKREG r2, 0x00020008; +CHECKREG r3, 0x00030008; +CHECKREG r4, 0xCCCC0008; +CHECKREG r5, 0x00050008; +CHECKREG r6, 0x00060008; +CHECKREG r7, 0x00070008; + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xaddd0000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = ONES R5; +R1.L = ONES R5; +R2.L = ONES R5; +R3.L = ONES R5; +R4.L = ONES R5; +R7.L = ONES R5; +R6.L = ONES R5; +R5.L = ONES R5; +CHECKREG r0, 0xA001000B; +CHECKREG r1, 0xA001000B; +CHECKREG r2, 0xA002000B; +CHECKREG r3, 0xA003000B; +CHECKREG r4, 0xA004000B; +CHECKREG r5, 0xADDD000B; +CHECKREG r6, 0xA006000B; +CHECKREG r7, 0xA007000B; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xeeee0000; +imm32 r7, 0xb0070000; +R0.L = ONES R6; +R1.L = ONES R6; +R2.L = ONES R6; +R3.L = ONES R6; +R4.L = ONES R6; +R5.L = ONES R6; +R7.L = ONES R6; +R6.L = ONES R6; +CHECKREG r0, 0xB001000C; +CHECKREG r1, 0xB001000C; +CHECKREG r2, 0xB002000C; +CHECKREG r3, 0xB003000C; +CHECKREG r4, 0xB004000C; +CHECKREG r5, 0xB005000C; +CHECKREG r6, 0xEEEE000C; +CHECKREG r7, 0xB007000C; + +imm32 r0, 0xd0010001; +imm32 r1, 0xd0010002; +imm32 r2, 0xd0020003; +imm32 r3, 0xd0030014; +imm32 r4, 0xd0040005; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060007; +imm32 r7, 0xffff0000; +R0.L = ONES R7; +R1.L = ONES R7; +R2.L = ONES R7; +R3.L = ONES R7; +R4.L = ONES R7; +R5.L = ONES R7; +R6.L = ONES R7; +R7.L = ONES R7; + +CHECKREG r0, 0xD0010010; +CHECKREG r1, 0xD0010010; +CHECKREG r2, 0xD0020010; +CHECKREG r3, 0xD0030010; +CHECKREG r4, 0xD0040010; +CHECKREG r5, 0xD0050010; +CHECKREG r6, 0xD0060010; +CHECKREG r7, 0xFFFF0010; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_pack.s b/sim/testsuite/sim/bfin/c_dsp32shift_pack.s new file mode 100644 index 0000000..5647309 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_pack.s @@ -0,0 +1,411 @@ +//Original:/testcases/core/c_dsp32shift_pack/c_dsp32shift_pack.dsp +// Spec Reference: dsp32shift pack +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x01230000; +imm32 r1, 0x02345678; +imm32 r2, 0x03456789; +imm32 r3, 0x0456789a; +imm32 r4, 0x056789ab; +imm32 r5, 0x06789abc; +imm32 r6, 0x0789abcd; +imm32 r7, 0x089abcde; +R1 = PACK( R0.L , R0.L ); +R2 = PACK( R1.L , R0.H ); +R3 = PACK( R2.H , R0.L ); +R4 = PACK( R3.H , R0.H ); +R5 = PACK( R4.L , R0.L ); +R6 = PACK( R5.L , R0.H ); +R7 = PACK( R6.H , R0.L ); +R0 = PACK( R7.H , R0.H ); +CHECKREG r1, 0x00000000; +CHECKREG r0, 0x00000123; +CHECKREG r2, 0x00000123; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000123; +CHECKREG r5, 0x01230000; +CHECKREG r6, 0x00000123; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x11230001; +imm32 r1, 0x12345678; +imm32 r2, 0x1bcdef12; +imm32 r3, 0x1456789a; +imm32 r4, 0x1cdef012; +imm32 r5, 0x1456789a; +imm32 r6, 0x1789abcd; +imm32 r7, 0x189abcde; +R2 = PACK( R0.L , R1.L ); +R3 = PACK( R1.L , R1.H ); +R4 = PACK( R2.H , R1.L ); +R5 = PACK( R3.H , R1.H ); +R6 = PACK( R4.L , R1.L ); +R7 = PACK( R5.L , R1.H ); +R0 = PACK( R6.H , R1.L ); +R1 = PACK( R7.H , R1.H ); +CHECKREG r0, 0x56785678; +CHECKREG r1, 0x12341234; +CHECKREG r2, 0x00015678; +CHECKREG r3, 0x56781234; +CHECKREG r4, 0x00015678; +CHECKREG r5, 0x56781234; +CHECKREG r6, 0x56785678; +CHECKREG r7, 0x12341234; + +imm32 r0, 0x20230002; +imm32 r1, 0x21345678; +imm32 r2, 0x22456789; +imm32 r3, 0x2356789a; +imm32 r4, 0x246789ab; +imm32 r5, 0x25789abc; +imm32 r6, 0x2689abcd; +imm32 r7, 0x279abcde; +R3 = PACK( R0.L , R2.L ); +R4 = PACK( R1.L , R2.H ); +R5 = PACK( R2.H , R2.L ); +R6 = PACK( R3.H , R2.H ); +R7 = PACK( R4.L , R2.L ); +R0 = PACK( R5.L , R2.H ); +R1 = PACK( R6.H , R2.L ); +R2 = PACK( R7.H , R2.H ); +CHECKREG r0, 0x67892245; +CHECKREG r1, 0x00026789; +CHECKREG r2, 0x22452245; +CHECKREG r3, 0x00026789; +CHECKREG r4, 0x56782245; +CHECKREG r5, 0x22456789; +CHECKREG r6, 0x00022245; +CHECKREG r7, 0x22456789; + +imm32 r0, 0x31230003; +imm32 r1, 0x31345678; +imm32 r2, 0x31456789; +imm32 r3, 0x3156789a; +imm32 r4, 0x316789ab; +imm32 r5, 0x31789abc; +imm32 r6, 0x3189abcd; +imm32 r7, 0x311abcde; +R4 = PACK( R0.L , R3.L ); +R5 = PACK( R1.L , R3.H ); +R6 = PACK( R2.H , R3.L ); +R7 = PACK( R3.H , R3.H ); +R0 = PACK( R4.L , R3.L ); +R1 = PACK( R5.L , R3.H ); +R2 = PACK( R6.H , R3.L ); +R3 = PACK( R7.H , R3.H ); +CHECKREG r0, 0x789A789A; +CHECKREG r1, 0x31563156; +CHECKREG r2, 0x3145789A; +CHECKREG r3, 0x31563156; +CHECKREG r4, 0x0003789A; +CHECKREG r5, 0x56783156; +CHECKREG r6, 0x3145789A; +CHECKREG r7, 0x31563156; + +imm32 r0, 0x41230004; +imm32 r1, 0x42345678; +imm32 r2, 0x43456789; +imm32 r3, 0x4456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x46789abc; +imm32 r6, 0x4789abcd; +imm32 r7, 0x489abcde; +R0 = PACK( R0.L , R4.L ); +R1 = PACK( R1.L , R4.H ); +R2 = PACK( R2.H , R4.L ); +R3 = PACK( R3.H , R4.H ); +R4 = PACK( R4.L , R4.L ); +R5 = PACK( R5.L , R4.H ); +R6 = PACK( R6.H , R4.L ); +R7 = PACK( R7.H , R4.H ); +CHECKREG r0, 0x000489AB; +CHECKREG r1, 0x56784567; +CHECKREG r2, 0x434589AB; +CHECKREG r3, 0x44564567; +CHECKREG r4, 0x89AB89AB; +CHECKREG r5, 0x9ABC89AB; +CHECKREG r6, 0x478989AB; +CHECKREG r7, 0x489A89AB; + +imm32 r0, 0x51230005; +imm32 r1, 0x52345678; +imm32 r2, 0x53456789; +imm32 r3, 0x5456789a; +imm32 r4, 0x556789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x5789abcd; +imm32 r7, 0x589abcde; +R6 = PACK( R0.L , R5.L ); +R7 = PACK( R1.L , R5.H ); +R0 = PACK( R2.H , R5.L ); +R1 = PACK( R3.H , R5.H ); +R2 = PACK( R4.L , R5.L ); +R3 = PACK( R5.L , R5.H ); +R4 = PACK( R6.H , R5.L ); +R5 = PACK( R7.H , R5.H ); +CHECKREG r0, 0x53459ABC; +CHECKREG r1, 0x54565678; +CHECKREG r2, 0x89AB9ABC; +CHECKREG r3, 0x9ABC5678; +CHECKREG r4, 0x00059ABC; +CHECKREG r5, 0x56785678; +CHECKREG r6, 0x00059ABC; +CHECKREG r7, 0x56785678; + +imm32 r0, 0x61230006; +imm32 r1, 0x62345678; +imm32 r2, 0x63456789; +imm32 r3, 0x6456789a; +imm32 r4, 0x656789ab; +imm32 r5, 0x66789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x689abcde; +R7 = PACK( R0.L , R6.L ); +R0 = PACK( R1.L , R6.H ); +R1 = PACK( R2.H , R6.L ); +R2 = PACK( R3.H , R6.H ); +R3 = PACK( R4.L , R6.L ); +R4 = PACK( R5.L , R6.H ); +R5 = PACK( R6.H , R6.L ); +R6 = PACK( R7.H , R6.H ); +CHECKREG r0, 0x56786789; +CHECKREG r1, 0x6345ABCD; +CHECKREG r2, 0x64566789; +CHECKREG r3, 0x89ABABCD; +CHECKREG r4, 0x9ABC6789; +CHECKREG r5, 0x6789ABCD; +CHECKREG r6, 0x00066789; +CHECKREG r7, 0x0006ABCD; + +imm32 r0, 0x71230007; +imm32 r1, 0x72345678; +imm32 r2, 0x73456789; +imm32 r3, 0x7456789a; +imm32 r4, 0x756789ab; +imm32 r5, 0x76789abc; +imm32 r6, 0x7789abcd; +imm32 r7, 0x789abcde; +R0 = PACK( R0.L , R7.L ); +R1 = PACK( R1.L , R7.H ); +R2 = PACK( R2.H , R7.L ); +R3 = PACK( R3.H , R7.H ); +R4 = PACK( R4.L , R7.L ); +R5 = PACK( R5.L , R7.H ); +R6 = PACK( R6.H , R7.L ); +R7 = PACK( R7.H , R7.H ); +CHECKREG r0, 0x0007BCDE; +CHECKREG r1, 0x5678789A; +CHECKREG r2, 0x7345BCDE; +CHECKREG r3, 0x7456789A; +CHECKREG r4, 0x89ABBCDE; +CHECKREG r5, 0x9ABC789A; +CHECKREG r6, 0x7789BCDE; +CHECKREG r7, 0x789A789A; + +imm32 r0, 0x81230008; +imm32 r1, 0x82345678; +imm32 r2, 0x83456789; +imm32 r3, 0x8456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x86789abc; +imm32 r6, 0x8789abcd; +imm32 r7, 0x889abcde; +R0 = PACK( R0.L , R0.L ); +R1 = PACK( R1.L , R0.H ); +R2 = PACK( R2.H , R0.L ); +R3 = PACK( R3.H , R0.H ); +R4 = PACK( R4.L , R0.L ); +R5 = PACK( R5.L , R0.H ); +R6 = PACK( R6.H , R0.L ); +R7 = PACK( R7.H , R0.H ); +CHECKREG r0, 0x00080008; +CHECKREG r1, 0x56780008; +CHECKREG r2, 0x83450008; +CHECKREG r3, 0x84560008; +CHECKREG r4, 0x89AB0008; +CHECKREG r5, 0x9ABC0008; +CHECKREG r6, 0x87890008; +CHECKREG r7, 0x889A0008; + +imm32 r0, 0x91230009; +imm32 r1, 0x92345678; +imm32 r2, 0x93456789; +imm32 r3, 0x9456789a; +imm32 r4, 0x956789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0x9789abcd; +imm32 r7, 0x989abcde; +R0 = PACK( R0.L , R1.L ); +R1 = PACK( R1.L , R1.H ); +R2 = PACK( R2.H , R1.L ); +R3 = PACK( R3.H , R1.H ); +R4 = PACK( R4.L , R1.L ); +R5 = PACK( R5.L , R1.H ); +R6 = PACK( R6.H , R1.L ); +R7 = PACK( R7.H , R1.H ); +CHECKREG r0, 0x00095678; +CHECKREG r1, 0x56789234; +CHECKREG r2, 0x93459234; +CHECKREG r3, 0x94565678; +CHECKREG r4, 0x89AB9234; +CHECKREG r5, 0x9ABC5678; +CHECKREG r6, 0x97899234; +CHECKREG r7, 0x989A5678; + + +imm32 r0, 0xa123000a; +imm32 r1, 0xa2345678; +imm32 r2, 0xa3456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xa56789ab; +imm32 r5, 0xa6789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xa89abcde; +R0 = PACK( R0.L , R2.L ); +R1 = PACK( R1.L , R2.H ); +R2 = PACK( R2.H , R2.L ); +R3 = PACK( R3.H , R2.H ); +R4 = PACK( R4.L , R2.L ); +R5 = PACK( R5.L , R2.H ); +R6 = PACK( R6.H , R2.L ); +R7 = PACK( R7.H , R2.H ); +CHECKREG r0, 0x000A6789; +CHECKREG r1, 0x5678A345; +CHECKREG r2, 0xA3456789; +CHECKREG r3, 0xA456A345; +CHECKREG r4, 0x89AB6789; +CHECKREG r5, 0x9ABCA345; +CHECKREG r6, 0xA7896789; +CHECKREG r7, 0xA89AA345; + +imm32 r0, 0xb123000b; +imm32 r1, 0xb2345678; +imm32 r2, 0xb3456789; +imm32 r3, 0xb456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xb6789abc; +imm32 r6, 0xb789abcd; +imm32 r7, 0xb89abcde; +R0 = PACK( R0.L , R3.L ); +R1 = PACK( R1.L , R3.H ); +R2 = PACK( R2.H , R3.L ); +R3 = PACK( R3.H , R3.H ); +R4 = PACK( R4.L , R3.L ); +R5 = PACK( R5.L , R3.H ); +R6 = PACK( R6.H , R3.L ); +R7 = PACK( R7.H , R3.H ); +CHECKREG r0, 0x000B789A; +CHECKREG r1, 0x5678B456; +CHECKREG r2, 0xB345789A; +CHECKREG r3, 0xB456B456; +CHECKREG r4, 0x89ABB456; +CHECKREG r5, 0x9ABCB456; +CHECKREG r6, 0xB789B456; +CHECKREG r7, 0xB89AB456; + +imm32 r0, 0xc123000c; +imm32 r1, 0xc2345678; +imm32 r2, 0xc3456789; +imm32 r3, 0xc456789a; +imm32 r4, 0xc56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xc789abcd; +imm32 r7, 0xc89abcde; +R0 = PACK( R0.L , R4.L ); +R1 = PACK( R1.L , R4.H ); +R2 = PACK( R2.H , R4.L ); +R3 = PACK( R3.H , R4.H ); +R4 = PACK( R4.L , R4.L ); +R5 = PACK( R5.L , R4.H ); +R6 = PACK( R6.H , R4.L ); +R7 = PACK( R7.H , R4.H ); +CHECKREG r0, 0x000C89AB; +CHECKREG r1, 0x5678C567; +CHECKREG r2, 0xC34589AB; +CHECKREG r3, 0xC456C567; +CHECKREG r4, 0x89AB89AB; +CHECKREG r5, 0x9ABC89AB; +CHECKREG r6, 0xC78989AB; +CHECKREG r7, 0xC89A89AB; + +imm32 r0, 0xd123000d; +imm32 r1, 0xd2345678; +imm32 r2, 0xd3456789; +imm32 r3, 0xd456789a; +imm32 r4, 0xd56789ab; +imm32 r5, 0xd6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xd89abcde; +R0 = PACK( R0.L , R5.L ); +R1 = PACK( R1.L , R5.H ); +R2 = PACK( R2.H , R5.L ); +R3 = PACK( R3.H , R5.H ); +R4 = PACK( R4.L , R5.L ); +R5 = PACK( R5.L , R5.H ); +R6 = PACK( R6.H , R5.L ); +R7 = PACK( R7.H , R5.H ); +CHECKREG r0, 0x000D9ABC; +CHECKREG r1, 0x5678D678; +CHECKREG r2, 0xD3459ABC; +CHECKREG r3, 0xD456D678; +CHECKREG r4, 0x89AB9ABC; +CHECKREG r5, 0x9ABCD678; +CHECKREG r6, 0xD789D678; +CHECKREG r7, 0xD89A9ABC; + + +imm32 r0, 0xe123000e; +imm32 r1, 0xe2345678; +imm32 r2, 0xe3456789; +imm32 r3, 0xe456789a; +imm32 r4, 0xe56789ab; +imm32 r5, 0xe6789abc; +imm32 r6, 0xe789abcd; +imm32 r7, 0xe89abcde; +R0 = PACK( R0.L , R6.L ); +R1 = PACK( R1.L , R6.H ); +R2 = PACK( R2.H , R6.L ); +R3 = PACK( R3.H , R6.H ); +R4 = PACK( R4.L , R6.L ); +R5 = PACK( R5.L , R6.H ); +R6 = PACK( R6.H , R6.L ); +R7 = PACK( R7.H , R6.H ); +CHECKREG r0, 0x000EABCD; +CHECKREG r1, 0x5678E789; +CHECKREG r2, 0xE345ABCD; +CHECKREG r3, 0xE456E789; +CHECKREG r4, 0x89ABABCD; +CHECKREG r5, 0x9ABCE789; +CHECKREG r6, 0xE789ABCD; +CHECKREG r7, 0xE89AE789; + +imm32 r0, 0xf123000f; +imm32 r1, 0xf2345678; +imm32 r2, 0xf3456789; +imm32 r3, 0xf456789a; +imm32 r4, 0xf56789ab; +imm32 r5, 0xf6789abc; +imm32 r6, 0xf789abcd; +imm32 r7, 0xf89abcde; +R0 = PACK( R0.L , R7.L ); +R1 = PACK( R1.L , R7.H ); +R2 = PACK( R2.H , R7.L ); +R3 = PACK( R3.H , R7.H ); +R4 = PACK( R4.L , R7.L ); +R5 = PACK( R5.L , R7.H ); +R6 = PACK( R6.H , R7.L ); +R7 = PACK( R7.H , R7.H ); +CHECKREG r0, 0x000FBCDE; +CHECKREG r1, 0x5678F89A; +CHECKREG r2, 0xF345BCDE; +CHECKREG r3, 0xF456F89A; +CHECKREG r4, 0x89ABBCDE; +CHECKREG r5, 0x9ABCF89A; +CHECKREG r6, 0xF789BCDE; +CHECKREG r7, 0xF89AF89A; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_rot.s b/sim/testsuite/sim/bfin/c_dsp32shift_rot.s new file mode 100644 index 0000000..d4b2ff2 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_rot.s @@ -0,0 +1,427 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot/c_dsp32shift_rot.dsp +// Spec Reference: dsp32shift rot +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x01230001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R1 = ROT R0 BY R0.L; + R2 = ROT R1 BY R0.L; + R3 = ROT R2 BY R0.L; + R4 = ROT R3 BY R0.L; + R5 = ROT R4 BY R0.L; + R6 = ROT R5 BY R0.L; + R7 = ROT R6 BY R0.L; + R0 = ROT R7 BY R0.L; + CHECKREG r1, 0x02460002; + CHECKREG r0, 0x23000100; + CHECKREG r2, 0x048C0004; + CHECKREG r3, 0x09180008; + CHECKREG r4, 0x12300010; + CHECKREG r5, 0x24600020; + CHECKREG r6, 0x48C00040; + CHECKREG r7, 0x91800080; + + imm32 r0, 0x01230001; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R1.L = 15; + R2 = ROT R0 BY R1.L; + R3 = ROT R1 BY R1.L; + R4 = ROT R2 BY R1.L; + R5 = ROT R3 BY R1.L; + R6 = ROT R4 BY R1.L; + R7 = ROT R5 BY R1.L; + R0 = ROT R6 BY R1.L; + R1 = ROT R7 BY R1.L; + CHECKREG r0, 0x2C04C400; + CHECKREG r1, 0x5C489000; + CHECKREG r2, 0x8000C048; + CHECKREG r3, 0x0007C48D; + CHECKREG r4, 0x60242000; + CHECKREG r5, 0xE2468001; + CHECKREG r6, 0x10005809; + CHECKREG r7, 0x4000B891; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2 = 16; + R3 = ROT R0 BY R2.L; + R4 = ROT R1 BY R2.L; + R5 = ROT R2 BY R2.L; + R6 = ROT R3 BY R2.L; + R7 = ROT R4 BY R2.L; + R0 = ROT R5 BY R2.L; + R1 = ROT R6 BY R2.L; + R2 = ROT R7 BY R2.L; + CHECKREG r0, 0x00000008; + CHECKREG r1, 0x00010048; + CHECKREG r2, 0x2B3CC48D; + CHECKREG r3, 0x00020091; + CHECKREG r4, 0x5678891A; + CHECKREG r5, 0x00100000; + CHECKREG r6, 0x00910001; + CHECKREG r7, 0x891A2B3C; + + imm32 r0, 0x01230003; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R3.L = 31; + R4 = ROT R0 BY R3.L; + R5 = ROT R1 BY R3.L; + R6 = ROT R2 BY R3.L; + R7 = ROT R3 BY R3.L; + R0 = ROT R4 BY R3.L; + R1 = ROT R5 BY R3.L; + R2 = ROT R6 BY R3.L; + R3 = ROT R7 BY R3.L; + CHECKREG r0, 0x60123000; + CHECKREG r1, 0x11234567; + CHECKREG r2, 0x62345678; + CHECKREG r3, 0xE3456001; + CHECKREG r4, 0x8048C000; + CHECKREG r5, 0x448D159E; + CHECKREG r6, 0x88D159E2; + CHECKREG r7, 0x8D158007; + + imm32 r0, 0x01230004; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -1; + R0 = ROT R0 BY R4.L; + R1 = ROT R1 BY R4.L; + R2 = ROT R2 BY R4.L; + R3 = ROT R3 BY R4.L; + R4 = ROT R4 BY R4.L; + R5 = ROT R5 BY R4.L; + R6 = ROT R6 BY R4.L; + R7 = ROT R7 BY R4.L; + CHECKREG r0, 0x80918002; + CHECKREG r1, 0x091A2B3C; + CHECKREG r2, 0x11A2B3C4; + CHECKREG r3, 0x9A2B3C4D; + CHECKREG r4, 0x22B3FFFF; + CHECKREG r5, 0xAB3C4D5E; + CHECKREG r6, 0x33C4D5E6; + CHECKREG r7, 0xBC4D5E6F; + + imm32 r0, 0x01230005; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R5.L = -15; + R6 = ROT R0 BY R5.L; + R7 = ROT R1 BY R5.L; + R0 = ROT R2 BY R5.L; + R1 = ROT R3 BY R5.L; + R2 = ROT R4 BY R5.L; + R3 = ROT R5 BY R5.L; + R4 = ROT R6 BY R5.L; + R5 = ROT R7 BY R5.L; + CHECKREG r0, 0x9E26468A; + CHECKREG r1, 0xE26A68AC; + CHECKREG r2, 0x26AE8ACF; + CHECKREG r3, 0xFFC4ACF1; + CHECKREG r4, 0x091A0028; + CHECKREG r5, 0x91A0B3C0; + CHECKREG r6, 0x00140246; + CHECKREG r7, 0x59E02468; + + imm32 r0, 0x01230006; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -16; + R7 = ROT R0 BY R6.L; + R0 = ROT R1 BY R6.L; + R1 = ROT R2 BY R6.L; + R2 = ROT R3 BY R6.L; + R3 = ROT R4 BY R6.L; + R4 = ROT R5 BY R6.L; + R5 = ROT R6 BY R6.L; + R6 = ROT R7 BY R6.L; + CHECKREG r0, 0xACF01234; + CHECKREG r1, 0xCF122345; + CHECKREG r2, 0xF1343456; + CHECKREG r3, 0x13564567; + CHECKREG r4, 0x35795678; + CHECKREG r5, 0xFFE16789; + CHECKREG r6, 0x0247000C; + CHECKREG r7, 0x000C0123; + + imm32 r0, 0x01230007; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R7.L = -27; + R0 = ROT R0 BY R7.L; + R1 = ROT R1 BY R7.L; + R2 = ROT R2 BY R7.L; + R3 = ROT R3 BY R7.L; + R4 = ROT R4 BY R7.L; + R5 = ROT R5 BY R7.L; + R6 = ROT R6 BY R7.L; + R7 = ROT R7 BY R7.L; + CHECKREG r0, 0x48C001C0; + CHECKREG r1, 0x8D159E02; + CHECKREG r2, 0xD159E244; + CHECKREG r3, 0x159E2686; + CHECKREG r4, 0x59E26AE8; + CHECKREG r5, 0x9E26AF2A; + CHECKREG r6, 0xE26AF36C; + CHECKREG r7, 0x26BFF96F; + + imm32 r0, 0x01230008; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R0.L = 7; +//r0 = rot (r0 by rl0); + R1 = ROT R1 BY R0.L; + R2 = ROT R2 BY R0.L; + R3 = ROT R3 BY R0.L; + R4 = ROT R4 BY R0.L; + R5 = ROT R5 BY R0.L; + R6 = ROT R6 BY R0.L; + R7 = ROT R7 BY R0.L; + CHECKREG r0, 0x01230007; + CHECKREG r1, 0x1A2B3C04; + CHECKREG r2, 0xA2B3C4C8; + CHECKREG r3, 0x2B3C4D4D; + CHECKREG r4, 0xB3C4D591; + CHECKREG r5, 0x3C4D5E15; + CHECKREG r6, 0xC4D5E6D9; + CHECKREG r7, 0x4D5E6F5E; + + imm32 r0, 0x01230009; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R1.L = 16; + R0 = ROT R0 BY R1.L; +//r1 = rot (r1 by rl1); + R2 = ROT R2 BY R1.L; + R3 = ROT R3 BY R1.L; + R4 = ROT R4 BY R1.L; + R5 = ROT R5 BY R1.L; + R6 = ROT R6 BY R1.L; + R7 = ROT R7 BY R1.L; + CHECKREG r0, 0x00090091; + CHECKREG r1, 0x12340010; + CHECKREG r2, 0x678991A2; + CHECKREG r3, 0x789A9A2B; + CHECKREG r4, 0x89AB22B3; + CHECKREG r5, 0x9ABCAB3C; + CHECKREG r6, 0xABCD33C4; + CHECKREG r7, 0xBCDEBC4D; + + imm32 r0, 0x0123000a; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2.L = 30; + R0 = ROT R0 BY R2.L; + R1 = ROT R1 BY R2.L; +//r2 = rot (r2 by rl2); + R3 = ROT R3 BY R2.L; + R4 = ROT R4 BY R2.L; + R5 = ROT R5 BY R2.L; + R6 = ROT R6 BY R2.L; + R7 = ROT R7 BY R2.L; + CHECKREG r0, 0x80246001; + CHECKREG r1, 0x02468ACF; + CHECKREG r2, 0x2345001E; + CHECKREG r3, 0x868ACF13; + CHECKREG r4, 0xC8ACF135; + CHECKREG r5, 0x0ACF1357; + CHECKREG r6, 0x6CF13579; + CHECKREG r7, 0xAF13579B; + + imm32 r0, 0x0123000b; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R3.L = 31; + R0 = ROT R0 BY R3.L; + R1 = ROT R1 BY R3.L; + R2 = ROT R2 BY R3.L; +//r3 = rot (r3 by rl3); + R4 = ROT R4 BY R3.L; + R5 = ROT R5 BY R3.L; + R6 = ROT R6 BY R3.L; + R7 = ROT R7 BY R3.L; + CHECKREG r0, 0xC048C002; + CHECKREG r1, 0x448D159E; + CHECKREG r2, 0x88D159E2; + CHECKREG r3, 0x3456001F; + CHECKREG r4, 0x9159E26A; + CHECKREG r5, 0x559E26AF; + CHECKREG r6, 0x99E26AF3; + CHECKREG r7, 0x1E26AF37; + + imm32 r0, 0x0123000c; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -2; + R0 = ROT R0 BY R4.L; + R1 = ROT R1 BY R4.L; + R2 = ROT R2 BY R4.L; + R3 = ROT R3 BY R4.L; +//r4 = rot (r4 by rl4); + R5 = ROT R5 BY R4.L; + R6 = ROT R6 BY R4.L; + R7 = ROT R7 BY R4.L; + CHECKREG r0, 0x4048C003; + CHECKREG r1, 0x048D159E; + CHECKREG r2, 0x88D159E2; + CHECKREG r3, 0x0D159E26; + CHECKREG r4, 0x4567FFFE; + CHECKREG r5, 0x559E26AF; + CHECKREG r6, 0x99E26AF3; + CHECKREG r7, 0x1E26AF37; + + imm32 r0, 0x0123000d; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R5.L = -17; + R0 = ROT R0 BY R5.L; + R1 = ROT R1 BY R5.L; + R2 = ROT R2 BY R5.L; + R3 = ROT R3 BY R5.L; + R4 = ROT R4 BY R5.L; +//r5 = rot (r5 by rl5); + R6 = ROT R6 BY R5.L; + R7 = ROT R7 BY R5.L; + CHECKREG r0, 0x000D8091; + CHECKREG r1, 0x5678891A; + CHECKREG r2, 0x678911A2; + CHECKREG r3, 0x789A9A2B; + CHECKREG r4, 0x89AB22B3; + CHECKREG r5, 0x5678FFEF; + CHECKREG r6, 0xABCDB3C4; + CHECKREG r7, 0xBCDEBC4D; + + imm32 r0, 0x0123000e; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -30; + R0 = ROT R0 BY R6.L; + R1 = ROT R1 BY R6.L; + R2 = ROT R2 BY R6.L; + R3 = ROT R3 BY R6.L; + R4 = ROT R4 BY R6.L; + R5 = ROT R5 BY R6.L; +//r6 = rot (r6 by rl6); + R7 = ROT R7 BY R6.L; + CHECKREG r0, 0x09180070; + CHECKREG r1, 0x91A2B3C0; + CHECKREG r2, 0x1A2B3C48; + CHECKREG r3, 0xA2B3C4D4; + CHECKREG r4, 0x2B3C4D5D; + CHECKREG r5, 0xB3C4D5E1; + CHECKREG r6, 0x6789FFE2; + CHECKREG r7, 0xC4D5E6F1; + + imm32 r0, 0x0123000f; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R7.L = -31; + R0 = ROT R0 BY R7.L; + R1 = ROT R1 BY R7.L; + R2 = ROT R2 BY R7.L; + R3 = ROT R3 BY R7.L; + R4 = ROT R4 BY R7.L; + R5 = ROT R5 BY R7.L; + R6 = ROT R6 BY R7.L; + R7 = ROT R7 BY R7.L; + CHECKREG r0, 0x048C003E; + CHECKREG r1, 0x48D159E0; + CHECKREG r2, 0x8D159E24; + CHECKREG r3, 0xD159E268; + CHECKREG r4, 0x159E26AC; + CHECKREG r5, 0x59E26AF2; + CHECKREG r6, 0x9E26AF36; + CHECKREG r7, 0xE26BFF86; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_rot_mix.s b/sim/testsuite/sim/bfin/c_dsp32shift_rot_mix.s new file mode 100644 index 0000000..7639b99 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_rot_mix.s @@ -0,0 +1,437 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot_mix/c_dsp32shift_rot_mix.dsp +// Spec Reference: dsp32shift rot +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + + imm32 r0, 0x01230000; + imm32 r1, 0x12345678; + imm32 r2, 0x83456789; + imm32 r3, 0x9456789a; + imm32 r4, 0xa56789ab; + imm32 r5, 0xb6789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0xd89abcde; + R1 = ROT R0 BY R0.L; + R2 = ROT R1 BY R0.L; + R3 = ROT R2 BY R0.L; + R4 = ROT R3 BY R0.L; + R5 = ROT R4 BY R0.L; + R6 = ROT R5 BY R0.L; + R7 = ROT R6 BY R0.L; + R0 = ROT R7 BY R0.L; + CHECKREG r0, 0x01230000; + CHECKREG r1, 0x01230000; + CHECKREG r2, 0x01230000; + CHECKREG r3, 0x01230000; + CHECKREG r4, 0x01230000; + CHECKREG r5, 0x01230000; + CHECKREG r6, 0x01230000; + CHECKREG r7, 0x01230000; + + A0 = 0; + A0.L = R0.L; + A0.H = R0.H; + A0 = ROT A0 BY R1.L; + R6 = A0.w; + imm32 r4, 0x30003000; + imm32 r1, 5; + R7 = ROT R4 BY R1.L; + CHECKREG r6, 0x01230000; + CHECKREG r7, 0x00060003; + + imm32 r0, 0x11230001; + imm32 r1, 0xc2345678; + imm32 r2, 0xd3456789; + imm32 r3, 0xb456789a; + imm32 r4, 0x056789ab; + imm32 r5, 0x36789abc; + imm32 r6, 0x1789abcd; + imm32 r7, 0x189abcde; + R1.L = 5; + R2 = ROT R0 BY R1.L; + R3 = ROT R1 BY R1.L; + R4 = ROT R2 BY R1.L; + R5 = ROT R3 BY R1.L; + R6 = ROT R4 BY R1.L; + R7 = ROT R5 BY R1.L; + R0 = ROT R6 BY R1.L; + R1 = ROT R7 BY R1.L; + CHECKREG r0, 0x00108908; + CHECKREG r1, 0x005613A0; + CHECKREG r2, 0x24600021; + CHECKREG r3, 0x468000AC; + CHECKREG r4, 0x8C000422; + CHECKREG r5, 0xD0001584; + CHECKREG r6, 0x80008448; + CHECKREG r7, 0x0002B09D; + + imm32 r0, 0x01230002; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x8456789a; + imm32 r4, 0x956789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0x789abcde; + R2 = 15; + R3 = ROT R0 BY R2.L; + R4 = ROT R1 BY R2.L; + R5 = ROT R2 BY R2.L; + R6 = ROT R3 BY R2.L; + R7 = ROT R4 BY R2.L; + R0 = ROT R5 BY R2.L; + R1 = ROT R6 BY R2.L; + R2 = ROT R7 BY R2.L; + CHECKREG r0, 0xC0000001; + CHECKREG r1, 0x10006009; + CHECKREG r2, 0x45678891; + CHECKREG r3, 0x80010048; + CHECKREG r4, 0x2B3C448D; + CHECKREG r5, 0x00078000; + CHECKREG r6, 0x80242000; + CHECKREG r7, 0x22468ACF; + + imm32 r0, 0x21230003; + imm32 r1, 0x22345678; + imm32 r2, 0x23456789; + imm32 r3, 0x2456789a; + imm32 r4, 0x256789ab; + imm32 r5, 0x26789abc; + imm32 r6, 0x2789abcd; + imm32 r7, 0x289abcde; + R3.L = 24; + R4 = ROT R0 BY R3.L; + R5 = ROT R1 BY R3.L; + R6 = ROT R2 BY R3.L; + R7 = ROT R3 BY R3.L; + R0 = ROT R4 BY R3.L; + R1 = ROT R5 BY R3.L; + R2 = ROT R6 BY R3.L; + R3 = ROT R7 BY R3.L; + CHECKREG r0, 0x8001C848; + CHECKREG r1, 0x2BBC088D; + CHECKREG r2, 0xB34488D1; + CHECKREG r3, 0x000C4915; + CHECKREG r4, 0x03909180; + CHECKREG r5, 0x78111A2B; + CHECKREG r6, 0x8911A2B3; + CHECKREG r7, 0x18922B00; + + imm32 r0, 0x01230004; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -1; + R0 = ROT R0 BY R4.L; + R1 = ROT R1 BY R4.L; + R2 = ROT R2 BY R4.L; + R3 = ROT R3 BY R4.L; + R4 = ROT R4 BY R4.L; + R5 = ROT R5 BY R4.L; + R6 = ROT R6 BY R4.L; + R7 = ROT R7 BY R4.L; + CHECKREG r0, 0x80918002; + CHECKREG r1, 0x091A2B3C; + CHECKREG r2, 0x11A2B3C4; + CHECKREG r3, 0x9A2B3C4D; + CHECKREG r4, 0x22B3FFFF; + CHECKREG r5, 0xAB3C4D5E; + CHECKREG r6, 0x33C4D5E6; + CHECKREG r7, 0xBC4D5E6F; + + imm32 r0, 0x01230005; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R5.L = -6; + R6 = ROT R0 BY R5.L; + R7 = ROT R1 BY R5.L; + R0 = ROT R2 BY R5.L; + R1 = ROT R3 BY R5.L; + R2 = ROT R4 BY R5.L; + R3 = ROT R5 BY R5.L; + R4 = ROT R6 BY R5.L; + R5 = ROT R7 BY R5.L; + CHECKREG r0, 0x4C8D159E; + CHECKREG r1, 0xD0D159E2; + CHECKREG r2, 0x59159E26; + CHECKREG r3, 0xD559E3FF; + CHECKREG r4, 0x04A01230; + CHECKREG r5, 0xCB012345; + CHECKREG r6, 0x28048C00; + CHECKREG r7, 0xC048D159; + + imm32 r0, 0x01230006; + imm32 r1, 0x82345678; + imm32 r2, 0x73456789; + imm32 r3, 0x3456789a; + imm32 r4, 0xd56789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0xc789abcd; + imm32 r7, 0x789abcde; + R6.L = -15; + R7 = ROT R0 BY R6.L; + R0 = ROT R1 BY R6.L; + R1 = ROT R2 BY R6.L; + R2 = ROT R3 BY R6.L; + R3 = ROT R4 BY R6.L; + R4 = ROT R5 BY R6.L; + R5 = ROT R6 BY R6.L; + R6 = ROT R7 BY R6.L; + CHECKREG r0, 0x59E10468; + CHECKREG r1, 0x9E26E68A; + CHECKREG r2, 0xE26A68AC; + CHECKREG r3, 0x26AFAACF; + CHECKREG r4, 0x6AF0ACF1; + CHECKREG r5, 0xFFC58F13; + CHECKREG r6, 0x091A0030; + CHECKREG r7, 0x00180246; + + imm32 r0, 0x01230007; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R7.L = -27; + R0 = ROT R0 BY R7.L; + R1 = ROT R1 BY R7.L; + R2 = ROT R2 BY R7.L; + R3 = ROT R3 BY R7.L; + R4 = ROT R4 BY R7.L; + R5 = ROT R5 BY R7.L; + R6 = ROT R6 BY R7.L; + R7 = ROT R7 BY R7.L; + CHECKREG r0, 0x48C001C0; + CHECKREG r1, 0x8D159E02; + CHECKREG r2, 0xD159E244; + CHECKREG r3, 0x159E2686; + CHECKREG r4, 0x59E26AE8; + CHECKREG r5, 0x9E26AF2A; + CHECKREG r6, 0xE26AF36C; + CHECKREG r7, 0x26BFF96F; + + imm32 r0, 0x01230008; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R0.L = 7; +//r0 = rot (r0 by rl0); + R1 = ROT R1 BY R0.L; + R2 = ROT R2 BY R0.L; + R3 = ROT R3 BY R0.L; + R4 = ROT R4 BY R0.L; + R5 = ROT R5 BY R0.L; + R6 = ROT R6 BY R0.L; + R7 = ROT R7 BY R0.L; + CHECKREG r0, 0x01230007; + CHECKREG r1, 0x1A2B3C04; + CHECKREG r2, 0xA2B3C4C8; + CHECKREG r3, 0x2B3C4D4D; + CHECKREG r4, 0xB3C4D591; + CHECKREG r5, 0x3C4D5E15; + CHECKREG r6, 0xC4D5E6D9; + CHECKREG r7, 0x4D5E6F5E; + + imm32 r0, 0x01230009; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R1.L = 16; + R0 = ROT R0 BY R1.L; +//r1 = rot (r1 by rl1); + R2 = ROT R2 BY R1.L; + R3 = ROT R3 BY R1.L; + R4 = ROT R4 BY R1.L; + R5 = ROT R5 BY R1.L; + R6 = ROT R6 BY R1.L; + R7 = ROT R7 BY R1.L; + CHECKREG r0, 0x00090091; + CHECKREG r1, 0x12340010; + CHECKREG r2, 0x678991A2; + CHECKREG r3, 0x789A9A2B; + CHECKREG r4, 0x89AB22B3; + CHECKREG r5, 0x9ABCAB3C; + CHECKREG r6, 0xABCD33C4; + CHECKREG r7, 0xBCDEBC4D; + + imm32 r0, 0x0123000a; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R2.L = 31; + R0 = ROT R0 BY R2.L; + R1 = ROT R1 BY R2.L; +//r2 = rot (r2 by rl2); + R3 = ROT R3 BY R2.L; + R4 = ROT R4 BY R2.L; + R5 = ROT R5 BY R2.L; + R6 = ROT R6 BY R2.L; + R7 = ROT R7 BY R2.L; + CHECKREG r0, 0x0048C002; + CHECKREG r1, 0x448D159E; + CHECKREG r2, 0x2345001F; + CHECKREG r3, 0x0D159E26; + CHECKREG r4, 0xD159E26A; + CHECKREG r5, 0x559E26AF; + CHECKREG r6, 0x99E26AF3; + CHECKREG r7, 0x1E26AF37; + + imm32 r0, 0x0123000b; + imm32 r1, 0x92345678; + imm32 r2, 0x93456789; + imm32 r3, 0xc456789a; + imm32 r4, 0xa56789ab; + imm32 r5, 0xb6789abc; + imm32 r6, 0xe789abcd; + imm32 r7, 0xf89abcde; + R3.L = 33; + R0 = ROT R0 BY R3.L; + R1 = ROT R1 BY R3.L; + R2 = ROT R2 BY R3.L; +//r3 = rot (r3 by rl3); + R4 = ROT R4 BY R3.L; + R5 = ROT R5 BY R3.L; + R6 = ROT R6 BY R3.L; + R7 = ROT R7 BY R3.L; + CHECKREG r0, 0x048C002E; + CHECKREG r1, 0x48D159E1; + CHECKREG r2, 0x4D159E25; + CHECKREG r3, 0xC4560021; + CHECKREG r4, 0x959E26AD; + CHECKREG r5, 0xD9E26AF1; + CHECKREG r6, 0x9E26AF35; + CHECKREG r7, 0xE26AF37B; + + imm32 r0, 0x0123000c; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R4.L = -2; + R0 = ROT R0 BY R4.L; + R1 = ROT R1 BY R4.L; + R2 = ROT R2 BY R4.L; + R3 = ROT R3 BY R4.L; +//r4 = rot (r4 by rl4); + R5 = ROT R5 BY R4.L; + R6 = ROT R6 BY R4.L; + R7 = ROT R7 BY R4.L; + CHECKREG r0, 0x4048C003; + CHECKREG r1, 0x048D159E; + CHECKREG r2, 0x88D159E2; + CHECKREG r3, 0x0D159E26; + CHECKREG r4, 0x4567FFFE; + CHECKREG r5, 0x559E26AF; + CHECKREG r6, 0x99E26AF3; + CHECKREG r7, 0x1E26AF37; + + imm32 r0, 0x0123000d; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R5.L = -14; + R0 = ROT R0 BY R5.L; + R1 = ROT R1 BY R5.L; + R2 = ROT R2 BY R5.L; + R3 = ROT R3 BY R5.L; + R4 = ROT R4 BY R5.L; +//r5 = rot (r5 by rl5); + R6 = ROT R6 BY R5.L; + R7 = ROT R7 BY R5.L; + CHECKREG r0, 0x006C048C; + CHECKREG r1, 0xB3C048D1; + CHECKREG r2, 0x3C488D15; + CHECKREG r3, 0xC4D4D159; + CHECKREG r4, 0x4D5D159E; + CHECKREG r5, 0x5678FFF2; + CHECKREG r6, 0x5E699E26; + CHECKREG r7, 0xE6F5E26A; + + imm32 r0, 0x0123000e; + imm32 r1, 0x12345678; + imm32 r2, 0x23456789; + imm32 r3, 0x3456789a; + imm32 r4, 0x456789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x6789abcd; + imm32 r7, 0x789abcde; + R6.L = -16; + R0 = ROT R0 BY R6.L; + R1 = ROT R1 BY R6.L; + R2 = ROT R2 BY R6.L; + R3 = ROT R3 BY R6.L; + R4 = ROT R4 BY R6.L; + R5 = ROT R5 BY R6.L; +//r6 = rot (r6 by rl6); + R7 = ROT R7 BY R6.L; + CHECKREG r0, 0x001D0123; + CHECKREG r1, 0xACF01234; + CHECKREG r2, 0xCF122345; + CHECKREG r3, 0xF1343456; + CHECKREG r4, 0x13564567; + CHECKREG r5, 0x35795678; + CHECKREG r6, 0x6789FFF0; + CHECKREG r7, 0x79BD789A; + + imm32 r0, 0x0123000f; + imm32 r1, 0x12345678; + imm32 r2, 0x83456789; + imm32 r3, 0x3456789a; + imm32 r4, 0xd56789ab; + imm32 r5, 0x56789abc; + imm32 r6, 0x9789abcd; + imm32 r7, 0x789abcde; + R7.L = -32; + R0 = ROT R0 BY R7.L; + R1 = ROT R1 BY R7.L; + R2 = ROT R2 BY R7.L; + R3 = ROT R3 BY R7.L; + R4 = ROT R4 BY R7.L; + R5 = ROT R5 BY R7.L; + R6 = ROT R6 BY R7.L; + R7 = ROT R7 BY R7.L; + CHECKREG r0, 0x0246001f; + CHECKREG r1, 0x2468ACF0; + CHECKREG r2, 0x068ACF12; + CHECKREG r3, 0x68ACF135; + CHECKREG r4, 0xAACF1356; + CHECKREG r5, 0xACF13579; + CHECKREG r6, 0x2F13579A; + CHECKREG r7, 0xF135FFC1; + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_signbits_r.s b/sim/testsuite/sim/bfin/c_dsp32shift_signbits_r.s new file mode 100644 index 0000000..6bdb7a0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_signbits_r.s @@ -0,0 +1,214 @@ +//Original:/testcases/core/c_dsp32shift_signbits_r/c_dsp32shift_signbits_r.dsp +// Spec Reference: dsp32shift signbits dregs +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0x88880000; +imm32 r1, 0x34560001; +imm32 r2, 0x08000002; +imm32 r3, 0x08000003; +imm32 r4, 0x08000004; +imm32 r5, 0x08000005; +imm32 r6, 0x08000006; +imm32 r7, 0x08000007; +R7.L = SIGNBITS R0; +R1.L = SIGNBITS R0; +R2.L = SIGNBITS R0; +R3.L = SIGNBITS R0; +R4.L = SIGNBITS R0; +R5.L = SIGNBITS R0; +R6.L = SIGNBITS R0; +R0.L = SIGNBITS R0; +CHECKREG r0, 0x88880000; +CHECKREG r1, 0x34560000; +CHECKREG r2, 0x08000000; +CHECKREG r3, 0x08000000; +CHECKREG r4, 0x08000000; +CHECKREG r5, 0x08000000; +CHECKREG r6, 0x08000000; +CHECKREG r7, 0x08000000; + +imm32 r0, 0x9999001E; +imm32 r1, 0x0000001E; +imm32 r2, 0x0000001E; +imm32 r3, 0x0000001E; +imm32 r4, 0x0000001E; +imm32 r5, 0x0000001E; +imm32 r6, 0x0000001E; +imm32 r7, 0x0000001E; +R0.L = SIGNBITS R1; +R7.L = SIGNBITS R1; +R2.L = SIGNBITS R1; +R3.L = SIGNBITS R1; +R4.L = SIGNBITS R1; +R5.L = SIGNBITS R1; +R6.L = SIGNBITS R1; +R1.L = SIGNBITS R1; +CHECKREG r0, 0x9999001A; +CHECKREG r1, 0x0000001A; +CHECKREG r2, 0x0000001A; +CHECKREG r3, 0x0000001A; +CHECKREG r4, 0x0000001A; +CHECKREG r5, 0x0000001A; +CHECKREG r6, 0x0000001A; +CHECKREG r7, 0x0000001A; + + +imm32 r0, 0x0aaae001; +imm32 r1, 0x0000e001; +imm32 r2, 0xaaaa000f; +imm32 r3, 0x0a00e003; +imm32 r4, 0x00a0e004; +imm32 r5, 0x00a0e005; +imm32 r6, 0x0a00e006; +imm32 r7, 0x0b00e007; +R0.L = SIGNBITS R2; +R1.L = SIGNBITS R2; +R7.L = SIGNBITS R2; +R3.L = SIGNBITS R2; +R4.L = SIGNBITS R2; +R5.L = SIGNBITS R2; +R6.L = SIGNBITS R2; +R2.L = SIGNBITS R2; +CHECKREG r0, 0x0AAA0000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0xAAAA0000; +CHECKREG r3, 0x0A000000; +CHECKREG r4, 0x00A00000; +CHECKREG r5, 0x00A00000; +CHECKREG r6, 0x0A000000; +CHECKREG r7, 0x0B000000; + +imm32 r0, 0x0b00f001; +imm32 r1, 0x0a00f001; +imm32 r2, 0x0b00f002; +imm32 r3, 0xbbbb0010; +imm32 r4, 0x0b00f004; +imm32 r5, 0x0b00f005; +imm32 r6, 0x0b00f006; +imm32 r7, 0x00b0f007; +R0.L = SIGNBITS R3; +R1.L = SIGNBITS R3; +R2.L = SIGNBITS R3; +R7.L = SIGNBITS R3; +R4.L = SIGNBITS R3; +R5.L = SIGNBITS R3; +R6.L = SIGNBITS R3; +R3.L = SIGNBITS R3; +CHECKREG r0, 0x0B000000; +CHECKREG r1, 0x0A000000; +CHECKREG r2, 0x0B000000; +CHECKREG r3, 0xBBBB0000; +CHECKREG r4, 0x0B000000; +CHECKREG r5, 0x0B000000; +CHECKREG r6, 0x0B000000; +CHECKREG r7, 0x00B00000; + +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0xcccc0000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = SIGNBITS R4; +R1.L = SIGNBITS R4; +R2.L = SIGNBITS R4; +R3.L = SIGNBITS R4; +R7.L = SIGNBITS R4; +R5.L = SIGNBITS R4; +R6.L = SIGNBITS R4; +R4.L = SIGNBITS R4; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020001; +CHECKREG r3, 0x00030001; +CHECKREG r4, 0xCCCC0001; +CHECKREG r5, 0x00050001; +CHECKREG r6, 0x00060001; +CHECKREG r7, 0x00070001; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xdddd0000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R0.L = SIGNBITS R5; +R1.L = SIGNBITS R5; +R2.L = SIGNBITS R5; +R3.L = SIGNBITS R5; +R4.L = SIGNBITS R5; +R7.L = SIGNBITS R5; +R6.L = SIGNBITS R5; +R5.L = SIGNBITS R5; +CHECKREG r0, 0xA0010001; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0xA0020001; +CHECKREG r3, 0xA0030001; +CHECKREG r4, 0xA0040001; +CHECKREG r5, 0xDDDD0001; +CHECKREG r6, 0xA0060001; +CHECKREG r7, 0xA0070001; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xeeee0000; +imm32 r7, 0xb0070000; +R0.L = SIGNBITS R6; +R1.L = SIGNBITS R6; +R2.L = SIGNBITS R6; +R3.L = SIGNBITS R6; +R4.L = SIGNBITS R6; +R5.L = SIGNBITS R6; +R7.L = SIGNBITS R6; +R6.L = SIGNBITS R6; +CHECKREG r0, 0xB0010002; +CHECKREG r1, 0xB0010002; +CHECKREG r2, 0xB0020002; +CHECKREG r3, 0xB0030002; +CHECKREG r4, 0xB0040002; +CHECKREG r5, 0xB0050002; +CHECKREG r6, 0xEEEE0002; +CHECKREG r7, 0xB0070002; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xffff0000; +R0.L = SIGNBITS R7; +R1.L = SIGNBITS R7; +R2.L = SIGNBITS R7; +R3.L = SIGNBITS R7; +R4.L = SIGNBITS R7; +R5.L = SIGNBITS R7; +R6.L = SIGNBITS R7; +R7.L = SIGNBITS R7; + +CHECKREG r0, 0xD001000F; +CHECKREG r1, 0xD001000F; +CHECKREG r2, 0xD002000F; +CHECKREG r3, 0xD003000F; +CHECKREG r4, 0xD004000F; +CHECKREG r5, 0xD005000F; +CHECKREG r6, 0xD006000F; +CHECKREG r7, 0xFFFF000F; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rh.s b/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rh.s new file mode 100644 index 0000000..8ae46ae --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rh.s @@ -0,0 +1,214 @@ +//Original:/testcases/core/c_dsp32shift_signbits_rh/c_dsp32shift_signbits_rh.dsp +// Spec Reference: dsp32shift signbits dregs_hi +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0xd1000000; +imm32 r1, 0xd2000001; +imm32 r2, 0xd3000002; +imm32 r3, 0xd4000003; +imm32 r4, 0xd5000004; +imm32 r5, 0xd6000005; +imm32 r6, 0xd7000006; +imm32 r7, 0xd8000007; +R0.L = SIGNBITS R0.H; +R1.L = SIGNBITS R0.H; +R2.L = SIGNBITS R0.H; +R3.L = SIGNBITS R0.H; +R4.L = SIGNBITS R0.H; +R5.L = SIGNBITS R0.H; +R6.L = SIGNBITS R0.H; +R7.L = SIGNBITS R0.H; +CHECKREG r0, 0xD1000001; +CHECKREG r1, 0xD2000001; +CHECKREG r2, 0xD3000001; +CHECKREG r3, 0xD4000001; +CHECKREG r4, 0xD5000001; +CHECKREG r5, 0xD6000001; +CHECKREG r6, 0xD7000001; +CHECKREG r7, 0xD8000001; + +imm32 r0, 0xe200d001; +imm32 r1, 0xe2000001; +imm32 r2, 0xe200d002; +imm32 r3, 0xe200d003; +imm32 r4, 0xe200d004; +imm32 r5, 0xe200d005; +imm32 r6, 0xe200d006; +imm32 r7, 0xe200d007; +R0.L = SIGNBITS R1.H; +R1.L = SIGNBITS R1.H; +R2.L = SIGNBITS R1.H; +R3.L = SIGNBITS R1.H; +R4.L = SIGNBITS R1.H; +R5.L = SIGNBITS R1.H; +R6.L = SIGNBITS R1.H; +R7.L = SIGNBITS R1.H; +CHECKREG r0, 0xE2000002; +CHECKREG r1, 0xE2000002; +CHECKREG r2, 0xE2000002; +CHECKREG r3, 0xE2000002; +CHECKREG r4, 0xE2000002; +CHECKREG r5, 0xE2000002; +CHECKREG r6, 0xE2000002; +CHECKREG r7, 0xE2000002; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0xf000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.L = SIGNBITS R2.H; +R1.L = SIGNBITS R2.H; +R2.L = SIGNBITS R2.H; +R3.L = SIGNBITS R2.H; +R4.L = SIGNBITS R2.H; +R5.L = SIGNBITS R2.H; +R6.L = SIGNBITS R2.H; +R7.L = SIGNBITS R2.H; +CHECKREG r0, 0x00000003; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0xF0000003; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000003; +CHECKREG r5, 0x00000003; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x0100f001; +imm32 r1, 0x0100f001; +imm32 r2, 0x0100f002; +imm32 r3, 0x01000010; +imm32 r4, 0x0100f004; +imm32 r5, 0x0100f005; +imm32 r6, 0x0100f006; +imm32 r7, 0x0100f007; +R0.L = SIGNBITS R3.H; +R1.L = SIGNBITS R3.H; +R2.L = SIGNBITS R3.H; +R3.L = SIGNBITS R3.H; +R4.L = SIGNBITS R3.H; +R5.L = SIGNBITS R3.H; +R6.L = SIGNBITS R3.H; +R7.L = SIGNBITS R3.H; +CHECKREG r0, 0x01000006; +CHECKREG r1, 0x01000006; +CHECKREG r2, 0x01000006; +CHECKREG r3, 0x01000006; +CHECKREG r4, 0x01000006; +CHECKREG r5, 0x01000006; +CHECKREG r6, 0x01000006; +CHECKREG r7, 0x01000006; + +imm32 r0, 0x04000000; +imm32 r1, 0x04010000; +imm32 r2, 0x04020000; +imm32 r3, 0x04030000; +imm32 r4, 0x04040000; +imm32 r5, 0x04050000; +imm32 r6, 0x04060000; +imm32 r7, 0x04070000; +R0.L = SIGNBITS R4.H; +R1.L = SIGNBITS R4.H; +R2.L = SIGNBITS R4.H; +R3.L = SIGNBITS R4.H; +R4.L = SIGNBITS R4.H; +R5.L = SIGNBITS R4.H; +R6.L = SIGNBITS R4.H; +R7.L = SIGNBITS R4.H; +CHECKREG r0, 0x04000004; +CHECKREG r1, 0x04010004; +CHECKREG r2, 0x04020004; +CHECKREG r3, 0x04030004; +CHECKREG r4, 0x04040004; +CHECKREG r5, 0x04050004; +CHECKREG r6, 0x04060004; +CHECKREG r7, 0x04070004; + +imm32 r0, 0xa5010000; +imm32 r1, 0xa5010001; +imm32 r2, 0xa5020000; +imm32 r3, 0xa5030000; +imm32 r4, 0xa5540000; +imm32 r5, 0xa5550000; +imm32 r6, 0xa5060000; +imm32 r7, 0xa5070000; +R0.L = SIGNBITS R5.H; +R1.L = SIGNBITS R5.H; +R2.L = SIGNBITS R5.H; +R3.L = SIGNBITS R5.H; +R4.L = SIGNBITS R5.H; +R5.L = SIGNBITS R5.H; +R6.L = SIGNBITS R5.H; +R7.L = SIGNBITS R5.H; +CHECKREG r0, 0xA5010000; +CHECKREG r1, 0xA5010000; +CHECKREG r2, 0xA5020000; +CHECKREG r3, 0xA5030000; +CHECKREG r4, 0xA5540000; +CHECKREG r5, 0xA5550000; +CHECKREG r6, 0xA5060000; +CHECKREG r7, 0xA5070000; + + +imm32 r0, 0xb6010000; +imm32 r1, 0xb6010000; +imm32 r2, 0xb602000f; +imm32 r3, 0xb6030000; +imm32 r4, 0xb6040000; +imm32 r5, 0xb6050000; +imm32 r6, 0xb6060000; +imm32 r7, 0xb6670000; +R0.L = SIGNBITS R6.H; +R1.L = SIGNBITS R6.H; +R2.L = SIGNBITS R6.H; +R3.L = SIGNBITS R6.H; +R4.L = SIGNBITS R6.H; +R5.L = SIGNBITS R6.H; +R6.L = SIGNBITS R6.H; +R7.L = SIGNBITS R6.H; +CHECKREG r0, 0xB6010000; +CHECKREG r1, 0xB6010000; +CHECKREG r2, 0xB6020000; +CHECKREG r3, 0xB6030000; +CHECKREG r4, 0xB6040000; +CHECKREG r5, 0xB6050000; +CHECKREG r6, 0xB6060000; +CHECKREG r7, 0xB6670000; + +imm32 r0, 0xd7010000; +imm32 r1, 0xd7010000; +imm32 r2, 0xd7020000; +imm32 r3, 0xd7030010; +imm32 r4, 0xd7040000; +imm32 r5, 0xd7050000; +imm32 r6, 0xd7060000; +imm32 r7, 0xd7070000; +R0.L = SIGNBITS R7.H; +R1.L = SIGNBITS R7.H; +R2.L = SIGNBITS R7.H; +R3.L = SIGNBITS R7.H; +R4.L = SIGNBITS R7.H; +R5.L = SIGNBITS R7.H; +R6.L = SIGNBITS R7.H; +R7.L = SIGNBITS R7.H; +CHECKREG r0, 0xD7010001; +CHECKREG r1, 0xD7010001; +CHECKREG r2, 0xD7020001; +CHECKREG r3, 0xD7030001; +CHECKREG r4, 0xD7040001; +CHECKREG r5, 0xD7050001; +CHECKREG r6, 0xD7060001; +CHECKREG r7, 0xD7070001; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rl.s b/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rl.s new file mode 100644 index 0000000..3f3ccfd --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_signbits_rl.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_signbits_rl/c_dsp32shift_signbits_rl.dsp +// Spec Reference: dsp32shift signbits dregs_lo +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R7.L = SIGNBITS R0.L; +R1.L = SIGNBITS R0.L; +R2.L = SIGNBITS R0.L; +R3.L = SIGNBITS R0.L; +R4.L = SIGNBITS R0.L; +R5.L = SIGNBITS R0.L; +R6.L = SIGNBITS R0.L; +R0.L = SIGNBITS R0.L; +CHECKREG r1, 0x0000000F; +CHECKREG r0, 0x0000000F; +CHECKREG r2, 0x0000000F; +CHECKREG r3, 0x0000000F; +CHECKREG r4, 0x0000000F; +CHECKREG r5, 0x0000000F; +CHECKREG r6, 0x0000000F; +CHECKREG r7, 0x0000000F; + +imm32 r0, 0x00000001; +imm32 r1, 0x00008001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R0.L = SIGNBITS R1.L; +R7.L = SIGNBITS R1.L; +R2.L = SIGNBITS R1.L; +R3.L = SIGNBITS R1.L; +R4.L = SIGNBITS R1.L; +R5.L = SIGNBITS R1.L; +R6.L = SIGNBITS R1.L; +R1.L = SIGNBITS R1.L; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +imm32 r0, 0x0000c001; +imm32 r1, 0x0000d001; +imm32 r2, 0x0000c00f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R0.L = SIGNBITS R2.L; +R1.L = SIGNBITS R2.L; +R7.L = SIGNBITS R2.L; +R3.L = SIGNBITS R2.L; +R4.L = SIGNBITS R2.L; +R5.L = SIGNBITS R2.L; +R6.L = SIGNBITS R2.L; +R2.L = SIGNBITS R2.L; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00009001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000b002; +imm32 r3, 0x00000e10; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000f007; +R0.L = SIGNBITS R3.L; +R1.L = SIGNBITS R3.L; +R2.L = SIGNBITS R3.L; +R7.L = SIGNBITS R3.L; +R4.L = SIGNBITS R3.L; +R5.L = SIGNBITS R3.L; +R6.L = SIGNBITS R3.L; +R3.L = SIGNBITS R3.L; +CHECKREG r0, 0x00000003; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0x00000003; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000003; +CHECKREG r5, 0x00000003; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000003; + +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x0000f000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.L = SIGNBITS R4.L; +R1.L = SIGNBITS R4.L; +R2.L = SIGNBITS R4.L; +R3.L = SIGNBITS R4.L; +R7.L = SIGNBITS R4.L; +R5.L = SIGNBITS R4.L; +R6.L = SIGNBITS R4.L; +R4.L = SIGNBITS R4.L; +CHECKREG r0, 0x00000003; +CHECKREG r1, 0x00010003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00000003; +CHECKREG r5, 0x00050003; +CHECKREG r6, 0x00060003; +CHECKREG r7, 0x00070003; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x9008f000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R0.L = SIGNBITS R5.L; +R1.L = SIGNBITS R5.L; +R2.L = SIGNBITS R5.L; +R3.L = SIGNBITS R5.L; +R4.L = SIGNBITS R5.L; +R7.L = SIGNBITS R5.L; +R6.L = SIGNBITS R5.L; +R5.L = SIGNBITS R5.L; +CHECKREG r0, 0x90010003; +CHECKREG r1, 0x00010003; +CHECKREG r2, 0x90020003; +CHECKREG r3, 0x90030003; +CHECKREG r4, 0x90040003; +CHECKREG r5, 0x90080003; +CHECKREG r6, 0x90060003; +CHECKREG r7, 0x90070003; + +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa000fc00; +imm32 r7, 0xa0070000; +R0.L = SIGNBITS R6.L; +R1.L = SIGNBITS R6.L; +R2.L = SIGNBITS R6.L; +R3.L = SIGNBITS R6.L; +R4.L = SIGNBITS R6.L; +R5.L = SIGNBITS R6.L; +R7.L = SIGNBITS R6.L; +R6.L = SIGNBITS R6.L; +CHECKREG r0, 0x90010005; +CHECKREG r1, 0xA0010005; +CHECKREG r2, 0xA0020005; +CHECKREG r3, 0xA0030005; +CHECKREG r4, 0xA0040005; +CHECKREG r5, 0xA0050005; +CHECKREG r6, 0xA0000005; +CHECKREG r7, 0xA0070005; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc007e007; +R0.L = SIGNBITS R7.L; +R1.L = SIGNBITS R7.L; +R2.L = SIGNBITS R7.L; +R3.L = SIGNBITS R7.L; +R4.L = SIGNBITS R7.L; +R5.L = SIGNBITS R7.L; +R6.L = SIGNBITS R7.L; +R7.L = SIGNBITS R7.L; +CHECKREG r0, 0xC0010002; +CHECKREG r1, 0xC0010002; +CHECKREG r2, 0xC0020002; +CHECKREG r3, 0xC0030002; +CHECKREG r4, 0xC0040002; +CHECKREG r5, 0xC0050002; +CHECKREG r6, 0xC0060002; +CHECKREG r7, 0xC0070002; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_vmax.s b/sim/testsuite/sim/bfin/c_dsp32shift_vmax.s new file mode 100644 index 0000000..4f3ccd1 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_vmax.s @@ -0,0 +1,113 @@ +//Original:/testcases/core/c_dsp32shift_vmax/c_dsp32shift_vmax.dsp +// Spec Reference: dsp32shift vmax +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x11001001; +imm32 r1, 0x11001001; +imm32 r2, 0x12345678; +imm32 r3, 0x11001003; +imm32 r4, 0x11001004; +imm32 r5, 0x11001005; +imm32 r6, 0x11001006; +imm32 r7, 0x11001007; +A0 = R2; +R0.L = VIT_MAX( R0 ) (ASL); +R1.L = VIT_MAX( R1 ) (ASL); +R2.L = VIT_MAX( R2 ) (ASL); +R3.L = VIT_MAX( R3 ) (ASL); +R4.L = VIT_MAX( R4 ) (ASL); +R5.L = VIT_MAX( R5 ) (ASL); +R6.L = VIT_MAX( R6 ) (ASL); +R7.L = VIT_MAX( R7 ) (ASL); +CHECKREG r0, 0x11001100; +CHECKREG r1, 0x11001100; +CHECKREG r2, 0x12345678; +CHECKREG r3, 0x11001100; +CHECKREG r4, 0x11001100; +CHECKREG r5, 0x11001100; +CHECKREG r6, 0x11001100; +CHECKREG r7, 0x11001100; + +imm32 r0, 0xa1001001; +imm32 r1, 0x1b001001; +imm32 r2, 0x11c01002; +imm32 r3, 0x110d1003; +imm32 r4, 0x1100e004; +imm32 r5, 0x11001f05; +imm32 r6, 0x11001006; +imm32 r7, 0x11001001; +R1.L = VIT_MAX( R0 ) (ASL); +R2.L = VIT_MAX( R1 ) (ASL); +R3.L = VIT_MAX( R2 ) (ASL); +R4.L = VIT_MAX( R3 ) (ASL); +R5.L = VIT_MAX( R4 ) (ASL); +R6.L = VIT_MAX( R5 ) (ASL); +R7.L = VIT_MAX( R6 ) (ASL); +R0.L = VIT_MAX( R7 ) (ASL); +CHECKREG r0, 0xA1001B00; +CHECKREG r1, 0x1B001001; +CHECKREG r2, 0x11C01B00; +CHECKREG r3, 0x110D1B00; +CHECKREG r4, 0x11001B00; +CHECKREG r5, 0x11001B00; +CHECKREG r6, 0x11001B00; +CHECKREG r7, 0x11001B00; + + +imm32 r0, 0x20000000; +imm32 r1, 0x4300c001; +imm32 r2, 0x4040c002; +imm32 r3, 0x40056003; +imm32 r4, 0x4000c704; +imm32 r5, 0x4000c085; +imm32 r6, 0x4000c096; +imm32 r7, 0x4000c000; +R0.L = VIT_MAX( R0 ) (ASR); +R1.L = VIT_MAX( R1 ) (ASR); +R2.L = VIT_MAX( R2 ) (ASR); +R3.L = VIT_MAX( R3 ) (ASR); +R4.L = VIT_MAX( R4 ) (ASR); +R5.L = VIT_MAX( R5 ) (ASR); +R6.L = VIT_MAX( R6 ) (ASR); +R7.L = VIT_MAX( R7 ) (ASR); +CHECKREG r0, 0x20002000; +CHECKREG r1, 0x4300C001; +CHECKREG r2, 0x4040C002; +CHECKREG r3, 0x40056003; +CHECKREG r4, 0x40004000; +CHECKREG r5, 0x40004000; +CHECKREG r6, 0x40004000; +CHECKREG r7, 0x4000C000; + +imm32 r0, 0x10000000; +imm32 r1, 0x4200c001; +imm32 r2, 0x4030c002; +imm32 r3, 0x4004c003; +imm32 r4, 0x40005004; +imm32 r5, 0x4000c605; +imm32 r6, 0x4000c076; +imm32 r7, 0x4000c008; +R2.L = VIT_MAX( R0 ) (ASR); +R3.L = VIT_MAX( R1 ) (ASR); +R4.L = VIT_MAX( R2 ) (ASR); +R5.L = VIT_MAX( R3 ) (ASR); +R6.L = VIT_MAX( R4 ) (ASR); +R7.L = VIT_MAX( R5 ) (ASR); +R0.L = VIT_MAX( R6 ) (ASR); +R1.L = VIT_MAX( R7 ) (ASR); +CHECKREG r0, 0x10004030; +CHECKREG r1, 0x42004000; +CHECKREG r2, 0x40301000; +CHECKREG r3, 0x4004C001; +CHECKREG r4, 0x40004030; +CHECKREG r5, 0x4000C001; +CHECKREG r6, 0x40004030; +CHECKREG r7, 0x40004000; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s b/sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s new file mode 100644 index 0000000..48e8d4b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s @@ -0,0 +1,113 @@ +//Original:/testcases/core/c_dsp32shift_vmaxvmax/c_dsp32shift_vmaxvmax.dsp +// Spec Reference: dsp32shift vmax / vmax +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x11002001; +imm32 r1, 0x12001001; +imm32 r2, 0x11301302; +imm32 r3, 0x43001003; +imm32 r4, 0x11601604; +imm32 r5, 0x71001705; +imm32 r6, 0x81008006; +imm32 r7, 0x1900b007; +A0 = R3; +R1 = VIT_MAX( R1 , R0 ) (ASL); +R2 = VIT_MAX( R2 , R1 ) (ASL); +R3 = VIT_MAX( R3 , R2 ) (ASL); +R4 = VIT_MAX( R4 , R3 ) (ASL); +R5 = VIT_MAX( R5 , R4 ) (ASL); +R6 = VIT_MAX( R6 , R5 ) (ASL); +R7 = VIT_MAX( R7 , R6 ) (ASL); +R0 = VIT_MAX( R0 , R7 ) (ASL); +CHECKREG r0, 0x20018100; +CHECKREG r1, 0x12002001; +CHECKREG r2, 0x13022001; +CHECKREG r3, 0x43002001; +CHECKREG r4, 0x16044300; +CHECKREG r5, 0x71004300; +CHECKREG r6, 0x81007100; +CHECKREG r7, 0x19008100; + +imm32 r0, 0xa11002001; +imm32 r1, 0xd2001001; +imm32 r2, 0x14301302; +imm32 r3, 0x43001003; +imm32 r4, 0x11f01604; +imm32 r5, 0xb1001705; +imm32 r6, 0xd1008006; +imm32 r7, 0x39056707; +R1 = VIT_MAX( R1 , R3 ) (ASL); +R2 = VIT_MAX( R2 , R4 ) (ASL); +R3 = VIT_MAX( R3 , R6 ) (ASL); +R4 = VIT_MAX( R4 , R5 ) (ASL); +R5 = VIT_MAX( R5 , R7 ) (ASL); +R6 = VIT_MAX( R6 , R0 ) (ASL); +R7 = VIT_MAX( R7 , R1 ) (ASL); +R0 = VIT_MAX( R0 , R2 ) (ASL); +CHECKREG r0, 0x20011604; +CHECKREG r1, 0x10014300; +CHECKREG r2, 0x14301604; +CHECKREG r3, 0x4300D100; +CHECKREG r4, 0x16041705; +CHECKREG r5, 0x17056707; +CHECKREG r6, 0xD1002001; +CHECKREG r7, 0x67074300; + +imm32 r0, 0xa1011001; +imm32 r1, 0x1b002001; +imm32 r2, 0x81c01302; +imm32 r3, 0x910d1403; +imm32 r4, 0x2100e504; +imm32 r5, 0x31007f65; +imm32 r6, 0x41007006; +imm32 r7, 0x15001801; +R1 = VIT_MAX( R1 , R0 ) (ASR); +R2 = VIT_MAX( R2 , R1 ) (ASR); +R3 = VIT_MAX( R3 , R2 ) (ASR); +R4 = VIT_MAX( R4 , R3 ) (ASR); +R5 = VIT_MAX( R5 , R4 ) (ASR); +R6 = VIT_MAX( R6 , R5 ) (ASR); +R7 = VIT_MAX( R7 , R6 ) (ASR); +R0 = VIT_MAX( R0 , R7 ) (ASR); +CHECKREG r0, 0x1001910D; +CHECKREG r1, 0x20011001; +CHECKREG r2, 0x81C02001; +CHECKREG r3, 0x910D81C0; +CHECKREG r4, 0x2100910D; +CHECKREG r5, 0x7F65910D; +CHECKREG r6, 0x7006910D; +CHECKREG r7, 0x1801910D; + +imm32 r0, 0xe1011001; +imm32 r1, 0x4b002001; +imm32 r2, 0x8fc01302; +imm32 r3, 0x910d1403; +imm32 r4, 0xb100e504; +imm32 r5, 0x41007f65; +imm32 r6, 0xaf007006; +imm32 r7, 0x16001801; +R0 = VIT_MAX( R4 , R0 ) (ASR); +R1 = VIT_MAX( R5 , R1 ) (ASR); +R2 = VIT_MAX( R6 , R2 ) (ASR); +R3 = VIT_MAX( R7 , R3 ) (ASR); +R4 = VIT_MAX( R0 , R4 ) (ASR); +R5 = VIT_MAX( R1 , R5 ) (ASR); +R6 = VIT_MAX( R2 , R6 ) (ASR); +R7 = VIT_MAX( R3 , R7 ) (ASR); +CHECKREG r0, 0xE5041001; +CHECKREG r1, 0x7F654B00; +CHECKREG r2, 0xAF008FC0; +CHECKREG r3, 0x1801910D; +CHECKREG r4, 0x1001E504; +CHECKREG r5, 0x7F657F65; +CHECKREG r6, 0xAF00AF00; +CHECKREG r7, 0x910D1801; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_a0alr.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_a0alr.s new file mode 100644 index 0000000..13bd532 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_a0alr.s @@ -0,0 +1,213 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_a0alr/c_dsp32shiftim_a0alr.dsp +// Spec Reference: dsp32shift a0 ashift, lshift, rot +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + imm32 r0, 0x11140000; + imm32 r1, 0x012C003E; + imm32 r2, 0x81359E24; + imm32 r3, 0x81459E24; + imm32 r4, 0xD159E268; + imm32 r5, 0x51626AF2; + imm32 r6, 0x9176AF36; + imm32 r7, 0xE18BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = A0 << 0; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x012C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = A0 << 1; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x026B3C48; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = A0 << 15; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0xCF120000; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = A0 << 31; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x00000000; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = A0 >>> 1; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x28B13579; + + R5.L = -16; + A0 = 0; + A0.L = R6.L; + A0.H = R6.H; + A0 = A0 >>> 16; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x00009176; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = A0 >>> 31; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x00000001; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + .dw 0xC683 // .dw 0xC683 // A0 = A0 >>> 32; + .dw 0x0100 + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x00000000; + + imm32 r0, 0x12340000; + imm32 r1, 0x028C003E; + imm32 r2, 0x82159E24; + imm32 r3, 0x82159E24; + imm32 r4, 0xD259E268; + imm32 r5, 0x52E26AF2; + imm32 r6, 0x9226AF36; + imm32 r7, 0xE26BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = A0 << 0; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x028C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = A0 << 3; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x10ACF120; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = A0 << 15; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0xCF120000; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = A0 << 31; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x00000000; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = A0 >> 1; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x29713579; + + R5.L = -16; + A0 = 0; + A0.L = R6.L; + A0.H = R6.H; + A0 = A0 >> 16; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x00009226; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = A0 >> 31; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0x00000001; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + .dw 0xC683 + .dw 0x4100 // A0 = A0 >> 32; + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x00000000; + + imm32 r0, 0x13340000; + imm32 r1, 0x038C003E; + imm32 r2, 0x83159E24; + imm32 r3, 0x83159E24; + imm32 r4, 0xD359E268; + imm32 r5, 0x53E26AF2; + imm32 r6, 0x9326AF36; + imm32 r7, 0xE36BFF86; + + R0.L = 0; + A0 = 0; + A0.L = R1.L; + A0.H = R1.H; + A0 = ROT A0 BY 0; /* a0 = 0x00000000 */ + R1 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r1, 0x038C003E; + + R1.L = 1; + A0.L = R2.L; + A0.H = R2.H; + A0 = ROT A0 BY 1; /* a0 = 0x00000000 */ + R2 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r2, 0x062B3C48; + + R2.L = 15; + A0.L = R3.L; + A0.H = R3.H; + A0 = ROT A0 BY 15; /* a0 = 0x00000000 */ + R3 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r3, 0xCF120060; + + R3.L = 31; + A0.L = R4.L; + A0.H = R4.H; + A0 = ROT A0 BY 31; /* a0 = 0x00000000 */ + R4 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r4, 0x62B4D678; + + R4.L = -1; + A0.L = R5.L; + A0.H = R5.H; + A0 = ROT A0 BY -1; /* a0 = 0x00000000 */ + R5 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r5, 0x29F13579; + + R5.L = -16; + A0.L = R6.L; + A0.H = R6.H; + A0 = ROT A0 BY -16; /* a0 = 0x00000000 */ + R6 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r6, 0x6C9A9326; + + R6.L = -31; + A0.L = R7.L; + A0.H = R7.H; + A0 = ROT A0 BY -31; /* a0 = 0x00000000 */ + R7 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r7, 0xAFFE1ABD; + + R7.L = -32; + A0.L = R0.L; + A0.H = R0.H; + A0 = ROT A0 BY -32; /* a0 = 0x00000000 */ + R0 = A0.w; /* r5 = 0x00000000 */ + CHECKREG r0, 0x6800018D; + + pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_af.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_af.s new file mode 100644 index 0000000..1c994f4 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_af.s @@ -0,0 +1,63 @@ +//Original:/testcases/core/c_dsp32shiftim_af/c_dsp32shiftim_af.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: ashift + + +imm32 r0, 0xa1230001; +imm32 r1, 0x1b345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x34d6789a; +imm32 r4, 0x85a789ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb8912cde; +R0 = R0 << 0; +R1 = R1 << 3; +R2 = R2 << 7; +R3 = R3 << 8; +R4 = R4 << 15; +R5 = R5 << 24; +R6 = R6 << 31; +R7 = R7 << 20; +CHECKREG r0, 0xA1230001; +CHECKREG r1, 0xD9A2B3C0; +CHECKREG r2, 0xE2B3C480; +CHECKREG r3, 0xD6789A00; +CHECKREG r4, 0xC4D58000; +CHECKREG r5, 0xBC000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0xCDE00000; + +imm32 r0, 0xa1230001; +imm32 r1, 0x1b345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x34d6789a; +imm32 r4, 0x85a789ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb8912cde; +R6 = R0 >>> 1; +R7 = R1 >>> 3; +R0 = R2 >>> 7; +R1 = R3 >>> 8; +R2 = R4 >>> 15; +R3 = R5 >>> 24; +R4 = R6 >>> 31; +R5 = R7 >>> 20; +CHECKREG r0, 0x00478ACF; +CHECKREG r1, 0x0034D678; +CHECKREG r2, 0xFFFF0B4F; +CHECKREG r3, 0xFFFFFF96; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0x00000036; +CHECKREG r6, 0xD0918000; +CHECKREG r7, 0x03668ACF; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s new file mode 100644 index 0000000..748d8c9 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s @@ -0,0 +1,63 @@ +//Original:/testcases/core/c_dsp32shiftim_af_s/c_dsp32shiftim_af_s.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: ashift saturated + + +imm32 r0, 0x81230001; +imm32 r1, 0x19345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x3ed6789a; +imm32 r4, 0x85d789ab; +imm32 r5, 0x967f9abc; +imm32 r6, 0xa789bbcd; +imm32 r7, 0xb891acde; +R0 = R0 << 0 (S); +R1 = R1 << 3 (S); +R2 = R2 << 7 (S); +R3 = R3 << 8 (S); +R4 = R4 << 15 (S); +R5 = R5 << 24 (S); +R6 = R6 << 31 (S); +R7 = R7 << 20 (S); +CHECKREG r0, 0x81230001; +CHECKREG r1, 0x7FFFFFFF; +CHECKREG r2, 0x7FFFFFFF; +CHECKREG r3, 0x7FFFFFFF; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + +imm32 r0, 0x3a1230001; +imm32 r1, 0x1e345678; +imm32 r2, 0x23f56789; +imm32 r3, 0x34db789a; +imm32 r4, 0x85a7a9ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa78dabcd; +imm32 r7, 0xb8914cde; +R6 = R0 >>> 1; +R7 = R1 >>> 3; +R0 = R2 >>> 7; +R1 = R3 >>> 8; +R2 = R4 >>> 15; +R3 = R5 >>> 24; +R4 = R6 >>> 31; +R5 = R7 >>> 20; +CHECKREG r0, 0x0047EACF; +CHECKREG r1, 0x0034DB78; +CHECKREG r2, 0xFFFF0B4F; +CHECKREG r3, 0xFFFFFF96; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0x0000003C; +CHECKREG r6, 0xD0918000; +CHECKREG r7, 0x03C68ACF; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln.s new file mode 100644 index 0000000..e911d3a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln.s @@ -0,0 +1,406 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_ln/c_dsp32shiftim_ahalf_ln.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + +// Ashift : neg data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x1000c000; +imm32 r1, 0x1000c001; +imm32 r2, 0x1000c002; +imm32 r3, 0x1000c003; +imm32 r4, 0x1000c004; +imm32 r5, 0x1000c005; +imm32 r6, 0x1000c006; +imm32 r7, 0x1000c007; +R0.L = R0.L << 1; +R1.L = R1.L << 1; +R2.L = R2.L << 1; +R3.L = R3.L << 1; +R4.L = R4.L << 1; +R5.L = R5.L << 1; +R6.L = R6.L << 1; +R7.L = R7.L << 1; +CHECKREG r0, 0x10008000; +CHECKREG r1, 0x10008002; +CHECKREG r2, 0x10008004; +CHECKREG r3, 0x10008006; +CHECKREG r4, 0x10008008; +CHECKREG r5, 0x1000800A; +CHECKREG r6, 0x1000800C; +CHECKREG r7, 0x1000800E; + +imm32 r0, 0x20008001; +imm32 r1, 0x20000001; +imm32 r2, 0x2000d002; +imm32 r3, 0x2000e003; +imm32 r4, 0x2000f004; +imm32 r5, 0x2000c005; +imm32 r6, 0x2000d006; +imm32 r7, 0x2000e007; +R7.L = R0.L << 1; +R6.L = R1.L << 1; +R5.L = R2.L << 1; +R4.L = R3.L << 1; +R3.L = R4.L << 1; +R2.L = R5.L << 1; +R1.L = R6.L << 1; +R0.L = R7.L << 1; + +imm32 r0, 0x3000c001; +imm32 r1, 0x3000d001; +imm32 r2, 0x3000000f; +imm32 r3, 0x3000e003; +imm32 r4, 0x3000f004; +imm32 r5, 0x3000f005; +imm32 r6, 0x3000f006; +imm32 r7, 0x3000f007; +R6.L = R0.L << 12; +R7.L = R1.L << 12; +R5.L = R2.L << 12; +R4.L = R3.L << 12; +R3.L = R4.L << 12; +R2.L = R5.L << 12; +R1.L = R6.L << 12; +R0.L = R7.L << 12; +CHECKREG r1, 0x30000000; +CHECKREG r0, 0x30000000; +CHECKREG r2, 0x30000000; +CHECKREG r3, 0x30000000; +CHECKREG r4, 0x30003000; +CHECKREG r5, 0x3000F000; +CHECKREG r6, 0x30001000; +CHECKREG r7, 0x30001000; + +imm32 r0, 0x40009001; +imm32 r1, 0x4000a001; +imm32 r2, 0x4000b002; +imm32 r3, 0x40000010; +imm32 r4, 0x4000c004; +imm32 r5, 0x4000d005; +imm32 r6, 0x4000e006; +imm32 r7, 0x4000f007; +R5.L = R0.L << 13; +R6.L = R1.L << 13; +R7.L = R2.L << 13; +R0.L = R3.L << 13; +R1.L = R4.L << 13; +R2.L = R5.L << 13; +R3.L = R6.L << 13; +R4.L = R7.L << 13; +CHECKREG r0, 0x40000000; +CHECKREG r1, 0x40008000; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0x40000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x40002000; +CHECKREG r6, 0x40002000; +CHECKREG r7, 0x40004000; + +imm32 r0, 0x00005000; +imm32 r1, 0x00015000; +imm32 r2, 0x00025000; +imm32 r3, 0x00035000; +imm32 r4, 0x00045000; +imm32 r5, 0x00055000; +imm32 r6, 0x00065000; +imm32 r7, 0x00075500; +R0.L = R0.H << 10; +R1.L = R1.H << 10; +R2.L = R2.H << 10; +R3.L = R3.H << 10; +R4.L = R4.H << 10; +R5.L = R5.H << 10; +R6.L = R6.H << 10; +R7.L = R7.H << 10; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010400; +CHECKREG r2, 0x00020800; +CHECKREG r3, 0x00030C00; +CHECKREG r4, 0x00041000; +CHECKREG r5, 0x00051400; +CHECKREG r6, 0x00061800; +CHECKREG r7, 0x00071C00; + +imm32 r0, 0x90010000; +imm32 r1, 0x90010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R2.L = R0.H << 11; +R3.L = R1.H << 11; +R4.L = R2.H << 11; +R5.L = R3.H << 11; +R6.L = R4.H << 11; +R7.L = R5.H << 11; +R0.L = R6.H << 11; +R1.L = R7.H << 11; +CHECKREG r0, 0x90013000; +CHECKREG r1, 0x90013800; +CHECKREG r2, 0x90020800; +CHECKREG r3, 0x90030800; +CHECKREG r4, 0x90041000; +CHECKREG r5, 0x90051800; +CHECKREG r6, 0x90062000; +CHECKREG r7, 0x90072800; + + +imm32 r0, 0xa0010600; +imm32 r1, 0xa0010600; +imm32 r2, 0xa002060f; +imm32 r3, 0xa0030600; +imm32 r4, 0xa0040600; +imm32 r5, 0xa0050600; +imm32 r6, 0xa0060600; +imm32 r7, 0xa0070600; +R0.L = R0.H << 12; +R1.L = R1.H << 12; +R2.L = R2.H << 12; +R3.L = R3.H << 12; +R4.L = R4.H << 12; +R5.L = R5.H << 12; +R6.L = R6.H << 12; +R7.L = R7.H << 12; +CHECKREG r0, 0xA0011000; +CHECKREG r1, 0xA0011000; +CHECKREG r2, 0xA0022000; +CHECKREG r3, 0xA0033000; +CHECKREG r4, 0xA0044000; +CHECKREG r5, 0xA0055000; +CHECKREG r6, 0xA0066000; +CHECKREG r7, 0xA0077000; + +imm32 r0, 0xc0010701; +imm32 r1, 0xc0010701; +imm32 r2, 0xc0020702; +imm32 r3, 0xc0030710; +imm32 r4, 0xc0040704; +imm32 r5, 0xc0050705; +imm32 r6, 0xc0060706; +imm32 r7, 0xc0070707; +R0.L = R0.H << 13; +R1.L = R1.H << 13; +R2.L = R2.H << 13; +R3.L = R3.H << 13; +R4.L = R4.H << 13; +R5.L = R5.H << 13; +R6.L = R6.H << 13; +R7.L = R7.H << 13; +CHECKREG r0, 0xC0012000; +CHECKREG r1, 0xC0012000; +CHECKREG r2, 0xC0024000; +CHECKREG r3, 0xC0036000; +CHECKREG r4, 0xC0048000; +CHECKREG r5, 0xC005A000; +CHECKREG r6, 0xC006C000; +CHECKREG r7, 0xC007E000; + +imm32 r0, 0x00008000; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = R0.L << 0; +R1.H = R1.L << 1; +R2.H = R2.L << 2; +R3.H = R3.L << 3; +R4.H = R4.L << 4; +R5.H = R5.L << 5; +R6.H = R6.L << 6; +R7.H = R7.L << 7; +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x00028001; +CHECKREG r2, 0x00088002; +CHECKREG r3, 0x00188003; +CHECKREG r4, 0x00408004; +CHECKREG r5, 0x00A08005; +CHECKREG r6, 0x01808006; +CHECKREG r7, 0x03808007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R2.H = R0.L << 8; +R3.H = R1.L << 9; +R4.H = R2.L << 10; +R5.H = R3.L << 11; +R6.H = R4.L << 12; +R7.H = R5.L << 13; +R0.H = R6.L << 14; +R1.H = R7.L << 15; +CHECKREG r0, 0x8000D001; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x0100D002; +CHECKREG r3, 0x0200D003; +CHECKREG r4, 0x0800D004; +CHECKREG r5, 0x1800D005; +CHECKREG r6, 0x4000D006; +CHECKREG r7, 0xA000D007; + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = R0.L << 12; +R1.H = R1.L << 12; +R2.H = R2.L << 12; +R3.H = R3.L << 12; +R4.H = R4.L << 12; +R5.H = R5.L << 12; +R6.H = R6.L << 12; +R7.H = R7.L << 12; +CHECKREG r0, 0x1000E001; +CHECKREG r1, 0x1000E001; +CHECKREG r2, 0xF000000F; +CHECKREG r3, 0x3000E003; +CHECKREG r4, 0x4000E004; +CHECKREG r5, 0x5000E005; +CHECKREG r6, 0x6000E006; +CHECKREG r7, 0x7000E007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R5.H = R0.L << 13; +R6.H = R1.L << 13; +R7.H = R2.L << 13; +R0.H = R3.L << 13; +R1.H = R4.L << 13; +R2.H = R5.L << 13; +R3.H = R6.L << 13; +R4.H = R7.L << 13; +CHECKREG r0, 0x0000F001; +CHECKREG r1, 0x8000F001; +CHECKREG r2, 0xA000F002; +CHECKREG r3, 0xC0000010; +CHECKREG r4, 0xE000F004; +CHECKREG r5, 0x2000F005; +CHECKREG r6, 0x2000F006; +CHECKREG r7, 0x4000F007; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x90000000; +imm32 r1, 0x90010000; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R4.H = R0.H << 10; +R5.H = R1.H << 10; +R6.H = R2.H << 10; +R7.H = R3.H << 10; +R0.H = R4.H << 10; +R1.H = R5.H << 10; +R2.H = R6.H << 10; +R3.H = R7.H << 10; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x04000000; +CHECKREG r6, 0x08000000; +CHECKREG r7, 0x0C000000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R7.H = R0.H << 11; +R0.H = R1.H << 11; +R1.H = R2.H << 11; +R2.H = R3.H << 11; +R3.H = R4.H << 11; +R4.H = R5.H << 11; +R5.H = R6.H << 11; +R6.H = R7.H << 11; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x10000001; +CHECKREG r2, 0x18000000; +CHECKREG r3, 0x20000000; +CHECKREG r4, 0x28000000; +CHECKREG r5, 0x30000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x08000000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R6.H = R0.H << 12; +R7.H = R1.H << 12; +R0.H = R2.H << 12; +R1.H = R3.H << 12; +R2.H = R4.H << 12; +R3.H = R5.H << 12; +R4.H = R6.H << 12; +R5.H = R7.H << 12; +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x30000000; +CHECKREG r2, 0x4000000F; +CHECKREG r3, 0x50000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x10000000; +CHECKREG r7, 0x10000000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R5.H = R0.H << 3; +R6.H = R1.H << 3; +R7.H = R2.H << 3; +R0.H = R3.H << 3; +R1.H = R4.H << 3; +R2.H = R5.H << 3; +R3.H = R6.H << 3; +R4.H = R7.H << 3; +CHECKREG r0, 0x80180000; +CHECKREG r1, 0x80200000; +CHECKREG r2, 0x00400000; +CHECKREG r3, 0x00400010; +CHECKREG r4, 0x00800000; +CHECKREG r5, 0x80080000; +CHECKREG r6, 0x80080000; +CHECKREG r7, 0x80100000; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln_s.s new file mode 100644 index 0000000..aa28f3f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_ln_s.s @@ -0,0 +1,408 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_ln_s/c_dsp32shiftim_ahalf_ln_s.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : neg data, count (+)=left (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x1000c000; +imm32 r1, 0x1000c001; +imm32 r2, 0x1000c002; +imm32 r3, 0x1000c003; +imm32 r4, 0x1000c004; +imm32 r5, 0x1000c005; +imm32 r6, 0x1000c006; +imm32 r7, 0x1000c007; +R0.L = R0.L << 1 (S); +R1.L = R1.L << 1 (S); +R2.L = R2.L << 1 (S); +R3.L = R3.L << 1 (S); +R4.L = R4.L << 1 (S); +R5.L = R5.L << 1 (S); +R6.L = R6.L << 1 (S); +R7.L = R7.L << 1 (S); +CHECKREG r0, 0x10008000; +CHECKREG r1, 0x10008002; +CHECKREG r2, 0x10008004; +CHECKREG r3, 0x10008006; +CHECKREG r4, 0x10008008; +CHECKREG r5, 0x1000800A; +CHECKREG r6, 0x1000800C; +CHECKREG r7, 0x1000800E; + +imm32 r0, 0x20008001; +imm32 r1, 0x20000001; +imm32 r2, 0x2000d002; +imm32 r3, 0x2000e003; +imm32 r4, 0x2000f004; +imm32 r5, 0x2000c005; +imm32 r6, 0x2000d006; +imm32 r7, 0x2000e007; +R7.L = R0.L << 1 (S); +R6.L = R1.L << 1 (S); +R5.L = R2.L << 1 (S); +R4.L = R3.L << 1 (S); +R3.L = R4.L << 1 (S); +R2.L = R5.L << 1 (S); +R1.L = R6.L << 1 (S); +R0.L = R7.L << 1 (S); + +imm32 r0, 0x3000c001; +imm32 r1, 0x3000d001; +imm32 r2, 0x3000000f; +imm32 r3, 0x3000e003; +imm32 r4, 0x3000f004; +imm32 r5, 0x3000f005; +imm32 r6, 0x3000f006; +imm32 r7, 0x3000f007; +R6.L = R0.L << 12 (S); +R7.L = R1.L << 12 (S); +R5.L = R2.L << 12 (S); +R4.L = R3.L << 12 (S); +R3.L = R4.L << 12 (S); +R2.L = R5.L << 12 (S); +R1.L = R6.L << 12 (S); +R0.L = R7.L << 12 (S); +CHECKREG r1, 0x30008000; +CHECKREG r0, 0x30008000; +CHECKREG r2, 0x30007FFF; +CHECKREG r3, 0x30008000; +CHECKREG r4, 0x30008000; +CHECKREG r5, 0x30007FFF; +CHECKREG r6, 0x30008000; +CHECKREG r7, 0x30008000; + +imm32 r0, 0x40009001; +imm32 r1, 0x4000a001; +imm32 r2, 0x4000b002; +imm32 r3, 0x40000010; +imm32 r4, 0x4000c004; +imm32 r5, 0x4000d005; +imm32 r6, 0x4000e006; +imm32 r7, 0x4000f007; +R5.L = R0.L << 13 (S); +R6.L = R1.L << 13 (S); +R7.L = R2.L << 13 (S); +R0.L = R3.L << 13 (S); +R1.L = R4.L << 13 (S); +R2.L = R5.L << 13 (S); +R3.L = R6.L << 13 (S); +R4.L = R7.L << 13 (S); +CHECKREG r0, 0x40007FFF; +CHECKREG r1, 0x40008000; +CHECKREG r2, 0x40008000; +CHECKREG r3, 0x40008000; +CHECKREG r4, 0x40008000; +CHECKREG r5, 0x40008000; +CHECKREG r6, 0x40008000; +CHECKREG r7, 0x40008000; + +imm32 r0, 0x00005000; +imm32 r1, 0x00015000; +imm32 r2, 0x00025000; +imm32 r3, 0x00035000; +imm32 r4, 0x00045000; +imm32 r5, 0x00055000; +imm32 r6, 0x00065000; +imm32 r7, 0x00075500; +R0.L = R0.H << 10 (S); +R1.L = R1.H << 10 (S); +R2.L = R2.H << 10 (S); +R3.L = R3.H << 10 (S); +R4.L = R4.H << 10 (S); +R5.L = R5.H << 10 (S); +R6.L = R6.H << 10 (S); +R7.L = R7.H << 10 (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010400; +CHECKREG r2, 0x00020800; +CHECKREG r3, 0x00030C00; +CHECKREG r4, 0x00041000; +CHECKREG r5, 0x00051400; +CHECKREG r6, 0x00061800; +CHECKREG r7, 0x00071C00; + +imm32 r0, 0x90010000; +imm32 r1, 0x90010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R2.L = R0.H << 11 (S); +R3.L = R1.H << 11 (S); +R4.L = R2.H << 11 (S); +R5.L = R3.H << 11 (S); +R6.L = R4.H << 11 (S); +R7.L = R5.H << 11 (S); +R0.L = R6.H << 11 (S); +R1.L = R7.H << 11 (S); +CHECKREG r0, 0x90018000; +CHECKREG r1, 0x90018000; +CHECKREG r2, 0x90028000; +CHECKREG r3, 0x90038000; +CHECKREG r4, 0x90048000; +CHECKREG r5, 0x90058000; +CHECKREG r6, 0x90068000; +CHECKREG r7, 0x90078000; + + +imm32 r0, 0xa0010600; +imm32 r1, 0xa0010600; +imm32 r2, 0xa002060f; +imm32 r3, 0xa0030600; +imm32 r4, 0xa0040600; +imm32 r5, 0xa0050600; +imm32 r6, 0xa0060600; +imm32 r7, 0xa0070600; +R0.L = R0.H << 12 (S); +R1.L = R1.H << 12 (S); +R2.L = R2.H << 12 (S); +R3.L = R3.H << 12 (S); +R4.L = R4.H << 12 (S); +R5.L = R5.H << 12 (S); +R6.L = R6.H << 12 (S); +R7.L = R7.H << 12 (S); +CHECKREG r0, 0xA0018000; +CHECKREG r1, 0xA0018000; +CHECKREG r2, 0xA0028000; +CHECKREG r3, 0xA0038000; +CHECKREG r4, 0xA0048000; +CHECKREG r5, 0xA0058000; +CHECKREG r6, 0xA0068000; +CHECKREG r7, 0xA0078000; + +imm32 r0, 0xc0010701; +imm32 r1, 0xc0010701; +imm32 r2, 0xc0020702; +imm32 r3, 0xc0030710; +imm32 r4, 0xc0040704; +imm32 r5, 0xc0050705; +imm32 r6, 0xc0060706; +imm32 r7, 0xc0070707; +R0.L = R0.H << 13 (S); +R1.L = R1.H << 13 (S); +R2.L = R2.H << 13 (S); +R3.L = R3.H << 13 (S); +R4.L = R4.H << 13 (S); +R5.L = R5.H << 13 (S); +R6.L = R6.H << 13 (S); +R7.L = R7.H << 13 (S); +CHECKREG r0, 0xC0018000; +CHECKREG r1, 0xC0018000; +CHECKREG r2, 0xC0028000; +CHECKREG r3, 0xC0038000; +CHECKREG r4, 0xC0048000; +CHECKREG r5, 0xC0058000; +CHECKREG r6, 0xC0068000; +CHECKREG r7, 0xC0078000; + +imm32 r0, 0x00008000; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.H = R0.L << 0 (S); +R1.H = R1.L << 1 (S); +R2.H = R2.L << 2 (S); +R3.H = R3.L << 3 (S); +R4.H = R4.L << 4 (S); +R5.H = R5.L << 5 (S); +R6.H = R6.L << 6 (S); +R7.H = R7.L << 7 (S); +CHECKREG r0, 0x80008000; +CHECKREG r1, 0x80008001; +CHECKREG r2, 0x80008002; +CHECKREG r3, 0x80008003; +CHECKREG r4, 0x80008004; +CHECKREG r5, 0x80008005; +CHECKREG r6, 0x80008006; +CHECKREG r7, 0x80008007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R2.H = R0.L << 8 (S); +R3.H = R1.L << 9 (S); +R4.H = R2.L << 10 (S); +R5.H = R3.L << 11 (S); +R6.H = R4.L << 12 (S); +R7.H = R5.L << 13 (S); +R0.H = R6.L << 14 (S); +R1.H = R7.L << 15 (S); +CHECKREG r0, 0x8000D001; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x8000D002; +CHECKREG r3, 0x0200D003; +CHECKREG r4, 0x8000D004; +CHECKREG r5, 0x8000D005; +CHECKREG r6, 0x8000D006; +CHECKREG r7, 0x8000D007; + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R0.H = R0.L << 12 (S); +R1.H = R1.L << 12 (S); +R2.H = R2.L << 12 (S); +R3.H = R3.L << 12 (S); +R4.H = R4.L << 12 (S); +R5.H = R5.L << 12 (S); +R6.H = R6.L << 12 (S); +R7.H = R7.L << 12 (S); +CHECKREG r0, 0x8000E001; +CHECKREG r1, 0x8000E001; +CHECKREG r2, 0x7FFF000F; +CHECKREG r3, 0x8000E003; +CHECKREG r4, 0x8000E004; +CHECKREG r5, 0x8000E005; +CHECKREG r6, 0x8000E006; +CHECKREG r7, 0x8000E007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R5.H = R0.L << 13 (S); +R6.H = R1.L << 13 (S); +R7.H = R2.L << 13 (S); +R0.H = R3.L << 13 (S); +R1.H = R4.L << 13 (S); +R2.H = R5.L << 13 (S); +R3.H = R6.L << 13 (S); +R4.H = R7.L << 13 (S); +CHECKREG r0, 0x7FFFF001; +CHECKREG r1, 0x8000F001; +CHECKREG r2, 0x8000F002; +CHECKREG r3, 0x80000010; +CHECKREG r4, 0x8000F004; +CHECKREG r5, 0x8000F005; +CHECKREG r6, 0x8000F006; +CHECKREG r7, 0x8000F007; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x90000000; +imm32 r1, 0x90010000; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R4.H = R0.H << 10 (S); +R5.H = R1.H << 10 (S); +R6.H = R2.H << 10 (S); +R7.H = R3.H << 10 (S); +R0.H = R4.H << 10 (S); +R1.H = R5.H << 10 (S); +R2.H = R6.H << 10 (S); +R3.H = R7.H << 10 (S); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x80000000; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R7.H = R0.H << 11 (S); +R0.H = R1.H << 11 (S); +R1.H = R2.H << 11 (S); +R2.H = R3.H << 11 (S); +R3.H = R4.H << 11 (S); +R4.H = R5.H << 11 (S); +R5.H = R6.H << 11 (S); +R6.H = R7.H << 11 (S); +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R6.H = R0.H << 12 (S); +R7.H = R1.H << 12 (S); +R0.H = R2.H << 12 (S); +R1.H = R3.H << 12 (S); +R2.H = R4.H << 12 (S); +R3.H = R5.H << 12 (S); +R4.H = R6.H << 12 (S); +R5.H = R7.H << 12 (S); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x80000000; +CHECKREG r2, 0x8000000F; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R5.H = R0.H << 3 (S); +R6.H = R1.H << 3 (S); +R7.H = R2.H << 3 (S); +R0.H = R3.H << 3 (S); +R1.H = R4.H << 3 (S); +R2.H = R5.H << 3 (S); +R3.H = R6.H << 3 (S); +R4.H = R7.H << 3 (S); +CHECKREG r0, 0x80000000; +CHECKREG r1, 0x80000000; +CHECKREG r2, 0x80000000; +CHECKREG r3, 0x80000010; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp.s new file mode 100644 index 0000000..44e8882 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp.s @@ -0,0 +1,418 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_lp/c_dsp32shiftim_ahalf_lp.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + +// Ashift : positive data, count (+)=left (half reg) +// d_lo = ashift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x01010100; +imm32 r1, 0x01020101; +imm32 r2, 0x01030102; +imm32 r3, 0x01040103; +imm32 r4, 0x01050104; +imm32 r5, 0x01060105; +imm32 r6, 0x01070106; +imm32 r7, 0x01080107; +R0.L = R0.L << 0; +R1.L = R1.L << 1; +R2.L = R2.L << 2; +R3.L = R3.L << 3; +R4.L = R4.L << 4; +R5.L = R5.L << 5; +R6.L = R6.L << 6; +R7.L = R7.L << 7; +CHECKREG r0, 0x01010100; +CHECKREG r1, 0x01020202; +CHECKREG r2, 0x01030408; +CHECKREG r3, 0x01040818; +CHECKREG r4, 0x01051040; +CHECKREG r5, 0x010620A0; +CHECKREG r6, 0x01074180; +CHECKREG r7, 0x01088380; + +imm32 r0, 0x00090201; +imm32 r1, 0x00100201; +imm32 r2, 0x00110202; +imm32 r3, 0x00120203; +imm32 r4, 0x00130204; +imm32 r5, 0x00140205; +imm32 r6, 0x00150206; +imm32 r7, 0x00160207; +R7.L = R0.L << 8; +R6.L = R1.L << 9; +R5.L = R2.L << 10; +R4.L = R3.L << 11; +R3.L = R4.L << 12; +R2.L = R5.L << 13; +R1.L = R6.L << 14; +R0.L = R7.L << 15; +CHECKREG r1, 0x00100000; +CHECKREG r0, 0x00090000; +CHECKREG r2, 0x00110000; +CHECKREG r3, 0x00120000; +CHECKREG r4, 0x00131800; +CHECKREG r5, 0x00140800; +CHECKREG r6, 0x00150200; +CHECKREG r7, 0x00160100; + + +imm32 r0, 0x00170401; +imm32 r1, 0x00180401; +imm32 r2, 0x0019040f; +imm32 r3, 0x00200403; +imm32 r4, 0x00210404; +imm32 r5, 0x00220405; +imm32 r6, 0x00230406; +imm32 r7, 0x00244407; +R6.L = R0.L << 15; +R5.L = R1.L << 15; +R4.L = R2.L << 15; +R3.L = R3.L << 15; +R2.L = R4.L << 15; +R1.L = R5.L << 15; +R0.L = R6.L << 15; +R7.L = R7.L << 15; +CHECKREG r0, 0x00170000; +CHECKREG r1, 0x00180000; +CHECKREG r2, 0x00190000; +CHECKREG r3, 0x00208000; +CHECKREG r4, 0x00218000; +CHECKREG r5, 0x00228000; +CHECKREG r6, 0x00238000; +CHECKREG r7, 0x00248000; + +imm32 r0, 0x00005001; +imm32 r1, 0x00005001; +imm32 r2, 0x00005002; +imm32 r3, 0x00005010; +imm32 r4, 0x00005004; +imm32 r5, 0x00005005; +imm32 r6, 0x00000506; +imm32 r7, 0x00000507; +R5.L = R0.L << 13; +R6.L = R1.L << 13; +R7.L = R2.L << 13; +R0.L = R3.L << 13; +R1.L = R4.L << 13; +R2.L = R5.L << 13; +R3.L = R6.L << 13; +R4.L = R7.L << 13; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00008000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00002000; +CHECKREG r6, 0x00002000; +CHECKREG r7, 0x00004000; + +// RHx by RLx +imm32 r0, 0x00006010; +imm32 r1, 0x00016020; +imm32 r2, 0x00026030; +imm32 r3, 0x00036040; +imm32 r4, 0x00046050; +imm32 r5, 0x00056060; +imm32 r6, 0x00066070; +imm32 r7, 0x00076080; +R0.L = R0.H << 10; +R1.L = R1.H << 10; +R2.L = R2.H << 10; +R3.L = R3.H << 10; +R4.L = R4.H << 10; +R5.L = R5.H << 10; +R6.L = R6.H << 10; +R7.L = R7.H << 10; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010400; +CHECKREG r2, 0x00020800; +CHECKREG r3, 0x00030C00; +CHECKREG r4, 0x00041000; +CHECKREG r5, 0x00051400; +CHECKREG r6, 0x00061800; +CHECKREG r7, 0x00071C00; + +imm32 r0, 0x00010090; +imm32 r1, 0x00010111; +imm32 r2, 0x00020120; +imm32 r3, 0x00030130; +imm32 r4, 0x00040140; +imm32 r5, 0x00050150; +imm32 r6, 0x00060160; +imm32 r7, 0x00070170; +R1.L = R0.H << 1; +R2.L = R1.H << 1; +R3.L = R2.H << 1; +R4.L = R3.H << 1; +R5.L = R4.H << 1; +R6.L = R5.H << 1; +R7.L = R6.H << 1; +R0.L = R7.H << 1; +CHECKREG r1, 0x00010002; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030004; +CHECKREG r4, 0x00040006; +CHECKREG r5, 0x00050008; +CHECKREG r6, 0x0006000A; +CHECKREG r7, 0x0007000C; +CHECKREG r0, 0x0001000E; + + +imm32 r0, 0x0a010000; +imm32 r1, 0x0b010000; +imm32 r2, 0x0c02000f; +imm32 r3, 0x0d030000; +imm32 r4, 0x0e040000; +imm32 r5, 0x0f050000; +imm32 r6, 0x01060000; +imm32 r7, 0x02070000; +R2.L = R0.H << 12; +R3.L = R1.H << 12; +R4.L = R2.H << 12; +R5.L = R3.H << 12; +R6.L = R4.H << 12; +R7.L = R5.H << 12; +R0.L = R6.H << 12; +R1.L = R7.H << 12; +CHECKREG r0, 0x0A016000; +CHECKREG r1, 0x0B017000; +CHECKREG r2, 0x0C021000; +CHECKREG r3, 0x0D031000; +CHECKREG r4, 0x0E042000; +CHECKREG r5, 0x0F053000; +CHECKREG r6, 0x01064000; +CHECKREG r7, 0x02075000; + +imm32 r0, 0x01010001; +imm32 r1, 0x02010001; +imm32 r2, 0x03020002; +imm32 r3, 0x04030010; +imm32 r4, 0x05040004; +imm32 r5, 0x06050005; +imm32 r6, 0x07060006; +imm32 r7, 0x08070007; +R3.L = R0.H << 13; +R4.L = R1.H << 13; +R5.L = R2.H << 13; +R6.L = R3.H << 13; +R7.L = R4.H << 13; +R0.L = R5.H << 13; +R1.L = R6.H << 13; +R2.L = R7.H << 13; +CHECKREG r0, 0x0101A000; +CHECKREG r1, 0x0201C000; +CHECKREG r2, 0x0302E000; +CHECKREG r3, 0x04032000; +CHECKREG r4, 0x05042000; +CHECKREG r5, 0x06054000; +CHECKREG r6, 0x07066000; +CHECKREG r7, 0x08078000; + +// RLx by RLx +imm32 r0, 0xa0000400; +imm32 r1, 0xbb000401; +imm32 r2, 0xc0000402; +imm32 r3, 0xd0000403; +imm32 r4, 0xe0000404; +imm32 r5, 0xf0000405; +imm32 r6, 0x10000406; +imm32 r7, 0x20000407; +R0.H = R0.L << 14; +R1.H = R1.L << 14; +R2.H = R2.L << 14; +R3.H = R3.L << 14; +R4.H = R4.L << 14; +R5.H = R5.L << 14; +R6.H = R6.L << 14; +R7.H = R7.L << 14; +CHECKREG r0, 0x00000400; +CHECKREG r1, 0x40000401; +CHECKREG r2, 0x80000402; +CHECKREG r3, 0xC0000403; +CHECKREG r4, 0x00000404; +CHECKREG r5, 0x40000405; +CHECKREG r6, 0x80000406; +CHECKREG r7, 0xC0000407; + +imm32 r0, 0x0a000001; +imm32 r1, 0x0b000001; +imm32 r2, 0x0cd00002; +imm32 r3, 0x0d000003; +imm32 r4, 0x0e000004; +imm32 r5, 0x0f000005; +imm32 r6, 0x03000006; +imm32 r7, 0x04000007; +R1.H = R0.L << 15; +R2.H = R1.L << 15; +R3.H = R2.L << 15; +R4.H = R3.L << 15; +R5.H = R4.L << 15; +R6.H = R5.L << 15; +R7.H = R6.L << 15; +R0.H = R7.L << 15; +CHECKREG r1, 0x80000001; +CHECKREG r2, 0x80000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x80000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x80000006; +CHECKREG r7, 0x00000007; +CHECKREG r0, 0x80000001; + + +imm32 r0, 0x10000001; +imm32 r1, 0x02000001; +imm32 r2, 0x0300000f; +imm32 r3, 0x04000003; +imm32 r4, 0x05000004; +imm32 r5, 0x06000005; +imm32 r6, 0x07000006; +imm32 r7, 0x00800007; +R2.H = R0.L << 2; +R3.H = R1.L << 2; +R4.H = R2.L << 2; +R5.H = R3.L << 2; +R6.H = R4.L << 2; +R7.H = R5.L << 2; +R0.H = R6.L << 2; +R1.H = R7.L << 2; +CHECKREG r0, 0x00180001; +CHECKREG r1, 0x001C0001; +CHECKREG r2, 0x0004000F; +CHECKREG r3, 0x00040003; +CHECKREG r4, 0x003C0004; +CHECKREG r5, 0x000C0005; +CHECKREG r6, 0x00100006; +CHECKREG r7, 0x00140007; + +imm32 r0, 0x00000801; +imm32 r1, 0x00000801; +imm32 r2, 0x00000802; +imm32 r3, 0x00000810; +imm32 r4, 0x00000804; +imm32 r5, 0x00000805; +imm32 r6, 0x00000806; +imm32 r7, 0x00000807; +R3.H = R0.L << 3; +R4.H = R1.L << 3; +R5.H = R2.L << 3; +R6.H = R3.L << 3; +R7.H = R4.L << 3; +R0.H = R5.L << 3; +R1.H = R6.L << 3; +R2.H = R7.L << 3; +CHECKREG r0, 0x40280801; +CHECKREG r1, 0x40300801; +CHECKREG r2, 0x40380802; +CHECKREG r3, 0x40080810; +CHECKREG r4, 0x40080804; +CHECKREG r5, 0x40100805; +CHECKREG r6, 0x40800806; +CHECKREG r7, 0x40200807; + +// RHx by RLx +imm32 r0, 0x00000400; +imm32 r1, 0x00010500; +imm32 r2, 0x00020060; +imm32 r3, 0x00030070; +imm32 r4, 0x00040800; +imm32 r5, 0x00050090; +imm32 r6, 0x00060d00; +imm32 r7, 0x00070a00; +R7.H = R0.H << 10; +R6.H = R1.H << 10; +R5.H = R2.H << 10; +R4.H = R3.H << 10; +R3.H = R4.H << 10; +R2.H = R5.H << 10; +R1.H = R6.H << 10; +R0.H = R7.H << 10; +CHECKREG r1, 0x00000500; +CHECKREG r2, 0x00000060; +CHECKREG r3, 0x00000070; +CHECKREG r4, 0x0C000800; +CHECKREG r5, 0x08000090; +CHECKREG r6, 0x04000D00; +CHECKREG r7, 0x00000A00; +CHECKREG r0, 0x00000400; + +imm32 r0, 0x00010000; +imm32 r1, 0x00010001; +imm32 r2, 0x00020001; +imm32 r3, 0x00030002; +imm32 r4, 0x00040003; +imm32 r5, 0x00050004; +imm32 r6, 0x00060005; +imm32 r7, 0x00070006; +R6.H = R0.H << 11; +R5.H = R1.H << 11; +R4.H = R2.H << 11; +R3.H = R3.H << 11; +R2.H = R4.H << 11; +R1.H = R5.H << 11; +R7.H = R6.H << 11; +R0.H = R7.H << 11; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x18000002; +CHECKREG r4, 0x10000003; +CHECKREG r5, 0x08000004; +CHECKREG r6, 0x08000005; +CHECKREG r7, 0x00000006; +CHECKREG r0, 0x00000000; + + +imm32 r0, 0x00010060; +imm32 r1, 0x00010060; +imm32 r2, 0x0002006f; +imm32 r3, 0x00030060; +imm32 r4, 0x00040060; +imm32 r5, 0x00050060; +imm32 r6, 0x00060060; +imm32 r7, 0x00070060; +R4.H = R0.H << 12; +R5.H = R1.H << 12; +R6.H = R2.H << 12; +R7.H = R3.H << 12; +R0.H = R4.H << 12; +R1.H = R5.H << 12; +R2.H = R6.H << 12; +R3.H = R7.H << 12; +CHECKREG r0, 0x00000060; +CHECKREG r1, 0x00000060; +CHECKREG r2, 0x0000006F; +CHECKREG r3, 0x00000060; +CHECKREG r4, 0x10000060; +CHECKREG r5, 0x10000060; +CHECKREG r6, 0x20000060; +CHECKREG r7, 0x30000060; + +imm32 r0, 0x12010070; +imm32 r1, 0x23010070; +imm32 r2, 0x34020070; +imm32 r3, 0x45030070; +imm32 r4, 0x56040070; +imm32 r5, 0x67050070; +imm32 r6, 0x78060070; +imm32 r7, 0x09070070; +R4.H = R0.H << 3; +R5.H = R1.H << 3; +R6.H = R2.H << 3; +R7.H = R3.H << 3; +R0.H = R4.H << 3; +R1.H = R5.H << 3; +R2.H = R6.H << 3; +R3.H = R7.H << 3; +CHECKREG r0, 0x80400070; +CHECKREG r1, 0xC0400070; +CHECKREG r2, 0x00800070; +CHECKREG r3, 0x40C00070; +CHECKREG r4, 0x90080070; +CHECKREG r5, 0x18080070; +CHECKREG r6, 0xA0100070; +CHECKREG r7, 0x28180070; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp_s.s new file mode 100644 index 0000000..45b2a7e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_lp_s.s @@ -0,0 +1,415 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_lp_s/c_dsp32shiftim_ahalf_lp_s.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00100a00; +imm32 r1, 0x00100a01; +imm32 r2, 0x00100a02; +imm32 r3, 0x00100a03; +imm32 r4, 0x00100a04; +imm32 r5, 0x00100a05; +imm32 r6, 0x00100a06; +imm32 r7, 0x00100a07; +R7.L = R0.L << 0 (S); +R0.L = R1.L << 1 (S); +R1.L = R2.L << 2 (S); +R2.L = R3.L << 3 (S); +R3.L = R4.L << 4 (S); +R4.L = R5.L << 5 (S); +R5.L = R6.L << 6 (S); +R6.L = R7.L << 7 (S); +CHECKREG r1, 0x00102808; +CHECKREG r0, 0x00101402; +CHECKREG r2, 0x00105018; +CHECKREG r3, 0x00107FFF; +CHECKREG r4, 0x00107FFF; +CHECKREG r5, 0x00107FFF; +CHECKREG r6, 0x00107FFF; +CHECKREG r7, 0x00100A00; + +imm32 r0, 0x00200018; +imm32 r1, 0x00200019; +imm32 r2, 0x0020001a; +imm32 r3, 0x0020001b; +imm32 r4, 0x0020001c; +imm32 r5, 0x0020001d; +imm32 r6, 0x0020001e; +imm32 r7, 0x0020001f; +R2.L = R0.L << 8 (S); +R3.L = R1.L << 9 (S); +R4.L = R2.L << 10 (S); +R5.L = R3.L << 11 (S); +R6.L = R4.L << 12 (S); +R7.L = R5.L << 13 (S); +R0.L = R6.L << 14 (S); +R1.L = R7.L << 15 (S); +CHECKREG r0, 0x00207FFF; +CHECKREG r1, 0x00207FFF; +CHECKREG r2, 0x00201800; +CHECKREG r3, 0x00203200; +CHECKREG r4, 0x00207FFF; +CHECKREG r5, 0x00207FFF; +CHECKREG r6, 0x00207FFF; +CHECKREG r7, 0x00207FFF; + +imm32 r0, 0x05002001; +imm32 r1, 0x05002001; +imm32 r2, 0x0500000f; +imm32 r3, 0x05002003; +imm32 r4, 0x05002004; +imm32 r5, 0x05002005; +imm32 r6, 0x05002006; +imm32 r7, 0x05002007; +R3.L = R0.L << 0 (S); +R4.L = R1.L << 1 (S); +R5.L = R2.L << 2 (S); +R6.L = R3.L << 3 (S); +R7.L = R4.L << 4 (S); +R0.L = R5.L << 5 (S); +R1.L = R6.L << 6 (S); +R2.L = R7.L << 7 (S); +CHECKREG r0, 0x05000780; +CHECKREG r1, 0x05007FFF; +CHECKREG r2, 0x05007FFF; +CHECKREG r3, 0x05002001; +CHECKREG r4, 0x05004002; +CHECKREG r5, 0x0500003C; +CHECKREG r6, 0x05007FFF; +CHECKREG r7, 0x05007FFF; + +imm32 r0, 0x03000031; +imm32 r1, 0x03000031; +imm32 r2, 0x03000032; +imm32 r3, 0x03000030; +imm32 r4, 0x03000034; +imm32 r5, 0x03000035; +imm32 r6, 0x03000036; +imm32 r7, 0x03000037; +R4.L = R0.L << 8 (S); +R5.L = R1.L << 9 (S); +R6.L = R2.L << 10 (S); +R7.L = R3.L << 11 (S); +R0.L = R4.L << 12 (S); +R1.L = R5.L << 13 (S); +R2.L = R6.L << 14 (S); +R3.L = R7.L << 15 (S); +CHECKREG r0, 0x03007FFF; +CHECKREG r1, 0x03007FFF; +CHECKREG r2, 0x03007FFF; +CHECKREG r3, 0x03007FFF; +CHECKREG r4, 0x03003100; +CHECKREG r5, 0x03006200; +CHECKREG r6, 0x03007FFF; +CHECKREG r7, 0x03007FFF; +// RHx by RLx +imm32 r0, 0x03000000; +imm32 r1, 0x03000000; +imm32 r2, 0x03000000; +imm32 r3, 0x03000000; +imm32 r4, 0x03003100; +imm32 r5, 0x03006200; +imm32 r6, 0x0300C800; +imm32 r7, 0x03008000; +R5.L = R0.H << 0 (S); +R6.L = R1.H << 1 (S); +R7.L = R2.H << 2 (S); +R0.L = R3.H << 3 (S); +R1.L = R4.H << 4 (S); +R2.L = R5.H << 5 (S); +R3.L = R6.H << 6 (S); +R4.L = R7.H << 7 (S); +CHECKREG r0, 0x03001800; +CHECKREG r1, 0x03003000; +CHECKREG r2, 0x03006000; +CHECKREG r3, 0x03007FFF; +CHECKREG r4, 0x03007FFF; +CHECKREG r5, 0x03000300; +CHECKREG r6, 0x03000600; +CHECKREG r7, 0x03000C00; + +imm32 r0, 0x05018000; +imm32 r1, 0x05018001; +imm32 r2, 0x05028000; +imm32 r3, 0x05038000; +imm32 r4, 0x05048000; +imm32 r5, 0x05058000; +imm32 r6, 0x05068000; +imm32 r7, 0x05078000; +R6.L = R0.H << 8 (S); +R7.L = R1.H << 9 (S); +R0.L = R2.H << 10 (S); +R1.L = R3.H << 11 (S); +R2.L = R4.H << 12 (S); +R3.L = R5.H << 13 (S); +R4.L = R6.H << 14 (S); +R5.L = R7.H << 15 (S); +CHECKREG r0, 0x05017FFF; +CHECKREG r1, 0x05017FFF; +CHECKREG r2, 0x05027FFF; +CHECKREG r3, 0x05037FFF; +CHECKREG r4, 0x05047FFF; +CHECKREG r5, 0x05057FFF; +CHECKREG r6, 0x05067FFF; +CHECKREG r7, 0x05077FFF; + + +imm32 r0, 0x60019000; +imm32 r1, 0x60019000; +imm32 r2, 0x6002900f; +imm32 r3, 0x60039000; +imm32 r4, 0x60049000; +imm32 r5, 0x60059000; +imm32 r6, 0x60069000; +imm32 r7, 0x60079000; +R7.L = R0.H << 0 (S); +R0.L = R1.H << 1 (S); +R1.L = R2.H << 2 (S); +R2.L = R3.H << 3 (S); +R3.L = R4.H << 4 (S); +R4.L = R5.H << 5 (S); +R5.L = R6.H << 6 (S); +R6.L = R7.H << 7 (S); +CHECKREG r0, 0x60017FFF; +CHECKREG r1, 0x60017FFF; +CHECKREG r2, 0x60027FFF; +CHECKREG r3, 0x60037FFF; +CHECKREG r4, 0x60047FFF; +CHECKREG r5, 0x60057FFF; +CHECKREG r6, 0x60067FFF; +CHECKREG r7, 0x60076001; + +imm32 r0, 0x70010001; +imm32 r1, 0x70010001; +imm32 r2, 0x70020002; +imm32 r3, 0x77030010; +imm32 r4, 0x70040004; +imm32 r5, 0x70050005; +imm32 r6, 0x70060006; +imm32 r7, 0x70070007; +R0.L = R0.H << 8 (S); +R1.L = R1.H << 9 (S); +R2.L = R2.H << 10 (S); +R3.L = R3.H << 11 (S); +R4.L = R4.H << 12 (S); +R5.L = R5.H << 13 (S); +R6.L = R6.H << 14 (S); +R7.L = R7.H << 15 (S); +CHECKREG r0, 0x70017FFF; +CHECKREG r1, 0x70017FFF; +CHECKREG r2, 0x70027FFF; +CHECKREG r3, 0x77037FFF; +CHECKREG r4, 0x70047FFF; +CHECKREG r5, 0x70057FFF; +CHECKREG r6, 0x70067FFF; +CHECKREG r7, 0x70077FFF; + +// d_hi = lshft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0xa8000000; +imm32 r1, 0xa8000001; +imm32 r2, 0xa8000002; +imm32 r3, 0xa8000003; +imm32 r4, 0xa8000004; +imm32 r5, 0xa8000005; +imm32 r6, 0xa8000006; +imm32 r7, 0xa8000007; +R0.H = R0.L << 0 (S); +R1.H = R1.L << 1 (S); +R2.H = R2.L << 2 (S); +R3.H = R3.L << 3 (S); +R4.H = R4.L << 4 (S); +R5.H = R5.L << 5 (S); +R6.H = R6.L << 6 (S); +R7.H = R7.L << 7 (S); +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00080002; +CHECKREG r3, 0x00180003; +CHECKREG r4, 0x00400004; +CHECKREG r5, 0x00A00005; +CHECKREG r6, 0x01800006; +CHECKREG r7, 0x03800007; + +imm32 r0, 0xf0090001; +imm32 r1, 0xf0090001; +imm32 r2, 0xf0090002; +imm32 r3, 0xf0090003; +imm32 r4, 0xf0090004; +imm32 r5, 0xf0090005; +imm32 r6, 0xf0000006; +imm32 r7, 0xf0000007; +R1.H = R0.L << 8 (S); +R2.H = R1.L << 9 (S); +R3.H = R2.L << 10 (S); +R4.H = R3.L << 11 (S); +R5.H = R4.L << 12 (S); +R6.H = R5.L << 13 (S); +R7.H = R6.L << 14 (S); +R0.H = R7.L << 15 (S); +CHECKREG r1, 0x01000001; +CHECKREG r2, 0x02000002; +CHECKREG r3, 0x08000003; +CHECKREG r4, 0x18000004; +CHECKREG r5, 0x40000005; +CHECKREG r6, 0x7FFF0006; +CHECKREG r7, 0x7FFF0007; +CHECKREG r0, 0x7FFF0001; + + +imm32 r0, 0x07000001; +imm32 r1, 0x07000001; +imm32 r2, 0x0700000f; +imm32 r3, 0x07000003; +imm32 r4, 0x07000004; +imm32 r5, 0x07000005; +imm32 r6, 0x07000006; +imm32 r7, 0x07000007; +R3.H = R0.L << 0 (S); +R4.H = R1.L << 1 (S); +R5.H = R2.L << 2 (S); +R6.H = R3.L << 3 (S); +R7.H = R4.L << 4 (S); +R0.H = R5.L << 5 (S); +R1.H = R6.L << 6 (S); +R2.H = R7.L << 7 (S); +CHECKREG r0, 0x00A00001; +CHECKREG r1, 0x01800001; +CHECKREG r2, 0x0380000F; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +CHECKREG r5, 0x003C0005; +CHECKREG r6, 0x00180006; +CHECKREG r7, 0x00400007; + +imm32 r0, 0x00000501; +imm32 r1, 0x00000501; +imm32 r2, 0x00000502; +imm32 r3, 0x00000510; +imm32 r4, 0x00000504; +imm32 r5, 0x00000505; +imm32 r6, 0x00000506; +imm32 r7, 0x00000507; +R4.H = R0.L << 8 (S); +R5.H = R1.L << 9 (S); +R6.H = R2.L << 10 (S); +R7.H = R3.L << 11 (S); +R0.H = R4.L << 12 (S); +R1.H = R5.L << 13 (S); +R2.H = R6.L << 14 (S); +R3.H = R7.L << 15 (S); +CHECKREG r0, 0x7FFF0501; +CHECKREG r1, 0x7FFF0501; +CHECKREG r2, 0x7FFF0502; +CHECKREG r3, 0x7FFF0510; +CHECKREG r4, 0x7FFF0504; +CHECKREG r5, 0x7FFF0505; +CHECKREG r6, 0x7FFF0506; +CHECKREG r7, 0x7FFF0507; + +imm32 r0, 0x00a00800; +imm32 r1, 0x00a10800; +imm32 r2, 0x00a20800; +imm32 r3, 0x00a30800; +imm32 r4, 0x00a40800; +imm32 r5, 0x00a50800; +imm32 r6, 0x00a60800; +imm32 r7, 0x00a70800; +R5.H = R0.H << 0 (S); +R6.H = R1.H << 1 (S); +R7.H = R2.H << 2 (S); +R0.H = R3.H << 3 (S); +R1.H = R4.H << 4 (S); +R2.H = R5.H << 5 (S); +R3.H = R6.H << 6 (S); +R4.H = R7.H << 7 (S); +CHECKREG r0, 0x05180800; +CHECKREG r1, 0x0A400800; +CHECKREG r2, 0x14000800; +CHECKREG r3, 0x50800800; +CHECKREG r4, 0x7FFF0800; +CHECKREG r5, 0x00A00800; +CHECKREG r6, 0x01420800; +CHECKREG r7, 0x02880800; + +imm32 r0, 0x0c010000; +imm32 r1, 0x0c010001; +imm32 r2, 0x0c020000; +imm32 r3, 0x0c030000; +imm32 r4, 0x0c040000; +imm32 r5, 0x0c050000; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c070000; +R6.H = R0.H << 8 (S); +R7.H = R1.H << 9 (S); +R0.H = R2.H << 10 (S); +R1.H = R3.H << 11 (S); +R2.H = R4.H << 12 (S); +R3.H = R5.H << 13 (S); +R4.H = R6.H << 14 (S); +R5.H = R7.H << 15 (S); +CHECKREG r0, 0x7FFF0000; +CHECKREG r1, 0x7FFF0001; +CHECKREG r2, 0x7FFF0000; +CHECKREG r3, 0x7FFF0000; +CHECKREG r4, 0x7FFF0000; +CHECKREG r5, 0x7FFF0000; +CHECKREG r6, 0x7FFF0000; +CHECKREG r7, 0x7FFF0000; + + +imm32 r0, 0x00b10000; +imm32 r1, 0x00b10000; +imm32 r2, 0x00b2000f; +imm32 r3, 0x00b30000; +imm32 r4, 0x00b40000; +imm32 r5, 0x00b50000; +imm32 r6, 0x00b60000; +imm32 r7, 0x00b70000; +R7.L = R0.H << 0 (S); +R0.L = R1.H << 1 (S); +R1.L = R2.H << 2 (S); +R2.L = R3.H << 3 (S); +R3.L = R4.H << 4 (S); +R4.L = R5.H << 5 (S); +R5.L = R6.H << 6 (S); +R6.L = R7.H << 7 (S); +CHECKREG r0, 0x00B10162; +CHECKREG r1, 0x00B102C8; +CHECKREG r2, 0x00B20598; +CHECKREG r3, 0x00B30B40; +CHECKREG r4, 0x00B416A0; +CHECKREG r5, 0x00B52D80; +CHECKREG r6, 0x00B65B80; +CHECKREG r7, 0x00B700B1; + +imm32 r0, 0x0a010700; +imm32 r1, 0x0a010700; +imm32 r2, 0x0a020700; +imm32 r3, 0x0a030710; +imm32 r4, 0x0a040700; +imm32 r5, 0x0a050700; +imm32 r6, 0x0a060700; +imm32 r7, 0x0a070700; +R0.H = R0.H << 8 (S); +R1.H = R1.H << 9 (S); +R2.H = R2.H << 10 (S); +R3.H = R3.H << 11 (S); +R4.H = R4.H << 12 (S); +R5.H = R5.H << 13 (S); +R6.H = R6.H << 14 (S); +R7.H = R7.H << 15 (S); +CHECKREG r0, 0x7FFF0700; +CHECKREG r1, 0x7FFF0700; +CHECKREG r2, 0x7FFF0700; +CHECKREG r3, 0x7FFF0710; +CHECKREG r4, 0x7FFF0700; +CHECKREG r5, 0x7FFF0700; +CHECKREG r6, 0x7FFF0700; +CHECKREG r7, 0x7FFF0700; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn.s new file mode 100644 index 0000000..30d84f2 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn.s @@ -0,0 +1,418 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_rn/c_dsp32shiftim_ahalf_rn.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = R0.L >>> 10; +R1.L = R1.L >>> 10; +R2.L = R2.L >>> 10; +R3.L = R3.L >>> 10; +R4.L = R4.L >>> 10; +R5.L = R5.L >>> 10; +R6.L = R6.L >>> 10; +R7.L = R7.L >>> 10; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x0000FFE0; +CHECKREG r2, 0x0000FFE0; +CHECKREG r3, 0x0000FFE0; +CHECKREG r4, 0x0000FFE0; +CHECKREG r5, 0x0000FFE0; +CHECKREG r6, 0x0000FFE0; +CHECKREG r7, 0x0000FFE0; + +imm32 r0, 0x02008020; +imm32 r0, 0x02008021; +imm32 r2, 0x02008022; +imm32 r3, 0x02008023; +imm32 r4, 0x02008024; +imm32 r5, 0x02008025; +imm32 r6, 0x02008026; +imm32 r7, 0x02008027; +R0.L = R0.L >>> 11; +R1.L = R1.L >>> 11; +R2.L = R2.L >>> 11; +R3.L = R3.L >>> 11; +R4.L = R4.L >>> 11; +R5.L = R5.L >>> 11; +R6.L = R6.L >>> 11; +R7.L = R7.L >>> 11; +CHECKREG r0, 0x0200FFF0; +CHECKREG r1, 0x0000FFFF; +CHECKREG r2, 0x0200FFF0; +CHECKREG r3, 0x0200FFF0; +CHECKREG r4, 0x0200FFF0; +CHECKREG r5, 0x0200FFF0; +CHECKREG r6, 0x0200FFF0; +CHECKREG r7, 0x0200FFF0; + + +imm32 r0, 0x00308001; +imm32 r1, 0x00308001; +R2.L = -15; +imm32 r3, 0x00308003; +imm32 r4, 0x00308004; +imm32 r5, 0x00308005; +imm32 r6, 0x00308006; +imm32 r7, 0x00308007; +R0.L = R0.L >>> 12; +R1.L = R1.L >>> 12; +R2.L = R2.L >>> 12; +R3.L = R3.L >>> 12; +R4.L = R4.L >>> 12; +R5.L = R5.L >>> 12; +R6.L = R6.L >>> 12; +R7.L = R7.L >>> 12; +CHECKREG r0, 0x0030FFF8; +CHECKREG r1, 0x0030FFF8; +CHECKREG r2, 0x0200FFFF; +CHECKREG r3, 0x0030FFF8; +CHECKREG r4, 0x0030FFF8; +CHECKREG r5, 0x0030FFF8; +CHECKREG r6, 0x0030FFF8; +CHECKREG r7, 0x0030FFF8; + +imm32 r0, 0x00008401; +imm32 r1, 0x00008401; +imm32 r2, 0x00008402; +R3.L = -16; +imm32 r4, 0x00008404; +imm32 r5, 0x00008405; +imm32 r6, 0x00008406; +imm32 r7, 0x00008407; +R0.L = R0.L >>> 3; +R1.L = R1.L >>> 3; +R2.L = R2.L >>> 3; +R3.L = R3.L >>> 3; +R4.L = R4.L >>> 3; +R5.L = R5.L >>> 3; +R6.L = R6.L >>> 3; +R7.L = R7.L >>> 3; +CHECKREG r0, 0x0000F080; +CHECKREG r1, 0x0000F080; +CHECKREG r2, 0x0000F080; +CHECKREG r3, 0x0030FFFE; +CHECKREG r4, 0x0000F080; +CHECKREG r5, 0x0000F080; +CHECKREG r6, 0x0000F080; +CHECKREG r7, 0x0000F080; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x05000500; +imm32 r1, 0x85010500; +imm32 r2, 0x85020500; +imm32 r3, 0x85030500; +imm32 r4, 0x85040500; +imm32 r5, 0x85050500; +imm32 r6, 0x85060500; +imm32 r7, 0x85070500; +R0.L = R0.H >>> 10; +R1.L = R1.H >>> 10; +R2.L = R2.H >>> 10; +R3.L = R3.H >>> 10; +R4.L = R4.H >>> 10; +R5.L = R5.H >>> 10; +R6.L = R6.H >>> 10; +R7.L = R7.H >>> 10; +CHECKREG r0, 0x05000001; +CHECKREG r1, 0x8501FFE1; +CHECKREG r2, 0x8502FFE1; +CHECKREG r3, 0x8503FFE1; +CHECKREG r4, 0x8504FFE1; +CHECKREG r5, 0x8505FFE1; +CHECKREG r6, 0x8506FFE1; +CHECKREG r7, 0x8507FFE1; + +imm32 r0, 0x80610000; +R1.L = -1; +imm32 r2, 0x80620000; +imm32 r3, 0x80630000; +imm32 r4, 0x80640000; +imm32 r5, 0x80650000; +imm32 r6, 0x80660000; +imm32 r7, 0x80670000; +R0.L = R0.H >>> 11; +R1.L = R1.H >>> 11; +R2.L = R2.H >>> 11; +R3.L = R3.H >>> 11; +R4.L = R4.H >>> 11; +R5.L = R5.H >>> 11; +R6.L = R6.H >>> 11; +R7.L = R7.H >>> 11; +CHECKREG r0, 0x8061FFF0; +CHECKREG r1, 0x8501FFF0; +CHECKREG r2, 0x8062FFF0; +CHECKREG r3, 0x8063FFF0; +CHECKREG r4, 0x8064FFF0; +CHECKREG r5, 0x8065FFF0; +CHECKREG r6, 0x8066FFF0; +CHECKREG r7, 0x8067FFF0; + + +imm32 r0, 0xa0010070; +imm32 r1, 0xa0010070; +R2.L = -15; +imm32 r3, 0xa0030070; +imm32 r4, 0xa0040070; +imm32 r5, 0xa0050070; +imm32 r6, 0xa0060070; +imm32 r7, 0xa0070070; +R0.L = R0.H >>> 12; +R1.L = R1.H >>> 12; +R2.L = R2.H >>> 12; +R3.L = R3.H >>> 12; +R4.L = R4.H >>> 12; +R5.L = R5.H >>> 12; +R6.L = R6.H >>> 12; +R7.L = R7.H >>> 12; +CHECKREG r0, 0xA001FFFA; +CHECKREG r1, 0xA001FFFA; +CHECKREG r2, 0x8062FFF8; +CHECKREG r3, 0xA003FFFA; +CHECKREG r4, 0xA004FFFA; +CHECKREG r5, 0xA005FFFA; +CHECKREG r6, 0xA006FFFA; +CHECKREG r7, 0xA007FFFA; + +imm32 r0, 0xb8010001; +imm32 r1, 0xb8010001; +imm32 r2, 0xb8020002; +R3.L = -16; +imm32 r4, 0xb8040004; +imm32 r5, 0xb8050005; +imm32 r6, 0xb8060006; +imm32 r7, 0xb8070007; +R0.L = R0.H >>> 13; +R1.L = R1.H >>> 13; +R2.L = R2.H >>> 13; +R3.L = R3.H >>> 13; +R4.L = R4.H >>> 13; +R5.L = R5.H >>> 13; +R6.L = R6.H >>> 13; +R7.L = R7.H >>> 13; +CHECKREG r0, 0xB801FFFD; +CHECKREG r1, 0xB801FFFD; +CHECKREG r2, 0xB802FFFD; +CHECKREG r3, 0xA003FFFD; +CHECKREG r4, 0xB804FFFD; +CHECKREG r5, 0xB805FFFD; +CHECKREG r6, 0xB806FFFD; +CHECKREG r7, 0xB807FFFD; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009000; +imm32 r5, 0x00009005; +imm32 r6, 0x00009006; +imm32 r7, 0x00009007; +R0.H = R0.L >>> 14; +R1.H = R1.L >>> 14; +R2.H = R2.L >>> 14; +R3.H = R3.L >>> 14; +R4.H = R4.L >>> 14; +R5.H = R5.L >>> 14; +R6.H = R6.L >>> 14; +R7.H = R7.L >>> 14; +CHECKREG r0, 0xFFFE9001; +CHECKREG r1, 0xFFFE9001; +CHECKREG r2, 0xFFFE9002; +CHECKREG r3, 0xFFFE9003; +CHECKREG r4, 0xFFFE9000; +CHECKREG r5, 0xFFFE9005; +CHECKREG r6, 0xFFFE9006; +CHECKREG r7, 0xFFFE9007; + +imm32 r0, 0xa0008001; +imm32 r1, 0xa0008001; +imm32 r2, 0xa0008002; +imm32 r3, 0xa0008003; +imm32 r4, 0xa0008004; +R5.L = -1; +imm32 r6, 0xa0008006; +imm32 r7, 0xa0008007; +R0.H = R0.L >>> 5; +R1.H = R1.L >>> 5; +R2.H = R2.L >>> 5; +R3.H = R3.L >>> 5; +R4.H = R4.L >>> 5; +R5.H = R5.L >>> 5; +R6.H = R6.L >>> 5; +R7.H = R7.L >>> 5; +CHECKREG r0, 0xFC008001; +CHECKREG r1, 0xFC008001; +CHECKREG r2, 0xFC008002; +CHECKREG r3, 0xFC008003; +CHECKREG r4, 0xFC008004; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFC008006; +CHECKREG r7, 0xFC008007; + + +imm32 r0, 0x00009b01; +imm32 r1, 0x00009b01; +imm32 r2, 0x00009b02; +imm32 r3, 0x00009b03; +imm32 r4, 0x00009b04; +imm32 r5, 0x00009b05; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = R0.L >>> 6; +R1.H = R1.L >>> 6; +R2.H = R2.L >>> 6; +R3.H = R3.L >>> 6; +R4.H = R4.L >>> 6; +R5.H = R5.L >>> 6; +R6.H = R6.L >>> 6; +R7.H = R7.L >>> 6; +CHECKREG r0, 0xFE6C9B01; +CHECKREG r1, 0xFE6C9B01; +CHECKREG r2, 0xFE6C9B02; +CHECKREG r3, 0xFE6C9B03; +CHECKREG r4, 0xFE6C9B04; +CHECKREG r5, 0xFE6C9B05; +CHECKREG r6, 0xFFFFFFF1; +CHECKREG r7, 0xFE409007; + +imm32 r0, 0x0000a0c1; +imm32 r1, 0x0000a0c1; +imm32 r2, 0x0000a0c2; +imm32 r3, 0x0000a0c3; +imm32 r4, 0x0000a0c4; +imm32 r5, 0x0000a0c5; +imm32 r6, 0x0000a0c6; +R7.L = -16; +R0.H = R0.L >>> 7; +R1.H = R1.L >>> 7; +R2.H = R2.L >>> 7; +R3.H = R3.L >>> 7; +R4.H = R4.L >>> 7; +R5.H = R5.L >>> 7; +R6.H = R6.L >>> 7; +R7.H = R7.L >>> 7; +CHECKREG r0, 0xFF41A0C1; +CHECKREG r1, 0xFF41A0C1; +CHECKREG r2, 0xFF41A0C2; +CHECKREG r3, 0xFF41A0C3; +CHECKREG r4, 0xFF41A0C4; +CHECKREG r5, 0xFF41A0C5; +CHECKREG r6, 0xFF41A0C6; +CHECKREG r7, 0xFFFFFFF0; + +imm32 r0, 0x80010d00; +imm32 r1, 0x80010d00; +imm32 r2, 0x80020d00; +imm32 r3, 0x80030d00; +R4.L = -1; +imm32 r5, 0x80050d00; +imm32 r6, 0x80060d00; +imm32 r7, 0x80070d00; +R0.H = R0.H >>> 14; +R1.H = R1.H >>> 14; +R2.H = R2.H >>> 14; +R3.H = R3.H >>> 14; +R4.H = R4.H >>> 14; +R5.H = R5.H >>> 14; +R6.H = R6.H >>> 14; +R7.H = R7.H >>> 14; +CHECKREG r0, 0xFFFE0D00; +CHECKREG r1, 0xFFFE0D00; +CHECKREG r2, 0xFFFE0D00; +CHECKREG r3, 0xFFFE0D00; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFE0D00; +CHECKREG r6, 0xFFFE0D00; +CHECKREG r7, 0xFFFE0D00; + +imm32 r0, 0x8d010000; +imm32 r1, 0x8d010000; +imm32 r2, 0x8d020000; +imm32 r3, 0x8d030000; +imm32 r4, 0x8d040000; +R5.L = -1; +imm32 r6, 0x8d060000; +imm32 r7, 0x8d070000; +R0.H = R0.H >>> 15; +R1.H = R1.H >>> 15; +R2.H = R2.H >>> 15; +R3.H = R3.H >>> 15; +R4.H = R4.H >>> 15; +R5.H = R5.H >>> 15; +R6.H = R6.H >>> 15; +R7.H = R7.H >>> 15; +CHECKREG r0, 0xFFFF0000; +CHECKREG r1, 0xFFFF0000; +CHECKREG r2, 0xFFFF0000; +CHECKREG r3, 0xFFFF0000; +CHECKREG r4, 0xFFFF0000; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFF0000; +CHECKREG r7, 0xFFFF0000; + + +imm32 r0, 0xde010000; +imm32 r1, 0xde010000; +imm32 r2, 0xde020000; +imm32 r3, 0xde030000; +imm32 r4, 0xde040000; +imm32 r5, 0xde050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = R0.H >>> 10; +R1.L = R1.H >>> 10; +R2.L = R2.H >>> 10; +R3.L = R3.H >>> 10; +R4.L = R4.H >>> 10; +R5.L = R5.H >>> 10; +R6.L = R6.H >>> 10; +R7.L = R7.H >>> 10; +CHECKREG r0, 0xDE01FFF7; +CHECKREG r1, 0xDE01FFF7; +CHECKREG r2, 0xDE02FFF7; +CHECKREG r3, 0xDE03FFF7; +CHECKREG r4, 0xDE04FFF7; +CHECKREG r5, 0xDE05FFF7; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xD007FFF4; + +imm32 r0, 0x9f010c00; +imm32 r1, 0xaf010c00; +imm32 r2, 0xbf020c00; +imm32 r3, 0xcf030c00; +imm32 r4, 0xdf040c00; +imm32 r5, 0xef050c00; +imm32 r6, 0xff060c00; +R7.L = -16; +R0.H = R0.H >>> 5; +R1.H = R1.H >>> 5; +R2.H = R2.H >>> 5; +R3.H = R3.H >>> 5; +R4.H = R4.H >>> 5; +R5.H = R5.H >>> 5; +R6.H = R6.H >>> 5; +R7.H = R7.H >>> 5; +CHECKREG r0, 0xFCF80C00; +CHECKREG r1, 0xFD780C00; +CHECKREG r2, 0xFDF80C00; +CHECKREG r3, 0xFE780C00; +CHECKREG r4, 0xFEF80C00; +CHECKREG r5, 0xFF780C00; +CHECKREG r6, 0xFFF80C00; +CHECKREG r7, 0xFE80FFF0; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn_s.s new file mode 100644 index 0000000..20770d5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn_s.s @@ -0,0 +1,418 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_rn_s/c_dsp32shiftim_ahalf_rn_s.dsp +// Spec Reference: dsp32shift ashift +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = R0.L >>> 10; +R1.L = R1.L >>> 10; +R2.L = R2.L >>> 10; +R3.L = R3.L >>> 10; +R4.L = R4.L >>> 10; +R5.L = R5.L >>> 10; +R6.L = R6.L >>> 10; +R7.L = R7.L >>> 10; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x0000FFE0; +CHECKREG r2, 0x0000FFE0; +CHECKREG r3, 0x0000FFE0; +CHECKREG r4, 0x0000FFE0; +CHECKREG r5, 0x0000FFE0; +CHECKREG r6, 0x0000FFE0; +CHECKREG r7, 0x0000FFE0; + +imm32 r0, 0x02008020; +imm32 r0, 0x02008021; +imm32 r2, 0x02008022; +imm32 r3, 0x02008023; +imm32 r4, 0x02008024; +imm32 r5, 0x02008025; +imm32 r6, 0x02008026; +imm32 r7, 0x02008027; +R0.L = R0.L >>> 11; +R1.L = R1.L >>> 11; +R2.L = R2.L >>> 11; +R3.L = R3.L >>> 11; +R4.L = R4.L >>> 11; +R5.L = R5.L >>> 11; +R6.L = R6.L >>> 11; +R7.L = R7.L >>> 11; +CHECKREG r0, 0x0200FFF0; +CHECKREG r1, 0x0000FFFF; +CHECKREG r2, 0x0200FFF0; +CHECKREG r3, 0x0200FFF0; +CHECKREG r4, 0x0200FFF0; +CHECKREG r5, 0x0200FFF0; +CHECKREG r6, 0x0200FFF0; +CHECKREG r7, 0x0200FFF0; + + +imm32 r0, 0x00308001; +imm32 r1, 0x00308001; +R2.L = -15; +imm32 r3, 0x00308003; +imm32 r4, 0x00308004; +imm32 r5, 0x00308005; +imm32 r6, 0x00308006; +imm32 r7, 0x00308007; +R0.L = R0.L >>> 12; +R1.L = R1.L >>> 12; +R2.L = R2.L >>> 12; +R3.L = R3.L >>> 12; +R4.L = R4.L >>> 12; +R5.L = R5.L >>> 12; +R6.L = R6.L >>> 12; +R7.L = R7.L >>> 12; +CHECKREG r0, 0x0030FFF8; +CHECKREG r1, 0x0030FFF8; +CHECKREG r2, 0x0200FFFF; +CHECKREG r3, 0x0030FFF8; +CHECKREG r4, 0x0030FFF8; +CHECKREG r5, 0x0030FFF8; +CHECKREG r6, 0x0030FFF8; +CHECKREG r7, 0x0030FFF8; + +imm32 r0, 0x00008401; +imm32 r1, 0x00008401; +imm32 r2, 0x00008402; +R3.L = -16; +imm32 r4, 0x00008404; +imm32 r5, 0x00008405; +imm32 r6, 0x00008406; +imm32 r7, 0x00008407; +R0.L = R0.L >>> 3; +R1.L = R1.L >>> 3; +R2.L = R2.L >>> 3; +R3.L = R3.L >>> 3; +R4.L = R4.L >>> 3; +R5.L = R5.L >>> 3; +R6.L = R6.L >>> 3; +R7.L = R7.L >>> 3; +CHECKREG r0, 0x0000F080; +CHECKREG r1, 0x0000F080; +CHECKREG r2, 0x0000F080; +CHECKREG r3, 0x0030FFFE; +CHECKREG r4, 0x0000F080; +CHECKREG r5, 0x0000F080; +CHECKREG r6, 0x0000F080; +CHECKREG r7, 0x0000F080; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x05000500; +imm32 r1, 0x85010500; +imm32 r2, 0x85020500; +imm32 r3, 0x85030500; +imm32 r4, 0x85040500; +imm32 r5, 0x85050500; +imm32 r6, 0x85060500; +imm32 r7, 0x85070500; +R0.L = R0.H >>> 10; +R1.L = R1.H >>> 10; +R2.L = R2.H >>> 10; +R3.L = R3.H >>> 10; +R4.L = R4.H >>> 10; +R5.L = R5.H >>> 10; +R6.L = R6.H >>> 10; +R7.L = R7.H >>> 10; +CHECKREG r0, 0x05000001; +CHECKREG r1, 0x8501FFE1; +CHECKREG r2, 0x8502FFE1; +CHECKREG r3, 0x8503FFE1; +CHECKREG r4, 0x8504FFE1; +CHECKREG r5, 0x8505FFE1; +CHECKREG r6, 0x8506FFE1; +CHECKREG r7, 0x8507FFE1; + +imm32 r0, 0x80610000; +R1.L = -1; +imm32 r2, 0x80620000; +imm32 r3, 0x80630000; +imm32 r4, 0x80640000; +imm32 r5, 0x80650000; +imm32 r6, 0x80660000; +imm32 r7, 0x80670000; +R0.L = R0.H >>> 11; +R1.L = R1.H >>> 11; +R2.L = R2.H >>> 11; +R3.L = R3.H >>> 11; +R4.L = R4.H >>> 11; +R5.L = R5.H >>> 11; +R6.L = R6.H >>> 11; +R7.L = R7.H >>> 11; +CHECKREG r0, 0x8061FFF0; +CHECKREG r1, 0x8501FFF0; +CHECKREG r2, 0x8062FFF0; +CHECKREG r3, 0x8063FFF0; +CHECKREG r4, 0x8064FFF0; +CHECKREG r5, 0x8065FFF0; +CHECKREG r6, 0x8066FFF0; +CHECKREG r7, 0x8067FFF0; + + +imm32 r0, 0xa0010070; +imm32 r1, 0xa0010070; +R2.L = -15; +imm32 r3, 0xa0030070; +imm32 r4, 0xa0040070; +imm32 r5, 0xa0050070; +imm32 r6, 0xa0060070; +imm32 r7, 0xa0070070; +R0.L = R0.H >>> 12; +R1.L = R1.H >>> 12; +R2.L = R2.H >>> 12; +R3.L = R3.H >>> 12; +R4.L = R4.H >>> 12; +R5.L = R5.H >>> 12; +R6.L = R6.H >>> 12; +R7.L = R7.H >>> 12; +CHECKREG r0, 0xA001FFFA; +CHECKREG r1, 0xA001FFFA; +CHECKREG r2, 0x8062FFF8; +CHECKREG r3, 0xA003FFFA; +CHECKREG r4, 0xA004FFFA; +CHECKREG r5, 0xA005FFFA; +CHECKREG r6, 0xA006FFFA; +CHECKREG r7, 0xA007FFFA; + +imm32 r0, 0xb8010001; +imm32 r1, 0xb8010001; +imm32 r2, 0xb8020002; +R3.L = -16; +imm32 r4, 0xb8040004; +imm32 r5, 0xb8050005; +imm32 r6, 0xb8060006; +imm32 r7, 0xb8070007; +R0.L = R0.H >>> 13; +R1.L = R1.H >>> 13; +R2.L = R2.H >>> 13; +R3.L = R3.H >>> 13; +R4.L = R4.H >>> 13; +R5.L = R5.H >>> 13; +R6.L = R6.H >>> 13; +R7.L = R7.H >>> 13; +CHECKREG r0, 0xB801FFFD; +CHECKREG r1, 0xB801FFFD; +CHECKREG r2, 0xB802FFFD; +CHECKREG r3, 0xA003FFFD; +CHECKREG r4, 0xB804FFFD; +CHECKREG r5, 0xB805FFFD; +CHECKREG r6, 0xB806FFFD; +CHECKREG r7, 0xB807FFFD; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009000; +imm32 r5, 0x00009005; +imm32 r6, 0x00009006; +imm32 r7, 0x00009007; +R0.H = R0.L >>> 14; +R1.H = R1.L >>> 14; +R2.H = R2.L >>> 14; +R3.H = R3.L >>> 14; +R4.H = R4.L >>> 14; +R5.H = R5.L >>> 14; +R6.H = R6.L >>> 14; +R7.H = R7.L >>> 14; +CHECKREG r0, 0xFFFE9001; +CHECKREG r1, 0xFFFE9001; +CHECKREG r2, 0xFFFE9002; +CHECKREG r3, 0xFFFE9003; +CHECKREG r4, 0xFFFE9000; +CHECKREG r5, 0xFFFE9005; +CHECKREG r6, 0xFFFE9006; +CHECKREG r7, 0xFFFE9007; + +imm32 r0, 0xa0008001; +imm32 r1, 0xa0008001; +imm32 r2, 0xa0008002; +imm32 r3, 0xa0008003; +imm32 r4, 0xa0008004; +R5.L = -1; +imm32 r6, 0xa0008006; +imm32 r7, 0xa0008007; +R0.H = R0.L >>> 5; +R1.H = R1.L >>> 5; +R2.H = R2.L >>> 5; +R3.H = R3.L >>> 5; +R4.H = R4.L >>> 5; +R5.H = R5.L >>> 5; +R6.H = R6.L >>> 5; +R7.H = R7.L >>> 5; +CHECKREG r0, 0xFC008001; +CHECKREG r1, 0xFC008001; +CHECKREG r2, 0xFC008002; +CHECKREG r3, 0xFC008003; +CHECKREG r4, 0xFC008004; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFC008006; +CHECKREG r7, 0xFC008007; + + +imm32 r0, 0x00009b01; +imm32 r1, 0x00009b01; +imm32 r2, 0x00009b02; +imm32 r3, 0x00009b03; +imm32 r4, 0x00009b04; +imm32 r5, 0x00009b05; +R6.L = -15; +imm32 r7, 0x00009007; +R0.H = R0.L >>> 6; +R1.H = R1.L >>> 6; +R2.H = R2.L >>> 6; +R3.H = R3.L >>> 6; +R4.H = R4.L >>> 6; +R5.H = R5.L >>> 6; +R6.H = R6.L >>> 6; +R7.H = R7.L >>> 6; +CHECKREG r0, 0xFE6C9B01; +CHECKREG r1, 0xFE6C9B01; +CHECKREG r2, 0xFE6C9B02; +CHECKREG r3, 0xFE6C9B03; +CHECKREG r4, 0xFE6C9B04; +CHECKREG r5, 0xFE6C9B05; +CHECKREG r6, 0xFFFFFFF1; +CHECKREG r7, 0xFE409007; + +imm32 r0, 0x0000a0c1; +imm32 r1, 0x0000a0c1; +imm32 r2, 0x0000a0c2; +imm32 r3, 0x0000a0c3; +imm32 r4, 0x0000a0c4; +imm32 r5, 0x0000a0c5; +imm32 r6, 0x0000a0c6; +R7.L = -16; +R0.H = R0.L >>> 7; +R1.H = R1.L >>> 7; +R2.H = R2.L >>> 7; +R3.H = R3.L >>> 7; +R4.H = R4.L >>> 7; +R5.H = R5.L >>> 7; +R6.H = R6.L >>> 7; +R7.H = R7.L >>> 7; +CHECKREG r0, 0xFF41A0C1; +CHECKREG r1, 0xFF41A0C1; +CHECKREG r2, 0xFF41A0C2; +CHECKREG r3, 0xFF41A0C3; +CHECKREG r4, 0xFF41A0C4; +CHECKREG r5, 0xFF41A0C5; +CHECKREG r6, 0xFF41A0C6; +CHECKREG r7, 0xFFFFFFF0; + +imm32 r0, 0x80010d00; +imm32 r1, 0x80010d00; +imm32 r2, 0x80020d00; +imm32 r3, 0x80030d00; +R4.L = -1; +imm32 r5, 0x80050d00; +imm32 r6, 0x80060d00; +imm32 r7, 0x80070d00; +R0.H = R0.H >>> 14; +R1.H = R1.H >>> 14; +R2.H = R2.H >>> 14; +R3.H = R3.H >>> 14; +R4.H = R4.H >>> 14; +R5.H = R5.H >>> 14; +R6.H = R6.H >>> 14; +R7.H = R7.H >>> 14; +CHECKREG r0, 0xFFFE0D00; +CHECKREG r1, 0xFFFE0D00; +CHECKREG r2, 0xFFFE0D00; +CHECKREG r3, 0xFFFE0D00; +CHECKREG r4, 0xFFFFFFFF; +CHECKREG r5, 0xFFFE0D00; +CHECKREG r6, 0xFFFE0D00; +CHECKREG r7, 0xFFFE0D00; + +imm32 r0, 0x8d010000; +imm32 r1, 0x8d010000; +imm32 r2, 0x8d020000; +imm32 r3, 0x8d030000; +imm32 r4, 0x8d040000; +R5.L = -1; +imm32 r6, 0x8d060000; +imm32 r7, 0x8d070000; +R0.H = R0.H >>> 15; +R1.H = R1.H >>> 15; +R2.H = R2.H >>> 15; +R3.H = R3.H >>> 15; +R4.H = R4.H >>> 15; +R5.H = R5.H >>> 15; +R6.H = R6.H >>> 15; +R7.H = R7.H >>> 15; +CHECKREG r0, 0xFFFF0000; +CHECKREG r1, 0xFFFF0000; +CHECKREG r2, 0xFFFF0000; +CHECKREG r3, 0xFFFF0000; +CHECKREG r4, 0xFFFF0000; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0xFFFF0000; +CHECKREG r7, 0xFFFF0000; + + +imm32 r0, 0xde010000; +imm32 r1, 0xde010000; +imm32 r2, 0xde020000; +imm32 r3, 0xde030000; +imm32 r4, 0xde040000; +imm32 r5, 0xde050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R0.L = R0.H >>> 10; +R1.L = R1.H >>> 10; +R2.L = R2.H >>> 10; +R3.L = R3.H >>> 10; +R4.L = R4.H >>> 10; +R5.L = R5.H >>> 10; +R6.L = R6.H >>> 10; +R7.L = R7.H >>> 10; +CHECKREG r0, 0xDE01FFF7; +CHECKREG r1, 0xDE01FFF7; +CHECKREG r2, 0xDE02FFF7; +CHECKREG r3, 0xDE03FFF7; +CHECKREG r4, 0xDE04FFF7; +CHECKREG r5, 0xDE05FFF7; +CHECKREG r6, 0xFFFFFFFF; +CHECKREG r7, 0xD007FFF4; + +imm32 r0, 0x9f010c00; +imm32 r1, 0xaf010c00; +imm32 r2, 0xbf020c00; +imm32 r3, 0xcf030c00; +imm32 r4, 0xdf040c00; +imm32 r5, 0xef050c00; +imm32 r6, 0xff060c00; +R7.L = -16; +R0.H = R0.H >>> 5; +R1.H = R1.H >>> 5; +R2.H = R2.H >>> 5; +R3.H = R3.H >>> 5; +R4.H = R4.H >>> 5; +R5.H = R5.H >>> 5; +R6.H = R6.H >>> 5; +R7.H = R7.H >>> 5; +CHECKREG r0, 0xFCF80C00; +CHECKREG r1, 0xFD780C00; +CHECKREG r2, 0xFDF80C00; +CHECKREG r3, 0xFE780C00; +CHECKREG r4, 0xFEF80C00; +CHECKREG r5, 0xFF780C00; +CHECKREG r6, 0xFFF80C00; +CHECKREG r7, 0xFE80FFF0; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp.s new file mode 100644 index 0000000..471795e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp.s @@ -0,0 +1,420 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_rp/c_dsp32shiftim_ahalf_rp.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + +// Ashift : positive data, count (+)=right (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00010001; +imm32 r2, 0x00010002; +imm32 r3, 0x00010003; +imm32 r4, 0x00010004; +imm32 r5, 0x00010005; +imm32 r6, 0x00010006; +imm32 r7, 0x00010007; +R0.L = R0.L >>> 1; +R1.L = R1.L >>> 1; +R2.L = R2.L >>> 1; +R3.L = R3.L >>> 1; +R4.L = R4.L >>> 1; +R5.L = R5.L >>> 1; +R6.L = R6.L >>> 1; +R7.L = R7.L >>> 1; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00010001; +CHECKREG r3, 0x00010001; +CHECKREG r4, 0x00010002; +CHECKREG r5, 0x00010002; +CHECKREG r6, 0x00010003; +CHECKREG r7, 0x00010003; + +imm32 r0, 0x00201001; +R1.L = -1; +imm32 r2, 0x00202002; +imm32 r3, 0x00203003; +imm32 r4, 0x00204004; +imm32 r5, 0x00205005; +imm32 r6, 0x00206006; +imm32 r7, 0x00207007; +R7.L = R0.L >>> 5; +R0.L = R1.L >>> 5; +R1.L = R2.L >>> 5; +R2.L = R3.L >>> 5; +R3.L = R4.L >>> 5; +R4.L = R5.L >>> 5; +R5.L = R6.L >>> 5; +R6.L = R7.L >>> 5; +CHECKREG r0, 0x0020FFFF; +CHECKREG r1, 0x00010100; +CHECKREG r2, 0x00200180; +CHECKREG r3, 0x00200200; +CHECKREG r4, 0x00200280; +CHECKREG r5, 0x00200300; +CHECKREG r6, 0x00200004; +CHECKREG r7, 0x00200080; + + +imm32 r0, 0x03001001; +imm32 r1, 0x03001001; +R2.L = -15; +imm32 r3, 0x03003003; +imm32 r4, 0x03004004; +imm32 r5, 0x03005005; +imm32 r6, 0x03006006; +imm32 r7, 0x03007007; +R6.L = R0.L >>> 2; +R7.L = R1.L >>> 2; +R0.L = R2.L >>> 2; +R1.L = R3.L >>> 2; +R2.L = R4.L >>> 2; +R3.L = R5.L >>> 2; +R4.L = R6.L >>> 2; +R5.L = R7.L >>> 2; +CHECKREG r0, 0x0300FFFC; +CHECKREG r1, 0x03000C00; +CHECKREG r2, 0x00201001; +CHECKREG r3, 0x03001401; +CHECKREG r4, 0x03000100; +CHECKREG r5, 0x03000100; +CHECKREG r6, 0x03000400; +CHECKREG r7, 0x03000400; + +imm32 r0, 0x40001001; +imm32 r1, 0x40001001; +imm32 r2, 0x40002002; +R3.L = -16; +imm32 r4, 0x40004004; +imm32 r5, 0x40005005; +imm32 r6, 0x40006006; +imm32 r7, 0x40007007; +R5.L = R0.L >>> 13; +R6.L = R1.L >>> 13; +R7.L = R2.L >>> 13; +R0.L = R3.L >>> 13; +R1.L = R4.L >>> 13; +R2.L = R5.L >>> 13; +R3.L = R6.L >>> 13; +R4.L = R7.L >>> 13; +CHECKREG r0, 0x4000FFFF; +CHECKREG r1, 0x40000002; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0x03000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x40000000; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x40000001; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x50000000; +imm32 r1, 0x50010000; +imm32 r2, 0x50020000; +imm32 r3, 0x50030000; +imm32 r4, 0x50040000; +imm32 r5, 0x50050000; +imm32 r6, 0x50060000; +imm32 r7, 0x50070000; +R3.L = R0.H >>> 10; +R4.L = R1.H >>> 10; +R5.L = R2.H >>> 10; +R6.L = R3.H >>> 10; +R7.L = R4.H >>> 10; +R0.L = R5.H >>> 10; +R1.L = R6.H >>> 10; +R2.L = R7.H >>> 10; +CHECKREG r0, 0x50000014; +CHECKREG r1, 0x50010014; +CHECKREG r2, 0x50020014; +CHECKREG r3, 0x50030014; +CHECKREG r4, 0x50040014; +CHECKREG r5, 0x50050014; +CHECKREG r6, 0x50060014; +CHECKREG r7, 0x50070014; + +imm32 r0, 0x10016000; +R1.L = -1; +imm32 r2, 0x20026000; +imm32 r3, 0x30036000; +imm32 r4, 0x40046000; +imm32 r5, 0x50056000; +imm32 r6, 0x60060000; +imm32 r7, 0x70076000; +R0.L = R0.H >>> 11; +R1.L = R1.H >>> 11; +R2.L = R2.H >>> 11; +R3.L = R3.H >>> 11; +R4.L = R4.H >>> 11; +R5.L = R5.H >>> 11; +R6.L = R6.H >>> 11; +R7.L = R7.H >>> 11; +CHECKREG r0, 0x10010002; +CHECKREG r1, 0x5001000A; +CHECKREG r2, 0x20020004; +CHECKREG r3, 0x30030006; +CHECKREG r4, 0x40040008; +CHECKREG r5, 0x5005000A; +CHECKREG r6, 0x6006000C; +CHECKREG r7, 0x7007000E; + + +imm32 r0, 0x10010700; +imm32 r1, 0x10010700; +R2.L = -15; +imm32 r3, 0x30030700; +imm32 r4, 0x40040000; +imm32 r5, 0x50050700; +imm32 r6, 0x60060000; +imm32 r7, 0x70070700; +R0.L = R0.H >>> 15; +R1.L = R1.H >>> 15; +R2.L = R2.H >>> 15; +R3.L = R3.H >>> 15; +R4.L = R4.H >>> 15; +R5.L = R5.H >>> 15; +R6.L = R6.H >>> 15; +R7.L = R7.H >>> 15; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x18010001; +imm32 r1, 0x18010001; +imm32 r2, 0x28020002; +R3.L = -16; +imm32 r4, 0x48040004; +imm32 r5, 0x58050005; +imm32 r6, 0x68060006; +imm32 r7, 0x78070007; +R0.L = R0.H >>> 13; +R1.L = R1.H >>> 13; +R2.L = R2.H >>> 13; +R3.L = R3.H >>> 13; +R4.L = R4.H >>> 13; +R5.L = R5.H >>> 13; +R6.L = R6.H >>> 13; +R7.L = R7.H >>> 13; +CHECKREG r0, 0x18010000; +CHECKREG r1, 0x18010000; +CHECKREG r2, 0x28020001; +CHECKREG r3, 0x30030001; +CHECKREG r4, 0x48040002; +CHECKREG r5, 0x58050002; +CHECKREG r6, 0x68060003; +CHECKREG r7, 0x78070003; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x09000091; +imm32 r1, 0x09000091; +imm32 r2, 0x09000092; +imm32 r3, 0x09000093; +imm32 r4, 0x09000090; +imm32 r5, 0x09000095; +imm32 r6, 0x09000096; +imm32 r7, 0x09000097; +R0.H = R0.L >>> 14; +R1.H = R1.L >>> 14; +R2.H = R2.L >>> 14; +R3.H = R3.L >>> 14; +R4.H = R4.L >>> 14; +R5.H = R5.L >>> 14; +R6.H = R6.L >>> 14; +R7.H = R7.L >>> 14; +CHECKREG r0, 0x00000091; +CHECKREG r1, 0x00000091; +CHECKREG r2, 0x00000092; +CHECKREG r3, 0x00000093; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0x00000095; +CHECKREG r6, 0x00000096; +CHECKREG r7, 0x00000097; + +imm32 r0, 0xa0000001; +imm32 r1, 0xa0000001; +imm32 r2, 0xa0000002; +imm32 r3, 0xa0000003; +imm32 r4, 0xa0000004; +R5.L = -1; +imm32 r6, 0xa0000006; +imm32 r7, 0xa0000007; +R0.H = R0.L >>> 15; +R1.H = R1.L >>> 15; +R2.H = R2.L >>> 15; +R3.H = R3.L >>> 15; +R4.H = R4.L >>> 15; +R5.H = R5.L >>> 15; +R6.H = R6.L >>> 15; +R7.H = R7.L >>> 15; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + + +imm32 r0, 0xb0001001; +imm32 r1, 0xb0001001; +imm32 r1, 0xb0002002; +imm32 r3, 0xb0003003; +imm32 r4, 0xb0004004; +imm32 r5, 0xb0005005; +R6.L = -15; +imm32 r7, 0xb0007007; +R0.H = R0.L >>> 6; +R1.H = R1.L >>> 6; +R2.H = R2.L >>> 6; +R3.H = R3.L >>> 6; +R4.H = R4.L >>> 6; +R5.H = R5.L >>> 6; +R6.H = R6.L >>> 6; +R7.H = R7.L >>> 6; +CHECKREG r0, 0x00401001; +CHECKREG r1, 0x00802002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00C03003; +CHECKREG r4, 0x01004004; +CHECKREG r5, 0x01405005; +CHECKREG r6, 0xFFFFFFF1; +CHECKREG r7, 0x01C07007; + +imm32 r0, 0x0c001c01; +imm32 r1, 0x0c002c01; +imm32 r2, 0x0c002c02; +imm32 r3, 0x0c003c03; +imm32 r4, 0x0c004c04; +imm32 r5, 0x0c005c05; +imm32 r6, 0x0c006c06; +R7.L = -16; +R0.H = R0.L >>> 7; +R1.H = R1.L >>> 7; +R2.H = R2.L >>> 7; +R3.H = R3.L >>> 7; +R4.H = R4.L >>> 7; +R5.H = R5.L >>> 7; +R6.H = R6.L >>> 7; +R7.H = R7.L >>> 7; +CHECKREG r0, 0x00381C01; +CHECKREG r1, 0x00582C01; +CHECKREG r2, 0x00582C02; +CHECKREG r3, 0x00783C03; +CHECKREG r4, 0x00984C04; +CHECKREG r5, 0x00B85C05; +CHECKREG r6, 0x00D86C06; +CHECKREG r7, 0xFFFFFFF0; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x0d01d000; +imm32 r1, 0x0d01d000; +imm32 r2, 0x0d02d000; +imm32 r3, 0x0d03d000; +R4.L = -1; +imm32 r5, 0x0d05d000; +imm32 r6, 0x0d06d000; +imm32 r7, 0x0d07d000; +R0.H = R0.H >>> 4; +R1.H = R1.H >>> 4; +R2.H = R2.H >>> 4; +R3.H = R3.H >>> 4; +R4.H = R4.H >>> 4; +R5.H = R5.H >>> 4; +R6.H = R6.H >>> 4; +R7.H = R6.H >>> 4; +CHECKREG r0, 0x00D0D000; +CHECKREG r1, 0x00D0D000; +CHECKREG r2, 0x00D0D000; +CHECKREG r3, 0x00D0D000; +CHECKREG r4, 0x0009FFFF; +CHECKREG r5, 0x00D0D000; +CHECKREG r6, 0x00D0D000; +CHECKREG r7, 0x000DD000; + +imm32 r0, 0x1e010000; +imm32 r1, 0x1e010000; +imm32 r2, 0x2e020000; +imm32 r3, 0x3e030000; +imm32 r4, 0x4e040000; +R5.L = -1; +imm32 r6, 0x6e060000; +imm32 r7, 0x7e070000; +R7.H = R0.H >>> 15; +R6.H = R1.H >>> 15; +R0.H = R2.H >>> 15; +R1.H = R3.H >>> 15; +R2.H = R4.H >>> 15; +R3.H = R5.H >>> 15; +R4.H = R6.H >>> 15; +R5.H = R7.H >>> 15; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x1f010000; +imm32 r1, 0x1f010000; +imm32 r2, 0x2f020000; +imm32 r3, 0x3f030000; +imm32 r4, 0x4f040000; +imm32 r5, 0x5f050000; +R6.L = -15; +imm32 r7, 0x70070000; +R6.H = R0.H >>> 6; +R7.H = R1.H >>> 6; +R5.H = R2.H >>> 6; +R0.H = R3.H >>> 6; +R1.H = R4.H >>> 6; +R2.H = R5.H >>> 6; +R3.H = R6.H >>> 6; +R4.H = R7.H >>> 6; +CHECKREG r0, 0x00FC0000; +CHECKREG r1, 0x013C0000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00010000; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x00BC0000; +CHECKREG r6, 0x007CFFF1; +CHECKREG r7, 0x007C0000; + +imm32 r0, 0x11010a00; +imm32 r1, 0x11010b00; +imm32 r2, 0x21020d00; +imm32 r2, 0x31030c00; +imm32 r4, 0x41040d00; +imm32 r5, 0x51050e00; +imm32 r6, 0x610600f0; +R7.L = -16; +R5.H = R0.H >>> 7; +R6.H = R1.H >>> 7; +R7.H = R2.H >>> 7; +R2.H = R3.H >>> 7; +R3.H = R4.H >>> 7; +R4.H = R5.H >>> 7; +R0.H = R6.H >>> 7; +R1.H = R7.H >>> 7; +CHECKREG r0, 0x00000A00; +CHECKREG r1, 0x00000B00; +CHECKREG r2, 0x00000C00; +CHECKREG r3, 0x00820000; +CHECKREG r4, 0x00000D00; +CHECKREG r5, 0x00220E00; +CHECKREG r6, 0x002200F0; +CHECKREG r7, 0x0062FFF0; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp_s.s new file mode 100644 index 0000000..6429fb1 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rp_s.s @@ -0,0 +1,422 @@ +//Original:/testcases/core/c_dsp32shiftim_ahalf_rp_s/c_dsp32shiftim_ahalf_rp_s.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated +# mach: bfin + +.include "testutils.inc" + start + + + +// Ashift : positive data, count (+)=right (half reg) +// d_lo = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00010001; +imm32 r2, 0x00010002; +imm32 r3, 0x00010003; +imm32 r4, 0x00010004; +imm32 r5, 0x00010005; +imm32 r6, 0x00010006; +imm32 r7, 0x00010007; +R0.L = R0.L >>> 1; +R1.L = R1.L >>> 1; +R2.L = R2.L >>> 1; +R3.L = R3.L >>> 1; +R4.L = R4.L >>> 1; +R5.L = R5.L >>> 1; +R6.L = R6.L >>> 1; +R7.L = R7.L >>> 1; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00010001; +CHECKREG r3, 0x00010001; +CHECKREG r4, 0x00010002; +CHECKREG r5, 0x00010002; +CHECKREG r6, 0x00010003; +CHECKREG r7, 0x00010003; + +imm32 r0, 0x00201001; +R1.L = -1; +imm32 r2, 0x00202002; +imm32 r3, 0x00203003; +imm32 r4, 0x00204004; +imm32 r5, 0x00205005; +imm32 r6, 0x00206006; +imm32 r7, 0x00207007; +R7.L = R0.L >>> 5; +R0.L = R1.L >>> 5; +R1.L = R2.L >>> 5; +R2.L = R3.L >>> 5; +R3.L = R4.L >>> 5; +R4.L = R5.L >>> 5; +R5.L = R6.L >>> 5; +R6.L = R7.L >>> 5; +CHECKREG r0, 0x0020FFFF; +CHECKREG r1, 0x00010100; +CHECKREG r2, 0x00200180; +CHECKREG r3, 0x00200200; +CHECKREG r4, 0x00200280; +CHECKREG r5, 0x00200300; +CHECKREG r6, 0x00200004; +CHECKREG r7, 0x00200080; + + +imm32 r0, 0x03001001; +imm32 r1, 0x03001001; +R2.L = -15; +imm32 r3, 0x03003003; +imm32 r4, 0x03004004; +imm32 r5, 0x03005005; +imm32 r6, 0x03006006; +imm32 r7, 0x03007007; +R6.L = R0.L >>> 2; +R7.L = R1.L >>> 2; +R0.L = R2.L >>> 2; +R1.L = R3.L >>> 2; +R2.L = R4.L >>> 2; +R3.L = R5.L >>> 2; +R4.L = R6.L >>> 2; +R5.L = R7.L >>> 2; +CHECKREG r0, 0x0300FFFC; +CHECKREG r1, 0x03000C00; +CHECKREG r2, 0x00201001; +CHECKREG r3, 0x03001401; +CHECKREG r4, 0x03000100; +CHECKREG r5, 0x03000100; +CHECKREG r6, 0x03000400; +CHECKREG r7, 0x03000400; + +imm32 r0, 0x40001001; +imm32 r1, 0x40001001; +imm32 r2, 0x40002002; +R3.L = -16; +imm32 r4, 0x40004004; +imm32 r5, 0x40005005; +imm32 r6, 0x40006006; +imm32 r7, 0x40007007; +R5.L = R0.L >>> 13; +R6.L = R1.L >>> 13; +R7.L = R2.L >>> 13; +R0.L = R3.L >>> 13; +R1.L = R4.L >>> 13; +R2.L = R5.L >>> 13; +R3.L = R6.L >>> 13; +R4.L = R7.L >>> 13; +CHECKREG r0, 0x4000FFFF; +CHECKREG r1, 0x40000002; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0x03000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x40000000; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x40000001; + +// d_lo = ashift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x50000000; +imm32 r1, 0x50010000; +imm32 r2, 0x50020000; +imm32 r3, 0x50030000; +imm32 r4, 0x50040000; +imm32 r5, 0x50050000; +imm32 r6, 0x50060000; +imm32 r7, 0x50070000; +R3.L = R0.H >>> 10; +R4.L = R1.H >>> 10; +R5.L = R2.H >>> 10; +R6.L = R3.H >>> 10; +R7.L = R4.H >>> 10; +R0.L = R5.H >>> 10; +R1.L = R6.H >>> 10; +R2.L = R7.H >>> 10; +CHECKREG r0, 0x50000014; +CHECKREG r1, 0x50010014; +CHECKREG r2, 0x50020014; +CHECKREG r3, 0x50030014; +CHECKREG r4, 0x50040014; +CHECKREG r5, 0x50050014; +CHECKREG r6, 0x50060014; +CHECKREG r7, 0x50070014; + +imm32 r0, 0x10016000; +R1.L = -1; +imm32 r2, 0x20026000; +imm32 r3, 0x30036000; +imm32 r4, 0x40046000; +imm32 r5, 0x50056000; +imm32 r6, 0x60060000; +imm32 r7, 0x70076000; +R0.L = R0.H >>> 11; +R1.L = R1.H >>> 11; +R2.L = R2.H >>> 11; +R3.L = R3.H >>> 11; +R4.L = R4.H >>> 11; +R5.L = R5.H >>> 11; +R6.L = R6.H >>> 11; +R7.L = R7.H >>> 11; +CHECKREG r0, 0x10010002; +CHECKREG r1, 0x5001000A; +CHECKREG r2, 0x20020004; +CHECKREG r3, 0x30030006; +CHECKREG r4, 0x40040008; +CHECKREG r5, 0x5005000A; +CHECKREG r6, 0x6006000C; +CHECKREG r7, 0x7007000E; + + +imm32 r0, 0x10010700; +imm32 r1, 0x10010700; +R2.L = -15; +imm32 r3, 0x30030700; +imm32 r4, 0x40040000; +imm32 r5, 0x50050700; +imm32 r6, 0x60060000; +imm32 r7, 0x70070700; +R0.L = R0.H >>> 15; +R1.L = R1.H >>> 15; +R2.L = R2.H >>> 15; +R3.L = R3.H >>> 15; +R4.L = R4.H >>> 15; +R5.L = R5.H >>> 15; +R6.L = R6.H >>> 15; +R7.L = R7.H >>> 15; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x18010001; +imm32 r1, 0x18010001; +imm32 r2, 0x28020002; +R3.L = -16; +imm32 r4, 0x48040004; +imm32 r5, 0x58050005; +imm32 r6, 0x68060006; +imm32 r7, 0x78070007; +R0.L = R0.H >>> 13; +R1.L = R1.H >>> 13; +R2.L = R2.H >>> 13; +R3.L = R3.H >>> 13; +R4.L = R4.H >>> 13; +R5.L = R5.H >>> 13; +R6.L = R6.H >>> 13; +R7.L = R7.H >>> 13; +CHECKREG r0, 0x18010000; +CHECKREG r1, 0x18010000; +CHECKREG r2, 0x28020001; +CHECKREG r3, 0x30030001; +CHECKREG r4, 0x48040002; +CHECKREG r5, 0x58050002; +CHECKREG r6, 0x68060003; +CHECKREG r7, 0x78070003; + +// d_hi = ashft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x09000091; +imm32 r1, 0x09000091; +imm32 r2, 0x09000092; +imm32 r3, 0x09000093; +imm32 r4, 0x09000090; +imm32 r5, 0x09000095; +imm32 r6, 0x09000096; +imm32 r7, 0x09000097; +R0.H = R0.L >>> 14; +R1.H = R1.L >>> 14; +R2.H = R2.L >>> 14; +R3.H = R3.L >>> 14; +R4.H = R4.L >>> 14; +R5.H = R5.L >>> 14; +R6.H = R6.L >>> 14; +R7.H = R7.L >>> 14; +CHECKREG r0, 0x00000091; +CHECKREG r1, 0x00000091; +CHECKREG r2, 0x00000092; +CHECKREG r3, 0x00000093; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0x00000095; +CHECKREG r6, 0x00000096; +CHECKREG r7, 0x00000097; + +imm32 r0, 0xa0000001; +imm32 r1, 0xa0000001; +imm32 r2, 0xa0000002; +imm32 r3, 0xa0000003; +imm32 r4, 0xa0000004; +R5.L = -1; +imm32 r6, 0xa0000006; +imm32 r7, 0xa0000007; +R0.H = R0.L >>> 15; +R1.H = R1.L >>> 15; +R2.H = R2.L >>> 15; +R3.H = R3.L >>> 15; +R4.H = R4.L >>> 15; +R5.H = R5.L >>> 15; +R6.H = R6.L >>> 15; +R7.H = R7.L >>> 15; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0xFFFFFFFF; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + + +imm32 r0, 0xb0001001; +imm32 r1, 0xb0001001; +imm32 r1, 0xb0002002; +imm32 r3, 0xb0003003; +imm32 r4, 0xb0004004; +imm32 r5, 0xb0005005; +R6.L = -15; +imm32 r7, 0xb0007007; +R0.H = R0.L >>> 6; +R1.H = R1.L >>> 6; +R2.H = R2.L >>> 6; +R3.H = R3.L >>> 6; +R4.H = R4.L >>> 6; +R5.H = R5.L >>> 6; +R6.H = R6.L >>> 6; +R7.H = R7.L >>> 6; +CHECKREG r0, 0x00401001; +CHECKREG r1, 0x00802002; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00C03003; +CHECKREG r4, 0x01004004; +CHECKREG r5, 0x01405005; +CHECKREG r6, 0xFFFFFFF1; +CHECKREG r7, 0x01C07007; + +imm32 r0, 0x0c001c01; +imm32 r1, 0x0c002c01; +imm32 r2, 0x0c002c02; +imm32 r3, 0x0c003c03; +imm32 r4, 0x0c004c04; +imm32 r5, 0x0c005c05; +imm32 r6, 0x0c006c06; +R7.L = -16; +R0.H = R0.L >>> 7; +R1.H = R1.L >>> 7; +R2.H = R2.L >>> 7; +R3.H = R3.L >>> 7; +R4.H = R4.L >>> 7; +R5.H = R5.L >>> 7; +R6.H = R6.L >>> 7; +R7.H = R7.L >>> 7; +CHECKREG r0, 0x00381C01; +CHECKREG r1, 0x00582C01; +CHECKREG r2, 0x00582C02; +CHECKREG r3, 0x00783C03; +CHECKREG r4, 0x00984C04; +CHECKREG r5, 0x00B85C05; +CHECKREG r6, 0x00D86C06; +CHECKREG r7, 0xFFFFFFF0; + +// d_lo = ashft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x0d01d000; +imm32 r1, 0x0d01d000; +imm32 r2, 0x0d02d000; +imm32 r3, 0x0d03d000; +R4.L = -1; +imm32 r5, 0x0d05d000; +imm32 r6, 0x0d06d000; +imm32 r7, 0x0d07d000; +R0.H = R0.H >>> 4; +R1.H = R1.H >>> 4; +R2.H = R2.H >>> 4; +R3.H = R3.H >>> 4; +R4.H = R4.H >>> 4; +R5.H = R5.H >>> 4; +R6.H = R6.H >>> 4; +R7.H = R6.H >>> 4; +CHECKREG r0, 0x00D0D000; +CHECKREG r1, 0x00D0D000; +CHECKREG r2, 0x00D0D000; +CHECKREG r3, 0x00D0D000; +CHECKREG r4, 0x0009FFFF; +CHECKREG r5, 0x00D0D000; +CHECKREG r6, 0x00D0D000; +CHECKREG r7, 0x000DD000; + +imm32 r0, 0x1e010000; +imm32 r1, 0x1e010000; +imm32 r2, 0x2e020000; +imm32 r3, 0x3e030000; +imm32 r4, 0x4e040000; +R5.L = -1; +imm32 r6, 0x6e060000; +imm32 r7, 0x7e070000; +R7.H = R0.H >>> 15; +R6.H = R1.H >>> 15; +R0.H = R2.H >>> 15; +R1.H = R3.H >>> 15; +R2.H = R4.H >>> 15; +R3.H = R5.H >>> 15; +R4.H = R6.H >>> 15; +R5.H = R7.H >>> 15; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0x1f010000; +imm32 r1, 0x1f010000; +imm32 r2, 0x2f020000; +imm32 r3, 0x3f030000; +imm32 r4, 0x4f040000; +imm32 r5, 0x5f050000; +R6.L = -15; +imm32 r7, 0x70070000; +R6.H = R0.H >>> 6; +R7.H = R1.H >>> 6; +R5.H = R2.H >>> 6; +R0.H = R3.H >>> 6; +R1.H = R4.H >>> 6; +R2.H = R5.H >>> 6; +R3.H = R6.H >>> 6; +R4.H = R7.H >>> 6; +CHECKREG r0, 0x00FC0000; +CHECKREG r1, 0x013C0000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00010000; +CHECKREG r4, 0x00010000; +CHECKREG r5, 0x00BC0000; +CHECKREG r6, 0x007CFFF1; +CHECKREG r7, 0x007C0000; + +imm32 r0, 0x11010a00; +imm32 r1, 0x11010b00; +imm32 r2, 0x21020d00; +imm32 r2, 0x31030c00; +imm32 r4, 0x41040d00; +imm32 r5, 0x51050e00; +imm32 r6, 0x610600f0; +R7.L = -16; +R5.H = R0.H >>> 7; +R6.H = R1.H >>> 7; +R7.H = R2.H >>> 7; +R2.H = R3.H >>> 7; +R3.H = R4.H >>> 7; +R4.H = R5.H >>> 7; +R0.H = R6.H >>> 7; +R1.H = R7.H >>> 7; +CHECKREG r0, 0x00000A00; +CHECKREG r1, 0x00000B00; +CHECKREG r2, 0x00000C00; +CHECKREG r3, 0x00820000; +CHECKREG r4, 0x00000D00; +CHECKREG r5, 0x00220E00; +CHECKREG r6, 0x002200F0; +CHECKREG r7, 0x0062FFF0; +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh.s new file mode 100644 index 0000000..79d1924 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh.s @@ -0,0 +1,65 @@ +//Original:/testcases/core/c_dsp32shiftim_ahh/c_dsp32shiftim_ahh.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: ashift / ashift + + + +imm32 r0, 0x01230abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0 = R0 << 0 (V); +R1 = R1 << 3 (V); +R2 = R2 << 5 (V); +R3 = R3 << 8 (V); +R4 = R4 << 9 (V); +R5 = R5 << 15 (V); +R6 = R6 << 7 (V); +R7 = R7 << 13 (V); +CHECKREG r0, 0x01230ABC; +CHECKREG r1, 0x91A0B3C0; +CHECKREG r2, 0x68A0F120; +CHECKREG r3, 0x56009A00; +CHECKREG r4, 0xCE005600; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xC480E680; +CHECKREG r7, 0x4000C000; + +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7 = R0 >>> 1 (V); +R0 = R1 >>> 8 (V); +R1 = R2 >>> 14 (V); +R2 = R3 >>> 15 (V); +R3 = R4 >>> 11 (V); +R4 = R5 >>> 4 (V); +R5 = R6 >>> 9 (V); +R6 = R7 >>> 6 (V); +CHECKREG r0, 0x00120056; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x0008FFF1; +CHECKREG r4, 0x0567F9AB; +CHECKREG r5, 0x0033FFD5; +CHECKREG r6, 0x00020000; +CHECKREG r7, 0x00910000; + + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh_s.s new file mode 100644 index 0000000..9e69f2a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_ahh_s.s @@ -0,0 +1,65 @@ +//Original:/testcases/core/c_dsp32shiftim_ahh_s/c_dsp32shiftim_ahh_s.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: ashift / ashift saturated + + + +imm32 r0, 0x01230abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0 = R0 << 0 (V , S); +R1 = R1 << 3 (V , S); +R2 = R2 << 5 (V , S); +R3 = R3 << 8 (V , S); +R4 = R4 << 9 (V , S); +R5 = R5 << 15 (V , S); +R6 = R6 << 7 (V , S); +R7 = R7 << 13 (V , S); +CHECKREG r0, 0x01230ABC; +CHECKREG r1, 0x7FFF7FFF; +CHECKREG r2, 0x7FFF7FFF; +CHECKREG r3, 0x7FFF7FFF; +CHECKREG r4, 0x7FFF8000; +CHECKREG r5, 0x7FFF8000; +CHECKREG r6, 0x7FFF8000; +CHECKREG r7, 0x7FFF8000; + +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7 = R0 >>> 1 (V, S); +R0 = R1 >>> 8 (V, S); +R1 = R2 >>> 14 (V, S); +R2 = R3 >>> 15 (V, S); +R3 = R4 >>> 11 (V, S); +R4 = R5 >>> 4 (V, S); +R5 = R6 >>> 9 (V, S); +R6 = R7 >>> 6 (V, S); +CHECKREG r0, 0x00120056; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x0008FFF1; +CHECKREG r4, 0x0567F9AB; +CHECKREG r5, 0x0033FFD5; +CHECKREG r6, 0x00020000; +CHECKREG r7, 0x00910000; + + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s new file mode 100644 index 0000000..1bf9178 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s @@ -0,0 +1,142 @@ +//Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm ashift: mix + + + +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// Ashift : positive data, count (+)=left (half reg) +imm32 r0, 0x00010001; +imm32 r1, 1; +imm32 r2, 0x00020002; +imm32 r3, 2; +R4.H = R0.H << 1; +R4.L = R0.L << 1; /* r4 = 0x00020002 */ +R5.H = R2.H << 2; +R5.L = R2.L << 2; /* r5 = 0x00080008 */ +R6 = R0 << 1 (V); /* r6 = 0x00020002 */ +R7 = R2 << 2 (V); /* r7 = 0x00080008 */ +CHECKREG r4, 0x00020002; +CHECKREG r5, 0x00080008; +CHECKREG r6, 0x00020002; +CHECKREG r7, 0x00080008; + +imm32 r1, 3; +imm32 r3, 4; +R6 = R0 << 3; /* r6 = 0x00080010 */ +R7 = R2 << 4; +CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ +CHECKREG r7, 0x00200020; + +A0 = 0; +A0.L = R0.L; +A0.H = R0.H; +A0 = A0 << 3; /* a0 = 0x00080008 */ +R5 = A0.w; /* r5 = 0x00080008 */ +CHECKREG r5, 0x00080008; + +imm32 r4, 0x30000003; +imm32 r1, 1; +R5 = R4 << 1; /* r5 = 0x60000006 */ + +imm32 r1, 2; +R6 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */ +CHECKREG r5, 0x60000006; +CHECKREG r6, 0xc000000c; + + +// Ashift : count (-)=right (half reg) +imm32 r0, 0x10001000; +imm32 r1, -1; +imm32 r2, 0x10001000; +imm32 r3, -2; +R4.H = R0.H >>> 1; +R4.L = R0.L >>> 1; /* r4 = 0x08000800 */ +R5.H = R2.H >>> 2; +R5.L = R2.L >>> 2; /* r4 = 0x04000400 */ +R6 = R0 >>> 1 (V); /* r4 = 0x08000800 */ +R7 = R2 >>> 2 (V); /* r4 = 0x04000400 */ +CHECKREG r4, 0x08000800; +CHECKREG r5, 0x04000400; +CHECKREG r6, 0x08000800; +CHECKREG r7, 0x04000400; + +// Ashift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = R0 >>> 3; /* r6 = 0x02000200 */ +R7 = R2 >>> 4; /* r7 = 0x01000100 */ +CHECKREG r6, 0x02000200; +CHECKREG r7, 0x01000100; + +// NEGATIVE +// Ashift : NEGATIVE data, count (+)=left (half reg) +imm32 r0, 0xc00f800f; +imm32 r1, 1; +imm32 r2, 0xe00fe00f; +imm32 r3, 2; +R4.H = R0.H << 1; +R4.L = R0.L << 1 (S); /* r4 = 0x801e801e */ +R5.H = R2.H << 2; +R5.L = R2.L << 2; /* r4 = 0x803c803c */ +CHECKREG r4, 0x801e8000; +CHECKREG r5, 0x803c803c; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +imm32 r1, 4; +imm32 r3, 5; +R6 = R0 << 4; /* r6 = 0x80fe00f0 */ +R7 = R2 << 5; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xf80fe00f; +imm32 r2, 0xfc0fe00f; +R6 = R0 << 4 (S); /* r6 = 0x80fe00f0 */ +R7 = R2 << 5 (S); /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +R6 = R0 << 4 (S); /* r6 = 0x80000000 zero bubble tru MSB */ +R7 = R2 << 5 (S); /* r7 = 0x80000000 */ +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + + +// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok +imm32 r0, 0x80f080f0; +imm32 r1, -1; +imm32 r2, 0x80f080f0; +imm32 r3, -2; +R4.H = R0.H >>> 1; +R4.L = R0.L >>> 1; /* r4 = 0xc078c078 */ +R5.H = R2.H >>> 2; +R5.L = R2.L >>> 2; /* r4 = 0xe03ce03c */ +CHECKREG r4, 0xc078c078; +CHECKREG r5, 0xe03ce03c; +R6 = R0 >>> 1 (V); /* r6 = 0xc078c078 */ +R7 = R2 >>> 2 (V); /* r7 = 0xe03ce03c */ +CHECKREG r6, 0xc078c078; +CHECKREG r7, 0xe03ce03c; + +imm32 r1, -3; +imm32 r3, -4; +R6 = R0 >>> 3; /* r6 = 0xf01e101e */ +R7 = R2 >>> 4; /* r7 = 0xf80f080f */ +CHECKREG r6, 0xf01e101e; +CHECKREG r7, 0xf80f080f; + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lf.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lf.s new file mode 100644 index 0000000..3083173 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_lf.s @@ -0,0 +1,63 @@ +//Original:/testcases/core/c_dsp32shiftim_lf/c_dsp32shiftim_lf.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm lshift: lshift + + +imm32 r0, 0xa1230001; +imm32 r1, 0x1b345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x34d6789a; +imm32 r4, 0x85a789ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb8912cde; +R0 = R0 << 0; +R1 = R1 << 3; +R2 = R2 << 7; +R3 = R3 << 8; +R4 = R4 << 15; +R5 = R5 << 24; +R6 = R6 << 31; +R7 = R7 << 20; +CHECKREG r0, 0xA1230001; +CHECKREG r1, 0xD9A2B3C0; +CHECKREG r2, 0xE2B3C480; +CHECKREG r3, 0xD6789A00; +CHECKREG r4, 0xC4D58000; +CHECKREG r5, 0xBC000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0xCDE00000; + +imm32 r0, 0xa1230001; +imm32 r1, 0x1b345678; +imm32 r2, 0x23c56789; +imm32 r3, 0x34d6789a; +imm32 r4, 0x85a789ab; +imm32 r5, 0x967c9abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb8912cde; +R6 = R0 >> 1; +R7 = R1 >> 3; +R0 = R2 >> 7; +R1 = R3 >> 8; +R2 = R4 >> 15; +R3 = R5 >> 24; +R4 = R6 >> 31; +R5 = R7 >> 20; +CHECKREG r0, 0x00478ACF; +CHECKREG r1, 0x0034D678; +CHECKREG r2, 0x00010B4F; +CHECKREG r3, 0x00000096; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000036; +CHECKREG r6, 0x50918000; +CHECKREG r7, 0x03668ACF; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_ln.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_ln.s new file mode 100644 index 0000000..36004fd --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_ln.s @@ -0,0 +1,401 @@ +//Original:/testcases/core/c_dsp32shiftim_lhalf_ln/c_dsp32shiftim_lhalf_ln.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : neg data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x0000c001; +imm32 r2, 0x0000c002; +imm32 r3, 0x0000c003; +imm32 r4, 0x0000c004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000c006; +imm32 r7, 0x0000c007; +R0.L = R0.L << 1; +R1.L = R1.L << 0; +R2.L = R2.L << 0; +R3.L = R3.L << 0; +R4.L = R4.L << 0; +R5.L = R5.L << 0; +R6.L = R6.L << 0; +R7.L = R7.L << 0; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x0000C001; +CHECKREG r2, 0x0000C002; +CHECKREG r3, 0x0000C003; +CHECKREG r4, 0x0000C004; +CHECKREG r5, 0x0000C005; +CHECKREG r6, 0x0000C006; +CHECKREG r7, 0x0000C007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000c005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000e007; +R1.L = R0.L << 1; +R2.L = R1.L << 2; +R3.L = R2.L << 3; +R4.L = R3.L << 4; +R5.L = R4.L << 5; +R6.L = R5.L << 6; +R7.L = R6.L << 7; +R0.L = R7.L << 8; +imm32 r1, 0x2000d001; +imm32 r2, 0x2000000f; +imm32 r3, 0x2000e003; +imm32 r4, 0x2000f004; +imm32 r5, 0x2200f005; +imm32 r6, 0x2000f006; +imm32 r7, 0x2000f007; +imm32 r0, 0x2000c001; + +R2.L = R0.L << 10; +R3.L = R1.L << 12; +R4.L = R2.L << 13; +R5.L = R3.L << 14; +R6.L = R4.L << 15; +R7.L = R5.L << 15; +R0.L = R6.L << 2; +R1.L = R7.L << 3; +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x20000000; +CHECKREG r2, 0x20000400; +CHECKREG r3, 0x20001000; +CHECKREG r4, 0x20000000; +CHECKREG r5, 0x22000000; +CHECKREG r6, 0x20000000; +CHECKREG r7, 0x20000000; + +imm32 r0, 0x30009001; +imm32 r1, 0x3000a001; +imm32 r2, 0x3000b002; +imm32 r3, 0x30000010; +imm32 r4, 0x3000c004; +imm32 r5, 0x3000d005; +imm32 r6, 0x3000e006; +imm32 r7, 0x3000f007; +R3.L = R0.L << 12; +R4.L = R1.L << 13; +R5.L = R2.L << 14; +R6.L = R3.L << 15; +R7.L = R4.L << 11; +R0.L = R5.L << 12; +R1.L = R6.L << 13; +R2.L = R7.L << 15; +CHECKREG r0, 0x30000000; +CHECKREG r1, 0x30000000; +CHECKREG r2, 0x30000000; +CHECKREG r3, 0x30001000; +CHECKREG r4, 0x30002000; +CHECKREG r5, 0x30008000; +CHECKREG r6, 0x30000000; +CHECKREG r7, 0x30000000; +// RHx by RLx +imm32 r0, 0x00000040; +imm32 r1, 0x00010040; +imm32 r2, 0x00020040; +imm32 r3, 0x00030040; +imm32 r4, 0x00040040; +imm32 r5, 0x00050040; +imm32 r6, 0x00060040; +imm32 r7, 0x00070040; +R0.L = R0.H << 0; +R1.L = R1.H << 1; +R2.L = R2.H << 2; +R3.L = R3.H << 3; +R4.L = R4.H << 4; +R5.L = R5.H << 5; +R6.L = R6.H << 6; +R7.L = R7.H << 7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010002; +CHECKREG r2, 0x00020008; +CHECKREG r3, 0x00030018; +CHECKREG r4, 0x00040040; +CHECKREG r5, 0x000500A0; +CHECKREG r6, 0x00060180; +CHECKREG r7, 0x00070380; + +imm32 r0, 0x90010000; +imm32 r1, 0x00010001; +imm32 r2, 0x90020000; +imm32 r3, 0x90030000; +imm32 r4, 0x90040000; +imm32 r5, 0x90050000; +imm32 r6, 0x90060000; +imm32 r7, 0x90070000; +R1.L = R0.H << 1; +R2.L = R1.H << 2; +R3.L = R2.H << 3; +R4.L = R3.H << 4; +R5.L = R4.H << 5; +R6.L = R5.H << 6; +R7.L = R6.H << 7; +R0.L = R7.H << 8; +CHECKREG r1, 0x00012002; +CHECKREG r2, 0x90020004; +CHECKREG r3, 0x90038010; +CHECKREG r4, 0x90040030; +CHECKREG r5, 0x90050080; +CHECKREG r6, 0x90060140; +CHECKREG r7, 0x90070300; +CHECKREG r0, 0x90010700; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +imm32 r2, 0xa002000f; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R2.L = R0.H << 15; +R3.L = R1.H << 15; +R4.L = R2.H << 15; +R5.L = R3.H << 15; +R6.L = R4.H << 15; +R7.L = R5.H << 15; +R0.L = R6.H << 15; +R1.L = R7.H << 15; +CHECKREG r0, 0xA0010000; +CHECKREG r1, 0xA0018000; +CHECKREG r2, 0xA0028000; +CHECKREG r3, 0xA0038000; +CHECKREG r4, 0xA0040000; +CHECKREG r5, 0xA0058000; +CHECKREG r6, 0xA0060000; +CHECKREG r7, 0xA0078000; + +imm32 r0, 0xc0010001; +imm32 r1, 0xc0010001; +imm32 r2, 0xc0020002; +imm32 r3, 0xc0030010; +imm32 r4, 0xc0040004; +imm32 r5, 0xc0050005; +imm32 r6, 0xc0060006; +imm32 r7, 0xc0070007; +R3.L = R0.H << 14; +R4.L = R1.H << 14; +R5.L = R2.H << 14; +R6.L = R3.H << 14; +R7.L = R4.H << 14; +R0.L = R5.H << 14; +R1.L = R6.H << 14; +R2.L = R7.H << 14; +CHECKREG r0, 0xC0014000; +CHECKREG r1, 0xC0018000; +CHECKREG r2, 0xC002C000; +CHECKREG r3, 0xC0034000; +CHECKREG r4, 0xC0044000; +CHECKREG r5, 0xC0058000; +CHECKREG r6, 0xC006C000; +CHECKREG r7, 0xC0070000; + +// RLx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = R0.L << 12; +R1.H = R1.L << 12; +R2.H = R2.L << 13; +R3.H = R3.L << 14; +R4.H = R4.L << 15; +R5.H = R5.L << 14; +R6.H = R6.L << 7; +R7.H = R7.L << 8; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x10000001; +CHECKREG r2, 0x40000002; +CHECKREG r3, 0xC0000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x40000005; +CHECKREG r6, 0x03000006; +CHECKREG r7, 0x07000007; + +imm32 r0, 0x0000d001; +imm32 r1, 0x00000001; +imm32 r2, 0x0000d002; +imm32 r3, 0x0000d003; +imm32 r4, 0x0000d004; +imm32 r5, 0x0000d005; +imm32 r6, 0x0000d006; +imm32 r7, 0x0000d007; +R1.H = R0.L << 3; +R2.H = R1.L << 4; +R3.H = R2.L << 5; +R4.H = R3.L << 6; +R5.H = R4.L << 7; +R6.H = R5.L << 8; +R7.H = R6.L << 9; +R0.H = R7.L << 8; +CHECKREG r1, 0x80080001; +CHECKREG r2, 0x0010D002; +CHECKREG r3, 0x0040D003; +CHECKREG r4, 0x00C0D004; +CHECKREG r5, 0x0200D005; +CHECKREG r6, 0x0500D006; +CHECKREG r7, 0x0C00D007; +CHECKREG r0, 0x0700D001; + + +imm32 r0, 0x0000e001; +imm32 r1, 0x0000e001; +imm32 r2, 0x0000000f; +imm32 r3, 0x0000e003; +imm32 r4, 0x0000e004; +imm32 r5, 0x0000e005; +imm32 r6, 0x0000e006; +imm32 r7, 0x0000e007; +R2.H = R0.L << 15; +R3.H = R1.L << 15; +R4.H = R2.L << 15; +R5.H = R3.L << 15; +R6.H = R4.L << 15; +R7.H = R5.L << 15; +R0.H = R6.L << 15; +R1.H = R7.L << 15; +CHECKREG r0, 0x0000E001; +CHECKREG r1, 0x8000E001; +CHECKREG r2, 0x8000000F; +CHECKREG r3, 0x8000E003; +CHECKREG r4, 0x8000E004; +CHECKREG r5, 0x8000E005; +CHECKREG r6, 0x0000E006; +CHECKREG r7, 0x8000E007; + +imm32 r0, 0x0000f001; +imm32 r1, 0x0000f001; +imm32 r2, 0x0000f002; +imm32 r3, 0x00000010; +imm32 r4, 0x0000f004; +imm32 r5, 0x0000f005; +imm32 r6, 0x0000f006; +imm32 r7, 0x0000f007; +R3.H = R0.L << 13; +R4.H = R1.L << 13; +R5.H = R2.L << 13; +R6.H = R3.L << 13; +R7.H = R4.L << 13; +R0.H = R5.L << 13; +R1.H = R6.L << 13; +R2.H = R7.L << 13; +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x00010000; +imm32 r2, 0x00020000; +imm32 r3, 0x00030000; +imm32 r4, 0x00040000; +imm32 r5, 0x00050000; +imm32 r6, 0x00060000; +imm32 r7, 0x00070000; +R0.H = R0.H << 0; +R1.H = R1.H << 0; +R2.H = R2.H << 0; +R3.H = R3.H << 0; +R4.H = R4.H << 0; +R5.H = R5.H << 0; +R6.H = R6.H << 0; +R7.H = R7.H << 0; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00020000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x00040000; +CHECKREG r5, 0x00050000; +CHECKREG r6, 0x00060000; +CHECKREG r7, 0x00070000; + +imm32 r0, 0xa0010000; +imm32 r1, 0x00010001; +imm32 r2, 0xa0020000; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R1.H = R0.H << 1; +R2.H = R1.H << 1; +R3.H = R2.H << 1; +R4.H = R3.H << 1; +R5.H = R4.H << 1; +R6.H = R5.H << 1; +R7.H = R6.H << 1; +R0.H = R7.H << 1; +CHECKREG r1, 0x40020001; +CHECKREG r2, 0x80040000; +CHECKREG r3, 0x00080000; +CHECKREG r4, 0x00100000; +CHECKREG r5, 0x00200000; +CHECKREG r6, 0x00400000; +CHECKREG r7, 0x00800000; +CHECKREG r0, 0x01000000; + + +imm32 r0, 0xb0010000; +imm32 r1, 0xb0010000; +imm32 r2, 0xb002000f; +imm32 r3, 0xb0030000; +imm32 r4, 0xb0040000; +imm32 r5, 0xb0050000; +imm32 r6, 0xb0060000; +imm32 r7, 0xb0070000; +R2.H = R0.H << 15; +R3.H = R1.H << 15; +R4.H = R2.H << 15; +R5.H = R3.H << 15; +R6.H = R4.H << 15; +R7.H = R5.H << 15; +R0.H = R6.H << 15; +R1.H = R7.H << 15; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x8000000F; +CHECKREG r3, 0x80000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030010; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +imm32 r6, 0xd0060000; +imm32 r7, 0xd0070000; +R6.H = R0.H << 12; +R7.H = R1.H << 12; +R0.H = R2.H << 12; +R1.H = R3.H << 12; +R2.H = R4.H << 12; +R3.H = R5.H << 12; +R4.H = R6.H << 12; +R5.H = R7.H << 12; +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x30000000; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0x50000010; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x10000000; +CHECKREG r7, 0x10000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_lp.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_lp.s new file mode 100644 index 0000000..53e53f2 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_lp.s @@ -0,0 +1,418 @@ +//Original:/testcases/core/c_dsp32shiftim_lhalf_lp/c_dsp32shiftim_lhalf_lp.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY imm5) +// RLx by imm5 +imm32 r0, 0x00100a00; +imm32 r1, 0x00100a01; +imm32 r2, 0x00100a02; +imm32 r3, 0x00100a03; +imm32 r4, 0x00100a04; +imm32 r5, 0x00100a05; +imm32 r6, 0x00100a06; +imm32 r7, 0x00100a07; +R7.L = R0.L << 0; +R0.L = R1.L << 1; +R1.L = R2.L << 2; +R2.L = R3.L << 3; +R3.L = R4.L << 4; +R4.L = R5.L << 5; +R5.L = R6.L << 6; +R6.L = R7.L << 7; +CHECKREG r1, 0x00102808; +CHECKREG r0, 0x00101402; +CHECKREG r2, 0x00105018; +CHECKREG r3, 0x0010A040; +CHECKREG r4, 0x001040A0; +CHECKREG r5, 0x00108180; +CHECKREG r6, 0x00100000; +CHECKREG r7, 0x00100A00; + +imm32 r0, 0x00200018; +imm32 r1, 0x00200019; +imm32 r2, 0x0020001a; +imm32 r3, 0x0020001b; +imm32 r4, 0x0020001c; +imm32 r5, 0x0020001d; +imm32 r6, 0x0020001e; +imm32 r7, 0x0020001f; +R2.L = R0.L << 8; +R3.L = R1.L << 9; +R4.L = R2.L << 10; +R5.L = R3.L << 11; +R6.L = R4.L << 12; +R7.L = R5.L << 13; +R0.L = R6.L << 14; +R1.L = R7.L << 15; +CHECKREG r0, 0x00200000; +CHECKREG r1, 0x00200000; +CHECKREG r2, 0x00201800; +CHECKREG r3, 0x00203200; +CHECKREG r4, 0x00200000; +CHECKREG r5, 0x00200000; +CHECKREG r6, 0x00200000; +CHECKREG r7, 0x00200000; + +imm32 r0, 0x05002001; +imm32 r1, 0x05002001; +imm32 r2, 0x0500000f; +imm32 r3, 0x05002003; +imm32 r4, 0x05002004; +imm32 r5, 0x05002005; +imm32 r6, 0x05002006; +imm32 r7, 0x05002007; +R3.L = R0.L << 0; +R4.L = R1.L << 1; +R5.L = R2.L << 2; +R6.L = R3.L << 3; +R7.L = R4.L << 4; +R0.L = R5.L << 5; +R1.L = R6.L << 6; +R2.L = R7.L << 7; +CHECKREG r0, 0x05000780; +CHECKREG r1, 0x05000200; +CHECKREG r2, 0x05001000; +CHECKREG r3, 0x05002001; +CHECKREG r4, 0x05004002; +CHECKREG r5, 0x0500003C; +CHECKREG r6, 0x05000008; +CHECKREG r7, 0x05000020; + +imm32 r0, 0x03000031; +imm32 r1, 0x03000031; +imm32 r2, 0x03000032; +imm32 r3, 0x03000030; +imm32 r4, 0x03000034; +imm32 r5, 0x03000035; +imm32 r6, 0x03000036; +imm32 r7, 0x03000037; +R4.L = R0.L << 8; +R5.L = R1.L << 9; +R6.L = R2.L << 10; +R7.L = R3.L << 11; +R0.L = R4.L << 12; +R1.L = R5.L << 13; +R2.L = R6.L << 14; +R3.L = R7.L << 15; +CHECKREG r0, 0x03000000; +CHECKREG r1, 0x03000000; +CHECKREG r2, 0x03000000; +CHECKREG r3, 0x03000000; +CHECKREG r4, 0x03003100; +CHECKREG r5, 0x03006200; +CHECKREG r6, 0x0300C800; +CHECKREG r7, 0x03008000; +// RHx by RLx +imm32 r0, 0x03000000; +imm32 r1, 0x03000000; +imm32 r2, 0x03000000; +imm32 r3, 0x03000000; +imm32 r4, 0x03003100; +imm32 r5, 0x03006200; +imm32 r6, 0x0300C800; +imm32 r7, 0x03008000; +R5.L = R0.H << 0; +R6.L = R1.H << 1; +R7.L = R2.H << 2; +R0.L = R3.H << 3; +R1.L = R4.H << 4; +R2.L = R5.H << 5; +R3.L = R6.H << 6; +R4.L = R7.H << 7; +CHECKREG r0, 0x03001800; +CHECKREG r1, 0x03003000; +CHECKREG r2, 0x03006000; +CHECKREG r3, 0x0300C000; +CHECKREG r4, 0x03008000; +CHECKREG r5, 0x03000300; +CHECKREG r6, 0x03000600; +CHECKREG r7, 0x03000C00; + +imm32 r0, 0x05018000; +imm32 r1, 0x05018001; +imm32 r2, 0x05028000; +imm32 r3, 0x05038000; +imm32 r4, 0x05048000; +imm32 r5, 0x05058000; +imm32 r6, 0x05068000; +imm32 r7, 0x05078000; +R6.L = R0.H << 8; +R7.L = R1.H << 9; +R0.L = R2.H << 10; +R1.L = R3.H << 11; +R2.L = R4.H << 12; +R3.L = R5.H << 13; +R4.L = R6.H << 14; +R5.L = R7.H << 15; +CHECKREG r0, 0x05010800; +CHECKREG r1, 0x05011800; +CHECKREG r2, 0x05024000; +CHECKREG r3, 0x0503A000; +CHECKREG r4, 0x05048000; +CHECKREG r5, 0x05058000; +CHECKREG r6, 0x05060100; +CHECKREG r7, 0x05070200; + + +imm32 r0, 0x60019000; +imm32 r1, 0x60019000; +imm32 r2, 0x6002900f; +imm32 r3, 0x60039000; +imm32 r4, 0x60049000; +imm32 r5, 0x60059000; +imm32 r6, 0x60069000; +imm32 r7, 0x60079000; +R7.L = R0.H << 0; +R0.L = R1.H << 1; +R1.L = R2.H << 2; +R2.L = R3.H << 3; +R3.L = R4.H << 4; +R4.L = R5.H << 5; +R5.L = R6.H << 6; +R6.L = R7.H << 7; +CHECKREG r0, 0x6001C002; +CHECKREG r1, 0x60018008; +CHECKREG r2, 0x60020018; +CHECKREG r3, 0x60030040; +CHECKREG r4, 0x600400A0; +CHECKREG r5, 0x60050180; +CHECKREG r6, 0x60060380; +CHECKREG r7, 0x60076001; + +imm32 r0, 0x70010001; +imm32 r1, 0x70010001; +imm32 r2, 0x70020002; +imm32 r3, 0x77030010; +imm32 r4, 0x70040004; +imm32 r5, 0x70050005; +imm32 r6, 0x70060006; +imm32 r7, 0x70070007; +R0.L = R0.H << 8; +R1.L = R1.H << 9; +R2.L = R2.H << 10; +R3.L = R3.H << 11; +R4.L = R4.H << 12; +R5.L = R5.H << 13; +R6.L = R6.H << 14; +R7.L = R7.H << 15; +CHECKREG r0, 0x70010100; +CHECKREG r1, 0x70010200; +CHECKREG r2, 0x70020800; +CHECKREG r3, 0x77031800; +CHECKREG r4, 0x70044000; +CHECKREG r5, 0x7005A000; +CHECKREG r6, 0x70068000; +CHECKREG r7, 0x70078000; + +// d_hi = lshft (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0xa8000000; +imm32 r1, 0xa8000001; +imm32 r2, 0xa8000002; +imm32 r3, 0xa8000003; +imm32 r4, 0xa8000004; +imm32 r5, 0xa8000005; +imm32 r6, 0xa8000006; +imm32 r7, 0xa8000007; +R0.H = R0.L << 0; +R1.H = R1.L << 1; +R2.H = R2.L << 2; +R3.H = R3.L << 3; +R4.H = R4.L << 4; +R5.H = R5.L << 5; +R6.H = R6.L << 6; +R7.H = R7.L << 7; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00080002; +CHECKREG r3, 0x00180003; +CHECKREG r4, 0x00400004; +CHECKREG r5, 0x00A00005; +CHECKREG r6, 0x01800006; +CHECKREG r7, 0x03800007; + +imm32 r0, 0xf0090001; +imm32 r1, 0xf0090001; +imm32 r2, 0xf0090002; +imm32 r3, 0xf0090003; +imm32 r4, 0xf0090004; +imm32 r5, 0xf0090005; +imm32 r6, 0xf0000006; +imm32 r7, 0xf0000007; +R1.H = R0.L << 8; +R2.H = R1.L << 9; +R3.H = R2.L << 10; +R4.H = R3.L << 11; +R5.H = R4.L << 12; +R6.H = R5.L << 13; +R7.H = R6.L << 14; +R0.H = R7.L << 15; +CHECKREG r1, 0x01000001; +CHECKREG r2, 0x02000002; +CHECKREG r3, 0x08000003; +CHECKREG r4, 0x18000004; +CHECKREG r5, 0x40000005; +CHECKREG r6, 0xA0000006; +CHECKREG r7, 0x80000007; +CHECKREG r0, 0x80000001; + + +imm32 r0, 0x07000001; +imm32 r1, 0x07000001; +imm32 r2, 0x0700000f; +imm32 r3, 0x07000003; +imm32 r4, 0x07000004; +imm32 r5, 0x07000005; +imm32 r6, 0x07000006; +imm32 r7, 0x07000007; +R3.H = R0.L << 0; +R4.H = R1.L << 1; +R5.H = R2.L << 2; +R6.H = R3.L << 3; +R7.H = R4.L << 4; +R0.H = R5.L << 5; +R1.H = R6.L << 6; +R2.H = R7.L << 7; +CHECKREG r0, 0x00A00001; +CHECKREG r1, 0x01800001; +CHECKREG r2, 0x0380000F; +CHECKREG r3, 0x00010003; +CHECKREG r4, 0x00020004; +CHECKREG r5, 0x003C0005; +CHECKREG r6, 0x00180006; +CHECKREG r7, 0x00400007; + +imm32 r0, 0x00000501; +imm32 r1, 0x00000501; +imm32 r2, 0x00000502; +imm32 r3, 0x00000510; +imm32 r4, 0x00000504; +imm32 r5, 0x00000505; +imm32 r6, 0x00000506; +imm32 r7, 0x00000507; +R4.H = R0.L << 8; +R5.H = R1.L << 9; +R6.H = R2.L << 10; +R7.H = R3.L << 11; +R0.H = R4.L << 12; +R1.H = R5.L << 13; +R2.H = R6.L << 14; +R3.H = R7.L << 15; +CHECKREG r0, 0x40000501; +CHECKREG r1, 0xA0000501; +CHECKREG r2, 0x80000502; +CHECKREG r3, 0x80000510; +CHECKREG r4, 0x01000504; +CHECKREG r5, 0x02000505; +CHECKREG r6, 0x08000506; +CHECKREG r7, 0x80000507; + +imm32 r0, 0x00a00800; +imm32 r1, 0x00a10800; +imm32 r2, 0x00a20800; +imm32 r3, 0x00a30800; +imm32 r4, 0x00a40800; +imm32 r5, 0x00a50800; +imm32 r6, 0x00a60800; +imm32 r7, 0x00a70800; +R5.H = R0.H << 0; +R6.H = R1.H << 1; +R7.H = R2.H << 2; +R0.H = R3.H << 3; +R1.H = R4.H << 4; +R2.H = R5.H << 5; +R3.H = R6.H << 6; +R4.H = R7.H << 7; +CHECKREG r0, 0x05180800; +CHECKREG r1, 0x0A400800; +CHECKREG r2, 0x14000800; +CHECKREG r3, 0x50800800; +CHECKREG r4, 0x44000800; +CHECKREG r5, 0x00A00800; +CHECKREG r6, 0x01420800; +CHECKREG r7, 0x02880800; + +imm32 r0, 0x0c010000; +imm32 r1, 0x0c010001; +imm32 r2, 0x0c020000; +imm32 r3, 0x0c030000; +imm32 r4, 0x0c040000; +imm32 r5, 0x0c050000; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c070000; +R6.H = R0.H << 8; +R7.H = R1.H << 9; +R0.H = R2.H << 10; +R1.H = R3.H << 11; +R2.H = R4.H << 12; +R3.H = R5.H << 13; +R4.H = R6.H << 14; +R5.H = R7.H << 15; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x18000001; +CHECKREG r2, 0x40000000; +CHECKREG r3, 0xA0000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x01000000; +CHECKREG r7, 0x02000000; + + +imm32 r0, 0x00b10000; +imm32 r1, 0x00b10000; +imm32 r2, 0x00b2000f; +imm32 r3, 0x00b30000; +imm32 r4, 0x00b40000; +imm32 r5, 0x00b50000; +imm32 r6, 0x00b60000; +imm32 r7, 0x00b70000; +R7.L = R0.H << 0; +R0.L = R1.H << 1; +R1.L = R2.H << 2; +R2.L = R3.H << 3; +R3.L = R4.H << 4; +R4.L = R5.H << 5; +R5.L = R6.H << 6; +R6.L = R7.H << 7; +CHECKREG r0, 0x00B10162; +CHECKREG r1, 0x00B102C8; +CHECKREG r2, 0x00B20598; +CHECKREG r3, 0x00B30B40; +CHECKREG r4, 0x00B416A0; +CHECKREG r5, 0x00B52D80; +CHECKREG r6, 0x00B65B80; +CHECKREG r7, 0x00B700B1; + +imm32 r0, 0x0a010700; +imm32 r1, 0x0a010700; +imm32 r2, 0x0a020700; +imm32 r3, 0x0a030710; +imm32 r4, 0x0a040700; +imm32 r5, 0x0a050700; +imm32 r6, 0x0a060700; +imm32 r7, 0x0a070700; +R0.H = R0.H << 8; +R1.H = R1.H << 9; +R2.H = R2.H << 10; +R3.H = R3.H << 11; +R4.H = R4.H << 12; +R5.H = R5.H << 13; +R6.H = R6.H << 14; +R7.H = R7.H << 15; +CHECKREG r0, 0x01000700; +CHECKREG r1, 0x02000700; +CHECKREG r2, 0x08000700; +CHECKREG r3, 0x18000710; +CHECKREG r4, 0x40000700; +CHECKREG r5, 0xA0000700; +CHECKREG r6, 0x80000700; +CHECKREG r7, 0x80000700; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rn.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rn.s new file mode 100644 index 0000000..a14a4c3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rn.s @@ -0,0 +1,424 @@ +//Original:/testcases/core/c_dsp32shiftim_lhalf_rn/c_dsp32shiftim_lhalf_rn.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : neg data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = R0.L >> 1; +R1.L = R1.L >> 2; +R2.L = R2.L >> 3; +R3.L = R3.L >> 4; +R4.L = R4.L >> 5; +R5.L = R5.L >> 6; +R6.L = R6.L >> 7; +R7.L = R7.L >> 8; +CHECKREG r0, 0x00007FFF; +CHECKREG r1, 0x00002000; +CHECKREG r2, 0x00001000; +CHECKREG r3, 0x00000800; +CHECKREG r4, 0x00000400; +CHECKREG r5, 0x00000200; +CHECKREG r6, 0x00000100; +CHECKREG r7, 0x00000080; + +imm32 r0, 0x00008001; +R1.L = -1; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R0.L = R0.L >> 9; +R1.L = R1.L >> 10; +R2.L = R2.L >> 11; +R3.L = R3.L >> 12; +R4.L = R4.L >> 13; +R5.L = R5.L >> 14; +R6.L = R6.L >> 15; +R7.L = R7.L >> 10; +CHECKREG r0, 0x00000040; +CHECKREG r1, 0x0000003F; +CHECKREG r2, 0x00000010; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000020; + + +imm32 r0, 0x30008001; +imm32 r1, 0x30008001; +R2.L = -15; +imm32 r3, 0x30008003; +imm32 r4, 0x30008004; +imm32 r5, 0x30008005; +imm32 r6, 0x30008006; +imm32 r7, 0x30008007; +R7.L = R0.L >> 1; +R6.L = R1.L >> 2; +R5.L = R2.L >> 3; +R4.L = R3.L >> 4; +R3.L = R4.L >> 5; +R2.L = R5.L >> 6; +R0.L = R7.L >> 8; +R1.L = R6.L >> 7; +CHECKREG r0, 0x30000040; +CHECKREG r1, 0x30000040; +CHECKREG r2, 0x0000007F; +CHECKREG r3, 0x30000040; +CHECKREG r4, 0x30000800; +CHECKREG r5, 0x30001FFE; +CHECKREG r6, 0x30002000; +CHECKREG r7, 0x30004000; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +R3.L = -16; +imm32 r4, 0x00008004; +imm32 r5, 0x00008005; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R6.L = R0.L >> 13; +R5.L = R1.L >> 13; +R4.L = R2.L >> 13; +R3.L = R3.L >> 13; +R2.L = R4.L >> 13; +R1.L = R5.L >> 13; +R0.L = R6.L >> 13; +R7.L = R7.L >> 13; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x30000007; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000004; +CHECKREG r6, 0x00000004; +CHECKREG r7, 0x00000004; + +// d_lo = lshift (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x00000000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.L = R0.H >> 1; +R1.L = R1.H >> 1; +R2.L = R2.H >> 1; +R3.L = R3.H >> 1; +R4.L = R4.H >> 1; +R5.L = R5.H >> 1; +R6.L = R6.H >> 1; +R7.L = R7.H >> 1; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x80014000; +CHECKREG r2, 0x80024001; +CHECKREG r3, 0x80034001; +CHECKREG r4, 0x80044002; +CHECKREG r5, 0x80054002; +CHECKREG r6, 0x80064003; +CHECKREG r7, 0x80074003; + +imm32 r0, 0x80010000; +R1.L = -1; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R1.L = R0.H >> 10; +R2.L = R1.H >> 11; +R3.L = R2.H >> 12; +R4.L = R3.H >> 13; +R5.L = R4.H >> 14; +R6.L = R5.H >> 15; +R0.L = R7.H >> 15; +R7.L = R6.H >> 15; +CHECKREG r0, 0x80010001; +CHECKREG r1, 0x80010020; +CHECKREG r2, 0x80020010; +CHECKREG r3, 0x80030008; +CHECKREG r4, 0x80040004; +CHECKREG r5, 0x80050002; +CHECKREG r6, 0x80060001; +CHECKREG r7, 0x80070001; + + +imm32 r0, 0xa0010000; +imm32 r1, 0xa0010000; +R2.L = -15; +imm32 r3, 0xa0030000; +imm32 r4, 0xa0040000; +imm32 r5, 0xa0050000; +imm32 r6, 0xa0060000; +imm32 r7, 0xa0070000; +R2.L = R0.H >> 2; +R3.L = R1.H >> 2; +R4.L = R2.H >> 2; +R5.L = R3.H >> 2; +R6.L = R4.H >> 2; +R7.L = R5.H >> 2; +R0.L = R6.H >> 2; +R1.L = R7.H >> 2; +CHECKREG r0, 0xA0012801; +CHECKREG r1, 0xA0012801; +CHECKREG r2, 0x80022800; +CHECKREG r3, 0xA0032800; +CHECKREG r4, 0xA0042000; +CHECKREG r5, 0xA0052800; +CHECKREG r6, 0xA0062801; +CHECKREG r7, 0xA0072801; + +imm32 r0, 0xb0010001; +imm32 r1, 0xb0010001; +imm32 r2, 0xb0020002; +R3.L = -16; +imm32 r4, 0xb0040004; +imm32 r5, 0xb0050005; +imm32 r6, 0xb0060006; +imm32 r7, 0xb0070007; +R3.L = R0.H >> 13; +R4.L = R1.H >> 13; +R5.L = R2.H >> 13; +R6.L = R3.H >> 13; +R7.L = R4.H >> 13; +R0.L = R5.H >> 13; +R1.L = R6.H >> 13; +R2.L = R7.H >> 13; +CHECKREG r0, 0xB0010005; +CHECKREG r1, 0xB0010005; +CHECKREG r2, 0xB0020005; +CHECKREG r3, 0xA0030005; +CHECKREG r4, 0xB0040005; +CHECKREG r5, 0xB0050005; +CHECKREG r6, 0xB0060005; +CHECKREG r7, 0xB0070005; + +// d_hi = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000001; +imm32 r1, 0x00000001; +imm32 r2, 0x00000002; +imm32 r3, 0x00000003; +imm32 r4, 0x00000004; +imm32 r5, 0x00000005; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = R0.L >> 14; +R1.H = R1.L >> 14; +R2.H = R2.L >> 14; +R3.H = R3.L >> 14; +R4.H = R4.L >> 14; +R5.H = R5.L >> 14; +R6.H = R6.L >> 14; +R7.H = R7.L >> 14; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000002; +CHECKREG r3, 0x00000003; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000005; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + +imm32 r0, 0x00008001; +imm32 r1, 0x00008001; +imm32 r2, 0x00008002; +imm32 r3, 0x00008003; +imm32 r4, 0x00008004; +R5.L = -1; +imm32 r6, 0x00008006; +imm32 r7, 0x00008007; +R1.H = R0.L >> 5; +R0.H = R7.L >> 5; +R2.H = R1.L >> 5; +R3.H = R2.L >> 5; +R4.H = R3.L >> 5; +R5.H = R4.L >> 5; +R6.H = R5.L >> 5; +R7.H = R6.L >> 5; +CHECKREG r0, 0x04008001; +CHECKREG r1, 0x04008001; +CHECKREG r2, 0x04008002; +CHECKREG r3, 0x04008003; +CHECKREG r4, 0x04008004; +CHECKREG r5, 0x0400FFFF; +CHECKREG r6, 0x07FF8006; +CHECKREG r7, 0x04008007; + + +imm32 r0, 0x00009001; +imm32 r1, 0x00009001; +imm32 r2, 0x00009002; +imm32 r3, 0x00009003; +imm32 r4, 0x00009004; +imm32 r5, 0x00009005; +R6.L = -15; +imm32 r7, 0x00009007; +R3.H = R0.L >> 14; +R4.H = R1.L >> 14; +R5.H = R2.L >> 14; +R6.H = R3.L >> 14; +R7.H = R4.L >> 14; +R0.H = R5.L >> 14; +R1.H = R6.L >> 14; +R2.H = R7.L >> 14; +CHECKREG r0, 0x00029001; +CHECKREG r1, 0x00039001; +CHECKREG r2, 0x00029002; +CHECKREG r3, 0x00029003; +CHECKREG r4, 0x00029004; +CHECKREG r5, 0x00029005; +CHECKREG r6, 0x0002FFF1; +CHECKREG r7, 0x00029007; + +imm32 r0, 0x0000a001; +imm32 r1, 0x0000a001; +imm32 r2, 0x0000a002; +imm32 r3, 0x0000a003; +imm32 r4, 0x0000a004; +imm32 r5, 0x0000a005; +imm32 r6, 0x0000a006; +R7.L = -16; +R4.H = R0.L >> 15; +R5.H = R1.L >> 15; +R6.H = R2.L >> 15; +R7.H = R3.L >> 15; +R0.H = R4.L >> 15; +R1.H = R5.L >> 15; +R2.H = R6.L >> 15; +R3.H = R7.L >> 15; +CHECKREG r0, 0x0001A001; +CHECKREG r1, 0x0001A001; +CHECKREG r2, 0x0001A002; +CHECKREG r3, 0x0001A003; +CHECKREG r4, 0x0001A004; +CHECKREG r5, 0x0001A005; +CHECKREG r6, 0x0001A006; +CHECKREG r7, 0x0001FFF0; + +// d_lo = lshft (d_hi BY d_lo) +// RHx by RLx +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +R4.L = -1; +imm32 r5, 0x80050000; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R0.H = R0.H >> 4; +R1.H = R1.H >> 4; +R2.H = R2.H >> 4; +R3.H = R3.H >> 4; +R4.H = R4.H >> 4; +R5.H = R5.H >> 4; +R6.H = R6.H >> 4; +R7.H = R7.H >> 4; +CHECKREG r0, 0x08000000; +CHECKREG r1, 0x08000000; +CHECKREG r2, 0x08000000; +CHECKREG r3, 0x08000000; +CHECKREG r4, 0x0000FFFF; +CHECKREG r5, 0x08000000; +CHECKREG r6, 0x08000000; +CHECKREG r7, 0x08000000; + +imm32 r0, 0x80010000; +imm32 r1, 0x80010000; +imm32 r2, 0x80020000; +imm32 r3, 0x80030000; +imm32 r4, 0x80040000; +R5.L = -1; +imm32 r6, 0x80060000; +imm32 r7, 0x80070000; +R1.H = R0.H >> 15; +R2.H = R1.H >> 15; +R3.H = R2.H >> 15; +R4.H = R3.H >> 15; +R5.H = R4.H >> 15; +R6.H = R5.H >> 15; +R0.H = R7.H >> 15; +R7.H = R6.H >> 15; +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x0000FFFF; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +imm32 r0, 0xd0010000; +imm32 r1, 0xd0010000; +imm32 r2, 0xd0020000; +imm32 r3, 0xd0030000; +imm32 r4, 0xd0040000; +imm32 r5, 0xd0050000; +R6.L = -15; +imm32 r7, 0xd0070000; +R3.H = R0.H >> 6; +R4.H = R1.H >> 6; +R5.H = R2.H >> 6; +R6.H = R3.H >> 6; +R7.H = R4.H >> 6; +R0.H = R5.H >> 6; +R1.H = R6.H >> 6; +R2.H = R7.H >> 6; +CHECKREG r0, 0x000D0000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x03400000; +CHECKREG r4, 0x03400000; +CHECKREG r5, 0x03400000; +CHECKREG r6, 0x000DFFF1; +CHECKREG r7, 0x000D0000; + +imm32 r0, 0xe0010000; +imm32 r1, 0xe0010000; +imm32 r2, 0xe0020000; +imm32 r3, 0xe0030000; +imm32 r4, 0xe0040000; +imm32 r5, 0xe0050000; +imm32 r6, 0xe0060000; +R7.L = -16; +R4.H = R0.H >> 7; +R5.H = R1.H >> 7; +R6.H = R2.H >> 7; +R7.H = R3.H >> 7; +R0.H = R4.H >> 7; +R1.H = R5.H >> 7; +R2.H = R6.H >> 7; +R3.H = R7.H >> 7; +CHECKREG r0, 0x00030000; +CHECKREG r1, 0x00030000; +CHECKREG r2, 0x00030000; +CHECKREG r3, 0x00030000; +CHECKREG r4, 0x01C00000; +CHECKREG r5, 0x01C00000; +CHECKREG r6, 0x01C00000; +CHECKREG r7, 0x01C0FFF0; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rp.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rp.s new file mode 100644 index 0000000..a26a3eb --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhalf_rp.s @@ -0,0 +1,421 @@ +//Original:/testcases/core/c_dsp32shiftim_lhalf_rp/c_dsp32shiftim_lhalf_rp.dsp +// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5) +# mach: bfin + +.include "testutils.inc" + start + + + +// lshift : positive data, count (+)=left (half reg) +// d_lo = lshift (d_lo BY d_lo) +// RLx by RLx +imm32 r0, 0x00000000; +R0.L = -1; +imm32 r1, 0x90000001; +imm32 r2, 0x90000002; +imm32 r3, 0x90000003; +imm32 r4, 0x90000004; +imm32 r5, 0x90000005; +imm32 r6, 0x90000006; +imm32 r7, 0x90000007; +R0.L = R0.L << 0; +R1.L = R1.L >> 1; +R2.L = R2.L >> 2; +R3.L = R3.L >> 3; +R4.L = R4.L >> 4; +R5.L = R5.L >> 5; +R6.L = R6.L >> 6; +R7.L = R7.L >> 7; +CHECKREG r0, 0x0000FFFF; +CHECKREG r1, 0x90000000; +CHECKREG r2, 0x90000000; +CHECKREG r3, 0x90000000; +CHECKREG r4, 0x90000000; +CHECKREG r5, 0x90000000; +CHECKREG r6, 0x90000000; +CHECKREG r7, 0x90000000; + +imm32 r0, 0x00001001; +R1.L = -1; +imm32 r2, 0xa0002002; +imm32 r3, 0xa0003003; +imm32 r4, 0xa0004004; +imm32 r5, 0xa0005005; +imm32 r6, 0xa0006006; +imm32 r7, 0xa0007007; +R0.L = R0.L >> 1; +R1.L = R1.L >> 1; +R2.L = R2.L >> 1; +R3.L = R3.L >> 1; +R4.L = R4.L >> 1; +R5.L = R5.L >> 1; +R6.L = R6.L >> 1; +R7.L = R7.L >> 1; +CHECKREG r0, 0x00000800; +CHECKREG r1, 0x90007FFF; +CHECKREG r2, 0xA0001001; +CHECKREG r3, 0xA0001801; +CHECKREG r4, 0xA0002002; +CHECKREG r5, 0xA0002802; +CHECKREG r6, 0xA0003003; +CHECKREG r7, 0xA0003803; + + +imm32 r0, 0xb0001001; +imm32 r1, 0xb0001001; +R2.L = -15; +imm32 r3, 0xb0003003; +imm32 r4, 0xb0004004; +imm32 r5, 0xb0005005; +imm32 r6, 0xb0006006; +imm32 r7, 0xb0007007; +R0.L = R0.L >> 15; +R1.L = R1.L >> 15; +R2.L = LSHIFT R2.L BY R2.L; +R3.L = R3.L >> 15; +R4.L = R4.L >> 15; +R5.L = R5.L >> 15; +R6.L = R6.L >> 15; +R7.L = R7.L >> 15; +CHECKREG r0, 0xb0000000; +CHECKREG r1, 0xb0000000; +CHECKREG r2, 0xA0000001; +CHECKREG r3, 0xB0000000; +CHECKREG r4, 0xb0000000; +CHECKREG r5, 0xb0000000; +CHECKREG r6, 0xb0000000; +CHECKREG r7, 0xB0000000; + +imm32 r0, 0xc0001001; +imm32 r1, 0xc0001001; +imm32 r2, 0xc0002002; +R3.L = -16; +imm32 r4, 0xc0004004; +imm32 r5, 0xc0005005; +imm32 r6, 0xc0006006; +imm32 r7, 0xc0007007; +R0.L = R0.L >> 13; +R1.L = R1.L >> 13; +R2.L = R2.L >> 13; +R3.L = R3.L >> 13; +R4.L = R4.L >> 13; +R5.L = R5.L >> 13; +R6.L = R6.L >> 13; +R7.L = R7.L >> 13; +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0000000; +CHECKREG r2, 0xC0000001; +CHECKREG r3, 0xB0000007; +CHECKREG r4, 0xC0000002; +CHECKREG r5, 0xC0000002; +CHECKREG r6, 0xC0000003; +CHECKREG r7, 0xC0000003; + +// RHx by RLx +imm32 r0, 0x0000c000; +imm32 r1, 0x0001c000; +imm32 r2, 0x0002c000; +imm32 r3, 0x0003c000; +imm32 r4, 0x0004c000; +imm32 r5, 0x0005c000; +imm32 r6, 0x0006c000; +imm32 r7, 0x0007c000; +R0.L = R0.H << 0; +R1.L = R1.H << 0; +R2.L = R2.H << 0; +R3.L = R3.H << 0; +R4.L = R4.H << 0; +R5.L = R5.H << 0; +R6.L = R6.H << 0; +R7.L = R7.H << 0; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00010001; +CHECKREG r2, 0x00020002; +CHECKREG r3, 0x00030003; +CHECKREG r4, 0x00040004; +CHECKREG r5, 0x00050005; +CHECKREG r6, 0x00060006; +CHECKREG r7, 0x00070007; + +imm32 r0, 0x10010000; +R1.L = -1; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.L = R0.H >> 1; +R1.L = R1.H >> 1; +R2.L = R2.H >> 1; +R3.L = R3.H >> 1; +R4.L = R4.H >> 1; +R5.L = R5.H >> 1; +R6.L = R6.H >> 1; +R7.L = R7.H >> 1; +CHECKREG r0, 0x10010800; +CHECKREG r1, 0x00010000; +CHECKREG r2, 0x20021001; +CHECKREG r3, 0x30031801; +CHECKREG r4, 0x40042002; +CHECKREG r5, 0x50052802; +CHECKREG r6, 0x60063003; +CHECKREG r7, 0x70073803; + + +imm32 r0, 0x1001e000; +imm32 r1, 0x1001e000; +R2.L = -15; +imm32 r3, 0x3003e000; +imm32 r4, 0x4004e000; +imm32 r5, 0x5005e000; +imm32 r6, 0x6006e000; +imm32 r7, 0x7007e000; +R0.L = R0.H >> 15; +R1.L = R1.H >> 15; +R2.L = R2.H >> 15; +R3.L = R3.H >> 15; +R4.L = R4.H >> 15; +R5.L = R5.H >> 15; +R6.L = R6.H >> 15; +R7.L = R7.H >> 15; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020000; +CHECKREG r3, 0x30030000; +CHECKREG r4, 0x40040000; +CHECKREG r5, 0x50050000; +CHECKREG r6, 0x60060000; +CHECKREG r7, 0x70070000; + +imm32 r0, 0x1001f001; +imm32 r1, 0x1001f001; +imm32 r2, 0x2002f002; +R3.L = -16; +imm32 r4, 0x4004f004; +imm32 r5, 0x5005f005; +imm32 r6, 0x6006f006; +imm32 r7, 0x7007f007; +R0.L = R0.H >> 13; +R1.L = R1.H >> 13; +R2.L = R2.H >> 13; +R3.L = R3.H >> 13; +R4.L = R4.H >> 13; +R5.L = R5.H >> 13; +R6.L = R6.H >> 13; +R7.L = R7.H >> 13; +CHECKREG r0, 0x10010000; +CHECKREG r1, 0x10010000; +CHECKREG r2, 0x20020001; +CHECKREG r3, 0x30030001; +CHECKREG r4, 0x40040002; +CHECKREG r5, 0x50050002; +CHECKREG r6, 0x60060003; +CHECKREG r7, 0x70070003; + +// RLx by RLx +imm32 r0, 0x00001001; +imm32 r1, 0x00001001; +imm32 r2, 0x00001002; +imm32 r3, 0x00001003; +imm32 r4, 0x00001000; +imm32 r5, 0x00001005; +imm32 r6, 0x00001006; +imm32 r7, 0x00001007; +R0.H = R0.L >> 14; +R1.H = R1.L >> 14; +R2.H = R2.L >> 14; +R3.H = R3.L >> 14; +R4.H = R4.L >> 14; +R5.H = R5.L >> 14; +R6.H = R6.L >> 14; +R7.H = R7.L >> 14; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00001001; +CHECKREG r2, 0x00001002; +CHECKREG r3, 0x00001003; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00001005; +CHECKREG r6, 0x00001006; +CHECKREG r7, 0x00001007; + +imm32 r0, 0x00002001; +imm32 r1, 0x00002001; +imm32 r2, 0x00002002; +imm32 r3, 0x00002003; +imm32 r4, 0x00002004; +R5.L = -1; +imm32 r6, 0x00000006; +imm32 r7, 0x00000007; +R0.H = R0.L >> 5; +R1.H = R1.L >> 5; +R2.H = R2.L >> 5; +R3.H = R3.L >> 5; +R4.H = R4.L >> 5; +R5.H = R5.L >> 5; +R6.H = R6.L >> 5; +R7.H = R7.L >> 5; +CHECKREG r0, 0x01002001; +CHECKREG r1, 0x01002001; +CHECKREG r2, 0x01002002; +CHECKREG r3, 0x01002003; +CHECKREG r4, 0x01002004; +CHECKREG r5, 0x07FFFFFF; +CHECKREG r6, 0x00000006; +CHECKREG r7, 0x00000007; + + +imm32 r0, 0x30001001; +imm32 r1, 0x30001001; +imm32 r1, 0x30002002; +imm32 r3, 0x30003003; +imm32 r4, 0x30004004; +imm32 r5, 0x30005005; +R6.L = -15; +imm32 r7, 0x00007007; +R0.H = R0.L >> 15; +R1.H = R1.L >> 15; +R2.H = R2.L >> 15; +R3.H = R3.L >> 15; +R4.H = R4.L >> 15; +R5.H = R5.L >> 15; +R6.H = R6.L >> 15; +R7.H = R7.L >> 15; +CHECKREG r0, 0x00001001; +CHECKREG r1, 0x00002002; +CHECKREG r2, 0x00002002; +CHECKREG r3, 0x00003003; +CHECKREG r4, 0x00004004; +CHECKREG r5, 0x00005005; +CHECKREG r6, 0x0001FFF1; +CHECKREG r7, 0x00007007; + +imm32 r0, 0x40001001; +imm32 r1, 0x40002001; +imm32 r2, 0x40002002; +imm32 r3, 0x40003003; +imm32 r4, 0x40004004; +imm32 r5, 0x40005005; +imm32 r6, 0x40006006; +R7.L = -16; +R0.H = R0.L >> 7; +R1.H = R1.L >> 7; +R2.H = R2.L >> 7; +R3.H = R3.L >> 7; +R4.H = R4.L >> 7; +R5.H = R5.L >> 7; +R6.H = R6.L >> 7; +R7.H = R7.L >> 7; +CHECKREG r0, 0x00201001; +CHECKREG r1, 0x00402001; +CHECKREG r2, 0x00402002; +CHECKREG r3, 0x00603003; +CHECKREG r4, 0x00804004; +CHECKREG r5, 0x00A05005; +CHECKREG r6, 0x00C06006; +CHECKREG r7, 0x01FFFFF0; + +// RHx by RLx +imm32 r0, 0x50010000; +imm32 r1, 0x50010000; +imm32 r2, 0x50020000; +imm32 r3, 0x50030000; +R4.L = -1; +imm32 r5, 0x50050000; +imm32 r6, 0x50060000; +imm32 r7, 0x50070000; +R0.H = R0.H >> 1; +R1.H = R1.H >> 1; +R2.H = R2.H >> 1; +R3.H = R3.H >> 1; +R4.H = R4.H >> 1; +R5.H = R5.H >> 1; +R6.H = R6.H >> 1; +R7.H = R7.H >> 1; +CHECKREG r0, 0x28000000; +CHECKREG r1, 0x28000000; +CHECKREG r2, 0x28010000; +CHECKREG r3, 0x28010000; +CHECKREG r4, 0x0040FFFF; +CHECKREG r5, 0x28020000; +CHECKREG r6, 0x28030000; +CHECKREG r7, 0x28030000; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +R5.L = -1; +imm32 r6, 0x60060000; +imm32 r7, 0x70070000; +R0.H = R0.H >> 5; +R1.H = R1.H >> 5; +R2.H = R2.H >> 5; +R3.H = R3.H >> 5; +R4.H = R4.H >> 5; +R5.H = R5.H >> 5; +R6.H = R6.H >> 5; +R7.H = R7.H >> 5; +CHECKREG r0, 0x00800000; +CHECKREG r1, 0x00800000; +CHECKREG r2, 0x01000000; +CHECKREG r3, 0x01800000; +CHECKREG r4, 0x02000000; +CHECKREG r5, 0x0140FFFF; +CHECKREG r6, 0x03000000; +CHECKREG r7, 0x03800000; + + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r3, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +R6.L = -15; +imm32 r7, 0x70070000; +R0.L = R0.H >> 6; +R1.L = R1.H >> 6; +R2.L = R2.H >> 6; +R3.L = R3.H >> 6; +R4.L = R4.H >> 6; +R5.L = R5.H >> 6; +R6.L = R6.H >> 6; +R7.L = R7.H >> 6; +CHECKREG r0, 0x10010040; +CHECKREG r1, 0x10010040; +CHECKREG r2, 0x20020080; +CHECKREG r3, 0x300300C0; +CHECKREG r4, 0x40040100; +CHECKREG r5, 0x50050140; +CHECKREG r6, 0x0300000C; +CHECKREG r7, 0x700701C0; + +imm32 r0, 0x10010000; +imm32 r1, 0x10010000; +imm32 r2, 0x20020000; +imm32 r2, 0x30030000; +imm32 r4, 0x40040000; +imm32 r5, 0x50050000; +imm32 r6, 0x60060000; +R7.L = -16; +R0.H = R0.H >> 15; +R1.H = R1.H >> 15; +R2.H = R2.H >> 15; +R3.H = R3.H >> 15; +R4.H = R4.H >> 15; +R5.H = R5.H >> 15; +R6.H = R6.H >> 15; +R7.H = R7.H >> 15; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x000000C0; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x0000FFF0; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lhh.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhh.s new file mode 100644 index 0000000..e129dca --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_lhh.s @@ -0,0 +1,65 @@ +//Original:/testcases/core/c_dsp32shiftim_lhh/c_dsp32shiftim_lhh.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm lshift: lshift / lshift + + + +imm32 r0, 0x01230abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R0 = R0 << 0 (V); +R1 = R1 << 3 (V); +R2 = R2 << 5 (V); +R3 = R3 << 8 (V); +R4 = R4 << 9 (V); +R5 = R5 << 15 (V); +R6 = R6 << 7 (V); +R7 = R7 << 13 (V); +CHECKREG r0, 0x01230ABC; +CHECKREG r1, 0x91A0B3C0; +CHECKREG r2, 0x68A0F120; +CHECKREG r3, 0x56009A00; +CHECKREG r4, 0xCE005600; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0xC480E680; +CHECKREG r7, 0x4000C000; + +imm32 r0, 0x01230000; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x456789ab; +imm32 r5, 0x56789abc; +imm32 r6, 0x6789abcd; +imm32 r7, 0x789abcde; +R7 = R0 >> 11 (V); +R0 = R1 >> 8 (V); +R1 = R2 >> 14 (V); +R2 = R3 >> 15 (V); +R3 = R4 >> 10 (V); +R4 = R5 >> 2 (V); +R5 = R6 >> 9 (V); +R6 = R7 >> 6 (V); +CHECKREG r0, 0x00120056; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00110022; +CHECKREG r4, 0x159E26AF; +CHECKREG r5, 0x00330055; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + + + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_lmix.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_lmix.s new file mode 100644 index 0000000..82845ff --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_lmix.s @@ -0,0 +1,138 @@ +//Original:/testcases/core/c_dsp32shiftim_lmix/c_dsp32shiftim_lmix.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: dsp32shiftimm lshift: mix + + + + +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + + +// Lshift (Logical ) +// Lshift : positive data, count (+)=left (half reg) +imm32 r0, 0x00010001; +imm32 r1, 1; +imm32 r2, 0x00020002; +imm32 r3, 2; +R4.H = R0.H << 1; +R4.L = R0.L << 1; /* r4 = 0x00020002 */ +R5.H = R2.H << 2; +R5.L = R2.L << 2; /* r5 = 0x00080008 */ +R6 = R0 << 1 (V); /* r6 = 0x00020002 */ +R7 = R2 << 2 (V); /* r7 = 0x00080008 */ +CHECKREG r4, 0x00020002; +CHECKREG r5, 0x00080008; +CHECKREG r6, 0x00020002; +CHECKREG r7, 0x00080008; + +// Lshift : (full reg) +imm32 r1, 3; +imm32 r3, 4; +R6 = R0 << 3; /* r6 = 0x00080010 */ +R7 = R2 << 4; +CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */ +CHECKREG r7, 0x00200020; + +A0 = 0; +A0.L = R0.L; +A0.H = R0.H; +A0 = A0 << 3; /* a0 = 0x00080008 */ +R5 = A0.w; /* r5 = 0x00080008 */ +CHECKREG r5, 0x00080008; + +imm32 r4, 0x30000003; +imm32 r1, 1; +R5 = R4 << 1; /* r5 = 0x60000006 */ +imm32 r1, 2; +R6 = R4 << 2; /* r6 = 0xc000000c like LSHIFT */ +CHECKREG r5, 0x60000006; +CHECKREG r6, 0xc000000c; + + +// lshift : count (-)=right (half reg) +imm32 r0, 0x10001000; +imm32 r1, -1; +imm32 r2, 0x10001000; +imm32 r3, -2; +R4.H = R0.H >> 1; +R4.L = R0.L >> 1; /* r4 = 0x08000800 */ +R5.H = R2.H >> 2; +R5.L = R2.L >> 2; /* r4 = 0x04000400 */ +R6 = R0 >> 1 (V); /* r4 = 0x08000800 */ +R7 = R2 >> 2 (V); /* r4 = 0x04000400 */ +CHECKREG r4, 0x08000800; +CHECKREG r5, 0x04000400; +CHECKREG r6, 0x08000800; +CHECKREG r7, 0x04000400; + +// lshift : (full reg) +imm32 r1, -3; +imm32 r3, -4; +R6 = R0 >> 3; /* r6 = 0x02000200 */ +R7 = R2 >> 4; /* r7 = 0x01000100 */ +CHECKREG r6, 0x02000200; +CHECKREG r7, 0x01000100; + +// NEGATIVE +// lshift : NEGATIVE data, count (+)=left (half reg) +imm32 r0, 0xc00f800f; +imm32 r1, 1; +imm32 r2, 0xe00fe00f; +imm32 r3, 2; +R4.H = R0.H << 1; +R4.L = R0.L << 1; /* r4 = 0x801e001e */ +R5.H = R2.H << 2; +R5.L = R2.L << 2; /* r4 = 0x803c803c */ +CHECKREG r4, 0x801e001e; +CHECKREG r5, 0x803c803c; + +imm32 r0, 0xc80fe00f; +imm32 r2, 0xe40fe00f; +imm32 r1, 4; +imm32 r3, 5; +R6 = R0 << 4; /* r6 = 0x80fe00f0 */ +R7 = R2 << 5; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + +imm32 r0, 0xf80fe00f; +imm32 r2, 0xfc0fe00f; +R6 = R0 << 4; /* r6 = 0x80fe00f0 */ +R7 = R2 << 5; /* r7 = 0x81fc01e0 */ +CHECKREG r6, 0x80fe00f0; +CHECKREG r7, 0x81fc01e0; + + + +// lshift : NEGATIVE data, count (-)=right (half reg) Working ok +imm32 r0, 0x80f080f0; +imm32 r1, -1; +imm32 r2, 0x80f080f0; +imm32 r3, -2; +R4.H = R0.H >> 1; +R4.L = R0.L >> 1; /* r4 = 0x40784078 */ +R5.H = R2.H >> 2; +R5.L = R2.L >> 2; /* r4 = 0x203c203c */ +CHECKREG r4, 0x40784078; +CHECKREG r5, 0x203c203c; +R6 = R0 >> 1 (V); /* r6 = 0x40784078 */ +R7 = R2 >> 2 (V); /* r7 = 0x203c203c */ +CHECKREG r6, 0x40784078; +CHECKREG r7, 0x203c203c; + +imm32 r1, -3; +imm32 r3, -4; +R6 = R0 >> 3; /* r6 = 0x101e101e */ +R7 = R2 >> 4; /* r7 = 0x080f080f */ +CHECKREG r6, 0x101e101e; +CHECKREG r7, 0x080f080f; + +pass diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s new file mode 100644 index 0000000..0b47eda --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s @@ -0,0 +1,62 @@ +//Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_rot/c_dsp32shiftim_rot.dsp +// Spec Reference: dsp32shiftimm rot: +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + + imm32 r0, 0xa1230001; + imm32 r1, 0x1b345678; + imm32 r2, 0x23c56789; + imm32 r3, 0x34d6789a; + imm32 r4, 0x85a789ab; + imm32 r5, 0x967c9abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb8912cde; + R0 = ROT R0 BY 1; + R1 = ROT R1 BY 5; + R2 = ROT R2 BY 9; + R3 = ROT R3 BY 8; + R4 = ROT R4 BY 24; + R5 = ROT R5 BY 31; + R6 = ROT R6 BY 14; + R7 = ROT R7 BY 25; + CHECKREG r0, 0x42460002; + CHECKREG r1, 0x668ACF11; + CHECKREG r2, 0x8ACF1323; + CHECKREG r3, 0xD6789A9A; + CHECKREG r4, 0xAB42D3C4; + CHECKREG r5, 0x659F26AF; + CHECKREG r6, 0x6AF354F1; + CHECKREG r7, 0xBCB8912C; + + imm32 r0, 0xa1230001; + imm32 r1, 0x1b345678; + imm32 r2, 0x23c56789; + imm32 r3, 0x34d6789a; + imm32 r4, 0x85a789ab; + imm32 r5, 0x967c9abc; + imm32 r6, 0xa789abcd; + imm32 r7, 0xb8912cde; + R6 = ROT R0 BY -3; + R7 = ROT R1 BY -9; + R0 = ROT R2 BY -8; + R1 = ROT R3 BY -7; + R2 = ROT R4 BY -15; + R3 = ROT R5 BY -24; + R4 = ROT R6 BY -31; + R5 = ROT R7 BY -22; + CHECKREG r0, 0x1223C567; + CHECKREG r1, 0x6A69ACF1; + CHECKREG r2, 0x26AD0B4F; + CHECKREG r3, 0xF9357896; + CHECKREG r4, 0xD0918000; + CHECKREG r5, 0x6CD15DE0; + CHECKREG r6, 0x74246000; + CHECKREG r7, 0x780D9A2B; + + pass diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_dr_i.s b/sim/testsuite/sim/bfin/c_dspldst_ld_dr_i.s new file mode 100644 index 0000000..02743cc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_ld_dr_i.s @@ -0,0 +1,168 @@ +//Original:/testcases/core/c_dspldst_ld_dr_i/c_dspldst_ld_dr_i.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: c_dspldst ld_dr_i + + +// set all regs + + INIT_R_REGS 0; + +// initial values + loadsym I0, DATA1 + loadsym I1, DATA2 + loadsym I2, DATA3 + loadsym I3, DATA4 + + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x00010203; + CHECKREG r5, 0x20212223; + CHECKREG r6, 0x40414243; + CHECKREG r7, 0x60616263; + R1 = [ I0 ]; + R2 = [ I1 ]; + R3 = [ I2 ]; + R4 = [ I3 ]; + R5 = [ I0 ]; + R6 = [ I1 ]; + R7 = [ I2 ]; + R0 = [ I3 ]; + CHECKREG r0, 0x60616263; + CHECKREG r1, 0x00010203; + CHECKREG r2, 0x20212223; + CHECKREG r3, 0x40414243; + CHECKREG r4, 0x60616263; + CHECKREG r5, 0x00010203; + CHECKREG r6, 0x20212223; + CHECKREG r7, 0x40414243; + R2 = [ I0 ]; + R3 = [ I1 ]; + R4 = [ I2 ]; + R5 = [ I3 ]; + R6 = [ I0 ]; + R7 = [ I1 ]; + R0 = [ I2 ]; + R1 = [ I3 ]; + CHECKREG r0, 0x40414243; + CHECKREG r1, 0x60616263; + CHECKREG r2, 0x00010203; + CHECKREG r3, 0x20212223; + CHECKREG r4, 0x40414243; + CHECKREG r5, 0x60616263; + CHECKREG r6, 0x00010203; + CHECKREG r7, 0x20212223; + + R3 = [ I0 ]; + R4 = [ I1 ]; + R5 = [ I2 ]; + R6 = [ I3 ]; + R7 = [ I0 ]; + R0 = [ I1 ]; + R1 = [ I2 ]; + R2 = [ I3 ]; + CHECKREG r0, 0x20212223; + CHECKREG r1, 0x40414243; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x00010203; + CHECKREG r4, 0x20212223; + CHECKREG r5, 0x40414243; + CHECKREG r6, 0x60616263; + CHECKREG r7, 0x00010203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ipp.s b/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ipp.s new file mode 100644 index 0000000..d94dfc2 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ipp.s @@ -0,0 +1,348 @@ +//Original:/testcases/core/c_dspldst_ld_dr_ipp/c_dspldst_ld_dr_ipp.dsp +// Spec Reference: c_dspldst ld_dr_i++/-- +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x04050607; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x44454647; + CHECKREG r7, 0x64656667; + R1 = [ I0 ++ ]; + R2 = [ I1 ++ ]; + R3 = [ I2 ++ ]; + R4 = [ I3 ++ ]; + R5 = [ I0 ++ ]; + R6 = [ I1 ++ ]; + R7 = [ I2 ++ ]; + R0 = [ I3 ++ ]; + CHECKREG r0, 0x6C6D6E6F; + CHECKREG r1, 0x08090A0B; + CHECKREG r2, 0x28292A2B; + CHECKREG r3, 0x48494A4B; + CHECKREG r4, 0x68696A6B; + CHECKREG r5, 0x0C0D0E0F; + CHECKREG r6, 0x2C2D2E2F; + CHECKREG r7, 0x4C4D4E4F; + R2 = [ I0 ++ ]; + R3 = [ I1 ++ ]; + R4 = [ I2 ++ ]; + R5 = [ I3 ++ ]; + R6 = [ I0 ++ ]; + R7 = [ I1 ++ ]; + R0 = [ I2 ++ ]; + R1 = [ I3 ++ ]; + CHECKREG r0, 0x54555657; + CHECKREG r1, 0x74757677; + CHECKREG r2, 0x10111213; + CHECKREG r3, 0x30313233; + CHECKREG r4, 0x50515253; + CHECKREG r5, 0x70717273; + CHECKREG r6, 0x14151617; + CHECKREG r7, 0x34353637; + + R3 = [ I0 ++ ]; + R4 = [ I1 ++ ]; + R5 = [ I2 ++ ]; + R6 = [ I3 ++ ]; + R7 = [ I0 ++ ]; + R0 = [ I1 ++ ]; + R1 = [ I2 ++ ]; + R2 = [ I3 ++ ]; + CHECKREG r0, 0x3C3D3E3F; + CHECKREG r1, 0xC5C6C7C8; + CHECKREG r2, 0x7C7D7E7F; + CHECKREG r3, 0x18191A1B; + CHECKREG r4, 0x38393A3B; + CHECKREG r5, 0x58595A5B; + CHECKREG r6, 0x78797A7B; + CHECKREG r7, 0x1C1D1E1F; + +// reverse to minus mninus i-- + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0x11223344; + CHECKREG r1, 0x91929394; + CHECKREG r2, 0xC9CACBCD; + CHECKREG r3, 0xEBECEDEE; + CHECKREG r4, 0x1C1D1E1F; + CHECKREG r5, 0x3C3D3E3F; + CHECKREG r6, 0xC5C6C7C8; + CHECKREG r7, 0x7C7D7E7F; + R1 = [ I0 -- ]; + R2 = [ I1 -- ]; + R3 = [ I2 -- ]; + R4 = [ I3 -- ]; + R5 = [ I0 -- ]; + R6 = [ I1 -- ]; + R7 = [ I2 -- ]; + R0 = [ I3 -- ]; + CHECKREG r0, 0x74757677; + CHECKREG r1, 0x18191A1B; + CHECKREG r2, 0x38393A3B; + CHECKREG r3, 0x58595A5B; + CHECKREG r4, 0x78797A7B; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x34353637; + CHECKREG r7, 0x54555657; + R2 = [ I0 -- ]; + R3 = [ I1 -- ]; + R4 = [ I2 -- ]; + R5 = [ I3 -- ]; + R6 = [ I0 -- ]; + R7 = [ I1 -- ]; + R0 = [ I2 -- ]; + R1 = [ I3 -- ]; + CHECKREG r0, 0x4C4D4E4F; + CHECKREG r1, 0x6C6D6E6F; + CHECKREG r2, 0x10111213; + CHECKREG r3, 0x30313233; + CHECKREG r4, 0x50515253; + CHECKREG r5, 0x70717273; + CHECKREG r6, 0x0C0D0E0F; + CHECKREG r7, 0x2C2D2E2F; + + R3 = [ I0 -- ]; + R4 = [ I1 -- ]; + R5 = [ I2 -- ]; + R6 = [ I3 -- ]; + R7 = [ I0 -- ]; + R0 = [ I1 -- ]; + R1 = [ I2 -- ]; + R2 = [ I3 -- ]; + CHECKREG r0, 0x24252627; + CHECKREG r1, 0x44454647; + CHECKREG r2, 0x64656667; + CHECKREG r3, 0x08090A0B; + CHECKREG r4, 0x28292A2B; + CHECKREG r5, 0x48494A4B; + CHECKREG r6, 0x68696A6B; + CHECKREG r7, 0x04050607; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xBC0DBE26 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ippm.s b/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ippm.s new file mode 100644 index 0000000..abdc823 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ippm.s @@ -0,0 +1,328 @@ +//Original:/testcases/core/c_dspldst_ld_dr_ippm/c_dspldst_ld_dr_ippm.dsp +// Spec Reference: c_dspldst ld_dr_i++m +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + M0 = 0 (X); + M1 = 0x4 (X); + M2 = 0x0 (X); + M3 = 0x4 (X); + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + R0 = [ I0 ++ M0 ]; + R1 = [ I1 ++ M1 ]; + R2 = [ I2 ++ M2 ]; + R3 = [ I3 ++ M3 ]; + R4 = [ I0 ++ M1 ]; + R5 = [ I1 ++ M2 ]; + R6 = [ I2 ++ M3 ]; + R7 = [ I3 ++ M0 ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x00010203; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x40414243; + CHECKREG r7, 0x64656667; + R1 = [ I0 ++ M2 ]; + R2 = [ I1 ++ M3 ]; + R3 = [ I2 ++ M0 ]; + R4 = [ I3 ++ M1 ]; + R5 = [ I0 ++ M3 ]; + R6 = [ I1 ++ M0 ]; + R7 = [ I2 ++ M1 ]; + R0 = [ I3 ++ M2 ]; + CHECKREG r0, 0x68696A6B; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x24252627; + CHECKREG r3, 0x44454647; + CHECKREG r4, 0x64656667; + CHECKREG r5, 0x04050607; + CHECKREG r6, 0x28292A2B; + CHECKREG r7, 0x44454647; + + M0 = 4 (X); + M1 = 0x0 (X); + M2 = 0x4 (X); + M3 = 0x0 (X); + R2 = [ I0 ++ M0 ]; + R3 = [ I1 ++ M1 ]; + R4 = [ I2 ++ M2 ]; + R5 = [ I3 ++ M3 ]; + R6 = [ I0 ++ M1 ]; + R7 = [ I1 ++ M2 ]; + R0 = [ I2 ++ M3 ]; + R1 = [ I3 ++ M0 ]; + CHECKREG r0, 0x4C4D4E4F; + CHECKREG r1, 0x68696A6B; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x28292A2B; + CHECKREG r4, 0x48494A4B; + CHECKREG r5, 0x68696A6B; + CHECKREG r6, 0x0C0D0E0F; + CHECKREG r7, 0x28292A2B; + + R3 = [ I0 ++ M2 ]; + R4 = [ I1 ++ M3 ]; + R5 = [ I2 ++ M0 ]; + R6 = [ I3 ++ M1 ]; + R7 = [ I0 ++ M3 ]; + R0 = [ I1 ++ M0 ]; + R1 = [ I2 ++ M1 ]; + R2 = [ I3 ++ M2 ]; + CHECKREG r0, 0x2C2D2E2F; + CHECKREG r1, 0x50515253; + CHECKREG r2, 0x6C6D6E6F; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x2C2D2E2F; + CHECKREG r5, 0x4C4D4E4F; + CHECKREG r6, 0x6C6D6E6F; + CHECKREG r7, 0x10111213; + + R5 = [ I0 ++ M2 ]; + R6 = [ I1 ++ M3 ]; + R7 = [ I2 ++ M0 ]; + R0 = [ I3 ++ M1 ]; + R1 = [ I0 ++ M3 ]; + R2 = [ I1 ++ M0 ]; + R3 = [ I2 ++ M1 ]; + R4 = [ I3 ++ M2 ]; + CHECKREG r0, 0x70717273; + CHECKREG r1, 0x14151617; + CHECKREG r2, 0x30313233; + CHECKREG r3, 0x54555657; + CHECKREG r4, 0x70717273; + CHECKREG r5, 0x10111213; + CHECKREG r6, 0x30313233; + CHECKREG r7, 0x50515253; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_i.s b/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_i.s new file mode 100644 index 0000000..3ada175 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_i.s @@ -0,0 +1,168 @@ +//Original:/testcases/core/c_dspldst_ld_drhi_i/c_dspldst_ld_drhi_i.dsp +// Spec Reference: c_dspldst ld_drhi_i +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + + INIT_R_REGS 0; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + +// Load upper half of Dregs + R0.H = W [ I0 ]; + R1.H = W [ I1 ]; + R2.H = W [ I2 ]; + R3.H = W [ I3 ]; + R4.H = W [ I0 ]; + R5.H = W [ I1 ]; + R6.H = W [ I2 ]; + R7.H = W [ I3 ]; + CHECKREG r0, 0x02030000; + CHECKREG r1, 0x22230000; + CHECKREG r2, 0x42430000; + CHECKREG r3, 0x62630000; + CHECKREG r4, 0x02030000; + CHECKREG r5, 0x22230000; + CHECKREG r6, 0x42430000; + CHECKREG r7, 0x62630000; + + R1.H = W [ I0 ]; + R2.H = W [ I1 ]; + R3.H = W [ I2 ]; + R4.H = W [ I3 ]; + R5.H = W [ I0 ]; + R6.H = W [ I1 ]; + R7.H = W [ I2 ]; + R0.H = W [ I3 ]; + CHECKREG r0, 0x62630000; + CHECKREG r1, 0x02030000; + CHECKREG r2, 0x22230000; + CHECKREG r3, 0x42430000; + CHECKREG r4, 0x62630000; + CHECKREG r5, 0x02030000; + CHECKREG r6, 0x22230000; + CHECKREG r7, 0x42430000; + + R2.H = W [ I0 ]; + R3.H = W [ I1 ]; + R4.H = W [ I2 ]; + R5.H = W [ I3 ]; + R6.H = W [ I0 ]; + R7.H = W [ I1 ]; + R0.H = W [ I2 ]; + R1.H = W [ I3 ]; + CHECKREG r0, 0x42430000; + CHECKREG r1, 0x62630000; + CHECKREG r2, 0x02030000; + CHECKREG r3, 0x22230000; + CHECKREG r4, 0x42430000; + CHECKREG r5, 0x62630000; + CHECKREG r6, 0x02030000; + CHECKREG r7, 0x22230000; + + R3.H = W [ I0 ]; + R4.H = W [ I1 ]; + R5.H = W [ I2 ]; + R6.H = W [ I3 ]; + R7.H = W [ I0 ]; + R0.H = W [ I1 ]; + R1.H = W [ I2 ]; + R2.H = W [ I3 ]; + + CHECKREG r0, 0x22230000; + CHECKREG r1, 0x42430000; + CHECKREG r2, 0x62630000; + CHECKREG r3, 0x02030000; + CHECKREG r4, 0x22230000; + CHECKREG r5, 0x42430000; + CHECKREG r6, 0x62630000; + CHECKREG r7, 0x02030000; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_ipp.s b/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_ipp.s new file mode 100644 index 0000000..e4531af --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_ld_drhi_ipp.s @@ -0,0 +1,364 @@ +//Original:/testcases/core/c_dspldst_ld_drhi_ipp/c_dspldst_ld_drhi_ipp.dsp +// Spec Reference: c_dspldst ld_drhi_i++/-- +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + + INIT_R_REGS 0; + +// initial values +//i0=0x3000; +//i1=0x4000; +//i2=0x5000; +//i3=0x6000; + loadsym I0, DATA_ADDR_3; + loadsym I1, DATA_ADDR_4; + loadsym I2, DATA_ADDR_5; + loadsym I3, DATA_ADDR_6; + +// Load Upper half of Dregs + R0.H = W [ I0 ++ ]; + R1.H = W [ I1 ++ ]; + R2.H = W [ I2 ++ ]; + R3.H = W [ I3 ++ ]; + R4.H = W [ I0 ++ ]; + R5.H = W [ I1 ++ ]; + R6.H = W [ I2 ++ ]; + R7.H = W [ I3 ++ ]; + CHECKREG r0, 0x02030000; + CHECKREG r1, 0x22230000; + CHECKREG r2, 0x42430000; + CHECKREG r3, 0x62630000; + CHECKREG r4, 0x00010000; + CHECKREG r5, 0x20210000; + CHECKREG r6, 0x40410000; + CHECKREG r7, 0x60610000; + + R1.H = W [ I0 ++ ]; + R2.H = W [ I1 ++ ]; + R3.H = W [ I2 ++ ]; + R4.H = W [ I3 ++ ]; + R5.H = W [ I0 ++ ]; + R6.H = W [ I1 ++ ]; + R7.H = W [ I2 ++ ]; + R0.H = W [ I3 ++ ]; + CHECKREG r0, 0x64650000; + CHECKREG r1, 0x06070000; + CHECKREG r2, 0x26270000; + CHECKREG r3, 0x46470000; + CHECKREG r4, 0x66670000; + CHECKREG r5, 0x04050000; + CHECKREG r6, 0x24250000; + CHECKREG r7, 0x44450000; + + R2.H = W [ I0 ++ ]; + R3.H = W [ I1 ++ ]; + R4.H = W [ I2 ++ ]; + R5.H = W [ I3 ++ ]; + R6.H = W [ I0 ++ ]; + R7.H = W [ I1 ++ ]; + R0.H = W [ I2 ++ ]; + R1.H = W [ I3 ++ ]; + CHECKREG r0, 0x48490000; + CHECKREG r1, 0x68690000; + CHECKREG r2, 0x0A0B0000; + CHECKREG r3, 0x2A2B0000; + CHECKREG r4, 0x4A4B0000; + CHECKREG r5, 0x6A6B0000; + CHECKREG r6, 0x08090000; + CHECKREG r7, 0x28290000; + + R3.H = W [ I0 ++ ]; + R4.H = W [ I1 ++ ]; + R5.H = W [ I2 ++ ]; + R6.H = W [ I3 ++ ]; + R7.H = W [ I0 ++ ]; + R0.H = W [ I1 ++ ]; + R1.H = W [ I2 ++ ]; + R2.H = W [ I3 ++ ]; + + CHECKREG r0, 0x2C2D0000; + CHECKREG r1, 0x4C4D0000; + CHECKREG r2, 0x6C6D0000; + CHECKREG r3, 0x0E0F0000; + CHECKREG r4, 0x2E2F0000; + CHECKREG r5, 0x4E4F0000; + CHECKREG r6, 0x6E6F0000; + CHECKREG r7, 0x0C0D0000; + +// reverse to minus mninus i-- +// Load Upper half of Dregs + R0.H = W [ I0 -- ]; + R1.H = W [ I1 -- ]; + R2.H = W [ I2 -- ]; + R3.H = W [ I3 -- ]; + R4.H = W [ I0 -- ]; + R5.H = W [ I1 -- ]; + R6.H = W [ I2 -- ]; + R7.H = W [ I3 -- ]; + CHECKREG r0, 0x12130000; + CHECKREG r1, 0x32330000; + CHECKREG r2, 0x52530000; + CHECKREG r3, 0x72730000; + CHECKREG r4, 0x0C0D0000; + CHECKREG r5, 0x2C2D0000; + CHECKREG r6, 0x4C4D0000; + CHECKREG r7, 0x6C6D0000; + + R1.H = W [ I0 -- ]; + R2.H = W [ I1 -- ]; + R3.H = W [ I2 -- ]; + R4.H = W [ I3 -- ]; + R5.H = W [ I0 -- ]; + R6.H = W [ I1 -- ]; + R7.H = W [ I2 -- ]; + R0.H = W [ I3 -- ]; + CHECKREG r0, 0x68690000; + CHECKREG r1, 0x0E0F0000; + CHECKREG r2, 0x2E2F0000; + CHECKREG r3, 0x4E4F0000; + CHECKREG r4, 0x6E6F0000; + CHECKREG r5, 0x08090000; + CHECKREG r6, 0x28290000; + CHECKREG r7, 0x48490000; + + R2.H = W [ I0 -- ]; + R3.H = W [ I1 -- ]; + R4.H = W [ I2 -- ]; + R5.H = W [ I3 -- ]; + R6.H = W [ I0 -- ]; + R7.H = W [ I1 -- ]; + R0.H = W [ I2 -- ]; + R1.H = W [ I3 -- ]; + CHECKREG r0, 0x44450000; + CHECKREG r1, 0x64650000; + CHECKREG r2, 0x0A0B0000; + CHECKREG r3, 0x2A2B0000; + CHECKREG r4, 0x4A4B0000; + CHECKREG r5, 0x6A6B0000; + CHECKREG r6, 0x04050000; + CHECKREG r7, 0x24250000; + + R3.H = W [ I0 -- ]; + R4.H = W [ I1 -- ]; + R5.H = W [ I2 -- ]; + R6.H = W [ I3 -- ]; + R7.H = W [ I0 -- ]; + R0.H = W [ I1 -- ]; + R1.H = W [ I2 -- ]; + R2.H = W [ I3 -- ]; + + CHECKREG r0, 0x20210000; + CHECKREG r1, 0x40410000; + CHECKREG r2, 0x60610000; + CHECKREG r3, 0x06070000; + CHECKREG r4, 0x26270000; + CHECKREG r5, 0x46470000; + CHECKREG r6, 0x66670000; + CHECKREG r7, 0x00010000; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xBC0DBE26 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_i.s b/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_i.s new file mode 100644 index 0000000..aec575c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_i.s @@ -0,0 +1,164 @@ +//Original:/testcases/core/c_dspldst_ld_drlo_i/c_dspldst_ld_drlo_i.dsp +// Spec Reference: c_dspldst ld_drlo_i +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + +// Load Lower half of Dregs + R0.L = W [ I0 ]; + R1.L = W [ I1 ]; + R2.L = W [ I2 ]; + R3.L = W [ I3 ]; + R4.L = W [ I0 ]; + R5.L = W [ I1 ]; + R6.L = W [ I2 ]; + R7.L = W [ I3 ]; + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00000203; + CHECKREG r5, 0x00002223; + CHECKREG r6, 0x00004243; + CHECKREG r7, 0x00006263; + + R1.L = W [ I0 ]; + R2.L = W [ I1 ]; + R3.L = W [ I2 ]; + R4.L = W [ I3 ]; + R5.L = W [ I0 ]; + R6.L = W [ I1 ]; + R7.L = W [ I2 ]; + R0.L = W [ I3 ]; + CHECKREG r0, 0x00006263; + CHECKREG r1, 0x00000203; + CHECKREG r2, 0x00002223; + CHECKREG r3, 0x00004243; + CHECKREG r4, 0x00006263; + CHECKREG r5, 0x00000203; + CHECKREG r6, 0x00002223; + CHECKREG r7, 0x00004243; + + R2.L = W [ I0 ]; + R3.L = W [ I1 ]; + R4.L = W [ I2 ]; + R5.L = W [ I3 ]; + R6.L = W [ I0 ]; + R7.L = W [ I1 ]; + R0.L = W [ I2 ]; + R1.L = W [ I3 ]; + CHECKREG r0, 0x00004243; + CHECKREG r1, 0x00006263; + CHECKREG r2, 0x00000203; + CHECKREG r3, 0x00002223; + CHECKREG r4, 0x00004243; + CHECKREG r5, 0x00006263; + CHECKREG r6, 0x00000203; + CHECKREG r7, 0x00002223; + + R3.L = W [ I0 ]; + R4.L = W [ I1 ]; + R5.L = W [ I2 ]; + R6.L = W [ I3 ]; + R7.L = W [ I0 ]; + R0.L = W [ I1 ]; + R1.L = W [ I2 ]; + R2.L = W [ I3 ]; + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0x00000203; + CHECKREG r4, 0x00002223; + CHECKREG r5, 0x00004243; + CHECKREG r6, 0x00006263; + CHECKREG r7, 0x00000203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_ipp.s b/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_ipp.s new file mode 100644 index 0000000..d47b6b8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_ld_drlo_ipp.s @@ -0,0 +1,355 @@ +//Original:/testcases/core/c_dspldst_ld_drlo_ipp/c_dspldst_ld_drlo_ipp.dsp +// Spec Reference: c_dspldst ld_drlo_i++/-- +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + +// Load Lower half of Dregs + R0.L = W [ I0 ++ ]; + R1.L = W [ I1 ++ ]; + R2.L = W [ I2 ++ ]; + R3.L = W [ I3 ++ ]; + R4.L = W [ I0 ++ ]; + R5.L = W [ I1 ++ ]; + R6.L = W [ I2 ++ ]; + R7.L = W [ I3 ++ ]; + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00000001; + CHECKREG r5, 0x00002021; + CHECKREG r6, 0x00004041; + CHECKREG r7, 0x00006061; + + R1.L = W [ I0 ++ ]; + R2.L = W [ I1 ++ ]; + R3.L = W [ I2 ++ ]; + R4.L = W [ I3 ++ ]; + R5.L = W [ I0 ++ ]; + R6.L = W [ I1 ++ ]; + R7.L = W [ I2 ++ ]; + R0.L = W [ I3 ++ ]; + CHECKREG r0, 0x00006465; + CHECKREG r1, 0x00000607; + CHECKREG r2, 0x00002627; + CHECKREG r3, 0x00004647; + CHECKREG r4, 0x00006667; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00004445; + + R2.L = W [ I0 ++ ]; + R3.L = W [ I1 ++ ]; + R4.L = W [ I2 ++ ]; + R5.L = W [ I3 ++ ]; + R6.L = W [ I0 ++ ]; + R7.L = W [ I1 ++ ]; + R0.L = W [ I2 ++ ]; + R1.L = W [ I3 ++ ]; + CHECKREG r0, 0x00004849; + CHECKREG r1, 0x00006869; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00002A2B; + CHECKREG r4, 0x00004A4B; + CHECKREG r5, 0x00006A6B; + CHECKREG r6, 0x00000809; + CHECKREG r7, 0x00002829; + + R3.L = W [ I0 ++ ]; + R4.L = W [ I1 ++ ]; + R5.L = W [ I2 ++ ]; + R6.L = W [ I3 ++ ]; + R7.L = W [ I0 ++ ]; + R0.L = W [ I1 ++ ]; + R1.L = W [ I2 ++ ]; + R2.L = W [ I3 ++ ]; + CHECKREG r0, 0x00002C2D; + CHECKREG r1, 0x00004C4D; + CHECKREG r2, 0x00006C6D; + CHECKREG r3, 0x00000E0F; + CHECKREG r4, 0x00002E2F; + CHECKREG r5, 0x00004E4F; + CHECKREG r6, 0x00006E6F; + CHECKREG r7, 0x00000C0D; + +// reverse to minus mninus i-- + +// Load Lower half of Dregs + R0.L = W [ I0 -- ]; + R1.L = W [ I1 -- ]; + R2.L = W [ I2 -- ]; + R3.L = W [ I3 -- ]; + R4.L = W [ I0 -- ]; + R5.L = W [ I1 -- ]; + R6.L = W [ I2 -- ]; + R7.L = W [ I3 -- ]; + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00003233; + CHECKREG r2, 0x00005253; + CHECKREG r3, 0x00007273; + CHECKREG r4, 0x00000C0D; + CHECKREG r5, 0x00002C2D; + CHECKREG r6, 0x00004C4D; + CHECKREG r7, 0x00006C6D; + + R1.L = W [ I0 -- ]; + R2.L = W [ I1 -- ]; + R3.L = W [ I2 -- ]; + R4.L = W [ I3 -- ]; + R5.L = W [ I0 -- ]; + R6.L = W [ I1 -- ]; + R7.L = W [ I2 -- ]; + R0.L = W [ I3 -- ]; + CHECKREG r0, 0x00006869; + CHECKREG r1, 0x00000E0F; + CHECKREG r2, 0x00002E2F; + CHECKREG r3, 0x00004E4F; + CHECKREG r4, 0x00006E6F; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00002829; + CHECKREG r7, 0x00004849; + + R2.L = W [ I0 -- ]; + R3.L = W [ I1 -- ]; + R4.L = W [ I2 -- ]; + R5.L = W [ I3 -- ]; + R6.L = W [ I0 -- ]; + R7.L = W [ I1 -- ]; + R0.L = W [ I2 -- ]; + R1.L = W [ I3 -- ]; + CHECKREG r0, 0x00004445; + CHECKREG r1, 0x00006465; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00002A2B; + CHECKREG r4, 0x00004A4B; + CHECKREG r5, 0x00006A6B; + CHECKREG r6, 0x00000405; + CHECKREG r7, 0x00002425; + + R3.L = W [ I0 -- ]; + R4.L = W [ I1 -- ]; + R5.L = W [ I2 -- ]; + R6.L = W [ I3 -- ]; + R7.L = W [ I0 -- ]; + R0.L = W [ I1 -- ]; + R1.L = W [ I2 -- ]; + R2.L = W [ I3 -- ]; + CHECKREG r0, 0x00002021; + CHECKREG r1, 0x00004041; + CHECKREG r2, 0x00006061; + CHECKREG r3, 0x00000607; + CHECKREG r4, 0x00002627; + CHECKREG r5, 0x00004647; + CHECKREG r6, 0x00006667; + CHECKREG r7, 0x00000001; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xBC0DBE26 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_dr_i.s b/sim/testsuite/sim/bfin/c_dspldst_st_dr_i.s new file mode 100644 index 0000000..7434607 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_st_dr_i.s @@ -0,0 +1,185 @@ +//Original:/testcases/core/c_dspldst_st_dr_i/c_dspldst_st_dr_i.dsp +// Spec Reference: c_dspldst st_dr_i +# mach: bfin + +.include "testutils.inc" + start + + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + [ I0 ] = R0; + [ I1 ] = R1; + [ I2 ] = R2; + [ I3 ] = R3; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x0a234507; + CHECKREG r5, 0x1b345618; + CHECKREG r6, 0x2c456729; + CHECKREG r7, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + [ I0 ] = R1; + [ I1 ] = R2; + [ I2 ] = R3; + [ I3 ] = R4; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x1b345618; + CHECKREG r5, 0x2c456729; + CHECKREG r6, 0x3d56783a; + CHECKREG r7, 0x4e67894b; + + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + [ I0 ] = R2; + [ I1 ] = R3; + [ I2 ] = R4; + [ I3 ] = R5; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x2c456729; + CHECKREG r5, 0x3d56783a; + CHECKREG r6, 0x4e67894b; + CHECKREG r7, 0x5f789a5c; + + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + [ I0 ] = R3; + [ I1 ] = R4; + [ I2 ] = R5; + [ I3 ] = R6; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x3d56783a; + CHECKREG r5, 0x4e67894b; + CHECKREG r6, 0x5f789a5c; + CHECKREG r7, 0x6089ab6d; + + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + [ I0 ] = R4; + [ I1 ] = R5; + [ I2 ] = R6; + [ I3 ] = R7; + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + CHECKREG r0, 0x4e67894b; + CHECKREG r1, 0x5f789a5c; + CHECKREG r2, 0x6089ab6d; + CHECKREG r3, 0x719abc7e; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_dr_ipp.s b/sim/testsuite/sim/bfin/c_dspldst_st_dr_ipp.s new file mode 100644 index 0000000..87404a1 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_st_dr_ipp.s @@ -0,0 +1,326 @@ +//Original:testcases/core/c_dspldst_st_dr_ipp/c_dspldst_st_dr_ipp.dsp +// Spec Reference: c_dspldst st_dr_ipp +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +//INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + +// initial values + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + [ I0 ++ ] = R0; + [ I1 ++ ] = R1; + [ I2 ++ ] = R2; + [ I3 ++ ] = R3; + + [ I0 ++ ] = R1; + [ I1 ++ ] = R2; + [ I2 ++ ] = R3; + [ I3 ++ ] = R4; + + [ I0 ++ ] = R3; + [ I1 ++ ] = R4; + [ I2 ++ ] = R5; + [ I3 ++ ] = R6; + + [ I0 ++ ] = R4; + [ I1 ++ ] = R5; + [ I2 ++ ] = R6; + [ I3 ++ ] = R7; + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x0a234507; + CHECKREG r1, 0x1b345618; + CHECKREG r2, 0x2c456729; + CHECKREG r3, 0x3d56783a; + CHECKREG r4, 0x1B345618; + CHECKREG r5, 0x2C456729; + CHECKREG r6, 0x3D56783A; + CHECKREG r7, 0x4E67894B; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x3D56783A; + CHECKREG r1, 0x4E67894B; + CHECKREG r2, 0x5F789A5C; + CHECKREG r3, 0x6089AB6D; + CHECKREG r4, 0x4E67894B; + CHECKREG r5, 0x5F789A5C; + CHECKREG r6, 0x6089AB6D; + CHECKREG r7, 0x719ABC7E; + +// initial values + + imm32 r0, 0xa0b2c3d4; + imm32 r1, 0x1b245618; + imm32 r2, 0x22b36729; + imm32 r3, 0xbd3c483a; + imm32 r4, 0xde64d54b; + imm32 r5, 0x5f785e6c; + imm32 r6, 0x30896bf7; + imm32 r7, 0x719ab770; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + + [ I0 -- ] = R0; + [ I1 -- ] = R1; + [ I2 -- ] = R2; + [ I3 -- ] = R3; + [ I0 -- ] = R4; + [ I1 -- ] = R5; + [ I2 -- ] = R6; + [ I3 -- ] = R7; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0xA0B2C3D4; + CHECKREG r1, 0x1B245618; + CHECKREG r2, 0x22B36729; + CHECKREG r3, 0xBD3C483A; + CHECKREG r4, 0xDE64D54B; + CHECKREG r5, 0x5F785E6C; + CHECKREG r6, 0x30896BF7; + CHECKREG r7, 0x719AB770; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_dr_ippm.s b/sim/testsuite/sim/bfin/c_dspldst_st_dr_ippm.s new file mode 100644 index 0000000..9b08838 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_st_dr_ippm.s @@ -0,0 +1,279 @@ +//Original:/testcases/core/c_dspldst_st_dr_ippm/c_dspldst_st_dr_ippm.dsp +// Spec Reference: c_dspldst st_dr_ippm +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + M0 = 4 (X); + M1 = 0x4 (X); + M2 = 0x4 (X); + M3 = 0x4 (X); + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + [ I0 ++ M0 ] = R0; + [ I1 ++ M1 ] = R1; + [ I2 ++ M2 ] = R2; + [ I3 ++ M3 ] = R3; + [ I0 ++ M1 ] = R1; + [ I1 ++ M2 ] = R2; + [ I2 ++ M3 ] = R3; + [ I3 ++ M0 ] = R4; + + [ I0 ++ M2 ] = R3; + [ I1 ++ M3 ] = R4; + [ I2 ++ M0 ] = R5; + [ I3 ++ M1 ] = R6; + [ I0 ++ M3 ] = R4; + [ I1 ++ M0 ] = R5; + [ I2 ++ M1 ] = R6; + [ I3 ++ M2 ] = R7; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + R0 = [ I0 ++ M0 ]; + R1 = [ I1 ++ M1 ]; + R2 = [ I2 ++ M2 ]; + R3 = [ I3 ++ M3 ]; + R4 = [ I0 ++ M1 ]; + R5 = [ I1 ++ M2 ]; + R6 = [ I2 ++ M3 ]; + R7 = [ I3 ++ M0 ]; + CHECKREG r0, 0x0A234507; + CHECKREG r1, 0x1B345618; + CHECKREG r2, 0x2C456729; + CHECKREG r3, 0x3D56783A; + CHECKREG r4, 0x1B345618; + CHECKREG r5, 0x2C456729; + CHECKREG r6, 0x3D56783A; + CHECKREG r7, 0x4E67894B; + R0 = [ I0 ++ M2 ]; + R1 = [ I1 ++ M3 ]; + R2 = [ I2 ++ M0 ]; + R3 = [ I3 ++ M1 ]; + R4 = [ I0 ++ M3 ]; + R5 = [ I1 ++ M0 ]; + R6 = [ I2 ++ M1 ]; + R7 = [ I3 ++ M2 ]; + CHECKREG r0, 0x3D56783A; + CHECKREG r1, 0x4E67894B; + CHECKREG r2, 0x5F789A5C; + CHECKREG r3, 0x6089AB6D; + CHECKREG r4, 0x4E67894B; + CHECKREG r5, 0x5F789A5C; + CHECKREG r6, 0x6089AB6D; + CHECKREG r7, 0x719ABC7E; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_drhi_i.s b/sim/testsuite/sim/bfin/c_dspldst_st_drhi_i.s new file mode 100644 index 0000000..a5aefc8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_st_drhi_i.s @@ -0,0 +1,161 @@ +//Original:/testcases/core/c_dspldst_st_drhi_i/c_dspldst_st_drhi_i.dsp +// Spec Reference: c_dspldst st_drhi_i +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + W [ I0 ] = R0.H; + W [ I1 ] = R1.H; + W [ I2 ] = R2.H; + W [ I3 ] = R3.H; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x00010A23; + CHECKREG r5, 0x20211B34; + CHECKREG r6, 0x40412C45; + CHECKREG r7, 0x60613D56; + W [ I0 ] = R1.H; + W [ I1 ] = R2.H; + W [ I2 ] = R3.H; + W [ I3 ] = R4.H; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x00011B34; + CHECKREG r5, 0x20212C45; + CHECKREG r6, 0x40413D56; + CHECKREG r7, 0x60610001; + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + W [ I0 ] = R2.H; + W [ I1 ] = R3.H; + W [ I2 ] = R4.H; + W [ I3 ] = R5.H; + R0 = [ I0 ]; + R1 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r0, 0x00012C45; + CHECKREG r1, 0x20213D56; + CHECKREG r6, 0x40414E67; + CHECKREG r7, 0x60615F78; + + W [ I0 ] = R4.H; + W [ I1 ] = R5.H; + W [ I2 ] = R6.H; + W [ I3 ] = R7.H; + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + CHECKREG r0, 0x00014E67; + CHECKREG r1, 0x20215F78; + CHECKREG r6, 0x40414E67; + CHECKREG r7, 0x60615F78; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_drhi_ipp.s b/sim/testsuite/sim/bfin/c_dspldst_st_drhi_ipp.s new file mode 100644 index 0000000..4e25d9d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_st_drhi_ipp.s @@ -0,0 +1,355 @@ +//Original:testcases/core/c_dspldst_st_drhi_ipp/c_dspldst_st_drhi_ipp.dsp +// Spec Reference: c_dspldst st_drhi_ipp +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + +// Half reg 16 bit mem store + + imm32 r0, 0x0a123456; + imm32 r1, 0x11b12345; + imm32 r2, 0x222c1234; + imm32 r3, 0x3344d012; + imm32 r4, 0x5566e012; + imm32 r5, 0x789abf01; + imm32 r6, 0xabcd0123; + imm32 r7, 0x01234567; + +// initial values + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + W [ I0 ++ ] = R0.H; + W [ I1 ++ ] = R1.H; + W [ I2 ++ ] = R2.H; + W [ I3 ++ ] = R3.H; + W [ I0 ++ ] = R1.H; + W [ I1 ++ ] = R2.H; + W [ I2 ++ ] = R3.H; + W [ I3 ++ ] = R4.H; + + W [ I0 ++ ] = R3.H; + W [ I1 ++ ] = R4.H; + W [ I2 ++ ] = R5.H; + W [ I3 ++ ] = R6.H; + + W [ I0 ++ ] = R4.H; + W [ I1 ++ ] = R5.H; + W [ I2 ++ ] = R6.H; + W [ I3 ++ ] = R7.H; + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x11B10A12; + CHECKREG r1, 0x222C11B1; + CHECKREG r2, 0x3344222C; + CHECKREG r3, 0x55663344; + CHECKREG r4, 0x55663344; + CHECKREG r5, 0x789A5566; + CHECKREG r6, 0xABCD789A; + CHECKREG r7, 0x0123ABCD; + + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x28292A2B; + CHECKREG r2, 0x48494A4B; + CHECKREG r3, 0x68696A6B; + CHECKREG r4, 0x0C0D0E0F; + CHECKREG r5, 0x2C2D2E2F; + CHECKREG r6, 0x4C4D4E4F; + CHECKREG r7, 0x6C6D6E6F; + +// initial values + + imm32 r0, 0x01b2c3d4; + imm32 r1, 0x10145618; + imm32 r2, 0xa2016729; + imm32 r3, 0xbb30183a; + imm32 r4, 0xdec4014b; + imm32 r5, 0x5f7d501c; + imm32 r6, 0x3089eb01; + imm32 r7, 0x719abf70; + + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + + W [ I0 -- ] = R0.H; + W [ I1 -- ] = R1.H; + W [ I2 -- ] = R2.H; + W [ I3 -- ] = R3.H; + W [ I0 -- ] = R1.H; + W [ I1 -- ] = R2.H; + W [ I2 -- ] = R3.H; + W [ I3 -- ] = R4.H; + + W [ I0 -- ] = R3.H; + W [ I1 -- ] = R4.H; + W [ I2 -- ] = R5.H; + W [ I3 -- ] = R6.H; + W [ I0 -- ] = R4.H; + W [ I1 -- ] = R5.H; + W [ I2 -- ] = R6.H; + W [ I3 -- ] = R7.H; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0x000001B2; + CHECKREG r1, 0x00001014; + CHECKREG r2, 0x0000A201; + CHECKREG r3, 0x0000BB30; + CHECKREG r4, 0x1014BB30; + CHECKREG r5, 0xA201DEC4; + CHECKREG r6, 0xBB305F7D; + CHECKREG r7, 0xDEC43089; + + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0xDEC41A1B; + CHECKREG r1, 0x5F7D3A3B; + CHECKREG r2, 0x30895A5B; + CHECKREG r3, 0x719A7A7B; + CHECKREG r4, 0x14151617; + CHECKREG r5, 0x34353637; + CHECKREG r6, 0x54555657; + CHECKREG r7, 0x74757677; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_drlo_i.s b/sim/testsuite/sim/bfin/c_dspldst_st_drlo_i.s new file mode 100644 index 0000000..7b36691 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_st_drlo_i.s @@ -0,0 +1,163 @@ +//Original:/testcases/core/c_dspldst_st_drlo_i/c_dspldst_st_drlo_i.dsp +// Spec Reference: c_dspldst st_drlo_i +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a234507; + imm32 r1, 0x1b345618; + imm32 r2, 0x2c456729; + imm32 r3, 0x3d56783a; + imm32 r4, 0x4e67894b; + imm32 r5, 0x5f789a5c; + imm32 r6, 0x6089ab6d; + imm32 r7, 0x719abc7e; + + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + W [ I0 ] = R0.L; + W [ I1 ] = R1.L; + W [ I2 ] = R2.L; + W [ I3 ] = R3.L; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x00014507; + CHECKREG r5, 0x20215618; + CHECKREG r6, 0x40416729; + CHECKREG r7, 0x6061783A; + W [ I0 ] = R3.L; + W [ I1 ] = R2.L; + W [ I2 ] = R1.L; + W [ I3 ] = R0.L; + R4 = [ I0 ]; + R5 = [ I1 ]; + R6 = [ I2 ]; + R7 = [ I3 ]; + CHECKREG r4, 0x0001783A; + CHECKREG r5, 0x20216729; + CHECKREG r6, 0x40415618; + CHECKREG r7, 0x60614507; + + imm32 r0, 0x1a334507; + imm32 r1, 0x12345618; + imm32 r2, 0x2c3e6729; + imm32 r3, 0x3d54f83a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f789c5c; + imm32 r6, 0x6089ad7d; + imm32 r7, 0x739abc88; + + W [ I0 ] = R4.L; + W [ I1 ] = R5.L; + W [ I2 ] = R6.L; + W [ I3 ] = R7.L; + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + CHECKREG r0, 0x0001594B; + CHECKREG r1, 0x20219C5C; + CHECKREG r2, 0x4041AD7D; + CHECKREG r3, 0x6061BC88; + + W [ I0 ] = R7.L; + W [ I1 ] = R6.L; + W [ I2 ] = R5.L; + W [ I3 ] = R4.L; + R0 = [ I0 ]; + R1 = [ I1 ]; + R2 = [ I2 ]; + R3 = [ I3 ]; + CHECKREG r0, 0x0001BC88; + CHECKREG r1, 0x2021AD7D; + CHECKREG r2, 0x40419C5C; + CHECKREG r3, 0x6061594B; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_drlo_ipp.s b/sim/testsuite/sim/bfin/c_dspldst_st_drlo_ipp.s new file mode 100644 index 0000000..08483e3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_dspldst_st_drlo_ipp.s @@ -0,0 +1,351 @@ +//Original:testcases/core/c_dspldst_st_drlo_ipp/c_dspldst_st_drlo_ipp.dsp +// Spec Reference: c_dspldst st_drlo_ipp +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + +// Half reg 16 bit mem store + + imm32 r0, 0x0a123456; + imm32 r1, 0x11b12345; + imm32 r2, 0x222c1234; + imm32 r3, 0x3344d012; + imm32 r4, 0x5566e012; + imm32 r5, 0x789abf01; + imm32 r6, 0xabcd0123; + imm32 r7, 0x01234567; + +// initial values + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + + W [ I0 ++ ] = R0.L; + W [ I1 ++ ] = R1.L; + W [ I2 ++ ] = R2.L; + W [ I3 ++ ] = R3.L; + W [ I0 ++ ] = R1.L; + W [ I1 ++ ] = R2.L; + W [ I2 ++ ] = R3.L; + W [ I3 ++ ] = R4.L; + + W [ I0 ++ ] = R3.L; + W [ I1 ++ ] = R4.L; + W [ I2 ++ ] = R5.L; + W [ I3 ++ ] = R6.L; + W [ I0 ++ ] = R4.L; + W [ I1 ++ ] = R5.L; + W [ I2 ++ ] = R6.L; + W [ I3 ++ ] = R7.L; + loadsym i0, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym i2, DATA_ADDR_5; + loadsym i3, DATA_ADDR_6; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x23453456; + CHECKREG r1, 0x12342345; + CHECKREG r2, 0xD0121234; + CHECKREG r3, 0xE012D012; + CHECKREG r4, 0xE012D012; + CHECKREG r5, 0xBF01E012; + CHECKREG r6, 0x0123BF01; + CHECKREG r7, 0x45670123; + + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + R2 = [ I2 ++ ]; + R3 = [ I3 ++ ]; + R4 = [ I0 ++ ]; + R5 = [ I1 ++ ]; + R6 = [ I2 ++ ]; + R7 = [ I3 ++ ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x28292A2B; + CHECKREG r2, 0x48494A4B; + CHECKREG r3, 0x68696A6B; + CHECKREG r4, 0x0C0D0E0F; + CHECKREG r5, 0x2C2D2E2F; + CHECKREG r6, 0x4C4D4E4F; + CHECKREG r7, 0x6C6D6E6F; + +// initial values + + imm32 r0, 0x01b2c3d4; + imm32 r1, 0x10145618; + imm32 r2, 0xa2016729; + imm32 r3, 0xbb30183a; + imm32 r4, 0xdec4014b; + imm32 r5, 0x5f7d501c; + imm32 r6, 0x3089eb01; + imm32 r7, 0x719abf70; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + + W [ I0 -- ] = R0.L; + W [ I1 -- ] = R1.L; + W [ I2 -- ] = R2.L; + W [ I3 -- ] = R3.L; + W [ I0 -- ] = R1.L; + W [ I1 -- ] = R2.L; + W [ I2 -- ] = R3.L; + W [ I3 -- ] = R4.L; + + W [ I0 -- ] = R3.L; + W [ I1 -- ] = R4.L; + W [ I2 -- ] = R5.L; + W [ I3 -- ] = R6.L; + W [ I0 -- ] = R4.L; + W [ I1 -- ] = R5.L; + W [ I2 -- ] = R6.L; + W [ I3 -- ] = R7.L; + loadsym i0, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym i2, DATA_ADDR_5, 0x20; + loadsym i3, DATA_ADDR_6, 0x20; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0x0000C3D4; + CHECKREG r1, 0x00005618; + CHECKREG r2, 0x00006729; + CHECKREG r3, 0x0000183A; + CHECKREG r4, 0x5618183A; + CHECKREG r5, 0x6729014B; + CHECKREG r6, 0x183A501C; + CHECKREG r7, 0x014BEB01; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; + R2 = [ I2 -- ]; + R3 = [ I3 -- ]; + R4 = [ I0 -- ]; + R5 = [ I1 -- ]; + R6 = [ I2 -- ]; + R7 = [ I3 -- ]; + CHECKREG r0, 0x014B1A1B; + CHECKREG r1, 0x501C3A3B; + CHECKREG r2, 0xEB015A5B; + CHECKREG r3, 0xBF707A7B; + CHECKREG r4, 0x14151617; + CHECKREG r5, 0x34353637; + CHECKREG r6, 0x54555657; + CHECKREG r7, 0x74757677; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_3: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_8: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_except_illopcode.S b/sim/testsuite/sim/bfin/c_except_illopcode.S new file mode 100644 index 0000000..bf6c66d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_except_illopcode.S @@ -0,0 +1,99 @@ +//Original:/proj/frio/dv/testcases/core/c_except_illopcode/c_except_illopcode.dsp +// Spec Reference: c_exception illegal opcode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +// load address of exception handler + +P0 = 0x200C (Z); // 0xFFE0200C EVT3 EXCEPTION +P0.H = 0xFFE0; +R0 = exception_handler (Z); // wr address of exception handler to MMR EVT3 +R0.H = exception_handler; +[ P0 ] = R0; + +// Jump to User mode and enable exceptions + +R0 = MidUserCode (Z); +R0.H = MidUserCode; +RETI = R0; +RTI; // cause it to go to Midusercode, .dd cause exception + +BeginUserCode: +P1 = 1; +P2 = 2; +P3 = 3; +P4 = 4; + +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000001); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000003); +// CHECKREG(r4, 0x00000098); +CHECKREG(r5, 0x00000005); +CHECKREG(r6, 0x00000006); +CHECKREG(r7, 0x00000007); +CHECKREG(p1, 0x00000001); +CHECKREG(p2, 0x00000002); +CHECKREG(p3, 0x00000003); +CHECKREG(p4, 0x00000004); + +dbg_pass; +//jump 2; +//jump -2; +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF + +//dbg_pass; + +MidUserCode: +.dd 0xFFFFFFFF +R0 = 0; +R1 = 1; +R2 = 2; +R3 = 3; +CC = R0; +IF !CC JUMP BeginUserCode; + +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF + +//.code 0x800 + +exception_handler: +R4 = RETX; // error handler: RETX has the address of the same Illegal instr +R5 = 5; +R6 = 6; +R7 = 7; +R4 += 4; // we have to add 4 to point to next instr after return +RETX = R4; + +RTX; // return from exception + //nop; + +.section MEM_DATA_ADDR_1,"aw" +.dd 0xDEADBEEF +.dd 0xBAD00BAD diff --git a/sim/testsuite/sim/bfin/c_except_sys_sstep.S b/sim/testsuite/sim/bfin/c_except_sys_sstep.S new file mode 100644 index 0000000..c719555 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_except_sys_sstep.S @@ -0,0 +1,252 @@ +//Original:/proj/frio/dv/testcases/core/c_except_sys_sstep/c_except_sys_sstep.dsp +// Spec Reference: Single Step Supervisor Exception Test (NO REGTRACE!) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +// CHECK_INIT(p2, 0x2000); +include(symtable.inc) +CHECK_INIT_DEF(p2); + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + R0 = 1; +SYSCFG = r0; // Enable Supervisor Single Step + R4 = 0; + +LD32_LABEL(r0, START); +RETI = r0; // We need to load the return address + +RTI; + + +START: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + R0 = 0; + R1 = 1; + R2 = 2; + R3 = 3; + R5 = 5; + R6 = 6; + R7 = 7; + +EXCPT 3; // turn off single step via handler + +CHECKREG(r4, 0x0b); // 11 instrs are executed before single step = disabled +CHECKREG(r0, 0x00); +CHECKREG(r1, 0x03); +CHECKREG(r2, 0x10); +CHECKREG(r3, 0x04); +CHECKREG(r5, 0x09); +CHECKREG(r6, 0x06); +CHECKREG(r7, 0x07); + + + // PUT YOUR TEST HERE! + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + [ -- SP ] = ASTAT; // save ASTAT + R1 = SEQSTAT; + R1 <<= 26; + R1 >>= 26; // only want EXCAUSE + R2 = 0x10; // EXCAUSE 0x10 means Single Step (exception) +CC = r1 == r2; +IF CC JUMP SSCOUNT; // Go to Single Step Handler + +SYSCFG = r0; // otherwise must be an EXCPT, so turn off singlestep + R3 += 1; + +JUMP.S EXIT; + +SSCOUNT: + R4 += 1; // R4 counts single step events + +EXIT: +ASTAT = [sp++]; + R5 += 1; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_except_user_mode.S b/sim/testsuite/sim/bfin/c_except_user_mode.S new file mode 100644 index 0000000..8c71bd7 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_except_user_mode.S @@ -0,0 +1,349 @@ +//Original:/proj/frio/dv/testcases/core/c_except_user_mode/c_except_user_mode.dsp +// Spec Reference: except_mode_user +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; // execute this instr put us in USER mode + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // USER MODE & go to different RAISE in USER mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +RAISE 2; // RTN // exception because we execute this in USER mode +RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; + + +CHECKREG(r0, 0x00000018); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x00000000); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = RETN; + R0 += 2; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +RETN = r0; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = RETX; + I0 += 2; + R1 += 2; // for return address +RETX = r1; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = RETI; + R2 += 2; + I0 += 2; + I1 += 2; +RETI = r2; +RTI; + +THANDLE: // Timer Handler 6 + R3 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + R3 += 2; +RETI = r3; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = RETI; + I0 += 2; + I1 += 2; + I3 += 2; + R4 += 2; +RETI = r4; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R5 += 2; +RETI = r5; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R6 += 2; +RETI = r6; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R7 += 2; +RETI = r7; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = RETI; + R0 += 2; + M0 = I0; + M1 = I1; + M2 = I2; + M3 = I3; +RETI = r0; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R1 += 2; +RETI = r1; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R2 += 2; +RETI = r2; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R3 += 2; +RETI = r3; +RTI; + +I15HANDLE: // IVG 15 Handler + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; +RTI; + +// nop;nop;nop;nop;nop;nop;nop; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: +// .space (STACKSIZE); // adding this may solve the problem diff --git a/sim/testsuite/sim/bfin/c_interr_disable.S b/sim/testsuite/sim/bfin/c_interr_disable.S new file mode 100644 index 0000000..5a64623 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_interr_disable.S @@ -0,0 +1,323 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_disable/c_interr_disable.dsp +// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0x00BFFFFC); + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +//.code 0x200 + START : + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +CLI R1; // stop interrupt +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000050, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000000, p0, r0); +CSYNC; + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000050); + +// RD_MMR(TCOUNT, p0, r3); +// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + +RD_MMR(TPERIOD, p0, r4); +CHECKREG(r4, 0x00000050); + +// RD_MMR(TCNTL, p0, r5); +// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000015, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000002, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) +CSYNC; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label4; + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label5: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label6; + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +label4: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +JUMP.S label5; + R5.L = 0x2222; // Will be killed + R5.H = 0x2222; // Will be killed +NOP; +NOP; +NOP; +NOP; +label6: R3.H = 0x7999; + R3.L = 0x7aaa; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + // With auto reload + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000015); + +// RD_MMR(TCNTL , p0, r3); +// CHECKREG(r3, 0x0000000F); +CHECKREG(r7, 0x00000000); // no interrupt being serviced +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +STI R1; +NOP; +CHECKREG(r7, 0x00000001); // interrupt being serviced +// WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +// csync; +NOP; + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_DATA_ADDR_1,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_interr_disable_enable.S b/sim/testsuite/sim/bfin/c_interr_disable_enable.S new file mode 100644 index 0000000..ac28cdb --- /dev/null +++ b/sim/testsuite/sim/bfin/c_interr_disable_enable.S @@ -0,0 +1,344 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_disable_enable/c_interr_disable_enable.dsp +// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0x00BFFFFC); + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + // LD32(sp, 0x000FF200); +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +//.code 0x200 + START : + P1 = 0; + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +CLI R1; // stop interrupt +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000050, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000000, p0, r0); +CSYNC; + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000050); + +// RD_MMR(TCOUNT, p0, r3); +// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + +RD_MMR(TPERIOD, p0, r4); +CHECKREG(r4, 0x00000050); + +// RD_MMR(TCNTL, p0, r5); +// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000015, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000002, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) +CSYNC; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label4; + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label5: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label6; + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +label4: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +JUMP.S label5; + R5.L = 0x2222; // Will be killed + R5.H = 0x2222; // Will be killed +NOP; +NOP; +NOP; +NOP; +label6: R3.H = 0x7999; + R3.L = 0x7aaa; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + // With auto reload + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000015); + +// RD_MMR(TCNTL , p0, r3); +// CHECKREG(r3, 0x0000000F); +CHECKREG(r7, 0x00000000); // no interrupt being serviced +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +STI R1; +NOP; +CHECKREG(r7, 0x00000001); // interrupt being serviced +WR_MMR(TCOUNT, 0x00000005, p0, r0); +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +CHECKREG(r7, 0x00000002); // interrupt being serviced +RAISE 7; +NOP; NOP; +CHECKREG(p1, 0x00000001); // interrupt being serviced + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// +//.code ITABLE + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler + P1 += 1; +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.data + +.space (STACKSIZE); +KSTACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_interr_excpt.S b/sim/testsuite/sim/bfin/c_interr_excpt.S new file mode 100644 index 0000000..911a78e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_interr_excpt.S @@ -0,0 +1,290 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_excpt/c_interr_excpt.dsp +// Spec Reference: interr excpt +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = 4; + + +EXCPT 1; // RTX +EXCPT 2; // RTX +EXCPT 3; // RTX +EXCPT 4; // RTX +EXCPT 5; // RTX +EXCPT 5; // RTX +EXCPT 6; // RTX +EXCPT 7; // RTX +EXCPT 8; // RTX +EXCPT 9; // RTX +EXCPT 10; // RTX +EXCPT 11; // RTX +EXCPT 12; // RTX +EXCPT 13; // RTX +EXCPT 14; // RTX +EXCPT 15; // RTX + +CHECKREG(r0, 0x33333333); +CHECKREG(r1, 0xCCCCCCCD); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x33333333); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x00000000); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + R0 = R1 + R2; + R1 = R2 + R3; + R2 = R0 + R1; + R3 = R0 + R2; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +//.data 0xF0000000 +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_interr_loopsetup_stld.S b/sim/testsuite/sim/bfin/c_interr_loopsetup_stld.S new file mode 100644 index 0000000..824b53e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_interr_loopsetup_stld.S @@ -0,0 +1,224 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_loopsetup_stld/c_interr_loopsetup_stld.dsp +// Spec Reference: interrupt loopsetup_ldst +# mach: bfin + +#include "test.h" +.include "testutils.inc" +start + + A0 = 0; // reset accumulators + A1 = 0; + +P1 = 3; +P2 = 4; + +LD32(r0, 0x00200005); +LD32(r1, 0x00300010); +LD32(r2, 0x00500012); +LD32(r3, 0x00600024); +LD32(r4, 0x00700016); +LD32(r5, 0x00900028); +LD32(r6, 0x0a000030); +LD32(r7, 0x00b00044); + +loadsym I0, DATA0; +loadsym I1, DATA1; +R0 = [ I0 ++ ]; +R1 = [ I1 ++ ]; +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += 2; + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; // dsp32mac dual + // a1 += h*h, a0 += l*l (r0,r1) ; r0 = [i0++]; r1 = [i1++]; // dsp32mac + R2 = ( R2 + R5 ) << 1; // alu2op +DIVQ ( R5 , R3 ); + R1 <<= R5; + R1 >>>= R1; + R6 = ~ R0; + //MY_GEN_INT(10, 1) +DIVQ ( R5 , R2 ); + R0 = R3.B (X); +DIVS ( R7 , R0 ); +end1: R2 += 3; + R3 = ( A0 += A1 ); +CHECKREG(r0, 0x00000024); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x0670098D); +CHECKREG(r3, 0x000015EC); +CHECKREG(r4, 0x00700016); +CHECKREG(r5, 0x0B240A39); +CHECKREG(r6, 0xFFF2FFFC); +CHECKREG(r7, 0x05800220); + +A0 = 0; +A1 = 0; +LSETUP ( start2 , end2 ) LC0 = P2; +start2: R4 += 4; + //a1 += h*h, a0 += l*l (r0,r1), r0 = [i0--], r1 = [i1--]; + A1 += R0.H * R1.H, A0 += R0.L * R1.L; R0 = [ I0 -- ]; R1 = [ I1 -- ]; + R1 <<= R5; + R6 = R7.B (Z); + R2 = - R6; + R3 = R4.L (Z); +DIVS ( R1 , R1 ); + R6 = - R0; + R0 >>= R0; +DIVS ( R4 , R7 ); + //MY_GEN_INT(13, 1) + R1 = R2.L (Z); +end2: R5 += -5; + R6 = ( A0 += A1 ); +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x0000FFE0); +CHECKREG(r2, 0xFFFFFFE0); +CHECKREG(r3, 0x000000EC); +CHECKREG(r4, 0x070001D8); +CHECKREG(r5, 0x0B240A25); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x05800220); +LD32(r0, 0x01200805); +LD32(r1, 0x02300710); +LD32(r2, 0x03500612); +LD32(r3, 0x04600524); +LD32(r4, 0x05700416); +LD32(r5, 0x06900328); +LD32(r6, 0x0a700230); +LD32(r7, 0x08b00044); + +loadsym I2, DATA0; +loadsym I3, DATA1; +[ I2 ++ ] = R0; +[ I3 ++ ] = R1; +LSETUP ( start3 , end3 ) LC0 = P1; +start3: + [ I2 ++ ] = R2; + [ I3 ++ ] = R3; + R2 += 1; +end3: + R3 += 1; + +A0 = 0; +A1 = 0; +LSETUP ( start4 , end4 ) LC0 = P2; +R0 = [ I0 -- ]; +R1 = [ I1 -- ]; +start4: + // a1 += h*h, a0 += l*l (r0,r1), r0 = [i2--], r1 = [i3--]; + A1 += R0.H * R1.H, A0 += R0.L * R1.L; R0 = [ I2 -- ]; R1 = [ I3 -- ]; + R4 = R4 + R0; // comp3op + R5 = R7.L (Z); + R4 >>>= R5; + R0 = R7.B (X); +DIVQ ( R6 , R6 ); + //MY_GEN_INT(7, 1) +end4: R5 = R5 + R1; + R6 = ( A0 += A1 ); + R7 = ( A0 += A1 ); +CHECKREG(r0, 0x00000044); +CHECKREG(r1, 0x04600524); +CHECKREG(r2, 0x03500615); +CHECKREG(r3, 0x04600527); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x04600568); +CHECKREG(r6, 0x007C3498); +CHECKREG(r7, 0x00812098); + + +pass; // End the test + +// +// Data Segment +// + + + +.data + +DATA0: +.dd 0x000a0000 +.dd 0x000b0001 +.dd 0x000c0002 +.dd 0x000d0003 +.dd 0x000e0004 +.dd 0x000f0005 +.dd 0x00100006 +.dd 0x00200007 +.dd 0x00300008 +.dd 0x00400009 +.dd 0x0050000a +.dd 0x0060000b +.dd 0x0070000c +.dd 0x0080000d +.dd 0x0090000e +.dd 0x0100000f +.dd 0x02000010 +.dd 0x03000011 +.dd 0x04000012 +.dd 0x05000013 +.dd 0x06000014 +.dd 0x001a0000 +.dd 0x001b0001 +.dd 0x001c0002 +.dd 0x001d0003 +.dd 0x00010004 +.dd 0x00010005 +.dd 0x02100006 +.dd 0x02200007 +.dd 0x02300008 +.dd 0x02200009 +.dd 0x0250000a +.dd 0x0260000b +.dd 0x0270000c +.dd 0x0280000d +.dd 0x0290000e +.dd 0x2100000f +.dd 0x22000010 +.dd 0x22000011 +.dd 0x24000012 +.dd 0x25000013 +.dd 0x26000014 + +DATA1: +.dd 0x00f00100 +.dd 0x00e00101 +.dd 0x00d00102 +.dd 0x00c00103 +.dd 0x00b00104 +.dd 0x00a00105 +.dd 0x00900106 +.dd 0x00800107 +.dd 0x00100108 +.dd 0x00200109 +.dd 0x0030010a +.dd 0x0040010b +.dd 0x0050011c +.dd 0x0060010d +.dd 0x0070010e +.dd 0x0080010f +.dd 0x00900110 +.dd 0x01000111 +.dd 0x02000112 +.dd 0x03000113 +.dd 0x04000114 +.dd 0x05000115 +.dd 0x03f00100 +.dd 0x03e00101 +.dd 0x03d00102 +.dd 0x03c00103 +.dd 0x03b00104 +.dd 0x03a00105 +.dd 0x03900106 +.dd 0x03800107 +.dd 0x03100108 +.dd 0x03200109 +.dd 0x0330010a +.dd 0x0330010b +.dd 0x0350011c +.dd 0x0360010d +.dd 0x0370010e +.dd 0x0380010f +.dd 0x03900110 +.dd 0x31000111 +.dd 0x32000112 +.dd 0x33000113 +.dd 0x34000114 diff --git a/sim/testsuite/sim/bfin/c_interr_nested.S b/sim/testsuite/sim/bfin/c_interr_nested.S new file mode 100644 index 0000000..55af970 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_interr_nested.S @@ -0,0 +1,289 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_nested/c_interr_nested.dsp +// Spec Reference: interrupt nested using raises +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +RAISE 2; // RTN +// RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +// RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +// RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI +RAISE 15; // RTI + +CHECKREG(r0, 0x0000000B); +CHECKREG(r1, 0x0000000C); +CHECKREG(r2, 0x0000000D); +CHECKREG(r3, 0x0000000E); +CHECKREG(r4, 0x00000007); +CHECKREG(r5, 0x00000008); +CHECKREG(r6, 0x00000009); +CHECKREG(r7, 0x0000000A); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +CHECKREG(r0, 0x00000002); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000005); +CHECKREG(r3, 0x00000006); +CHECKREG(r4, 0x00000007); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RAISE 5; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RAISE 8; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RAISE 12; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_interr_nmi.S b/sim/testsuite/sim/bfin/c_interr_nmi.S new file mode 100644 index 0000000..5124494 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_interr_nmi.S @@ -0,0 +1,318 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_nmi/c_interr_nmi.dsp +// Spec Reference: progctrl raise rti rtn +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +R0 = 0; +R1 = 0; +R2 = 0; +R3 = 0; +R4 = 0; +R5 = 0; +R6 = 0; +R7 = 0; + +RAISE 2; // RTN +RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI +RAISE 15; // RTI + +CHECKREG(r0, 0x0000000B); +CHECKREG(r1, 0x0000001A); +CHECKREG(r2, 0x00000024); +CHECKREG(r3, 0x00000028); +CHECKREG(r4, 0x0000000E); +CHECKREG(r5, 0x00000010); +CHECKREG(r6, 0x00000012); +CHECKREG(r7, 0x00000014); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +CHECKREG(r0, 0x0000000B); +CHECKREG(r1, 0x0000000E); +CHECKREG(r2, 0x00000017); +CHECKREG(r3, 0x0000001A); +CHECKREG(r4, 0x0000000E); + +( R7:0 ) = [ SP ++ ]; // pop + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x00000000); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x00000000); +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 += 1; + R1 += 2; +RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI +RAISE 15; // RTI + [ -- SP ] = ( R7:0 ); // push +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 += 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 += 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 += 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 += 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 += 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 += 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 += 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 += 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 += 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 += 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_interr_pending.S b/sim/testsuite/sim/bfin/c_interr_pending.S new file mode 100644 index 0000000..96b5a96 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_interr_pending.S @@ -0,0 +1,324 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_pending/c_interr_pending.dsp +// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0x00BFFFFC); + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +//.code 0x200 + START : + P1 = 0x0; + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +CLI R1; // stop interrupt +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000050, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000000, p0, r0); +CSYNC; + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000050); + +// RD_MMR(TCOUNT, p0, r3); +// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + +RD_MMR(TPERIOD, p0, r4); +CHECKREG(r4, 0x00000050); + +// RD_MMR(TCNTL, p0, r5); +// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000015, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000002, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) +CSYNC; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label4; + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label5: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label6; + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +label4: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +JUMP.S label5; + R5.L = 0x2222; // Will be killed + R5.H = 0x2222; // Will be killed +NOP; +NOP; +NOP; +NOP; +label6: R3.H = 0x7999; + R3.L = 0x7aaa; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + // With auto reload + // Read the contents of the Timer +RAISE 7; +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000015); + +CHECKREG(p1, 0x00000000); // no interrupt being serviced +CHECKREG(r7, 0x00000000); // no interrupt being serviced +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +STI R1; +NOP; NOP; NOP; +CHECKREG(r7, 0x00000001); // interrupt being serviced +CHECKREG(p1, 0x00000001); // interrupt being serviced +NOP; + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// +//.code ITABLE + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler + P1 += 1; + +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_DATA_ADDR_1,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_interr_pending_2.S b/sim/testsuite/sim/bfin/c_interr_pending_2.S new file mode 100644 index 0000000..2f1cf6c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_interr_pending_2.S @@ -0,0 +1,268 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_pending_2/c_interr_pending_2.dsp +// Spec Reference: interr pending (raise) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +// + +////MY_GEN_INT_INIT(0x000f0000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + //CHECK_INIT(p5, 0x00002000); +include(symtable.inc) +CHECK_INIT_DEF(p0); + + +LD32(r0, 0x8b235625); +LD32(r1, 0x93ba5127); +LD32(r2, 0xa3446725); +LD32(r3, 0x00050027); +LD32(r4, 0xb0ab6d29); +LD32(r5, 0x10ace72b); +LD32(r6, 0xc00c008d); +LD32(r7, 0xd2467029); +R4.H = R0.L * R1.L, R4.L = R0.L * R1.L; +CLI R0; +R5.H = R2.H * R3.L, R5.L = R2.L * R3.H; +RAISE 8; +RAISE 9; +CHECKREG(r4, 0x369E369E); +CHECKREG(r5, 0xFFE40004); +SSYNC; +STI R0; +R6.H = R1.L * R2.L, R6.L = R1.H * R2.L; +R7.H = R1.L * R3.H, R7.L = R1.H * R3.H; + +CHECKREG(r4, 0x369E369F); +CHECKREG(r5, 0xFFE40005); +CHECKREG(r6, 0x4165A8C0); +CHECKREG(r7, 0x0003FFFC); + + + +END: +dbg_pass; // End the test + +//********************************************************************* +// +// Handlers for Events +// +//.code 0x000f0000 + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler + R4 += 1; +RTI; + +I9HANDLE: // IVG 9 Handler + R5 += 1; +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" + +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_interr_timer.S b/sim/testsuite/sim/bfin/c_interr_timer.S new file mode 100644 index 0000000..181213e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_interr_timer.S @@ -0,0 +1,384 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_timer/c_interr_timer.dsp +// Spec Reference: interrupt on HW TIMER +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +//.code 0x200 + START : + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR(0) (active state) +WR_MMR(TPERIOD, 0x00000050, p0, r0); + // WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TCOUNT, 0x00000000, p0, r0); +WR_MMR(TSCALE, 0x00000000, p0, r0); +CSYNC; + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000050); + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR(0), TMREN(1)) +CSYNC; // TIMER interrupt + +RD_MMR(TCOUNT, p0, r3); +CSYNC; +CHECKREG(r3, 0x00000000); +CHECKREG(r7, 0x00000001); +WR_MMR(TCNTL, 0x00000001, p0, r0); // enable Timer (TMPWR(0), TMREN(1)=0) +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR(0), TMREN(1)) +CSYNC; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +RD_MMR(TCOUNT, p0, r4); +CHECKREG(r4, 0x00000000); + +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000B); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Power, EN -> interr +CSYNC; +CHECKREG(r7, 0x00000003); // 3 interr already happened + R7 = 0; // reset r7 +WR_MMR(TPERIOD, 0x00000040, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000002, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auto load +CSYNC; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label4; + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label5: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label6; + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +label4: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +JUMP.S label5; + R5.L = 0x2222; // Will be killed + R5.H = 0x2222; // Will be killed +NOP; +NOP; +NOP; +NOP; +label6: R3.H = 0x7999; + R3.L = 0x7aaa; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + // With auto reload + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000040); + +// CHECKREG(r7, 0x00000002); +CC = R7 == 0; +IF !CC JUMP LABEL1; +WR_MMR(TPERIOD, 0x00000030, p0, r0); // SHOULD NOT EXECUTE + +LABEL1: + +NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; + + +RD_MMR(TCNTL , p0, r3); +CHECKREG(r3, 0x0000000F); + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer +CSYNC; +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000040); + + +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; +RD_MMR(TCOUNT, p0, r4); +CHECKREG(r4, 0x00000000); + +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000B); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; NOP; NOP; + +WR_MMR(TPERIOD, 0x00000060, p0, r0); +CSYNC; +NOP; +RD_MMR(TPERIOD, p0, r6); +CHECKREG(r6, 0x00000060); + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_DATA_ADDR_1,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_interr_timer_reload.S b/sim/testsuite/sim/bfin/c_interr_timer_reload.S new file mode 100644 index 0000000..d84e5f5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_interr_timer_reload.S @@ -0,0 +1,286 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_timer_reload/c_interr_timer_reload.dsp +// Spec Reference: interrupt on HW TIMER auto-reload +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0x00BFFFFC); + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; + +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; + +//.code 0x200 + START : + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000020, p0, r0); +WR_MMR(TCOUNT, 0x00000002, p0, r0); +WR_MMR(TSCALE, 0x00000005, p0, r0); +CSYNC; + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000020); + +RD_MMR(TCOUNT, p0, r3); +CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + + + +NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; + +RD_MMR(TCOUNT, p0, r4); +CHECKREG(r4, 0x00000000); + +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000B); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +CHECKREG(r7, 0x00000001); + R7 = 0; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000020, p0, r0); +WR_MMR(TCOUNT, 0x00000003, p0, r0); +WR_MMR(TSCALE, 0x00000002, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auo-reload +CSYNC; +NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; + // With auto reload + // Read the contents of the Timer + +// CHECKREG(r7, 0x00000002); +CC = R7 == 0; +IF !CC JUMP LABEL1; +WR_MMR(TPERIOD, 0x00000030, p0, r0); // SHOULD NOT EXECUTE + +LABEL1: + + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000020); + +RD_MMR(TCNTL , p0, r3); +CHECKREG(r3, 0x0000000F); + +WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer but not auto-reload +CSYNC; + +NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; +RD_MMR(TCOUNT, p0, r4); +CHECKREG(r4, 0x00000000); + +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000B); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; NOP; NOP; + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_DATA_ADDR_1,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_interr_timer_tcount.S b/sim/testsuite/sim/bfin/c_interr_timer_tcount.S new file mode 100644 index 0000000..cc8fddc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_interr_timer_tcount.S @@ -0,0 +1,242 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_timer_tcount/c_interr_timer_tcount.dsp +// Spec Reference: interrupt on HW TIMER tcount +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0x00BFFFFC); + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; + +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; + +//.code 0x200 + START : + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000010, p0, r0); +WR_MMR(TCOUNT, 0x00000002, p0, r0); +WR_MMR(TSCALE, 0x00000001, p0, r0); +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + + +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000B); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +CHECKREG(r7, 0x00000001); + R7 = 0; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000010, p0, r0); +WR_MMR(TCOUNT, 0x00000002, p0, r0); +WR_MMR(TSCALE, 0x00000003, p0, r0); +WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer +CSYNC; +NOP; +NOP; + // Read the contents of the Timer + + +RD_MMR(TCNTL , p0, r3); +CHECKREG(r3, 0x0000000B); + +CHECKREG(r7, 0x00000001); + + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; NOP; NOP; + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_DATA_ADDR_1,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_interr_timer_tscale.S b/sim/testsuite/sim/bfin/c_interr_timer_tscale.S new file mode 100644 index 0000000..f8a87ac --- /dev/null +++ b/sim/testsuite/sim/bfin/c_interr_timer_tscale.S @@ -0,0 +1,304 @@ +//Original:/proj/frio/dv/testcases/core/c_interr_timer_tscale/c_interr_timer_tscale.dsp +// Spec Reference: interrupt on HW TIMER tscale +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + // CHECK_INIT(p5, 0x00BFFFFC); + // CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; + +//.code 0x200 + START : + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000010, p0, r0); +WR_MMR(TCOUNT, 0x00000002, p0, r0); +WR_MMR(TSCALE, 0x00000001, p0, r0); +CSYNC; + // Read the contents of the Timer +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000010); + +RD_MMR(TCOUNT, p0, r3); +CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace -seed 8b8db910 + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + +RD_MMR(TCOUNT, p0, r4); +CHECKREG(r4, 0x00000000); + +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000B); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +CHECKREG(r7, 0x00000001); + R7 = 0; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000010, p0, r0); +WR_MMR(TCOUNT, 0x00000003, p0, r0); +WR_MMR(TSCALE, 0x00000128, p0, r0); +WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer +CSYNC; +NOP; +NOP; +label5: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label6; + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +label4: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +JUMP.S label5; + R5.L = 0x2222; // Will be killed + R5.H = 0x2222; // Will be killed +NOP; +label6: R3.H = 0x7999; + R3.L = 0x7aaa; +NOP; + // With auto reload + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000010); + +RD_MMR(TCNTL , p0, r3); +CHECKREG(r3, 0x0000000b); + +CHECKREG(r7, 0x00000001); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn ON Timer auto-reload +WR_MMR(TPERIOD, 0x00000020, p0, r0); +WR_MMR(TSCALE, 0x00000003, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auto-reload + +NOP; NOP; + R7 = 0; +CSYNC; + +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; +NOP; NOP; NOP; NOP; NOP; NOP; + R1 = 1; + R2 = 1; + R3 = 2; +RD_MMR(TCNTL, p0, r5); +CHECKREG(r5, 0x0000000F); +CC = R1 < R7; +IF CC R2 = R3; + +CHECKREG(r2, 0x00000002); + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; NOP; NOP; + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_DATA_ADDR_1,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_dreg.s b/sim/testsuite/sim/bfin/c_ldimmhalf_dreg.s new file mode 100644 index 0000000..b39e4e1 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_dreg.s @@ -0,0 +1,60 @@ +//Original:/testcases/core/c_ldimmhalf_dreg/c_ldimmhalf_dreg.dsp +// Spec Reference: ldimmhalf dreg imm16 +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + +// test Dreg +R0 = 0x0123 (X); +R1 = 0x1234 (X); +R2 = 0x2345 (X); +R3 = 0x3456 (X); +R4 = 0x4567 (X); +R5 = 0x5678 (X); +R6 = 0x6789 (X); +R7 = 0x789a (X); +CHECKREG r0, 0x00000123; +CHECKREG r1, 0x00001234; +CHECKREG r2, 0x00002345; +CHECKREG r3, 0x00003456; +CHECKREG r4, 0x00004567; +CHECKREG r5, 0x00005678; +CHECKREG r6, 0x00006789; +CHECKREG r7, 0x0000789A; + +R0 = -32768 (X); +R1 = -1111 (X); +R2 = -2222 (X); +R3 = -3333 (X); +R4 = -4444 (X); +R5 = -5555 (X); +R6 = -6666 (X); +R7 = -7777 (X); +CHECKREG r0, 0xFFFF8000; +CHECKREG r1, 0xFFFFFBA9; +CHECKREG r2, 0xFFFFF752; +CHECKREG r3, 0xFFFFF2FB; +CHECKREG r4, 0xFFFFEEA4; +CHECKREG r5, 0xFFFFEA4D; +CHECKREG r6, 0xFFFFE5F6; +CHECKREG r7, 0xFFFFE19F; + +R0 = 0x7fff (X); +R1 = 0x7ffe (X); +R2 = 32767 (X); +R3 = 32766 (X); +R4 = -32768 (X); +R5 = -32767 (X); +CHECKREG r0, 0x00007fff; +CHECKREG r1, 0x00007ffe; +CHECKREG r2, 0x00007fff; +CHECKREG r3, 0x00007ffe; +CHECKREG r4, 0xFFFF8000; +CHECKREG r5, 0xFFFF8001; + +pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s b/sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s new file mode 100644 index 0000000..3b7194a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s @@ -0,0 +1,85 @@ +//Original:/testcases/core/c_ldimmhalf_drhi/c_ldimmhalf_drhi.dsp +// Spec Reference: ldimmhalf dreg hi +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + +// test Dreg +R0.H = 0x0001; +R1.H = 0x0003; +R2.H = 0x0005; +R3.H = 0x0007; +R4.H = 0x0009; +R5.H = 0x000b; +R6.H = 0x000d; +R7.H = 0x000f; +CHECKREG r0, 0x0001FFFF; +CHECKREG r1, 0x0003FFFF; +CHECKREG r2, 0x0005FFFF; +CHECKREG r3, 0x0007FFFF; +CHECKREG r4, 0x0009FFFF; +CHECKREG r5, 0x000bFFFF; +CHECKREG r6, 0x000dFFFF; +CHECKREG r7, 0x000fFFFF; + +R0.H = 0x0020; +R1.H = 0x0040; +R2.H = 0x0060; +R3.H = 0x0080; +R4.H = 0x00a0; +R5.H = 0x00b0; +R6.H = 0x00c0; +R7.H = 0x00d0; +CHECKREG r0, 0x0020FFFF; +CHECKREG r1, 0x0040FFFF; +CHECKREG r2, 0x0060FFFF; +CHECKREG r3, 0x0080FFFF; +CHECKREG r4, 0x00a0FFFF; +CHECKREG r5, 0x00b0FFFF; +CHECKREG r6, 0x00c0FFFF; +CHECKREG r7, 0x00d0FFFF; + +R0.H = 0x0100; +R1.H = 0x0200; +R2.H = 0x0300; +R3.H = 0x0400; +R4.H = 0x0500; +R5.H = 0x0600; +R6.H = 0x0700; +R7.H = 0x0800; +CHECKREG r0, 0x0100FFFF; +CHECKREG r1, 0x0200FFFF; +CHECKREG r2, 0x0300FFFF; +CHECKREG r3, 0x0400FFFF; +CHECKREG r4, 0x0500FFFF; +CHECKREG r5, 0x0600FFFF; +CHECKREG r6, 0x0700FFFF; +CHECKREG r7, 0x0800FFFF; + +R0 = 0; +R1 = 0; +R2 = 0; +R3 = 0; +R4 = 0; +R5 = 0; +R6 = 0; +R7 = 0; +R0.H = 0x7fff; +R1.H = 0x7ffe; +R2.H = 32767; +R3.H = 32766; +R4.H = -32768; +R5.H = -32767; +CHECKREG r0, 0x7fff0000; +CHECKREG r1, 0x7ffe0000; +CHECKREG r2, 0x7fff0000; +CHECKREG r3, 0x7ffe0000; +CHECKREG r4, 0x80000000; +CHECKREG r5, 0x80010000; + +pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s b/sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s new file mode 100644 index 0000000..0a33d4a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s @@ -0,0 +1,89 @@ +//Original:/testcases/core/c_ldimmhalf_drlo/c_ldimmhalf_drlo.dsp +// Spec Reference: ldimmhalf dreg lo +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + +// test Dreg +R0.L = 0x0001; +R1.L = 0x0003; +R2.L = 0x0005; +R3.L = 0x0007; +R4.L = 0x0009; +R5.L = 0x000b; +R6.L = 0x000d; +R7.L = 0x000f; +CHECKREG r0, 0xFFFF0001; +CHECKREG r1, 0xFFFF0003; +CHECKREG r2, 0xFFFF0005; +CHECKREG r3, 0xFFFF0007; +CHECKREG r4, 0xFFFF0009; +CHECKREG r5, 0xFFFF000b; +CHECKREG r6, 0xFFFF000D; +CHECKREG r7, 0xFFFF000F; + +R0.L = 0x0020; +R1.L = 0x0040; +R2.L = 0x0060; +R3.L = 0x0080; +R4.L = 0x00a0; +R5.L = 0x00b0; +R6.L = 0x00c0; +R7.L = 0x00d0; +CHECKREG r0, 0xFFFF0020; +CHECKREG r1, 0xFFFF0040; +CHECKREG r2, 0xFFFF0060; +CHECKREG r3, 0xFFFF0080; +CHECKREG r4, 0xFFFF00a0; +CHECKREG r5, 0xFFFF00b0; +CHECKREG r6, 0xFFFF00c0; +CHECKREG r7, 0xFFFF00d0; + +R0.L = 0x0100; +R1.L = 0x0200; +R2.L = 0x0300; +R3.L = 0x0400; +R4.L = 0x0500; +R5.L = 0x0600; +R6.L = 0x0700; +R7.L = 0x0800; +CHECKREG r0, 0xFFFF0100; +CHECKREG r1, 0xFFFF0200; +CHECKREG r2, 0xFFFF0300; +CHECKREG r3, 0xFFFF0400; +CHECKREG r4, 0xFFFF0500; +CHECKREG r5, 0xFFFF0600; +CHECKREG r6, 0xFFFF0700; +CHECKREG r7, 0xFFFF0800; + +R0 = 0; +R1 = 0; +R2 = 0; +R3 = 0; +R4 = 0; +R5 = 0; +R6 = 0; +R7 = 0; +R0.L = 0x7fff; +R1.L = 0x7ffe; +R2.L = -32768; +R3.L = -32767; +R4.L = 32767; +R5.L = 32766; +R6.L = 32765; +R7.L = 32764; +CHECKREG r0, 0x00007fff; +CHECKREG r1, 0x00007ffe; +CHECKREG r2, 0x00008000; +CHECKREG r3, 0x00008001; +CHECKREG r4, 0x00007FFF; +CHECKREG r5, 0x00007FFE; +CHECKREG r6, 0x00007FFD; +CHECKREG r7, 0x00007FFC; + +pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_h_dr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_h_dr.s new file mode 100644 index 0000000..83e60db --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_h_dr.s @@ -0,0 +1,82 @@ +//Original:/testcases/core/c_ldimmhalf_h_dr/c_ldimmhalf_h_dr.dsp +// Spec Reference: ldimmhalf h dreg +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + + +// test Dreg +R0.H = 0x0000; +R1.H = 0x0002; +R2.H = 0x0004; +R3.H = 0x0006; +R4.H = 0x0008; +R5.H = 0x000a; +R6.H = 0x000c; +R7.H = 0x000e; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0002ffff; +CHECKREG r2, 0x0004ffff; +CHECKREG r3, 0x0006ffff; +CHECKREG r4, 0x0008ffff; +CHECKREG r5, 0x000affff; +CHECKREG r6, 0x000cffff; +CHECKREG r7, 0x000effff; + +R0.H = 0x0000; +R1.H = 0x0020; +R2.H = 0x0040; +R3.H = 0x0060; +R4.H = 0x0080; +R5.H = 0x00a0; +R6.H = 0x00c0; +R7.H = 0x00e0; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0020ffff; +CHECKREG r2, 0x0040ffff; +CHECKREG r3, 0x0060ffff; +CHECKREG r4, 0x0080ffff; +CHECKREG r5, 0x00a0ffff; +CHECKREG r6, 0x00c0ffff; +CHECKREG r7, 0x00e0ffff; + +R0.H = 0x0000; +R1.H = 0x0200; +R2.H = 0x0400; +R3.H = 0x0600; +R4.H = 0x0800; +R5.H = 0x0a00; +R6.H = 0x0c00; +R7.H = 0x0e00; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x0200ffff; +CHECKREG r2, 0x0400ffff; +CHECKREG r3, 0x0600ffff; +CHECKREG r4, 0x0800ffff; +CHECKREG r5, 0x0a00ffff; +CHECKREG r6, 0x0c00ffff; +CHECKREG r7, 0x0e00ffff; + +R0.H = 0x0000; +R1.H = 0x2000; +R2.H = 0x4000; +R3.H = 0x6000; +R4.H = 0x8000; +R5.H = 0xa000; +R6.H = 0xc000; +R7.H = 0xe000; +CHECKREG r0, 0x0000ffff; +CHECKREG r1, 0x2000ffff; +CHECKREG r2, 0x4000ffff; +CHECKREG r3, 0x6000ffff; +CHECKREG r4, 0x8000ffff; +CHECKREG r5, 0xa000ffff; +CHECKREG r6, 0xc000ffff; +CHECKREG r7, 0xe000ffff; + +pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_h_ibml.s b/sim/testsuite/sim/bfin/c_ldimmhalf_h_ibml.s new file mode 100644 index 0000000..8aedc09 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_h_ibml.s @@ -0,0 +1,165 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_ibml/c_ldimmhalf_h_ibml.dsp +// Spec Reference: ldimmhalf h ibml +# mach: bfin + +.include "testutils.inc" + start + + INIT_I_REGS -1; + INIT_L_REGS -1; + INIT_B_REGS -1; + INIT_M_REGS -1; + + I0.H = 0x2000; + I1.H = 0x2002; + I2.H = 0x2004; + I3.H = 0x2006; + L0.H = 0x2008; + L1.H = 0x200a; + L2.H = 0x200c; + L3.H = 0x200e; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x2000ffff; + CHECKREG r1, 0x2002ffff; + CHECKREG r2, 0x2004ffff; + CHECKREG r3, 0x2006ffff; + CHECKREG r4, 0x2008ffff; + CHECKREG r5, 0x200affff; + CHECKREG r6, 0x200cffff; + CHECKREG r7, 0x200effff; + + I0.H = 0x0111; + I1.H = 0x1111; + I2.H = 0x2222; + I3.H = 0x3333; + L0.H = 0x4444; + L1.H = 0x5555; + L2.H = 0x6666; + L3.H = 0x7777; + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x0111ffff; + CHECKREG r1, 0x1111ffff; + CHECKREG r2, 0x2222ffff; + CHECKREG r3, 0x3333ffff; + CHECKREG r4, 0x4444ffff; + CHECKREG r5, 0x5555ffff; + CHECKREG r6, 0x6666ffff; + CHECKREG r7, 0x7777ffff; + + I0.H = 0x8888; + I1.H = 0x9aaa; + I2.H = 0xabbb; + I3.H = 0xbccc; + L0.H = 0xcddd; + L1.H = 0xdeee; + L2.H = 0xefff; + L3.H = 0xf111; + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x8888ffff; + CHECKREG r1, 0x9aaaffff; + CHECKREG r2, 0xabbbffff; + CHECKREG r3, 0xbcccffff; + CHECKREG r4, 0xcdddffff; + CHECKREG r5, 0xdeeeffff; + CHECKREG r6, 0xefffffff; + CHECKREG r7, 0xf111ffff; + + B0.H = 0x3000; + B1.H = 0x3002; + B2.H = 0x3004; + B3.H = 0x3006; + M0.H = 0x3008; + M1.H = 0x300a; + M2.H = 0x300c; + M3.H = 0x300e; + + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0x3000ffff; + CHECKREG r1, 0x3002ffff; + CHECKREG r2, 0x3004ffff; + CHECKREG r3, 0x3006ffff; + CHECKREG r4, 0x3008ffff; + CHECKREG r5, 0x300Affff; + CHECKREG r6, 0x300cffff; + CHECKREG r7, 0x300effff; + + B0.H = 0x0110; + B1.H = 0x1110; + B2.H = 0x2220; + B3.H = 0x3330; + M0.H = 0x4440; + M1.H = 0x5550; + M2.H = 0x6660; + M3.H = 0x7770; + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0x0110FFFF; + CHECKREG r1, 0x1110FFFF; + CHECKREG r2, 0x2220FFFF; + CHECKREG r3, 0x3330FFFF; + CHECKREG r4, 0x4440FFFF; + CHECKREG r5, 0x5550FFFF; + CHECKREG r6, 0x6660FFFF; + CHECKREG r7, 0x7770FFFF; + + B0.H = 0xf880; + B1.H = 0xfaa0; + B2.H = 0xfbb0; + B3.H = 0xfcc0; + M0.H = 0xfdd0; + M1.H = 0xfee0; + M2.H = 0xfff0; + M3.H = 0xf110; + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xf880ffff; + CHECKREG r1, 0xfaa0ffff; + CHECKREG r2, 0xfbb0ffff; + CHECKREG r3, 0xfcc0ffff; + CHECKREG r4, 0xfdd0ffff; + CHECKREG r5, 0xfee0ffff; + CHECKREG r6, 0xfff0ffff; + CHECKREG r7, 0xf110ffff; + + pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_h_pr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_h_pr.s new file mode 100644 index 0000000..cf7fb41 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_h_pr.s @@ -0,0 +1,74 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_pr/c_ldimmhalf_h_pr.dsp +// Spec Reference: ldimmhalf h preg +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS -1; + INIT_P_REGS -1; + imm32 sp, 0xffffffff; + imm32 fp, 0xffffffff; + +// test Preg + P1.H = 0x0002; + P2.H = 0x0004; + P3.H = 0x0006; + P4.H = 0x0008; + P5.H = 0x000a; + FP.H = 0x000c; + SP.H = 0x000e; + CHECKREG p1, 0x0002ffff; + CHECKREG p2, 0x0004ffff; + CHECKREG p3, 0x0006ffff; + CHECKREG p4, 0x0008ffff; + CHECKREG p5, 0x000affff; + CHECKREG fp, 0x000cffff; + CHECKREG sp, 0x000effff; + + P1.H = 0x0020; + P2.H = 0x0040; + P3.H = 0x0060; + P4.H = 0x0080; + P5.H = 0x00a0; + FP.H = 0x00c0; + SP.H = 0x00e0; + CHECKREG p1, 0x0020ffff; + CHECKREG p2, 0x0040ffff; + CHECKREG p3, 0x0060ffff; + CHECKREG p4, 0x0080ffff; + CHECKREG p5, 0x00a0ffff; + CHECKREG fp, 0x00c0ffff; + CHECKREG sp, 0x00e0ffff; + + P1.H = 0x0200; + P2.H = 0x0400; + P3.H = 0x0600; + P4.H = 0x0800; + P5.H = 0x0a00; + FP.H = 0x0c00; + SP.H = 0x0e00; + CHECKREG p1, 0x0200ffff; + CHECKREG p2, 0x0400ffff; + CHECKREG p3, 0x0600ffff; + CHECKREG p4, 0x0800ffff; + CHECKREG p5, 0x0a00ffff; + CHECKREG fp, 0x0c00ffff; + CHECKREG sp, 0x0e00ffff; + + P1.H = 0x2000; + P2.H = 0x4000; + P3.H = 0x6000; + P4.H = 0x8000; + P5.H = 0xa000; + FP.H = 0xc000; + SP.H = 0xe000; + CHECKREG p1, 0x2000ffff; + CHECKREG p2, 0x4000ffff; + CHECKREG p3, 0x6000ffff; + CHECKREG p4, 0x8000ffff; + CHECKREG p5, 0xa000ffff; + CHECKREG fp, 0xc000ffff; + CHECKREG sp, 0xe000ffff; + + pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_l_dr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_l_dr.s new file mode 100644 index 0000000..b47284d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_l_dr.s @@ -0,0 +1,82 @@ +//Original:/testcases/core/c_ldimmhalf_l_dr/c_ldimmhalf_l_dr.dsp +// Spec Reference: ldimmhalf l dreg +# mach: bfin + +.include "testutils.inc" + start + + + +INIT_R_REGS -1; + + +// test Dreg +R0.L = 0x0001; +R1.L = 0x0003; +R2.L = 0x0005; +R3.L = 0x0007; +R4.L = 0x0009; +R5.L = 0x000b; +R6.L = 0x000d; +R7.L = 0x000f; +CHECKREG r0, 0xffff0001; +CHECKREG r1, 0xffff0003; +CHECKREG r2, 0xffff0005; +CHECKREG r3, 0xffff0007; +CHECKREG r4, 0xffff0009; +CHECKREG r5, 0xffff000b; +CHECKREG r6, 0xffff000d; +CHECKREG r7, 0xffff000f; + +R0.L = 0x0010; +R1.L = 0x0030; +R2.L = 0x0050; +R3.L = 0x0070; +R4.L = 0x0090; +R5.L = 0x00b0; +R6.L = 0x00d0; +R7.L = 0x00f0; +CHECKREG r0, 0xffff0010; +CHECKREG r1, 0xffff0030; +CHECKREG r2, 0xffff0050; +CHECKREG r3, 0xffff0070; +CHECKREG r4, 0xffff0090; +CHECKREG r5, 0xffff00b0; +CHECKREG r6, 0xffff00d0; +CHECKREG r7, 0xffff00f0; + +R0.L = 0x0100; +R1.L = 0x0300; +R2.L = 0x0500; +R3.L = 0x0700; +R4.L = 0x0900; +R5.L = 0x0b00; +R6.L = 0x0d00; +R7.L = 0x0f00; +CHECKREG r0, 0xffff0100; +CHECKREG r1, 0xffff0300; +CHECKREG r2, 0xffff0500; +CHECKREG r3, 0xffff0700; +CHECKREG r4, 0xffff0900; +CHECKREG r5, 0xffff0b00; +CHECKREG r6, 0xffff0d00; +CHECKREG r7, 0xffff0f00; + +R0.L = 0x1000; +R1.L = 0x3000; +R2.L = 0x5000; +R3.L = 0x7000; +R4.L = 0x9000; +R5.L = 0xb000; +R6.L = 0xd000; +R7.L = 0xf000; +CHECKREG r0, 0xffff1000; +CHECKREG r1, 0xffff3000; +CHECKREG r2, 0xffff5000; +CHECKREG r3, 0xffff7000; +CHECKREG r4, 0xffff9000; +CHECKREG r5, 0xffffb000; +CHECKREG r6, 0xffffd000; +CHECKREG r7, 0xfffff000; + +pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_l_ibml.s b/sim/testsuite/sim/bfin/c_ldimmhalf_l_ibml.s new file mode 100644 index 0000000..66f83b0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_l_ibml.s @@ -0,0 +1,165 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_ibml/c_ldimmhalf_l_ibml.dsp +// Spec Reference: ldimmhalf l ibml +# mach: bfin + +.include "testutils.inc" + start + + INIT_I_REGS -1; + INIT_L_REGS -1; + INIT_M_REGS -1; + INIT_B_REGS -1; + + I0.L = 0x2001; + I1.L = 0x2003; + I2.L = 0x2005; + I3.L = 0x2007; + L0.L = 0x2009; + L1.L = 0x200b; + L2.L = 0x200d; + L3.L = 0x200f; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0xffff2001; + CHECKREG r1, 0xffff2003; + CHECKREG r2, 0xffff2005; + CHECKREG r3, 0xffff2007; + CHECKREG r4, 0xffff2009; + CHECKREG r5, 0xffff200b; + CHECKREG r6, 0xffff200d; + CHECKREG r7, 0xffff200f; + + I0.L = 0x0111; + I1.L = 0x1111; + I2.L = 0x2222; + I3.L = 0x3333; + L0.L = 0x4444; + L1.L = 0x5555; + L2.L = 0x6666; + L3.L = 0x7777; + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0xffff0111; + CHECKREG r1, 0xffff1111; + CHECKREG r2, 0xffff2222; + CHECKREG r3, 0xffff3333; + CHECKREG r4, 0xffff4444; + CHECKREG r5, 0xffff5555; + CHECKREG r6, 0xffff6666; + CHECKREG r7, 0xffff7777; + + I0.L = 0x8888; + I1.L = 0x9aaa; + I2.L = 0xabbb; + I3.L = 0xbccc; + L0.L = 0xcddd; + L1.L = 0xdeee; + L2.L = 0xefff; + L3.L = 0xf111; + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0xffff8888; + CHECKREG r1, 0xffff9aaa; + CHECKREG r2, 0xffffabbb; + CHECKREG r3, 0xffffbccc; + CHECKREG r4, 0xffffcddd; + CHECKREG r5, 0xffffdeee; + CHECKREG r6, 0xffffefff; + CHECKREG r7, 0xfffff111; + + B0.L = 0x3001; + B1.L = 0x3003; + B2.L = 0x3005; + B3.L = 0x3007; + M0.L = 0x3009; + M1.L = 0x300b; + M2.L = 0x300d; + M3.L = 0x300f; + + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xffff3001; + CHECKREG r1, 0xffff3003; + CHECKREG r2, 0xffff3005; + CHECKREG r3, 0xffff3007; + CHECKREG r4, 0xffff3009; + CHECKREG r5, 0xffff300B; + CHECKREG r6, 0xffff300d; + CHECKREG r7, 0xffff300f; + + B0.L = 0x0110; + B1.L = 0x1110; + B2.L = 0x2220; + B3.L = 0x3330; + M0.L = 0x4440; + M1.L = 0x5550; + M2.L = 0x6660; + M3.L = 0x7770; + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xffff0110; + CHECKREG r1, 0xffff1110; + CHECKREG r2, 0xffff2220; + CHECKREG r3, 0xffff3330; + CHECKREG r4, 0xffff4440; + CHECKREG r5, 0xffff5550; + CHECKREG r6, 0xffff6660; + CHECKREG r7, 0xffff7770; + + B0.L = 0xf880; + B1.L = 0xfaa0; + B2.L = 0xfbb0; + B3.L = 0xfcc0; + M0.L = 0xfdd0; + M1.L = 0xfee0; + M2.L = 0xfff0; + M3.L = 0xf110; + R0 = B0; + R1 = B1; + R2 = B2; + R3 = B3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xfffff880; + CHECKREG r1, 0xfffffaa0; + CHECKREG r2, 0xfffffbb0; + CHECKREG r3, 0xfffffcc0; + CHECKREG r4, 0xfffffdd0; + CHECKREG r5, 0xfffffee0; + CHECKREG r6, 0xfffffff0; + CHECKREG r7, 0xfffff110; + + pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_l_pr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_l_pr.s new file mode 100644 index 0000000..c067862 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_l_pr.s @@ -0,0 +1,76 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_pr/c_ldimmhalf_l_pr.dsp +// Spec Reference: ldimmhalf l preg +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS -1; + INIT_P_REGS -1; + + imm32 sp, 0xffffffff; + imm32 fp, 0xffffffff; + +// test Preg + P1.L = 0x0003; + P2.L = 0x0005; + P3.L = 0x0007; + P4.L = 0x0009; + P5.L = 0x000b; + FP.L = 0x000d; + SP.L = 0x000f; + CHECKREG p1, 0xffff0003; + CHECKREG p2, 0xffff0005; + CHECKREG p3, 0xffff0007; + CHECKREG p4, 0xffff0009; + CHECKREG p5, 0xffff000b; + CHECKREG fp, 0xffff000d; + CHECKREG sp, 0xffff000f; + + P1.L = 0x0030; + P2.L = 0x0050; + P3.L = 0x0070; + P4.L = 0x0090; + P5.L = 0x00b0; + FP.L = 0x00d0; + SP.L = 0x00f0; +//CHECKREG p0, 0x00000010; + CHECKREG p1, 0xffff0030; + CHECKREG p2, 0xffff0050; + CHECKREG p3, 0xffff0070; + CHECKREG p4, 0xffff0090; + CHECKREG p5, 0xffff00b0; + CHECKREG fp, 0xffff00d0; + CHECKREG sp, 0xffff00f0; + + P1.L = 0x0300; + P2.L = 0x0500; + P3.L = 0x0700; + P4.L = 0x0900; + P5.L = 0x0b00; + FP.L = 0x0d00; + SP.L = 0x0f00; + CHECKREG p1, 0xffff0300; + CHECKREG p2, 0xffff0500; + CHECKREG p3, 0xffff0700; + CHECKREG p4, 0xffff0900; + CHECKREG p5, 0xffff0b00; + CHECKREG fp, 0xffff0d00; + CHECKREG sp, 0xffff0f00; + + P1.L = 0x3000; + P2.L = 0x5000; + P3.L = 0x7000; + P4.L = 0x9000; + P5.L = 0xb000; + FP.L = 0xd000; + SP.L = 0xf000; + CHECKREG p1, 0xffff3000; + CHECKREG p2, 0xffff5000; + CHECKREG p3, 0xffff7000; + CHECKREG p4, 0xffff9000; + CHECKREG p5, 0xffffb000; + CHECKREG fp, 0xffffd000; + CHECKREG sp, 0xfffff000; + + pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_lz_dr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_lz_dr.s new file mode 100644 index 0000000..a2ae95f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_lz_dr.s @@ -0,0 +1,81 @@ +//Original:/testcases/core/c_ldimmhalf_lz_dr/c_ldimmhalf_lz_dr.dsp +// Spec Reference: ldimmhalf lz dreg +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS -1; + + +// test Dreg +R0 = 0x0001 (Z); +R1 = 0x0003 (Z); +R2 = 0x0005 (Z); +R3 = 0x0007 (Z); +R4 = 0x0009 (Z); +R5 = 0x000b (Z); +R6 = 0x000d (Z); +R7 = 0x000f (Z); +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0x00000005; +CHECKREG r3, 0x00000007; +CHECKREG r4, 0x00000009; +CHECKREG r5, 0x0000000b; +CHECKREG r6, 0x0000000d; +CHECKREG r7, 0x0000000f; + +R0 = 0x0010 (Z); +R1 = 0x0030 (Z); +R2 = 0x0050 (Z); +R3 = 0x0070 (Z); +R4 = 0x0090 (Z); +R5 = 0x00b0 (Z); +R6 = 0x00d0 (Z); +R7 = 0x00f0 (Z); +CHECKREG r0, 0x00000010; +CHECKREG r1, 0x00000030; +CHECKREG r2, 0x00000050; +CHECKREG r3, 0x00000070; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0x000000b0; +CHECKREG r6, 0x000000d0; +CHECKREG r7, 0x000000f0; + +R0 = 0x0100 (Z); +R1 = 0x0300 (Z); +R2 = 0x0500 (Z); +R3 = 0x0700 (Z); +R4 = 0x0900 (Z); +R5 = 0x0b00 (Z); +R6 = 0x0d00 (Z); +R7 = 0x0f00 (Z); +CHECKREG r0, 0x00000100; +CHECKREG r1, 0x00000300; +CHECKREG r2, 0x00000500; +CHECKREG r3, 0x00000700; +CHECKREG r4, 0x00000900; +CHECKREG r5, 0x00000b00; +CHECKREG r6, 0x00000d00; +CHECKREG r7, 0x00000f00; + +R0 = 0x1000 (Z); +R1 = 0x3000 (Z); +R2 = 0x5000 (Z); +R3 = 0x7000 (Z); +R4 = 0x9000 (Z); +R5 = 0xb000 (Z); +R6 = 0xd000 (Z); +R7 = 0xf000 (Z); +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x00003000; +CHECKREG r2, 0x00005000; +CHECKREG r3, 0x00007000; +CHECKREG r4, 0x00009000; +CHECKREG r5, 0x0000b000; +CHECKREG r6, 0x0000d000; +CHECKREG r7, 0x0000f000; + +pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_lz_ibml.s b/sim/testsuite/sim/bfin/c_ldimmhalf_lz_ibml.s new file mode 100644 index 0000000..efe77ae --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_lz_ibml.s @@ -0,0 +1,168 @@ +//Original:/testcases/core/c_ldimmhalf_lz_ibml/c_ldimmhalf_lz_ibml.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: ldimmhalf lz ibml + + + + +I0 = 0x2001 (Z); +I1 = 0x2003 (Z); +I2 = 0x2005 (Z); +I3 = 0x2007 (Z); +L0 = 0x2009 (Z); +L1 = 0x200b (Z); +L2 = 0x200d (Z); +L3 = 0x200f (Z); + + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x00002001; +CHECKREG r1, 0x00002003; +CHECKREG r2, 0x00002005; +CHECKREG r3, 0x00002007; +CHECKREG r4, 0x00002009; +CHECKREG r5, 0x0000200b; +CHECKREG r6, 0x0000200d; +CHECKREG r7, 0x0000200f; + +I0 = 0x0111 (Z); +I1 = 0x1111 (Z); +I2 = 0x2222 (Z); +I3 = 0x3333 (Z); +L0 = 0x4444 (Z); +L1 = 0x5555 (Z); +L2 = 0x6666 (Z); +L3 = 0x7777 (Z); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x00000111; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00002222; +CHECKREG r3, 0x00003333; +CHECKREG r4, 0x00004444; +CHECKREG r5, 0x00005555; +CHECKREG r6, 0x00006666; +CHECKREG r7, 0x00007777; + +I0 = 0x8888 (Z); +I1 = 0x9aaa (Z); +I2 = 0xabbb (Z); +I3 = 0xbccc (Z); +L0 = 0xcddd (Z); +L1 = 0xdeee (Z); +L2 = 0xefff (Z); +L3 = 0xf111 (Z); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x00008888; +CHECKREG r1, 0x00009aaa; +CHECKREG r2, 0x0000abbb; +CHECKREG r3, 0x0000bccc; +CHECKREG r4, 0x0000cddd; +CHECKREG r5, 0x0000deee; +CHECKREG r6, 0x0000efff; +CHECKREG r7, 0x0000f111; + +B0 = 0x3001 (Z); +B1 = 0x3003 (Z); +B2 = 0x3005 (Z); +B3 = 0x3007 (Z); +M0 = 0x3009 (Z); +M1 = 0x300b (Z); +M2 = 0x300d (Z); +M3 = 0x300f (Z); + +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00003001; +CHECKREG r1, 0x00003003; +CHECKREG r2, 0x00003005; +CHECKREG r3, 0x00003007; +CHECKREG r4, 0x00003009; +CHECKREG r5, 0x0000300B; +CHECKREG r6, 0x0000300d; +CHECKREG r7, 0x0000300f; + + +B0 = 0x0110 (Z); +B1 = 0x1110 (Z); +B2 = 0x2220 (Z); +B3 = 0x3330 (Z); +M0 = 0x4440 (Z); +M1 = 0x5550 (Z); +M2 = 0x6660 (Z); +M3 = 0x7770 (Z); +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00000110; +CHECKREG r1, 0x00001110; +CHECKREG r2, 0x00002220; +CHECKREG r3, 0x00003330; +CHECKREG r4, 0x00004440; +CHECKREG r5, 0x00005550; +CHECKREG r6, 0x00006660; +CHECKREG r7, 0x00007770; + +B0 = 0xf880 (Z); +B1 = 0xfaa0 (Z); +B2 = 0xfbb0 (Z); +B3 = 0xfcc0 (Z); +M0 = 0xfdd0 (Z); +M1 = 0xfee0 (Z); +M2 = 0xfff0 (Z); +M3 = 0xf110 (Z); +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x0000f880; +CHECKREG r1, 0x0000faa0; +CHECKREG r2, 0x0000fbb0; +CHECKREG r3, 0x0000fcc0; +CHECKREG r4, 0x0000fdd0; +CHECKREG r5, 0x0000fee0; +CHECKREG r6, 0x0000fff0; +CHECKREG r7, 0x0000f110; + + +pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_lz_pr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_lz_pr.s new file mode 100644 index 0000000..23d3191 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_lz_pr.s @@ -0,0 +1,72 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lz_pr/c_ldimmhalf_lz_pr.dsp +// Spec Reference: ldimmhalf lz preg +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS -1; + +// test Preg + P1 = 0x0003 (Z); + P2 = 0x0005 (Z); + P3 = 0x0007 (Z); + P4 = 0x0009 (Z); + P5 = 0x000b (Z); + FP = 0x000d (Z); + SP = 0x000f (Z); + CHECKREG p1, 0x00000003; + CHECKREG p2, 0x00000005; + CHECKREG p3, 0x00000007; + CHECKREG p4, 0x00000009; + CHECKREG p5, 0x0000000b; + CHECKREG fp, 0x0000000d; + CHECKREG sp, 0x0000000f; + + P1 = 0x0030 (Z); + P2 = 0x0050 (Z); + P3 = 0x0070 (Z); + P4 = 0x0090 (Z); + P5 = 0x00b0 (Z); + FP = 0x00d0 (Z); + SP = 0x00f0 (Z); +//CHECKREG p0, 0x00000010; + CHECKREG p1, 0x00000030; + CHECKREG p2, 0x00000050; + CHECKREG p3, 0x00000070; + CHECKREG p4, 0x00000090; + CHECKREG p5, 0x000000b0; + CHECKREG fp, 0x000000d0; + CHECKREG sp, 0x000000f0; + + P1 = 0x0300 (Z); + P2 = 0x0500 (Z); + P3 = 0x0700 (Z); + P4 = 0x0900 (Z); + P5 = 0x0b00 (Z); + FP = 0x0d00 (Z); + SP = 0x0f00 (Z); + CHECKREG p1, 0x00000300; + CHECKREG p2, 0x00000500; + CHECKREG p3, 0x00000700; + CHECKREG p4, 0x00000900; + CHECKREG p5, 0x00000b00; + CHECKREG fp, 0x00000d00; + CHECKREG sp, 0x00000f00; + + P1 = 0x3000 (Z); + P2 = 0x5000 (Z); + P3 = 0x7000 (Z); + P4 = 0x9000 (Z); + P5 = 0xb000 (Z); + FP = 0xd000 (Z); + SP = 0xf000 (Z); + CHECKREG p1, 0x00003000; + CHECKREG p2, 0x00005000; + CHECKREG p3, 0x00007000; + CHECKREG p4, 0x00009000; + CHECKREG p5, 0x0000b000; + CHECKREG fp, 0x0000d000; + CHECKREG sp, 0x0000f000; + + pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_dr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_dr.s new file mode 100644 index 0000000..67e652a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_dr.s @@ -0,0 +1,113 @@ +//Original:/testcases/core/c_ldimmhalf_lzhi_dr/c_ldimmhalf_lzhi_dr.dsp +// Spec Reference: ldimmhalf lz & hi dreg +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS -1; + + +// test Dreg +R0 = 0x0001 (Z); +R0.H = 0x0000; +R1 = 0x0003 (Z); +R1.H = 0x0002; +R2 = 0x0005 (Z); +R2.H = 0x0004; +R3 = 0x0007 (Z); +R3.H = 0x0006; +R4 = 0x0009 (Z); +R4.H = 0x0008; +R5 = 0x000b (Z); +R5.H = 0x000a; +R6 = 0x000d (Z); +R6.H = 0x000c; +R7 = 0x000f (Z); +R7.H = 0x000e; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000e000f; + +R0 = 0x0010 (Z); +R0.H = 0x0000; +R1 = 0x0030 (Z); +R1.H = 0x0020; +R2 = 0x0050 (Z); +R2.H = 0x0040; +R3 = 0x0070 (Z); +R3.H = 0x0060; +R4 = 0x0090 (Z); +R4.H = 0x0080; +R5 = 0x00b0 (Z); +R5.H = 0x00a0; +R6 = 0x00d0 (Z); +R6.H = 0x00c0; +R7 = 0x00f0 (Z); +R7.H = 0x00e0; +CHECKREG r0, 0x00000010; +CHECKREG r1, 0x00200030; +CHECKREG r2, 0x00400050; +CHECKREG r3, 0x00600070; +CHECKREG r4, 0x00800090; +CHECKREG r5, 0x00a000b0; +CHECKREG r6, 0x00c000d0; +CHECKREG r7, 0x00e000f0; + +R0 = 0x0100 (Z); +R0.H = 0x0000; +R1 = 0x0300 (Z); +R1.H = 0x0200; +R2 = 0x0500 (Z); +R2.H = 0x0400; +R3 = 0x0700 (Z); +R3.H = 0x0600; +R4 = 0x0900 (Z); +R4.H = 0x0800; +R5 = 0x0b00 (Z); +R5.H = 0x0a00; +R6 = 0x0d00 (Z); +R6.H = 0x0c00; +R7 = 0x0f00 (Z); +R7.H = 0x0e00; +CHECKREG r0, 0x00000100; +CHECKREG r1, 0x02000300; +CHECKREG r2, 0x04000500; +CHECKREG r3, 0x06000700; +CHECKREG r4, 0x08000900; +CHECKREG r5, 0x0a000b00; +CHECKREG r6, 0x0c000d00; +CHECKREG r7, 0x0e000f00; + +R0 = 0x1000 (Z); +R0.H = 0x0000; +R1 = 0x3000 (Z); +R1.H = 0x2000; +R2 = 0x5000 (Z); +R2.H = 0x4000; +R3 = 0x7000 (Z); +R3.H = 0x6000; +R4 = 0x9000 (Z); +R4.H = 0x8000; +R5 = 0xb000 (Z); +R5.H = 0xa000; +R6 = 0xd000 (Z); +R6.H = 0xc000; +R7 = 0xf000 (Z); +R7.H = 0xe000; +CHECKREG r0, 0x00001000; +CHECKREG r1, 0x20003000; +CHECKREG r2, 0x40005000; +CHECKREG r3, 0x60007000; +CHECKREG r4, 0x80009000; +CHECKREG r5, 0xa000b000; +CHECKREG r6, 0xc000d000; +CHECKREG r7, 0xe000f000; + +pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_ibml.s b/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_ibml.s new file mode 100644 index 0000000..6f5720b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_ibml.s @@ -0,0 +1,216 @@ +//Original:/testcases/core/c_ldimmhalf_lzhi_ibml/c_ldimmhalf_lzhi_ibml.dsp +# mach: bfin + +.include "testutils.inc" + start + + +// Spec Reference: ldimmhalf lzhi ibml + + + + +I0 = 0x2001 (Z); +I0.H = 0x2000; +I1 = 0x2003 (Z); +I1.H = 0x2002; +I2 = 0x2005 (Z); +I2.H = 0x2004; +I3 = 0x2007 (Z); +I3.H = 0x2006; +L0 = 0x2009 (Z); +L0.H = 0x2008; +L1 = 0x200b (Z); +L1.H = 0x200a; +L2 = 0x200d (Z); +L2.H = 0x200c; +L3 = 0x200f (Z); +L3.H = 0x200e; + + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x20002001; +CHECKREG r1, 0x20022003; +CHECKREG r2, 0x20042005; +CHECKREG r3, 0x20062007; +CHECKREG r4, 0x20082009; +CHECKREG r5, 0x200a200b; +CHECKREG r6, 0x200c200d; +CHECKREG r7, 0x200e200f; + +I0 = 0x0111 (Z); +I0.H = 0x1000; +I1 = 0x1111 (Z); +I1.H = 0x1000; +I2 = 0x2222 (Z); +I2.H = 0x2000; +I3 = 0x3333 (Z); +I3.H = 0x3000; +L0 = 0x4444 (Z); +L0.H = 0x4000; +L1 = 0x5555 (Z); +L1.H = 0x5000; +L2 = 0x6666 (Z); +L2.H = 0x6000; +L3 = 0x7777 (Z); +L3.H = 0x7000; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x10000111; +CHECKREG r1, 0x10001111; +CHECKREG r2, 0x20002222; +CHECKREG r3, 0x30003333; +CHECKREG r4, 0x40004444; +CHECKREG r5, 0x50005555; +CHECKREG r6, 0x60006666; +CHECKREG r7, 0x70007777; + +I0 = 0x8888 (Z); +I0.H = 0x8000; +I1 = 0x9aaa (Z); +I1.H = 0x9000; +I2 = 0xabbb (Z); +I2.H = 0xa000; +I3 = 0xbccc (Z); +I3.H = 0xb000; +L0 = 0xcddd (Z); +L0.H = 0xc000; +L1 = 0xdeee (Z); +L1.H = 0xd000; +L2 = 0xefff (Z); +L2.H = 0xe000; +L3 = 0xf111 (Z); +L3.H = 0xf000; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = L0; +R5 = L1; +R6 = L2; +R7 = L3; +CHECKREG r0, 0x80008888; +CHECKREG r1, 0x90009aaa; +CHECKREG r2, 0xa000abbb; +CHECKREG r3, 0xb000bccc; +CHECKREG r4, 0xc000cddd; +CHECKREG r5, 0xd000deee; +CHECKREG r6, 0xe000efff; +CHECKREG r7, 0xf000f111; + +B0 = 0x3001 (Z); +B0.H = 0x3000; +B1 = 0x3003 (Z); +B1.H = 0x3002; +B2 = 0x3005 (Z); +B2.H = 0x3004; +B3 = 0x3007 (Z); +B3.H = 0x3006; +M0 = 0x3009 (Z); +M0.H = 0x3008; +M1 = 0x300b (Z); +M1.H = 0x300a; +M2 = 0x300d (Z); +M2.H = 0x300c; +M3 = 0x300f (Z); +M3.H = 0x300e; + +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x30003001; +CHECKREG r1, 0x30023003; +CHECKREG r2, 0x30043005; +CHECKREG r3, 0x30063007; +CHECKREG r4, 0x30083009; +CHECKREG r5, 0x300A300B; +CHECKREG r6, 0x300c300d; +CHECKREG r7, 0x300e300f; + + +B0 = 0x0110 (Z); +B0.H = 0x1000; +B1 = 0x1110 (Z); +B1.H = 0x1000; +B2 = 0x2220 (Z); +B2.H = 0x2000; +B3 = 0x3330 (Z); +B3.H = 0x3000; +M0 = 0x4440 (Z); +M0.H = 0x4000; +M1 = 0x5550 (Z); +M1.H = 0x5000; +M2 = 0x6660 (Z); +M2.H = 0x6000; +M3 = 0x7770 (Z); +M3.H = 0x7000; +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x10000110; +CHECKREG r1, 0x10001110; +CHECKREG r2, 0x20002220; +CHECKREG r3, 0x30003330; +CHECKREG r4, 0x40004440; +CHECKREG r5, 0x50005550; +CHECKREG r6, 0x60006660; +CHECKREG r7, 0x70007770; + +B0 = 0xf880 (Z); +B0.H = 0x8000; +B1 = 0xfaa0 (Z); +B1.H = 0xa000; +B2 = 0xfbb0 (Z); +B2.H = 0xb000; +B3 = 0xfcc0 (Z); +B3.H = 0xc000; +M0 = 0xfdd0 (Z); +M0.H = 0xd000; +M1 = 0xfee0 (Z); +M1.H = 0xe000; +M2 = 0xfff0 (Z); +M2.H = 0xf000; +M3 = 0xf110 (Z); +M3.H = 0x1000; +R0 = B0; +R1 = B1; +R2 = B2; +R3 = B3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x8000f880; +CHECKREG r1, 0xa000faa0; +CHECKREG r2, 0xb000fbb0; +CHECKREG r3, 0xc000fcc0; +CHECKREG r4, 0xd000fdd0; +CHECKREG r5, 0xe000fee0; +CHECKREG r6, 0xf000fff0; +CHECKREG r7, 0x1000f110; + + +pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_pr.s b/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_pr.s new file mode 100644 index 0000000..9276d36 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_lzhi_pr.s @@ -0,0 +1,102 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lzhi_pr/c_ldimmhalf_lzhi_pr.dsp +// Spec Reference: ldimmhalf lzhi preg +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS -1; + +// test Preg +//lz(p0)=0x0001; +//h(p0) =0x0000; + P1 = 0x0003 (Z); + P1.H = 0x0002; + P2 = 0x0005 (Z); + P2.H = 0x0004; + P3 = 0x0007 (Z); + P3.H = 0x0006; + P4 = 0x0009 (Z); + P4.H = 0x0008; + P5 = 0x000b (Z); + P5.H = 0x000a; + FP = 0x000d (Z); + FP.H = 0x000c; + SP = 0x000f (Z); + SP.H = 0x000e; + CHECKREG p1, 0x00020003; + CHECKREG p2, 0x00040005; + CHECKREG p3, 0x00060007; + CHECKREG p4, 0x00080009; + CHECKREG p5, 0x000a000b; + CHECKREG fp, 0x000c000d; + CHECKREG sp, 0x000e000f; + + P1 = 0x0030 (Z); + P1.H = 0x0020; + P2 = 0x0050 (Z); + P2.H = 0x0040; + P3 = 0x0070 (Z); + P3.H = 0x0060; + P4 = 0x0090 (Z); + P4.H = 0x0080; + P5 = 0x00b0 (Z); + P5.H = 0x00a0; + FP = 0x00d0 (Z); + FP.H = 0x00c0; + SP = 0x00f0 (Z); + SP.H = 0x00e0; +//CHECKREG p0, 0x00000010; + CHECKREG p1, 0x00200030; + CHECKREG p2, 0x00400050; + CHECKREG p3, 0x00600070; + CHECKREG p4, 0x00800090; + CHECKREG p5, 0x00a000b0; + CHECKREG fp, 0x00c000d0; + CHECKREG sp, 0x00e000f0; + + P1 = 0x0300 (Z); + P1.H = 0x0200; + P2 = 0x0500 (Z); + P2.H = 0x0400; + P3 = 0x0700 (Z); + P3.H = 0x0600; + P4 = 0x0900 (Z); + P4.H = 0x0800; + P5 = 0x0b00 (Z); + P5.H = 0x0a00; + FP = 0x0d00 (Z); + FP.H = 0x0c00; + SP = 0x0f00 (Z); + SP.H = 0x0e00; + CHECKREG p1, 0x02000300; + CHECKREG p2, 0x04000500; + CHECKREG p3, 0x06000700; + CHECKREG p4, 0x08000900; + CHECKREG p5, 0x0a000b00; + CHECKREG fp, 0x0c000d00; + CHECKREG sp, 0x0e000f00; + + P1 = 0x3000 (Z); + P1.H = 0x2000; + P2 = 0x5000 (Z); + P2.H = 0x4000; + P3 = 0x7000 (Z); + P3.H = 0x6000; + P4 = 0x9000 (Z); + P4.H = 0x8000; + P5 = 0xb000 (Z); + P5.H = 0xa000; + FP = 0xd000 (Z); + FP.H = 0xc000; + SP = 0xf000 (Z); + SP.H = 0xe000; + CHECKREG p1, 0x20003000; + CHECKREG p2, 0x40005000; + CHECKREG p3, 0x60007000; + CHECKREG p4, 0x80009000; + CHECKREG p5, 0xa000b000; + CHECKREG fp, 0xc000d000; + CHECKREG sp, 0xe000f000; + + pass diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_pibml.s b/sim/testsuite/sim/bfin/c_ldimmhalf_pibml.s new file mode 100644 index 0000000..a7e8f8b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldimmhalf_pibml.s @@ -0,0 +1,212 @@ +//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_pibml/c_ldimmhalf_pibml.dsp +// Spec Reference: ldimmhalf p i b m l +# mach: bfin + +.include "testutils.inc" + start + +// set all reg=-1 + + +//p0 =0x0123; + P1 = 0x1234 (X); + P2 = 0x2345 (X); + P3 = 0x3456 (X); + P4 = 0x4567 (X); + P5 = 0x5678 (X); + FP = 0x6789 (X); + SP = 0x789a (X); +//CHECKREG p0, 0x00000123; + CHECKREG p1, 0x00001234; + CHECKREG p2, 0x00002345; + CHECKREG p3, 0x00003456; + CHECKREG p4, 0x00004567; + CHECKREG p5, 0x00005678; + CHECKREG fp, 0x00006789; + CHECKREG sp, 0x0000789A; + +//p0 = -32768; + P1 = -32768 (X); + P2 = -2222 (X); + P3 = -3333 (X); + P4 = -4444 (X); + P5 = -5555 (X); + FP = -6666 (X); + SP = -7777 (X); +//CHECKREG r0, 0xFFFF8000; + CHECKREG p1, 0xFFFF8000; + CHECKREG p2, 0xFFFFF752; + CHECKREG p3, 0xFFFFF2FB; + CHECKREG p4, 0xFFFFEEA4; + CHECKREG p5, 0xFFFFEA4D; + CHECKREG fp, 0xFFFFE5F6; + CHECKREG sp, 0xFFFFE19F; + +//p0 =0x0123; + P1 = 0x7abc (X); + P2 = 0x6def (X); + P3 = 0x5f56 (X); + P4 = 0x7dd7 (X); + P5 = 0x4abd (X); + FP = 0x7fff (X); + SP = 0x7ffa (X); +//CHECKREG p0, 0x00000123; + CHECKREG p1, 0x00007abc; + CHECKREG p2, 0x00006def; + CHECKREG p3, 0x00005f56; + CHECKREG p4, 0x00007dd7; + CHECKREG p5, 0x00004abd; + CHECKREG fp, 0x00007fff; + CHECKREG sp, 0x00007ffa; + + I0 = 0x0123 (X); + I1 = 0x1234 (X); + I2 = 0x2345 (X); + I3 = 0x3456 (X); + B0 = 0x0567 (X); + B1 = 0x1678 (X); + B2 = 0x2789 (X); + B3 = 0x389a (X); + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0x00000123; + CHECKREG r1, 0x00001234; + CHECKREG r2, 0x00002345; + CHECKREG r3, 0x00003456; + CHECKREG r4, 0x00000567; + CHECKREG r5, 0x00001678; + CHECKREG r6, 0x00002789; + CHECKREG r7, 0x0000389A; + + I0 = -32768 (X); + I1 = -12345 (X); + I2 = -23456 (X); + I3 = -3456 (X); + B0 = -4567 (X); + B1 = -5678 (X); + B2 = -6678 (X); + B3 = -7012 (X); + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0xFFFF8000; + CHECKREG r1, 0xFFFFCFC7; + CHECKREG r2, 0xFFFFA460; + CHECKREG r3, 0xFFFFF280; + CHECKREG r4, 0xFFFFEE29; + CHECKREG r5, 0xFFFFE9D2; + CHECKREG r6, 0xFFFFE5EA; + CHECKREG r7, 0xFFFFE49C; + + I0 = 0x7abd (X); + I1 = 0x7bf4 (X); + I2 = 0x6c45 (X); + I3 = 0x7d56 (X); + B0 = 0x7e67 (X); + B1 = 0x7f78 (X); + B2 = 0x7ff9 (X); + B3 = 0x7fff (X); + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0x00007abd; + CHECKREG r1, 0x00007bf4; + CHECKREG r2, 0x00006c45; + CHECKREG r3, 0x00007d56; + CHECKREG r4, 0x00007e67; + CHECKREG r5, 0x00007f78; + CHECKREG r6, 0x00007ff9; + CHECKREG r7, 0x00007fff; + + M0 = 0x7123 (X); + M1 = 0x7234 (X); + M2 = 0x7345 (X); + M3 = 0x7456 (X); + L0 = 0x7567 (X); + L1 = 0x7678 (X); + L2 = 0x7789 (X); + L3 = 0x789a (X); + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x00007123; + CHECKREG r1, 0x00007234; + CHECKREG r2, 0x00007345; + CHECKREG r3, 0x00007456; + CHECKREG r4, 0x00007567; + CHECKREG r5, 0x00007678; + CHECKREG r6, 0x00007789; + CHECKREG r7, 0x0000789A; + + M0 = -32768 (X); + M1 = -123 (X); + M2 = -234 (X); + M3 = -345 (X); + L0 = -456 (X); + L1 = -567 (X); + L2 = -667 (X); + L3 = -701 (X); + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0xFFFF8000; + CHECKREG r1, 0xFFFFFF85; + CHECKREG r2, 0xFFFFFF16; + CHECKREG r3, 0xFFFFFEA7; + CHECKREG r4, 0xFFFFFE38; + CHECKREG r5, 0xFFFFFDC9; + CHECKREG r6, 0xFFFFFD65; + CHECKREG r7, 0xFFFFFD43; + + M0 = 0x7aaa (X); + M1 = 0x7bbb (X); + M2 = 0x7ccc (X); + M3 = 0x7ddd (X); + L0 = 0x7eee (X); + L1 = 0x7fa8 (X); + L2 = 0x7fb9 (X); + L3 = 0x7fcc (X); + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = L0; + R5 = L1; + R6 = L2; + R7 = L3; + CHECKREG r0, 0x00007aaa; + CHECKREG r1, 0x00007bbb; + CHECKREG r2, 0x00007ccc; + CHECKREG r3, 0x00007ddd; + CHECKREG r4, 0x00007eee; + CHECKREG r5, 0x00007fa8; + CHECKREG r6, 0x00007fb9; + CHECKREG r7, 0x00007fcc; + + pass diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p.s new file mode 100644 index 0000000..1183e44 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p.s @@ -0,0 +1,372 @@ +//Original:/testcases/core/c_ldst_ld_d_p/c_ldst_ld_d_p.dsp +// Spec Reference: c_ldst ld d [p] +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ P5 ]; + R6 = [ FP ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x80818283; + CHECKREG r6, 0x00010203; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + R7 = [ P1 ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + R7 = [ P1 ]; + R0 = [ P2 ]; + CHECKREG r0, 0x20212223; + CHECKREG r1, 0x20212223; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + R7 = [ P1 ]; + R0 = [ P2 ]; + CHECKREG r0, 0x20212223; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R4 = [ P5 ]; + R5 = [ FP ]; + R7 = [ P1 ]; + R0 = [ P2 ]; + R2 = [ P4 ]; + CHECKREG r0, 0x20212223; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x60616263; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R5 = [ FP ]; + R7 = [ P1 ]; + R0 = [ P2 ]; + R2 = [ P4 ]; + R3 = [ P5 ]; + CHECKREG r0, 0x20212223; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x80818283; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R7 = [ P1 ]; + R0 = [ P2 ]; + R2 = [ P4 ]; + R3 = [ P5 ]; + R4 = [ FP ]; + CHECKREG r0, 0x20212223; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x80818283; + CHECKREG r4, 0x00010203; + CHECKREG r5, 0x00010203; + CHECKREG r7, 0x00010203; + + R7 = [ P1 ]; + R0 = [ P2 ]; + R2 = [ P4 ]; + R3 = [ P5 ]; + R4 = [ FP ]; + CHECKREG r0, 0x20212223; + CHECKREG r2, 0x60616263; + CHECKREG r3, 0x80818283; + CHECKREG r4, 0x00010203; + CHECKREG r6, 0x00010203; + CHECKREG r7, 0x00010203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_b.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_b.s new file mode 100644 index 0000000..369bb6d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_b.s @@ -0,0 +1,353 @@ +//Original:/testcases/core/c_ldst_ld_d_p_b/c_ldst_ld_d_p_b.dsp +// Spec Reference: c_ldst ld d [p] b +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// load 8 bits from memory, and zero extend into 32-bit reg + R0 = B [ P1 ] (Z); + R1 = B [ P2 ] (Z); +.ifndef BFIN_HOST + R2 = B [ P3 ] (Z); +.else + R2 = 0x43 (Z); +.endif + R3 = B [ P4 ] (Z); + R4 = B [ P5 ] (Z); + R5 = B [ P5 ] (Z); + R6 = B [ FP ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000063; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000083; + CHECKREG r6, 0x00000003; + R1 = B [ P2 ] (Z); +.ifndef BFIN_HOST + R2 = B [ P3 ] (Z); +.else + R2 = 0x43 (Z); +.endif + R3 = B [ P4 ] (Z); + R4 = B [ P5 ] (Z); + R5 = B [ FP ] (Z); + R7 = B [ P1 ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000063; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; +.ifndef BFIN_HOST + R2 = B [ P3 ] (Z); +.else + R2 = 0x43 (Z); +.endif + R3 = B [ P4 ] (Z); + R4 = B [ P5 ] (Z); + R5 = B [ FP ] (Z); + R7 = B [ P1 ] (Z); + R0 = B [ P2 ] (Z); + CHECKREG r0, 0x00000023; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000063; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + R3 = B [ P4 ] (Z); + R4 = B [ P5 ] (Z); + R5 = B [ FP ] (Z); + R7 = B [ P1 ] (Z); + R0 = B [ P2 ] (Z); +.ifndef BFIN_HOST + R1 = B [ P3 ] (Z); +.else + R1 = 0x43; +.endif + CHECKREG r0, 0x00000023; + CHECKREG r1, 0x00000043; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000063; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_h.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_h.s new file mode 100644 index 0000000..fb68de5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_h.s @@ -0,0 +1,351 @@ +//Original:/testcases/core/c_ldst_ld_d_p_h/c_ldst_ld_d_p_h.dsp +// Spec Reference: c_ldst ld d [p] h +# mach: bfin + +.include "testutils.inc" + start + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// load 16 bits from memory and zero extend into 32-bit reg + R0 = W [ P1 ] (Z); + R1 = W [ P2 ] (Z); +.ifndef BFIN_HOST + R2 = W [ P3 ] (Z); +.else + R2 = 0x4243(Z); +.endif + R3 = W [ P4 ] (Z); + R4 = W [ P5 ] (Z); + R5 = W [ P5 ] (Z); + R6 = W [ FP ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00008283; + CHECKREG r6, 0x00000203; + R1 = W [ P2 ] (Z); +.ifndef BFIN_HOST + R2 = W [ P3 ] (Z); +.else + R2 = 0x4243 (Z); +.endif + R3 = W [ P4 ] (Z); + R4 = W [ P5 ] (Z); + R5 = W [ FP ] (Z); + R7 = W [ P1 ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; +.ifndef BFIN_HOST + R2 = W [ P3 ] (Z); +.else + R2 = 0x4243 (Z); +.endif + R3 = W [ P4 ] (Z); + R4 = W [ P5 ] (Z); + R5 = W [ FP ] (Z); + R7 = W [ P1 ] (Z); + R0 = W [ P2 ] (Z); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + R3 = W [ P4 ] (Z); + R4 = W [ P5 ] (Z); + R5 = W [ FP ] (Z); + R7 = W [ P1 ] (Z); + R0 = W [ P2 ] (Z); +.ifndef BFIN_HOST + R1 = W [ P3 ] (Z); +.else + R1 = 0x4243 (Z); +.endif + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00006263; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm.s new file mode 100644 index 0000000..56e49a4 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm.s @@ -0,0 +1,417 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm/c_ldst_ld_d_p_mm.dsp +// Spec Reference: c_ldst ld d [p--] +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P5 -- ]; + R1 = [ P1 -- ]; + R2 = [ P2 -- ]; + R3 = [ P3 -- ]; + R4 = [ P4 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r0, 0x11223344; + CHECKREG r1, 0x91929394; + CHECKREG r2, 0xC9CACBCD; + CHECKREG r3, 0xEBECEDEE; + CHECKREG r4, 0x0F101213; + CHECKREG r5, 0x20212223; + CHECKREG r6, 0xA0A1A2A3; + R1 = [ P5 -- ]; + R2 = [ P1 -- ]; + R3 = [ P2 -- ]; + R4 = [ P3 -- ]; + R5 = [ P4 -- ]; + R6 = [ FP -- ]; + R7 = [ SP -- ]; + CHECKREG r0, 0x11223344; + CHECKREG r1, 0x1C1D1E1F; + CHECKREG r2, 0x3C3D3E3F; + CHECKREG r3, 0xC5C6C7C8; + CHECKREG r4, 0x7C7D7E7F; + CHECKREG r5, 0x9C9D9E9F; + CHECKREG r6, 0x1C1D1E1F; + CHECKREG r7, 0x9C9D9E9F; + R2 = [ P5 -- ]; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ FP -- ]; + R0 = [ SP -- ]; + CHECKREG r0, 0x98999A9B; + CHECKREG r1, 0x1C1D1E1F; + CHECKREG r2, 0x18191A1B; + CHECKREG r3, 0x38393A3B; + CHECKREG r4, 0x58595A5B; + CHECKREG r5, 0x78797A7B; + CHECKREG r6, 0x98999A9B; + CHECKREG r7, 0x18191A1B; + + R3 = [ P5 -- ]; + R4 = [ P1 -- ]; + R5 = [ P2 -- ]; + R6 = [ P3 -- ]; + R7 = [ P4 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r0, 0x14151617; + CHECKREG r1, 0x94959697; + CHECKREG r2, 0x18191A1B; + CHECKREG r3, 0x14151617; + CHECKREG r4, 0x34353637; + CHECKREG r5, 0x54555657; + CHECKREG r6, 0x74757677; + CHECKREG r7, 0x94959697; + + R4 = [ P5 -- ]; + R5 = [ P1 -- ]; + R6 = [ P2 -- ]; + R7 = [ P3 -- ]; + R0 = [ P4 -- ]; + R1 = [ FP -- ]; + R2 = [ SP -- ]; + CHECKREG r0, 0x90919293; + CHECKREG r1, 0x10111213; + CHECKREG r2, 0x90919293; + CHECKREG r3, 0x14151617; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x30313233; + CHECKREG r6, 0x50515253; + CHECKREG r7, 0x70717273; + + R5 = [ P5 -- ]; + R6 = [ P1 -- ]; + R7 = [ P2 -- ]; + R0 = [ P3 -- ]; + R1 = [ P4 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + CHECKREG r0, 0x6C6D6E6F; + CHECKREG r1, 0x8C8D8E8F; + CHECKREG r2, 0x0C0D0E0F; + CHECKREG r3, 0x8C8D8E8F; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x0C0D0E0F; + CHECKREG r6, 0x2C2D2E2F; + CHECKREG r7, 0x4C4D4E4F; + + R6 = [ P5 -- ]; + R7 = [ P1 -- ]; + R0 = [ P2 -- ]; + R1 = [ P3 -- ]; + R2 = [ P4 -- ]; + R3 = [ FP -- ]; + R4 = [ SP -- ]; + CHECKREG r0, 0x48494A4B; + CHECKREG r1, 0x68696A6B; + CHECKREG r2, 0x88898A8B; + CHECKREG r3, 0x08090A0B; + CHECKREG r4, 0x88898A8B; + CHECKREG r5, 0x0C0D0E0F; + CHECKREG r6, 0x08090A0B; + CHECKREG r7, 0x28292A2B; + + R7 = [ P5 -- ]; + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ FP -- ]; + R5 = [ SP -- ]; + CHECKREG r0, 0x24252627; + CHECKREG r1, 0x44454647; + CHECKREG r2, 0x64656667; + CHECKREG r3, 0x84858687; + CHECKREG r4, 0x04050607; + CHECKREG r5, 0x84858687; + CHECKREG r6, 0x08090A0B; + CHECKREG r7, 0x04050607; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_b.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_b.s new file mode 100644 index 0000000..f571553 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_b.s @@ -0,0 +1,353 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm_b/c_ldst_ld_d_p_mm_b.dsp +// Spec Reference: c_ldst ld d [p--] b +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x14; + loadsym p1, DATA_ADDR_2, 0x14; + loadsym p2, DATA_ADDR_3, 0x14; + loadsym i1, DATA_ADDR_4, 0x14; + loadsym p4, DATA_ADDR_5, 0x14; + loadsym fp, DATA_ADDR_6, 0x14; + loadsym i3, DATA_ADDR_7, 0x14; + P3 = I1; SP = I3; + + R0 = B [ P5 -- ] (Z); + R1 = B [ P1 -- ] (Z); + R2 = B [ P2 -- ] (Z); + R3 = B [ P3 -- ] (Z); + R4 = B [ P4 -- ] (Z); + R5 = B [ FP -- ] (Z); + R6 = B [ SP -- ] (Z); + CHECKREG r0, 0x00000017; + CHECKREG r1, 0x00000037; + CHECKREG r2, 0x00000057; + CHECKREG r3, 0x00000077; + CHECKREG r4, 0x00000097; + CHECKREG r5, 0x00000017; + CHECKREG r6, 0x00000097; + R1 = B [ P5 -- ] (Z); + R2 = B [ P1 -- ] (Z); + R3 = B [ P2 -- ] (Z); + R4 = B [ P3 -- ] (Z); + R5 = B [ P4 -- ] (Z); + R6 = B [ FP -- ] (Z); + R7 = B [ SP -- ] (Z); + CHECKREG r0, 0x00000017; + CHECKREG r1, 0x00000010; + CHECKREG r2, 0x00000030; + CHECKREG r3, 0x00000050; + CHECKREG r4, 0x00000070; + CHECKREG r5, 0x00000090; + CHECKREG r6, 0x00000010; + CHECKREG r7, 0x00000090; + R2 = B [ P5 -- ] (Z); + R3 = B [ P1 -- ] (Z); + R4 = B [ P2 -- ] (Z); + R5 = B [ P3 -- ] (Z); + R6 = B [ P4 -- ] (Z); + R7 = B [ FP -- ] (Z); + R0 = B [ SP -- ] (Z); + CHECKREG r0, 0x00000091; + CHECKREG r1, 0x00000010; + CHECKREG r2, 0x00000011; + CHECKREG r3, 0x00000031; + CHECKREG r4, 0x00000051; + CHECKREG r5, 0x00000071; + CHECKREG r6, 0x00000091; + CHECKREG r7, 0x00000011; + + R3 = B [ P5 -- ] (Z); + R4 = B [ P1 -- ] (Z); + R5 = B [ P2 -- ] (Z); + R6 = B [ P3 -- ] (Z); + R7 = B [ P4 -- ] (Z); + R0 = B [ FP -- ] (Z); + R1 = B [ SP -- ] (Z); + CHECKREG r0, 0x00000012; + CHECKREG r1, 0x00000092; + CHECKREG r2, 0x00000011; + CHECKREG r3, 0x00000012; + CHECKREG r4, 0x00000032; + CHECKREG r5, 0x00000052; + CHECKREG r6, 0x00000072; + CHECKREG r7, 0x00000092; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_h.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_h.s new file mode 100644 index 0000000..207f93a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_h.s @@ -0,0 +1,330 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm_h/c_ldst_ld_d_p_mm_h.dsp +// Spec Reference: c_ldst ld d [p--] h +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + +// initial values + loadsym p5, DATA_ADDR_1, 0x10; + loadsym p1, DATA_ADDR_2, 0x10; + loadsym p2, DATA_ADDR_3, 0x10; + loadsym p4, DATA_ADDR_5, 0x10; + loadsym fp, DATA_ADDR_6, 0x10; + + R0 = W [ P5 -- ] (Z); + R1 = W [ P1 -- ] (Z); + R2 = W [ P2 -- ] (Z); + R4 = W [ P4 -- ] (Z); + R5 = W [ FP -- ] (Z); + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00003233; + CHECKREG r2, 0x00005253; + CHECKREG r4, 0x00009293; + CHECKREG r5, 0x00001213; + R1 = W [ P5 -- ] (Z); + R2 = W [ P1 -- ] (Z); + R3 = W [ P2 -- ] (Z); + R5 = W [ P4 -- ] (Z); + R6 = W [ FP -- ] (Z); + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00000C0D; + CHECKREG r2, 0x00002C2D; + CHECKREG r3, 0x00004C4D; + CHECKREG r5, 0x00008C8D; + CHECKREG r6, 0x00000C0D; + R2 = W [ P5 -- ] (Z); + R3 = W [ P1 -- ] (Z); + R4 = W [ P2 -- ] (Z); + R6 = W [ P4 -- ] (Z); + R7 = W [ FP -- ] (Z); + CHECKREG r1, 0x00000C0D; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00002E2F; + CHECKREG r4, 0x00004E4F; + CHECKREG r6, 0x00008E8F; + CHECKREG r7, 0x00000E0F; + + R3 = W [ P5 -- ] (Z); + R4 = W [ P1 -- ] (Z); + R5 = W [ P2 -- ] (Z); + R7 = W [ P4 -- ] (Z); + R0 = W [ FP -- ] (Z); + CHECKREG r0, 0x00000809; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00002829; + CHECKREG r5, 0x00004849; + CHECKREG r7, 0x00008889; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xb.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xb.s new file mode 100644 index 0000000..e545ca8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xb.s @@ -0,0 +1,341 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm_xb/c_ldst_ld_d_p_mm_xb.dsp +// Spec Reference: c_ldst ld d [p--] xb + +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R5 = B [ P5 -- ] (X); + R6 = B [ P1 -- ] (X); + R7 = B [ P2 -- ] (X); + R0 = B [ P3 -- ] (X); + R1 = B [ P4 -- ] (X); + R2 = B [ FP -- ] (X); + R3 = B [ SP -- ] (X); + CHECKREG r0, 0xFFFFFFEE; + CHECKREG r1, 0x00000013; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0xFFFFFFA3; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000044; + CHECKREG r6, 0xFFFFFF94; + CHECKREG r7, 0xFFFFFFCD; + + R6 = B [ P5 -- ] (X); + R7 = B [ P1 -- ] (X); + R0 = B [ P2 -- ] (X); + R1 = B [ P3 -- ] (X); + R2 = B [ P4 -- ] (X); + R3 = B [ FP -- ] (X); + R4 = B [ SP -- ] (X); + CHECKREG r0, 0xFFFFFFC5; + CHECKREG r1, 0x0000007C; + CHECKREG r2, 0xFFFFFF9C; + CHECKREG r3, 0x0000001C; + CHECKREG r4, 0xFFFFFF9C; + CHECKREG r5, 0x00000044; + CHECKREG r6, 0x0000001C; + CHECKREG r7, 0x0000003C; + + R7 = B [ P5 -- ] (X); + R0 = B [ P1 -- ] (X); + R1 = B [ P2 -- ] (X); + R2 = B [ P3 -- ] (X); + R3 = B [ P4 -- ] (X); + R4 = B [ FP -- ] (X); + R5 = B [ SP -- ] (X); + CHECKREG r0, 0x0000003D; + CHECKREG r1, 0xFFFFFFC6; + CHECKREG r2, 0x0000007D; + CHECKREG r3, 0xFFFFFF9D; + CHECKREG r4, 0x0000001D; + CHECKREG r5, 0xFFFFFF9D; + CHECKREG r6, 0x0000001C; + CHECKREG r7, 0x0000001D; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xh.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xh.s new file mode 100644 index 0000000..16676a5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_mm_xh.s @@ -0,0 +1,355 @@ +//Original:testcases/core/c_ldst_ld_d_p_mm_xh/c_ldst_ld_d_p_mm_xh.dsp +// Spec Reference: c_ldst ld d [p++/--] h b xh xb +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x08; + loadsym p1, DATA_ADDR_2, 0x08; + loadsym p2, DATA_ADDR_3, 0x08; + loadsym i1, DATA_ADDR_4, 0x08; + loadsym p4, DATA_ADDR_5, 0x08; + loadsym fp, DATA_ADDR_6, 0x08; + loadsym i3, DATA_ADDR_7, 0x08; + P3 = I1; SP = I3; + + R4 = W [ P5 -- ] (X); + R5 = W [ P1 -- ] (X); + R6 = W [ P2 -- ] (X); + R7 = W [ P3 -- ] (X); + R0 = W [ P4 -- ] (X); + R1 = W [ FP -- ] (X); + R2 = W [ SP -- ] (X); + CHECKREG r0, 0xFFFF8A8B; + CHECKREG r1, 0x00000A0B; + CHECKREG r2, 0xFFFF8A8B; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0x00004A4B; + CHECKREG r7, 0x00006A6B; + + R5 = W [ P5 -- ] (X); + R6 = W [ P1 -- ] (X); + R7 = W [ P2 -- ] (X); + R0 = W [ P3 -- ] (X); + R1 = W [ P4 -- ] (X); + R2 = W [ FP -- ] (X); + R3 = W [ SP -- ] (X); + CHECKREG r0, 0x00006465; + CHECKREG r1, 0xFFFF8485; + CHECKREG r2, 0x00000405; + CHECKREG r3, 0xFFFF8485; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00004445; + + R6 = W [ P5 -- ] (X); + R7 = W [ P1 -- ] (X); + R0 = W [ P2 -- ] (X); + R1 = W [ P3 -- ] (X); + R2 = W [ P4 -- ] (X); + R3 = W [ FP -- ] (X); + R4 = W [ SP -- ] (X); + CHECKREG r0, 0x00004647; + CHECKREG r1, 0x00006667; + CHECKREG r2, 0xFFFF8687; + CHECKREG r3, 0x00000607; + CHECKREG r4, 0xFFFF8687; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00000607; + CHECKREG r7, 0x00002627; + + R7 = W [ P5 -- ] (X); + R0 = W [ P1 -- ] (X); + R1 = W [ P2 -- ] (X); + R2 = W [ P3 -- ] (X); + R3 = W [ P4 -- ] (X); + R4 = W [ FP -- ] (X); + R5 = W [ SP -- ] (X); + CHECKREG r0, 0x00002021; + CHECKREG r1, 0x00004041; + CHECKREG r2, 0x00006061; + CHECKREG r3, 0xFFFF8081; + CHECKREG r4, 0x00000001; + CHECKREG r5, 0xFFFF8081; + CHECKREG r6, 0x00000607; + CHECKREG r7, 0x00000001; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp.s new file mode 100644 index 0000000..c03ed68 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp.s @@ -0,0 +1,371 @@ +//Original:/testcases/core/c_ldst_ld_d_p_pp/c_ldst_ld_d_p_pp.dsp +// Spec Reference: c_ldst ld d [p++] +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = [ P5 ++ ]; + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x20212223; + CHECKREG r2, 0x40414243; + CHECKREG r4, 0x80818283; + CHECKREG r5, 0x00010203; + R1 = [ P5 ++ ]; + R2 = [ P1 ++ ]; + R3 = [ P2 ++ ]; + R5 = [ P4 ++ ]; + R6 = [ FP ++ ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x24252627; + CHECKREG r3, 0x44454647; + CHECKREG r5, 0x84858687; + CHECKREG r6, 0x04050607; + R2 = [ P5 ++ ]; + R3 = [ P1 ++ ]; + R4 = [ P2 ++ ]; + R6 = [ P4 ++ ]; + R7 = [ FP ++ ]; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x28292A2B; + CHECKREG r4, 0x48494A4B; + CHECKREG r6, 0x88898A8B; + CHECKREG r7, 0x08090A0B; + + R3 = [ P5 ++ ]; + R4 = [ P1 ++ ]; + R5 = [ P2 ++ ]; + R7 = [ P4 ++ ]; + R0 = [ FP ++ ]; + CHECKREG r0, 0x0C0D0E0F; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x2C2D2E2F; + CHECKREG r5, 0x4C4D4E4F; + CHECKREG r7, 0x8C8D8E8F; + + R4 = [ P5 ++ ]; + R5 = [ P1 ++ ]; + R6 = [ P2 ++ ]; + R0 = [ P4 ++ ]; + R1 = [ FP ++ ]; + CHECKREG r0, 0x90919293; + CHECKREG r1, 0x10111213; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x30313233; + CHECKREG r6, 0x50515253; + + R5 = [ P5 ++ ]; + R6 = [ P1 ++ ]; + R7 = [ P2 ++ ]; + R1 = [ P4 ++ ]; + R2 = [ FP ++ ]; + CHECKREG r1, 0x94959697; + CHECKREG r2, 0x14151617; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x34353637; + CHECKREG r7, 0x54555657; + + R6 = [ P5 ++ ]; + R7 = [ P1 ++ ]; + R0 = [ P2 ++ ]; + R2 = [ P4 ++ ]; + R3 = [ FP ++ ]; + CHECKREG r0, 0x58595A5B; + CHECKREG r2, 0x98999A9B; + CHECKREG r3, 0x18191A1B; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x18191A1B; + CHECKREG r7, 0x38393A3B; + + R7 = [ P5 ++ ]; + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ FP ++ ]; + CHECKREG r0, 0x3C3D3E3F; + CHECKREG r1, 0xC5C6C7C8; + CHECKREG r3, 0x9C9D9E9F; + CHECKREG r4, 0x1C1D1E1F; + CHECKREG r6, 0x18191A1B; + CHECKREG r7, 0x1C1D1E1F; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_b.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_b.s new file mode 100644 index 0000000..492ef3c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_b.s @@ -0,0 +1,324 @@ +//Original:/testcases/core/c_ldst_ld_d_p_pp_b/c_ldst_ld_d_p_pp_b.dsp +// Spec Reference: c_ldst ld d [p++] b +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = B [ P5 ++ ] (Z); + R1 = B [ P1 ++ ] (Z); + R2 = B [ P2 ++ ] (Z); + R4 = B [ P4 ++ ] (Z); + R5 = B [ FP ++ ] (Z); + + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + R1 = B [ P5 ++ ] (Z); + R2 = B [ P1 ++ ] (Z); + R3 = B [ P2 ++ ] (Z); + R5 = B [ P4 ++ ] (Z); + R6 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000022; + CHECKREG r3, 0x00000042; + CHECKREG r5, 0x00000082; + CHECKREG r6, 0x00000002; + R2 = B [ P5 ++ ] (Z); + R3 = B [ P1 ++ ] (Z); + R4 = B [ P2 ++ ] (Z); + R6 = B [ P4 ++ ] (Z); + R7 = B [ FP ++ ] (Z); + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000021; + CHECKREG r4, 0x00000041; + CHECKREG r6, 0x00000081; + CHECKREG r7, 0x00000001; + + R3 = B [ P5 ++ ] (Z); + R4 = B [ P1 ++ ] (Z); + R5 = B [ P2 ++ ] (Z); + R7 = B [ P4 ++ ] (Z); + R0 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000000; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000020; + CHECKREG r5, 0x00000040; + CHECKREG r7, 0x00000080; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_h.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_h.s new file mode 100644 index 0000000..b5bd84f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_h.s @@ -0,0 +1,350 @@ +//Original:/testcases/core/c_ldst_ld_d_p_pp_h/c_ldst_ld_d_p_pp_h.dsp +// Spec Reference: c_ldst ld d [p++] h +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_4; +.endif + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = W [ P5 ++ ] (Z); + R1 = W [ P1 ++ ] (Z); + R2 = W [ P2 ++ ] (Z); +.ifndef BFIN_HOST + R3 = W [ P3 ++ ] (Z); +.endif + R4 = W [ P4 ++ ] (Z); + R5 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; +.ifndef BFIN_HOST + CHECKREG r3, 0x00006263; +.endif + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + R1 = W [ P5 ++ ] (Z); + R2 = W [ P1 ++ ] (Z); + R3 = W [ P2 ++ ] (Z); +.ifndef BFIN_HOST + R4 = W [ P3 ++ ] (Z); +.endif + R5 = W [ P4 ++ ] (Z); + R6 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00002021; + CHECKREG r3, 0x00004041; +.ifndef BFIN_HOST + CHECKREG r4, 0x00006061; +.endif + CHECKREG r5, 0x00008081; + CHECKREG r6, 0x00000001; + R2 = W [ P5 ++ ] (Z); + R3 = W [ P1 ++ ] (Z); + R4 = W [ P2 ++ ] (Z); +.ifndef BFIN_HOST + R5 = W [ P3 ++ ] (Z); +.endif + R6 = W [ P4 ++ ] (Z); + R7 = W [ FP ++ ] (Z); + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00004647; +.ifndef BFIN_HOST + CHECKREG r5, 0x00006667; +.endif + CHECKREG r6, 0x00008687; + CHECKREG r7, 0x00000607; + + R3 = W [ P5 ++ ] (Z); + R4 = W [ P1 ++ ] (Z); + R5 = W [ P2 ++ ] (Z); +.ifndef BFIN_HOST + R6 = W [ P3 ++ ] (Z); +.endif + R7 = W [ P4 ++ ] (Z); + R0 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000405; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00000405; + CHECKREG r4, 0x00002425; +.ifndef BFIN_HOST + CHECKREG r5, 0x00004445; + CHECKREG r6, 0x00006465; +.endif + CHECKREG r7, 0x00008485; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xb.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xb.s new file mode 100644 index 0000000..834508b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xb.s @@ -0,0 +1,355 @@ +//Original:testcases/core/c_ldst_ld_d_p_pp_xb/c_ldst_ld_d_p_pp_xb.dsp +// Spec Reference: c_ldst ld d [p++] xb +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x04; + loadsym p1, DATA_ADDR_2, 0x04; + loadsym p2, DATA_ADDR_3, 0x04; + loadsym i1, DATA_ADDR_4, 0x04; + loadsym p4, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x04; + loadsym i3, DATA_ADDR_7, 0x04; + P3 = I1; SP = I3; + + R4 = B [ P5 ++ ] (X); + R5 = B [ P1 ++ ] (X); + R6 = B [ P2 ++ ] (X); + R7 = B [ P3 ++ ] (X); + R0 = B [ P4 ++ ] (X); + R1 = B [ FP ++ ] (X); + R2 = B [ SP ++ ] (X); + CHECKREG r0, 0xFFFFFF87; + CHECKREG r1, 0x00000007; + CHECKREG r2, 0xFFFFFF87; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000027; + CHECKREG r6, 0x00000047; + CHECKREG r7, 0x00000067; + + R5 = B [ P5 ++ ] (X); + R6 = B [ P1 ++ ] (X); + R7 = B [ P2 ++ ] (X); + R0 = B [ P3 ++ ] (X); + R1 = B [ P4 ++ ] (X); + R2 = B [ FP ++ ] (X); + R3 = B [ SP ++ ] (X); + CHECKREG r0, 0x00000066; + CHECKREG r1, 0xFFFFFF86; + CHECKREG r2, 0x00000006; + CHECKREG r3, 0xFFFFFF86; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000026; + CHECKREG r7, 0x00000046; + + R6 = B [ P5 ++ ] (X); + R7 = B [ P1 ++ ] (X); + R0 = B [ P2 ++ ] (X); + R1 = B [ P3 ++ ] (X); + R2 = B [ P4 ++ ] (X); + R3 = B [ FP ++ ] (X); + R4 = B [ SP ++ ] (X); + CHECKREG r0, 0x00000045; + CHECKREG r1, 0x00000065; + CHECKREG r2, 0xFFFFFF85; + CHECKREG r3, 0x00000005; + CHECKREG r4, 0xFFFFFF85; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000005; + CHECKREG r7, 0x00000025; + + R7 = B [ P5 ++ ] (X); + R0 = B [ P1 ++ ] (X); + R1 = B [ P2 ++ ] (X); + R2 = B [ P3 ++ ] (X); + R3 = B [ P4 ++ ] (X); + R4 = B [ FP ++ ] (X); + R5 = B [ SP ++ ] (X); + CHECKREG r0, 0x00000024; + CHECKREG r1, 0x00000044; + CHECKREG r2, 0x00000064; + CHECKREG r3, 0xFFFFFF84; + CHECKREG r4, 0x00000004; + CHECKREG r5, 0xFFFFFF84; + CHECKREG r6, 0x00000005; + CHECKREG r7, 0x00000004; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xh.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xh.s new file mode 100644 index 0000000..bab5d78 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_pp_xh.s @@ -0,0 +1,333 @@ +//Original:testcases/core/c_ldst_ld_d_p_pp_xh/c_ldst_ld_d_p_pp_xh.dsp +// Spec Reference: c_ldst ld d [p++] xh +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; + +// initial values + loadsym p5, DATA_ADDR_1, 0x08; + loadsym p1, DATA_ADDR_2, 0x08; + loadsym p2, DATA_ADDR_3, 0x08; + loadsym p4, DATA_ADDR_5, 0x08; + loadsym fp, DATA_ADDR_6, 0x08; + + R4 = W [ P5 ++ ] (X); + R5 = W [ P1 ++ ] (X); + R6 = W [ P2 ++ ] (X); + R0 = W [ P4 ++ ] (X); + R1 = W [ FP ++ ] (X); + CHECKREG r0, 0xFFFF8A8B; + CHECKREG r1, 0x00000A0B; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0x00004A4B; + + R5 = W [ P5 ++ ] (X); + R6 = W [ P1 ++ ] (X); + R7 = W [ P2 ++ ] (X); + R1 = W [ P4 ++ ] (X); + R2 = W [ FP ++ ] (X); + CHECKREG r1, 0xFFFF8889; + CHECKREG r2, 0x00000809; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00002829; + CHECKREG r7, 0x00004849; + + R6 = W [ P5 ++ ] (X); + R7 = W [ P1 ++ ] (X); + R0 = W [ P2 ++ ] (X); + R2 = W [ P4 ++ ] (X); + R3 = W [ FP ++ ] (X); + CHECKREG r0, 0x00004E4F; + CHECKREG r2, 0xFFFF8E8F; + CHECKREG r3, 0x00000E0F; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00000E0F; + CHECKREG r7, 0x00002E2F; + + R7 = W [ P5 ++ ] (X); + R0 = W [ P1 ++ ] (X); + R1 = W [ P2 ++ ] (X); + R3 = W [ P4 ++ ] (X); + R4 = W [ FP ++ ] (X); + CHECKREG r0, 0x00002C2D; + CHECKREG r1, 0x00004C4D; + CHECKREG r3, 0xFFFF8C8D; + CHECKREG r4, 0x00000C0D; + CHECKREG r6, 0x00000E0F; + CHECKREG r7, 0x00000C0D; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_ppmm_hbx.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_ppmm_hbx.s new file mode 100644 index 0000000..f782e83 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_ppmm_hbx.s @@ -0,0 +1,656 @@ +//Original:/testcases/core/c_ldst_ld_d_p_ppmm_hbx/c_ldst_ld_d_p_ppmm_hbx.dsp +// Spec Reference: c_ldst ld d [p++/--] h b xh xb +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = W [ P5 ++ ] (Z); + R1 = W [ P1 ++ ] (Z); + R2 = W [ P2 ++ ] (Z); + R4 = W [ P4 ++ ] (Z); + R5 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00002223; + CHECKREG r2, 0x00004243; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00000203; + R1 = W [ P5 ++ ] (Z); + R2 = W [ P1 ++ ] (Z); + R3 = W [ P2 ++ ] (Z); + R5 = W [ P4 ++ ] (Z); + R6 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00002021; + CHECKREG r3, 0x00004041; + CHECKREG r5, 0x00008081; + CHECKREG r6, 0x00000001; + R2 = W [ P5 ++ ] (Z); + R3 = W [ P1 ++ ] (Z); + R4 = W [ P2 ++ ] (Z); + R6 = W [ P4 ++ ] (Z); + R7 = W [ FP ++ ] (Z); + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00004647; + CHECKREG r6, 0x00008687; + CHECKREG r7, 0x00000607; + + R3 = W [ P5 ++ ] (Z); + R4 = W [ P1 ++ ] (Z); + R5 = W [ P2 ++ ] (Z); + R7 = W [ P4 ++ ] (Z); + R0 = W [ FP ++ ] (Z); + CHECKREG r0, 0x00000405; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00000405; + CHECKREG r4, 0x00002425; + CHECKREG r5, 0x00004445; + CHECKREG r7, 0x00008485; + + R4 = W [ P5 ++ ] (X); + R5 = W [ P1 ++ ] (X); + R6 = W [ P2 ++ ] (X); + R0 = W [ P4 ++ ] (X); + R1 = W [ FP ++ ] (X); + CHECKREG r0, 0xFFFF8A8B; + CHECKREG r1, 0x00000A0B; + CHECKREG r3, 0x00000405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0x00004A4B; + + R5 = W [ P5 ++ ] (X); + R6 = W [ P1 ++ ] (X); + R7 = W [ P2 ++ ] (X); + R1 = W [ P4 ++ ] (X); + R2 = W [ FP ++ ] (X); + CHECKREG r1, 0xFFFF8889; + CHECKREG r2, 0x00000809; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00002829; + CHECKREG r7, 0x00004849; + + R6 = W [ P5 ++ ] (X); + R7 = W [ P1 ++ ] (X); + R0 = W [ P2 ++ ] (X); + R2 = W [ P4 ++ ] (X); + R3 = W [ FP ++ ] (X); + CHECKREG r0, 0x00004E4F; + CHECKREG r2, 0xFFFF8E8F; + CHECKREG r3, 0x00000E0F; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00000E0F; + CHECKREG r7, 0x00002E2F; + + R7 = W [ P5 ++ ] (X); + R0 = W [ P1 ++ ] (X); + R1 = W [ P2 ++ ] (X); + R3 = W [ P4 ++ ] (X); + R4 = W [ FP ++ ] (X); + CHECKREG r0, 0x00002C2D; + CHECKREG r1, 0x00004C4D; + CHECKREG r3, 0xFFFF8C8D; + CHECKREG r4, 0x00000C0D; + CHECKREG r6, 0x00000E0F; + CHECKREG r7, 0x00000C0D; + + R0 = W [ P5 -- ] (Z); + R1 = W [ P1 -- ] (Z); + R2 = W [ P2 -- ] (Z); + R4 = W [ P4 -- ] (Z); + R5 = W [ FP -- ] (Z); + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00003233; + CHECKREG r2, 0x00005253; + CHECKREG r4, 0x00009293; + CHECKREG r5, 0x00001213; + R1 = W [ P5 -- ] (Z); + R2 = W [ P1 -- ] (Z); + R3 = W [ P2 -- ] (Z); + R5 = W [ P4 -- ] (Z); + R6 = W [ FP -- ] (Z); + CHECKREG r0, 0x00001213; + CHECKREG r1, 0x00000C0D; + CHECKREG r2, 0x00002C2D; + CHECKREG r3, 0x00004C4D; + CHECKREG r5, 0x00008C8D; + CHECKREG r6, 0x00000C0D; + R2 = W [ P5 -- ] (Z); + R3 = W [ P1 -- ] (Z); + R4 = W [ P2 -- ] (Z); + R6 = W [ P4 -- ] (Z); + R7 = W [ FP -- ] (Z); + CHECKREG r1, 0x00000C0D; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00002E2F; + CHECKREG r4, 0x00004E4F; + CHECKREG r6, 0x00008E8F; + CHECKREG r7, 0x00000E0F; + + R3 = W [ P5 -- ] (Z); + R4 = W [ P1 -- ] (Z); + R5 = W [ P2 -- ] (Z); + R7 = W [ P4 -- ] (Z); + R0 = W [ FP -- ] (Z); + CHECKREG r0, 0x00000809; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00002829; + CHECKREG r5, 0x00004849; + CHECKREG r7, 0x00008889; + + R4 = W [ P5 -- ] (X); + R5 = W [ P1 -- ] (X); + R6 = W [ P2 -- ] (X); + R0 = W [ P4 -- ] (X); + R1 = W [ FP -- ] (X); + CHECKREG r0, 0xFFFF8A8B; + CHECKREG r1, 0x00000A0B; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0x00004A4B; + + R5 = W [ P5 -- ] (X); + R6 = W [ P1 -- ] (X); + R7 = W [ P2 -- ] (X); + R1 = W [ P4 -- ] (X); + R2 = W [ FP -- ] (X); + CHECKREG r1, 0xFFFF8485; + CHECKREG r2, 0x00000405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00004445; + + R6 = W [ P5 -- ] (X); + R7 = W [ P1 -- ] (X); + R0 = W [ P2 -- ] (X); + R2 = W [ P4 -- ] (X); + R3 = W [ FP -- ] (X); + CHECKREG r0, 0x00004647; + CHECKREG r2, 0xFFFF8687; + CHECKREG r3, 0x00000607; + CHECKREG r5, 0x00000405; + CHECKREG r6, 0x00000607; + CHECKREG r7, 0x00002627; + + R7 = W [ P5 -- ] (X); + R0 = W [ P1 -- ] (X); + R1 = W [ P2 -- ] (X); + R3 = W [ P4 -- ] (X); + R4 = W [ FP -- ] (X); + CHECKREG r0, 0x00002021; + CHECKREG r1, 0x00004041; + CHECKREG r3, 0xFFFF8081; + CHECKREG r4, 0x00000001; + CHECKREG r6, 0x00000607; + CHECKREG r7, 0x00000001; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + R0 = B [ P5 ++ ] (Z); + R1 = B [ P1 ++ ] (Z); + R2 = B [ P2 ++ ] (Z); + R4 = B [ P4 ++ ] (Z); + R5 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000023; + CHECKREG r2, 0x00000043; + CHECKREG r4, 0x00000083; + CHECKREG r5, 0x00000003; + R1 = B [ P5 ++ ] (Z); + R2 = B [ P1 ++ ] (Z); + R3 = B [ P2 ++ ] (Z); + R5 = B [ P4 ++ ] (Z); + R6 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000003; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000022; + CHECKREG r3, 0x00000042; + CHECKREG r5, 0x00000082; + CHECKREG r6, 0x00000002; + R2 = B [ P5 ++ ] (Z); + R3 = B [ P1 ++ ] (Z); + R4 = B [ P2 ++ ] (Z); + R6 = B [ P4 ++ ] (Z); + R7 = B [ FP ++ ] (Z); + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000021; + CHECKREG r4, 0x00000041; + CHECKREG r6, 0x00000081; + CHECKREG r7, 0x00000001; + + R3 = B [ P5 ++ ] (Z); + R4 = B [ P1 ++ ] (Z); + R5 = B [ P2 ++ ] (Z); + R7 = B [ P4 ++ ] (Z); + R0 = B [ FP ++ ] (Z); + CHECKREG r0, 0x00000000; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000020; + CHECKREG r5, 0x00000040; + CHECKREG r7, 0x00000080; + + R4 = B [ P5 ++ ] (X); + R5 = B [ P1 ++ ] (X); + R6 = B [ P2 ++ ] (X); + R0 = B [ P4 ++ ] (X); + R1 = B [ FP ++ ] (X); + CHECKREG r0, 0xFFFFFF87; + CHECKREG r1, 0x00000007; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000027; + CHECKREG r6, 0x00000047; + + R5 = B [ P5 ++ ] (X); + R6 = B [ P1 ++ ] (X); + R7 = B [ P2 ++ ] (X); + R1 = B [ P4 ++ ] (X); + R2 = B [ FP ++ ] (X); + CHECKREG r1, 0xFFFFFF86; + CHECKREG r2, 0x00000006; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000026; + CHECKREG r7, 0x00000046; + + R6 = B [ P5 ++ ] (X); + R7 = B [ P1 ++ ] (X); + R0 = B [ P2 ++ ] (X); + R2 = B [ P4 ++ ] (X); + R3 = B [ FP ++ ] (X); + CHECKREG r0, 0x00000045; + CHECKREG r2, 0xFFFFFF85; + CHECKREG r3, 0x00000005; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000005; + CHECKREG r7, 0x00000025; + + R7 = B [ P5 ++ ] (X); + R0 = B [ P1 ++ ] (X); + R1 = B [ P2 ++ ] (X); + R3 = B [ P4 ++ ] (X); + R4 = B [ FP ++ ] (X); + CHECKREG r0, 0x00000024; + CHECKREG r1, 0x00000044; + CHECKREG r3, 0xFFFFFF84; + CHECKREG r4, 0x00000004; + CHECKREG r6, 0x00000005; + CHECKREG r7, 0x00000004; + + R0 = B [ P5 -- ] (Z); + R1 = B [ P1 -- ] (Z); + R2 = B [ P2 -- ] (Z); + R4 = B [ P4 -- ] (Z); + R5 = B [ FP -- ] (Z); + CHECKREG r0, 0x0000000B; + CHECKREG r1, 0x0000002B; + CHECKREG r2, 0x0000004B; + CHECKREG r4, 0x0000008B; + CHECKREG r5, 0x0000000B; + R1 = B [ P5 -- ] (Z); + R2 = B [ P1 -- ] (Z); + R3 = B [ P2 -- ] (Z); + R5 = B [ P4 -- ] (Z); + R6 = B [ FP -- ] (Z); + CHECKREG r0, 0x0000000B; + CHECKREG r1, 0x00000004; + CHECKREG r2, 0x00000024; + CHECKREG r3, 0x00000044; + CHECKREG r5, 0x00000084; + CHECKREG r6, 0x00000004; + R2 = B [ P5 -- ] (Z); + R3 = B [ P1 -- ] (Z); + R4 = B [ P2 -- ] (Z); + R6 = B [ P4 -- ] (Z); + R7 = B [ FP -- ] (Z); + CHECKREG r1, 0x00000004; + CHECKREG r2, 0x00000005; + CHECKREG r3, 0x00000025; + CHECKREG r4, 0x00000045; + CHECKREG r6, 0x00000085; + CHECKREG r7, 0x00000005; + + R3 = B [ P5 -- ] (Z); + R4 = B [ P1 -- ] (Z); + R5 = B [ P2 -- ] (Z); + R7 = B [ P4 -- ] (Z); + R0 = B [ FP -- ] (Z); + CHECKREG r0, 0x00000006; + CHECKREG r2, 0x00000005; + CHECKREG r3, 0x00000006; + CHECKREG r4, 0x00000026; + CHECKREG r5, 0x00000046; + CHECKREG r7, 0x00000086; + + R4 = B [ P5 -- ] (X); + R5 = B [ P1 -- ] (X); + R6 = B [ P2 -- ] (X); + R0 = B [ P4 -- ] (X); + R1 = B [ FP -- ] (X); + CHECKREG r0, 0xFFFFFF87; + CHECKREG r1, 0x00000007; + CHECKREG r3, 0x00000006; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000027; + CHECKREG r6, 0x00000047; + + R5 = B [ P5 -- ] (X); + R6 = B [ P1 -- ] (X); + R7 = B [ P2 -- ] (X); + R1 = B [ P4 -- ] (X); + R2 = B [ FP -- ] (X); + CHECKREG r1, 0xFFFFFF80; + CHECKREG r2, 0x00000000; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000020; + CHECKREG r7, 0x00000040; + + R6 = B [ P5 -- ] (X); + R7 = B [ P1 -- ] (X); + R0 = B [ P2 -- ] (X); + R2 = B [ P4 -- ] (X); + R3 = B [ FP -- ] (X); + CHECKREG r0, 0x00000041; + CHECKREG r2, 0xFFFFFF81; + CHECKREG r3, 0x00000001; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000001; + CHECKREG r7, 0x00000021; + + R7 = B [ P5 -- ] (X); + R0 = B [ P1 -- ] (X); + R1 = B [ P2 -- ] (X); + R3 = B [ P4 -- ] (X); + R4 = B [ FP -- ] (X); + CHECKREG r0, 0x00000022; + CHECKREG r1, 0x00000042; + CHECKREG r3, 0xFFFFFF82; + CHECKREG r4, 0x00000002; + CHECKREG r6, 0x00000001; + CHECKREG r7, 0x00000002; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xb.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xb.s new file mode 100644 index 0000000..2337a7a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xb.s @@ -0,0 +1,326 @@ +//Original:/testcases/core/c_ldst_ld_d_p_xb/c_ldst_ld_d_p_xb.dsp +// Spec Reference: c_ldst ld d [p] xb +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// load 8 bits from memory & sign extend into 32-bit reg + R4 = B [ P5 ] (X); + R5 = B [ FP ] (X); + R7 = B [ P1 ] (X); + R0 = B [ P2 ] (X); + R2 = B [ P4 ] (X); + CHECKREG r0, 0x00000023; + CHECKREG r2, 0x00000063; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0xFFFFFF83; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + R5 = B [ FP ] (X); + R7 = B [ P1 ] (X); + R0 = B [ P2 ] (X); + R2 = B [ P4 ] (X); + R3 = B [ P5 ] (X); + CHECKREG r0, 0x00000023; + CHECKREG r2, 0x00000063; + CHECKREG r3, 0xFFFFFF83; + CHECKREG r4, 0xFFFFFF83; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + R7 = B [ P1 ] (X); + R0 = B [ P2 ] (X); + R2 = B [ P4 ] (X); + R3 = B [ P5 ] (X); + R4 = B [ FP ] (X); + CHECKREG r0, 0x00000023; + CHECKREG r2, 0x00000063; + CHECKREG r3, 0xFFFFFF83; + CHECKREG r4, 0x00000003; + CHECKREG r5, 0x00000003; + CHECKREG r7, 0x00000003; + + R7 = B [ P1 ] (X); + R0 = B [ P2 ] (X); + R2 = B [ P4 ] (X); + R3 = B [ P5 ] (X); + R4 = B [ FP ] (X); + CHECKREG r0, 0x00000023; + CHECKREG r2, 0x00000063; + CHECKREG r3, 0xFFFFFF83; + CHECKREG r4, 0x00000003; + CHECKREG r7, 0x00000003; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xh.s b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xh.s new file mode 100644 index 0000000..480a98d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_d_p_xh.s @@ -0,0 +1,354 @@ +//Original:/testcases/core/c_ldst_ld_d_p_xh/c_ldst_ld_d_p_xh.dsp +// Spec Reference: c_ldst ld d [p] xh +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// load 16 bits from memory and sign extend into 32-bit reg + R4 = W [ P5 ] (X); + R5 = W [ FP ] (X); + R7 = W [ P1 ] (X); + R0 = W [ P2 ] (X); +.ifndef BFIN_HOST + R1 = W [ P3 ] (X); +.else + imm32 r1, 0x00004243; +.endif + R2 = W [ P4 ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0xFFFF8283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + R5 = W [ FP ] (X); + R7 = W [ P1 ] (X); + R0 = W [ P2 ] (X); +.ifndef BFIN_HOST + R1 = W [ P3 ] (X); +.else + imm32 R1, 0x00004243; +.endif + R2 = W [ P4 ] (X); + R3 = W [ P5 ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0xFFFF8283; + CHECKREG r4, 0xFFFF8283; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + R7 = W [ P1 ] (X); + R0 = W [ P2 ] (X); +.ifndef BFIN_HOST + R1 = W [ P3 ] (X); +.else + imm32 R1, 0x00004243; +.endif + R2 = W [ P4 ] (X); + R3 = W [ P5 ] (X); + R4 = W [ FP ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0xFFFF8283; + CHECKREG r4, 0x00000203; + CHECKREG r5, 0x00000203; + CHECKREG r7, 0x00000203; + + R7 = W [ P1 ] (X); + R0 = W [ P2 ] (X); +.ifndef BFIN_HOST + R1 = W [ P3 ] (X); +.else + imm32 R1, 0x00004243; +.endif + R2 = W [ P4 ] (X); + R3 = W [ P5 ] (X); + R4 = W [ FP ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00004243; + CHECKREG r2, 0x00006263; + CHECKREG r3, 0xFFFF8283; + CHECKREG r4, 0x00000203; + CHECKREG r7, 0x00000203; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_p_p.s b/sim/testsuite/sim/bfin/c_ldst_ld_p_p.s new file mode 100644 index 0000000..96658b5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_p_p.s @@ -0,0 +1,327 @@ +//Original:/testcases/core/c_ldst_ld_p_p/c_ldst_ld_p_p.dsp +// Spec Reference: c_ldst ld p [p] +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + P2 = [ P1 ]; + P4 = [ P1 ]; + P5 = [ P1 ]; + FP = [ P1 ]; + CHECKREG p2, 0x78910213; + CHECKREG p4, 0x78910213; + CHECKREG p5, 0x78910213; + CHECKREG fp, 0x78910213; + + loadsym p2, DATA_ADDR_2; + P1 = [ P2 ]; + P4 = [ P2 ]; + P5 = [ P2 ]; + FP = [ P2 ]; + CHECKREG p1, 0x20212223; + CHECKREG p4, 0x20212223; + CHECKREG p5, 0x20212223; + CHECKREG fp, 0x20212223; + + loadsym p4, DATA_ADDR_4; + P1 = [ P4 ]; + P2 = [ P4 ]; + P5 = [ P4 ]; + FP = [ P4 ]; + CHECKREG p1, 0x60616263; + CHECKREG p2, 0x60616263; + CHECKREG p5, 0x60616263; + CHECKREG fp, 0x60616263; + + loadsym p5, DATA_ADDR_5; + P1 = [ P5 ]; + P2 = [ P5 ]; + P4 = [ P5 ]; + FP = [ P5 ]; + CHECKREG p1, 0x8A8B8C8D; + CHECKREG p2, 0x8A8B8C8D; + CHECKREG p4, 0x8A8B8C8D; + CHECKREG fp, 0x8A8B8C8D; + + loadsym fp, DATA_ADDR_7; + P1 = [ FP ]; + P2 = [ FP ]; + P4 = [ FP ]; + P5 = [ FP ]; + CHECKREG p1, 0x80818283; + CHECKREG p2, 0x80818283; + CHECKREG p4, 0x80818283; + CHECKREG p5, 0x80818283; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x78910213 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x8A8B8C8D + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_p_p_mm.s b/sim/testsuite/sim/bfin/c_ldst_ld_p_p_mm.s new file mode 100644 index 0000000..75471c8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_p_p_mm.s @@ -0,0 +1,406 @@ +//Original:testcases/core/c_ldst_ld_p_p_mm/c_ldst_ld_p_p_mm.dsp +// Spec Reference: c_ldst ld p [p--] +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x18; + loadsym p2, DATA_ADDR_2, 0x18; + loadsym i1, DATA_ADDR_3, 0x18; + loadsym p4, DATA_ADDR_4, 0x18; + loadsym p5, DATA_ADDR_5, 0x18; + loadsym fp, DATA_ADDR_6, 0x18; + loadsym i3, DATA_ADDR_7, 0x18; + P3 = I1; SP = I3; + + P2 = [ P1 -- ]; + P3 = [ P1 -- ]; + P4 = [ P1 -- ]; + P5 = [ P1 -- ]; + SP = [ P1 -- ]; + FP = [ P1 -- ]; + CHECKREG p2, 0x18191A1B; + CHECKREG p3, 0x14151617; + CHECKREG p4, 0x10111213; + CHECKREG p5, 0x0C0D0E0F; + CHECKREG sp, 0x08090A0B; + CHECKREG fp, 0x04050607; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x18; + P3 = I1; SP = I3; + + P1 = [ P2 -- ]; + P3 = [ P2 -- ]; + P4 = [ P2 -- ]; + P5 = [ P2 -- ]; + SP = [ P2 -- ]; + FP = [ P2 -- ]; + CHECKREG p1, 0x38393A3B; + CHECKREG p3, 0x34353637; + CHECKREG p4, 0x30313233; + CHECKREG p5, 0x2C2D2E2F; + CHECKREG sp, 0x28292A2B; + CHECKREG fp, 0x24252627; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x18; + P3 = I1; SP = I3; + + P1 = [ P3 -- ]; + P2 = [ P3 -- ]; + P4 = [ P3 -- ]; + P5 = [ P3 -- ]; + SP = [ P3 -- ]; + FP = [ P3 -- ]; + CHECKREG p1, 0x58595A5B; + CHECKREG p2, 0x54555657; + CHECKREG p4, 0x50515253; + CHECKREG p5, 0x4C4D4E4F; + CHECKREG sp, 0x48494A4B; + CHECKREG fp, 0x44454647; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x18; + P3 = I1; SP = I3; + + P1 = [ P4 -- ]; + P2 = [ P4 -- ]; + P3 = [ P4 -- ]; + P5 = [ P4 -- ]; + SP = [ P4 -- ]; + FP = [ P4 -- ]; + CHECKREG p1, 0x78797A7B; + CHECKREG p2, 0x74757677; + CHECKREG p3, 0x70717273; + CHECKREG p5, 0x6C6D6E6F; + CHECKREG sp, 0x68696A6B; + CHECKREG fp, 0x64656667; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x18; + P3 = I1; SP = I3; + + P1 = [ P5 -- ]; + P2 = [ P5 -- ]; + P3 = [ P5 -- ]; + P4 = [ P5 -- ]; + SP = [ P5 -- ]; + FP = [ P5 -- ]; + CHECKREG p1, 0x98999A9B; + CHECKREG p2, 0x94959697; + CHECKREG p3, 0x90919293; + CHECKREG p4, 0x8C8D8E8F; + CHECKREG sp, 0x88898A8B; + CHECKREG fp, 0x84858687; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x18; + P3 = I1; SP = I3; + + P1 = [ SP -- ]; + P2 = [ SP -- ]; + P3 = [ SP -- ]; + P4 = [ SP -- ]; + P5 = [ SP -- ]; + FP = [ SP -- ]; + CHECKREG p1, 0x18191A1B; + CHECKREG p2, 0x14151617; + CHECKREG p3, 0x10111213; + CHECKREG p4, 0x0C0D0E0F; + CHECKREG p5, 0x08090A0B; + CHECKREG fp, 0x04050607; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x18; + P3 = I1; SP = I3; + + P1 = [ FP -- ]; + P2 = [ FP -- ]; + P3 = [ FP -- ]; + P4 = [ FP -- ]; + P5 = [ FP -- ]; + SP = [ FP -- ]; + CHECKREG p1, 0x98999A9B; + CHECKREG p2, 0x94959697; + CHECKREG p3, 0x90919293; + CHECKREG p4, 0x8C8D8E8F; + CHECKREG p5, 0x88898A8B; + CHECKREG sp, 0x84858687; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x78910213 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x8A8B8C8D + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_ld_p_p_pp.s b/sim/testsuite/sim/bfin/c_ldst_ld_p_p_pp.s new file mode 100644 index 0000000..c66440a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_ld_p_p_pp.s @@ -0,0 +1,335 @@ +//Original:/testcases/core/c_ldst_ld_p_p_pp/c_ldst_ld_p_p_pp.dsp +// Spec Reference: c_ldst ld p [p++] +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + P2 = [ P1 ++ ]; + P1 += 4; + P4 = [ P1 ++ ]; + P5 = [ P1 ++ ]; + P1 += 4; + FP = [ P1 ++ ]; + CHECKREG p2, 0x78910213; + CHECKREG p4, 0x08090A0B; + CHECKREG p5, 0x0C0D0E0F; + CHECKREG fp, 0x14151617; + + loadsym p2, DATA_ADDR_2; + P1 = [ P2 ++ ]; + P2 += 4; + P4 = [ P2 ++ ]; + P5 = [ P2 ++ ]; + P2 += 4; + FP = [ P2 ++ ]; + CHECKREG p1, 0x20212223; + CHECKREG p4, 0x28292A2B; + CHECKREG p5, 0x2C2D2E2F; + CHECKREG fp, 0x34353637; + + loadsym p4, DATA_ADDR_4; + P1 = [ P4 ++ ]; + P2 = [ P4 ++ ]; + P4 += 4; + P5 = [ P4 ++ ]; + P4 += 4; + FP = [ P4 ++ ]; + CHECKREG p1, 0x60616263; + CHECKREG p2, 0x64656667; + CHECKREG p5, 0x6C6D6E6F; + CHECKREG fp, 0x74757677; + + loadsym p5, DATA_ADDR_5; + P1 = [ P5 ++ ]; + P2 = [ P5 ++ ]; + P5 += 4; + P4 = [ P5 ++ ]; + P5 += 4; + FP = [ P5 ++ ]; + CHECKREG p1, 0x8A8B8C8D; + CHECKREG p2, 0x84858687; + CHECKREG p4, 0x8C8D8E8F; + CHECKREG fp, 0x94959697; + + loadsym fp, DATA_ADDR_7; + P1 = [ FP ++ ]; + P2 = [ FP ++ ]; + FP += 4; + P4 = [ FP ++ ]; + P5 = [ FP ++ ]; + CHECKREG p1, 0x80818283; + CHECKREG p2, 0x84858687; + CHECKREG p4, 0x8C8D8E8F; + CHECKREG p5, 0x90919293; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data +DATA_ADDR_1: + .dd 0x78910213 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xAB0CAD0E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x8A8B8C8D + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d.s new file mode 100644 index 0000000..504b027 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_st_p_d.s @@ -0,0 +1,299 @@ +//Original:/testcases/core/c_ldst_st_p_d/c_ldst_st_p_d.dsp +// Spec Reference: c_ldst st_p_d +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + [ P5 ] = R0; + [ P1 ] = R1; + [ P2 ] = R2; + [ P4 ] = R4; + [ FP ] = R5; + + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x0A231507; + CHECKREG r5, 0x5F786A5C; + CHECKREG r7, 0x719A8C7E; + + imm32 r0, 0x1a231507; + imm32 r1, 0x12342618; + imm32 r2, 0x2c353729; + imm32 r3, 0x3d54483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f78665c; + imm32 r6, 0x60897b7d; + imm32 r7, 0x719a8c78; + [ P5 ] = R1; + [ P1 ] = R2; + [ P2 ] = R3; + [ P4 ] = R5; + [ FP ] = R6; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2C353729; + CHECKREG r1, 0x3D54483A; + CHECKREG r3, 0x5F78665C; + CHECKREG r4, 0x12342618; + CHECKREG r5, 0x60897B7D; + CHECKREG r7, 0x719A8C78; + + imm32 r0, 0x2a231507; + imm32 r1, 0x12342618; + imm32 r2, 0x2c253729; + imm32 r3, 0x3d52483a; + imm32 r4, 0x4e67294b; + imm32 r5, 0x5f78625c; + imm32 r6, 0x60897b2d; + imm32 r7, 0x719a8c72; + [ P5 ] = R2; + [ P1 ] = R3; + [ P2 ] = R4; + [ P4 ] = R6; + [ FP ] = R7; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x3D52483A; + CHECKREG r1, 0x4E67294B; + CHECKREG r3, 0x60897B2D; + CHECKREG r4, 0x2C253729; + CHECKREG r5, 0x719A8C72; + CHECKREG r7, 0x719A8C72; + + imm32 r0, 0x3a231507; + imm32 r1, 0x13342618; + imm32 r2, 0x2c353729; + imm32 r3, 0x3d53483a; + imm32 r4, 0x4e67394b; + imm32 r5, 0x5f78635c; + imm32 r6, 0x60897b3d; + imm32 r7, 0x719a8c73; + [ P5 ] = R3; + [ P1 ] = R4; + [ P2 ] = R5; + [ P4 ] = R7; + [ FP ] = R0; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x4E67394B; + CHECKREG r1, 0x5F78635C; + CHECKREG r3, 0x719A8C73; + CHECKREG r4, 0x3D53483A; + CHECKREG r5, 0x3A231507; + CHECKREG r7, 0x719A8C73; + + imm32 r0, 0x4a231507; + imm32 r1, 0x14342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d54483a; + imm32 r4, 0x4e67494b; + imm32 r5, 0x5f78645c; + imm32 r6, 0x60897b4d; + imm32 r7, 0x719a8c74; + [ P5 ] = R4; + [ P1 ] = R5; + [ P2 ] = R6; + [ P4 ] = R0; + [ FP ] = R1; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x5F78645C; + CHECKREG r1, 0x60897B4D; + CHECKREG r3, 0x4A231507; + CHECKREG r4, 0x4E67494B; + CHECKREG r5, 0x14342618; + CHECKREG r7, 0x719A8C74; + + imm32 r0, 0x5a231507; + imm32 r1, 0x15342618; + imm32 r2, 0x2c553729; + imm32 r3, 0x3d55483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f78655c; + imm32 r6, 0x60897b5d; + imm32 r7, 0x719a8c75; + [ P5 ] = R5; + [ P1 ] = R6; + [ P2 ] = R7; + [ P4 ] = R1; + [ FP ] = R2; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x60897B5D; + CHECKREG r1, 0x719A8C75; + CHECKREG r3, 0x15342618; + CHECKREG r4, 0x5F78655C; + CHECKREG r5, 0x2C553729; + CHECKREG r7, 0x719A8C75; + + imm32 r0, 0x6a231507; + imm32 r1, 0x16342618; + imm32 r2, 0x2c653729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67694b; + imm32 r5, 0x5f78665c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c76; + [ P5 ] = R6; + [ P1 ] = R7; + [ P2 ] = R0; + [ P4 ] = R2; + [ FP ] = R3; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x719A8C76; + CHECKREG r1, 0x6A231507; + CHECKREG r3, 0x2C653729; + CHECKREG r4, 0x60897B6D; + CHECKREG r5, 0x3D56483A; + CHECKREG r7, 0x719A8C76; + + imm32 r0, 0x7a231507; + imm32 r1, 0x17342618; + imm32 r2, 0x2c753729; + imm32 r3, 0x3d57483a; + imm32 r4, 0x4e67794b; + imm32 r5, 0x5f78675c; + imm32 r6, 0x60897b7d; + imm32 r7, 0x719a8c77; + [ P5 ] = R7; + [ P1 ] = R0; + [ P2 ] = R1; + [ P4 ] = R3; + [ FP ] = R4; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x7A231507; + CHECKREG r1, 0x17342618; + CHECKREG r3, 0x3D57483A; + CHECKREG r4, 0x719A8C77; + CHECKREG r5, 0x4E67794B; + CHECKREG r7, 0x719A8C77; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_b.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_b.s new file mode 100644 index 0000000..1575c00 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_st_p_d_b.s @@ -0,0 +1,300 @@ +//Original:/testcases/core/c_ldst_st_p_d_b/c_ldst_st_p_d_b.dsp +// Spec Reference: c_ldst st_p d b +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + B [ P5 ] = R0; + B [ P1 ] = R1; + B [ P2 ] = R2; + B [ P4 ] = R4; + B [ FP ] = R5; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212218; + CHECKREG r1, 0x40414229; + CHECKREG r3, 0x8081824B; + CHECKREG r4, 0x00010207; + CHECKREG r5, 0xA0A1A25C; + CHECKREG r7, 0x719A8C7E; + + imm32 r0, 0x1a231507; + imm32 r1, 0x11342618; + imm32 r2, 0x2c153729; + imm32 r3, 0x3d51483a; + imm32 r4, 0x4e67194b; + imm32 r5, 0x5f78615c; + imm32 r6, 0x60897b1d; + imm32 r7, 0x719a8c71; + B [ P5 ] = R1; + B [ P1 ] = R2; + B [ P2 ] = R3; + B [ P4 ] = R5; + B [ FP ] = R6; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212229; + CHECKREG r1, 0x4041423A; + CHECKREG r3, 0x8081825C; + CHECKREG r4, 0x00010218; + CHECKREG r5, 0xA0A1A21D; + CHECKREG r7, 0x719A8C71; + + imm32 r0, 0x2a231507; + imm32 r1, 0x12342618; + imm32 r2, 0x2c253729; + imm32 r3, 0x3d52483a; + imm32 r4, 0x4e67294b; + imm32 r5, 0x5f78625c; + imm32 r6, 0x60897b2d; + imm32 r7, 0x719a8c72; + B [ P5 ] = R2; + B [ P1 ] = R3; + B [ P2 ] = R4; + B [ P4 ] = R6; + B [ FP ] = R7; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021223A; + CHECKREG r1, 0x4041424B; + CHECKREG r2, 0x2c253729; + CHECKREG r3, 0x8081822D; + CHECKREG r4, 0x00010229; + CHECKREG r5, 0xA0A1A272; + CHECKREG r7, 0x719A8C72; + + imm32 r0, 0x3a231507; + imm32 r1, 0x13342618; + imm32 r3, 0x3d53483a; + imm32 r4, 0x4e67394b; + imm32 r5, 0x5f78635c; + imm32 r6, 0x60897b3d; + imm32 r7, 0x719a8c73; + B [ P5 ] = R3; + B [ P1 ] = R4; + B [ P2 ] = R5; + B [ P4 ] = R7; + B [ FP ] = R0; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021224B; + CHECKREG r1, 0x4041425C; + CHECKREG r3, 0x80818273; + CHECKREG r4, 0x0001023A; + CHECKREG r5, 0xA0A1A207; + CHECKREG r7, 0x719A8C73; + + imm32 r0, 0x4a231507; + imm32 r1, 0x14342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d54483a; + imm32 r4, 0x4e67494b; + imm32 r5, 0x5f78645c; + imm32 r6, 0x60897b4d; + imm32 r7, 0x719a8c74; + B [ P5 ] = R4; + B [ P1 ] = R5; + B [ P2 ] = R6; + B [ P4 ] = R0; + B [ FP ] = R1; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021225C; + CHECKREG r1, 0x4041424D; + CHECKREG r3, 0x80818207; + CHECKREG r4, 0x0001024B; + CHECKREG r5, 0xA0A1A218; + CHECKREG r7, 0x719A8C74; + + imm32 r0, 0x5a231507; + imm32 r1, 0x15342618; + imm32 r2, 0x2c553729; + imm32 r3, 0x3d55483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f78655c; + imm32 r6, 0x60897b5d; + imm32 r7, 0x719a8c75; + B [ P5 ] = R5; + B [ P1 ] = R6; + B [ P2 ] = R7; + B [ P4 ] = R1; + B [ FP ] = R2; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021225D; + CHECKREG r1, 0x40414275; + CHECKREG r3, 0x80818218; + CHECKREG r4, 0x0001025C; + CHECKREG r5, 0xA0A1A229; + CHECKREG r7, 0x719A8C75; + + imm32 r0, 0x6a231507; + imm32 r1, 0x16342618; + imm32 r2, 0x2c653729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67694b; + imm32 r5, 0x5f78665c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c76; + B [ P5 ] = R6; + B [ P1 ] = R7; + B [ P2 ] = R0; + B [ P4 ] = R2; + B [ FP ] = R3; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212276; + CHECKREG r1, 0x40414207; + CHECKREG r3, 0x80818229; + CHECKREG r4, 0x0001026D; + CHECKREG r5, 0xA0A1A23A; + CHECKREG r7, 0x719A8C76; + + imm32 r0, 0x7a231507; + imm32 r1, 0x17342618; + imm32 r2, 0x2c753729; + imm32 r3, 0x3d57483a; + imm32 r4, 0x4e67794b; + imm32 r5, 0x5f78675c; + imm32 r6, 0x60897b7d; + imm32 r7, 0x719a8c77; + B [ P5 ] = R7; + B [ P1 ] = R0; + B [ P2 ] = R1; + B [ P4 ] = R3; + B [ FP ] = R4; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212207; + CHECKREG r1, 0x40414218; + CHECKREG r3, 0x8081823A; + CHECKREG r4, 0x00010277; + CHECKREG r5, 0xA0A1A24B; + CHECKREG r7, 0x719A8C77; + + pass + +// Pre-load memory witb known data +// More data is defined than will actually be used + + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_h.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_h.s new file mode 100644 index 0000000..dc0906c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_st_p_d_h.s @@ -0,0 +1,280 @@ +//Original:/testcases/core/c_ldst_st_p_d_h/c_ldst_st_p_d_h.dsp +// Spec Reference: c_ldst st_p d h +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + W [ P5 ] = R0; + W [ P1 ] = R1; + W [ P2 ] = R2; + W [ P4 ] = R4; + W [ FP ] = R5; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20212618; + CHECKREG r1, 0x40413729; + CHECKREG r3, 0x8081594B; + CHECKREG r4, 0x00011507; + CHECKREG r5, 0xA0A16A5C; + CHECKREG r7, 0x719A8C7E; + + imm32 r0, 0x1a231507; + imm32 r1, 0x11342618; + imm32 r2, 0x2c153729; + imm32 r3, 0x3d51483a; + imm32 r4, 0x4e67194b; + imm32 r5, 0x5f78615c; + imm32 r6, 0x60897b1d; + imm32 r7, 0x719a8c71; + W [ P5 ] = R1; + W [ P1 ] = R2; + W [ P2 ] = R3; + W [ P4 ] = R5; + W [ FP ] = R6; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20213729; + CHECKREG r1, 0x4041483A; + CHECKREG r3, 0x8081615C; + CHECKREG r4, 0x00012618; + CHECKREG r5, 0xA0A17B1D; + CHECKREG r6, 0x60897b1d; + + imm32 r0, 0x2a231507; + imm32 r1, 0x12342618; + imm32 r2, 0x2c253729; + imm32 r3, 0x3d52483a; + imm32 r4, 0x4e67294b; + imm32 r5, 0x5f78625c; + imm32 r6, 0x60897b2d; + imm32 r7, 0x719a8c72; + W [ P5 ] = R2; + W [ P1 ] = R3; + W [ P2 ] = R4; + W [ P4 ] = R6; + W [ FP ] = R7; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021483A; + CHECKREG r1, 0x4041294B; + CHECKREG r3, 0x80817B2D; + CHECKREG r4, 0x00013729; + CHECKREG r5, 0xA0A18C72; + CHECKREG r7, 0x719A8C72; + + imm32 r0, 0x3a231507; + imm32 r1, 0x13342618; + imm32 r2, 0x2c353729; + imm32 r3, 0x3d53483a; + imm32 r4, 0x4e67394b; + imm32 r5, 0x5f78635c; + imm32 r6, 0x60897b3d; + imm32 r7, 0x719a8c73; + W [ P5 ] = R3; + W [ P1 ] = R4; + W [ P2 ] = R5; + W [ P4 ] = R7; + W [ FP ] = R0; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x2021394B; + CHECKREG r1, 0x4041635C; + CHECKREG r3, 0x80818C73; + CHECKREG r4, 0x0001483A; + CHECKREG r5, 0xA0A11507; + CHECKREG r7, 0x719A8C73; + + imm32 r0, 0x4a231507; + imm32 r1, 0x14342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d54483a; + imm32 r4, 0x4e67494b; + imm32 r5, 0x5f78645c; + imm32 r6, 0x60897b4d; + imm32 r7, 0x719a8c74; + W [ P5 ] = R4; + W [ P1 ] = R5; + W [ P2 ] = R6; + W [ P4 ] = R0; + W [ FP ] = R1; + + W [ P5 ] = R5; + W [ P1 ] = R6; + W [ P2 ] = R7; + W [ P4 ] = R1; + W [ FP ] = R2; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20217B4D; + CHECKREG r1, 0x40418C74; + CHECKREG r3, 0x80812618; + CHECKREG r4, 0x0001645C; + CHECKREG r5, 0xA0A13729; + CHECKREG r7, 0x719A8C74; + + imm32 r0, 0x5a231507; + imm32 r1, 0x15342618; + imm32 r2, 0x2c553729; + imm32 r3, 0x3d55483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f78655c; + imm32 r6, 0x60897b5d; + imm32 r7, 0x719a8c75; + W [ P5 ] = R6; + W [ P1 ] = R7; + W [ P2 ] = R0; + W [ P4 ] = R2; + W [ FP ] = R3; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20218C75; + CHECKREG r1, 0x40411507; + CHECKREG r3, 0x80813729; + CHECKREG r4, 0x00017B5D; + CHECKREG r5, 0xA0A1483A; + CHECKREG r7, 0x719A8C75; + + imm32 r0, 0x6a231507; + imm32 r1, 0x16342618; + imm32 r2, 0x2c653729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67694b; + imm32 r5, 0x5f78665c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c76; + W [ P5 ] = R7; + W [ P1 ] = R0; + W [ P2 ] = R1; + W [ P4 ] = R3; + W [ FP ] = R4; + R0 = [ P1 ]; + R1 = [ P2 ]; + R3 = [ P4 ]; + R4 = [ P5 ]; + R5 = [ FP ]; + CHECKREG r0, 0x20211507; + CHECKREG r1, 0x40412618; + CHECKREG r3, 0x8081483A; + CHECKREG r4, 0x00018C76; + CHECKREG r5, 0xA0A1694B; + CHECKREG r7, 0x719A8C76; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm.s new file mode 100644 index 0000000..54d7faa --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm.s @@ -0,0 +1,601 @@ +//Original:testcases/core/c_ldst_st_p_d_mm/c_ldst_st_p_d_mm.dsp +// Spec Reference: c_ldst st_p++/p-- +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + loadsym i3, DATA_ADDR_7; + P3 = I1; SP = I3; + + [ P5 ++ ] = R0; + [ P1 ++ ] = R1; + [ P2 ++ ] = R2; + [ P3 ++ ] = R3; + [ P4 ++ ] = R4; + [ FP ++ ] = R5; + [ SP ++ ] = R6; + + [ P5 ++ ] = R2; + [ P1 ++ ] = R3; + [ P2 ++ ] = R4; + [ P3 ++ ] = R5; + [ P4 ++ ] = R6; + [ FP ++ ] = R7; + [ SP ++ ] = R0; + + [ P5 ++ ] = R5; + [ P1 ++ ] = R6; + [ P2 ++ ] = R7; + [ P3 ++ ] = R0; + [ P4 ++ ] = R1; + [ FP ++ ] = R2; + [ SP ++ ] = R3; + + [ P5 ++ ] = R7; + [ P1 ++ ] = R0; + [ P2 ++ ] = R1; + [ P3 ++ ] = R2; + [ P4 ++ ] = R3; + [ FP ++ ] = R4; + [ SP ++ ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + loadsym i3, DATA_ADDR_7; + P3 = I1; SP = I3; + + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R2 = [ P3 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + R6 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x0A231507; + CHECKREG r5, 0x5F786A5C; + CHECKREG r6, 0x60897B6D; + CHECKREG r7, 0x719A8C7E; + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R2 = [ P3 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + R6 = [ SP ++ ]; + CHECKREG r0, 0x3D56483A; + CHECKREG r1, 0x4E67594B; + CHECKREG r2, 0x5F786A5C; + CHECKREG r3, 0x60897B6D; + CHECKREG r4, 0x2C453729; + CHECKREG r5, 0x719A8C7E; + CHECKREG r6, 0x0A231507; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R3 = [ P3 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ P5 ++ ]; + R6 = [ FP ++ ]; + R7 = [ SP ++ ]; + CHECKREG r0, 0x3D56483A; + CHECKREG r1, 0x60897B6D; + CHECKREG r2, 0x719A8C7E; + CHECKREG r3, 0x0A231507; + CHECKREG r4, 0x1B342618; + CHECKREG r5, 0x5F786A5C; + CHECKREG r6, 0x2C453729; + CHECKREG r7, 0x3D56483A; + R3 = [ P1 ++ ]; + R4 = [ P2 ++ ]; + R5 = [ P3 ++ ]; + R6 = [ P4 ++ ]; + R7 = [ P5 ++ ]; + R0 = [ FP ++ ]; + R1 = [ SP ++ ]; + CHECKREG r0, 0x4E67594B; + CHECKREG r1, 0x5F786A5C; + CHECKREG r2, 0x719A8C7E; + CHECKREG r3, 0x0A231507; + CHECKREG r4, 0x1B342618; + CHECKREG r5, 0x2C453729; + CHECKREG r6, 0x3D56483A; + CHECKREG r7, 0x719A8C7E; + +// reset values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + [ P5 -- ] = R0; + [ P1 -- ] = R1; + [ P2 -- ] = R2; + [ P3 -- ] = R3; + [ P4 -- ] = R4; + [ FP -- ] = R5; + [ SP -- ] = R6; + + [ P5 -- ] = R2; + [ P1 -- ] = R3; + [ P2 -- ] = R4; + [ P3 -- ] = R5; + [ P4 -- ] = R6; + [ FP -- ] = R7; + [ SP -- ] = R0; + + [ P5 -- ] = R5; + [ P1 -- ] = R6; + [ P2 -- ] = R7; + [ P3 -- ] = R0; + [ P4 -- ] = R1; + [ FP -- ] = R2; + [ SP -- ] = R3; + + [ P5 -- ] = R6; + [ P1 -- ] = R7; + [ P2 -- ] = R0; + [ P3 -- ] = R1; + [ P4 -- ] = R2; + [ FP -- ] = R3; + [ SP -- ] = R4; + [ P1 -- ] = R0; + [ P2 -- ] = R1; + [ P3 -- ] = R2; + [ P4 -- ] = R3; + [ FP -- ] = R4; + [ SP -- ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ P5 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r0, 0x5F786A5C; + CHECKREG r1, 0x719A8C7E; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x1B342618; + CHECKREG r4, 0x4E67594B; + CHECKREG r5, 0x2C453729; + CHECKREG r6, 0x3D56483A; + CHECKREG r7, 0x719A8C7E; + R2 = [ P1 -- ]; + R3 = [ P2 -- ]; + R4 = [ P3 -- ]; + R5 = [ P4 -- ]; + R6 = [ P5 -- ]; + R7 = [ FP -- ]; + R0 = [ SP -- ]; + CHECKREG r0, 0x4E67594B; + CHECKREG r1, 0x719A8C7E; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x1B342618; + CHECKREG r4, 0x2C453729; + CHECKREG r5, 0x3D56483A; + CHECKREG r6, 0x719A8C7E; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r0, 0x719A8C7E; + CHECKREG r1, 0x0A231507; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x3D56483A; + CHECKREG r4, 0x719A8C7E; + CHECKREG r5, 0x4E67594B; + CHECKREG r6, 0x5F786A5C; + CHECKREG r7, 0x2C453729; + R5 = [ P1 -- ]; + R6 = [ P2 -- ]; + R7 = [ P3 -- ]; + R0 = [ P4 -- ]; + R1 = [ P5 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + CHECKREG r0, 0x719A8C7E; + CHECKREG r1, 0x3D56483A; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x1B342618; + CHECKREG r4, 0x719A8C7E; + CHECKREG r5, 0x719A8C7E; + CHECKREG r6, 0x4E67594B; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_b.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_b.s new file mode 100644 index 0000000..1a2c3a9 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_b.s @@ -0,0 +1,498 @@ +//Original:testcases/core/c_ldst_st_p_d_mm_b/c_ldst_st_p_d_mm_b.dsp +// Spec Reference: c_ldst st_p-- b byte +# mach: bfin + +.include "testutils.inc" + start + + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// reset values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + B [ P5 -- ] = R0; + B [ P1 -- ] = R1; + B [ P2 -- ] = R2; + B [ P3 -- ] = R3; + B [ P4 -- ] = R4; + B [ FP -- ] = R5; + B [ SP -- ] = R6; + + B [ P5 -- ] = R1; + B [ P1 -- ] = R2; + B [ P2 -- ] = R3; + B [ P3 -- ] = R4; + B [ P4 -- ] = R5; + B [ FP -- ] = R6; + B [ SP -- ] = R7; + + B [ P5 -- ] = R2; + B [ P1 -- ] = R3; + B [ P2 -- ] = R4; + B [ P3 -- ] = R5; + B [ P4 -- ] = R6; + B [ FP -- ] = R7; + B [ SP -- ] = R0; + + B [ P5 -- ] = R3; + B [ P1 -- ] = R4; + B [ P2 -- ] = R5; + B [ P3 -- ] = R6; + B [ P4 -- ] = R7; + B [ FP -- ] = R0; + B [ SP -- ] = R1; + + B [ P5 -- ] = R4; + B [ P1 -- ] = R5; + B [ P2 -- ] = R6; + B [ P3 -- ] = R7; + B [ P4 -- ] = R0; + B [ FP -- ] = R1; + B [ SP -- ] = R2; + + B [ P5 -- ] = R5; + B [ P1 -- ] = R6; + B [ P2 -- ] = R7; + B [ P3 -- ] = R0; + B [ P4 -- ] = R1; + B [ FP -- ] = R2; + B [ SP -- ] = R3; + + B [ P5 -- ] = R6; + B [ P1 -- ] = R7; + B [ P2 -- ] = R0; + B [ P3 -- ] = R1; + B [ P4 -- ] = R2; + B [ FP -- ] = R3; + B [ SP -- ] = R4; + + B [ P5 -- ] = R7; + B [ P1 -- ] = R0; + B [ P2 -- ] = R1; + B [ P3 -- ] = R2; + B [ P4 -- ] = R3; + B [ FP -- ] = R4; + B [ SP -- ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ P5 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r1, 0x00000029; + CHECKREG r2, 0x0000003A; + CHECKREG r3, 0x0000004B; + CHECKREG r4, 0x00000007; + CHECKREG r5, 0x0000005C; + CHECKREG r6, 0xE0E1E26D; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 -- ]; + R2 = [ P2 -- ]; + R3 = [ P3 -- ]; + R4 = [ P4 -- ]; + R5 = [ P5 -- ]; + R6 = [ FP -- ]; + R7 = [ SP -- ]; + CHECKREG r1, 0x293A4B5C; + CHECKREG r2, 0x3A4B5C6D; + CHECKREG r3, 0x4B5C6D7E; + CHECKREG r4, 0x5C6D7E07; + CHECKREG r5, 0x18293A4B; + CHECKREG r6, 0x6D7E0718; + CHECKREG r7, 0x7E071829; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r1, 0x3A4B5CDB; + CHECKREG r2, 0x3A4B5C6D; + CHECKREG r3, 0x6D7E073B; + CHECKREG r4, 0x7E07185B; + CHECKREG r5, 0x0718297B; + CHECKREG r6, 0x18293A9B; + CHECKREG r7, 0x5C6D7E1B; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_h.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_h.s new file mode 100644 index 0000000..883bf35 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_st_p_d_mm_h.s @@ -0,0 +1,554 @@ +//Original:testcases/core/c_ldst_st_p_d_mm_h/c_ldst_st_p_d_mm_h.dsp +// Spec Reference: c_ldst st_p-- h half +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +INIT_R_REGS 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// reset values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + W [ P5 -- ] = R0; + W [ P1 -- ] = R1; + W [ P2 -- ] = R2; + W [ P3 -- ] = R3; + W [ P4 -- ] = R4; + W [ FP -- ] = R5; + W [ SP -- ] = R6; + + W [ P5 -- ] = R1; + W [ P1 -- ] = R2; + W [ P2 -- ] = R3; + W [ P3 -- ] = R4; + W [ P4 -- ] = R5; + W [ FP -- ] = R6; + W [ SP -- ] = R7; + + W [ P5 -- ] = R2; + W [ P1 -- ] = R3; + W [ P2 -- ] = R4; + W [ P3 -- ] = R5; + W [ P4 -- ] = R6; + W [ FP -- ] = R7; + W [ SP -- ] = R0; + + W [ P5 -- ] = R3; + W [ P1 -- ] = R4; + W [ P2 -- ] = R5; + W [ P3 -- ] = R6; + W [ P4 -- ] = R7; + W [ FP -- ] = R0; + W [ SP -- ] = R1; + + W [ P5 -- ] = R4; + W [ P1 -- ] = R5; + W [ P2 -- ] = R6; + W [ P3 -- ] = R7; + W [ P4 -- ] = R0; + W [ FP -- ] = R1; + W [ SP -- ] = R2; + + W [ P5 -- ] = R5; + W [ P1 -- ] = R6; + W [ P2 -- ] = R7; + W [ P3 -- ] = R0; + W [ P4 -- ] = R1; + W [ FP -- ] = R2; + W [ SP -- ] = R3; + + W [ P5 -- ] = R6; + W [ P1 -- ] = R7; + W [ P2 -- ] = R0; + W [ P3 -- ] = R1; + W [ P4 -- ] = R2; + W [ FP -- ] = R3; + W [ SP -- ] = R4; + + W [ P5 -- ] = R7; + W [ P1 -- ] = R0; + W [ P2 -- ] = R1; + W [ P3 -- ] = R2; + W [ P4 -- ] = R3; + W [ FP -- ] = R4; + W [ SP -- ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ P5 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r1, 0x00003729; + CHECKREG r2, 0x0000483A; + CHECKREG r3, 0x0000594B; + CHECKREG r4, 0x00001507; + CHECKREG r5, 0x00006A5C; + CHECKREG r6, 0xE0E17B6D; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 -- ]; + R2 = [ P2 -- ]; + R3 = [ P3 -- ]; + R4 = [ P4 -- ]; + R5 = [ P5 -- ]; + R6 = [ FP -- ]; + R7 = [ SP -- ]; + CHECKREG r1, 0x3729483A; + CHECKREG r2, 0x483A594B; + CHECKREG r3, 0x594B6A5C; + CHECKREG r4, 0x6A5C7B6D; + CHECKREG r5, 0x26183729; + CHECKREG r6, 0x7B6D8C7E; + CHECKREG r7, 0x8C7E1507; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r1, 0x26183729; + CHECKREG r2, 0x483A594B; + CHECKREG r3, 0x594B6A5C; + CHECKREG r4, 0x6A5C7B6D; + CHECKREG r5, 0x7B6D8C7E; + CHECKREG r6, 0x8C7E1507; + CHECKREG r7, 0x483A594B; + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r1, 0x483A594B; + CHECKREG r2, 0x483A594B; + CHECKREG r3, 0x7B6D8C7E; + CHECKREG r4, 0x8C7E1507; + CHECKREG r5, 0x15072618; + CHECKREG r6, 0x26183729; + CHECKREG r7, 0x6A5C7B6D; + R4 = [ P1 -- ]; + R5 = [ P2 -- ]; + R6 = [ P3 -- ]; + R7 = [ P4 -- ]; + R0 = [ P5 -- ]; + R1 = [ FP -- ]; + R2 = [ SP -- ]; + CHECKREG r1, 0x594BB2B3; + CHECKREG r2, 0x6A5CD2D3; + CHECKREG r3, 0x7B6D8C7E; + CHECKREG r4, 0x15073233; + CHECKREG r5, 0x26185253; + CHECKREG r6, 0x37297273; + CHECKREG r7, 0x483A9293; + R5 = [ P1 -- ]; + R6 = [ P2 -- ]; + R7 = [ P3 -- ]; + R0 = [ P4 -- ]; + R1 = [ P5 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + CHECKREG r1, 0x0C0D0E0F; + CHECKREG r2, 0xACADAEAF; + CHECKREG r3, 0xCCCDCECF; + CHECKREG r4, 0x15073233; + CHECKREG r5, 0x2C2D2E2F; + CHECKREG r6, 0x4C4D4E4F; + CHECKREG r7, 0x6C6D6E6F; + R6 = [ P1 -- ]; + R7 = [ P2 -- ]; + R0 = [ P3 -- ]; + R1 = [ P4 -- ]; + R2 = [ P5 -- ]; + R3 = [ FP -- ]; + R0 = [ SP -- ]; + CHECKREG r1, 0x88898A8B; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0xA8A9AAAB; + CHECKREG r4, 0x15073233; + CHECKREG r5, 0x2C2D2E2F; + CHECKREG r6, 0x28292A2B; + CHECKREG r7, 0x48494A4B; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp.s new file mode 100644 index 0000000..05e96bc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp.s @@ -0,0 +1,804 @@ +//Original:testcases/core/c_ldst_st_p_d_pp/c_ldst_st_p_d_pp.dsp +// Spec Reference: c_ldst st_p++ d +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + loadsym i3, DATA_ADDR_7; + P3 = I1; SP = I3; + + [ P5 ++ ] = R0; + [ P1 ++ ] = R1; + [ P2 ++ ] = R2; + [ P3 ++ ] = R3; + [ P4 ++ ] = R4; + [ FP ++ ] = R5; + [ SP ++ ] = R6; + + [ P5 ++ ] = R1; + [ P1 ++ ] = R2; + [ P2 ++ ] = R3; + [ P3 ++ ] = R4; + [ P4 ++ ] = R5; + [ FP ++ ] = R6; + [ SP ++ ] = R7; + + [ P5 ++ ] = R2; + [ P1 ++ ] = R3; + [ P2 ++ ] = R4; + [ P3 ++ ] = R5; + [ P4 ++ ] = R6; + [ FP ++ ] = R7; + [ SP ++ ] = R0; + + [ P5 ++ ] = R3; + [ P1 ++ ] = R4; + [ P2 ++ ] = R5; + [ P3 ++ ] = R6; + [ P4 ++ ] = R7; + [ FP ++ ] = R0; + [ SP ++ ] = R1; + + [ P5 ++ ] = R4; + [ P1 ++ ] = R5; + [ P2 ++ ] = R6; + [ P3 ++ ] = R7; + [ P4 ++ ] = R0; + [ FP ++ ] = R1; + [ SP ++ ] = R2; + + [ P5 ++ ] = R5; + [ P1 ++ ] = R6; + [ P2 ++ ] = R7; + [ P3 ++ ] = R0; + [ P4 ++ ] = R1; + [ FP ++ ] = R2; + [ SP ++ ] = R3; + + [ P5 ++ ] = R6; + [ P1 ++ ] = R7; + [ P2 ++ ] = R0; + [ P3 ++ ] = R1; + [ P4 ++ ] = R2; + [ FP ++ ] = R3; + [ SP ++ ] = R4; + + [ P5 ++ ] = R7; + [ P1 ++ ] = R0; + [ P2 ++ ] = R1; + [ P3 ++ ] = R2; + [ P4 ++ ] = R3; + [ FP ++ ] = R4; + [ SP ++ ] = R5; + +// Read back and check + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym i1, DATA_ADDR_4; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + loadsym i3, DATA_ADDR_7; + P3 = I1; SP = I3; + + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R2 = [ P3 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + R6 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x0A231507; + CHECKREG r5, 0x5F786A5C; + CHECKREG r6, 0x60897B6D; + CHECKREG r7, 0x719A8C7E; + + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R3 = [ P3 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ P5 ++ ]; + R6 = [ FP ++ ]; + R7 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x1B342618; + CHECKREG r6, 0x60897B6D; + CHECKREG r7, 0x719A8C7E; + + R2 = [ P1 ++ ]; + R3 = [ P2 ++ ]; + R4 = [ P3 ++ ]; + R5 = [ P4 ++ ]; + R6 = [ P5 ++ ]; + R7 = [ FP ++ ]; + R0 = [ SP ++ ]; + CHECKREG r0, 0x0A231507; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x2C453729; + CHECKREG r7, 0x719A8C7E; + + R3 = [ P1 ++ ]; + R4 = [ P2 ++ ]; + R5 = [ P3 ++ ]; + R6 = [ P4 ++ ]; + R7 = [ P5 ++ ]; + R0 = [ FP ++ ]; + R1 = [ SP ++ ]; + CHECKREG r0, 0x0A231507; + CHECKREG r1, 0x1B342618; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x3D56483A; + + R4 = [ P1 ++ ]; + R5 = [ P2 ++ ]; + R6 = [ P3 ++ ]; + R7 = [ P4 ++ ]; + R0 = [ P5 ++ ]; + R1 = [ FP ++ ]; + R2 = [ SP ++ ]; + CHECKREG r0, 0x4E67594B; + CHECKREG r1, 0x1B342618; + CHECKREG r2, 0x2C453729; + CHECKREG r3, 0x4E67594B; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x0A231507; + + R5 = [ P1 ++ ]; + R6 = [ P2 ++ ]; + R7 = [ P3 ++ ]; + R0 = [ P4 ++ ]; + R1 = [ P5 ++ ]; + R2 = [ FP ++ ]; + R3 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x5F786A5C; + CHECKREG r2, 0x2C453729; + CHECKREG r3, 0x3D56483A; + CHECKREG r4, 0x5F786A5C; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x0A231507; + + R6 = [ P1 ++ ]; + R7 = [ P2 ++ ]; + R0 = [ P3 ++ ]; + R1 = [ P4 ++ ]; + R2 = [ P5 ++ ]; + R3 = [ FP ++ ]; + R4 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x60897B6D; + CHECKREG r3, 0x3D56483A; + CHECKREG r4, 0x4E67594B; + CHECKREG r5, 0x60897B6D; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x0A231507; + + R7 = [ P1 ++ ]; + R0 = [ P2 ++ ]; + R1 = [ P3 ++ ]; + R2 = [ P4 ++ ]; + R3 = [ P5 ++ ]; + R4 = [ FP ++ ]; + R5 = [ SP ++ ]; + CHECKREG r0, 0x1B342618; + CHECKREG r1, 0x2C453729; + CHECKREG r2, 0x3D56483A; + CHECKREG r3, 0x719A8C7E; + CHECKREG r4, 0x4E67594B; + CHECKREG r5, 0x5F786A5C; + CHECKREG r6, 0x719A8C7E; + CHECKREG r7, 0x0A231507; + +// reset values + imm32 r0, 0x1a235507; + imm32 r1, 0x12342518; + imm32 r2, 0x23353729; + imm32 r3, 0x3f54483a; + imm32 r4, 0x4467694b; + imm32 r5, 0x5ff86a5c; + imm32 r6, 0x608b7b1d; + imm32 r7, 0x719a8c71; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + [ P5 -- ] = R0; + [ P1 -- ] = R1; + [ P2 -- ] = R2; + [ P3 -- ] = R3; + [ P4 -- ] = R4; + [ FP -- ] = R5; + [ SP -- ] = R6; + + [ P5 -- ] = R1; + [ P1 -- ] = R2; + [ P2 -- ] = R3; + [ P3 -- ] = R4; + [ P4 -- ] = R5; + [ FP -- ] = R6; + [ SP -- ] = R7; + + [ P5 -- ] = R2; + [ P1 -- ] = R3; + [ P2 -- ] = R4; + [ P3 -- ] = R5; + [ P4 -- ] = R6; + [ FP -- ] = R7; + [ SP -- ] = R0; + + [ P5 -- ] = R3; + [ P1 -- ] = R4; + [ P2 -- ] = R5; + [ P3 -- ] = R6; + [ P4 -- ] = R7; + [ FP -- ] = R0; + [ SP -- ] = R1; + + [ P5 -- ] = R4; + [ P1 -- ] = R5; + [ P2 -- ] = R6; + [ P3 -- ] = R7; + [ P4 -- ] = R0; + [ FP -- ] = R1; + [ SP -- ] = R2; + + [ P5 -- ] = R5; + [ P1 -- ] = R6; + [ P2 -- ] = R7; + [ P3 -- ] = R0; + [ P4 -- ] = R1; + [ FP -- ] = R2; + [ SP -- ] = R3; + + [ P5 -- ] = R6; + [ P1 -- ] = R7; + [ P2 -- ] = R0; + [ P3 -- ] = R1; + [ P4 -- ] = R2; + [ FP -- ] = R3; + [ SP -- ] = R4; + + [ P5 -- ] = R7; + [ P1 -- ] = R0; + [ P2 -- ] = R1; + [ P3 -- ] = R2; + [ P4 -- ] = R3; + [ FP -- ] = R4; + [ SP -- ] = R5; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x20; + loadsym p1, DATA_ADDR_2, 0x20; + loadsym p2, DATA_ADDR_3, 0x20; + loadsym i1, DATA_ADDR_4, 0x20; + loadsym p4, DATA_ADDR_5, 0x20; + loadsym fp, DATA_ADDR_6, 0x20; + loadsym i3, DATA_ADDR_7, 0x20; + P3 = I1; SP = I3; + + R0 = [ P1 -- ]; + R1 = [ P2 -- ]; + R2 = [ P3 -- ]; + R3 = [ P4 -- ]; + R4 = [ P5 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x1A235507; + CHECKREG r5, 0x5FF86A5C; + CHECKREG r6, 0x608B7B1D; + CHECKREG r7, 0x719A8C71; + + R1 = [ P1 -- ]; + R2 = [ P2 -- ]; + R3 = [ P3 -- ]; + R4 = [ P4 -- ]; + R5 = [ P5 -- ]; + R6 = [ FP -- ]; + R7 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x12342518; + CHECKREG r6, 0x608B7B1D; + CHECKREG r7, 0x719A8C71; + + R2 = [ P1 -- ]; + R3 = [ P2 -- ]; + R4 = [ P3 -- ]; + R5 = [ P4 -- ]; + R6 = [ P5 -- ]; + R7 = [ FP -- ]; + R0 = [ SP -- ]; + CHECKREG r0, 0x1A235507; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x23353729; + CHECKREG r7, 0x719A8C71; + + R3 = [ P1 -- ]; + R4 = [ P2 -- ]; + R5 = [ P3 -- ]; + R6 = [ P4 -- ]; + R7 = [ P5 -- ]; + R0 = [ FP -- ]; + R1 = [ SP -- ]; + CHECKREG r0, 0x1A235507; + CHECKREG r1, 0x12342518; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x3F54483A; + + R4 = [ P1 -- ]; + R5 = [ P2 -- ]; + R6 = [ P3 -- ]; + R7 = [ P4 -- ]; + R0 = [ P5 -- ]; + R1 = [ FP -- ]; + R2 = [ SP -- ]; + CHECKREG r0, 0x4467694B; + CHECKREG r1, 0x12342518; + CHECKREG r2, 0x23353729; + CHECKREG r3, 0x4467694B; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x1A235507; + + R5 = [ P1 -- ]; + R6 = [ P2 -- ]; + R7 = [ P3 -- ]; + R0 = [ P4 -- ]; + R1 = [ P5 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x5FF86A5C; + CHECKREG r2, 0x23353729; + CHECKREG r3, 0x3F54483A; + CHECKREG r4, 0x5FF86A5C; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x1A235507; + + R6 = [ P1 -- ]; + R7 = [ P2 -- ]; + R0 = [ P3 -- ]; + R1 = [ P4 -- ]; + R2 = [ P5 -- ]; + R3 = [ FP -- ]; + R4 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x608B7B1D; + CHECKREG r3, 0x3F54483A; + CHECKREG r4, 0x4467694B; + CHECKREG r5, 0x608B7B1D; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x1A235507; + + R7 = [ P1 -- ]; + R0 = [ P2 -- ]; + R1 = [ P3 -- ]; + R2 = [ P4 -- ]; + R3 = [ P5 -- ]; + R4 = [ FP -- ]; + R5 = [ SP -- ]; + CHECKREG r0, 0x12342518; + CHECKREG r1, 0x23353729; + CHECKREG r2, 0x3F54483A; + CHECKREG r3, 0x719A8C71; + CHECKREG r4, 0x4467694B; + CHECKREG r5, 0x5FF86A5C; + CHECKREG r6, 0x719A8C71; + CHECKREG r7, 0x1A235507; + + P3 = I1; SP = I3; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_b.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_b.s new file mode 100644 index 0000000..823aa9b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_b.s @@ -0,0 +1,455 @@ +//Original:/testcases/core/c_ldst_st_p_d_pp_b/c_ldst_st_p_d_pp_b.dsp +// Spec Reference: c_ldst st_p++ b byte +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// store incremented by 1 loc + B [ P5 ++ ] = R0; + B [ P1 ++ ] = R1; + B [ P2 ++ ] = R2; + B [ P4 ++ ] = R4; + B [ FP ++ ] = R5; + + B [ P5 ++ ] = R1; + B [ P1 ++ ] = R2; + B [ P2 ++ ] = R3; + B [ P4 ++ ] = R5; + B [ FP ++ ] = R6; + + B [ P5 ++ ] = R2; + B [ P1 ++ ] = R3; + B [ P2 ++ ] = R4; + B [ P4 ++ ] = R6; + B [ FP ++ ] = R7; + + B [ P5 ++ ] = R3; + B [ P1 ++ ] = R4; + B [ P2 ++ ] = R5; + B [ P4 ++ ] = R7; + B [ FP ++ ] = R0; + + B [ P5 ++ ] = R4; + B [ P1 ++ ] = R5; + B [ P2 ++ ] = R6; + B [ P4 ++ ] = R0; + B [ FP ++ ] = R1; + + B [ P5 ++ ] = R5; + B [ P1 ++ ] = R6; + B [ P2 ++ ] = R7; + B [ P4 ++ ] = R1; + B [ FP ++ ] = R2; + + B [ P5 ++ ] = R6; + B [ P1 ++ ] = R7; + B [ P2 ++ ] = R0; + B [ P4 ++ ] = R2; + B [ FP ++ ] = R3; + + B [ P5 ++ ] = R7; + B [ P1 ++ ] = R0; + B [ P2 ++ ] = R1; + B [ P4 ++ ] = R3; + B [ FP ++ ] = R4; + +// Read back and check + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r0, 0x4B3A2918; + CHECKREG r1, 0x5C4B3A29; + CHECKREG r3, 0x7E6D5C4B; + CHECKREG r4, 0x3A291807; + CHECKREG r5, 0x077E6D5C; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ P5 ++ ]; + R6 = [ FP ++ ]; + CHECKREG r0, 0x4B3A2918; + CHECKREG r1, 0x077E6D5C; + CHECKREG r2, 0x18077E6D; + CHECKREG r4, 0x3A291807; + CHECKREG r5, 0x7E6D5C4B; + CHECKREG r6, 0x4B3A2918; + R2 = [ P1 ++ ]; + R3 = [ P2 ++ ]; + R5 = [ P4 ++ ]; + R6 = [ P5 ++ ]; + R7 = [ FP ++ ]; + CHECKREG r1, 0x077E6D5C; + CHECKREG r2, 0x28292A2B; + CHECKREG r3, 0x48494A4B; + CHECKREG r5, 0x88898A8B; + CHECKREG r6, 0x08090A0B; + CHECKREG r7, 0xA8A9AAAB; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_h.s b/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_h.s new file mode 100644 index 0000000..c8b453a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_st_p_d_pp_h.s @@ -0,0 +1,457 @@ +//Original:/testcases/core/c_ldst_st_p_d_pp_h/c_ldst_st_p_d_pp_h.dsp +// Spec Reference: c_ldst st_p++/p-- h half +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + +// half word 16-bit store incremented by 2 + W [ P5 ++ ] = R0; + W [ P1 ++ ] = R1; + W [ P2 ++ ] = R2; + W [ P4 ++ ] = R4; + W [ FP ++ ] = R5; + + W [ P5 ++ ] = R1; + W [ P1 ++ ] = R2; + W [ P2 ++ ] = R3; + W [ P4 ++ ] = R5; + W [ FP ++ ] = R6; + + W [ P5 ++ ] = R2; + W [ P1 ++ ] = R3; + W [ P2 ++ ] = R4; + W [ P4 ++ ] = R6; + W [ FP ++ ] = R7; + + W [ P5 ++ ] = R3; + W [ P1 ++ ] = R4; + W [ P2 ++ ] = R5; + W [ P4 ++ ] = R7; + W [ FP ++ ] = R0; + + W [ P5 ++ ] = R4; + W [ P1 ++ ] = R5; + W [ P2 ++ ] = R6; + W [ P4 ++ ] = R0; + W [ FP ++ ] = R1; + + W [ P5 ++ ] = R5; + W [ P1 ++ ] = R6; + W [ P2 ++ ] = R7; + W [ P4 ++ ] = R1; + W [ FP ++ ] = R2; + + W [ P5 ++ ] = R6; + W [ P1 ++ ] = R7; + W [ P2 ++ ] = R0; + W [ P4 ++ ] = R2; + W [ FP ++ ] = R3; + + W [ P5 ++ ] = R7; + W [ P1 ++ ] = R0; + W [ P2 ++ ] = R1; + W [ P4 ++ ] = R3; + W [ FP ++ ] = R4; + +// Read back and check + loadsym p5, DATA_ADDR_1; + loadsym p1, DATA_ADDR_2; + loadsym p2, DATA_ADDR_3; + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + R0 = [ P1 ++ ]; + R1 = [ P2 ++ ]; + R3 = [ P4 ++ ]; + R4 = [ P5 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r0, 0x37292618; + CHECKREG r1, 0x483A3729; + CHECKREG r3, 0x6A5C594B; + CHECKREG r4, 0x26181507; + CHECKREG r5, 0x7B6D6A5C; + CHECKREG r7, 0x719A8C7E; + R1 = [ P1 ++ ]; + R2 = [ P2 ++ ]; + R4 = [ P4 ++ ]; + R5 = [ P5 ++ ]; + R6 = [ FP ++ ]; + CHECKREG r0, 0x37292618; + CHECKREG r1, 0x594B483A; + CHECKREG r2, 0x6A5C594B; + CHECKREG r4, 0x8C7E7B6D; + CHECKREG r5, 0x483A3729; + CHECKREG r6, 0x15078C7E; + R2 = [ P1 ++ ]; + R3 = [ P2 ++ ]; + R5 = [ P4 ++ ]; + R6 = [ P5 ++ ]; + R7 = [ FP ++ ]; + CHECKREG r1, 0x594B483A; + CHECKREG r2, 0x7B6D6A5C; + CHECKREG r3, 0x8C7E7B6D; + CHECKREG r5, 0x26181507; + CHECKREG r6, 0x6A5C594B; + CHECKREG r7, 0x37292618; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_p.s b/sim/testsuite/sim/bfin/c_ldst_st_p_p.s new file mode 100644 index 0000000..1cc87a1 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_st_p_p.s @@ -0,0 +1,128 @@ +//Original:/testcases/core/c_ldst_st_p_p/c_ldst_st_p_p.dsp +// Spec Reference: c_ldst st_p_p +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values p-p + imm32 p5, 0x0a231507; + imm32 p1, 0x1b342618; + imm32 p2, 0x2c453729; + + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + [ P4 ] = P1; + [ FP ] = P2; + R5 = [ P4 ]; + R6 = [ FP ]; + CHECKREG r5, 0x1B342618; + CHECKREG r6, 0x2C453729; + + [ P4 ] = P2; + [ FP ] = R3; + R5 = [ P4 ]; + R6 = [ FP ]; + CHECKREG r5, 0x2C453729; + CHECKREG r6, 0x3D56483A; + + [ P4 ] = R3; + [ FP ] = P5; + R5 = [ P4 ]; + R6 = [ FP ]; + CHECKREG r5, 0x3D56483A; + CHECKREG r6, 0x0A231507; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_p_mm.s b/sim/testsuite/sim/bfin/c_ldst_st_p_p_mm.s new file mode 100644 index 0000000..e7dd3cd --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_st_p_p_mm.s @@ -0,0 +1,428 @@ +//Original:testcases/core/c_ldst_st_p_p_mm/c_ldst_st_p_p_mm.dsp +// Spec Reference: c_ldst st p-- p +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +INIT_I_REGS -1; +init_b_regs 0; +init_l_regs 0; +init_m_regs -1; +I0 = P3; +I2 = SP; + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values p-p + imm32 p5, 0x0a231507; + imm32 p1, 0x1b342618; + imm32 p2, 0x2c453729; + imm32 p3, 0x4356789a; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_5, 0x18; + loadsym fp, DATA_ADDR_6, 0x18; + loadsym i3, DATA_ADDR_7, 0x18; + P3 = I1; SP = I3; + + [ P4 -- ] = P1; + [ FP -- ] = P2; + [ SP -- ] = R3; + + [ P4 -- ] = P2; + [ FP -- ] = P3; + [ SP -- ] = P5; + + [ P4 -- ] = P3; + [ FP -- ] = P5; + [ SP -- ] = P1; + + [ P4 -- ] = P5; + [ FP -- ] = P1; + [ SP -- ] = P2; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_5, 0x18; + loadsym fp, DATA_ADDR_6, 0x18; + loadsym i3, DATA_ADDR_7, 0x18; + P3 = I1; SP = I3; + + R1 = [ P4 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + R4 = [ P4 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r1, 0x1B342618; + CHECKREG r2, 0x2C453729; + CHECKREG r3, 0x3D56483A; + CHECKREG r4, 0x2C453729; + CHECKREG r5, 0x4356789A; + CHECKREG r6, 0x0A231507; + R1 = [ P4 -- ]; + R2 = [ FP -- ]; + R3 = [ SP -- ]; + R4 = [ P4 -- ]; + R5 = [ FP -- ]; + R6 = [ SP -- ]; + CHECKREG r1, 0x4356789A; + CHECKREG r2, 0x0A231507; + CHECKREG r3, 0x1B342618; + CHECKREG r4, 0x0A231507; + CHECKREG r5, 0x1B342618; + CHECKREG r6, 0x2C453729; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x10000080 + .dd 0x02000800 + .dd 0x00207000 + .dd 0x000d0000 + .dd 0x0006b000 + .dd 0x00500a00 + .dd 0x0d0000f0 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x10006000 + .dd 0xa2050800 + .dd 0x0c30db00 + .dd 0x00b40000 + .dd 0xa0045000 + .dd 0x0000f600 + .dd 0x00d00070 + .dd 0x00000008 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x10000000 + .dd 0x0d000000 + .dd 0x00400000 + .dd 0x000b0000 + .dd 0x000d0b00 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldst_st_p_p_pp.s b/sim/testsuite/sim/bfin/c_ldst_st_p_p_pp.s new file mode 100644 index 0000000..c8068de --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldst_st_p_p_pp.s @@ -0,0 +1,397 @@ +//Original:/testcases/core/c_ldst_st_p_p_pp/c_ldst_st_p_p_pp.dsp +// Spec Reference: c_ldst st p++ p +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x0a231507; + imm32 r1, 0x1b342618; + imm32 r2, 0x2c453729; + imm32 r3, 0x3d56483a; + imm32 r4, 0x4e67594b; + imm32 r5, 0x5f786a5c; + imm32 r6, 0x60897b6d; + imm32 r7, 0x719a8c7e; + +// initial values p-p + imm32 p5, 0x0a231507; + imm32 p1, 0x1b342618; + imm32 p2, 0x2c453729; + imm32 p0, 0x125afbd3; + + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + + [ P4 ++ ] = P1; + [ FP ++ ] = P2; + + [ P4 ++ ] = P2; + [ FP ++ ] = P0; + + [ P4 ++ ] = P0; + [ FP ++ ] = P5; + + loadsym p4, DATA_ADDR_5; + loadsym fp, DATA_ADDR_6; + R1 = [ P4 ++ ]; + R2 = [ FP ++ ]; + R4 = [ P4 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r1, 0x1B342618; + CHECKREG r2, 0x2C453729; + CHECKREG r4, 0x2C453729; + CHECKREG r5, 0x125AFBD3; + R1 = [ P4 ++ ]; + R2 = [ FP ++ ]; + R4 = [ P4 ++ ]; + R5 = [ FP ++ ]; + CHECKREG r1, 0x125AFBD3; + CHECKREG r2, 0x0A231507; + CHECKREG r4, 0x8C8D8E8F; + CHECKREG r5, 0xACADAEAF; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + .data + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_6: + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +DATA_ADDR_7: + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_b.s b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_b.s new file mode 100644 index 0000000..74b4222 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_b.s @@ -0,0 +1,554 @@ +//Original:testcases/core/c_ldstidxl_ld_dr_b/c_ldstidxl_ld_dr_b.dsp +// Spec Reference: c_ldstidxl load dreg B (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; + +// initial values + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + + R0 = B [ P1 + 151 ] (Z); + R1 = B [ P1 + 83 ] (Z); + R2 = B [ P1 + 45 ] (Z); + R3 = B [ P1 + 17 ] (Z); + R4 = B [ P1 + 39 ] (Z); + R5 = B [ P1 + 21 ] (Z); + R6 = B [ P1 + 123 ] (Z); + R7 = B [ P1 + 155 ] (Z); + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000018; + CHECKREG r2, 0x00000076; + CHECKREG r3, 0x00000012; + CHECKREG r4, 0x00000055; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000058; + CHECKREG r7, 0x00000004; + + R0 = B [ P2 + -121 ] (Z); + R1 = B [ P2 + -113 ] (Z); + R2 = B [ P2 + -35 ] (Z); + R3 = B [ P2 + -27 ] (Z); + R4 = B [ P2 + -49 ] (Z); + R5 = B [ P2 + -5 ] (Z); + R6 = B [ P2 + -51 ] (Z); + R7 = B [ P2 + -147 ] (Z); + CHECKREG r0, 0x000000CF; + CHECKREG r1, 0x000000D7; + CHECKREG r2, 0x00000056; + CHECKREG r3, 0x00000064; + CHECKREG r4, 0x00000094; + CHECKREG r5, 0x0000004C; + CHECKREG r6, 0x00000099; + CHECKREG r7, 0x0000004E; + + R0 = B [ P4 + 47 ] (Z); + R1 = B [ P4 + -41 ] (Z); + R2 = B [ P4 + 38 ] (Z); + R3 = B [ P4 + -31 ] (Z); + R4 = B [ P4 + 28 ] (Z); + R5 = B [ P4 + 26 ] (Z); + R6 = B [ P4 + -22 ] (Z); + R7 = B [ P4 + 105 ] (Z); + CHECKREG r0, 0x00000050; + CHECKREG r1, 0x00000093; + CHECKREG r2, 0x00000049; + CHECKREG r3, 0x00000099; + CHECKREG r4, 0x00000043; + CHECKREG r5, 0x00000067; + CHECKREG r6, 0x000000E8; + CHECKREG r7, 0x00000099; + + R0 = B [ P5 + -14 ] (Z); + R1 = B [ P5 + 12 ] (Z); + R2 = B [ P5 + -6 ] (Z); + R3 = B [ P5 + 4 ] (Z); + R4 = B [ P5 + 0 ] (Z); + R5 = B [ P5 + -2 ] (Z); + R6 = B [ P5 + 8 ] (Z); + R7 = B [ P5 + -107 ] (Z); + CHECKREG r0, 0x00000035; + CHECKREG r1, 0x00000065; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000057; + CHECKREG r4, 0x00000053; + CHECKREG r5, 0x00000047; + CHECKREG r6, 0x00000061; + CHECKREG r7, 0x00000006; + + R0 = B [ FP + 99 ] (Z); + R1 = B [ FP + -15 ] (Z); + R2 = B [ FP + 41 ] (Z); + R3 = B [ FP + -65 ] (Z); + R4 = B [ FP + 25 ] (Z); + R5 = B [ FP + -34 ] (Z); + R6 = B [ FP + 37 ] (Z); + R7 = B [ FP + -97 ] (Z); + CHECKREG r0, 0x00000093; + CHECKREG r1, 0x00000099; + CHECKREG r2, 0x0000004E; + CHECKREG r3, 0x000000D7; + CHECKREG r4, 0x00000068; + CHECKREG r5, 0x000000E8; + CHECKREG r6, 0x0000004A; + CHECKREG r7, 0x0000004C; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_h.s b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_h.s new file mode 100644 index 0000000..334ad17 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_h.s @@ -0,0 +1,595 @@ +//Original:testcases/core/c_ldstidxl_ld_dr_h/c_ldstidxl_ld_dr_h.dsp +// Spec Reference: c_ldstidxl load dreg H (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym i1, DATA_ADDR_1, 0x70; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + loadsym i3, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + R0 = W [ P1 + 154 ] (Z); + R1 = W [ P1 + 84 ] (Z); + R2 = W [ P1 + 48 ] (Z); + R3 = W [ P1 + 10 ] (Z); + R4 = W [ P1 + 34 ] (Z); + R5 = W [ P1 + 20 ] (Z); + R6 = W [ P1 + 126 ] (Z); + R7 = W [ P1 + 154 ] (Z); + CHECKREG r0, 0x00000405; + CHECKREG r1, 0x00002425; + CHECKREG r2, 0x00008485; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00001122; + CHECKREG r5, 0x00001617; + CHECKREG r6, 0x00006263; + CHECKREG r7, 0x00000405; + + R0 = W [ P2 + -120 ] (Z); + R1 = W [ P2 + -114 ] (Z); + R2 = W [ P2 + -36 ] (Z); + R3 = W [ P2 + -22 ] (Z); + R4 = W [ P2 + -44 ] (Z); + R5 = W [ P2 + -6 ] (Z); + R6 = W [ P2 + -52 ] (Z); + R7 = W [ P2 + -146 ] (Z); + CHECKREG r0, 0x0000D5D6; + CHECKREG r1, 0x0000D7D8; + CHECKREG r2, 0x0000565A; + CHECKREG r3, 0x0000A667; + CHECKREG r4, 0x000099EA; + CHECKREG r5, 0x00004C4D; + CHECKREG r6, 0x000099EA; + CHECKREG r7, 0x00004C4D; + + R0 = W [ P3 + 56 ] (Z); + R1 = W [ P3 + 62 ] (Z); + R2 = W [ P3 + -64 ] (Z); + R3 = W [ P3 + 60 ] (Z); + R4 = W [ P3 + -56 ] (Z); + R5 = W [ P3 + 10 ] (Z); + R6 = W [ P3 + -28 ] (Z); + R7 = W [ P3 + -110 ] (Z); + CHECKREG r0, 0x00001617; + CHECKREG r1, 0x00001819; + CHECKREG r2, 0x00008485; + CHECKREG r3, 0x00001A1B; + CHECKREG r4, 0x00008283; + CHECKREG r5, 0x00005859; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00000001; + + R0 = W [ P4 + 42 ] (Z); + R1 = W [ P4 + -40 ] (Z); + R2 = W [ P4 + 38 ] (Z); + R3 = W [ P4 + -32 ] (Z); + R4 = W [ P4 + 28 ] (Z); + R5 = W [ P4 + 26 ] (Z); + R6 = W [ P4 + -22 ] (Z); + R7 = W [ P4 + 106 ] (Z); + CHECKREG r0, 0x00004C4D; + CHECKREG r1, 0x000099EA; + CHECKREG r2, 0x00004849; + CHECKREG r3, 0x000099EA; + CHECKREG r4, 0x00004243; + CHECKREG r5, 0x0000A667; + CHECKREG r6, 0x000098E8; + CHECKREG r7, 0x000095E8; + + R0 = W [ P5 + -14 ] (Z); + R1 = W [ P5 + 12 ] (Z); + R2 = W [ P5 + -6 ] (Z); + R3 = W [ P5 + 4 ] (Z); + R4 = W [ P5 + 0 ] (Z); + R5 = W [ P5 + -2 ] (Z); + R6 = W [ P5 + 8 ] (Z); + R7 = W [ P5 + -108 ] (Z); + CHECKREG r0, 0x00003435; + CHECKREG r1, 0x00006465; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00005657; + CHECKREG r4, 0x00005253; + CHECKREG r5, 0x00004647; + CHECKREG r6, 0x00006061; + CHECKREG r7, 0x00000607; + + R0 = W [ FP + 90 ] (Z); + R1 = W [ FP + -14 ] (Z); + R2 = W [ FP + 42 ] (Z); + R3 = W [ FP + -66 ] (Z); + R4 = W [ FP + 26 ] (Z); + R5 = W [ FP + -34 ] (Z); + R6 = W [ FP + 38 ] (Z); + R7 = W [ FP + -98 ] (Z); + CHECKREG r0, 0x000091E8; + CHECKREG r1, 0x000091E8; + CHECKREG r2, 0x00004C4D; + CHECKREG r3, 0x0000D7D8; + CHECKREG r4, 0x0000A667; + CHECKREG r5, 0x000095E8; + CHECKREG r6, 0x00004849; + CHECKREG r7, 0x00004C4D; + + R0 = W [ SP + 46 ] (Z); + R1 = W [ SP + -42 ] (Z); + R2 = W [ SP + 48 ] (Z); + R3 = W [ SP + 50 ] (Z); + R4 = W [ SP + -102 ] (Z); + R5 = W [ SP + 82 ] (Z); + R6 = W [ SP + 62 ] (Z); + R7 = W [ SP + 46 ] (Z); + CHECKREG r0, 0x00000809; + CHECKREG r1, 0x00000506; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00000C0D; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0x00007475; + CHECKREG r6, 0x00001819; + CHECKREG r7, 0x00000809; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xb.s b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xb.s new file mode 100644 index 0000000..e5a3515 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xb.s @@ -0,0 +1,594 @@ +//Original:testcases/core/c_ldstidxl_ld_dr_xb/c_ldstidxl_ld_dr_xb.dsp +// Spec Reference: c_ldstidxl load dreg XB (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym i1, DATA_ADDR_1, 0x70; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + loadsym i3, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + R0 = B [ P1 + 151 ] (X); + R1 = B [ P1 + 83 ] (X); + R2 = B [ P1 + 45 ] (X); + R3 = B [ P1 + 17 ] (X); + R4 = B [ P1 + 39 ] (X); + R5 = B [ P1 + 21 ] (X); + R6 = B [ P1 + 123 ] (X); + R7 = B [ P1 + 155 ] (X); + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000018; + CHECKREG r2, 0x00000076; + CHECKREG r3, 0x00000012; + CHECKREG r4, 0x00000055; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000058; + CHECKREG r7, 0x00000004; + + R0 = B [ P2 + -121 ] (X); + R1 = B [ P2 + -113 ] (X); + R2 = B [ P2 + -35 ] (X); + R3 = B [ P2 + -27 ] (X); + R4 = B [ P2 + -49 ] (X); + R5 = B [ P2 + -5 ] (X); + R6 = B [ P2 + -51 ] (X); + R7 = B [ P2 + -147 ] (X); + CHECKREG r0, 0xFFFFFFCF; + CHECKREG r1, 0xFFFFFFD7; + CHECKREG r2, 0x00000056; + CHECKREG r3, 0x00000064; + CHECKREG r4, 0xFFFFFF94; + CHECKREG r5, 0x0000004C; + CHECKREG r6, 0xFFFFFF99; + CHECKREG r7, 0x0000004E; + + R0 = B [ P3 + 56 ] (X); + R1 = B [ P3 + 62 ] (X); + R2 = B [ P3 + -63 ] (X); + R3 = B [ P3 + 61 ] (X); + R4 = B [ P3 + -59 ] (X); + R5 = B [ P3 + 11 ] (X); + R6 = B [ P3 + -23 ] (X); + R7 = B [ P3 + -111 ] (X); + CHECKREG r0, 0x00000017; + CHECKREG r1, 0x00000019; + CHECKREG r2, 0xFFFFFF84; + CHECKREG r3, 0x0000001A; + CHECKREG r4, 0xFFFFFF88; + CHECKREG r5, 0x00000058; + CHECKREG r6, 0x00000028; + CHECKREG r7, 0x00000002; + + R0 = B [ P4 + 47 ] (X); + R1 = B [ P4 + -41 ] (X); + R2 = B [ P4 + 38 ] (X); + R3 = B [ P4 + -31 ] (X); + R4 = B [ P4 + 28 ] (X); + R5 = B [ P4 + 26 ] (X); + R6 = B [ P4 + -22 ] (X); + R7 = B [ P4 + 105 ] (X); + CHECKREG r0, 0x00000050; + CHECKREG r1, 0xFFFFFF93; + CHECKREG r2, 0x00000049; + CHECKREG r3, 0xFFFFFF99; + CHECKREG r4, 0x00000043; + CHECKREG r5, 0x00000067; + CHECKREG r6, 0xFFFFFFE8; + CHECKREG r7, 0xFFFFFF99; + + R0 = B [ P5 + -14 ] (X); + R1 = B [ P5 + 12 ] (X); + R2 = B [ P5 + -6 ] (X); + R3 = B [ P5 + 4 ] (X); + R4 = B [ P5 + 0 ] (X); + R5 = B [ P5 + -2 ] (X); + R6 = B [ P5 + 8 ] (X); + R7 = B [ P5 + -107 ] (X); + CHECKREG r0, 0x00000035; + CHECKREG r1, 0x00000065; + CHECKREG r2, 0x00000043; + CHECKREG r3, 0x00000057; + CHECKREG r4, 0x00000053; + CHECKREG r5, 0x00000047; + CHECKREG r6, 0x00000061; + CHECKREG r7, 0x00000006; + + R0 = B [ FP + 99 ] (X); + R1 = B [ FP + -15 ] (X); + R2 = B [ FP + 41 ] (X); + R3 = B [ FP + -65 ] (X); + R4 = B [ FP + 25 ] (X); + R5 = B [ FP + -34 ] (X); + R6 = B [ FP + 37 ] (X); + R7 = B [ FP + -97 ] (X); + CHECKREG r0, 0xFFFFFF93; + CHECKREG r1, 0xFFFFFF99; + CHECKREG r2, 0x0000004E; + CHECKREG r3, 0xFFFFFFD7; + CHECKREG r4, 0x00000068; + CHECKREG r5, 0xFFFFFFE8; + CHECKREG r6, 0x0000004A; + CHECKREG r7, 0x0000004C; + + R0 = B [ SP + 46 ] (X); + R1 = B [ SP + -41 ] (X); + R2 = B [ SP + 48 ] (X); + R3 = B [ SP + 51 ] (X); + R4 = B [ SP + -102 ] (X); + R5 = B [ SP + 89 ] (X); + R6 = B [ SP + 62 ] (X); + R7 = B [ SP + 43 ] (X); + CHECKREG r0, 0x00000009; + CHECKREG r1, 0x00000005; + CHECKREG r2, 0x0000000F; + CHECKREG r3, 0x0000000C; + CHECKREG r4, 0x00000009; + CHECKREG r5, 0xFFFFFF88; + CHECKREG r6, 0x00000019; + CHECKREG r7, 0x00000004; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s new file mode 100644 index 0000000..7d1dda1 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s @@ -0,0 +1,595 @@ +//Original:testcases/core/c_ldstidxl_ld_dr_xh/c_ldstidxl_ld_dr_xh.dsp +// Spec Reference: c_ldstidxl load dreg XH (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym i1, DATA_ADDR_1, 0x70; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + loadsym i3, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + R0 = W [ P1 + 154 ] (X); + R1 = W [ P1 + 84 ] (X); + R2 = W [ P1 + 48 ] (X); + R3 = W [ P1 + 10 ] (X); + R4 = W [ P1 + 34 ] (X); + R5 = W [ P1 + 20 ] (X); + R6 = W [ P1 + 126 ] (X); + R7 = W [ P1 + 154 ] (X); + CHECKREG r0, 0x00000405; + CHECKREG r1, 0x00002425; + CHECKREG r2, 0xFFFF8485; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00001122; + CHECKREG r5, 0x00001617; + CHECKREG r6, 0x00006263; + CHECKREG r7, 0x00000405; + + R0 = W [ P2 + -120 ] (X); + R1 = W [ P2 + -114 ] (X); + R2 = W [ P2 + -36 ] (X); + R3 = W [ P2 + -22 ] (X); + R4 = W [ P2 + -44 ] (X); + R5 = W [ P2 + -6 ] (X); + R6 = W [ P2 + -52 ] (X); + R7 = W [ P2 + -146 ] (X); + CHECKREG r0, 0xFFFFD5D6; + CHECKREG r1, 0xFFFFD7D8; + CHECKREG r2, 0x0000565A; + CHECKREG r3, 0xFFFFA667; + CHECKREG r4, 0xFFFF99EA; + CHECKREG r5, 0x00004C4D; + CHECKREG r6, 0xFFFF99EA; + CHECKREG r7, 0x00004C4D; + + R0 = W [ P3 + 56 ] (X); + R1 = W [ P3 + 62 ] (X); + R2 = W [ P3 + -64 ] (X); + R3 = W [ P3 + 60 ] (X); + R4 = W [ P3 + -56 ] (X); + R5 = W [ P3 + 10 ] (X); + R6 = W [ P3 + -28 ] (X); + R7 = W [ P3 + -110 ] (X); + CHECKREG r0, 0x00001617; + CHECKREG r1, 0x00001819; + CHECKREG r2, 0xFFFF8485; + CHECKREG r3, 0x00001A1B; + CHECKREG r4, 0xFFFF8283; + CHECKREG r5, 0x00005859; + CHECKREG r6, 0x00002425; + CHECKREG r7, 0x00000001; + + R0 = W [ P4 + 42 ] (X); + R1 = W [ P4 + -40 ] (X); + R2 = W [ P4 + 38 ] (X); + R3 = W [ P4 + -32 ] (X); + R4 = W [ P4 + 28 ] (X); + R5 = W [ P4 + 26 ] (X); + R6 = W [ P4 + -22 ] (X); + R7 = W [ P4 + 106 ] (X); + CHECKREG r0, 0x00004C4D; + CHECKREG r1, 0xFFFF99EA; + CHECKREG r2, 0x00004849; + CHECKREG r3, 0xFFFF99EA; + CHECKREG r4, 0x00004243; + CHECKREG r5, 0xFFFFA667; + CHECKREG r6, 0xFFFF98E8; + CHECKREG r7, 0xFFFF95E8; + + R0 = W [ P5 + -14 ] (X); + R1 = W [ P5 + 12 ] (X); + R2 = W [ P5 + -6 ] (X); + R3 = W [ P5 + 4 ] (X); + R4 = W [ P5 + 0 ] (X); + R5 = W [ P5 + -2 ] (X); + R6 = W [ P5 + 8 ] (X); + R7 = W [ P5 + -108 ] (X); + CHECKREG r0, 0x00003435; + CHECKREG r1, 0x00006465; + CHECKREG r2, 0x00004243; + CHECKREG r3, 0x00005657; + CHECKREG r4, 0x00005253; + CHECKREG r5, 0x00004647; + CHECKREG r6, 0x00006061; + CHECKREG r7, 0x00000607; + + R0 = W [ FP + 90 ] (X); + R1 = W [ FP + -14 ] (X); + R2 = W [ FP + 42 ] (X); + R3 = W [ FP + -66 ] (X); + R4 = W [ FP + 26 ] (X); + R5 = W [ FP + -34 ] (X); + R6 = W [ FP + 38 ] (X); + R7 = W [ FP + -98 ] (X); + CHECKREG r0, 0xFFFF91E8; + CHECKREG r1, 0xFFFF91E8; + CHECKREG r2, 0x00004C4D; + CHECKREG r3, 0xFFFFD7D8; + CHECKREG r4, 0xFFFFA667; + CHECKREG r5, 0xFFFF95E8; + CHECKREG r6, 0x00004849; + CHECKREG r7, 0x00004C4D; + + R0 = W [ SP + 46 ] (X); + R1 = W [ SP + -42 ] (X); + R2 = W [ SP + 48 ] (X); + R3 = W [ SP + 50 ] (X); + R4 = W [ SP + -102 ] (X); + R5 = W [ SP + 82 ] (X); + R6 = W [ SP + 62 ] (X); + R7 = W [ SP + 46 ] (X); + CHECKREG r0, 0x00000809; + CHECKREG r1, 0x00000506; + CHECKREG r2, 0x00000E0F; + CHECKREG r3, 0x00000C0D; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0x00007475; + CHECKREG r6, 0x00001819; + CHECKREG r7, 0x00000809; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dreg.s b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dreg.s new file mode 100644 index 0000000..4c25099 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstidxl_ld_dreg.s @@ -0,0 +1,554 @@ +//Original:testcases/core/c_ldstidxl_ld_dreg/c_ldstidxl_ld_dreg.dsp +// Spec Reference: c_ldstidxl load dreg (ld with indexed addressing) +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; + +// initial values + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + + R0 = [ P1 + 156 ]; + R1 = [ P1 + 84 ]; + R2 = [ P1 + 48 ]; + R3 = [ P1 + 12 ]; + R4 = [ P1 + 36 ]; + R5 = [ P1 + 20 ]; + R6 = [ P1 + 128 ]; + R7 = [ P1 + 156 ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x22232425; + CHECKREG r2, 0x82838485; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x55667788; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x66676869; + CHECKREG r7, 0x08090A0B; + + R0 = [ P2 + -120 ]; + R1 = [ P2 + -112 ]; + R2 = [ P2 + -36 ]; + R3 = [ P2 + -24 ]; + R4 = [ P2 + -44 ]; + R5 = [ P2 + -8 ]; + R6 = [ P2 + -52 ]; + R7 = [ P2 + -148 ]; + CHECKREG r0, 0xD3D4D5D6; + CHECKREG r1, 0xDBDCDDDE; + CHECKREG r2, 0xA455565A; + CHECKREG r3, 0xA667686A; + CHECKREG r4, 0x96E899EA; + CHECKREG r5, 0x4C4D4E4F; + CHECKREG r6, 0x94E899EA; + CHECKREG r7, 0x4C4D4E4F; + + R0 = [ P4 + 44 ]; + R1 = [ P4 + -40 ]; + R2 = [ P4 + 36 ]; + R3 = [ P4 + -32 ]; + R4 = [ P4 + 28 ]; + R5 = [ P4 + 24 ]; + R6 = [ P4 + -20 ]; + R7 = [ P4 + 108 ]; + CHECKREG r0, 0x50515253; + CHECKREG r1, 0x94E899EA; + CHECKREG r2, 0x48494A4B; + CHECKREG r3, 0x96E899EA; + CHECKREG r4, 0x40414243; + CHECKREG r5, 0xA667686A; + CHECKREG r6, 0x99E899EA; + CHECKREG r7, 0x96E899EA; + + R0 = [ P5 + -16 ]; + R1 = [ P5 + 12 ]; + R2 = [ P5 + -8 ]; + R3 = [ P5 + 4 ]; + R4 = [ P5 + 0 ]; + R5 = [ P5 + -4 ]; + R6 = [ P5 + 8 ]; + R7 = [ P5 + -108 ]; + CHECKREG r0, 0x34353637; + CHECKREG r1, 0x62636465; + CHECKREG r2, 0x42434445; + CHECKREG r3, 0x54555657; + CHECKREG r4, 0x50515253; + CHECKREG r5, 0x46474849; + CHECKREG r6, 0x58596061; + CHECKREG r7, 0x04050607; + + R0 = [ FP + 92 ]; + R1 = [ FP + -16 ]; + R2 = [ FP + 40 ]; + R3 = [ FP + -64 ]; + R4 = [ FP + 28 ]; + R5 = [ FP + -32 ]; + R6 = [ FP + 36 ]; + R7 = [ FP + -96 ]; + CHECKREG r0, 0x92E899EA; + CHECKREG r1, 0x91E899EA; + CHECKREG r2, 0x4C4D4E4F; + CHECKREG r3, 0xDBDCDDDE; + CHECKREG r4, 0x40414243; + CHECKREG r5, 0x96E899EA; + CHECKREG r6, 0x48494A4B; + CHECKREG r7, 0x50515253; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + +DATA_ADDR_2: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_preg.s b/sim/testsuite/sim/bfin/c_ldstidxl_ld_preg.s new file mode 100644 index 0000000..503c24e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstidxl_ld_preg.s @@ -0,0 +1,672 @@ +//Original:testcases/core/c_ldstidxl_ld_preg/c_ldstidxl_ld_preg.dsp +// Spec Reference: c_ldstidxl load dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xA0; + loadsym i1, DATA_ADDR_1, 0x70; + loadsym p4, DATA_ADDR_2, 0x70; + loadsym p5, DATA_ADDR_1, 0x70; + loadsym fp, DATA_ADDR_2, 0x70; + loadsym i3, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + P2 = [ P1 + 12 ]; + P3 = [ P1 + 44 ]; + P4 = [ P1 + 8 ]; + P5 = [ P1 + 156 ]; + SP = [ P1 + 16 ]; + FP = [ P1 + 120 ]; + P1 = [ P1 + 24 ]; + CHECKREG p1, 0x18191A1B; + CHECKREG p2, 0x0C0D0E0F; + CHECKREG p3, 0x74757677; + CHECKREG p4, 0x08090A0B; + CHECKREG p5, 0x08090A0B; + CHECKREG sp, 0x10111213; + CHECKREG fp, 0x58596061; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0xA0; + P3 = I1; SP = I3; + + P1 = [ P2 + -128 ]; + P3 = [ P2 + -36 ]; + P4 = [ P2 + -40 ]; + P5 = [ P2 + -144 ]; + SP = [ P2 + -48 ]; + FP = [ P2 + 52 ]; + P2 = [ P2 + -132 ]; + CHECKREG p1, 0xEBECEDEE; + CHECKREG p2, 0x7C7D7E7F; + CHECKREG p3, 0xA60CAD7E; + CHECKREG p4, 0xA50CAD6E; + CHECKREG p5, 0x70717273; + CHECKREG sp, 0xA30CAD4E; + CHECKREG fp, 0x64656667; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + P1 = [ P3 + 56 ]; + P2 = [ P3 + -104 ]; + P4 = [ P3 + 80 ]; + P5 = [ P3 + -56 ]; + SP = [ P3 + 52 ]; + FP = [ P3 + -48 ]; + P3 = [ P3 + 84 ]; + CHECKREG p1, 0x14151617; + CHECKREG p2, 0x08090A0B; + CHECKREG p3, 0x82838485; + CHECKREG p4, 0x74757677; + CHECKREG p5, 0x80818283; + CHECKREG sp, 0x10111213; + CHECKREG fp, 0x01020304; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_2, 0x70; + P3 = I1; SP = I3; + P1 = [ P4 + 44 ]; + P2 = [ P4 + -40 ]; + P3 = [ P4 + -96 ]; + P5 = [ P4 + -68 ]; + SP = [ P4 + 84 ]; + FP = [ P4 + 108 ]; + P4 = [ P4 + -32 ]; + CHECKREG p1, 0x6C6D6E6F; + CHECKREG p2, 0xAB0CAD03; + CHECKREG p3, 0x70717273; + CHECKREG p4, 0xAB0CAD05; + CHECKREG p5, 0xFBFCFDFE; + CHECKREG sp, 0x03040506; + CHECKREG fp, 0x6C6D6E6F; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x70; + P3 = I1; SP = I3; + + P1 = [ P5 + 16 ]; + P2 = [ P5 + 12 ]; + P3 = [ P5 + 96 ]; + P4 = [ P5 + 0 ]; + SP = [ P5 + -44 ]; + FP = [ P5 + 28 ]; + P5 = [ P5 + -84 ]; + CHECKREG p1, 0x66676869; + CHECKREG p2, 0x62636465; + CHECKREG p3, 0x84858687; + CHECKREG p4, 0x50515253; + CHECKREG p5, 0x1C1D1E1F; + CHECKREG sp, 0x05060708; + CHECKREG fp, 0x72636467; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_2, 0x70; + P3 = I1; SP = I3; + + P1 = [ SP + -72 ]; + P2 = [ SP + 16 ]; + P3 = [ SP + -80 ]; + P4 = [ SP + 92 ]; + P5 = [ SP + -28 ]; + FP = [ SP + 32 ]; + SP = [ SP + -36 ]; + CHECKREG p1, 0xF7F8F9FA; + CHECKREG p2, 0xB455565B; + CHECKREG p3, 0xEBECEDEE; + CHECKREG p4, 0x0B0CAD0E; + CHECKREG p5, 0xAB0CAD06; + CHECKREG sp, 0xAB0CAD04; + CHECKREG fp, 0x60616263; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_2, 0x70; + P3 = I1; SP = I3; + + P1 = [ FP + 40 ]; + P2 = [ FP + 44 ]; + P3 = [ FP + 96 ]; + P4 = [ FP + 52 ]; + P5 = [ FP + 104 ]; + SP = [ FP + 60 ]; + FP = [ FP + 64 ]; + CHECKREG p1, 0x68696A6B; + CHECKREG p2, 0x6C6D6E6F; + CHECKREG p3, 0x60616263; + CHECKREG p4, 0x74757677; + CHECKREG p5, 0x68696A6B; + CHECKREG sp, 0x7C7D7E7F; + CHECKREG fp, 0xEBECEDEE; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xa667686a + +DATA_ADDR_2: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_b.s b/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_b.s new file mode 100644 index 0000000..5ed1a11 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_b.s @@ -0,0 +1,612 @@ +//Original:testcases/core/c_ldstidxl_st_dr_b/c_ldstidxl_st_dr_b.dsp +// Spec Reference: c_ldstidxl store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f5080; + imm32 r1, 0x204e6091; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80b3; + imm32 r4, 0x501b90c4; + imm32 r5, 0x600aa0d5; + imm32 r6, 0x7019b0e6; + imm32 r7, 0xd028c0f7; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xc8; + loadsym i1, DATA_ADDR_1, 0x10; + loadsym p4, DATA_ADDR_2, 0xc8; + loadsym p5, DATA_ADDR_1, 0x00; + loadsym fp, DATA_ADDR_2, 0xc8; + loadsym i3, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + B [ P1 + 0x1101 ] = R0; + B [ P1 + 0x1013 ] = R1; + B [ P1 + 0x1015 ] = R2; + B [ P1 + 0x1007 ] = R3; + B [ P2 + -0x1019 ] = R4; + B [ P2 + -0x1011 ] = R5; + B [ P2 + -0x1013 ] = R6; + B [ P2 + -0x1015 ] = R7; + R6 = B [ P1 + 0x1101 ] (Z); + R5 = B [ P1 + 0x1013 ] (Z); + R4 = B [ P1 + 0x1015 ] (Z); + R3 = B [ P1 + 0x1007 ] (Z); + R2 = B [ P2 + -0x1019 ] (Z); + R7 = B [ P2 + -0x1011 ] (Z); + R0 = B [ P2 + -0x1013 ] (Z); + R1 = B [ P2 + -0x1015 ] (Z); + CHECKREG r0, 0x000000E6; + CHECKREG r1, 0x000000F7; + CHECKREG r2, 0x000000C4; + CHECKREG r3, 0x000000B3; + CHECKREG r4, 0x000000A2; + CHECKREG r5, 0x00000091; + CHECKREG r6, 0x00000080; + CHECKREG r7, 0x000000D5; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + B [ P3 + 0x1011 ] = R0; + B [ P3 + 0x1023 ] = R1; + B [ P3 + 0x1025 ] = R2; + B [ P3 + 0x1027 ] = R3; + B [ P4 + -0x1029 ] = R4; + B [ P4 + -0x1021 ] = R5; + B [ P4 + -0x1033 ] = R6; + B [ P4 + -0x1035 ] = R7; + R3 = B [ P3 + 0x1011 ] (Z); + R4 = B [ P3 + 0x1023 ] (Z); + R0 = B [ P3 + 0x1025 ] (Z); + R1 = B [ P3 + 0x1027 ] (Z); + R2 = B [ P4 + -0x1029 ] (Z); + R5 = B [ P4 + -0x1021 ] (Z); + R6 = B [ P4 + -0x1033 ] (Z); + R7 = B [ P4 + -0x1035 ] (Z); + CHECKREG r0, 0x000000B2; + CHECKREG r1, 0x000000B3; + CHECKREG r2, 0x000000B4; + CHECKREG r3, 0x000000B0; + CHECKREG r4, 0x000000B1; + CHECKREG r5, 0x000000B5; + CHECKREG r6, 0x000000B6; + CHECKREG r7, 0x000000B7; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + B [ P5 + 0x1031 ] = R0; + B [ P5 + 0x1033 ] = R1; + B [ P5 + 0x1035 ] = R2; + B [ P5 + 0x1047 ] = R3; + B [ SP + -0x1049 ] = R4; + B [ SP + -0x1041 ] = R5; + B [ SP + -0x1043 ] = R6; + B [ SP + -0x1045 ] = R7; + R6 = B [ P5 + 0x1031 ] (Z); + R5 = B [ P5 + 0x1033 ] (Z); + R4 = B [ P5 + 0x1035 ] (Z); + R3 = B [ P5 + 0x1047 ] (Z); + R2 = B [ SP + -0x1049 ] (Z); + R0 = B [ SP + -0x1041 ] (Z); + R7 = B [ SP + -0x1043 ] (Z); + R1 = B [ SP + -0x1045 ] (Z); + CHECKREG r0, 0x000000C5; + CHECKREG r1, 0x000000C7; + CHECKREG r2, 0x000000C4; + CHECKREG r3, 0x000000C3; + CHECKREG r4, 0x000000C2; + CHECKREG r5, 0x000000C1; + CHECKREG r6, 0x000000C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + B [ FP + 0x1051 ] = R0; + B [ FP + 0x1053 ] = R1; + B [ FP + 0x1055 ] = R2; + B [ FP + 0x1057 ] = R3; + B [ FP + 0x1059 ] = R4; + B [ FP + 0x1061 ] = R5; + B [ FP + 0x1063 ] = R6; + B [ FP + 0x1065 ] = R7; + R3 = B [ FP + 0x1051 ] (Z); + R4 = B [ FP + 0x1053 ] (Z); + R0 = B [ FP + 0x1055 ] (Z); + R1 = B [ FP + 0x1057 ] (Z); + R2 = B [ FP + 0x1059 ] (Z); + R5 = B [ FP + 0x1061 ] (Z); + R6 = B [ FP + 0x1063 ] (Z); + R7 = B [ FP + 0x1065 ] (Z); + CHECKREG r0, 0x000000D2; + CHECKREG r1, 0x000000D3; + CHECKREG r2, 0x000000D4; + CHECKREG r3, 0x000000D0; + CHECKREG r4, 0x000000D1; + CHECKREG r5, 0x000000D5; + CHECKREG r6, 0x000000D6; + CHECKREG r7, 0x000000D7; + + P3 = I0; SP = I2; + pass + +// Pre-load memory witb known data +// More data is defined than will actually be used + + .data +// Make sure there is space between the text and data sections + .space (0x2000); + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + +// Make sure there is space for us to scribble + .space (0x2000); diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_h.s b/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_h.s new file mode 100644 index 0000000..114d192 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstidxl_st_dr_h.s @@ -0,0 +1,609 @@ +//Original:testcases/core/c_ldstidxl_st_dr_h/c_ldstidxl_st_dr_h.dsp +// Spec Reference: c_ldstidxl store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xc8; + loadsym i1, DATA_ADDR_1, 0x10; + loadsym p4, DATA_ADDR_2, 0xc8; + loadsym p5, DATA_ADDR_1, 0x00; + loadsym fp, DATA_ADDR_2, 0xc8; + loadsym i3, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + W [ P1 + 0x1002 ] = R0; + W [ P1 + 0x1004 ] = R1; + W [ P1 + 0x1006 ] = R2; + W [ P1 + 0x1008 ] = R3; + W [ P2 + -0x1010 ] = R4; + W [ P2 + -0x1022 ] = R5; + W [ P2 + -0x1034 ] = R6; + W [ P2 + -0x1046 ] = R7; + R6 = W [ P1 + 0x1002 ] (Z); + R5 = W [ P1 + 0x1004 ] (Z); + R4 = W [ P1 + 0x1006 ] (Z); + R3 = W [ P1 + 0x1008 ] (Z); + R2 = W [ P2 + -0x1010 ] (Z); + R7 = W [ P2 + -0x1022 ] (Z); + R0 = W [ P2 + -0x1034 ] (Z); + R1 = W [ P2 + -0x1046 ] (Z); + CHECKREG r0, 0x0000B0A6; + CHECKREG r1, 0x0000C0A7; + CHECKREG r2, 0x000090A4; + CHECKREG r3, 0x000080A3; + CHECKREG r4, 0x000070A2; + CHECKREG r5, 0x000060A1; + CHECKREG r6, 0x000050A0; + CHECKREG r7, 0x0000A0A5; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + W [ P3 + 0x1018 ] = R0; + W [ P3 + 0x1020 ] = R1; + W [ P3 + 0x1022 ] = R2; + W [ P3 + 0x1024 ] = R3; + W [ P4 + -0x1026 ] = R4; + W [ P4 + -0x1028 ] = R5; + W [ P4 + -0x1030 ] = R6; + W [ P4 + -0x1052 ] = R7; + R3 = W [ P3 + 0x1018 ] (Z); + R4 = W [ P3 + 0x1020 ] (Z); + R0 = W [ P3 + 0x1022 ] (Z); + R1 = W [ P3 + 0x1024 ] (Z); + R2 = W [ P4 + -0x1026 ] (Z); + R5 = W [ P4 + -0x1028 ] (Z); + R6 = W [ P4 + -0x1030 ] (Z); + R7 = W [ P4 + -0x1052 ] (Z); + CHECKREG r0, 0x000070B2; + CHECKREG r1, 0x000080B3; + CHECKREG r2, 0x000090B4; + CHECKREG r3, 0x000050B0; + CHECKREG r4, 0x000060B1; + CHECKREG r5, 0x0000A0B5; + CHECKREG r6, 0x0000B0B6; + CHECKREG r7, 0x0000C0B7; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + W [ P5 + 0x1034 ] = R0; + W [ P5 + 0x1036 ] = R1; + W [ P5 + 0x1038 ] = R2; + W [ P5 + 0x1040 ] = R3; + W [ SP + -0x1042 ] = R4; + W [ SP + -0x1054 ] = R5; + W [ SP + -0x1066 ] = R6; + W [ SP + -0x1078 ] = R7; + R6 = W [ P5 + 0x1034 ] (Z); + R5 = W [ P5 + 0x1036 ] (Z); + R4 = W [ P5 + 0x1038 ] (Z); + R3 = W [ P5 + 0x1040 ] (Z); + R2 = W [ SP + -0x1042 ] (Z); + R0 = W [ SP + -0x1054 ] (Z); + R7 = W [ SP + -0x1066 ] (Z); + R1 = W [ SP + -0x1078 ] (Z); + CHECKREG r0, 0x0000A0C5; + CHECKREG r1, 0x0000C0C7; + CHECKREG r2, 0x000090C4; + CHECKREG r3, 0x000080C3; + CHECKREG r4, 0x000070C2; + CHECKREG r5, 0x000060C1; + CHECKREG r6, 0x000050C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + W [ FP + 0x1050 ] = R0; + W [ FP + 0x1052 ] = R1; + W [ FP + 0x1054 ] = R2; + W [ FP + 0x1056 ] = R3; + W [ FP + 0x1058 ] = R4; + W [ FP + 0x1060 ] = R5; + W [ FP + 0x1062 ] = R6; + W [ FP + 0x1064 ] = R7; + R3 = W [ FP + 0x1050 ] (Z); + R4 = W [ FP + 0x1052 ] (Z); + R0 = W [ FP + 0x1054 ] (Z); + R1 = W [ FP + 0x1056 ] (Z); + R2 = W [ FP + 0x1058 ] (Z); + R5 = W [ FP + 0x1060 ] (Z); + R6 = W [ FP + 0x1062 ] (Z); + R7 = W [ FP + 0x1064 ] (Z); + CHECKREG r0, 0x000070D2; + CHECKREG r1, 0x000080D3; + CHECKREG r2, 0x000090D4; + CHECKREG r3, 0x000050D0; + CHECKREG r4, 0x000060D1; + CHECKREG r5, 0x0000A0D5; + CHECKREG r6, 0x0000B0D6; + CHECKREG r7, 0x0000C0D7; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + .space (0x2000); +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + +// Make sure there is space for us to scribble + .space (0x2000); diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_st_dreg.s b/sim/testsuite/sim/bfin/c_ldstidxl_st_dreg.s new file mode 100644 index 0000000..ac1f028 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstidxl_st_dreg.s @@ -0,0 +1,780 @@ +//Original:testcases/core/c_ldstidxl_st_dreg/c_ldstidxl_st_dreg.dsp +// Spec Reference: c_ldstidxl store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0xc8; + loadsym i1, DATA_ADDR_1, 0x10; + loadsym p4, DATA_ADDR_2, 0xc8; + loadsym p5, DATA_ADDR_1, 0x00; + loadsym fp, DATA_ADDR_2, 0xc8; + loadsym i3, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + [ P1 + 0x1004 ] = R0; + [ P1 + 0x1008 ] = R1; + [ P1 + 0x1010 ] = R2; + [ P1 + 0x1014 ] = R3; + [ P2 + -0x1020 ] = R4; + [ P2 + -0x1024 ] = R5; + [ P2 + -0x1028 ] = R6; + [ P2 + -0x1030 ] = R7; + R6 = [ P1 + 0x1004 ]; + R5 = [ P1 + 0x1008 ]; + R4 = [ P1 + 0x1010 ]; + R3 = [ P1 + 0x1014 ]; + R2 = [ P2 + -0x1020 ]; + R7 = [ P2 + -0x1024 ]; + R0 = [ P2 + -0x1028 ]; + R1 = [ P2 + -0x1030 ]; + CHECKREG r0, 0x7019B0A6; + CHECKREG r1, 0xD028C0A7; + CHECKREG r2, 0x501B90A4; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300370A2; + CHECKREG r5, 0x204E60A1; + CHECKREG r6, 0x105F50A0; + CHECKREG r7, 0x600AA0A5; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + [ P3 + 0x1034 ] = R0; + [ P3 + 0x1040 ] = R1; + [ P3 + 0x1044 ] = R2; + [ P3 + 0x1048 ] = R3; + [ P4 + -0x1050 ] = R4; + [ P4 + -0x1054 ] = R5; + [ P4 + -0x1060 ] = R6; + [ P4 + -0x1064 ] = R7; + R3 = [ P3 + 0x1034 ]; + R4 = [ P3 + 0x1040 ]; + R0 = [ P3 + 0x1044 ]; + R1 = [ P3 + 0x1048 ]; + R2 = [ P4 + -0x1050 ]; + R5 = [ P4 + -0x1054 ]; + R6 = [ P4 + -0x1060 ]; + R7 = [ P4 + -0x1064 ]; + CHECKREG r0, 0x30BD70B2; + CHECKREG r1, 0x40BC80B3; + CHECKREG r2, 0x55BB90B4; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x20BE60B1; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B9B0B6; + CHECKREG r7, 0x80B8C0B7; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + [ P5 + 1004 ] = R0; + [ P5 + 1008 ] = R1; + [ P5 + 1012 ] = R2; + [ P5 + 1016 ] = R3; + [ SP + -0x1020 ] = R4; + [ SP + -0x1024 ] = R5; + [ SP + -0x1028 ] = R6; + [ SP + -0x1030 ] = R7; + R6 = [ P5 + 1004 ]; + R4 = [ P5 + 1008 ]; + R5 = [ P5 + 1012 ]; + R3 = [ P5 + 1016 ]; + R2 = [ SP + -0x1020 ]; + R0 = [ SP + -0x1024 ]; + R7 = [ SP + -0x1028 ]; + R1 = [ SP + -0x1030 ]; + CHECKREG r0, 0x60CAA0C5; + CHECKREG r1, 0xD0C8C0C7; + CHECKREG r2, 0x50CB90C4; + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x20CE60C1; + CHECKREG r5, 0x30C370C2; + CHECKREG r6, 0x10CF50C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + [ FP + 0x1034 ] = R0; + [ FP + 0x1040 ] = R1; + [ FP + 0x1044 ] = R2; + [ FP + 0x1048 ] = R3; + [ FP + 0x1050 ] = R4; + [ FP + 0x1054 ] = R5; + [ FP + 0x1060 ] = R6; + [ FP + 0x1064 ] = R7; + + R3 = [ FP + 0x1034 ]; + R4 = [ FP + 0x1040 ]; + R0 = [ FP + 0x1044 ]; + R1 = [ FP + 0x1048 ]; + R2 = [ FP + 0x1050 ]; + R5 = [ FP + 0x1054 ]; + R6 = [ FP + 0x1060 ]; + R7 = [ FP + 0x1064 ]; + CHECKREG r0, 0x80DD70D2; + CHECKREG r1, 0x90DC80D3; + CHECKREG r2, 0xA0DB90D4; + CHECKREG r3, 0x60DF50D0; + CHECKREG r4, 0x70DE60D1; + CHECKREG r5, 0xB0DAA0D5; + CHECKREG r6, 0xC0D9B0D6; + CHECKREG r7, 0xD0D8C0D7; + + P3 = I0; SP = I2; + pass + + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +// Make sure there is space between the text section, and the data section + .space (0x2000); + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_2: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xa263646a + .dd 0xa667686a + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + +// Make sure there is space for us to scribble + .space (0x2000); diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_st_preg.s b/sim/testsuite/sim/bfin/c_ldstidxl_st_preg.s new file mode 100644 index 0000000..6520f82 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstidxl_st_preg.s @@ -0,0 +1,709 @@ +//Original:testcases/core/c_ldstidxl_st_preg/c_ldstidxl_st_preg.dsp +// Spec Reference: c_ldstidxl store preg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + P3 = 0x0123 (X); + P4 = 0x4567 (X); + P5 = 0x79ab (X); + FP = 0x6def (X); + SP = 0x1ace (X); + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x0000; + loadsym p2, DATA_ADDR_2, 0x00c8; + P3 = I1; SP = I3; + + [ P1 + 0x1004 ] = P5; + [ P1 + 0x1008 ] = P3; + [ P1 + 0x1014 ] = P4; + [ P1 + 0x1018 ] = P3; + [ P2 + -0x1020 ] = P4; + [ P2 + -0x1024 ] = P5; + [ P2 + -0x1028 ] = SP; + [ P2 + -0x1034 ] = FP; + R6 = [ P1 + 0x1004 ]; + R5 = [ P1 + 0x1008 ]; + R4 = [ P1 + 0x1014 ]; + R3 = [ P1 + 0x1018 ]; + R2 = [ P2 + -0x1020 ]; + R7 = [ P2 + -0x1024 ]; + R0 = [ P2 + -0x1028 ]; + R1 = [ P2 + -0x1034 ]; + CHECKREG r0, 0x00001ACE; + CHECKREG r1, 0x00006DEF; + CHECKREG r2, 0x00004567; + CHECKREG r3, 0x00000123; + CHECKREG r4, 0x00004567; + CHECKREG r5, 0x00000123; + CHECKREG r6, 0x000079AB; + CHECKREG r7, 0x000079AB; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + P1 = 0x3456 (X); + P2 = 0x1234 (X); + P5 = 0x5e23 (X); + FP = 0x2ac5 (X); + SP = 0x6378 (X); + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_1, 0x0000; + loadsym p4, DATA_ADDR_2, 0x00c8; + P3 = I1; SP = I3; + + [ P3 + 0x1034 ] = P2; + [ P3 + 0x1040 ] = P1; + [ P3 + 0x1044 ] = P2; + [ P3 + 0x1048 ] = P1; + [ P4 + -0x1054 ] = P2; + [ P4 + -0x1058 ] = P5; + [ P4 + -0x1060 ] = SP; + [ P4 + -0x1064 ] = FP; + R3 = [ P3 + 0x1034 ]; + R4 = [ P3 + 0x1040 ]; + R0 = [ P3 + 0x1044 ]; + R1 = [ P3 + 0x1048 ]; + R2 = [ P4 + -0x1054 ]; + R5 = [ P4 + -0x1058 ]; + R6 = [ P4 + -0x1060 ]; + R7 = [ P4 + -0x1064 ]; + CHECKREG r0, 0x00001234; + CHECKREG r1, 0x00003456; + CHECKREG r2, 0x00001234; + CHECKREG r3, 0x00001234; + CHECKREG r4, 0x00003456; + CHECKREG r5, 0x00005E23; + CHECKREG r6, 0x00006378; + CHECKREG r7, 0x00002AC5; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + P1 = 0x2125 (X); + P2 = 0x7345 (X); + P3 = 0x3230 (X); + P4 = 0x5789 (X); + FP = 0x5bcd (X); + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x0000; + loadsym i3, DATA_ADDR_2, 0x00c8; + P3 = I1; SP = I3; + + [ P5 + 0x1004 ] = P2; + [ P5 + 0x1008 ] = P1; + [ P5 + 0x1014 ] = P2; + [ P5 + 0x1018 ] = P3; + [ SP + -0x1020 ] = P4; + [ SP + -0x1024 ] = P2; + [ SP + -0x1028 ] = P3; + [ SP + -0x1034 ] = FP; + R6 = [ P5 + 0x1004 ]; + R5 = [ P5 + 0x1008 ]; + R4 = [ P5 + 0x1014 ]; + R3 = [ P5 + 0x1018 ]; + R2 = [ SP + -0x1020 ]; + R0 = [ SP + -0x1024 ]; + R7 = [ SP + -0x1028 ]; + R1 = [ SP + -0x1034 ]; + CHECKREG r0, 0x00007345; + CHECKREG r1, 0x00005BCD; + CHECKREG r2, 0x00005789; + CHECKREG r3, 0x00003230; + CHECKREG r4, 0x00007345; + CHECKREG r5, 0x00002125; + CHECKREG r6, 0x00007345; + CHECKREG r7, 0x00003230; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + P1 = 0x5bcd (X); + P2 = 0x1122 (X); + P3 = 0x3455 (X); + P4 = 0x6677 (X); + P5 = 0x58ab (X); + SP = 0x1ace (X); + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0x0010; + P3 = I1; SP = I3; + [ FP + 0x1034 ] = P1; + [ FP + 0x2040 ] = P1; + [ FP + 0x1144 ] = P2; + [ FP + 0x2048 ] = P3; + [ FP + 0x1050 ] = P4; + [ FP + 0x2058 ] = P5; + [ FP + 0x1160 ] = P2; + [ FP + 0x2064 ] = SP; + R3 = [ FP + 0x1034 ]; + R4 = [ FP + 0x2040 ]; + R0 = [ FP + 0x1144 ]; + R1 = [ FP + 0x2048 ]; + R2 = [ FP + 0x1050 ]; + R5 = [ FP + 0x2058 ]; + R6 = [ FP + 0x1160 ]; + R7 = [ FP + 0x2064 ]; + CHECKREG r0, 0x00001122; + CHECKREG r1, 0x00003455; + CHECKREG r2, 0x00006677; + CHECKREG r3, 0x00005BCD; + CHECKREG r4, 0x00005BCD; + CHECKREG r5, 0x000058AB; + CHECKREG r6, 0x00001122; + CHECKREG r7, 0x00001ace; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +// Make sure there is space between the text and data sections + .space (0x2000); + +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_2: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF + +// Make sure there is space for us to scribble + .space (0x2000); diff --git a/sim/testsuite/sim/bfin/c_ldstii_ld_dr_h.s b/sim/testsuite/sim/bfin/c_ldstii_ld_dr_h.s new file mode 100644 index 0000000..a2daecd --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstii_ld_dr_h.s @@ -0,0 +1,541 @@ +//Original:testcases/core/c_ldstii_ld_dr_h/c_ldstii_ld_dr_h.dsp +// Spec Reference: c_ldstii load dreg h +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x04; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_1, 0x00; + loadsym p5, DATA_ADDR_2, 0x00; + loadsym fp, DATA_ADDR_3, 0x00; + loadsym i3, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + R0 = W [ P1 + 0 ] (Z); + R1 = W [ P1 + 4 ] (Z); + R2 = W [ P1 + 8 ] (Z); + R3 = W [ P1 + 12 ] (Z); + R4 = W [ P1 + 16 ] (Z); + R5 = W [ P1 + 20 ] (Z); + R6 = W [ P1 + 24 ] (Z); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000607; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000E0F; + CHECKREG r4, 0x00001213; + CHECKREG r5, 0x00001617; + CHECKREG r6, 0x00001A1B; + + R0 = W [ P2 + 28 ] (Z); + R1 = W [ P2 + 32 ] (Z); + R2 = W [ P2 + 36 ] (Z); + R3 = W [ P2 + 40 ] (Z); + R4 = W [ P2 + 44 ] (Z); + R5 = W [ P2 + 48 ] (Z); + R6 = W [ P2 + 52 ] (Z); + CHECKREG r0, 0x00009394; + CHECKREG r1, 0x00009798; + CHECKREG r2, 0x0000A2A3; + CHECKREG r3, 0x0000A7A8; + CHECKREG r4, 0x0000B1B2; + CHECKREG r5, 0x0000B5B6; + CHECKREG r6, 0x0000B9C0; + + R0 = W [ P3 + 56 ] (Z); + R1 = W [ P3 + 60 ] (Z); + R2 = W [ P3 + 64 ] (Z); + R3 = W [ P3 + 60 ] (Z); + R4 = W [ P3 + 56 ] (Z); + R5 = W [ P3 + 52 ] (Z); + R6 = W [ P3 + 48 ] (Z); + CHECKREG r0, 0x000099EA; + CHECKREG r1, 0x000099EA; + CHECKREG r2, 0x000099EA; + CHECKREG r3, 0x000099EA; + CHECKREG r4, 0x000099EA; + CHECKREG r5, 0x0000E5E6; + CHECKREG r6, 0x0000E1E2; + + R0 = W [ P4 + 44 ] (Z); + R1 = W [ P4 + 40 ] (Z); + R2 = W [ P4 + 36 ] (Z); + R3 = W [ P4 + 32 ] (Z); + R4 = W [ P4 + 28 ] (Z); + R5 = W [ P4 + 24 ] (Z); + R6 = W [ P4 + 20 ] (Z); + CHECKREG r0, 0x00007677; + CHECKREG r1, 0x00007273; + CHECKREG r2, 0x00007788; + CHECKREG r3, 0x00003344; + CHECKREG r4, 0x00001E1F; + CHECKREG r5, 0x00001A1B; + CHECKREG r6, 0x00001617; + + R0 = W [ P5 + 16 ] (Z); + R1 = W [ P5 + 12 ] (Z); + R2 = W [ P5 + 8 ] (Z); + R3 = W [ P5 + 4 ] (Z); + R4 = W [ P5 + 0 ] (Z); + R5 = W [ P5 + 4 ] (Z); + R6 = W [ P5 + 8 ] (Z); + CHECKREG r0, 0x00003233; + CHECKREG r1, 0x00002E2F; + CHECKREG r2, 0x00002A2B; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00002223; + CHECKREG r5, 0x00002627; + CHECKREG r6, 0x00002A2B; + + R0 = W [ FP + 12 ] (Z); + R1 = W [ FP + 16 ] (Z); + R2 = W [ FP + 20 ] (Z); + R3 = W [ FP + 24 ] (Z); + R4 = W [ FP + 28 ] (Z); + R5 = W [ FP + 32 ] (Z); + R6 = W [ FP + 36 ] (Z); + CHECKREG r0, 0x00004E4F; + CHECKREG r1, 0x00005253; + CHECKREG r2, 0x00005657; + CHECKREG r3, 0x00005A5B; + CHECKREG r4, 0x0000C7C8; + CHECKREG r5, 0x0000CBCD; + CHECKREG r6, 0x0000D1D2; + + R0 = W [ SP + 40 ] (Z); + R1 = W [ SP + 44 ] (Z); + R2 = W [ SP + 48 ] (Z); + R3 = W [ SP + 52 ] (Z); + R4 = W [ SP + 56 ] (Z); + R5 = W [ SP + 60 ] (Z); + R6 = W [ SP + 64 ] (Z); + CHECKREG r0, 0x0000F9FA; + CHECKREG r1, 0x0000FDFE; + CHECKREG r2, 0x00000102; + CHECKREG r3, 0x00000506; + CHECKREG r4, 0x0000090A; + CHECKREG r5, 0x0000AD0E; + CHECKREG r6, 0x0000AD01; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstii_ld_dr_xh.s b/sim/testsuite/sim/bfin/c_ldstii_ld_dr_xh.s new file mode 100644 index 0000000..07b097f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstii_ld_dr_xh.s @@ -0,0 +1,541 @@ +//Original:testcases/core/c_ldstii_ld_dr_xh/c_ldstii_ld_dr_xh.dsp +// Spec Reference: c_ldstii load dreg xh +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x04; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_1, 0x00; + loadsym p5, DATA_ADDR_2, 0x00; + loadsym fp, DATA_ADDR_3, 0x00; + loadsym i3, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + R0 = W [ P1 + 0 ] (X); + R1 = W [ P1 + 4 ] (X); + R2 = W [ P1 + 8 ] (X); + R3 = W [ P1 + 12 ] (X); + R4 = W [ P1 + 16 ] (X); + R5 = W [ P1 + 20 ] (X); + R6 = W [ P1 + 24 ] (X); + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000607; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000E0F; + CHECKREG r4, 0x00001213; + CHECKREG r5, 0x00001617; + CHECKREG r6, 0x00001A1B; + + R0 = W [ P2 + 28 ] (X); + R1 = W [ P2 + 32 ] (X); + R2 = W [ P2 + 36 ] (X); + R3 = W [ P2 + 40 ] (X); + R4 = W [ P2 + 44 ] (X); + R5 = W [ P2 + 48 ] (X); + R6 = W [ P2 + 52 ] (X); + CHECKREG r0, 0xFFFF9394; + CHECKREG r1, 0xFFFF9798; + CHECKREG r2, 0xFFFFA2A3; + CHECKREG r3, 0xFFFFA7A8; + CHECKREG r4, 0xFFFFB1B2; + CHECKREG r5, 0xFFFFB5B6; + CHECKREG r6, 0xFFFFB9C0; + + R0 = W [ P3 + 56 ] (X); + R1 = W [ P3 + 60 ] (X); + R2 = W [ P3 + 64 ] (X); + R3 = W [ P3 + 60 ] (X); + R4 = W [ P3 + 56 ] (X); + R5 = W [ P3 + 52 ] (X); + R6 = W [ P3 + 48 ] (X); + CHECKREG r0, 0xFFFF99EA; + CHECKREG r1, 0xFFFF99EA; + CHECKREG r2, 0xFFFF99EA; + CHECKREG r3, 0xFFFF99EA; + CHECKREG r4, 0xFFFF99EA; + CHECKREG r5, 0xFFFFE5E6; + CHECKREG r6, 0xFFFFE1E2; + + R0 = W [ P4 + 44 ] (X); + R1 = W [ P4 + 40 ] (X); + R2 = W [ P4 + 36 ] (X); + R3 = W [ P4 + 32 ] (X); + R4 = W [ P4 + 28 ] (X); + R5 = W [ P4 + 24 ] (X); + R6 = W [ P4 + 20 ] (X); + CHECKREG r0, 0x00007677; + CHECKREG r1, 0x00007273; + CHECKREG r2, 0x00007788; + CHECKREG r3, 0x00003344; + CHECKREG r4, 0x00001E1F; + CHECKREG r5, 0x00001A1B; + CHECKREG r6, 0x00001617; + + R0 = W [ P5 + 16 ] (X); + R1 = W [ P5 + 12 ] (X); + R2 = W [ P5 + 8 ] (X); + R3 = W [ P5 + 4 ] (X); + R4 = W [ P5 + 0 ] (X); + R5 = W [ P5 + 4 ] (X); + R6 = W [ P5 + 8 ] (X); + CHECKREG r0, 0x00003233; + CHECKREG r1, 0x00002E2F; + CHECKREG r2, 0x00002A2B; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00002223; + CHECKREG r5, 0x00002627; + CHECKREG r6, 0x00002A2B; + + R0 = W [ FP + 12 ] (X); + R1 = W [ FP + 16 ] (X); + R2 = W [ FP + 20 ] (X); + R3 = W [ FP + 24 ] (X); + R4 = W [ FP + 28 ] (X); + R5 = W [ FP + 32 ] (X); + R6 = W [ FP + 36 ] (X); + CHECKREG r0, 0x00004E4F; + CHECKREG r1, 0x00005253; + CHECKREG r2, 0x00005657; + CHECKREG r3, 0x00005A5B; + CHECKREG r4, 0xFFFFC7C8; + CHECKREG r5, 0xFFFFCBCD; + CHECKREG r6, 0xFFFFD1D2; + + R0 = W [ SP + 40 ] (X); + R1 = W [ SP + 44 ] (X); + R2 = W [ SP + 48 ] (X); + R3 = W [ SP + 52 ] (X); + R4 = W [ SP + 56 ] (X); + R5 = W [ SP + 60 ] (X); + R6 = W [ SP + 64 ] (X); + CHECKREG r0, 0xFFFFF9FA; + CHECKREG r1, 0xFFFFFDFE; + CHECKREG r2, 0x00000102; + CHECKREG r3, 0x00000506; + CHECKREG r4, 0x0000090A; + CHECKREG r5, 0xFFFFAD0E; + CHECKREG r6, 0xFFFFAD01; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstii_ld_dreg.s b/sim/testsuite/sim/bfin/c_ldstii_ld_dreg.s new file mode 100644 index 0000000..00757f3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstii_ld_dreg.s @@ -0,0 +1,540 @@ +//Original:testcases/core/c_ldstii_ld_dreg/c_ldstii_ld_dreg.dsp +// Spec Reference: c_ldstii load dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x04; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_1, 0x00; + loadsym p5, DATA_ADDR_2, 0x00; + loadsym fp, DATA_ADDR_3, 0x00; + loadsym i3, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + R0 = [ P1 + 0 ]; + R1 = [ P1 + 4 ]; + R2 = [ P1 + 8 ]; + R3 = [ P1 + 12 ]; + R4 = [ P1 + 16 ]; + R5 = [ P1 + 20 ]; + R6 = [ P1 + 24 ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x18191A1B; + + R0 = [ P2 + 28 ]; + R1 = [ P2 + 32 ]; + R2 = [ P2 + 36 ]; + R3 = [ P2 + 40 ]; + R4 = [ P2 + 44 ]; + R5 = [ P2 + 48 ]; + R6 = [ P2 + 52 ]; + CHECKREG r0, 0x91929394; + CHECKREG r1, 0x95969798; + CHECKREG r2, 0x99A1A2A3; + CHECKREG r3, 0xA5A6A7A8; + CHECKREG r4, 0xA9B0B1B2; + CHECKREG r5, 0xB3B4B5B6; + CHECKREG r6, 0xB7B8B9C0; + + R0 = [ P3 + 56 ]; + R1 = [ P3 + 60 ]; + R2 = [ P3 + 64 ]; + R3 = [ P3 + 60 ]; + R4 = [ P3 + 56 ]; + R5 = [ P3 + 52 ]; + R6 = [ P3 + 48 ]; + CHECKREG r0, 0x91E899EA; + CHECKREG r1, 0x92E899EA; + CHECKREG r2, 0x93E899EA; + CHECKREG r3, 0x92E899EA; + CHECKREG r4, 0x91E899EA; + CHECKREG r5, 0xE3E4E5E6; + CHECKREG r6, 0xDFE0E1E2; + + R0 = [ P4 + 44 ]; + R1 = [ P4 + 40 ]; + R2 = [ P4 + 36 ]; + R3 = [ P4 + 32 ]; + R4 = [ P4 + 28 ]; + R5 = [ P4 + 24 ]; + R6 = [ P4 + 20 ]; + CHECKREG r0, 0x74757677; + CHECKREG r1, 0x99717273; + CHECKREG r2, 0x55667788; + CHECKREG r3, 0x11223344; + CHECKREG r4, 0x1C1D1E1F; + CHECKREG r5, 0x18191A1B; + CHECKREG r6, 0x14151617; + + R0 = [ P5 + 16 ]; + R1 = [ P5 + 12 ]; + R2 = [ P5 + 8 ]; + R3 = [ P5 + 4 ]; + R4 = [ P5 + 0 ]; + R5 = [ P5 + 4 ]; + R6 = [ P5 + 8 ]; + CHECKREG r0, 0x30313233; + CHECKREG r1, 0x2C2D2E2F; + CHECKREG r2, 0x28292A2B; + CHECKREG r3, 0x24252627; + CHECKREG r4, 0x20212223; + CHECKREG r5, 0x24252627; + CHECKREG r6, 0x28292A2B; + + R0 = [ FP + 12 ]; + R1 = [ FP + 16 ]; + R2 = [ FP + 20 ]; + R3 = [ FP + 24 ]; + R4 = [ FP + 28 ]; + R5 = [ FP + 32 ]; + R6 = [ FP + 36 ]; + CHECKREG r0, 0x4C4D4E4F; + CHECKREG r1, 0x50515253; + CHECKREG r2, 0x54555657; + CHECKREG r3, 0x58595A5B; + CHECKREG r4, 0xC5C6C7C8; + CHECKREG r5, 0xC9CACBCD; + CHECKREG r6, 0xCFD0D1D2; + + R0 = [ SP + 40 ]; + R1 = [ SP + 44 ]; + R2 = [ SP + 48 ]; + R3 = [ SP + 52 ]; + R4 = [ SP + 56 ]; + R5 = [ SP + 60 ]; + R6 = [ SP + 64 ]; + CHECKREG r0, 0xF7F8F9FA; + CHECKREG r1, 0xFBFCFDFE; + CHECKREG r2, 0xFF000102; + CHECKREG r3, 0x03040506; + CHECKREG r4, 0x0708090A; + CHECKREG r5, 0x0B0CAD0E; + CHECKREG r6, 0xAB0CAD01; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstii_ld_preg.s b/sim/testsuite/sim/bfin/c_ldstii_ld_preg.s new file mode 100644 index 0000000..961b7d3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstii_ld_preg.s @@ -0,0 +1,564 @@ +//Original:testcases/core/c_ldstii_ld_preg/c_ldstii_ld_preg.dsp +// Spec Reference: c_ldstii load preg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x04; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_1, 0x00; + loadsym p5, DATA_ADDR_2, 0x00; + loadsym fp, DATA_ADDR_3, 0x00; + loadsym i3, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + P2 = [ P1 + 0 ]; + P3 = [ P1 + 4 ]; + P4 = [ P1 + 8 ]; + P5 = [ P1 + 12 ]; + SP = [ P1 + 16 ]; + FP = [ P1 + 20 ]; + P1 = [ P1 + 24 ]; + CHECKREG p1, 0x18191A1B; + CHECKREG p2, 0x00010203; + CHECKREG p3, 0x04050607; + CHECKREG p4, 0x08090A0B; + CHECKREG p5, 0x0C0D0E0F; + CHECKREG sp, 0x10111213; + CHECKREG fp, 0x14151617; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x04; + P3 = I1; SP = I3; + + P1 = [ P2 + 28 ]; + P3 = [ P2 + 36 ]; + P4 = [ P2 + 40 ]; + P5 = [ P2 + 44 ]; + SP = [ P2 + 48 ]; + FP = [ P2 + 52 ]; + P2 = [ P2 + 32 ]; + CHECKREG p1, 0x91929394; + CHECKREG p2, 0x95969798; + CHECKREG p3, 0x99A1A2A3; + CHECKREG p4, 0xA5A6A7A8; + CHECKREG p5, 0xA9B0B1B2; + CHECKREG sp, 0xB3B4B5B6; + CHECKREG fp, 0xB7B8B9C0; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + + P1 = [ P3 + 56 ]; + P2 = [ P3 + 60 ]; + P4 = [ P3 + 60 ]; + P5 = [ P3 + 56 ]; + SP = [ P3 + 52 ]; + FP = [ P3 + 48 ]; + P3 = [ P3 + 64 ]; + CHECKREG p1, 0xE3E4E5E6; + CHECKREG p2, 0x91E899EA; + CHECKREG p3, 0x92E899EA; + CHECKREG p4, 0x91E899EA; + CHECKREG p5, 0xE3E4E5E6; + CHECKREG sp, 0xDFE0E1E2; + CHECKREG fp, 0xDBDCDDDE; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + P1 = [ P4 + 44 ]; + P2 = [ P4 + 40 ]; + P3 = [ P4 + 36 ]; + P5 = [ P4 + 28 ]; + SP = [ P4 + 24 ]; + FP = [ P4 + 20 ]; + P4 = [ P4 + 32 ]; + CHECKREG p1, 0xFBFCFDFE; + CHECKREG p2, 0xF7F8F9FA; + CHECKREG p3, 0xF3F4F5F6; + CHECKREG p4, 0xEBECEDEE; + CHECKREG p5, 0x7C7D7E7F; + CHECKREG sp, 0x78797A7B; + CHECKREG fp, 0x74757677; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + P1 = [ P5 + 16 ]; + P2 = [ P5 + 12 ]; + P3 = [ P5 + 8 ]; + P4 = [ P5 + 0 ]; + SP = [ P5 + 4 ]; + FP = [ P5 + 8 ]; + P5 = [ P5 + 4 ]; + CHECKREG p1, 0x10111213; + CHECKREG p2, 0x0C0D0E0F; + CHECKREG p3, 0x08090A0B; + CHECKREG p4, 0x00010203; + CHECKREG p5, 0x04050607; + CHECKREG sp, 0x04050607; + CHECKREG fp, 0x08090A0B; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + + P1 = [ SP + 12 ]; + P2 = [ SP + 16 ]; + P3 = [ SP + 20 ]; + P4 = [ SP + 24 ]; + P5 = [ SP + 28 ]; + FP = [ SP + 32 ]; + SP = [ SP + 36 ]; + CHECKREG p1, 0x2C2D2E2F; + CHECKREG p2, 0x30313233; + CHECKREG p3, 0x34353637; + CHECKREG p4, 0x38393A3B; + CHECKREG p5, 0x3C3D3E3F; + CHECKREG sp, 0x95969798; + CHECKREG fp, 0x91929394; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + + P1 = [ FP + 40 ]; + P2 = [ FP + 44 ]; + P3 = [ FP + 48 ]; + P4 = [ FP + 52 ]; + P5 = [ FP + 56 ]; + SP = [ FP + 60 ]; + FP = [ FP + 64 ]; + CHECKREG p1, 0xD3D4D5D6; + CHECKREG p2, 0xD7D8D9DA; + CHECKREG p3, 0xDBDCDDDE; + CHECKREG p4, 0xDFE0E1E2; + CHECKREG p5, 0xE3E4E5E6; + CHECKREG sp, 0x91E899EA; + CHECKREG fp, 0x92E899EA; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstii_st_dr_h.s b/sim/testsuite/sim/bfin/c_ldstii_st_dr_h.s new file mode 100644 index 0000000..2f85534 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstii_st_dr_h.s @@ -0,0 +1,605 @@ +//Original:/testcases/core/c_ldstii_st_dr_h/c_ldstii_st_dr_h.dsp +// Spec Reference: c_ldstii store dreg +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_1; + loadsym fp, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym sp, DATA_ADDR_3; +.endif + + W [ P1 + 2 ] = R0; + W [ P1 + 4 ] = R1; + W [ P1 + 6 ] = R2; + W [ P1 + 8 ] = R3; + W [ P2 + 10 ] = R4; + W [ P2 + 12 ] = R5; + W [ P2 + 14 ] = R6; + W [ P2 + 16 ] = R7; + R6 = W [ P1 + 2 ] (Z); + R5 = W [ P1 + 4 ] (Z); + R4 = W [ P1 + 6 ] (Z); + R3 = W [ P1 + 8 ] (Z); + R2 = W [ P2 + 10 ] (Z); + R7 = W [ P2 + 12 ] (Z); + R0 = W [ P2 + 14 ] (Z); + R1 = W [ P2 + 16 ] (Z); + CHECKREG r0, 0x0000B0A6; + CHECKREG r1, 0x0000C0A7; + CHECKREG r2, 0x000090A4; + CHECKREG r3, 0x000080A3; + CHECKREG r4, 0x000070A2; + CHECKREG r5, 0x000060A1; + CHECKREG r6, 0x000050A0; + CHECKREG r7, 0x0000A0A5; + +.ifndef BFIN_HOST + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + W [ P3 + 18 ] = R0; + W [ P3 + 20 ] = R1; + W [ P3 + 22 ] = R2; + W [ P3 + 24 ] = R3; + W [ P4 + 26 ] = R4; + W [ P4 + 28 ] = R5; + W [ P4 + 30 ] = R6; + W [ P4 + 32 ] = R7; + R3 = W [ P3 + 18 ] (Z); + R4 = W [ P3 + 20 ] (Z); + R0 = W [ P3 + 22 ] (Z); + R1 = W [ P3 + 24 ] (Z); + R2 = W [ P4 + 26 ] (Z); + R5 = W [ P4 + 28 ] (Z); + R6 = W [ P4 + 30 ] (Z); + R7 = W [ P4 + 32 ] (Z); + CHECKREG r0, 0x000070B2; + CHECKREG r1, 0x000080B3; + CHECKREG r2, 0x000090B4; + CHECKREG r3, 0x000050B0; + CHECKREG r4, 0x000060B1; + CHECKREG r5, 0x0000A0B5; + CHECKREG r6, 0x0000B0B6; + CHECKREG r7, 0x0000C0B7; +.endif + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + W [ P5 + 34 ] = R0; + W [ P5 + 36 ] = R1; + W [ P5 + 38 ] = R2; + W [ P5 + 40 ] = R3; +.ifndef BFIN_HOST + W [ SP + 42 ] = R4; + W [ SP + 44 ] = R5; + W [ SP + 46 ] = R6; + W [ SP + 48 ] = R7; +.endif + R6 = W [ P5 + 34 ] (Z); + R5 = W [ P5 + 36 ] (Z); + R4 = W [ P5 + 38 ] (Z); + R3 = W [ P5 + 40 ] (Z); +.ifndef BFIN_HOST + R2 = W [ SP + 42 ] (Z); + R0 = W [ SP + 44 ] (Z); + R7 = W [ SP + 46 ] (Z); + R1 = W [ SP + 48 ] (Z); + + CHECKREG r0, 0x0000A0C5; + CHECKREG r1, 0x0000C0C7; + CHECKREG r2, 0x000090C4; +.endif + CHECKREG r3, 0x000080C3; + CHECKREG r4, 0x000070C2; + CHECKREG r5, 0x000060C1; + CHECKREG r6, 0x000050C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + W [ FP + 50 ] = R0; + W [ FP + 52 ] = R1; + W [ FP + 54 ] = R2; + W [ FP + 56 ] = R3; + W [ FP + 58 ] = R4; + W [ FP + 60 ] = R5; + W [ FP + 62 ] = R6; + W [ FP + 64 ] = R7; + R3 = W [ FP + 50 ] (Z); + R4 = W [ FP + 52 ] (Z); + R0 = W [ FP + 54 ] (Z); + R1 = W [ FP + 56 ] (Z); + R2 = W [ FP + 58 ] (Z); + R5 = W [ FP + 60 ] (Z); + R6 = W [ FP + 62 ] (Z); + R7 = W [ FP + 64 ] (Z); + CHECKREG r0, 0x000070D2; + CHECKREG r1, 0x000080D3; + CHECKREG r2, 0x000090D4; + CHECKREG r3, 0x000050D0; + CHECKREG r4, 0x000060D1; + CHECKREG r5, 0x0000A0D5; + CHECKREG r6, 0x0000B0D6; + CHECKREG r7, 0x0000C0D7; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstii_st_dreg.s b/sim/testsuite/sim/bfin/c_ldstii_st_dreg.s new file mode 100644 index 0000000..af04cd5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstii_st_dreg.s @@ -0,0 +1,640 @@ +//Original:/testcases/core/c_ldstii_st_dreg/c_ldstii_st_dreg.dsp +// Spec Reference: c_ldstii store dreg +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym p3, DATA_ADDR_3; +.endif + loadsym p4, DATA_ADDR_4; + loadsym p5, DATA_ADDR_1; + loadsym fp, DATA_ADDR_2; +.ifndef BFIN_HOST + loadsym sp, DATA_ADDR_3; +.endif + + [ P1 + 4 ] = R0; + [ P1 + 8 ] = R1; + [ P1 + 12 ] = R2; + [ P1 + 16 ] = R3; + [ P2 + 20 ] = R4; + [ P2 + 24 ] = R5; + [ P2 + 28 ] = R6; + [ P2 + 32 ] = R7; + R6 = [ P1 + 4 ]; + R5 = [ P1 + 8 ]; + R4 = [ P1 + 12 ]; + R3 = [ P1 + 16 ]; + R2 = [ P2 + 20 ]; + R7 = [ P2 + 24 ]; + R0 = [ P2 + 28 ]; + R1 = [ P2 + 32 ]; + CHECKREG r0, 0x7019B0A6; + CHECKREG r1, 0xD028C0A7; + CHECKREG r2, 0x501B90A4; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300370A2; + CHECKREG r5, 0x204E60A1; + CHECKREG r6, 0x105F50A0; + CHECKREG r7, 0x600AA0A5; + +.ifndef BFIN_HOST + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + [ P3 + 36 ] = R0; + [ P3 + 40 ] = R1; + [ P3 + 44 ] = R2; + [ P3 + 48 ] = R3; + [ P4 + 52 ] = R4; + [ P4 + 56 ] = R5; + [ P4 + 60 ] = R6; + [ P4 + 64 ] = R7; + R3 = [ P3 + 36 ]; + R4 = [ P3 + 40 ]; + R0 = [ P3 + 44 ]; + R1 = [ P3 + 48 ]; + R2 = [ P4 + 52 ]; + R5 = [ P4 + 56 ]; + R6 = [ P4 + 60 ]; + R7 = [ P4 + 64 ]; + CHECKREG r0, 0x30BD70B2; + CHECKREG r1, 0x40BC80B3; + CHECKREG r2, 0x55BB90B4; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x20BE60B1; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B9B0B6; + CHECKREG r7, 0x80B8C0B7; +.endif + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + [ P5 + 4 ] = R0; + [ P5 + 8 ] = R1; + [ P5 + 12 ] = R2; + [ P5 + 16 ] = R3; +.ifndef BFIN_HOST + [ SP + 20 ] = R4; + [ SP + 24 ] = R5; + [ SP + 28 ] = R6; + [ SP + 32 ] = R7; +.endif + R6 = [ P5 + 4 ]; + R5 = [ P5 + 8 ]; + R4 = [ P5 + 12 ]; + R3 = [ P5 + 16 ]; +.ifndef BFIN_HOST + R2 = [ SP + 20 ]; + R0 = [ SP + 24 ]; + R7 = [ SP + 28 ]; + R1 = [ SP + 32 ]; + CHECKREG r0, 0x60CAA0C5; + CHECKREG r1, 0xD0C8C0C7; + CHECKREG r2, 0x50CB90C4; +.endif + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x30C370C2; + CHECKREG r5, 0x20CE60C1; + CHECKREG r6, 0x10CF50C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + [ FP + 36 ] = R0; + [ FP + 40 ] = R1; + [ FP + 44 ] = R2; + [ FP + 48 ] = R3; + [ FP + 52 ] = R4; + [ FP + 56 ] = R5; + [ FP + 60 ] = R6; + [ FP + 64 ] = R7; + R3 = [ FP + 36 ]; + R4 = [ FP + 40 ]; + R0 = [ FP + 44 ]; + R1 = [ FP + 48 ]; + R2 = [ FP + 52 ]; + R5 = [ FP + 56 ]; + R6 = [ FP + 60 ]; + R7 = [ FP + 64 ]; + CHECKREG r0, 0x80DD70D2; + CHECKREG r1, 0x90DC80D3; + CHECKREG r2, 0xA0DB90D4; + CHECKREG r3, 0x60DF50D0; + CHECKREG r4, 0x70DE60D1; + CHECKREG r5, 0xB0DAA0D5; + CHECKREG r6, 0xC0D9B0D6; + CHECKREG r7, 0xD0D8C0D7; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstii_st_preg.s b/sim/testsuite/sim/bfin/c_ldstii_st_preg.s new file mode 100644 index 0000000..126bd4d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstii_st_preg.s @@ -0,0 +1,603 @@ +//Original:/testcases/core/c_ldstii_st_preg/c_ldstii_st_preg.dsp +// Spec Reference: c_ldstii store preg +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + + P4 = 0x4567 (X); + P5 = 0x79ab (X); + FP = 0x6def (X); + + loadsym p1, DATA_ADDR_1; + loadsym p2, DATA_ADDR_2; + + [ P1 + 8 ] = P4; + [ P1 + 12 ] = P5; + [ P2 + 20 ] = P4; + [ P2 + 24 ] = P5; + [ P2 + 32 ] = FP; + R5 = [ P1 + 8 ]; + R4 = [ P1 + 12 ]; + R2 = [ P2 + 20 ]; + R7 = [ P2 + 24 ]; + R1 = [ P2 + 32 ]; + CHECKREG r1, 0x00006DEF; + CHECKREG r2, 0x00004567; + CHECKREG r4, 0x000079AB; + CHECKREG r5, 0x00004567; + CHECKREG r7, 0x000079AB; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + P1 = 0x3456 (X); + P2 = 0x1234 (X); + P5 = 0x5e23 (X); + FP = 0x2ac5 (X); + loadsym p4, DATA_ADDR_4; + + [ P4 + 52 ] = P2; + [ P4 + 56 ] = P5; + [ P4 + 64 ] = FP; + R2 = [ P4 + 52 ]; + R5 = [ P4 + 56 ]; + R7 = [ P4 + 64 ]; + CHECKREG r2, 0x00001234; + CHECKREG r5, 0x00005E23; + CHECKREG r7, 0x00002AC5; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + P1 = 0x2125 (X); + P2 = 0x7345 (X); + P4 = 0x5789 (X); + FP = 0x5bcd (X); + loadsym p5, DATA_ADDR_1; + + [ P5 + 4 ] = P2; + [ P5 + 8 ] = P1; + [ P5 + 12 ] = P2; + R6 = [ P5 + 4 ]; + R5 = [ P5 + 8 ]; + R4 = [ P5 + 12 ]; + CHECKREG r4, 0x00007345; + CHECKREG r5, 0x00002125; + CHECKREG r6, 0x00007345; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + P1 = 0x5bcd (X); + P2 = 0x1122 (X); + P4 = 0x6677 (X); + P5 = 0x58ab (X); + loadsym fp, DATA_ADDR_2; + [ FP + 36 ] = P4; + [ FP + 40 ] = P1; + [ FP + 44 ] = P2; + [ FP + 52 ] = P4; + [ FP + 56 ] = P5; + [ FP + 64 ] = P2; + R3 = [ FP + 36 ]; + R4 = [ FP + 40 ]; + R0 = [ FP + 44 ]; + R2 = [ FP + 52 ]; + R5 = [ FP + 56 ]; + R7 = [ FP + 64 ]; + CHECKREG r0, 0x00001122; + CHECKREG r2, 0x00006677; + CHECKREG r3, 0x00006677; + CHECKREG r4, 0x00005BCD; + CHECKREG r5, 0x000058AB; + CHECKREG r7, 0x00001122; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstiifp_ld_dreg.s b/sim/testsuite/sim/bfin/c_ldstiifp_ld_dreg.s new file mode 100644 index 0000000..ad5cb82 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstiifp_ld_dreg.s @@ -0,0 +1,528 @@ +//Original:testcases/core/c_ldstiifp_ld_dreg/c_ldstiifp_ld_dreg.dsp +// Spec Reference: c_ldstiifp load dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + P1 = 0x0000; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0000; + P5 = 0x0000; + SP = 0x0000; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + r0 = [ fp + 0 ]; + R1 = [ FP + 4 ]; + R2 = [ FP + 8 ]; + R3 = [ FP + 12 ]; + R4 = [ FP + 16 ]; + R5 = [ FP + 20 ]; + R6 = [ FP + 24 ]; + R7 = [ FP + 28 ]; + CHECKREG r0, 0x86878889; + CHECKREG r1, 0x80818283; + CHECKREG r2, 0x84858687; + CHECKREG r3, 0x01020304; + CHECKREG r4, 0x05060708; + CHECKREG r5, 0x09101112; + CHECKREG r6, 0x14151617; + + R0 = [ FP + 32 ]; + R1 = [ FP + 36 ]; + R2 = [ FP + 40 ]; + R3 = [ FP + 44 ]; + R4 = [ FP + 48 ]; + R5 = [ FP + 52 ]; + R7 = [ FP + 56 ]; + CHECKREG r0, 0x22232425; + CHECKREG r1, 0x26272829; + CHECKREG r2, 0x30313233; + CHECKREG r3, 0x34353637; + CHECKREG r4, 0x38394041; + CHECKREG r5, 0x42434445; + CHECKREG r6, 0x14151617; + + R0 = [ FP + 56 ]; + R1 = [ FP + 60 ]; + R2 = [ FP + 64 ]; + R3 = [ FP + 68 ]; + R4 = [ FP + 72 ]; + R5 = [ FP + 76 ]; + R6 = [ FP + 80 ]; + CHECKREG r0, 0x46474849; + CHECKREG r1, 0x50515253; + CHECKREG r2, 0x54555657; + CHECKREG r3, 0x58596061; + CHECKREG r4, 0x62636465; + CHECKREG r5, 0x66676869; + CHECKREG r6, 0x74555657; + + R0 = [ FP + 84 ]; + R1 = [ FP + 88 ]; + R2 = [ FP + 92 ]; + R3 = [ FP + 96 ]; + R4 = [ FP + 100 ]; + R5 = [ FP + 104 ]; + R6 = [ FP + 108 ]; + CHECKREG r0, 0x78596067; + CHECKREG r1, 0x72636467; + CHECKREG r2, 0x76676867; + CHECKREG r3, 0x20212223; + CHECKREG r4, 0x24252627; + CHECKREG r5, 0x28292A2B; + CHECKREG r6, 0x2C2D2E2F; + + R0 = [ FP + 112 ]; + R1 = [ FP + 116 ]; + R2 = [ FP + 120 ]; + R3 = [ FP + 124 ]; + R4 = [ FP + 128 ]; + R5 = [ FP + -4 ]; + R6 = [ FP + -8 ]; + CHECKREG r0, 0x30313233; + CHECKREG r1, 0x34353637; + CHECKREG r2, 0x38393A3B; + CHECKREG r3, 0x3C3D3E3F; + CHECKREG r4, 0x91929394; + CHECKREG r5, 0x82838485; + CHECKREG r6, 0x74757677; + + R0 = [ FP + -12 ]; + R1 = [ FP + -16 ]; + R2 = [ FP + -20 ]; + R3 = [ FP + -24 ]; + R4 = [ FP + -28 ]; + R5 = [ FP + -32 ]; + R6 = [ FP + -36 ]; + CHECKREG r0, 0x99717273; + CHECKREG r1, 0x55667788; + CHECKREG r2, 0x11223344; + CHECKREG r3, 0x1C1D1E1F; + CHECKREG r4, 0x18191A1B; + CHECKREG r5, 0x14151617; + CHECKREG r6, 0x10111213; + + R0 = [ FP + -40 ]; + R1 = [ FP + -44 ]; + R2 = [ FP + -48 ]; + R3 = [ FP + -64 ]; + R4 = [ FP + -88 ]; + R5 = [ FP + -96 ]; + R6 = [ FP + -128 ]; + CHECKREG r0, 0x0C0D0E0F; + CHECKREG r1, 0x08090A0B; + CHECKREG r2, 0x04050607; + CHECKREG r3, 0x78596067; + CHECKREG r4, 0x50515253; + CHECKREG r5, 0x42434445; + CHECKREG r6, 0x09101112; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstiifp_ld_preg.s b/sim/testsuite/sim/bfin/c_ldstiifp_ld_preg.s new file mode 100644 index 0000000..7945d30 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstiifp_ld_preg.s @@ -0,0 +1,511 @@ +//Original:testcases/core/c_ldstiifp_ld_preg/c_ldstiifp_ld_preg.dsp +// Spec Reference: c_ldstiifp load preg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P3 = I1; SP = I3; + p1 = [ fp + 0 ]; + P2 = [ FP + -4 ]; + P3 = [ FP + -8 ]; + P4 = [ FP + -12 ]; + P5 = [ FP + -16 ]; + SP = [ FP + -20 ]; + FP = [ FP + -24 ]; + CHECKREG p1, 0x86878889; + CHECKREG p2, 0x82838485; + CHECKREG p3, 0x74757677; + CHECKREG p4, 0x99717273; + CHECKREG p5, 0x55667788; + CHECKREG sp, 0x11223344; + CHECKREG fp, 0x1C1D1E1F; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P1 = [ FP + -28 ]; + P2 = [ FP + -32 ]; + P3 = [ FP + -36 ]; + P4 = [ FP + -40 ]; + P5 = [ FP + -44 ]; + SP = [ FP + -48 ]; + FP = [ FP + -52 ]; + CHECKREG p1, 0x18191A1B; + CHECKREG p2, 0x14151617; + CHECKREG p3, 0x10111213; + CHECKREG p4, 0x0C0D0E0F; + CHECKREG p5, 0x08090A0B; + CHECKREG sp, 0x04050607; + CHECKREG fp, 0x00010203; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P1 = [ FP + -56 ]; + P2 = [ FP + -60 ]; + P3 = [ FP + -64 ]; + P4 = [ FP + -68 ]; + P5 = [ FP + -72 ]; + SP = [ FP + -76 ]; + FP = [ FP + -80 ]; + CHECKREG p1, 0x76676867; + CHECKREG p2, 0x72636467; + CHECKREG p3, 0x78596067; + CHECKREG p4, 0x74555657; + CHECKREG p5, 0x66676869; + CHECKREG sp, 0x62636465; + CHECKREG fp, 0x58596061; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P1 = [ FP + -84 ]; + P2 = [ FP + -88 ]; + P3 = [ FP + -92 ]; + P4 = [ FP + -96 ]; + P5 = [ FP + -100 ]; + SP = [ FP + -104 ]; + FP = [ FP + -108 ]; + CHECKREG p1, 0x54555657; + CHECKREG p2, 0x50515253; + CHECKREG p3, 0x46474849; + CHECKREG p4, 0x42434445; + CHECKREG p5, 0x38394041; + CHECKREG sp, 0x34353637; + CHECKREG fp, 0x30313233; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0xc8; + P3 = I1; SP = I3; + + P1 = [ FP + -112 ]; + P2 = [ FP + -116 ]; + P3 = [ FP + -120 ]; + P4 = [ FP + -124 ]; + P5 = [ FP + -128 ]; + SP = [ FP + -4 ]; + FP = [ FP + -8 ]; + CHECKREG p1, 0x26272829; + CHECKREG p2, 0x22232425; + CHECKREG p3, 0x18192021; + CHECKREG p4, 0x14151617; + CHECKREG p5, 0x09101112; + CHECKREG sp, 0x82838485; + CHECKREG fp, 0x74757677; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstiifp_st_dreg.s b/sim/testsuite/sim/bfin/c_ldstiifp_st_dreg.s new file mode 100644 index 0000000..4d1a363 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstiifp_st_dreg.s @@ -0,0 +1,641 @@ +//Original:testcases/core/c_ldstiifp_st_dreg/c_ldstiifp_st_dreg.dsp +// Spec Reference: c_ldstiifp store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x00; + loadsym i1, DATA_ADDR_3, 0x00; + loadsym p4, DATA_ADDR_4, 0x00; + loadsym p5, DATA_ADDR_1, 0x00; + loadsym i3, DATA_ADDR_3, 0x00; + loadsym fp, DATA_ADDR_1, 0xC8; + P3 = I1; SP = I3; + + [ FP + -4 ] = R0; + [ FP + -8 ] = R1; + [ FP + -12 ] = R2; + [ FP + -16 ] = R3; + [ FP + -20 ] = R4; + [ FP + -24 ] = R5; + [ FP + -28 ] = R6; + [ FP + -32 ] = R7; + R6 = [ FP + -4 ]; + R5 = [ FP + -8 ]; + R4 = [ FP + -12 ]; + R3 = [ FP + -16 ]; + R2 = [ FP + -20 ]; + R7 = [ FP + -24 ]; + R0 = [ FP + -28 ]; + R1 = [ FP + -32 ]; + CHECKREG r0, 0x7019B0A6; + CHECKREG r1, 0xD028C0A7; + CHECKREG r2, 0x501B90A4; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300370A2; + CHECKREG r5, 0x204E60A1; + CHECKREG r6, 0x105F50A0; + CHECKREG r7, 0x600AA0A5; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + [ FP + -36 ] = R0; + [ FP + -40 ] = R1; + [ FP + -44 ] = R2; + [ FP + -48 ] = R3; + [ FP + -52 ] = R4; + [ FP + -56 ] = R5; + [ FP + -60 ] = R6; + [ FP + -64 ] = R7; + R3 = [ FP + -36 ]; + R4 = [ FP + -40 ]; + R0 = [ FP + -44 ]; + R1 = [ FP + -48 ]; + R2 = [ FP + -52 ]; + R5 = [ FP + -56 ]; + R6 = [ FP + -60 ]; + R7 = [ FP + -64 ]; + CHECKREG r0, 0x30BD70B2; + CHECKREG r1, 0x40BC80B3; + CHECKREG r2, 0x55BB90B4; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x20BE60B1; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B9B0B6; + CHECKREG r7, 0x80B8C0B7; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + [ FP + -68 ] = R0; + [ FP + -72 ] = R1; + [ FP + -76 ] = R2; + [ FP + -80 ] = R3; + [ FP + -84 ] = R4; + [ FP + -88 ] = R5; + [ FP + -92 ] = R6; + [ FP + -96 ] = R7; + R6 = [ FP + -68 ]; + R5 = [ FP + -72 ]; + R4 = [ FP + -76 ]; + R3 = [ FP + -80 ]; + R2 = [ FP + -84 ]; + R0 = [ FP + -88 ]; + R7 = [ FP + -92 ]; + R1 = [ FP + -96 ]; + CHECKREG r0, 0x60CAA0C5; + CHECKREG r1, 0xD0C8C0C7; + CHECKREG r2, 0x50CB90C4; + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x30C370C2; + CHECKREG r5, 0x20CE60C1; + CHECKREG r6, 0x10CF50C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + [ FP + -100 ] = R0; + [ FP + -104 ] = R1; + [ FP + -108 ] = R2; + [ FP + -112 ] = R3; + [ FP + -116 ] = R4; + [ FP + -120 ] = R5; + [ FP + -124 ] = R6; + [ FP + -128 ] = R7; + R3 = [ FP + -100 ]; + R4 = [ FP + -104 ]; + R0 = [ FP + -108 ]; + R1 = [ FP + -112 ]; + R2 = [ FP + -116 ]; + R5 = [ FP + -120 ]; + R6 = [ FP + -124 ]; + R7 = [ FP + -128 ]; + CHECKREG r0, 0x80DD70D2; + CHECKREG r1, 0x90DC80D3; + CHECKREG r2, 0xA0DB90D4; + CHECKREG r3, 0x60DF50D0; + CHECKREG r4, 0x70DE60D1; + CHECKREG r5, 0xB0DAA0D5; + CHECKREG r6, 0xC0D9B0D6; + CHECKREG r7, 0xD0D8C0D7; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstiifp_st_preg.s b/sim/testsuite/sim/bfin/c_ldstiifp_st_preg.s new file mode 100644 index 0000000..3a132dc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstiifp_st_preg.s @@ -0,0 +1,618 @@ +//Original:testcases/core/c_ldstiifp_st_preg/c_ldstiifp_st_preg.dsp +// Spec Reference: c_ldstiifp store preg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + imm32 p1, 0x12345678; + imm32 p2, 0x6789abcd; + imm32 p4, 0x24680123; + imm32 p5, 0x57913597; + + loadsym fp, DATA_ADDR_1, 0xC8; + [ FP + -4 ] = P2; + [ FP + -8 ] = P1; + [ FP + -12 ] = P2; + [ FP + -20 ] = P4; + [ FP + -24 ] = P5; + [ FP + -32 ] = P5; + R6 = [ FP + -4 ]; + R5 = [ FP + -8 ]; + R4 = [ FP + -12 ]; + R2 = [ FP + -20 ]; + R7 = [ FP + -24 ]; + R1 = [ FP + -32 ]; + CHECKREG r1, 0x57913597; + CHECKREG r2, 0x24680123; + CHECKREG r4, 0x6789ABCD; + CHECKREG r5, 0x12345678; + CHECKREG r6, 0x6789ABCD; + CHECKREG r7, 0x57913597; + + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + imm32 p1, 0x11223344; + imm32 p2, 0x2349abcd; + imm32 p4, 0x44556623; + imm32 p5, 0x57913597; + [ FP + -36 ] = P4; + [ FP + -40 ] = P1; + [ FP + -44 ] = P2; + [ FP + -52 ] = P4; + [ FP + -56 ] = P5; + [ FP + -64 ] = P1; + R3 = [ FP + -36 ]; + R4 = [ FP + -40 ]; + R0 = [ FP + -44 ]; + R2 = [ FP + -52 ]; + R5 = [ FP + -56 ]; + R7 = [ FP + -64 ]; + CHECKREG r0, 0x2349ABCD; + CHECKREG r2, 0x44556623; + CHECKREG r3, 0x44556623; + CHECKREG r4, 0x11223344; + CHECKREG r5, 0x57913597; + CHECKREG r7, 0x11223344; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + imm32 p1, 0x19012345; + imm32 p2, 0x2146abcd; + imm32 p4, 0x24680123; + imm32 p5, 0x57913597; + [ FP + -68 ] = P2; + [ FP + -72 ] = P1; + [ FP + -76 ] = P2; + [ FP + -84 ] = P4; + [ FP + -88 ] = P5; + [ FP + -96 ] = P2; + R6 = [ FP + -68 ]; + R5 = [ FP + -72 ]; + R4 = [ FP + -76 ]; + R2 = [ FP + -84 ]; + R0 = [ FP + -88 ]; + R1 = [ FP + -96 ]; + CHECKREG r0, 0x57913597; + CHECKREG r1, 0x2146ABCD; + CHECKREG r2, 0x24680123; + CHECKREG r4, 0x2146ABCD; + CHECKREG r5, 0x19012345; + CHECKREG r6, 0x2146ABCD; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + imm32 p1, 0x13579678; + imm32 p2, 0x2468abcd; + imm32 p4, 0x45678123; + imm32 p5, 0x57913597; + [ FP + -104 ] = P1; + [ FP + -108 ] = P2; + [ FP + -116 ] = P4; + [ FP + -120 ] = P5; + R4 = [ FP + -104 ]; + R0 = [ FP + -108 ]; + R2 = [ FP + -116 ]; + R5 = [ FP + -120 ]; + CHECKREG r0, 0x2468ABCD; + CHECKREG r2, 0x45678123; + CHECKREG r4, 0x13579678; + CHECKREG r5, 0x57913597; + + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_hi.s b/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_hi.s new file mode 100644 index 0000000..982444e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_hi.s @@ -0,0 +1,411 @@ +//Original:testcases/core/c_ldstpmod_ld_dr_hi/c_ldstpmod_ld_dr_hi.dsp +// Spec Reference: c_ldstpmod load dr hi +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_2, 0x04; + loadsym p2, DATA_ADDR_3, 0x04; + loadsym i1, DATA_ADDR_4, 0x04; + loadsym p4, DATA_ADDR_5, 0x08; + loadsym p5, DATA_ADDR_1, 0x08; + loadsym fp, DATA_ADDR_6, 0x08; + loadsym i3, DATA_ADDR_7, 0x0c; + P3 = I1; SP = I3; + + R0.H = W [ P1 ]; + R1.H = W [ P1 ]; + R2.H = W [ P1 ]; + R3.H = W [ P1 ]; + R4.H = W [ P1 ]; + R5.H = W [ P1 ]; + R6.H = W [ P1 ]; + R7.H = W [ P1 ]; + CHECKREG r0, 0x26270000; + CHECKREG r1, 0x26270000; + CHECKREG r2, 0x26270000; + CHECKREG r3, 0x26270000; + CHECKREG r4, 0x26270000; + CHECKREG r5, 0x26270000; + CHECKREG r6, 0x26270000; + CHECKREG r7, 0x26270000; + + R0.H = W [ P2 ]; + R1.H = W [ P2 ]; + R2.H = W [ P2 ]; + R3.H = W [ P2 ]; + R4.H = W [ P2 ]; + R5.H = W [ P2 ]; + R6.H = W [ P2 ]; + R7.H = W [ P2 ]; + CHECKREG r0, 0x46470000; + CHECKREG r1, 0x46470000; + CHECKREG r2, 0x46470000; + CHECKREG r3, 0x46470000; + CHECKREG r4, 0x46470000; + CHECKREG r5, 0x46470000; + CHECKREG r6, 0x46470000; + CHECKREG r7, 0x46470000; + + R0.H = W [ P3 ]; + R1.H = W [ P3 ]; + R2.H = W [ P3 ]; + R3.H = W [ P3 ]; + R4.H = W [ P3 ]; + R5.H = W [ P3 ]; + R6.H = W [ P3 ]; + R7.H = W [ P3 ]; + CHECKREG r0, 0x66670000; + CHECKREG r1, 0x66670000; + CHECKREG r2, 0x66670000; + CHECKREG r3, 0x66670000; + CHECKREG r4, 0x66670000; + CHECKREG r5, 0x66670000; + CHECKREG r6, 0x66670000; + CHECKREG r7, 0x66670000; + + R0.H = W [ P4 ]; + R1.H = W [ P4 ]; + R2.H = W [ P4 ]; + R3.H = W [ P4 ]; + R4.H = W [ P4 ]; + R5.H = W [ P4 ]; + R6.H = W [ P4 ]; + R7.H = W [ P4 ]; + CHECKREG r0, 0x8A8B0000; + CHECKREG r1, 0x8A8B0000; + CHECKREG r2, 0x8A8B0000; + CHECKREG r3, 0x8A8B0000; + CHECKREG r4, 0x8A8B0000; + CHECKREG r5, 0x8A8B0000; + CHECKREG r6, 0x8A8B0000; + CHECKREG r7, 0x8A8B0000; + + R0.H = W [ P5 ]; + R1.H = W [ P5 ]; + R2.H = W [ P5 ]; + R3.H = W [ P5 ]; + R4.H = W [ P5 ]; + R5.H = W [ P5 ]; + R6.H = W [ P5 ]; + R7.H = W [ P5 ]; + CHECKREG r0, 0x0A0B0000; + CHECKREG r1, 0x0A0B0000; + CHECKREG r2, 0x0A0B0000; + CHECKREG r3, 0x0A0B0000; + CHECKREG r4, 0x0A0B0000; + CHECKREG r5, 0x0A0B0000; + CHECKREG r6, 0x0A0B0000; + CHECKREG r7, 0x0A0B0000; + + R0.H = W [ SP ]; + R1.H = W [ SP ]; + R2.H = W [ SP ]; + R3.H = W [ SP ]; + R4.H = W [ SP ]; + R5.H = W [ SP ]; + R6.H = W [ SP ]; + R7.H = W [ SP ]; + CHECKREG r0, 0x8E8F0000; + CHECKREG r1, 0x8E8F0000; + CHECKREG r2, 0x8E8F0000; + CHECKREG r3, 0x8E8F0000; + CHECKREG r4, 0x8E8F0000; + CHECKREG r5, 0x8E8F0000; + CHECKREG r6, 0x8E8F0000; + CHECKREG r7, 0x8E8F0000; + + R0.H = W [ FP ]; + R1.H = W [ FP ]; + R2.H = W [ FP ]; + R3.H = W [ FP ]; + R4.H = W [ FP ]; + R5.H = W [ FP ]; + R6.H = W [ FP ]; + R7.H = W [ FP ]; + CHECKREG r0, 0x0A0B0000; + CHECKREG r1, 0x0A0B0000; + CHECKREG r2, 0x0A0B0000; + CHECKREG r3, 0x0A0B0000; + CHECKREG r4, 0x0A0B0000; + CHECKREG r5, 0x0A0B0000; + CHECKREG r6, 0x0A0B0000; + CHECKREG r7, 0x0A0B0000; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_lo.s b/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_lo.s new file mode 100644 index 0000000..e399a24 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstpmod_ld_dr_lo.s @@ -0,0 +1,410 @@ +//Original:testcases/core/c_ldstpmod_ld_dr_lo/c_ldstpmod_ld_dr_lo.dsp +// Spec Reference: c_ldstpmod load dr lo +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS(0); +I0 = P3; +I2 = SP; + +// initial values + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_2, 0x04; + loadsym p2, DATA_ADDR_3, 0x04; + loadsym i1, DATA_ADDR_4, 0x04; + loadsym p4, DATA_ADDR_5, 0x08; + loadsym p5, DATA_ADDR_1, 0x08; + loadsym fp, DATA_ADDR_6, 0x08; + loadsym i3, DATA_ADDR_7, 0x0c; + P3 = I1; SP = I3; + + R0.L = W [ P1 ]; + R1.L = W [ P1 ]; + R2.L = W [ P1 ]; + R3.L = W [ P1 ]; + R4.L = W [ P1 ]; + R5.L = W [ P1 ]; + R6.L = W [ P1 ]; + R7.L = W [ P1 ]; + CHECKREG r0, 0x00002627; + CHECKREG r1, 0x00002627; + CHECKREG r2, 0x00002627; + CHECKREG r3, 0x00002627; + CHECKREG r4, 0x00002627; + CHECKREG r5, 0x00002627; + CHECKREG r6, 0x00002627; + CHECKREG r7, 0x00002627; + + R0.L = W [ P2 ]; + R1.L = W [ P2 ]; + R2.L = W [ P2 ]; + R3.L = W [ P2 ]; + R4.L = W [ P2 ]; + R5.L = W [ P2 ]; + R6.L = W [ P2 ]; + R7.L = W [ P2 ]; + CHECKREG r0, 0x00004647; + CHECKREG r1, 0x00004647; + CHECKREG r2, 0x00004647; + CHECKREG r3, 0x00004647; + CHECKREG r4, 0x00004647; + CHECKREG r5, 0x00004647; + CHECKREG r6, 0x00004647; + CHECKREG r7, 0x00004647; + + R0.L = W [ P3 ]; + R1.L = W [ P3 ]; + R2.L = W [ P3 ]; + R3.L = W [ P3 ]; + R4.L = W [ P3 ]; + R5.L = W [ P3 ]; + R6.L = W [ P3 ]; + R7.L = W [ P3 ]; + CHECKREG r0, 0x00006667; + CHECKREG r1, 0x00006667; + CHECKREG r2, 0x00006667; + CHECKREG r3, 0x00006667; + CHECKREG r4, 0x00006667; + CHECKREG r5, 0x00006667; + CHECKREG r6, 0x00006667; + CHECKREG r7, 0x00006667; + + R0.L = W [ P4 ]; + R1.L = W [ P4 ]; + R2.L = W [ P4 ]; + R3.L = W [ P4 ]; + R4.L = W [ P4 ]; + R5.L = W [ P4 ]; + R6.L = W [ P4 ]; + R7.L = W [ P4 ]; + CHECKREG r0, 0x00008A8B; + CHECKREG r1, 0x00008A8B; + CHECKREG r2, 0x00008A8B; + CHECKREG r3, 0x00008A8B; + CHECKREG r4, 0x00008A8B; + CHECKREG r5, 0x00008A8B; + CHECKREG r6, 0x00008A8B; + CHECKREG r7, 0x00008A8B; + + R0.L = W [ P5 ]; + R1.L = W [ P5 ]; + R2.L = W [ P5 ]; + R3.L = W [ P5 ]; + R4.L = W [ P5 ]; + R5.L = W [ P5 ]; + R6.L = W [ P5 ]; + R7.L = W [ P5 ]; + CHECKREG r0, 0x00000A0B; + CHECKREG r1, 0x00000A0B; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000A0B; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000A0B; + CHECKREG r6, 0x00000A0B; + CHECKREG r7, 0x00000A0B; + + R0.L = W [ SP ]; + R1.L = W [ SP ]; + R2.L = W [ SP ]; + R3.L = W [ SP ]; + R4.L = W [ SP ]; + R5.L = W [ SP ]; + R6.L = W [ SP ]; + R7.L = W [ SP ]; + CHECKREG r0, 0x00008E8F; + CHECKREG r1, 0x00008E8F; + CHECKREG r2, 0x00008E8F; + CHECKREG r3, 0x00008E8F; + CHECKREG r4, 0x00008E8F; + CHECKREG r5, 0x00008E8F; + CHECKREG r6, 0x00008E8F; + CHECKREG r7, 0x00008E8F; + + R0.L = W [ FP ]; + R1.L = W [ FP ]; + R2.L = W [ FP ]; + R3.L = W [ FP ]; + R4.L = W [ FP ]; + R5.L = W [ FP ]; + R6.L = W [ FP ]; + R7.L = W [ FP ]; + CHECKREG r0, 0x00000A0B; + CHECKREG r1, 0x00000A0B; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000A0B; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000A0B; + CHECKREG r6, 0x00000A0B; + CHECKREG r7, 0x00000A0B; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_ld_dreg.s b/sim/testsuite/sim/bfin/c_ldstpmod_ld_dreg.s new file mode 100644 index 0000000..cfcdf1d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstpmod_ld_dreg.s @@ -0,0 +1,462 @@ +//Original:testcases/core/c_ldstpmod_ld_dreg/c_ldstpmod_ld_dreg.dsp +// Spec Reference: c_ldstpmod load dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0008; + FP = 0x0008; + SP = 0x000c; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + R0 = [ P5 ++ P3 ]; + R1 = [ P5 ++ P1 ]; + R2 = [ P5 ++ P2 ]; + R3 = [ P5 ++ P3 ]; + R4 = [ P5 ++ P4 ]; + R5 = [ P5 ++ SP ]; + R6 = [ P5 ++ FP ]; + CHECKREG r0, 0x00010203; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x08090A0B; + CHECKREG r3, 0x0C0D0E0F; + CHECKREG r4, 0x10111213; + CHECKREG r5, 0x18191A1B; + CHECKREG r6, 0x55667788; + +// initial values + P5 = 0x0000; + P2 = 0x0004; + P3 = 0x0008; + P4 = 0x0008; + FP = 0x000c; + SP = 0x000c; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x04; + P3 = I1; SP = I3; + + R0 = [ P1 ++ P5 ]; + R1 = [ P1 ++ P3 ]; + R2 = [ P1 ++ P2 ]; + R3 = [ P1 ++ P3 ]; + R4 = [ P1 ++ P4 ]; + R5 = [ P1 ++ SP ]; + R6 = [ P1 ++ FP ]; + CHECKREG r0, 0x04050607; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x0C0D0E0F; + CHECKREG r3, 0x10111213; + CHECKREG r4, 0x18191A1B; + CHECKREG r5, 0x11223344; + CHECKREG r6, 0x74757677; + +// initial values + P5 = 0x0000; + P1 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0008; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + + R0 = [ P2 ++ P5 ]; + R1 = [ P2 ++ P1 ]; + R2 = [ P2 ++ P4 ]; + R3 = [ P2 ++ P3 ]; + R4 = [ P2 ++ P4 ]; + R5 = [ P2 ++ SP ]; + R6 = [ P2 ++ FP ]; + CHECKREG r0, 0x40414243; + CHECKREG r1, 0x40414243; + CHECKREG r2, 0x44454647; + CHECKREG r3, 0x48494A4B; + CHECKREG r4, 0x4C4D4E4F; + CHECKREG r5, 0x50515253; + CHECKREG r6, 0x54555657; + +// initial values + P5 = 0x0010; + P1 = 0x0004; + P2 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_1, 0x04; + P3 = I1; SP = I3; + + R0 = [ P3 ++ P5 ]; + R1 = [ P3 ++ P1 ]; + R2 = [ P3 ++ P2 ]; + R3 = [ P3 ++ P1 ]; + R4 = [ P3 ++ P4 ]; + R5 = [ P3 ++ SP ]; + R6 = [ P3 ++ FP ]; + CHECKREG r0, 0x04050607; + CHECKREG r1, 0x14151617; + CHECKREG r2, 0x18191A1B; + CHECKREG r3, 0x1C1D1E1F; + CHECKREG r4, 0x11223344; + CHECKREG r5, 0x55667788; + CHECKREG r6, 0x99717273; + +// initial values + P5 = 0x0004; + P1 = 0x0008; + P2 = 0x000C; + P3 = 0x0004; + FP = 0x0008; + SP = 0x0008; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_2, 0x04; + P3 = I1; SP = I3; + + R0 = [ P4 ++ P5 ]; + R1 = [ P4 ++ P1 ]; + R2 = [ P4 ++ P2 ]; + R3 = [ P4 ++ P3 ]; + R4 = [ P4 ++ P2 ]; + R5 = [ P4 ++ SP ]; + R6 = [ P4 ++ FP ]; + CHECKREG r0, 0x24252627; + CHECKREG r1, 0x28292A2B; + CHECKREG r2, 0x30313233; + CHECKREG r3, 0x3C3D3E3F; + CHECKREG r4, 0x91929394; + CHECKREG r5, 0xA5A6A7A8; + CHECKREG r6, 0xB3B4B5B6; + +// initial values + P5 = 0x0000; + P1 = 0x0010; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + SP = 0x0008; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0x04; + P3 = I1; SP = I3; + + R0 = [ FP ++ P5 ]; + R1 = [ FP ++ P1 ]; + R2 = [ FP ++ P2 ]; + R3 = [ FP ++ P3 ]; + R4 = [ FP ++ P4 ]; + R5 = [ FP ++ SP ]; + R6 = [ FP ++ SP ]; + CHECKREG r0, 0x04050607; + CHECKREG r1, 0x04050607; + CHECKREG r2, 0x14151617; + CHECKREG r3, 0x18191A1B; + CHECKREG r4, 0x1C1D1E1F; + CHECKREG r5, 0x11223344; + CHECKREG r6, 0x99717273; + +// initial values + P5 = 0x0000; + P1 = 0x0004; + P2 = 0x0008; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_1, 0x08; + P3 = I1; SP = I3; + + R0 = [ SP ++ P5 ]; + R1 = [ SP ++ P1 ]; + R2 = [ SP ++ P2 ]; + R3 = [ SP ++ P3 ]; + R4 = [ SP ++ P4 ]; + R5 = [ SP ++ FP ]; + R6 = [ SP ++ FP ]; + CHECKREG r0, 0x08090A0B; + CHECKREG r1, 0x08090A0B; + CHECKREG r2, 0x0C0D0E0F; + CHECKREG r3, 0x14151617; + CHECKREG r4, 0x18191A1B; + CHECKREG r5, 0x1C1D1E1F; + CHECKREG r6, 0x11223344; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_ld_h_xh.s b/sim/testsuite/sim/bfin/c_ldstpmod_ld_h_xh.s new file mode 100644 index 0000000..c3c4eda --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstpmod_ld_h_xh.s @@ -0,0 +1,458 @@ +//Original:testcases/core/c_ldstpmod_ld_h_xh/c_ldstpmod_ld_h_xh.dsp +// Spec Reference: c_ldstpmod load dreg h & xh +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + R0 = W [ P5 ++ P1 ] (Z); + R1 = W [ P5 ++ P1 ] (Z); + R2 = W [ P5 ++ P2 ] (Z); + R3 = W [ P5 ++ P3 ] (Z); + R4 = W [ P5 ++ P4 ] (Z); + R5 = W [ P5 ++ SP ] (Z); + R6 = W [ P5 ++ FP ] (Z); + CHECKREG r0, 0x0000A203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x0000B607; + CHECKREG r3, 0x00009405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x0000CE0F; + +// initial values + P5 = 0x0002; + P2 = 0x0002; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + R0 = W [ P1 ++ P5 ] (X); + R1 = W [ P1 ++ P2 ] (X); + R2 = W [ P1 ++ P2 ] (X); + R3 = W [ P1 ++ P3 ] (X); + R4 = W [ P1 ++ P4 ] (X); + R5 = W [ P1 ++ SP ] (X); + R6 = W [ P1 ++ FP ] (X); + CHECKREG r0, 0xFFFFA203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0xFFFFB607; + CHECKREG r3, 0xFFFF9405; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0xFFFFAC0D; + CHECKREG r6, 0x00001011; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P3 = 0x0002; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_3, 0x06; + P3 = I1; SP = I3; + R0 = W [ P2 ++ P5 ] (Z); + R1 = W [ P2 ++ P1 ] (Z); + R2 = W [ P2 ++ P2 ] (Z); + R3 = W [ P2 ++ P3 ] (Z); + R4 = W [ P2 ++ P4 ] (Z); + R5 = W [ P2 ++ SP ] (Z); + R6 = W [ P2 ++ FP ] (Z); + CHECKREG r0, 0x00008445; + CHECKREG r1, 0x00004A4B; + CHECKREG r2, 0x00004849; + CHECKREG r3, 0x00004849; + CHECKREG r4, 0x00004E4F; + CHECKREG r5, 0x00005253; + CHECKREG r6, 0x00005051; + +// initial values + P5 = 0x0004; + P1 = 0x0002; + P2 = 0x0002; + P4 = 0x0004; + FP = 0x1002 (X); + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_1, 0x02; + P3 = I1; SP = I3; + R0 = W [ P3 ++ P5 ] (X); + R1 = W [ P3 ++ P1 ] (X); + R2 = W [ P3 ++ P2 ] (X); + R3 = W [ P3 ++ P3 ] (X); + R4 = W [ P3 ++ P4 ] (X); + R5 = W [ P3 ++ SP ] (X); + R6 = W [ P3 ++ FP ] (X); + CHECKREG r0, 0x00000001; + CHECKREG r1, 0xFFFF9405; + CHECKREG r2, 0x00000A0B; + CHECKREG r3, 0x00000809; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0xFFFFAC0D; + CHECKREG r6, 0x00001213; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + R0 = W [ P4 ++ P5 ] (Z); + R1 = W [ P4 ++ P1 ] (X); + R2 = W [ P4 ++ P2 ] (X); + R3 = W [ P4 ++ P3 ] (Z); + R4 = W [ P4 ++ P4 ] (Z); + R5 = W [ P4 ++ SP ] (X); + R6 = W [ P4 ++ FP ] (X); + CHECKREG r0, 0x00002223; + CHECKREG r1, 0x00002021; + CHECKREG r2, 0x00002627; + CHECKREG r3, 0x0000A425; + CHECKREG r4, 0x00002A2B; + CHECKREG r5, 0x00002A2B; + CHECKREG r6, 0xFFFF8829; + +// initial values + P5 = 0x0000; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_1, 0x02; + P3 = I1; SP = I3; + R0 = W [ FP ++ P5 ] (X); + R1 = W [ FP ++ P1 ] (X); + R2 = W [ FP ++ P2 ] (X); + R3 = W [ FP ++ P3 ] (X); + R4 = W [ FP ++ P4 ] (Z); + R5 = W [ FP ++ SP ] (Z); + R6 = W [ FP ++ FP ] (X); + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0xFFFFB607; + CHECKREG r3, 0xFFFF9405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0xFFFFAC0D; + +// initial values + P5 = 0x0000; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_1, 0x04; + P3 = I1; SP = I3; + + R0 = W [ SP ++ P5 ] (Z); + R1 = W [ SP ++ P1 ] (X); + R2 = W [ SP ++ P2 ] (Z); + R3 = W [ SP ++ P3 ] (X); + R4 = W [ SP ++ P4 ] (Z); + R5 = W [ SP ++ P1 ] (X); + R6 = W [ SP ++ FP ] (Z); + CHECKREG r0, 0x0000B607; + CHECKREG r1, 0xFFFFB607; + CHECKREG r2, 0x00009405; + CHECKREG r3, 0x00000A0B; + CHECKREG r4, 0x00000809; + CHECKREG r5, 0xFFFFCE0F; + CHECKREG r6, 0x0000AC0D; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data + .space (0x2000); + +DATA_ADDR_1: + .dd 0x0001a203 + .dd 0x9405b607 + .dd 0x08090A0B + .dd 0xaC0DcE0F + .dd 0x10111213 + .dd 0xb415c617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0xa5060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0xc8192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0xb0313233 + .dd 0x34353637 + .dd 0xd8394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0xf0515253 + .dd 0x54555657 + .dd 0xe8596061 + .dd 0x62636465 + .dd 0xf6676869 + .dd 0x74555657 + .dd 0xa8596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0xa4252627 + .dd 0x88292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x84454647 + .dd 0x48494A4B + .dd 0x9C4D4E4F + .dd 0x50515253 + .dd 0xa4555657 + .dd 0xb8595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x90616263 + .dd 0x64656667 + .dd 0xa8696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0xd4757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x08898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x54959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0xa4050607 + .dd 0x08090A0B + .dd 0xfC0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x98191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x74252627 + .dd 0x28292A2B + .dd 0x8C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x98393A3B + .dd 0x3C3D3E3F + .dd 0xb0414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0xdC4D4E4F + .dd 0x50515253 + .dd 0x94555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0xf0616263 + .dd 0xf4656667 + .dd 0xf8696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x10919293 + .dd 0x24959697 + .dd 0x38999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0x54A5A6A7 + .dd 0x68A9AAAB + .dd 0x7CADAEAF + .dd 0xB0B1B2B3 + .dd 0x84B5B6B7 + .dd 0xB8B9BABB + .dd 0x4CBDBEBF + .dd 0xC0C1C2C3 + .dd 0x34C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0x20D1D2D3 + .dd 0xD4D5D6D7 + .dd 0x18D9DADB + .dd 0xDCDDDEDF + .dd 0x00E1E2E3 + .dd 0xE4E5E6E7 + .dd 0x18E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_ld_lohi.s b/sim/testsuite/sim/bfin/c_ldstpmod_ld_lohi.s new file mode 100644 index 0000000..4223e59 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstpmod_ld_lohi.s @@ -0,0 +1,462 @@ +//Original:testcases/core/c_ldstpmod_ld_lohi/c_ldstpmod_ld_lohi.dsp +// Spec Reference: c_ldstpmod load dreg lo & hi +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +INIT_R_REGS 0; +I0 = P3; +I2 = SP; + +// initial values + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + + R0.L = W [ P5 ++ P1 ]; + R1.L = W [ P5 ++ P1 ]; + R2.L = W [ P5 ++ P2 ]; + R3.L = W [ P5 ++ P3 ]; + R4.L = W [ P5 ++ P4 ]; + R5.L = W [ P5 ++ SP ]; + R6.L = W [ P5 ++ FP ]; + CHECKREG r0, 0x00000203; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000607; + CHECKREG r3, 0x00000405; + CHECKREG r4, 0x00000A0B; + CHECKREG r5, 0x00000809; + CHECKREG r6, 0x00000E0F; + +// initial values + P5 = 0x0000; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + + R0.H = W [ P1 ++ P5 ]; + R1.H = W [ P1 ++ P2 ]; + R2.H = W [ P1 ++ P2 ]; + R3.H = W [ P1 ++ P3 ]; + R4.H = W [ P1 ++ P4 ]; + R5.H = W [ P1 ++ SP ]; + R6.H = W [ P1 ++ FP ]; + CHECKREG r0, 0x22230203; + CHECKREG r1, 0x22230001; + CHECKREG r2, 0x20210607; + CHECKREG r3, 0x26270405; + CHECKREG r4, 0x24250A0B; + CHECKREG r5, 0x2A2B0809; + CHECKREG r6, 0x28290E0F; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x02; + P3 = I1; SP = I3; + + R0.L = W [ P2 ++ P5 ]; + R0.H = W [ P2 ++ P1 ]; + R1.L = W [ P2 ++ P1 ]; + R1.H = W [ P2 ++ P3 ]; + R2.H = W [ P2 ++ P4 ]; + R2.L = W [ P2 ++ SP ]; + R3.L = W [ P2 ++ FP ]; + CHECKREG r0, 0x26272021; + CHECKREG r1, 0x2A2B2425; + CHECKREG r2, 0x28292E2F; + CHECKREG r3, 0x26272C2D; + CHECKREG r4, 0x24250A0B; + CHECKREG r5, 0x2A2B0809; + CHECKREG r6, 0x28290E0F; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + + R3.L = W [ P3 ++ P5 ]; + R3.H = W [ P3 ++ P1 ]; + R4.L = W [ P3 ++ P2 ]; + R5.H = W [ P3 ++ P1 ]; + R5.L = W [ P3 ++ P4 ]; + R6.H = W [ P3 ++ SP ]; + R6.L = W [ P3 ++ FP ]; + CHECKREG r0, 0x26272021; + CHECKREG r1, 0x2A2B2425; + CHECKREG r2, 0x28292E2F; + CHECKREG r3, 0x40414243; + CHECKREG r4, 0x24254647; + CHECKREG r5, 0x44454A4B; + CHECKREG r6, 0x48494E4F; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + + R0.H = W [ P4 ++ P5 ]; + R0.L = W [ P4 ++ P1 ]; + R1.L = W [ P4 ++ P2 ]; + R1.H = W [ P4 ++ P3 ]; + R2.H = W [ P4 ++ P4 ]; + R3.L = W [ P4 ++ SP ]; + R3.H = W [ P4 ++ FP ]; + CHECKREG r0, 0x62636061; + CHECKREG r1, 0x64656667; + CHECKREG r2, 0x6A6B2E2F; + CHECKREG r3, 0x68696A6B; + CHECKREG r4, 0x24254647; + CHECKREG r5, 0x44454A4B; + CHECKREG r6, 0x48494E4F; + +// initial values + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + + R0.H = W [ FP ++ P5 ]; + R1.L = W [ FP ++ P1 ]; + R2.H = W [ FP ++ P2 ]; + R3.H = W [ FP ++ P3 ]; + R4.L = W [ FP ++ P4 ]; + R5.H = W [ FP ++ SP ]; + R6.L = W [ FP ++ P1 ]; + CHECKREG r0, 0x82836061; + CHECKREG r1, 0x64658081; + CHECKREG r2, 0x86872E2F; + CHECKREG r3, 0x84856A6B; + CHECKREG r4, 0x24258A8B; + CHECKREG r5, 0x88894A4B; + CHECKREG r6, 0x48498E8F; + +// initial values + P5 = 0x0000; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x00; + P3 = I1; SP = I3; + + R0.L = W [ SP ++ P5 ]; + R1.H = W [ SP ++ P1 ]; + R2.H = W [ SP ++ P2 ]; + R3.L = W [ SP ++ P3 ]; + R4.H = W [ SP ++ P4 ]; + R5.L = W [ SP ++ P5 ]; + R6.H = W [ SP ++ FP ]; + CHECKREG r0, 0x82830203; + CHECKREG r1, 0x02038081; + CHECKREG r2, 0x00012E2F; + CHECKREG r3, 0x84850607; + CHECKREG r4, 0x04058A8B; + CHECKREG r5, 0x88890A0B; + CHECKREG r6, 0x0A0B8E8F; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_hi.s b/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_hi.s new file mode 100644 index 0000000..4e19e60 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_hi.s @@ -0,0 +1,400 @@ +//Original:testcases/core/c_ldstpmod_st_dr_hi/c_ldstpmod_st_dr_hi.dsp +// Spec Reference: c_ldstpmod store dreg hi +# mach: bfin + +.include "testutils.inc" + start + +// set all regs + +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x600f5000; + imm32 r1, 0x700e6001; + imm32 r2, 0x800d7002; + imm32 r3, 0x900c8003; + imm32 r4, 0xa00b9004; + imm32 r5, 0xb00aa005; + imm32 r6, 0xc009b006; + imm32 r7, 0xd008c007; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x02; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_4, 0x06; + loadsym p5, DATA_ADDR_5, 0x08; + loadsym fp, DATA_ADDR_6, 0x0a; + loadsym i3, DATA_ADDR_7, 0x0c; + P3 = I1; SP = I3; + W [ P1 ] = R1.H; + W [ P2 ] = R2.H; + W [ P3 ] = R3.H; + W [ P4 ] = R4.H; + W [ P5 ] = R5.H; + W [ SP ] = R6.H; + W [ FP ] = R0.H; + R6.H = W [ P1 ]; + R5.H = W [ P2 ]; + R4.H = W [ P3 ]; + R3.H = W [ P4 ]; + R2.H = W [ P5 ]; + R0.H = W [ SP ]; + R1.H = W [ FP ]; + CHECKREG r0, 0xC0095000; + CHECKREG r1, 0x600F6001; + CHECKREG r2, 0xB00A7002; + CHECKREG r3, 0xA00B8003; + CHECKREG r4, 0x900C9004; + CHECKREG r5, 0x800DA005; + CHECKREG r6, 0x700EB006; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x0c; + loadsym p2, DATA_ADDR_2, 0x0a; + loadsym i1, DATA_ADDR_3, 0x08; + loadsym p4, DATA_ADDR_4, 0x06; + loadsym p5, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x02; + loadsym i3, DATA_ADDR_7, 0x00; + P3 = I1; SP = I3; + W [ P1 ] = R2.H; + W [ P2 ] = R3.H; + W [ P3 ] = R4.H; + W [ P4 ] = R5.H; + W [ P5 ] = R6.H; + W [ SP ] = R7.H; + W [ FP ] = R1.H; + R1.L = W [ P1 ]; + R2.L = W [ P2 ]; + R3.L = W [ P3 ]; + R4.L = W [ P4 ]; + R5.L = W [ P5 ]; + R6.L = W [ SP ]; + R0.L = W [ FP ]; + CHECKREG r0, 0x105F204E; + CHECKREG r1, 0x204E3003; + CHECKREG r2, 0x3003402C; + CHECKREG r3, 0x402C501B; + CHECKREG r4, 0x501B600A; + CHECKREG r5, 0x600A7019; + CHECKREG r6, 0x7019D028; + +// initial values + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x12345675; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x10; + loadsym p2, DATA_ADDR_2, 0x02; + loadsym i1, DATA_ADDR_3, 0x00; + loadsym p4, DATA_ADDR_4, 0x08; + loadsym p5, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x06; + loadsym i3, DATA_ADDR_7, 0x02; + P3 = I1; SP = I3; + W [ P1 ] = R5.H; + W [ P2 ] = R6.H; + W [ P3 ] = R7.H; + W [ P4 ] = R0.H; + W [ P5 ] = R1.H; + W [ SP ] = R2.H; + W [ FP ] = R3.H; + R5.H = W [ P1 ]; + R4.H = W [ P2 ]; + R3.H = W [ P3 ]; + R2.H = W [ P4 ]; + R1.H = W [ P5 ]; + R0.H = W [ SP ]; + R6.H = W [ FP ]; + CHECKREG r0, 0x30BD50B0; + CHECKREG r1, 0x20BE60B1; + CHECKREG r2, 0x10BF70B2; + CHECKREG r3, 0x80B880B3; + CHECKREG r4, 0x70B990B4; + CHECKREG r5, 0x12345675; + CHECKREG r6, 0x40BCB0B6; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_lo.s b/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_lo.s new file mode 100644 index 0000000..b005545 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstpmod_st_dr_lo.s @@ -0,0 +1,401 @@ +//Original:testcases/core/c_ldstpmod_st_dr_lo/c_ldstpmod_st_dr_lo.dsp +// Spec Reference: c_ldstpmod store dreg lo +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x600f5000; + imm32 r1, 0x700e6001; + imm32 r2, 0x800d7002; + imm32 r3, 0x900c8003; + imm32 r4, 0xa00b9004; + imm32 r5, 0xb00aa005; + imm32 r6, 0xc009b006; + imm32 r7, 0xd008c007; + + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + loadsym p2, DATA_ADDR_2, 0x02; + loadsym i1, DATA_ADDR_3, 0x04; + loadsym p4, DATA_ADDR_4, 0x06; + loadsym p5, DATA_ADDR_5, 0x08; + loadsym fp, DATA_ADDR_6, 0x0a; + loadsym i3, DATA_ADDR_7, 0x0c; + P3 = I1; SP = I3; + + W [ P1 ] = R1.L; + W [ P2 ] = R2.L; + W [ P3 ] = R3.L; + W [ P4 ] = R4.L; + W [ P5 ] = R5.L; + W [ SP ] = R6.L; + W [ FP ] = R0.L; + R6.L = W [ P1 ]; + R5.L = W [ P2 ]; + R4.L = W [ P3 ]; + R3.L = W [ P4 ]; + R2.L = W [ P5 ]; + R0.L = W [ SP ]; + R1.L = W [ FP ]; + CHECKREG r0, 0x600FB006; + CHECKREG r1, 0x700E5000; + CHECKREG r2, 0x800DA005; + CHECKREG r3, 0x900C9004; + CHECKREG r4, 0xA00B8003; + CHECKREG r5, 0xB00A7002; + CHECKREG r6, 0xC0096001; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x0c; + loadsym p2, DATA_ADDR_2, 0x0a; + loadsym i1, DATA_ADDR_3, 0x08; + loadsym p4, DATA_ADDR_4, 0x06; + loadsym p5, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x02; + loadsym i3, DATA_ADDR_7, 0x00; + P3 = I1; SP = I3; + W [ P1 ] = R2.L; + W [ P2 ] = R3.L; + W [ P3 ] = R4.L; + W [ P4 ] = R5.L; + W [ P5 ] = R6.L; + W [ SP ] = R7.L; + W [ FP ] = R1.L; + R1.L = W [ P1 ]; + R2.L = W [ P2 ]; + R3.L = W [ P3 ]; + R4.L = W [ P4 ]; + R5.L = W [ P5 ]; + R6.L = W [ SP ]; + R0.L = W [ FP ]; + CHECKREG r0, 0x105F60A1; + CHECKREG r1, 0x204E70A2; + CHECKREG r2, 0x300380A3; + CHECKREG r3, 0x402C90A4; + CHECKREG r4, 0x501BA0A5; + CHECKREG r5, 0x600AB0A6; + CHECKREG r6, 0x7019C0A7; + +// initial values + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x10; + loadsym p2, DATA_ADDR_2, 0x02; + loadsym i1, DATA_ADDR_3, 0x00; + loadsym p4, DATA_ADDR_4, 0x08; + loadsym p5, DATA_ADDR_5, 0x04; + loadsym fp, DATA_ADDR_6, 0x06; + loadsym i3, DATA_ADDR_7, 0x02; + P3 = I1; SP = I3; + W [ P1 ] = R5.L; + W [ P2 ] = R6.L; + W [ P3 ] = R7.L; + W [ P4 ] = R0.L; + W [ P5 ] = R1.L; + W [ SP ] = R2.L; + W [ FP ] = R3.L; + R5.L = W [ P1 ]; + R4.L = W [ P2 ]; + R3.L = W [ P3 ]; + R2.L = W [ P4 ]; + R1.L = W [ P5 ]; + R0.L = W [ SP ]; + R6.L = W [ FP ]; + CHECKREG r0, 0x10BF70B2; + CHECKREG r1, 0x20BE60B1; + CHECKREG r2, 0x30BD50B0; + CHECKREG r3, 0x40BCC0B7; + CHECKREG r4, 0x55BBB0B6; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B980B3; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_st_dreg.s b/sim/testsuite/sim/bfin/c_ldstpmod_st_dreg.s new file mode 100644 index 0000000..e1ec36f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstpmod_st_dreg.s @@ -0,0 +1,623 @@ +//Original:testcases/core/c_ldstpmod_st_dreg/c_ldstpmod_st_dreg.dsp +// Spec Reference: c_ldstpmod store dreg +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x600f5000; + imm32 r1, 0x700e6001; + imm32 r2, 0x800d7002; + imm32 r3, 0x900c8003; + imm32 r4, 0xa00b9004; + imm32 r5, 0xb00aa005; + imm32 r6, 0xc009b006; + imm32 r7, 0xd008c007; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0008; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + [ P5 ++ P1 ] = R0; + [ P5 ++ P1 ] = R1; + [ P5 ++ P2 ] = R2; + [ P5 ++ P3 ] = R3; + [ P5 ++ P4 ] = R4; + [ P5 ++ SP ] = R5; + [ P5 ++ FP ] = R6; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0008; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + R6 = [ P5 ++ P1 ]; + R5 = [ P5 ++ P1 ]; + R4 = [ P5 ++ P2 ]; + R3 = [ P5 ++ P3 ]; + R2 = [ P5 ++ P4 ]; + R0 = [ P5 ++ SP ]; + R1 = [ P5 ++ FP ]; + CHECKREG r0, 0xB00AA005; + CHECKREG r1, 0xC009B006; + CHECKREG r2, 0xA00B9004; + CHECKREG r3, 0x900C8003; + CHECKREG r4, 0x800D7002; + CHECKREG r5, 0x700E6001; + CHECKREG r6, 0x600F5000; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x600aa0a5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + P5 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0008; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + [ P1 ++ P5 ] = R0; + [ P1 ++ P5 ] = R1; + [ P1 ++ P2 ] = R2; + [ P1 ++ P3 ] = R3; + [ P1 ++ P4 ] = R4; + [ P1 ++ SP ] = R5; + [ P1 ++ FP ] = R6; + P5 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0008; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + R6 = [ P1 ++ P5 ]; + R5 = [ P1 ++ P5 ]; + R4 = [ P1 ++ P2 ]; + R3 = [ P1 ++ P3 ]; + R2 = [ P1 ++ P4 ]; + R0 = [ P1 ++ SP ]; + R1 = [ P1 ++ FP ]; + CHECKREG r0, 0x600AA0A5; + CHECKREG r1, 0x7019B0A6; + CHECKREG r2, 0x501B90A4; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300370A2; + CHECKREG r5, 0x204E60A1; + CHECKREG r6, 0x105F50A0; + +// initial values + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + P5 = 0x0004; + P1 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + [ P2 ++ P5 ] = R0; + [ P2 ++ P1 ] = R1; + [ P2 ++ P1 ] = R2; + [ P2 ++ P3 ] = R3; + [ P2 ++ P4 ] = R4; + [ P2 ++ SP ] = R5; + [ P2 ++ FP ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x00; + P3 = I1; SP = I3; + R3 = [ P2 ++ P5 ]; + R4 = [ P2 ++ P1 ]; + R0 = [ P2 ++ P1 ]; + R1 = [ P2 ++ P3 ]; + R2 = [ P2 ++ P4 ]; + R5 = [ P2 ++ SP ]; + R6 = [ P2 ++ FP ]; + CHECKREG r0, 0x30BD70B2; + CHECKREG r1, 0x40BC80B3; + CHECKREG r2, 0x55BB90B4; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x20BE60B1; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B9B0B6; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + [ P3 ++ P5 ] = R0; + [ P3 ++ P1 ] = R1; + [ P3 ++ P2 ] = R2; + [ P3 ++ P1 ] = R3; + [ P3 ++ P4 ] = R4; + [ P3 ++ SP ] = R5; + [ P3 ++ FP ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x00; + P3 = I1; SP = I3; + R6 = [ P3 ++ P5 ]; + R5 = [ P3 ++ P1 ]; + R4 = [ P3 ++ P2 ]; + R3 = [ P3 ++ P1 ]; + R2 = [ P3 ++ P4 ]; + R0 = [ P3 ++ SP ]; + R1 = [ P3 ++ FP ]; + CHECKREG r0, 0x60CAA0C5; + CHECKREG r1, 0x70C9B0C6; + CHECKREG r2, 0x50CB90C4; + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x30C370C2; + CHECKREG r5, 0x20CE60C1; + CHECKREG r6, 0x10CF50C0; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + [ P4 ++ P5 ] = R0; + [ P4 ++ P1 ] = R1; + [ P4 ++ P2 ] = R2; + [ P4 ++ P3 ] = R3; + [ P4 ++ P1 ] = R4; + [ P4 ++ SP ] = R5; + [ P4 ++ FP ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + FP = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x00; + P3 = I1; SP = I3; + R5 = [ P4 ++ P5 ]; + R6 = [ P4 ++ P1 ]; + R0 = [ P4 ++ P2 ]; + R1 = [ P4 ++ P3 ]; + R2 = [ P4 ++ P1 ]; + R3 = [ P4 ++ SP ]; + R4 = [ P4 ++ FP ]; + CHECKREG r0, 0x80DD70D2; + CHECKREG r1, 0x90DC80D3; + CHECKREG r2, 0xA0DB90D4; + CHECKREG r3, 0xB0DAA0D5; + CHECKREG r4, 0xC0D9B0D6; + CHECKREG r5, 0x60DF50D0; + CHECKREG r6, 0x70DE60D1; + +// initial values + imm32 r0, 0x1e5f50e0; + imm32 r1, 0x2e4e60e1; + imm32 r2, 0x3e0370e2; + imm32 r3, 0x4e2c80e3; + imm32 r4, 0x5e1b90e4; + imm32 r5, 0x6e0aa0e5; + imm32 r6, 0x7e19b0e6; + imm32 r7, 0xde28c0e7; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x00; + P3 = I1; SP = I3; + [ SP ++ P5 ] = R0; + [ SP ++ P1 ] = R1; + [ SP ++ P2 ] = R2; + [ SP ++ P3 ] = R3; + [ SP ++ P4 ] = R4; + [ SP ++ P1 ] = R5; + [ SP ++ FP ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x00; + P3 = I1; SP = I3; + R6 = [ SP ++ P5 ]; + R5 = [ SP ++ P1 ]; + R4 = [ SP ++ P2 ]; + R3 = [ SP ++ P3 ]; + R2 = [ SP ++ P4 ]; + R0 = [ SP ++ P1 ]; + R1 = [ SP ++ FP ]; + CHECKREG r0, 0x6E0AA0E5; + CHECKREG r1, 0x7E19B0E6; + CHECKREG r2, 0x5E1B90E4; + CHECKREG r3, 0x4E2C80E3; + CHECKREG r4, 0x3E0370E2; + CHECKREG r5, 0x2E4E60E1; + CHECKREG r6, 0x1E5F50E0; + +// initial values + imm32 r0, 0x10ff50f0; + imm32 r1, 0x20fe60f1; + imm32 r2, 0x30fd70f2; + imm32 r3, 0x40fc80f3; + imm32 r4, 0x55fb90f4; + imm32 r5, 0x60faa0f5; + imm32 r6, 0x70f9b0f6; + imm32 r7, 0x80f8c0f7; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x1004 (X); + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x00; + P3 = I1; SP = I3; + [ FP ++ P5 ] = R0; + [ FP ++ P1 ] = R1; + [ FP ++ P2 ] = R2; + [ FP ++ P3 ] = R3; + [ FP ++ P4 ] = R4; + [ FP ++ SP ] = R5; + [ FP ++ P1 ] = R6; + P5 = 0x0004; + P1 = 0x0004; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x00; + P3 = I1; SP = I3; + R3 = [ FP ++ P5 ]; + R4 = [ FP ++ P1 ]; + R0 = [ FP ++ P2 ]; + R1 = [ FP ++ P3 ]; + R2 = [ FP ++ P4 ]; + R5 = [ FP ++ SP ]; + R6 = [ FP ++ P1 ]; + CHECKREG r0, 0x30FD70F2; + CHECKREG r1, 0x40FC80F3; + CHECKREG r2, 0x55FB90F4; + CHECKREG r3, 0x10FF50F0; + CHECKREG r4, 0x20FE60F1; + CHECKREG r5, 0x60FAA0F5; + CHECKREG r6, 0x70F9B0F6; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_ldstpmod_st_lohi.s b/sim/testsuite/sim/bfin/c_ldstpmod_st_lohi.s new file mode 100644 index 0000000..58990ad --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ldstpmod_st_lohi.s @@ -0,0 +1,625 @@ +//Original:testcases/core/c_ldstpmod_st_lohi/c_ldstpmod_st_lohi.dsp +// Spec Reference: c_ldstpmod store dreg lo & hi +# mach: bfin + +.include "testutils.inc" + start + +// set all regs +init_i_regs 0; +init_b_regs 0; +init_l_regs 0; +init_m_regs 0; +I0 = P3; +I2 = SP; + +// initial values + imm32 r0, 0x600f5000; + imm32 r1, 0x700e6001; + imm32 r2, 0x800d7002; + imm32 r3, 0x900c8003; + imm32 r4, 0xa00b9004; + imm32 r5, 0xb00aa005; + imm32 r6, 0xc009b006; + imm32 r7, 0xd008c007; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0006; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + + W [ P5 ++ P1 ] = R0.L; + W [ P5 ++ P1 ] = R1.L; + W [ P5 ++ P2 ] = R2.L; + W [ P5 ++ P3 ] = R3.L; + W [ P5 ++ P4 ] = R4.L; + W [ P5 ++ SP ] = R5.L; + W [ P5 ++ FP ] = R6.L; + + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0002; + FP = 0x0002; + SP = 0x0006; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p5, DATA_ADDR_5, 0x00; + P3 = I1; SP = I3; + + R6.L = W [ P5 ++ P1 ]; + R5.L = W [ P5 ++ P1 ]; + R4.L = W [ P5 ++ P2 ]; + R3.L = W [ P5 ++ P3 ]; + R2.L = W [ P5 ++ P4 ]; + R0.L = W [ P5 ++ SP ]; + R1.L = W [ P5 ++ FP ]; + CHECKREG r0, 0x600FA005; + CHECKREG r1, 0x700EB006; + CHECKREG r2, 0x800D9004; + CHECKREG r3, 0x900C8003; + CHECKREG r4, 0xA00B7002; + CHECKREG r5, 0xB00A6001; + CHECKREG r6, 0xC0095000; + +// initial values + imm32 r0, 0x105f50a0; + imm32 r1, 0x204e60a1; + imm32 r2, 0x300370a2; + imm32 r3, 0x402c80a3; + imm32 r4, 0x501b90a4; + imm32 r5, 0x204EA0A5; + imm32 r6, 0x7019b0a6; + imm32 r7, 0xd028c0a7; + P5 = 0x0002; + P2 = 0x0002; + P3 = 0x0004; + P4 = 0x0002; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + W [ P1 ++ P5 ] = R0.H; + W [ P1 ++ P2 ] = R1.H; + W [ P1 ++ P2 ] = R2.H; + W [ P1 ++ P3 ] = R3.H; + W [ P1 ++ P4 ] = R4.H; + W [ P1 ++ SP ] = R5.H; + W [ P1 ++ FP ] = R6.H; + P5 = 0x0002; + P2 = 0x0002; + P3 = 0x0004; + P4 = 0x0002; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p1, DATA_ADDR_1, 0x00; + P3 = I1; SP = I3; + R6.H = W [ P1 ++ P5 ]; + R5.H = W [ P1 ++ P2 ]; + R4.H = W [ P1 ++ P2 ]; + R3.H = W [ P1 ++ P3 ]; + R2.H = W [ P1 ++ P4 ]; + R0.H = W [ P1 ++ SP ]; + R1.H = W [ P1 ++ FP ]; + CHECKREG r0, 0x204E50A0; + CHECKREG r1, 0x701960A1; + CHECKREG r2, 0x501B70A2; + CHECKREG r3, 0x402C80A3; + CHECKREG r4, 0x300390A4; + CHECKREG r5, 0x204EA0A5; + CHECKREG r6, 0x105FB0A6; + +// initial values + imm32 r0, 0x10bf50b0; + imm32 r1, 0x20be60b1; + imm32 r2, 0x30bd70b2; + imm32 r3, 0x40bc80b3; + imm32 r4, 0x55bb90b4; + imm32 r5, 0x60baa0b5; + imm32 r6, 0x70b9b0b6; + imm32 r7, 0x80b8c0b7; + P5 = 0x0002; + P1 = 0x0002; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x02; + P3 = I1; SP = I3; + W [ P2 ++ P5 ] = R0.L; + W [ P2 ++ P1 ] = R0.H; + W [ P2 ++ P2 ] = R2.H; + W [ P2 ++ P3 ] = R2.H; + W [ P2 ++ P4 ] = R4.L; + W [ P2 ++ SP ] = R4.H; + W [ P2 ++ FP ] = R6.L; + P5 = 0x0002; + P1 = 0x0002; + P3 = 0x0002; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p2, DATA_ADDR_2, 0x02; + P3 = I1; SP = I3; + R3.L = W [ P2 ++ P5 ]; + R3.H = W [ P2 ++ P1 ]; + R0.L = W [ P2 ++ P2 ]; + R0.H = W [ P2 ++ P3 ]; + R2.L = W [ P2 ++ P4 ]; + R2.H = W [ P2 ++ SP ]; + R6.L = W [ P2 ++ FP ]; + CHECKREG r0, 0x30BD30BD; + CHECKREG r1, 0x20BE60B1; + CHECKREG r2, 0x2E2F2A2B; + CHECKREG r3, 0x10BF50B0; + CHECKREG r4, 0x55BB90B4; + CHECKREG r5, 0x60BAA0B5; + CHECKREG r6, 0x70B955BB; + +// initial values + imm32 r0, 0x10cf50c0; + imm32 r1, 0x20ce60c1; + imm32 r2, 0x30c370c2; + imm32 r3, 0x40cc80c3; + imm32 r4, 0x50cb90c4; + imm32 r5, 0x60caa0c5; + imm32 r6, 0x70c9b0c6; + imm32 r7, 0xd0c8c0c7; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x02; + P3 = I1; SP = I3; + W [ P3 ++ P5 ] = R1.H; + W [ P3 ++ P1 ] = R1.L; + W [ P3 ++ P2 ] = R3.L; + W [ P3 ++ P2 ] = R3.H; + W [ P3 ++ P4 ] = R5.H; + W [ P3 ++ SP ] = R6.H; + W [ P3 ++ FP ] = R6.L; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P4 = 0x0004; + FP = 0x0006; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i1, DATA_ADDR_3, 0x02; + P3 = I1; SP = I3; + R6.L = W [ P3 ++ P5 ]; + R6.H = W [ P3 ++ P1 ]; + R4.H = W [ P3 ++ P2 ]; + R4.L = W [ P3 ++ P2 ]; + R5.L = W [ P3 ++ P4 ]; + R5.H = W [ P3 ++ SP ]; + R1.L = W [ P3 ++ FP ]; + CHECKREG r0, 0x10CF50C0; + CHECKREG r1, 0x20CEB0C6; + CHECKREG r2, 0x30C370C2; + CHECKREG r3, 0x40CC80C3; + CHECKREG r4, 0x80C340CC; + CHECKREG r5, 0x70C960CA; + CHECKREG r6, 0x60C120CE; + +// initial values + imm32 r0, 0x60df50d0; + imm32 r1, 0x70de60d1; + imm32 r2, 0x80dd70d2; + imm32 r3, 0x90dc80d3; + imm32 r4, 0xa0db90d4; + imm32 r5, 0xb0daa0d5; + imm32 r6, 0xc0d9b0d6; + imm32 r7, 0xd0d8c0d7; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x02; + P3 = I1; SP = I3; + W [ P4 ++ P5 ] = R0.L; + W [ P4 ++ P1 ] = R1.H; + W [ P4 ++ P2 ] = R2.L; + W [ P4 ++ P3 ] = R3.H; + W [ P4 ++ P3 ] = R4.H; + W [ P4 ++ SP ] = R5.L; + W [ P4 ++ FP ] = R6.H; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + FP = 0x0002; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym p4, DATA_ADDR_4, 0x02; + P3 = I1; SP = I3; + R5.L = W [ P4 ++ P5 ]; + R6.L = W [ P4 ++ P1 ]; + R0.H = W [ P4 ++ P2 ]; + R1.L = W [ P4 ++ P3 ]; + R2.L = W [ P4 ++ P3 ]; + R3.H = W [ P4 ++ SP ]; + R4.H = W [ P4 ++ FP ]; + CHECKREG r0, 0x70D250D0; + CHECKREG r1, 0x70DE90DC; + CHECKREG r2, 0x80DDA0DB; + CHECKREG r3, 0xA0D580D3; + CHECKREG r4, 0xC0D990D4; + CHECKREG r5, 0xB0DA50D0; + CHECKREG r6, 0xC0D970DE; + +// initial values + imm32 r0, 0x1e5f50e0; + imm32 r1, 0x2e4e60e1; + imm32 r2, 0x3e0370e2; + imm32 r3, 0x4e2c80e3; + imm32 r4, 0x5e1b90e4; + imm32 r5, 0x6e0aa0e5; + imm32 r6, 0x7e19b0e6; + imm32 r7, 0xde28c0e7; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0002; + FP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x02; + P3 = I1; SP = I3; + W [ SP ++ P5 ] = R0.H; + W [ SP ++ P1 ] = R1.H; + W [ SP ++ P2 ] = R2.L; + W [ SP ++ P3 ] = R3.L; + W [ SP ++ P4 ] = R4.H; + W [ SP ++ FP ] = R5.H; + W [ SP ++ FP ] = R6.L; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0004; + P3 = 0x0004; + P4 = 0x0004; + FP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym i3, DATA_ADDR_6, 0x02; + P3 = I1; SP = I3; + R6.H = W [ SP ++ P5 ]; + R5.H = W [ SP ++ P1 ]; + R4.H = W [ SP ++ P2 ]; + R3.H = W [ SP ++ P3 ]; + R3.L = W [ SP ++ P4 ]; + R0.L = W [ SP ++ FP ]; + R1.L = W [ SP ++ FP ]; + CHECKREG r0, 0x1E5FB0E6; + CHECKREG r1, 0x2E4E1617; + CHECKREG r2, 0x3E0370E2; + CHECKREG r3, 0x80E35E1B; + CHECKREG r4, 0x70E290E4; + CHECKREG r5, 0x2E4EA0E5; + CHECKREG r6, 0x1E5FB0E6; + +// initial values + imm32 r0, 0x10ff50f0; + imm32 r1, 0x20fe60f1; + imm32 r2, 0x30fd70f2; + imm32 r3, 0x40fc80f3; + imm32 r4, 0x55fb90f4; + imm32 r5, 0x60faa0f5; + imm32 r6, 0x70f9b0f6; + imm32 r7, 0x80f8c0f7; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0004; + SP = 0x0002; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x02; + P3 = I1; SP = I3; + W [ FP ++ P5 ] = R0.L; + W [ FP ++ P1 ] = R1.H; + W [ FP ++ P2 ] = R2.H; + W [ FP ++ P3 ] = R3.H; + W [ FP ++ P4 ] = R4.L; + W [ FP ++ SP ] = R5.L; + W [ FP ++ SP ] = R6.L; + P5 = 0x0002; + P1 = 0x0002; + P2 = 0x0002; + P3 = 0x0002; + P4 = 0x0004; + SP = 0x0004; + I1 = P3; P3 = I0; I3 = SP; SP = I2; + loadsym fp, DATA_ADDR_7, 0x02; + P3 = I1; SP = I3; + R3.L = W [ FP ++ P5 ]; + R4.L = W [ FP ++ P1 ]; + R0.H = W [ FP ++ P2 ]; + R1.H = W [ FP ++ P3 ]; + R2.L = W [ FP ++ P4 ]; + R5.H = W [ FP ++ SP ]; + R6.H = W [ FP ++ SP ]; + CHECKREG r0, 0x30FD50F0; + CHECKREG r1, 0x40FC60F1; + CHECKREG r2, 0x30FD90F4; + CHECKREG r3, 0x40FC50F0; + CHECKREG r4, 0x55FB20FE; + CHECKREG r5, 0xA0F5A0F5; + CHECKREG r6, 0x9091B0F6; + + P3 = I0; SP = I2; + pass + +// Pre-load memory with known data +// More data is defined than will actually be used + + .data +DATA_ADDR_1: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x11223344 + .dd 0x55667788 + .dd 0x99717273 + .dd 0x74757677 + .dd 0x82838485 + .dd 0x86878889 + .dd 0x80818283 + .dd 0x84858687 + .dd 0x01020304 + .dd 0x05060708 + .dd 0x09101112 + .dd 0x14151617 + .dd 0x18192021 + .dd 0x22232425 + .dd 0x26272829 + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38394041 + .dd 0x42434445 + .dd 0x46474849 + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58596061 + .dd 0x62636465 + .dd 0x66676869 + .dd 0x74555657 + .dd 0x78596067 + .dd 0x72636467 + .dd 0x76676867 + +DATA_ADDR_2: + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x91929394 + .dd 0x95969798 + .dd 0x99A1A2A3 + .dd 0xA5A6A7A8 + .dd 0xA9B0B1B2 + .dd 0xB3B4B5B6 + .dd 0xB7B8B9C0 + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78798081 + .dd 0x82838485 + .dd 0x86C283C4 + .dd 0x81C283C4 + .dd 0x82C283C4 + .dd 0x83C283C4 + .dd 0x84C283C4 + .dd 0x85C283C4 + .dd 0x86C283C4 + .dd 0x87C288C4 + .dd 0x88C283C4 + .dd 0x89C283C4 + .dd 0x80C283C4 + .dd 0x81C283C4 + .dd 0x82C288C4 + .dd 0x94555659 + .dd 0x98596069 + .dd 0x92636469 + .dd 0x96676869 + +DATA_ADDR_3: + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0xC5C6C7C8 + .dd 0xC9CACBCD + .dd 0xCFD0D1D2 + .dd 0xD3D4D5D6 + .dd 0xD7D8D9DA + .dd 0xDBDCDDDE + .dd 0xDFE0E1E2 + .dd 0xE3E4E5E6 + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x97E899EA + .dd 0x98E899EA + .dd 0x99E899EA + .dd 0x91E899EA + .dd 0x92E899EA + .dd 0x93E899EA + .dd 0x94E899EA + .dd 0x95E899EA + .dd 0x96E899EA + .dd 0x977899EA + .dd 0xa455565a + .dd 0xa859606a + .dd 0xa263646a + .dd 0xa667686a + +DATA_ADDR_4: + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + .dd 0xEBECEDEE + .dd 0xF3F4F5F6 + .dd 0xF7F8F9FA + .dd 0xFBFCFDFE + .dd 0xFF000102 + .dd 0x03040506 + .dd 0x0708090A + .dd 0x0B0CAD0E + .dd 0xAB0CAD01 + .dd 0xAB0CAD02 + .dd 0xAB0CAD03 + .dd 0xAB0CAD04 + .dd 0xAB0CAD05 + .dd 0xAB0CAD06 + .dd 0xAB0CAA07 + .dd 0xAB0CAD08 + .dd 0xAB0CAD09 + .dd 0xA00CAD1E + .dd 0xA10CAD2E + .dd 0xA20CAD3E + .dd 0xA30CAD4E + .dd 0xA40CAD5E + .dd 0xA50CAD6E + .dd 0xA60CAD7E + .dd 0xB455565B + .dd 0xB859606B + .dd 0xB263646B + .dd 0xB667686B + +DATA_ADDR_5: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0x0F101213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0xBC0DBE21 + .dd 0xBC1DBE22 + .dd 0xBC2DBE23 + .dd 0xBC3DBE24 + .dd 0xBC4DBE65 + .dd 0xBC5DBE27 + .dd 0xBC6DBE28 + .dd 0xBC7DBE29 + .dd 0xBC8DBE2F + .dd 0xBC9DBE20 + .dd 0xBCADBE21 + .dd 0xBCBDBE2F + .dd 0xBCCDBE23 + .dd 0xBCDDBE24 + .dd 0xBCFDBE25 + .dd 0xC455565C + .dd 0xC859606C + .dd 0xC263646C + .dd 0xC667686C + .dd 0xCC0DBE2C + +DATA_ADDR_6: + .dd 0x00010203 + .dd 0x04050607 + .dd 0x08090A0B + .dd 0x0C0D0E0F + .dd 0x10111213 + .dd 0x14151617 + .dd 0x18191A1B + .dd 0x1C1D1E1F + .dd 0x20212223 + .dd 0x24252627 + .dd 0x28292A2B + .dd 0x2C2D2E2F + .dd 0x30313233 + .dd 0x34353637 + .dd 0x38393A3B + .dd 0x3C3D3E3F + .dd 0x40414243 + .dd 0x44454647 + .dd 0x48494A4B + .dd 0x4C4D4E4F + .dd 0x50515253 + .dd 0x54555657 + .dd 0x58595A5B + .dd 0x5C5D5E5F + .dd 0x60616263 + .dd 0x64656667 + .dd 0x68696A6B + .dd 0x6C6D6E6F + .dd 0x70717273 + .dd 0x74757677 + .dd 0x78797A7B + .dd 0x7C7D7E7F + +DATA_ADDR_7: + .dd 0x80818283 + .dd 0x84858687 + .dd 0x88898A8B + .dd 0x8C8D8E8F + .dd 0x90919293 + .dd 0x94959697 + .dd 0x98999A9B + .dd 0x9C9D9E9F + .dd 0xA0A1A2A3 + .dd 0xA4A5A6A7 + .dd 0xA8A9AAAB + .dd 0xACADAEAF + .dd 0xB0B1B2B3 + .dd 0xB4B5B6B7 + .dd 0xB8B9BABB + .dd 0xBCBDBEBF + .dd 0xC0C1C2C3 + .dd 0xC4C5C6C7 + .dd 0xC8C9CACB + .dd 0xCCCDCECF + .dd 0xD0D1D2D3 + .dd 0xD4D5D6D7 + .dd 0xD8D9DADB + .dd 0xDCDDDEDF + .dd 0xE0E1E2E3 + .dd 0xE4E5E6E7 + .dd 0xE8E9EAEB + .dd 0xECEDEEEF + .dd 0xF0F1F2F3 + .dd 0xF4F5F6F7 + .dd 0xF8F9FAFB + .dd 0xFCFDFEFF diff --git a/sim/testsuite/sim/bfin/c_linkage.s b/sim/testsuite/sim/bfin/c_linkage.s new file mode 100644 index 0000000..d7d673e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_linkage.s @@ -0,0 +1,60 @@ +//Original:testcases/core/c_linkage/c_linkage.dsp +// Spec Reference: linkage (link & unlnk) +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS(0); + + loadsym sp, DATA_ADDR_1, 0x24; + p0 = sp; + + FP = 0x0064 (X); + R0 = 5; + RETS = R0; + + LINK 4; // push rets, push fp, fp=sp, sp=sp-framesize (4) + + R1 = 3; + RETS = R1; // initialize rets by a different value + + loadsym p1, SUBR + CALL ( P1 ); + + SP = 0x3333 (X); + + UNLINK; // sp = fp, fp = pop (old fp), rets = pop(old rets), + + R2 = RETS; // for checking + + CHECKREG r0, 0x00000005; + CHECKREG r1, 0x00000003; + CHECKREG r2, 0x00000005; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00001111; + CHECKREG r7, 0x00000000; + CHECKREG fp, 0x00000064; + CC = SP == P0; + if CC JUMP 1f; + fail; +1: + pass + +SUBR: // should jump here + R6.L = 0x1111; + RTS; + R7.L = 0x2222; // should not go here + RTS; + + .data +DATA_ADDR_1: +DATA: + .space (0x0100); + +// Stack Segments + + .space (0x100); +KSTACK: diff --git a/sim/testsuite/sim/bfin/c_logi2op_alshft_mix.s b/sim/testsuite/sim/bfin/c_logi2op_alshft_mix.s new file mode 100644 index 0000000..7e42664 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_logi2op_alshft_mix.s @@ -0,0 +1,143 @@ +//Original:/testcases/core/c_logi2op_alshft_mix/c_logi2op_alshft_mix.dsp +// Spec Reference: Logi2op >>>=, >>=, <<= +# mach: bfin + +.include "testutils.inc" + start + +// Arithmetic >>>= : positive data +imm32 r0, 0x40000000; +imm32 r1, 0x01111111; +imm32 r2, 0x22222222; +imm32 r3, 0x33333333; +imm32 r4, 0x44444444; +imm32 r5, 0x55555555; +imm32 r6, 0x66666666; +imm32 r7, 0x77777777; +R0 >>>= 1; /* r0 = 0x20000000 */ +R1 >>>= 1; /* r1 = 0x00888888 */ +R2 >>>= 2; /* r2 = 0x08888888 */ +R3 >>>= 8; /* r3 = 0x00333333 */ +R4 >>>= 1; /* r4 = 0x22222222 */ +R5 >>>= 27; /* r5 = 0x0000000a */ +R6 >>>= 30; /* r5 = 0x00000001 */ +R7 >>>= 31; /* r5 = 0x00000000 */ +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x00888888; +CHECKREG r2, 0x08888888; +CHECKREG r3, 0x00333333; +CHECKREG r4, 0x22222222; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + + + +// Arithmetic >>>= : negative data , +imm32 r0, 0x80000000; +imm32 r1, 0x81111111; +imm32 r2, 0xa2222222; +imm32 r3, 0xb3333333; +imm32 r4, 0xc4444444; +imm32 r5, 0xd5555555; +imm32 r6, 0xe6666666; +imm32 r7, 0xf7777777; +R0 >>>= 1; /* r0 = 0xc0000000 */ +R1 >>>= 1; /* r1 = 0xc0888888 */ +R2 >>>= 2; /* r2 = 0xe8888888 */ +R3 >>>= 8; /* r3 = 0x00333333 */ +R4 >>>= 1; /* r4 = 0x22222222 */ +R5 >>>= 27; /* r5 = 0x0000000a */ +R6 >>>= 30; /* r5 = 0x00000001 */ +R7 >>>= 31; /* r5 = 0x00000000 */ +CHECKREG r0, 0xc0000000; +CHECKREG r1, 0xc0888888; +CHECKREG r2, 0xe8888888; +CHECKREG r3, 0xffb33333; +CHECKREG r4, 0xe2222222; +CHECKREG r5, 0xfffffffa; +CHECKREG r6, 0xffffffff; +CHECKREG r7, 0xffffffff; + + +// Logical >>>= : positive data +imm32 r0, 0x40000000; +imm32 r1, 0x01111111; +imm32 r2, 0x22222222; +imm32 r3, 0x33333333; +imm32 r4, 0x44444444; +imm32 r5, 0x55555555; +imm32 r6, 0x66666666; +imm32 r7, 0x77777777; +R0 >>= 1; /* r0 = 0x20000000 */ +R1 >>= 1; /* r1 = 0x00888888 */ +R2 >>= 2; /* r2 = 0x08888888 */ +R3 >>= 8; /* r3 = 0x00333333 */ +R4 >>= 1; /* r4 = 0x22222222 */ +R5 >>= 27; /* r5 = 0x0000000a */ +R6 >>= 30; /* r5 = 0x00000001 */ +R7 >>= 31; /* r5 = 0x00000000 */ +CHECKREG r0, 0x20000000; +CHECKREG r1, 0x00888888; +CHECKREG r2, 0x08888888; +CHECKREG r3, 0x00333333; +CHECKREG r4, 0x22222222; +CHECKREG r5, 0x0000000a; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +// Logical >>= : negative data , +imm32 r0, 0x80000000; +imm32 r1, 0x81111111; +imm32 r2, 0xa2222222; +imm32 r3, 0xb3333333; +imm32 r4, 0xc4444444; +imm32 r5, 0xd5555555; +imm32 r6, 0xe6666666; +imm32 r7, 0xf7777777; +R0 >>= 1; /* r0 = 0x40000000 */ +R1 >>= 1; /* r1 = 0x40888888 */ +R2 >>= 2; /* r2 = 0x48888888 */ +R3 >>= 8; /* r3 = 0x40333333 */ +R4 >>= 1; /* r4 = 0xa2222222 */ +R5 >>= 27; /* r5 = 0x0000000a */ +R6 >>= 30; /* r5 = 0x00000001 */ +R7 >>= 31; /* r5 = 0x00000000 */ +CHECKREG r0, 0x40000000; +CHECKREG r1, 0x40888888; +CHECKREG r2, 0x28888888; +CHECKREG r3, 0x00b33333; +CHECKREG r4, 0x62222222; +CHECKREG r5, 0x0000001a; +CHECKREG r6, 0x00000003; +CHECKREG r7, 0x00000001; + + +// Logical <<= : negative data , +imm32 r0, 0x80000000; +imm32 r1, 0x81111111; +imm32 r2, 0xa2222222; +imm32 r3, 0xb3333333; +imm32 r4, 0xc4444444; +imm32 r5, 0xd5555555; +imm32 r6, 0xe6666666; +imm32 r7, 0xf7777777; +R0 <<= 1; /* r0 = 0x00000000 */ +R1 <<= 1; /* r1 = 0x40888888 */ +R2 <<= 2; /* r2 = 0x88888888 */ +R3 <<= 8; /* r3 = 0x33333300 */ +R4 <<= 1; /* r4 = 0x88888888 */ +R5 <<= 27; /* r5 = 0xa8000000 */ +R6 <<= 30; /* r5 = 0x80000000 */ +R7 <<= 31; /* r5 = 0x80000000 */ +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x02222222; +CHECKREG r2, 0x88888888; +CHECKREG r3, 0x33333300; +CHECKREG r4, 0x88888888; +CHECKREG r5, 0xa8000000; +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + // hlt; + +pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_arith_shft.s b/sim/testsuite/sim/bfin/c_logi2op_arith_shft.s new file mode 100644 index 0000000..110feee --- /dev/null +++ b/sim/testsuite/sim/bfin/c_logi2op_arith_shft.s @@ -0,0 +1,223 @@ +//Original:/testcases/core/c_logi2op_arith_shft/c_logi2op_arith_shft.dsp +// Spec Reference: Logi2op >>>= +# mach: bfin + +.include "testutils.inc" + start + + + + + +// Arithmetic >>>= : negative data +// bit 0-7 +imm32 r0, 0x81111111; +imm32 r1, 0x81111111; +imm32 r2, 0x81111111; +imm32 r3, 0x81111111; +imm32 r4, 0x81111111; +imm32 r5, 0x81111111; +imm32 r6, 0x81111111; +imm32 r7, 0x81111111; +R0 >>>= 0; /* r0 = 0x81111111 */ +R1 >>>= 1; /* r1 = 0xC0888888 */ +R2 >>>= 2; /* r2 = 0xE0444444 */ +R3 >>>= 3; /* r3 = 0xF0222222 */ +R4 >>>= 4; /* r4 = 0xF8111111 */ +R5 >>>= 5; /* r5 = 0xFC088888 */ +R6 >>>= 6; /* r6 = 0xFE044444 */ +R7 >>>= 7; /* r7 = 0xFF022222 */ +CHECKREG r0, 0x81111111; +CHECKREG r1, 0xC0888888; +CHECKREG r2, 0xE0444444; +CHECKREG r3, 0xF0222222; +CHECKREG r4, 0xF8111111; +CHECKREG r5, 0xFC088888; +CHECKREG r6, 0xFE044444; +CHECKREG r7, 0xFF022222; + +// bit 8-15 +imm32 r0, 0x82222222; +imm32 r1, 0x82222222; +imm32 r2, 0x82222222; +imm32 r3, 0x82222222; +imm32 r4, 0x82222222; +imm32 r5, 0x82222222; +imm32 r6, 0x82222222; +imm32 r7, 0x82222222; +R0 >>>= 8; /* r0 = 0xFF822222 */ +R1 >>>= 9; /* r1 = 0xFFC11111 */ +R2 >>>= 10; /* r2 = 0xFFE08888 */ +R3 >>>= 11; /* r3 = 0xFFF04444 */ +R4 >>>= 12; /* r4 = 0xFFF82222 */ +R5 >>>= 13; /* r5 = 0xFFFC1111 */ +R6 >>>= 14; /* r6 = 0xFFFE0888 */ +R7 >>>= 15; /* r7 = 0xFFFF0444 */ +CHECKREG r0, 0xFF822222; +CHECKREG r1, 0xFFC11111; +CHECKREG r2, 0xFFE08888; +CHECKREG r3, 0xFFF04444; +CHECKREG r4, 0xFFF82222; +CHECKREG r5, 0xFFFC1111; +CHECKREG r6, 0xFFFE0888; +CHECKREG r7, 0xFFFF0444; + +// bit 16-23 +imm32 r0, 0x83333333; +imm32 r1, 0x83333333; +imm32 r2, 0x83333333; +imm32 r3, 0x83333333; +imm32 r4, 0x83333333; +imm32 r5, 0x83333333; +imm32 r6, 0x83333333; +imm32 r7, 0x83333333; +R0 >>>= 16; /* r0 = 0xFFFF8333 */ +R1 >>>= 17; /* r1 = 0xFFFFC199 */ +R2 >>>= 18; /* r2 = 0xFFFFE0CC */ +R3 >>>= 19; /* r3 = 0xFFFFF066 */ +R4 >>>= 20; /* r4 = 0xFFFFF833 */ +R5 >>>= 21; /* r5 = 0xFFFFFC19 */ +R6 >>>= 22; /* r6 = 0xFFFFFE0C */ +R7 >>>= 23; /* r7 = 0xFFFFFF06 */ +CHECKREG r0, 0xFFFF8333; +CHECKREG r1, 0xFFFFC199; +CHECKREG r2, 0xFFFFE0CC; +CHECKREG r3, 0xFFFFF066; +CHECKREG r4, 0xFFFFF833; +CHECKREG r5, 0xFFFFFC19; +CHECKREG r6, 0xFFFFFE0C; +CHECKREG r7, 0xFFFFFF06; + +// bit 24-31 +imm32 r0, 0x84444444; +imm32 r1, 0x84444444; +imm32 r2, 0x84444444; +imm32 r3, 0x84444444; +imm32 r4, 0x84444444; +imm32 r5, 0x84444444; +imm32 r6, 0x84444444; +imm32 r7, 0x84444444; +R0 >>>= 24; /* r0 = 0xFFFFFF84 */ +R1 >>>= 25; /* r1 = 0xFFFFFFC2 */ +R2 >>>= 26; /* r2 = 0xFFFFFFE1 */ +R3 >>>= 27; /* r3 = 0xFFFFFFF0 */ +R4 >>>= 28; /* r4 = 0xFFFFFFF8 */ +R5 >>>= 29; /* r5 = 0xFFFFFFFC */ +R6 >>>= 30; /* r6 = 0xFFFFFFFE */ +R7 >>>= 31; /* r7 = 0xFFFFFFFF */ +CHECKREG r0, 0xFFFFFF84; +CHECKREG r1, 0xFFFFFFC2; +CHECKREG r2, 0xFFFFFFE1; +CHECKREG r3, 0xFFFFFFF0; +CHECKREG r4, 0xFFFFFFF8; +CHECKREG r5, 0xFFFFFFFC; +CHECKREG r6, 0xFFFFFFFE; +CHECKREG r7, 0xFFFFFFFF; + +// Arithmetic >>>= : positive data +// bit 0-7 +imm32 r0, 0x41111111; +imm32 r1, 0x41111111; +imm32 r2, 0x41111111; +imm32 r3, 0x41111111; +imm32 r4, 0x41111111; +imm32 r5, 0x41111111; +imm32 r6, 0x41111111; +imm32 r7, 0x41111111; +R0 >>>= 0; /* r0 = 0x41111111 */ +R1 >>>= 1; /* r1 = 0x20888888 */ +R2 >>>= 2; /* r2 = 0x10444444 */ +R3 >>>= 3; /* r3 = 0x08222222 */ +R4 >>>= 4; /* r4 = 0x04111111 */ +R5 >>>= 5; /* r5 = 0x02088888 */ +R6 >>>= 6; /* r6 = 0x01044444 */ +R7 >>>= 7; /* r7 = 0x00822222 */ +CHECKREG r0, 0x41111111; +CHECKREG r1, 0x20888888; +CHECKREG r2, 0x10444444; +CHECKREG r3, 0x08222222; +CHECKREG r4, 0x04111111; +CHECKREG r5, 0x02088888; +CHECKREG r6, 0x01044444; +CHECKREG r7, 0x00822222; + +// bit 8-15 +imm32 r0, 0x42222222; +imm32 r1, 0x42222222; +imm32 r2, 0x42222222; +imm32 r3, 0x42222222; +imm32 r4, 0x42222222; +imm32 r5, 0x42222222; +imm32 r6, 0x42222222; +imm32 r7, 0x42222222; +R0 >>>= 8; /* r0 = 0x00422222 */ +R1 >>>= 9; /* r1 = 0x00211111 */ +R2 >>>= 10; /* r2 = 0x00108888 */ +R3 >>>= 11; /* r3 = 0x00084444 */ +R4 >>>= 12; /* r4 = 0x00042222 */ +R5 >>>= 13; /* r5 = 0x00021111 */ +R6 >>>= 14; /* r6 = 0x00010888 */ +R7 >>>= 15; /* r7 = 0x00008444 */ +CHECKREG r0, 0x00422222; +CHECKREG r1, 0x00211111; +CHECKREG r2, 0x00108888; +CHECKREG r3, 0x00084444; +CHECKREG r4, 0x00042222; +CHECKREG r5, 0x00021111; +CHECKREG r6, 0x00010888; +CHECKREG r7, 0x00008444; + +// bit 16-23 +imm32 r0, 0x43333333; +imm32 r1, 0x43333333; +imm32 r2, 0x43333333; +imm32 r3, 0x43333333; +imm32 r4, 0x43333333; +imm32 r5, 0x43333333; +imm32 r6, 0x43333333; +imm32 r7, 0x43333333; +R0 >>>= 16; /* r0 = 0x00004333 */ +R1 >>>= 17; /* r1 = 0x00002199 */ +R2 >>>= 18; /* r2 = 0x000010CC */ +R3 >>>= 19; /* r3 = 0x00000866 */ +R4 >>>= 20; /* r4 = 0x00000433 */ +R5 >>>= 21; /* r5 = 0x00000219 */ +R6 >>>= 22; /* r6 = 0x0000010C */ +R7 >>>= 23; /* r7 = 0x00000086 */ +CHECKREG r0, 0x00004333; +CHECKREG r1, 0x00002199; +CHECKREG r2, 0x000010CC; +CHECKREG r3, 0x00000866; +CHECKREG r4, 0x00000433; +CHECKREG r5, 0x00000219; +CHECKREG r6, 0x0000010C; +CHECKREG r7, 0x00000086; + +// bit 24-31 +imm32 r0, 0x44444444; +imm32 r1, 0x44444444; +imm32 r2, 0x44444444; +imm32 r3, 0x44444444; +imm32 r4, 0x44444444; +imm32 r5, 0x44444444; +imm32 r6, 0x44444444; +imm32 r7, 0x44444444; +R0 >>>= 24; /* r0 = 0x00000044 */ +R1 >>>= 25; /* r1 = 0x00000022 */ +R2 >>>= 26; /* r2 = 0x00000011 */ +R3 >>>= 27; /* r3 = 0x00000008 */ +R4 >>>= 28; /* r4 = 0x00000004 */ +R5 >>>= 29; /* r5 = 0x00000002 */ +R6 >>>= 30; /* r6 = 0x00000001 */ +R7 >>>= 31; /* r7 = 0x00000000 */ +CHECKREG r0, 0x00000044; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000011; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + + +pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_bitclr.s b/sim/testsuite/sim/bfin/c_logi2op_bitclr.s new file mode 100644 index 0000000..b5ca481 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_logi2op_bitclr.s @@ -0,0 +1,92 @@ +//Original:/testcases/core/c_logi2op_bitclr/c_logi2op_bitclr.dsp +// Spec Reference: Logi2op functions: bitclr +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0xffffffff; +imm32 r1, 0xffffffff; +imm32 r2, 0xffffffff; +imm32 r3, 0xffffffff; +imm32 r4, 0xffffffff; +imm32 r5, 0xffffffff; +imm32 r6, 0xffffffff; +imm32 r7, 0xffffffff; + +// bit clr +BITCLR( R0 , 0 ); /* r0 = 0x00000001 */ +BITCLR( R1 , 1 ); /* r1 = 0x00000002 */ +BITCLR( R2 , 2 ); /* r2 = 0x00000004 */ +BITCLR( R3 , 3 ); /* r3 = 0x00000008 */ +BITCLR( R4 , 4 ); /* r4 = 0x00000010 */ +BITCLR( R5 , 5 ); /* r5 = 0x00000020 */ +BITCLR( R6 , 6 ); /* r6 = 0x00000040 */ +BITCLR( R7 , 7 ); /* r7 = 0x00000080 */ +CHECKREG r0, 0xfffffffe; +CHECKREG r1, 0xfffffffd; +CHECKREG r2, 0xfffffffb; +CHECKREG r3, 0xfffffff7; +CHECKREG r4, 0xffffffef; +CHECKREG r5, 0xffffffdf; +CHECKREG r6, 0xffffffbf; +CHECKREG r7, 0xffffff7f; + +// bit clr +BITCLR( R0 , 8 ); /* r0 = 0x00000100 */ +BITCLR( R1 , 9 ); /* r1 = 0x00000200 */ +BITCLR( R2 , 10 ); /* r2 = 0x00000400 */ +BITCLR( R3 , 11 ); /* r3 = 0x00000800 */ +BITCLR( R4 , 12 ); /* r4 = 0x00001000 */ +BITCLR( R5 , 13 ); /* r5 = 0x00002000 */ +BITCLR( R6 , 14 ); /* r6 = 0x00004000 */ +BITCLR( R7 , 15 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0xfffffefe; +CHECKREG r1, 0xfffffdfd; +CHECKREG r2, 0xfffffbfb; +CHECKREG r3, 0xfffff7f7; +CHECKREG r4, 0xffffefef; +CHECKREG r5, 0xffffdfdf; +CHECKREG r6, 0xffffbfbf; +CHECKREG r7, 0xffff7f7f; + +// bit clr +BITCLR( R0 , 16 ); /* r0 = 0x00000100 */ +BITCLR( R1 , 17 ); /* r1 = 0x00000200 */ +BITCLR( R2 , 18 ); /* r2 = 0x00000400 */ +BITCLR( R3 , 19 ); /* r3 = 0x00000800 */ +BITCLR( R4 , 20 ); /* r4 = 0x00001000 */ +BITCLR( R5 , 21 ); /* r5 = 0x00002000 */ +BITCLR( R6 , 22 ); /* r6 = 0x00004000 */ +BITCLR( R7 , 23 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0xfffefefe; +CHECKREG r1, 0xfffdfdfd; +CHECKREG r2, 0xfffbfbfb; +CHECKREG r3, 0xfff7f7f7; +CHECKREG r4, 0xffefefef; +CHECKREG r5, 0xffdfdfdf; +CHECKREG r6, 0xffbfbfbf; +CHECKREG r7, 0xff7f7f7f; + +// bit clr +BITCLR( R0 , 24 ); /* r0 = 0x00000100 */ +BITCLR( R1 , 25 ); /* r1 = 0x00000200 */ +BITCLR( R2 , 26 ); /* r2 = 0x00000400 */ +BITCLR( R3 , 27 ); /* r3 = 0x00000800 */ +BITCLR( R4 , 28 ); /* r4 = 0x00001000 */ +BITCLR( R5 , 29 ); /* r5 = 0x00002000 */ +BITCLR( R6 , 30 ); /* r6 = 0x00004000 */ +BITCLR( R7 , 31 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0xfefefefe; +CHECKREG r1, 0xfdfdfdfd; +CHECKREG r2, 0xfbfbfbfb; +CHECKREG r3, 0xf7f7f7f7; +CHECKREG r4, 0xefefefef; +CHECKREG r5, 0xdfdfdfdf; +CHECKREG r6, 0xbfbfbfbf; +CHECKREG r7, 0x7f7f7f7f; + + +pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_bitset.s b/sim/testsuite/sim/bfin/c_logi2op_bitset.s new file mode 100644 index 0000000..ce86d67 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_logi2op_bitset.s @@ -0,0 +1,92 @@ +//Original:/testcases/core/c_logi2op_bitset/c_logi2op_bitset.dsp +// Spec Reference: Logi2op +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// bit set +BITSET( R0 , 0 ); /* r0 = 0x00000001 */ +BITSET( R1 , 1 ); /* r1 = 0x00000002 */ +BITSET( R2 , 2 ); /* r2 = 0x00000004 */ +BITSET( R3 , 3 ); /* r3 = 0x00000008 */ +BITSET( R4 , 4 ); /* r4 = 0x00000010 */ +BITSET( R5 , 5 ); /* r5 = 0x00000020 */ +BITSET( R6 , 6 ); /* r6 = 0x00000040 */ +BITSET( R7 , 7 ); /* r7 = 0x00000080 */ +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000040; +CHECKREG r7, 0x00000080; + +// bit set +BITSET( R0 , 8 ); /* r0 = 0x00000100 */ +BITSET( R1 , 9 ); /* r1 = 0x00000200 */ +BITSET( R2 , 10 ); /* r2 = 0x00000400 */ +BITSET( R3 , 11 ); /* r3 = 0x00000800 */ +BITSET( R4 , 12 ); /* r4 = 0x00001000 */ +BITSET( R5 , 13 ); /* r5 = 0x00002000 */ +BITSET( R6 , 14 ); /* r6 = 0x00004000 */ +BITSET( R7 , 15 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00000101; +CHECKREG r1, 0x00000202; +CHECKREG r2, 0x00000404; +CHECKREG r3, 0x00000808; +CHECKREG r4, 0x00001010; +CHECKREG r5, 0x00002020; +CHECKREG r6, 0x00004040; +CHECKREG r7, 0x00008080; + +// bit set +BITSET( R0 , 16 ); /* r0 = 0x00000100 */ +BITSET( R1 , 17 ); /* r1 = 0x00000200 */ +BITSET( R2 , 18 ); /* r2 = 0x00000400 */ +BITSET( R3 , 19 ); /* r3 = 0x00000800 */ +BITSET( R4 , 20 ); /* r4 = 0x00001000 */ +BITSET( R5 , 21 ); /* r5 = 0x00002000 */ +BITSET( R6 , 22 ); /* r6 = 0x00004000 */ +BITSET( R7 , 23 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00010101; +CHECKREG r1, 0x00020202; +CHECKREG r2, 0x00040404; +CHECKREG r3, 0x00080808; +CHECKREG r4, 0x00101010; +CHECKREG r5, 0x00202020; +CHECKREG r6, 0x00404040; +CHECKREG r7, 0x00808080; + +// bit set +BITSET( R0 , 24 ); /* r0 = 0x00000100 */ +BITSET( R1 , 25 ); /* r1 = 0x00000200 */ +BITSET( R2 , 26 ); /* r2 = 0x00000400 */ +BITSET( R3 , 27 ); /* r3 = 0x00000800 */ +BITSET( R4 , 28 ); /* r4 = 0x00001000 */ +BITSET( R5 , 29 ); /* r5 = 0x00002000 */ +BITSET( R6 , 30 ); /* r6 = 0x00004000 */ +BITSET( R7 , 31 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x01010101; +CHECKREG r1, 0x02020202; +CHECKREG r2, 0x04040404; +CHECKREG r3, 0x08080808; +CHECKREG r4, 0x10101010; +CHECKREG r5, 0x20202020; +CHECKREG r6, 0x40404040; +CHECKREG r7, 0x80808080; + + +pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_bittgl.s b/sim/testsuite/sim/bfin/c_logi2op_bittgl.s new file mode 100644 index 0000000..ca9fe41 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_logi2op_bittgl.s @@ -0,0 +1,165 @@ +//Original:/testcases/core/c_logi2op_bittgl/c_logi2op_bittgl.dsp +// Spec Reference: Logi2op functions: bittgl +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// bit 0-7 +BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ +BITTGL( R1 , 1 ); /* r1 = 0x00000002 */ +BITTGL( R2 , 2 ); /* r2 = 0x00000004 */ +BITTGL( R3 , 3 ); /* r3 = 0x00000008 */ +BITTGL( R4 , 4 ); /* r4 = 0x00000010 */ +BITTGL( R5 , 5 ); /* r5 = 0x00000020 */ +BITTGL( R6 , 6 ); /* r6 = 0x00000040 */ +BITTGL( R7 , 7 ); /* r7 = 0x00000080 */ +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000040; +CHECKREG r7, 0x00000080; + +// bit 8-15 +BITTGL( R0 , 8 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 9 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 10 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 11 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 12 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 13 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 14 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 15 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00000101; +CHECKREG r1, 0x00000202; +CHECKREG r2, 0x00000404; +CHECKREG r3, 0x00000808; +CHECKREG r4, 0x00001010; +CHECKREG r5, 0x00002020; +CHECKREG r6, 0x00004040; +CHECKREG r7, 0x00008080; + +// bit 16-23 +BITTGL( R0 , 16 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 17 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 18 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 19 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 20 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 21 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 22 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 23 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00010101; +CHECKREG r1, 0x00020202; +CHECKREG r2, 0x00040404; +CHECKREG r3, 0x00080808; +CHECKREG r4, 0x00101010; +CHECKREG r5, 0x00202020; +CHECKREG r6, 0x00404040; +CHECKREG r7, 0x00808080; + +// bit 24-31 +BITTGL( R0 , 24 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 25 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 26 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 27 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 28 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 29 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 30 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 31 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x01010101; +CHECKREG r1, 0x02020202; +CHECKREG r2, 0x04040404; +CHECKREG r3, 0x08080808; +CHECKREG r4, 0x10101010; +CHECKREG r5, 0x20202020; +CHECKREG r6, 0x40404040; +CHECKREG r7, 0x80808080; + +// bit 0-7 +BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ +BITTGL( R1 , 1 ); /* r1 = 0x00000002 */ +BITTGL( R2 , 2 ); /* r2 = 0x00000004 */ +BITTGL( R3 , 3 ); /* r3 = 0x00000008 */ +BITTGL( R4 , 4 ); /* r4 = 0x00000010 */ +BITTGL( R5 , 5 ); /* r5 = 0x00000020 */ +BITTGL( R6 , 6 ); /* r6 = 0x00000040 */ +BITTGL( R7 , 7 ); /* r7 = 0x00000080 */ +CHECKREG r0, 0x01010100; +CHECKREG r1, 0x02020200; +CHECKREG r2, 0x04040400; +CHECKREG r3, 0x08080800; +CHECKREG r4, 0x10101000; +CHECKREG r5, 0x20202000; +CHECKREG r6, 0x40404000; +CHECKREG r7, 0x80808000; + +// bit 8-15 +BITTGL( R0 , 8 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 9 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 10 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 11 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 12 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 13 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 14 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 15 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x01010000; +CHECKREG r1, 0x02020000; +CHECKREG r2, 0x04040000; +CHECKREG r3, 0x08080000; +CHECKREG r4, 0x10100000; +CHECKREG r5, 0x20200000; +CHECKREG r6, 0x40400000; +CHECKREG r7, 0x80800000; + +// bit 16-23 +BITTGL( R0 , 16 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 17 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 18 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 19 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 20 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 21 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 22 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 23 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x01000000; +CHECKREG r1, 0x02000000; +CHECKREG r2, 0x04000000; +CHECKREG r3, 0x08000000; +CHECKREG r4, 0x10000000; +CHECKREG r5, 0x20000000; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x80000000; + +// bit 24-31 +BITTGL( R0 , 24 ); /* r0 = 0x00000100 */ +BITTGL( R1 , 25 ); /* r1 = 0x00000200 */ +BITTGL( R2 , 26 ); /* r2 = 0x00000400 */ +BITTGL( R3 , 27 ); /* r3 = 0x00000800 */ +BITTGL( R4 , 28 ); /* r4 = 0x00001000 */ +BITTGL( R5 , 29 ); /* r5 = 0x00002000 */ +BITTGL( R6 , 30 ); /* r6 = 0x00004000 */ +BITTGL( R7 , 31 ); /* r7 = 0x00008000 */ +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + + +pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_bittst.s b/sim/testsuite/sim/bfin/c_logi2op_bittst.s new file mode 100644 index 0000000..cce9df5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_logi2op_bittst.s @@ -0,0 +1,583 @@ +//Original:/testcases/core/c_logi2op_bittst/c_logi2op_bittst.dsp +// Spec Reference: Logi2op functions: bittst +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// bit(0-7) tst set clr toggle +CC = BITTST ( R0 , 0 ); /* cc = 0 */ +BITSET( R0 , 0 ); /* r0 = 0x00000001 */ +R1 = CC; +CC = BITTST ( R0 , 0 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 0 ); /* r0 = 0x00000000 */ +CC = BITTST ( R0 , 0 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ +CC = BITTST ( R0 , 0 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; + +CC = BITTST ( R1 , 1 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 1 ); /* r1 = 0x00000002 */ +CC = BITTST ( R1 , 1 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 1 ); /* r1 = 0x00000000 */ +CC = BITTST ( R1 , 1 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 1 ); /* r1 = 0x00000002 */ +CC = BITTST ( R1 , 1 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; + +CC = BITTST ( R2 , 2 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 2 ); /* r2 = 0x00000004 */ +CC = BITTST ( R2 , 2 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 2 ); /* r2 = 0x00000000 */ +CC = BITTST ( R2 , 2 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 2 ); /* r2 = 0x00000004 */ +CC = BITTST ( R2 , 2 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; + +CC = BITTST ( R3 , 3 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 3 ); /* r3 = 0x00000008 */ +CC = BITTST ( R3 , 3 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 3 ); /* r3 = 0x00000000 */ +CC = BITTST ( R3 , 3 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 3 ); /* r3 = 0x00000008 */ +CC = BITTST ( R3 , 3 ); /* cc = 1 */ +R7 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000004; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +CC = BITTST ( R4 , 4 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 4 ); /* r4 = 0x00000010 */ +CC = BITTST ( R4 , 4 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 4 ); /* r4 = 0x00000000 */ +CC = BITTST ( R4 , 4 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 4 ); /* r4 = 0x00000010 */ +CC = BITTST ( R4 , 4 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; + +CC = BITTST ( R5 , 5 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 5 ); /* r5 = 0x00000020 */ +CC = BITTST ( R5 , 5 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 5 ); /* r5 = 0x00000000 */ +CC = BITTST ( R5 , 5 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 5 ); /* r5 = 0x00000020 */ +CC = BITTST ( R5 , 5 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; + +CC = BITTST ( R6 , 6 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 6 ); /* r6 = 0x00000040 */ +CC = BITTST ( R6 , 6 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 6 ); /* r6 = 0x00000000 */ +CC = BITTST ( R6 , 6 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 6 ); /* r6 = 0x00000040 */ +CC = BITTST ( R6 , 6 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00000040; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; + +CC = BITTST ( R7 , 7 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 7 ); /* r7 = 0x00000080 */ +CC = BITTST ( R7 , 7 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 7 ); /* r7 = 0x00000000 */ +CC = BITTST ( R7 , 7 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 7 ); /* r7 = 0x00000080 */ +CC = BITTST ( R7 , 7 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; + +CHECKREG r4, 0x00000010; +CHECKREG r5, 0x00000020; +CHECKREG r6, 0x00000040; +CHECKREG r7, 0x00000080; + +// bit(8-15) tst set clr toggle +CC = BITTST ( R0 , 8 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 8 ); /* r0 = 0x00000101 */ +CC = BITTST ( R0 , 8 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 8 ); /* r0 = 0x00000000 */ +CC = BITTST ( R0 , 8 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 8 ); /* r0 = 0x00000101 */ +CC = BITTST ( R0 , 8 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00000100; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; + +CC = BITTST ( R1 , 9 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 9 ); /* r1 = 0x00000200 */ +CC = BITTST ( R1 , 9 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 9 ); /* r1 = 0x00000000 */ +CC = BITTST ( R1 , 9 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 9 ); /* r1 = 0x00000200 */ +CC = BITTST ( R1 , 9 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00000200; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; + +CC = BITTST ( R2 , 10 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 10 ); /* r2 = 0x00000400 */ +CC = BITTST ( R2 , 10 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 10 ); /* r2 = 0x00000000 */ +CC = BITTST ( R2 , 10 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 10 ); /* r2 = 0x00000400 */ +CC = BITTST ( R2 , 10 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x00000400; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; + +CC = BITTST ( R3 , 11 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 11 ); /* r3 = 0x00000800 */ +CC = BITTST ( R3 , 11 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 11 ); /* r3 = 0x00000000 */ +CC = BITTST ( R3 , 11 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 11 ); /* r3 = 0x00000800 */ +CC = BITTST ( R3 , 11 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x00000800; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +CC = BITTST ( R4 , 12 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 12 ); /* r4 = 0x00001000 */ +CC = BITTST ( R4 , 12 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 12 ); /* r4 = 0x00000000 */ +CC = BITTST ( R4 , 12 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 12 ); /* r4 = 0x00001000 */ +CC = BITTST ( R4 , 12 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; + +CC = BITTST ( R5 , 13 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 13 ); /* r5 = 0x00002000 */ +CC = BITTST ( R5 , 13 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 13 ); /* r5 = 0x00000000 */ +CC = BITTST ( R5 , 13 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 13 ); /* r5 = 0x00002000 */ +CC = BITTST ( R5 , 13 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00002000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; + +CC = BITTST ( R6 , 14 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 14 ); /* r6 = 0x00004000 */ +CC = BITTST ( R6 , 14 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 14 ); /* r6 = 0x00000000 */ +CC = BITTST ( R6 , 14 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 14 ); /* r6 = 0x00004000 */ +CC = BITTST ( R6 , 14 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00004000; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; + +CC = BITTST ( R7 , 15 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 15 ); /* r7 = 0x00008000 */ +CC = BITTST ( R7 , 15 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 15 ); /* r7 = 0x00000000 */ +CC = BITTST ( R7 , 15 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 15 ); /* r7 = 0x00008000 */ +CC = BITTST ( R7 , 15 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00001000; +CHECKREG r5, 0x00002000; +CHECKREG r6, 0x00004000; +CHECKREG r7, 0x00008000; + +// bit(16-23) tst set clr toggle +CC = BITTST ( R0 , 16 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 16 ); /* r0 = 0x00010000 */ +CC = BITTST ( R0 , 16 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 16 ); /* r0 = 0x00000000 */ +CC = BITTST ( R0 , 16 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 16 ); /* r0 = 0x00010000 */ +CC = BITTST ( R0 , 16 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; + +CC = BITTST ( R1 , 17 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 17 ); /* r1 = 0x00020000 */ +CC = BITTST ( R1 , 17 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 17 ); /* r1 = 0x00000000 */ +CC = BITTST ( R1 , 17 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 17 ); /* r1 = 0x00020000 */ +CC = BITTST ( R1 , 17 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00020000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; + +CC = BITTST ( R2 , 18 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 18 ); /* r2 = 0x00020000 */ +CC = BITTST ( R2 , 18 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 18 ); /* r2 = 0x00000000 */ +CC = BITTST ( R2 , 18 ); /* cc = 1 */ +R4 = CC; +BITTGL( R2 , 18 ); /* r2 = 0x00020000 */ +CC = BITTST ( R2 , 18 ); /* cc = 1 */ +R5 = CC; +CHECKREG r2, 0x00040000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00004000; + +CC = BITTST ( R3 , 19 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 19 ); /* r3 = 0x00080000 */ +CC = BITTST ( R3 , 19 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 19 ); /* r3 = 0x00000000 */ +CC = BITTST ( R3 , 19 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 19 ); /* r3 = 0x00080000 */ +CC = BITTST ( R3 , 19 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x00080000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +CC = BITTST ( R4 , 20 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 20 ); /* r4 = 0x00100000 */ +CC = BITTST ( R4 , 20 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 20 ); /* r4 = 0x00000000 */ +CC = BITTST ( R4 , 20 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 20 ); /* r4 = 0x00100000 */ +CC = BITTST ( R4 , 20 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00100000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; + +CC = BITTST ( R5 , 21 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 21 ); /* r5 = 0x00200000 */ +CC = BITTST ( R5 , 21 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 21 ); /* r5 = 0x00000000 */ +CC = BITTST ( R5 , 21 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 21 ); /* r5 = 0x00200000 */ +CC = BITTST ( R5 , 21 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00200000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; + +CC = BITTST ( R6 , 22 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 22 ); /* r6 = 0x00400000 */ +CC = BITTST ( R6 , 22 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 22 ); /* r6 = 0x00000000 */ +CC = BITTST ( R6 , 22 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 22 ); /* r6 = 0x00400000 */ +CC = BITTST ( R6 , 22 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00400000; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; + +CC = BITTST ( R7 , 23 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 23 ); /* r7 = 0x00800000 */ +CC = BITTST ( R7 , 23 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 23 ); /* r7 = 0x00000000 */ +CC = BITTST ( R7 , 23 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 23 ); /* r7 = 0x00800000 */ +CC = BITTST ( R7 , 23 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00100000; +CHECKREG r5, 0x00200000; +CHECKREG r6, 0x00400000; +CHECKREG r7, 0x00800000; + +// bit(24-31) tst set clr toggle +CC = BITTST ( R0 , 24 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 24 ); /* r0 = 0x00000101 */ +CC = BITTST ( R0 , 24 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 24 ); /* r0 = 0x01000000 */ +CC = BITTST ( R0 , 24 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 24 ); /* r0 = 0x01000000 */ +CC = BITTST ( R0 , 24 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x01000000; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; + +CC = BITTST ( R1 , 25 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 25 ); /* r1 = 0x02000000 */ +CC = BITTST ( R1 , 25 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 25 ); /* r1 = 0x00000000 */ +CC = BITTST ( R1 , 25 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 25 ); /* r1 = 0x02000000 */ +CC = BITTST ( R1 , 25 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x02000000; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; + +CC = BITTST ( R2 , 26 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 26 ); /* r2 = 0x04000000 */ +CC = BITTST ( R2 , 26 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 26 ); /* r2 = 0x00000000 */ +CC = BITTST ( R2 , 26 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 26 ); /* r2 = 0x04000000 */ +CC = BITTST ( R2 , 26 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x04000000; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; + +CC = BITTST ( R3 , 27 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 27 ); /* r3 = 0x08000000 */ +CC = BITTST ( R3 , 27 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 27 ); /* r3 = 0x00000000 */ +CC = BITTST ( R3 , 27 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 27 ); /* r3 = 0x08000000 */ +CC = BITTST ( R3 , 27 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x08000000; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; + +CC = BITTST ( R4 , 28 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 28 ); /* r4 = 0x10000000 */ +CC = BITTST ( R4 , 28 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 28 ); /* r4 = 0x00000000 */ +CC = BITTST ( R4 , 28 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 28 ); /* r4 = 0x10000000 */ +CC = BITTST ( R4 , 28 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x10000000; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; + +CC = BITTST ( R5 , 29 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 29 ); /* r5 = 0x20000000 */ +CC = BITTST ( R5 , 29 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 29 ); /* r5 = 0x00000000 */ +CC = BITTST ( R5 , 29 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 29 ); /* r5 = 0x20000000 */ +CC = BITTST ( R5 , 29 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x20000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; + +CC = BITTST ( R6 , 30 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 30 ); /* r6 = 0x40000000 */ +CC = BITTST ( R6 , 30 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 30 ); /* r6 = 0x00000000 */ +CC = BITTST ( R6 , 30 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 30 ); /* r6 = 0x40000000 */ +CC = BITTST ( R6 , 30 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; + +CC = BITTST ( R7 , 31 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 31 ); /* r7 = 0x80000000 */ +CC = BITTST ( R7 , 31 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 31 ); /* r7 = 0x00000000 */ +CC = BITTST ( R7 , 31 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 31 ); /* r7 = 0x80000000 */ +CC = BITTST ( R7 , 31 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x10000000; +CHECKREG r5, 0x20000000; +CHECKREG r6, 0x40000000; +CHECKREG r7, 0x80000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_log_l_shft.s b/sim/testsuite/sim/bfin/c_logi2op_log_l_shft.s new file mode 100644 index 0000000..46a457a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_logi2op_log_l_shft.s @@ -0,0 +1,222 @@ +//Original:/testcases/core/c_logi2op_log_l_shft/c_logi2op_log_l_shft.dsp +// Spec Reference: Logi2op <<= +# mach: bfin + +.include "testutils.inc" + start + + + + +// Logical <<= : negative data +// bit 0-7 +imm32 r0, 0x81111111; +imm32 r1, 0x81111111; +imm32 r2, 0x81111111; +imm32 r3, 0x81111111; +imm32 r4, 0x81111111; +imm32 r5, 0x81111111; +imm32 r6, 0x81111111; +imm32 r7, 0x81111111; +R0 <<= 0; /* r0 = 0x81111111 */ +R1 <<= 1; /* r1 = 0x40888888 */ +R2 <<= 2; /* r2 = 0x20444444 */ +R3 <<= 3; /* r3 = 0x10222222 */ +R4 <<= 4; /* r4 = 0x08111111 */ +R5 <<= 5; /* r5 = 0x04088888 */ +R6 <<= 6; /* r6 = 0x02044444 */ +R7 <<= 7; /* r7 = 0x01022222 */ +CHECKREG r0, 0x81111111; +CHECKREG r1, 0x02222222; +CHECKREG r2, 0x04444444; +CHECKREG r3, 0x08888888; +CHECKREG r4, 0x11111110; +CHECKREG r5, 0x22222220; +CHECKREG r6, 0x44444440; +CHECKREG r7, 0x88888880; + +// bit 8-15 +imm32 r0, 0x82222222; +imm32 r1, 0x82222222; +imm32 r2, 0x82222222; +imm32 r3, 0x82222222; +imm32 r4, 0x82222222; +imm32 r5, 0x82222222; +imm32 r6, 0x82222222; +imm32 r7, 0x82222222; +R0 <<= 8; +R1 <<= 9; +R2 <<= 10; +R3 <<= 11; +R4 <<= 12; +R5 <<= 13; +R6 <<= 14; +R7 <<= 15; +CHECKREG r0, 0x22222200; +CHECKREG r1, 0x44444400; +CHECKREG r2, 0x88888800; +CHECKREG r3, 0x11111000; +CHECKREG r4, 0x22222000; +CHECKREG r5, 0x44444000; +CHECKREG r6, 0x88888000; +CHECKREG r7, 0x11110000; + +// bit 16-23 +imm32 r0, 0x83333333; +imm32 r1, 0x83333333; +imm32 r2, 0x83333333; +imm32 r3, 0x83333333; +imm32 r4, 0x83333333; +imm32 r5, 0x83333333; +imm32 r6, 0x83333333; +imm32 r7, 0x83333333; +R0 <<= 16; +R1 <<= 17; +R2 <<= 18; +R3 <<= 19; +R4 <<= 20; +R5 <<= 21; +R6 <<= 22; +R7 <<= 23; +CHECKREG r0, 0x33330000; +CHECKREG r1, 0x66660000; +CHECKREG r2, 0xCCCC0000; +CHECKREG r3, 0x99980000; +CHECKREG r4, 0x33300000; +CHECKREG r5, 0x66600000; +CHECKREG r6, 0xCCC00000; +CHECKREG r7, 0x99800000; + +// bit 24-31 +imm32 r0, 0x84444444; +imm32 r1, 0x84444444; +imm32 r2, 0x84444444; +imm32 r3, 0x84444444; +imm32 r4, 0x84444444; +imm32 r5, 0x84444444; +imm32 r6, 0x84444444; +imm32 r7, 0x84444444; +R0 <<= 24; +R1 <<= 25; +R2 <<= 26; +R3 <<= 27; +R4 <<= 28; +R5 <<= 29; +R6 <<= 30; +R7 <<= 31; +CHECKREG r0, 0x44000000; +CHECKREG r1, 0x88000000; +CHECKREG r2, 0x10000000; +CHECKREG r3, 0x20000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +// Arithmetic <<= : positive data +// bit 0-7 +imm32 r0, 0x41111111; +imm32 r1, 0x41111111; +imm32 r2, 0x41111111; +imm32 r3, 0x41111111; +imm32 r4, 0x41111111; +imm32 r5, 0x41111111; +imm32 r6, 0x41111111; +imm32 r7, 0x41111111; +R0 <<= 0; +R1 <<= 1; +R2 <<= 2; +R3 <<= 3; +R4 <<= 4; +R5 <<= 5; +R6 <<= 6; +R7 <<= 7; +CHECKREG r0, 0x41111111; +CHECKREG r1, 0x82222222; +CHECKREG r2, 0x04444444; +CHECKREG r3, 0x08888888; +CHECKREG r4, 0x11111110; +CHECKREG r5, 0x22222220; +CHECKREG r6, 0x44444440; +CHECKREG r7, 0x88888880; + +// bit 8-15 +imm32 r0, 0x42222222; +imm32 r1, 0x42222222; +imm32 r2, 0x42222222; +imm32 r3, 0x42222222; +imm32 r4, 0x42222222; +imm32 r5, 0x42222222; +imm32 r6, 0x42222222; +imm32 r7, 0x42222222; +R0 <<= 8; +R1 <<= 9; +R2 <<= 10; +R3 <<= 11; +R4 <<= 12; +R5 <<= 13; +R6 <<= 14; +R7 <<= 15; +CHECKREG r0, 0x22222200; +CHECKREG r1, 0x44444400; +CHECKREG r2, 0x88888800; +CHECKREG r3, 0x11111000; +CHECKREG r4, 0x22222000; +CHECKREG r5, 0x44444000; +CHECKREG r6, 0x88888000; +CHECKREG r7, 0x11110000; + +// bit 16-23 +imm32 r0, 0x43333333; +imm32 r1, 0x43333333; +imm32 r2, 0x43333333; +imm32 r3, 0x43333333; +imm32 r4, 0x43333333; +imm32 r5, 0x43333333; +imm32 r6, 0x43333333; +imm32 r7, 0x43333333; +R0 <<= 16; +R1 <<= 17; +R2 <<= 18; +R3 <<= 19; +R4 <<= 20; +R5 <<= 21; +R6 <<= 22; +R7 <<= 23; +CHECKREG r0, 0x33330000; +CHECKREG r1, 0x66660000; +CHECKREG r2, 0xCCCC0000; +CHECKREG r3, 0x99980000; +CHECKREG r4, 0x33300000; +CHECKREG r5, 0x66600000; +CHECKREG r6, 0xCCC00000; +CHECKREG r7, 0x99800000; + +// bit 24-31 +imm32 r0, 0x44444444; +imm32 r1, 0x44444444; +imm32 r2, 0x44444444; +imm32 r3, 0x44444444; +imm32 r4, 0x44444444; +imm32 r5, 0x44444444; +imm32 r6, 0x44444444; +imm32 r7, 0x44444444; +R0 <<= 24; +R1 <<= 25; +R2 <<= 26; +R3 <<= 27; +R4 <<= 28; +R5 <<= 29; +R6 <<= 30; +R7 <<= 31; +CHECKREG r0, 0x44000000; +CHECKREG r1, 0x88000000; +CHECKREG r2, 0x10000000; +CHECKREG r3, 0x20000000; +CHECKREG r4, 0x40000000; +CHECKREG r5, 0x80000000; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + + +pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_log_l_shft_astat.S b/sim/testsuite/sim/bfin/c_logi2op_log_l_shft_astat.S new file mode 100644 index 0000000..6b3e8ca --- /dev/null +++ b/sim/testsuite/sim/bfin/c_logi2op_log_l_shft_astat.S @@ -0,0 +1,82 @@ +# Test ASTAT bits with logical left shift (<<=) +# mach: bfin + +.include "testutils.inc" +#include "test.h" +start + +.macro __do val:req, shift:req, exp:req + # First test when ASTAT starts with all bits cleared + imm32 R2, \val; + ASTAT = R0; + R2 <<= \shift; + R3 = ASTAT; + CHECKREG R2, (\val << \shift); + CHECKREG R3, \exp; + + # Then test when ASTAT starts with all bits set + imm32 R2, \val; + ASTAT = R1; + R2 <<= \shift; + R3 = ASTAT; + CHECKREG R3, (\exp) | ~(_AZ|_AN|_V|_V_COPY); +.endm + +.macro _do shift:req, val:req + # Automatically test all shifted values + .if ((\val << \shift) & 0xffffffff) == 0 + __do \val, \shift, _AZ + .else + .if (\val << \shift) == 0x80000000 + __do \val, \shift, _AN + .else + __do \val, \shift, 0 + .endif + .endif + .if (\val << 1) & 0xffffffff + _do \shift, (\val << 1) + .endif +.endm + +.macro do shift:req +_l_shft_\shift: + _do \shift, 1 +.endm + +R0 = 0; +R1 = -1; + +do 0 +do 1 +do 2 +do 3 +do 4 +do 5 +do 6 +do 7 +do 8 +do 9 +do 10 +do 11 +do 12 +do 13 +do 14 +do 15 +do 16 +do 17 +do 18 +do 19 +do 20 +do 21 +do 22 +do 23 +do 24 +do 25 +do 26 +do 27 +do 28 +do 29 +do 30 +do 31 + +pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_log_r_shft.s b/sim/testsuite/sim/bfin/c_logi2op_log_r_shft.s new file mode 100644 index 0000000..af4eb73 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_logi2op_log_r_shft.s @@ -0,0 +1,222 @@ +//Original:/testcases/core/c_logi2op_log_r_shft/c_logi2op_log_r_shft.dsp +// Spec Reference: Logi2op >>= +# mach: bfin + +.include "testutils.inc" + start + + + + +// Logical >>= : negative data +// bit 0-7 +imm32 r0, 0x81111111; +imm32 r1, 0x81111111; +imm32 r2, 0x81111111; +imm32 r3, 0x81111111; +imm32 r4, 0x81111111; +imm32 r5, 0x81111111; +imm32 r6, 0x81111111; +imm32 r7, 0x81111111; +R0 >>= 0; /* r0 = 0x81111111 */ +R1 >>= 1; /* r1 = 0x40888888 */ +R2 >>= 2; /* r2 = 0x20444444 */ +R3 >>= 3; /* r3 = 0x10222222 */ +R4 >>= 4; /* r4 = 0x08111111 */ +R5 >>= 5; /* r5 = 0x04088888 */ +R6 >>= 6; /* r6 = 0x02044444 */ +R7 >>= 7; /* r7 = 0x01022222 */ +CHECKREG r0, 0x81111111; +CHECKREG r1, 0x40888888; +CHECKREG r2, 0x20444444; +CHECKREG r3, 0x10222222; +CHECKREG r4, 0x08111111; +CHECKREG r5, 0x04088888; +CHECKREG r6, 0x02044444; +CHECKREG r7, 0x01022222; + +// bit 8-15 +imm32 r0, 0x82222222; +imm32 r1, 0x82222222; +imm32 r2, 0x82222222; +imm32 r3, 0x82222222; +imm32 r4, 0x82222222; +imm32 r5, 0x82222222; +imm32 r6, 0x82222222; +imm32 r7, 0x82222222; +R0 >>= 8; /* r0 = 0x00822222 */ +R1 >>= 9; /* r1 = 0x00411111 */ +R2 >>= 10; /* r2 = 0x00208888 */ +R3 >>= 11; /* r3 = 0x00104444 */ +R4 >>= 12; /* r4 = 0x00082222 */ +R5 >>= 13; /* r5 = 0x00041111 */ +R6 >>= 14; /* r6 = 0x00020888 */ +R7 >>= 15; /* r7 = 0x00010444 */ +CHECKREG r0, 0x00822222; +CHECKREG r1, 0x00411111; +CHECKREG r2, 0x00208888; +CHECKREG r3, 0x00104444; +CHECKREG r4, 0x00082222; +CHECKREG r5, 0x00041111; +CHECKREG r6, 0x00020888; +CHECKREG r7, 0x00010444; + +// bit 16-23 +imm32 r0, 0x83333333; +imm32 r1, 0x83333333; +imm32 r2, 0x83333333; +imm32 r3, 0x83333333; +imm32 r4, 0x83333333; +imm32 r5, 0x83333333; +imm32 r6, 0x83333333; +imm32 r7, 0x83333333; +R0 >>= 16; /* r0 = 0x00008333 */ +R1 >>= 17; /* r1 = 0x00004199 */ +R2 >>= 18; /* r2 = 0x000020CC */ +R3 >>= 19; /* r3 = 0x00001066 */ +R4 >>= 20; /* r4 = 0x00000833 */ +R5 >>= 21; /* r5 = 0x00000419 */ +R6 >>= 22; /* r6 = 0x0000020C */ +R7 >>= 23; /* r7 = 0x00000106 */ +CHECKREG r0, 0x00008333; +CHECKREG r1, 0x00004199; +CHECKREG r2, 0x000020CC; +CHECKREG r3, 0x00001066; +CHECKREG r4, 0x00000833; +CHECKREG r5, 0x00000419; +CHECKREG r6, 0x0000020C; +CHECKREG r7, 0x00000106; + +// bit 24-31 +imm32 r0, 0x84444444; +imm32 r1, 0x84444444; +imm32 r2, 0x84444444; +imm32 r3, 0x84444444; +imm32 r4, 0x84444444; +imm32 r5, 0x84444444; +imm32 r6, 0x84444444; +imm32 r7, 0x84444444; +R0 >>= 24; /* r0 = 0x00000084 */ +R1 >>= 25; /* r1 = 0x00000042 */ +R2 >>= 26; /* r2 = 0x00000021 */ +R3 >>= 27; /* r3 = 0x00000010 */ +R4 >>= 28; /* r4 = 0x00000008 */ +R5 >>= 29; /* r5 = 0x00000004 */ +R6 >>= 30; /* r6 = 0x00000002 */ +R7 >>= 31; /* r7 = 0x00000001 */ +CHECKREG r0, 0x00000084; +CHECKREG r1, 0x00000042; +CHECKREG r2, 0x00000021; +CHECKREG r3, 0x00000010; +CHECKREG r4, 0x00000008; +CHECKREG r5, 0x00000004; +CHECKREG r6, 0x00000002; +CHECKREG r7, 0x00000001; + +// Arithmetic >>= : positive data +// bit 0-7 +imm32 r0, 0x41111111; +imm32 r1, 0x41111111; +imm32 r2, 0x41111111; +imm32 r3, 0x41111111; +imm32 r4, 0x41111111; +imm32 r5, 0x41111111; +imm32 r6, 0x41111111; +imm32 r7, 0x41111111; +R0 >>= 0; /* r0 = 0x41111111 */ +R1 >>= 1; /* r1 = 0x20888888 */ +R2 >>= 2; /* r2 = 0x10444444 */ +R3 >>= 3; /* r3 = 0x08222222 */ +R4 >>= 4; /* r4 = 0x04111111 */ +R5 >>= 5; /* r5 = 0x02088888 */ +R6 >>= 6; /* r6 = 0x01044444 */ +R7 >>= 7; /* r7 = 0x00822222 */ +CHECKREG r0, 0x41111111; +CHECKREG r1, 0x20888888; +CHECKREG r2, 0x10444444; +CHECKREG r3, 0x08222222; +CHECKREG r4, 0x04111111; +CHECKREG r5, 0x02088888; +CHECKREG r6, 0x01044444; +CHECKREG r7, 0x00822222; + +// bit 8-15 +imm32 r0, 0x42222222; +imm32 r1, 0x42222222; +imm32 r2, 0x42222222; +imm32 r3, 0x42222222; +imm32 r4, 0x42222222; +imm32 r5, 0x42222222; +imm32 r6, 0x42222222; +imm32 r7, 0x42222222; +R0 >>= 8; /* r0 = 0x00422222 */ +R1 >>= 9; /* r1 = 0x00211111 */ +R2 >>= 10; /* r2 = 0x00108888 */ +R3 >>= 11; /* r3 = 0x00084444 */ +R4 >>= 12; /* r4 = 0x00042222 */ +R5 >>= 13; /* r5 = 0x00021111 */ +R6 >>= 14; /* r6 = 0x00010888 */ +R7 >>= 15; /* r7 = 0x00008444 */ +CHECKREG r0, 0x00422222; +CHECKREG r1, 0x00211111; +CHECKREG r2, 0x00108888; +CHECKREG r3, 0x00084444; +CHECKREG r4, 0x00042222; +CHECKREG r5, 0x00021111; +CHECKREG r6, 0x00010888; +CHECKREG r7, 0x00008444; + +// bit 16-23 +imm32 r0, 0x43333333; +imm32 r1, 0x43333333; +imm32 r2, 0x43333333; +imm32 r3, 0x43333333; +imm32 r4, 0x43333333; +imm32 r5, 0x43333333; +imm32 r6, 0x43333333; +imm32 r7, 0x43333333; +R0 >>= 16; /* r0 = 0x00004333 */ +R1 >>= 17; /* r1 = 0x00002199 */ +R2 >>= 18; /* r2 = 0x000010CC */ +R3 >>= 19; /* r3 = 0x00000866 */ +R4 >>= 20; /* r4 = 0x00000433 */ +R5 >>= 21; /* r5 = 0x00000219 */ +R6 >>= 22; /* r6 = 0x0000010C */ +R7 >>= 23; /* r7 = 0x00000086 */ +CHECKREG r0, 0x00004333; +CHECKREG r1, 0x00002199; +CHECKREG r2, 0x000010CC; +CHECKREG r3, 0x00000866; +CHECKREG r4, 0x00000433; +CHECKREG r5, 0x00000219; +CHECKREG r6, 0x0000010C; +CHECKREG r7, 0x00000086; + +// bit 24-31 +imm32 r0, 0x44444444; +imm32 r1, 0x44444444; +imm32 r2, 0x44444444; +imm32 r3, 0x44444444; +imm32 r4, 0x44444444; +imm32 r5, 0x44444444; +imm32 r6, 0x44444444; +imm32 r7, 0x44444444; +R0 >>= 24; /* r0 = 0x00000044 */ +R1 >>= 25; /* r1 = 0x00000022 */ +R2 >>= 26; /* r2 = 0x00000011 */ +R3 >>= 27; /* r3 = 0x00000008 */ +R4 >>= 28; /* r4 = 0x00000004 */ +R5 >>= 29; /* r5 = 0x00000002 */ +R6 >>= 30; /* r6 = 0x00000001 */ +R7 >>= 31; /* r7 = 0x00000000 */ +CHECKREG r0, 0x00000044; +CHECKREG r1, 0x00000022; +CHECKREG r2, 0x00000011; +CHECKREG r3, 0x00000008; +CHECKREG r4, 0x00000004; +CHECKREG r5, 0x00000002; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + + +pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_log_r_shft_astat.S b/sim/testsuite/sim/bfin/c_logi2op_log_r_shft_astat.S new file mode 100644 index 0000000..4f2a22b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_logi2op_log_r_shft_astat.S @@ -0,0 +1,82 @@ +# Test ASTAT bits with logical right shift (>>=) +# mach: bfin + +.include "testutils.inc" +#include "test.h" +start + +.macro __do val:req, shift:req, exp:req + # First test when ASTAT starts with all bits cleared + imm32 R2, \val; + ASTAT = R0; + R2 >>= \shift; + R3 = ASTAT; + CHECKREG R2, (\val >> \shift); + CHECKREG R3, \exp; + + # Then test when ASTAT starts with all bits set + imm32 R2, \val; + ASTAT = R1; + R2 >>= \shift; + R3 = ASTAT; + CHECKREG R3, (\exp) | ~(_AZ|_AN|_V|_V_COPY); +.endm + +.macro _do shift:req, val:req + # Automatically test all shifted values + .if ((\val >> \shift) & 0xffffffff) == 0 + __do \val, \shift, _AZ + .else + .if (\val >> \shift) == 0x80000000 + __do \val, \shift, _AN + .else + __do \val, \shift, 0 + .endif + .endif + .if (\val >> 1) & 0xffffffff + _do \shift, (\val >> 1) + .endif +.endm + +.macro do shift:req +_l_shft_\shift: + _do \shift, 0x80000000 +.endm + +R0 = 0; +R1 = -1; + +do 0 +do 1 +do 2 +do 3 +do 4 +do 5 +do 6 +do 7 +do 8 +do 9 +do 10 +do 11 +do 12 +do 13 +do 14 +do 15 +do 16 +do 17 +do 18 +do 19 +do 20 +do 21 +do 22 +do 23 +do 24 +do 25 +do 26 +do 27 +do 28 +do 29 +do 30 +do 31 + +pass diff --git a/sim/testsuite/sim/bfin/c_logi2op_nbittst.s b/sim/testsuite/sim/bfin/c_logi2op_nbittst.s new file mode 100644 index 0000000..b881c2b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_logi2op_nbittst.s @@ -0,0 +1,584 @@ +//Original:/testcases/core/c_logi2op_nbittst/c_logi2op_nbittst.dsp +// Spec Reference: Logi2op !bittst +# mach: bfin + +.include "testutils.inc" + start + + + + +imm32 r0, 0x00000000; +imm32 r1, 0x00000000; +imm32 r2, 0x00000000; +imm32 r3, 0x00000000; +imm32 r4, 0x00000000; +imm32 r5, 0x00000000; +imm32 r6, 0x00000000; +imm32 r7, 0x00000000; + +// bit(0-7) tst set clr toggle +CC = ! BITTST( R0 , 0 ); /* cc = 0 */ +BITSET( R0 , 0 ); /* r0 = 0x00000001 */ +R1 = CC; +CC = ! BITTST( R0 , 0 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 0 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R0 , 0 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 0 ); /* r0 = 0x00000001 */ +CC = ! BITTST( R0 , 0 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; + +CC = ! BITTST( R1 , 1 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 1 ); /* r0 = 0x00000002 */ +CC = ! BITTST( R1 , 1 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 1 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R1 , 1 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 1 ); /* r0 = 0x00000002 */ +CC = ! BITTST( R1 , 1 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; + +CC = ! BITTST( R2 , 2 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 2 ); /* r0 = 0x00000004 */ +CC = ! BITTST( R2 , 2 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 2 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R2 , 2 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 2 ); /* r0 = 0x00000004 */ +CC = ! BITTST( R2 , 2 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x00000005; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; + +CC = ! BITTST( R3 , 3 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 3 ); /* r0 = 0x00000008 */ +CC = ! BITTST( R3 , 3 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 3 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R3 , 3 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 3 ); /* r0 = 0x00000008 */ +CC = ! BITTST( R3 , 3 ); /* cc = 1 */ +R7 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000003; +CHECKREG r2, 0x00000005; +CHECKREG r3, 0x00000009; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +CC = ! BITTST( R4 , 4 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 4 ); /* r0 = 0x00000010 */ +CC = ! BITTST( R4 , 4 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 4 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R4 , 4 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 4 ); /* r0 = 0x00000010 */ +CC = ! BITTST( R4 , 4 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00000011; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; + +CC = ! BITTST( R5 , 5 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 5 ); /* r0 = 0x00000020 */ +CC = ! BITTST( R5 , 5 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 5 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R5 , 5 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 5 ); /* r0 = 0x00000020 */ +CC = ! BITTST( R5 , 5 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00000021; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; + +CC = ! BITTST( R6 , 6 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 6 ); /* r0 = 0x00000040 */ +CC = ! BITTST( R6 , 6 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 6 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R6 , 6 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 6 ); /* r0 = 0x00000040 */ +CC = ! BITTST( R6 , 6 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00000041; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; + +CC = ! BITTST( R7 , 7 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 7 ); /* r0 = 0x00000080 */ +CC = ! BITTST( R7 , 7 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 7 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R7 , 7 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 7 ); /* r0 = 0x00000080 */ +CC = ! BITTST( R7 , 7 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; + +CHECKREG r4, 0x00000011; +CHECKREG r5, 0x00000021; +CHECKREG r6, 0x00000041; +CHECKREG r7, 0x00000081; + +// bit(8-15) tst set clr toggle +CC = ! BITTST( R0 , 8 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 8 ); /* r0 = 0x00000101 */ +CC = ! BITTST( R0 , 8 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 8 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R0 , 8 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 8 ); /* r0 = 0x00000101 */ +CC = ! BITTST( R0 , 8 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00000101; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; + +CC = ! BITTST( R1 , 9 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 9 ); /* r0 = 0x00000202 */ +CC = ! BITTST( R1 , 9 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 9 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R1 , 9 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 9 ); /* r0 = 0x00000202 */ +CC = ! BITTST( R1 , 9 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00000201; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; + +CC = ! BITTST( R2 , 10 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 10 ); /* r0 = 0x00000404 */ +CC = ! BITTST( R2 , 10 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 10 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R2 , 10 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 10 ); /* r0 = 0x00000404 */ +CC = ! BITTST( R2 , 10 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x00000401; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; + +CC = ! BITTST( R3 , 11 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 11 ); /* r0 = 0x00000808 */ +CC = ! BITTST( R3 , 11 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 11 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R3 , 11 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 11 ); /* r0 = 0x00000808 */ +CC = ! BITTST( R3 , 11 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x00000801; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +CC = ! BITTST( R4 , 12 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 12 ); /* r0 = 0x00001010 */ +CC = ! BITTST( R4 , 12 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 12 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R4 , 12 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 12 ); /* r0 = 0x00001010 */ +CC = ! BITTST( R4 , 12 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00001001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; + +CC = ! BITTST( R5 , 13 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 13 ); /* r0 = 0x00002020 */ +CC = ! BITTST( R5 , 13 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 13 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R5 , 13 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 13 ); /* r0 = 0x00002020 */ +CC = ! BITTST( R5 , 13 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00002001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; + +CC = ! BITTST( R6 , 14 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 14 ); /* r0 = 0x00004040 */ +CC = ! BITTST( R6 , 14 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 14 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R6 , 14 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 14 ); /* r0 = 0x00004040 */ +CC = ! BITTST( R6 , 14 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00004001; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; + +CC = ! BITTST( R7 , 15 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 15 ); /* r0 = 0x00008080 */ +CC = ! BITTST( R7 , 15 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 15 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R7 , 15 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 15 ); /* r0 = 0x00008080 */ +CC = ! BITTST( R7 , 15 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00001001; +CHECKREG r5, 0x00002001; +CHECKREG r6, 0x00004001; +CHECKREG r7, 0x00008001; + +// bit(16-23) tst set clr toggle +CC = ! BITTST( R0 , 16 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 16 ); /* r0 = 0x00000001 */ +CC = ! BITTST( R0 , 16 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 16 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R0 , 16 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 16 ); /* r0 = 0x00000001 */ +CC = ! BITTST( R0 , 16 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x00010001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; + +CC = ! BITTST( R1 , 17 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 17 ); /* r0 = 0x00000002 */ +CC = ! BITTST( R1 , 17 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 17 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R1 , 17 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 17 ); /* r0 = 0x00000002 */ +CC = ! BITTST( R1 , 17 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x00020001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; + +CC = ! BITTST( R2 , 18 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 18 ); /* r0 = 0x00000004 */ +CC = ! BITTST( R2 , 18 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 18 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R2 , 18 ); /* cc = 1 */ +R4 = CC; +BITTGL( R2 , 18 ); /* r0 = 0x00000004 */ +CC = ! BITTST( R2 , 18 ); /* cc = 1 */ +R5 = CC; +CHECKREG r2, 0x00040001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00004001; + +CC = ! BITTST( R3 , 19 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 19 ); /* r0 = 0x00000008 */ +CC = ! BITTST( R3 , 19 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 19 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R3 , 19 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 19 ); /* r0 = 0x00000008 */ +CC = ! BITTST( R3 , 19 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x00080001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +CC = ! BITTST( R4 , 20 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 20 ); /* r0 = 0x00000010 */ +CC = ! BITTST( R4 , 20 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 20 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R4 , 20 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 20 ); /* r0 = 0x00000010 */ +CC = ! BITTST( R4 , 20 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x00100001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; + +CC = ! BITTST( R5 , 21 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 21 ); /* r0 = 0x00000020 */ +CC = ! BITTST( R5 , 21 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 21 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R5 , 21 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 21 ); /* r0 = 0x00000020 */ +CC = ! BITTST( R5 , 21 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x00200001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; + +CC = ! BITTST( R6 , 22 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 22 ); /* r0 = 0x00000040 */ +CC = ! BITTST( R6 , 22 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 22 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R6 , 22 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 22 ); /* r0 = 0x00000040 */ +CC = ! BITTST( R6 , 22 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x00400001; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; + +CC = ! BITTST( R7 , 23 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 23 ); /* r0 = 0x00000080 */ +CC = ! BITTST( R7 , 23 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 23 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R7 , 23 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 23 ); /* r0 = 0x00000080 */ +CC = ! BITTST( R7 , 23 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00100001; +CHECKREG r5, 0x00200001; +CHECKREG r6, 0x00400001; +CHECKREG r7, 0x00800001; + +// bit(24-31) tst set clr toggle +CC = ! BITTST( R0 , 24 ); /* cc = 0 */ +R1 = CC; +BITSET( R0 , 24 ); /* r0 = 0x00000101 */ +CC = ! BITTST( R0 , 24 ); /* cc = 1 */ +R2 = CC; +BITCLR( R0 , 24 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R0 , 24 ); /* cc = 1 */ +R3 = CC; +BITTGL( R0 , 24 ); /* r0 = 0x00000101 */ +CC = ! BITTST( R0 , 24 ); /* cc = 1 */ +R4 = CC; +CHECKREG r0, 0x01000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; + +CC = ! BITTST( R1 , 25 ); /* cc = 0 */ +R2 = CC; +BITSET( R1 , 25 ); /* r0 = 0x00000202 */ +CC = ! BITTST( R1 , 25 ); /* cc = 1 */ +R3 = CC; +BITCLR( R1 , 25 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R1 , 25 ); /* cc = 1 */ +R4 = CC; +BITTGL( R1 , 25 ); /* r0 = 0x00000202 */ +CC = ! BITTST( R1 , 25 ); /* cc = 1 */ +R5 = CC; +CHECKREG r1, 0x02000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; + +CC = ! BITTST( R2 , 26 ); /* cc = 0 */ +R3 = CC; +BITSET( R2 , 26 ); /* r0 = 0x00000404 */ +CC = ! BITTST( R2 , 26 ); /* cc = 1 */ +R4 = CC; +BITCLR( R2 , 26 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R2 , 26 ); /* cc = 1 */ +R5 = CC; +BITTGL( R2 , 26 ); /* r0 = 0x00000404 */ +CC = ! BITTST( R2 , 26 ); /* cc = 1 */ +R6 = CC; +CHECKREG r2, 0x04000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000000; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; + +CC = ! BITTST( R3 , 27 ); /* cc = 0 */ +R4 = CC; +BITSET( R3 , 27 ); /* r0 = 0x00000808 */ +CC = ! BITTST( R3 , 27 ); /* cc = 1 */ +R5 = CC; +BITCLR( R3 , 27 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R3 , 27 ); /* cc = 1 */ +R6 = CC; +BITTGL( R3 , 27 ); /* r0 = 0x00000808 */ +CC = ! BITTST( R3 , 27 ); /* cc = 1 */ +R7 = CC; +CHECKREG r3, 0x08000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; + +CC = ! BITTST( R4 , 28 ); /* cc = 0 */ +R5 = CC; +BITSET( R4 , 28 ); /* r0 = 0x00001010 */ +CC = ! BITTST( R4 , 28 ); /* cc = 1 */ +R6 = CC; +BITCLR( R4 , 28 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R4 , 28 ); /* cc = 1 */ +R7 = CC; +BITTGL( R4 , 28 ); /* r0 = 0x00001010 */ +CC = ! BITTST( R4 , 28 ); /* cc = 1 */ +R0 = CC; +CHECKREG r4, 0x10000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; + +CC = ! BITTST( R5 , 29 ); /* cc = 0 */ +R6 = CC; +BITSET( R5 , 29 ); /* r0 = 0x00002020 */ +CC = ! BITTST( R5 , 29 ); /* cc = 1 */ +R7 = CC; +BITCLR( R5 , 29 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R5 , 29 ); /* cc = 1 */ +R0 = CC; +BITTGL( R5 , 29 ); /* r0 = 0x00002020 */ +CC = ! BITTST( R5 , 29 ); /* cc = 1 */ +R1 = CC; +CHECKREG r5, 0x20000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000000; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; + +CC = ! BITTST( R6 , 30 ); /* cc = 0 */ +R7 = CC; +BITSET( R6 , 30 ); /* r0 = 0x00004040 */ +CC = ! BITTST( R6 , 30 ); /* cc = 1 */ +R0 = CC; +BITCLR( R6 , 30 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R6 , 30 ); /* cc = 1 */ +R1 = CC; +BITTGL( R6 , 30 ); /* r0 = 0x00004040 */ +CC = ! BITTST( R6 , 30 ); /* cc = 1 */ +R2 = CC; +CHECKREG r6, 0x40000001; +CHECKREG r7, 0x00000001; +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000000; + +CC = ! BITTST( R7 , 31 ); /* cc = 0 */ +R0 = CC; +BITSET( R7 , 31 ); /* r0 = 0x00008080 */ +CC = ! BITTST( R7 , 31 ); /* cc = 1 */ +R1 = CC; +BITCLR( R7 , 31 ); /* r0 = 0x00000000 */ +CC = ! BITTST( R7 , 31 ); /* cc = 1 */ +R2 = CC; +BITTGL( R7 , 31 ); /* r0 = 0x80808080 */ +CC = ! BITTST( R7 , 31 ); /* cc = 1 */ +R3 = CC; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000000; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000000; +CHECKREG r4, 0x10000001; +CHECKREG r5, 0x20000001; +CHECKREG r6, 0x40000001; +CHECKREG r7, 0x80000001; + +pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_nested.s b/sim/testsuite/sim/bfin/c_loopsetup_nested.s new file mode 100644 index 0000000..b351bc5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_loopsetup_nested.s @@ -0,0 +1,166 @@ +//Original:/testcases/core/c_loopsetup_nested/c_loopsetup_nested.dsp +// Spec Reference: loopsetup nested inside +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; +LSETUP ( start3 , end3 ) LC1 = P3; +start3: R6 += 6; +LSETUP ( start4 , end4 ) LC0 = P4 >> 1; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000017; +CHECKREG r1, 0xFFFFFFEC; +CHECKREG r2, 0x00000056; +CHECKREG r3, 0x0000004C; +CHECKREG r4, 0x00000070; +CHECKREG r5, 0x00000014; +CHECKREG r6, 0x0000007E; +CHECKREG r7, 0x0000004D; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start5 , end5 ) LC0 = P5; +start5: R4 += 1; +LSETUP ( start6 , end6 ) LC1 = SP >> 1; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +end5: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x0000005D; +CHECKREG r4, 0x00000047; +CHECKREG r5, 0x00000042; +CHECKREG r6, 0x000000D0; +CHECKREG r7, 0xFFFFFFE4; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000063; +CHECKREG r4, 0x0000006B; +CHECKREG r5, 0x00000015; +CHECKREG r6, 0x000000D0; +CHECKREG r7, 0xFFFFFFE4; + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 20; +SP = 22; +FP = 24; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1; +start11: R0 += 1; + R1 += -1; +LSETUP ( start15 , end15 ) LC0 = P5; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start13 , end13 ) LC1 = P3; +start13: R6 += 1; +LSETUP ( start12 , end12 ) LC0 = P2; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000011; +CHECKREG r1, 0x00000004; +CHECKREG r2, 0x0000002C; +CHECKREG r3, 0x0000004E; +CHECKREG r4, 0x00000210; +CHECKREG r5, 0xFFFFFE80; +CHECKREG r6, 0x00000070; +CHECKREG r7, 0x00000060; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start14 , end14 ) LC0 = P4; +start14: R0 += 1; + R1 += -1; +LSETUP ( start16 , end16 ) LC1 = SP; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +end14: R2 += 1; + R3 += 1; +CHECKREG r0, 0x00000017; +CHECKREG r1, 0xFFFFFFFE; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x00000055; +CHECKREG r4, 0x00000118; +CHECKREG r5, 0xFFFFFF78; +CHECKREG r6, 0x000001EC; +CHECKREG r7, 0xFFFFFEE4; + +pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_nested_bot.s b/sim/testsuite/sim/bfin/c_loopsetup_nested_bot.s new file mode 100644 index 0000000..118b6d2 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_loopsetup_nested_bot.s @@ -0,0 +1,165 @@ +//Original:/testcases/core/c_loopsetup_nested_bot/c_loopsetup_nested_bot.dsp +// Spec Reference: loopsetup nested same bottom +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; +ASTAT = r0; + +//p0 = 2; +P1 = 2; +P2 = 4; +P3 = 6; +P4 = 8; +P5 = 10; +SP = 12; +FP = 14; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x32; +R4 = 0x46 (X); +R5 = 0x50 (X); +R6 = 0x68 (X); +R7 = 0x72 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; +LSETUP ( start3 , end3 ) LC1 = P3; +start3: R6 += 6; +LSETUP ( start4 , end3 ) LC0 = P4 >> 1; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000010; +CHECKREG r1, 0xFFFFFFFA; +CHECKREG r2, 0x00000041; +CHECKREG r3, 0x0000005D; +CHECKREG r4, 0x00000066; +CHECKREG r5, 0x00000028; +CHECKREG r6, 0x0000008C; +CHECKREG r7, 0x00000033; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x14; +R3 = 0x18; +R4 = 0x20; +R5 = 0x12; +R6 = 0x24; +R7 = 0x16; +LSETUP ( start5 , end5 ) LC0 = P5; +start5: R4 += 1; +LSETUP ( start6 , end5 ) LC1 = SP >> 1; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +end5: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000014; +CHECKREG r3, 0x00000183; +CHECKREG r4, 0x0000002A; +CHECKREG r5, 0xFFFFFF9A; +CHECKREG r6, 0x00000114; +CHECKREG r7, 0xFFFFFEEA; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000014; +CHECKREG r3, 0x00000189; +CHECKREG r4, 0x00000062; +CHECKREG r5, 0xFFFFFF54; +CHECKREG r6, 0x00000114; +CHECKREG r7, 0xFFFFFEEA; + +P1 = 04; +P2 = 08; +P3 = 10; +P4 = 12; +P5 = 14; +SP = 16; +FP = 18; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x12; +R3 = 0x20; +R4 = 0x18; +R5 = 0x14; +R6 = 0x16; +R7 = 0x28; +LSETUP ( start11 , end11 ) LC0 = P5; +start11: R0 += 1; + R1 += -1; +LSETUP ( start15 , end15 ) LC1 = P1; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start13 , end12 ) LC0 = P2; +start13: R6 += 1; +LSETUP ( start12 , end12 ) LC1 = P3; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000013; +CHECKREG r1, 0x00000002; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000031; +CHECKREG r4, 0x0000005A; +CHECKREG r5, 0xFFFFFFD2; +CHECKREG r6, 0x00000017; +CHECKREG r7, 0x00000027; + +R0 = 0x05; +R1 = 0x08; +R2 = 0x12; +R3 = 0x24; +R4 = 0x18; +R5 = 0x20; +R6 = 0x32; +R7 = 0x46 (X); +LSETUP ( start14 , end14 ) LC0 = P4; +start14: R0 += 1; + R1 += -1; +LSETUP ( start16 , end16 ) LC1 = SP; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +LSETUP ( start17 , end14 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +end14: R2 += 1; + R3 += 1; +CHECKREG r0, 0x00000011; +CHECKREG r1, 0xFFFFFFFC; +CHECKREG r2, 0x0000007E; +CHECKREG r3, 0x0000009D; +CHECKREG r4, 0x00000084; +CHECKREG r5, 0xFFFFFFB4; +CHECKREG r6, 0x000000F2; +CHECKREG r7, 0xFFFFFF86; + +pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s b/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s new file mode 100644 index 0000000..f7de63c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s @@ -0,0 +1,184 @@ +//Original:/testcases/core/c_loopsetup_nested_prelc/c_loopsetup_nested_prelc.dsp +// Spec Reference: loopsetup nested preload lc0 lc1 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x12; +R3 = 0x14; +R4 = 0x18; +R5 = 0x16; +R6 = 0x16; +R7 = 0x18; + +LC0 = R0; +LC1 = R1; +LSETUP ( start1 , end1 ) LC0; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; +LC0 = R7; +LC1 = R6; +LSETUP ( start3 , end3 ) LC0; +start3: R6 += 6; +LSETUP ( start4 , end4 ) LC1; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000037; +CHECKREG r1, 0xFFFFFFAC; +CHECKREG r2, 0x000000A8; +CHECKREG r3, 0x0000007E; +CHECKREG r4, 0x00000068; +CHECKREG r5, 0xFFFFFFB2; +CHECKREG r6, 0x000000A6; +CHECKREG r7, 0xFFFFFF70; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x08; +R3 = 0x0C; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); + +LC0 = R2; +LC1 = R3; +LSETUP ( start5 , end5 ) LC0; +start5: R4 += 1; +LSETUP ( start6 , end6 ) LC1; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +end5: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000008; +CHECKREG r3, 0x0000003F; +CHECKREG r4, 0x00000048; +CHECKREG r5, 0x00000040; +CHECKREG r6, 0x000000AC; +CHECKREG r7, 0x00000011; +LSETUP ( start7 , end7 ) LC0; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000008; +CHECKREG r3, 0x00000045; +CHECKREG r4, 0x0000004C; +CHECKREG r5, 0x0000003B; +CHECKREG r6, 0x000000AC; +CHECKREG r7, 0x00000011; + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 12; +SP = 14; +FP = 16; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x14; +R3 = 0x18; +R4 = 0x16; +R5 = 0x04; +R6 = 0x30; +R7 = 0x30; + +LC0 = R5; +LC1 = R4; +LSETUP ( start11 , end11 ) LC0; +start11: R0 += 1; + R1 += -1; +LSETUP ( start15 , end15 ) LC1; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +end11: R2 += 1; + R3 += 1; + + +LSETUP ( start13 , end13 ) LC0 = P5; +start13: R6 += 1; +LSETUP ( start12 , end12 ) LC1 = P2; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000009; +CHECKREG r1, 0x0000000C; +CHECKREG r2, 0x00000018; +CHECKREG r3, 0x0000002A; +CHECKREG r4, 0x000000D7; +CHECKREG r5, 0xFFFFFF43; +CHECKREG r6, 0x0000003C; +CHECKREG r7, 0x00000024; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x14; +R7 = 0x08; +P4 = 6; +FP = 8; + +LC0 = R6; +LC1 = R7; +LSETUP ( start14 , end14 ) LC0 = P4; +start14: R0 += 1; + R1 += -1; +LSETUP ( start16 , end16 ) LC1; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +end14: R2 += 1; + R3 += 1; +CHECKREG r0, 0x0000000B; +CHECKREG r1, 0x0000000A; +CHECKREG r2, 0x00000026; +CHECKREG r3, 0x0000003D; +CHECKREG r4, 0x00000058; +CHECKREG r5, 0x00000038; +CHECKREG r6, 0x00000021; +CHECKREG r7, 0xFFFFFFFB; + +pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_nested_top.s b/sim/testsuite/sim/bfin/c_loopsetup_nested_top.s new file mode 100644 index 0000000..54146a3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_loopsetup_nested_top.s @@ -0,0 +1,166 @@ +//Original:/testcases/core/c_loopsetup_nested_top/c_loopsetup_nested_top.dsp +// Spec Reference: loopsetup nested top +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; +LSETUP ( start3 , end3 ) LC1 = P3; +LSETUP ( start3 , end4 ) LC0 = P4; +start3: R6 += 6; + R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000012; +CHECKREG r1, 0xFFFFFFF6; +CHECKREG r2, 0x00000047; +CHECKREG r3, 0x0000004C; +CHECKREG r4, 0x00000070; +CHECKREG r5, 0x00000014; +CHECKREG r6, 0x0000009C; +CHECKREG r7, 0x0000004D; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start5 , end5 ) LC0 = P5; +LSETUP ( start5 , end6 ) LC1 = SP >> 1; +start5: R4 += 1; + R6 += 4; +end6: R7 += -5; + R3 += 6; +end5: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x0000005D; +CHECKREG r4, 0x0000004A; +CHECKREG r5, 0x00000042; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x0000003E; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000063; +CHECKREG r4, 0x0000006E; +CHECKREG r5, 0x00000015; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x0000003E; + +P1 = 8; +P2 = 10; +P3 = 12; +P4 = 14; +P5 = 16; +SP = 18; +FP = 20; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1 >> 1; +LSETUP ( start11 , end15 ) LC0 = P5; +start11: R0 += 1; + R1 += -1; + R4 += 1; +end15: R5 += -1; + R3 += 1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start12 , end12 ) LC1 = P3 >> 1; +LSETUP ( start12 , end13 ) LC0 = P2 >> 1; +start12: R6 += 1; + R4 += 1; +end13: R5 += -1; + R3 += 1; +end12: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000018; +CHECKREG r1, 0xFFFFFFFD; +CHECKREG r2, 0x00000024; +CHECKREG r3, 0x0000003C; +CHECKREG r4, 0x0000005D; +CHECKREG r5, 0x00000033; +CHECKREG r6, 0x0000006A; +CHECKREG r7, 0x0000006A; + +R0 = 0x04; +R1 = 0x06; +R2 = 0x08; +R3 = 0x10; +R4 = 0x12; +R5 = 0x14; +R6 = 0x16; +R7 = 0x18; +LSETUP ( start14 , end14 ) LC0 = P4; +LSETUP ( start14 , end16 ) LC1 = SP >> 1; +start14: R0 += 1; + R1 += -1; + R6 += 1; +end16: R7 += -1; + R3 += 1; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +end14: R2 += 1; + R3 += 1; +CHECKREG r0, 0x0000001A; +CHECKREG r1, 0xFFFFFFF0; +CHECKREG r2, 0x00000016; +CHECKREG r3, 0x0000002D; +CHECKREG r4, 0x0000009E; +CHECKREG r5, 0xFFFFFF88; +CHECKREG r6, 0x0000002C; +CHECKREG r7, 0x00000002; + +pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_overlap.s b/sim/testsuite/sim/bfin/c_loopsetup_overlap.s new file mode 100644 index 0000000..ff3b343 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_loopsetup_overlap.s @@ -0,0 +1,167 @@ +//Original:/testcases/core/c_loopsetup_overlap/c_loopsetup_overlap.dsp +// Spec Reference: loopsetup overlap +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +LSETUP ( start2 , end2 ) LC1 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +end1: R2 += 3; + R3 += 4; + +LSETUP ( start3 , end3 ) LC1 = P3; +start3: R6 += 6; +LSETUP ( start4 , end4 ) LC0 = P4 >> 1; +start4: R0 += 1; + R1 += -2; +end3: R2 += 3; + R3 += 4; +end4: R7 += -7; + R3 += 1; +CHECKREG r0, 0x0000000F; +CHECKREG r1, 0xFFFFFFFC; +CHECKREG r2, 0x0000003E; +CHECKREG r3, 0x00000044; +CHECKREG r4, 0x00000070; +CHECKREG r5, 0x00000014; +CHECKREG r6, 0x0000007E; +CHECKREG r7, 0x0000005B; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start5 , end5 ) LC0 = P5; +start5: R4 += 1; +LSETUP ( start6 , end6 ) LC1 = SP >> 1; +start6: R6 += 4; +end5: R7 += -5; + R3 += 6; +end6: R5 += -2; + R3 += 3; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x0000004B; +CHECKREG r4, 0x00000047; +CHECKREG r5, 0x00000048; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x0000003E; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000005; +CHECKREG r1, 0x00000010; +CHECKREG r2, 0x00000020; +CHECKREG r3, 0x00000051; +CHECKREG r4, 0x0000006B; +CHECKREG r5, 0x0000001B; +CHECKREG r6, 0x00000088; +CHECKREG r7, 0x0000003E; + +P1 = 8; +P2 = 10; +P3 = 12; +P4 = 14; +P5 = 16; +SP = 18; +FP = 20; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1; +start11: R0 += 1; + R1 += -1; +LSETUP ( start15 , end15 ) LC0 = P5; +start15: R4 += 5; +end11: R5 += -14; + R3 += 1; +end15: R2 += 17; + R3 += 12; +LSETUP ( start13 , end13 ) LC1 = P3; +start13: R6 += 1; +LSETUP ( start12 , end12 ) LC0 = P2; +start12: R4 += 22; +end13: R5 += -11; + R3 += 13; +end12: R7 += -1; + R3 += 14; +CHECKREG r0, 0x0000000D; +CHECKREG r1, 0x00000008; +CHECKREG r2, 0x00000130; +CHECKREG r3, 0x000000DC; +CHECKREG r4, 0x00000281; +CHECKREG r5, 0xFFFFFE27; +CHECKREG r6, 0x0000006C; +CHECKREG r7, 0x00000066; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start14 , end14 ) LC0 = P4; +start14: R0 += 21; + R1 += -11; +LSETUP ( start16 , end16 ) LC1 = SP; +start16: R6 += 10; +end16: R7 += -12; + R3 += 1; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 31; +end14: R5 += -1; + R3 += 11; +end17: R2 += 41; + R3 += 1; +CHECKREG r0, 0x0000012B; +CHECKREG r1, 0xFFFFFF76; +CHECKREG r2, 0x000001BA; +CHECKREG r3, 0x000000AD; +CHECKREG r4, 0x00000309; +CHECKREG r5, 0x00000039; +CHECKREG r6, 0x00000A38; +CHECKREG r7, 0xFFFFF4A0; + +pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc0.s b/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc0.s new file mode 100644 index 0000000..b147659 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc0.s @@ -0,0 +1,95 @@ +//Original:/testcases/core/c_loopsetup_preg_div2_lc0/c_loopsetup_preg_div2_lc0.dsp +// Spec Reference: loopsetup preg lc0 / 2 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +P5 = 20; +P1 = 30; +P2 = 40; +P3 = 50; +P4 = 60; +//p5 = 7; +SP = 80 (X); +FP = 90 (X); + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1 >> 1; +start1: R0 += 1; + R1 += -2; +end1: R2 += 3; + R3 += 4; +LSETUP ( start2 , end2 ) LC0 = P2 >> 1; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +LSETUP ( start3 , end3 ) LC0 = P3 >> 1; +start3: R6 += 6; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000014; +CHECKREG r1, 0xFFFFFFF2; +CHECKREG r2, 0x0000004D; +CHECKREG r3, 0x00000036; +CHECKREG r4, 0x00000090; +CHECKREG r5, 0xFFFFFFEC; +CHECKREG r6, 0x000000F6; +CHECKREG r7, 0xFFFFFFC1; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start4 , end4 ) LC0 = P4 >> 1; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +LSETUP ( start5 , end5 ) LC0 = P5 >> 1; +start5: R4 += 1; +end5: R5 += -2; + R3 += 3; +LSETUP ( start6 , end6 ) LC0 = SP >> 1; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +CHECKREG r0, 0x00000023; +CHECKREG r1, 0xFFFFFFD4; +CHECKREG r2, 0x0000007A; +CHECKREG r3, 0x0000003D; +CHECKREG r4, 0x0000004A; +CHECKREG r5, 0x0000003C; +CHECKREG r6, 0x00000100; +CHECKREG r7, 0xFFFFFFA8; +LSETUP ( start7 , end7 ) LC0 = FP >> 1; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000023; +CHECKREG r1, 0xFFFFFFD4; +CHECKREG r2, 0x0000007A; +CHECKREG r3, 0x00000043; +CHECKREG r4, 0x000000FE; +CHECKREG r5, 0xFFFFFF5B; +CHECKREG r6, 0x00000100; +CHECKREG r7, 0xFFFFFFA8; + + +pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc1.s b/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc1.s new file mode 100644 index 0000000..73c7aa0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc1.s @@ -0,0 +1,94 @@ +//Original:/testcases/core/c_loopsetup_preg_div2_lc1/c_loopsetup_preg_div2_lc1.dsp +// Spec Reference: loopsetup preg lc1 / 2 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 20; +SP = 22; +FP = 24; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1 >> 1; +start11: R0 += 1; + R1 += -1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start12 , end12 ) LC1 = P2 >> 1; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +LSETUP ( start13 , end13 ) LC1 = P3 >> 1; +start13: R6 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x0000000B; +CHECKREG r1, 0x0000000A; +CHECKREG r2, 0x00000026; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x00000047; +CHECKREG r5, 0x00000049; +CHECKREG r6, 0x00000068; +CHECKREG r7, 0x00000068; + +R0 = 0x06; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start14 , end14 ) LC1 = P4 >> 1; +start14: R0 += 1; + R1 += -1; +end14: R2 += 1; + R3 += 1; +LSETUP ( start15 , end15 ) LC1 = P5 >> 1; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +LSETUP ( start16 , end16 ) LC1 = SP >> 1; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +CHECKREG r0, 0x0000000F; +CHECKREG r1, 0x00000007; +CHECKREG r2, 0x00000029; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x0000004A; +CHECKREG r5, 0x00000046; +CHECKREG r6, 0x0000006B; +CHECKREG r7, 0x00000065; +LSETUP ( start17 , end17 ) LC1 = FP >> 1; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +CHECKREG r0, 0x0000000F; +CHECKREG r1, 0x00000007; +CHECKREG r2, 0x00000029; +CHECKREG r3, 0x00000034; +CHECKREG r4, 0x00000056; +CHECKREG r5, 0x0000003A; +CHECKREG r6, 0x0000006B; +CHECKREG r7, 0x00000065; + +pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_preg_lc0.s b/sim/testsuite/sim/bfin/c_loopsetup_preg_lc0.s new file mode 100644 index 0000000..4429b1e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_loopsetup_preg_lc0.s @@ -0,0 +1,95 @@ +//Original:/testcases/core/c_loopsetup_preg_lc0/c_loopsetup_preg_lc0.dsp +// Spec Reference: loopsetup preg lc0 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start1 , end1 ) LC0 = P1; +start1: R0 += 1; + R1 += -2; +end1: R2 += 3; + R3 += 4; +LSETUP ( start2 , end2 ) LC0 = P2; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +LSETUP ( start3 , end3 ) LC0 = P3; +start3: R6 += 6; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x00000008; +CHECKREG r1, 0x0000000A; +CHECKREG r2, 0x00000029; +CHECKREG r3, 0x00000036; +CHECKREG r4, 0x00000050; +CHECKREG r5, 0x0000003C; +CHECKREG r6, 0x0000007E; +CHECKREG r7, 0x0000004D; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start4 , end4 ) LC0 = P4; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +LSETUP ( start5 , end5 ) LC0 = P5; +start5: R4 += 1; +end5: R5 += -2; + R3 += 3; +LSETUP ( start6 , end6 ) LC0 = SP; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +CHECKREG r0, 0x0000000B; +CHECKREG r1, 0x00000004; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x0000003D; +CHECKREG r4, 0x00000047; +CHECKREG r5, 0x00000042; +CHECKREG r6, 0x00000080; +CHECKREG r7, 0x00000048; +LSETUP ( start7 , end7 ) LC0 = FP; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x0000000B; +CHECKREG r1, 0x00000004; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x00000043; +CHECKREG r4, 0x0000006B; +CHECKREG r5, 0x00000015; +CHECKREG r6, 0x00000080; +CHECKREG r7, 0x00000048; + + +pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_preg_lc1.s b/sim/testsuite/sim/bfin/c_loopsetup_preg_lc1.s new file mode 100644 index 0000000..8970f40 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_loopsetup_preg_lc1.s @@ -0,0 +1,93 @@ +//Original:/testcases/core/c_loopsetup_preg_lc1/c_loopsetup_preg_lc1.dsp +// Spec Reference: loopsetup preg lc1 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 20; +SP = 22; +FP = 24; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start11 , end11 ) LC1 = P1; +start11: R0 += 1; + R1 += -1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start12 , end12 ) LC1 = P2; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +LSETUP ( start13 , end13 ) LC1 = P3; +start13: R6 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000011; +CHECKREG r1, 0x00000004; +CHECKREG r2, 0x0000002C; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x0000004E; +CHECKREG r5, 0x00000042; +CHECKREG r6, 0x00000070; +CHECKREG r7, 0x00000060; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); +LSETUP ( start14 , end14 ) LC1 = P4; +start14: R0 += 1; + R1 += -1; +end14: R2 += 1; + R3 += 1; +LSETUP ( start15 , end15 ) LC1 = P5; +start15: R4 += 1; +end15: R5 += -1; + R3 += 1; +LSETUP ( start16 , end16 ) LC1 = SP; +start16: R6 += 1; +end16: R7 += -1; + R3 += 1; +CHECKREG r0, 0x00000017; +CHECKREG r1, 0xFFFFFFFE; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x00000054; +CHECKREG r5, 0x0000003c; +CHECKREG r6, 0x00000076; +CHECKREG r7, 0x0000005A; +LSETUP ( start17 , end17 ) LC1 = FP; +start17: R4 += 1; +end17: R5 += -1; + R3 += 1; +CHECKREG r0, 0x00000017; +CHECKREG r1, 0xFFFFFFFE; +CHECKREG r2, 0x00000032; +CHECKREG r3, 0x00000034; +CHECKREG r4, 0x0000006c; +CHECKREG r5, 0x00000024; +CHECKREG r6, 0x00000076; +CHECKREG r7, 0x0000005A; + +pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_preg_stld.s b/sim/testsuite/sim/bfin/c_loopsetup_preg_stld.s new file mode 100644 index 0000000..ab549a6 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_loopsetup_preg_stld.s @@ -0,0 +1,194 @@ +//Original:/testcases/core/c_loopsetup_preg_stld/c_loopsetup_preg_stld.dsp +// Spec Reference: loopsetup preg st & ld +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + A0 = 0; + A1 = 0; + ASTAT = r0; + + P1 = 9; + P2 = 8; + P0 = 7; + P4 = 6; + P5 = 5; + FP = 3; + + imm32 r0, 0x00200005; + imm32 r1, 0x00300010; + imm32 r2, 0x00500012; + imm32 r3, 0x00600024; + imm32 r4, 0x00700016; + imm32 r5, 0x00900028; + imm32 r6, 0x0a000030; + imm32 r7, 0x00b00044; + + loadsym I0, DATA0; + loadsym I1, DATA1; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; + LSETUP ( start1 , end1 ) LC0 = P1; +start1: + R0 += 1; + R1 += 2; + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; +end1: + R2 += 3; + + R3 = ( A0 += A1 ); + + A0 = 0; + A1 = 0; + LSETUP ( start2 , end2 ) LC0 = P2; +start2: + R4 += 4; + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 -- ] || R1 = [ I1 -- ]; +end2: + R5 += -5; + R6 = ( A0 += A1 ); + CHECKREG r0, 0x000D0003; + CHECKREG r1, 0x00C00103; + CHECKREG r2, 0x0050002D; + CHECKREG r3, 0x00010794; + CHECKREG r4, 0x00700036; + CHECKREG r5, 0x00900000; + CHECKREG r6, 0x00011388; + CHECKREG r7, 0x00B00044; + + imm32 r0, 0x01200805; + imm32 r1, 0x02300710; + imm32 r2, 0x03500612; + imm32 r3, 0x04600524; + imm32 r4, 0x05700416; + imm32 r5, 0x06900328; + imm32 r6, 0x0a700230; + imm32 r7, 0x08b00044; + + loadsym I2, DATA0; + loadsym I3, DATA1; + [ I2 ++ ] = R0; + [ I3 ++ ] = R1; + LSETUP ( start3 , end3 ) LC0 = P1; +start3: + [ I2 ++ ] = R2; + [ I3 ++ ] = R3; + R2 += 1; +end3: + R3 += 1; + + A0 = 0; + A1 = 0; + LSETUP ( start4 , end4 ) LC0 = P2; + R0 = [ I0 -- ]; + R1 = [ I1 -- ]; +start4: + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I2 -- ] || R1 = [ I3 -- ]; + R4 = R4 + R0; // comp3op +end4: + R5 = R5 + R1; + + R6 = ( A0 += A1 ); + CHECKREG r0, 0x03500614; + CHECKREG r1, 0x04600526; + CHECKREG r2, 0x0350061B; + CHECKREG r3, 0x0460052D; + CHECKREG r4, 0x1CF02EC1; + CHECKREG r5, 0x25602851; + CHECKREG r6, 0x0282F220; + CHECKREG r7, 0x08B00044; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + .dd 0x000f0005 + .dd 0x00100006 + .dd 0x00200007 + .dd 0x00300008 + .dd 0x00400009 + .dd 0x0050000a + .dd 0x0060000b + .dd 0x0070000c + .dd 0x0080000d + .dd 0x0090000e + .dd 0x0100000f + .dd 0x02000010 + .dd 0x03000011 + .dd 0x04000012 + .dd 0x05000013 + .dd 0x06000014 + .dd 0x001a0000 + .dd 0x001b0001 + .dd 0x001c0002 + .dd 0x001d0003 + .dd 0x00010004 + .dd 0x00010005 + .dd 0x02100006 + .dd 0x02200007 + .dd 0x02300008 + .dd 0x02200009 + .dd 0x0250000a + .dd 0x0260000b + .dd 0x0270000c + .dd 0x0280000d + .dd 0x0290000e + .dd 0x2100000f + .dd 0x22000010 + .dd 0x22000011 + .dd 0x24000012 + .dd 0x25000013 + .dd 0x26000014 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 + .dd 0x00b00104 + .dd 0x00a00105 + .dd 0x00900106 + .dd 0x00800107 + .dd 0x00100108 + .dd 0x00200109 + .dd 0x0030010a + .dd 0x0040010b + .dd 0x0050011c + .dd 0x0060010d + .dd 0x0070010e + .dd 0x0080010f + .dd 0x00900110 + .dd 0x01000111 + .dd 0x02000112 + .dd 0x03000113 + .dd 0x04000114 + .dd 0x05000115 + .dd 0x03f00100 + .dd 0x03e00101 + .dd 0x03d00102 + .dd 0x03c00103 + .dd 0x03b00104 + .dd 0x03a00105 + .dd 0x03900106 + .dd 0x03800107 + .dd 0x03100108 + .dd 0x03200109 + .dd 0x0330010a + .dd 0x0330010b + .dd 0x0350011c + .dd 0x0360010d + .dd 0x0370010e + .dd 0x0380010f + .dd 0x03900110 + .dd 0x31000111 + .dd 0x32000112 + .dd 0x33000113 + .dd 0x34000114 diff --git a/sim/testsuite/sim/bfin/c_loopsetup_prelc.s b/sim/testsuite/sim/bfin/c_loopsetup_prelc.s new file mode 100644 index 0000000..527988a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_loopsetup_prelc.s @@ -0,0 +1,145 @@ +//Original:/testcases/core/c_loopsetup_prelc/c_loopsetup_prelc.dsp +// Spec Reference: loopsetup preload lc0 lc1 +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +//p0 = 2; +P1 = 3; +P2 = 4; +P3 = 5; +P4 = 6; +P5 = 7; +SP = 8; +FP = 9; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); + +LC0 = R0; +LC1 = R1; + +LSETUP ( start1 , end1 ) LC0; +start1: R0 += 1; + R1 += -2; +end1: R2 += 3; + R3 += 4; +LSETUP ( start2 , end2 ) LC1; +start2: R4 += 4; +end2: R5 += -5; + R3 += 1; +LSETUP ( start3 , end3 ) LC0 = P3; +start3: R6 += 6; +end3: R7 += -7; + R3 += 1; +CHECKREG r0, 0x0000000a; +CHECKREG r1, 0x00000006; +CHECKREG r2, 0x0000002f; +CHECKREG r3, 0x00000036; +CHECKREG r4, 0x00000080; +CHECKREG r5, 0x00000000; +CHECKREG r6, 0x0000007E; +CHECKREG r7, 0x0000004D; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x60 (X); +R7 = 0x70 (X); + +LC0 = R2; +LC1 = R3; + +LSETUP ( start4 , end4 ) LC0; +start4: R0 += 1; + R1 += -2; +end4: R2 += 3; + R3 += 4; +LSETUP ( start5 , end5 ) LC1; +start5: R4 += 1; +end5: R5 += -2; + R3 += 3; + +LSETUP ( start6 , end6 ) LC0 = P2; +start6: R6 += 4; +end6: R7 += -5; + R3 += 6; +CHECKREG r0, 0x00000025; +CHECKREG r1, 0xFFFFFFD0; +CHECKREG r2, 0x00000080; +CHECKREG r3, 0x0000003D; +CHECKREG r4, 0x00000070; +CHECKREG r5, 0xFFFFFFF0; +CHECKREG r6, 0x00000070; +CHECKREG r7, 0x0000005C; +LSETUP ( start7 , end7 ) LC1; +start7: R4 += 4; +end7: R5 += -5; + R3 += 6; +CHECKREG r0, 0x00000025; +CHECKREG r1, 0xFFFFFFD0; +CHECKREG r2, 0x00000080; +CHECKREG r3, 0x00000043; +CHECKREG r4, 0x00000074; +CHECKREG r5, 0xFFFFFFEB; +CHECKREG r6, 0x00000070; +CHECKREG r7, 0x0000005C; + +P1 = 12; +P2 = 14; +P3 = 16; +P4 = 18; +P5 = 20; +SP = 22; +FP = 24; + +R0 = 0x05; +R1 = 0x10; +R2 = 0x20; +R3 = 0x30; +R4 = 0x40 (X); +R5 = 0x50 (X); +R6 = 0x25; +R7 = 0x32; + +LC0 = R6; +LC1 = R7; +LSETUP ( start11 , end11 ) LC0; +start11: R0 += 1; + R1 += -1; +end11: R2 += 1; + R3 += 1; +LSETUP ( start12 , end12 ) LC1; +start12: R4 += 1; +end12: R5 += -1; + R3 += 1; +LSETUP ( start13 , end13 ) LC1 = P4; +start13: R6 += 1; +end13: R7 += -1; + R3 += 1; +CHECKREG r0, 0x0000002A; +CHECKREG r1, 0xFFFFFFEB; +CHECKREG r2, 0x00000045; +CHECKREG r3, 0x00000033; +CHECKREG r4, 0x00000072; +CHECKREG r5, 0x0000001E; +CHECKREG r6, 0x00000037; +CHECKREG r7, 0x00000020; + + +pass diff --git a/sim/testsuite/sim/bfin/c_loopsetup_topbotcntr.s b/sim/testsuite/sim/bfin/c_loopsetup_topbotcntr.s new file mode 100644 index 0000000..dc19b7d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_loopsetup_topbotcntr.s @@ -0,0 +1,110 @@ +//Original:/proj/frio/dv/testcases/core/c_loopsetup_topbotcntr/c_loopsetup_topbotcntr.dsp +// Spec Reference: loopsetup top bot counter +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + + ASTAT = r0; + + R1 = 0x10; + R2 = 0x20; + R3 = 0x30; + R4 = 0x40 (X); + R5 = 0x08; + + loadsym R6, start1; + loadsym R7, end1; + + LT0 = R6; + LB0 = R7; + LC0 = R5; +//start immmediately +start1: R0 += 1; + R1 += -2; +end1: R2 += 3; + R3 += 4; + + CHECKREG r0, 0x00000008; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000038; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000040; + CHECKREG r5, 0x00000008; +//CHECKREG r6, 0x00000090; +//CHECKREG r7, 0x00000094; + + R0 = 0x05; + R1 = 0x10; + R2 = 0x10; + R3 = 0x10; + R4 = 0x20; + R5 = 0x20; + R6 = 0x30; + R7 = 0x30; + + loadsym R1, start2; + R0 = R1; + loadsym R1, end2; + LT1 = R0; + LB1 = R1; + LC1 = R2; + +start2: R4 += 1; + R5 += 2; +end2: R6 += -3; + R7 += 4; + CHECKREG r3, 0x00000010; + CHECKREG r4, 0x00000030; + CHECKREG r5, 0x00000040; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000034; + + R0 = 0x05; + R1 = 0x10; + R2 = 0x20; + R3 = 0x30; + R4 = 0x40 (X); + R5 = 0x50 (X); + R6 = 0x60 (X); + R7 = 0x70 (X); + + loadsym R1, start3 + r0 = r1; + loadsym r1, end3; + LT0 = R0; + LB0 = R1; + LC0 = R2; + loadsym r3, start4; + loadsym r4, end4; + LT1 = R3; + LB1 = R4; + LC1 = R5; + + R0 = 0x10; + R1 = 0x15; + R2 = 0x20; + R3 = 0x26; + R4 = 0x30; + R5 = 0x40 (X); + +start3: R0 += 1; + R1 += -2; +start4: R2 += 3; + R3 += 4; +end4: R6 += 5; +end3: R7 += -6; + + CHECKREG r0, 0x00000030; + CHECKREG r1, 0xFFFFFFD5; + CHECKREG r2, 0x0000016D; + CHECKREG r3, 0x000001E2; + CHECKREG r4, 0x00000030; + CHECKREG r5, 0x00000040; + CHECKREG r6, 0x0000028B; + CHECKREG r7, 0xFFFFFFB0; + + pass diff --git a/sim/testsuite/sim/bfin/c_mmr_interr_ctl.s b/sim/testsuite/sim/bfin/c_mmr_interr_ctl.s new file mode 100644 index 0000000..ad4d88b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_mmr_interr_ctl.s @@ -0,0 +1,398 @@ +# Blackfin testcase for the CEC +# mach: bfin +# sim: --environment operating + + .include "testutils.inc" + + start + + INIT_R_REGS 0; + INIT_P_REGS 0; + INIT_I_REGS 0; + INIT_M_REGS 0; + INIT_L_REGS 0; + INIT_B_REGS 0; + + CLI R1; // inhibit events during MMR writes + + loadsym sp, USTACK; // setup the user stack pointer + usp = sp; // and frame pointer + + loadsym sp, KSTACK; // setup the stack pointer + fp = sp; // and frame pointer + + imm32 p0, 0xFFE02000; + loadsym r0, EHANDLE; // Emulation Handler (Int0) + [p0++] = r0; + + loadsym r0, RHANDLE; // Reset Handler (Int1) + [p0++] = r0; + + loadsym r0, NHANDLE; // NMI Handler (Int2) + [p0++] = r0; + + loadsym r0, XHANDLE; // Exception Handler (Int3) + [p0++] = r0; + + [p0++] = r0; // EVT4 not used global Interr Enable (INT4) + + loadsym r0, HWHANDLE; // HW Error Handler (Int5) + [p0++] = r0; + + loadsym r0, THANDLE; // Timer Handler (Int6) + [p0++] = r0; + + loadsym r0, I7HANDLE; // IVG7 Handler + [p0++] = r0; + + loadsym r0, I8HANDLE; // IVG8 Handler + [p0++] = r0; + + loadsym r0, I9HANDLE; // IVG9 Handler + [p0++] = r0; + + loadsym r0, I10HANDLE;// IVG10 Handler + [p0++] = r0; + + loadsym r0, I11HANDLE;// IVG11 Handler + [p0++] = r0; + + loadsym r0, I12HANDLE;// IVG12 Handler + [p0++] = r0; + + loadsym r0, I13HANDLE;// IVG13 Handler + [p0++] = r0; + + loadsym r0, I14HANDLE;// IVG14 Handler + [p0++] = r0; + + loadsym r0, I15HANDLE;// IVG15 Handler + [p0++] = r0; + + imm32 p0, 0xFFE02100 // EVT_OVERRIDE + r0 = 0; + [p0++] = r0; + + r1 = -1; // Change this to mask interrupts (*) + csync; // wait for MMR writes to finish + sti r1; // sync and reenable events (implicit write to IMASK) + + imm32 p0, 0xFFE02104; + r0 = [p0]; + // ckeck that sti allows the lower 5 bits of imask to be written + CHECKREG r0, 0xffff; + +DUMMY: + + r0 = 0 (z); + + LT0 = r0; // set loop counters to something deterministic + LB0 = r0; + LC0 = r0; + LT1 = r0; + LB1 = r0; + LC1 = r0; + + ASTAT = r0; // reset other internal regs + SYSCFG = r0; + RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + + loadsym r0, STARTUSER;// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) + RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + + JUMP STARTSUP; // jump to code start for SUPERVISOR mode + + RTI; + +STARTSUP: + loadsym p1, BEGIN; + + imm32 p0, (0xFFE02000 + 4 * 15); + + CLI R1; // inhibit events during write to MMR + [p0] = p1; // IVG15 (General) handler (Int 15) load with start + csync; // wait for it + sti r1; // reenable events with proper imask + + RAISE 15; // after we RTI, INT 15 should be taken + + RTI; + +// +// The Main Program +// +STARTUSER: + LINK 0; // change for how much stack frame space you need. + + JUMP BEGIN; + +// ********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [--sp] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** +// EVTx + // wrt-rd EVT0: 0 bits, rw=0 = 0xFFE02000 + imm32 p0, 0xFFE02000; + imm32 r0, 0x00000000 + [p0] = r0; + + // wrt-rd EVT1: 32 bits, rw=0 = 0xFFE02004 + imm32 p0, 0xFFE02004; + imm32 r0, 0x00000000 + [p0] = r0; + + // wrt-rd EVT2 = 0xFFE02008 + imm32 p0, 0xFFE02008 + imm32 r0, 0xE1DE5D1C + [p0] = r0; + + // wrt-rd EVT3 = 0xFFE0200C + imm32 p0, 0xFFE0200C + imm32 r0, 0x9CC20332 + [p0] = r0; + + // wrt-rd EVT4 = 0xFFE02010 + imm32 p0, 0xFFE02010 + imm32 r0, 0x00000000 + [p0] = r0; + + // wrt-rd EVT5 = 0xFFE02014 + imm32 p0, 0xFFE02014 + imm32 r0, 0x55552345 + [p0] = r0; + + // wrt-rd EVT6 = 0xFFE02018 + imm32 p0, 0xFFE02018 + imm32 r0, 0x66663456 + [p0] = r0; + + // wrt-rd EVT7 = 0xFFE0201C + imm32 p0, 0xFFE0201C + imm32 r0, 0x77774567 + [p0] = r0; + + // wrt-rd EVT8 = 0xFFE02020 + imm32 p0, 0xFFE02020 + imm32 r0, 0x88885678 + [p0] = r0; + + // wrt-rd EVT9 = 0xFFE02024 + imm32 p0, 0xFFE02024 + imm32 r0, 0x99996789 + [p0] = r0; + + // wrt-rd EVT10 = 0xFFE02028 + imm32 p0, 0xFFE02028 + imm32 r0, 0xaaaa1234 + [p0] = r0; + + // wrt-rd EVT11 = 0xFFE0202C + imm32 p0, 0xFFE0202C + imm32 r0, 0xBBBBABC6 + [p0] = r0; + + // wrt-rd EVT12 = 0xFFE02030 + imm32 p0, 0xFFE02030 + imm32 r0, 0xCCCCABC6 + [p0] = r0; + + // wrt-rd EVT13 = 0xFFE02034 + imm32 p0, 0xFFE02034 + imm32 r0, 0xDDDDABC6 + [p0] = r0; + + // wrt-rd EVT14 = 0xFFE02038 + imm32 p0, 0xFFE02038 + imm32 r0, 0xEEEEABC6 + [p0] = r0; + + // wrt-rd EVT15 = 0xFFE0203C + imm32 p0, 0xFFE0203C + imm32 r0, 0xFFFFABC6 + [p0] = r0; + + // wrt-rd EVT_OVERRIDE:9 bits = 0xFFE02100 + imm32 p0, 0xFFE02100 + imm32 r0, 0x000001ff + [p0] = r0; + + // wrt-rd IMASK: 16 bits = 0xFFE02104 + imm32 p0, 0xFFE02104 + imm32 r0, 0x00000fff + [p0] = r0; + + // wrt-rd IPEND: 16 bits, rw=0 = 0xFFE02108 + imm32 p0, 0xFFE02108 + imm32 r0, 0x00000000 + //[p0] = r0; + raise 12; + raise 13; + + // wrt-rd ILAT: 16 bits, rw=0 = 0xFFE0210C + imm32 p0, 0xFFE0210C + imm32 r0, 0x00000000 + //[p0] = r0; + csync; + + // *** read ops + imm32 p0, 0xFFE02000 + r0 = [p0]; + CHECKREG r0, 0; + + imm32 p0, 0xFFE02004 + r1 = [p0]; + CHECKREG r1, 0; + + imm32 p0, 0xFFE02008 + r2 = [p0]; + CHECKREG r2, 0xE1DE5D1C; + + imm32 p0, 0xFFE0200C + r3 = [p0]; + CHECKREG r3, 0x9CC20332; + + imm32 p0, 0xFFE02014 + r4 = [p0]; + imm32 p0, 0xFFE02018 + r5 = [p0]; + imm32 p0, 0xFFE0201C + r6 = [p0]; + imm32 p0, 0xFFE02020 /* EVT8 */ + r7 = [p0]; +CHECKREG r0, 0x00000000; +//CHECKREG(r1, 0x00000000); /// mismatch = 00 +CHECKREG r2, 0xE1DE5D1C; +CHECKREG r3, 0x9CC20332; +CHECKREG r4, 0x55552345; +CHECKREG r5, 0x66663456; +CHECKREG r6, 0x77774567; +CHECKREG r7, 0x88885678; + + imm32 p0, 0xFFE02024 /* EVT9 */ + r0 = [p0]; + imm32 p0, 0xFFE02028 /* EVT10 */ + r1 = [p0]; + imm32 p0, 0xFFE0202C /* EVT11 */ + r2 = [p0]; + imm32 p0, 0xFFE02030 /* EVT12 */ + r3 = [p0]; + imm32 p0, 0xFFE02034 /* EVT13 */ + r4 = [p0]; + imm32 p0, 0xFFE02038 /* EVT14 */ + r5 = [p0]; + imm32 p0, 0xFFE0203C /* EVT15 */ + r6 = [p0]; +CHECKREG r0, 0x99996789; +CHECKREG r1, 0xaaaa1234; +CHECKREG r2, 0xBBBBABC6; +CHECKREG r3, 0xCCCCABC6; +CHECKREG r4, 0xDDDDABC6; +CHECKREG r5, 0xEEEEABC6; +CHECKREG r6, 0xFFFFABC6; + + imm32 p0, 0xFFE02100 /* EVT_OVERRIDE */ + r0 = [p0]; + imm32 p0, 0xFFE02104 /* IMASK */ + r1 = [p0]; + imm32 p0, 0xFFE02108 /* IPEND */ + r2 = [p0]; + imm32 p0, 0xFFE0210C /* ILAT */ + r3 = [p0]; +CHECKREG r0, 0x000001ff; +CHECKREG r1, 0x00000fff; /* XXX: original had 0xfe0 ?? */ +CHECKREG r2, 0x00008000; +CHECKREG r3, 0x00003000; + + dbg_pass; + +// ********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 + RTE; + +RHANDLE: // Reset Handler 1 + RTI; + +NHANDLE: // NMI Handler 2 + r0 = 2; + RTN; + +XHANDLE: // Exception Handler 3 + + RTX; + +HWHANDLE: // HW Error Handler 5 + r2 = 5; + RTI; + +THANDLE: // Timer Handler 6 + r3 = 6; + RTI; + +I7HANDLE: // IVG 7 Handler + r4 = 7; + RTI; + +I8HANDLE: // IVG 8 Handler + r5 = 8; + RTI; + +I9HANDLE: // IVG 9 Handler + r6 = 9; + RTI; + +I10HANDLE: // IVG 10 Handler + r7 = 10; + RTI; + +I11HANDLE: // IVG 11 Handler + r0 = 11; + RTI; + +I12HANDLE: // IVG 12 Handler + r1 = 12; + RTI; + +I13HANDLE: // IVG 13 Handler + r2 = 13; + RTI; + +I14HANDLE: // IVG 14 Handler + r3 = 14; + RTI; + +I15HANDLE: // IVG 15 Handler + r4 = 15; + RTI; + + nop;nop;nop;nop;nop;nop;nop; // needed for icache bug + +// +// Data Segment +// + +.data +// Stack Segments (Both Kernel and User) + +.rep 0x10 +.byte 0 +.endr +KSTACK: + +.rep 0x10 +.byte 0 +.endr +USTACK: diff --git a/sim/testsuite/sim/bfin/c_mmr_loop.S b/sim/testsuite/sim/bfin/c_mmr_loop.S new file mode 100644 index 0000000..b0fa404 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_mmr_loop.S @@ -0,0 +1,417 @@ +//Original:/proj/frio/dv/testcases/core/c_mmr_loop/c_mmr_loop.dsp +// Spec Reference: mmr loop (interr control) no exception +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we set the processor operating modes, initialize registers +// etc.) +// + +BOOT: + +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + //CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; // and frame pointer + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// +STARTUSER: +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + + + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** +// EVTx + // wrt-rd EVT0: 0 bits, rw=0 = 0xFFE02000 +LD32(p0, 0xFFE02000); +LD32(r0, 0x00000000); + [ P0 ] = R0; + + // wrt-rd EVT1: 32 bits, rw=0 = 0xFFE02004 +LD32(p0, 0xFFE02004); +LD32(r0, 0x00000000); + [ P0 ] = R0; + + // wrt-rd EVT2 = 0xFFE02008 +LD32(p0, 0xFFE02008); +LD32(r0, 0xE1DE5D1C); + [ P0 ] = R0; + + // wrt-rd EVT3 = 0xFFE0200C +LD32(p0, 0xFFE0200C); +LD32(r0, 0x9CC20332); + [ P0 ] = R0; + + // wrt-rd EVT4 = 0xFFE02010 +LD32(p0, 0xFFE02010); +LD32(r0, 0x00000000); // not implemented + [ P0 ] = R0; + + // wrt-rd EVT5 = 0xFFE02014 +LD32(p0, 0xFFE02014); +LD32(r0, 0x55552345); + [ P0 ] = R0; + + // wrt-rd EVT6 = 0xFFE02018 +LD32(p0, 0xFFE02018); +LD32(r0, 0x66663456); + [ P0 ] = R0; + + // wrt-rd EVT7 = 0xFFE0201C +LD32(p0, 0xFFE0201C); +LD32(r0, 0x77774567); + [ P0 ] = R0; + + // wrt-rd EVT8 = 0xFFE02020 +LD32(p0, 0xFFE02020); +LD32(r0, 0x88885678); + [ P0 ] = R0; + + // wrt-rd EVT9 = 0xFFE02024 +LD32(p0, 0xFFE02024); +LD32(r0, 0x99996789); + [ P0 ] = R0; + + // wrt-rd EVT10 = 0xFFE02028 +LD32(p0, 0xFFE02028); +LD32(r0, 0xaaaa1234); + [ P0 ] = R0; + + // wrt-rd EVT11 = 0xFFE0202C +LD32(p0, 0xFFE0202C); +LD32(r0, 0xBBBBABC6); + [ P0 ] = R0; + + // wrt-rd EVT12 = 0xFFE02030 +LD32(p0, 0xFFE02030); +LD32(r0, 0xCCCCABC6); + [ P0 ] = R0; + + // wrt-rd EVT13 = 0xFFE02034 +LD32(p0, 0xFFE02034); +LD32(r0, 0xDDDDABC6); + [ P0 ] = R0; + + // wrt-rd EVT14 = 0xFFE02038 +LD32(p0, 0xFFE02038); +LD32(r0, 0xEEEEABC6); + [ P0 ] = R0; + + // wrt-rd EVT15 = 0xFFE0203C +LD32(p0, 0xFFE0203C); +LD32(r0, 0xFFFFABC6); + [ P0 ] = R0; + + // wrt-rd EVT_OVERRIDE:9 bits = 0xFFE02100 +LD32(p0, 0xFFE02100); +LD32(r0, 0x000001ff); + [ P0 ] = R0; + + // wrt-rd IMASK: 16 bits = 0xFFE02104 +LD32(p0, 0xFFE02104); +LD32(r0, 0x00000fe0); + [ P0 ] = R0; + + + // wrt-rd IPEND: 16 bits, rw=0 = 0xFFE02108 +LD32(p0, 0xFFE02108); +LD32(r0, 0x00000000); + //[p0] = r0; +RAISE 12; +RAISE 13; + + // wrt-rd ILAT: 16 bits, rw=0 = 0xFFE0210C +LD32(p0, 0xFFE0210C); +LD32(r0, 0x00000000); + //[p0] = r0; +CSYNC; +//*** read ops +P1.L = DATA0; +P1.H = DATA0; + +LD32(p0, 0xFFE02000); + P2 = 16; +LSETUP ( start1 , end1 ) LC0 = P2; +start1: + R0 = [ P0 ++ ]; +end1: [ P1 ++ ] = R0; +//nop; +P1.L = DATA0; +P1.H = DATA0; + R0 = [ P1 ++ ]; + R1 = [ P1 ++ ]; + R2 = [ P1 ++ ]; + R3 = [ P1 ++ ]; + R4 = [ P1 ++ ]; + R5 = [ P1 ++ ]; + R6 = [ P1 ++ ]; + R7 = [ P1 ++ ]; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0xE1DE5D1C); +CHECKREG(r3, 0x9CC20332); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x55552345); +CHECKREG(r6, 0x66663456); +CHECKREG(r7, 0x77774567); + R0 = [ P1 ++ ]; + R1 = [ P1 ++ ]; + R2 = [ P1 ++ ]; + R3 = [ P1 ++ ]; + R4 = [ P1 ++ ]; + R5 = [ P1 ++ ]; + R6 = [ P1 ++ ]; + R7 = [ P1 ++ ]; +CHECKREG(r0, 0x88885678); +CHECKREG(r1, 0x99996789); +CHECKREG(r2, 0xAAAA1234); +CHECKREG(r3, 0xBBBBABC6); +CHECKREG(r4, 0xCCCCABC6); +CHECKREG(r5, 0xDDDDABC6); +CHECKREG(r6, 0xEEEEABC6); +CHECKREG(r7, 0xFFFFABC6); + +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + R7 = 0x00006789 (X); +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA0: +.dd 0x000a0000 +.dd 0x000b0001 +.dd 0x000c0002 +.dd 0x000d0003 +.dd 0x000e0004 +.dd 0x000f0005 +.dd 0x00100006 +.dd 0x00200007 +.dd 0x00300008 +.dd 0x00400009 +.dd 0x0050000a +.dd 0x0060000b +.dd 0x0070000c +.dd 0x0080000d +.dd 0x0090000e +.dd 0x0100000f +.dd 0x02000010 +.dd 0x03000011 +.dd 0x04000012 +.dd 0x05000013 +.dd 0x06000014 +.dd 0x001a0000 +.dd 0x001b0001 +.dd 0x001c0002 +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_mmr_loop_user_except.S b/sim/testsuite/sim/bfin/c_mmr_loop_user_except.S new file mode 100644 index 0000000..7e0bc40 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_mmr_loop_user_except.S @@ -0,0 +1,325 @@ +//Original:/proj/frio/dv/testcases/core/c_mmr_loop_user_except/c_mmr_loop_user_except.dsp +// Spec Reference: c_mmr_loop_user_except +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we set the processor operating modes, initialize registers +// etc.) +// + +BOOT: + +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + //CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + + + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; // and frame pointer + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) + + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +// LD32_LABEL(r0, I13HANDLE);// IVG13 Handler +// [p0++] = r0; + +// LD32_LABEL(r0, I14HANDLE);// IVG14 Handler +// [p0++] = r0; + +//***************** + // wrt-rd EVT13 = 0xFFE02034 +LD32(p0, 0xFFE02034); +LD32(r0, 0xDDDDABC6); + [ P0 ] = R0; + + // wrt-rd EVT14 = 0xFFE02038 +LD32(p0, 0xFFE02038); +LD32(r0, 0xEEEEABC6); + [ P0 ] = R0; +//***************** +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; // execute this instr put us in USER mode + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // USER MODE & go to different RAISE in USER mode + // until the end of the test. + +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +// LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +// RAISE 2; // RTN // exception because we execute this in USER mode + R0 = 0; +LD32(p0, 0xFFE02034); + P2 = 2; +LSETUP ( start1 , end1 ) LC0 = P2; +start1: + R0 = [ P0 ++ ]; // 16 bit instr +end1: R1 = R0; + +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +//CHECKREG(r3, 0x00000030); +CHECKREG(r4, 0x0000000F); +CHECKREG(r5, 0x00000012); +CHECKREG(r6, 0x00000015); +CHECKREG(r7, 0x00000018); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = RETN; + R0 += 2; +RETN = r0; +RTN; + +XHANDLE: // Exception Handler 3 + R3 = RETX; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; + R3 += 2; // for resturn address +RETX = r3; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = RETI; + R2 += 2; +RETI = r2; +RTI; + +THANDLE: // Timer Handler 6 + R3 = RETI; + R3 += 2; +RETI = r3; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = RETI; + R4 += 2; +RETI = r4; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = RETI; + R5 += 2; +RETI = r5; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = RETI; + R6 += 2; +RETI = r6; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = RETI; + R7 += 2; +RETI = r7; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = RETI; + R0 += 2; +RETI = r0; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = RETI; + R1 += 2; +RETI = r1; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = RETI; + R2 += 2; +RETI = r2; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = RETI; + R3 += 2; +RETI = r3; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: +// .space (STACKSIZE); // adding this may solve the problem diff --git a/sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S b/sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S new file mode 100644 index 0000000..82bb45d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_mmr_ppop_illegal_adr.S @@ -0,0 +1,307 @@ +//Original:/proj/frio/dv/testcases/core/c_mmr_ppop_illegal_adr/c_mmr_ppop_illegal_adr.dsp +// Spec Reference: mmr ppop illegal address +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we set the processor operating modes, initialize registers +// etc.) +// + +BOOT: + +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + //CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; // and frame pointer + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// +STARTUSER: +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + + + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + +LD32(r0, 0206037020); +LD32(r1, 0x10070030); +LD32(r2, 0xe2000043); +LD32(r3, 0x30305050); +LD32(r4, 0x0f040860); +LD32(r5, 0x0a0050d0); +LD32(r6, 0x00000000); +LD32(r7, 0x0f060071); +// LD32(sp, 0xFFE02104); +// [--sp] = (r7-r6); + [ -- SP ] = R7; + [ -- SP ] = R6; +.dd 0xffff + R1 += 2; + +CHECKREG(r1, 0x10070034); +CHECKREG(r2, 0xE2000046); +CHECKREG(r3, 0x30305054); +CHECKREG(r4, 0x0f040865); +CHECKREG(r5, 0x0a0050d6); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x0f060079); + R7 = [ SP ++ ]; +CHECKREG(r7, 0x00000000); + +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 +R0 = RETX; // error handler:RETX has the address of the same Illegal instr + R1 += 2; + R2 += 3; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; +R0 += 2; // we have to add 2 to point to next instr after return (16-bit illegal instr) +RETX = R0; +NOP; NOP; NOP; NOP; + + +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA0: +.dd 0x000a0000 +.dd 0x000b0001 +.dd 0x000c0002 +.dd 0x000d0003 +.dd 0x000e0004 +.dd 0x000f0005 +.dd 0x00100006 +.dd 0x00200007 +.dd 0x00300008 +.dd 0x00400009 +.dd 0x0050000a +.dd 0x0060000b +.dd 0x0070000c +.dd 0x0080000d +.dd 0x0090000e +.dd 0x0100000f +.dd 0x02000010 +.dd 0x03000011 +.dd 0x04000012 +.dd 0x05000013 +.dd 0x06000014 +.dd 0x001a0000 +.dd 0x001b0001 +.dd 0x001c0002 +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S b/sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S new file mode 100644 index 0000000..0b78d5e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_mmr_ppopm_illegal_adr.S @@ -0,0 +1,308 @@ +//Original:/proj/frio/dv/testcases/core/c_mmr_ppopm_illegal_adr/c_mmr_ppopm_illegal_adr.dsp +// Spec Reference: mmr ppopm illegal address +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we set the processor operating modes, initialize registers +// etc.) +// + +BOOT: + +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + //CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; // and frame pointer + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// +STARTUSER: +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + + + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + +LD32(r0, 0206037020); +LD32(r1, 0x10070030); +LD32(r2, 0xe2000043); +LD32(r3, 0x30305050); +LD32(r4, 0x0f040860); +LD32(r5, 0x0a0050d0); +LD32(r6, 0x00000000); +LD32(r7, 0x0f060071); + [ -- SP ] = ( R7:7 ); +LD32(r7, 0x123456af); + [ -- SP ] = ( R7:6 ); +// [--sp] = r7; +// [--sp] = r6; +.dd 0xffff + R1 += 2; + +CHECKREG(r1, 0x10070034); +CHECKREG(r2, 0xE2000046); +CHECKREG(r3, 0x30305054); +CHECKREG(r4, 0x0f040865); +CHECKREG(r5, 0x0a0050d6); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x123456b7); + R7 = [ SP ++ ]; +CHECKREG(r7, 0x123456af); + +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 +R0 = RETX; // error handler:RETX has the address of the same Illegal instr + R1 += 2; + R2 += 3; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; +R0 += 2; // we have to add 2 to point to next instr after return (16-bit illegal instr) +RETX = R0; +NOP; NOP; NOP; NOP; + + +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA0: +.dd 0x000a0000 +.dd 0x000b0001 +.dd 0x000c0002 +.dd 0x000d0003 +.dd 0x000e0004 +.dd 0x000f0005 +.dd 0x00100006 +.dd 0x00200007 +.dd 0x00300008 +.dd 0x00400009 +.dd 0x0050000a +.dd 0x0060000b +.dd 0x0070000c +.dd 0x0080000d +.dd 0x0090000e +.dd 0x0100000f +.dd 0x02000010 +.dd 0x03000011 +.dd 0x04000012 +.dd 0x05000013 +.dd 0x06000014 +.dd 0x001a0000 +.dd 0x001b0001 +.dd 0x001c0002 +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_mmr_timer.S b/sim/testsuite/sim/bfin/c_mmr_timer.S new file mode 100644 index 0000000..ac34e17 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_mmr_timer.S @@ -0,0 +1,282 @@ +//Original:/proj/frio/dv/testcases/core/c_mmr_timer/c_mmr_timer.dsp +// Spec Reference: mmr timer +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we set the processor operating modes, initialize registers +// etc.) +// + +BOOT: + +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + //CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; // and frame pointer + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// +STARTUSER: +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // TCNTL: 4 bits, rw=1 = 0xFFE03000 +LD32(p0, 0xFFE03000); +LD32(r0, 0x0000000D); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R1 = [ P0 ]; + + // TPERIOD: 32 bits, rw=1 = 0xFFE03004 +LD32(p0, 0xFFE03004); +LD32(r0, 0x11112222); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R2 = [ P0 ]; + + // TSCALE: 8 bits, rw=1 = 0xFFE03008 +LD32(p0, 0xFFE03008); +LD32(r0, 0x00000050); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R3 = [ P0 ]; + + + // TCOUNT: 32 bits, rw=1 = 0xFFE0300C +LD32(p0, 0xFFE0300C); +LD32(r0, 0x00000100); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R4 = [ P0 ]; + + +CHECKREG(r1, 0x0000000D); +CHECKREG(r2, 0x11112222); +CHECKREG(r3, 0x00000050); +CHECKREG(r4, 0x00000100); + +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +//.data 0xFFE03000 +//.dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/c_mode_supervisor.S b/sim/testsuite/sim/bfin/c_mode_supervisor.S new file mode 100644 index 0000000..4ea0d6c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_mode_supervisor.S @@ -0,0 +1,287 @@ +//Original:/proj/frio/dv/testcases/core/c_mode_supervisor/c_mode_supervisor.dsp +// Spec Reference: mode_supervisor +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +RAISE 2; // RTN +RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI +RAISE 15; // RTI + +CHECKREG(r0, 0x0000000B); +CHECKREG(r1, 0x0000000C); +CHECKREG(r2, 0x0000000D); +CHECKREG(r3, 0x0000000E); +CHECKREG(r4, 0x00000007); +CHECKREG(r5, 0x00000008); +CHECKREG(r6, 0x00000009); +CHECKREG(r7, 0x0000000A); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +CHECKREG(r0, 0x00000002); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000005); +CHECKREG(r3, 0x00000006); +CHECKREG(r4, 0x00000007); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_mode_user.S b/sim/testsuite/sim/bfin/c_mode_user.S new file mode 100644 index 0000000..1b72035 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_mode_user.S @@ -0,0 +1,338 @@ +//Original:/proj/frio/dv/testcases/core/c_mode_user/c_mode_user.dsp +// Spec Reference: mode_user +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + A0 = 0; // reset accumulators + A1 = 0; + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; // execute this instr put us in USER mode + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // USER MODE & go to different RAISE in USER mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +A1 = A0 = 0; +ASTAT = R0; + + +// R-reg to P-reg to R reg: stall +LD32(r0, 0x1357bdad); +LD32(r1, 0x02dfe804); +LD32(r2, 0x12345679); +LD32(r3, 0x34751975); +LD32(r4, 0x08810990); +LD32(r5, 0x01a1b0b0); +LD32(r6, 0x01c1dd00); +LD32(r7, 0x01e1fff0); +R5 = R3.L * R1.L, R4 = R3.L * R1.L; // dsp32mult_pair +P4 = R5; +R6 = P4; +R1 = ( A1 += R5.L * R6.H ), A0 = R5.H * R6.L; // dsp32mac_pair +P3 = A0.w; +P4 = A1.w; +A1 = A1 (S), A0 = A0 (S); // dsp32alu_sat_aa +R6 = A0.w; +R7 = A1.w; +R0 = R7; +R2 = R0; // regmv +R2 >>>= R3; // c_alu2op_arith_r_sft.dsp +R4 = R2 - R1; +R5.L = ASHIFT R4.L BY R3.L; +R6 += -3; //c_compi2opd_dr_add_i7_n.dsp +I2 = R6; +I2 += 2; +I2 += M1; +R7 = I2; + + +CHECKREG(r0, 0x015AF820); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x34751975); +CHECKREG(r4, 0xFEA507E0); +CHECKREG(r5, 0xFB3A0000); +CHECKREG(r6, 0x015AF81D); +CHECKREG(r7, 0x015AF81F); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x015AF81F); +CHECKREG(r3, 0x00000000); +CHECKREG(r4, 0xFEA507E0); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = RETN; + R0 += 2; +RETN = r0; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = RETX; + R0 += 1; + R1 += 2; + R2 += 1; + R3 += 1; + R4 += 1; + R5 += 1; + R6 += 1; + R7 += 1; +RETX = r1; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = RETI; + R2 += 2; +RETI = r2; +RTI; + +THANDLE: // Timer Handler 6 + R3 = RETI; + R3 += 2; +RETI = r3; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = RETI; + R4 += 2; +RETI = r4; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = RETI; + R5 += 2; +RETI = r5; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = RETI; + R6 += 2; +RETI = r6; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = RETI; + R7 += 2; +RETI = r7; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = RETI; + R0 += 2; +RETI = r0; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = RETI; + R1 += 2; +RETI = r1; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = RETI; + R2 += 2; +RETI = r2; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = RETI; + R3 += 2; +RETI = r3; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: +// .space (STACKSIZE); // adding this may solve the problem diff --git a/sim/testsuite/sim/bfin/c_mode_user_superivsor.S b/sim/testsuite/sim/bfin/c_mode_user_superivsor.S new file mode 100644 index 0000000..ef8a2b4 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_mode_user_superivsor.S @@ -0,0 +1,353 @@ +//Original:/proj/frio/dv/testcases/core/c_mode_user_superivsor/c_mode_user_superivsor.dsp +// Spec Reference: mode_user_supervisor +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +// + +////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; // execute this instr put us in USER mode + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // USER MODE & go to different RAISE in USER mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 +RAISE 2; // RTN +RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; + +CHECKREG(r0, 0x00000018); +CHECKREG(r1, 0x00000018); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000018); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x00000000); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = RETN; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETN = r0; +RTN; + +XHANDLE: // Exception Handler 3 + R0 = RETX; + I0 += 2; + I1 += 2; + I3 += 2; + R0 += 2; +RETX = r0; +RTX; + +HWHANDLE: // HW Error Handler 5 + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + R0 += 2; +RETI = r0; +RTI; + +THANDLE: // Timer Handler 6 + R0 = RETI; + R0 += 2; +RETI = r0; +RTI; + +I7HANDLE: // IVG 7 Handler + R0 = RETI; + I0 += 2; + I1 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I8HANDLE: // IVG 8 Handler + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + M0 = I0; + M1 = I1; + M2 = I2; + M3 = I3; + R0 += 2; +RETI = r0; +RTI; + +I9HANDLE: // IVG 9 Handler + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I10HANDLE: // IVG 10 Handler + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + M0 = R4; + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I12HANDLE: // IVG 12 Handler + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I13HANDLE: // IVG 13 Handler + R0 = RETI; + I0 += 2; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I14HANDLE: // IVG 14 Handler + R0 = RETI; + I1 += 2; + I2 += 2; + I3 += 2; + R0 += 2; +RETI = r0; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; + I1 += 2; + I2 += 2; +RTI; + +// nop;nop;nop;nop;nop;nop;nop; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: +// .space (STACKSIZE); // adding this may solve the problem diff --git a/sim/testsuite/sim/bfin/c_multi_issue_dsp_ld_ld.s b/sim/testsuite/sim/bfin/c_multi_issue_dsp_ld_ld.s new file mode 100644 index 0000000..1af87dc --- /dev/null +++ b/sim/testsuite/sim/bfin/c_multi_issue_dsp_ld_ld.s @@ -0,0 +1,197 @@ +//Original:/testcases/core/c_multi_issue_dsp_ld_ld/c_multi_issue_dsp_ld_ld.dsp +// Spec Reference: dsp32mac and 2 loads +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + imm32 r0, 0x00000000; + A0 = 0; + A1 = 0; + ASTAT = r0; + + loadsym I0, DATA0 + loadsym I1, DATA1 + + loadsym P1, DATA0 + loadsym P2, DATA1 + +// test the default (signed fraction : left ) + imm32 r0, 0x12345678; + imm32 r1, 0x33456789; + imm32 r2, 0x5556789a; + imm32 r3, 0x75678912; + imm32 r4, 0x86789123; + imm32 r5, 0xa7891234; + imm32 r6, 0xc1234567; + imm32 r7, 0xf1234567; + A1 = R0.L * R1.L, A0 = R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; + A1 += R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ I0 ++ ] || R3 = [ I1 ++ ]; + A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = [ P1 ++ ] || R5 = [ I1 ++ ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x000A0000; + CHECKREG r1, 0x00F00100; + CHECKREG r2, 0x000B0001; + CHECKREG r3, 0x00E00101; + CHECKREG r4, 0x000A0000; + CHECKREG r5, 0x00D00102; + CHECKREG r6, 0x92793486; + CHECKREG r7, 0xDD2F9BAA; + + imm32 r0, 0x12245618; + imm32 r1, 0x23256719; + imm32 r2, 0x3426781a; + imm32 r3, 0x45278912; + imm32 r4, 0x56289113; + imm32 r5, 0x67291214; + imm32 r6, 0xa1234517; + imm32 r7, 0xc1234517; + A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = [ P1 ++ ] || R6 = [ I0 ++ ]; + A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ P2 ++ ] || R3 = [ I1 ++ ]; + A1 += R4.H * R6.H, A0 -= R4.H * R6.L || [ P2 ++ ] = R5 || R7 = [ I1 ++ ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x12245618; + CHECKREG r1, 0x23256719; + CHECKREG r2, 0x00F00100; + CHECKREG r3, 0x00C00103; + CHECKREG r4, 0x000B0001; + CHECKREG r5, 0x67291214; + CHECKREG r6, 0x863ABC70; + CHECKREG r7, 0xB4EF6A10; + + imm32 r0, 0x15245648; + imm32 r1, 0x25256749; + imm32 r2, 0x3526784a; + imm32 r3, 0x45278942; + imm32 r4, 0x55389143; + imm32 r5, 0x65391244; + imm32 r6, 0xa5334547; + imm32 r7, 0xc5334547; + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = [ P1 ++ ] || R0 = [ I1 -- ]; + A1 += R2.H * R3.H, A0 += R2.L * R3.H || NOP || R4 = [ I0 ++ ]; + A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = [ P2 -- ] || R5 = [ I0 -- ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x00A00105; + CHECKREG r1, 0x25256749; + CHECKREG r2, 0x000C0002; + CHECKREG r3, 0x00D00102; + CHECKREG r4, 0x000D0003; + CHECKREG r5, 0x000E0004; + CHECKREG r6, 0xCBDCD104; + CHECKREG r7, 0x0001DAE8; + + imm32 r1, 0x02450789; + imm32 r2, 0x0356089a; + imm32 r3, 0x04670912; + imm32 r4, 0x05780123; + imm32 r5, 0x06890234; + imm32 r6, 0x07230567; + imm32 r7, 0x00230567; + R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R1 = [ I1 ++ ] || R0 = [ I0 -- ]; + R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = [ P1 ] || R3 = [ I0 -- ]; + R5 = R4 +|+ R2, R0 = R4 -|- R2 (CO) || NOP || R4 = [ I0 ++ ]; + CHECKREG r0, 0xFA99FFDD; + CHECKREG r1, 0x0B8A0E79; + CHECKREG r2, 0x00610336; + CHECKREG r3, 0x000C0002; + CHECKREG r4, 0x000B0001; + CHECKREG r5, 0x009F0105; + CHECKREG r6, 0x000D0003; + CHECKREG r7, 0x00230567; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + .dd 0x000f0005 + .dd 0x00100006 + .dd 0x00200007 + .dd 0x00300008 + .dd 0x00400009 + .dd 0x0050000a + .dd 0x0060000b + .dd 0x0070000c + .dd 0x0080000d + .dd 0x0090000e + .dd 0x0100000f + .dd 0x02000010 + .dd 0x03000011 + .dd 0x04000012 + .dd 0x05000013 + .dd 0x06000014 + .dd 0x001a0000 + .dd 0x001b0001 + .dd 0x001c0002 + .dd 0x001d0003 + .dd 0x00010004 + .dd 0x00010005 + .dd 0x02100006 + .dd 0x02200007 + .dd 0x02300008 + .dd 0x02200009 + .dd 0x0250000a + .dd 0x0260000b + .dd 0x0270000c + .dd 0x0280000d + .dd 0x0290000e + .dd 0x2100000f + .dd 0x22000010 + .dd 0x22000011 + .dd 0x24000012 + .dd 0x25000013 + .dd 0x26000014 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 + .dd 0x00b00104 + .dd 0x00a00105 + .dd 0x00900106 + .dd 0x00800107 + .dd 0x00100108 + .dd 0x00200109 + .dd 0x0030010a + .dd 0x0040010b + .dd 0x0050011c + .dd 0x0060010d + .dd 0x0070010e + .dd 0x0080010f + .dd 0x00900110 + .dd 0x01000111 + .dd 0x02000112 + .dd 0x03000113 + .dd 0x04000114 + .dd 0x05000115 + .dd 0x03f00100 + .dd 0x03e00101 + .dd 0x03d00102 + .dd 0x03c00103 + .dd 0x03b00104 + .dd 0x03a00105 + .dd 0x03900106 + .dd 0x03800107 + .dd 0x03100108 + .dd 0x03200109 + .dd 0x0330010a + .dd 0x0330010b + .dd 0x0350011c + .dd 0x0360010d + .dd 0x0370010e + .dd 0x0380010f + .dd 0x03900110 + .dd 0x31000111 + .dd 0x32000112 + .dd 0x33000113 + .dd 0x34000114 diff --git a/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_1.s b/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_1.s new file mode 100644 index 0000000..8dc8373 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_1.s @@ -0,0 +1,198 @@ +//Original:/testcases/core/c_multi_issue_dsp_ldst_1/c_multi_issue_dsp_ldst_1.dsp +// Spec Reference: dsp32mac and 2 load/store +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + + imm32 r0, 0x00000000; + A0 = 0; + A1 = 0; + ASTAT = r0; + + loadsym I0, DATA0; + loadsym I1, DATA1; + + loadsym P1, DATA0; + loadsym P2, DATA1; + +// test the default (signed fraction : left ) + imm32 r0, 0x12345678; + imm32 r1, 0x33456789; + imm32 r2, 0x5556789a; + imm32 r3, 0x75678912; + imm32 r4, 0x86789123; + imm32 r5, 0xa7891234; + imm32 r6, 0xc1234567; + imm32 r7, 0xf1234567; + A1 = R0.L * R1.L, A0 = R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; + A1 += R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ I0 ++ ] || R3 = [ I1 ++ ]; + A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = [ P1 ++ ] || [ I1 ++ ] = R5; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x000A0000; + CHECKREG r1, 0x00F00100; + CHECKREG r2, 0x000B0001; + CHECKREG r3, 0x00E00101; + CHECKREG r4, 0x000A0000; + CHECKREG r5, 0xA7891234; + CHECKREG r6, 0x92793486; + CHECKREG r7, 0xDD2F9BAA; + + imm32 r0, 0x12245618; + imm32 r1, 0x23256719; + imm32 r2, 0x3426781a; + imm32 r3, 0x45278912; + imm32 r4, 0x56289113; + imm32 r5, 0x67291214; + imm32 r6, 0xa1234517; + imm32 r7, 0xc1234517; + A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = [ P1 ++ ] || [ I0 ++ ] = R6; + A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ P2 ++ ] || [ I1 ++ ] = R3; + A1 += R4.H * R6.H, A0 -= R4.H * R6.L || [ P2 ++ ] = R5 || R7 = [ I1 ++ ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x12245618; + CHECKREG r1, 0x23256719; + CHECKREG r2, 0x00F00100; + CHECKREG r3, 0x45278912; + CHECKREG r4, 0x000B0001; + CHECKREG r5, 0x67291214; + CHECKREG r6, 0x8634CCA2; + CHECKREG r7, 0xB4E7420A; + + imm32 r0, 0x15245648; + imm32 r1, 0x25256749; + imm32 r2, 0x3526784a; + imm32 r3, 0x45278942; + imm32 r4, 0x55389143; + imm32 r5, 0x65391244; + imm32 r6, 0xa5334547; + imm32 r7, 0xc5334547; + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = [ P1 ++ ] || [ I1 -- ] = R3; + A1 += R2.H * R3.H, A0 += R2.L * R3.H || NOP || [ I0 ++ ] = R2; + A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = [ P2 -- ] || R6 = [ I0 -- ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x15245648; + CHECKREG r1, 0x25256749; + CHECKREG r2, 0xA1234517; + CHECKREG r3, 0xA7891234; + CHECKREG r4, 0x55389143; + CHECKREG r5, 0x65391244; + CHECKREG r6, 0xFD508A74; + CHECKREG r7, 0x0C2925C0; + + imm32 r1, 0x02450789; + imm32 r2, 0x0356089a; + imm32 r3, 0x04670912; + imm32 r4, 0x05780123; + imm32 r5, 0x06890234; + imm32 r6, 0x07230567; + imm32 r7, 0x00230567; + R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R0 = [ I1 ++ ] || [ I0 -- ] = R2; + R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = [ P1 ] || [ I0 -- ] = R3; + R5 = R4 +|+ R2, R0 = R4 -|- R2 (CO) || NOP || [ I0 ++ ] = R5; + CHECKREG r0, 0xFA99FFDD; + CHECKREG r1, 0x0B8A0E79; + CHECKREG r2, 0x0AA32DD7; + CHECKREG r3, 0x04670912; + CHECKREG r4, 0x0A802870; + CHECKREG r5, 0x15235647; + CHECKREG r6, 0x0356089A; + CHECKREG r7, 0x00230567; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + .dd 0x000f0005 + .dd 0x00100006 + .dd 0x00200007 + .dd 0x00300008 + .dd 0x00400009 + .dd 0x0050000a + .dd 0x0060000b + .dd 0x0070000c + .dd 0x0080000d + .dd 0x0090000e + .dd 0x0100000f + .dd 0x02000010 + .dd 0x03000011 + .dd 0x04000012 + .dd 0x05000013 + .dd 0x06000014 + .dd 0x001a0000 + .dd 0x001b0001 + .dd 0x001c0002 + .dd 0x001d0003 + .dd 0x00010004 + .dd 0x00010005 + .dd 0x02100006 + .dd 0x02200007 + .dd 0x02300008 + .dd 0x02200009 + .dd 0x0250000a + .dd 0x0260000b + .dd 0x0270000c + .dd 0x0280000d + .dd 0x0290000e + .dd 0x2100000f + .dd 0x22000010 + .dd 0x22000011 + .dd 0x24000012 + .dd 0x25000013 + .dd 0x26000014 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 + .dd 0x00b00104 + .dd 0x00a00105 + .dd 0x00900106 + .dd 0x00800107 + .dd 0x00100108 + .dd 0x00200109 + .dd 0x0030010a + .dd 0x0040010b + .dd 0x0050011c + .dd 0x0060010d + .dd 0x0070010e + .dd 0x0080010f + .dd 0x00900110 + .dd 0x01000111 + .dd 0x02000112 + .dd 0x03000113 + .dd 0x04000114 + .dd 0x05000115 + .dd 0x03f00100 + .dd 0x03e00101 + .dd 0x03d00102 + .dd 0x03c00103 + .dd 0x03b00104 + .dd 0x03a00105 + .dd 0x03900106 + .dd 0x03800107 + .dd 0x03100108 + .dd 0x03200109 + .dd 0x0330010a + .dd 0x0330010b + .dd 0x0350011c + .dd 0x0360010d + .dd 0x0370010e + .dd 0x0380010f + .dd 0x03900110 + .dd 0x31000111 + .dd 0x32000112 + .dd 0x33000113 + .dd 0x34000114 diff --git a/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_2.s b/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_2.s new file mode 100644 index 0000000..16fd3e5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_2.s @@ -0,0 +1,198 @@ +//Original:/testcases/core/c_multi_issue_dsp_ldst_2/c_multi_issue_dsp_ldst_2.dsp +// Spec Reference: dsp32mac and 2 load/store +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + INIT_R_REGS 0; + + imm32 r0, 0x00000000; + A0 = 0; + A1 = 0; + ASTAT = r0; + + loadsym I0, DATA0; + loadsym I1, DATA1; + + loadsym P1, DATA0; + loadsym P2, DATA1; + +// test the default (signed fraction : left ) + imm32 r0, 0x12345678; + imm32 r1, 0x33456789; + imm32 r2, 0x5556789a; + imm32 r3, 0x75678912; + imm32 r4, 0x86789123; + imm32 r5, 0xa7891234; + imm32 r6, 0xc1234567; + imm32 r7, 0xf1234567; + A1 = R0.L * R1.L, A0 = R0.L * R1.L || R2 = B [ P1 ++ ] (X) || R3 = [ I1 ++ ]; + A1 += R2.L * R3.L, A0 += R2.L * R3.H || R0 = B [ P1 ++ ] (X) || R1 = [ I1 ++ ]; + A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = B [ P2 ++ ] (X) || [ I1 ++ ] = R5; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00E00101; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00F00100; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0xA7891234; + CHECKREG r6, 0x23DB649A; + CHECKREG r7, 0x4D3DD202; + + imm32 r0, 0x12245618; + imm32 r1, 0x23256719; + imm32 r2, 0x3426781a; + imm32 r3, 0x45278912; + imm32 r4, 0x56289113; + imm32 r5, 0x67291214; + imm32 r6, 0xa1234517; + imm32 r7, 0xc1234517; + A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = B [ P1 ++ ] (X) || [ I0 ++ ] = R6; + A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = B [ P2 ++ ] (X) || [ I1 ++ ] = R3; + A1 += R4.H * R6.H, A0 -= R4.H * R6.L || R5 = B [ P2 ++ ] (X) || R7 = [ I1 ++ ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x12245618; + CHECKREG r1, 0x23256719; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x45278912; + CHECKREG r4, 0x0000000A; + CHECKREG r5, 0xFFFFFFF0; + CHECKREG r6, 0x863ABC9C; + CHECKREG r7, 0xB4EF6908; + + imm32 r0, 0x15245648; + imm32 r1, 0x25256749; + imm32 r2, 0x3526784a; + imm32 r3, 0x45278942; + imm32 r4, 0x55389143; + imm32 r5, 0x65391244; + imm32 r6, 0xa5334547; + imm32 r7, 0xc5334547; + A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = B [ P1 ++ ] (X) || [ I1 -- ] = R3; + A1 += R2.H * R3.H, A0 += R2.L * R3.H || R0 = B [ P2 -- ] (X) || [ I0 ++ ] = R2; + A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = B [ P2 ++ ] (X) || R1 = [ I0 -- ]; + R6 = A0.w; + R7 = A1.w; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x000C0002; + CHECKREG r2, 0xFFFFFFA1; + CHECKREG r3, 0xFFFFFFF0; + CHECKREG r4, 0x55389143; + CHECKREG r5, 0x65391244; + CHECKREG r6, 0xD7CFB47A; + CHECKREG r7, 0x0C2925C0; + + imm32 r1, 0x02450789; + imm32 r2, 0x0356089a; + imm32 r3, 0x04670912; + imm32 r4, 0x05780123; + imm32 r5, 0x06890234; + imm32 r6, 0x07230567; + imm32 r7, 0x00230567; + R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R0 = B [ P1 ++ ] (X) || [ I0 -- ] = R2; + R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = B [ P1 ] (X) || [ I0 -- ] = R3; + R5 = R4 +|+ R2, R0 = R4 -|- R2 || R3 = B [ P2 ++ ] (X) || R7 = [ I1 ++ ]; + CHECKREG r0, 0xFFDDFA99; + CHECKREG r1, 0x0B8A0E79; + CHECKREG r2, 0x001102B3; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0xFFEEFD4C; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0x00000008; + CHECKREG r7, 0x00B00104; + + pass + + .data +DATA0: + .dd 0x000a0000 + .dd 0x000b0001 + .dd 0x000c0002 + .dd 0x000d0003 + .dd 0x000e0004 + .dd 0x000f0005 + .dd 0x00100006 + .dd 0x00200007 + .dd 0x00300008 + .dd 0x00400009 + .dd 0x0050000a + .dd 0x0060000b + .dd 0x0070000c + .dd 0x0080000d + .dd 0x0090000e + .dd 0x0100000f + .dd 0x02000010 + .dd 0x03000011 + .dd 0x04000012 + .dd 0x05000013 + .dd 0x06000014 + .dd 0x001a0000 + .dd 0x001b0001 + .dd 0x001c0002 + .dd 0x001d0003 + .dd 0x00010004 + .dd 0x00010005 + .dd 0x02100006 + .dd 0x02200007 + .dd 0x02300008 + .dd 0x02200009 + .dd 0x0250000a + .dd 0x0260000b + .dd 0x0270000c + .dd 0x0280000d + .dd 0x0290000e + .dd 0x2100000f + .dd 0x22000010 + .dd 0x22000011 + .dd 0x24000012 + .dd 0x25000013 + .dd 0x26000014 + +DATA1: + .dd 0x00f00100 + .dd 0x00e00101 + .dd 0x00d00102 + .dd 0x00c00103 + .dd 0x00b00104 + .dd 0x00a00105 + .dd 0x00900106 + .dd 0x00800107 + .dd 0x00100108 + .dd 0x00200109 + .dd 0x0030010a + .dd 0x0040010b + .dd 0x0050011c + .dd 0x0060010d + .dd 0x0070010e + .dd 0x0080010f + .dd 0x00900110 + .dd 0x01000111 + .dd 0x02000112 + .dd 0x03000113 + .dd 0x04000114 + .dd 0x05000115 + .dd 0x03f00100 + .dd 0x03e00101 + .dd 0x03d00102 + .dd 0x03c00103 + .dd 0x03b00104 + .dd 0x03a00105 + .dd 0x03900106 + .dd 0x03800107 + .dd 0x03100108 + .dd 0x03200109 + .dd 0x0330010a + .dd 0x0330010b + .dd 0x0350011c + .dd 0x0360010d + .dd 0x0370010e + .dd 0x0380010f + .dd 0x03900110 + .dd 0x31000111 + .dd 0x32000112 + .dd 0x33000113 + .dd 0x34000114 diff --git a/sim/testsuite/sim/bfin/c_progctrl_call_pcpr.s b/sim/testsuite/sim/bfin/c_progctrl_call_pcpr.s new file mode 100644 index 0000000..4cc5b29 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_progctrl_call_pcpr.s @@ -0,0 +1,63 @@ +//Original:/testcases/core/c_progctrl_call_pcpr/c_progctrl_call_pcpr.dsp +// Spec Reference: progctrl call (pc+pr) +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = r0; + + FP = SP; + + P2 = 0x0006; + +JMP: + CALL ( PC + P2 ); + JUMP.S JMP; + +STOP: + JUMP.S END; + +LAB1: + P2 = 0x000e; + R1 = 0x1111 (X); + RTS; + +LAB2: + P2 = 0x0016; + R2 = 0x2222 (X); + RTS; + +LAB3: + P2 = 0x001e; + R3 = 0x3333 (X); + RTS; + +LAB4: + P2 = 0x0026; + R4 = 0x4444 (X); + RTS; + +LAB5: + P2 = 0x0004; + R5 = 0x5555 (X); + RTS; + +END: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00001111; + CHECKREG r2, 0x00002222; + CHECKREG r3, 0x00003333; + CHECKREG r4, 0x00004444; + CHECKREG r5, 0x00005555; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass + + .data +DATA: + .space (0x0100); diff --git a/sim/testsuite/sim/bfin/c_progctrl_call_pr.s b/sim/testsuite/sim/bfin/c_progctrl_call_pr.s new file mode 100644 index 0000000..be8278e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_progctrl_call_pr.s @@ -0,0 +1,32 @@ +//Original:/testcases/core/c_progctrl_call_pr/c_progctrl_call_pr.dsp +// Spec Reference: progctrl call (pr) +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = r0; + + FP = SP; + + loadsym P1, SUBR; + CALL ( P1 ); + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00001111; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass + +SUBR: // should jump here + R1.L = 0x1111; + RTS; + R2.L = 0x2222; // should not go here + RTS; diff --git a/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S b/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S new file mode 100644 index 0000000..78d6e67 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S @@ -0,0 +1,330 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_clisti_interr/c_progctrl_clisti_interr.dsp +// Spec Reference: CLI STI interrupt on HW TIMER +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Include Files +// + +include(std.inc) +include(selfcheck.inc) + +// Defines + +#ifndef TCNTL +#define TCNTL 0xFFE03000 +#endif +#ifndef TPERIOD +#define TPERIOD 0xFFE03004 +#endif +#ifndef TSCALE +#define TSCALE 0xFFE03008 +#endif +#ifndef TCOUNT +#define TCOUNT 0xFFE0300c +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203c +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0x000FF000 +#endif +#ifndef PROGRAM_STACK +#define PROGRAM_STACK 0x000FF100 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000300 +#endif + +// Boot code + + +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + + //CHECK_INIT(p5, 0xE0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + BOOT : + +LD32(sp, 0x000FF200); +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +LD32_LABEL(r7, START); +RETI = r7; +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + + START : + R7 = 0x0; + R6 = 0x1; + [ -- SP ] = RETI; // Enable Nested Interrupts + +CLI R1; // stop interrupt +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) +WR_MMR(TPERIOD, 0x00000050, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000000, p0, r0); +CSYNC; + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000050); + +// RD_MMR(TCOUNT, p0, r3); +// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 + + +WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) +CSYNC; + +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +NOP; NOP; NOP; +RD_MMR(TPERIOD, p0, r4); +CHECKREG(r4, 0x00000050); + +// RD_MMR(TCNTL, p0, r5); +// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen + +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; +WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power +WR_MMR(TPERIOD, 0x00000015, p0, r0); +WR_MMR(TCOUNT, 0x00000013, p0, r0); +WR_MMR(TSCALE, 0x00000002, p0, r0); +WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) +CSYNC; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label4; + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label5: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label6; + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +label4: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +JUMP.S label5; + R5.L = 0x2222; // Will be killed + R5.H = 0x2222; // Will be killed +NOP; +NOP; +NOP; +NOP; +label6: R3.H = 0x7999; + R3.L = 0x7aaa; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + // With auto reload + // Read the contents of the Timer + +RD_MMR(TPERIOD, p0, r2); +CHECKREG(r2, 0x00000015); + +// RD_MMR(TCNTL , p0, r3); +// CHECKREG(r3, 0x0000000F); +NOP; +CHECKREG(r7, 0x00000000); // no interrupt being serviced +NOP; +STI R1; + +NOP; NOP; NOP; +NOP; NOP; NOP; +WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer +CSYNC; +NOP; NOP; NOP; + + + + + +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 + R7 = R7 + R6; +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler + R5 = RETI; + P0 = R5; +JUMP ( P0 ); +RTI; + +.section MEM_PROGRAM_STACK,"aw" + +.space (STACKSIZE); +STACK: +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug diff --git a/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S b/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S new file mode 100644 index 0000000..0aeccde --- /dev/null +++ b/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S @@ -0,0 +1,280 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_csync_mmr/c_progctrl_csync_mmr.dsp +// Spec Reference: csync mmr timer +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +INIT_R_REGS(-1); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // TCNTL: 4 bits, rw=1 = 0xFFE03000 +LD32(p0, 0xFFE03000); +LD32(r0, 0x00000001); + [ P0 ] = R0; +LD32(r0, 0x0000000D); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R1 = [ P0 ]; + + // TPERIOD: 32 bits, rw=1 = 0xFFE03004 +LD32(p0, 0xFFE03004); +LD32(r0, 0x11112222); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R2 = [ P0 ]; + + // TSCALE: 8 bits, rw=1 = 0xFFE03008 +LD32(p0, 0xFFE03008); +LD32(r0, 0x00000050); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R3 = [ P0 ]; + + + // TCOUNT: 32 bits, rw=1 = 0xFFE0300C +LD32(p0, 0xFFE0300C); +LD32(r0, 0x00000100); + [ P0 ] = R0; +CSYNC; // without this it read out zero + R4 = [ P0 ]; + + +CHECKREG(r1, 0x0000000D); +CHECKREG(r2, 0x11112222); +CHECKREG(r3, 0x00000050); +CHECKREG(r4, 0x00000100); + +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_progctrl_except_rtx.S b/sim/testsuite/sim/bfin/c_progctrl_except_rtx.S new file mode 100644 index 0000000..9cacc28 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_progctrl_except_rtx.S @@ -0,0 +1,96 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_except_rtx/c_progctrl_except_rtx.dsp +// Spec Reference: c_progctrl_except_rtx +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); +// load address of exception handler + +P0 = 0x200C (Z); // 0xFFE0200C EVT3 EXCEPTION +P0.H = 0xFFE0; +R0 = exception_handler (Z); // wr address of exception handler to MMR EVT3 +R0.H = exception_handler; +[ P0 ] = R0; + +// Jump to User mode and enable exceptions + +R0 = MidUserCode (Z); +R0.H = MidUserCode; +RETI = R0; +RTI; // cause it to go to Midusercode, .dd cause exception + +BeginUserCode: +P1 = 1; +P2 = 2; +P3 = 3; +P4 = 4; + +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000001); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000003); +CHECKREG(r5, 0x00000000); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x00000000); +CHECKREG(p1, 0x00000001); +CHECKREG(p2, 0x00000002); +CHECKREG(p3, 0x00000003); +CHECKREG(p4, 0x00000004); + +dbg_pass; +//jump 2; +//jump -2; +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF + +//dbg_pass; + +MidUserCode: +.dd 0xFFFFFFFF +R0 = 0; +R1 = 1; +R2 = 2; +R3 = 3; +CC = R0; +IF !CC JUMP BeginUserCode; + +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF +.dd 0xFFFFFFFF + + +exception_handler: +R4 = RETX; // error handler: RETX has the address of the same Illegal instr +R1 += 1; +R2 += 2; +R3 += 3; +R1 += 1; +R4 += 4; // we have to add 4 to point to next instr after return +RETX = R4; + +RTX; // return from exception + +.section MEM_DATA_ADDR_1,"aw" +.dd 0xDEADBEEF +.dd 0xBAD00BAD diff --git a/sim/testsuite/sim/bfin/c_progctrl_excpt.S b/sim/testsuite/sim/bfin/c_progctrl_excpt.S new file mode 100644 index 0000000..625a5c0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_progctrl_excpt.S @@ -0,0 +1,261 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_excpt/c_progctrl_excpt.dsp +// Spec Reference: progctrl excpt uimm4 +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +EXCPT 2; // RETX RTX + +CHECKREG(r0, 0x0000000A); +CHECKREG(r1, 0x0000000B); +CHECKREG(r2, 0x0000000C); +CHECKREG(r3, 0x0000000D); +CHECKREG(r4, 0x00000000); +CHECKREG(r5, 0x00000000); +CHECKREG(r6, 0x00000000); +CHECKREG(r7, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + R0 = 10; + R1 = 11; + R2 = 12; + R3 = 13; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s b/sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s new file mode 100644 index 0000000..727025c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s @@ -0,0 +1,58 @@ +//Original:/testcases/core/c_progctrl_jump_pcpr/c_progctrl_jump_pcpr.dsp +// Spec Reference: progctrl jump pc+pr +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + + P2 = 0x0004; + +JMP: + JUMP ( PC + P2 ); +// jump JMP; + +STOP: +JUMP.S END; + +LAB1: + P2 = 0x000c; + R1 = 0x1111 (X); +JUMP.S JMP; + +LAB2: + P2 = 0x0014; + R2 = 0x2222 (X); +JUMP.S JMP; + +LAB3: + P2 = 0x001c; + R3 = 0x3333 (X); +JUMP.S JMP; + +LAB4: + P2 = 0x0024; + R4 = 0x4444 (X); +JUMP.S JMP; + +LAB5: + P2 = 0x0002; + R5 = 0x5555 (X); +JUMP.S JMP; + +END: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00002222; +CHECKREG r3, 0x00003333; +CHECKREG r4, 0x00004444; +CHECKREG r5, 0x00005555; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/c_progctrl_jump_pr.s b/sim/testsuite/sim/bfin/c_progctrl_jump_pr.s new file mode 100644 index 0000000..8b77c31 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_progctrl_jump_pr.s @@ -0,0 +1,56 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_jump_pr/c_progctrl_jump_pr.dsp +// Spec Reference: progctrl jump(p) +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = r0; + + loadsym p1, LAB1; + loadsym p2, LAB2; + loadsym fp, LAB3; + loadsym p4, LAB4; + loadsym p5, LAB5; + + JUMP ( P1 ); + +STOP: + JUMP.S END; + +LAB1: + R1 = 0x1111 (X); + JUMP ( P5 ); + R6 = 0x6666 (X); + +LAB2: + R2 = 0x2222 (X); + JUMP.S STOP; + +LAB3: + R3 = 0x3333 (X); + JUMP ( P2 ); + R7 = 0x7777 (X); + +LAB4: + R4 = 0x4444 (X); + JUMP ( FP ); + +LAB5: + R5 = 0x5555 (X); + JUMP ( P4 ); + +END: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00001111; + CHECKREG r2, 0x00002222; + CHECKREG r3, 0x00003333; + CHECKREG r4, 0x00004444; + CHECKREG r5, 0x00005555; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass diff --git a/sim/testsuite/sim/bfin/c_progctrl_nop.s b/sim/testsuite/sim/bfin/c_progctrl_nop.s new file mode 100644 index 0000000..77f744b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_progctrl_nop.s @@ -0,0 +1,55 @@ +//Original:/testcases/core/c_progctrl_nop/c_progctrl_nop.dsp +// Spec Reference: progctrl nop +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + + +I0 = 0x1122 (Z); +NOP; +R0 = I0; + +I1 = 0x3344 (Z); +NOP; +R1 = I1; + +I2 = 0x5566 (Z); +NOP; +R2 = I2; + +I3 = 0x7788 (Z); +NOP; +R3 = I3; + + +P2 = 0x99aa (Z); +NOP; NOP; +R4 = P2; + +P3 = 0xbbcc (Z); +NOP; NOP; +R5 = P3; + +P4 = 0xddee (Z); +NOP; NOP; +R6 = P4; + +P5 = 0x1234 (Z); +NOP; NOP; +R7 = P5; + +CHECKREG r0, 0x00001122; +CHECKREG r1, 0x00003344; +CHECKREG r2, 0x00005566; +CHECKREG r3, 0x00007788; +CHECKREG r4, 0x000099AA; +CHECKREG r5, 0x0000BBCC; +CHECKREG r6, 0x0000DDEE; +CHECKREG r7, 0x00001234; + + +pass diff --git a/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S b/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S new file mode 100644 index 0000000..9444f5d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S @@ -0,0 +1,285 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_raise_rt_i_n/c_progctrl_raise_rt_i_n.dsp +// Spec Reference: progctrl raise rti rtn +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +CHECK_INIT(p5, 0xe0000000); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: + + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +RAISE 2; // RTN +RAISE 5; // RTI +RAISE 6; // RTI +RAISE 7; // RTI +RAISE 8; // RTI +RAISE 9; // RTI +RAISE 10; // RTI +RAISE 11; // RTI +RAISE 12; // RTI +RAISE 13; // RTI +RAISE 14; // RTI +RAISE 15; // RTI + +CHECKREG(r0, 0x0000000B); +CHECKREG(r1, 0x0000000C); +CHECKREG(r2, 0x0000000D); +CHECKREG(r3, 0x0000000E); +CHECKREG(r4, 0x00000007); +CHECKREG(r5, 0x00000008); +CHECKREG(r6, 0x00000009); +CHECKREG(r7, 0x0000000A); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +CHECKREG(r0, 0x00000002); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000005); +CHECKREG(r3, 0x00000006); +CHECKREG(r4, 0x00000007); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R0 = 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + R2 = 5; +RTI; + +THANDLE: // Timer Handler 6 + R3 = 6; +RTI; + +I7HANDLE: // IVG 7 Handler + R4 = 7; +RTI; + +I8HANDLE: // IVG 8 Handler + R5 = 8; +RTI; + +I9HANDLE: // IVG 9 Handler + R6 = 9; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_progctrl_rts.s b/sim/testsuite/sim/bfin/c_progctrl_rts.s new file mode 100644 index 0000000..3aa3bed --- /dev/null +++ b/sim/testsuite/sim/bfin/c_progctrl_rts.s @@ -0,0 +1,36 @@ +//Original:/proj/frio/dv/testcases/core/c_progctrl_rts/c_progctrl_rts.dsp +// Spec Reference: progctrl rts +# mach: bfin + +.include "testutils.inc" + start + + INIT_R_REGS 0; + + ASTAT = r0; + + loadsym R2, SUBR; + RETS = R2; + RTS; + +STOP: + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r4, 0x00004444; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000000; + + pass + +SUBR: // should jump here + loadsym R3, STOP; + RETS = R3; + R4.L = 0x4444; + RTS; + RETS = R3; + R5.L = 0x5555; // should not go here + RTS; + + fail diff --git a/sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s b/sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s new file mode 100644 index 0000000..2d27849 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s @@ -0,0 +1,163 @@ +//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_neg_pr/c_ptr2op_pr_neg_pr.dsp +// Spec Reference: ptr2op preg -= preg +# mach: bfin + +.include "testutils.inc" + start + +// check p-reg to p-reg move + imm32 p1, 0xf0021003; + imm32 p2, 0x2e041005; + imm32 p3, 0x20d61007; + imm32 p4, 0x200a1009; + imm32 p5, 0x200a300b; + imm32 sp, 0x200c180d; + imm32 fp, 0x200e109f; + P1 -= P1; + P2 -= P1; + P3 -= P1; + P4 -= P1; + P5 -= P1; + SP -= P1; + FP -= P1; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x2E041005; + CHECKREG p3, 0x20D61007; + CHECKREG p4, 0x200A1009; + CHECKREG p5, 0x200A300B; + CHECKREG sp, 0x200C180D; + CHECKREG fp, 0x200E109F; + + imm32 p1, 0x50021003; + imm32 p2, 0x26041005; + imm32 p3, 0x20761007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a900b; + imm32 sp, 0x200c1a0d; + imm32 fp, 0x200e10bf; + P1 -= P2; + P2 -= P2; + P3 -= P2; + P4 -= P2; + P5 -= P2; + SP -= P2; + FP -= P2; + CHECKREG p1, 0x29FDFFFE; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x20761007; + CHECKREG p4, 0x20081009; + CHECKREG p5, 0x200A900B; + CHECKREG sp, 0x200C1A0D; + CHECKREG fp, 0x200E10BF; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p3, 0x20061007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 sp, 0x200c100d; + imm32 fp, 0x200e100f; + P1 -= P3; + P2 -= P3; + P3 -= P3; + P4 -= P3; + P5 -= P3; + SP -= P3; + FP -= P3; + CHECKREG p1, 0xFFFBFFFC; + CHECKREG p2, 0xFFFDFFFE; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x20081009; + CHECKREG p5, 0x200A100B; + CHECKREG sp, 0x200C100D; + CHECKREG fp, 0x200E100F; + + imm32 p1, 0xa0021003; + imm32 p2, 0x2c041005; + imm32 p3, 0x20b61007; + imm32 p4, 0x200d1009; + imm32 p5, 0x200ae00b; + imm32 sp, 0x200c110d; + imm32 fp, 0x200e104f; + P1 -= P4; + P2 -= P4; + P3 -= P4; + P4 -= P4; + P5 -= P4; + SP -= P4; + FP -= P4; + CHECKREG p1, 0x7FF4FFFA; + CHECKREG p2, 0x0BF6FFFC; + CHECKREG p3, 0x00A8FFFE; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0x200AE00B; + CHECKREG sp, 0x200C110D; + CHECKREG fp, 0x200E104F; + + imm32 p1, 0x10021003; + imm32 p2, 0x22041005; + imm32 p3, 0x20361007; + imm32 p4, 0x20041009; + imm32 p5, 0x200aa00b; + imm32 sp, 0x200c1b0d; + imm32 fp, 0x200e10cf; + P1 -= P5; + P2 -= P5; + P3 -= P5; + P4 -= P5; + P5 -= P5; + SP -= P5; + FP -= P5; + CHECKREG p1, 0xEFF76FF8; + CHECKREG p2, 0x01F96FFA; + CHECKREG p3, 0x002B6FFC; + CHECKREG p4, 0xFFF96FFE; + CHECKREG p5, 0x00000000; + CHECKREG sp, 0x200C1B0D; + CHECKREG fp, 0x200E10CF; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p3, 0x20061007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 sp, 0x200c100d; + imm32 fp, 0x200e100f; + P1 -= SP; + P2 -= SP; + P3 -= SP; + P4 -= SP; + P5 -= SP; + SP -= SP; + FP -= SP; + CHECKREG p1, 0xFFF5FFF6; + CHECKREG p2, 0xFFF7FFF8; + CHECKREG p3, 0xFFF9FFFA; + CHECKREG p4, 0xFFFBFFFC; + CHECKREG p5, 0xFFFDFFFE; + CHECKREG sp, 0x00000000; + CHECKREG fp, 0x200E100F; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p3, 0x20061007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 sp, 0x200c100d; + imm32 fp, 0x200e100f; + P1 -= FP; + P2 -= FP; + P3 -= FP; + P4 -= FP; + P5 -= FP; + SP -= FP; + FP -= FP; + CHECKREG p1, 0xFFF3FFF4; + CHECKREG p2, 0xFFF5FFF6; + CHECKREG p3, 0xFFF7FFF8; + CHECKREG p4, 0xFFF9FFFA; + CHECKREG p5, 0xFFFBFFFC; + CHECKREG sp, 0xFFFDFFFE; + CHECKREG fp, 0x00000000; + + pass diff --git a/sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s b/sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s new file mode 100644 index 0000000..dabd216 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s @@ -0,0 +1,162 @@ +//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_sft_2_1/c_ptr2op_pr_sft_2_1.dsp +// Spec Reference: ptr2op preg = preg << 2 (>>2, >> 1) +# mach: bfin + +.include "testutils.inc" + start +// check p-reg to p-reg move + imm32 p1, 0xf0921203; + imm32 p2, 0xbe041305; + imm32 p3, 0xd0d61407; + imm32 p4, 0xa00a1089; + imm32 p5, 0x400a300b; + imm32 sp, 0xe07c180d; + imm32 fp, 0x206e109f; + P1 = P1 << 2; + P2 = P1 >> 2; + P3 = P1 << 2; + P4 = P1 >> 1; + P5 = P1 >> 2; + SP = P1 << 2; + FP = P1 >> 1; + CHECKREG p1, 0xC248480C; + CHECKREG p2, 0x30921203; + CHECKREG p3, 0x09212030; + CHECKREG p4, 0x61242406; + CHECKREG p5, 0x30921203; + CHECKREG sp, 0x09212030; + CHECKREG fp, 0x61242406; + + imm32 p1, 0x50021003; + imm32 p2, 0x26041005; + imm32 p3, 0x60761007; + imm32 p4, 0x20081009; + imm32 p5, 0xf00a900b; + imm32 sp, 0xb00c1a0d; + imm32 fp, 0x200e10bf; + P1 = P2; + P2 = P2; + P3 = P2; + P4 = P2; + P5 = P2; + SP = P2; + FP = P2; + CHECKREG p1, 0x26041005; + CHECKREG p2, 0x26041005; + CHECKREG p3, 0x26041005; + CHECKREG p4, 0x26041005; + CHECKREG p5, 0x26041005; + CHECKREG sp, 0x26041005; + CHECKREG fp, 0x26041005; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p3, 0x20061007; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 sp, 0x200c100d; + imm32 fp, 0x200e100f; + P1 = P3 << 2; + P2 = P3 >> 1; + P3 = P3 >> 2; + P4 = P3 << 2; + P5 = P3 << 2; + SP = P3 >> 1; + FP = P3 << 2; + CHECKREG p1, 0x8018401C; + CHECKREG p2, 0x10030803; + CHECKREG p3, 0x08018401; + CHECKREG p4, 0x20061004; + CHECKREG p5, 0x20061004; + CHECKREG sp, 0x0400C200; + CHECKREG fp, 0x20061004; + + imm32 p1, 0xa0021003; + imm32 p2, 0x2c041005; + imm32 p3, 0x40b61007; + imm32 p4, 0x250d1009; + imm32 p5, 0x260ae00b; + imm32 sp, 0x700c110d; + imm32 fp, 0x900e104f; + P1 = P4 >> 1; + P2 = P4 << 2; + P3 = P4 << 2; + P4 = P4 >> 2; + P5 = P4 << 2; + SP = P4 >> 2; + FP = P4 << 2; + CHECKREG p1, 0x12868804; + CHECKREG p2, 0x94344024; + CHECKREG p3, 0x94344024; + CHECKREG p4, 0x09434402; + CHECKREG p5, 0x250D1008; + CHECKREG sp, 0x0250D100; + CHECKREG fp, 0x250D1008; + + imm32 p1, 0x10021003; + imm32 p2, 0x22041005; + imm32 p3, 0x20361007; + imm32 p4, 0x20041009; + imm32 p5, 0x200aa00b; + imm32 sp, 0x200c1b0d; + imm32 fp, 0x200e10cf; + P1 = P5 << 2; + P2 = P5 >> 2; + P3 = P5 << 2; + P4 = P5 << 2; + P5 = P5 >> 1; + SP = P5 >> 2; + FP = P5 << 2; + CHECKREG p1, 0x802A802C; + CHECKREG p2, 0x0802A802; + CHECKREG p3, 0x802A802C; + CHECKREG p4, 0x802A802C; + CHECKREG p5, 0x10055005; + CHECKREG sp, 0x04015401; + CHECKREG fp, 0x40154014; + + imm32 p1, 0x50021003; + imm32 p2, 0x62041005; + imm32 p3, 0x70e61007; + imm32 p4, 0x290f1009; + imm32 p5, 0x700ab00b; + imm32 sp, 0x2a0c1d0d; + imm32 fp, 0xb00e1e0f; + P1 = SP << 2; + P2 = SP << 2; + P3 = SP >> 2; + P4 = SP << 2; + P5 = SP >> 2; + SP = SP >> 1; + FP = SP >> 2; + CHECKREG p1, 0xA8307434; + CHECKREG p2, 0xA8307434; + CHECKREG p3, 0x0A830743; + CHECKREG p4, 0xA8307434; + CHECKREG p5, 0x0A830743; + CHECKREG sp, 0x15060E86; + CHECKREG fp, 0x054183A1; + + imm32 p1, 0x32002003; + imm32 p2, 0x24004005; + imm32 p3, 0x20506007; + imm32 p4, 0x20068009; + imm32 p5, 0x200ae00b; + imm32 sp, 0x200c1f0d; + imm32 fp, 0x200e10bf; + P1 = FP >> 2; + P2 = FP >> 1; + P3 = FP << 2; + P4 = FP >> 2; + P5 = FP << 2; + SP = FP >> 2; + FP = FP << 2; + CHECKREG p1, 0x0803842F; + CHECKREG p2, 0x1007085F; + CHECKREG p3, 0x803842FC; + CHECKREG p4, 0x0803842F; + CHECKREG p5, 0x803842FC; + CHECKREG sp, 0x0803842F; + CHECKREG fp, 0x803842FC; + + pass diff --git a/sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s b/sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s new file mode 100644 index 0000000..dc6e2e8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s @@ -0,0 +1,167 @@ +//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_shadd_1_2/c_ptr2op_pr_shadd_1_2.dsp +// Spec Reference: ptr2op shadd preg, pregs, 1 (2) +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + +// check p-reg to p-reg move + + imm32 p1, 0xf0921203; + imm32 p2, 0xbe041305; + imm32 p3, 0xd0d61407; + imm32 p4, 0xa00a1089; + imm32 p5, 0x400a300b; + imm32 sp, 0xe07c180d; + imm32 fp, 0x206e109f; + P1 = ( P1 + P1 ) << 2; + P2 = ( P2 + P1 ) << 2; + P3 = ( P3 + P1 ) << 2; + P4 = ( P4 + P1 ) << 1; + P5 = ( P5 + P1 ) << 2; + SP = ( SP + P1 ) << 2; + FP = ( FP + P1 ) << 1; + CHECKREG p1, 0x84909018; + CHECKREG p2, 0x0A528C74; + CHECKREG p3, 0x559A907C; + CHECKREG p4, 0x49354142; + CHECKREG p5, 0x126B008C; + CHECKREG sp, 0x9432A094; + CHECKREG fp, 0x49FD416E; + + imm32 p1, 0x50021003; + imm32 p2, 0x26041005; + imm32 p3, 0x60761007; + imm32 p4, 0x20081009; + imm32 p5, 0xf00a900b; + imm32 sp, 0xb00c1a0d; + imm32 fp, 0x200e10bf; + P1 = ( P1 + P2 ) << 1; + P2 = ( P2 + P2 ) << 2; + P3 = ( P3 + P2 ) << 1; + P4 = ( P4 + P2 ) << 2; + P5 = ( P5 + P2 ) << 2; + SP = ( SP + P2 ) << 1; + FP = ( FP + P2 ) << 2; + CHECKREG p1, 0xEC0C4010; + CHECKREG p2, 0x30208028; + CHECKREG p3, 0x212D205E; + CHECKREG p4, 0x40A240C4; + CHECKREG p5, 0x80AC40CC; + CHECKREG sp, 0xC059346A; + CHECKREG fp, 0x40BA439C; + + imm32 p1, 0x30026003; + imm32 p2, 0x40051005; + imm32 p3, 0x20e65057; + imm32 p4, 0x2d081089; + imm32 p5, 0xf00ab07b; + imm32 sp, 0x200c1b0d; + imm32 fp, 0x200e100f; + P1 = ( P1 + P3 ) << 2; + P2 = ( P2 + P3 ) << 1; + P3 = ( P3 + P3 ) << 2; + P4 = ( P4 + P3 ) << 2; + P5 = ( P5 + P3 ) << 2; + SP = ( SP + P3 ) << 1; + FP = ( FP + P3 ) << 2; + CHECKREG p1, 0x43A2C168; + CHECKREG p2, 0xC1D6C0B8; + CHECKREG p3, 0x073282B8; + CHECKREG p4, 0xD0EA4D04; + CHECKREG p5, 0xDCF4CCCC; + CHECKREG sp, 0x4E7D3B8A; + CHECKREG fp, 0x9D024B1C; + + imm32 p1, 0xa0021003; + imm32 p2, 0x2c041005; + imm32 p3, 0x40b61007; + imm32 p4, 0x250d1009; + imm32 p5, 0x260ae00b; + imm32 sp, 0x700c110d; + imm32 fp, 0x900e104f; + P1 = ( P1 + P4 ) << 1; + P2 = ( P2 + P4 ) << 2; + P3 = ( P3 + P4 ) << 2; + P4 = ( P4 + P4 ) << 2; + P5 = ( P5 + P4 ) << 1; + SP = ( SP + P4 ) << 2; + FP = ( FP + P4 ) << 2; + CHECKREG p1, 0x8A1E4018; + CHECKREG p2, 0x44448038; + CHECKREG p3, 0x970C8040; + CHECKREG p4, 0x28688048; + CHECKREG p5, 0x9CE6C0A6; + CHECKREG sp, 0x61D24554; + CHECKREG fp, 0xE1DA425C; + + imm32 p1, 0xae021003; + imm32 p2, 0x22041705; + imm32 p3, 0x20361487; + imm32 p4, 0x90743009; + imm32 p5, 0xa60aa00b; + imm32 sp, 0xb00c1b0d; + imm32 fp, 0x200e10cf; + P1 = ( P1 + P5 ) << 2; + P2 = ( P2 + P5 ) << 2; + P3 = ( P3 + P5 ) << 2; + P4 = ( P4 + P5 ) << 2; + P5 = ( P5 + P5 ) << 1; + SP = ( SP + P5 ) << 2; + FP = ( FP + P5 ) << 2; + CHECKREG p1, 0x5032C038; + CHECKREG p2, 0x203ADC40; + CHECKREG p3, 0x1902D248; + CHECKREG p4, 0xD9FB4050; + CHECKREG p5, 0x982A802C; + CHECKREG sp, 0x20DA6CE4; + CHECKREG fp, 0xE0E243EC; + + imm32 p1, 0x50021003; + imm32 p2, 0x62041005; + imm32 p3, 0x70e61007; + imm32 p4, 0x290f1009; + imm32 p5, 0x700ab00b; + imm32 sp, 0x2a0c1d0d; + imm32 fp, 0xb00e1e0f; + P1 = ( P1 + SP ) << 2; + P2 = ( P2 + SP ) << 1; + P3 = ( P3 + SP ) << 2; + P4 = ( P4 + SP ) << 2; + P5 = ( P5 + SP ) << 2; + SP = ( SP + SP ) << 1; + FP = ( FP + SP ) << 2; + CHECKREG p1, 0xE838B440; + CHECKREG p2, 0x18205A24; + CHECKREG p3, 0x6BC8B450; + CHECKREG p4, 0x4C6CB458; + CHECKREG p5, 0x685B3460; + CHECKREG sp, 0xA8307434; + CHECKREG fp, 0x60FA490C; + + imm32 p1, 0x32002003; + imm32 p2, 0x24004005; + imm32 p3, 0xe0506007; + imm32 p4, 0xd0068009; + imm32 p5, 0x230ae00b; + imm32 sp, 0x205c1f0d; + imm32 fp, 0x200e10bf; + P1 = ( P1 + FP ) << 2; + P2 = ( P2 + FP ) << 1; + P3 = ( P3 + FP ) << 2; + P4 = ( P4 + FP ) << 2; + P5 = ( P5 + FP ) << 2; + SP = ( SP + FP ) << 2; + FP = ( FP + FP ) << 2; + CHECKREG p1, 0x4838C308; + CHECKREG p2, 0x881CA188; + CHECKREG p3, 0x0179C318; + CHECKREG p4, 0xC0524320; + CHECKREG p5, 0x0C63C328; + CHECKREG sp, 0x01A8BF30; + CHECKREG fp, 0x007085F8; + + pass diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s b/sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s new file mode 100644 index 0000000..5d7de57 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s @@ -0,0 +1,213 @@ +//Original:/testcases/core/c_pushpopmultiple_dp/c_pushpopmultiple_dp.dsp +// Spec Reference: pushpopmultiple dreg preg single group +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + + imm32 r0, 0x00000000; + ASTAT = r0; + + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + P1 = 0xa1 (X); + P2 = 0xa2 (X); + P3 = 0xa3 (X); + P4 = 0xa4 (X); + P5 = 0xa5 (X); + [ -- SP ] = ( R7:0 ); + [ -- SP ] = ( P5:1 ); + + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + + P2 = 0xb2 (X); + P3 = 0xb3 (X); + P4 = 0xb4 (X); + P5 = 0xb5 (X); + [ -- SP ] = ( R7:1 ); + [ -- SP ] = ( P5:2 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + + P3 = 0xc3 (X); + P4 = 0xc4 (X); + P5 = 0xc5 (X); + [ -- SP ] = ( R7:2 ); + [ -- SP ] = ( P5:3 ); + + R3 = 0x34; + R4 = 0x35; + R5 = 0x36; + R6 = 0x37; + R7 = 0x38; + + P4 = 0xd4 (X); + P5 = 0xd5 (X); + [ -- SP ] = ( R7:3 ); + [ -- SP ] = ( P5:4 ); + + R4 = 0x45 (X); + R5 = 0x46 (X); + R6 = 0x47 (X); + R7 = 0x48 (X); + P5 = 0xe5 (X); + [ -- SP ] = ( R7:4 ); + [ -- SP ] = ( P5:5 ); + + R5 = 0x56 (X); + R6 = 0x57 (X); + R7 = 0x58 (X); + [ -- SP ] = ( R7:5 ); + R6 = 0x67 (X); + R7 = 0x68 (X); + [ -- SP ] = ( R7:6 ); + R7 = 0x78 (X); + [ -- SP ] = ( R7:7 ); + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + P1 = 0; + P2 = 0; + P3 = 0; + P4 = 0; + P5 = 0; + ( R7:7 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000078; + + ( R7:6 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000067; + CHECKREG r7, 0x00000068; + + ( R7:5 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000057; + CHECKREG r7, 0x00000058; + + ( P5:5 ) = [ SP ++ ]; + ( R7:4 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0x000000e5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000046; + CHECKREG r6, 0x00000047; + CHECKREG r7, 0x00000048; + + ( P5:4 ) = [ SP ++ ]; + ( R7:3 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x000000d4; + CHECKREG p5, 0x000000d5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000035; + CHECKREG r5, 0x00000036; + CHECKREG r6, 0x00000037; + CHECKREG r7, 0x00000038; + + ( P5:3 ) = [ SP ++ ]; + ( R7:2 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000c4; + CHECKREG p5, 0x000000c5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000024; + CHECKREG r4, 0x00000025; + CHECKREG r5, 0x00000026; + CHECKREG r6, 0x00000027; + CHECKREG r7, 0x00000028; + + ( P5:2 ) = [ SP ++ ]; + ( R7:1 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000b3; + CHECKREG p4, 0x000000b4; + CHECKREG p5, 0x000000b5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000013; + CHECKREG r3, 0x00000014; + CHECKREG r4, 0x00000015; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000017; + CHECKREG r7, 0x00000018; + + ( P5:1 ) = [ SP ++ ]; + ( R7:0 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000a2; + CHECKREG p3, 0x000000a3; + CHECKREG p4, 0x000000a4; + CHECKREG p5, 0x000000a5; + + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000003; + CHECKREG r3, 0x00000004; + CHECKREG r4, 0x00000005; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000007; + CHECKREG r7, 0x00000008; + pass diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s b/sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s new file mode 100644 index 0000000..78dae01 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s @@ -0,0 +1,203 @@ +//Original:/testcases/core/c_pushpopmultiple_dp_pair/c_pushpopmultiple_dp_pair.dsp +// Spec Reference: pushpopmultiple dreg preg in group pair +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + + imm32 r0, 0x00000000; + ASTAT = r0; + + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + P1 = 0xa1 (X); + P2 = 0xa2 (X); + P3 = 0xa3 (X); + P4 = 0xa4 (X); + P5 = 0xa5 (X); + [ -- SP ] = ( R7:0, P5:1 ); + + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + + P2 = 0xb2 (X); + P3 = 0xb3 (X); + P4 = 0xb4 (X); + P5 = 0xb5 (X); + [ -- SP ] = ( R7:1, P5:2 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + + P3 = 0xc3 (X); + P4 = 0xc4 (X); + P5 = 0xc5 (X); + [ -- SP ] = ( R7:2, P5:3 ); + + R3 = 0x34; + R4 = 0x35; + R5 = 0x36; + R6 = 0x37; + R7 = 0x38; + + P4 = 0xd4 (X); + P5 = 0xd5 (X); + [ -- SP ] = ( R7:3, P5:4 ); + + R4 = 0x45 (X); + R5 = 0x46 (X); + R6 = 0x47 (X); + R7 = 0x48 (X); + P5 = 0xe5 (X); + [ -- SP ] = ( R7:4, P5:5 ); + + R5 = 0x56 (X); + R6 = 0x57 (X); + R7 = 0x58 (X); + [ -- SP ] = ( R7:5 ); + R6 = 0x67 (X); + R7 = 0x68 (X); + [ -- SP ] = ( R7:6 ); + R7 = 0x78 (X); + [ -- SP ] = ( R7:7 ); + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + P1 = 0; + P2 = 0; + P3 = 0; + P4 = 0; + P5 = 0; + ( R7:7 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + CHECKREG r7, 0x00000078; + + ( R7:6 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000067; + CHECKREG r7, 0x00000068; + + ( R7:5 ) = [ SP ++ ]; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000057; + CHECKREG r7, 0x00000058; + + ( R7:4, P5:5 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x00000000; + CHECKREG p5, 0x000000e5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000046; + CHECKREG r6, 0x00000047; + CHECKREG r7, 0x00000048; + + ( R7:3, P5:4 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x00000000; + CHECKREG p4, 0x000000d4; + CHECKREG p5, 0x000000d5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000000; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000035; + CHECKREG r5, 0x00000036; + CHECKREG r6, 0x00000037; + CHECKREG r7, 0x00000038; + + ( R7:2, P5:3 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x00000000; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000c4; + CHECKREG p5, 0x000000c5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000000; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000024; + CHECKREG r4, 0x00000025; + CHECKREG r5, 0x00000026; + CHECKREG r6, 0x00000027; + CHECKREG r7, 0x00000028; + + ( R7:1, P5:2 ) = [ SP ++ ]; + CHECKREG p1, 0x00000000; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000b3; + CHECKREG p4, 0x000000b4; + CHECKREG p5, 0x000000b5; + + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000013; + CHECKREG r3, 0x00000014; + CHECKREG r4, 0x00000015; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000017; + CHECKREG r7, 0x00000018; + + ( R7:0, P5:1 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000a2; + CHECKREG p3, 0x000000a3; + CHECKREG p4, 0x000000a4; + CHECKREG p5, 0x000000a5; + + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000003; + CHECKREG r3, 0x00000004; + CHECKREG r4, 0x00000005; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000007; + CHECKREG r7, 0x00000008; + pass diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s b/sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s new file mode 100644 index 0000000..ca1ebf1 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s @@ -0,0 +1,173 @@ +//Original:/testcases/core/c_pushpopmultiple_dreg/c_pushpopmultiple_dreg.dsp +// Spec Reference: pushpopmultiple dreg +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + + imm32 r0, 0x00000000; + ASTAT = r0; + + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:0 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000002; + CHECKREG r2, 0x00000003; + CHECKREG r3, 0x00000004; + CHECKREG r4, 0x00000005; + CHECKREG r5, 0x00000006; + CHECKREG r6, 0x00000007; + CHECKREG r7, 0x00000008; + + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + [ -- SP ] = ( R7:1 ); + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:1 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000013; + CHECKREG r3, 0x00000014; + CHECKREG r4, 0x00000015; + CHECKREG r5, 0x00000016; + CHECKREG r6, 0x00000017; + CHECKREG r7, 0x00000018; + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + [ -- SP ] = ( R7:2 ); + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:2 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000024; + CHECKREG r4, 0x00000025; + CHECKREG r5, 0x00000026; + CHECKREG r6, 0x00000027; + CHECKREG r7, 0x00000028; + + R3 = 0x34; + R4 = 0x35; + R5 = 0x36; + R6 = 0x37; + R7 = 0x38; + [ -- SP ] = ( R7:3 ); + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:3 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000035; + CHECKREG r5, 0x00000036; + CHECKREG r6, 0x00000037; + CHECKREG r7, 0x00000038; + + R4 = 0x45 (X); + R5 = 0x46 (X); + R6 = 0x47 (X); + R7 = 0x48 (X); + [ -- SP ] = ( R7:4 ); + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:4 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000046; + CHECKREG r6, 0x00000047; + CHECKREG r7, 0x00000048; + + R5 = 0x56 (X); + R6 = 0x57 (X); + R7 = 0x58 (X); + [ -- SP ] = ( R7:5 ); + R5 = 0; + R6 = 0; + R7 = 0; + ( R7:5 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000057; + CHECKREG r7, 0x00000058; + + R6 = 0x67 (X); + R7 = 0x68 (X); + [ -- SP ] = ( R7:6 ); + R6 = 0; + R7 = 0; + ( R7:6 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000067; + CHECKREG r7, 0x00000068; + + R7 = 0x78 (X); + [ -- SP ] = ( R7:7 ); + R7 = 0; + ( R7:7 ) = [ SP ++ ]; + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000012; + CHECKREG r2, 0x00000023; + CHECKREG r3, 0x00000034; + CHECKREG r4, 0x00000045; + CHECKREG r5, 0x00000056; + CHECKREG r6, 0x00000067; + CHECKREG r7, 0x00000078; + + pass diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s b/sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s new file mode 100644 index 0000000..15c1937 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s @@ -0,0 +1,83 @@ +//Original:/testcases/core/c_pushpopmultiple_preg/c_pushpopmultiple_preg.dsp +// Spec Reference: pushpopmultiple preg +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + + imm32 r0, 0x00000000; + ASTAT = r0; + + P1 = 0xa1 (X); + P2 = 0xa2 (X); + P3 = 0xa3 (X); + P4 = 0xa4 (X); + P5 = 0xa5 (X); + [ -- SP ] = ( P5:1 ); + P1 = 0; + P2 = 0; + P3 = 0; + P4 = 0; + P5 = 0; + ( P5:1 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000a2; + CHECKREG p3, 0x000000a3; + CHECKREG p4, 0x000000a4; + CHECKREG p5, 0x000000a5; + + P2 = 0xb2 (X); + P3 = 0xb3 (X); + P4 = 0xb4 (X); + P5 = 0xb5 (X); + [ -- SP ] = ( P5:2 ); + P2 = 0; + P3 = 0; + P4 = 0; + P5 = 0; + ( P5:2 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000b3; + CHECKREG p4, 0x000000b4; + CHECKREG p5, 0x000000b5; + + P3 = 0xc3 (X); + P4 = 0xc4 (X); + P5 = 0xc5 (X); + [ -- SP ] = ( P5:3 ); + P3 = 0; + P4 = 0; + P5 = 0; + ( P5:3 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000c4; + CHECKREG p5, 0x000000c5; + + P4 = 0xd4 (X); + P5 = 0xd5 (X); + [ -- SP ] = ( P5:4 ); + P4 = 0; + P5 = 0; + ( P5:4 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000d4; + CHECKREG p5, 0x000000d5; + + P5 = 0xe5 (X); + [ -- SP ] = ( P5:5 ); + P5 = 0; + ( P5:5 ) = [ SP ++ ]; + CHECKREG p1, 0x000000a1; + CHECKREG p2, 0x000000b2; + CHECKREG p3, 0x000000c3; + CHECKREG p4, 0x000000d4; + CHECKREG p5, 0x000000e5; + + pass diff --git a/sim/testsuite/sim/bfin/c_regmv_acc_acc.s b/sim/testsuite/sim/bfin/c_regmv_acc_acc.s new file mode 100644 index 0000000..08e4414 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_acc_acc.s @@ -0,0 +1,125 @@ +//Original:/testcases/core/c_regmv_acc_acc/c_regmv_acc_acc.dsp +// Spec Reference: regmv acc-acc +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0xa9627911; + imm32 r1, 0xd0158978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0x0004000d; + imm32 r7, 0x000e500f; + A0 = R0; + + A1 = A0; + R2 = A1.w; + R3 = A1.x; + + A1.x = A0.w; + A1.w = A0.w; + A0.x = A0.w; + A0.w = A0.w; + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + + CHECKREG r0, 0xA9627911; + CHECKREG r1, 0xD0158978; + CHECKREG r2, 0xA9627911; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r4, 0xA9627911; + CHECKREG r5, 0x00000011; + CHECKREG r6, 0xA9627911; + CHECKREG r7, 0x00000011; + + imm32 r0, 0x90ba7911; + imm32 r1, 0xe3458978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x56080009; + imm32 r5, 0x783a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x489e534f; + A1 = R0; + + A0 = A1; + R2 = A0.w; + R3 = A0.x; + + A0.x = A1.w; + A0.w = A1.w; + A1.x = A1.w; + A1.w = A1.w; + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + CHECKREG r0, 0x90BA7911; + CHECKREG r1, 0xE3458978; + CHECKREG r2, 0x90BA7911; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r4, 0x90BA7911; + CHECKREG r5, 0x00000011; + CHECKREG r6, 0x90BA7911; + CHECKREG r7, 0x00000011; + + imm32 r0, 0xf9627911; + imm32 r1, 0xd0158978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x789e534f; + A0 = R0; + + A0.x = A0.x; + A0.w = A0.x; + A1.w = A0.x; + A1.x = A0.x; + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + CHECKREG r0, 0xF9627911; + CHECKREG r1, 0xD0158978; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x10060007; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0xFFFFFFFF; + + imm32 r0, 0x90ba7911; + imm32 r1, 0xe3458978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x56080009; + imm32 r5, 0x783a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x489e534f; + A1 = R0; + + A0.x = A1.x; + A0.w = A1.x; + A1.w = A1.x; + A1.x = A1.x; + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + CHECKREG r0, 0x90BA7911; + CHECKREG r1, 0xE3458978; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x10060007; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0xFFFFFFFF; + + pass diff --git a/sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s b/sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s new file mode 100644 index 0000000..fb95a73 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s @@ -0,0 +1,148 @@ +//Original:/testcases/core/c_regmv_dag_lz_dep/c_regmv_dag_lz_dep.dsp +// Spec Reference: regmv dag lz dep forward +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +imm32 r0, 0x11111111; +imm32 r1, 0x22223331; +imm32 r2, 0x44445551; +imm32 r3, 0x66667771; +imm32 r4, 0x88889991; +imm32 r5, 0xaaaabbb1; +imm32 r6, 0xccccddd1; +imm32 r7, 0xeeeefff1; + +I0 = R0; +I0 = 0x1122 (Z); +R0 = I0; + +I1 = R1; +I1 = 0x3344 (Z); +R1 = I1; + +I2 = R2; +I2 = 0x5566 (Z); +R2 = I2; + +I3 = R3; +I3 = 0x7788 (Z); +R3 = I3; + + +B0 = R4; +B0 = 0x99aa (Z); +R4 = B0; + +B1 = R5; +B1 = 0xbbcc (Z); +R5 = B1; + +B2 = R6; +B2 = 0xddee (Z); +R6 = B2; + +B3 = R7; +B3 = 0xff01 (Z); +R7 = B3; + +CHECKREG r0, 0x00001122; +CHECKREG r1, 0x00003344; +CHECKREG r2, 0x00005566; +CHECKREG r3, 0x00007788; +CHECKREG r4, 0x000099AA; +CHECKREG r5, 0x0000BBCC; +CHECKREG r6, 0x0000DDEE; +CHECKREG r7, 0x0000FF01; + +imm32 r0, 0x11111112; +imm32 r1, 0x22223332; +imm32 r2, 0x44445552; +imm32 r3, 0x66667772; +imm32 r4, 0x88889992; +imm32 r5, 0xaaaabbb2; +imm32 r6, 0xccccddd2; +imm32 r7, 0xeeeefff2; +M0 = R0; +M0 = 0xa1a2 (Z); +R0 = M0; + +M1 = R1; +M1 = 0xb1b2 (Z); +R1 = M1; + +M2 = R2; +M2 = 0xc1c2 (Z); +R2 = M2; + +M3 = R3; +M3 = 0xd1d2 (Z); +R3 = M3; + + +L0 = R4; +L0 = 0xe1e2 (Z); +R4 = L0; + +L1 = R5; +L1 = 0xf1f2 (Z); +R5 = L1; + +L2 = R6; +L2 = 0x1112 (Z); +R6 = L2; + +L3 = R7; +L3 = 0x2122 (Z); +R7 = L3; + +CHECKREG r0, 0x0000A1A2; +CHECKREG r1, 0x0000B1B2; +CHECKREG r2, 0x0000C1C2; +CHECKREG r3, 0x0000D1D2; +CHECKREG r4, 0x0000E1E2; +CHECKREG r5, 0x0000F1F2; +CHECKREG r6, 0x00001112; +CHECKREG r7, 0x00002122; + +imm32 r0, 0x11111113; +imm32 r1, 0x22223333; +imm32 r2, 0x44445553; +imm32 r3, 0x66667773; +imm32 r4, 0x88889993; +imm32 r5, 0xaaaabbb3; +imm32 r6, 0xccccddd3; +imm32 r7, 0xeeeefff3; + +P1 = R1; +P1 = 0x3A3B (Z); +R1 = P1; + + +P2 = R2; +P2 = 0x4A4B (Z); +R2 = P2; + +P3 = R3; +P3 = 0x5A5B (Z); +R3 = P3; + +P4 = R4; +P4 = 0x6A6B (Z); +R4 = P4; + +P5 = R5; +P5 = 0x7A7B (Z); +R5 = P5; + +CHECKREG r1, 0x00003A3B; +CHECKREG r2, 0x00004A4B; +CHECKREG r3, 0x00005A5B; +CHECKREG r4, 0x00006A6B; +CHECKREG r5, 0x00007A7B; + +pass diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s b/sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s new file mode 100644 index 0000000..6af3d04 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s @@ -0,0 +1,191 @@ +//Original:/testcases/core/c_regmv_dr_acc_acc/c_regmv_dr_acc_acc.dsp +// Spec Reference: regmv dreg-acc-acc +# mach: bfin + +.include "testutils.inc" + start + + + +// check R-reg to ACC + imm32 r0, 0x00000000; + imm32 r1, 0x12345678; + imm32 r2, 0x91234567; + imm32 r3, 0x00060007; + imm32 r4, 0x00080009; + imm32 r5, 0x000a000b; + imm32 r6, 0x000c000d; + imm32 r7, 0x000e000f; + A0 = R0; + A1 = R0; + A0 = R1; + A1 = R2; + + R3 = A0.w; + R4 = A0.x; + R5 = A1.w; + R6 = A1.x; + CHECKREG r0, 0x00000000; + CHECKREG r1, 0x12345678; + CHECKREG r2, 0x91234567; + CHECKREG r3, 0x12345678; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x91234567; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0x000E000F; + + A1 = A0 = 0; + R3 = A0.w; + R4 = A0.x; + R5 = A1.w; + R6 = A1.x; + CHECKREG r3, 0x00000000; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x00000000; + + imm32 r0, 0xa5678901; + imm32 r1, 0xb0158978; + imm32 r2, 0x91234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0x0004000d; + imm32 r7, 0x000e500f; + A0 = R0; + A1 = R1; + + R3 = A0.w; + R4 = A0.x; + R5 = A1.w; + R6 = A1.x; + CHECKREG r0, 0xA5678901; + CHECKREG r1, 0xB0158978; + CHECKREG r2, 0x91234567; + CHECKREG r3, 0xA5678901; + CHECKREG r4, 0xFFFFFFFF; + CHECKREG r5, 0xB0158978; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0x000E500F; + + imm32 r0, 0xe9627911; + imm32 r1, 0xd0158978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0x0004000d; + imm32 r7, 0x000e500f; + A0 = R0; + A1 = A0; + + imm32 r0, 0x90ba7911; + imm32 r1, 0xe3458978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x56080009; + imm32 r5, 0x783a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x489e534f; + A0.w = R0; + A0.x = R1; + A1.w = R2; + A1.x = R3; + + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + + CHECKREG r0, 0x90BA7911; + CHECKREG r1, 0xE3458978; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x10060007; + CHECKREG r4, 0x90BA7911; + CHECKREG r5, 0x00000078; + CHECKREG r6, 0xC1234567; + CHECKREG r7, 0x00000007; + + R3 = A0.w; + R4 = A0.x; + R5 = A1.w; + R6 = A1.x; + CHECKREG r0, 0x90BA7911; + CHECKREG r1, 0xE3458978; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x90BA7911; + CHECKREG r4, 0x00000078; + CHECKREG r5, 0xC1234567; + CHECKREG r6, 0x00000007; + CHECKREG r7, 0x00000007; + + imm32 r0, 0xf9627911; + imm32 r1, 0xd0158978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x02080009; + imm32 r5, 0x003a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x789e534f; + A0 = R6; + A1.w = A0.w; + A1.x = A0.x; + + R0 = A0.w; + R1 = A0.x; + R2 = A1.w; + R3 = A1.x; + + A1 = R7; + A0.w = A1.w; + A0.x = A1.x; + + R4 = A0.w; + R5 = A0.x; + R6 = A1.w; + R7 = A1.x; + + CHECKREG r0, 0xF247890D; + CHECKREG r1, 0xFFFFFFFF; + CHECKREG r2, 0xF247890D; + CHECKREG r3, 0xFFFFFFFF; + CHECKREG r4, 0x789E534F; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0x789E534F; + CHECKREG r7, 0x00000000; + + imm32 r0, 0x90ba7911; + imm32 r1, 0xe3458978; + imm32 r2, 0xc1234567; + imm32 r3, 0x10060007; + imm32 r4, 0x56080009; + imm32 r5, 0x783a000b; + imm32 r6, 0xf247890d; + imm32 r7, 0x489e534f; + A0.w = A1.x; + A0.x = A1.x; + R4 = A0.w; + R5 = A0.x; + + A0 = R2; + A1.w = A0.x; + A1.x = A0.x; + + R6 = A1.w; + R7 = A1.x; + + A0.x = A1.w; + A1.x = A0.w; + R0 = A0.x; + R1 = A1.x; + + CHECKREG r0, 0xFFFFFFFF; + CHECKREG r1, 0x00000067; + CHECKREG r2, 0xC1234567; + CHECKREG r3, 0x10060007; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x00000000; + CHECKREG r6, 0xFFFFFFFF; + CHECKREG r7, 0xFFFFFFFF; + + pass diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s b/sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s new file mode 100644 index 0000000..118274d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s @@ -0,0 +1,245 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_dr_dep_nostall/c_regmv_dr_dep_nostall.dsp +// Spec Reference: regmv dr-dep no stall +# mach: bfin + +.include "testutils.inc" + start + + imm32 r0, 0x00000001; + imm32 r1, 0x00110001; + imm32 r2, 0x00220002; + imm32 r3, 0x00330003; + imm32 r4, 0x00440004; + imm32 r5, 0x00550005; + imm32 r6, 0x00660006; + imm32 r7, 0x00770007; +// R-reg to R-reg: no stall + R0 = R0; + R1 = R0; + R2 = R1; + R3 = R2; + R4 = R3; + R5 = R4; + R6 = R5; + R7 = R6; + R0 = R7; + + CHECKREG r0, 0x00000001; + CHECKREG r1, 0x00000001; + CHECKREG r2, 0x00000001; + CHECKREG r3, 0x00000001; + CHECKREG r4, 0x00000001; + CHECKREG r5, 0x00000001; + CHECKREG r6, 0x00000001; + CHECKREG r7, 0x00000001; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22223333; + imm32 p2, 0x44445555; + imm32 p3, 0x66667777; + imm32 p4, 0x88889999; + imm32 p5, 0xaaaabbbb; + imm32 fp, 0xccccdddd; + imm32 sp, 0xeeeeffff; + +// P-reg to R-reg to I,M reg: no stall + R0 = P0; + I0 = R0; + R1 = P1; + I1 = R1; + R2 = P2; + I2 = R2; + R3 = P3; + I3 = R3; + R4 = P4; + M0 = R4; + R5 = P5; + M1 = R5; + R6 = FP; + M2 = R6; + R7 = SP; + M3 = R7; + + CHECKREG r1, 0x22223333; + CHECKREG r2, 0x44445555; + CHECKREG r3, 0x66667777; + CHECKREG r4, 0x88889999; + CHECKREG r5, 0xAAAABBBB; + CHECKREG r6, 0xCCCCDDDD; + CHECKREG r7, 0xEEEEFFFF; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0xEEEEFFFF; + CHECKREG r1, 0xCCCCDDDD; + CHECKREG r2, 0xAAAABBBB; + CHECKREG r3, 0x88889999; + CHECKREG r4, 0x66667777; + CHECKREG r5, 0x44445555; + CHECKREG r6, 0x22223333; + + imm32 i0, 0x00001111; + imm32 i1, 0x22223333; + imm32 i2, 0x44445555; + imm32 i3, 0x66667777; + imm32 m0, 0x88889999; + imm32 m0, 0xaaaabbbb; + imm32 m0, 0xccccdddd; + imm32 m0, 0xeeeeffff; + +// I,M-reg to R-reg to P-reg: no stall + R0 = I0; + P1 = R0; + R1 = I1; + P1 = R1; + R2 = I2; + P2 = R2; + R3 = I3; + P3 = R3; + R4 = M0; + P4 = R4; + R5 = M1; + P5 = R5; + R6 = M2; + SP = R6; + R7 = M3; + FP = R7; + + CHECKREG p1, 0x22223333; + CHECKREG p2, 0x44445555; + CHECKREG p3, 0x66667777; + CHECKREG p4, 0xEEEEFFFF; + CHECKREG p5, 0xAAAABBBB; + CHECKREG sp, 0xCCCCDDDD; + CHECKREG fp, 0xEEEEFFFF; + + imm32 i0, 0x10001111; + imm32 i1, 0x12221333; + imm32 i2, 0x14441555; + imm32 i3, 0x16661777; + imm32 m0, 0x18881999; + imm32 m1, 0x1aaa1bbb; + imm32 m2, 0x1ccc1ddd; + imm32 m3, 0x1eee1fff; + +// I,M-reg to R-reg to L,B reg: no stall + R0 = I0; + L0 = R0; + R1 = I1; + L1 = R1; + R2 = I2; + L2 = R2; + R3 = I3; + L3 = R3; + R4 = M0; + B0 = R4; + R5 = M1; + B1 = R5; + R6 = M2; + B2 = R6; + R7 = M3; + B3 = R7; + + CHECKREG r0, 0x10001111; + CHECKREG r1, 0x12221333; + CHECKREG r2, 0x14441555; + CHECKREG r3, 0x16661777; + CHECKREG r4, 0x18881999; + CHECKREG r5, 0x1AAA1BBB; + CHECKREG r6, 0x1CCC1DDD; + CHECKREG r7, 0x1EEE1FFF; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x16661777; + CHECKREG r1, 0x14441555; + CHECKREG r2, 0x12221333; + CHECKREG r3, 0x10001111; + CHECKREG r4, 0x1EEE1FFF; + CHECKREG r5, 0x1CCC1DDD; + CHECKREG r6, 0x1AAA1BBB; + CHECKREG r7, 0x18881999; + + imm32 l0, 0x20003111; + imm32 l1, 0x22223333; + imm32 l2, 0x24443555; + imm32 l3, 0x26663777; + imm32 b0, 0x28883999; + imm32 b0, 0x2aaa3bbb; + imm32 b0, 0x2ccc3ddd; + imm32 b0, 0x2eee3fff; + +// L,B-reg to R-reg to I,M reg: no stall + R0 = L0; + I0 = R0; + R1 = L1; + I1 = R1; + R2 = L2; + I2 = R2; + R3 = L3; + I3 = R3; + R4 = B0; + M0 = R4; + R5 = B1; + M1 = R5; + R6 = B2; + M2 = R6; + R7 = B3; + M3 = R7; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x1EEE1FFF; + CHECKREG r1, 0x1CCC1DDD; + CHECKREG r2, 0x1AAA1BBB; + CHECKREG r3, 0x2EEE3FFF; + CHECKREG r4, 0x26663777; + CHECKREG r5, 0x24443555; + CHECKREG r6, 0x22223333; + CHECKREG r7, 0x20003111; + + imm32 r0, 0x00000030; + imm32 r1, 0x00000031; + imm32 r2, 0x00000003; + imm32 r3, 0x00330003; + imm32 r4, 0x00440004; + imm32 r5, 0x00550005; + imm32 r6, 0x00660006; + imm32 r7, 0x00770007; + +// R-reg to R-reg to sysreg to Reg: no stall + R3 = R0; + ASTAT = R3; + R6 = ASTAT; + R4 = R1; + RETS = R4; + R7 = RETS; + + CHECKREG r0, 0x00000030; + CHECKREG r1, 0x00000031; + CHECKREG r2, 0x00000003; + CHECKREG r3, 0x00000030; + CHECKREG r4, 0x00000031; + CHECKREG r5, 0x00550005; + CHECKREG r6, 0x00000030; + CHECKREG r7, 0x00000031; + + pass diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_dr.s b/sim/testsuite/sim/bfin/c_regmv_dr_dr.s new file mode 100644 index 0000000..e1fb658 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_dr_dr.s @@ -0,0 +1,209 @@ +//Original:/testcases/core/c_regmv_dr_dr/c_regmv_dr_dr.dsp +// Spec Reference: regmv dreg-to-dreg +# mach: bfin + +.include "testutils.inc" + start + +// check R-reg to R-reg move +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R0; +R1 = R0; +R2 = R0; +R3 = R0; +R4 = R0; +R5 = R0; +R6 = R0; +R7 = R0; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R1; +R1 = R1; +R2 = R1; +R3 = R1; +R4 = R1; +R5 = R1; +R6 = R1; +R7 = R1; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R2; +R1 = R2; +R2 = R2; +R3 = R2; +R4 = R2; +R5 = R2; +R6 = R2; +R7 = R2; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R3; +R1 = R3; +R2 = R3; +R3 = R3; +R4 = R3; +R5 = R3; +R6 = R3; +R7 = R3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R4; +R1 = R4; +R2 = R4; +R3 = R4; +R4 = R4; +R5 = R4; +R6 = R4; +R7 = R4; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R5; +R1 = R5; +R2 = R5; +R3 = R5; +R4 = R5; +R5 = R5; +R6 = R5; +R7 = R5; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R6; +R1 = R6; +R2 = R6; +R3 = R6; +R4 = R6; +R5 = R6; +R6 = R6; +R7 = R6; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +R0 = R7; +R1 = R7; +R2 = R7; +R3 = R7; +R4 = R7; +R5 = R7; +R6 = R7; +R7 = R7; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + +pass diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_imlb.s b/sim/testsuite/sim/bfin/c_regmv_dr_imlb.s new file mode 100644 index 0000000..01650b0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_dr_imlb.s @@ -0,0 +1,539 @@ +//Original:/testcases/core/c_regmv_dr_imlb/c_regmv_dr_imlb.dsp +// Spec Reference: regmv dreg-to-imlb +# mach: bfin + +.include "testutils.inc" + start + +// check DR-reg to imlb-reg move +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R0; +I1 = R0; +I2 = R0; +I3 = R0; +M0 = R0; +M1 = R0; +M2 = R0; +M3 = R0; + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R1; +I1 = R1; +I2 = R1; +I3 = R1; +M0 = R1; +M1 = R1; +M2 = R1; +M3 = R1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R2; +I1 = R2; +I2 = R2; +I3 = R2; +M0 = R2; +M1 = R2; +M2 = R2; +M3 = R2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R3; +I1 = R3; +I2 = R3; +I3 = R3; +M0 = R3; +M1 = R3; +M2 = R3; +M3 = R3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R4; +I1 = R4; +I2 = R4; +I3 = R4; +M0 = R4; +M1 = R4; +M2 = R4; +M3 = R4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R5; +I1 = R5; +I2 = R5; +I3 = R5; +M0 = R5; +M1 = R5; +M2 = R5; +M3 = R5; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R6; +I1 = R6; +I2 = R6; +I3 = R6; +M0 = R6; +M1 = R6; +M2 = R6; +M3 = R6; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +I0 = R7; +I1 = R7; +I2 = R7; +I3 = R7; +M0 = R7; +M1 = R7; +M2 = R7; +M3 = R7; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R0; +L1 = R0; +L2 = R0; +L3 = R0; +B0 = R0; +B1 = R0; +B2 = R0; +B3 = R0; + +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00000001; +CHECKREG r1, 0x00000001; +CHECKREG r2, 0x00000001; +CHECKREG r3, 0x00000001; +CHECKREG r4, 0x00000001; +CHECKREG r5, 0x00000001; +CHECKREG r6, 0x00000001; +CHECKREG r7, 0x00000001; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R1; +L1 = R1; +L2 = R1; +L3 = R1; +B0 = R1; +B1 = R1; +B2 = R1; +B3 = R1; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R2; +L1 = R2; +L2 = R2; +L3 = R2; +B0 = R2; +B1 = R2; +B2 = R2; +B3 = R2; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R3; +L1 = R3; +L2 = R3; +L3 = R3; +B0 = R3; +B1 = R3; +B2 = R3; +B3 = R3; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R4; +L1 = R4; +L2 = R4; +L3 = R4; +B0 = R4; +B1 = R4; +B2 = R4; +B3 = R4; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R5; +L1 = R5; +L2 = R5; +L3 = R5; +B0 = R5; +B1 = R5; +B2 = R5; +B3 = R5; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R6; +L1 = R6; +L2 = R6; +L3 = R6; +B0 = R6; +B1 = R6; +B2 = R6; +B3 = R6; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; +L0 = R7; +L1 = R7; +L2 = R7; +L3 = R7; +B0 = R7; +B1 = R7; +B2 = R7; +B3 = R7; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + +pass diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_pr.s b/sim/testsuite/sim/bfin/c_regmv_dr_pr.s new file mode 100644 index 0000000..fd8967c --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_dr_pr.s @@ -0,0 +1,107 @@ +//Original:/testcases/core/c_regmv_dr_pr/c_regmv_dr_pr.dsp +// Spec Reference: regmv dreg-to-preg +# mach: bfin + +.include "testutils.inc" + start + +// check R-reg to R-reg move + imm32 r0, 0x20001001; + imm32 r1, 0x20021003; + imm32 r2, 0x20041005; + imm32 r3, 0x20061007; + imm32 r4, 0x20081009; + imm32 r5, 0x200a100b; + imm32 r6, 0x200c100d; + imm32 r7, 0x200e100f; + + P1 = R0; + P2 = R0; + P4 = R0; + P5 = R0; + FP = R0; + CHECKREG p1, 0x20001001; + CHECKREG p2, 0x20001001; + CHECKREG p4, 0x20001001; + CHECKREG p5, 0x20001001; + CHECKREG fp, 0x20001001; + + P1 = R1; + P2 = R1; + P4 = R1; + P5 = R1; + FP = R1; + CHECKREG p1, 0x20021003; + CHECKREG p2, 0x20021003; + CHECKREG p4, 0x20021003; + CHECKREG p5, 0x20021003; + CHECKREG fp, 0x20021003; + + P1 = R2; + P2 = R2; + P4 = R2; + P5 = R2; + FP = R2; + CHECKREG p1, 0x20041005; + CHECKREG p2, 0x20041005; + CHECKREG p4, 0x20041005; + CHECKREG p5, 0x20041005; + CHECKREG fp, 0x20041005; + + P1 = R3; + P2 = R3; + P4 = R3; + P5 = R3; + FP = R3; + CHECKREG p1, 0x20061007; + CHECKREG p2, 0x20061007; + CHECKREG p4, 0x20061007; + CHECKREG p5, 0x20061007; + CHECKREG fp, 0x20061007; + + P1 = R4; + P2 = R4; + P4 = R4; + P5 = R4; + FP = R4; + CHECKREG p1, 0x20081009; + CHECKREG p2, 0x20081009; + CHECKREG p4, 0x20081009; + CHECKREG p5, 0x20081009; + CHECKREG fp, 0x20081009; + + P1 = R5; + P2 = R5; + P4 = R5; + P5 = R5; + FP = R5; + CHECKREG p1, 0x200a100b; + CHECKREG p2, 0x200a100b; + CHECKREG p4, 0x200a100b; + CHECKREG p5, 0x200a100b; + CHECKREG fp, 0x200a100b; + + P1 = R6; + P2 = R6; + P4 = R6; + P5 = R6; + FP = R6; + CHECKREG p1, 0x200c100d; + CHECKREG p2, 0x200c100d; + CHECKREG p4, 0x200c100d; + CHECKREG p5, 0x200c100d; + CHECKREG fp, 0x200c100d; + + P1 = R7; + P2 = R7; + P4 = R7; + P5 = R7; + FP = R7; + CHECKREG p1, 0x200e100f; + CHECKREG p2, 0x200e100f; + CHECKREG p4, 0x200e100f; + CHECKREG p5, 0x200e100f; + CHECKREG fp, 0x200e100f; + +End: + pass diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s b/sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s new file mode 100644 index 0000000..cda1fb1 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s @@ -0,0 +1,664 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_nostall/c_regmv_imlb_dep_nostall.dsp +// Spec Reference: regmv imlb-dep no stall +# mach: bfin + +.include "testutils.inc" + start + +// P-reg to I,M-reg to R-reg: no stall +//imm32 p0, 0x00001111; + imm32 p1, 0x12213330; + imm32 p2, 0x14415550; + imm32 p3, 0x16617770; + imm32 p4, 0x18819990; + imm32 p5, 0x1aa1bbb0; + imm32 fp, 0x1cc1ddd0; + imm32 sp, 0x1ee1fff0; + I0 = P0; + R0 = I0; + I1 = P1; + R1 = I1; + I2 = P2; + R2 = I2; + I3 = P3; + R3 = I3; + M0 = P4; + R4 = M0; + M1 = P5; + R5 = M1; + M2 = SP; + R6 = M2; + M3 = FP; + R7 = M3; + + CHECKREG r1, 0x12213330; + CHECKREG r2, 0x14415550; + CHECKREG r3, 0x16617770; + CHECKREG r4, 0x18819990; + CHECKREG r5, 0x1aa1bbb0; + CHECKREG r6, 0x1EE1FFF0; + CHECKREG r7, 0x1CC1DDD0; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x1CC1DDD0; + CHECKREG r1, 0x1EE1FFF0; + CHECKREG r2, 0x1AA1BBB0; + CHECKREG r3, 0x18819990; + CHECKREG r4, 0x16617770; + CHECKREG r5, 0x14415550; + CHECKREG r6, 0x12213330; + +// P-reg to L,B-reg to R-reg: no stall +//imm32 p0, 0x00001111; + imm32 p1, 0x21213331; + imm32 p2, 0x21415551; + imm32 p3, 0x21617771; + imm32 p4, 0x21819991; + imm32 p5, 0x21a1bbb1; + imm32 fp, 0x21c1ddd1; + imm32 sp, 0x21e1fff1; + L0 = P0; + R0 = L0; + L1 = P1; + R1 = L1; + L2 = P2; + R2 = L2; + L3 = P3; + R3 = L3; + B0 = P4; + R4 = B0; + B1 = P5; + R5 = B1; + B2 = SP; + R6 = B2; + B3 = FP; + R7 = B3; + + CHECKREG r1, 0x21213331; + CHECKREG r2, 0x21415551; + CHECKREG r3, 0x21617771; + CHECKREG r4, 0x21819991; + CHECKREG r5, 0x21a1bbb1; + CHECKREG r6, 0x21E1FFF1; + CHECKREG r7, 0x21C1DDD1; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x21617771; + CHECKREG r1, 0x21415551; + CHECKREG r2, 0x21213331; + CHECKREG r4, 0x21C1DDD1; + CHECKREG r5, 0x21E1FFF1; + CHECKREG r6, 0x21A1BBB1; + CHECKREG r7, 0x21819991; + +// P-reg to I,M-reg to L,B-reg: no stall +//imm32 p0, 0x00001111; + imm32 p1, 0x72213337; + imm32 p2, 0x74415557; + imm32 p3, 0x76617777; + imm32 p4, 0x78819997; + imm32 p5, 0x7aa1bbb7; + imm32 fp, 0x7cc1ddd7; + imm32 sp, 0x77e1fff7; + I0 = P0; + L0 = I0; + I1 = P1; + L1 = I1; + I2 = P2; + L2 = I2; + I3 = P3; + L3 = I3; + M0 = P4; + B0 = M0; + M1 = P5; + B1 = M1; + M2 = SP; + B2 = M2; + M3 = FP; + B3 = M3; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x76617777; + CHECKREG r1, 0x74415557; + CHECKREG r2, 0x72213337; + CHECKREG r4, 0x7CC1DDD7; + CHECKREG r5, 0x77E1FFF7; + CHECKREG r6, 0x7AA1BBB7; + CHECKREG r7, 0x78819997; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x7CC1DDD7; + CHECKREG r1, 0x77E1FFF7; + CHECKREG r2, 0x7AA1BBB7; + CHECKREG r3, 0x78819997; + CHECKREG r4, 0x76617777; + CHECKREG r5, 0x74415557; + CHECKREG r6, 0x72213337; + +// P-reg to L,B-reg to I,Mreg: no stall +//imm32 p0, 0x00001111; + imm32 p1, 0x81213338; + imm32 p2, 0x81415558; + imm32 p3, 0x81617778; + imm32 p4, 0x81819998; + imm32 p5, 0x81a1bbb8; + imm32 fp, 0x81c1ddd8; + imm32 sp, 0x81e1fff8; + L0 = P0; + I0 = L0; + L1 = P1; + I1 = L1; + L2 = P2; + I2 = L2; + L3 = P3; + I3 = L3; + B0 = P4; + M0 = B0; + B1 = P5; + M1 = B1; + B2 = SP; + M2 = B2; + B3 = FP; + M3 = B3; + + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x81819998; + CHECKREG r1, 0x81A1BBB8; + CHECKREG r2, 0x81E1FFF8; + CHECKREG r3, 0x81C1DDD8; + CHECKREG r5, 0x81213338; + CHECKREG r6, 0x81415558; + CHECKREG r7, 0x81617778; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x81617778; + CHECKREG r1, 0x81415558; + CHECKREG r2, 0x81213338; + CHECKREG r4, 0x81C1DDD8; + CHECKREG r5, 0x81E1FFF8; + CHECKREG r6, 0x81A1BBB8; + CHECKREG r7, 0x81819998; + +// I-to-M, I-to-I and to R-reg: no stall + imm32 i0, 0x30001111; + imm32 i1, 0x23213332; + imm32 i2, 0x14315552; + imm32 i3, 0x01637772; + imm32 m0, 0x80113992; + imm32 m1, 0xaa01b3b2; + imm32 m2, 0xccc01d32; + imm32 m3, 0xeee101f3; + M0 = I0; + R4 = M0; + M1 = I1; + R5 = M1; + M2 = I2; + R6 = M2; + M3 = I3; + R7 = M3; + I0 = I3; + R0 = I0; + I1 = I2; + R1 = I1; + I3 = I0; + R2 = I3; + I2 = I1; + R3 = I2; + + CHECKREG r0, 0x01637772; + CHECKREG r1, 0x14315552; + CHECKREG r2, 0x01637772; + CHECKREG r3, 0x14315552; + CHECKREG r4, 0x30001111; + CHECKREG r5, 0x23213332; + CHECKREG r6, 0x14315552; + CHECKREG r7, 0x01637772; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x30001111; + CHECKREG r1, 0x23213332; + CHECKREG r2, 0x14315552; + CHECKREG r3, 0x01637772; + CHECKREG r4, 0x01637772; + CHECKREG r5, 0x14315552; + CHECKREG r6, 0x14315552; + CHECKREG r7, 0x01637772; + +// I-to-M, I-to-I and to P-reg: no stall + imm32 i0, 0x00001111; + imm32 i1, 0x42213342; + imm32 i2, 0x44415542; + imm32 i3, 0x46617742; + imm32 m0, 0x48819942; + imm32 m1, 0x4aa1bb42; + imm32 m2, 0x4cc1dd42; + imm32 m3, 0x4ee1ff42; + M0 = I0; + R0 = M0; + M1 = I1; + P1 = M1; + M2 = I2; + P2 = M2; + M3 = I3; + P3 = M3; + I0 = I3; + P4 = I0; + I1 = I2; + P5 = I1; + I2 = I0; + SP = I2; + I3 = I1; + FP = I3; + + CHECKREG r0, 0x00001111; + CHECKREG p1, 0x42213342; + CHECKREG p2, 0x44415542; + CHECKREG p3, 0x46617742; + CHECKREG p4, 0x46617742; + CHECKREG p5, 0x44415542; + CHECKREG sp, 0x46617742; + CHECKREG fp, 0x44415542; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x00001111; + CHECKREG r1, 0x42213342; + CHECKREG r2, 0x44415542; + CHECKREG r3, 0x46617742; + CHECKREG r4, 0x46617742; + CHECKREG r5, 0x44415542; + CHECKREG r6, 0x46617742; + CHECKREG r7, 0x44415542; + +// L-to-B, L-to-L and to R-reg: no stall + imm32 l0, 0x40001114; + imm32 l1, 0x24213334; + imm32 l2, 0x54415554; + imm32 l3, 0x05647774; + imm32 b0, 0x60514994; + imm32 b1, 0xa605b4b4; + imm32 b2, 0xcc605d44; + imm32 b3, 0xeee605f4; + B0 = L0; + R4 = B0; + B1 = L1; + R5 = B1; + B2 = L2; + R6 = B2; + B3 = L3; + R7 = B3; + L0 = L3; + R0 = L0; + L1 = L2; + R1 = L1; + L3 = L0; + R2 = L3; + L2 = L1; + R3 = L2; + + CHECKREG r0, 0x05647774; + CHECKREG r1, 0x54415554; + CHECKREG r2, 0x05647774; + CHECKREG r3, 0x54415554; + CHECKREG r4, 0x40001114; + CHECKREG r5, 0x24213334; + CHECKREG r6, 0x54415554; + CHECKREG r7, 0x05647774; + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0x05647774; + CHECKREG r1, 0x54415554; + CHECKREG r2, 0x54415554; + CHECKREG r3, 0x05647774; + CHECKREG r4, 0x40001114; + CHECKREG r5, 0x24213334; + CHECKREG r6, 0x54415554; + CHECKREG r7, 0x05647774; + +// L-to-B, L-to-L and to P-reg: no stall + imm32 l0, 0x60001116; + imm32 l1, 0x46213346; + imm32 l2, 0x74615546; + imm32 l3, 0x47667746; + imm32 b0, 0x48716946; + imm32 b1, 0x8aa7b646; + imm32 b2, 0x48c17d66; + imm32 b3, 0x4e81f746; + M0 = I0; + R0 = M0; + M1 = I1; + P1 = M1; + M2 = I2; + P2 = M2; + M3 = I3; + P3 = M3; + I0 = I3; + P4 = I0; + I1 = I2; + P5 = I1; + I2 = I0; + SP = I2; + I3 = I1; + FP = I3; + + CHECKREG r0, 0x46617742; + CHECKREG p1, 0x44415542; + CHECKREG p2, 0x46617742; + CHECKREG p3, 0x44415542; + CHECKREG p4, 0x44415542; + CHECKREG p5, 0x46617742; + CHECKREG sp, 0x44415542; + CHECKREG fp, 0x46617742; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x46617742; + CHECKREG r1, 0x44415542; + CHECKREG r2, 0x46617742; + CHECKREG r3, 0x44415542; + CHECKREG r4, 0x44415542; + CHECKREG r5, 0x46617742; + CHECKREG r6, 0x44415542; + CHECKREG r7, 0x46617742; + +// I-to-M-to-L, I-to-I-to-B -reg: no stall + imm32 i0, 0x90001119; + imm32 i1, 0x93213339; + imm32 i2, 0x94315559; + imm32 i3, 0x91637779; + imm32 m0, 0x90113999; + imm32 m1, 0x9a01b3b9; + imm32 m2, 0x9cc01d39; + imm32 m3, 0x9ee101f9; + M0 = I0; + L0 = M0; + M1 = I1; + L1 = M1; + M2 = I2; + L2 = M2; + M3 = I3; + L3 = M3; + I0 = I3; + B0 = I0; + I1 = I2; + B1 = I1; + I3 = I0; + B2 = I3; + I2 = I1; + B3 = I2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0x90001119; + CHECKREG r1, 0x93213339; + CHECKREG r2, 0x94315559; + CHECKREG r3, 0x91637779; + CHECKREG r4, 0x91637779; + CHECKREG r5, 0x94315559; + CHECKREG r6, 0x91637779; + CHECKREG r7, 0x94315559; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x90001119; + CHECKREG r1, 0x93213339; + CHECKREG r2, 0x94315559; + CHECKREG r3, 0x91637779; + CHECKREG r4, 0x91637779; + CHECKREG r5, 0x94315559; + CHECKREG r6, 0x94315559; + CHECKREG r7, 0x91637779; + +// I-to-M-B, I-to-I-L reg: no stall + imm32 i0, 0xa000111a; + imm32 i1, 0xaa21334a; + imm32 i2, 0xa4a1554a; + imm32 i3, 0xa66a774a; + imm32 m0, 0xa881a94a; + imm32 m1, 0xaaa1ba4a; + imm32 m2, 0xacc1ddaa; + imm32 m3, 0xaee1ff4a; + M0 = I0; + B3 = M0; + M1 = I1; + B2 = M1; + M2 = I2; + B1 = M2; + M3 = I3; + B0 = M3; + I0 = I3; + L1 = I0; + I1 = I2; + L2 = I1; + I2 = I0; + L3 = I2; + I3 = I1; + L0 = I3; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0xA4A1554A; + CHECKREG r1, 0xA66A774A; + CHECKREG r2, 0xA4A1554A; + CHECKREG r3, 0xA66A774A; + CHECKREG r4, 0xA66A774A; + CHECKREG r5, 0xA4A1554A; + CHECKREG r6, 0xAA21334A; + CHECKREG r7, 0xA000111A; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0xA000111A; + CHECKREG r1, 0xAA21334A; + CHECKREG r2, 0xA4A1554A; + CHECKREG r3, 0xA66A774A; + CHECKREG r4, 0xA66A774A; + CHECKREG r5, 0xA4A1554A; + CHECKREG r6, 0xA66A774A; + CHECKREG r7, 0xA4A1554A; + +// L-to-B-to-I, L-to-L-to-M reg: no stall + imm32 l0, 0xb000111b; + imm32 l1, 0xb421333b; + imm32 l2, 0xb441555b; + imm32 l3, 0xb564777b; + imm32 b0, 0xb051499b; + imm32 b1, 0xb605b4bb; + imm32 b2, 0xbc605d4b; + imm32 b3, 0xbee605fb; + B0 = L0; + I2 = B0; + B1 = L1; + I3 = B1; + B2 = L2; + I0 = B2; + B3 = L3; + I1 = B3; + L0 = L3; + M0 = L0; + L1 = L2; + M1 = L1; + L3 = L0; + M2 = L3; + L2 = L1; + M3 = L2; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + CHECKREG r0, 0xB441555B; + CHECKREG r1, 0xB564777B; + CHECKREG r2, 0xB000111B; + CHECKREG r3, 0xB421333B; + CHECKREG r4, 0xB564777B; + CHECKREG r5, 0xB441555B; + CHECKREG r6, 0xB564777B; + CHECKREG r7, 0xB441555B; + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0xB564777B; + CHECKREG r1, 0xB441555B; + CHECKREG r2, 0xB441555B; + CHECKREG r3, 0xB564777B; + CHECKREG r4, 0xB000111B; + CHECKREG r5, 0xB421333B; + CHECKREG r6, 0xB441555B; + CHECKREG r7, 0xB564777B; + +// B-to-L-to-M, B-to-B-to-I reg: no stall + imm32 l0, 0xc000111c; + imm32 l1, 0xc621334c; + imm32 l2, 0xc461554c; + imm32 l3, 0xc766774c; + imm32 b0, 0xc871694c; + imm32 b1, 0xcaa7b64c; + imm32 b2, 0xc8c17d6c; + imm32 b3, 0xce81f74c; + L0 = B0; + M1 = L0; + L1 = B1; + M2 = L1; + L2 = B2; + M3 = L2; + L3 = B3; + M0 = L3; + B3 = B0; + I0 = B3; + B0 = B1; + I1 = B0; + B1 = B2; + I2 = B1; + B2 = B3; + I3 = B2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + CHECKREG r0, 0xC871694C; + CHECKREG r1, 0xCAA7B64C; + CHECKREG r2, 0xC8C17D6C; + CHECKREG r3, 0xCE81F74C; + CHECKREG r4, 0xCAA7B64C; + CHECKREG r5, 0xC8C17D6C; + CHECKREG r6, 0xC871694C; + CHECKREG r7, 0xC871694C; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0xCE81F74C; + CHECKREG r1, 0xC871694C; + CHECKREG r2, 0xCAA7B64C; + CHECKREG r3, 0xC8C17D6C; + CHECKREG r4, 0xC871694C; + CHECKREG r5, 0xCAA7B64C; + CHECKREG r6, 0xC8C17D6C; + CHECKREG r7, 0xC871694C; + + pass diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_dep_stall.s b/sim/testsuite/sim/bfin/c_regmv_imlb_dep_stall.s new file mode 100644 index 0000000..8fd2235 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_imlb_dep_stall.s @@ -0,0 +1,335 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_stall/c_regmv_imlb_dep_stall.dsp +// Spec Reference: regmv imlb-depepency stall +# mach: bfin + +.include "testutils.inc" + start + +// R-reg to I,M-reg to R-reg: stall + imm32 r0, 0x00001110; + imm32 r1, 0x00213330; + imm32 r2, 0x04015550; + imm32 r3, 0x06607770; + imm32 r4, 0x08010990; + imm32 r5, 0x0a01b0b0; + imm32 r6, 0x0c01dd00; + imm32 r7, 0x0e01f0f0; + I0 = R0; + R7 = I0; + I1 = R1; + R0 = I1; + I2 = R2; + R1 = I2; + I3 = R3; + R2 = I3; + M0 = R4; + R3 = M0; + M1 = R5; + R4 = M1; + M2 = R6; + R5 = M2; + M3 = R7; + R6 = M3; + + CHECKREG r0, 0x00213330; + CHECKREG r1, 0x04015550; + CHECKREG r2, 0x06607770; + CHECKREG r3, 0x08010990; + CHECKREG r4, 0x0A01B0B0; + CHECKREG r5, 0x0C01DD00; + CHECKREG r6, 0x00001110; + CHECKREG r7, 0x00001110; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x00001110; + CHECKREG r1, 0x0C01DD00; + CHECKREG r2, 0x0A01B0B0; + CHECKREG r3, 0x08010990; + CHECKREG r4, 0x06607770; + CHECKREG r5, 0x04015550; + CHECKREG r6, 0x00213330; + CHECKREG r7, 0x00001110; + +// R-to-M,I and to P-reg: stall + imm32 i0, 0x00001111; + imm32 i1, 0x12213341; + imm32 i2, 0x14415541; + imm32 i3, 0x16617741; + imm32 m0, 0x18819941; + imm32 m1, 0x1aa1bb41; + imm32 m2, 0x1cc1dd41; + imm32 m3, 0x1ee1ff41; + M0 = R0; + R0 = M0; + M1 = R1; + P1 = M1; + M2 = R2; + P2 = M2; + M3 = R3; + P3 = M3; + I0 = R4; + P4 = I0; + I1 = R5; + P5 = I1; + I2 = R6; + SP = I2; + I3 = R7; + FP = I3; + + CHECKREG r0, 0x00001110; + CHECKREG p1, 0x0C01DD00; + CHECKREG p2, 0x0A01B0B0; + CHECKREG p3, 0x08010990; + CHECKREG p4, 0x06607770; + CHECKREG p5, 0x04015550; + CHECKREG sp, 0x00213330; + CHECKREG fp, 0x00001110; + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x00001110; + CHECKREG r1, 0x0C01DD00; + CHECKREG r2, 0x0A01B0B0; + CHECKREG r3, 0x08010990; + CHECKREG r4, 0x06607770; + CHECKREG r5, 0x04015550; + CHECKREG r6, 0x00213330; + CHECKREG r7, 0x00001110; + +// R-reg to L,B-reg to R-reg: stall + imm32 r0, 0x20001112; + imm32 r1, 0x22213332; + imm32 r2, 0x21215552; + imm32 r3, 0x21627772; + imm32 r4, 0x21812992; + imm32 r5, 0x21a1b2b2; + imm32 r6, 0x21c1d222; + imm32 r7, 0x21e1ff22; + L0 = R1; + R0 = L0; + L1 = R2; + R1 = L1; + L2 = R3; + R2 = L2; + L3 = R4; + R3 = L3; + B0 = R5; + R4 = B0; + B1 = R6; + R5 = B1; + B2 = R7; + R6 = B2; + B3 = R0; + R7 = B3; + + CHECKREG r0, 0x22213332; + CHECKREG r1, 0x21215552; + CHECKREG r2, 0x21627772; + CHECKREG r3, 0x21812992; + CHECKREG r4, 0x21A1B2B2; + CHECKREG r5, 0x21C1D222; + CHECKREG r6, 0x21E1FF22; + CHECKREG r7, 0x22213332; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x21812992; + CHECKREG r1, 0x21627772; + CHECKREG r2, 0x21215552; + CHECKREG r3, 0x22213332; + CHECKREG r4, 0x22213332; + CHECKREG r5, 0x21E1FF22; + CHECKREG r6, 0x21C1D222; + CHECKREG r7, 0x21A1B2B2; + +// R-reg to L,B-reg to P-reg: stall + imm32 r0, 0x50001115; + imm32 r1, 0x51213335; + imm32 r2, 0x51415555; + imm32 r3, 0x51617775; + imm32 r4, 0x51819995; + imm32 r5, 0x51a1bbb5; + imm32 r6, 0x51c1ddd5; + imm32 r7, 0x51e1fff5; + L0 = R1; + R0 = L0; + L1 = R2; + SP = L1; + L2 = R3; + FP = L2; + L3 = R4; + P1 = L3; + B0 = R5; + P2 = B0; + B1 = R6; + P3 = B1; + B2 = R7; + P4 = B2; + B3 = R0; + P5 = B3; + + CHECKREG r0, 0x51213335; + CHECKREG p1, 0x51819995; + CHECKREG p2, 0x51A1BBB5; + CHECKREG p3, 0x51C1DDD5; + CHECKREG p4, 0x51E1FFF5; + CHECKREG p5, 0x51213335; + CHECKREG sp, 0x51415555; + CHECKREG fp, 0x51617775; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x51819995; + CHECKREG r1, 0x51617775; + CHECKREG r2, 0x51415555; + CHECKREG r3, 0x51213335; + CHECKREG r4, 0x51213335; + CHECKREG r5, 0x51E1FFF5; + CHECKREG r6, 0x51C1DDD5; + CHECKREG r7, 0x51A1BBB5; + +// R-reg to I,M-reg to L,B-reg: stall + imm32 r0, 0x00001111; + imm32 r1, 0x72213337; + imm32 r2, 0x74415557; + imm32 r3, 0x76617777; + imm32 r4, 0x78819997; + imm32 r5, 0x7aa1bbb7; + imm32 r6, 0x7cc1ddd7; + imm32 r7, 0x77e1fff7; + I0 = R0; + L0 = I0; + I1 = R1; + L1 = I1; + I2 = R2; + L2 = I2; + I3 = R3; + L3 = I3; + M0 = R4; + B0 = M0; + M1 = R5; + B1 = M1; + M2 = R6; + B2 = M2; + M3 = R7; + B3 = M3; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x76617777; + CHECKREG r1, 0x74415557; + CHECKREG r2, 0x72213337; + CHECKREG r3, 0x00001111; + CHECKREG r4, 0x77E1FFF7; + CHECKREG r5, 0x7CC1DDD7; + CHECKREG r6, 0x7AA1BBB7; + CHECKREG r7, 0x78819997; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r0, 0x77E1FFF7; + CHECKREG r1, 0x7CC1DDD7; + CHECKREG r2, 0x7AA1BBB7; + CHECKREG r3, 0x78819997; + CHECKREG r4, 0x76617777; + CHECKREG r5, 0x74415557; + CHECKREG r6, 0x72213337; + CHECKREG r7, 0x00001111; + +// R-reg to L,B-reg to I,M reg: stall + imm32 r0, 0x00001111; + imm32 r1, 0x81213338; + imm32 r2, 0x81415558; + imm32 r3, 0x81617778; + imm32 r4, 0x81819998; + imm32 r5, 0x81a1bbb8; + imm32 r6, 0x81c1ddd8; + imm32 r7, 0x81e1fff8; + L0 = R0; + I0 = L0; + L1 = R1; + I1 = L1; + L2 = R2; + I2 = L2; + L3 = R3; + I3 = L3; + B0 = R4; + M0 = B0; + B1 = R5; + M1 = B1; + B2 = R6; + M2 = B2; + B3 = R7; + M3 = B3; + + R0 = M0; + R1 = M1; + R2 = M2; + R3 = M3; + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + CHECKREG r0, 0x81819998; + CHECKREG r1, 0x81A1BBB8; + CHECKREG r2, 0x81C1DDD8; + CHECKREG r3, 0x81E1FFF8; + CHECKREG r4, 0x00001111; + CHECKREG r5, 0x81213338; + CHECKREG r6, 0x81415558; + CHECKREG r7, 0x81617778; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x81617778; + CHECKREG r1, 0x81415558; + CHECKREG r2, 0x81213338; + CHECKREG r3, 0x00001111; + CHECKREG r4, 0x81E1FFF8; + CHECKREG r5, 0x81C1DDD8; + CHECKREG r6, 0x81A1BBB8; + CHECKREG r7, 0x81819998; + + pass diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_dr.s b/sim/testsuite/sim/bfin/c_regmv_imlb_dr.s new file mode 100644 index 0000000..ec15df0 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_imlb_dr.s @@ -0,0 +1,313 @@ +//Original:/testcases/core/c_regmv_imlb_dr/c_regmv_imlb_dr.dsp +// Spec Reference: regmv imlb to dr +# mach: bfin + +.include "testutils.inc" + start + + + + + + +// initialize source regs +imm32 i0, 0x11111111; +imm32 i1, 0x22222222; +imm32 i2, 0x33333333; +imm32 i3, 0x44444444; + + +// i to dreg +R0 = I0; +R1 = I0; +R2 = I0; +R3 = I0; +R4 = I1; +R5 = I1; +R6 = I1; +R7 = I1; +CHECKREG r0, 0x11111111; +CHECKREG r1, 0x11111111; +CHECKREG r2, 0x11111111; +CHECKREG r3, 0x11111111; +CHECKREG r4, 0x22222222; +CHECKREG r5, 0x22222222; +CHECKREG r6, 0x22222222; +CHECKREG r7, 0x22222222; + +R0 = I1; +R1 = I1; +R2 = I1; +R3 = I1; +R4 = I0; +R5 = I0; +R6 = I0; +R7 = I0; +CHECKREG r0, 0x22222222; +CHECKREG r1, 0x22222222; +CHECKREG r2, 0x22222222; +CHECKREG r3, 0x22222222; +CHECKREG r4, 0x11111111; +CHECKREG r5, 0x11111111; +CHECKREG r6, 0x11111111; +CHECKREG r7, 0x11111111; + + +// i to dreg +R0 = I2; +R1 = I2; +R2 = I2; +R3 = I2; +R4 = I3; +R5 = I3; +R6 = I3; +R7 = I3; +CHECKREG r0, 0x33333333; +CHECKREG r1, 0x33333333; +CHECKREG r2, 0x33333333; +CHECKREG r3, 0x33333333; +CHECKREG r4, 0x44444444; +CHECKREG r5, 0x44444444; +CHECKREG r6, 0x44444444; +CHECKREG r7, 0x44444444; + +R0 = I3; +R1 = I3; +R2 = I3; +R3 = I3; +R4 = I2; +R5 = I2; +R6 = I2; +R7 = I2; +CHECKREG r0, 0x44444444; +CHECKREG r1, 0x44444444; +CHECKREG r2, 0x44444444; +CHECKREG r3, 0x44444444; +CHECKREG r4, 0x33333333; +CHECKREG r5, 0x33333333; +CHECKREG r6, 0x33333333; +CHECKREG r7, 0x33333333; + + +imm32 m0, 0x55555555; +imm32 m1, 0x66666666; +imm32 m2, 0x77777777; +imm32 m3, 0x88888888; +// m to dreg +R0 = M0; +R1 = M0; +R2 = M0; +R3 = M0; +R4 = M1; +R5 = M1; +R6 = M1; +R7 = M1; +CHECKREG r0, 0x55555555; +CHECKREG r1, 0x55555555; +CHECKREG r2, 0x55555555; +CHECKREG r3, 0x55555555; +CHECKREG r4, 0x66666666; +CHECKREG r5, 0x66666666; +CHECKREG r6, 0x66666666; +CHECKREG r7, 0x66666666; + +R0 = M1; +R1 = M1; +R2 = M1; +R3 = M1; +R4 = M0; +R5 = M0; +R6 = M0; +R7 = M0; +CHECKREG r0, 0x66666666; +CHECKREG r1, 0x66666666; +CHECKREG r2, 0x66666666; +CHECKREG r3, 0x66666666; +CHECKREG r4, 0x55555555; +CHECKREG r5, 0x55555555; +CHECKREG r6, 0x55555555; +CHECKREG r7, 0x55555555; + +R0 = M2; +R1 = M2; +R2 = M2; +R3 = M2; +R4 = M3; +R5 = M3; +R6 = M3; +R7 = M3; +CHECKREG r0, 0x77777777; +CHECKREG r1, 0x77777777; +CHECKREG r2, 0x77777777; +CHECKREG r3, 0x77777777; +CHECKREG r4, 0x88888888; +CHECKREG r5, 0x88888888; +CHECKREG r6, 0x88888888; +CHECKREG r7, 0x88888888; + +R0 = M3; +R1 = M3; +R2 = M3; +R3 = M3; +R4 = M2; +R5 = M2; +R6 = M2; +R7 = M2; +CHECKREG r0, 0x88888888; +CHECKREG r1, 0x88888888; +CHECKREG r2, 0x88888888; +CHECKREG r3, 0x88888888; +CHECKREG r4, 0x77777777; +CHECKREG r5, 0x77777777; +CHECKREG r6, 0x77777777; +CHECKREG r7, 0x77777777; + +imm32 l0, 0x99999999; +imm32 l1, 0xaaaaaaaa; +imm32 l2, 0xbbbbbbbb; +imm32 l3, 0xcccccccc; +// l to dreg +R0 = L0; +R1 = L0; +R2 = L0; +R3 = L0; +R4 = L1; +R5 = L1; +R6 = L1; +R7 = L1; +CHECKREG r0, 0x99999999; +CHECKREG r1, 0x99999999; +CHECKREG r2, 0x99999999; +CHECKREG r3, 0x99999999; +CHECKREG r4, 0xaaaaaaaa; +CHECKREG r5, 0xaaaaaaaa; +CHECKREG r6, 0xaaaaaaaa; +CHECKREG r7, 0xaaaaaaaa; + +R0 = L1; +R1 = L1; +R2 = L1; +R3 = L1; +R4 = L0; +R5 = L0; +R6 = L0; +R7 = L0; +CHECKREG r0, 0xaaaaaaaa; +CHECKREG r1, 0xaaaaaaaa; +CHECKREG r2, 0xaaaaaaaa; +CHECKREG r3, 0xaaaaaaaa; +CHECKREG r4, 0x99999999; +CHECKREG r5, 0x99999999; +CHECKREG r6, 0x99999999; +CHECKREG r7, 0x99999999; + + +R0 = L2; +R1 = L2; +R2 = L2; +R3 = L2; +R4 = L3; +R5 = L3; +R6 = L3; +R7 = L3; +CHECKREG r0, 0xbbbbbbbb; +CHECKREG r1, 0xbbbbbbbb; +CHECKREG r2, 0xbbbbbbbb; +CHECKREG r3, 0xbbbbbbbb; +CHECKREG r4, 0xcccccccc; +CHECKREG r5, 0xcccccccc; +CHECKREG r6, 0xcccccccc; +CHECKREG r7, 0xcccccccc; + +R0 = L3; +R1 = L3; +R2 = L3; +R3 = L3; +R4 = L2; +R5 = L2; +R6 = L2; +R7 = L2; +CHECKREG r0, 0xcccccccc; +CHECKREG r1, 0xcccccccc; +CHECKREG r2, 0xcccccccc; +CHECKREG r3, 0xcccccccc; +CHECKREG r4, 0xbbbbbbbb; +CHECKREG r5, 0xbbbbbbbb; +CHECKREG r6, 0xbbbbbbbb; +CHECKREG r7, 0xbbbbbbbb; + + +imm32 b0, 0xdddddddd; +imm32 b1, 0xeeeeeeee; +imm32 b2, 0xffffffff; +imm32 b3, 0x12345678; +// b to dreg +R0 = B0; +R1 = B0; +R2 = B0; +R3 = B0; +R4 = B1; +R5 = B1; +R6 = B1; +R7 = B1; +CHECKREG r0, 0xdddddddd; +CHECKREG r1, 0xdddddddd; +CHECKREG r2, 0xdddddddd; +CHECKREG r3, 0xdddddddd; +CHECKREG r4, 0xeeeeeeee; +CHECKREG r5, 0xeeeeeeee; +CHECKREG r6, 0xeeeeeeee; +CHECKREG r7, 0xeeeeeeee; + +R0 = B1; +R1 = B1; +R2 = B1; +R3 = B1; +R4 = B0; +R5 = B0; +R6 = B0; +R7 = B0; +CHECKREG r0, 0xeeeeeeee; +CHECKREG r1, 0xeeeeeeee; +CHECKREG r2, 0xeeeeeeee; +CHECKREG r3, 0xeeeeeeee; +CHECKREG r4, 0xdddddddd; +CHECKREG r5, 0xdddddddd; +CHECKREG r6, 0xdddddddd; +CHECKREG r7, 0xdddddddd; + +R0 = B2; +R1 = B2; +R2 = B2; +R3 = B2; +R4 = B3; +R5 = B3; +R6 = B3; +R7 = B3; +CHECKREG r0, 0xffffffff; +CHECKREG r1, 0xffffffff; +CHECKREG r2, 0xffffffff; +CHECKREG r3, 0xffffffff; +CHECKREG r4, 0x12345678; +CHECKREG r5, 0x12345678; +CHECKREG r6, 0x12345678; +CHECKREG r7, 0x12345678; + +R0 = B3; +R1 = B3; +R2 = B3; +R3 = B3; +R4 = B2; +R5 = B2; +R6 = B2; +R7 = B2; +CHECKREG r0, 0x12345678; +CHECKREG r1, 0x12345678; +CHECKREG r2, 0x12345678; +CHECKREG r3, 0x12345678; +CHECKREG r4, 0xffffffff; +CHECKREG r5, 0xffffffff; +CHECKREG r6, 0xffffffff; +CHECKREG r7, 0xffffffff; + +pass diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_imlb.s b/sim/testsuite/sim/bfin/c_regmv_imlb_imlb.s new file mode 100644 index 0000000..35146ec --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_imlb_imlb.s @@ -0,0 +1,925 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_imlb/c_regmv_imlb_imlb.dsp +// Spec Reference: regmv imlb-imlb +# mach: bfin + +.include "testutils.inc" + start + +// initialize source regs + imm32 i0, 0x11111111; + imm32 i1, 0x22222222; + imm32 i2, 0x33333333; + imm32 i3, 0x44444444; + imm32 m0, 0x55555555; + imm32 m1, 0x66666666; + imm32 m2, 0x77777777; + imm32 m3, 0x88888888; + imm32 l0, 0x99999999; + imm32 l1, 0xAAAAAAAA; + imm32 l2, 0xBBBBBBBB; + imm32 l3, 0xCCCCCCCC; + imm32 b0, 0xDDDDDDDD; + imm32 b1, 0xEEEEEEEE; + imm32 b2, 0xFFFFFFFF; + imm32 b3, 0x12345667; + +//*******************i-i & m-m, i-m & m-i, l-l & b-b, l-b & b-l +// i to i & m to m + I0 = I0; + I1 = I1; + I2 = I2; + I3 = I3; + M0 = M0; + M1 = M1; + M2 = M2; + M3 = M3; + + I0 = I1; + I1 = I2; + I2 = I3; + I3 = I0; + M0 = M1; + M1 = M2; + M2 = M3; + M3 = M0; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x22222222; + CHECKREG r1, 0x33333333; + CHECKREG r2, 0x44444444; + CHECKREG r3, 0x22222222; + CHECKREG r4, 0x66666666; + CHECKREG r5, 0x77777777; + CHECKREG r6, 0x88888888; + CHECKREG r7, 0x66666666; + + I0 = I2; + I1 = I3; + I2 = I0; + I3 = I1; + M0 = M2; + M1 = M3; + M2 = M0; + M3 = M1; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x44444444; + CHECKREG r1, 0x22222222; + CHECKREG r2, 0x44444444; + CHECKREG r3, 0x22222222; + CHECKREG r4, 0x88888888; + CHECKREG r5, 0x66666666; + CHECKREG r6, 0x88888888; + CHECKREG r7, 0x66666666; + + I0 = I3; + I1 = I0; + I2 = I1; + I3 = I2; + M0 = M3; + M1 = M0; + M2 = M1; + M3 = M2; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x22222222; + CHECKREG r1, 0x22222222; + CHECKREG r2, 0x22222222; + CHECKREG r3, 0x22222222; + CHECKREG r4, 0x66666666; + CHECKREG r5, 0x66666666; + CHECKREG r6, 0x66666666; + CHECKREG r7, 0x66666666; + + imm32 i0, 0xa1111110; + imm32 i1, 0xb2222220; + imm32 i2, 0xc3333330; + imm32 i3, 0xd4444440; + imm32 m0, 0xe5555550; + imm32 m1, 0xf6666660; + imm32 m2, 0x17777770; + imm32 m3, 0x28888888; + +// m to i & i to m + I0 = M0; + I1 = M1; + I2 = M2; + I3 = M3; + M0 = I0; + M1 = I1; + M2 = I2; + M3 = I3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xE5555550; + CHECKREG r1, 0xF6666660; + CHECKREG r2, 0x17777770; + CHECKREG r3, 0x28888888; + CHECKREG r4, 0xE5555550; + CHECKREG r5, 0xF6666660; + CHECKREG r6, 0x17777770; + CHECKREG r7, 0x28888888; + + I0 = M1; + I1 = M2; + I2 = M3; + I3 = M0; + M0 = I1; + M1 = I2; + M2 = I3; + M3 = I0; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xF6666660; + CHECKREG r1, 0x17777770; + CHECKREG r2, 0x28888888; + CHECKREG r3, 0xE5555550; + CHECKREG r4, 0x17777770; + CHECKREG r5, 0x28888888; + CHECKREG r6, 0xE5555550; + CHECKREG r7, 0xF6666660; + + I0 = M2; + I1 = M3; + I2 = M0; + I3 = M1; + M0 = I2; + M1 = I3; + M2 = I0; + M3 = I1; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xE5555550; + CHECKREG r1, 0xF6666660; + CHECKREG r2, 0x17777770; + CHECKREG r3, 0x28888888; + CHECKREG r4, 0x17777770; + CHECKREG r5, 0x28888888; + CHECKREG r6, 0xE5555550; + CHECKREG r7, 0xF6666660; + + I0 = M3; + I1 = M0; + I2 = M1; + I3 = M2; + M0 = I3; + M1 = I0; + M2 = I1; + M3 = I2; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xF6666660; + CHECKREG r1, 0x17777770; + CHECKREG r2, 0x28888888; + CHECKREG r3, 0xE5555550; + CHECKREG r4, 0xE5555550; + CHECKREG r5, 0xF6666660; + CHECKREG r6, 0x17777770; + CHECKREG r7, 0x28888888; + +// l to l & b to b + L0 = L0; + L1 = L1; + L2 = L2; + L3 = L3; + B0 = B0; + B1 = B1; + B2 = B2; + B3 = B3; + + L0 = L1; + L1 = L2; + L2 = L3; + L3 = L0; + B0 = B1; + B1 = B2; + B2 = B3; + B3 = B0; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0xAAAAAAAA; + CHECKREG r1, 0xBBBBBBBB; + CHECKREG r2, 0xCCCCCCCC; + CHECKREG r3, 0xAAAAAAAA; + CHECKREG r4, 0xEEEEEEEE; + CHECKREG r5, 0xFFFFFFFF; + CHECKREG r6, 0x12345667; + CHECKREG r7, 0xEEEEEEEE; + + L0 = L2; + L1 = L3; + L2 = L0; + L3 = L1; + B0 = B2; + B1 = B3; + B2 = B0; + B3 = B1; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0xCCCCCCCC; + CHECKREG r1, 0xAAAAAAAA; + CHECKREG r2, 0xCCCCCCCC; + CHECKREG r3, 0xAAAAAAAA; + CHECKREG r4, 0x12345667; + CHECKREG r5, 0xEEEEEEEE; + CHECKREG r6, 0x12345667; + CHECKREG r7, 0xEEEEEEEE; + + imm32 l0, 0x09499091; + imm32 l1, 0x0A55A0A2; + imm32 l2, 0x0B6BB0B3; + imm32 l3, 0x0C7CC0C4; + imm32 b0, 0x0D8DD0D5; + imm32 b1, 0x0E9EE0E6; + imm32 b2, 0x0F0FF0F7; + imm32 b3, 0x12145068; + + L0 = L3; + L1 = L0; + L2 = L1; + L3 = L2; + B0 = B3; + B1 = B0; + B2 = B1; + B3 = B2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x0C7CC0C4; + CHECKREG r1, 0x0C7CC0C4; + CHECKREG r2, 0x0C7CC0C4; + CHECKREG r3, 0x0C7CC0C4; + CHECKREG r4, 0x12145068; + CHECKREG r5, 0x12145068; + CHECKREG r6, 0x12145068; + CHECKREG r7, 0x12145068; + +// b to l & l to b + L0 = B0; + L1 = B1; + L2 = B2; + L3 = B3; + B0 = L0; + B1 = L1; + B2 = L2; + B3 = L3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0xF6666660; + CHECKREG r1, 0x17777770; + CHECKREG r2, 0x28888888; + CHECKREG r3, 0xE5555550; + CHECKREG r4, 0xE5555550; + CHECKREG r5, 0xF6666660; + CHECKREG r6, 0x17777770; + CHECKREG r7, 0x28888888; + + imm32 l0, 0x01909910; + imm32 l1, 0x12A11220; + imm32 l2, 0x23B25530; + imm32 l3, 0x34C36640; + imm32 b0, 0x45D47750; + imm32 b1, 0x56E58860; + imm32 b2, 0x67F66676; + imm32 b3, 0x78375680; + + L0 = B1; + L1 = B2; + L2 = B3; + L3 = B0; + B0 = L1; + B1 = L2; + B2 = L3; + B3 = L0; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x56E58860; + CHECKREG r1, 0x67F66676; + CHECKREG r2, 0x78375680; + CHECKREG r3, 0x45D47750; + CHECKREG r4, 0x67F66676; + CHECKREG r5, 0x78375680; + CHECKREG r6, 0x45D47750; + CHECKREG r7, 0x56E58860; + + imm32 l0, 0x09909990; + imm32 l1, 0x1AA11230; + imm32 l2, 0x2BB25550; + imm32 l3, 0x3CC36660; + imm32 b0, 0x4DD47770; + imm32 b1, 0x5EE58880; + imm32 b2, 0x6FF66666; + imm32 b3, 0x72375660; + + L0 = B2; + L1 = B3; + L2 = B0; + L3 = B1; + B0 = L2; + B1 = L3; + B2 = L0; + B3 = L1; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x6FF66666; + CHECKREG r1, 0x72375660; + CHECKREG r2, 0x4DD47770; + CHECKREG r3, 0x5EE58880; + CHECKREG r4, 0x4DD47770; + CHECKREG r5, 0x5EE58880; + CHECKREG r6, 0x6FF66666; + CHECKREG r7, 0x72375660; + + L0 = B3; + L1 = B0; + L2 = B1; + L3 = B2; + B0 = L3; + B1 = L0; + B2 = L1; + B3 = L2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x72375660; + CHECKREG r1, 0x4DD47770; + CHECKREG r2, 0x5EE58880; + CHECKREG r3, 0x6FF66666; + CHECKREG r4, 0x6FF66666; + CHECKREG r5, 0x72375660; + CHECKREG r6, 0x4DD47770; + CHECKREG r7, 0x5EE58880; + + imm32 l0, 0x09999990; + imm32 l1, 0x1AAAAAA0; + imm32 l2, 0x2BBBBBB0; + imm32 l3, 0x3CCCCCC0; + imm32 b0, 0x4DDDDDD0; + imm32 b1, 0x5EEEEEE0; + imm32 b2, 0x6FFFFFF0; + imm32 b3, 0x72345660; + +//*******************l-i & l-m, b-i & b-m, i-l & i-b, m-l & m-b +// l to i & l to m + I0 = L0; + I1 = L1; + I2 = L2; + I3 = L3; + M0 = L0; + M1 = L1; + M2 = L2; + M3 = L3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x09999990; + CHECKREG r1, 0x1AAAAAA0; + CHECKREG r2, 0x2BBBBBB0; + CHECKREG r3, 0x3CCCCCC0; + CHECKREG r4, 0x09999990; + CHECKREG r5, 0x1AAAAAA0; + CHECKREG r6, 0x2BBBBBB0; + CHECKREG r7, 0x3CCCCCC0; + + I0 = L1; + I1 = L2; + I2 = L3; + I3 = L0; + M0 = L1; + M1 = L2; + M2 = L3; + M3 = L0; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x1AAAAAA0; + CHECKREG r1, 0x2BBBBBB0; + CHECKREG r2, 0x3CCCCCC0; + CHECKREG r3, 0x09999990; + CHECKREG r4, 0x1AAAAAA0; + CHECKREG r5, 0x2BBBBBB0; + CHECKREG r6, 0x3CCCCCC0; + CHECKREG r7, 0x09999990; + + I0 = L2; + I1 = L3; + I2 = L0; + I3 = L1; + M0 = L2; + M1 = L3; + M2 = L0; + M3 = L1; + + R4 = I0; + R5 = I1; + R6 = I2; + R7 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x1AAAAAA0; + CHECKREG r1, 0x2BBBBBB0; + CHECKREG r2, 0x3CCCCCC0; + CHECKREG r3, 0x09999990; + CHECKREG r4, 0x2BBBBBB0; + CHECKREG r5, 0x3CCCCCC0; + CHECKREG r6, 0x09999990; + CHECKREG r7, 0x1AAAAAA0; + + I0 = L3; + I1 = L0; + I2 = L1; + I3 = L2; + M0 = L3; + M1 = L0; + M2 = L1; + M3 = L2; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x3CCCCCC0; + CHECKREG r1, 0x09999990; + CHECKREG r2, 0x1AAAAAA0; + CHECKREG r3, 0x2BBBBBB0; + CHECKREG r4, 0x3CCCCCC0; + CHECKREG r5, 0x09999990; + CHECKREG r6, 0x1AAAAAA0; + CHECKREG r7, 0x2BBBBBB0; + +// b to i & b to m + I0 = B0; + I1 = B1; + I2 = B2; + I3 = B3; + M0 = B0; + M1 = B1; + M2 = B2; + M3 = B3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x4DDDDDD0; + CHECKREG r1, 0x5EEEEEE0; + CHECKREG r2, 0x6FFFFFF0; + CHECKREG r3, 0x72345660; + CHECKREG r4, 0x4DDDDDD0; + CHECKREG r5, 0x5EEEEEE0; + CHECKREG r6, 0x6FFFFFF0; + CHECKREG r7, 0x72345660; + + I0 = B1; + I1 = B2; + I2 = B3; + I3 = B0; + M0 = B1; + M1 = B2; + M2 = B3; + M3 = B0; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x5EEEEEE0; + CHECKREG r1, 0x6FFFFFF0; + CHECKREG r2, 0x72345660; + CHECKREG r3, 0x4DDDDDD0; + CHECKREG r4, 0x5EEEEEE0; + CHECKREG r5, 0x6FFFFFF0; + CHECKREG r6, 0x72345660; + CHECKREG r7, 0x4DDDDDD0; + + I0 = B2; + I1 = B3; + I2 = B0; + I3 = B1; + M0 = B2; + M1 = B3; + M2 = B0; + M3 = B1; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x6FFFFFF0; + CHECKREG r1, 0x72345660; + CHECKREG r2, 0x4DDDDDD0; + CHECKREG r3, 0x5EEEEEE0; + CHECKREG r4, 0x6FFFFFF0; + CHECKREG r5, 0x72345660; + CHECKREG r6, 0x4DDDDDD0; + CHECKREG r7, 0x5EEEEEE0; + + I0 = B3; + I1 = B0; + I2 = B1; + I3 = B2; + M0 = B3; + M1 = B0; + M2 = B1; + M3 = B2; + + P1 = I1; + P2 = I2; + P3 = I3; + P4 = M0; + P5 = M1; + FP = M2; + SP = M3; + + CHECKREG p1, 0x4DDDDDD0; + CHECKREG p2, 0x5EEEEEE0; + CHECKREG p3, 0x6FFFFFF0; + CHECKREG p4, 0x72345660; + CHECKREG p5, 0x4DDDDDD0; + CHECKREG fp, 0x5EEEEEE0; + CHECKREG sp, 0x6FFFFFF0; + +// i to l & i to b + imm32 i0, 0x09999990; + imm32 i1, 0x1AAAAAA0; + imm32 i2, 0x2BBBBBB0; + imm32 i3, 0x3CCCCCC0; + + L0 = I0; + L1 = I1; + L2 = I2; + L3 = I3; + B0 = I0; + B1 = I1; + B2 = I2; + B3 = I3; + + L0 = I1; + L1 = I2; + L2 = I3; + L3 = I0; + B0 = I1; + B1 = I2; + B2 = I3; + B3 = I0; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x1AAAAAA0; + CHECKREG r1, 0x2BBBBBB0; + CHECKREG r2, 0x3CCCCCC0; + CHECKREG r3, 0x09999990; + CHECKREG r4, 0x1AAAAAA0; + CHECKREG r5, 0x2BBBBBB0; + CHECKREG r6, 0x3CCCCCC0; + CHECKREG r7, 0x09999990; + + L0 = I2; + L1 = I3; + L2 = I0; + L3 = I1; + B0 = I2; + B1 = I3; + B2 = I0; + B3 = I1; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x2BBBBBB0; + CHECKREG r1, 0x3CCCCCC0; + CHECKREG r2, 0x09999990; + CHECKREG r3, 0x1AAAAAA0; + CHECKREG r4, 0x2BBBBBB0; + CHECKREG r5, 0x3CCCCCC0; + CHECKREG r6, 0x09999990; + CHECKREG r7, 0x1AAAAAA0; + + imm32 l0, 0x09499091; + imm32 l1, 0x0A55A0A2; + imm32 l2, 0x0B6BB0B3; + imm32 l3, 0x0C7CC0C4; + imm32 b0, 0x0D8DD0D5; + imm32 b1, 0x0E9EE0E6; + imm32 b2, 0x0F0FF0F7; + imm32 b3, 0x12145068; + + L0 = I3; + L1 = I0; + L2 = I1; + L3 = I2; + B0 = I3; + B1 = I0; + B2 = I1; + B3 = I2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x3CCCCCC0; + CHECKREG r1, 0x09999990; + CHECKREG r2, 0x1AAAAAA0; + CHECKREG r3, 0x2BBBBBB0; + CHECKREG r4, 0x3CCCCCC0; + CHECKREG r5, 0x09999990; + CHECKREG r6, 0x1AAAAAA0; + CHECKREG r7, 0x2BBBBBB0; + +// m to l & m to b + imm32 m0, 0x4DDDDDD0; + imm32 m1, 0x5EEEEEE0; + imm32 m2, 0x6FFFFFF0; + imm32 m3, 0x72345660; + L0 = M0; + L1 = M1; + L2 = M2; + L3 = M3; + B0 = M0; + B1 = M1; + B2 = M2; + B3 = M3; + + R0 = I0; + R1 = I1; + R2 = I2; + R3 = I3; + R4 = M0; + R5 = M1; + R6 = M2; + R7 = M3; + + CHECKREG r0, 0x09999990; + CHECKREG r1, 0x1AAAAAA0; + CHECKREG r2, 0x2BBBBBB0; + CHECKREG r3, 0x3CCCCCC0; + CHECKREG r4, 0x4DDDDDD0; + CHECKREG r5, 0x5EEEEEE0; + CHECKREG r6, 0x6FFFFFF0; + CHECKREG r7, 0x72345660; + + imm32 l0, 0x01909910; + imm32 l1, 0x12A11220; + imm32 l2, 0x23B25530; + imm32 l3, 0x34C36640; + imm32 b0, 0x45D47750; + imm32 b1, 0x56E58860; + imm32 b2, 0x67F66676; + imm32 b3, 0x78375680; + + L0 = M1; + L1 = M2; + L2 = M3; + L3 = M0; + B0 = M1; + B1 = M2; + B2 = M3; + B3 = M0; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x5EEEEEE0; + CHECKREG r1, 0x6FFFFFF0; + CHECKREG r2, 0x72345660; + CHECKREG r3, 0x4DDDDDD0; + CHECKREG r4, 0x5EEEEEE0; + CHECKREG r5, 0x6FFFFFF0; + CHECKREG r6, 0x72345660; + CHECKREG r7, 0x4DDDDDD0; + + imm32 l0, 0x09909990; + imm32 l1, 0x1AA11230; + imm32 l2, 0x2BB25550; + imm32 l3, 0x3CC36660; + imm32 b0, 0x4DD47770; + imm32 b1, 0x5EE58880; + imm32 b2, 0x6FF66666; + imm32 b3, 0x72375660; + + L0 = M2; + L1 = M3; + L2 = M0; + L3 = M1; + B0 = M2; + B1 = M3; + B2 = M0; + B3 = M1; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x6FFFFFF0; + CHECKREG r1, 0x72345660; + CHECKREG r2, 0x4DDDDDD0; + CHECKREG r3, 0x5EEEEEE0; + CHECKREG r4, 0x6FFFFFF0; + CHECKREG r5, 0x72345660; + CHECKREG r6, 0x4DDDDDD0; + CHECKREG r7, 0x5EEEEEE0; + + L0 = M3; + L1 = M0; + L2 = M1; + L3 = M2; + B0 = M3; + B1 = M0; + B2 = M1; + B3 = M2; + + R0 = L0; + R1 = L1; + R2 = L2; + R3 = L3; + R4 = B0; + R5 = B1; + R6 = B2; + R7 = B3; + + CHECKREG r0, 0x72345660; + CHECKREG r1, 0x4DDDDDD0; + CHECKREG r2, 0x5EEEEEE0; + CHECKREG r3, 0x6FFFFFF0; + CHECKREG r4, 0x72345660; + CHECKREG r5, 0x4DDDDDD0; + CHECKREG r6, 0x5EEEEEE0; + CHECKREG r7, 0x6FFFFFF0; + + pass diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_pr.s b/sim/testsuite/sim/bfin/c_regmv_imlb_pr.s new file mode 100644 index 0000000..7e32a29 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_imlb_pr.s @@ -0,0 +1,302 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_pr/c_regmv_imlb_pr.dsp +// Spec Reference: regmv imlb to dr +# mach: bfin + +.include "testutils.inc" + start + +// initialize source regs + imm32 i0, 0x11111111; + imm32 i1, 0x22222222; + imm32 i2, 0x33333333; + imm32 i3, 0x44444444; + +// i to preg + R0 = I0; + P1 = I0; + P2 = I0; + P3 = I0; + P4 = I1; + P5 = I1; + SP = I1; + FP = I1; + CHECKREG r0, 0x11111111; + CHECKREG p1, 0x11111111; + CHECKREG p2, 0x11111111; + CHECKREG p3, 0x11111111; + CHECKREG p4, 0x22222222; + CHECKREG p5, 0x22222222; + CHECKREG sp, 0x22222222; + CHECKREG fp, 0x22222222; + + R0 = I1; + P1 = I1; + P2 = I1; + P3 = I1; + P4 = I0; + P5 = I0; + SP = I0; + FP = I0; + CHECKREG r0, 0x22222222; + CHECKREG p1, 0x22222222; + CHECKREG p2, 0x22222222; + CHECKREG p3, 0x22222222; + CHECKREG p4, 0x11111111; + CHECKREG p5, 0x11111111; + CHECKREG sp, 0x11111111; + CHECKREG fp, 0x11111111; + + R0 = I2; + P1 = I2; + P2 = I2; + P3 = I2; + P4 = I3; + P5 = I3; + SP = I3; + FP = I3; + CHECKREG r0, 0x33333333; + CHECKREG p1, 0x33333333; + CHECKREG p2, 0x33333333; + CHECKREG p3, 0x33333333; + CHECKREG p4, 0x44444444; + CHECKREG p5, 0x44444444; + CHECKREG sp, 0x44444444; + CHECKREG fp, 0x44444444; + + R0 = I3; + P1 = I3; + P2 = I3; + P3 = I3; + P4 = I2; + P5 = I2; + SP = I2; + FP = I2; + CHECKREG r0, 0x44444444; + CHECKREG p1, 0x44444444; + CHECKREG p2, 0x44444444; + CHECKREG p3, 0x44444444; + CHECKREG p4, 0x33333333; + CHECKREG p5, 0x33333333; + CHECKREG sp, 0x33333333; + CHECKREG fp, 0x33333333; + + imm32 m0, 0x55555555; + imm32 m1, 0x66666666; + imm32 m2, 0x77777777; + imm32 m3, 0x88888888; +// m to preg + R0 = M0; + P1 = M0; + P2 = M0; + P3 = M0; + P4 = M1; + P5 = M1; + SP = M1; + FP = M1; + CHECKREG r0, 0x55555555; + CHECKREG p1, 0x55555555; + CHECKREG p2, 0x55555555; + CHECKREG p3, 0x55555555; + CHECKREG p4, 0x66666666; + CHECKREG p5, 0x66666666; + CHECKREG sp, 0x66666666; + CHECKREG fp, 0x66666666; + + R0 = M1; + P1 = M1; + P2 = M1; + P3 = M1; + P4 = M0; + P5 = M0; + SP = M0; + FP = M0; + CHECKREG r0, 0x66666666; + CHECKREG p1, 0x66666666; + CHECKREG p2, 0x66666666; + CHECKREG p3, 0x66666666; + CHECKREG p4, 0x55555555; + CHECKREG p5, 0x55555555; + CHECKREG sp, 0x55555555; + CHECKREG fp, 0x55555555; + + R0 = M2; + P1 = M2; + P2 = M2; + P3 = M2; + P4 = M3; + P5 = M3; + SP = M3; + FP = M3; + CHECKREG r0, 0x77777777; + CHECKREG p1, 0x77777777; + CHECKREG p2, 0x77777777; + CHECKREG p3, 0x77777777; + CHECKREG p4, 0x88888888; + CHECKREG p5, 0x88888888; + CHECKREG sp, 0x88888888; + CHECKREG fp, 0x88888888; + + R0 = M3; + P1 = M3; + P2 = M3; + P3 = M3; + P4 = M2; + P5 = M2; + SP = M2; + FP = M2; + CHECKREG r0, 0x88888888; + CHECKREG p1, 0x88888888; + CHECKREG p2, 0x88888888; + CHECKREG p3, 0x88888888; + CHECKREG p4, 0x77777777; + CHECKREG p5, 0x77777777; + CHECKREG sp, 0x77777777; + CHECKREG fp, 0x77777777; + + imm32 l0, 0x99999999; + imm32 l1, 0xaaaaaaaa; + imm32 l2, 0xbbbbbbbb; + imm32 l3, 0xcccccccc; +// l to preg + R0 = L0; + P1 = L0; + P2 = L0; + P3 = L0; + P4 = L1; + P5 = L1; + SP = L1; + FP = L1; + CHECKREG r0, 0x99999999; + CHECKREG p1, 0x99999999; + CHECKREG p2, 0x99999999; + CHECKREG p3, 0x99999999; + CHECKREG p4, 0xaaaaaaaa; + CHECKREG p5, 0xaaaaaaaa; + CHECKREG sp, 0xaaaaaaaa; + CHECKREG fp, 0xaaaaaaaa; + + R0 = L1; + P1 = L1; + P2 = L1; + P3 = L1; + P4 = L0; + P5 = L0; + SP = L0; + FP = L0; + CHECKREG r0, 0xaaaaaaaa; + CHECKREG p1, 0xaaaaaaaa; + CHECKREG p2, 0xaaaaaaaa; + CHECKREG p3, 0xaaaaaaaa; + CHECKREG p4, 0x99999999; + CHECKREG p5, 0x99999999; + CHECKREG sp, 0x99999999; + CHECKREG fp, 0x99999999; + + R0 = L2; + P1 = L2; + P2 = L2; + P3 = L2; + P4 = L3; + P5 = L3; + SP = L3; + FP = L3; + CHECKREG r0, 0xbbbbbbbb; + CHECKREG p1, 0xbbbbbbbb; + CHECKREG p2, 0xbbbbbbbb; + CHECKREG p3, 0xbbbbbbbb; + CHECKREG p4, 0xcccccccc; + CHECKREG p5, 0xcccccccc; + CHECKREG sp, 0xcccccccc; + CHECKREG fp, 0xcccccccc; + + R0 = L3; + P1 = L3; + P2 = L3; + P3 = L3; + P4 = L2; + P5 = L2; + SP = L2; + FP = L2; + CHECKREG r0, 0xcccccccc; + CHECKREG p1, 0xcccccccc; + CHECKREG p2, 0xcccccccc; + CHECKREG p3, 0xcccccccc; + CHECKREG p4, 0xbbbbbbbb; + CHECKREG p5, 0xbbbbbbbb; + CHECKREG sp, 0xbbbbbbbb; + CHECKREG fp, 0xbbbbbbbb; + + imm32 b0, 0xdddddddd; + imm32 b1, 0xeeeeeeee; + imm32 b2, 0xffffffff; + imm32 b3, 0x12345678; +// b to preg + R0 = B0; + P1 = B0; + P2 = B0; + P3 = B0; + P4 = B1; + P5 = B1; + SP = B1; + FP = B1; + CHECKREG r0, 0xdddddddd; + CHECKREG p1, 0xdddddddd; + CHECKREG p2, 0xdddddddd; + CHECKREG p3, 0xdddddddd; + CHECKREG p4, 0xeeeeeeee; + CHECKREG p5, 0xeeeeeeee; + CHECKREG sp, 0xeeeeeeee; + CHECKREG fp, 0xeeeeeeee; + + R0 = B1; + P1 = B1; + P2 = B1; + P3 = B1; + P4 = B0; + P5 = B0; + SP = B0; + FP = B0; + CHECKREG r0, 0xeeeeeeee; + CHECKREG p1, 0xeeeeeeee; + CHECKREG p2, 0xeeeeeeee; + CHECKREG p3, 0xeeeeeeee; + CHECKREG p4, 0xdddddddd; + CHECKREG p5, 0xdddddddd; + CHECKREG sp, 0xdddddddd; + CHECKREG fp, 0xdddddddd; + + R0 = B2; + P1 = B2; + P2 = B2; + P3 = B2; + P4 = B3; + P5 = B3; + SP = B3; + FP = B3; + CHECKREG r0, 0xffffffff; + CHECKREG p1, 0xffffffff; + CHECKREG p2, 0xffffffff; + CHECKREG p3, 0xffffffff; + CHECKREG p4, 0x12345678; + CHECKREG p5, 0x12345678; + CHECKREG sp, 0x12345678; + CHECKREG fp, 0x12345678; + + R0 = B3; + P1 = B3; + P2 = B3; + P3 = B3; + P4 = B2; + P5 = B2; + SP = B2; + FP = B2; + CHECKREG r0, 0x12345678; + CHECKREG p1, 0x12345678; + CHECKREG p2, 0x12345678; + CHECKREG p3, 0x12345678; + CHECKREG p4, 0xffffffff; + CHECKREG p5, 0xffffffff; + CHECKREG sp, 0xffffffff; + CHECKREG fp, 0xffffffff; + + pass diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_dep_nostall.s b/sim/testsuite/sim/bfin/c_regmv_pr_dep_nostall.s new file mode 100644 index 0000000..5525bea --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_pr_dep_nostall.s @@ -0,0 +1,280 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_nostall/c_regmv_pr_dep_nostall.dsp +// Spec Reference: regmv pr-dep no stall +# mach: bfin + +.include "testutils.inc" + start + +//imm32 p0, 0x00001111; + imm32 p1, 0x32213330; + imm32 p2, 0x34415550; + imm32 p3, 0x36617770; + imm32 p4, 0x38819990; + imm32 p5, 0x3aa1bbb0; + imm32 fp, 0x3cc1ddd0; + imm32 sp, 0x3ee1fff0; +// P-reg to P-reg to R-reg: no stall + P4 = P1; + R1 = P4; + SP = P5; + R2 = SP; + P1 = FP; + R3 = P1; + CHECKREG r1, 0x32213330; + CHECKREG r2, 0x3AA1BBB0; + CHECKREG r3, 0x3CC1DDD0; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22213332; + imm32 p2, 0x44415552; + imm32 p3, 0x66617772; + imm32 p4, 0x88819992; + imm32 p5, 0xaaa1bbb2; + imm32 fp, 0xccc1ddd2; + imm32 sp, 0xeee1fff2; + +// P-reg to P-reg to I reg: no stall + P1 = P2; + I0 = P1; + P3 = P2; + I1 = P3; + P5 = P4; + I2 = P5; + FP = SP; + I3 = FP; + + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; + CHECKREG r4, 0xEEE1FFF2; + CHECKREG r5, 0x88819992; + CHECKREG r6, 0x44415552; + CHECKREG r7, 0x44415552; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22213332; + imm32 p2, 0x44415552; + imm32 p3, 0x66617772; + imm32 p4, 0x88819992; + imm32 p5, 0xaaa1bbb2; + imm32 fp, 0xccc1ddd2; + imm32 sp, 0xe111fff2; + +// P-reg to P-reg to M reg: no stall + P1 = P4; + M0 = P1; + P3 = P2; + M1 = P3; + P5 = P4; + M2 = P5; + FP = SP; + M3 = FP; + + R4 = M3; + R5 = M2; + R6 = M1; + R7 = M0; + CHECKREG r4, 0xE111FFF2; + CHECKREG r5, 0x88819992; + CHECKREG r6, 0x44415552; + CHECKREG r7, 0x88819992; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22213332; + imm32 p2, 0x44215552; + imm32 p3, 0x66217772; + imm32 p4, 0x88219992; + imm32 p5, 0xaa21bbb2; + imm32 fp, 0xcc21ddd2; + imm32 sp, 0xee21fff2; + +// P-reg to P-reg to L reg: no stall + P1 = P0; + L0 = P1; + P3 = P2; + L1 = P3; + P5 = P4; + L2 = P5; + FP = SP; + L3 = FP; + + R4 = L3; + R5 = L2; + R6 = L1; + R7 = L0; + CHECKREG r4, 0xEE21FFF2; + CHECKREG r5, 0x88219992; + CHECKREG r6, 0x44215552; + +//imm32 p0, 0x00001111; + imm32 p1, 0x22213332; + imm32 p2, 0x44415532; + imm32 p3, 0x66617732; + imm32 p4, 0x88819932; + imm32 p5, 0xaaa1bb32; + imm32 fp, 0xccc1dd32; + imm32 sp, 0xeee1ff32; + +// P-reg to P-reg to B reg: no stall + P1 = FP; + B0 = P1; + P3 = P2; + B1 = P3; + P5 = P4; + B2 = P5; + FP = SP; + B3 = FP; + + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r4, 0xEEE1FF32; + CHECKREG r5, 0x88819932; + CHECKREG r6, 0x44415532; + CHECKREG r7, 0xccc1dd32; + + imm32 i0, 0x03001131; + imm32 i1, 0x23223333; + imm32 i2, 0x43445535; + imm32 i3, 0x63667737; + imm32 m0, 0x83889939; + imm32 m1, 0xa3aabb3b; + imm32 m2, 0xc3ccdd3d; + imm32 m3, 0xe3eeff3f; + +// I,M-reg to P-reg to R-reg: no stall + P1 = I0; + R0 = P1; + P2 = I1; + R1 = P2; + P3 = I2; + R2 = P3; + P4 = I3; + R3 = P4; + P5 = M0; + R4 = P5; + SP = M1; + R5 = SP; + FP = M2; + R6 = FP; + FP = M3; + R7 = FP; + + CHECKREG r0, 0x03001131; + CHECKREG r1, 0x23223333; + CHECKREG r2, 0x43445535; + CHECKREG r3, 0x63667737; + CHECKREG r4, 0x83889939; + CHECKREG r5, 0xA3AABB3B; + CHECKREG r6, 0xC3CCDD3D; + CHECKREG r7, 0xE3EEFF3F; + + imm32 i0, 0x12001111; + imm32 i1, 0x12221333; + imm32 i2, 0x12441555; + imm32 i3, 0x12661777; + imm32 m0, 0x12881999; + imm32 m1, 0x12aa1bbb; + imm32 m2, 0x12cc1ddd; + imm32 m3, 0x12ee1fff; + +// I,M-reg to P-reg to L,B reg: no stall + P1 = I0; + L0 = P1; + P1 = I1; + L1 = P1; + P2 = I2; + L2 = P2; + P3 = I3; + L3 = P3; + P4 = M0; + B0 = P4; + P5 = M1; + B1 = P5; + SP = M2; + B2 = SP; + FP = M3; + B3 = FP; + +//CHECKREG r0, 0x12001111; + CHECKREG p1, 0x12221333; + CHECKREG p2, 0x12441555; + CHECKREG p3, 0x12661777; + CHECKREG p4, 0x12881999; + CHECKREG p5, 0x12AA1BBB; + CHECKREG sp, 0x12CC1DDD; + CHECKREG fp, 0x12EE1FFF; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x12661777; + CHECKREG r1, 0x12441555; + CHECKREG r2, 0x12221333; + CHECKREG r3, 0x12001111; + CHECKREG r4, 0x12EE1FFF; + CHECKREG r5, 0x12CC1DDD; + CHECKREG r6, 0x12AA1BBB; + CHECKREG r7, 0x12881999; + + imm32 l0, 0x23003111; + imm32 l1, 0x23223333; + imm32 l2, 0x23443555; + imm32 l3, 0x23663777; + imm32 b0, 0x23883999; + imm32 b0, 0x23aa3bbb; + imm32 b0, 0x23cc3ddd; + imm32 b0, 0x23ee3fff; + +// L,B-reg to P-reg to I,M reg: no stall + P1 = L0; + I0 = P1; + P1 = L1; + I1 = P1; + P2 = L2; + I2 = P2; + P3 = L3; + I3 = P3; + P4 = B0; + M0 = P4; + P5 = B1; + M1 = P5; + SP = B2; + M2 = SP; + FP = B3; + M3 = FP; + + R0 = M3; + R1 = M2; + R2 = M1; + R3 = M0; + R4 = I3; + R5 = I2; + R6 = I1; + R7 = I0; +//CHECKREG r0, 0x1EEE1FFF; + CHECKREG p1, 0x23223333; + CHECKREG p2, 0x23443555; + CHECKREG p3, 0x23663777; + CHECKREG p4, 0x23EE3FFF; + CHECKREG p5, 0x12AA1BBB; + CHECKREG sp, 0x12CC1DDD; + CHECKREG fp, 0x12EE1FFF; + + CHECKREG r0, 0x12EE1FFF; + CHECKREG r1, 0x12CC1DDD; + CHECKREG r2, 0x12AA1BBB; + CHECKREG r3, 0x23EE3FFF; + CHECKREG r4, 0x23663777; + CHECKREG r5, 0x23443555; + CHECKREG r6, 0x23223333; + CHECKREG r7, 0x23003111; + + pass diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_dep_stall.s b/sim/testsuite/sim/bfin/c_regmv_pr_dep_stall.s new file mode 100644 index 0000000..91dd0f8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_pr_dep_stall.s @@ -0,0 +1,237 @@ +//Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_stall/c_regmv_pr_dep_stall.dsp +// Spec Reference: regmv pr-dependency stall +# mach: bfin + +.include "testutils.inc" + start + + INIT_M_REGS 0; + +// R-reg to P-reg to R reg: stall + imm32 r0, 0x00001110; + imm32 r1, 0x00213330; + imm32 r2, 0x04015550; + imm32 r3, 0x06607770; + imm32 r4, 0x08810990; + imm32 r5, 0x01a1b0b0; + imm32 r6, 0x01c1dd00; + imm32 r7, 0x01e1fff0; + P1 = R1; + R0 = P1; + P2 = R2; + R1 = P2; + P3 = R3; + R2 = P3; + P4 = R4; + R3 = P4; + P5 = R5; + R4 = P5; + SP = R6; + R5 = P2; + FP = R7; + R6 = P3; + + CHECKREG r0, 0x00213330; + CHECKREG r1, 0x04015550; + CHECKREG r2, 0x06607770; + CHECKREG r3, 0x08810990; + CHECKREG r4, 0x01A1B0B0; + CHECKREG r5, 0x04015550; + CHECKREG r6, 0x06607770; + CHECKREG r7, 0x01E1FFF0; + +// R-reg to P-reg to I,M reg: stall + imm32 r0, 0x10001111; + imm32 r1, 0x11213331; + imm32 r2, 0x14115551; + imm32 r3, 0x16617771; + imm32 r4, 0x18811991; + imm32 r5, 0x11a1b1b1; + imm32 r6, 0x11c1dd11; + imm32 r7, 0x11e1fff1; + P1 = R0; + I0 = P1; + P2 = R1; + I1 = P2; + P3 = R2; + I2 = P3; + P4 = R3; + I3 = P4; + P5 = R4; + M0 = P5; + SP = R5; + M1 = SP; + FP = R6; + M2 = FP; + + R0 = I3; + R1 = I2; + R2 = I1; + R3 = I0; + R4 = M3; + R5 = M2; + R6 = M1; + R7 = M0; + CHECKREG r0, 0x16617771; + CHECKREG r1, 0x14115551; + CHECKREG r2, 0x11213331; + CHECKREG r3, 0x10001111; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x11C1DD11; + CHECKREG r6, 0x11A1B1B1; + CHECKREG r7, 0x18811991; + + CHECKREG p1, 0x10001111; + CHECKREG p2, 0x11213331; + CHECKREG p3, 0x14115551; + CHECKREG p4, 0x16617771; + CHECKREG p5, 0x18811991; + CHECKREG sp, 0x11A1B1B1; + CHECKREG fp, 0x11C1DD11; + + imm32 r0, 0x20001112; + imm32 r1, 0x21213332; + imm32 r2, 0x24115552; + imm32 r3, 0x26617772; + imm32 r4, 0x28811992; + imm32 r5, 0x21a1b1b2; + imm32 r6, 0x21c1dd12; + imm32 r7, 0x21e1fff2; + P1 = R3; + I3 = P1; + P2 = R4; + I0 = P2; + P3 = R5; + I1 = P3; + P4 = R6; + I2 = P4; + P5 = R7; + M1 = P5; + SP = R0; + M2 = SP; + FP = R1; + M3 = FP; + + R0 = I3; + R1 = I2; + R2 = I1; + R3 = I0; + R4 = M3; + R5 = M2; + R6 = M1; + R7 = M0; + CHECKREG r0, 0x26617772; + CHECKREG r1, 0x21C1DD12; + CHECKREG r2, 0x21A1B1B2; + CHECKREG r3, 0x28811992; + CHECKREG r4, 0x21213332; + CHECKREG r5, 0x20001112; + CHECKREG r6, 0x21E1FFF2; + CHECKREG r7, 0x18811991; + + CHECKREG p1, 0x26617772; + CHECKREG p2, 0x28811992; + CHECKREG p3, 0x21A1B1B2; + CHECKREG p4, 0x21C1DD12; + CHECKREG p5, 0x21E1FFF2; + CHECKREG sp, 0x20001112; + CHECKREG fp, 0x21213332; + +// R-reg to P-reg to L,B reg: stall + imm32 r0, 0x30001113; + imm32 r1, 0x31213333; + imm32 r2, 0x34115553; + imm32 r3, 0x36617773; + imm32 r4, 0x38811993; + imm32 r5, 0x31a1b1b3; + imm32 r6, 0x31c1dd13; + imm32 r7, 0x31e1fff3; + P1 = R4; + L0 = P1; + P2 = R5; + L1 = P2; + P3 = R6; + L2 = P3; + P4 = R7; + L3 = P4; + P5 = R0; + B0 = P5; + SP = R1; + B1 = SP; + FP = R2; + B2 = FP; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x31E1FFF3; + CHECKREG r1, 0x31C1DD13; + CHECKREG r2, 0x31A1B1B3; + CHECKREG r3, 0x38811993; + CHECKREG r4, 0x00000000; + CHECKREG r5, 0x34115553; + CHECKREG r6, 0x31213333; + CHECKREG r7, 0x30001113; + + CHECKREG p1, 0x38811993; + CHECKREG p2, 0x31A1B1B3; + CHECKREG p3, 0x31C1DD13; + CHECKREG p4, 0x31E1FFF3; + CHECKREG p5, 0x30001113; + CHECKREG sp, 0x31213333; + CHECKREG fp, 0x34115553; + + imm32 r0, 0x40001114; + imm32 r1, 0x44213334; + imm32 r2, 0x44415554; + imm32 r3, 0x46647774; + imm32 r4, 0x48814994; + imm32 r5, 0x41a1b4b4; + imm32 r6, 0x41c1dd44; + imm32 r7, 0x41e1fff4; + P1 = R5; + L2 = P1; + P2 = R6; + L3 = P2; + P3 = R7; + L0 = P3; + P4 = R0; + L1 = P4; + P5 = R1; + B2 = P5; + SP = R2; + B3 = SP; + FP = R3; + B0 = FP; + + R0 = L3; + R1 = L2; + R2 = L1; + R3 = L0; + R4 = B3; + R5 = B2; + R6 = B1; + R7 = B0; + CHECKREG r0, 0x41C1DD44; + CHECKREG r1, 0x41A1B4B4; + CHECKREG r2, 0x40001114; + CHECKREG r3, 0x41E1FFF4; + CHECKREG r4, 0x44415554; + CHECKREG r5, 0x44213334; + CHECKREG r6, 0x31213333; + CHECKREG r7, 0x46647774; + + CHECKREG p1, 0x41A1B4B4; + CHECKREG p2, 0x41C1DD44; + CHECKREG p3, 0x41E1FFF4; + CHECKREG p4, 0x40001114; + CHECKREG p5, 0x44213334; + CHECKREG sp, 0x44415554; + CHECKREG fp, 0x46647774; + + pass diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_dr.s b/sim/testsuite/sim/bfin/c_regmv_pr_dr.s new file mode 100644 index 0000000..fe1826f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_pr_dr.s @@ -0,0 +1,147 @@ +//Original:/testcases/core/c_regmv_pr_dr/c_regmv_pr_dr.dsp +// Spec Reference: regmv preg to dreg +# mach: bfin + +.include "testutils.inc" + start + + + + + +imm32 r0, 0x00000001; +imm32 r1, 0x00020003; +imm32 r2, 0x00040005; +imm32 r3, 0x00060007; +imm32 r4, 0x00080009; +imm32 r5, 0x000a000b; +imm32 r6, 0x000c000d; +imm32 r7, 0x000e000f; + +//imm32 p0, 0x00000001; +imm32 p1, 0x10082001; +imm32 p2, 0x10092002; +imm32 p3, 0x100a2003; +imm32 p4, 0x100b2004; +imm32 p5, 0x100c2005; +imm32 sp, 0x100d2006; +imm32 fp, 0x100e2007; + +//--------- Preg to dreg : Rx <= Px ------ + + +R0 = P1; +R1 = P1; +R2 = P1; +R3 = P1; +R4 = P1; +R5 = P1; +R6 = P1; +R7 = P1; +CHECKREG r1, 0x10082001; +CHECKREG r2, 0x10082001; +CHECKREG r3, 0x10082001; +CHECKREG r4, 0x10082001; +CHECKREG r5, 0x10082001; +CHECKREG r6, 0x10082001; +CHECKREG r7, 0x10082001; + +R0 = P2; +R1 = P2; +R2 = P2; +R3 = P2; +R4 = P2; +R5 = P2; +R6 = P2; +R7 = P2; +CHECKREG r0, 0x10092002; +CHECKREG r1, 0x10092002; +CHECKREG r2, 0x10092002; +CHECKREG r3, 0x10092002; +CHECKREG r4, 0x10092002; +CHECKREG r5, 0x10092002; +CHECKREG r6, 0x10092002; +CHECKREG r7, 0x10092002; + +R0 = P3; +R1 = P3; +R2 = P3; +R3 = P3; +R4 = P3; +R5 = P3; +R6 = P3; +R7 = P3; +CHECKREG r1, 0x100a2003; +CHECKREG r2, 0x100a2003; +CHECKREG r3, 0x100a2003; +CHECKREG r4, 0x100a2003; +CHECKREG r5, 0x100a2003; +CHECKREG r6, 0x100a2003; +CHECKREG r7, 0x100a2003; + +R0 = P4; +R1 = P4; +R2 = P4; +R3 = P4; +R4 = P4; +R5 = P4; +R6 = P4; +R7 = P4; +CHECKREG r0, 0x100b2004; +CHECKREG r1, 0x100b2004; +CHECKREG r2, 0x100b2004; +CHECKREG r3, 0x100b2004; +CHECKREG r4, 0x100b2004; +CHECKREG r5, 0x100b2004; +CHECKREG r6, 0x100b2004; +CHECKREG r7, 0x100b2004; + +R1 = P5; +R2 = P5; +R3 = P5; +R4 = P5; +R5 = P5; +R6 = P5; +R7 = P5; +CHECKREG r1, 0x100c2005; +CHECKREG r2, 0x100c2005; +CHECKREG r3, 0x100c2005; +CHECKREG r4, 0x100c2005; +CHECKREG r5, 0x100c2005; +CHECKREG r6, 0x100c2005; +CHECKREG r7, 0x100c2005; + +R0 = SP; +R1 = SP; +R2 = SP; +R3 = SP; +R4 = SP; +R5 = SP; +R6 = SP; +R7 = SP; +CHECKREG r0, 0x100d2006; +CHECKREG r1, 0x100d2006; +CHECKREG r2, 0x100d2006; +CHECKREG r3, 0x100d2006; +CHECKREG r4, 0x100d2006; +CHECKREG r5, 0x100d2006; +CHECKREG r6, 0x100d2006; +CHECKREG r7, 0x100d2006; + +R0 = FP; +R1 = FP; +R2 = FP; +R3 = FP; +R4 = FP; +R5 = FP; +R6 = FP; +R7 = FP; +CHECKREG r1, 0x100e2007; +CHECKREG r2, 0x100e2007; +CHECKREG r3, 0x100e2007; +CHECKREG r4, 0x100e2007; +CHECKREG r5, 0x100e2007; +CHECKREG r6, 0x100e2007; +CHECKREG r7, 0x100e2007; + +pass diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_imlb.s b/sim/testsuite/sim/bfin/c_regmv_pr_imlb.s new file mode 100644 index 0000000..31ff3e9 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_pr_imlb.s @@ -0,0 +1,382 @@ +//Original:/testcases/core/c_regmv_pr_imlb/c_regmv_pr_imlb.dsp +// Spec Reference: regmv preg-to-imlb reg +# mach: bfin + +.include "testutils.inc" + start + +// check R-reg to imlb-reg move + +imm32 r0, 0x00000001; +imm32 p1, 0x00020003; +imm32 p2, 0x00040005; +imm32 p3, 0x00060007; +imm32 p4, 0x00080009; +imm32 p5, 0x000a000b; +imm32 sp, 0x000c000d; +imm32 fp, 0x000e000f; +I0 = P1; +I1 = P1; +I2 = P1; +I3 = P1; +M0 = P1; +M1 = P1; +M2 = P1; +M3 = P1; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 p2, 0x00040005; +I0 = P2; +I1 = P2; +I2 = P2; +I3 = P2; +M0 = P2; +M1 = P2; +M2 = P2; +M3 = P2; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 p3, 0x00060007; +I0 = P3; +I1 = P3; +I2 = P3; +I3 = P3; +M0 = P3; +M1 = P3; +M2 = P3; +M3 = P3; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 p4, 0x00080009; +I0 = P4; +I1 = P4; +I2 = P4; +I3 = P4; +M0 = P4; +M1 = P4; +M2 = P4; +M3 = P4; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 p5, 0x000a000b; +I0 = P5; +I1 = P5; +I2 = P5; +I3 = P5; +M0 = P5; +M1 = P5; +M2 = P5; +M3 = P5; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 sp, 0x000c000d; +I0 = SP; +I1 = SP; +I2 = SP; +I3 = SP; +M0 = SP; +M1 = SP; +M2 = SP; +M3 = SP; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 fp, 0x000e000f; +I0 = FP; +I1 = FP; +I2 = FP; +I3 = FP; +M0 = FP; +M1 = FP; +M2 = FP; +M3 = FP; +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +R4 = M0; +R5 = M1; +R6 = M2; +R7 = M3; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + + +imm32 p1, 0x00020003; +L0 = P1; +L1 = P1; +L2 = P1; +L3 = P1; +B0 = P1; +B1 = P1; +B2 = P1; +B3 = P1; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00020003; +CHECKREG r1, 0x00020003; +CHECKREG r2, 0x00020003; +CHECKREG r3, 0x00020003; +CHECKREG r4, 0x00020003; +CHECKREG r5, 0x00020003; +CHECKREG r6, 0x00020003; +CHECKREG r7, 0x00020003; + +imm32 p2, 0x00040005; +L0 = P2; +L1 = P2; +L2 = P2; +L3 = P2; +B0 = P2; +B1 = P2; +B2 = P2; +B3 = P2; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00040005; +CHECKREG r1, 0x00040005; +CHECKREG r2, 0x00040005; +CHECKREG r3, 0x00040005; +CHECKREG r4, 0x00040005; +CHECKREG r5, 0x00040005; +CHECKREG r6, 0x00040005; +CHECKREG r7, 0x00040005; + +imm32 p3, 0x00060007; +L0 = P3; +L1 = P3; +L2 = P3; +L3 = P3; +B0 = P3; +B1 = P3; +B2 = P3; +B3 = P3; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00060007; +CHECKREG r1, 0x00060007; +CHECKREG r2, 0x00060007; +CHECKREG r3, 0x00060007; +CHECKREG r4, 0x00060007; +CHECKREG r5, 0x00060007; +CHECKREG r6, 0x00060007; +CHECKREG r7, 0x00060007; + +imm32 p4, 0x00080009; +L0 = P4; +L1 = P4; +L2 = P4; +L3 = P4; +B0 = P4; +B1 = P4; +B2 = P4; +B3 = P4; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x00080009; +CHECKREG r1, 0x00080009; +CHECKREG r2, 0x00080009; +CHECKREG r3, 0x00080009; +CHECKREG r4, 0x00080009; +CHECKREG r5, 0x00080009; +CHECKREG r6, 0x00080009; +CHECKREG r7, 0x00080009; + +imm32 p5, 0x000a000b; +L0 = P5; +L1 = P5; +L2 = P5; +L3 = P5; +B0 = P5; +B1 = P5; +B2 = P5; +B3 = P5; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000a000b; +CHECKREG r1, 0x000a000b; +CHECKREG r2, 0x000a000b; +CHECKREG r3, 0x000a000b; +CHECKREG r4, 0x000a000b; +CHECKREG r5, 0x000a000b; +CHECKREG r6, 0x000a000b; +CHECKREG r7, 0x000a000b; + +imm32 sp, 0x000c000d; +L0 = SP; +L1 = SP; +L2 = SP; +L3 = SP; +B0 = SP; +B1 = SP; +B2 = SP; +B3 = SP; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000c000d; +CHECKREG r1, 0x000c000d; +CHECKREG r2, 0x000c000d; +CHECKREG r3, 0x000c000d; +CHECKREG r4, 0x000c000d; +CHECKREG r5, 0x000c000d; +CHECKREG r6, 0x000c000d; +CHECKREG r7, 0x000c000d; + +imm32 fp, 0x000e000f; +L0 = FP; +L1 = FP; +L2 = FP; +L3 = FP; +B0 = FP; +B1 = FP; +B2 = FP; +B3 = FP; +R0 = L0; +R1 = L1; +R2 = L2; +R3 = L3; +R4 = B0; +R5 = B1; +R6 = B2; +R7 = B3; +CHECKREG r0, 0x000e000f; +CHECKREG r1, 0x000e000f; +CHECKREG r2, 0x000e000f; +CHECKREG r3, 0x000e000f; +CHECKREG r4, 0x000e000f; +CHECKREG r5, 0x000e000f; +CHECKREG r6, 0x000e000f; +CHECKREG r7, 0x000e000f; + +pass diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_pr.s b/sim/testsuite/sim/bfin/c_regmv_pr_pr.s new file mode 100644 index 0000000..9fb83f6 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_regmv_pr_pr.s @@ -0,0 +1,95 @@ +//Original:/testcases/core/c_regmv_pr_pr/c_regmv_pr_pr.dsp +// Spec Reference: regmv preg-to-preg +# mach: bfin + +.include "testutils.inc" + start + +// check p-reg to p-reg move + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = P1; + P2 = P1; + P4 = P1; + P5 = P1; + FP = P1; + CHECKREG p1, 0x20021003; + CHECKREG p2, 0x20021003; + CHECKREG p4, 0x20021003; + CHECKREG p5, 0x20021003; + CHECKREG fp, 0x20021003; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = P2; + P2 = P2; + P4 = P2; + P5 = P2; + FP = P2; + CHECKREG p1, 0x20041005; + CHECKREG p2, 0x20041005; + CHECKREG p4, 0x20041005; + CHECKREG p5, 0x20041005; + CHECKREG fp, 0x20041005; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = P4; + P2 = P4; + P4 = P4; + P5 = P4; + FP = P4; + CHECKREG p1, 0x20081009; + CHECKREG p2, 0x20081009; + CHECKREG p4, 0x20081009; + CHECKREG p5, 0x20081009; + CHECKREG fp, 0x20081009; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = P5; + P2 = P5; + P4 = P5; + P5 = P5; + FP = P5; + CHECKREG p1, 0x200a100b; + CHECKREG p2, 0x200a100b; + CHECKREG p4, 0x200a100b; + CHECKREG p5, 0x200a100b; + CHECKREG fp, 0x200a100b; + + imm32 p1, 0x20021003; + imm32 p2, 0x20041005; + imm32 p4, 0x20081009; + imm32 p5, 0x200a100b; + imm32 fp, 0x200e100f; + P1 = FP; + P2 = FP; + P4 = FP; + P5 = FP; + FP = FP; + CHECKREG p1, 0x200e100f; + CHECKREG p2, 0x200e100f; + CHECKREG p4, 0x200e100f; + CHECKREG p5, 0x200e100f; + CHECKREG fp, 0x200e100f; + + pass diff --git a/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S b/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S new file mode 100644 index 0000000..fb231d3 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S @@ -0,0 +1,342 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv/c_seq_ac_raise_mv.dsp +// Spec Reference: sequencer stage AC (raise + regmv) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0xa01 (X); + R1 = 0xb02 (X); + R2 = 0xc03 (X); + R3 = 0xd04 (X); + R4 = 0xe05 (X); + R5 = 0xf06 (X); + R6 = 0x107 (X); + R7 = 0x208 (X); +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + +RAISE 2; // RTN + P1 = R7; + R0 = P1; +// [--sp] = (r7-r0); + +RAISE 5; // RTI + P2 = R6; + R1 = P2; + +// [--sp] = (r7-r1); + + +RAISE 6; // RTI + P3 = R5; + R2 = P3; + [ -- SP ] = ( R7:2 ); +// POP + +RAISE 7; // RTI + P4 = R4; + R3 = P4; +// (r7-r2) = [sp++]; + + + +CHECKREG(r0, 0x00000208); +CHECKREG(r1, 0x00000107); +CHECKREG(r2, 0x00000F06); +CHECKREG(r3, 0x00000E05); +CHECKREG(r4, 0x00000E05); +CHECKREG(r5, 0x00000F06); +CHECKREG(r6, 0x00000107); +CHECKREG(r7, 0x00000208); + + R0 = 0xa41 (X); + R1 = 0xb52 (X); + R2 = 0xc63 (X); + R3 = 0xd74 (X); + R4 = 0xe85 (X); + R5 = 0xf96 (X); + R6 = 0x1a7 (X); + R7 = 0x2b8 (X); +RAISE 8; // RTI + P1 = R0; + R6 = P1; +// (r7-r1) = [sp++]; +CHECKREG(r0, 0x00000A41); +CHECKREG(r1, 0x00000B52); +CHECKREG(r2, 0x00000C63); +CHECKREG(r3, 0x00000D74); +CHECKREG(r4, 0x00000E85); +CHECKREG(r5, 0x00000F96); +CHECKREG(r6, 0x00000A41); +CHECKREG(r7, 0x000002B8); + +RAISE 9; // RTI + P2 = R1; + R7 = P2; +// (r7-r0) = [sp++]; + +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); +CHECKREG(r4, 0x00000E85); +CHECKREG(r5, 0x00000F96); +CHECKREG(r6, 0x00000A41); +CHECKREG(r7, 0x00000B52); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I0 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I1 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I2 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I3 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S b/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S new file mode 100644 index 0000000..f5fdd4a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S @@ -0,0 +1,359 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv_ppop/c_seq_ac_raise_mv_ppop.dsp +// Spec Reference: sequencer stage AC (raise + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + +RAISE 2; // RTN + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:1 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +RAISE 6; // RTI + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:2 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:2 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000024); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); + +RAISE 8; // RTI + P1 = R1; + R5 = P1; + ( R7:1 ) = [ SP ++ ]; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + +RAISE 9; // RTI + P2 = R2; + R5 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S b/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S new file mode 100644 index 0000000..163b2ed --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S @@ -0,0 +1,359 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ac_regmv_pushpop/c_seq_ac_regmv_pushpop.dsp +// Spec Reference: sequencer stage AC (regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + //RAISE 2; // RTN + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + + //RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:1 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + + //RAISE 6; // RTI + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:2 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + + //RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:2 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000024); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); + + //RAISE 8; // RTI + P1 = R1; + R5 = P1; + ( R7:1 ) = [ SP ++ ]; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + + //RAISE 9; // RTI + P2 = R2; + R5 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S b/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S new file mode 100644 index 0000000..6ac5d60 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S @@ -0,0 +1,341 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_dec_raise_pushpop/c_seq_dec_raise_pushpop.dsp +// Spec Reference: sequencer stage DEC (raise + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + +RAISE 2; // RTN + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +RAISE 5; // RTI + [ -- SP ] = ( R7:1 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +RAISE 6; // RTI + [ -- SP ] = ( R7:2 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +RAISE 7; // RTI + ( R7:2 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000025); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); + +RAISE 8; // RTI + ( R7:1 ) = [ SP ++ ]; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000014); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + +RAISE 9; // RTI + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S new file mode 100644 index 0000000..be9be51 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S @@ -0,0 +1,377 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex1_brcc_mv_pop/c_seq_ex1_brcc_mv_pop.dsp +// Spec Reference: sequencer stage ex1 ( brcc + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +R0 = 0; +ASTAT = R0; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN +IF !CC JUMP LABEL1 (BP); + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// RAISE 6; // RTI +IF !CC JUMP LABEL2 (BP); + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +// RAISE 7; // RTI +IF CC JUMP LABEL4; // SHOULD NOT EXECUTE + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + +LABEL4: + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000003); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); + +// RAISE 8; // RTI +IF !CC JUMP LABEL3 (BP); + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +// RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S new file mode 100644 index 0000000..d55d61d --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S @@ -0,0 +1,393 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex1_call_mv_pop/c_seq_ex1_call_mv_pop.dsp +// Spec Reference: sequencer stage ex1 ( call + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + +LD32_LABEL(p1, SUBR1); + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN +CALL (p1); + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// RAISE 6; // RTI +CALL SUBR2; + P1 = R3; + R4 = P1; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +// RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000024); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); + +// RAISE 8; // RTI +CALL SUBR3; + P3 = R5; + R6 = P3; + ( R7:0 ) = [ SP ++ ]; +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +// RAISE 9; // RTI + P4 = R6; + R7 = P4; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000002); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + + +SUBR1: // should jump here + I0 += 2; + RTS; + I3 += 2; // should not go here + RTS; + +SUBR2: // should jump here + I1 += 2; + RTS; + I3 += 2; // should not go here + RTS; + +SUBR3: // should jump here + I2 += 2; + RTS; + I3 += 2; // should not go here + RTS; + + + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S new file mode 100644 index 0000000..089c300 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S @@ -0,0 +1,375 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex1_j_mv_pop/c_seq_ex1_j_mv_pop.dsp +// Spec Reference: sequencer stage ex1 (jump + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN +JUMP.S LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// RAISE 6; // RTI +JUMP.S LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +// RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000003); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); + +// RAISE 8; // RTI +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +// RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S new file mode 100644 index 0000000..059a61b --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S @@ -0,0 +1,377 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_brcc_mv_pop/c_seq_ex1_raise_brcc_mv_pop.dsp +// Spec Reference: sequencer stage ex1 (raise+ brcc + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +R0 = 0; +ASTAT = R0; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN +IF !CC JUMP LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +RAISE 6; // RTI +IF !CC JUMP LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +RAISE 7; // RTI +IF CC JUMP LABEL4; // SHOULD NOT EXECUTE + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + +LABEL4: + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000003); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); + +RAISE 8; // RTI +IF !CC JUMP LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S new file mode 100644 index 0000000..1b70686 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S @@ -0,0 +1,393 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_call_mv_pop/c_seq_ex1_raise_call_mv_pop.dsp +// Spec Reference: sequencer stage ex1 (raise+ call + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + +LD32_LABEL(p1, SUBR1); + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN +CALL (p1); + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +RAISE 6; // RTI +CALL SUBR2; + P1 = R3; + R4 = P1; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000024); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); + +RAISE 8; // RTI +CALL SUBR3; + P3 = R5; + R6 = P3; + ( R7:0 ) = [ SP ++ ]; +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +RAISE 9; // RTI + P4 = R6; + R7 = P4; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000008); +CHECKREG(r1, 0x00000004); +CHECKREG(r2, 0x00000004); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + + +SUBR1: // should jump here + I0 += 2; + RTS; + I3 += 2; // should not go here + RTS; + +SUBR2: // should jump here + I1 += 2; + RTS; + I3 += 2; // should not go here + RTS; + +SUBR3: // should jump here + I2 += 2; + RTS; + I3 += 2; // should not go here + RTS; + + + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S new file mode 100644 index 0000000..2d88bb4 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S @@ -0,0 +1,375 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_j_mv_pop/c_seq_ex1_raise_j_mv_pop.dsp +// Spec Reference: sequencer stage ex1 (raise+ jump + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN +JUMP.S LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +RAISE 6; // RTI +JUMP.S LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000003); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); + +RAISE 8; // RTI +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S b/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S new file mode 100644 index 0000000..c32d062 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S @@ -0,0 +1,377 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex2_brcc_mp_mv_pop/c_seq_ex2_brcc_mp_mv_pop.dsp +// Spec Reference: sequencer stage ex2 ( brcc (mis-pred)+ regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +R0 = 0; +ASTAT = R0; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN +IF CC JUMP LABEL1 (BP); + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// RAISE 6; // RTI +IF !CC JUMP LABEL2 (BP); + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +// RAISE 7; // RTI +IF CC JUMP LABEL4 (BP); // SHOULD NOT EXECUTE + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + +LABEL4: + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + +// RAISE 8; // RTI +IF !CC JUMP LABEL3 (BP); + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +// RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S b/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S new file mode 100644 index 0000000..6e156d7 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex2_mmr_mvpop.S @@ -0,0 +1,386 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmr_mvpop/c_seq_ex2_mmr_mvpop.dsp +// Spec Reference: sequencer stage ex2 (mmr + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + +// [--sp] = (r7-r0); +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +LD32(r0, 0x55552345); +// RAISE 2; // RTN + [ P1 ] = R0; +// jump LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; +CSYNC; +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +// RAISE 6; // RTI + R0 = [ P1 ]; +// jump LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +//CHECKREG(r0, 0x55552345); +// RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x55552345); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000024); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +// RAISE 8; // RTI + R0 = [ P1 ]; +// jump LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +CSYNC; +CHECKREG(r0, 0x55552345); // CHECKREG can not be skipped +CHECKREG(r1, 0x00000012); // so they cannot appear here +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +//CHECKREG(r0, 0x55552345); +// RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x55552345); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S b/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S new file mode 100644 index 0000000..11eba1a --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex2_mmrj_mvpop.S @@ -0,0 +1,386 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmrj_mvpop/c_seq_ex2_mmrj_mvpop.dsp +// Spec Reference: sequencer stage ex2 ( mmr + jump + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +LD32(p2, DATA_ADDR_1); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; +CSYNC; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN + [ P1 ] = R0; +JUMP.S LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +// RAISE 6; // RTI + R0 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CHECKREG(r0, 0x00000001); +// RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000003); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +// RAISE 8; // RTI + R0 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CHECKREG(r0, 0x00000001); +// RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S b/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S new file mode 100644 index 0000000..5f86570 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S @@ -0,0 +1,385 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmr_mvpop/c_seq_ex2_raise_mmr_mvpop.dsp +// Spec Reference: sequencer stage ex2 (raise+ mmr + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + +// [--sp] = (r7-r0); +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +LD32(r0, 0x55552345); +RAISE 2; // RTN + [ P1 ] = R0; +// jump LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; +CSYNC; +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R0 = [ P1 ]; +// jump LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x55552345); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000024); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x00000027); +CHECKREG(r7, 0x00000028); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI + R0 = [ P1 ]; +// jump LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +CSYNC; +CHECKREG(r0, 0x55552345); // CHECKREG can not be skipped +CHECKREG(r1, 0x00000012); // so they cannot appear here +CHECKREG(r2, 0x00000013); +CHECKREG(r3, 0x00000013); +CHECKREG(r4, 0x00000015); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +//CHECKREG(r0, 0x55552345); +RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x55552345); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S b/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S new file mode 100644 index 0000000..f32ec69 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S @@ -0,0 +1,385 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmrj_mvpop/c_seq_ex2_raise_mmrj_mvpop.dsp +// Spec Reference: sequencer stage ex2 (raise+ mmr + jump+ regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p1, 0x12345678); +LD32(p2, 0x05612496); +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +LD32(r0, 0x55552345); +RAISE 2; // RTN + [ P1 ] = R0; +JUMP.S LABEL1; + P1 = R1; + R2 = P1; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + P2 = R2; + R3 = P2; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; +CSYNC; +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R0 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R4 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CHECKREG(r0, 0x55552345); +RAISE 7; // RTI + P4 = R4; + R5 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x55552345); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000003); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI + R0 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CHECKREG(r0, 0x55552345); +RAISE 9; // RTI + P2 = R6; + R7 = P2; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S b/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S new file mode 100644 index 0000000..d64de59 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S @@ -0,0 +1,440 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_brcc_mvp/c_seq_ex3_ls_brcc_mvp.dsp +// Spec Reference: sequencer stage ex3 (ldst + brcc + regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** +R0 = 0; +ASTAT = R0; + // PUT YOUR TEST HERE! +// PUSH + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + + + [ -- SP ] = ( R7:0 ); +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym p2, DATA; +LD32(r0, 0x55552345); +// RAISE 2; // RTN +// r0 = [p2++]; + R1 = [ P1 ]; +IF !CC JUMP LABEL1 (BP); + + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI +// r2 = [p2++]; + R3 = [ P1 ]; +IF CC JUMP LABEL2 (BP); // not taken + + P4 = R6; + R4 = P4; + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +// RAISE 6; // RTI +// r4 = [p2++]; + R5 = [ P1 ]; +IF !CC JUMP LABEL2 (BP); + P3 = R3; + R6 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x55552345); +//CHECKREG(r1, 0x000002B8); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000025); +//CHECKREG(r5, 0x000002B8); +// RAISE 7; // RTI +// r0 = [p2++]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x55552345); +//CHECKREG(r1, 0x000002B8); +CHECKREG(r2, 0x00000003); +//CHECKREG(r3, 0x000002B8); +CHECKREG(r4, 0x00000007); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +// RAISE 8; // RTI +// r0 = [p2++]; + R1 = [ P1 ]; +IF !CC JUMP LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x55552345); +//CHECKREG(r1, 0x000002B8); +// RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S b/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S new file mode 100644 index 0000000..1b0d7b5 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S @@ -0,0 +1,442 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmr_mvp/c_seq_ex3_ls_mmr_mvp.dsp +// Spec Reference: sequencer stage ex3 (ldst + mmr regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** +R0 = 0; +ASTAT = R0; + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym p2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; + + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +// brf LABEL1 (bp); + + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + R2 = [ P2 ++ ]; + R3 = [ P1 ]; +// brt LABEL2 (bp); // not taken + + P4 = R6; + R4 = P4; + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +// RAISE 6; // RTI + R4 = [ P2 ++ ]; + R5 = [ P1 ]; +// brf LABEL2 (bp) ; + P3 = R3; + R6 = P3; + [ -- SP ] = ( R7:0 ); +// POP +// r0 = 0x00; +// r1 = 0x00; +// r2 = 0x00; +// r3 = 0x00; +// r4 = 0x00; +// r5 = 0x00; +// r6 = 0x00; +// r7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000016); +CHECKREG(r5, 0x14789232); +// RAISE 7; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x00000012); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x00000016); +CHECKREG(r5, 0x14789232); +CHECKREG(r6, 0x00000024); +CHECKREG(r7, 0x00000028); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +// RAISE 8; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +// brf LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +CHECKREG(r0, 0x00010203); // CHECKREG can not be skipped +CHECKREG(r1, 0x00000012); // so they cannot appear here +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x14789232); +CHECKREG(r4, 0x00000017); +CHECKREG(r5, 0x00000016); +CHECKREG(r6, 0x00000017); +CHECKREG(r7, 0x00000018); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x0000000C); +CHECKREG(r1, 0x0000000D); +// RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000008); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S new file mode 100644 index 0000000..96543f4 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S @@ -0,0 +1,443 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmrj_mvp/c_seq_ex3_ls_mmrj_mvp.dsp +// Spec Reference: sequencer stage ex3 (ldst + mmr + jump+ regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym p2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; +CSYNC; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R4 = [ P2 ++ ]; + R5 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R6 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x14789232); +CHECKREG(r6, 0x00000027); +// RAISE 7; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000007); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +// RAISE 8; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +// RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S new file mode 100644 index 0000000..35abb66 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S @@ -0,0 +1,442 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_ex3_raise_ls_mmrj_mvp/c_seq_ex3_raise_ls_mmrj_mvp.dsp +// Spec Reference: sequencer stage ex3 (raise+ ldst + mmr + jump+ regmv + pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym p2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; +CSYNC; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R4 = [ P2 ++ ]; + R5 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R6 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x14789232); +CHECKREG(r6, 0x00000027); +RAISE 7; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000007); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S new file mode 100644 index 0000000..bf2a33f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S @@ -0,0 +1,446 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_wb_cs_lsmmrj_mvp/c_seq_wb_cs_lsmmrj_mvp.dsp +// Spec Reference: sequencer:wb ( csync ldst mmr jump regmv pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym P2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); +// RAISE 2; // RTN +CSYNC; + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +// RAISE 5; // RTI +CSYNC; + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +// RAISE 6; // RTI +CSYNC; + R4 = [ P2 ++ ]; + R6 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R5 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x14789232); +// RAISE 7; // RTI +CSYNC; + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000007); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +// RAISE 8; // RTI +CSYNC; + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +// RAISE 9; // RTI +CSYNC; + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000000); +CHECKREG(r1, 0x00000000); +CHECKREG(r2, 0x00000000); +CHECKREG(r3, 0x00000000); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S new file mode 100644 index 0000000..cbcf9ed --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S @@ -0,0 +1,446 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_wb_raisecs_lsmmrj_mvp/c_seq_wb_raisecs_lsmmrj_mvp.dsp +// Spec Reference: sequencer:wb (raise csync ldst mmr jump regmv pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym P2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN +CSYNC; + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI +CSYNC; + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI +CSYNC; + R4 = [ P2 ++ ]; + R6 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R5 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x14789232); +RAISE 7; // RTI +CSYNC; + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000007); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI +CSYNC; + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +RAISE 9; // RTI +CSYNC; + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S new file mode 100644 index 0000000..4b97bee --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S @@ -0,0 +1,455 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_wb_rti_lsmmrj_mvp/c_seq_wb_rti_lsmmrj_mvp.dsp +// Spec Reference: sequencer:wb ( rti ldst mmr jump regmv pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym P2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R4 = [ P2 ++ ]; + R6 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R5 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x14789232); +RAISE 7; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000007); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; + // *********** + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; + // *********** +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + // *********** + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; + // *********** + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S new file mode 100644 index 0000000..b18a52f --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S @@ -0,0 +1,447 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_wb_rtn_lsmmrj_mvp/c_seq_wb_rtn_lsmmrj_mvp.dsp +// Spec Reference: sequencer:wb ( rtn ldst mmr jump regmv pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym P2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R4 = [ P2 ++ ]; + R6 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R5 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x00000023); +CHECKREG(r3, 0x00000024); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x00000026); +CHECKREG(r6, 0x14789232); +RAISE 7; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000007); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + // *********** + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; + // *********** + +XHANDLE: // Exception Handler 3 + R1 = 3; +RTX; + +HWHANDLE: // HW Error Handler 5 + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler + I3 += 2; +RTI; +I8HANDLE: // IVG 8 Handler + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S b/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S new file mode 100644 index 0000000..52eb6c8 --- /dev/null +++ b/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S @@ -0,0 +1,466 @@ +//Original:/proj/frio/dv/testcases/core/c_seq_wb_rtx_lsmmrj_mvp/c_seq_wb_rtx_lsmmrj_mvp.dsp +// Spec Reference: sequencer:wb ( rtx ldst mmr jump regmv pushpopmultiple) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(selfcheck.inc) +include(gen_int.inc) +INIT_R_REGS(0); +INIT_P_REGS(0); +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); +//CHECK_INIT(p5, 0xe0000000); +include(symtable.inc) +CHECK_INIT_DEF(p5); + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE DATA_ADDR_1 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// + +BOOT: + + // in reset mode now +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in + // SUPERVISOR MODE & go to different RAISE in supervisor mode + // until the end of the test. + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + + + // PUT YOUR TEST HERE! +// PUSH +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +//LD32(p2, DATA_ADDR_1); +loadsym P2, DATA; +LD32(p3, 0xab5fd490); +LD32(p4, 0xa581bd94); + +LD32(r2, 0x14789232); + [ P1 ] = R2; + R0 = 0x01; + R1 = 0x02; + R2 = 0x03; + R3 = 0x04; + R4 = 0x05; + R5 = 0x06; + R6 = 0x07; + R7 = 0x08; + [ -- SP ] = ( R7:0 ); +RAISE 2; // RTN + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL1; + P3 = R7; + R4 = P3; + [ -- SP ] = ( R7:0 ); + R1 = 0x12; + R2 = 0x13; + R3 = 0x14; + R4 = 0x15; + R5 = 0x16; + R6 = 0x17; + R7 = 0x18; + +LABEL1: +RAISE 5; // RTI + R2 = [ P2 ++ ]; + + P4 = R6; + R3 = P4; + + [ -- SP ] = ( R7:0 ); + + R2 = 0x23; + R3 = 0x24; + R4 = 0x25; + R5 = 0x26; + R6 = 0x27; + R7 = 0x28; + +// wrt-rd EVT5 = 0xFFE02034 +LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 +RAISE 6; // RTI + R4 = [ P2 ++ ]; + R6 = [ P1 ]; +JUMP.S LABEL2; + P3 = R3; + R5 = P3; + [ -- SP ] = ( R7:0 ); +// POP + R0 = 0x00; + R1 = 0x00; + R2 = 0x00; + R3 = 0x00; + R4 = 0x00; + R5 = 0x00; + R6 = 0x00; + R7 = 0x00; + +LABEL2: +CSYNC; +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789234); +CHECKREG(r2, 0x00000024); +CHECKREG(r3, 0x00000025); +CHECKREG(r4, 0x08090A0B); +CHECKREG(r5, 0x00000027); +CHECKREG(r6, 0x14789232); +RAISE 7; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; + P4 = R4; + R2 = P4; + ( R7:0 ) = [ SP ++ ]; + + + +CHECKREG(r0, 0x00010203); +CHECKREG(r1, 0x14789233); +CHECKREG(r2, 0x04050607); +CHECKREG(r3, 0x00000008); +//CHECKREG(r4, 0x000002CC); +CHECKREG(r5, 0x00000007); +CHECKREG(r6, 0x00000008); +CHECKREG(r7, 0x00000009); +// wrt-rd EVT13 = 0xFFE02034 +LD32(p1, 0xFFE02034); +RAISE 8; // RTI + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; +//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped +//CHECKREG(r1, 0x000000b2); // so they cannot appear here +//CHECKREG(r2, 0x000000c3); +//CHECKREG(r3, 0x000000d4); +//CHECKREG(r4, 0x000000e5); +//CHECKREG(r5, 0x000000f6); +//CHECKREG(r6, 0x00000017); +//CHECKREG(r7, 0x00000028); + R0 = 12; + R1 = 13; + R2 = 14; + R3 = 15; + R4 = 16; + R5 = 17; + R6 = 18; + R7 = 19; + + +LABEL3: +CSYNC; +CHECKREG(r0, 0x10111213); +CHECKREG(r1, 0x14789232); +CHECKREG(r2, 0x04050608); +CHECKREG(r3, 0x00000009); +//CHECKREG(r4, 0x000002E4); +CHECKREG(r5, 0x00000008); +CHECKREG(r6, 0x00000009); +CHECKREG(r7, 0x0000000A); +RAISE 9; // RTI + P3 = R6; + R7 = P3; + ( R7:0 ) = [ SP ++ ]; + +CHECKREG(r0, 0x00000001); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000003); +CHECKREG(r3, 0x00000004); +CHECKREG(r4, 0x00000005); +CHECKREG(r5, 0x00000006); +CHECKREG(r6, 0x00000007); +CHECKREG(r7, 0x00000008); +R0 = I0; +R1 = I1; +R2 = I2; +R3 = I3; +CHECKREG(r0, 0x00000006); +CHECKREG(r1, 0x00000002); +CHECKREG(r2, 0x00000002); +CHECKREG(r3, 0x00000002); + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + I0 += 2; +RTN; + +XHANDLE: // Exception Handler 3 +R4 = RETX; // error handler: RETX has the address of the same Illegal instr + R1 += 1; + R2 += 1; + R3 += 1; + R5 += 1; + R6 += 1; + R7 += 1; +R4 += 4; // we have to add 4 to point to next instr after return +RETX = R4; +RTX; + // *********** + R0 = [ P2 ++ ]; + R1 = [ P1 ]; +JUMP.S LABEL3; + P1 = R5; + R6 = P1; + ( R7:0 ) = [ SP ++ ]; + // *********** + +HWHANDLE: // HW Error Handler 5 +.dd 0xFFFFFFFF + I1 += 2; +RTI; + +THANDLE: // Timer Handler 6 +.dd 0xFFFFFFFF + I2 += 2; +RTI; + +I7HANDLE: // IVG 7 Handler +.dd 0xFFFFFFFF + I3 += 2; +RTI; +I8HANDLE: // IVG 8 Handler +.dd 0xFFFFFFFF + I0 += 2; +RTI; + +I9HANDLE: // IVG 9 Handler +.dd 0xFFFFFFFF + I0 += 2; +RTI; + +I10HANDLE: // IVG 10 Handler + R7 = 10; +RTI; + +I11HANDLE: // IVG 11 Handler + I0 = R0; + I1 = R1; + I2 = R2; + I3 = R3; + M0 = R4; + R0 = 11; +RTI; + +I12HANDLE: // IVG 12 Handler + R1 = 12; +RTI; + +I13HANDLE: // IVG 13 Handler + R2 = 13; +RTI; + +I14HANDLE: // IVG 14 Handler + R3 = 14; +RTI; + +I15HANDLE: // IVG 15 Handler + R4 = 15; +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1,"aw" +DATA: +// .space (0x10); +.dd 0x00010203 +.dd 0x04050607 +.dd 0x08090A0B +.dd 0x0C0D0E0F +.dd 0x10111213 +.dd 0x14151617 +.dd 0x18191A1B +.dd 0x1C1D1E1F +.dd 0x11223344 +.dd 0x55667788 +.dd 0x99717273 +.dd 0x74757677 +.dd 0x82838485 +.dd 0x86878889 +.dd 0x80818283 +.dd 0x84858687 +.dd 0x01020304 +.dd 0x05060708 +.dd 0x09101112 +.dd 0x14151617 +.dd 0x18192021 + + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: + +.section MEM_DATA_ADDR_2,"aw" +.dd 0x20212223 +.dd 0x24252627 +.dd 0x28292A2B +.dd 0x2C2D2E2F +.dd 0x30313233 +.dd 0x34353637 +.dd 0x38393A3B +.dd 0x3C3D3E3F +.dd 0x91929394 +.dd 0x95969798 +.dd 0x99A1A2A3 +.dd 0xA5A6A7A8 +.dd 0xA9B0B1B2 +.dd 0xB3B4B5B6 +.dd 0xB7B8B9C0 diff --git a/sim/testsuite/sim/bfin/c_ujump.s b/sim/testsuite/sim/bfin/c_ujump.s new file mode 100644 index 0000000..65dcf5e --- /dev/null +++ b/sim/testsuite/sim/bfin/c_ujump.s @@ -0,0 +1,52 @@ +//Original:/testcases/core/c_ujump/c_ujump.dsp +// Spec Reference: ujump +# mach: bfin + +.include "testutils.inc" + start + + +INIT_R_REGS 0; + +ASTAT = r0; + +JUMP.S LAB1; + + +STOP: +JUMP.S END; + +LAB1: + R1 = 0x1111 (X); +JUMP.S LAB5; + R6 = 0x6666 (X); + +LAB2: + R2 = 0x2222 (X); +JUMP.S STOP; + +LAB3: + R3 = 0x3333 (X); +JUMP.S LAB2; + R7 = 0x7777 (X); + +LAB4: + R4 = 0x4444 (X); +JUMP.S LAB3; + +LAB5: + R5 = 0x5555 (X); +JUMP.S LAB4; + +END: + +CHECKREG r0, 0x00000000; +CHECKREG r1, 0x00001111; +CHECKREG r2, 0x00002222; +CHECKREG r3, 0x00003333; +CHECKREG r4, 0x00004444; +CHECKREG r5, 0x00005555; +CHECKREG r6, 0x00000000; +CHECKREG r7, 0x00000000; + +pass diff --git a/sim/testsuite/sim/bfin/cc-alu.S b/sim/testsuite/sim/bfin/cc-alu.S new file mode 100644 index 0000000..089fbe7 --- /dev/null +++ b/sim/testsuite/sim/bfin/cc-alu.S @@ -0,0 +1,126 @@ +# Blackfin testcase for CC/A0/A1 compares +# mach: bfin + +#include "test.h" + .include "testutils.inc" + + start + +/* Clear ASTAT before test */ +#define CHECK_ASTAT(op, exp) ASTAT = R2; CC = A0 op A1; check_astat exp + .macro check_astat exp:req + R5 = ASTAT; + R6 = \exp; + CC = R5 == R6; + IF !CC JUMP 1f; + .endm + + .macro _acc_test exp_eq:req, exp_le:req, exp_lt:req + CHECK_ASTAT(==, \exp_eq) + CHECK_ASTAT(<=, \exp_le) + CHECK_ASTAT(<, \exp_lt) + + jump 2f; +1: fail +2: + .endm + + .macro acc_test acc0:req, acc1:req, eq:req, le:req, lt:req + dmm32 A0, \acc0 + dmm32 A1, \acc1 + _acc_test \eq, \le, \lt + .endm + + .macro acc_ex_test a0x:req, a0w:req, a1x:req, a1w:req, eq:req, le:req, lt:req + imm32 R0, \a0w + A0.W = R0; + R0 = \a0x; + A0.X = R0; + imm32 R1, \a1w + A1.W = R1; + R1 = \a1x; + A1.X = R1; + _acc_test \eq, \le, \lt + .endm + + # Keep R2 with a value of 0 + imm32 R2, 0 + +#define _EQ _AC0|_CC|_AC0_COPY|_AZ, _AC0|_CC|_AC0_COPY|_AZ, _AC0| _AC0_COPY|_AZ +#define _POS_GT _AN, _CC| _AN, _CC| _AN +#define _POS_LT _AC0| _AC0_COPY , _AC0| _AC0_COPY , _AC0| _AC0_COPY +#define _NEG_GT _AC0| _AC0_COPY|_AN, _AC0|_CC|_AC0_COPY|_AN, _AC0|_CC|_AC0_COPY|_AN +#define _NEG_LT 0, 0, 0 + + # Simple tests around zero + acc_test 0, 0, _EQ + acc_test 0, 1, _POS_GT + acc_test 0, 10000, _POS_GT + acc_test 1, 0, _POS_LT + acc_test 10000, 0, _POS_LT + acc_test 0, -1, _NEG_LT + acc_test 0, -10000, _NEG_LT + acc_test -1, 0, _NEG_GT + acc_test -10000, 0, _NEG_GT + + # Simple positive-only tests + acc_test 1, 1, _EQ + acc_test 10000, 10000, _EQ + acc_test 1, 2, _POS_GT + acc_test 1, 20000, _POS_GT + acc_test 2, 1, _POS_LT + acc_test 20000, 1, _POS_LT + + # Simple negative-only tests + acc_test -1, -1, _EQ + acc_test -10000, -10000, _EQ + acc_test -1, -2, _POS_LT + acc_test -1, -20000, _POS_LT + acc_test -2, -1, _POS_GT + acc_test -20000, -1, _POS_GT + + # Simple postitive/negative tests + acc_test 1, -1, _NEG_LT + acc_test -1, 1, _NEG_GT + acc_test 1, -10000, _NEG_LT + acc_test -10000, 1, _NEG_GT + acc_test -1, 10000, _NEG_GT + acc_test 10000, -1, _NEG_LT + acc_test -10000, 10000, _NEG_GT + acc_test 10000, -10000, _NEG_LT + + # Max boundary limits +#define MAX_POS 0x7f, 0xffffffff +#define MAX_NEG 0x80, 0x00000000 + acc_ex_test 0, 0, MAX_POS, _POS_GT + acc_ex_test MAX_POS, 0, 0, _POS_LT + acc_ex_test 0, 1, MAX_POS, _POS_GT + acc_ex_test MAX_POS, 0, 1, _POS_LT + acc_ex_test -1, -1, MAX_POS, _NEG_GT + acc_ex_test MAX_POS, -1, -1, _NEG_LT + acc_ex_test MAX_POS, MAX_POS, _EQ + acc_ex_test 0, 0, MAX_POS, _POS_GT + acc_ex_test MAX_POS, 0, 0, _POS_LT + acc_ex_test 0, 1, MAX_POS, _POS_GT + acc_ex_test MAX_POS, 0, 1, _POS_LT + acc_ex_test -1, -1, MAX_POS, _NEG_GT + acc_ex_test MAX_POS, -1, -1, _NEG_LT + + acc_ex_test 0, 0, MAX_NEG, _NEG_LT + acc_ex_test MAX_NEG, 0, 0, _NEG_GT + acc_ex_test 0, 1, MAX_NEG, _NEG_LT + acc_ex_test MAX_NEG, 0, 1, _NEG_GT + acc_ex_test -1, -1, MAX_NEG, _POS_LT + acc_ex_test MAX_NEG, -1, -1, _POS_GT + acc_ex_test MAX_NEG, MAX_NEG, _EQ + acc_ex_test 0, 0, MAX_NEG, _NEG_LT + acc_ex_test MAX_NEG, 0, 0, _NEG_GT + acc_ex_test 0, 1, MAX_NEG, _NEG_LT + acc_ex_test MAX_NEG, 0, 1, _NEG_GT + acc_ex_test -1, -1, MAX_NEG, _POS_LT + acc_ex_test MAX_NEG, -1, -1, _POS_GT + + acc_ex_test MAX_POS, MAX_NEG, _NEG_LT + acc_ex_test MAX_NEG, MAX_POS, _NEG_GT + + pass diff --git a/sim/testsuite/sim/bfin/cc-astat-bits.s b/sim/testsuite/sim/bfin/cc-astat-bits.s new file mode 100644 index 0000000..1c7d485 --- /dev/null +++ b/sim/testsuite/sim/bfin/cc-astat-bits.s @@ -0,0 +1,101 @@ +# Blackfin testcase for setting all ASTAT bits via CC +# mach: bfin + +# We encode the opcodes directly since we test reserved bits +# which lack an insn in the ISA for it. It's a 16bit insn; +# the low 8 bits are always 0x03 while the encoding for the +# high 8 bits are: +# bit 7 - direction +# 0: CC=...; +# 1: ...=CC; +# bit 6/5 - operation +# 0: = assignment +# 1: | bit or +# 2: & bit and +# 3: ^ bit xor +# bit 4-0 - the bit in ASTAT to access + + .include "testutils.inc" + + .macro _do dir:req, op:req, bit:req, bit_in:req, cc_in:req, bg_val:req, bit_out:req, cc_out:req + /* CC = CC; is invalid, so skip it */ + .if \bit != 5 + + /* Calculate the before and after ASTAT values */ + imm32 R1, (\bg_val & ~((1 << \bit) | (1 << 5))) | (\bit_in << \bit) | (\cc_in << 5); + imm32 R3, (\bg_val & ~((1 << \bit) | (1 << 5))) | (\bit_out << \bit) | (\cc_out << 5); + + /* Test the actual opcode */ + ASTAT = R1; + .byte (\dir << 7) | (\op << 5) | \bit + .byte 0x03 + R2 = ASTAT; + + /* Make sure things line up */ + CC = R3 == R2; + IF !CC JUMP 1f; + JUMP 2f; +1: fail +2: + .endif + + /* Recurse through all the bits */ + .if \bit > 0 + _do \dir, \op, \bit - 1, \bit_in, \cc_in, \bg_val, \bit_out, \cc_out + .endif + .endm + + /* Test different background fields on ASTAT */ + .macro do dir:req, op:req, bit_in:req, cc_in:req, bit_out:req, cc_out:req + _do \dir, \op, 31, \bit_in, \cc_in, 0, \bit_out, \cc_out + _do \dir, \op, 31, \bit_in, \cc_in, -1, \bit_out, \cc_out + .endm + + start + nop; + +_cc_eq_bit: /* CC = bit */ + do 0, 0, 0, 0, 0, 0 + do 0, 0, 0, 1, 0, 0 + do 0, 0, 1, 0, 1, 1 + do 0, 0, 1, 1, 1, 1 +_bit_eq_cc: /* bit = CC */ + do 1, 0, 0, 0, 0, 0 + do 1, 0, 0, 1, 1, 1 + do 1, 0, 1, 0, 0, 0 + do 1, 0, 1, 1, 1, 1 + +_cc_or_bit: /* CC |= bit */ + do 0, 1, 0, 0, 0, 0 + do 0, 1, 0, 1, 0, 1 + do 0, 1, 1, 0, 1, 1 + do 0, 1, 1, 1, 1, 1 +_bit_or_cc: /* bit |= CC */ + do 1, 1, 0, 0, 0, 0 + do 1, 1, 0, 1, 1, 1 + do 1, 1, 1, 0, 1, 0 + do 1, 1, 1, 1, 1, 1 + +_cc_and_bit: /* CC &= bit */ + do 0, 2, 0, 0, 0, 0 + do 0, 2, 0, 1, 0, 0 + do 0, 2, 1, 0, 1, 0 + do 0, 2, 1, 1, 1, 1 +_bit_and_cc: /* bit &= CC */ + do 1, 2, 0, 0, 0, 0 + do 1, 2, 0, 1, 0, 1 + do 1, 2, 1, 0, 0, 0 + do 1, 2, 1, 1, 1, 1 + +_cc_xor_bit: /* CC ^= bit */ + do 0, 3, 0, 0, 0, 0 + do 0, 3, 0, 1, 0, 1 + do 0, 3, 1, 0, 1, 1 + do 0, 3, 1, 1, 1, 0 +_bit_xor_cc: /* bit ^= CC */ + do 1, 3, 0, 0, 0, 0 + do 1, 3, 0, 1, 1, 1 + do 1, 3, 1, 0, 1, 0 + do 1, 3, 1, 1, 0, 1 + + pass diff --git a/sim/testsuite/sim/bfin/cc0.s b/sim/testsuite/sim/bfin/cc0.s new file mode 100644 index 0000000..3fee01e --- /dev/null +++ b/sim/testsuite/sim/bfin/cc0.s @@ -0,0 +1,30 @@ +# Blackfin testcase for overflow +# mach: bfin + + .include "testutils.inc" + + start + + # add 0x80000000 + 0x80000000 + R1 = 1; + R1 <<= 31; + R0 = R1; + R0 = R0 + R1; + CC = V; // check to see if av0 and ac get set + CC &= AC0; + IF !CC JUMP art; + R1 = 0; + R1 += 0; + CC = AZ; + IF !CC JUMP art; + pass + +art: + R0 = CC; + R1 = 1 (Z); + + CC = R1 == R0 + if CC jump 1f; + fail +1: + pass diff --git a/sim/testsuite/sim/bfin/cc1.s b/sim/testsuite/sim/bfin/cc1.s new file mode 100644 index 0000000..d5d86d8 --- /dev/null +++ b/sim/testsuite/sim/bfin/cc1.s @@ -0,0 +1,26 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0x1234 (X); + CC = BITTST ( R0 , 2 ); + IF !CC JUMP s$0; + R0 += 1; +s$0: + nop; + DBGA ( R0.L , 0x1235 ); + CC = BITTST ( R0 , 1 ); + IF !CC JUMP s$1; + R0 += 1; +s$1: + nop; + DBGA ( R0.L , 0x1235 ); + CC = BITTST ( R0 , 12 ); + IF !CC JUMP s$3; + R0 = - R0; +s$3: + nop; + DBGA ( R0.L , 0xedcb ); + pass diff --git a/sim/testsuite/sim/bfin/cc5.S b/sim/testsuite/sim/bfin/cc5.S new file mode 100644 index 0000000..593b3bd --- /dev/null +++ b/sim/testsuite/sim/bfin/cc5.S @@ -0,0 +1,90 @@ +// ALU test program. +// Test instructions reg = (A0+=A1) + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + loadsym P0, data0; + + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// add accums and transfer result + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R6 = ( A0 += A1 ); + CHECKREG R6, 0x22222222; + R6 = A0.w; + CHECKREG R6, 0x22222222; + R7 = A0.x; + CHECKREG R7, 0; + R6 = A1.w; + CHECKREG R6, 0x11111111; + R7 = A1.x; + CHECKREG R7, 0; + +// add accums and transfer result (saturate positive) + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R6 = ( A0 += A1 ); + CHECKREG R6, 0x7fffffff; + R6 = A0.w; + CHECKREG R6, 0xfffffffe; + R7 = A0.x; + CHECKREG R7, 0; + R6 = A1.w; + CHECKREG R6, 0x7fffffff; + _DBG ASTAT; + R7 = A1.x; + _DBG ASTAT; + CHECKREG R7, 0; + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY); + +// add accums and transfer result (saturate negative) + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + A1.x = R3.L; + A0.x = R3.L; + R6 = ( A0 += A1 ); + CHECKREG R6, 0x80000000; + R6 = A0.w; + CHECKREG R6, 0x00000000; + R7 = A0.x; + CHECKREG R6, 0; + R6 = A1.w; + CHECKREG R6, 0x80000000; + R7 = A1.x; + CHECKREG R7, 0xffffffff; + R7 = ASTAT; + _DBG ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN); + + pass + + .data +data0: + .dw 0x1111 + .dw 0x1111 + .dw 0xffff + .dw 0x7fff + .dw 0x0000 + .dw 0x8000 + .dw 0x00ff + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/cec-exact-exception.S b/sim/testsuite/sim/bfin/cec-exact-exception.S new file mode 100644 index 0000000..fd22f94 --- /dev/null +++ b/sim/testsuite/sim/bfin/cec-exact-exception.S @@ -0,0 +1,54 @@ +# Blackfin testcase for aborting an excepting insn immediately +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + # This test keeps P5 as the base of the EVT table + + .macro set_evt lvl:req, sym:req + loadsym R1, \sym; + [P5 + 4 * \lvl\()] = R1; + .endm + + start + + # Set up exception handler + imm32 P4, EVT3; + loadsym R1, _evx; + [P4] = R1; + + # Lower ourselves to userspace + loadsym R1, _user; + RETI = R1; + RTI; + +_user: + imm32 R0, 0x12345678; + R1 = R0; + imm32 P0, 0xffffffff; + P1 = P0; +_user_fail: + # Sometimes this even causes immediate double faults when + # exceptions are not exact since this may trigger multiple + R0 = [P0++]; + + JUMP fail_lvl; + +_evx: + # RETX should be pointing to the right place + loadsym R6, _user_fail; + R7 = RETX; + CC = R6 == R7; + IF !CC JUMP fail_lvl; + + # R0 and P0 should be unchanged + CC = R1 == R0; + IF !CC JUMP fail_lvl; + CC = P1 == P0; + IF !CC JUMP fail_lvl; + + dbg_pass +fail_lvl: + dbg_fail diff --git a/sim/testsuite/sim/bfin/cec-ifetch.S b/sim/testsuite/sim/bfin/cec-ifetch.S new file mode 100644 index 0000000..5ed54b5 --- /dev/null +++ b/sim/testsuite/sim/bfin/cec-ifetch.S @@ -0,0 +1,69 @@ +# Blackfin testcase for making sure RETX is the excepting insn +# and not the target of the insn (like indirect jumps) +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + # Set our handler + imm32 P5, EVT3; + loadsym R1, _evtx; + [P5] = R1; + + # Lower ourselves below EVT3 + loadsym R4, _i_rts; + RETI = R4; + RAISE 12; + RTI; + +_i_rts: + # Check unaligned RETS + loadsym R6, 1f; + loadsym R5, 2f; + R0 = 1; + RETS = R0; +1: RTS; +2: + +_i_jump: + # Check unaligned indirect jump + loadsym R6, 1f; + loadsym R5, 2f; + P0 = 1; +1: JUMP (P0); +2: + +_i_jump_off: + # Check unaligned indirect jump (pc-relative) + loadsym R6, 1f; + loadsym R5, 2f; + P0 = 1; +1: JUMP (PC + P0); +2: + +_i_call: + # Check unaligned indirect call + loadsym R6, 1f; + loadsym R5, 2f; + P0 = 1; +1: CALL (P0); +2: + +_pass_lvl: + dbg_pass + +_evtx: + # Make sure R6 matches RETX + R7 = RETX; + CC = R6 == R7; + if !CC jump _fail_lvl; + + # Move on to next test + RETX = R5; + RTX; + +_fail_lvl: + dbg_fail diff --git a/sim/testsuite/sim/bfin/cec-multi-pending.S b/sim/testsuite/sim/bfin/cec-multi-pending.S new file mode 100644 index 0000000..63f3780 --- /dev/null +++ b/sim/testsuite/sim/bfin/cec-multi-pending.S @@ -0,0 +1,182 @@ +# Blackfin testcase for multiple pending IVGs vs masked state +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + # This test keeps P5 as the base of the EVT table + + .macro set_evt lvl:req, sym:req + loadsym R1, \sym; + [P5 + 4 * \lvl\()] = R1; + .endm + + .macro check_cec mmr:req, valid:req + imm32 P3, \mmr; + R0 = [P3]; + R1 = ~0x1f; + R0 = R0 & R1; + imm32 R1, \valid; + CC = R1 == R0; + IF CC JUMP 1f; + dbg_fail +1: + .endm + + .macro delay cnt:req + imm32 P2, \cnt + LSETUP (1f, 1f) LC1 = P2; +1: mnop; + .endm + + start + + # First mark all EVTs as fails (they shouldn't be activated) + imm32 P5, EVT0; + P1 = P5; + loadsym R1, fail_lvl + imm32 P2, 16 + LSETUP (1f, 1f) LC0 = P2; +1: [P1++] = R1; + + # Lower ourselves to EVT15 + set_evt 15, evt15; + R7 = 0 (x); + BITSET (R7, 15); + sti R7; + loadsym R1, wait; + RETI = R1; + RAISE 15; + RTI; + +wait: + jump wait; + +evt15: + # We shouldn't come back here + set_evt 15, fail_lvl; + + # Activate interrupt nesting early + [--SP] = RETI; + + # Raise some higher levels, but they should be masked and so + # they should never be activated ... + RAISE 6; + RAISE 5; + RAISE 9; + RAISE 12; + + # Only IVG15 should be pending + check_cec IPEND, (1<<15); + + # But all should be latched + check_cec ILAT, (1<<5) | (1<<6) | (1<<9) | (1<<12); + + # Delay a little in case a higher level wrongly activates + delay 30 + + # If we're still here, things are still good. So let's + # transition up *slightly*, but not to the highest latched. + set_evt 12, evt12; + cli R7; + BITSET (R7, 12); + sti R7; + + # Let CEC raise us to IVG12 + delay 30 + # CEC should have been faster than this ... + dbg_fail + +evt12: + # We shouldn't come back here + set_evt 12, fail_lvl; + + # Raise some higher levels, but they should be masked and so + # they should never be activated ... + RAISE 11; + + # Both IVG15 and IVG12 should be pending + check_cec IPEND, (1<<15) | (1<<12); + + # But all should be latched + check_cec ILAT, (1<<5) | (1<<6) | (1<<9) | (1<<11); + + # Activate interrupt nesting a little later + [--SP] = RETI; + + # Still here, so unmask a higher IVG again to move up + set_evt 9, evt9; + cli R7; + BITSET (R7, 9); + sti R7; + delay 30 + + # CEC should have been faster than this ... + dbg_fail + +evt9: + # We shouldn't come back here + set_evt 9, fail_lvl; + + # IVG9 should also be pending now + check_cec IPEND, (1<<15) | (1<<12) | (1<<9); + + # But all should be latched + check_cec ILAT, (1<<5) | (1<<6) | (1<<11); + + # Unmask the next level, but IPEND[4] is set, so we should stay here + set_evt 6, evt6; + cli R7; + BITSET (R7, 6); + sti R7; + + # Delay a little in case a higher level wrongly activates + delay 30 + + # Good, now unmask things globally + [--SP] = RETI; + delay 30 + + # CEC should have been faster than this ... + dbg_fail + +evt6: + # We shouldn't come back here + set_evt 6, fail_lvl; + + # IVG6 should also be pending now + check_cec IPEND, (1<<15) | (1<<12) | (1<<9) | (1<<6); + + # But all should be latched + check_cec ILAT, (1<<5) | (1<<11); + + # Activate interrupt nesting a little later + [--SP] = RETI; + + # Unmask the next level, but do it via IMASK + set_evt 5, evt5; + imm32 P2, IMASK; + R7 = [P2]; + BITSET (R7, 5); + [P2] = R7; + delay 30 + + # CEC should have been faster than this ... + dbg_fail + +evt5: + # We shouldn't come back here + set_evt 5, fail_lvl; + + # IVG5 should also be pending now + check_cec IPEND, (1<<15) | (1<<12) | (1<<9) | (1<<6) | (1<<5); + + # But all should be latched + check_cec ILAT, (1<<11); + + # All good! + dbg_pass; + +fail_lvl: + dbg_fail; diff --git a/sim/testsuite/sim/bfin/cec-no-snen-reti.S b/sim/testsuite/sim/bfin/cec-no-snen-reti.S new file mode 100644 index 0000000..bb9557d --- /dev/null +++ b/sim/testsuite/sim/bfin/cec-no-snen-reti.S @@ -0,0 +1,128 @@ +# Blackfin testcase for having RETI LSB set correctly when not self nested +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + # Set our handler + imm32 P5, EVT11; + loadsym R1, _ivg11; + [P5] = R1; + loadsym R1, _fail_lvl; + [P5 + 4] = R1; /* IVG12 */ + [P5 + 12] = R1; /* IVG14 */ + loadsym R1, _ivg13; + [P5 + 8] = R1; + + # Disable self nesting + R2 = SYSCFG; + BITCLR (R2, 2); + SYSCFG = R2; + CSYNC; + + # Enable IVG11/IVG13/IVG14 but not IVG12 + cli R3; + BITSET (R3, 11); + BITCLR (R3, 12); + BITSET (R3, 13); + BITSET (R3, 14); + sti R3; + + # Counters to keep track of nesting depth + R7 = 0; + R5 = 0; + + # Lower ourselves to IVG11 + loadsym R4, _fail_lvl; + RETI = R4; + RAISE 11; + RAISE 12; + RAISE 13; + RAISE 14; + RTI; + +# This IVG makes sure we don't re-enter when self RAISE is pending +_ivg11: + R0 = RETI; + + # Make sure we are indeed at IVG11 + imm32 P0, IPEND; + R1 = [P0]; + CC = BITTST (R1, 11); + IF !CC JUMP _fail_lvl; + + # Should not be re-entering + CC = R5 == 0; + IF !CC JUMP _fail_lvl; + + # Make sure LSB of RETI is not set + CC = BITTST (R0, 0); + IF CC JUMP _fail_lvl; + + # Try to avoid nesting a few times + R5 += 1; + R6 = 3; + CC = R7 < R6; + IF !CC JUMP 1f; + [--sp] = RETI; + R7 += 1; + RAISE 11; + MNOP;NOP;MNOP;NOP; + R5 = 0; + RTI; + + # Move down to IVG13 for next test +1: loadsym R4, _fail_lvl; + RETI = R4; + RTI; + +# This IVG makes sure RETI LSB is ignored on transition out (RTI) +_ivg13: + R0 = RETI; + + # Make sure we are indeed at IVG13 + imm32 P0, IPEND; + R1 = [P0]; + CC = BITTST (R1, 13); + IF !CC JUMP _fail_lvl; + + # RETI LSB should not be set when entering IVG13 + CC = BITTST (R0, 0); + IF CC JUMP _fail_lvl; + + # Should get here only after a few IVG11 tests + CC = R7 == R6; + IF !CC JUMP _fail_lvl; + + # Make sure IVG13 isn't pending + imm32 P0, ILAT; + R1 = [P0]; + CC = BITTST (R1, 13); + IF CC JUMP _fail_lvl; + + # Manually set RETI to with LSB set so we should stay at IVG13 + # even though SNEN is disabled + loadsym R1, 1f; + BITSET (R1, 0); + RETI = R1; + R7 += 1; + RTI; + +1: # Make sure we get here in right number of tests + R6 = 4; + CC = R7 == R6; + IF !CC JUMP _fail_lvl; + + # Make sure we are still at IVG13 + imm32 P0, IPEND; + R1 = [P0]; + CC = BITTST (R1, 13); + IF !CC JUMP _fail_lvl; + + dbg_pass + +_fail_lvl: + dbg_fail; diff --git a/sim/testsuite/sim/bfin/cec-non-operating-env.s b/sim/testsuite/sim/bfin/cec-non-operating-env.s new file mode 100644 index 0000000..a35344c --- /dev/null +++ b/sim/testsuite/sim/bfin/cec-non-operating-env.s @@ -0,0 +1,37 @@ +# Make sure the sim doesn't segfault when doing things that don't +# make much sense in a non-operating environment +# mach: bfin + + .include "testutils.inc" + + start + + csync; + ssync; + idle; + raise 12; + cli r0; + sti r0; + + loadsym r0, .Lreti; + reti = r0; + rti; + fail; +.Lreti: + + loadsym r0, .Lretx; + retx = r0; + rtx; + fail; +.Lretx: + + loadsym r0, .Lretn; + retn = r0; + rtn; + fail; +.Lretn: + + usp = p0; + p0 = usp; + + pass; diff --git a/sim/testsuite/sim/bfin/cec-raise-reti.S b/sim/testsuite/sim/bfin/cec-raise-reti.S new file mode 100644 index 0000000..1735ab8 --- /dev/null +++ b/sim/testsuite/sim/bfin/cec-raise-reti.S @@ -0,0 +1,111 @@ +# Blackfin testcase for having RETI set correctly +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + # This test keeps P5 as the base of the EVT table + + .macro set_evt lvl:req, sym:req + loadsym R1, \sym; + [P5 + 4 * \lvl\()] = R1; + .endm + + start + + # First mark all EVTs as fails (they shouldn't be activated) + imm32 P5, EVT0; + P1 = P5; + loadsym R1, fail_lvl + imm32 P2, 16 + LSETUP (1f, 1f) LC0 = P2; +1: [P1++] = R1; + + # We'll bounce up a few + set_evt 6, evt6; + set_evt 7, evt7; + set_evt 8, evt8; + set_evt 9, evt9; + + # Lower ourselves down so we can RAISE up + set_evt 14, evt14; + loadsym R1, wait; + RETI = R1; + RAISE 14; + R7 = -1; + sti R7; + RTI; + +wait: + jump wait; + +evt14: + # Activate interrupt nesting early + [--SP] = RETI; + + # We activate the interrupt here ... + loadsym R1, 1f; + RAISE 9; + # ... but we should RETI here +1: JUMP fail_lvl; + +evt9: + R2 = RETI; + CC = R1 == R2; + IF !CC JUMP fail_lvl; + + # We activate the interrupt here ... + loadsym R1, 1f; + RAISE 8; + [--SP] = RETI; + # ... but we should RETI here +1: JUMP fail_lvl; + +evt8: + R2 = RETI; + CC = R1 == R2; + IF !CC JUMP fail_lvl; + + # Activate interrupt nesting early + [--SP] = RETI; + + # We activate the interrupt here ... + loadsym R1, 1f; + cli R7; + RAISE 7; + sti R7; + # ... but we should RETI here +1: JUMP fail_lvl; + +evt7: + R2 = RETI; + CC = R1 == R2; + IF !CC JUMP fail_lvl; + + # Activate interrupt nesting early + [--SP] = RETI; + + # We activate the interrupt here ... + imm32 P0, IMASK + R7 = [P0]; + R6 = 0; + [P0] = R6; + loadsym R1, 1f; + RAISE 6; + [P0] = R7; + # ... but we should RETI here + # don't jump to fail_lvl as the pipeline might advance + # the PC to the fail_lvl point before the ivg actually + # gets a chance to fire +1: JUMP 1b; + +evt6: + R2 = RETI; + CC = R1 == R2; + IF !CC JUMP fail_lvl; + + dbg_pass + +fail_lvl: + dbg_fail; diff --git a/sim/testsuite/sim/bfin/cec-snen-reti.S b/sim/testsuite/sim/bfin/cec-snen-reti.S new file mode 100644 index 0000000..306d99b --- /dev/null +++ b/sim/testsuite/sim/bfin/cec-snen-reti.S @@ -0,0 +1,122 @@ +# Blackfin testcase for having RETI LSB set correctly when self nested +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + # Set our handler + imm32 P5, EVT11; + loadsym R1, _ivg11; + [P5] = R1; + loadsym R1, _fail_lvl; + [P5 + 4] = R1; /* IVG12 */ + [P5 + 12] = R1; /* IVG14 */ + loadsym R1, _ivg13; + [P5 + 8] = R1; + + # Enable self nesting + R2 = SYSCFG; + BITSET (R2, 2); + SYSCFG = R2; + CSYNC; + + # Enable IVG11/IVG13/IVG14 but not IVG12 + cli R3; + BITSET (R3, 11); + BITCLR (R3, 12); + BITSET (R3, 13); + BITSET (R3, 14); + sti R3; + + # Counter to keep track of nesting depth + R7 = 0; + + # Lower ourselves to IVG11 + loadsym R4, _fail_lvl; + RETI = R4; + RAISE 11; + RAISE 12; + RAISE 13; + RAISE 14; + RTI; + +# This IVG makes sure RETI LSB is set correctly on transition in (RAISE) +_ivg11: + R0 = RETI; + + # Make sure we are indeed at IVG11 + imm32 P0, IPEND; + R1 = [P0]; + CC = BITTST (R1, 11); + IF !CC JUMP _fail_lvl; + + # Make sure LSB of RETI is set only on first pass + CC = ! BITTST (R0, 0); + R1 = CC; + CC = R7 == 0; + R2 = CC; + CC = R1 == R2; + IF !CC JUMP _fail_lvl; + + # Nest ourselves a few times + R6 = 3; + CC = R7 < R6; + IF !CC JUMP 1f; + [--sp] = RETI; + R7 += 1; + RAISE 11; + MNOP; + JUMP _fail_lvl; + + # Move down to IVG13 for next test +1: loadsym R4, _fail_lvl; + RETI = R4; + RTI; + +# This IVG makes sure RETI LSB is respected on transition out (RTI) +_ivg13: + R0 = RETI; + + # Make sure we are indeed at IVG13 + imm32 P0, IPEND; + R1 = [P0]; + CC = BITTST (R1, 13); + IF !CC JUMP _fail_lvl; + + # RETI LSB should be set when re-entering IVG13 + CC = ! BITTST (R0, 0); + R1 = CC; + CC = R7 == R6; + R2 = CC; + CC = R1 == R2; + IF !CC JUMP _fail_lvl; + + # Should get here only after a few IVG11 tests + CC = R7 < R6; + IF CC JUMP _fail_lvl; + + # Make sure IVG13 isn't pending + imm32 P0, ILAT; + R1 = [P0]; + CC = BITTST (R1, 13); + IF CC JUMP _fail_lvl; + + # Manually set RETI to with LSB set so we return there + R5 = R6; + R5 += 3; + CC = R7 < R5; + IF !CC JUMP 1f; + loadsym R1, _ivg13; + BITSET (R1, 0); + RETI = R1; + R7 += 1; + RTI; + + # All done! +1: dbg_pass + +_fail_lvl: + dbg_fail; diff --git a/sim/testsuite/sim/bfin/cec-syscfg-ssstep.S b/sim/testsuite/sim/bfin/cec-syscfg-ssstep.S new file mode 100644 index 0000000..169a605 --- /dev/null +++ b/sim/testsuite/sim/bfin/cec-syscfg-ssstep.S @@ -0,0 +1,72 @@ +# Blackfin testcase for hardware single stepping +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + # Set up exception handler + imm32 P4, EVT3; + loadsym R1, _evx; + [P4] = R1; + + # Enable single stepping + R0 = 1; + SYSCFG = R0; + + # Lower to the code we want to single step through + R1 = 1; + imm32 R5, 0xffff + R6 = 0; + R7 = 0; + loadsym R1, _usr; + RETI = R1; + RTI; + +_usr: + # Single step and set a new bit every time + BITSET (R7, 0); + BITSET (R7, 1); + BITSET (R7, 2); + BITSET (R7, 3); + BITSET (R7, 4); + BITSET (R7, 5); + BITSET (R7, 6); + BITSET (R7, 7); + BITSET (R7, 8); + BITSET (R7, 9); + BITSET (R7, 10); + BITSET (R7, 11); + BITSET (R7, 12); + BITSET (R7, 13); + BITSET (R7, 14); + BITSET (R7, 15); + JUMP fail_lvl; + +_evx: + # Make sure exception reason is single step + R3 = SEQSTAT; + R4 = 0x3f; + R3 = R3 & R4; + R4 = 0x10; + CC = R3 == R4; + IF !CC JUMP fail_lvl; + + # Set a new bit in R6 every single step to match R7 + CC = R1; + R6 = ROT R6 BY 1; + CC = R6 == R7; + IF !CC JUMP fail_lvl; + + # Do it through each bit + CC = R5 == R6; + IF CC JUMP pass_lvl; + + RTX; + +pass_lvl: + dbg_pass; +fail_lvl: + dbg_fail; diff --git a/sim/testsuite/sim/bfin/cec-system-call.S b/sim/testsuite/sim/bfin/cec-system-call.S new file mode 100644 index 0000000..6aaf3ca --- /dev/null +++ b/sim/testsuite/sim/bfin/cec-system-call.S @@ -0,0 +1,64 @@ +# Blackfin testcase for returning to the right place while bouncing between +# multiple CEC levels (like in a Linux system call) +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + # This test keeps P5 as the base of the EVT table + + .macro set_evt lvl:req, sym:req + loadsym R1, \sym; + [P5 + 4 * \lvl\()] = R1; + .endm + + start + + # First mark all EVTs as fails (they shouldn't be activated) + imm32 P5, EVT0; + P1 = P5; + loadsym R1, fail_lvl + imm32 P2, 16 + LSETUP (1f, 1f) LC0 = P2; +1: [P1++] = R1; + + # The OS exception handler + set_evt 3, _evx; + # The OS system call handler + set_evt 15, _evt15; + + # Lower ourselves to userspace + loadsym R1, _user; + loadsym R2, _next_user; + RETI = R1; + R7 = -1; + sti R7; + RTI; + +_user: + EXCPT 0; +_next_user: + dbg_pass + +_evx: + # RETX should be pointing to the right place + R1 = RETX; + CC = R1 == R2; + IF !CC JUMP fail_lvl; + + # Lower ourselves to the system call handler + RAISE 15; + RTX; + +_evt15: + # RETI should be pointing to the right place + R1 = RETI; + CC = R1 == R2; + IF !CC JUMP fail_lvl; + + # Return to userspace now + RTI; + +fail_lvl: + dbg_fail diff --git a/sim/testsuite/sim/bfin/cir.s b/sim/testsuite/sim/bfin/cir.s new file mode 100644 index 0000000..efbb9d4 --- /dev/null +++ b/sim/testsuite/sim/bfin/cir.s @@ -0,0 +1,20 @@ +# Blackfin testcase for circular buffer limits +# mach: bfin + + .include "testutils.inc" + + start + + B0 = 0 (X); + I0 = 0x1100 (X); + L0 = 0x10c0 (X); + M0 = 0 (X); + I0 += M0; + R0 = I0; + + R1 = 0x40 (Z); + CC = R1 == R0 + if CC jump 1f; + fail +1: + pass diff --git a/sim/testsuite/sim/bfin/cir1.s b/sim/testsuite/sim/bfin/cir1.s new file mode 100644 index 0000000..78381ac --- /dev/null +++ b/sim/testsuite/sim/bfin/cir1.s @@ -0,0 +1,84 @@ +# Blackfin testcase for circular buffers +# mach: bfin + + .include "testutils.inc" + + .macro daginit i:req, b:req, l:req, m:req + imm32 I0, \i + imm32 B0, \b + imm32 L0, \l + imm32 M0, \m + .endm + .macro dagcheck newi:req + DBGA ( I0.L, \newi & 0xFFFF ); + DBGA ( I0.H, \newi >> 16 ); + .endm + + .macro dagadd i:req, b:req, l:req, m:req, newi:req + daginit \i, \b, \l, \m + I0 += M0; + dagcheck \newi + .endm + + .macro dagsub i:req, b:req, l:req, m:req, newi:req + daginit \i, \b, \l, \m + I0 -= M0; + dagcheck \newi + .endm + + .macro dag i:req, b:req, l:req, m:req, addi:req, subi:req + daginit \i, \b, \l, \m + I0 += M0; + dagcheck \addi + imm32 I0, \i + I0 -= M0; + dagcheck \subi + .endm + + start + + init_l_regs 0 + init_i_regs 0 + init_b_regs 0 + init_m_regs 0 + +_zero_len: + dag 0, 0, 0, 0, 0, 0 + dag 100, 0, 0, 0, 100, 100 + dag 100, 0, 0, 11, 111, 89 + dag 100, 0xaa00ff00, 0, 0, 100, 100 + dag 100, 0xaa00ff00, 0, 11, 111, 89 + +_zero_base: + dag 0, 0, 100, 10, 10, 90 + dag 50, 0, 100, 10, 60, 40 + dag 99, 0, 100, 10, 9, 89 + dag 50, 0, 100, 50, 0, 0 + dag 50, 0, 100, 100, 50, 50 + dag 50, 0, 100, 200, 150, -50 + dag 50, 0, 100, 2100, 2050, -1950 + dag 1000, 0, 100, 0, 900, 1000 + dag 1000, 0, 1000, 0, 0, 1000 + + dag 0xffff1000, 0, 0x1000, 0, 0xffff0000, 0xffff1000 + dag 0xaaaa1000, 0, 0xaaa1000, 0, 0xa0000000, 0xaaaa1000 + dag 0xaaaa1000, 0, 0xaaa1000, 0x1000, 0xa0001000, 0xaaaa0000 + dag 0xffff1000, 0, 0xffff0000, 0xffffff, 0x1000fff, 0xfeff1001 + +_positive_base: + dag 0, 100, 100, 10, 10, 90 + dag 90, 100, 100, 10, 100, 180 + dag 90, 100, 100, 2100, 2090, -1910 + dag 100, 100, 100, 100, 100, 100 + dag 0xfffff000, 0xffffff00, 0x10, 0xffff, 0xefef, 0xfffef011 + +_large_base_len: + dag 0, 0xffffff00, 0xffffff00, 0x00000100, 0x00000200, 0xfffffe00 + dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0x88888887, 0x77777779 + dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0x4ccccccc, 0x91111111, 0x6eeeeeef + dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0x00000000, 0x44444445, 0xbbbbbbbb + dag 0, 0xdddddddd, 0x7bbbbbbb, 0xcccccccc, 0xcccccccc, 0xb7777779 + dag 0, 0xbbbbbbbb, 0x7bbbbbbb, 0x4ccccccc, 0x4ccccccc, 0xb3333334 + dag 0, 0xbbbbbbbb, 0x7bbbbbbb, 0x00000000, 0x84444445, 0x7bbbbbbb + + pass diff --git a/sim/testsuite/sim/bfin/cli-sti.s b/sim/testsuite/sim/bfin/cli-sti.s new file mode 100644 index 0000000..9e775cb --- /dev/null +++ b/sim/testsuite/sim/bfin/cli-sti.s @@ -0,0 +1,25 @@ +# Blackfin testcase for cli/sti instructions +# mach: bfin +# sim: --environment operating + + .include "testutils.inc" + + start + + # Make sure we can't mask <=EVT4 + R0 = 0; + sti R0; + cli R1; + R2 = 0x1f; + CC = R1 == R2; + IF !CC JUMP 1f; + + # Make sure we can mask >=EVT5 + R0 = 0xff; + sti R0; + cli R1; + CC = R0 == R1; + IF !CC JUMP 1f; + + dbg_pass +1: dbg_fail diff --git a/sim/testsuite/sim/bfin/cmpacc.s b/sim/testsuite/sim/bfin/cmpacc.s new file mode 100644 index 0000000..ed31f62 --- /dev/null +++ b/sim/testsuite/sim/bfin/cmpacc.s @@ -0,0 +1,50 @@ +# Blackfin testcase for the accumulator and compares +# mach: bfin + + .include "testutils.inc" + + start + +r7=0; +astat=r7; +r7.l=0x80; +A1.x=r7.l; +r0 = 0; +A1.w=r0; +r1.l = 0xffff; +r1.h =0xffff; +A0.w=r1; +r7.l=0x7f; +A0.x=r7.l; +#dbg A0; +#dbg A1; +#dbg astat; +cc = A0==A1; +#dbg astat; +r7=astat; +dbga (r7.h, 0x0); +dbga (r7.l, 0x0); +astat=r0; +#dbg astat; +r7.l=0x80; +A0.x=r7.l; +r0 = 0; +A0.w=r0; +r1.l = 0xffff; +r1.h =0xffff; +A1.w=r1; +r7.l=0x7f; +A1.x=r7.l; +cc = A0 G0 +// | | | | +// +------------------------------+ +// | b0 b1 b2 b3 b14 b15 | <- in +// +------------------------------+ +// | | | | | +// ----- XOR------------> G1 +// Instruction BXOR computes the bit G0 or G1 and stores it into CC +// and also into a destination reg half. Here, we take CC and rotate it +// into an output register. +// However, one can also store the output bit directly by storing +// the register half where this bit is placed. This would result +// in an output structure similar to the one in the original function +// Convolutional_Encode(), where an entire half word holds a bit. +// The resulting execution speed would be roughly twice as fast, +// since there is no need to rotate output bit via CC. + +.include "testutils.inc" + start + + loadsym P0, input; + loadsym P1, output; + + R1 = 0; R2 = 0;R3 = 0; + + R2.L = 0; + R2.H = 0xa01d; // polynom 0 + R3.L = 0; + R3.H = 0x12f4; // polynom 1 + + // load and CurrentState to upper half of A0 + A1 = A0 = 0; + R0 = 0x0000; + A0.w = R0; + A0 = A0 << 16; + + // l-loop counter is in P4 + P4 = 2(Z); + // **** START l-LOOP ***** +l$0: + + // insert 16 bits of input into lower half of A0 + // and advance input pointer + R0 = W [ P0 ++ ] (Z); + A0.L = R0.L; + + P5 = 2 (Z); + LSETUP ( m$0 , m$0end ) LC0 = P5; // **** BEGIN m-LOOP ***** +m$0: + + P5 = 8 (Z); + LSETUP ( i$1 , i$1end ) LC1 = P5; // **** BEGIN i-LOOP ***** +i$1: + R4.L = CC = BXORSHIFT( A0 , R2 ); // polynom0 -> CC + R1 = ROT R1 BY 1; // CC -> R1 + R4.L = CC = BXOR( A0 , R3 ); // polynom1 -> CC +i$1end: + R1 = ROT R1 BY 1; // CC -> R1 + + // store 16 bits of outdata RL1 +m$0end: + W [ P1 ++ ] = R1; + + P4 += -1; + CC = P4 == 0; + IF !CC JUMP l$0; // **** END l-LOOP ***** + + // Check results + loadsym I2, output; + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x8c62 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x262e ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5b4d ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x834f ); + pass + + .data +input: + .dw 0x999f + .dw 0x1999 + +output: + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/cycles.s b/sim/testsuite/sim/bfin/cycles.s new file mode 100644 index 0000000..bdea7eb --- /dev/null +++ b/sim/testsuite/sim/bfin/cycles.s @@ -0,0 +1,41 @@ +# Blackfin testcase for playing with CYCLES +# mach: bfin + + .include "testutils.inc" + + start + + R0 = 0; + R1 = 1; + CYCLES = R0; + CYCLES2 = R1; + + /* CYCLES should be "small" while CYCLES2 should be R1 still */ + R2 = CYCLES; + CC = R2 <= 3; + if ! CC jump 1f; + + R3 = CYCLES2; + CC = R3 == 1; + if ! CC jump 1f; + + nop; + mnop; + nop; + mnop; + + /* Test the "shadowed" CYCLES2 -- only a read of CYCLES reloads it */ + imm32 R1, 0x12345678 + CYCLES2 = R1; + R2 = CYCLES2; + CC = R2 == R3; + if ! CC jump 1f; + + R2 = CYCLES; + R2 = CYCLES2; + CC = R2 == R1; + if ! CC jump 1f; + + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/d0.s b/sim/testsuite/sim/bfin/d0.s new file mode 100644 index 0000000..5e13959 --- /dev/null +++ b/sim/testsuite/sim/bfin/d0.s @@ -0,0 +1,31 @@ +# mach: bfin + +.include "testutils.inc" + start + + I1 = 0x4 (X); + B1 = 0x0 (X); + L1 = 0x10 (X); + M0 = 8 (X); + I1 -= M0; + R0 = I1; + DBGA ( R0.L , 0xc ); + + I1 = 0xf0 (X); + B1 = 0x100 (X); + L1 = 0x10 (X); + M0 = 2 (X); + I1 += M0; + R0 = I1; + DBGA ( R0.L , 0xf2 ); + + I2 = 0x1000 (X); + B2.L = 0; + B2.H = 0x9000; + L2 = 0x10 (X); + M2 = 0 (X); + I2 += M2; + R0 = I2; + DBGA ( R0.L , 0x1000 ); + + pass diff --git a/sim/testsuite/sim/bfin/d1.s b/sim/testsuite/sim/bfin/d1.s new file mode 100644 index 0000000..ea56330 --- /dev/null +++ b/sim/testsuite/sim/bfin/d1.s @@ -0,0 +1,17 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + I0 = 0x1100 (X); + L0 = 0x10c0 (X); + M0 = 0 (X); + B0 = 0 (X); + I0 += M0; + R0 = I0; + DBGA ( R0.L , 0x40 ); + + pass diff --git a/sim/testsuite/sim/bfin/d2.s b/sim/testsuite/sim/bfin/d2.s new file mode 100644 index 0000000..2634f4b --- /dev/null +++ b/sim/testsuite/sim/bfin/d2.s @@ -0,0 +1,56 @@ +# Blackfin testcase for circular buffers and BREV +# mach: bfin + + .include "testutils.inc" + + start + + I0 = 0 (X); + M0 = 0x8 (X); + P0 = 16; + loadsym R1, vals; + +aaa: + I0 += M0 (BREV); + P0 += -1; + + R2 = I0; + R0 = R1 + R2 + P1 = R0; + R0 = B[P1] (Z); + + R3 = P0; + + CC = R0 == R3; + if !CC JUMP _fail; + + CC = P0 == 0; + IF !CC JUMP aaa (BP); + R0 = I0; + + DBGA(R0.L, 0x0000); + DBGA(R0.H, 0x0000); + + pass + +_fail: + fail + + .data +vals: +.db 0x0 /* 0 */ +.db 0x8 +.db 0xc +.db 0x4 /* 4 */ +.db 0xe +.db 0x6 +.db 0xa +.db 0x2 /* 8 */ +.db 0xf +.db 0x7 +.db 0xB +.db 0x3 /* c */ +.db 0xD +.db 0x5 +.db 0x9 /* f */ +.db 0x1 diff --git a/sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S b/sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S new file mode 100644 index 0000000..a86ecdc --- /dev/null +++ b/sim/testsuite/sim/bfin/dbg_brprd_ntkn_src_kill.S @@ -0,0 +1,545 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_brprd_ntkn_src_kill/dbg_brprd_ntkn_src_kill.dsp +// Description: This test checks that the trace buffer keeps track of a +// branch source instruction that is predicted but not taken getting killed +// at each stage in the pipe. The test consists of 8 instances of an EXCPT +// instruction followed by 0 to 7 NOPs and a BRF instruction (and bp), with +// the trace buffer enabled. +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000020 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + + // Save all the registers used in the ISR + [ -- SP ] = R0; + [ -- SP ] = R1; + [ -- SP ] = P0; + [ -- SP ] = P1; + [ -- SP ] = LC0; + [ -- SP ] = LB0; + [ -- SP ] = LT0; + [ -- SP ] = ASTAT; + + // Get EXCAUSE bits out of SEQSTAT + R0 = SEQSTAT; + R0 = R0 << 26; + R0 = R0 >> 26; + + // Check for Trace Exception + // Load r1 with EXCAUSE for Trace Exception + R1 = 0x0011 (Z); + // Check for Trace Exception +CC = R0 == R1; + // Branch to OUT if the EXCAUSE is not TRACE. +IF !CC JUMP OUT; + + // Read out the Trace Buffer. +LD32(p0, TBUFSTAT); + // Read TBUFSTAT MMR + P1 = [ P0 ]; + + // if p1 is zero skip the loop. +CC = P1 == 0; +IF CC JUMP OUT; + + // Read out the Entire Trace Buffer. +LD32(p0, TBUF); +LSETUP ( l0s , l0e ) LC0 = P1; +l0s:R0 = [ P0 ]; +l0e:R0 = [ P0 ]; + +OUT: + // Check for other exception, if any. + + // Restore all saved registers. +ASTAT = [ SP ++ ]; +LT0 = [ SP ++ ]; +LB0 = [ SP ++ ]; +LC0 = [ SP ++ ]; + P1 = [ SP ++ ]; + P0 = [ SP ++ ]; + R1 = [ SP ++ ]; + R0 = [ SP ++ ]; + + // Return +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +WR_MMR(TBUFCTL, 0x7, p0, r0); // Enable trace buffer & overflow + +CSYNC; // Wait for MMR write to complete + +CC = R7 == R6; // Set CC +EXCPT 1; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in WB stage +NOP; +NOP; + +EXCPT 2; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in EX3 stage +NOP; +NOP; + +EXCPT 3; +NOP; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in EX2 stage +NOP; +NOP; + +EXCPT 4; +NOP; +NOP; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in EX1 stage +NOP; +NOP; + +EXCPT 5; +NOP; +NOP; +NOP; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in AC stage +NOP; +NOP; + +EXCPT 6; +NOP; +NOP; +NOP; +NOP; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in DEC stage +NOP; +NOP; + +EXCPT 7; NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in IF2 stage +NOP; +NOP; + +EXCPT 8; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in IF1 stage +NOP; +NOP; + + // Read out the Rest of the Trace Buffer. +LD32(p0, TBUFSTAT); + // Read TBUFSTAT MMR + P1 = [ P0 ]; + + // if p1 is zero skip the loop. +CC = P1 == 0; +IF CC JUMP OUT1; + + // Read out the Entire Trace Buffer. +LD32(p0, TBUF); +LSETUP ( l1s , l1e ) LC0 = P1; +l1s:R0 = [ P0 ]; +l1e:R0 = [ P0 ]; + + // Don't RTI if you never wish to go to User Mode + // use END_TEST instead. + +OUT1: +dbg_pass; + +// rti; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + + // YOUR USER CODE GOES HERE. + +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_DATA_ADDR_2 //.data 0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S b/sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S new file mode 100644 index 0000000..812c8c7 --- /dev/null +++ b/sim/testsuite/sim/bfin/dbg_brtkn_nprd_src_kill.S @@ -0,0 +1,544 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_brtkn_nprd_src_kill/dbg_brtkn_nprd_src_kill.dsp +// Description: This test checks that the trace buffer keeps track of a +// branch source instruction that is taken but not predicted getting killed +// at each stage in the pipe. The test consists of 8 instances of an EXCPT +// instruction followed by 0 to 7 NOPs and a BRT instruction (no bp), with +// the trace buffer enabled. +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000020 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + + // Save all the registers used in the ISR + [ -- SP ] = R0; + [ -- SP ] = R1; + [ -- SP ] = P0; + [ -- SP ] = P1; + [ -- SP ] = LC0; + [ -- SP ] = LB0; + [ -- SP ] = LT0; + [ -- SP ] = ASTAT; + + // Get EXCAUSE bits out of SEQSTAT + R0 = SEQSTAT; + R0 = R0 << 26; + R0 = R0 >> 26; + + // Check for Trace Exception + // Load r1 with EXCAUSE for Trace Exception + R1 = 0x0011 (Z); + // Check for Trace Exception +CC = R0 == R1; + // Branch to OUT if the EXCAUSE is not TRACE. +IF !CC JUMP OUT; + + // Read out the Trace Buffer. +LD32(p0, TBUFSTAT); + // Read TBUFSTAT MMR + P1 = [ P0 ]; + + // if p1 is zero skip the loop. +CC = P1 == 0; +IF CC JUMP OUT; + + // Read out the Entire Trace Buffer. +LD32(p0, TBUF); +LSETUP ( l0s , l0e ) LC0 = P1; +l0s:R0 = [ P0 ]; +l0e:R0 = [ P0 ]; + +OUT: + // Check for other exception, if any. + + // Restore all saved registers. +ASTAT = [ SP ++ ]; +LT0 = [ SP ++ ]; +LB0 = [ SP ++ ]; +LC0 = [ SP ++ ]; + P1 = [ SP ++ ]; + P0 = [ SP ++ ]; + R1 = [ SP ++ ]; + R0 = [ SP ++ ]; + + // Return +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +WR_MMR(TBUFCTL, 0x7, p0, r0); // Enable trace buffer & overflow + +CSYNC; // Wait for MMR write to complete + +CC = R7 == R6; // Set CC +EXCPT 1; +IF CC JUMP 4; // Mispredicted branch gets killed in WB stage +NOP; +NOP; + +EXCPT 2; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in EX3 stage +NOP; +NOP; + +EXCPT 3; +NOP; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in EX2 stage +NOP; +NOP; + +EXCPT 4; +NOP; +NOP; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in EX1 stage +NOP; +NOP; + +EXCPT 5; +NOP; +NOP; +NOP; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in AC stage +NOP; +NOP; + +EXCPT 6; +NOP; +NOP; +NOP; +NOP; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in DEC stage +NOP; +NOP; + +EXCPT 7; NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in IF2 stage +NOP; +NOP; + +EXCPT 8; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +IF CC JUMP 4; // Mispredicted branch gets killed in IF1 stage +NOP; +NOP; + + // Read out the Rest of the Trace Buffer. +LD32(p0, TBUFSTAT); + // Read TBUFSTAT MMR + P1 = [ P0 ]; + + // if p1 is zero skip the loop. +CC = P1 == 0; +IF CC JUMP OUT1; + + // Read out the Entire Trace Buffer. +LD32(p0, TBUF); +LSETUP ( l1s , l1e ) LC0 = P1; +l1s:R0 = [ P0 ]; +l1e:R0 = [ P0 ]; + + // Don't RTI if you never wish to go to User Mode + // use END_TEST instead. + +OUT1: +dbg_pass; + +// rti; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + + // YOUR USER CODE GOES HERE. + +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_DATA_ADDR_2 //.data 0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/dbg_jmp_src_kill.S b/sim/testsuite/sim/bfin/dbg_jmp_src_kill.S new file mode 100644 index 0000000..c0caf5b --- /dev/null +++ b/sim/testsuite/sim/bfin/dbg_jmp_src_kill.S @@ -0,0 +1,543 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_jmp_src_kill/dbg_jmp_src_kill.dsp +// Description: This test checks that the trace buffer keeps track of a JUMP +// source instruction getting killed at each stage in the pipe. The test +// consists of 8 instances of an EXCPT instruction followed by 0 to 7 NOPs +// and a JUMP, with the trace buffer enabled. +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000020 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + + // Save all the registers used in the ISR + [ -- SP ] = R0; + [ -- SP ] = R1; + [ -- SP ] = P0; + [ -- SP ] = P1; + [ -- SP ] = LC0; + [ -- SP ] = LB0; + [ -- SP ] = LT0; + [ -- SP ] = ASTAT; + + // Get EXCAUSE bits out of SEQSTAT + R0 = SEQSTAT; + R0 = R0 << 26; + R0 = R0 >> 26; + + // Check for Trace Exception + // Load r1 with EXCAUSE for Trace Exception + R1 = 0x0011 (Z); + // Check for Trace Exception +CC = R0 == R1; + // Branch to OUT if the EXCAUSE is not TRACE. +IF !CC JUMP OUT; + + // Read out the Trace Buffer. +LD32(p0, TBUFSTAT); + // Read TBUFSTAT MMR + P1 = [ P0 ]; + + // if p1 is zero skip the loop. +CC = P1 == 0; +IF CC JUMP OUT; + + // Read out the Entire Trace Buffer. +LD32(p0, TBUF); +LSETUP ( l0s , l0e ) LC0 = P1; +l0s:R0 = [ P0 ]; +l0e:R0 = [ P0 ]; + +OUT: + // Check for other exception, if any. + + // Restore all saved registers. +ASTAT = [ SP ++ ]; +LT0 = [ SP ++ ]; +LB0 = [ SP ++ ]; +LC0 = [ SP ++ ]; + P1 = [ SP ++ ]; + P0 = [ SP ++ ]; + R1 = [ SP ++ ]; + R0 = [ SP ++ ]; + + // Return +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +WR_MMR(TBUFCTL, 0x7, p0, r0); // Enable trace buffer & overflow + +CSYNC; // Wait for MMR write to complete + +EXCPT 1; +JUMP 4; // Jump gets killed in WB stage +NOP; +NOP; + +EXCPT 2; +NOP; +JUMP 4; // Jump gets killed in EX3 stage +NOP; +NOP; + +EXCPT 3; +NOP; +NOP; +JUMP 4; // Jump gets killed in EX2 stage +NOP; +NOP; + +EXCPT 4; +NOP; +NOP; +NOP; +JUMP 4; // Jump gets killed in EX1 stage +NOP; +NOP; + +EXCPT 5; +NOP; +NOP; +NOP; +NOP; +JUMP 4; // Jump gets killed in AC stage +NOP; +NOP; + +EXCPT 6; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP 4; // Jump gets killed in DEC stage +NOP; +NOP; + +EXCPT 7; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP 4; // Jump gets killed in IF2 stage +NOP; +NOP; + +EXCPT 8; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP 4; // Jump gets killed in IF1 stage +NOP; +NOP; + + // Read out the Rest of the Trace Buffer. +LD32(p0, TBUFSTAT); + // Read TBUFSTAT MMR + P1 = [ P0 ]; + + // if p1 is zero skip the loop. +CC = P1 == 0; +IF CC JUMP OUT1; + + // Read out the Entire Trace Buffer. +LD32(p0, TBUF); +LSETUP ( l1s , l1e ) LC0 = P1; +l1s:R0 = [ P0 ]; +l1e:R0 = [ P0 ]; + + // Don't RTI if you never wish to go to User Mode + // use END_TEST instead. + +OUT1: +dbg_pass; + +// rti; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + + // YOUR USER CODE GOES HERE. + +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_DATA_ADDR_2 //.data 0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/dbg_tr_basic.S b/sim/testsuite/sim/bfin/dbg_tr_basic.S new file mode 100644 index 0000000..b7fa5b6 --- /dev/null +++ b/sim/testsuite/sim/bfin/dbg_tr_basic.S @@ -0,0 +1,272 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_tr_basic/dbg_tr_basic.dsp +// Description: Verify the basic functionality of TBUFPWR and TBUFEN in +// Supervisor mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(mmrs.inc) +include(selfcheck.inc) + +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +// This test embeds .text offsets, so pad our test so it lines up. +.space 0x70 + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + +CHECK_INIT(p5, 0x00BFFFFC); + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +LD32_LABEL(r7, DUMMY); +RETI = r7; +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; + + + + START : +WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn ON trace Buffer + // TBUFPWR = 0 + // TBUFEN = 0 + // TBUFOVF = 0 + // CMPLP = 0 +NOP; +NOP; +NOP; +NOP; +NOP; + NOP; +NOP; +JUMP.S label1; // + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label2: R5.H = 0x7777; // + R5.L = 0x7888; +JUMP.S label3; // + R6.L = 0x1111; // Will be killed + R6.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +label1: R4.H = 0x5555; // + R4.L = 0x6666; +NOP; +WR_MMR(TBUFCTL, 0x00000002, p0, r0); // + // TBUFPWR = 0 + // TBUFEN = 1 + // TBUFOVF = 0 + // CMPLP = 0 +NOP; +NOP; +NOP; +NOP; +JUMP.S label2; // + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +label3: R6.H = 0x7999; // + R6.L = 0x7aaa; +NOP; +NOP; +WR_MMR(TBUFCTL, 0x00000001, p0, r0); + NOP; + NOP; + NOP; +WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer + // TBUFPWR = 1 + // TBUFEN = 1 + // TBUFOVF = 0 + // CMPLP = 0 +NOP; +NOP; +NOP; +NOP; +JUMP.S label4; // + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; + +label4: R6.H = 0x1aaa; // + R6.L = 0x2222; +NOP; +NOP; +NOP; +NOP; + +WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn OFF trace Buffer + +NOP; +NOP; +NOP; +NOP; + // Read the contents of the Trace Buffer + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000001); + + // Read 3rd Entry of the Trace Buffer +RD_MMR(TBUF, p0, r0); +CHECKREG(r0, 0x000002d2); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000001); + +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x000002c0); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000000); + + +WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn OFF trace Buffer Power + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; diff --git a/sim/testsuite/sim/bfin/dbg_tr_simplejp.S b/sim/testsuite/sim/bfin/dbg_tr_simplejp.S new file mode 100644 index 0000000..8fe5f20 --- /dev/null +++ b/sim/testsuite/sim/bfin/dbg_tr_simplejp.S @@ -0,0 +1,267 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_tr_simplejp/dbg_tr_simplejp.dsp +// Description: This test performs simple jumps and verifies the trace buffer +// recording for simple jumps. +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(mmrs.inc) +include(selfcheck.inc) +include(symtable.inc) + +#ifndef ITABLE +#define ITABLE CODE_ADDR_1 // +#endif + +// This test embeds .text offsets, so pad our test so it lines up. +.space 0x5e + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + +CHECK_INIT_DEF(p5); // CHECK_INIT(p5, 0x00BFFFFC); + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +LD32_LABEL(r7, DUMMY); +RETI = r7; +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; + + + + START : +WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer + // TBUFPWR = 1 + // TBUFEN = 1 + // TBUFOVF = 0 + // CMPLP = 0 +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label1; // 0x0224 + R4.L = 0x1111; // Will be killed + R4.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +label2: R5.H = 0x7777; // 0x0234 + R5.L = 0x7888; +JUMP.S label3; //0x023c + R6.L = 0x1111; // Will be killed + R6.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +NOP; +label1: R4.H = 0x5555; // 0x0250 + R4.L = 0x6666; +NOP; +JUMP.S label2; // 0x0258 + R5.L = 0x1111; // Will be killed + R5.H = 0x1111; // Will be killed +NOP; +NOP; +NOP; +NOP; +label3: R6.H = 0x7999; //0x026c + R6.L = 0x7aaa; +NOP; +NOP; +NOP; +NOP; + +WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn OFF trace Buffer + +NOP; +NOP; +NOP; +NOP; +NOP; + // Read the contents of the Trace Buffer + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000003); + + // Read 3rd Entry of the Trace Buffer +RD_MMR(TBUF, p0, r0); +CHECKREG(r0, 0x0000026c); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000003); + +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x0000023c); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000002); + + // Read 2nd Entry of the Trace Buffer +RD_MMR(TBUF, p0, r0); +CHECKREG(r0, 0x00000234); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000002); + +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x0000025a); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000001); + + // Read ist Entry of the Trace Buffer +RD_MMR(TBUF, p0, r0); +CHECKREG(r0, 0x00000250); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000001); + +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x00000224); + +RD_MMR(TBUFSTAT, p0, r2); +CHECKREG(r2, 0x00000000); + +WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn OFF trace Buffer Power + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; diff --git a/sim/testsuite/sim/bfin/dbg_tr_tbuf0.S b/sim/testsuite/sim/bfin/dbg_tr_tbuf0.S new file mode 100644 index 0000000..82ca6ce --- /dev/null +++ b/sim/testsuite/sim/bfin/dbg_tr_tbuf0.S @@ -0,0 +1,262 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_tr_tbuf0/dbg_tr_tbuf0.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(mmrs.inc) +include(selfcheck.inc) + +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +// This test embeds .text offsets, so pad our test so it lines up. +.space 0x64 + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + +CHECK_INIT(p5, 0x00BFFFFC); + + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +LD32_LABEL(r7, DUMMY); +RETI = r7; +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; + + + + START : + +WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn ON trace Buffer +WR_MMR(TBUFCTL, 0x0000000b, p0, r0); // Turn ON trace Buffer + // TBUFPWR = 1 + // TBUFEN = 1 + // TBUFOVF = 0 + // CMPLP = 01 +NOP; +NOP; +NOP; + NOP; + NOP; + R6 = 0; + R7 = 10; + +JMP: + JUMP.S LABEL0; + NOP; + NOP; + +LABEL0: + P1 = 0x0006; + JUMP (PC+P1); + +LABEL1: + LD32(R3, 0xBADD); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + +LABEL2: + CC = R7 == R6; + IF CC JUMP END; + R6 += 1; + JUMP LABEL2; + +LABEL3: + NOP; + +LABEL4: + LD32(R4, 0xBADD); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + + + + +END: + R0 = 1; + NOP; + NOP; + NOP; + +CHECKREG(r3, 0x00000000); +CHECKREG(r4, 0x00000000); + // Read the contents of the Trace Buffer + +RD_MMR(TBUFSTAT, p0, r0); +CHECKREG(r0, 0x00000004); + + // Read last entry of the Trace Buffer +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x00000256); + +RD_MMR(TBUF, p0, r2); +CHECKREG(r2, 0x00000246); + +RD_MMR(TBUFSTAT, p0, r0); +CHECKREG(r0, 0x00000003); + + // Read last entry of the Trace Buffer +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x00000245); + +RD_MMR(TBUF, p0, r2); +CHECKREG(r2, 0x0000024a); + +RD_MMR(TBUFSTAT, p0, r0); +CHECKREG(r0, 0x00000002); + + // Read last entry of the Trace Buffer +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x00000240); + +RD_MMR(TBUF, p0, r2); +CHECKREG(r2, 0x0000023a); + +RD_MMR(TBUFSTAT, p0, r0); +CHECKREG(r0, 0x00000001); + + // Read last entry of the Trace Buffer +RD_MMR(TBUF, p0, r1); +CHECKREG(r1, 0x00000238); + +RD_MMR(TBUF, p0, r2); +CHECKREG(r2, 0x00000232); + + + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + +RTX; + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; diff --git a/sim/testsuite/sim/bfin/dbg_tr_umode.S b/sim/testsuite/sim/bfin/dbg_tr_umode.S new file mode 100644 index 0000000..83c3f74 --- /dev/null +++ b/sim/testsuite/sim/bfin/dbg_tr_umode.S @@ -0,0 +1,314 @@ +//Original:/proj/frio/dv/testcases/debug/dbg_tr_umode/dbg_tr_umode.dsp +// Description: Verify the basic functionality of TBUFPWR and TBUFEN in +// Supervisor mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(std.inc) +include(mmrs.inc) +include(selfcheck.inc) + +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x20 +#endif + +// This test embeds .text offsets, so pad our test so it lines up. +.space 0x64 + +// Boot code + + BOOT : +INIT_R_REGS(0); // Initialize Dregs +INIT_P_REGS(0); // Initialize Pregs + +CHECK_INIT(p5, 0x00BFFFFC); + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE); // IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE); // IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE); // IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE); // IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE); // IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE); // IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +LD32_LABEL(p1, START); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +LD32_LABEL(r7, DUMMY); +RETI = r7; +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; +NOP; +NOP; +NOP; +DUMMY: + NOP; +NOP; +NOP; +NOP; + +// .code 0x200 +START: +WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn ON trace Buffer +WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer + // TBUFPWR = 1 + // TBUFEN = 1 + // TBUFOVF = 0 + // CMPLP = 0 +NOP; +NOP; +NOP; +NOP; + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +RTI; + +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + +NOP; + NOP; +NOP; +JUMP.S label1; + R4.L = 0x1111; + R4.H = 0x1111; +NOP; +NOP; +NOP; +label2: R5.H = 0x7777; + R5.L = 0x7888; +JUMP.S label3; + R6.L = 0x1111; + R6.H = 0x1111; +NOP; +NOP; +NOP; +NOP; +NOP; +label1: R4.H = 0x5555; + R4.L = 0x6666; +NOP; +NOP; +NOP; +NOP; +NOP; +JUMP.S label2; + R5.L = 0x1111; + R5.H = 0x1111; +NOP; +NOP; +NOP; +NOP; +label3: + NOP; +NOP; +NOP; + NOP; + NOP; + NOP; +NOP; +NOP; + // Checks the contents of the Trace Buffer + + EXCPT 0; + NOP; NOP; NOP; NOP; +CHECKREG(r2, 0x00000006); +CHECKREG(r1, 0x00000416); +CHECKREG(r0, 0x000002aa); +CHECKREG(r3, 0x0000029a); +CHECKREG(r4, 0x00000262); +CHECKREG(r5, 0x00000004); +CHECKREG(r6, 0x0000025a); +CHECKREG(r7, 0x00000288); + NOP; NOP; NOP; NOP; + NOP; NOP; NOP; NOP; + + EXCPT 1; + NOP; NOP; NOP; NOP; + CHECKREG(r2, 0x00000005); +CHECKREG(r1, 0x00000416); +CHECKREG(r0, 0x00000304); +CHECKREG(r3, 0x000002ac); +CHECKREG(r4, 0x00000470); +CHECKREG(r5, 0x00000003); +CHECKREG(r6, 0x00000276); +CHECKREG(r7, 0x0000024a); + NOP; NOP; NOP; NOP; + NOP; NOP; NOP; NOP; + + EXCPT 2; + NOP; NOP; NOP; NOP; + CHECKREG(r2, 0x00000004); +CHECKREG(r1, 0x00000416); +CHECKREG(r0, 0x0000035e); +CHECKREG(r3, 0x00000306); +CHECKREG(r4, 0x00000470); +CHECKREG(r5, 0x00000002); +CHECKREG(r6, 0x00000244); +CHECKREG(r7, 0x00000242); + NOP; NOP; NOP; NOP; + + EXCPT 3; + NOP; NOP; NOP; NOP; + CHECKREG(r2, 0x00000003); +CHECKREG(r1, 0x00000416); +CHECKREG(r0, 0x000003b0); +CHECKREG(r3, 0x00000360); +CHECKREG(r4, 0x00000470); +CHECKREG(r5, 0x00000001); +CHECKREG(r6, 0x00000238); +CHECKREG(r7, 0x00000236); + + + +NOP; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + + + +//********************************************************************* +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + R7 = SEQSTAT; + +RD_MMR(TBUFSTAT, p0, r2); +RD_MMR(TBUF, p0, r1); +RD_MMR(TBUF, p0, r0); +RD_MMR(TBUF, p0, r3); +RD_MMR(TBUF, p0, r4); +RD_MMR(TBUFSTAT, p0, r5); +RD_MMR(TBUF, p0, r6); +RD_MMR(TBUF, p0, r7); + + NOP; NOP; NOP; NOP; + +RTX; + + NOP; NOP; NOP; NOP; + NOP; NOP; NOP; NOP; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/disalnexcpt_implicit.S b/sim/testsuite/sim/bfin/disalnexcpt_implicit.S new file mode 100644 index 0000000..9f6c83c --- /dev/null +++ b/sim/testsuite/sim/bfin/disalnexcpt_implicit.S @@ -0,0 +1,122 @@ +# Blackfin testcase for insns that implicitly have DISALGNEXCPT behavior +# when used in parallel insns +# mach: bfin + +#include "test.h" + .include "testutils.inc" + + start + + LINK 0x100; + + # Set up I0/I1/I2/I3 to be unaligned by 0/1/2/3 bytes + init_l_regs 0 + init_m_regs 0 + R0 = SP; + BITCLR (R0, 0); + BITCLR (R0, 1); + I0 = R0; + B0 = R0; + R1 = 1; + R1 = R0 + R1; + I1 = R1; + B1 = R1; + R2 = 2; + R2 = R0 + R2; + I2 = R2; + B2 = R2; + R3 = 3; + R3 = R0 + R3; + I3 = R3; + B3 = R3; + +#define EXP_VAL 0x12345678 +#define EXP(r, n) CHECKREG (r, EXP_VAL); r = 0; I##n = B##n + imm32 R5, EXP_VAL; + imm32 R6, 0x9abcdef0; + imm32 R7, 0x0a1b2c3e; + [SP] = R5; + [SP - 4] = R6; + [SP + 4] = R7; + +#define BYTEPACK(n) \ + R7 = BYTEPACK (R0, R1) || R4 = [I##n]; EXP (R4, n); \ + R6 = BYTEPACK (R0, R1) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + R5 = BYTEPACK (R0, R1) || R6 = [I##n++]; EXP (R6, n); \ + R4 = BYTEPACK (R0, R1) || R7 = [I##n--]; EXP (R7, n); + BYTEPACK(0) + BYTEPACK(1) + BYTEPACK(2) + BYTEPACK(3) + +#define BYTEUNPACK(n) \ + (R7, R5) = BYTEUNPACK R1:0 || R4 = [I##n]; EXP (R4, n); \ + (R6, R7) = BYTEUNPACK R3:2 || R5 = [I##n ++ M##n]; EXP (R5, n); \ + (R5, R4) = BYTEUNPACK R1:0 || R6 = [I##n++]; EXP (R6, n); \ + (R4, R6) = BYTEUNPACK R3:2 || R7 = [I##n--]; EXP (R7, n); + BYTEUNPACK(0) + BYTEUNPACK(1) + BYTEUNPACK(2) + BYTEUNPACK(3) + +#define SAA(n) \ + SAA (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \ + SAA (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + SAA (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \ + SAA (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n); + SAA(0) + SAA(1) + SAA(2) + SAA(3) + +#define BYTEOP1P(n) \ + R7 = BYTEOP1P (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \ + R6 = BYTEOP1P (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + R5 = BYTEOP1P (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \ + R4 = BYTEOP1P (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n); + BYTEOP1P(0) + BYTEOP1P(1) + BYTEOP1P(2) + BYTEOP1P(3) + +#define BYTEOP2P(n) \ + R7 = BYTEOP2P (R1:0, R3:2) (TL) || R4 = [I##n]; EXP (R4, n); \ + R6 = BYTEOP2P (R1:0, R3:2) (TH) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + R5 = BYTEOP2P (R1:0, R3:2) (RNDL) || R6 = [I##n++]; EXP (R6, n); \ + R4 = BYTEOP2P (R1:0, R3:2) (RNDH) || R7 = [I##n--]; EXP (R7, n); + BYTEOP2P(0) + BYTEOP2P(1) + BYTEOP2P(2) + BYTEOP2P(3) + +#define BYTEOP3P(n) \ + R7 = BYTEOP3P (R1:0, R3:2) (LO) || R4 = [I##n]; EXP (R4, n); \ + R6 = BYTEOP3P (R1:0, R3:2) (HI) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + R5 = BYTEOP3P (R1:0, R3:2) (LO) || R6 = [I##n++]; EXP (R6, n); \ + R4 = BYTEOP3P (R1:0, R3:2) (HI) || R7 = [I##n--]; EXP (R7, n); + BYTEOP3P(0) + BYTEOP3P(1) + BYTEOP3P(2) + BYTEOP3P(3) + +#define BYTEOP16P(n) \ + (R7, R6) = BYTEOP16P (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \ + (R6, R4) = BYTEOP16P (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + (R5, R7) = BYTEOP16P (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \ + (R4, R6) = BYTEOP16P (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n); + BYTEOP16P(0) + BYTEOP16P(1) + BYTEOP16P(2) + BYTEOP16P(3) + +#define BYTEOP16M(n) \ + (R7, R5) = BYTEOP16M (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \ + (R6, R7) = BYTEOP16M (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \ + (R5, R4) = BYTEOP16M (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \ + (R4, R5) = BYTEOP16M (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n); + BYTEOP16M(0) + BYTEOP16M(1) + BYTEOP16M(2) + BYTEOP16M(3) + + pass diff --git a/sim/testsuite/sim/bfin/div0.s b/sim/testsuite/sim/bfin/div0.s new file mode 100644 index 0000000..e52fe45 --- /dev/null +++ b/sim/testsuite/sim/bfin/div0.s @@ -0,0 +1,37 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 70 (X); + R1 = 5; + + P2 = 16; + DIVS ( R0 , R1 ); + LSETUP ( s0 , s0 ) LC0 = P2; +s0: + DIVQ ( R0 , R1 ); + + DBGA ( R0.L , 14 ); + + R0 = 3272 (X); + R1 = 55; + + DIVS ( R0 , R1 ); + LSETUP ( s1 , s1 ) LC0 = P2; +s1: + DIVQ ( R0 , R1 ); + + DBGA ( R0.L , 59 ); + + R0 = 32767 (X); + R1 = 55; + DIVS ( R0 , R1 ); + + LSETUP ( s2 , s2 ) LC0 = P2; +s2: + DIVQ ( R0 , R1 ); + + DBGA ( R0.L , 595 ); + + pass diff --git a/sim/testsuite/sim/bfin/divq.s b/sim/testsuite/sim/bfin/divq.s new file mode 100644 index 0000000..6cb881b --- /dev/null +++ b/sim/testsuite/sim/bfin/divq.s @@ -0,0 +1,1322 @@ +# Blackfin testcase for divide instructions +# mach: bfin + + + .include "testutils.inc" + + start + + /* + * Evaluate given a signed integer dividend and signed interger divisor + * input is: + * r0 = dividend, or numerator + * r1 = divisor, or denominator + * output is: + * r0 = quotient (16-bits) + */ + .macro divide num:req, den:req + imm32 r0 \num + r1 = \den (Z); + + r0 <<= 1; /* Left shift dividend by 1 needed for integer division */ + p0 = 15; /* Evaluate the quotient to 16 bits. */ + + /* Initialize AQ status bit and dividend for the DIVQ loop. */ + divs (r0, r1); + + /* Evaluate DIVQ p0=15 times. */ + lsetup (1f, 1f) lc0=p0; +1: + divq (r0, r1); + + /* Sign extend the 16-bit quotient to 32bits. */ + r0 = r0.l (x); + + imm32 r1, (\num / \den); + CC = r0 == r1 + if CC jump 2f; + fail +2: + .endm + + /* test a bunch of values, making sure not to : + * - exceed a signed 16-bit divisor + * - exceed a signed 16-bit answer + */ + divide 0x00000001, 0x0001 /* expect 0x0001 */ + divide 0x00000001, 0x0002 /* expect 0x0000 */ + divide 0x00000001, 0x0003 /* expect 0x0000 */ + divide 0x00000001, 0x0004 /* expect 0x0000 */ + divide 0x00000001, 0x0007 /* expect 0x0000 */ + divide 0x00000001, 0x0008 /* expect 0x0000 */ + divide 0x00000001, 0x000f /* expect 0x0000 */ + divide 0x00000001, 0x0010 /* expect 0x0000 */ + divide 0x00000001, 0x001f /* expect 0x0000 */ + divide 0x00000001, 0x0020 /* expect 0x0000 */ + divide 0x00000001, 0x003f /* expect 0x0000 */ + divide 0x00000001, 0x0040 /* expect 0x0000 */ + divide 0x00000001, 0x007f /* expect 0x0000 */ + divide 0x00000001, 0x0080 /* expect 0x0000 */ + divide 0x00000001, 0x00ff /* expect 0x0000 */ + divide 0x00000001, 0x0100 /* expect 0x0000 */ + divide 0x00000001, 0x01ff /* expect 0x0000 */ + divide 0x00000001, 0x0200 /* expect 0x0000 */ + divide 0x00000001, 0x03ff /* expect 0x0000 */ + divide 0x00000001, 0x0400 /* expect 0x0000 */ + divide 0x00000001, 0x07ff /* expect 0x0000 */ + divide 0x00000001, 0x0800 /* expect 0x0000 */ + divide 0x00000001, 0x0fff /* expect 0x0000 */ + divide 0x00000001, 0x1000 /* expect 0x0000 */ + divide 0x00000001, 0x1fff /* expect 0x0000 */ + divide 0x00000001, 0x2000 /* expect 0x0000 */ + divide 0x00000001, 0x3fff /* expect 0x0000 */ + divide 0x00000001, 0x4000 /* expect 0x0000 */ + divide 0x00000001, 0x7fff /* expect 0x0000 */ + divide 0x00000002, 0x0001 /* expect 0x0002 */ + divide 0x00000002, 0x0002 /* expect 0x0001 */ + divide 0x00000002, 0x0003 /* expect 0x0000 */ + divide 0x00000002, 0x0004 /* expect 0x0000 */ + divide 0x00000002, 0x0007 /* expect 0x0000 */ + divide 0x00000002, 0x0008 /* expect 0x0000 */ + divide 0x00000002, 0x000f /* expect 0x0000 */ + divide 0x00000002, 0x0010 /* expect 0x0000 */ + divide 0x00000002, 0x001f /* expect 0x0000 */ + divide 0x00000002, 0x0020 /* expect 0x0000 */ + divide 0x00000002, 0x003f /* expect 0x0000 */ + divide 0x00000002, 0x0040 /* expect 0x0000 */ + divide 0x00000002, 0x007f /* expect 0x0000 */ + divide 0x00000002, 0x0080 /* expect 0x0000 */ + divide 0x00000002, 0x00ff /* expect 0x0000 */ + divide 0x00000002, 0x0100 /* expect 0x0000 */ + divide 0x00000002, 0x01ff /* expect 0x0000 */ + divide 0x00000002, 0x0200 /* expect 0x0000 */ + divide 0x00000002, 0x03ff /* expect 0x0000 */ + divide 0x00000002, 0x0400 /* expect 0x0000 */ + divide 0x00000002, 0x07ff /* expect 0x0000 */ + divide 0x00000002, 0x0800 /* expect 0x0000 */ + divide 0x00000002, 0x0fff /* expect 0x0000 */ + divide 0x00000002, 0x1000 /* expect 0x0000 */ + divide 0x00000002, 0x1fff /* expect 0x0000 */ + divide 0x00000002, 0x2000 /* expect 0x0000 */ + divide 0x00000002, 0x3fff /* expect 0x0000 */ + divide 0x00000002, 0x4000 /* expect 0x0000 */ + divide 0x00000002, 0x7fff /* expect 0x0000 */ + divide 0x00000003, 0x0001 /* expect 0x0003 */ + divide 0x00000003, 0x0002 /* expect 0x0001 */ + divide 0x00000003, 0x0003 /* expect 0x0001 */ + divide 0x00000003, 0x0004 /* expect 0x0000 */ + divide 0x00000003, 0x0007 /* expect 0x0000 */ + divide 0x00000003, 0x0008 /* expect 0x0000 */ + divide 0x00000003, 0x000f /* expect 0x0000 */ + divide 0x00000003, 0x0010 /* expect 0x0000 */ + divide 0x00000003, 0x001f /* expect 0x0000 */ + divide 0x00000003, 0x0020 /* expect 0x0000 */ + divide 0x00000003, 0x003f /* expect 0x0000 */ + divide 0x00000003, 0x0040 /* expect 0x0000 */ + divide 0x00000003, 0x007f /* expect 0x0000 */ + divide 0x00000003, 0x0080 /* expect 0x0000 */ + divide 0x00000003, 0x00ff /* expect 0x0000 */ + divide 0x00000003, 0x0100 /* expect 0x0000 */ + divide 0x00000003, 0x01ff /* expect 0x0000 */ + divide 0x00000003, 0x0200 /* expect 0x0000 */ + divide 0x00000003, 0x03ff /* expect 0x0000 */ + divide 0x00000003, 0x0400 /* expect 0x0000 */ + divide 0x00000003, 0x07ff /* expect 0x0000 */ + divide 0x00000003, 0x0800 /* expect 0x0000 */ + divide 0x00000003, 0x0fff /* expect 0x0000 */ + divide 0x00000003, 0x1000 /* expect 0x0000 */ + divide 0x00000003, 0x1fff /* expect 0x0000 */ + divide 0x00000003, 0x2000 /* expect 0x0000 */ + divide 0x00000003, 0x3fff /* expect 0x0000 */ + divide 0x00000003, 0x4000 /* expect 0x0000 */ + divide 0x00000003, 0x7fff /* expect 0x0000 */ + divide 0x00000004, 0x0001 /* expect 0x0004 */ + divide 0x00000004, 0x0002 /* expect 0x0002 */ + divide 0x00000004, 0x0003 /* expect 0x0001 */ + divide 0x00000004, 0x0004 /* expect 0x0001 */ + divide 0x00000004, 0x0007 /* expect 0x0000 */ + divide 0x00000004, 0x0008 /* expect 0x0000 */ + divide 0x00000004, 0x000f /* expect 0x0000 */ + divide 0x00000004, 0x0010 /* expect 0x0000 */ + divide 0x00000004, 0x001f /* expect 0x0000 */ + divide 0x00000004, 0x0020 /* expect 0x0000 */ + divide 0x00000004, 0x003f /* expect 0x0000 */ + divide 0x00000004, 0x0040 /* expect 0x0000 */ + divide 0x00000004, 0x007f /* expect 0x0000 */ + divide 0x00000004, 0x0080 /* expect 0x0000 */ + divide 0x00000004, 0x00ff /* expect 0x0000 */ + divide 0x00000004, 0x0100 /* expect 0x0000 */ + divide 0x00000004, 0x01ff /* expect 0x0000 */ + divide 0x00000004, 0x0200 /* expect 0x0000 */ + divide 0x00000004, 0x03ff /* expect 0x0000 */ + divide 0x00000004, 0x0400 /* expect 0x0000 */ + divide 0x00000004, 0x07ff /* expect 0x0000 */ + divide 0x00000004, 0x0800 /* expect 0x0000 */ + divide 0x00000004, 0x0fff /* expect 0x0000 */ + divide 0x00000004, 0x1000 /* expect 0x0000 */ + divide 0x00000004, 0x1fff /* expect 0x0000 */ + divide 0x00000004, 0x2000 /* expect 0x0000 */ + divide 0x00000004, 0x3fff /* expect 0x0000 */ + divide 0x00000004, 0x4000 /* expect 0x0000 */ + divide 0x00000004, 0x7fff /* expect 0x0000 */ + divide 0x00000007, 0x0001 /* expect 0x0007 */ + divide 0x00000007, 0x0002 /* expect 0x0003 */ + divide 0x00000007, 0x0003 /* expect 0x0002 */ + divide 0x00000007, 0x0004 /* expect 0x0001 */ + divide 0x00000007, 0x0007 /* expect 0x0001 */ + divide 0x00000007, 0x0008 /* expect 0x0000 */ + divide 0x00000007, 0x000f /* expect 0x0000 */ + divide 0x00000007, 0x0010 /* expect 0x0000 */ + divide 0x00000007, 0x001f /* expect 0x0000 */ + divide 0x00000007, 0x0020 /* expect 0x0000 */ + divide 0x00000007, 0x003f /* expect 0x0000 */ + divide 0x00000007, 0x0040 /* expect 0x0000 */ + divide 0x00000007, 0x007f /* expect 0x0000 */ + divide 0x00000007, 0x0080 /* expect 0x0000 */ + divide 0x00000007, 0x00ff /* expect 0x0000 */ + divide 0x00000007, 0x0100 /* expect 0x0000 */ + divide 0x00000007, 0x01ff /* expect 0x0000 */ + divide 0x00000007, 0x0200 /* expect 0x0000 */ + divide 0x00000007, 0x03ff /* expect 0x0000 */ + divide 0x00000007, 0x0400 /* expect 0x0000 */ + divide 0x00000007, 0x07ff /* expect 0x0000 */ + divide 0x00000007, 0x0800 /* expect 0x0000 */ + divide 0x00000007, 0x0fff /* expect 0x0000 */ + divide 0x00000007, 0x1000 /* expect 0x0000 */ + divide 0x00000007, 0x1fff /* expect 0x0000 */ + divide 0x00000007, 0x2000 /* expect 0x0000 */ + divide 0x00000007, 0x3fff /* expect 0x0000 */ + divide 0x00000007, 0x4000 /* expect 0x0000 */ + divide 0x00000007, 0x7fff /* expect 0x0000 */ + divide 0x00000008, 0x0001 /* expect 0x0008 */ + divide 0x00000008, 0x0002 /* expect 0x0004 */ + divide 0x00000008, 0x0003 /* expect 0x0002 */ + divide 0x00000008, 0x0004 /* expect 0x0002 */ + divide 0x00000008, 0x0007 /* expect 0x0001 */ + divide 0x00000008, 0x0008 /* expect 0x0001 */ + divide 0x00000008, 0x000f /* expect 0x0000 */ + divide 0x00000008, 0x0010 /* expect 0x0000 */ + divide 0x00000008, 0x001f /* expect 0x0000 */ + divide 0x00000008, 0x0020 /* expect 0x0000 */ + divide 0x00000008, 0x003f /* expect 0x0000 */ + divide 0x00000008, 0x0040 /* expect 0x0000 */ + divide 0x00000008, 0x007f /* expect 0x0000 */ + divide 0x00000008, 0x0080 /* expect 0x0000 */ + divide 0x00000008, 0x00ff /* expect 0x0000 */ + divide 0x00000008, 0x0100 /* expect 0x0000 */ + divide 0x00000008, 0x01ff /* expect 0x0000 */ + divide 0x00000008, 0x0200 /* expect 0x0000 */ + divide 0x00000008, 0x03ff /* expect 0x0000 */ + divide 0x00000008, 0x0400 /* expect 0x0000 */ + divide 0x00000008, 0x07ff /* expect 0x0000 */ + divide 0x00000008, 0x0800 /* expect 0x0000 */ + divide 0x00000008, 0x0fff /* expect 0x0000 */ + divide 0x00000008, 0x1000 /* expect 0x0000 */ + divide 0x00000008, 0x1fff /* expect 0x0000 */ + divide 0x00000008, 0x2000 /* expect 0x0000 */ + divide 0x00000008, 0x3fff /* expect 0x0000 */ + divide 0x00000008, 0x4000 /* expect 0x0000 */ + divide 0x00000008, 0x7fff /* expect 0x0000 */ + divide 0x0000000f, 0x0001 /* expect 0x000f */ + divide 0x0000000f, 0x0002 /* expect 0x0007 */ + divide 0x0000000f, 0x0003 /* expect 0x0005 */ + divide 0x0000000f, 0x0004 /* expect 0x0003 */ + divide 0x0000000f, 0x0007 /* expect 0x0002 */ + divide 0x0000000f, 0x0008 /* expect 0x0001 */ + divide 0x0000000f, 0x000f /* expect 0x0001 */ + divide 0x0000000f, 0x0010 /* expect 0x0000 */ + divide 0x0000000f, 0x001f /* expect 0x0000 */ + divide 0x0000000f, 0x0020 /* expect 0x0000 */ + divide 0x0000000f, 0x003f /* expect 0x0000 */ + divide 0x0000000f, 0x0040 /* expect 0x0000 */ + divide 0x0000000f, 0x007f /* expect 0x0000 */ + divide 0x0000000f, 0x0080 /* expect 0x0000 */ + divide 0x0000000f, 0x00ff /* expect 0x0000 */ + divide 0x0000000f, 0x0100 /* expect 0x0000 */ + divide 0x0000000f, 0x01ff /* expect 0x0000 */ + divide 0x0000000f, 0x0200 /* expect 0x0000 */ + divide 0x0000000f, 0x03ff /* expect 0x0000 */ + divide 0x0000000f, 0x0400 /* expect 0x0000 */ + divide 0x0000000f, 0x07ff /* expect 0x0000 */ + divide 0x0000000f, 0x0800 /* expect 0x0000 */ + divide 0x0000000f, 0x0fff /* expect 0x0000 */ + divide 0x0000000f, 0x1000 /* expect 0x0000 */ + divide 0x0000000f, 0x1fff /* expect 0x0000 */ + divide 0x0000000f, 0x2000 /* expect 0x0000 */ + divide 0x0000000f, 0x3fff /* expect 0x0000 */ + divide 0x0000000f, 0x4000 /* expect 0x0000 */ + divide 0x0000000f, 0x7fff /* expect 0x0000 */ + divide 0x00000010, 0x0001 /* expect 0x0010 */ + divide 0x00000010, 0x0002 /* expect 0x0008 */ + divide 0x00000010, 0x0003 /* expect 0x0005 */ + divide 0x00000010, 0x0004 /* expect 0x0004 */ + divide 0x00000010, 0x0007 /* expect 0x0002 */ + divide 0x00000010, 0x0008 /* expect 0x0002 */ + divide 0x00000010, 0x000f /* expect 0x0001 */ + divide 0x00000010, 0x0010 /* expect 0x0001 */ + divide 0x00000010, 0x001f /* expect 0x0000 */ + divide 0x00000010, 0x0020 /* expect 0x0000 */ + divide 0x00000010, 0x003f /* expect 0x0000 */ + divide 0x00000010, 0x0040 /* expect 0x0000 */ + divide 0x00000010, 0x007f /* expect 0x0000 */ + divide 0x00000010, 0x0080 /* expect 0x0000 */ + divide 0x00000010, 0x00ff /* expect 0x0000 */ + divide 0x00000010, 0x0100 /* expect 0x0000 */ + divide 0x00000010, 0x01ff /* expect 0x0000 */ + divide 0x00000010, 0x0200 /* expect 0x0000 */ + divide 0x00000010, 0x03ff /* expect 0x0000 */ + divide 0x00000010, 0x0400 /* expect 0x0000 */ + divide 0x00000010, 0x07ff /* expect 0x0000 */ + divide 0x00000010, 0x0800 /* expect 0x0000 */ + divide 0x00000010, 0x0fff /* expect 0x0000 */ + divide 0x00000010, 0x1000 /* expect 0x0000 */ + divide 0x00000010, 0x1fff /* expect 0x0000 */ + divide 0x00000010, 0x2000 /* expect 0x0000 */ + divide 0x00000010, 0x3fff /* expect 0x0000 */ + divide 0x00000010, 0x4000 /* expect 0x0000 */ + divide 0x00000010, 0x7fff /* expect 0x0000 */ + divide 0x0000001f, 0x0001 /* expect 0x001f */ + divide 0x0000001f, 0x0002 /* expect 0x000f */ + divide 0x0000001f, 0x0003 /* expect 0x000a */ + divide 0x0000001f, 0x0004 /* expect 0x0007 */ + divide 0x0000001f, 0x0007 /* expect 0x0004 */ + divide 0x0000001f, 0x0008 /* expect 0x0003 */ + divide 0x0000001f, 0x000f /* expect 0x0002 */ + divide 0x0000001f, 0x0010 /* expect 0x0001 */ + divide 0x0000001f, 0x001f /* expect 0x0001 */ + divide 0x0000001f, 0x0020 /* expect 0x0000 */ + divide 0x0000001f, 0x003f /* expect 0x0000 */ + divide 0x0000001f, 0x0040 /* expect 0x0000 */ + divide 0x0000001f, 0x007f /* expect 0x0000 */ + divide 0x0000001f, 0x0080 /* expect 0x0000 */ + divide 0x0000001f, 0x00ff /* expect 0x0000 */ + divide 0x0000001f, 0x0100 /* expect 0x0000 */ + divide 0x0000001f, 0x01ff /* expect 0x0000 */ + divide 0x0000001f, 0x0200 /* expect 0x0000 */ + divide 0x0000001f, 0x03ff /* expect 0x0000 */ + divide 0x0000001f, 0x0400 /* expect 0x0000 */ + divide 0x0000001f, 0x07ff /* expect 0x0000 */ + divide 0x0000001f, 0x0800 /* expect 0x0000 */ + divide 0x0000001f, 0x0fff /* expect 0x0000 */ + divide 0x0000001f, 0x1000 /* expect 0x0000 */ + divide 0x0000001f, 0x1fff /* expect 0x0000 */ + divide 0x0000001f, 0x2000 /* expect 0x0000 */ + divide 0x0000001f, 0x3fff /* expect 0x0000 */ + divide 0x0000001f, 0x4000 /* expect 0x0000 */ + divide 0x0000001f, 0x7fff /* expect 0x0000 */ + divide 0x00000020, 0x0001 /* expect 0x0020 */ + divide 0x00000020, 0x0002 /* expect 0x0010 */ + divide 0x00000020, 0x0003 /* expect 0x000a */ + divide 0x00000020, 0x0004 /* expect 0x0008 */ + divide 0x00000020, 0x0007 /* expect 0x0004 */ + divide 0x00000020, 0x0008 /* expect 0x0004 */ + divide 0x00000020, 0x000f /* expect 0x0002 */ + divide 0x00000020, 0x0010 /* expect 0x0002 */ + divide 0x00000020, 0x001f /* expect 0x0001 */ + divide 0x00000020, 0x0020 /* expect 0x0001 */ + divide 0x00000020, 0x003f /* expect 0x0000 */ + divide 0x00000020, 0x0040 /* expect 0x0000 */ + divide 0x00000020, 0x007f /* expect 0x0000 */ + divide 0x00000020, 0x0080 /* expect 0x0000 */ + divide 0x00000020, 0x00ff /* expect 0x0000 */ + divide 0x00000020, 0x0100 /* expect 0x0000 */ + divide 0x00000020, 0x01ff /* expect 0x0000 */ + divide 0x00000020, 0x0200 /* expect 0x0000 */ + divide 0x00000020, 0x03ff /* expect 0x0000 */ + divide 0x00000020, 0x0400 /* expect 0x0000 */ + divide 0x00000020, 0x07ff /* expect 0x0000 */ + divide 0x00000020, 0x0800 /* expect 0x0000 */ + divide 0x00000020, 0x0fff /* expect 0x0000 */ + divide 0x00000020, 0x1000 /* expect 0x0000 */ + divide 0x00000020, 0x1fff /* expect 0x0000 */ + divide 0x00000020, 0x2000 /* expect 0x0000 */ + divide 0x00000020, 0x3fff /* expect 0x0000 */ + divide 0x00000020, 0x4000 /* expect 0x0000 */ + divide 0x00000020, 0x7fff /* expect 0x0000 */ + divide 0x0000003f, 0x0001 /* expect 0x003f */ + divide 0x0000003f, 0x0002 /* expect 0x001f */ + divide 0x0000003f, 0x0003 /* expect 0x0015 */ + divide 0x0000003f, 0x0004 /* expect 0x000f */ + divide 0x0000003f, 0x0007 /* expect 0x0009 */ + divide 0x0000003f, 0x0008 /* expect 0x0007 */ + divide 0x0000003f, 0x000f /* expect 0x0004 */ + divide 0x0000003f, 0x0010 /* expect 0x0003 */ + divide 0x0000003f, 0x001f /* expect 0x0002 */ + divide 0x0000003f, 0x0020 /* expect 0x0001 */ + divide 0x0000003f, 0x003f /* expect 0x0001 */ + divide 0x0000003f, 0x0040 /* expect 0x0000 */ + divide 0x0000003f, 0x007f /* expect 0x0000 */ + divide 0x0000003f, 0x0080 /* expect 0x0000 */ + divide 0x0000003f, 0x00ff /* expect 0x0000 */ + divide 0x0000003f, 0x0100 /* expect 0x0000 */ + divide 0x0000003f, 0x01ff /* expect 0x0000 */ + divide 0x0000003f, 0x0200 /* expect 0x0000 */ + divide 0x0000003f, 0x03ff /* expect 0x0000 */ + divide 0x0000003f, 0x0400 /* expect 0x0000 */ + divide 0x0000003f, 0x07ff /* expect 0x0000 */ + divide 0x0000003f, 0x0800 /* expect 0x0000 */ + divide 0x0000003f, 0x0fff /* expect 0x0000 */ + divide 0x0000003f, 0x1000 /* expect 0x0000 */ + divide 0x0000003f, 0x1fff /* expect 0x0000 */ + divide 0x0000003f, 0x2000 /* expect 0x0000 */ + divide 0x0000003f, 0x3fff /* expect 0x0000 */ + divide 0x0000003f, 0x4000 /* expect 0x0000 */ + divide 0x0000003f, 0x7fff /* expect 0x0000 */ + divide 0x00000040, 0x0001 /* expect 0x0040 */ + divide 0x00000040, 0x0002 /* expect 0x0020 */ + divide 0x00000040, 0x0003 /* expect 0x0015 */ + divide 0x00000040, 0x0004 /* expect 0x0010 */ + divide 0x00000040, 0x0007 /* expect 0x0009 */ + divide 0x00000040, 0x0008 /* expect 0x0008 */ + divide 0x00000040, 0x000f /* expect 0x0004 */ + divide 0x00000040, 0x0010 /* expect 0x0004 */ + divide 0x00000040, 0x001f /* expect 0x0002 */ + divide 0x00000040, 0x0020 /* expect 0x0002 */ + divide 0x00000040, 0x003f /* expect 0x0001 */ + divide 0x00000040, 0x0040 /* expect 0x0001 */ + divide 0x00000040, 0x007f /* expect 0x0000 */ + divide 0x00000040, 0x0080 /* expect 0x0000 */ + divide 0x00000040, 0x00ff /* expect 0x0000 */ + divide 0x00000040, 0x0100 /* expect 0x0000 */ + divide 0x00000040, 0x01ff /* expect 0x0000 */ + divide 0x00000040, 0x0200 /* expect 0x0000 */ + divide 0x00000040, 0x03ff /* expect 0x0000 */ + divide 0x00000040, 0x0400 /* expect 0x0000 */ + divide 0x00000040, 0x07ff /* expect 0x0000 */ + divide 0x00000040, 0x0800 /* expect 0x0000 */ + divide 0x00000040, 0x0fff /* expect 0x0000 */ + divide 0x00000040, 0x1000 /* expect 0x0000 */ + divide 0x00000040, 0x1fff /* expect 0x0000 */ + divide 0x00000040, 0x2000 /* expect 0x0000 */ + divide 0x00000040, 0x3fff /* expect 0x0000 */ + divide 0x00000040, 0x4000 /* expect 0x0000 */ + divide 0x00000040, 0x7fff /* expect 0x0000 */ + divide 0x0000007f, 0x0001 /* expect 0x007f */ + divide 0x0000007f, 0x0002 /* expect 0x003f */ + divide 0x0000007f, 0x0003 /* expect 0x002a */ + divide 0x0000007f, 0x0004 /* expect 0x001f */ + divide 0x0000007f, 0x0007 /* expect 0x0012 */ + divide 0x0000007f, 0x0008 /* expect 0x000f */ + divide 0x0000007f, 0x000f /* expect 0x0008 */ + divide 0x0000007f, 0x0010 /* expect 0x0007 */ + divide 0x0000007f, 0x001f /* expect 0x0004 */ + divide 0x0000007f, 0x0020 /* expect 0x0003 */ + divide 0x0000007f, 0x003f /* expect 0x0002 */ + divide 0x0000007f, 0x0040 /* expect 0x0001 */ + divide 0x0000007f, 0x007f /* expect 0x0001 */ + divide 0x0000007f, 0x0080 /* expect 0x0000 */ + divide 0x0000007f, 0x00ff /* expect 0x0000 */ + divide 0x0000007f, 0x0100 /* expect 0x0000 */ + divide 0x0000007f, 0x01ff /* expect 0x0000 */ + divide 0x0000007f, 0x0200 /* expect 0x0000 */ + divide 0x0000007f, 0x03ff /* expect 0x0000 */ + divide 0x0000007f, 0x0400 /* expect 0x0000 */ + divide 0x0000007f, 0x07ff /* expect 0x0000 */ + divide 0x0000007f, 0x0800 /* expect 0x0000 */ + divide 0x0000007f, 0x0fff /* expect 0x0000 */ + divide 0x0000007f, 0x1000 /* expect 0x0000 */ + divide 0x0000007f, 0x1fff /* expect 0x0000 */ + divide 0x0000007f, 0x2000 /* expect 0x0000 */ + divide 0x0000007f, 0x3fff /* expect 0x0000 */ + divide 0x0000007f, 0x4000 /* expect 0x0000 */ + divide 0x0000007f, 0x7fff /* expect 0x0000 */ + divide 0x00000080, 0x0001 /* expect 0x0080 */ + divide 0x00000080, 0x0002 /* expect 0x0040 */ + divide 0x00000080, 0x0003 /* expect 0x002a */ + divide 0x00000080, 0x0004 /* expect 0x0020 */ + divide 0x00000080, 0x0007 /* expect 0x0012 */ + divide 0x00000080, 0x0008 /* expect 0x0010 */ + divide 0x00000080, 0x000f /* expect 0x0008 */ + divide 0x00000080, 0x0010 /* expect 0x0008 */ + divide 0x00000080, 0x001f /* expect 0x0004 */ + divide 0x00000080, 0x0020 /* expect 0x0004 */ + divide 0x00000080, 0x003f /* expect 0x0002 */ + divide 0x00000080, 0x0040 /* expect 0x0002 */ + divide 0x00000080, 0x007f /* expect 0x0001 */ + divide 0x00000080, 0x0080 /* expect 0x0001 */ + divide 0x00000080, 0x00ff /* expect 0x0000 */ + divide 0x00000080, 0x0100 /* expect 0x0000 */ + divide 0x00000080, 0x01ff /* expect 0x0000 */ + divide 0x00000080, 0x0200 /* expect 0x0000 */ + divide 0x00000080, 0x03ff /* expect 0x0000 */ + divide 0x00000080, 0x0400 /* expect 0x0000 */ + divide 0x00000080, 0x07ff /* expect 0x0000 */ + divide 0x00000080, 0x0800 /* expect 0x0000 */ + divide 0x00000080, 0x0fff /* expect 0x0000 */ + divide 0x00000080, 0x1000 /* expect 0x0000 */ + divide 0x00000080, 0x1fff /* expect 0x0000 */ + divide 0x00000080, 0x2000 /* expect 0x0000 */ + divide 0x00000080, 0x3fff /* expect 0x0000 */ + divide 0x00000080, 0x4000 /* expect 0x0000 */ + divide 0x00000080, 0x7fff /* expect 0x0000 */ + divide 0x000000ff, 0x0001 /* expect 0x00ff */ + divide 0x000000ff, 0x0002 /* expect 0x007f */ + divide 0x000000ff, 0x0003 /* expect 0x0055 */ + divide 0x000000ff, 0x0004 /* expect 0x003f */ + divide 0x000000ff, 0x0007 /* expect 0x0024 */ + divide 0x000000ff, 0x0008 /* expect 0x001f */ + divide 0x000000ff, 0x000f /* expect 0x0011 */ + divide 0x000000ff, 0x0010 /* expect 0x000f */ + divide 0x000000ff, 0x001f /* expect 0x0008 */ + divide 0x000000ff, 0x0020 /* expect 0x0007 */ + divide 0x000000ff, 0x003f /* expect 0x0004 */ + divide 0x000000ff, 0x0040 /* expect 0x0003 */ + divide 0x000000ff, 0x007f /* expect 0x0002 */ + divide 0x000000ff, 0x0080 /* expect 0x0001 */ + divide 0x000000ff, 0x00ff /* expect 0x0001 */ + divide 0x000000ff, 0x0100 /* expect 0x0000 */ + divide 0x000000ff, 0x01ff /* expect 0x0000 */ + divide 0x000000ff, 0x0200 /* expect 0x0000 */ + divide 0x000000ff, 0x03ff /* expect 0x0000 */ + divide 0x000000ff, 0x0400 /* expect 0x0000 */ + divide 0x000000ff, 0x07ff /* expect 0x0000 */ + divide 0x000000ff, 0x0800 /* expect 0x0000 */ + divide 0x000000ff, 0x0fff /* expect 0x0000 */ + divide 0x000000ff, 0x1000 /* expect 0x0000 */ + divide 0x000000ff, 0x1fff /* expect 0x0000 */ + divide 0x000000ff, 0x2000 /* expect 0x0000 */ + divide 0x000000ff, 0x3fff /* expect 0x0000 */ + divide 0x000000ff, 0x4000 /* expect 0x0000 */ + divide 0x000000ff, 0x7fff /* expect 0x0000 */ + divide 0x00000100, 0x0001 /* expect 0x0100 */ + divide 0x00000100, 0x0002 /* expect 0x0080 */ + divide 0x00000100, 0x0003 /* expect 0x0055 */ + divide 0x00000100, 0x0004 /* expect 0x0040 */ + divide 0x00000100, 0x0007 /* expect 0x0024 */ + divide 0x00000100, 0x0008 /* expect 0x0020 */ + divide 0x00000100, 0x000f /* expect 0x0011 */ + divide 0x00000100, 0x0010 /* expect 0x0010 */ + divide 0x00000100, 0x001f /* expect 0x0008 */ + divide 0x00000100, 0x0020 /* expect 0x0008 */ + divide 0x00000100, 0x003f /* expect 0x0004 */ + divide 0x00000100, 0x0040 /* expect 0x0004 */ + divide 0x00000100, 0x007f /* expect 0x0002 */ + divide 0x00000100, 0x0080 /* expect 0x0002 */ + divide 0x00000100, 0x00ff /* expect 0x0001 */ + divide 0x00000100, 0x0100 /* expect 0x0001 */ + divide 0x00000100, 0x01ff /* expect 0x0000 */ + divide 0x00000100, 0x0200 /* expect 0x0000 */ + divide 0x00000100, 0x03ff /* expect 0x0000 */ + divide 0x00000100, 0x0400 /* expect 0x0000 */ + divide 0x00000100, 0x07ff /* expect 0x0000 */ + divide 0x00000100, 0x0800 /* expect 0x0000 */ + divide 0x00000100, 0x0fff /* expect 0x0000 */ + divide 0x00000100, 0x1000 /* expect 0x0000 */ + divide 0x00000100, 0x1fff /* expect 0x0000 */ + divide 0x00000100, 0x2000 /* expect 0x0000 */ + divide 0x00000100, 0x3fff /* expect 0x0000 */ + divide 0x00000100, 0x4000 /* expect 0x0000 */ + divide 0x00000100, 0x7fff /* expect 0x0000 */ + divide 0x000001ff, 0x0001 /* expect 0x01ff */ + divide 0x000001ff, 0x0002 /* expect 0x00ff */ + divide 0x000001ff, 0x0003 /* expect 0x00aa */ + divide 0x000001ff, 0x0004 /* expect 0x007f */ + divide 0x000001ff, 0x0007 /* expect 0x0049 */ + divide 0x000001ff, 0x0008 /* expect 0x003f */ + divide 0x000001ff, 0x000f /* expect 0x0022 */ + divide 0x000001ff, 0x0010 /* expect 0x001f */ + divide 0x000001ff, 0x001f /* expect 0x0010 */ + divide 0x000001ff, 0x0020 /* expect 0x000f */ + divide 0x000001ff, 0x003f /* expect 0x0008 */ + divide 0x000001ff, 0x0040 /* expect 0x0007 */ + divide 0x000001ff, 0x007f /* expect 0x0004 */ + divide 0x000001ff, 0x0080 /* expect 0x0003 */ + divide 0x000001ff, 0x00ff /* expect 0x0002 */ + divide 0x000001ff, 0x0100 /* expect 0x0001 */ + divide 0x000001ff, 0x01ff /* expect 0x0001 */ + divide 0x000001ff, 0x0200 /* expect 0x0000 */ + divide 0x000001ff, 0x03ff /* expect 0x0000 */ + divide 0x000001ff, 0x0400 /* expect 0x0000 */ + divide 0x000001ff, 0x07ff /* expect 0x0000 */ + divide 0x000001ff, 0x0800 /* expect 0x0000 */ + divide 0x000001ff, 0x0fff /* expect 0x0000 */ + divide 0x000001ff, 0x1000 /* expect 0x0000 */ + divide 0x000001ff, 0x1fff /* expect 0x0000 */ + divide 0x000001ff, 0x2000 /* expect 0x0000 */ + divide 0x000001ff, 0x3fff /* expect 0x0000 */ + divide 0x000001ff, 0x4000 /* expect 0x0000 */ + divide 0x000001ff, 0x7fff /* expect 0x0000 */ + divide 0x00000200, 0x0001 /* expect 0x0200 */ + divide 0x00000200, 0x0002 /* expect 0x0100 */ + divide 0x00000200, 0x0003 /* expect 0x00aa */ + divide 0x00000200, 0x0004 /* expect 0x0080 */ + divide 0x00000200, 0x0007 /* expect 0x0049 */ + divide 0x00000200, 0x0008 /* expect 0x0040 */ + divide 0x00000200, 0x000f /* expect 0x0022 */ + divide 0x00000200, 0x0010 /* expect 0x0020 */ + divide 0x00000200, 0x001f /* expect 0x0010 */ + divide 0x00000200, 0x0020 /* expect 0x0010 */ + divide 0x00000200, 0x003f /* expect 0x0008 */ + divide 0x00000200, 0x0040 /* expect 0x0008 */ + divide 0x00000200, 0x007f /* expect 0x0004 */ + divide 0x00000200, 0x0080 /* expect 0x0004 */ + divide 0x00000200, 0x00ff /* expect 0x0002 */ + divide 0x00000200, 0x0100 /* expect 0x0002 */ + divide 0x00000200, 0x01ff /* expect 0x0001 */ + divide 0x00000200, 0x0200 /* expect 0x0001 */ + divide 0x00000200, 0x03ff /* expect 0x0000 */ + divide 0x00000200, 0x0400 /* expect 0x0000 */ + divide 0x00000200, 0x07ff /* expect 0x0000 */ + divide 0x00000200, 0x0800 /* expect 0x0000 */ + divide 0x00000200, 0x0fff /* expect 0x0000 */ + divide 0x00000200, 0x1000 /* expect 0x0000 */ + divide 0x00000200, 0x1fff /* expect 0x0000 */ + divide 0x00000200, 0x2000 /* expect 0x0000 */ + divide 0x00000200, 0x3fff /* expect 0x0000 */ + divide 0x00000200, 0x4000 /* expect 0x0000 */ + divide 0x00000200, 0x7fff /* expect 0x0000 */ + divide 0x000003ff, 0x0001 /* expect 0x03ff */ + divide 0x000003ff, 0x0002 /* expect 0x01ff */ + divide 0x000003ff, 0x0003 /* expect 0x0155 */ + divide 0x000003ff, 0x0004 /* expect 0x00ff */ + divide 0x000003ff, 0x0007 /* expect 0x0092 */ + divide 0x000003ff, 0x0008 /* expect 0x007f */ + divide 0x000003ff, 0x000f /* expect 0x0044 */ + divide 0x000003ff, 0x0010 /* expect 0x003f */ + divide 0x000003ff, 0x001f /* expect 0x0021 */ + divide 0x000003ff, 0x0020 /* expect 0x001f */ + divide 0x000003ff, 0x003f /* expect 0x0010 */ + divide 0x000003ff, 0x0040 /* expect 0x000f */ + divide 0x000003ff, 0x007f /* expect 0x0008 */ + divide 0x000003ff, 0x0080 /* expect 0x0007 */ + divide 0x000003ff, 0x00ff /* expect 0x0004 */ + divide 0x000003ff, 0x0100 /* expect 0x0003 */ + divide 0x000003ff, 0x01ff /* expect 0x0002 */ + divide 0x000003ff, 0x0200 /* expect 0x0001 */ + divide 0x000003ff, 0x03ff /* expect 0x0001 */ + divide 0x000003ff, 0x0400 /* expect 0x0000 */ + divide 0x000003ff, 0x07ff /* expect 0x0000 */ + divide 0x000003ff, 0x0800 /* expect 0x0000 */ + divide 0x000003ff, 0x0fff /* expect 0x0000 */ + divide 0x000003ff, 0x1000 /* expect 0x0000 */ + divide 0x000003ff, 0x1fff /* expect 0x0000 */ + divide 0x000003ff, 0x2000 /* expect 0x0000 */ + divide 0x000003ff, 0x3fff /* expect 0x0000 */ + divide 0x000003ff, 0x4000 /* expect 0x0000 */ + divide 0x000003ff, 0x7fff /* expect 0x0000 */ + divide 0x00000400, 0x0001 /* expect 0x0400 */ + divide 0x00000400, 0x0002 /* expect 0x0200 */ + divide 0x00000400, 0x0003 /* expect 0x0155 */ + divide 0x00000400, 0x0004 /* expect 0x0100 */ + divide 0x00000400, 0x0007 /* expect 0x0092 */ + divide 0x00000400, 0x0008 /* expect 0x0080 */ + divide 0x00000400, 0x000f /* expect 0x0044 */ + divide 0x00000400, 0x0010 /* expect 0x0040 */ + divide 0x00000400, 0x001f /* expect 0x0021 */ + divide 0x00000400, 0x0020 /* expect 0x0020 */ + divide 0x00000400, 0x003f /* expect 0x0010 */ + divide 0x00000400, 0x0040 /* expect 0x0010 */ + divide 0x00000400, 0x007f /* expect 0x0008 */ + divide 0x00000400, 0x0080 /* expect 0x0008 */ + divide 0x00000400, 0x00ff /* expect 0x0004 */ + divide 0x00000400, 0x0100 /* expect 0x0004 */ + divide 0x00000400, 0x01ff /* expect 0x0002 */ + divide 0x00000400, 0x0200 /* expect 0x0002 */ + divide 0x00000400, 0x03ff /* expect 0x0001 */ + divide 0x00000400, 0x0400 /* expect 0x0001 */ + divide 0x00000400, 0x07ff /* expect 0x0000 */ + divide 0x00000400, 0x0800 /* expect 0x0000 */ + divide 0x00000400, 0x0fff /* expect 0x0000 */ + divide 0x00000400, 0x1000 /* expect 0x0000 */ + divide 0x00000400, 0x1fff /* expect 0x0000 */ + divide 0x00000400, 0x2000 /* expect 0x0000 */ + divide 0x00000400, 0x3fff /* expect 0x0000 */ + divide 0x00000400, 0x4000 /* expect 0x0000 */ + divide 0x00000400, 0x7fff /* expect 0x0000 */ + divide 0x000007ff, 0x0001 /* expect 0x07ff */ + divide 0x000007ff, 0x0002 /* expect 0x03ff */ + divide 0x000007ff, 0x0003 /* expect 0x02aa */ + divide 0x000007ff, 0x0004 /* expect 0x01ff */ + divide 0x000007ff, 0x0007 /* expect 0x0124 */ + divide 0x000007ff, 0x0008 /* expect 0x00ff */ + divide 0x000007ff, 0x000f /* expect 0x0088 */ + divide 0x000007ff, 0x0010 /* expect 0x007f */ + divide 0x000007ff, 0x001f /* expect 0x0042 */ + divide 0x000007ff, 0x0020 /* expect 0x003f */ + divide 0x000007ff, 0x003f /* expect 0x0020 */ + divide 0x000007ff, 0x0040 /* expect 0x001f */ + divide 0x000007ff, 0x007f /* expect 0x0010 */ + divide 0x000007ff, 0x0080 /* expect 0x000f */ + divide 0x000007ff, 0x00ff /* expect 0x0008 */ + divide 0x000007ff, 0x0100 /* expect 0x0007 */ + divide 0x000007ff, 0x01ff /* expect 0x0004 */ + divide 0x000007ff, 0x0200 /* expect 0x0003 */ + divide 0x000007ff, 0x03ff /* expect 0x0002 */ + divide 0x000007ff, 0x0400 /* expect 0x0001 */ + divide 0x000007ff, 0x07ff /* expect 0x0001 */ + divide 0x000007ff, 0x0800 /* expect 0x0000 */ + divide 0x000007ff, 0x0fff /* expect 0x0000 */ + divide 0x000007ff, 0x1000 /* expect 0x0000 */ + divide 0x000007ff, 0x1fff /* expect 0x0000 */ + divide 0x000007ff, 0x2000 /* expect 0x0000 */ + divide 0x000007ff, 0x3fff /* expect 0x0000 */ + divide 0x000007ff, 0x4000 /* expect 0x0000 */ + divide 0x000007ff, 0x7fff /* expect 0x0000 */ + divide 0x00000800, 0x0001 /* expect 0x0800 */ + divide 0x00000800, 0x0002 /* expect 0x0400 */ + divide 0x00000800, 0x0003 /* expect 0x02aa */ + divide 0x00000800, 0x0004 /* expect 0x0200 */ + divide 0x00000800, 0x0007 /* expect 0x0124 */ + divide 0x00000800, 0x0008 /* expect 0x0100 */ + divide 0x00000800, 0x000f /* expect 0x0088 */ + divide 0x00000800, 0x0010 /* expect 0x0080 */ + divide 0x00000800, 0x001f /* expect 0x0042 */ + divide 0x00000800, 0x0020 /* expect 0x0040 */ + divide 0x00000800, 0x003f /* expect 0x0020 */ + divide 0x00000800, 0x0040 /* expect 0x0020 */ + divide 0x00000800, 0x007f /* expect 0x0010 */ + divide 0x00000800, 0x0080 /* expect 0x0010 */ + divide 0x00000800, 0x00ff /* expect 0x0008 */ + divide 0x00000800, 0x0100 /* expect 0x0008 */ + divide 0x00000800, 0x01ff /* expect 0x0004 */ + divide 0x00000800, 0x0200 /* expect 0x0004 */ + divide 0x00000800, 0x03ff /* expect 0x0002 */ + divide 0x00000800, 0x0400 /* expect 0x0002 */ + divide 0x00000800, 0x07ff /* expect 0x0001 */ + divide 0x00000800, 0x0800 /* expect 0x0001 */ + divide 0x00000800, 0x0fff /* expect 0x0000 */ + divide 0x00000800, 0x1000 /* expect 0x0000 */ + divide 0x00000800, 0x1fff /* expect 0x0000 */ + divide 0x00000800, 0x2000 /* expect 0x0000 */ + divide 0x00000800, 0x3fff /* expect 0x0000 */ + divide 0x00000800, 0x4000 /* expect 0x0000 */ + divide 0x00000800, 0x7fff /* expect 0x0000 */ + divide 0x00000fff, 0x0001 /* expect 0x0fff */ + divide 0x00000fff, 0x0002 /* expect 0x07ff */ + divide 0x00000fff, 0x0003 /* expect 0x0555 */ + divide 0x00000fff, 0x0004 /* expect 0x03ff */ + divide 0x00000fff, 0x0007 /* expect 0x0249 */ + divide 0x00000fff, 0x0008 /* expect 0x01ff */ + divide 0x00000fff, 0x000f /* expect 0x0111 */ + divide 0x00000fff, 0x0010 /* expect 0x00ff */ + divide 0x00000fff, 0x001f /* expect 0x0084 */ + divide 0x00000fff, 0x0020 /* expect 0x007f */ + divide 0x00000fff, 0x003f /* expect 0x0041 */ + divide 0x00000fff, 0x0040 /* expect 0x003f */ + divide 0x00000fff, 0x007f /* expect 0x0020 */ + divide 0x00000fff, 0x0080 /* expect 0x001f */ + divide 0x00000fff, 0x00ff /* expect 0x0010 */ + divide 0x00000fff, 0x0100 /* expect 0x000f */ + divide 0x00000fff, 0x01ff /* expect 0x0008 */ + divide 0x00000fff, 0x0200 /* expect 0x0007 */ + divide 0x00000fff, 0x03ff /* expect 0x0004 */ + divide 0x00000fff, 0x0400 /* expect 0x0003 */ + divide 0x00000fff, 0x07ff /* expect 0x0002 */ + divide 0x00000fff, 0x0800 /* expect 0x0001 */ + divide 0x00000fff, 0x0fff /* expect 0x0001 */ + divide 0x00000fff, 0x1000 /* expect 0x0000 */ + divide 0x00000fff, 0x1fff /* expect 0x0000 */ + divide 0x00000fff, 0x2000 /* expect 0x0000 */ + divide 0x00000fff, 0x3fff /* expect 0x0000 */ + divide 0x00000fff, 0x4000 /* expect 0x0000 */ + divide 0x00000fff, 0x7fff /* expect 0x0000 */ + divide 0x00001000, 0x0001 /* expect 0x1000 */ + divide 0x00001000, 0x0002 /* expect 0x0800 */ + divide 0x00001000, 0x0003 /* expect 0x0555 */ + divide 0x00001000, 0x0004 /* expect 0x0400 */ + divide 0x00001000, 0x0007 /* expect 0x0249 */ + divide 0x00001000, 0x0008 /* expect 0x0200 */ + divide 0x00001000, 0x000f /* expect 0x0111 */ + divide 0x00001000, 0x0010 /* expect 0x0100 */ + divide 0x00001000, 0x001f /* expect 0x0084 */ + divide 0x00001000, 0x0020 /* expect 0x0080 */ + divide 0x00001000, 0x003f /* expect 0x0041 */ + divide 0x00001000, 0x0040 /* expect 0x0040 */ + divide 0x00001000, 0x007f /* expect 0x0020 */ + divide 0x00001000, 0x0080 /* expect 0x0020 */ + divide 0x00001000, 0x00ff /* expect 0x0010 */ + divide 0x00001000, 0x0100 /* expect 0x0010 */ + divide 0x00001000, 0x01ff /* expect 0x0008 */ + divide 0x00001000, 0x0200 /* expect 0x0008 */ + divide 0x00001000, 0x03ff /* expect 0x0004 */ + divide 0x00001000, 0x0400 /* expect 0x0004 */ + divide 0x00001000, 0x07ff /* expect 0x0002 */ + divide 0x00001000, 0x0800 /* expect 0x0002 */ + divide 0x00001000, 0x0fff /* expect 0x0001 */ + divide 0x00001000, 0x1000 /* expect 0x0001 */ + divide 0x00001000, 0x1fff /* expect 0x0000 */ + divide 0x00001000, 0x2000 /* expect 0x0000 */ + divide 0x00001000, 0x3fff /* expect 0x0000 */ + divide 0x00001000, 0x4000 /* expect 0x0000 */ + divide 0x00001000, 0x7fff /* expect 0x0000 */ + divide 0x00001fff, 0x0001 /* expect 0x1fff */ + divide 0x00001fff, 0x0002 /* expect 0x0fff */ + divide 0x00001fff, 0x0003 /* expect 0x0aaa */ + divide 0x00001fff, 0x0004 /* expect 0x07ff */ + divide 0x00001fff, 0x0007 /* expect 0x0492 */ + divide 0x00001fff, 0x0008 /* expect 0x03ff */ + divide 0x00001fff, 0x000f /* expect 0x0222 */ + divide 0x00001fff, 0x0010 /* expect 0x01ff */ + divide 0x00001fff, 0x001f /* expect 0x0108 */ + divide 0x00001fff, 0x0020 /* expect 0x00ff */ + divide 0x00001fff, 0x003f /* expect 0x0082 */ + divide 0x00001fff, 0x0040 /* expect 0x007f */ + divide 0x00001fff, 0x007f /* expect 0x0040 */ + divide 0x00001fff, 0x0080 /* expect 0x003f */ + divide 0x00001fff, 0x00ff /* expect 0x0020 */ + divide 0x00001fff, 0x0100 /* expect 0x001f */ + divide 0x00001fff, 0x01ff /* expect 0x0010 */ + divide 0x00001fff, 0x0200 /* expect 0x000f */ + divide 0x00001fff, 0x03ff /* expect 0x0008 */ + divide 0x00001fff, 0x0400 /* expect 0x0007 */ + divide 0x00001fff, 0x07ff /* expect 0x0004 */ + divide 0x00001fff, 0x0800 /* expect 0x0003 */ + divide 0x00001fff, 0x0fff /* expect 0x0002 */ + divide 0x00001fff, 0x1000 /* expect 0x0001 */ + divide 0x00001fff, 0x1fff /* expect 0x0001 */ + divide 0x00001fff, 0x2000 /* expect 0x0000 */ + divide 0x00001fff, 0x3fff /* expect 0x0000 */ + divide 0x00001fff, 0x4000 /* expect 0x0000 */ + divide 0x00001fff, 0x7fff /* expect 0x0000 */ + divide 0x00002000, 0x0001 /* expect 0x2000 */ + divide 0x00002000, 0x0002 /* expect 0x1000 */ + divide 0x00002000, 0x0003 /* expect 0x0aaa */ + divide 0x00002000, 0x0004 /* expect 0x0800 */ + divide 0x00002000, 0x0007 /* expect 0x0492 */ + divide 0x00002000, 0x0008 /* expect 0x0400 */ + divide 0x00002000, 0x000f /* expect 0x0222 */ + divide 0x00002000, 0x0010 /* expect 0x0200 */ + divide 0x00002000, 0x001f /* expect 0x0108 */ + divide 0x00002000, 0x0020 /* expect 0x0100 */ + divide 0x00002000, 0x003f /* expect 0x0082 */ + divide 0x00002000, 0x0040 /* expect 0x0080 */ + divide 0x00002000, 0x007f /* expect 0x0040 */ + divide 0x00002000, 0x0080 /* expect 0x0040 */ + divide 0x00002000, 0x00ff /* expect 0x0020 */ + divide 0x00002000, 0x0100 /* expect 0x0020 */ + divide 0x00002000, 0x01ff /* expect 0x0010 */ + divide 0x00002000, 0x0200 /* expect 0x0010 */ + divide 0x00002000, 0x03ff /* expect 0x0008 */ + divide 0x00002000, 0x0400 /* expect 0x0008 */ + divide 0x00002000, 0x07ff /* expect 0x0004 */ + divide 0x00002000, 0x0800 /* expect 0x0004 */ + divide 0x00002000, 0x0fff /* expect 0x0002 */ + divide 0x00002000, 0x1000 /* expect 0x0002 */ + divide 0x00002000, 0x1fff /* expect 0x0001 */ + divide 0x00002000, 0x2000 /* expect 0x0001 */ + divide 0x00002000, 0x3fff /* expect 0x0000 */ + divide 0x00002000, 0x4000 /* expect 0x0000 */ + divide 0x00002000, 0x7fff /* expect 0x0000 */ + divide 0x00003fff, 0x0001 /* expect 0x3fff */ + divide 0x00003fff, 0x0002 /* expect 0x1fff */ + divide 0x00003fff, 0x0003 /* expect 0x1555 */ + divide 0x00003fff, 0x0004 /* expect 0x0fff */ + divide 0x00003fff, 0x0007 /* expect 0x0924 */ + divide 0x00003fff, 0x0008 /* expect 0x07ff */ + divide 0x00003fff, 0x000f /* expect 0x0444 */ + divide 0x00003fff, 0x0010 /* expect 0x03ff */ + divide 0x00003fff, 0x001f /* expect 0x0210 */ + divide 0x00003fff, 0x0020 /* expect 0x01ff */ + divide 0x00003fff, 0x003f /* expect 0x0104 */ + divide 0x00003fff, 0x0040 /* expect 0x00ff */ + divide 0x00003fff, 0x007f /* expect 0x0081 */ + divide 0x00003fff, 0x0080 /* expect 0x007f */ + divide 0x00003fff, 0x00ff /* expect 0x0040 */ + divide 0x00003fff, 0x0100 /* expect 0x003f */ + divide 0x00003fff, 0x01ff /* expect 0x0020 */ + divide 0x00003fff, 0x0200 /* expect 0x001f */ + divide 0x00003fff, 0x03ff /* expect 0x0010 */ + divide 0x00003fff, 0x0400 /* expect 0x000f */ + divide 0x00003fff, 0x07ff /* expect 0x0008 */ + divide 0x00003fff, 0x0800 /* expect 0x0007 */ + divide 0x00003fff, 0x0fff /* expect 0x0004 */ + divide 0x00003fff, 0x1000 /* expect 0x0003 */ + divide 0x00003fff, 0x1fff /* expect 0x0002 */ + divide 0x00003fff, 0x2000 /* expect 0x0001 */ + divide 0x00003fff, 0x3fff /* expect 0x0001 */ + divide 0x00003fff, 0x4000 /* expect 0x0000 */ + divide 0x00003fff, 0x7fff /* expect 0x0000 */ + divide 0x00004000, 0x0001 /* expect 0x4000 */ + divide 0x00004000, 0x0002 /* expect 0x2000 */ + divide 0x00004000, 0x0003 /* expect 0x1555 */ + divide 0x00004000, 0x0004 /* expect 0x1000 */ + divide 0x00004000, 0x0007 /* expect 0x0924 */ + divide 0x00004000, 0x0008 /* expect 0x0800 */ + divide 0x00004000, 0x000f /* expect 0x0444 */ + divide 0x00004000, 0x0010 /* expect 0x0400 */ + divide 0x00004000, 0x001f /* expect 0x0210 */ + divide 0x00004000, 0x0020 /* expect 0x0200 */ + divide 0x00004000, 0x003f /* expect 0x0104 */ + divide 0x00004000, 0x0040 /* expect 0x0100 */ + divide 0x00004000, 0x007f /* expect 0x0081 */ + divide 0x00004000, 0x0080 /* expect 0x0080 */ + divide 0x00004000, 0x00ff /* expect 0x0040 */ + divide 0x00004000, 0x0100 /* expect 0x0040 */ + divide 0x00004000, 0x01ff /* expect 0x0020 */ + divide 0x00004000, 0x0200 /* expect 0x0020 */ + divide 0x00004000, 0x03ff /* expect 0x0010 */ + divide 0x00004000, 0x0400 /* expect 0x0010 */ + divide 0x00004000, 0x07ff /* expect 0x0008 */ + divide 0x00004000, 0x0800 /* expect 0x0008 */ + divide 0x00004000, 0x0fff /* expect 0x0004 */ + divide 0x00004000, 0x1000 /* expect 0x0004 */ + divide 0x00004000, 0x1fff /* expect 0x0002 */ + divide 0x00004000, 0x2000 /* expect 0x0002 */ + divide 0x00004000, 0x3fff /* expect 0x0001 */ + divide 0x00004000, 0x4000 /* expect 0x0001 */ + divide 0x00004000, 0x7fff /* expect 0x0000 */ + divide 0x00007fff, 0x0001 /* expect 0x7fff */ + divide 0x00007fff, 0x0002 /* expect 0x3fff */ + divide 0x00007fff, 0x0003 /* expect 0x2aaa */ + divide 0x00007fff, 0x0004 /* expect 0x1fff */ + divide 0x00007fff, 0x0007 /* expect 0x1249 */ + divide 0x00007fff, 0x0008 /* expect 0x0fff */ + divide 0x00007fff, 0x000f /* expect 0x0888 */ + divide 0x00007fff, 0x0010 /* expect 0x07ff */ + divide 0x00007fff, 0x001f /* expect 0x0421 */ + divide 0x00007fff, 0x0020 /* expect 0x03ff */ + divide 0x00007fff, 0x003f /* expect 0x0208 */ + divide 0x00007fff, 0x0040 /* expect 0x01ff */ + divide 0x00007fff, 0x007f /* expect 0x0102 */ + divide 0x00007fff, 0x0080 /* expect 0x00ff */ + divide 0x00007fff, 0x00ff /* expect 0x0080 */ + divide 0x00007fff, 0x0100 /* expect 0x007f */ + divide 0x00007fff, 0x01ff /* expect 0x0040 */ + divide 0x00007fff, 0x0200 /* expect 0x003f */ + divide 0x00007fff, 0x03ff /* expect 0x0020 */ + divide 0x00007fff, 0x0400 /* expect 0x001f */ + divide 0x00007fff, 0x07ff /* expect 0x0010 */ + divide 0x00007fff, 0x0800 /* expect 0x000f */ + divide 0x00007fff, 0x0fff /* expect 0x0008 */ + divide 0x00007fff, 0x1000 /* expect 0x0007 */ + divide 0x00007fff, 0x1fff /* expect 0x0004 */ + divide 0x00007fff, 0x2000 /* expect 0x0003 */ + divide 0x00007fff, 0x3fff /* expect 0x0002 */ + divide 0x00007fff, 0x4000 /* expect 0x0001 */ + divide 0x00007fff, 0x7fff /* expect 0x0001 */ + divide 0x00008000, 0x0002 /* expect 0x4000 */ + divide 0x00008000, 0x0003 /* expect 0x2aaa */ + divide 0x00008000, 0x0004 /* expect 0x2000 */ + divide 0x00008000, 0x0007 /* expect 0x1249 */ + divide 0x00008000, 0x0008 /* expect 0x1000 */ + divide 0x00008000, 0x000f /* expect 0x0888 */ + divide 0x00008000, 0x0010 /* expect 0x0800 */ + divide 0x00008000, 0x001f /* expect 0x0421 */ + divide 0x00008000, 0x0020 /* expect 0x0400 */ + divide 0x00008000, 0x003f /* expect 0x0208 */ + divide 0x00008000, 0x0040 /* expect 0x0200 */ + divide 0x00008000, 0x007f /* expect 0x0102 */ + divide 0x00008000, 0x0080 /* expect 0x0100 */ + divide 0x00008000, 0x00ff /* expect 0x0080 */ + divide 0x00008000, 0x0100 /* expect 0x0080 */ + divide 0x00008000, 0x01ff /* expect 0x0040 */ + divide 0x00008000, 0x0200 /* expect 0x0040 */ + divide 0x00008000, 0x03ff /* expect 0x0020 */ + divide 0x00008000, 0x0400 /* expect 0x0020 */ + divide 0x00008000, 0x07ff /* expect 0x0010 */ + divide 0x00008000, 0x0800 /* expect 0x0010 */ + divide 0x00008000, 0x0fff /* expect 0x0008 */ + divide 0x00008000, 0x1000 /* expect 0x0008 */ + divide 0x00008000, 0x1fff /* expect 0x0004 */ + divide 0x00008000, 0x2000 /* expect 0x0004 */ + divide 0x00008000, 0x3fff /* expect 0x0002 */ + divide 0x00008000, 0x4000 /* expect 0x0002 */ + divide 0x00008000, 0x7fff /* expect 0x0001 */ + divide 0x0000ffff, 0x0002 /* expect 0x7fff */ + divide 0x0000ffff, 0x0003 /* expect 0x5555 */ + divide 0x0000ffff, 0x0004 /* expect 0x3fff */ + divide 0x0000ffff, 0x0007 /* expect 0x2492 */ + divide 0x0000ffff, 0x0008 /* expect 0x1fff */ + divide 0x0000ffff, 0x000f /* expect 0x1111 */ + divide 0x0000ffff, 0x0010 /* expect 0x0fff */ + divide 0x0000ffff, 0x001f /* expect 0x0842 */ + divide 0x0000ffff, 0x0020 /* expect 0x07ff */ + divide 0x0000ffff, 0x003f /* expect 0x0410 */ + divide 0x0000ffff, 0x0040 /* expect 0x03ff */ + divide 0x0000ffff, 0x007f /* expect 0x0204 */ + divide 0x0000ffff, 0x0080 /* expect 0x01ff */ + divide 0x0000ffff, 0x00ff /* expect 0x0101 */ + divide 0x0000ffff, 0x0100 /* expect 0x00ff */ + divide 0x0000ffff, 0x01ff /* expect 0x0080 */ + divide 0x0000ffff, 0x0200 /* expect 0x007f */ + divide 0x0000ffff, 0x03ff /* expect 0x0040 */ + divide 0x0000ffff, 0x0400 /* expect 0x003f */ + divide 0x0000ffff, 0x07ff /* expect 0x0020 */ + divide 0x0000ffff, 0x0800 /* expect 0x001f */ + divide 0x0000ffff, 0x0fff /* expect 0x0010 */ + divide 0x0000ffff, 0x1000 /* expect 0x000f */ + divide 0x0000ffff, 0x1fff /* expect 0x0008 */ + divide 0x0000ffff, 0x2000 /* expect 0x0007 */ + divide 0x0000ffff, 0x3fff /* expect 0x0004 */ + divide 0x0000ffff, 0x4000 /* expect 0x0003 */ + divide 0x0000ffff, 0x7fff /* expect 0x0002 */ + divide 0x00010000, 0x0003 /* expect 0x5555 */ + divide 0x00010000, 0x0004 /* expect 0x4000 */ + divide 0x00010000, 0x0007 /* expect 0x2492 */ + divide 0x00010000, 0x0008 /* expect 0x2000 */ + divide 0x00010000, 0x000f /* expect 0x1111 */ + divide 0x00010000, 0x0010 /* expect 0x1000 */ + divide 0x00010000, 0x001f /* expect 0x0842 */ + divide 0x00010000, 0x0020 /* expect 0x0800 */ + divide 0x00010000, 0x003f /* expect 0x0410 */ + divide 0x00010000, 0x0040 /* expect 0x0400 */ + divide 0x00010000, 0x007f /* expect 0x0204 */ + divide 0x00010000, 0x0080 /* expect 0x0200 */ + divide 0x00010000, 0x00ff /* expect 0x0101 */ + divide 0x00010000, 0x0100 /* expect 0x0100 */ + divide 0x00010000, 0x01ff /* expect 0x0080 */ + divide 0x00010000, 0x0200 /* expect 0x0080 */ + divide 0x00010000, 0x03ff /* expect 0x0040 */ + divide 0x00010000, 0x0400 /* expect 0x0040 */ + divide 0x00010000, 0x07ff /* expect 0x0020 */ + divide 0x00010000, 0x0800 /* expect 0x0020 */ + divide 0x00010000, 0x0fff /* expect 0x0010 */ + divide 0x00010000, 0x1000 /* expect 0x0010 */ + divide 0x00010000, 0x1fff /* expect 0x0008 */ + divide 0x00010000, 0x2000 /* expect 0x0008 */ + divide 0x00010000, 0x3fff /* expect 0x0004 */ + divide 0x00010000, 0x4000 /* expect 0x0004 */ + divide 0x00010000, 0x7fff /* expect 0x0002 */ + divide 0x0001ffff, 0x0004 /* expect 0x7fff */ + divide 0x0001ffff, 0x0007 /* expect 0x4924 */ + divide 0x0001ffff, 0x0008 /* expect 0x3fff */ + divide 0x0001ffff, 0x000f /* expect 0x2222 */ + divide 0x0001ffff, 0x0010 /* expect 0x1fff */ + divide 0x0001ffff, 0x001f /* expect 0x1084 */ + divide 0x0001ffff, 0x0020 /* expect 0x0fff */ + divide 0x0001ffff, 0x003f /* expect 0x0820 */ + divide 0x0001ffff, 0x0040 /* expect 0x07ff */ + divide 0x0001ffff, 0x007f /* expect 0x0408 */ + divide 0x0001ffff, 0x0080 /* expect 0x03ff */ + divide 0x0001ffff, 0x00ff /* expect 0x0202 */ + divide 0x0001ffff, 0x0100 /* expect 0x01ff */ + divide 0x0001ffff, 0x01ff /* expect 0x0100 */ + divide 0x0001ffff, 0x0200 /* expect 0x00ff */ + divide 0x0001ffff, 0x03ff /* expect 0x0080 */ + divide 0x0001ffff, 0x0400 /* expect 0x007f */ + divide 0x0001ffff, 0x07ff /* expect 0x0040 */ + divide 0x0001ffff, 0x0800 /* expect 0x003f */ + divide 0x0001ffff, 0x0fff /* expect 0x0020 */ + divide 0x0001ffff, 0x1000 /* expect 0x001f */ + divide 0x0001ffff, 0x1fff /* expect 0x0010 */ + divide 0x0001ffff, 0x2000 /* expect 0x000f */ + divide 0x0001ffff, 0x3fff /* expect 0x0008 */ + divide 0x0001ffff, 0x4000 /* expect 0x0007 */ + divide 0x0001ffff, 0x7fff /* expect 0x0004 */ + divide 0x00020000, 0x0007 /* expect 0x4924 */ + divide 0x00020000, 0x0008 /* expect 0x4000 */ + divide 0x00020000, 0x000f /* expect 0x2222 */ + divide 0x00020000, 0x0010 /* expect 0x2000 */ + divide 0x00020000, 0x001f /* expect 0x1084 */ + divide 0x00020000, 0x0020 /* expect 0x1000 */ + divide 0x00020000, 0x003f /* expect 0x0820 */ + divide 0x00020000, 0x0040 /* expect 0x0800 */ + divide 0x00020000, 0x007f /* expect 0x0408 */ + divide 0x00020000, 0x0080 /* expect 0x0400 */ + divide 0x00020000, 0x00ff /* expect 0x0202 */ + divide 0x00020000, 0x0100 /* expect 0x0200 */ + divide 0x00020000, 0x01ff /* expect 0x0100 */ + divide 0x00020000, 0x0200 /* expect 0x0100 */ + divide 0x00020000, 0x03ff /* expect 0x0080 */ + divide 0x00020000, 0x0400 /* expect 0x0080 */ + divide 0x00020000, 0x07ff /* expect 0x0040 */ + divide 0x00020000, 0x0800 /* expect 0x0040 */ + divide 0x00020000, 0x0fff /* expect 0x0020 */ + divide 0x00020000, 0x1000 /* expect 0x0020 */ + divide 0x00020000, 0x1fff /* expect 0x0010 */ + divide 0x00020000, 0x2000 /* expect 0x0010 */ + divide 0x00020000, 0x3fff /* expect 0x0008 */ + divide 0x00020000, 0x4000 /* expect 0x0008 */ + divide 0x00020000, 0x7fff /* expect 0x0004 */ + divide 0x0003ffff, 0x0008 /* expect 0x7fff */ + divide 0x0003ffff, 0x000f /* expect 0x4444 */ + divide 0x0003ffff, 0x0010 /* expect 0x3fff */ + divide 0x0003ffff, 0x001f /* expect 0x2108 */ + divide 0x0003ffff, 0x0020 /* expect 0x1fff */ + divide 0x0003ffff, 0x003f /* expect 0x1041 */ + divide 0x0003ffff, 0x0040 /* expect 0x0fff */ + divide 0x0003ffff, 0x007f /* expect 0x0810 */ + divide 0x0003ffff, 0x0080 /* expect 0x07ff */ + divide 0x0003ffff, 0x00ff /* expect 0x0404 */ + divide 0x0003ffff, 0x0100 /* expect 0x03ff */ + divide 0x0003ffff, 0x01ff /* expect 0x0201 */ + divide 0x0003ffff, 0x0200 /* expect 0x01ff */ + divide 0x0003ffff, 0x03ff /* expect 0x0100 */ + divide 0x0003ffff, 0x0400 /* expect 0x00ff */ + divide 0x0003ffff, 0x07ff /* expect 0x0080 */ + divide 0x0003ffff, 0x0800 /* expect 0x007f */ + divide 0x0003ffff, 0x0fff /* expect 0x0040 */ + divide 0x0003ffff, 0x1000 /* expect 0x003f */ + divide 0x0003ffff, 0x1fff /* expect 0x0020 */ + divide 0x0003ffff, 0x2000 /* expect 0x001f */ + divide 0x0003ffff, 0x3fff /* expect 0x0010 */ + divide 0x0003ffff, 0x4000 /* expect 0x000f */ + divide 0x0003ffff, 0x7fff /* expect 0x0008 */ + divide 0x00040000, 0x000f /* expect 0x4444 */ + divide 0x00040000, 0x0010 /* expect 0x4000 */ + divide 0x00040000, 0x001f /* expect 0x2108 */ + divide 0x00040000, 0x0020 /* expect 0x2000 */ + divide 0x00040000, 0x003f /* expect 0x1041 */ + divide 0x00040000, 0x0040 /* expect 0x1000 */ + divide 0x00040000, 0x007f /* expect 0x0810 */ + divide 0x00040000, 0x0080 /* expect 0x0800 */ + divide 0x00040000, 0x00ff /* expect 0x0404 */ + divide 0x00040000, 0x0100 /* expect 0x0400 */ + divide 0x00040000, 0x01ff /* expect 0x0201 */ + divide 0x00040000, 0x0200 /* expect 0x0200 */ + divide 0x00040000, 0x03ff /* expect 0x0100 */ + divide 0x00040000, 0x0400 /* expect 0x0100 */ + divide 0x00040000, 0x07ff /* expect 0x0080 */ + divide 0x00040000, 0x0800 /* expect 0x0080 */ + divide 0x00040000, 0x0fff /* expect 0x0040 */ + divide 0x00040000, 0x1000 /* expect 0x0040 */ + divide 0x00040000, 0x1fff /* expect 0x0020 */ + divide 0x00040000, 0x2000 /* expect 0x0020 */ + divide 0x00040000, 0x3fff /* expect 0x0010 */ + divide 0x00040000, 0x4000 /* expect 0x0010 */ + divide 0x00040000, 0x7fff /* expect 0x0008 */ + divide 0x0007ffff, 0x0010 /* expect 0x7fff */ + divide 0x0007ffff, 0x001f /* expect 0x4210 */ + divide 0x0007ffff, 0x0020 /* expect 0x3fff */ + divide 0x0007ffff, 0x003f /* expect 0x2082 */ + divide 0x0007ffff, 0x0040 /* expect 0x1fff */ + divide 0x0007ffff, 0x007f /* expect 0x1020 */ + divide 0x0007ffff, 0x0080 /* expect 0x0fff */ + divide 0x0007ffff, 0x00ff /* expect 0x0808 */ + divide 0x0007ffff, 0x0100 /* expect 0x07ff */ + divide 0x0007ffff, 0x01ff /* expect 0x0402 */ + divide 0x0007ffff, 0x0200 /* expect 0x03ff */ + divide 0x0007ffff, 0x03ff /* expect 0x0200 */ + divide 0x0007ffff, 0x0400 /* expect 0x01ff */ + divide 0x0007ffff, 0x07ff /* expect 0x0100 */ + divide 0x0007ffff, 0x0800 /* expect 0x00ff */ + divide 0x0007ffff, 0x0fff /* expect 0x0080 */ + divide 0x0007ffff, 0x1000 /* expect 0x007f */ + divide 0x0007ffff, 0x1fff /* expect 0x0040 */ + divide 0x0007ffff, 0x2000 /* expect 0x003f */ + divide 0x0007ffff, 0x3fff /* expect 0x0020 */ + divide 0x0007ffff, 0x4000 /* expect 0x001f */ + divide 0x0007ffff, 0x7fff /* expect 0x0010 */ + divide 0x00080000, 0x001f /* expect 0x4210 */ + divide 0x00080000, 0x0020 /* expect 0x4000 */ + divide 0x00080000, 0x003f /* expect 0x2082 */ + divide 0x00080000, 0x0040 /* expect 0x2000 */ + divide 0x00080000, 0x007f /* expect 0x1020 */ + divide 0x00080000, 0x0080 /* expect 0x1000 */ + divide 0x00080000, 0x00ff /* expect 0x0808 */ + divide 0x00080000, 0x0100 /* expect 0x0800 */ + divide 0x00080000, 0x01ff /* expect 0x0402 */ + divide 0x00080000, 0x0200 /* expect 0x0400 */ + divide 0x00080000, 0x03ff /* expect 0x0200 */ + divide 0x00080000, 0x0400 /* expect 0x0200 */ + divide 0x00080000, 0x07ff /* expect 0x0100 */ + divide 0x00080000, 0x0800 /* expect 0x0100 */ + divide 0x00080000, 0x0fff /* expect 0x0080 */ + divide 0x00080000, 0x1000 /* expect 0x0080 */ + divide 0x00080000, 0x1fff /* expect 0x0040 */ + divide 0x00080000, 0x2000 /* expect 0x0040 */ + divide 0x00080000, 0x3fff /* expect 0x0020 */ + divide 0x00080000, 0x4000 /* expect 0x0020 */ + divide 0x00080000, 0x7fff /* expect 0x0010 */ + divide 0x000fffff, 0x0020 /* expect 0x7fff */ + divide 0x000fffff, 0x003f /* expect 0x4104 */ + divide 0x000fffff, 0x0040 /* expect 0x3fff */ + divide 0x000fffff, 0x007f /* expect 0x2040 */ + divide 0x000fffff, 0x0080 /* expect 0x1fff */ + divide 0x000fffff, 0x00ff /* expect 0x1010 */ + divide 0x000fffff, 0x0100 /* expect 0x0fff */ + divide 0x000fffff, 0x01ff /* expect 0x0804 */ + divide 0x000fffff, 0x0200 /* expect 0x07ff */ + divide 0x000fffff, 0x03ff /* expect 0x0401 */ + divide 0x000fffff, 0x0400 /* expect 0x03ff */ + divide 0x000fffff, 0x07ff /* expect 0x0200 */ + divide 0x000fffff, 0x0800 /* expect 0x01ff */ + divide 0x000fffff, 0x0fff /* expect 0x0100 */ + divide 0x000fffff, 0x1000 /* expect 0x00ff */ + divide 0x000fffff, 0x1fff /* expect 0x0080 */ + divide 0x000fffff, 0x2000 /* expect 0x007f */ + divide 0x000fffff, 0x3fff /* expect 0x0040 */ + divide 0x000fffff, 0x4000 /* expect 0x003f */ + divide 0x000fffff, 0x7fff /* expect 0x0020 */ + divide 0x00100000, 0x003f /* expect 0x4104 */ + divide 0x00100000, 0x0040 /* expect 0x4000 */ + divide 0x00100000, 0x007f /* expect 0x2040 */ + divide 0x00100000, 0x0080 /* expect 0x2000 */ + divide 0x00100000, 0x00ff /* expect 0x1010 */ + divide 0x00100000, 0x0100 /* expect 0x1000 */ + divide 0x00100000, 0x01ff /* expect 0x0804 */ + divide 0x00100000, 0x0200 /* expect 0x0800 */ + divide 0x00100000, 0x03ff /* expect 0x0401 */ + divide 0x00100000, 0x0400 /* expect 0x0400 */ + divide 0x00100000, 0x07ff /* expect 0x0200 */ + divide 0x00100000, 0x0800 /* expect 0x0200 */ + divide 0x00100000, 0x0fff /* expect 0x0100 */ + divide 0x00100000, 0x1000 /* expect 0x0100 */ + divide 0x00100000, 0x1fff /* expect 0x0080 */ + divide 0x00100000, 0x2000 /* expect 0x0080 */ + divide 0x00100000, 0x3fff /* expect 0x0040 */ + divide 0x00100000, 0x4000 /* expect 0x0040 */ + divide 0x00100000, 0x7fff /* expect 0x0020 */ + divide 0x001fffff, 0x0040 /* expect 0x7fff */ + divide 0x001fffff, 0x007f /* expect 0x4081 */ + divide 0x001fffff, 0x0080 /* expect 0x3fff */ + divide 0x001fffff, 0x00ff /* expect 0x2020 */ + divide 0x001fffff, 0x0100 /* expect 0x1fff */ + divide 0x001fffff, 0x01ff /* expect 0x1008 */ + divide 0x001fffff, 0x0200 /* expect 0x0fff */ + divide 0x001fffff, 0x03ff /* expect 0x0802 */ + divide 0x001fffff, 0x0400 /* expect 0x07ff */ + divide 0x001fffff, 0x07ff /* expect 0x0400 */ + divide 0x001fffff, 0x0800 /* expect 0x03ff */ + divide 0x001fffff, 0x0fff /* expect 0x0200 */ + divide 0x001fffff, 0x1000 /* expect 0x01ff */ + divide 0x001fffff, 0x1fff /* expect 0x0100 */ + divide 0x001fffff, 0x2000 /* expect 0x00ff */ + divide 0x001fffff, 0x3fff /* expect 0x0080 */ + divide 0x001fffff, 0x4000 /* expect 0x007f */ + divide 0x001fffff, 0x7fff /* expect 0x0040 */ + divide 0x00200000, 0x007f /* expect 0x4081 */ + divide 0x00200000, 0x0080 /* expect 0x4000 */ + divide 0x00200000, 0x00ff /* expect 0x2020 */ + divide 0x00200000, 0x0100 /* expect 0x2000 */ + divide 0x00200000, 0x01ff /* expect 0x1008 */ + divide 0x00200000, 0x0200 /* expect 0x1000 */ + divide 0x00200000, 0x03ff /* expect 0x0802 */ + divide 0x00200000, 0x0400 /* expect 0x0800 */ + divide 0x00200000, 0x07ff /* expect 0x0400 */ + divide 0x00200000, 0x0800 /* expect 0x0400 */ + divide 0x00200000, 0x0fff /* expect 0x0200 */ + divide 0x00200000, 0x1000 /* expect 0x0200 */ + divide 0x00200000, 0x1fff /* expect 0x0100 */ + divide 0x00200000, 0x2000 /* expect 0x0100 */ + divide 0x00200000, 0x3fff /* expect 0x0080 */ + divide 0x00200000, 0x4000 /* expect 0x0080 */ + divide 0x00200000, 0x7fff /* expect 0x0040 */ + divide 0x003fffff, 0x0080 /* expect 0x7fff */ + divide 0x003fffff, 0x00ff /* expect 0x4040 */ + divide 0x003fffff, 0x0100 /* expect 0x3fff */ + divide 0x003fffff, 0x01ff /* expect 0x2010 */ + divide 0x003fffff, 0x0200 /* expect 0x1fff */ + divide 0x003fffff, 0x03ff /* expect 0x1004 */ + divide 0x003fffff, 0x0400 /* expect 0x0fff */ + divide 0x003fffff, 0x07ff /* expect 0x0801 */ + divide 0x003fffff, 0x0800 /* expect 0x07ff */ + divide 0x003fffff, 0x0fff /* expect 0x0400 */ + divide 0x003fffff, 0x1000 /* expect 0x03ff */ + divide 0x003fffff, 0x1fff /* expect 0x0200 */ + divide 0x003fffff, 0x2000 /* expect 0x01ff */ + divide 0x003fffff, 0x3fff /* expect 0x0100 */ + divide 0x003fffff, 0x4000 /* expect 0x00ff */ + divide 0x003fffff, 0x7fff /* expect 0x0080 */ + divide 0x00400000, 0x00ff /* expect 0x4040 */ + divide 0x00400000, 0x0100 /* expect 0x4000 */ + divide 0x00400000, 0x01ff /* expect 0x2010 */ + divide 0x00400000, 0x0200 /* expect 0x2000 */ + divide 0x00400000, 0x03ff /* expect 0x1004 */ + divide 0x00400000, 0x0400 /* expect 0x1000 */ + divide 0x00400000, 0x07ff /* expect 0x0801 */ + divide 0x00400000, 0x0800 /* expect 0x0800 */ + divide 0x00400000, 0x0fff /* expect 0x0400 */ + divide 0x00400000, 0x1000 /* expect 0x0400 */ + divide 0x00400000, 0x1fff /* expect 0x0200 */ + divide 0x00400000, 0x2000 /* expect 0x0200 */ + divide 0x00400000, 0x3fff /* expect 0x0100 */ + divide 0x00400000, 0x4000 /* expect 0x0100 */ + divide 0x00400000, 0x7fff /* expect 0x0080 */ + divide 0x007fffff, 0x0100 /* expect 0x7fff */ + divide 0x007fffff, 0x01ff /* expect 0x4020 */ + divide 0x007fffff, 0x0200 /* expect 0x3fff */ + divide 0x007fffff, 0x03ff /* expect 0x2008 */ + divide 0x007fffff, 0x0400 /* expect 0x1fff */ + divide 0x007fffff, 0x07ff /* expect 0x1002 */ + divide 0x007fffff, 0x0800 /* expect 0x0fff */ + divide 0x007fffff, 0x0fff /* expect 0x0800 */ + divide 0x007fffff, 0x1000 /* expect 0x07ff */ + divide 0x007fffff, 0x1fff /* expect 0x0400 */ + divide 0x007fffff, 0x2000 /* expect 0x03ff */ + divide 0x007fffff, 0x3fff /* expect 0x0200 */ + divide 0x007fffff, 0x4000 /* expect 0x01ff */ + divide 0x007fffff, 0x7fff /* expect 0x0100 */ + divide 0x00800000, 0x01ff /* expect 0x4020 */ + divide 0x00800000, 0x0200 /* expect 0x4000 */ + divide 0x00800000, 0x03ff /* expect 0x2008 */ + divide 0x00800000, 0x0400 /* expect 0x2000 */ + divide 0x00800000, 0x07ff /* expect 0x1002 */ + divide 0x00800000, 0x0800 /* expect 0x1000 */ + divide 0x00800000, 0x0fff /* expect 0x0800 */ + divide 0x00800000, 0x1000 /* expect 0x0800 */ + divide 0x00800000, 0x1fff /* expect 0x0400 */ + divide 0x00800000, 0x2000 /* expect 0x0400 */ + divide 0x00800000, 0x3fff /* expect 0x0200 */ + divide 0x00800000, 0x4000 /* expect 0x0200 */ + divide 0x00800000, 0x7fff /* expect 0x0100 */ + divide 0x00ffffff, 0x0200 /* expect 0x7fff */ + divide 0x00ffffff, 0x03ff /* expect 0x4010 */ + divide 0x00ffffff, 0x0400 /* expect 0x3fff */ + divide 0x00ffffff, 0x07ff /* expect 0x2004 */ + divide 0x00ffffff, 0x0800 /* expect 0x1fff */ + divide 0x00ffffff, 0x0fff /* expect 0x1001 */ + divide 0x00ffffff, 0x1000 /* expect 0x0fff */ + divide 0x00ffffff, 0x1fff /* expect 0x0800 */ + divide 0x00ffffff, 0x2000 /* expect 0x07ff */ + divide 0x00ffffff, 0x3fff /* expect 0x0400 */ + divide 0x00ffffff, 0x4000 /* expect 0x03ff */ + divide 0x00ffffff, 0x7fff /* expect 0x0200 */ + divide 0x01000000, 0x03ff /* expect 0x4010 */ + divide 0x01000000, 0x0400 /* expect 0x4000 */ + divide 0x01000000, 0x07ff /* expect 0x2004 */ + divide 0x01000000, 0x0800 /* expect 0x2000 */ + divide 0x01000000, 0x0fff /* expect 0x1001 */ + divide 0x01000000, 0x1000 /* expect 0x1000 */ + divide 0x01000000, 0x1fff /* expect 0x0800 */ + divide 0x01000000, 0x2000 /* expect 0x0800 */ + divide 0x01000000, 0x3fff /* expect 0x0400 */ + divide 0x01000000, 0x4000 /* expect 0x0400 */ + divide 0x01000000, 0x7fff /* expect 0x0200 */ + divide 0x01ffffff, 0x0400 /* expect 0x7fff */ + divide 0x01ffffff, 0x07ff /* expect 0x4008 */ + divide 0x01ffffff, 0x0800 /* expect 0x3fff */ + divide 0x01ffffff, 0x0fff /* expect 0x2002 */ + divide 0x01ffffff, 0x1000 /* expect 0x1fff */ + divide 0x01ffffff, 0x1fff /* expect 0x1000 */ + divide 0x01ffffff, 0x2000 /* expect 0x0fff */ + divide 0x01ffffff, 0x3fff /* expect 0x0800 */ + divide 0x01ffffff, 0x4000 /* expect 0x07ff */ + divide 0x01ffffff, 0x7fff /* expect 0x0400 */ + divide 0x02000000, 0x07ff /* expect 0x4008 */ + divide 0x02000000, 0x0800 /* expect 0x4000 */ + divide 0x02000000, 0x0fff /* expect 0x2002 */ + divide 0x02000000, 0x1000 /* expect 0x2000 */ + divide 0x02000000, 0x1fff /* expect 0x1000 */ + divide 0x02000000, 0x2000 /* expect 0x1000 */ + divide 0x02000000, 0x3fff /* expect 0x0800 */ + divide 0x02000000, 0x4000 /* expect 0x0800 */ + divide 0x02000000, 0x7fff /* expect 0x0400 */ + divide 0x03ffffff, 0x0800 /* expect 0x7fff */ + divide 0x03ffffff, 0x0fff /* expect 0x4004 */ + divide 0x03ffffff, 0x1000 /* expect 0x3fff */ + divide 0x03ffffff, 0x1fff /* expect 0x2001 */ + divide 0x03ffffff, 0x2000 /* expect 0x1fff */ + divide 0x03ffffff, 0x3fff /* expect 0x1000 */ + divide 0x03ffffff, 0x4000 /* expect 0x0fff */ + divide 0x03ffffff, 0x7fff /* expect 0x0800 */ + divide 0x04000000, 0x0fff /* expect 0x4004 */ + divide 0x04000000, 0x1000 /* expect 0x4000 */ + divide 0x04000000, 0x1fff /* expect 0x2001 */ + divide 0x04000000, 0x2000 /* expect 0x2000 */ + divide 0x04000000, 0x3fff /* expect 0x1000 */ + divide 0x04000000, 0x4000 /* expect 0x1000 */ + divide 0x04000000, 0x7fff /* expect 0x0800 */ + divide 0x07ffffff, 0x1000 /* expect 0x7fff */ + divide 0x07ffffff, 0x1fff /* expect 0x4002 */ + divide 0x07ffffff, 0x2000 /* expect 0x3fff */ + divide 0x07ffffff, 0x3fff /* expect 0x2000 */ + divide 0x07ffffff, 0x4000 /* expect 0x1fff */ + divide 0x07ffffff, 0x7fff /* expect 0x1000 */ + divide 0x08000000, 0x1fff /* expect 0x4002 */ + divide 0x08000000, 0x2000 /* expect 0x4000 */ + divide 0x08000000, 0x3fff /* expect 0x2000 */ + divide 0x08000000, 0x4000 /* expect 0x2000 */ + divide 0x08000000, 0x7fff /* expect 0x1000 */ + divide 0x0fffffff, 0x2000 /* expect 0x7fff */ + divide 0x0fffffff, 0x3fff /* expect 0x4001 */ + divide 0x0fffffff, 0x4000 /* expect 0x3fff */ + divide 0x0fffffff, 0x7fff /* expect 0x2000 */ + divide 0x10000000, 0x3fff /* expect 0x4001 */ + divide 0x10000000, 0x4000 /* expect 0x4000 */ + divide 0x10000000, 0x7fff /* expect 0x2000 */ + divide 0x1fffffff, 0x4000 /* expect 0x7fff */ + divide 0x1fffffff, 0x7fff /* expect 0x4000 */ + divide 0x20000000, 0x7fff /* expect 0x4000 */ + + pass diff --git a/sim/testsuite/sim/bfin/dotproduct.s b/sim/testsuite/sim/bfin/dotproduct.s new file mode 100644 index 0000000..bfae545 --- /dev/null +++ b/sim/testsuite/sim/bfin/dotproduct.s @@ -0,0 +1,304 @@ +# Blackfin testcase for a simple vector dot product using hard +# wired input buffers of 128 samples each. These values are in +# 1.15 signed . + +# mach: bfin + + .include "testutils.inc" + + start + + loadsym P0, _buf0 + loadsym P1, _buf1 + + /* loop control + * number of loop iterations is 2^N with r4|=1< 32 + + A1 = R0.H * R1.L (M), A0 = R0.L * R1.L (FU); + A1 += R1.H * R0.L (M,IS); + A0 = A0 >>> 16; + A0 += A1; + A0 = A0 >>> 16; + A0 += R0.H * R1.H (IS); + R7 = A0.w; + +loop1end: + [ P2 ++ ] = R7; // store 32 bit output + + // test results + loadsym P1, output; + R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xab6b ); + R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xa627 ); + R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xa0e3 ); + R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0x9b9f ); + pass + + .data +input_a: + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .dw 0x0000 + .dw 0xfabc + .align 4; +input_b: + .dw 0x1000 + .dw 0x4010 + .dw 0x1000 + .dw 0x4011 + .dw 0x1000 + .dw 0x4012 + .dw 0x1000 + .dw 0x4013 + .dw 0x1000 + .dw 0x4014 + .dw 0x1000 + .dw 0x4015 + .dw 0x1000 + .dw 0x4016 + .dw 0x1000 + .dw 0x4017 + .dw 0x1000 + .dw 0x4018 + .dw 0x1000 + .dw 0x4019 + .align 4; +output: + .space (40); diff --git a/sim/testsuite/sim/bfin/dsp_a4.s b/sim/testsuite/sim/bfin/dsp_a4.s new file mode 100644 index 0000000..fdafcdf --- /dev/null +++ b/sim/testsuite/sim/bfin/dsp_a4.s @@ -0,0 +1,113 @@ +/* ALU test program. + * Test instructions + * r3= + (r0,r0); + * r3= + (r0,r0) s; + * r3= - (r0,r0); + * r3= - (r0,r0) s; + */ +# mach: bfin + +.include "testutils.inc" + start + + +// overflow positive + R0.L = 0xffff; + R0.H = 0x7fff; + R7 = 0; + ASTAT = R7; + R3 = R0 + R0 (NS); + DBGA ( R3.L , 0xfffe ); + DBGA ( R3.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// overflow negative + R0.L = 0x0000; + R0.H = 0x8000; + R7 = 0; + ASTAT = R7; + R3 = R0 + R0 (NS); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// zero + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R3 = R1 + R0 (NS); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate positive + R0.L = 0; + R0.H = 0x7fff; + R7 = 0; + ASTAT = R7; + R3 = R0 + R0 (S); + DBGA ( R3.L , 0xffff ); + DBGA ( R3.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// saturate negative + R0.L = 0; + R0.H = 0x8000; + R7 = 0; + ASTAT = R7; + R3 = R0 + R0 (S); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x8000 ); + + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate positive with subtraction + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0xffff; + R1.H = 0x7fff; + R7 = 0; + ASTAT = R7; + R3 = R1 - R0 (S); + DBGA ( R3.L , 0xffff ); + DBGA ( R3.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + +// saturate negative with subtraction + R0.L = 0x1; + R0.H = 0x0; + R1.L = 0x0000; + R1.H = 0x8000; + R7 = 0; + ASTAT = R7; + R3 = R1 - R0 (S); + DBGA ( R3.L , 0x0000 ); + DBGA ( R3.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + + pass diff --git a/sim/testsuite/sim/bfin/dsp_a7.s b/sim/testsuite/sim/bfin/dsp_a7.s new file mode 100644 index 0000000..075fbc7 --- /dev/null +++ b/sim/testsuite/sim/bfin/dsp_a7.s @@ -0,0 +1,103 @@ +/* ALU test program. + * Test instructions + * r7 = +/- (r0,r1); + * r7 = -/+ (r0,r1); + * r7 = -/- (r0,r1); + */ + +# mach: bfin + +.include "testutils.inc" + start + +// test subtraction + R0.L = 0x000f; + R0.H = 0x0010; + R1.L = 0x000f; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|- R1; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test overflow negative on subtraction + R0.L = 0x8000; + R0.H = 0x0010; + R1.L = 0x0001; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|- R1; + DBGA ( R7.L , 0x7fff ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test saturate negative on subtraction +/- + R0.L = 0x8000; + R0.H = 0x0010; + R1.L = 0x0001; + R1.H = 0x0010; + R7 = 0; + ASTAT = R7; + R7 = R0 +|- R1 (S); + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0020 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test saturate negative on subtraction -/+ + R0.L = 0x8000; + R0.H = 0x8000; + R1.L = 0x0001; + R1.H = 0x0001; + R7 = 0; + ASTAT = R7; + R7 = R0 -|+ R1 (S); + DBGA ( R7.L , 0x8001 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R5 = CC; DBGA ( R5.L , 0x0 ); + CC = AN; R5 = CC; DBGA ( R5.L , 0x1 ); + CC = V; R5 = CC; DBGA ( R5.L , 0x1 ); + CC = AC0; R5 = CC; DBGA ( R5.L , 0x0 ); + +// test saturate negative on subtraction -/- + R0.L = 0x8000; + R0.H = 0x8000; + R1.L = 0x0001; + R1.H = 0x0001; + R7 = 0; + ASTAT = R7; + R7 = R0 -|- R1 (S); + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test saturate positive on subtraction -/+ + R0.L = 0x7fff; + R0.H = 0x7fff; + R1.L = 0xffff; + R1.H = 0xffff; + R7 = 0; + ASTAT = R7; + R7 = R0 -|+ R1 (S); + DBGA ( R7.L , 0x7ffe ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + + pass diff --git a/sim/testsuite/sim/bfin/dsp_a8.s b/sim/testsuite/sim/bfin/dsp_a8.s new file mode 100644 index 0000000..0383e20 --- /dev/null +++ b/sim/testsuite/sim/bfin/dsp_a8.s @@ -0,0 +1,80 @@ +/* ALU test program. + * Test instructions + * (r7,r6) = +/- (r0,r1); + * (r7,r6) = +/- (r0,r1)s; + */ +# mach: bfin + +.include "testutils.inc" + start + + +// test positive overflow + R0.L = 0xffff; + R0.H = 0x7fff; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R6 = R0 + R1, R7 = R0 - R1 (NS); + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test positive overflow + R0.L = 0xffff; + R0.H = 0x7fff; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R7 = R0 + R1, R6 = R0 - R1 (NS); + DBGA ( R6.L , 0xfffe ); + DBGA ( R6.H , 0x7fff ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test positive sat + R0.L = 0xffff; + R0.H = 0x7fff; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R6 = R0 + R1, R7 = R0 - R1 (S); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x7fff ); + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + +// test positive sat + R0.L = 0xffff; + R0.H = 0x7fff; + R1.L = 0x0001; + R1.H = 0x0000; + R7 = 0; + ASTAT = R7; + R7 = R0 + R1, R6 = R0 - R1 (S); + DBGA ( R6.L , 0xfffe ); + DBGA ( R6.H , 0x7fff ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 ); + + pass diff --git a/sim/testsuite/sim/bfin/dsp_d0.s b/sim/testsuite/sim/bfin/dsp_d0.s new file mode 100644 index 0000000..ff7aaf0 --- /dev/null +++ b/sim/testsuite/sim/bfin/dsp_d0.s @@ -0,0 +1,31 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym I0, vec; + + R0 = [ I0 ++ ]; + DBGA ( R0.L , 1 ); DBGA ( R0.H , 2 ); + R0 = [ I0 ++ ]; + DBGA ( R0.L , 2 ); DBGA ( R0.H , 3 ); + + loadsym I3, vec; + R0 = 4; + M1 = R0; + + _DBG I3; + R0 = [ I3 ++ M1 ]; + DBGA ( R0.L , 1 ); DBGA ( R0.H , 2 ); + _DBG I3; + R0 = [ I3 ++ M1 ]; + DBGA ( R0.L , 2 ); DBGA ( R0.H , 3 ); + + pass + + .data +vec: + .dw 1 + .dw 2 + .dw 2 + .dw 3 diff --git a/sim/testsuite/sim/bfin/dsp_d1.s b/sim/testsuite/sim/bfin/dsp_d1.s new file mode 100644 index 0000000..c045ba5 --- /dev/null +++ b/sim/testsuite/sim/bfin/dsp_d1.s @@ -0,0 +1,117 @@ +/* DAG test program. + * Test circular buffers + */ +# mach: bfin + +.include "testutils.inc" + start + + loadsym I0, foo; + loadsym B0, foo; + loadsym R2, foo; + L0 = 0x10 (X); + M1 = 8 (X); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2 + DBGA ( R1.L , 0x0008 ); + R0 = [ I0 ++ M1 ]; + R7 = I0; + + R1 = R7 - R2; + DBGA ( R1.L , 0x0000 ); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2 + DBGA ( R1.L , 0x0008 ); + + loadsym I0, foo; + loadsym B0, foo; + loadsym R2, foo; + L0 = 0x10 (X); + M1 = -4 (X); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2 + DBGA ( R1.L , 0x000c ); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2 + DBGA ( R1.L , 0x0008 ); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0004 ); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0000 ); + R0 = [ I0 ++ M1 ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x000c ); + + loadsym I0, foo; + loadsym B0, foo; + loadsym R2, foo; + L0 = 0x8 (X); + R0 = [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0004 ); + R0 = [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0000 ); + R0 = [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0004 ); + + loadsym I0, foo; + loadsym B0, foo; + loadsym R2, foo; + L0 = 0x8 (X); + R0.L = W [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0002 ); + R0.L = W [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0004 ); + R0.L = W [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0006 ); + R0.L = W [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0000 ); + R0.L = W [ I0 ++ ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0002 ); + + loadsym I0, foo; + loadsym B0, foo; + loadsym R2, foo; + L0 = 0x8 (X); + R0 = [ I0 -- ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0004 ); + R0 = [ I0 -- ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0000 ); + R0 = [ I0 -- ]; + R7 = I0; + R1 = R7 - R2; + DBGA ( R1.L , 0x0004 ); + + pass + + .data +foo: + .space (0x10); diff --git a/sim/testsuite/sim/bfin/dsp_neg.S b/sim/testsuite/sim/bfin/dsp_neg.S new file mode 100644 index 0000000..a6ec10a --- /dev/null +++ b/sim/testsuite/sim/bfin/dsp_neg.S @@ -0,0 +1,36 @@ +// ALU test program. +// Test instructions: +// dreg = -dreg (ns); +// dreg = -dreg (s); +// dspalu32 negate instruction +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + +// CHECK MULTI ISSUE + r1=0x5; + loadsym i0, data0; + r2 = -r1 (ns) || r3=[i0++]; + checkreg r2, 0xfffffffb; + r3 = astat + checkreg r3, (_AN); + + r1.h = 0x8000; + r1.l = 0x0; + r2 = -r1 (s); + checkreg r2, 0x7fffffff; + + r3 = astat; + _dbg astat; + checkreg r3, (_VS|_V|_V_COPY); + + pass + + .data +data0: + .space (0x10); diff --git a/sim/testsuite/sim/bfin/dsp_s1.s b/sim/testsuite/sim/bfin/dsp_s1.s new file mode 100644 index 0000000..70d8a5d --- /dev/null +++ b/sim/testsuite/sim/bfin/dsp_s1.s @@ -0,0 +1,85 @@ +/* SHIFT test program. + * Test r0, r1, A0 >>= BITMUX; + */ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = r0; + +// load r0=0x80000009 +// load r1=0x10000009 +// load r2=0x0000000f +// load r3=0x00000000 +// load r4=0x80000008 +// load r5=0x00000000 + loadsym P0, data0; + loadsym P1, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + +// insert two bits, both equal to 1 +// A0: 00 0000 000f -> c0 0000 0003 +// r0: 8000 0009 -> 4000 0004 +// r1: 1000 0009 -> 0800 0004 + R0 = [ P1 + 0 ]; + R1 = [ P1 + 4 ]; + A0.w = R2; + A0.x = R3.L; + BITMUX( R0 , R1, A0) (ASR); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0003 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xffc0 ); + DBGA ( R0.L , 0x0004 ); + DBGA ( R0.H , 0x4000 ); + DBGA ( R1.L , 0x0004 ); + DBGA ( R1.H , 0x0800 ); + +// insert two bits, one equal to 1, other to 0 +// A0: 00 0000 000f -> 40 0000 0003 +// r0: 8000 0009 -> 4000 0004 +// r4: 8000 0008 -> 4000 0004 + R0 = [ P1 + 0 ]; + R4 = [ P1 + 16 ]; + A0.w = R2; + A0.x = R3.L; + BITMUX( R0 , R4, A0) (ASR); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0003 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0040 ); + DBGA ( R0.L , 0x0004 ); + DBGA ( R0.H , 0x4000 ); + DBGA ( R4.L , 0x0004 ); + DBGA ( R4.H , 0x4000 ); + + pass + + .data +data0: + .dw 0x0009 + .dw 0x8000 + + .dw 0x0009 + .dw 0x1000 + + .dw 0x000f + .dw 0x0000 + + .dw 0x0000 + .dw 0x0000 + + .dw 0x0008 + .dw 0x8000 + + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/e0.s b/sim/testsuite/sim/bfin/e0.s new file mode 100644 index 0000000..bdcd71b --- /dev/null +++ b/sim/testsuite/sim/bfin/e0.s @@ -0,0 +1,51 @@ +// assert that we can issue a software exception +// and that the expt number is passed correctly through +// SEQSTAT. +# mach: bfin +# sim: --environment operating + + .include "testutils.inc" + + start +.ifndef BFIN_HOST + imm32 p0, 0xFFE02000; /* EVT0 */ + P1 = re (Z); // load a pointer to ihandler interrupt 1 + P1.H = re; + [ P0 + (4*3) ] = P1; + + R0 = -1; /* unmask all interrupts */ + imm32 p1, 0xFFE02104; + [P1] = R0; + + R0 = start_uspace (Z); + R0.H = start_uspace; + RETI = R0; + RTI; +start_uspace: + EXCPT 10; + + DBGA ( R1.L , 0x1238 ); + + dbg_pass; + + // ihandler +re: + R0 = SEQSTAT; + R0 <<= (32-6); + R0 >>= (32-6); + R2 = 0x20; + CC = R0 < R2; + IF !CC JUMP _error; + DBGA ( R0.L , 0xa ); + R1 = 0x1234 (X); + R1 += 1; + R1 += 1; + R1 += 1; + R1 += 1; + RTX; + +_error: + DBGA ( R0.L , EXCPT_PROTVIOL ); + dbg_fail; + +.endif diff --git a/sim/testsuite/sim/bfin/edn_snafu.s b/sim/testsuite/sim/bfin/edn_snafu.s new file mode 100644 index 0000000..b97d7e8 --- /dev/null +++ b/sim/testsuite/sim/bfin/edn_snafu.s @@ -0,0 +1,45 @@ +# mach: bfin + +.include "testutils.inc" + start + + + + loadsym r7, foo; + + p0 = r7; + + r0.h=0x2a2a; + r0.l=0x2a2a; + + [p0++]=r0; + [p0++]=r0; + r0=0; + [p0++]=r0; + + p0 = r7; + p1=-1; + + lsetup(lstart, lend) lc0=p1; + +lstart: + _dbg p0; + r1=b[p0++] (z); + cc = r1 == 0; + if cc jump ldone; +lend: + nop; + +ldone: + + r1=b[p0++](z); + r1=p0; + r6 = r1 - r7; + + DBGA (R6.L, 0xA); + + pass; + + .data +foo: + .space (0x100) diff --git a/sim/testsuite/sim/bfin/eu_dsp32mac_s.s b/sim/testsuite/sim/bfin/eu_dsp32mac_s.s new file mode 100644 index 0000000..6935aa6 --- /dev/null +++ b/sim/testsuite/sim/bfin/eu_dsp32mac_s.s @@ -0,0 +1,38 @@ +// Check MAC with scaling +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0; + R1 = 0; + R2 = 0; + A1 = A0 = 0; +// The result accumulated in A1, and stored to a reg half + R0.L = 23229; + R0.H = -23724; + R1.L = -313; + R1.H = -17732; + R2.H = ( A1 = R1.L * R0.L ), A0 += R1.L * R0.L (S2RND); + _DBG R2; + DBGA ( R2.H , 0xfe44 ); + + R0 = 0; + ASTAT = R0; // clear all flags + A0 = 0; + A1 = 0; + R0.H = 0x8000; + R0.L = 0x7fff; + R1.H = 0x7fff; + R1.L = 0x8000; + A1 = R0.H * R1.H (M), R0.L = ( A0 -= R0.H * R1.H ) (ISS2); + _DBG R0; + DBGA ( R0.L , 0x7fff ); + + R0 += 0; // clear flags + NOP; + NOP; + NOP; + NOP; + pass diff --git a/sim/testsuite/sim/bfin/events.s b/sim/testsuite/sim/bfin/events.s new file mode 100644 index 0000000..689f47b --- /dev/null +++ b/sim/testsuite/sim/bfin/events.s @@ -0,0 +1,44 @@ +# Blackfin testcase for event processing +# mach: bfin + + .include "testutils.inc" + + start + + # Run enough instructions to trigger event processing + # and thus cpu stopping/restarting + + R0 = 0; + imm32 R1, 100000 + +3: + R0 += 1; # 1 + R0 += 1; + R0 += 1; # 3 + R0 += 1; + R0 += 1; # 5 + R0 += 1; + R0 += 1; # 7 + R0 += 1; + R0 += 1; # 9 + R0 += 1; + R0 += 1; # 11 + R0 += 1; + R0 += 1; # 13 + R0 += 1; + R0 += 1; # 15 + R0 += 1; + R0 += 1; # 17 + R0 += 1; + R0 += 1; # 19 + R0 += 1; + + CC = R0 < R1; + IF CC JUMP 3b; + + CC = R0 == R1; + IF !CC JUMP 1f; + + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/f221.s b/sim/testsuite/sim/bfin/f221.s new file mode 100644 index 0000000..7968843 --- /dev/null +++ b/sim/testsuite/sim/bfin/f221.s @@ -0,0 +1,56 @@ +# Blackfin testcase for the CEC (handling exceptions from usermode) +# mach: bfin +# sim: --environment operating + + .include "testutils.inc" + + start +.ifndef BFIN_HOST + // load address of exception handler + imm32 p0, 0xFFE02000; /* EVT0 */ + R0 = exception_handler (Z); + R0.H = exception_handler; + [ P0 + (4*3) ] = R0; + // Jump to User mode and enable exceptions + R0 = UserCode (Z); + R0.H = UserCode; + RETI = R0; + RTI; + +UserCode: + R4 = 0xec39 (Z); + R0 = 0xcafe (Z); + L3 = 0xf41f (Z); + L3.H = 0x1ce9; + I3 = 0xfe10 (Z); + I3.H = 0x20a9; + B3 = 0x4552 (Z); + B3.H = 0x15f0; + + // should except - r4 dep + // R4 = R4 >> 25 || W [ I3 ++ ] = R0.H || R4 = [ I3 ]; +.Lskip_start: + .rep 8 + .byte 0xff + .endr + dbg_fail; +.Lskip_end: + NOP; + NOP; + NOP; + NOP; + NOP; + dbg_pass; + +exception_handler: + // just skip over excepting instructions + R0 = RETX; + R1.L = .Lskip_start; + R1.H = .Lskip_start; + R2.L = .Lskip_end; + R2.H = .Lskip_end; + R2 = R2 - R1; + R0 = R0 + R2; + RETX = R0; + RTX; +.endif diff --git a/sim/testsuite/sim/bfin/fact.s b/sim/testsuite/sim/bfin/fact.s new file mode 100644 index 0000000..38e756c --- /dev/null +++ b/sim/testsuite/sim/bfin/fact.s @@ -0,0 +1,47 @@ +# Blackfin testcase for factorial +# mach: bfin + + .include "testutils.inc" + + start + + .macro factorial num:req answer:req + R0 = \num (Z); + CALL _fact; + imm32 r1, \answer; + CC = R1 == R0; + if CC JUMP 1f; + fail +1: + .endm + +_test: + factorial 1 1 + factorial 2 2 + factorial 3 6 + factorial 4 24 + factorial 5 120 + factorial 6 720 + factorial 7 5040 + factorial 8 40320 + factorial 9 362880 + factorial 10 3628800 + factorial 11 39916800 + factorial 12 479001600 + factorial 13 6227020800 + factorial 13 1932053504 + pass + +_fact: + LINK 0; + [ -- SP ] = R7; + CC = R0 < 2; + IF CC JUMP 1f; + R7 = R0; + R0 += -1; + CALL _fact; + R0 *= R7; +1: + R7 = [ SP ++ ]; + UNLINK; + RTS; diff --git a/sim/testsuite/sim/bfin/fir.s b/sim/testsuite/sim/bfin/fir.s new file mode 100644 index 0000000..0ba4d2f --- /dev/null +++ b/sim/testsuite/sim/bfin/fir.s @@ -0,0 +1,201 @@ +# mach: bfin + +// FIR FILTER COMPTUED DIRECTLY ON INPUT WITH NO +// INTERNAL STATE +// TWO OUTPUTS PER ITERATION +// This program computes a FIR filter without maintaining a buffer of internal +// state. +// This example computes two output samples per inner loop. The following +// diagram shows the alignment required for signal x and coefficients c: +// x0 x1 x2 x3 x4 x5 +// c0 c1 c2 c3 c4 -> output z(0)=x0*c0 + x1*c1 + ... +// c0 c1 c2 c3 c4 -> z(1)=x1*c0 + x2*c1 + ... +// L-1 +// --- +// Z(k) = \ c(n) * x(n+k) +// / +// --- +// n=0 +// Naive, first stab at spliting this for dual MACS. +// L/2-1 L/2-1 +// --- --- +// R(k) = \ (x(2n) * y(2n+k)) + \ (x(2n-1) * y(2n-1+k)) +// / / +// --- --- +// n=0 n=0 +// Alternate, better partitioning for the machine. +// L-1 +// --- +// R(0) = \ x(n) * y(n) +// / +// --- +// n=0 +// L-1 +// --- +// R(1) = \ x(n) * y(n+1) +// / +// --- +// n=0 +// L-1 +// --- +// R(2) = \ x(n) * y(n+2) +// / +// --- +// n=0 +// L-1 +// --- +// R(3) = \ x(n) * y(n+3) +// / +// --- +// n=0 +// . +// . +// . +// . +// Okay in this verion the inner loop will compute R(2k) and R(2k+1) in parallel +// L-1 +// --- +// R(2k) = \ x(n) * y(n+2k) +// / +// --- +// n=0 +// L-1 +// --- +// R(2k+1) = \ x(n) * y(n+2k+1) +// / +// --- +// n=0 +// Implementation +// -------------- +// Sample pair x1 x0 is loaded into register R0, and coefficients c1 c0 +// is loaded into register R1: +// +-------+ R0 +// | x1 x0 | +// +-------+ +// +-------+ R1 +// | c1 c0 | compute two MACs: z(0)+=x0*c0, and z(1)+=x1*c0 +// +-------+ +// Now load x2 into lo half of R0, and compute the next two MACs: +// +-------+ R0 +// | x1 x2 | +// +-------+ +// +-------+ R1 +// | c1 c0 | compute z(0)+=x1*c1 and z(1)+=x2*c1 (c0 not used) +// +-------+ +// Meanwhile, load coefficient pair c3 c2 into R2, and x3 into hi half of R0: +// +-------+ R0 +// | x3 x2 | +// +-------+ +// +-------+ R2 +// | c3 c2 | compute z(0)+=x2*c2 and z(1)+=x3*c2 (c3 not used) +// +-------+ +// Load x4 into low half of R0: +// +-------+ R0 +// | x3 x4 | +// +-------+ +// +-------+ R1 +// | c3 c2 | compute z(0)+=x3*c3 and z(1)+=x4*c3 (c2 not used) +// +-------+ +// //This is a reference FIR function used to test: */ +//void firf (float input[], float output[], float coeffs[], +// long input_size, long coeffs_size) +//{ +// long i, k; +// for(i=0; i< input_size; i++){ +// output[i] = 0; +// for(k=0; k < coeffs_size; k++) +// output[i] += input[k+i] * coeffs[k]; +// } +//} + +.include "testutils.inc" + start + + + R0 = 0; R1 = 0; R2 = 0; + P1 = 128 (X); // Load loop bounds in R5, R6, and divide by 2 + P2 = 64 (X); + + // P0 holds pointer to input data in one memory + // bank. Increments by 2 after each inner-loop iter + loadsym P0, input; + + // Pointer to coeffs in alternate memory bank. + loadsym I1, coef; + + // Pointer to outputs in any memory bank. + loadsym I2, output; + + // Setup outer do-loop for M/2 iterations + // (2 outputs are computed per pass) + + LSETUP ( L$0 , L$0end ) LC0 = P1 >> 1; + +L$0: + loadsym I1, coef; + I0 = P0; + // Set-up inner do-loop for L/2 iterations + // (2 MACs are computed per pass) + + LSETUP ( L$1 , L$1end ) LC1 = P2 >> 1; + + // Load first two data elements in r0, + // and two coeffs into r1: + + R0.L = W [ I0 ++ ]; + A1 = A0 = 0 || R0.H = W [ I0 ++ ] || R1 = [ I1 ++ ]; + +L$1: + A1 += R0.H * R1.L, A0 += R0.L * R1.L || R0.L = W [ I0 ++ ] || NOP; +L$1end: + A1 += R0.L * R1.H, A0 += R0.H * R1.H || R0.H = W [ I0 ++ ] || R1 = [ I1 ++ ]; + + // Line 1: do 2 MACs and load next data element into RL0. + // Line 2: do 2 MACs, load next data element into RH0, + // and load next 2 coeffs + + R0.H = A1, R0.L = A0; + + // advance data pointer by 2 16b elements + P0 += 4; + +L$0end: + [ I2 ++ ] = R0; // store 2 outputs + + // Check results + loadsym I2, output; + + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0800 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1000 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x2000 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1000 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0800 ); + pass + + .data +input: + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x4000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .space ((128-10)*2); // must pad with zeros or uninitialized values. + + .data +coef: + .dw 0x1000 + .dw 0x2000 + .dw 0x4000 + .dw 0x2000 + .dw 0x1000 + .dw 0x0000 + .space ((64-6)*2); // must pad with zeros or uninitialized values. + + .data +output: + .space (128*4) diff --git a/sim/testsuite/sim/bfin/fsm.s b/sim/testsuite/sim/bfin/fsm.s new file mode 100644 index 0000000..a15ffa0 --- /dev/null +++ b/sim/testsuite/sim/bfin/fsm.s @@ -0,0 +1,57 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R1 = 0; + R0 = R1; + R7 = 7; +L$10: + CC = R0 == 1; + IF CC JUMP L$14; + CC = R0 <= 1; + IF !CC JUMP L$30; + CC = R0 == 0; + IF CC JUMP L$12; + JUMP.S L$25; +L$30: + CC = R0 == R7; + IF CC JUMP L$16; + R5 = 17; + CC = R0 == R5; + IF CC JUMP L$23; + JUMP.S L$25; +L$12: + R1 += 5; + R0 = 1; + JUMP.S L$8; +L$14: + R1 <<= 4; + R0 = 4; + JUMP.S L$8; +L$16: + CC = BITTST ( R1 , 3 ); + IF CC JUMP L$17; + BITSET( R1 , 3 ); + R0 = 4; + JUMP.S L$20; +L$17: + BITSET( R1 , 5 ); + R0 = 14; +L$20: + JUMP.S L$8; +L$23: + R5 = 13; + R1 = R1 ^ R5; + R0 = 20; + JUMP.S L$8; +L$25: + R1 += 1; + R0 += 1; +L$8: + R5 = 19; + CC = R0 <= R5; + IF CC JUMP L$10 (BP); + DBGA ( R0.L , 20 ); DBGA ( R1.L , 140 ); + pass diff --git a/sim/testsuite/sim/bfin/greg2.s b/sim/testsuite/sim/bfin/greg2.s new file mode 100644 index 0000000..7135130 --- /dev/null +++ b/sim/testsuite/sim/bfin/greg2.s @@ -0,0 +1,18 @@ +# mach: bfin + +.include "testutils.inc" + start + + r3.l=0x5678; + r3.h=0x1234; + + p5=8; + + p5=r3; + p5.l =4; + + r5=p5; + dbga( r5.h, 0x1234); + +_halt: + pass; diff --git a/sim/testsuite/sim/bfin/hwloop-bits.S b/sim/testsuite/sim/bfin/hwloop-bits.S new file mode 100644 index 0000000..76d9003 --- /dev/null +++ b/sim/testsuite/sim/bfin/hwloop-bits.S @@ -0,0 +1,104 @@ +# Blackfin testcase for HW Loops and user->super transitions +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + .macro check_hwloop_regs lc:req, lt:req, lb:req + R0 = LC0; + CC = R0 == \lc; + IF !CC JUMP fail; + + R0 = LT0; + CC = R0 == \lt; + IF !CC JUMP fail; + + R0 = LB0; + CC = R0 == \lb; + IF !CC JUMP fail; + + R0 = LC1; + CC = R0 == \lc; + IF !CC JUMP fail; + + R0 = LT1; + CC = R0 == \lt; + IF !CC JUMP fail; + + R0 = LB1; + CC = R0 == \lb; + IF !CC JUMP fail; + .endm + + start + + imm32 P0, EVT3; + loadsym R0, exception; + [P0] = R0; + + imm32 P0, EVT2; + loadsym R0, nmi; + [P0] = R0; + + loadsym R0, usermode; + RETI = R0; + + # Set the LC/LB/LT up with LSB set + # - Hardware clears LT LSB, but LB remains until we lower + imm32 R6, 0xaaaa5555 + R4 = R6; + BITCLR (R4, 0); + imm32 R7, 0xaa55aa55 + R5 = R7; + BITCLR (R5, 0); + + LC0 = R6; + LT0 = R6; + LB0 = R7; + LC1 = R6; + LT1 = R6; + LB1 = R7; + + # Sanity check + check_hwloop_regs R6, R4, R7 + + RTI; + +usermode: + # Make sure LSB has been cleared in LB + check_hwloop_regs R6, R4, R5 + + # Clear LSB in all LC/LT/LB + LC0 = R4; + LT0 = R4; + LB0 = R5; + LC1 = R4; + LT1 = R4; + LB1 = R5; + + # Now move back up to supervisor + EXCPT 4; + +exception: + # Make sure LSB is set in LB + check_hwloop_regs R4, R4, R7 + + # Clear the LSB and move up another supervisor level + LC0 = R4; + LT0 = R4; + LB0 = R5; + LC1 = R4; + LT1 = R4; + LB1 = R5; + + RAISE 2; + +nmi: + # Make sure LSB stayed clear + check_hwloop_regs R4, R4, R5 + + dbg_pass + +fail: + dbg_fail diff --git a/sim/testsuite/sim/bfin/hwloop-branch-in.s b/sim/testsuite/sim/bfin/hwloop-branch-in.s new file mode 100644 index 0000000..c477c94 --- /dev/null +++ b/sim/testsuite/sim/bfin/hwloop-branch-in.s @@ -0,0 +1,99 @@ +# Blackfin testcase for branching into the middle of a hardware loop +# mach: bfin + + .include "testutils.inc" + + .macro test_prep lc:req + loadsym P5, 1f; + dmm32 LC0, \lc + R5 = 0; + R6 = 0; + R7 = 0; + .endm + + .macro test_check exp5:req, exp6:req, exp7:req, expLC:req +1: + imm32 R4, \exp5; + CC = R4 == R5; + IF !CC JUMP 2f; + imm32 R4, \exp6; + CC = R4 == R6; + IF !CC JUMP 2f; + imm32 R4, \exp7; + CC = R4 == R7; + IF !CC JUMP 2f; + R3 = LC0; + imm32 R4, \expLC; + CC = R4 == R3; + IF !CC JUMP 2f; + JUMP 3f; +2: fail +3: + .endm + + .macro test_rts entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req + loadsym R1, \entry; + RETS = R1; + test_prep \lc + RTS; + test_check \exp5, \exp6, \exp7, \expLC + .endm + + .macro test_jump entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req + loadsym P1, \entry; + test_prep \lc + JUMP (P1); + test_check \exp5, \exp6, \exp7, \expLC + .endm + + start + + loadsym R1, hws; + LT0 = R1; + loadsym R1, hwe; + LB0 = R1; + + test_rts hws, 0, 1, 1, 1, 0 + test_rts hws, 1, 1, 1, 1, 0 + test_rts hws, 2, 2, 2, 2, 0 + test_rts hws, 20, 20, 20, 20, 0 + + test_rts hwm, 0, 0, 1, 1, 0 + test_rts hwm, 1, 0, 1, 1, 0 + test_rts hwm, 2, 1, 2, 2, 0 + test_rts hwm, 20, 19, 20, 20, 0 + + test_rts hwe, 0, 0, 0, 1, 0 + test_rts hwe, 1, 0, 0, 1, 0 + test_rts hwe, 2, 1, 1, 2, 0 + test_rts hwe, 20, 19, 19, 20, 0 + + test_rts hwp, 0, 0, 0, 0, 0 + test_rts hwp, 1, 0, 0, 0, 1 + test_rts hwp, 2, 0, 0, 0, 2 + + test_jump hws, 0, 1, 1, 1, 0 + test_jump hws, 1, 1, 1, 1, 0 + test_jump hws, 2, 2, 2, 2, 0 + test_jump hws, 20, 20, 20, 20, 0 + + test_jump hwm, 0, 0, 1, 1, 0 + test_jump hwm, 1, 0, 1, 1, 0 + test_jump hwm, 2, 1, 2, 2, 0 + test_jump hwm, 20, 19, 20, 20, 0 + + test_jump hwe, 0, 0, 0, 1, 0 + test_jump hwe, 1, 0, 0, 1, 0 + test_jump hwe, 2, 1, 1, 2, 0 + test_jump hwe, 20, 19, 19, 20, 0 + + test_jump hwp, 0, 0, 0, 0, 0 + test_jump hwp, 1, 0, 0, 0, 1 + test_jump hwp, 2, 0, 0, 0, 2 + + pass + +hws: R5 += 1; +hwm: R6 += 1; +hwe: R7 += 1; +hwp: JUMP (P5); diff --git a/sim/testsuite/sim/bfin/hwloop-branch-out.s b/sim/testsuite/sim/bfin/hwloop-branch-out.s new file mode 100644 index 0000000..54f712b --- /dev/null +++ b/sim/testsuite/sim/bfin/hwloop-branch-out.s @@ -0,0 +1,129 @@ +# Blackfin testcase for branching out of the middle of a hardware loop +# mach: bfin + + .include "testutils.inc" + + .macro test_prep lc:req, sym:req + imm32 P0, \lc + loadsym P1, \sym + R5 = 0; + R6 = 0; + R7 = 0; + LSETUP (1f, 2f) LC0 = P0; + .endm + + .macro test_check exp5:req, exp6:req, exp7:req, expLC + imm32 R4, \exp5; + CC = R4 == R5; + IF !CC JUMP 2f; + imm32 R4, \exp6; + CC = R4 == R6; + IF !CC JUMP 2f; + imm32 R4, \exp7; + CC = R4 == R7; + IF !CC JUMP 2f; + R3 = LC0; + imm32 R4, \expLC; + CC = R4 == R3; + IF !CC JUMP 2f; + JUMP 3f; +2: fail +3: + .endm + + start + mnop; + +test_jump_s: + .macro test_jump_s lc:req + test_prep \lc, 3f +1: JUMP (P1); + R5 += 1; +2: R6 += 1; + fail +3: R7 += 1; + test_check 0, 0, 1, \lc + .endm + test_jump_s 0 + test_jump_s 1 + test_jump_s 2 + test_jump_s 10 + +test_jump_m: + .macro test_jump_m lc:req + test_prep \lc, 3f +1: R5 += 1; + JUMP (P1); +2: R6 += 1; + fail +3: R7 += 1; + test_check 1, 0, 1, \lc + .endm + test_jump_m 0 + test_jump_m 1 + test_jump_m 2 + test_jump_m 10 + +test_jump_e: + .macro test_jump_e lc:req, lcend:req + test_prep \lc, 3f +1: R5 += 1; + R6 += 1; +2: JUMP (P1); + fail +3: R7 += 1; + test_check 1, 1, 1, \lcend + .endm + test_jump_e 0, 0 + test_jump_e 1, 0 + test_jump_e 2, 1 + test_jump_e 10, 9 + +test_call_s: + .macro test_call_s lc:req, exp5:req, exp6:req, exp7:req + test_prep \lc, __ret +1: CALL (P1); + R5 += 1; +2: R6 += 1; +3: R7 += 1; + test_check \exp5, \exp6, \exp7, 0 + .endm + test_call_s 0, 1, 1, 2 + test_call_s 1, 1, 1, 2 + test_call_s 2, 2, 2, 3 + test_call_s 10, 10, 10, 11 + +test_call_m: + .macro test_call_m lc:req, exp5:req, exp6:req, exp7:req + test_prep \lc, __ret +1: R5 += 1; + CALL (P1); +2: R6 += 1; +3: R7 += 1; + test_check \exp5, \exp6, \exp7, 0 + .endm + test_call_m 0, 1, 1, 2 + test_call_m 1, 1, 1, 2 + test_call_m 2, 2, 2, 3 + test_call_m 10, 10, 10, 11 + +test_call_e: + .macro test_call_e lc:req, exp5:req, exp6:req, exp7:req + test_prep \lc, __ret +1: R5 += 1; + R6 += 1; +2: CALL (P1); +3: R7 += 1; + test_check \exp5, \exp6, \exp7, 0 + .endm + test_call_e 0, 1, 1, 2 + test_call_e 1, 1, 1, 2 + test_call_e 2, 2, 2, 3 + test_call_e 10, 10, 10, 11 + + pass + +__ret: + nop;nop;nop; + R7 += 1; + rts; diff --git a/sim/testsuite/sim/bfin/hwloop-lt-bits.s b/sim/testsuite/sim/bfin/hwloop-lt-bits.s new file mode 100644 index 0000000..dd21c8a --- /dev/null +++ b/sim/testsuite/sim/bfin/hwloop-lt-bits.s @@ -0,0 +1,25 @@ +# Blackfin testcase for HW Loops (LT) LSB behavior +# mach: bfin + + .include "testutils.inc" + + start + + # Loading LT should always clear LSB + imm32 R6, 0xaaaa5555 + R4 = R6; + BITCLR (R4, 0); + + LT0 = R6; + LT1 = R6; + + R0 = LT0; + CC = R0 == R4; + IF ! CC JUMP 1f; + + R0 = LT1; + CC = R0 == R4; + IF ! CC JUMP 1f; + + pass +1: fail diff --git a/sim/testsuite/sim/bfin/hwloop-nested.s b/sim/testsuite/sim/bfin/hwloop-nested.s new file mode 100644 index 0000000..9d1b71c --- /dev/null +++ b/sim/testsuite/sim/bfin/hwloop-nested.s @@ -0,0 +1,33 @@ +# Blackfin testcase for overlapping nested hwloops (LB) +# mach: bfin + + .include "testutils.inc" + + start + + R0 = 0; + R1 = 0; + P0 = 2; + P1 = 2; + LSETUP (1f, 3f) LC0 = P0; +1: R0 += 1; + + LSETUP (2f, 3f) LC1 = P1; +2: R1 += 1; + + CC = R1 == 2; + IF !CC JUMP 3f; + CC = R0 == 1; + IF !CC JUMP fail; + R3 = LC0; + CC = R3 == 2; + IF !CC JUMP fail; + R3 = LC1; + CC = R3 == 1; + IF !CC JUMP fail; + pass + +3: nop; + +fail: + fail diff --git a/sim/testsuite/sim/bfin/i0.s b/sim/testsuite/sim/bfin/i0.s new file mode 100644 index 0000000..89c7fd5 --- /dev/null +++ b/sim/testsuite/sim/bfin/i0.s @@ -0,0 +1,57 @@ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + R0.L = 0x1234; + R0.H = 0x7765; + DBGA ( R0.L , 0x1234 ); + DBGA ( R0.H , 0x7765 ); + R0.L = -1; + DBGA ( R0.H , 0x7765 ); + DBGA ( R0.L , 0xffff ); + + R0.L = 0x5555; + R0.H = 0xAAAA; + DBGA ( R0.H , 0xAAAA ); + DBGA ( R0.L , 0x5555 ); + + I0.L = 0x1234; + I0.H = 0x256; + R0 = I0; + DBGA ( R0.L , 0x1234 ); + DBGA ( R0.H , 0x256 ); + + R0 = -50; + R1 = -77 (X); + R2 = -99 (X); + R3 = 32767 (X); + R4 = -32768 (X); + R5 = 256 (X); + R6 = 128 (X); + R7 = 1023 (X); + DBGA ( R0.L , 0xffce ); + DBGA ( R1.L , 0xffb3 ); + DBGA ( R2.L , 0xff9d ); + DBGA ( R3.L , 0x7fff ); + DBGA ( R4.L , 0x8000 ); + DBGA ( R5.L , 256 ); + DBGA ( R6.L , 128 ); + DBGA ( R7.L , 1023 ); + + R6 = -1; + DBGA ( R6.L , 0xffff ); + + R0.L = 0x5555; + R1.L = 0xaaaa; + + DBGA ( R0.L , 0x5555 ); + DBGA ( R1.L , 0xaaaa ); + + R0 = R0 + R1; + DBGA ( R0.H , 0xfffe ); + + pass diff --git a/sim/testsuite/sim/bfin/iir.s b/sim/testsuite/sim/bfin/iir.s new file mode 100644 index 0000000..b1cb420 --- /dev/null +++ b/sim/testsuite/sim/bfin/iir.s @@ -0,0 +1,207 @@ +# mach: bfin + +// GENERIC BIQUAD: +// --------------- +// x ---------+---------|---------+-------y +// | |t1 | +// | D | +// | a1 | b1 | +// +---<-----|---->----+ +// | | | +// | D | D's are delays +// | a2 | b2 | ">" represent multiplications +// +---<-----|---->----+ +// To test this routine, use a biquad with a pole pair at z = (0.7 +- 0.1j), +// and a double zero at z = -1.0, which is a low-pass. The transfer function is: +// 1 + 2z^-1 + z^-2 +// H(z) = ---------------------- +// 1 - 1.4z^-1 + 0.5z^-2 +// a1 = 1.4 +// a2 = -0.5 +// b1 = 2 +// b2 = 1 +// This filter conforms to the biquad test in BDT, since it has coefficients +// larger than 1.0 in magnitude, and b0=1. (Note that the a's have a negative +// sign.) +// This filter can be simulated in matlab. To simulate one biquad, use +// A = [1.0, -1.4, 0.5] +// B = [1, 2, 1] +// Y=filter(B,A,X) +// To simulate two cascaded biquads, use +// Y=filter(B,A,filter(B,A,X)) +// SCALED COEFFICIENTS: +// -------------------- +// In order to conform to 1.15 representation, must scale coeffs by 0.5. +// This requires an additional internal re-scale. The equations for the Type II +// filter are: +// t1 = x + a1*t1*z^-1 + a2*t1*z^-2 +// y = b0*t1 + b1*t1*z^-1 + b2*t1*z^-2 +// (Note inclusion of term b0, which in the example is b0 = 1.) +// If all coeffs are replaced by +// ai --> ai' = 0.5*a1 +// then the two equations become +// t1 = x + 2*a1'*t1*z^-1 + 2*a2'*t1*z^-2 +// 0.5*y = b0'*t1 + b1'*t1*z^-1 + b2'*t1*z^-2 +// which can be implemented as: +// 2.0 b0'=0.5 +// x ---------+--->-----|---->----+-------y +// | |t1 | +// | D | +// | a1' | b1' | +// +---<-----|---->----+ +// | | | +// | D | +// | a2' | b2' | +// +---<-----|---->----+ +// But, b0' can be eliminated by: +// x ---------+---------|---------+-------y +// | | | +// | V 2.0 | +// | | | +// | |t1 | +// | D | +// | a1' | b1' | +// +---<-----|---->----+ +// | | | +// | D | +// | a2' | b2' | +// +---<-----|---->----+ +// Function biquadf() computes this implementation on float data. +// CASCADED BIQUADS +// ---------------- +// Cascaded biquads are simulated by simply cascading copies of the +// filter defined above. However, one must be careful with the resulting +// filter, as it is not very stable numerically (double poles in the +// vecinity of +1). It would of course be better to cascade different +// filters, as that would result in more stable structures. +// The functions biquadf() and biquadR() have been tested with up to 3 +// stages using this technique, with inputs having small signal amplitude +// (less than 0.001) and under 300 samples. +// +// In order to pipeline, need to maintain two pointers into the state +// array: one to load (I0) and one to store (I2). This is required since +// the load of iteration i+1 is hoisted above the store of iteration i. + +.include "testutils.inc" + start + + + // I3 points to input buffer + loadsym I3, input; + + // P1 points to output buffer + loadsym P1, output; + + R0 = 0; R7 = 0; + + P2 = 10; + LSETUP ( L$0 , L$0end ) LC0 = P2; +L$0: + + // I0 and I2 are pointers to state + loadsym I0, state; + I2 = I0; + + // pointer to coeffs + loadsym I1, Coeff; + + R0.H = W [ I3 ++ ]; // load input value into RH0 + A0.w = R0; // A0 holds x + + P2 = 2; + LSETUP ( L$1 , L$1end ) LC1 = P2; + + // load 2 coeffs into R1 and R2 + // load state into R3 + R1 = [ I1 ++ ]; + MNOP || R2 = [ I1 ++ ] || R3 = [ I0 ++ ]; + +L$1: + + // A1=b1*s0 A0=a1*s0+x + A1 = R1.L * R3.L, A0 += R1.H * R3.L || R1 = [ I1 ++ ] || NOP; + + // A1+=b2*s1 A0+=a2*s1 + // and move scaled value in A0 (t1) into RL4 + A1 += R2.L * R3.H, R4.L = ( A0 += R2.H * R3.H ) (S2RND) || R2 = [ I1 ++ ] || NOP; + + // Advance state. before: + // R4 = uuuu t1 + // R3 = stat[1] stat[0] + // after PACKLL: + // R3 = stat[0] t1 + R5 = PACK( R3.L , R4.L ) || R3 = [ I0 ++ ] || NOP; + + // collect output into A0, and move to RL0. + // Keep output value in A0, since it is also + // the accumulator used to store the input to + // the next stage. Also, store updated state +L$1end: + R0.L = ( A0 += A1 ) || [ I2 ++ ] = R5 || NOP; + + // store output +L$0end: + W [ P1 ++ ] = R0; + + // Check results + loadsym I2, output; + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0028 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0110 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0373 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x075b ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0c00 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1064 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x13d3 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x15f2 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x16b9 ); + R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1650 ); + + pass + + .data +state: + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + + .data +Coeff: + .dw 0x7fff + .dw 0x5999 + .dw 0x4000 + .dw 0xe000 + .dw 0x7fff + .dw 0x5999 + .dw 0x4000 + .dw 0xe000 +input: + .dw 0x0028 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 +output: + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/issue103.s b/sim/testsuite/sim/bfin/issue103.s new file mode 100644 index 0000000..6244a7f --- /dev/null +++ b/sim/testsuite/sim/bfin/issue103.s @@ -0,0 +1,34 @@ +# mach: bfin + +.include "testutils.inc" + start + + A0 = 0; + A1 = 0; + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R2.H = 0xf12e; + R2.L = 0xbeaa; + R3.L = 0x00ff; + A1.w = R2; + A1.x = R3; + R0.H = 0xd136; + R0.L = 0x459d; + R1.H = 0xabd6; + R1.L = 0x9ec7; + + _DBG A1; + R5 = A1 , A0 = R1.L * R0.L (FU); + + DBGA ( R5.H , 0xffff ); + DBGA ( R5.L , 0xffff ); + + NOP; + NOP; + NOP; + NOP; + pass diff --git a/sim/testsuite/sim/bfin/issue109.s b/sim/testsuite/sim/bfin/issue109.s new file mode 100644 index 0000000..65b78b7 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue109.s @@ -0,0 +1,16 @@ +//Statement of problem... +//16-bit ashift and lshift uses a 6-bit signed magnitude, which gives a +//range from -32 to 31. test the boundary. +# mach: bfin + +.include "testutils.inc" + start + + + R1.L = 0x8000; + R0.L = -32; + R2.L = ASHIFT R1.L BY R0.L; + + DBGA ( R2.L , 0xffff ); + + pass diff --git a/sim/testsuite/sim/bfin/issue112.s b/sim/testsuite/sim/bfin/issue112.s new file mode 100644 index 0000000..e116936 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue112.s @@ -0,0 +1,38 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + A0 = 0; + A1 = 0; + R2.H = 0xfafa; + R2.L = 0xf5f6; + R3.L = 0x00ff; + A0.w = R2; + A0.x = R3; + R2.H = 0x7ebc; + R2.L = 0xd051; + R3 = 0; + A1.w = R2; + A1.x = R3; + R1.H = 0x7fff; + R1.L = 0x8000; + R0.H = 0x8000; + R0.L = 0x7fff; + A1 += R0.L * R1.L (M), R0.L = ( A0 = R0.H * R1.H ) (IH); + + _DBG A1; + R0 = A1.w; + R1 = A1.x; + DBGA ( R0.L , 0xffff ); + DBGA ( R0.H , 0x7fff ); + DBGA ( R1.L , 0 ); + + NOP; + NOP; + pass diff --git a/sim/testsuite/sim/bfin/issue113.s b/sim/testsuite/sim/bfin/issue113.s new file mode 100644 index 0000000..4bebaea --- /dev/null +++ b/sim/testsuite/sim/bfin/issue113.s @@ -0,0 +1,18 @@ +# mach: bfin + +.include "testutils.inc" + start + + A0 = 0; + R0.L = 0x10; + A0.x = R0; + + R0.L = 0x0038; + R0.H = 0x0006; + + R0.L = SIGNBITS A0; + + DBGA ( R0.L , 0xfffa ); + DBGA ( R0.H , 0x0006 ); + + pass diff --git a/sim/testsuite/sim/bfin/issue117.s b/sim/testsuite/sim/bfin/issue117.s new file mode 100644 index 0000000..00e92b7 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue117.s @@ -0,0 +1,19 @@ +# mach: bfin + +.include "testutils.inc" + start + +// issue 117 + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + A0 = 0; + A1 = 0; + R0.L = 0x0400; + R1.L = 0x0010; + R2.L = ( A0 = R0.L * R1.L ) (S2RND); + + DBGA ( R2.L , 0x1 ); + pass diff --git a/sim/testsuite/sim/bfin/issue118.s b/sim/testsuite/sim/bfin/issue118.s new file mode 100644 index 0000000..bc455b3 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue118.s @@ -0,0 +1,41 @@ +# mach: bfin + +.include "testutils.inc" + start + + +// issue 118 + + R0 = 1; + R1 = 0; + A0.x = R1; + A0.w = R0; + + A0 = - A0; + + _DBG A0; + _DBG ASTAT; + +//R0 = ASTAT; +//DBGA ( R0.L , 0x2 ); + + cc = az; + r0 = cc; + dbga( r0.l, 0); + cc = an; + r0 = cc; + dbga( r0.l, 1); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + pass diff --git a/sim/testsuite/sim/bfin/issue119.s b/sim/testsuite/sim/bfin/issue119.s new file mode 100644 index 0000000..ade8818 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue119.s @@ -0,0 +1,26 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R0.L = -32768; + R0.H = 32767; + R1.L = 32767; + R1.H = -32768; + R2.H = (A1 = R0.L * R1.H) (M), R2.L = (A0 = R0.L * R1.L) (TFU); + + _DBG R2; + DBGA ( R2.L , 0x3fff ); + DBGA ( R2.H , 0xc000 ); + + R3 = ( A1 = R0.L * R1.H ) (M), R2 = ( A0 = R0.L * R1.L ) (FU); + + _DBG R3; + DBGA ( R3.L , 0 ); + DBGA ( R3.H , 0xc000 ); + + pass diff --git a/sim/testsuite/sim/bfin/issue121.s b/sim/testsuite/sim/bfin/issue121.s new file mode 100644 index 0000000..7e609cd --- /dev/null +++ b/sim/testsuite/sim/bfin/issue121.s @@ -0,0 +1,40 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + R0.L = 32767; + R0.H = 32767; + R1.L = -32768; + R1.H = -32768; + R0.L = R0 + R1 (RND12); + + _DBG R0; + _DBG ASTAT; +//R1 = ASTAT; +//_DBG R1; + +//DBGA ( R1.H , 0x0 ); +//DBGA ( R1.L , 0x0001 ); + cc = az; + r0 = cc; + dbga( r0.l, 1); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + pass diff --git a/sim/testsuite/sim/bfin/issue123.s b/sim/testsuite/sim/bfin/issue123.s new file mode 100644 index 0000000..9f40c3f --- /dev/null +++ b/sim/testsuite/sim/bfin/issue123.s @@ -0,0 +1,20 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0.L = 0x7bb8; + R0.H = 0x8d5e; + R4.L = 0x7e1c; + R4.H = 0x9e22; +// end load regs and acc; + R6.H = R4.H * R0.L (M), R6.L = R4.L * R0.H (ISS2); + + _DBG R6; + + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x8000 ); + +//------------- + + pass diff --git a/sim/testsuite/sim/bfin/issue124.s b/sim/testsuite/sim/bfin/issue124.s new file mode 100644 index 0000000..b28f141 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue124.s @@ -0,0 +1,26 @@ +# mach: bfin + +.include "testutils.inc" + start + +// issue 124 + + R0 = 0; + R1.L = 0x80; + + A0.w = R0; + A0.x = R1; + + A1.w = R0; + A1.x = R1; + + _DBG A0; + _DBG A1; + + R5 = ( A0 += A1 ); + + _DBG A0; + R7 = A0.w; DBGA ( R7.H , 0 ); DBGA ( R7.L , 0 ); + R7 = A0.x; DBGA ( R7.L , 0xff80 ); + + pass diff --git a/sim/testsuite/sim/bfin/issue125.s b/sim/testsuite/sim/bfin/issue125.s new file mode 100644 index 0000000..826bf7f --- /dev/null +++ b/sim/testsuite/sim/bfin/issue125.s @@ -0,0 +1,75 @@ +# mach: bfin + +.include "testutils.inc" + start + + A0 = 0; + A1 = 0; + R0 = -1; + R1 = 0; + R1.L = 0x007f; + A0.w = R0; + A0.x = R1; + A1.w = R0; + A1.x = R1; + _DBG A0; + _DBG A1; + _DBG astat; + A0 += A1; + + _DBG A0; +// _DBG ASTAT; +// R0 = ASTAT; +// _DBG R0; +// DBGA ( R0.L , 0x0 ); +// DBGA ( R0.H , 0x3 ); + cc = az; + r0 = cc; + dbga( r0.l, 0); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 1); + cc = av0s; + r0 = cc; + dbga( r0.l, 1); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + A1 = 0; + _DBG A0; + A0 += A1; + + _DBG A0; +// _DBG ASTAT; +// R0 = ASTAT; +// _DBG R0; + +// DBGA ( R0.L , 0 ); +// DBGA ( R0.H , 2 ); + cc = az; + r0 = cc; + dbga( r0.l, 0); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 1); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + pass diff --git a/sim/testsuite/sim/bfin/issue126.s b/sim/testsuite/sim/bfin/issue126.s new file mode 100644 index 0000000..ff15bac --- /dev/null +++ b/sim/testsuite/sim/bfin/issue126.s @@ -0,0 +1,19 @@ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + P1 = R0; + P2 = R0; + + R0 = R0; + P1 = ( P1 + P0 ) << 2; + P2 = ( P2 + P0 ) << 1; + + _DBG ASTAT; + R5 = ASTAT; + DBGA ( R5.H , 0 ); DBGA ( R5.L , 0 ); + + pass diff --git a/sim/testsuite/sim/bfin/issue127.s b/sim/testsuite/sim/bfin/issue127.s new file mode 100644 index 0000000..811bc37 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue127.s @@ -0,0 +1,35 @@ +# mach: bfin + +.include "testutils.inc" + start + +// load acc with values; + R0.L = 0x5d8c; + R0.H = 0x90c4; + A0.w = R0; + R0.L = 0x8308; + A0.x = R0; + R0.L = 0x32da; + R0.H = 0xa6ec; + A1.w = R0; + R0.L = 0x1772; + A1.x = R0; +// load regs with values; + R0.L = 0x83de; + R0.H = 0x7070; + R1.L = 0x8b86; + R1.H = 0x85ac; + R2.L = 0x2398; + R2.H = 0x3adc; + R3.L = 0x1480; + R3.H = 0x7f90; +// end load regs and acc; + SAA ( R1:0 , R3:2 ) (R); + + _DBG A0; + _DBG A1; + + R0 = A0.x; DBGA ( R0.L , 0 ); + R0 = A1.x; DBGA ( R0.L , 0 ); + + pass diff --git a/sim/testsuite/sim/bfin/issue129.s b/sim/testsuite/sim/bfin/issue129.s new file mode 100644 index 0000000..f9653a8 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue129.s @@ -0,0 +1,36 @@ +# Blackfin testcase for PREGS and BREV +# mach: bfin + + .include "testutils.inc" + + start + +// issue 129 + + P0.L = 0x0000; + P0.H = 0x8000; + + P4.L = 0x0000; + P4.H = 0x8000; + + P4 += P0 (BREV); + + R0 = P4; + DBGA ( R0.H , 0x4000 ); + DBGA ( R0.L , 0 ); + +//-------------- + + P0.L = 0x0000; + P0.H = 0xE000; + + P4.L = 0x1f09; + P4.H = 0x9008; + + P4 += P0 (BREV); + + R0 = P4; + DBGA ( R0.H , 0x0808 ); + DBGA ( R0.L , 0x1f09 ); + + pass diff --git a/sim/testsuite/sim/bfin/issue139.S b/sim/testsuite/sim/bfin/issue139.S new file mode 100644 index 0000000..8df28ba --- /dev/null +++ b/sim/testsuite/sim/bfin/issue139.S @@ -0,0 +1,108 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + ASTAT = R0; + R0.L = 0x33; + R0.H = 0x55; + R1.L = 0x66; + R1.H = 0x77; + R7 = R1 +|+ R0, R6 = R1 -|- R0 (SCO , ASR); + + _DBG R7; + CHECKREG R7, 0x0066004c; + CHECKREG R6, 0x00190011; + R7 = ASTAT + CHECKREG R7, 0; + +//----------------------- + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + R0.L = 0x33; + R0.H = 0x55; + R1.L = 0x66; + R1.H = 0x77; + R3 = R1 +|+ R0, R2 = R1 -|- R0 (ASR); + + R7 = ASTAT; + CHECKREG R7, 0; + +//----------------------- + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + R0.L = 0x33; + R0.H = 0x55; + R1.L = 0x66; + R1.H = 0x77; + R5 = R1 +|+ R0, R4 = R1 -|- R0 (CO , ASR); + + R7 = ASTAT; + CHECKREG R7, 0; + +//----------------------- + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + R0.L = 0x33; + R0.H = 0x55; + R1.L = 0x66; + R1.H = 0x77; + R3 = R1 +|+ R0, R2 = R1 -|- R0 (ASL); + CHECKREG R3, 0x01980132; + CHECKREG R2, 0x00440066; + + R7 = ASTAT; + CHECKREG R7, 0; + +//----------------------- + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R6 = 0; + R7 = 0; + R0.L = 0x33; + R0.H = 0x55; + R1.L = 0x7fff; + R1.H = 0x77; + R3 = R1 +|+ R0, R2 = R1 -|- R0 (S , ASL); + CHECKREG R3, 0x01987fff; + CHECKREG R2, 0x00447fff; + + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY); + + pass diff --git a/sim/testsuite/sim/bfin/issue140.S b/sim/testsuite/sim/bfin/issue140.S new file mode 100644 index 0000000..df27517 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue140.S @@ -0,0 +1,22 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + + R6.L = -32768; + R6.H = -32768; + R1.L = -32768; + R1.H = -32768; + + R4 = R6.L * R1.H; + + _DBG ASTAT; + + R7 = ASTAT; + CHECKREG R7, (_VS|_V|_V_COPY); + + pass diff --git a/sim/testsuite/sim/bfin/issue142.s b/sim/testsuite/sim/bfin/issue142.s new file mode 100644 index 0000000..be290b5 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue142.s @@ -0,0 +1,34 @@ +# mach: bfin + +.include "testutils.inc" + start + +// load acc with values; + imm32 R0, 0x7d647b42; + A0.w = R0; + R0 = 0x0000 (Z); + A0.x = R0; + + imm32 R0, 0x7be27f50; + A1.w = R0; + R0 = 0x0000 (Z); + A1.x = R0; + +// load regs with values; + I1 = 0 (X); + I0 = 1 (X); + imm32 R2, 0xefef1212; + imm32 R3, 0xf23c0189; + + SAA ( R3:2 , R3:2 ) (R); + + R0 = A0.w + CHECKREG R0, 0x7d9f7bca; + R0 = A0.x + CHECKREG R0, 0; + R1 = A1.w; + CHECKREG R1, 0x7cc28006; + R1 = A1.x; + CHECKREG R1, 0; + + pass diff --git a/sim/testsuite/sim/bfin/issue144.s b/sim/testsuite/sim/bfin/issue144.s new file mode 100644 index 0000000..3c029a3 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue144.s @@ -0,0 +1,31 @@ +# mach: bfin + +.include "testutils.inc" + start + + a0=0; + R0.L = 1; + R0.H = 0; + R0 *= R0; + _DBG R0; + _DBG A0; + + R7 = A0.w; + DBGA ( R7.H , 0 ); DBGA ( R7.L , 0 ); + + R0.L = -1; + R0.H = 32767; + + _DBG R0; + + a0=0; + R0 *= R0; + + _DBG R0; + _DBG A0; + R7 = A0.w; + DBGA ( R7.H , 0 ); DBGA ( R7.L , 0 ); + R7 = A0.x; + DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/sim/bfin/issue146.S b/sim/testsuite/sim/bfin/issue146.S new file mode 100644 index 0000000..b14e78c --- /dev/null +++ b/sim/testsuite/sim/bfin/issue146.S @@ -0,0 +1,32 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + +// razor issue 146 + + A0 = 0; + A1 = 0; + R0 = 0; + ASTAT = R0; + R1 = 0; + R0.L = 0x891b; + R0.H = 0x8537; + R1.L = 0xab2d; + R1.H = 0x3759; + A0 = R0; + A1 = R1; + + _DBG A0; + _DBG A1; + + R3 = A1 + A0, R7 = A1 - A0 (S); + _DBG R3; + _DBG R7; + + _DBG ASTAT; + R0 = ASTAT; + CHECKREG R0, (_VS|_V|_V_COPY|_AN); + + pass diff --git a/sim/testsuite/sim/bfin/issue175.s b/sim/testsuite/sim/bfin/issue175.s new file mode 100644 index 0000000..3073823 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue175.s @@ -0,0 +1,34 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 0; + ASTAT = R0; + imm32 R1, 0x80007fff; + imm32 R0, 0x00010001; + R0 = R1 +|+ R0, R2 = R1 -|- R0 (S , ASL); + _DBG R0; + _DBG R2; + CHECKREG R0, 0x80007fff; + CHECKREG R2, 0x80007fff; + + R0 = ASTAT; + _dbg r0; + DBGA ( R0.L , 0x000a ); + DBGA ( R0.H , 0x0300 ); + + R0 = 0; + R1 = 0; + R4 = 0; + ASTAT = R0; + R4 = R1 +|+ R0, R0 = R1 -|- R0 (S , ASL); + _DBG R4; + _DBG R0; + R7 = ASTAT; + _DBG R7; + _DBG ASTAT; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + + pass diff --git a/sim/testsuite/sim/bfin/issue205.s b/sim/testsuite/sim/bfin/issue205.s new file mode 100644 index 0000000..44cb1e0 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue205.s @@ -0,0 +1,66 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0; R1 = 0; R2 = 0; R3 = 0; R4 = 0; R5 = 0; R6 = 0; R7 = 0; + P0 = 0; P1 = 0; P2 = 0; P4 = 0; P5 = 0; + I0 = 0 (X); I1 = 0 (X); I2 = 0 (X); I3 = 0 (X); + M0 = 0 (X); M1 = 0 (X); M2 = 0 (X); M3 = 0 (X); + L0 = 0 (X); L1 = 0 (X); L2 = 0 (X); L3 = 0 (X); + B0 = 0 (X); B1 = 0 (X); B2 = 0 (X); B3 = 0 (X); + + R0 = -1; + R1 = 0x1234 (X); + R2 = -2000 (X); + R3 = 2000 (X); + R4 = 0; + R5 = 1; + R6 = 5555 (X); + R7 = -1000 (X); + + loadsym P1, tmp0; + loadsym P2, tmp1; + loadsym P4, tmp2; + + I1 = P1; + I2 = P2; + I3 = P4; + + + R0.L = 0x0017; + R0.H = 0xffff; + R0.L = EXPADJ( R2 , R1.L ) || [ P2 ] = R0 || NOP; + R6 = [ P2 ]; + DBGA ( R6.L , 0x17 ); + DBGA ( R6.H , 0xffff ); + + DBGA ( R0.L , 0x1234 ); + DBGA ( R0.H , 0xffff ); + + pass + + .data +tmp0: + .dd 0x12345678 // 0x1000 + .dd 0x10101010 // 0x1004 + .dd 0x55555555 // 0x1008 + .dd 0xaaaaaaaa // 0x100c + .dd 0xffffffff // 0x1010 + + .data +tmp1: + .dd 0xabcdefef // 0x2000 + .dd 0x12121212 // 0x2004 + .dd 0x45454545 // 0x2008 + .dd 0xabababab // 0x200c + .dd 0x0f0f0f0f // 0x2010 + + .data +tmp2: + .dd 0xff00ff00 // 0x3000 + .dd 0x02020202 // 0x3004 + .dd 0x4f4f4f45 // 0x3008 + .dd 0xafafafaf // 0x300c + .dd 0x1f1f1f1f // 0x3010 diff --git a/sim/testsuite/sim/bfin/issue257.s b/sim/testsuite/sim/bfin/issue257.s new file mode 100644 index 0000000..01f0396 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue257.s @@ -0,0 +1,28 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 0; + R1 = 0; + R2 = 0; + R0.H = 0xfffe; + R0.L = 0x9be8; + R1.L = 0xeb53; + R2.H = R0 - R1 (RND20); + + _DBG R2; + _DBG ASTAT; + DBGA ( R2.H , 0 ); + + R0 = ASTAT; +//DBGA ( R0.L , 1 ); + cc = az; + r0 = cc; + dbga( r0.l, 1); + cc = an; + r0 = cc; + dbga( r0.l, 0); + + pass diff --git a/sim/testsuite/sim/bfin/issue272.S b/sim/testsuite/sim/bfin/issue272.S new file mode 100644 index 0000000..ee8ec38 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue272.S @@ -0,0 +1,23 @@ +// When the RND12 instruction produces large negative results, the AV0 flag is +// should not be set. +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + R0.H = 0xcef4; + R0.L = 0x3ed6; + R1.H = 0x56f4; + R1.L = 0x417a; + R2.H = R0 - R1 (RND12); + + _DBG ASTAT; + R0 = ASTAT; + CHECKREG R0, (_VS|_V|_V_COPY|_AN); + CHECKREG R2, 0x80000000; + + pass diff --git a/sim/testsuite/sim/bfin/issue83.s b/sim/testsuite/sim/bfin/issue83.s new file mode 100644 index 0000000..2474d4b --- /dev/null +++ b/sim/testsuite/sim/bfin/issue83.s @@ -0,0 +1,93 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0.H = -32768; + R0.L = 0; + R0 >>= 0x1; + + _DBG R0; + R7 = ASTAT; + _DBG R7; + +//DBGA ( R7.H , 0x0000 ); +//DBGA ( R7.L , 0x0000 ); + cc = az; + r0 = cc; + dbga( r0.l, 0); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + R0.H = 0; + R0.L = 1; + R0 <<= 0x1f; + + _DBG R0; + R7 = ASTAT; + _DBG R7; +//DBGA ( R7.H , 0x0000 ); +//DBGA ( R7.L , 0x0002 ); + cc = az; + r0 = cc; + dbga( r0.l, 0); + cc = an; + r0 = cc; + dbga( r0.l, 1); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + R1.L = -1; + R1.H = 32767; + R0 = 31; + R1 >>= R0; + + _DBG R1; + R7 = ASTAT; + _DBG R7; +//DBGA ( R7.H , 0x0000 ); +//DBGA ( R7.L , 0x0001 ); + cc = az; + r0 = cc; + dbga( r0.l, 1); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + pass diff --git a/sim/testsuite/sim/bfin/issue89.s b/sim/testsuite/sim/bfin/issue89.s new file mode 100644 index 0000000..24d0517 --- /dev/null +++ b/sim/testsuite/sim/bfin/issue89.s @@ -0,0 +1,30 @@ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + R2.L = 0x000f; + R2.H = 0x038c; + _DBG R2; + + R7.L = 0x007c; + R7.H = 0x0718; + A0 = 0; + A0.w = R7; + _DBG A0; + + A0 = ROT A0 BY R2.L; + + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x003e ); + DBGA ( R4.L , 0x0001 ); + DBGA ( R5.H , 0xffff ); + DBGA ( R5.L , 0xff8c ); + + pass diff --git a/sim/testsuite/sim/bfin/l0.s b/sim/testsuite/sim/bfin/l0.s new file mode 100644 index 0000000..88fcb59 --- /dev/null +++ b/sim/testsuite/sim/bfin/l0.s @@ -0,0 +1,137 @@ +// simple test to ensure that we can load data from memory. +# mach: bfin + +.include "testutils.inc" + start + + loadsym P0, tab; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + R6 = [ P0 ++ ]; + R7 = [ P0 ++ ]; + + DBGA ( R0.H , 0x1111 ); + DBGA ( R1.H , 0x2222 ); + DBGA ( R2.H , 0x3333 ); + DBGA ( R3.H , 0x4444 ); + DBGA ( R4.H , 0x5555 ); + DBGA ( R5.H , 0x6666 ); + DBGA ( R6.H , 0x7777 ); + DBGA ( R7.H , 0x8888 ); + + loadsym P0, tab2; + + R0 = W [ P0 ++ ] (Z); + DBGA ( R0.L , 0x1111 ); + + R1 = W [ P0 ++ ] (Z); + DBGA ( R1.L , 0x8888 ); + + R2 = W [ P0 ++ ] (Z); + DBGA ( R2.L , 0x2222 ); + + R3 = W [ P0 ++ ] (Z); + DBGA ( R3.L , 0x7777 ); + + R4 = W [ P0 ++ ] (Z); + DBGA ( R4.L , 0x3333 ); + + R5 = W [ P0 ++ ] (Z); + DBGA ( R5.L , 0x6666 ); + + R0 = B [ P0 ++ ] (Z); + DBGA ( R0.L , 0x44 ); + R1 = B [ P0 ++ ] (Z); + DBGA ( R1.L , 0x44 ); + R2 = B [ P0 ++ ] (Z); + DBGA ( R2.L , 0x55 ); + R3 = B [ P0 ++ ] (Z); + DBGA ( R3.L , 0x55 ); + + R0 = B [ P0 ++ ] (X); + DBGA ( R0.L , 0x55 ); + + R1 = B [ P0 ++ ] (X); + DBGA ( R1.L , 0x55 ); + + R0 = W [ P0 ++ ] (X); + DBGA ( R0.L , 0x4444 ); + + R1 = [ P0 ++ ]; + DBGA ( R1.L , 0x6666 ); + DBGA ( R1.H , 0x3333 ); + + P1 = [ P0 ++ ]; + R0 = P1; + DBGA ( R0.L , 0x7777 ); + DBGA ( R0.H , 0x2222 ); + + P1 = [ P0 ++ ]; + R0 = P1; + DBGA ( R0.L , 0x8888 ); + DBGA ( R0.H , 0x1111 ); + + loadsym P5, tab3; + + R0 = B [ P5 ++ ] (X); + DBGA ( R0.H , 0 ); + DBGA ( R0.L , 0 ); + + R0 = B [ P5 ++ ] (X); + DBGA ( R0.H , 0xffff ); + DBGA ( R0.L , 0xffff ); + + R1 = W [ P5 ++ ] (X); + DBGA ( R1.H , 0xffff ); + DBGA ( R1.L , 0xffff ); + + pass + + .data +tab: + .dw 0 + .dw 0x1111 + .dw 0 + .dw 0x2222 + .dw 0 + .dw 0x3333 + .dw 0 + .dw 0x4444 + .dw 0 + .dw 0x5555 + .dw 0 + .dw 0x6666 + .dw 0 + .dw 0x7777 + .dw 0 + .dw 0x8888 + .dw 0 + .dw 0 + .dw 0 + .dw 0 + +tab2: + .dw 0x1111 + .dw 0x8888 + .dw 0x2222 + .dw 0x7777 + .dw 0x3333 + .dw 0x6666 + .dw 0x4444 + .dw 0x5555 + .dw 0x5555 + .dw 0x4444 + .dw 0x6666 + .dw 0x3333 + .dw 0x7777 + .dw 0x2222 + .dw 0x8888 + .dw 0x1111 + +tab3: + .dw 0xff00 + .dw 0xffff diff --git a/sim/testsuite/sim/bfin/l0shift.s b/sim/testsuite/sim/bfin/l0shift.s new file mode 100644 index 0000000..3f5dc2c --- /dev/null +++ b/sim/testsuite/sim/bfin/l0shift.s @@ -0,0 +1,13 @@ +# mach: bfin + +.include "testutils.inc" + start + + + r5 = 0; + r2.L = 0xadbd; + r2.h = 0xfedc; + r5 = r2 >> 0; + dbga (r5.l, 0xadbd); + dbga (r5.h, 0xfedc); + pass diff --git a/sim/testsuite/sim/bfin/l2_loop.s b/sim/testsuite/sim/bfin/l2_loop.s new file mode 100644 index 0000000..a6cde54 --- /dev/null +++ b/sim/testsuite/sim/bfin/l2_loop.s @@ -0,0 +1,28 @@ +# mach: bfin + +.include "testutils.inc" + start + + p0=10; + loadsym i0, foo; + + R2 = i0; + r0.l = 0x5678; + r0.h = 0x1234; + + lsetup(lstart, lend) lc0=p0; + +lstart: + [i0++] = r0; +lend: + [i0++] = r0; + + r0=i0; + R0 = R0 - R2; + dbga(r0.l, 0x0050); + + pass + + .data +foo: + .space (0x100) diff --git a/sim/testsuite/sim/bfin/link-2.s b/sim/testsuite/sim/bfin/link-2.s new file mode 100644 index 0000000..ac711c6 --- /dev/null +++ b/sim/testsuite/sim/bfin/link-2.s @@ -0,0 +1,24 @@ +# Blackfin testcase for link/unlink instructions +# mach: bfin + + .include "testutils.inc" + + start + + /* Make sure size arg to LINK works */ + R0 = SP; + LINK 0x20; + R1 = SP; + R1 += 0x8 + 0x20; + CC = R1 == R0; + IF !CC JUMP 1f; + + /* Make sure UNLINK restores old SP */ + UNLINK + R1 = SP; + CC = R1 == R0; + IF !CC JUMP 1f; + + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/link.s b/sim/testsuite/sim/bfin/link.s new file mode 100644 index 0000000..c92ae1b --- /dev/null +++ b/sim/testsuite/sim/bfin/link.s @@ -0,0 +1,67 @@ +# Blackfin testcase for link/unlink instructions +# mach: bfin + + .include "testutils.inc" + + start + + /* give FP/RETS known/different values */ + R7.H = 0xdead; + R7.L = 0x1234; + RETS = R7; + R6 = R7; + R6 += 0x23; + FP = R6; + + /* SP should have moved by -8 bytes (to push FP/RETS) */ + R0 = SP; + LINK 0; + R1 = SP; + R1 += 8; + CC = R0 == R1; + IF !CC JUMP 1f; + + /* FP should now have the same value as SP */ + R1 = SP; + R2 = FP; + CC = R1 == R2; + IF !CC JUMP 1f; + + /* make sure FP/RETS on the stack have our known values */ + R1 = [SP]; + CC = R1 == R6; + IF !CC JUMP 1f; + + R1 = [SP + 4]; + CC = R1 == R7; + IF !CC JUMP 1f; + + /* UNLINK should: + * assign SP to current FP + * adjust SP by -8 bytes + * restore RETS/FP from the stack + */ + R4 = 0; + RETS = R4; + R0 = SP; + UNLINK; + + /* Check new SP */ + R1 = SP; + R1 += -0x8; + CC = R1 == R0; + IF !CC JUMP 1f; + + /* Check restored RETS */ + R1 = RETS; + CC = R1 == R7; + IF !CC JUMP 1f; + + /* Check restored FP */ + R1 = FP; + CC = R1 == R6; + IF !CC JUMP 1f; + + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/lmu_cplb_multiple0.S b/sim/testsuite/sim/bfin/lmu_cplb_multiple0.S new file mode 100644 index 0000000..9399c43 --- /dev/null +++ b/sim/testsuite/sim/bfin/lmu_cplb_multiple0.S @@ -0,0 +1,2678 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple0/lmu_cplb_multiple0.dsp +// Description: Multiple CPLB Hit exceptions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +//------------------------------------- + +// Test LMU/CPLB exceptions + +// Basic outline: +// Set exception handler +// program CPLB Entries +// Enable CPLB in DMEM_CNTL +// perform access +// verify exception occurred + +CHECK_INIT(p5, 0xEFFFFFFC); + +//------------------------- +// Zero the CPLB Address and Data regs. + + LD32(p0, DCPLB_ADDR0); + R0 = 0; + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + LD32(p0, DCPLB_DATA0); + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + // Now set the CPLB entries we will need + + + + + // Data area for the desired error + WR_MMR(DCPLB_ADDR0, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR1, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR2, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR3, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR4, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR5, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR6, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR7, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR8, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR9, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR10, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR11, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR12, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR13, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR14, 0x10000000, p0, r0); + + // MMR space + WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); + WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + WR_MMR_LABEL(EVT15, int_15, p0, r1); + WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); + WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); + CSYNC; + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + + // But first raise interrupt 15 so we can do one test + // in supervisor mode. + RAISE 15; + NOP; + + RTI; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + +handler: + // generic protection exception handler + // Inputs: + // p2: addr of CPLB entry to be modified ( current test) + // + // Outputs: + // r4: SEQSTAT + // r5: DCPLB_FAULT_ADDR + // r6: DCPLB_STATUS + // r7: RETX (instruction addr where exception occurred) + + + R4 = SEQSTAT; // Get exception cause + R4 <<= 24; // Clear HWERRCAUSE + SFTRESET + R4 >>= 24; + + // read data addr which caused exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r5); + + RD_MMR(DCPLB_STATUS, p0, r6); + + R7 = RETX; // get address of excepting instruction + + // disable the offending CPLB entries + R2 = 0; + [ P2 ] = R2; + + CSYNC; + + // return from exception and re-execute offending instruction + RTX; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +int_15: + // Interrupt 15 handler - test will run in supervisor mode + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x41C6 (Z); + LD32(p2, DCPLB_DATA1); + +X0_1: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB1)); + CHECKREG_SYM(r7, X0_1, r0); // RETX should be value of X0_1 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x167E (Z); + LD32(p2, DCPLB_DATA2); + +X0_2: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB2)); + CHECKREG_SYM(r7, X0_2, r0); // RETX should be value of X0_2 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2781 (Z); + LD32(p2, DCPLB_DATA3); + +X0_3: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB3)); + CHECKREG_SYM(r7, X0_3, r0); // RETX should be value of X0_3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x446B (Z); + LD32(p2, DCPLB_DATA4); + +X0_4: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB4)); + CHECKREG_SYM(r7, X0_4, r0); // RETX should be value of X0_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x794B (Z); + LD32(p2, DCPLB_DATA5); + +X0_5: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB5)); + CHECKREG_SYM(r7, X0_5, r0); // RETX should be value of X0_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x15FB (Z); + LD32(p2, DCPLB_DATA6); + +X0_6: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB6)); + CHECKREG_SYM(r7, X0_6, r0); // RETX should be value of X0_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x59E2 (Z); + LD32(p2, DCPLB_DATA7); + +X0_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB7)); + CHECKREG_SYM(r7, X0_7, r0); // RETX should be value of X0_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1CFB (Z); + LD32(p2, DCPLB_DATA8); + +X0_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB8)); + CHECKREG_SYM(r7, X0_8, r0); // RETX should be value of X0_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3F54 (Z); + LD32(p2, DCPLB_DATA9); + +X0_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB9)); + CHECKREG_SYM(r7, X0_9, r0); // RETX should be value of X0_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0FF6 (Z); + LD32(p2, DCPLB_DATA10); + +X0_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB10)); + CHECKREG_SYM(r7, X0_10, r0); // RETX should be value of X0_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0ABD (Z); + LD32(p2, DCPLB_DATA11); + +X0_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB11)); + CHECKREG_SYM(r7, X0_11, r0); // RETX should be value of X0_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x31DF (Z); + LD32(p2, DCPLB_DATA12); + +X0_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB12)); + CHECKREG_SYM(r7, X0_12, r0); // RETX should be value of X0_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x237C (Z); + LD32(p2, DCPLB_DATA13); + +X0_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB13)); + CHECKREG_SYM(r7, X0_13, r0); // RETX should be value of X0_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2F1C (Z); + LD32(p2, DCPLB_DATA14); + +X0_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB14)); + CHECKREG_SYM(r7, X0_14, r0); // RETX should be value of X0_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7DE1 (Z); + LD32(p2, DCPLB_DATA2); + +X1_2: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB2)); + CHECKREG_SYM(r7, X1_2, r0); // RETX should be value of X1_2 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4487 (Z); + LD32(p2, DCPLB_DATA3); + +X1_3: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB3)); + CHECKREG_SYM(r7, X1_3, r0); // RETX should be value of X1_3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6201 (Z); + LD32(p2, DCPLB_DATA4); + +X1_4: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB4)); + CHECKREG_SYM(r7, X1_4, r0); // RETX should be value of X1_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x52BF (Z); + LD32(p2, DCPLB_DATA5); + +X1_5: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB5)); + CHECKREG_SYM(r7, X1_5, r0); // RETX should be value of X1_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6231 (Z); + LD32(p2, DCPLB_DATA6); + +X1_6: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB6)); + CHECKREG_SYM(r7, X1_6, r0); // RETX should be value of X1_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x63DE (Z); + LD32(p2, DCPLB_DATA7); + +X1_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB7)); + CHECKREG_SYM(r7, X1_7, r0); // RETX should be value of X1_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6956 (Z); + LD32(p2, DCPLB_DATA8); + +X1_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB8)); + CHECKREG_SYM(r7, X1_8, r0); // RETX should be value of X1_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1372 (Z); + LD32(p2, DCPLB_DATA9); + +X1_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB9)); + CHECKREG_SYM(r7, X1_9, r0); // RETX should be value of X1_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x500F (Z); + LD32(p2, DCPLB_DATA10); + +X1_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB10)); + CHECKREG_SYM(r7, X1_10, r0); // RETX should be value of X1_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2847 (Z); + LD32(p2, DCPLB_DATA11); + +X1_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB11)); + CHECKREG_SYM(r7, X1_11, r0); // RETX should be value of X1_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2C67 (Z); + LD32(p2, DCPLB_DATA12); + +X1_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB12)); + CHECKREG_SYM(r7, X1_12, r0); // RETX should be value of X1_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7566 (Z); + LD32(p2, DCPLB_DATA13); + +X1_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB13)); + CHECKREG_SYM(r7, X1_13, r0); // RETX should be value of X1_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4287 (Z); + LD32(p2, DCPLB_DATA14); + +X1_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB14)); + CHECKREG_SYM(r7, X1_14, r0); // RETX should be value of X1_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3359 (Z); + LD32(p2, DCPLB_DATA3); + +X2_3: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB3)); + CHECKREG_SYM(r7, X2_3, r0); // RETX should be value of X2_3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4DAA (Z); + LD32(p2, DCPLB_DATA4); + +X2_4: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB4)); + CHECKREG_SYM(r7, X2_4, r0); // RETX should be value of X2_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6488 (Z); + LD32(p2, DCPLB_DATA5); + +X2_5: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB5)); + CHECKREG_SYM(r7, X2_5, r0); // RETX should be value of X2_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x773C (Z); + LD32(p2, DCPLB_DATA6); + +X2_6: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB6)); + CHECKREG_SYM(r7, X2_6, r0); // RETX should be value of X2_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6F59 (Z); + LD32(p2, DCPLB_DATA7); + +X2_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB7)); + CHECKREG_SYM(r7, X2_7, r0); // RETX should be value of X2_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6EEA (Z); + LD32(p2, DCPLB_DATA8); + +X2_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB8)); + CHECKREG_SYM(r7, X2_8, r0); // RETX should be value of X2_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5656 (Z); + LD32(p2, DCPLB_DATA9); + +X2_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB9)); + CHECKREG_SYM(r7, X2_9, r0); // RETX should be value of X2_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6113 (Z); + LD32(p2, DCPLB_DATA10); + +X2_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB10)); + CHECKREG_SYM(r7, X2_10, r0); // RETX should be value of X2_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4A7B (Z); + LD32(p2, DCPLB_DATA11); + +X2_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB11)); + CHECKREG_SYM(r7, X2_11, r0); // RETX should be value of X2_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x31D2 (Z); + LD32(p2, DCPLB_DATA12); + +X2_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB12)); + CHECKREG_SYM(r7, X2_12, r0); // RETX should be value of X2_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2D85 (Z); + LD32(p2, DCPLB_DATA13); + +X2_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB13)); + CHECKREG_SYM(r7, X2_13, r0); // RETX should be value of X2_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x19A1 (Z); + LD32(p2, DCPLB_DATA14); + +X2_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB14)); + CHECKREG_SYM(r7, X2_14, r0); // RETX should be value of X2_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x69D8 (Z); + LD32(p2, DCPLB_DATA4); + +X3_4: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB4)); + CHECKREG_SYM(r7, X3_4, r0); // RETX should be value of X3_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x353C (Z); + LD32(p2, DCPLB_DATA5); + +X3_5: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB5)); + CHECKREG_SYM(r7, X3_5, r0); // RETX should be value of X3_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3B54 (Z); + LD32(p2, DCPLB_DATA6); + +X3_6: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB6)); + CHECKREG_SYM(r7, X3_6, r0); // RETX should be value of X3_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7D55 (Z); + LD32(p2, DCPLB_DATA7); + +X3_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB7)); + CHECKREG_SYM(r7, X3_7, r0); // RETX should be value of X3_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x102F (Z); + LD32(p2, DCPLB_DATA8); + +X3_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB8)); + CHECKREG_SYM(r7, X3_8, r0); // RETX should be value of X3_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1B37 (Z); + LD32(p2, DCPLB_DATA9); + +X3_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB9)); + CHECKREG_SYM(r7, X3_9, r0); // RETX should be value of X3_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7AAE (Z); + LD32(p2, DCPLB_DATA10); + +X3_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB10)); + CHECKREG_SYM(r7, X3_10, r0); // RETX should be value of X3_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5E65 (Z); + LD32(p2, DCPLB_DATA11); + +X3_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB11)); + CHECKREG_SYM(r7, X3_11, r0); // RETX should be value of X3_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x345B (Z); + LD32(p2, DCPLB_DATA12); + +X3_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB12)); + CHECKREG_SYM(r7, X3_12, r0); // RETX should be value of X3_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x63DA (Z); + LD32(p2, DCPLB_DATA13); + +X3_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB13)); + CHECKREG_SYM(r7, X3_13, r0); // RETX should be value of X3_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6102 (Z); + LD32(p2, DCPLB_DATA14); + +X3_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB14)); + CHECKREG_SYM(r7, X3_14, r0); // RETX should be value of X3_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7A79 (Z); + LD32(p2, DCPLB_DATA5); + +X4_5: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB5)); + CHECKREG_SYM(r7, X4_5, r0); // RETX should be value of X4_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0398 (Z); + LD32(p2, DCPLB_DATA6); + +X4_6: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB6)); + CHECKREG_SYM(r7, X4_6, r0); // RETX should be value of X4_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x28CC (Z); + LD32(p2, DCPLB_DATA7); + +X4_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB7)); + CHECKREG_SYM(r7, X4_7, r0); // RETX should be value of X4_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x60E3 (Z); + LD32(p2, DCPLB_DATA8); + +X4_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB8)); + CHECKREG_SYM(r7, X4_8, r0); // RETX should be value of X4_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1F1A (Z); + LD32(p2, DCPLB_DATA9); + +X4_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB9)); + CHECKREG_SYM(r7, X4_9, r0); // RETX should be value of X4_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4B76 (Z); + LD32(p2, DCPLB_DATA10); + +X4_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB10)); + CHECKREG_SYM(r7, X4_10, r0); // RETX should be value of X4_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x058E (Z); + LD32(p2, DCPLB_DATA11); + +X4_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB11)); + CHECKREG_SYM(r7, X4_11, r0); // RETX should be value of X4_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7A5F (Z); + LD32(p2, DCPLB_DATA12); + +X4_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB12)); + CHECKREG_SYM(r7, X4_12, r0); // RETX should be value of X4_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x28D9 (Z); + LD32(p2, DCPLB_DATA13); + +X4_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB13)); + CHECKREG_SYM(r7, X4_13, r0); // RETX should be value of X4_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0799 (Z); + LD32(p2, DCPLB_DATA14); + +X4_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB14)); + CHECKREG_SYM(r7, X4_14, r0); // RETX should be value of X4_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x388F (Z); + LD32(p2, DCPLB_DATA6); + +X5_6: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB6)); + CHECKREG_SYM(r7, X5_6, r0); // RETX should be value of X5_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x751F (Z); + LD32(p2, DCPLB_DATA7); + +X5_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB7)); + CHECKREG_SYM(r7, X5_7, r0); // RETX should be value of X5_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x493F (Z); + LD32(p2, DCPLB_DATA8); + +X5_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB8)); + CHECKREG_SYM(r7, X5_8, r0); // RETX should be value of X5_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0F36 (Z); + LD32(p2, DCPLB_DATA9); + +X5_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB9)); + CHECKREG_SYM(r7, X5_9, r0); // RETX should be value of X5_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x48EE (Z); + LD32(p2, DCPLB_DATA10); + +X5_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB10)); + CHECKREG_SYM(r7, X5_10, r0); // RETX should be value of X5_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2043 (Z); + LD32(p2, DCPLB_DATA11); + +X5_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB11)); + CHECKREG_SYM(r7, X5_11, r0); // RETX should be value of X5_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3F78 (Z); + LD32(p2, DCPLB_DATA12); + +X5_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB12)); + CHECKREG_SYM(r7, X5_12, r0); // RETX should be value of X5_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1E4D (Z); + LD32(p2, DCPLB_DATA13); + +X5_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB13)); + CHECKREG_SYM(r7, X5_13, r0); // RETX should be value of X5_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3D0D (Z); + LD32(p2, DCPLB_DATA14); + +X5_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB14)); + CHECKREG_SYM(r7, X5_14, r0); // RETX should be value of X5_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x33FA (Z); + LD32(p2, DCPLB_DATA7); + +X6_7: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB7)); + CHECKREG_SYM(r7, X6_7, r0); // RETX should be value of X6_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6FBE (Z); + LD32(p2, DCPLB_DATA8); + +X6_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB8)); + CHECKREG_SYM(r7, X6_8, r0); // RETX should be value of X6_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x36A6 (Z); + LD32(p2, DCPLB_DATA9); + +X6_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB9)); + CHECKREG_SYM(r7, X6_9, r0); // RETX should be value of X6_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2DDA (Z); + LD32(p2, DCPLB_DATA10); + +X6_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB10)); + CHECKREG_SYM(r7, X6_10, r0); // RETX should be value of X6_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x30E4 (Z); + LD32(p2, DCPLB_DATA11); + +X6_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB11)); + CHECKREG_SYM(r7, X6_11, r0); // RETX should be value of X6_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0586 (Z); + LD32(p2, DCPLB_DATA12); + +X6_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB12)); + CHECKREG_SYM(r7, X6_12, r0); // RETX should be value of X6_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x148E (Z); + LD32(p2, DCPLB_DATA13); + +X6_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB13)); + CHECKREG_SYM(r7, X6_13, r0); // RETX should be value of X6_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x42DC (Z); + LD32(p2, DCPLB_DATA14); + +X6_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB14)); + CHECKREG_SYM(r7, X6_14, r0); // RETX should be value of X6_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5929 (Z); + LD32(p2, DCPLB_DATA8); + +X7_8: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB8)); + CHECKREG_SYM(r7, X7_8, r0); // RETX should be value of X7_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0C6D (Z); + LD32(p2, DCPLB_DATA9); + +X7_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB9)); + CHECKREG_SYM(r7, X7_9, r0); // RETX should be value of X7_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x334E (Z); + LD32(p2, DCPLB_DATA10); + +X7_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB10)); + CHECKREG_SYM(r7, X7_10, r0); // RETX should be value of X7_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x62FF (Z); + LD32(p2, DCPLB_DATA11); + +X7_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB11)); + CHECKREG_SYM(r7, X7_11, r0); // RETX should be value of X7_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1F56 (Z); + LD32(p2, DCPLB_DATA12); + +X7_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB12)); + CHECKREG_SYM(r7, X7_12, r0); // RETX should be value of X7_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2BE1 (Z); + LD32(p2, DCPLB_DATA13); + +X7_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB13)); + CHECKREG_SYM(r7, X7_13, r0); // RETX should be value of X7_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1D70 (Z); + LD32(p2, DCPLB_DATA14); + +X7_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB14)); + CHECKREG_SYM(r7, X7_14, r0); // RETX should be value of X7_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2620 (Z); + LD32(p2, DCPLB_DATA9); + +X8_9: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB9)); + CHECKREG_SYM(r7, X8_9, r0); // RETX should be value of X8_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x26FB (Z); + LD32(p2, DCPLB_DATA10); + +X8_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB10)); + CHECKREG_SYM(r7, X8_10, r0); // RETX should be value of X8_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x718F (Z); + LD32(p2, DCPLB_DATA11); + +X8_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB11)); + CHECKREG_SYM(r7, X8_11, r0); // RETX should be value of X8_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x04B1 (Z); + LD32(p2, DCPLB_DATA12); + +X8_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB12)); + CHECKREG_SYM(r7, X8_12, r0); // RETX should be value of X8_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5358 (Z); + LD32(p2, DCPLB_DATA13); + +X8_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB13)); + CHECKREG_SYM(r7, X8_13, r0); // RETX should be value of X8_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3305 (Z); + LD32(p2, DCPLB_DATA14); + +X8_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB14)); + CHECKREG_SYM(r7, X8_14, r0); // RETX should be value of X8_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5690 (Z); + LD32(p2, DCPLB_DATA10); + +X9_10: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB10)); + CHECKREG_SYM(r7, X9_10, r0); // RETX should be value of X9_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5DC5 (Z); + LD32(p2, DCPLB_DATA11); + +X9_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB11)); + CHECKREG_SYM(r7, X9_11, r0); // RETX should be value of X9_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7809 (Z); + LD32(p2, DCPLB_DATA12); + +X9_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB12)); + CHECKREG_SYM(r7, X9_12, r0); // RETX should be value of X9_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1DDC (Z); + LD32(p2, DCPLB_DATA13); + +X9_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB13)); + CHECKREG_SYM(r7, X9_13, r0); // RETX should be value of X9_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6B53 (Z); + LD32(p2, DCPLB_DATA14); + +X9_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB14)); + CHECKREG_SYM(r7, X9_14, r0); // RETX should be value of X9_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7BCD (Z); + LD32(p2, DCPLB_DATA11); + +X10_11: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB11)); + CHECKREG_SYM(r7, X10_11, r0); // RETX should be value of X10_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x63AA (Z); + LD32(p2, DCPLB_DATA12); + +X10_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB12)); + CHECKREG_SYM(r7, X10_12, r0); // RETX should be value of X10_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x373B (Z); + LD32(p2, DCPLB_DATA13); + +X10_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB13)); + CHECKREG_SYM(r7, X10_13, r0); // RETX should be value of X10_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5648 (Z); + LD32(p2, DCPLB_DATA14); + +X10_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB14)); + CHECKREG_SYM(r7, X10_14, r0); // RETX should be value of X10_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6799 (Z); + LD32(p2, DCPLB_DATA12); + +X11_12: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA11, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB12)); + CHECKREG_SYM(r7, X11_12, r0); // RETX should be value of X11_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1452 (Z); + LD32(p2, DCPLB_DATA13); + +X11_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA11, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB13)); + CHECKREG_SYM(r7, X11_13, r0); // RETX should be value of X11_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x23D3 (Z); + LD32(p2, DCPLB_DATA14); + +X11_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA11, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB14)); + CHECKREG_SYM(r7, X11_14, r0); // RETX should be value of X11_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1152 (Z); + LD32(p2, DCPLB_DATA13); + +X12_13: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA12, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB13)); + CHECKREG_SYM(r7, X12_13, r0); // RETX should be value of X12_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6E9D (Z); + LD32(p2, DCPLB_DATA14); + +X12_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA12, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB14)); + CHECKREG_SYM(r7, X12_14, r0); // RETX should be value of X12_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6006 (Z); + LD32(p2, DCPLB_DATA14); + +X13_14: [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA13, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB13|FAULT_CPLB14)); + CHECKREG_SYM(r7, X13_14, r0); // RETX should be value of X13_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- +User: + NOP; + dbg_pass; diff --git a/sim/testsuite/sim/bfin/lmu_cplb_multiple1.S b/sim/testsuite/sim/bfin/lmu_cplb_multiple1.S new file mode 100644 index 0000000..cf8cdf4 --- /dev/null +++ b/sim/testsuite/sim/bfin/lmu_cplb_multiple1.S @@ -0,0 +1,2680 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple1/lmu_cplb_multiple1.dsp +// Description: Multiple CPLB Hit exceptions (DAG1) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +//------------------------------------- + +// Test LMU/CPLB exceptions + +// Basic outline: +// Set exception handler +// program CPLB Entries +// Enable CPLB in DMEM_CNTL +// perform access +// verify exception occurred + +CHECK_INIT(p5, 0xEFFFFFFC); + +//------------------------- +// Zero the CPLB Address and Data regs. + + LD32(p0, DCPLB_ADDR0); + R0 = 0; + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + LD32(p0, DCPLB_DATA0); + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + // Now set the CPLB entries we will need + + + + + // Data area for the desired error + WR_MMR(DCPLB_ADDR0, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR1, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR2, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR3, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR4, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR5, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR6, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR7, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR8, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR9, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR10, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR11, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR12, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR13, 0x10000000, p0, r0); + WR_MMR(DCPLB_ADDR14, 0x10000000, p0, r0); + + // MMR space + WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); + WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + WR_MMR_LABEL(EVT15, int_15, p0, r1); + WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); + WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); + CSYNC; + + A0 = 0; + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + + // But first raise interrupt 15 so we can do one test + // in supervisor mode. + RAISE 15; + NOP; + + RTI; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + +handler: + // generic protection exception handler + // Inputs: + // p2: addr of CPLB entry to be modified ( current test) + // + // Outputs: + // r4: SEQSTAT + // r5: DCPLB_FAULT_ADDR + // r6: DCPLB_STATUS + // r7: RETX (instruction addr where exception occurred) + + + R4 = SEQSTAT; // Get exception cause + R4 <<= 24; // Clear HWERRCAUSE + SFTRESET + R4 >>= 24; + + // read data addr which caused exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r5); + + RD_MMR(DCPLB_STATUS, p0, r6); + + R7 = RETX; // get address of excepting instruction + + // disable the offending CPLB entries + R2 = 0; + [ P2 ] = R2; + + CSYNC; + + // return from exception and re-execute offending instruction + RTX; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +int_15: + // Interrupt 15 handler - test will run in supervisor mode + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x41C6 (Z); + LD32(p2, DCPLB_DATA1); + +X0_1: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB1)); + CHECKREG_SYM(r7, X0_1, r0); // RETX should be value of X0_1 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x167E (Z); + LD32(p2, DCPLB_DATA2); + +X0_2: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB2)); + CHECKREG_SYM(r7, X0_2, r0); // RETX should be value of X0_2 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2781 (Z); + LD32(p2, DCPLB_DATA3); + +X0_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB3)); + CHECKREG_SYM(r7, X0_3, r0); // RETX should be value of X0_3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x446B (Z); + LD32(p2, DCPLB_DATA4); + +X0_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB4)); + CHECKREG_SYM(r7, X0_4, r0); // RETX should be value of X0_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x794B (Z); + LD32(p2, DCPLB_DATA5); + +X0_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB5)); + CHECKREG_SYM(r7, X0_5, r0); // RETX should be value of X0_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x15FB (Z); + LD32(p2, DCPLB_DATA6); + +X0_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB6)); + CHECKREG_SYM(r7, X0_6, r0); // RETX should be value of X0_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x59E2 (Z); + LD32(p2, DCPLB_DATA7); + +X0_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB7)); + CHECKREG_SYM(r7, X0_7, r0); // RETX should be value of X0_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1CFB (Z); + LD32(p2, DCPLB_DATA8); + +X0_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB8)); + CHECKREG_SYM(r7, X0_8, r0); // RETX should be value of X0_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3F54 (Z); + LD32(p2, DCPLB_DATA9); + +X0_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB9)); + CHECKREG_SYM(r7, X0_9, r0); // RETX should be value of X0_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0FF6 (Z); + LD32(p2, DCPLB_DATA10); + +X0_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB10)); + CHECKREG_SYM(r7, X0_10, r0); // RETX should be value of X0_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0ABD (Z); + LD32(p2, DCPLB_DATA11); + +X0_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB11)); + CHECKREG_SYM(r7, X0_11, r0); // RETX should be value of X0_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x31DF (Z); + LD32(p2, DCPLB_DATA12); + +X0_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB12)); + CHECKREG_SYM(r7, X0_12, r0); // RETX should be value of X0_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x237C (Z); + LD32(p2, DCPLB_DATA13); + +X0_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB13)); + CHECKREG_SYM(r7, X0_13, r0); // RETX should be value of X0_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2F1C (Z); + LD32(p2, DCPLB_DATA14); + +X0_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA0, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB14)); + CHECKREG_SYM(r7, X0_14, r0); // RETX should be value of X0_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7DE1 (Z); + LD32(p2, DCPLB_DATA2); + +X1_2: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB2)); + CHECKREG_SYM(r7, X1_2, r0); // RETX should be value of X1_2 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4487 (Z); + LD32(p2, DCPLB_DATA3); + +X1_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB3)); + CHECKREG_SYM(r7, X1_3, r0); // RETX should be value of X1_3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6201 (Z); + LD32(p2, DCPLB_DATA4); + +X1_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB4)); + CHECKREG_SYM(r7, X1_4, r0); // RETX should be value of X1_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x52BF (Z); + LD32(p2, DCPLB_DATA5); + +X1_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB5)); + CHECKREG_SYM(r7, X1_5, r0); // RETX should be value of X1_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6231 (Z); + LD32(p2, DCPLB_DATA6); + +X1_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB6)); + CHECKREG_SYM(r7, X1_6, r0); // RETX should be value of X1_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x63DE (Z); + LD32(p2, DCPLB_DATA7); + +X1_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB7)); + CHECKREG_SYM(r7, X1_7, r0); // RETX should be value of X1_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6956 (Z); + LD32(p2, DCPLB_DATA8); + +X1_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB8)); + CHECKREG_SYM(r7, X1_8, r0); // RETX should be value of X1_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1372 (Z); + LD32(p2, DCPLB_DATA9); + +X1_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB9)); + CHECKREG_SYM(r7, X1_9, r0); // RETX should be value of X1_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x500F (Z); + LD32(p2, DCPLB_DATA10); + +X1_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB10)); + CHECKREG_SYM(r7, X1_10, r0); // RETX should be value of X1_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2847 (Z); + LD32(p2, DCPLB_DATA11); + +X1_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB11)); + CHECKREG_SYM(r7, X1_11, r0); // RETX should be value of X1_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2C67 (Z); + LD32(p2, DCPLB_DATA12); + +X1_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB12)); + CHECKREG_SYM(r7, X1_12, r0); // RETX should be value of X1_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7566 (Z); + LD32(p2, DCPLB_DATA13); + +X1_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB13)); + CHECKREG_SYM(r7, X1_13, r0); // RETX should be value of X1_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4287 (Z); + LD32(p2, DCPLB_DATA14); + +X1_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA1, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB14)); + CHECKREG_SYM(r7, X1_14, r0); // RETX should be value of X1_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3359 (Z); + LD32(p2, DCPLB_DATA3); + +X2_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB3)); + CHECKREG_SYM(r7, X2_3, r0); // RETX should be value of X2_3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4DAA (Z); + LD32(p2, DCPLB_DATA4); + +X2_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB4)); + CHECKREG_SYM(r7, X2_4, r0); // RETX should be value of X2_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6488 (Z); + LD32(p2, DCPLB_DATA5); + +X2_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB5)); + CHECKREG_SYM(r7, X2_5, r0); // RETX should be value of X2_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x773C (Z); + LD32(p2, DCPLB_DATA6); + +X2_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB6)); + CHECKREG_SYM(r7, X2_6, r0); // RETX should be value of X2_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6F59 (Z); + LD32(p2, DCPLB_DATA7); + +X2_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB7)); + CHECKREG_SYM(r7, X2_7, r0); // RETX should be value of X2_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6EEA (Z); + LD32(p2, DCPLB_DATA8); + +X2_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB8)); + CHECKREG_SYM(r7, X2_8, r0); // RETX should be value of X2_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5656 (Z); + LD32(p2, DCPLB_DATA9); + +X2_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB9)); + CHECKREG_SYM(r7, X2_9, r0); // RETX should be value of X2_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6113 (Z); + LD32(p2, DCPLB_DATA10); + +X2_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB10)); + CHECKREG_SYM(r7, X2_10, r0); // RETX should be value of X2_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4A7B (Z); + LD32(p2, DCPLB_DATA11); + +X2_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB11)); + CHECKREG_SYM(r7, X2_11, r0); // RETX should be value of X2_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x31D2 (Z); + LD32(p2, DCPLB_DATA12); + +X2_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB12)); + CHECKREG_SYM(r7, X2_12, r0); // RETX should be value of X2_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2D85 (Z); + LD32(p2, DCPLB_DATA13); + +X2_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB13)); + CHECKREG_SYM(r7, X2_13, r0); // RETX should be value of X2_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x19A1 (Z); + LD32(p2, DCPLB_DATA14); + +X2_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA2, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB14)); + CHECKREG_SYM(r7, X2_14, r0); // RETX should be value of X2_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x69D8 (Z); + LD32(p2, DCPLB_DATA4); + +X3_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB4)); + CHECKREG_SYM(r7, X3_4, r0); // RETX should be value of X3_4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x353C (Z); + LD32(p2, DCPLB_DATA5); + +X3_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB5)); + CHECKREG_SYM(r7, X3_5, r0); // RETX should be value of X3_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3B54 (Z); + LD32(p2, DCPLB_DATA6); + +X3_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB6)); + CHECKREG_SYM(r7, X3_6, r0); // RETX should be value of X3_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7D55 (Z); + LD32(p2, DCPLB_DATA7); + +X3_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB7)); + CHECKREG_SYM(r7, X3_7, r0); // RETX should be value of X3_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x102F (Z); + LD32(p2, DCPLB_DATA8); + +X3_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB8)); + CHECKREG_SYM(r7, X3_8, r0); // RETX should be value of X3_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1B37 (Z); + LD32(p2, DCPLB_DATA9); + +X3_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB9)); + CHECKREG_SYM(r7, X3_9, r0); // RETX should be value of X3_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7AAE (Z); + LD32(p2, DCPLB_DATA10); + +X3_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB10)); + CHECKREG_SYM(r7, X3_10, r0); // RETX should be value of X3_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5E65 (Z); + LD32(p2, DCPLB_DATA11); + +X3_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB11)); + CHECKREG_SYM(r7, X3_11, r0); // RETX should be value of X3_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x345B (Z); + LD32(p2, DCPLB_DATA12); + +X3_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB12)); + CHECKREG_SYM(r7, X3_12, r0); // RETX should be value of X3_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x63DA (Z); + LD32(p2, DCPLB_DATA13); + +X3_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB13)); + CHECKREG_SYM(r7, X3_13, r0); // RETX should be value of X3_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6102 (Z); + LD32(p2, DCPLB_DATA14); + +X3_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA3, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB14)); + CHECKREG_SYM(r7, X3_14, r0); // RETX should be value of X3_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7A79 (Z); + LD32(p2, DCPLB_DATA5); + +X4_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB5)); + CHECKREG_SYM(r7, X4_5, r0); // RETX should be value of X4_5 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0398 (Z); + LD32(p2, DCPLB_DATA6); + +X4_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB6)); + CHECKREG_SYM(r7, X4_6, r0); // RETX should be value of X4_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x28CC (Z); + LD32(p2, DCPLB_DATA7); + +X4_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB7)); + CHECKREG_SYM(r7, X4_7, r0); // RETX should be value of X4_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x60E3 (Z); + LD32(p2, DCPLB_DATA8); + +X4_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB8)); + CHECKREG_SYM(r7, X4_8, r0); // RETX should be value of X4_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1F1A (Z); + LD32(p2, DCPLB_DATA9); + +X4_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB9)); + CHECKREG_SYM(r7, X4_9, r0); // RETX should be value of X4_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x4B76 (Z); + LD32(p2, DCPLB_DATA10); + +X4_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB10)); + CHECKREG_SYM(r7, X4_10, r0); // RETX should be value of X4_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x058E (Z); + LD32(p2, DCPLB_DATA11); + +X4_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB11)); + CHECKREG_SYM(r7, X4_11, r0); // RETX should be value of X4_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7A5F (Z); + LD32(p2, DCPLB_DATA12); + +X4_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB12)); + CHECKREG_SYM(r7, X4_12, r0); // RETX should be value of X4_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x28D9 (Z); + LD32(p2, DCPLB_DATA13); + +X4_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB13)); + CHECKREG_SYM(r7, X4_13, r0); // RETX should be value of X4_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0799 (Z); + LD32(p2, DCPLB_DATA14); + +X4_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA4, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB14)); + CHECKREG_SYM(r7, X4_14, r0); // RETX should be value of X4_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x388F (Z); + LD32(p2, DCPLB_DATA6); + +X5_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB6)); + CHECKREG_SYM(r7, X5_6, r0); // RETX should be value of X5_6 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x751F (Z); + LD32(p2, DCPLB_DATA7); + +X5_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB7)); + CHECKREG_SYM(r7, X5_7, r0); // RETX should be value of X5_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x493F (Z); + LD32(p2, DCPLB_DATA8); + +X5_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB8)); + CHECKREG_SYM(r7, X5_8, r0); // RETX should be value of X5_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0F36 (Z); + LD32(p2, DCPLB_DATA9); + +X5_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB9)); + CHECKREG_SYM(r7, X5_9, r0); // RETX should be value of X5_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x48EE (Z); + LD32(p2, DCPLB_DATA10); + +X5_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB10)); + CHECKREG_SYM(r7, X5_10, r0); // RETX should be value of X5_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2043 (Z); + LD32(p2, DCPLB_DATA11); + +X5_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB11)); + CHECKREG_SYM(r7, X5_11, r0); // RETX should be value of X5_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3F78 (Z); + LD32(p2, DCPLB_DATA12); + +X5_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB12)); + CHECKREG_SYM(r7, X5_12, r0); // RETX should be value of X5_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1E4D (Z); + LD32(p2, DCPLB_DATA13); + +X5_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB13)); + CHECKREG_SYM(r7, X5_13, r0); // RETX should be value of X5_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3D0D (Z); + LD32(p2, DCPLB_DATA14); + +X5_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA5, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB14)); + CHECKREG_SYM(r7, X5_14, r0); // RETX should be value of X5_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x33FA (Z); + LD32(p2, DCPLB_DATA7); + +X6_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB7)); + CHECKREG_SYM(r7, X6_7, r0); // RETX should be value of X6_7 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6FBE (Z); + LD32(p2, DCPLB_DATA8); + +X6_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB8)); + CHECKREG_SYM(r7, X6_8, r0); // RETX should be value of X6_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x36A6 (Z); + LD32(p2, DCPLB_DATA9); + +X6_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB9)); + CHECKREG_SYM(r7, X6_9, r0); // RETX should be value of X6_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2DDA (Z); + LD32(p2, DCPLB_DATA10); + +X6_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB10)); + CHECKREG_SYM(r7, X6_10, r0); // RETX should be value of X6_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x30E4 (Z); + LD32(p2, DCPLB_DATA11); + +X6_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB11)); + CHECKREG_SYM(r7, X6_11, r0); // RETX should be value of X6_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0586 (Z); + LD32(p2, DCPLB_DATA12); + +X6_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB12)); + CHECKREG_SYM(r7, X6_12, r0); // RETX should be value of X6_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x148E (Z); + LD32(p2, DCPLB_DATA13); + +X6_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB13)); + CHECKREG_SYM(r7, X6_13, r0); // RETX should be value of X6_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x42DC (Z); + LD32(p2, DCPLB_DATA14); + +X6_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA6, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB14)); + CHECKREG_SYM(r7, X6_14, r0); // RETX should be value of X6_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5929 (Z); + LD32(p2, DCPLB_DATA8); + +X7_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB8)); + CHECKREG_SYM(r7, X7_8, r0); // RETX should be value of X7_8 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x0C6D (Z); + LD32(p2, DCPLB_DATA9); + +X7_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB9)); + CHECKREG_SYM(r7, X7_9, r0); // RETX should be value of X7_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x334E (Z); + LD32(p2, DCPLB_DATA10); + +X7_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB10)); + CHECKREG_SYM(r7, X7_10, r0); // RETX should be value of X7_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x62FF (Z); + LD32(p2, DCPLB_DATA11); + +X7_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB11)); + CHECKREG_SYM(r7, X7_11, r0); // RETX should be value of X7_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1F56 (Z); + LD32(p2, DCPLB_DATA12); + +X7_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB12)); + CHECKREG_SYM(r7, X7_12, r0); // RETX should be value of X7_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2BE1 (Z); + LD32(p2, DCPLB_DATA13); + +X7_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB13)); + CHECKREG_SYM(r7, X7_13, r0); // RETX should be value of X7_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1D70 (Z); + LD32(p2, DCPLB_DATA14); + +X7_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA7, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB14)); + CHECKREG_SYM(r7, X7_14, r0); // RETX should be value of X7_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x2620 (Z); + LD32(p2, DCPLB_DATA9); + +X8_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB9)); + CHECKREG_SYM(r7, X8_9, r0); // RETX should be value of X8_9 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x26FB (Z); + LD32(p2, DCPLB_DATA10); + +X8_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB10)); + CHECKREG_SYM(r7, X8_10, r0); // RETX should be value of X8_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x718F (Z); + LD32(p2, DCPLB_DATA11); + +X8_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB11)); + CHECKREG_SYM(r7, X8_11, r0); // RETX should be value of X8_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x04B1 (Z); + LD32(p2, DCPLB_DATA12); + +X8_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB12)); + CHECKREG_SYM(r7, X8_12, r0); // RETX should be value of X8_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5358 (Z); + LD32(p2, DCPLB_DATA13); + +X8_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB13)); + CHECKREG_SYM(r7, X8_13, r0); // RETX should be value of X8_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x3305 (Z); + LD32(p2, DCPLB_DATA14); + +X8_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA8, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB14)); + CHECKREG_SYM(r7, X8_14, r0); // RETX should be value of X8_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5690 (Z); + LD32(p2, DCPLB_DATA10); + +X9_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB10)); + CHECKREG_SYM(r7, X9_10, r0); // RETX should be value of X9_10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5DC5 (Z); + LD32(p2, DCPLB_DATA11); + +X9_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB11)); + CHECKREG_SYM(r7, X9_11, r0); // RETX should be value of X9_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7809 (Z); + LD32(p2, DCPLB_DATA12); + +X9_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB12)); + CHECKREG_SYM(r7, X9_12, r0); // RETX should be value of X9_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1DDC (Z); + LD32(p2, DCPLB_DATA13); + +X9_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB13)); + CHECKREG_SYM(r7, X9_13, r0); // RETX should be value of X9_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6B53 (Z); + LD32(p2, DCPLB_DATA14); + +X9_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA9, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB14)); + CHECKREG_SYM(r7, X9_14, r0); // RETX should be value of X9_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x7BCD (Z); + LD32(p2, DCPLB_DATA11); + +X10_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB11)); + CHECKREG_SYM(r7, X10_11, r0); // RETX should be value of X10_11 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x63AA (Z); + LD32(p2, DCPLB_DATA12); + +X10_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB12)); + CHECKREG_SYM(r7, X10_12, r0); // RETX should be value of X10_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x373B (Z); + LD32(p2, DCPLB_DATA13); + +X10_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB13)); + CHECKREG_SYM(r7, X10_13, r0); // RETX should be value of X10_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x5648 (Z); + LD32(p2, DCPLB_DATA14); + +X10_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA10, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB14)); + CHECKREG_SYM(r7, X10_14, r0); // RETX should be value of X10_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6799 (Z); + LD32(p2, DCPLB_DATA12); + +X11_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA11, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB12)); + CHECKREG_SYM(r7, X11_12, r0); // RETX should be value of X11_12 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1452 (Z); + LD32(p2, DCPLB_DATA13); + +X11_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA11, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB13)); + CHECKREG_SYM(r7, X11_13, r0); // RETX should be value of X11_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x23D3 (Z); + LD32(p2, DCPLB_DATA14); + +X11_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA11, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB14)); + CHECKREG_SYM(r7, X11_14, r0); // RETX should be value of X11_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x1152 (Z); + LD32(p2, DCPLB_DATA13); + +X12_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA12, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB13)); + CHECKREG_SYM(r7, X12_13, r0); // RETX should be value of X12_13 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6E9D (Z); + LD32(p2, DCPLB_DATA14); + +X12_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA12, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB14)); + CHECKREG_SYM(r7, X12_14, r0); // RETX should be value of X12_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + CSYNC; + + LD32(i1, 0x10000000); + R1 = 0x6006 (Z); + LD32(p2, DCPLB_DATA14); + +X13_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); + CSYNC; + WR_MMR(DCPLB_DATA13, 0, p0, r0); + + // Now check that handler read correct values + CHECKREG(r4,0x27); // supv and EXCPT_PROT + CHECKREG(r5, 0x10000000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB13|FAULT_CPLB14)); + CHECKREG_SYM(r7, X13_14, r0); // RETX should be value of X13_14 (HARDCODED ADDR!!) + + //------------------------------------------------------- +User: + NOP; + dbg_pass; diff --git a/sim/testsuite/sim/bfin/lmu_excpt_align.S b/sim/testsuite/sim/bfin/lmu_excpt_align.S new file mode 100644 index 0000000..b978155 --- /dev/null +++ b/sim/testsuite/sim/bfin/lmu_excpt_align.S @@ -0,0 +1,345 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_align/lmu_excpt_align.dsp +// Description: LMU data alignment exceptions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +CHECK_INIT(p5, 0xE0000000); + + // test address for DAG0 + // test address for DAG1 + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + + // Write fault addr MMR to known state + WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6); + + //nop;nop;nop;nop;nop; // in lieu of CSYNC + CSYNC; + + A0 = 0; + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + RTI; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +User: + NOP;NOP;NOP;NOP;NOP; + + //------------------------------------------------------- + // First do stores + //------------------------------------------------------- + // 16-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X01: W [ I1 ] = R1.L; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X02: [ I1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 2))); + LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X03: [ I1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 3))); + LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X04: [ I1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 16-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X05: A0 = 0 || NOP || W [ I1 ] = R1.L; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X05, r0); // RETX should be value of X05 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X06: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X06, r0); // RETX should be value of X06 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 2))); + LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X07: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X07, r0); // RETX should be value of X07 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 3))); + LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X08: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X08, r0); // RETX should be value of X08 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // Now repeat for Loads + //------------------------------------------------------- + // 16-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X11: R1.L = W [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X11, r0); // RETX should be value of X11 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X12: R1 = [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X12, r0); // RETX should be value of X12 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 2))); + LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X13: R1 = [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X13, r0); // RETX should be value of X13 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG0 + + + + LD32(i1, ((0x1000 + 3))); + LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X14: R1 = [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X14, r0); // RETX should be value of X14 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 16-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X15: A0 = 0 || NOP || R1.L = W [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X15, r0); // RETX should be value of X15 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 1))); + LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X16, r0); // RETX should be value of X16 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 2))); + LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X17: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X17, r0); // RETX should be value of X17 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // 32-bit alignment, DAG1 + + + + LD32(i1, ((0x1000 + 3))); + LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X18: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here + + CHECKREG(r5,0x24); // supv and EXCPT_ALIGN + CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address + CHECKREG_SYM(r7, X18, r0); // RETX should be value of X18 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + dbg_pass; + + +handler: + R5 = SEQSTAT; // Get exception cause + + // read and check fail addr (addr_which_causes_exception) + // should not be set for alignment exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r6); + + R7 = RETX; // get address of excepting instruction + + // align the offending address + I1 = P2; + + RTX; + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +.section MEM_0x1000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/lmu_excpt_default.S b/sim/testsuite/sim/bfin/lmu_excpt_default.S new file mode 100644 index 0000000..9b8a14f --- /dev/null +++ b/sim/testsuite/sim/bfin/lmu_excpt_default.S @@ -0,0 +1,307 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_default/lmu_excpt_default.dsp +// Description: Default protection checks (CPLB disabled) +// - MMR access in User mode +// - DAG1 Access MMRs (supv/user mode, read/write) +// - DAG1 Access Scratch SRAM (user or supervisor mode, read/write) +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#define EXCPT_PROTVIOL 0x23 +#define OMODE_SUPV 0 // not used in the hardware + + + + CHECK_INIT(p5, 0xE0000000); + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + WR_MMR_LABEL(EVT15, Supv, p0, r1); + WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); + WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); + CSYNC; + + A0 = 0; + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + + // But first raise interrupt 15 so we can run in supervisor mode. + RAISE 15; + + RTI; + +Supv: + + //------------------------------------------------------- + // DAG1 MMR Write access + + + + LD32(i1, (DCPLB_ADDR0)); + LD32_LABEL(p2, Y01); // Exception handler will return to this address + LD32(r0, 0xdeadbeef); + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X01: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here +Y01: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS + CHECKREG_SYM(r7, X01, r0); // RETX X01: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG1 MMR Read access + + + + LD32(i1, (DCPLB_ADDR1)); + LD32_LABEL(p2, Y02); // Exception handler will return to this address + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X02: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here +Y02: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS + CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS + CHECKREG_SYM(r7, X02, r0); // RETX X02: (HARDCODED ADDR!!) + +#if 0 + //------------------------------------------------------- + // DAG1 Scratch SRAM Write access + + + + LD32(i1, (( 0xFF800000 + 0x300000))); + LD32_LABEL(p2, Y03); // Exception handler will return to this address + LD32(r1, 0xdeadbeef); + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X03: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here +Y03: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS + CHECKREG_SYM(r7, X03, r0); // RETX X03: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG1 Scratch SRAM Read access + + + + LD32(i1, ((( 0xFF800000 + 0x300000) + 4))); + LD32_LABEL(p2, Y04); // Exception handler will return to this address + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X04: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here +Y04: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS + CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS + CHECKREG_SYM(r7, X04, r0); // RETX X04: (HARDCODED ADDR!!) +#endif + + //------------------------------------------------------- + + // Now, go to User mode + LD32_LABEL(r0, User); + RETI = R0; + RTI; + + +User: + + //------------------------------------------------------- + // DAG0 MMR Write access (multi-issue) + + + + LD32(i1, (DCPLB_ADDR0)); + LD32_LABEL(p2, Y11); // Exception handler will return to this address + LD32(r0, 0xdeadbeef); + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X11: A0 = 0 || [ I1 ] = R1 || NOP; // Exception should occur here +Y11: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X11, r0); // RETX X11: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG0 MMR Read access (multi-issue) + + + + LD32(i1, (DCPLB_ADDR1)); + LD32_LABEL(p2, Y12); // Exception handler will return to this address + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X12: A0 = 0 || R1 = [ I1 ] || NOP; // Exception should occur here +Y12: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS + CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X12, r0); // RETX X12: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG1 MMR Write access + + + + LD32(i1, (DCPLB_ADDR0)); + LD32_LABEL(p2, Y13); // Exception handler will return to this address + LD32(r0, 0xdeadbeef); + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here +Y13: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X13, r0); // RETX X13: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG1 MMR Read access + + + + LD32(i1, (DCPLB_ADDR1)); + LD32_LABEL(p2, Y14); // Exception handler will return to this address + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X14: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here +Y14: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS + CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X14, r0); // RETX X14: (HARDCODED ADDR!!) + +#if 0 + //------------------------------------------------------- + // DAG1 Scratch SRAM Write access + + + + LD32(i1, (( 0xFF800000 + 0x300000))); + LD32_LABEL(p2, Y15); // Exception handler will return to this address + LD32(r1, 0xdeadbeef); + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X15: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here +Y15: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X15, r0); // RETX X15: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG1 Scratch SRAM Read access + + + + LD32(i1, ((( 0xFF800000 + 0x300000) + 4))); + LD32_LABEL(p2, Y16); // Exception handler will return to this address + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here +Y16: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS + CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X16, r0); // RETX X16: (HARDCODED ADDR!!) +#endif + + //------------------------------------------------------- + // DAG0 MMR Write access (single-issue) + + + + LD32(i1, (DCPLB_ADDR0)); + LD32_LABEL(p2, Y17); // Exception handler will return to this address + LD32(r0, 0xdeadbeef); + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X17: [ I1 ] = R1; // Exception should occur here +Y17: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X17, r0); // RETX X17: (HARDCODED ADDR!!) + + //------------------------------------------------------- + // DAG0 MMR Read access (single-issue) + + + + LD32(i1, (DCPLB_ADDR1)); + LD32_LABEL(p2, Y18); // Exception handler will return to this address + + + R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first +X18: R1 = [ I1 ]; // Exception should occur here +Y18: + + // Now check that handler read correct values + CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT + CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS + CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS + CHECKREG_SYM(r7, X18, r0); // RETX X18: (HARDCODED ADDR!!) + + //------------------------------------------------------- + dbg_pass; + + +handler: + R4 = SEQSTAT; // Get exception cause + + // read and check fail addr (addr_which_causes_exception) + // should not be set for alignment exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r5); + RD_MMR(DCPLB_STATUS, p0, r6); + R7 = RETX; // get address of excepting instruction + + RETX = P2; + + RTX; diff --git a/sim/testsuite/sim/bfin/lmu_excpt_illaddr.S b/sim/testsuite/sim/bfin/lmu_excpt_illaddr.S new file mode 100644 index 0000000..7c84b64 --- /dev/null +++ b/sim/testsuite/sim/bfin/lmu_excpt_illaddr.S @@ -0,0 +1,337 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_illaddr/lmu_excpt_illaddr.dsp +// Description: LMU illegal address exceptions +// Illegal core MMR: addr[19:16] != 0 +// Illegal core MMR: Illegal peripheral +// Illegal core MMR: Illegal addr in peripheral +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +#ifndef SR_BASE +#define SR_BASE 0xFF800000 // must match value used for sram_baddr inputs +#endif +#ifndef A_SRAM_BASE +#define A_SRAM_BASE SR_BASE +#endif +#ifndef B_SRAM_BASE +#define B_SRAM_BASE SR_BASE + 0x100000 +#endif +#ifndef I_SRAM_BASE +#define I_SRAM_BASE SR_BASE + 0x200000 +#endif +#ifndef SCRATCH_SRAM_BASE +#define SCRATCH_SRAM_BASE SR_BASE + 0x300000 +#endif + +#ifndef A_SRAM_SIZE +#define A_SRAM_SIZE 0x4000 +#endif +#ifndef B_SRAM_SIZE +#define B_SRAM_SIZE 0x4000 +#endif +#ifndef I_SRAM_SIZE +#define I_SRAM_SIZE 0x4000 +#endif +#ifndef SCRATCH_SRAM_SIZE +#define SCRATCH_SRAM_SIZE 0x1000 +#endif + +CHECK_INIT(p5, 0xE0000000); + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + WR_MMR_LABEL(EVT15, int15, p0, r1); + WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); + WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); + + // Set up CPLB + + WR_MMR(DCPLB_ADDR1, SR_BASE, p0, r0); // SRAM segment: Non-cacheable + WR_MMR(DCPLB_DATA1, ( CPLB_VALID | CPLB_L1SRAM | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0); + + WR_MMR(DCPLB_ADDR2, 0xE0000000, p0, r0); // CHECKREG segment: Non-cacheable + WR_MMR(DCPLB_DATA2, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0); + + WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); // MMRs: Non-cacheable + WR_MMR(DCPLB_DATA15, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0); + + WR_MMR(DMEM_CONTROL, (DMC_AB_SRAM | ENDCPLB | ENDM), p0, r0); + + CSYNC; + + // Write fault addr MMR to known state + WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6); + NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + + // But first raise interrupt 15 so we will run in supervisor mode. + RAISE 15; + NOP; + RTI; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + +int15: + NOP;NOP;NOP;NOP;NOP; + + //------------------------------------------------------- + // First do stores + //------------------------------------------------------- + // + + // illegal core MMR: addr[19] !=0 + + + LD32(p1, 0xFFE80000); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X01: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE80000); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: addr[18] !=0 + + + LD32(p1, 0xFFE40000); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X02: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE40000); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: addr[17] !=0 + + + LD32(p1, 0xFFE20000); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X03: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE20000); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: addr[16] !=0 + + + LD32(p1, 0xFFE10000); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X04: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE10000); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal periperal (addr[15:12] > 8) + + + LD32(p1, 0xFFE09000); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X10: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE09000); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X10, r0); // RETX should be value of X10 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 00 + + + LD32(p1, 0xFFE00408); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X20: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE00408); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X20, r0); // RETX should be value of X20 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 01 + + + LD32(p1, 0xFFE01408); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X21: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE01408); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X21, r0); // RETX should be value of X21 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 02 + + + LD32(p1, 0xFFE02114); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X22: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE02114); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X22, r0); // RETX should be value of X22 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 03 + + + LD32(p1, 0xFFE03010); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X23: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE03010); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X23, r0); // RETX should be value of X23 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 04 + + + LD32(p1, 0xFFE04008); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X24: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE04008); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X24, r0); // RETX should be value of X24 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 05 + + + LD32(p1, 0xFFE05010); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X25: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE05010); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X25, r0); // RETX should be value of X25 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 06 + + + LD32(p1, 0xFFE06104); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X26: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE06104); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X26, r0); // RETX should be value of X26 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 07 + + + LD32(p1, 0xFFE07204); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X27: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE07204); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X27, r0); // RETX should be value of X27 (HARDCODED ADDR!!) + + //------------------------------------------------------- + + // illegal core MMR: illegal addr in peripheral 08 + + + LD32(p1, 0xFFE08108); + LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1) + LD32(r1, 0xDEADBEEF); + R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first + +X28: [ P1 ] = R1; // Exception should occur here + + CHECKREG(r5,0x2e); // supv and EXCPT_PROT + CHECKREG(r6, 0xFFE08108); // FAULT_ADDR should contain test address + CHECKREG_SYM(r7, X28, r0); // RETX should be value of X28 (HARDCODED ADDR!!) + + //------------------------------------------------------- +User: + dbg_pass; + + + //------------------------------------------------------- +handler: + R5 = SEQSTAT; // Get exception cause + + // read and check fail addr (addr_which_causes_exception) + // should not be set for alignment exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r6); + + R7 = RETX; // get address of excepting instruction + + // align the offending address + P1 = P2; + + RTX; + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; diff --git a/sim/testsuite/sim/bfin/lmu_excpt_prot0.S b/sim/testsuite/sim/bfin/lmu_excpt_prot0.S new file mode 100644 index 0000000..279cc02 --- /dev/null +++ b/sim/testsuite/sim/bfin/lmu_excpt_prot0.S @@ -0,0 +1,392 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot0/lmu_excpt_prot0.dsp +// Description: LMU protection exceptions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +//------------------------------------- + +// Test LMU/CPLB exceptions + +// Basic outline: +// Set exception handler +// program CPLB Entries +// Enable CPLB in DMEM_CNTL +// perform access +// verify exception occurred + +CHECK_INIT(p5, 0xEFFFFFFC); + +//------------------------- +// Zero the CPLB Address and Data regs. + + LD32(p0, DCPLB_ADDR0); + R0 = 0; + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + LD32(p0, DCPLB_DATA0); + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + // Now set the CPLB entries we will need + + + + + + + + + + + + + + + + + + + + + + + + + + // Data area for the desired error + WR_MMR(DCPLB_ADDR0, 0x800, p0, r0); + WR_MMR(DCPLB_ADDR1, 0x1000, p0, r0); + WR_MMR(DCPLB_DATA0, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW, p0, r0); + WR_MMR(DCPLB_ADDR2, 0x2000, p0, r0); + WR_MMR(DCPLB_ADDR3, 0x3000, p0, r0); + WR_MMR(DCPLB_ADDR4, 0x4000, p0, r0); + WR_MMR(DCPLB_ADDR5, 0x5000, p0, r0); + WR_MMR(DCPLB_ADDR6, 0x6000, p0, r0); + WR_MMR(DCPLB_ADDR7, 0x7000, p0, r0); + + // CHECKREG segment + WR_MMR(DCPLB_ADDR14, 0xEFFFFC00, p0, r0); + WR_MMR(DCPLB_DATA14, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_WT|CPLB_L1_CACHABLE|CPLB_SUPV_WR|CPLB_USER_RW, p0, r0); + + // MMR space + WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); + WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + WR_MMR_LABEL(EVT15, int_15, p0, r1); + WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); + WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); + + // enable CPLB + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + + // But first raise interrupt 15 so we can do one test + // in supervisor mode. + RAISE 15; + NOP; + + RTI; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +int_15: + // Interrupt 15 handler - needed to try supervisor access with exceptions enabled + //------------------------------------------------------- + // Protection violation - Illegal Supervisor Write Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(p1, 0x800); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA0); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA1); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); + + +X0: [ P1 ] = R1; // Exception should occur here + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x800); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0)); + CHECKREG_SYM(r7, X0, r0); // RETX should be value of X0 (HARDCODED ADDR!!) + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RTI; + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +User: + NOP;NOP;NOP;NOP;NOP; + + //------------------------------------------------------- + // Protection violation - Illegal User Write Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(p1, 0x1000); + LD32(r1, 0xDEADBEEF); + + + // values to fix up current test + LD32(p2, DCPLB_DATA1); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + // values for next test + LD32(p3, DCPLB_DATA2); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE); + +X1: [ P1 ] = R1; // Exception should occur here + + // Now check that handler read correct values + + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x1000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER | FAULT_CPLB1)); + CHECKREG_SYM(r7, X1, r0); // RETX should be value of X1 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // Protection violation - Illegal User Read Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(p1, 0x2000); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA2); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RO|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA3); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + +X2: //[p1] = r1; // Exception should occur here + R0 = [ P1 ]; + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x2000); + CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER | FAULT_CPLB2)); + CHECKREG_SYM(r7, X2, r0); // RETX should be value of X2 (HARDCODED ADDR!!) + + //------------------------------------------------------- + // Protection violation - Illegal Dirty Page Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(p1, 0x3000); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA3); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA4); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DA0ACC|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + +X3: [ P1 ] = R1; // Exception should occur here + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x3000); + CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER | FAULT_CPLB3)); + CHECKREG_SYM(r7, X3, r0); // RETX should be value of X3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + // Protection violation - Illegal DAG1 Access + // Since this test uses DAG0, there shouldn't be any exception + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(p1, 0x4000); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA4); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA5); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + +X4: [ P1 ] = R1; // Exception should NOT occur here + + + // Now check that handler read correct values + // Handler shouldn't have been invoked, so registers should + // remain unchanged. + CHECKREG(r4,0); // supv and EXCPT_PROT + CHECKREG(r5, 0); + CHECKREG(r6, 0); + CHECKREG(r7, 0); // RETX should NOT be value of X4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + // L1Miss not implemented yet - skip for now.... + +// //------------------------------------------------------- +// // Protection violation - L1 Miss +// r0=0;r1=0;r2=0;r3=0;r4=0;r5=0;r6=0;r7=0; +// +// LD32(p1, 0x5000); +// LD32(r1, 0xDEADBEEF); +// +// LD32(p2, DCPLB_DATA5); +// LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); +// +// LD32(p3, DCPLB_DATA6); +// LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_USER_RW|CPLB_SUPV_WR); +// +// +//X5: //[p1] = r1; // Exception should occur here +// r0 = [p1]; +// +// +// // Now check that handler read correct values +// CHECKREG(r4,0x23); // supv and EXCPT_PROT +// CHECKREG(r5, 0x5000); +// // CHECKREG(r6, FAULT_DATA | FAULT_CPLB5); +// CHECKREG_SYM(r7, X5, r0); // RETX should be value of X5 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + dbg_pass; + + +handler: + // generic protection exception handler + // Inputs: + // p2: addr of CPLB entry to be modified ( current test) + // r2: new data for CPLB entry + // + // p3: addr of CPLB entry to be modified ( next test) + // r3: new data for CPLB entry + // + // Outputs: + // r4: SEQSTAT + // r5: DCPLB_FAULT_ADDR + // r6: DCPLB_STATUS + // r7: RETX (instruction addr where exception occurred) + + + R4 = SEQSTAT; // Get exception cause + + // read data addr which caused exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r5); + + RD_MMR(DCPLB_STATUS, p0, r6); + + R7 = RETX; // get address of excepting instruction + + + // modify CPLB to allow access. Main pgm passes in addr and data + [ P2 ] = R2; + + // Set up for next test + [ P3 ] = R3; + + NOP;NOP;NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC; + + // return from exception and re-execute offending instruction + RTX; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +.section MEM_0x800,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x1000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x2000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x3000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x4000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x5000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +// Need illegal SRAM addr to test CPLB_L1SRAM +//.data 0x6000 +// .dd 0x00000000 +// .dd 0x00000000 +// .dd 0x00000000 +// .dd 0x00000000 + +.section MEM_0x7000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/lmu_excpt_prot1.S b/sim/testsuite/sim/bfin/lmu_excpt_prot1.S new file mode 100644 index 0000000..5ffa680 --- /dev/null +++ b/sim/testsuite/sim/bfin/lmu_excpt_prot1.S @@ -0,0 +1,401 @@ +//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot1/lmu_excpt_prot1.dsp +// Description: LMU protection exceptions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) + +//------------------------------------- + +// Test LMU/CPLB exceptions + +// Basic outline: +// Set exception handler +// program CPLB Entries +// Enable CPLB in DMEM_CNTL +// perform access +// verify exception occurred + +CHECK_INIT(p5, 0xEFFFFFFC); + + A0 = 0; + +//------------------------- +// Zero the CPLB Address and Data regs. + + LD32(p0, DCPLB_ADDR0); + R0 = 0; + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + LD32(p0, DCPLB_DATA0); + [ P0 ++ ] = R0; // 0 + [ P0 ++ ] = R0; // 1 + [ P0 ++ ] = R0; // 2 + [ P0 ++ ] = R0; // 3 + [ P0 ++ ] = R0; // 4 + [ P0 ++ ] = R0; // 5 + [ P0 ++ ] = R0; // 6 + [ P0 ++ ] = R0; // 7 + [ P0 ++ ] = R0; // 8 + [ P0 ++ ] = R0; // 9 + [ P0 ++ ] = R0; // 10 + [ P0 ++ ] = R0; // 11 + [ P0 ++ ] = R0; // 12 + [ P0 ++ ] = R0; // 13 + [ P0 ++ ] = R0; // 14 + [ P0 ++ ] = R0; // 15 + + // Now set the CPLB entries we will need + + + + + + + + + + + + + + + + + + + + + + + + + + // Data area for the desired error + WR_MMR(DCPLB_ADDR0, 0x800, p0, r0); + WR_MMR(DCPLB_ADDR1, 0x1000, p0, r0); + WR_MMR(DCPLB_DATA0, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE, p0, r0); + WR_MMR(DCPLB_ADDR2, 0x2000, p0, r0); + WR_MMR(DCPLB_ADDR3, 0x3000, p0, r0); + WR_MMR(DCPLB_ADDR4, 0x4000, p0, r0); + WR_MMR(DCPLB_ADDR5, 0x5000, p0, r0); + WR_MMR(DCPLB_ADDR6, 0x6000, p0, r0); + WR_MMR(DCPLB_ADDR7, 0x7000, p0, r0); + + // CHECKREG segment + WR_MMR(DCPLB_ADDR14, 0xEFFFFC00, p0, r0); + WR_MMR(DCPLB_DATA14, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_WT|CPLB_L1_CACHABLE|CPLB_SUPV_WR|CPLB_USER_RW, p0, r0); + + // MMR space + WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); + WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); + + // setup interrupt controller with exception handler address + WR_MMR_LABEL(EVT3, handler, p0, r1); + WR_MMR_LABEL(EVT15, int_15, p0, r1); + WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); + WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); + + // enable CPLB + WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); + NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC + + // Address for slot 0 accesses + // LD32(p4, 0xEFFFFFF8); + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RETI = R0; + + // But first raise interrupt 15 so we can do one test + // in supervisor mode. + RAISE 15; + NOP; + + RTI; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +int_15: + // Interrupt 15 handler - needed to try supervisor access with exceptions enabled + //------------------------------------------------------- + // Protection violation - Illegal Supervisor Write Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(i1, 0x800); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA0); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA1); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); + + +X0: //[p1] = r1; // Exception should occur here + A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1 + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x800); + CHECKREG(r6, (FAULT_SUPV|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB0)); + CHECKREG_SYM(r7, X0, r0); // RETX should be value of X0 (HARDCODED ADDR!!) + + // go to user mode. and enable exceptions + LD32_LABEL(r0, User); + RTI; + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +User: + NOP;NOP;NOP;NOP;NOP; + + //------------------------------------------------------- + // Protection violation - Illegal User Write Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(i1, 0x1000); + LD32(r1, 0xDEADBEEF); + + + // values to fix up current test + LD32(p2, DCPLB_DATA1); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + // values for next test + LD32(p3, DCPLB_DATA2); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE); + +X1: //[p1] = r1; // Exception should occur here + A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1 + + // Now check that handler read correct values + + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x1000); + CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB1)); + CHECKREG_SYM(r7, X1, r0); // RETX should be value of X1 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + // Protection violation - Illegal User Read Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(i1, 0x2000); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA2); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RO|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA3); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + +X2: //[p1] = r1; // Exception should occur here + A0 = 0 || NOP || R0 = [ I1 ]; // test access with DAG1 + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x2000); + CHECKREG(r6, (FAULT_USER|FAULT_READ|FAULT_DAG1 | FAULT_CPLB2)); + CHECKREG_SYM(r7, X2, r0); // RETX should be value of X2 (HARDCODED ADDR!!) + + //------------------------------------------------------- + // Protection violation - Illegal Dirty Page Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(i1, 0x3000); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA3); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA4); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DA0ACC|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR); + + +X3: //[p1] = r1; // Exception should occur here + A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1 + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x3000); + CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB3)); + CHECKREG_SYM(r7, X3, r0); // RETX should be value of X3 (HARDCODED ADDR!!) + + //------------------------------------------------------- + // Protection violation - Illegal DAG1 Access + R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; + + LD32(i1, 0x4000); + LD32(r1, 0xDEADBEEF); + + LD32(p2, DCPLB_DATA4); + LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + LD32(p3, DCPLB_DATA5); + LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); + + +X4: //[p1] = r1; // Exception should occur here + A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1 + + + // Now check that handler read correct values + CHECKREG(r4,0x23); // supv and EXCPT_PROT + CHECKREG(r5, 0x4000); + CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB4)); + CHECKREG_SYM(r7, X4, r0); // RETX should be value of X4 (HARDCODED ADDR!!) + + //------------------------------------------------------- + // L1Miss not implemented yet - skip for now.... + +// //------------------------------------------------------- +// // Protection violation - L1 Miss +// r0=0;r1=0;r2=0;r3=0;r4=0;r5=0;r6=0;r7=0; +// +// LD32(p1, 0x6000); +// LD32(r1, 0xDEADBEEF); +// +// LD32(p2, DCPLB_DATA6); +// LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR); +// +// LD32(p3, DCPLB_DATA7); +// LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_USER_RW|CPLB_SUPV_WR); +// +// +//X6: //[p1] = r1; // Exception should occur here +// r0 = [p1]; +// +// +// // Now check that handler read correct values +// CHECKREG(r4,0x23); // supv and EXCPT_PROT +// CHECKREG(r5, 0x6000); +// // CHECKREG(r6, FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB6); +// CHECKREG_SYM(r7, X6, r0); // RETX should be value of X6 (HARDCODED ADDR!!) + + + //------------------------------------------------------- + dbg_pass; + + +handler: + // generic protection exception handler + // Inputs: + // p2: addr of CPLB entry to be modified ( current test) + // r2: new data for CPLB entry + // + // p3: addr of CPLB entry to be modified ( next test) + // r3: new data for CPLB entry + // + // Outputs: + // r4: SEQSTAT + // r5: DCPLB_FAULT_ADDR + // r6: DCPLB_STATUS + // r7: RETX (instruction addr where exception occurred) + + + R4 = SEQSTAT; // Get exception cause + + // read data addr which caused exception + RD_MMR(DCPLB_FAULT_ADDR, p0, r5); + RD_MMR(DCPLB_STATUS, p0, r6); + + // Reset status regs + WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r0); + WR_MMR(DCPLB_STATUS, 0, p0, r0); + + R7 = RETX; // get address of excepting instruction + + + // modify CPLB to allow access. Main pgm passes in addr and data + [ P2 ] = R2; + + // Set up for next test + [ P3 ] = R3; + + NOP;NOP;NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC; + + // return from exception and re-execute offending instruction + RTX; + + // Nops to work around ICache bug + NOP;NOP;NOP;NOP;NOP; + NOP;NOP;NOP;NOP;NOP; + + +.section MEM_0x800,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x1000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x2000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x3000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x4000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +.section MEM_0x5000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + +// Need a cache miss to test CPLB_L1REF +//.data 0x6000 +// .dd 0x00000000 +// .dd 0x00000000 +// .dd 0x00000000 +// .dd 0x00000000 + +.section MEM_0x7000,"aw" + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 + .dd 0x00000000 diff --git a/sim/testsuite/sim/bfin/load.s b/sim/testsuite/sim/bfin/load.s new file mode 100644 index 0000000..2fca3de --- /dev/null +++ b/sim/testsuite/sim/bfin/load.s @@ -0,0 +1,239 @@ +# Blackfin testcase for register load instructions +# mach: bfin + + + .include "testutils.inc" + + start + + .macro load32 num:req, reg0:req, reg1:req + imm32 \reg0 \num + imm32 \reg1 \num + CC = \reg0 == \reg1 + if CC jump 2f; + fail +2: + .endm + + .macro load32p num:req preg:req + imm32 r0 \num + imm32 \preg \num + r1 = \preg + cc = r0 == r1 + if CC jump 3f; + fail +3: + imm32 \preg 0 + .endm + + .macro load16z num:req reg0:req reg1:req + \reg0 = \num (Z); + imm32 \reg1 \num + CC = \reg0 == \reg1 + if CC jump 4f; + fail +4: + .endm + + .macro load16zp num:req reg:req + \reg = \num (Z); + imm32 r1 \num; + r0 = \reg; + cc = r0 == r1 + if CC jump 5f; + fail +5: + .endm + + .macro load16x num:req reg0:req reg1:req + \reg0 = \num (X); + imm32 \reg1, \num + CC = \reg0 == \reg1 + if CC jump 6f; + fail +6: + .endm + + /* Clobbers R0 */ + .macro loadinc preg0:req, preg1:req, dreg:req + loadsym \preg0, _buf + \preg1 = \preg0; + \dreg = \preg0; + [\preg0\()++] = \preg0; + \dreg += 4; + R0 = \preg0; + CC = \dreg == R0; + if CC jump 7f; + fail +7: + R0 = [ \preg1\() ]; + \dreg += -4; + CC = \dreg == R0; + if CC jump 8f; + fail +8: + .endm + + /* test a bunch of values */ + + /* load_immediate (Half-Word Load) + * register = constant + * reg_lo = uimm16; + * reg_hi = uimm16; + */ + + load32 0 R0 R1 + load32 0xFFFFFFFF R0 R1 + load32 0x55aaaa55 r0 r1 + load32 0x12345678 r0 r1 + load32 0x12345678 R0 R2 + load32 0x23456789 R0 R3 + load32 0x3456789a R0 R4 + load32 0x456789ab R0 R5 + load32 0x56789abc R0 R6 + load32 0x6789abcd R0 R7 + load32 0x789abcde R0 R0 + load32 0x89abcdef R1 R0 + load32 0x9abcdef0 R2 R0 + load32 0xabcdef01 R3 R0 + load32 0xbcdef012 R4 R0 + load32 0xcdef0123 R5 R0 + load32 0xdef01234 R6 R0 + load32 0xef012345 R7 R0 + + load32p 0xf0123456 P0 + load32p 0x01234567 P1 + load32p 0x12345678 P2 +.ifndef BFIN_HOST + load32p 0x23456789 P3 +.endif + load32p 0x3456789a P4 + load32p 0x456789ab P5 + load32p 0x56789abc SP + load32p 0x6789abcd FP + + load32p 0x789abcde I0 + load32p 0x89abcdef I1 + load32p 0x9abcdef0 I2 + load32p 0xabcdef01 I3 + load32p 0xbcdef012 M0 + load32p 0xcdef0123 M1 + load32p 0xdef01234 M2 + load32p 0xef012345 M3 + + load32p 0xf0123456 B0 + load32p 0x01234567 B1 + load32p 0x12345678 B2 + load32p 0x23456789 B3 + load32p 0x3456789a L0 + load32p 0x456789ab L1 + load32p 0x56789abc L2 + load32p 0x6789abcd L3 + + /* Zero Extended */ + load16z 0x1234 R0 R1 + load16z 0x2345 R0 R1 + load16z 0x3456 R0 R2 + load16z 0x4567 R0 R3 + load16z 0x5678 R0 R4 + load16z 0x6789 R0 R5 + load16z 0x789a R0 R6 + load16z 0x89ab R0 R7 + load16z 0x9abc R1 R0 + load16z 0xabcd R2 R0 + load16z 0xbcde R3 R0 + load16z 0xcdef R4 R0 + load16z 0xdef0 R5 R0 + load16z 0xef01 R6 R0 + load16z 0xf012 R7 R0 + + load16zp 0x0123 P0 + load16zp 0x1234 P1 + load16zp 0x1234 p2 +.ifndef BFIN_HOST + load16zp 0x2345 p3 +.endif + load16zp 0x3456 p4 + load16zp 0x4567 p5 + load16zp 0x5678 sp + load16zp 0x6789 fp + load16zp 0x789a i0 + load16zp 0x89ab i1 + load16zp 0x9abc i2 + load16zp 0xabcd i3 + load16zp 0xbcde m0 + load16zp 0xcdef m1 + load16zp 0xdef0 m2 + load16zp 0xef01 m3 + load16zp 0xf012 b0 + load16zp 0x0123 b1 + load16zp 0x1234 b2 + load16zp 0x2345 b3 + load16zp 0x3456 l0 + load16zp 0x4567 l1 + load16zp 0x5678 l2 + load16zp 0x6789 l3 + + /* Sign Extended */ + load16x 0x20 R0 R1 + load16x 0x3F R0 R1 + load16x -0x20 R0 R1 + load16x -0x3F R0 R1 + load16x 0x1234 R0 R1 + load16x 0x2345 R0 R1 + load16x 0x3456 R0 R2 + load16x 0x4567 R0 R3 + load16x 0x5678 R0 R4 + load16x 0x6789 R0 R5 + load16x 0x789a R0 R6 + load16x 0x09ab R0 R7 + load16x -0x1abc R1 R0 + load16x -0x2bcd R2 R0 + load16x -0x3cde R3 R0 + load16x -0x4def R4 R0 + load16x -0x5ef0 R5 R0 + load16x -0x6f01 R6 R0 + load16x -0x7012 R7 R0 + + loadinc P0, P1, R1 + loadinc P1, P2, R1 + loadinc P2, P1, R2 +.ifndef BFIN_HOST + loadinc P3, P4, R3 +.endif + loadinc P4, P5, R4 + loadinc FP, P0, R7 + loadinc P0, I0, R1 + loadinc P1, I1, R1 + loadinc P2, I2, R1 +.ifndef BFIN_HOST + loadinc P3, I0, R1 +.endif + loadinc P4, I2, R1 + loadinc P5, I3, R1 + + A1 = A0 = 0; + R0 = 0x01 (Z); + A0.x = R0; + imm32 r4, 0x32e02d1a + A1.x = R4; + A0.w = A1.x; + R3 = A0.w; + R2 = A0.x; + imm32 r0, 0x0000001a + imm32 r1, 0x00000001 + CC = R1 == R2; + if CC jump 1f; + fail +1: + CC = R0 == R3 + if CC jump 2f; + fail +2: + pass + +.data +_buf: + .rept 0x80 + .long 0 + .endr diff --git a/sim/testsuite/sim/bfin/logic.s b/sim/testsuite/sim/bfin/logic.s new file mode 100644 index 0000000..9a41ccd --- /dev/null +++ b/sim/testsuite/sim/bfin/logic.s @@ -0,0 +1,64 @@ +// test program for microcontroller instructions +// Test instructions +// r4 = r2 & r3; +// r4 = r2 | r3; +// r4 = r2 ^ r3; +// r4 = ~ r2; +# mach: bfin + +.include "testutils.inc" + start + + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + + R7 = R0 & R1; + DBGA ( R7.L , 0x1111 ); + DBGA ( R7.H , 0x1111 ); + + R7 = R2 & R3; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + + R7 = R0 | R1; + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + + R7 = R2 | R3; + DBGA ( R7.L , 0x000f ); + DBGA ( R7.H , 0x0000 ); + + R7 = R0 ^ R1; + DBGA ( R7.L , 0xeeee ); + DBGA ( R7.H , 0xeeee ); + + R7 = R2 ^ R3; + DBGA ( R7.L , 0x000e ); + DBGA ( R7.H , 0x0000 ); + + R7 = ~ R0; + DBGA ( R7.L , 0xeeee ); + DBGA ( R7.H , 0xeeee ); + + R7 = ~ R2; + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0xffff ); + + pass + + .data +data0: + .dw 0x1111 + .dw 0x1111 + .dw 0xffff + .dw 0xffff + .dw 0x0001 + .dw 0x0000 + .dw 0x000f + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/loop_snafu.s b/sim/testsuite/sim/bfin/loop_snafu.s new file mode 100644 index 0000000..b1e3664 --- /dev/null +++ b/sim/testsuite/sim/bfin/loop_snafu.s @@ -0,0 +1,28 @@ +# mach: bfin + +.include "testutils.inc" + start + + r5=10; + p1=r5; + r7=20; + lsetup (lstart, lend) lc0=p1; + +lstart: + nop; + nop; + nop; + nop; + jump lend; + nop; + nop; + nop; +lend: + r7 += -1; + + nop; + nop; + + dbga( r7.l,10); + + pass diff --git a/sim/testsuite/sim/bfin/loop_strncpy.s b/sim/testsuite/sim/bfin/loop_strncpy.s new file mode 100644 index 0000000..13b3711 --- /dev/null +++ b/sim/testsuite/sim/bfin/loop_strncpy.s @@ -0,0 +1,76 @@ +# Blackfin testcase for loop counter values when jumping out from the last insn +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + loadsym r1, dest; + r0 = r1; + loadsym r1, src; + r2 = 0x10; + +_strncpy: + CC = R2 == 0; + if CC JUMP 4f; + + P2 = R2 ; /* size */ + P0 = R0 ; /* dst*/ + P1 = R1 ; /* src*/ + + LSETUP (1f, 2f) LC0 = P2; +1: + R1 = B [P1++] (Z); + B [P0++] = R1; + CC = R1 == 0; +2: + if CC jump 3f; + + fail + + /* if src is shorter than n, we need to null pad bytes in dest + * but, we can get here when the last byte is zero, and we don't + * want to copy an extra byte at the end, so we need to check + */ +3: + R2 = LC0; + CHECKREG R2, 0x0a; + + CC = R2 + if ! CC jump 4f; + + LSETUP(5f, 5f) LC0; +5: + B [P0++] = R1; + +4: + loadsym P1, answer; + P0 = R0; + p2 = 0x20; + LSETUP (6f, 7f) LC0 = P2; +6: + R1 = B [P0++]; + R2 = B [P1++]; + CC = R1 == R2 + IF ! CC JUMP wrong; +7: + NOP; + + pass + +wrong: + fail + + .data +dest: + .db 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F + .db 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F + +src: + .db 0x21, 0x22, 0x23, 0x24, 0x25, 0x00, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30 + +answer: + .db 0x21, 0x22, 0x23, 0x24, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + .db 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F diff --git a/sim/testsuite/sim/bfin/lp0.s b/sim/testsuite/sim/bfin/lp0.s new file mode 100644 index 0000000..dd7bc30 --- /dev/null +++ b/sim/testsuite/sim/bfin/lp0.s @@ -0,0 +1,17 @@ +// Assert that loops can have coincidental loop ends. +# mach: bfin + +.include "testutils.inc" + start + + + P0 = 3; + R1 = 0; + LSETUP ( out0 , out1 ) LC0 = P0; +out0: + LSETUP ( out1 , out1 ) LC1 = P0; +out1: + R1 += 1; + + DBGA ( R1.L , 9 ); + pass diff --git a/sim/testsuite/sim/bfin/lp1.s b/sim/testsuite/sim/bfin/lp1.s new file mode 100644 index 0000000..89fa2a9 --- /dev/null +++ b/sim/testsuite/sim/bfin/lp1.s @@ -0,0 +1,16 @@ +# mach: bfin +.include "testutils.inc" + start + + P0 = 10; + + LSETUP ( xxx , yyy ) LC0 = P0; +xxx: + R1 += 1; + CC = R1 == 3; +yyy: + IF CC JUMP zzz; + R3 = 7; +zzz: + DBGA ( R1.L , 3 ); + pass diff --git a/sim/testsuite/sim/bfin/lsetup.s b/sim/testsuite/sim/bfin/lsetup.s new file mode 100644 index 0000000..ac39613 --- /dev/null +++ b/sim/testsuite/sim/bfin/lsetup.s @@ -0,0 +1,109 @@ +# Blackfin testcase for playing with LSETUP +# mach: bfin + + .include "testutils.inc" + + start + + R0 = 0x123; + P0 = R0; + LSETUP (.L1, .L1) LC0 = P0; +.L1: + R0 += -1; + + R1 = 0; + CC = R1 == R0; + IF CC JUMP 1f; + fail +1: + p0=10; + loadsym i0, _buf + imm32 r0, 0x12345678 + LSETUP(.L2, .L3) lc0 = p0; +.L2: + [i0++] = r0; +.L3: + [i0++] = r0; + + loadsym R1, _buf + R0 = 0x50; + R1 = R0 + R1; + R0 = I0; + CC = R0 == R1; + if CC JUMP 2f; + fail +2: + + r5=10; + p1=r5; + r7=20; + lsetup (.L4, .L5) lc0=p1; +.L4: + nop; + nop; + nop; + nop; + jump .L5; + nop; + nop; + nop; +.L5: + r7 += -1; + + R0 = 10 (Z); + CC = R7 == R0; + if CC jump 3f; + fail +3: + r1 = 1; + r2 = 2; + r0 = 0; + p1 = 10; + loadsym p0, _buf; + lsetup (.L6, .L7) lc0 = p1; +.L6: + [p0++] = r1; +.L7: + [p0++] = r2; + + r3 = P0; + loadsym r1, _buf + r0 = 80; + r1 = r1 + r0; + CC = R1 == R3 + if CC jump 4f; + fail +4: + + R0 = 1; + R1 = 2; + R2 = 3; + R4 = 4; + P1 = R1; + LSETUP (.L8, .L8) LC0 = P1; + R5 = 5; + R6 = 6; + R7 = 7; +.L8: + R1 += 1; + + R7 = 4; + CC = R7 == R1; + if CC jump 5f; + fail +5: + P1 = R1; + LSETUP (.L9, .L9 ) LC1 = P1; +.L9: + R1 += 1; + R7 = 8; + if CC jump 6f; + fail +6: + pass + +.data +_buf: + .rept 0x80 + .long 0 + .endr diff --git a/sim/testsuite/sim/bfin/m0boundary.s b/sim/testsuite/sim/bfin/m0boundary.s new file mode 100644 index 0000000..5995d88 --- /dev/null +++ b/sim/testsuite/sim/bfin/m0boundary.s @@ -0,0 +1,46 @@ +# mach: bfin + +.include "testutils.inc" + start + +// setup a circular buffer calculation based on illegal register values + I0 = 0xf2ef (Z); + I0.H = 0xff88; + + L0 = 0xbd5f (Z); + L0.H = 0xea9b; + + M0 = 0x0000 (Z); + M0.H = 0x8000; + + B0 = 0x3fb9 (Z); + B0.H = 0xff80; + +op1: + I0 -= M0; + + R0 = I0; + DBGA ( R0.H , 0x7f88 ); + DBGA ( R0.L , 0xf2ef ); + +// setup a circular buffer calculation based on illegal register values + I0 = 0xf2ef (Z); + I0.H = 0xff88; + + L0 = 0xbd5f (Z); + L0.H = 0xea9b; + + M0 = 0x0001 (Z); + M0.H = 0x8000; + + B0 = 0x3fb9 (Z); + B0.H = 0xff80; + +op2: + I0 -= M0; + + R0 = I0; + DBGA ( R0.H , 0x7f88 ); + DBGA ( R0.L , 0xf2ee ); + + pass diff --git a/sim/testsuite/sim/bfin/m1.S b/sim/testsuite/sim/bfin/m1.S new file mode 100644 index 0000000..5ddc5d3 --- /dev/null +++ b/sim/testsuite/sim/bfin/m1.S @@ -0,0 +1,58 @@ +// MAC test program. +// Test for positive and negative saturation using +// SIGNED FRACTIONAL mode. +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + +// load r0=0x00007fff +// load r1=0x00007fff + loadsym p0, data0 + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + + R5 = 0; + R4 = 0; + BITSET( R4 , 9 ); + A1 = A0 = 0; + +LOOP1: + A1 -= R0.L * R1.L, A0 += R0.L * R1.L; +//_DBG a1; +//_DBG a0; + R4 += -1; + CC = R4 == R5; + IF !CC JUMP LOOP1; +R3 = ASTAT; +CHECKREG R3, (_AV1S|_AV1|_AV0S|_AV0|_AC0|_AC0_COPY|_CC|_AZ); + + _DBG A1; + _DBG A0; + + R6 = A1.w; + _DBG ASTAT; + R7.L = A1.x; + R3 = ASTAT; + _DBG r3; + CHECKREG R3, (_AV1S|_AV1|_AV0S|_AV0|_AC0|_AC0_COPY|_CC|_AZ); + + CHECKREG R6, 0; + CHECKREG R7, 0x0000FF80; + R6 = A0.w; + R7.L = A0.x; + CHECKREG R6, 0xffffffff; + CHECKREG R7, 0x7f; + + pass + + .data 0x1000; +data0: + .dw 0x7fff + .dw 0x0000 + .dw 0x7fff + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m10.s b/sim/testsuite/sim/bfin/m10.s new file mode 100644 index 0000000..5feb42f --- /dev/null +++ b/sim/testsuite/sim/bfin/m10.s @@ -0,0 +1,63 @@ +# mach: bfin + +// Test extraction from accumulators: +// ROUND/TRUNCATE in UNSIGNED FRACTIONAL mode +// test ops: "+=" + +.include "testutils.inc" + start + + +// load r0=0xfffef000 +// load r1=0xfffff000 +// load r2=0x00008000 +// load r3=0x00018000 +// load r4=0x0000007f + loadsym P0, data0 + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// round +// 0x00fffef000 -> 0xffff + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1, R5.L = A0 (FU); + DBGA ( R5.L , 0xffff ); + DBGA ( R5.H , 0xffff ); + +// truncate +// 0x00fffef00 -> 0xfffe + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1, R5.L = A0 (TFU); + DBGA ( R5.L , 0xfffe ); + DBGA ( R5.H , 0xfffe ); + +// round +// 0x00fffff000 -> 0xffff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R5.H = A1, R5.L = A0 (FU); + DBGA ( R5.L , 0xffff ); + DBGA ( R5.H , 0xffff ); + + pass + + .data; +data0: + .dw 0xf000 + .dw 0xfffe + .dw 0xf000 + .dw 0xffff + .dw 0x8000 + .dw 0x0000 + .dw 0x8000 + .dw 0x0001 + .dw 0x007f + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m11.s b/sim/testsuite/sim/bfin/m11.s new file mode 100644 index 0000000..843c0ab --- /dev/null +++ b/sim/testsuite/sim/bfin/m11.s @@ -0,0 +1,72 @@ +// Test extraction from accumulators: +// SCALE in SIGNED FRACTIONAL mode +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x3fff0000 +// load r1=0x0fffc000 +// load r2=0x7ff00000 +// load r3=0x80100000 +// load r4=0x000000ff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// SCALE +// 0x003fff0000 -> SCALE 0x7ffe + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1, R5.L = A0 (S2RND); + DBGA ( R5.L , 0x7ffe ); + DBGA ( R5.H , 0x7ffe ); + +// SCALE +// 0x000fffc000 -> SCALE 0x2000 + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R5.H = A1, R5.L = A0 (S2RND); + DBGA ( R5.L , 0x2000 ); + DBGA ( R5.H , 0x2000 ); + +// SCALE +// 0x007ff00000 -> SCALE 0x7fff + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + R5.H = A1, R5.L = A0 (S2RND); + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + +// SCALE +// 0xff80100000 -> SCALE 0x8000 + A1 = A0 = 0; + A1.w = R3; + A0.w = R3; + A1.x = R4.L; + A0.x = R4.L; + R5.H = A1, R5.L = A0 (S2RND); + DBGA ( R5.L , 0x8000 ); + DBGA ( R5.H , 0x8000 ); + + pass + + .data; +data0: + .dw 0x0000 + .dw 0x3fff + .dw 0xc000 + .dw 0x0fff + .dw 0x0000 + .dw 0x7ff0 + .dw 0x0000 + .dw 0x8010 + .dw 0x00ff + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m12.s b/sim/testsuite/sim/bfin/m12.s new file mode 100644 index 0000000..37306e7 --- /dev/null +++ b/sim/testsuite/sim/bfin/m12.s @@ -0,0 +1,74 @@ +// Test extraction from accumulators: +// SCALE in SIGNED INTEGER mode +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x00000fff +// load r1=0x00007fff +// load r2=0xffffffff +// load r3=0xffff0fff +// load r4=0x000000ff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// SCALE +// 0x0000000fff -> SCALE 0x1ffe + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1, R5.L = A0 (ISS2); + DBGA ( R5.L , 0x1ffe ); + DBGA ( R5.H , 0x1ffe ); + +// SCALE +// 0x0000007fff -> SCALE 0x7fff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R5.H = A1, R5.L = A0 (ISS2); + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + +// SCALE +// 0xffffffffff -> SCALE 0xfffe + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + A1.x = R4.L; + A0.x = R4.L; + R5.H = A1, R5.L = A0 (ISS2); + DBGA ( R5.L , 0xfffe ); + DBGA ( R5.H , 0xfffe ); + +// SCALE +// 0xffffff0fff -> SCALE 0x8000 + A1 = A0 = 0; + A1.w = R3; + A0.w = R3; + A1.x = R4.L; + A0.x = R4.L; + R5.H = A1, R5.L = A0 (ISS2); + DBGA ( R5.L , 0x8000 ); + DBGA ( R5.H , 0x8000 ); + + pass + + .data +data0: + .dw 0x0fff + .dw 0x0000 + .dw 0x7fff + .dw 0x0000 + .dw 0xffff + .dw 0xffff + .dw 0x0fff + .dw 0xffff + .dw 0x00ff + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m13.s b/sim/testsuite/sim/bfin/m13.s new file mode 100644 index 0000000..05547a7 --- /dev/null +++ b/sim/testsuite/sim/bfin/m13.s @@ -0,0 +1,93 @@ +// Test extraction from accumulators: +// SIGNED FRACTIONAL and SIGNED INT mode into register PAIR +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x7ffffff0 +// load r1=0xfffffff0 +// load r2=0x0fffffff +// load r3=0x80100000 +// load r4=0x000000ff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// extract +// 0x007ffffff0 -> 0x7fffffff0 + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R7 = A1, R6 = A0; + DBGA ( R7.L , 0xfff0 ); + DBGA ( R7.H , 0x7fff ); + DBGA ( R6.L , 0xfff0 ); + DBGA ( R6.H , 0x7fff ); + +// extract with saturate +// 0x00fffffff0 -> 0x7ffffffff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R7 = A1, R6 = A0; + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x7fff ); + +// extract with saturate negative +// 0xff0ffffff0 -> 0x80000000 + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + A1.x = R4.L; + A0.x = R4.L; + R7 = A1, R6 = A0; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x8000 ); + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + +// extract integer (same as fract) +// 0x007ffffff0 -> 0x7fffffff0 + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R7 = A1, R6 = A0 (IS); + DBGA ( R7.L , 0xfff0 ); + DBGA ( R7.H , 0x7fff ); + DBGA ( R6.L , 0xfff0 ); + DBGA ( R6.H , 0x7fff ); + +// extract with saturate negative +// 0xff0ffffff0 -> 0x80000000 + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + A1.x = R4.L; + A0.x = R4.L; + R7 = A1, R6 = A0 (IS); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x8000 ); + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + + pass + + .data +data0: + .dw 0xfff0 + .dw 0x7fff + .dw 0xfff0 + .dw 0xffff + .dw 0xffff + .dw 0x0fff + .dw 0x0000 + .dw 0x8010 + .dw 0x00ff + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m14.s b/sim/testsuite/sim/bfin/m14.s new file mode 100644 index 0000000..bd3134e --- /dev/null +++ b/sim/testsuite/sim/bfin/m14.s @@ -0,0 +1,82 @@ +// Test extraction from accumulators: +// UNSIGNED FRACTIONAL and SIGNED INT mode into register PAIR +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x7ffffff0 +// load r1=0xfffffff0 +// load r2=0x0fffffff +// load r3=0x00000001 +// load r4=0x000000ff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// extract +// 0x00fffffff0 -> 0xffffffff0 + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R7 = A1, R6 = A0 (FU); + DBGA ( R7.L , 0xfff0 ); + DBGA ( R7.H , 0xffff ); + DBGA ( R6.L , 0xfff0 ); + DBGA ( R6.H , 0xffff ); + +// extract with saturation +// 0x01fffffff0 -> 0xfffffffff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + A1.x = R3.L; + A0.x = R3.L; + R7 = A1, R6 = A0 (FU); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + +// extract with saturation +// 0xfffffffff0 -> 0xfffffffff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + A1.x = R4.L; + A0.x = R4.L; + R7 = A1, R6 = A0 (FU); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + +// extract unsigned +// 0x00fffffff0 -> 0xffffffff0 + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R7 = A1, R6 = A0 (FU); + DBGA ( R7.L , 0xfff0 ); + DBGA ( R7.H , 0xffff ); + DBGA ( R6.L , 0xfff0 ); + DBGA ( R6.H , 0xffff ); + + pass + + .data +data0: + .dw 0xfff0 + .dw 0x7fff + .dw 0xfff0 + .dw 0xffff + .dw 0xffff + .dw 0x0fff + .dw 0x0001 + .dw 0x0000 + .dw 0x00ff + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m15.s b/sim/testsuite/sim/bfin/m15.s new file mode 100644 index 0000000..e429232 --- /dev/null +++ b/sim/testsuite/sim/bfin/m15.s @@ -0,0 +1,80 @@ +// Test extraction from accumulators: +// SIGNED FRACTIONAL and SIGNED INT mode into register PAIR with SCALE +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x0ffffff0 +// load r1=0x7ffffff0 +// load r2=0x0fffffff +// load r3=0x80100000 +// load r4=0x000000ff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// extract +// 0x000ffffff0 -> 0x1ffffffe0 + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R7 = A1, R6 = A0 (S2RND); + DBGA ( R7.L , 0xffe0 ); + DBGA ( R7.H , 0x1fff ); + DBGA ( R6.L , 0xffe0 ); + DBGA ( R6.H , 0x1fff ); + +// extract (saturate) +// 0x007ffffff0 -> 0x7ffffffff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R7 = A1, R6 = A0 (S2RND); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x7fff ); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x7fff ); + +// extract (saturate negative) +// 0xff0ffffff0 -> 0x80000000 + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + A1.x = R4.L; + A0.x = R4.L; + R7 = A1, R6 = A0 (S2RND); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x8000 ); + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + +// extract int +// 0x000ffffff0 -> 0x1ffffffe0 + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R7 = A1, R6 = A0 (ISS2); + DBGA ( R7.L , 0xffe0 ); + DBGA ( R7.H , 0x1fff ); + DBGA ( R6.L , 0xffe0 ); + DBGA ( R6.H , 0x1fff ); + + pass + + .data +data0: + .dw 0xfff0 + .dw 0x0fff + .dw 0xfff0 + .dw 0x7fff + .dw 0xffff + .dw 0x0fff + .dw 0x0000 + .dw 0x8010 + .dw 0x00ff + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m16.s b/sim/testsuite/sim/bfin/m16.s new file mode 100644 index 0000000..9cbc57c --- /dev/null +++ b/sim/testsuite/sim/bfin/m16.s @@ -0,0 +1,65 @@ +// Test various moves to single register half +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x7fffffff +// load r1=0x00ffffff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// extract only to high half + R5 = 0; + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1; + DBGA ( R5.L , 0x0000 ); + DBGA ( R5.H , 0x7fff ); + +// extract only to low half + R5 = 0; + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.L = A0; + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x0000 ); + +// extract only to high half + R5 = 0; + A1 = A0 = 0; + R5.H = ( A1 += R0.H * R0.H ), A0 += R0.H * R0.H; + DBGA ( R5.L , 0x0000 ); + DBGA ( R5.H , 0x7ffe ); + +// extract only to low half + R5 = 0; + A1 = A0 = 0; + A1 += R0.H * R0.H, R5.L = ( A0 += R0.H * R0.H ); + DBGA ( R5.L , 0x7ffe ); + DBGA ( R5.H , 0x0000 ); + + pass + + .data +data0: + .dw 0xffff + .dw 0x7fff + .dw 0xffff + .dw 0x00ff + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m17.s b/sim/testsuite/sim/bfin/m17.s new file mode 100644 index 0000000..c7aec4b --- /dev/null +++ b/sim/testsuite/sim/bfin/m17.s @@ -0,0 +1,74 @@ +// Test various moves to single register +# mach: bfin + + +.include "testutils.inc" + start + + +// load r0=0x7fffffff +// load r1=0x00ffffff +// load r2=0xf0000000 +// load r3=0x0000007f + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + +// extract only to high register + R5 = 0; + R4 = 0; + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5 = A1; + DBGA ( R4.L , 0x0000 ); + DBGA ( R4.H , 0x0000 ); + DBGA ( R5.L , 0xffff ); + DBGA ( R5.H , 0x7fff ); + +// extract only to low register + R5 = 0; + R4 = 0; + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R4 = A0; + DBGA ( R4.L , 0xffff ); + DBGA ( R4.H , 0x7fff ); + DBGA ( R5.L , 0x0000 ); + DBGA ( R5.H , 0x0000 ); + +// extract only to high reg + R5 = 0; + R4 = 0; + A1 = A0 = 0; + R5 = ( A1 += R0.H * R0.H ), A0 += R0.H * R0.H; + DBGA ( R4.L , 0x0000 ); + DBGA ( R4.H , 0x0000 ); + DBGA ( R5.L , 0x0002 ); + DBGA ( R5.H , 0x7ffe ); + +// extract only to low reg + R5 = 0; + R4 = 0; + A1 = A0 = 0; + A1 += R0.H * R0.H, R4 = ( A0 += R0.H * R0.H ); + DBGA ( R4.L , 0x0002 ); + DBGA ( R4.H , 0x7ffe ); + DBGA ( R5.L , 0x0000 ); + DBGA ( R5.H , 0x0000 ); + + pass + + .data +data0: + .dw 0xffff + .dw 0x7fff + .dw 0xffff + .dw 0x00ff + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m2.s b/sim/testsuite/sim/bfin/m2.s new file mode 100644 index 0000000..2ff155c --- /dev/null +++ b/sim/testsuite/sim/bfin/m2.s @@ -0,0 +1,263 @@ +// MAC test program. +// Test basic edge values +// SIGNED FRACTIONAL mode +// test ops: "+=" "-=" "=" "NOP" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80007fff +// load r1=0x80007fff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// 0x7fff * 0x7fff = 0x007ffe0002 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 += R0.L * R1.L, A0 += R0.L * R1.L; + R6 = A1.w; + _DBG ASTAT; + _DBG A0; + R7.L = A1.x; + _DBG ASTAT; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x7ffe ); + DBGA ( R7.L , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// 0x8000 * 0x7fff = 0xff80010000 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 += R0.H * R1.L, A0 += R0.H * R1.L; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8001 ); + DBGA ( R7.L , 0xffff ); + _DBG ASTAT; + R7 = ASTAT; + DBGA (R7.H, 0x0); + DBGA (R7.L, 0x0); + +// 0x8000 * 0x8000 = 0x007fffffff + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 += R0.H * R1.H, A0 += R0.H * R1.H; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + DBGA ( R7.L , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// saturate positive by first loading large value into accums +// expected value is 0x7fffffffff + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A1.x = R3.L; + A0.w = R2; + A0.x = R3.L; + A1 += R0.L * R1.L, A0 += R0.L * R1.L; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0x007f ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate negative +// expected value is 0x8000000000 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.x = R4.L; + A0.x = R4.L; + A1 += R0.L * R1.H, A0 += R0.L * R1.H; + R6 = A1.w; + _DBG ASTAT; + R7.L = A1.x; + _DBG ASTAT; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xff80 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate positive with "-=" +// expected value is 0x7fffffffff + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A1.x = R3.L; + A0.w = R2; + A0.x = R3.L; + A1 -= R0.H * R1.L, A0 -= R0.H * R1.L; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0x007f ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 ); + +// saturate negative with "-=" +// expected value is 0x8000000000 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.x = R4.L; + A0.x = R4.L; + A1 -= R0.L * R1.L, A0 -= R0.L * R1.L; + R6 = A1.w; + _DBG ASTAT; + R7.L = A1.x; + _DBG ASTAT; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xff80 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 ); + +// 0x8000 * 0x8000 = 0xff80000001 with "-=" + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 -= R0.H * R1.H, A0 -= R0.H * R1.H; + R6 = A1.w; + _DBG ASTAT; + R7.L = A1.x; + _DBG ASTAT; + + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + DBGA ( R7.L , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// 0x7fff * 0x7fff = 0x007ffe0002 with "=" + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 += R0.L * R1.L, A0 += R0.L * R1.L; + A1 = R0.L * R1.L, A0 = R0.L * R1.L; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x7ffe ); + DBGA ( R7.L , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// 0x7fff * 0x7fff = 0x007ffe0002 with "NOP" + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 += R0.L * R1.L; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x7ffe ); + DBGA ( R7.L , 0x0000 ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// 0x8000 * 0x8000 = 0x007fffffff with "NOP" + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1 += R0.H * R1.H; + _DBG A1; + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + DBGA ( R7.L , 0x0000 ); + + R6 = A0.w; + _DBG ASTAT; + R7.L = A0.x; + _DBG ASTAT; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + R7 = ASTAT; _dbg astat; +//AV1 AV1S should be 0. + DBGA ( R7.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + + _DBG ASTAT; + A1 = A0 = 0; + _DBG A1; + _DBG R0; _DBG R1; + A1 += R0.L * R1.L; // make sure overflow flag is not set to zero + _DBG A1; + _DBG ASTAT; + R7 = ASTAT; +//AV1S should be 0. + DBGA ( R7.H, 0x0000 ); + DBGA ( R7.L, 0x0000 ); + + pass + + .data +data0: + .dw 0x7fff + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m3.s b/sim/testsuite/sim/bfin/m3.s new file mode 100644 index 0000000..116263c --- /dev/null +++ b/sim/testsuite/sim/bfin/m3.s @@ -0,0 +1,138 @@ +// MAC test program. +// Test basic edge values +// UNSIGNED FRACTIONAL mode U +// test ops: "+=" "-=" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80007fff +// load r1=0x80007fff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 +// load r5=0xffffffff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + + dbga(r0.h, 0x8000); + dbga(r0.l, 0x7fff); + dbga(r1.h, 0x8000); + dbga(r1.l, 0x7fff); + dbga(r2.h, 0xf000); + dbga(r2.l, 0); + +// 0x8000 * 0x7fff = 0x003fff8000 + A1 = A0 = 0; + A1 += R0.H * R1.L, A0 += R0.H * R1.L (FU); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x3fff ); + DBGA ( R7.L , 0x0000 ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x3fff ); + DBGA ( R7.L , 0x0000 ); + +// 0x8000 * 0x8000 = 0x0040000000 + A1 = A0 = 0; + A1 += R0.H * R1.H, A0 += R0.H * R1.H (FU); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + DBGA ( R7.L , 0x0000 ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + DBGA ( R7.L , 0x0000 ); + +// 0xffff * 0xffff = 0x00fffe0001 + A1 = A0 = 0; + A1 += R5.H * R5.H, A0 += R5.H * R5.H (FU); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0xfffe ); + DBGA ( R7.L , 0x0000 ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0xfffe ); + DBGA ( R7.L , 0x0000 ); + +// saturate high by first loading large value into accums +// expected value is 0xffffffffff + A1 = A0 = 0; + A1.w = R5; + A1.x = R5.L; + A0.w = R5; + A0.x = R5.L; + A1 += R5.H * R5.H, A0 += R5.H * R5.H (FU); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0xffff ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0xffff ); + +// saturate low with "-=" +// expected value is 0x0000000000 + A1 = A0 = 0; + A1 -= R4.L * R4.L, A0 -= R4.L * R4.L (FU); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + +// saturate low with "-=" +// expected value is 0x0000000000 + A1 = A0 = 0; + A1 -= R1.H * R0.H, A0 -= R1.H * R0.H (FU); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + + pass + + .data +data0: + .dw 0x7fff + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 + .dw 0xffff + .dw 0xffff diff --git a/sim/testsuite/sim/bfin/m4.s b/sim/testsuite/sim/bfin/m4.s new file mode 100644 index 0000000..8977063 --- /dev/null +++ b/sim/testsuite/sim/bfin/m4.s @@ -0,0 +1,124 @@ +// MAC test program. +// Test basic edge values +// SIGNED INTEGER mode +// test ops: "+=" "-=" "=" "NOP" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80007fff +// load r1=0x80007fff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// 0x7fff * 0x7fff = 0x003fff0001 + A1 = A0 = 0; + A1 += R0.L * R1.L, A0 += R0.L * R1.L (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x3fff ); + DBGA ( R7.L , 0x0000 ); + +// 0x8000 * 0x7fff = 0xffc0008000 + A1 = A0 = 0; + A1 += R0.H * R1.L, A0 += R0.H * R1.L (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0xc000 ); + DBGA ( R7.L , 0xffff ); + +// 0x8000 * 0x8000 = 0x0040000000 + A1 = A0 = 0; + A1 += R0.H * R1.H, A0 += R0.H * R1.H (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + DBGA ( R7.L , 0x0000 ); + +// saturate positive by first loading large value into accums +// expected value is 0x7fffffffff + A1 = A0 = 0; + A1.w = R2; + A1.x = R3.L; + A0.w = R2; + A0.x = R3.L; + A1 += R0.L * R1.L, A0 += R0.L * R1.L (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0x007f ); + +// saturate negative +// expected value is 0x8000000000 + A1 = A0 = 0; + A1.x = R4.L; + A0.x = R4.L; + A1 += R0.L * R1.H, A0 += R0.L * R1.H (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xff80 ); + +// saturate positive with "-=" +// expected value is 0x7fffffffff + A1 = A0 = 0; + A1.w = R2; + A1.x = R3.L; + A0.w = R2; + A0.x = R3.L; + A1 -= R0.H * R1.L, A0 -= R0.H * R1.L (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0x007f ); + +// saturate negative with "-=" +// expected value is 0x8000000000 + A1 = A0 = 0; + A1.x = R4.L; + A0.x = R4.L; + A1 -= R0.L * R1.L, A0 -= R0.L * R1.L (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xff80 ); + +// 0x8000 * 0x8000 = 0xffc0000000 with "-=" + A1 = A0 = 0; + A1 -= R0.H * R1.H, A0 -= R0.H * R1.H (IS); + R6 = A1.w; + R7.L = A1.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xc000 ); + DBGA ( R7.L , 0xffff ); + + pass + + .data 0x1000; +data0: + .dw 0x7fff + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m5.s b/sim/testsuite/sim/bfin/m5.s new file mode 100644 index 0000000..e39a2e0 --- /dev/null +++ b/sim/testsuite/sim/bfin/m5.s @@ -0,0 +1,153 @@ +// Test result extraction of mac instructions. +// Test basic edge values +// SIGNED FRACTIONAL mode into SINGLE destination register +// test ops: "+=" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80007fff +// load r1=0x80007fff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 + loadsym p0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// simple extraction with no saturation +// 0x7fff * 0x7fff = 0x007ffe0002 -> 0x7ffe + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + R5.H = (A1 += R0.L * R1.L), R5.L = (A0 += R0.L * R1.L); + DBGA ( R5.L , 0x7ffe ); + DBGA ( R5.H , 0x7ffe ); + _DBG ASTAT; + R7 = ASTAT; + DBGA (R7.H, 0x0); + DBGA (R7.L, 0x0); + +// positive saturation at 32 bits +// 0x0 * 0x0 + 0x7ff0000000 -> 0x7fff + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A1.x = R3.L; + A0.x = R3.L; + A0.w = R2; + R5.H = (A1 += R0.L * R2.L), R5.L = (A0 += R0.L * R2.L); + _DBG A1; + _DBG A0; + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + _DBG ASTAT; + R7 = ASTAT; + _DBG R7; + DBGA (R7.H, 0x300); + DBGA (R7.L, 0x8); + +// positive saturation at 32 bits +// 0x7fff * 0x7fff + 0x7ff0000000 -> 0x7fff + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A1.x = R3.L; + A0.w = R2; + A0.x = R3.L; + R5.H = (A1 += R0.L * R1.L), R5.L = (A0 += R0.L * R1.L); + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + _DBG ASTAT; + R7 = ASTAT; + DBGA (R7.H, 0x30f); + DBGA (R7.L, 0x8); + +// negative saturation at 32 bits +// 0x0 * 0x0 + 0x80f0000000 -> 0x8000 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A1.x = R4.L; + A0.w = R2; + A0.x = R4.L; + R5.H = (A1 += R0.L * R2.L), R5.L = (A0 += R0.L * R2.L); + DBGA ( R5.L , 0x8000 ); + DBGA ( R5.H , 0x8000 ); + _DBG A1; + _DBG A0; + _DBG ASTAT; + R7=ASTAT; + _DBG R7; + DBGA (R7.H, 0x300); + DBGA (R7.L, 0x0008); + +// negative saturation at 32 bits +// 0x7fff * 0x8000 + 0x80f0000000 -> 0x8000 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A1.w = R2; + A1.x = R4.L; + A0.w = R2; + A0.x = R4.L; + R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L); + DBGA ( R5.L , 0x8000 ); + DBGA ( R5.H , 0x8000 ); + R7=ASTAT; + _DBG ASTAT; + DBGA (R7.H, 0x300); + DBGA (R7.L, 0x0008); + +// negative saturation at 32 bits on MAC only +// 0x7fff * 0x8000 + 0x80f0000000 -> 0x8000 + R7 = 0; + ASTAT = R7; + A1 = A0 = 0; + A0.w = R2; + A0.x = R4.L; + _DBG ASTAT; + R5.H = A1, R5.L = (A0 += R0.H * R1.L); + _DBG A0; + DBGA ( R5.L , 0x8000 ); + DBGA ( R5.H , 0x0000 ); + R7=ASTAT; + _DBG ASTAT; + DBGA (R7.H, 0x300); + DBGA (R7.L, 0x0009); + +// 0x0100 * 0x0100 = 0x00020000 -> 0x0002 + R7 = 0; + ASTAT = R7; + R0.L = 0x0100; + R1.L = 0x0100; + A1 = A0 = 0; + R5.H = (A1 = R0.L * R1.L), R5.L = (A0 = R0.L * R1.L) (T); + DBGA ( R5.L , 0x0002 ); + DBGA ( R5.H , 0x0002 ); + R7 = ASTAT; + DBGA (R7.H, 0x000); + DBGA (R7.L, 0x000); + + pass + + .data +data0: + .dw 0x7fff + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m6.s b/sim/testsuite/sim/bfin/m6.s new file mode 100644 index 0000000..738d623 --- /dev/null +++ b/sim/testsuite/sim/bfin/m6.s @@ -0,0 +1,57 @@ +// Test result extraction of mac instructions. +// Test basic edge values +// SIGNED INTEGER mode into SINGLE destination register +// test ops: "+=" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80000001 +// load r1=0x80007fff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// integer extraction with no saturation +// 0x1 * 0x1 = 0x0000000001 -> 0x1 + A1 = A0 = 0; + R5.H = (A1 += R0.L * R0.L), R5.L = (A0 += R0.L * R0.L) (IS); + DBGA ( R5.L , 0x1 ); + DBGA ( R5.H , 0x1 ); + +// integer extraction with positive saturation +// 0x7fff * 0x7f -> 0x7fff + A1 = A0 = 0; + R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IS); + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + +// integer extraction with negative saturation +// 0x8000 * 0x7f -> 0x8000 + A1 = A0 = 0; + R5.H = (A1 += R1.H * R3.L), R5.L = (A0 += R1.H * R3.L) (IS); + DBGA ( R5.L , 0x8000 ); + DBGA ( R5.H , 0x8000 ); + + pass + + .data; +data0: + .dw 0x0001 + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m7.s b/sim/testsuite/sim/bfin/m7.s new file mode 100644 index 0000000..07e664e --- /dev/null +++ b/sim/testsuite/sim/bfin/m7.s @@ -0,0 +1,66 @@ +// Test result extraction of mac instructions. +// Test basic edge values +// UNSIGNED FRACTIONAL mode into SINGLE destination register +// test ops: "+=" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80000001 +// load r1=0x80007fff +// load r2=0xf000ffff +// load r3=0x0000007f +// load r4=0x00000080 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// extraction with no saturation (truncate) +// 0x8000 * 0x7fff = 0x003fff8000 -> 0x3fff + A1 = A0 = 0; + R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L) (TFU); + DBGA ( R5.L , 0x3fff ); + DBGA ( R5.H , 0x3fff ); + +// extraction with no saturation (round) +// 0x8000 * 0x7fff = 0x003fff8000 -> 0x4000 + A1 = A0 = 0; + R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L) (FU); + DBGA ( R5.L , 0x4000 ); + DBGA ( R5.H , 0x4000 ); + +// extraction with no saturation +// 0xffff * 0xffff = 0x00fffe0001 -> 0xfffe + A1 = A0 = 0; + R5.H = (A1 += R2.L * R2.L), R5.L = (A0 += R2.L * R2.L) (FU); + DBGA ( R5.L , 0xfffe ); + DBGA ( R5.H , 0xfffe ); + +// extraction with saturation +//0x7ffffe0001 -> 0xffff + A1 = A0 = 0; + A1.x = R3.L; + A0.x = R3.L; + R5.H = (A1 += R2.L * R2.L), R5.L = (A0 += R2.L * R2.L) (FU); + DBGA ( R5.L , 0xffff ); + DBGA ( R5.H , 0xffff ); + + pass + + .data +data0: + .dw 0x0001 + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0xffff + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/m8.s b/sim/testsuite/sim/bfin/m8.s new file mode 100644 index 0000000..fe8507f --- /dev/null +++ b/sim/testsuite/sim/bfin/m8.s @@ -0,0 +1,54 @@ +// MAC test program. +// Test result extraction of mac instructions. +// Test basic edge values +// UNSIGNED INTEGER mode into SINGLE destination register +// test ops: "+=" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x80000002 +// load r1=0x80007fff +// load r2=0xf0000000 +// load r3=0x0000007f +// load r4=0x00000080 +// load r5=0xffffffff + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + +// 0x0002 * 0x0002 = 0x0000000004 -> 0x0004 + A1 = A0 = 0; + R5.H = (A1 += R0.L * R0.L), R5.L = (A0 += R0.L * R0.L) (IU); + DBGA ( R5.L , 0x4 ); + DBGA ( R5.H , 0x4 ); + +// 0x7fff * 0x007f = 0x00003f7f81 -> 0xffff + A1 = A0 = 0; + R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IU); + R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IU); + DBGA ( R5.L , 0xffff ); + DBGA ( R5.H , 0xffff ); + + pass + + .data; +data0: + .dw 0x0002 + .dw 0x8000 + .dw 0x7fff + .dw 0x8000 + .dw 0x0000 + .dw 0xf000 + .dw 0x007f + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 + .dw 0xffff + .dw 0xffff diff --git a/sim/testsuite/sim/bfin/m9.s b/sim/testsuite/sim/bfin/m9.s new file mode 100644 index 0000000..79cab4c --- /dev/null +++ b/sim/testsuite/sim/bfin/m9.s @@ -0,0 +1,91 @@ +// Test extraction from accumulators: +// ROUND/TRUNCATE in SIGNED FRACTIONAL mode +// test ops: "+=" +# mach: bfin + +.include "testutils.inc" + start + + +// load r0=0x7ffef000 +// load r1=0x7ffff000 +// load r2=0x00008000 +// load r3=0x00018000 +// load r4=0x0000007f + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + +// round +// 0x007ffef00 -> 0x7fff + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1, R5.L = A0; + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + +// round with ovflw +// 0x007ffff00 -> 0x7fff + A1 = A0 = 0; + A1.w = R1; + A0.w = R1; + R5.H = A1, R5.L = A0; + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + +// trunc +// 0x007ffef00 -> 0x7ffe + A1 = A0 = 0; + A1.w = R0; + A0.w = R0; + R5.H = A1, R5.L = A0 (T); + DBGA ( R5.L , 0x7ffe ); + DBGA ( R5.H , 0x7ffe ); + +// round with ovflw +// 0x7f7ffff00 -> 0x7fff + A1 = A0 = 0; + A1.w = R1; + A1.x = R4.L; + A0.w = R1; + A0.x = R4.L; + R5.H = A1, R5.L = A0; + DBGA ( R5.L , 0x7fff ); + DBGA ( R5.H , 0x7fff ); + +// round, nearest even is zero +// 0x0000008000 -> 0x0000 + A1 = A0 = 0; + A1.w = R2; + A0.w = R2; + R5.H = A1, R5.L = A0; + DBGA ( R5.L , 0x0 ); + DBGA ( R5.H , 0x0 ); + +// round, nearest even is 2 +// 0x00000018000 -> 0x0002 + A1 = A0 = 0; + A1.w = R3; + A0.w = R3; + R5.H = A1, R5.L = A0; + DBGA ( R5.L , 0x2 ); + DBGA ( R5.H , 0x2 ); + + pass + + .data +data0: + .dw 0xf000 + .dw 0x7ffe + .dw 0xf000 + .dw 0x7ffe + .dw 0x8000 + .dw 0x0000 + .dw 0x8000 + .dw 0x0001 + .dw 0x007f + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/mac2halfreg.S b/sim/testsuite/sim/bfin/mac2halfreg.S new file mode 100644 index 0000000..0a73dd3 --- /dev/null +++ b/sim/testsuite/sim/bfin/mac2halfreg.S @@ -0,0 +1,27 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + r3.h=0x8000; + r2.h=0x8000; + r7=0; + r6.l=0x7f; + a0.x=r6.l; + r6.h=0x7fff; + r6.l=0xffff; + a0.w=r6; + _dbg a0; + r3.l=(a0+=r3.h*r2.h); + r7=ASTAT; + _dbg A0; + _dbg r3; + _dbg ASTAT; +//AV0 does not overflow + checkreg r7, (_VS|_V|_V_COPY); + + pass diff --git a/sim/testsuite/sim/bfin/math.s b/sim/testsuite/sim/bfin/math.s new file mode 100644 index 0000000..bd88f70 --- /dev/null +++ b/sim/testsuite/sim/bfin/math.s @@ -0,0 +1,66 @@ +# Blackfin testcase for ashift +# mach: bfin + + .include "testutils.inc" + + start + + R0 = 5; + R0 += -1; + R1 = 4; + CC = R0 == R1; + if CC jump 1f; + fail +1: + + imm32 r2, 0xff901234 + r4=8; + i2=r2; + m2 = 4; + a0 = 0; + r1.l = (a0 += r4.l *r4.l) (IS) || I2 += m2 || nop; + r0 = i2; + imm32 r1, 0xff901238; + CC = r1 == r0; + if CC jump 2f; + fail +2: + + A0 = 0; + A1 = 0; + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + R4 = 0; + R5 = 0; + R2.H = 0xf12e; + R2.L = 0xbeaa; + R3.L = 0x00ff; + A1.w = R2; + A1.x = R3; + R0.H = 0xd136; + R0.L = 0x459d; + R1.H = 0xabd6; + R1.L = 0x9ec7; + + R5 = A1 , A0 = R1.L * R0.L (FU); + + R0 = -1 (X); + CC = r5 == r0; + if CC jump 3f; + fail +3: + + R0.L = 0x7bb8; + R0.H = 0x8d5e; + R4.L = 0x7e1c; + R4.H = 0x9e22; + R6.H = R4.H * R0.L (M), R6.L = R4.L * R0.H (ISS2); + + imm32 r0, 0x80008000 + CC = r6 == r0; + if CC jump 4f; + fail +4: + pass diff --git a/sim/testsuite/sim/bfin/max_min_flags.s b/sim/testsuite/sim/bfin/max_min_flags.s new file mode 100644 index 0000000..a4ad33b --- /dev/null +++ b/sim/testsuite/sim/bfin/max_min_flags.s @@ -0,0 +1,275 @@ +// Check Flag Settings for MAX/MIN +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + + r0=1; + r1= -1; + r2=min(r1,r0); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x2); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0xffff); + dbga (r2.h, 0xffff); + + r2=min(r0,r1); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x2); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0xffff); + dbga (r2.h, 0xffff); + + r2=max(r1,r0); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x0); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x1); + dbga (r2.h, 0x0); + + r2=max(r0,r1); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x0); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x1); + dbga (r2.h, 0x0); + + r0.h=1; + r2=min(r1,r0) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x2); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0xffff); + dbga (r2.h, 0xffff); + + r2=min(r0,r1) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x2); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 1); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0xffff); + dbga (r2.h, 0xffff); + + r2=max(r1,r0) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x0); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x1); + dbga (r2.h, 0x1); + + r2=max(r0,r1) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x0); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 0); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x1); + dbga (r2.h, 0x1); + + r0=0; + r2=max(r1,r0); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x1); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 1); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x0); + dbga (r2.h, 0x0); + + r0.h=1; + r2=max(r1,r0) (v); + _DBG ASTAT; +//r3=ASTAT; +//dbga (r3.l, 0x1); +//dbga (r3.h, 0x0); + cc = az; + r7 = cc; + dbga( r7.l, 1); + cc = an; + r7 = cc; + dbga( r7.l, 0); + cc = av0; + r7 = cc; + dbga( r7.l, 0); + cc = av0s; + r7 = cc; + dbga( r7.l, 0); + cc = av1; + r7 = cc; + dbga( r7.l, 0); + cc = av1s; + r7 = cc; + dbga( r7.l, 0); + dbga (r2.l, 0x0); + dbga (r2.h, 0x1); + + pass diff --git a/sim/testsuite/sim/bfin/mc_s2.s b/sim/testsuite/sim/bfin/mc_s2.s new file mode 100644 index 0000000..024ee92 --- /dev/null +++ b/sim/testsuite/sim/bfin/mc_s2.s @@ -0,0 +1,78 @@ +/* SHIFT test program. + * Test r0, r1, A0 <<= BITMUX; + */ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + +// load r0=0x90000001 +// load r1=0x90000002 +// load r2=0x00000000 +// load r3=0x00000000 +// load r4=0x20000002 +// load r5=0x00000000 + loadsym P1, data0; + +// insert two bits, both equal to 1 +// A0: 00 0000 0000 -> 00 0000 0003 +// r0: 9000 0001 -> 2000 0002 +// r1: 9000 0002 -> 2000 0004 + R0 = [ P1 + 0 ]; + R1 = [ P1 + 4 ]; + A0.w = R2; + A0.x = R3.L; + BITMUX( R0 , R1, A0) (ASL); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0003 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R0.L , 0x0002 ); + DBGA ( R0.H , 0x2000 ); + DBGA ( R1.L , 0x0004 ); + DBGA ( R1.H , 0x2000 ); + +// insert two bits, one equal to 1, other to 0 +// A0: 00 0000 0000 -> 00 0000 0001 +// r0: 9000 0001 -> 2000 0002 +// r4: 2000 0002 -> 4000 0004 + R0 = [ P1 + 0 ]; + R4 = [ P1 + 16 ]; + A0.w = R2; + A0.x = R3.L; + BITMUX( R0 , R4, A0) (ASL); + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R0.L , 0x0002 ); + DBGA ( R0.H , 0x2000 ); + DBGA ( R4.L , 0x0004 ); + DBGA ( R4.H , 0x4000 ); + + pass + + .data +data0: + .dw 0x0001 + .dw 0x9000 + + .dw 0x0002 + .dw 0x9000 + + .dw 0x0000 + .dw 0x0000 + + .dw 0x0000 + .dw 0x0000 + + .dw 0x0002 + .dw 0x2000 + + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/mdma-32bit-1d-neg-count.c b/sim/testsuite/sim/bfin/mdma-32bit-1d-neg-count.c new file mode 100644 index 0000000..e380254 --- /dev/null +++ b/sim/testsuite/sim/bfin/mdma-32bit-1d-neg-count.c @@ -0,0 +1,18 @@ +/* Basic MDMA device tests. +# mach: bfin +# cc: -mcpu=bf537 -nostdlib -lc +# sim: --env operating --model bf537 +*/ + +#include "test.h" + +static volatile struct bfin_dma *s = (void *)MDMA_S1_NEXT_DESC_PTR; +static volatile struct bfin_dma *d = (void *)MDMA_D1_NEXT_DESC_PTR; + +#include "mdma-skel.h" + +void mdma_memcpy (bu32 dst, bu32 src, bu32 size) +{ + /* Negative transfers start at end of buffer. */ + _mdma_memcpy (dst + size - 4, src + size - 4, size, -4); +} diff --git a/sim/testsuite/sim/bfin/mdma-32bit-1d.c b/sim/testsuite/sim/bfin/mdma-32bit-1d.c new file mode 100644 index 0000000..acb891e --- /dev/null +++ b/sim/testsuite/sim/bfin/mdma-32bit-1d.c @@ -0,0 +1,17 @@ +/* Basic MDMA device tests. +# mach: bfin +# cc: -mcpu=bf537 -nostdlib -lc +# sim: --env operating --model bf537 +*/ + +#include "test.h" + +static volatile struct bfin_dma *s = (void *)MDMA_S0_NEXT_DESC_PTR; +static volatile struct bfin_dma *d = (void *)MDMA_D0_NEXT_DESC_PTR; + +#include "mdma-skel.h" + +void mdma_memcpy (bu32 dst, bu32 src, bu32 size) +{ + _mdma_memcpy (dst, src, size, 4); +} diff --git a/sim/testsuite/sim/bfin/mdma-8bit-1d-neg-count.c b/sim/testsuite/sim/bfin/mdma-8bit-1d-neg-count.c new file mode 100644 index 0000000..26ba577 --- /dev/null +++ b/sim/testsuite/sim/bfin/mdma-8bit-1d-neg-count.c @@ -0,0 +1,18 @@ +/* Basic MDMA device tests. +# mach: bfin +# cc: -mcpu=bf537 -nostdlib -lc +# sim: --env operating --model bf537 +*/ + +#include "test.h" + +static volatile struct bfin_dma *s = (void *)MDMA_S1_NEXT_DESC_PTR; +static volatile struct bfin_dma *d = (void *)MDMA_D1_NEXT_DESC_PTR; + +#include "mdma-skel.h" + +void mdma_memcpy (bu32 dst, bu32 src, bu32 size) +{ + /* Negative transfers start at end of buffer. */ + _mdma_memcpy (dst + size - 1, src + size - 1, size, -1); +} diff --git a/sim/testsuite/sim/bfin/mdma-8bit-1d.c b/sim/testsuite/sim/bfin/mdma-8bit-1d.c new file mode 100644 index 0000000..8384093 --- /dev/null +++ b/sim/testsuite/sim/bfin/mdma-8bit-1d.c @@ -0,0 +1,17 @@ +/* Basic MDMA device tests. +# mach: bfin +# cc: -mcpu=bf537 -nostdlib -lc +# sim: --env operating --model bf537 +*/ + +#include "test.h" + +static volatile struct bfin_dma *s = (void *)MDMA_S0_NEXT_DESC_PTR; +static volatile struct bfin_dma *d = (void *)MDMA_D0_NEXT_DESC_PTR; + +#include "mdma-skel.h" + +void mdma_memcpy (bu32 dst, bu32 src, bu32 size) +{ + _mdma_memcpy (dst, src, size, 1); +} diff --git a/sim/testsuite/sim/bfin/mdma-skel.h b/sim/testsuite/sim/bfin/mdma-skel.h new file mode 100644 index 0000000..399cddc --- /dev/null +++ b/sim/testsuite/sim/bfin/mdma-skel.h @@ -0,0 +1,79 @@ +#include + +void _mdma_memcpy (bu32 dst, bu32 src, bu32 size, bs16 mod) +{ + bu32 count = size >> (abs (mod) / 2); + bu16 wdsize; + switch (abs (mod)) + { + case 4: wdsize = WDSIZE_32; break; + case 2: wdsize = WDSIZE_16; break; + default: wdsize = WDSIZE_8; break; + } + + s->config = d->config = 0; + + d->irq_status = DMA_DONE | DMA_ERR; + + /* Destination */ + d->start_addr = dst; + d->x_count = count; + d->x_modify = mod; + d->irq_status = DMA_DONE | DMA_ERR; + + /* Source */ + s->start_addr = src; + s->x_count = count; + s->x_modify = mod; + s->irq_status = DMA_DONE | DMA_ERR; + + /* Enable */ + s->config = DMAEN | wdsize; + d->config = WNR | DI_EN | DMAEN | wdsize; + + while (!(d->irq_status & DMA_DONE)) + continue; +} + +void mdma_memcpy (bu32 dst, bu32 src, bu32 size); + +#ifndef MAX_LEN +#define MAX_LEN 0x40000 +#endif +bu32 _data[(MAX_LEN / 4) * 2 + 3]; +char *data = (char *)(_data + 1); + +int _start (void) +{ + char *src, *dst; + bu32 len, canary, *canaries[3]; + + canary = 0x12345678; + + len = 4; + while (len < MAX_LEN) + { + src = data; + dst = data + len + 4; + /* Set up the canaries. */ + canaries[0] = (void *)&src[-4]; + canaries[1] = (void *)&dst[-4]; + canaries[2] = (void *)&dst[len]; + *canaries[0] = *canaries[1] = *canaries[2] = canary; + + memset (src, 0xad, len); + memset (dst, 0x00, len); + + mdma_memcpy ((bu32)dst, (bu32)src, len); + if (memcmp (src, dst, len)) + DBG_FAIL; + + if (*canaries[0] != canary || + *canaries[1] != canary || + *canaries[2] != canary) + DBG_FAIL; + + len <<= 4; + } + DBG_PASS; +} diff --git a/sim/testsuite/sim/bfin/mem3.s b/sim/testsuite/sim/bfin/mem3.s new file mode 100644 index 0000000..da070e0 --- /dev/null +++ b/sim/testsuite/sim/bfin/mem3.s @@ -0,0 +1,42 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0.H = 0x1234; + R0.L = 0x5678; + loadsym P0, data0; + + [ P0 ] = R0; + P1 = [ P0 ]; + _DBG P1; + R1 = [ P0 ]; + _DBG R1; + CC = R0 == R1; + IF !CC JUMP abrt; + + W [ P0 ] = R0; + R1 = W [ P0 ] (Z); + R2 = R0; + R2 <<= 16; + R2 >>= 16; + _DBG R1; + CC = R2 == R1; + IF !CC JUMP abrt; + + B [ P0 ] = R0; + R1 = B [ P0 ] (Z); + R2 = R0; + R2 <<= 24; + R2 >>= 24; + _DBG R1; + CC = R2 == R1; + IF !CC JUMP abrt; + pass +abrt: + fail; + + .data +data0: + .dd 0xDEADBEAF; diff --git a/sim/testsuite/sim/bfin/mmr-exception.s b/sim/testsuite/sim/bfin/mmr-exception.s new file mode 100644 index 0000000..5e9a268 --- /dev/null +++ b/sim/testsuite/sim/bfin/mmr-exception.s @@ -0,0 +1,43 @@ +# Blackfin testcase for MMR exceptions in a lower EVT +# mach: bfin +# sim: --environment operating + + .include "testutils.inc" + + start + + imm32 P0, 0xFFE02000 + loadsym R1, _evx + [P0 + (4 * 3)] = R1; + loadsym R1, _ivg9 + [P0 + (4 * 9)] = R1; + CSYNC; + + RETI = R1; + RAISE 9; + R0 = -1; + STI R0; + RTI; + dbg_fail + +_ivg9: + # Invalid MMR + imm32 P0, 0xFFEE0000 +1: [P0] = R0; +9: dbg_fail + +_evx: + # Make sure SEQSTAT is set to correct value + R0 = SEQSTAT; + R0 = R0.B; + R1 = 0x2e (x); + CC = R0 == R1; + IF !CC JUMP 9b; + + # Make sure RETX is set to correct address + loadsym R0, 1b; + R1 = RETX; + CC = R0 == R1; + IF !CC JUMP 9b; + + dbg_pass diff --git a/sim/testsuite/sim/bfin/move.s b/sim/testsuite/sim/bfin/move.s new file mode 100644 index 0000000..b8f41c8 --- /dev/null +++ b/sim/testsuite/sim/bfin/move.s @@ -0,0 +1,36 @@ +# Blackfin testcase for register move instructions +# mach: bfin + + + .include "testutils.inc" + + start + + .macro move reg0:req, reg1:req, clobber:req + imm32 \reg0, 0x5555aaaa + imm32 \reg1, 0x12345678 + imm32 \clobber, 0x12345678 + \reg0 = \reg1; + CC = \reg0 == \clobber; + if CC jump 1f; + fail +1: + .endm + + move R0, R1, R2 + move R0, R2, R3 + move R0, R2, R4 + move R0, R3, R5 + move R0, R4, R6 + move R0, R5, R7 + move R0, R6, R1 + move R0, R7, R2 + move R7, R0, R1 + move R7, R1, R2 + move R7, R2, R3 + move R7, R3, R4 + move R7, R4, R5 + move R7, R5, R6 + move R7, R6, R0 + + pass diff --git a/sim/testsuite/sim/bfin/msa_acp_5.10.S b/sim/testsuite/sim/bfin/msa_acp_5.10.S new file mode 100644 index 0000000..75e50e3 --- /dev/null +++ b/sim/testsuite/sim/bfin/msa_acp_5.10.S @@ -0,0 +1,40 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + init_r_regs 0 + astat = r0; + + r1.l = 0x0; + r1.h = 0x8000; + A0.w=r1; + _dbg a1; + a0 = a0 << 8; + _dbg a0; + _dbg astat; + + + A0 = - A0; + _dbg astat; + _dbg a0; + r7 = astat; + checkreg r7, (_AV0|_AV0S); + + r1.l = 0x0; + r1.h = 0x8000; + A1.w=r1; + _dbg a0; + a1 = a1 << 8; + _dbg a1; + _dbg astat; + r7 = astat; + checkreg r7, (_AV0|_AV0S|_AN); + + A1 = - A1; + r7 = astat; + checkreg r7, (_AV1|_AV1S|_AV0|_AV0S); + _dbg astat; + _dbg a1; + pass; diff --git a/sim/testsuite/sim/bfin/msa_acp_5.12_1.S b/sim/testsuite/sim/bfin/msa_acp_5.12_1.S new file mode 100644 index 0000000..d65496d --- /dev/null +++ b/sim/testsuite/sim/bfin/msa_acp_5.12_1.S @@ -0,0 +1,71 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + + init_r_regs 0; + ASTAT = r0; + + r0 = -1; + A0 = r0; + _dbg astat; + r0 +=1; + _dbg astat; + A0 = A0 (S); + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AN) + _dbg a0; + _dbg astat; + A0 = 0; + A0 = A0 (S); + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AZ) + _dbg a0; + _dbg astat; + + r0 = -1; + A1 = r0; + _dbg astat; + r0 +=1; + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AZ); + _dbg astat; + A1 = A1 (S); + r7 = astat; + _dbg astat; + checkreg r7, (_AC0|_AC0_COPY|_AN) + _dbg a1; + _dbg astat; + A1 = 0; + A1 = A1 (S); + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AZ) + _dbg a1; + _dbg astat; + + r1.l = 0x0; + r1.h = 0x8000; + a1 = r1; + a1 = a1 << 8; + _dbg a1; + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AN) + a1 = a1(s); + _dbg astat; + _dbg a1; + r7 = astat; + checkreg r7, (_AV1S|_AV1|_AC0|_AC0_COPY|_AN) + + r1.l = 0x0; + r1.h = 0x8000; + a0 = r1; + a0 = a0 << 8; + _dbg a0; + a0 = a0(s); + _dbg astat; + _dbg a0; + r7 = astat; + checkreg r7, (_AV1S|_AV1|_AV0S|_AV0|_AC0|_AC0_COPY|_AN) + pass diff --git a/sim/testsuite/sim/bfin/msa_acp_5.12_2.S b/sim/testsuite/sim/bfin/msa_acp_5.12_2.S new file mode 100644 index 0000000..e965ad1 --- /dev/null +++ b/sim/testsuite/sim/bfin/msa_acp_5.12_2.S @@ -0,0 +1,58 @@ +# mach: bfin + +#include "test.h" +.include "testutils.inc" + start + + r0 = 0; + ASTAT = R0; + + r0 = -1; + A0 = r0; + A1 = 0; + _dbg astat; + r0 +=1; + _dbg astat; + A1 = A1(S), A0 = A0 (S); + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AN|_AZ); + _dbg a0; + _dbg astat; + + r0.l = 0x0; + r0.h = 0x8000; + r1 = 1; + a0 = r0; + a0 = a0 << 8; + a1 = r1; + r7 = astat; + checkreg r7, (_AC0|_AC0_COPY|_AN); + dbga(r7.l,0x1006); + dbga(r7.h,0); + + A1 = A1(S), A0 = A0(S); + _dbg a0; + _dbg a1; + _dbg astat; + r7 = astat; + checkreg r7, (_AV0S|_AV0|_AC0|_AC0_COPY|_AN); + + r0.l = 0x0; + r0.h = 0x8000; + r1 = 0; + a1 = r0; + a1 = a1 << 8; + a0 = r1; + r7 = astat; + + A1 = A1(S), A0 = A0(S); + _dbg a0; + _dbg a1; + _dbg astat; + r7 = astat; + checkreg r7, (_AV1S|_AV1|_AV0S|_AC0|_AC0_COPY|_AN|_AZ); + dbga(r7.l,0x1007); + + dbga(r7.h,0xe); + + pass; diff --git a/sim/testsuite/sim/bfin/msa_acp_5_10.s b/sim/testsuite/sim/bfin/msa_acp_5_10.s new file mode 100644 index 0000000..eae4277 --- /dev/null +++ b/sim/testsuite/sim/bfin/msa_acp_5_10.s @@ -0,0 +1,69 @@ +# mach: bfin + +.include "testutils.inc" + start + + + r1.l = 0x0; + r1.h = 0x8000; + A0.w=r1; + _dbg a1; + a0 = a0 << 8; + _dbg a0; + _dbg astat; + + A0 = - A0; + _dbg astat; + _dbg a0; + r7 = astat; + + cc = az; + r7 = cc; + dbga(r7.l, 0); + cc = an; + r7 = cc; + dbga(r7.l, 0); + cc = av0; + r7 = cc; + dbga(r7.l, 1); + cc = av0s; + r7 = cc; + dbga(r7.l, 1); + cc = av1; + r7 = cc; + dbga(r7.l, 0); + cc = av1s; + r7 = cc; + dbga(r7.l, 0); + + r1.l = 0x0; + r1.h = 0x8000; + A1.w=r1; + _dbg a0; + a1 = a1 << 8; + _dbg a1; + _dbg astat; + + A1 = - A1; + cc = az; + r7 = cc; + dbga(r7.l, 0); + cc = an; + r7 = cc; + dbga(r7.l, 0); + cc = av0; + r7 = cc; + dbga(r7.l, 1); + cc = av0s; + r7 = cc; + dbga(r7.l, 1); + cc = av1; + r7 = cc; + dbga(r7.l, 1); + cc = av1s; + r7 = cc; + dbga(r7.l, 1); + + _dbg astat; + _dbg a1; + pass diff --git a/sim/testsuite/sim/bfin/mult.s b/sim/testsuite/sim/bfin/mult.s new file mode 100644 index 0000000..26bb55e --- /dev/null +++ b/sim/testsuite/sim/bfin/mult.s @@ -0,0 +1,22 @@ +# Blackfin testcase for multiply +# mach: bfin + + .include "testutils.inc" + + start + + R0 = 0; + R1 = 0; + R2 = 0; + R3 = 0; + A0 = 0; + A1 = 0; + R0.L = 0x0400; + R1.L = 0x0010; + R2.L = ( A0 = R0.L * R1.L ) (S2RND); + R3 = 0x1 (Z); + CC = R3 == R2; + if CC jump 1f; + fail +1: + pass diff --git a/sim/testsuite/sim/bfin/neg-2.S b/sim/testsuite/sim/bfin/neg-2.S new file mode 100644 index 0000000..4430171 --- /dev/null +++ b/sim/testsuite/sim/bfin/neg-2.S @@ -0,0 +1,42 @@ +# Blackfin testcase for negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x8000; + R0.L = 0x0000; + R1 = -R0; + R7 = ASTAT; + R2.H = 0x8000; + R2.L = 0x0000; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AC0 AC0_COPY */ + R3.H = HI(_AZ|_AC0|_AC0_COPY); + R3.L = LO(_AZ|_AC0|_AC0_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AN V V_COPY VS */ + R3.H = HI(_AN|_V|_V_COPY|_VS); + R3.L = LO(_AN|_V|_V_COPY|_VS); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/neg-3.S b/sim/testsuite/sim/bfin/neg-3.S new file mode 100644 index 0000000..f1f0a2f --- /dev/null +++ b/sim/testsuite/sim/bfin/neg-3.S @@ -0,0 +1,42 @@ +# Blackfin testcase for negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x0; + R0.L = 0x0; + R1 = -R0; + R7 = ASTAT; + R2.H = 0x0; + R2.L = 0x0; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN V V_COPY */ + R3.H = HI(_AN|_V|_V_COPY); + R3.L = LO(_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ AC0 AC0_COPY */ + R3.H = HI(_AZ|_AC0|_AC0_COPY); + R3.L = LO(_AZ|_AC0|_AC0_COPY); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/neg.S b/sim/testsuite/sim/bfin/neg.S new file mode 100644 index 0000000..45649a1 --- /dev/null +++ b/sim/testsuite/sim/bfin/neg.S @@ -0,0 +1,42 @@ +# Blackfin testcase for negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x1234; + R0.L = 0x5678; + R1 = -R0; + R7 = ASTAT; + R2.H = 0xedcb; + R2.L = 0xa988; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ V V_COPY AC0 AC0_COPY */ + R3.H = HI(_AZ|_V|_V_COPY|_AC0|_AC0_COPY); + R3.L = LO(_AZ|_V|_V_COPY|_AC0|_AC0_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AN */ + R3.H = HI(_AN); + R3.L = LO(_AN); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/nshift.s b/sim/testsuite/sim/bfin/nshift.s new file mode 100644 index 0000000..f9e345b --- /dev/null +++ b/sim/testsuite/sim/bfin/nshift.s @@ -0,0 +1,33 @@ +// ACP 5.18: Shifter uses wrong shift value +# mach: bfin + +.include "testutils.inc" + start + + + r0=0; + r0.h=0x8000; + r1=0x20 (z); + r0 >>>= r1; + dbga (r0.h, 0xffff); + dbga (r0.l, 0xffff); + + r0=0; + r0.h=0x7fff; + r0 >>>= r1; + dbga (r0.h, 0x0000); + dbga (r0.l, 0x0000); + + r0.l=0xffff; + r0.h=0xffff; + r0 >>= r1; + dbga (r0.h, 0x0000); + dbga (r0.l, 0x0000); + + r0.l=0xffff; + r0.h=0xffff; + r0 <<= r1; + dbga (r0.h, 0x0000); + dbga (r0.l, 0x0000); + + pass; diff --git a/sim/testsuite/sim/bfin/pr.s b/sim/testsuite/sim/bfin/pr.s new file mode 100644 index 0000000..d290184 --- /dev/null +++ b/sim/testsuite/sim/bfin/pr.s @@ -0,0 +1,81 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym R3, foo; + I1 = R3; + + R4 = 0x10 + R4 = R4 + R3; + P0 = R4; + + R4 = 0x14; + R4 = R4 + R3; + I0 = R4; + + r0 = 0x22; + loadsym P1, bar; + + [i0] = r0; + [i1] = r0; + +doItAgain: + + p2 = 4; + r5=0; + + LSETUP ( lstart , lend) LC0 = P2; +lstart: + + MNOP || R2 = [ I0 ++ ] || R1 = [ I1 ++ ]; + CC = R1 == R2; + IF CC JUMP lend; + R1 = [ P1 + 0x0 ]; + R1 = R1 + R0; + [ P1 + 0x0 ] = R1; + +lend: + NOP; + + if !cc jump _halt0; + cc = r5 == 0; + if !cc jump _halt0; + + r4=1; + r5=r5+r4; + r1=i0; + R4 = 0x24; + R4 = R3 + R4 + CC = R1 == R4 + if !CC JUMP _fail; + + i2=i0; + r2=0x1234; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + [i2++]=r2; + jump doItAgain; + +_halt0: + r0=i0; + R4 = 0x34; + R4 = R4 + R3; + CC = R0 == R4; + IF !CC JUMP _fail; + + pass; + +_fail: + fail; + + .data +foo: + .space (0x100); + +bar: + .space (0x1000); diff --git a/sim/testsuite/sim/bfin/push-pop-multiple.s b/sim/testsuite/sim/bfin/push-pop-multiple.s new file mode 100644 index 0000000..2a2b356 --- /dev/null +++ b/sim/testsuite/sim/bfin/push-pop-multiple.s @@ -0,0 +1,169 @@ +# Blackfin testcase for push/pop multiples instructions +# mach: bfin + + .include "testutils.inc" + + # Tests follow the pattern: + # - do the push multiple + # - write a garbage value to all registers pushed + # - do the pop multiple + # - check all registers popped against known values + + start + + # Repeat the same operation multiple times, so this: + # do_x moo, R, 1 + # becomes this: + # moo R1, 0x11111111 + # moo R0, 0x00000000 + .macro _do_x func:req, reg:req, max:req, x:req + .ifle (\max - \x) + \func \reg\()\x, 0x\x\x\x\x\x\x\x\x + .endif + .endm + .macro do_x func:req, reg:req, max:req + .ifc \reg, R + _do_x \func, \reg, \max, 7 + _do_x \func, \reg, \max, 6 + .endif + _do_x \func, \reg, \max, 5 + _do_x \func, \reg, \max, 4 + _do_x \func, \reg, \max, 3 + _do_x \func, \reg, \max, 2 + _do_x \func, \reg, \max, 1 + _do_x \func, \reg, \max, 0 + .endm + + # Keep the garbage value in I0 + .macro loadi reg:req, val:req + \reg = I0; + .endm + imm32 I0, 0xAABCDEFF + + # + # Test push/pop multiples with (R7:x) syntax + # + + _push_r_tests: + + # initialize all Rx regs with a known value + do_x imm32, R, 0 + + .macro checkr tochk:req, val:req + P0 = \tochk; + imm32 P1, \val + CC = P0 == P1; + IF !CC JUMP 8f; + .endm + + .macro pushr maxr:req + _push_r\maxr: + [--SP] = (R7:\maxr); + do_x loadi, R, \maxr + (R7:\maxr) = [SP++]; + do_x checkr, R, \maxr + # need to do a long jump to avoid PCREL issues + jump 9f; + 8: jump.l 1f; + 9: + .endm + + pushr 7 + pushr 6 + pushr 5 + pushr 4 + pushr 3 + pushr 2 + pushr 1 + pushr 0 + + # + # Test push/pop multiples with (P5:x) syntax + # + + _push_p_tests: + + # initialize all Px regs with a known value + do_x imm32, P, 0 + + .macro checkp tochk:req, val:req + R0 = \tochk; + imm32 R1, \val + CC = R0 == R1; + IF !CC JUMP 8f; + .endm + + .macro pushp maxp:req + _push_p\maxp: + [--SP] = (P5:\maxp); + do_x loadi, P, \maxp + (P5:\maxp) = [SP++]; + do_x checkp, P, \maxp + # need to do a long jump to avoid PCREL issues + jump 9f; + 8: jump.l 1f; + 9: + .endm + + # checkp func clobbers R0/R1 + L0 = R0; + L1 = R1; + pushp 5 + pushp 4 + pushp 3 + pushp 2 + pushp 1 + pushp 0 + R0 = L0; + R1 = L1; + + # + # Test push/pop multiples with (R7:x, P5:x) syntax + # + + _push_rp_tests: + + .macro _pushrp maxr:req, maxp:req + _push_r\maxr\()_p\maxp: + [--SP] = (R7:\maxr, P5:\maxp); + do_x loadi, R, \maxr + do_x loadi, P, \maxp + (R7:\maxr, P5:\maxp) = [SP++]; + # checkr func clobbers P0/P1 + L0 = P0; + L1 = P1; + do_x checkr, R, \maxr + P1 = L1; + P0 = L0; + # checkp func clobbers R0/R1 + L0 = R0; + L1 = R1; + do_x checkp, P, \maxp + R0 = L0; + R1 = L1; + # need to do a long jump to avoid PCREL issues + jump 9f; + 8: jump.l 1f; + 9: + .endm + .macro pushrp maxr:req + _pushrp \maxr, 5 + _pushrp \maxr, 4 + _pushrp \maxr, 3 + _pushrp \maxr, 2 + _pushrp \maxr, 1 + _pushrp \maxr, 0 + .endm + + pushrp 7 + pushrp 6 + pushrp 5 + pushrp 4 + pushrp 3 + pushrp 2 + pushrp 1 + pushrp 0 + + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/push-pop.s b/sim/testsuite/sim/bfin/push-pop.s new file mode 100644 index 0000000..bd6eda8 --- /dev/null +++ b/sim/testsuite/sim/bfin/push-pop.s @@ -0,0 +1,95 @@ +# Blackfin testcase for push/pop instructions +# mach: bfin + + .include "testutils.inc" + + start + + # This uses R0/R1 as scratch ... assume those work fine in general + .macro check loader:req, reg:req + \loader \reg, 0x12345678 + [--SP] = \reg; + R0 = [SP]; + R1 = \reg; + CC = R0 == R1; + IF !CC JUMP 8f; + \loader \reg, 0x87654321 + \reg = [SP++]; + CC = R0 == R1; + IF !CC JUMP 8f; + # need to do a long jump to avoid PCREL issues + jump 9f; + 8: jump 1f; + 9: + .endm + .macro imm_check reg:req + check imm32, \reg + .endm + .macro dmm_check reg:req + check dmm32, \reg + .endm + + imm_check R2 + imm_check R3 + imm_check R4 + imm_check R5 + imm_check R6 + imm_check R7 + imm_check P0 + imm_check P1 + imm_check P2 + imm_check P3 + imm_check P4 + imm_check P5 + imm_check FP + imm_check I0 + imm_check I1 + imm_check I2 + imm_check I3 + imm_check M0 + imm_check M1 + imm_check M2 + imm_check M3 + imm_check B0 + imm_check B1 + imm_check B2 + imm_check B3 + imm_check L0 + imm_check L1 + imm_check L2 + imm_check L3 + dmm_check A0.X + dmm_check A0.W + dmm_check A1.X + dmm_check A1.W + dmm_check LC0 + dmm_check LC1 + # Make sure the top/bottom regs have bit 1 set + dmm_check LT0 + dmm_check LT1 + dmm_check LB0 + dmm_check LB1 + dmm_check RETS + + # These require supervisor resources +.ifndef BFIN_HOST + dmm_check RETI + dmm_check RETX + dmm_check RETN + # RETE likes to change on the fly with an ICE + # dmm_check RETE + # CYCLES can be user mode, but screws kernel + dmm_check CYCLES + dmm_check CYCLES2 + dmm_check USP + + # No one pushes/pops these +# dmm_check EMUDAT + dmm_check SEQSTAT + dmm_check SYSCFG +.endif + dmm_check ASTAT + + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/pushpopreg_1.s b/sim/testsuite/sim/bfin/pushpopreg_1.s new file mode 100644 index 0000000..5bf4aa6 --- /dev/null +++ b/sim/testsuite/sim/bfin/pushpopreg_1.s @@ -0,0 +1,292 @@ +# mach: bfin + +.include "testutils.inc" + start + + + r0.l = 0x1111; + r0.h = 0x0011; + r1.l = 0x2222; + r1.h = 0x0022; + r2.l = 0x3333; + r2.h = 0x0033; + r3.l = 0x4444; + r3.h = 0x0044; + r4.l = 0x5555; + r4.h = 0x0055; + r5.l = 0x6666; + r5.h = 0x0066; + r6.l = 0x7777; + r6.h = 0x0077; + r7.l = 0x8888; + r7.h = 0x0088; + p1.l = 0x5a5a; + p1.h = 0x005a; + p2.l = 0x6363; + p2.h = 0x0063; + p3.l = 0x7777; + p3.h = 0x0077; + p4.l = 0x7878; + p4.h = 0x0078; + p5.l = 0x3e3e; + p5.h = 0x003e; + sp = 0x4000(x); + + jump.s prog_start; + + nop; + nop; // ADD reg update to roll back + nop; + +prog_start: + nop; + [--sp] = r0; + [--sp] = r1; + [--sp] = r2; + [--sp] = r3; + [--sp] = r4; + [--sp] = r5; + [--sp] = r6; + [--sp] = r7; + [--sp] = p0; + [--sp] = p1; + [--sp] = p2; + [--sp] = p3; + [--sp] = p4; + [--sp] = p5; + + nop; + nop; + nop; + nop; + r0.l = 0xdead; + r0.h = 0xdead; + r1.l = 0xdead; + r1.h = 0xdead; + r2.l = 0xdead; + r2.h = 0xdead; + r3.l = 0xdead; + r3.h = 0xdead; + r4.l = 0xdead; + r4.h = 0xdead; + r5.l = 0xdead; + r5.h = 0xdead; + r6.l = 0xdead; + r6.h = 0xdead; + r7.l = 0xdead; + r7.h = 0xdead; + p1.l = 0xdead; + p1.h = 0xdead; + p2.l = 0xdead; + p2.h = 0xdead; + p3.l = 0xdead; + p3.h = 0xdead; + p4.l = 0xdead; + p4.h = 0xdead; + p5.l = 0xdead; + p5.h = 0xdead; + nop; + nop; + nop; + r0 = [sp++]; + r1 = [sp++]; + r2 = [sp++]; + r3 = [sp++]; + r4 = [sp++]; + r5 = [sp++]; + r6 = [sp++]; + r7 = [sp++]; + p0 = [sp++]; + p1 = [sp++]; + p2 = [sp++]; + p3 = [sp++]; + p4 = [sp++]; + p5 = [sp++]; + + nop; + nop; + nop; + nop; + nop; + nop; + nop; +_tp1: + nop; + nop; + nop; + nop; + nop; + nop; + nop; + [--sp] = r0; + [--sp] = r1; + [--sp] = r2; + [--sp] = r3; + [--sp] = r4; + [--sp] = r5; + [--sp] = r6; + [--sp] = r7; + [--sp] = p0; + [--sp] = p1; + [--sp] = p2; + [--sp] = p3; + [--sp] = p4; + [--sp] = p5; + + nop; + nop; + nop; + nop; + r0.l = 0xdead; + r0.h = 0xdead; + r1.l = 0xdead; + r1.h = 0xdead; + r2.l = 0xdead; + r2.h = 0xdead; + r3.l = 0xdead; + r3.h = 0xdead; + r4.l = 0xdead; + r4.h = 0xdead; + r5.l = 0xdead; + r5.h = 0xdead; + r6.l = 0xdead; + r6.h = 0xdead; + r7.l = 0xdead; + r7.h = 0xdead; + p1.l = 0xdead; + p1.h = 0xdead; + p2.l = 0xdead; + p2.h = 0xdead; + p3.l = 0xdead; + p3.h = 0xdead; + p4.l = 0xdead; + p4.h = 0xdead; + p5.l = 0xdead; + p5.h = 0xdead; + nop; + nop; + nop; + r0 = [sp++]; + r1 = [sp++]; + r2 = [sp++]; + r3 = [sp++]; + r4 = [sp++]; + r5 = [sp++]; + r6 = [sp++]; + r7 = [sp++]; + p0 = [sp++]; + p1 = [sp++]; + a0.x = [sp++]; + + a1.w = r0; //preserve r0 + + r0 = a0.x; + DBGA(r0.l,0x0063); + + a0.w = [sp++]; + r0 = a0.w; + DBGA(r0.l,0x7777); + DBGA(r0.h,0x0077); + + a0 = a1; //perserver r0, still + + a1.x = [sp++]; + r0 = a1.x; + DBGA(r0.l,0x0078); + + a1.w = [sp++]; + r0 = a1.w; + DBGA(r0.l,0x3e3e); + DBGA(r0.h,0x003e); + + r0 = a0.w; //restore r0 + + nop; + nop; + nop; + nop; + nop; + nop; + nop; +_tp2: + nop; + nop; + nop; + [--sp] = r0; + [--sp] = r1; + [--sp] = r2; + [--sp] = r3; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + [--sp] = p0; + [--sp] = p1; + [--sp] = p2; + [--sp] = p3; + [--sp] = p4; + [--sp] = p5; + + nop; + nop; + nop; + nop; + r0.l = 0xdead; + r0.h = 0xdead; + r1.l = 0xdead; + r1.h = 0xdead; + r2.l = 0xdead; + r2.h = 0xdead; + r3.l = 0xdead; + r3.h = 0xdead; + r4.l = 0xdead; + r4.h = 0xdead; + r5.l = 0xdead; + r5.h = 0xdead; + r6.l = 0xdead; + r6.h = 0xdead; + r7.l = 0xdead; + r7.h = 0xdead; + p1.l = 0xdead; + p1.h = 0xdead; + p2.l = 0xdead; + p2.h = 0xdead; + p3.l = 0xdead; + p3.h = 0xdead; + p4.l = 0xdead; + p4.h = 0xdead; + p5.l = 0xdead; + p5.h = 0xdead; + nop; + nop; + nop; + r0 = [sp++]; + r1 = [sp++]; + r2 = [sp++]; + r3 = [sp++]; + r4 = [sp++]; + r5 = [sp++]; + r6 = [sp++]; + r7 = [sp++]; + p0 = [sp++]; + p1 = [sp++]; + p2 = [sp++]; + p3 = [sp++]; + p4 = [sp++]; + p5 = [sp++]; + + nop; + nop; + nop; + nop; + nop; + nop; + nop; +_tp3: + nop; + nop; + nop; + nop; + nop; +_halt: + pass; diff --git a/sim/testsuite/sim/bfin/quadaddsub.s b/sim/testsuite/sim/bfin/quadaddsub.s new file mode 100644 index 0000000..1502179 --- /dev/null +++ b/sim/testsuite/sim/bfin/quadaddsub.s @@ -0,0 +1,58 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R6.L = 32767; + R6.H = 2768; + R1.L = 2767; + R1.H = 2768; + + r7=0; + astat = r7; + r3 = r6 -|- r1; + _DBG r3; + _DBG ASTAT; + r7=ASTAT; + _DBG R7; + DBGA (R7.H, 0x0); + DBGA (R7.L, 0x3005); + + r7=0; + astat=r7; + r2 = r6 +|+ r1; + _DBG r2; + _DBG ASTAT; + r7=ASTAT; + _DBG R7; + DBGA (R7.H, 0x0300); + DBGA (R7.L, 0x000a); + + r7=0; + astat=r7; + r2 = r6 +|+ r1, r3 = r6 -|- r1; + + _DBG r2; + _DBG r3; + _DBG ASTAT; + + R7 = ASTAT; + _DBG R7; + DBGA (R7.H, 0x0300); + DBGA (R7.L, 0x000b); + + r7=0; + astat=r7; + r2 = r6 +|- r1, r3 = r6 -|+ r1; + + _DBG r2; + _DBG r3; + _DBG ASTAT; + + R7 = ASTAT; + _DBG R7; + DBGA (R7.H, 0x0300); + DBGA (R7.L, 0x000b); + + pass diff --git a/sim/testsuite/sim/bfin/random_0001.s b/sim/testsuite/sim/bfin/random_0001.s new file mode 100644 index 0000000..3cc946f --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0001.s @@ -0,0 +1,13 @@ +# Test for saturation behavior with fract multiplication +# mach: bfin + +.include "testutils.inc" + + start + + dmm32 A0.w, 0x45c1969f; + dmm32 A0.x, 0x00000000; + R4 = A0 (IU); + checkreg R4, 0x45c1969f; + + pass diff --git a/sim/testsuite/sim/bfin/random_0002.S b/sim/testsuite/sim/bfin/random_0002.S new file mode 100644 index 0000000..3567ae0 --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0002.S @@ -0,0 +1,25 @@ +# Test for ASTAT V overflows with dsp mult insns +# mach: bfin + +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x54604e00 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY); + imm32 R1, 0x47f491c5; + imm32 R3, 0xfe4cfc98; + imm32 R7, 0x77aa2b21; + R3.L = R7.H * R1.H (IU); + checkreg R3, 0xfe4cffff; + checkreg ASTAT, (0x54604e00 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x10f00200 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AN); + imm32 R0, 0x24f45737; + imm32 R1, 0x6752f56b; + imm32 R4, 0x3f939925; + R4.H = R0.L * R1.H (IS); + checkreg R4, 0x7fff9925; + checkreg ASTAT, (0x10f00200 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AN); + + pass diff --git a/sim/testsuite/sim/bfin/random_0003.S b/sim/testsuite/sim/bfin/random_0003.S new file mode 100644 index 0000000..d9852f2 --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0003.S @@ -0,0 +1,48 @@ +# Test for ASTAT AN setting when overflows occur +# mach: bfin + +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x18204a80 | _AV1S | _AV0 | _AQ | _CC | _AC0_COPY | _AN | _AZ); + dmm32 A1.w, 0x1098e30b; + dmm32 A1.x, 0x0000001f; + imm32 R0, 0x440ed6ae; + imm32 R5, 0x3272c296; + R0.H = (A1 += R0.L * R5.H); + checkreg R0, 0x7fffd6ae; + checkreg A1.w, 0x00500e03; + checkreg A1.x, 0x0000001f; + checkreg ASTAT, (0x18204a80 | _VS | _V | _AV1S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x28c08e90 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN); + dmm32 A0.w, 0xb9da9f02; + dmm32 A0.x, 0x00000010; + imm32 R0, 0xc104b252; + R0.L = A0 (IS); + checkreg R0, 0xc1047fff; + checkreg ASTAT, (0x28c08e90 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x3cc04000 | _AV0S | _AV0 | _CC | _AC0_COPY | _AZ); + dmm32 A0.w, 0x2cc20f30; + dmm32 A0.x, 0xffffffd0; + imm32 R2, 0x367adfeb; + imm32 R5, 0x53eeff3c; + A0 += R5.H * R2.H (IS); + checkreg A0.w, 0x3e9e429c; + checkreg A0.x, 0xffffffd0; + checkreg ASTAT, (0x3cc04000 | _AV0S | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x18c0ca90 | _V | _AV1S | _AV1 | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ); + dmm32 A1.w, 0x0614ca96; + dmm32 A1.x, 0x00000053; + imm32 R3, 0x6c490457; + R3 = (A1 -= R3.L * R3.L) (M, S2RND); + checkreg R3, 0x7fffffff; + checkreg A1.w, 0x0601f505; + checkreg A1.x, 0x00000053; + checkreg ASTAT, (0x18c0ca90 | _VS | _V | _AV1S | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ); + + pass diff --git a/sim/testsuite/sim/bfin/random_0004.S b/sim/testsuite/sim/bfin/random_0004.S new file mode 100644 index 0000000..fddabbc --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0004.S @@ -0,0 +1,33 @@ +# Test for ASTAT bits being written when they shouldn't (only a reg mov) +# mach: bfin + +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x1c304e90 | _VS | _V | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x74d5f9df; + dmm32 A0.x, 0x0000005e; + imm32 R4, 0x00b47e9b; + R4 = A0; + checkreg R4, 0x7fffffff; + checkreg ASTAT, (0x1c304e90 | _VS | _V | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x6cd08a00 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _AN | _AZ); + dmm32 A1.w, 0x124e2817; + dmm32 A1.x, 0x00000011; + imm32 R2, 0x545a7c91; + R2.H = A1; + checkreg R2, 0x7fff7c91; + checkreg ASTAT, (0x6cd08a00 | _VS | _V | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x60700280 | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN); + dmm32 A0.w, 0x02184a1c; + dmm32 A0.x, 0xffffffc0; + imm32 R5, 0x60dc408a; + R5.L = A0 (IS); + checkreg R5, 0x60dc8000; + checkreg ASTAT, (0x60700280 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN); + + pass diff --git a/sim/testsuite/sim/bfin/random_0005.S b/sim/testsuite/sim/bfin/random_0005.S new file mode 100644 index 0000000..8980dfe --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0005.S @@ -0,0 +1,24 @@ +# Test for ASTAT AZ bit update with 16 bit add and sub insns +# mach: bfin + +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x10a04e10 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY); + imm32 R3, 0x05fd7405; + imm32 R7, 0x7fff7fff; + R3.H = R7.L - R7.H (NS); + checkreg R3, 0x00007405; + checkreg ASTAT, (0x10a04e10 | _VS | _AV1S | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x64200e10 | _VS | _AV0S | _AC1 | _AC0 | _AZ); + imm32 R1, 0x2c388489; + imm32 R3, 0x38f39dcc; + imm32 R5, 0x27ed8efa; + R3.H = R1.L + R5.L (NS); + checkreg R3, 0x13839dcc; + checkreg ASTAT, (0x64200e10 | _VS | _V | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + pass diff --git a/sim/testsuite/sim/bfin/random_0006.S b/sim/testsuite/sim/bfin/random_0006.S new file mode 100644 index 0000000..bafe19a --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0006.S @@ -0,0 +1,23 @@ +# Test BYTEOP[123]P behavior when source reg pairs match +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + imm32 R0, (0x18204e10 | _VS | _AV1S | _AV0S | _AC1 | _CC); ASTAT = R0; + imm32 R1, 0x05b931c4; + imm32 R4, 0x05f205f2; + R4 = BYTEOP1P (R1:0, R1:0) (T, R); + + imm32 R0, (0x3470cc10 | _VS | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); ASTAT = R0; + imm32 R1, 0x00000000; + imm32 R6, 0x0000007f; + R6 = BYTEOP2P (R1:0, R1:0) (RNDH); + + imm32 R0, (0x1c708c90 | _VS | _V | _AV1S | _AC0 | _V_COPY | _AC0_COPY | _AN); ASTAT = R0; + imm32 R0, 0x3e2a80ca; + imm32 R1, 0x20dec740; + R0 = BYTEOP3P (R1:0, R1:0) (LO); + + pass diff --git a/sim/testsuite/sim/bfin/random_0007.S b/sim/testsuite/sim/bfin/random_0007.S new file mode 100644 index 0000000..eb98e07 --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0007.S @@ -0,0 +1,60 @@ +# Make sure the acc regs are updated even when the search criteria is not met +# (this implicitly affects the top 8 bits) +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x08e00690 | _VS | _AC1 | _AN); + dmm32 A0.w, 0x42357aea; + dmm32 A0.x, 0x00000001; + dmm32 A1.w, 0x3a3f0000; + dmm32 A1.x, 0x00000000; + imm32 P0, 0x7119f94d; + imm32 R4, 0xcdeea690; + imm32 R5, 0xffb58000; + imm32 R6, 0x72252b1e; + (R4, R5) = SEARCH R6 (GE); + checkreg R4, 0x7119f94d; + checkreg A0.w, 0x00007aea; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0x00007225; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x08e00690 | _VS | _AC1 | _AN); + + dmm32 ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x4193c6bc; + dmm32 A0.x, 0xffffffd4; + dmm32 A1.w, 0xa97e7452; + dmm32 A1.x, 0xffffffff; + imm32 P0, 0x51e152a5; + imm32 R1, 0x36deeb9a; + imm32 R5, 0x386ab3f7; + imm32 R7, 0x2a3d5114; + (R5, R1) = SEARCH R7 (GT); + checkreg R1, 0x51e152a5; + checkreg A0.w, 0x00005114; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0x00007452; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x4193c6bc; + dmm32 A0.x, 0xffffffd4; + dmm32 A1.w, 0x0000ffff; + dmm32 A1.x, 0x00000000; + imm32 P0, 0x51e152a5; + imm32 R1, 0x36deeb9a; + imm32 R5, 0x386ab3f7; + imm32 R7, 0xFa3d5114; + (R5, R1) = SEARCH R7 (GT); + checkreg R1, 0x51e152a5; + checkreg A0.w, 0x00005114; + checkreg A0.x, 0x00000000; + checkreg A1.w, 0xffffffff; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x2cf04210 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + pass diff --git a/sim/testsuite/sim/bfin/random_0008.S b/sim/testsuite/sim/bfin/random_0008.S new file mode 100644 index 0000000..d856b0c --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0008.S @@ -0,0 +1,44 @@ +# check ASTAT ac/av flags are handled correctly when doing Acc = -Acc +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x5020ca80 | _VS | _AV1S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A1.w, 0x549e07b3; + dmm32 A1.x, 0x0000002a; + A1 = -A1; + checkreg A1.w, 0xab61f84d; + checkreg A1.x, 0xffffffd5; + checkreg ASTAT, (0x5020ca80 | _VS | _AV1S | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x48908a10 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AN); + dmm32 A0.w, 0x3c57e100; + dmm32 A0.x, 0xfffffff2; + dmm32 A1.w, 0xfb63b8a0; + dmm32 A1.x, 0xffffffff; + A1 = -A0; + checkreg A1.w, 0xc3a81f00; + checkreg A1.x, 0x0000000d; + checkreg ASTAT, (0x48908a10 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY); + + dmm32 ASTAT, (0x10900880 | _V | _AC0 | _CC | _AC0_COPY); + dmm32 A0.w, 0x4ca147ce; + dmm32 A0.x, 0xffffff9d; + dmm32 A1.w, 0x0e2534b9; + dmm32 A1.x, 0xffffff85; + A0 = -A1; + checkreg A0.w, 0xf1dacb47; + checkreg A0.x, 0x0000007a; + checkreg ASTAT, (0x10900880 | _V | _CC); + + dmm32 ASTAT, (0x34904e90 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x7826f07d; + dmm32 A0.x, 0xffffffc2; + A0 = -A0; + checkreg A0.w, 0x87d90f83; + checkreg A0.x, 0x0000003d; + checkreg ASTAT, (0x34904e90 | _VS | _V | _AV1S | _AC1 | _V_COPY); + + pass diff --git a/sim/testsuite/sim/bfin/random_0009.S b/sim/testsuite/sim/bfin/random_0009.S new file mode 100644 index 0000000..6b3960a --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0009.S @@ -0,0 +1,103 @@ +# Verify ASTAT bits are set correctly during dsp mac insns +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x16ba2677; + dmm32 A0.x, 0x00000000; + imm32 R4, 0x80007fff; + A0 -= R4.H * R4.H (W32); + checkreg A0.w, 0x96ba2678; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x3c30c800 | _VS | _AV0S | _AC1 | _CC); + dmm32 A0.w, 0xf170d0c7; + dmm32 A0.x, 0xffffffff; + imm32 R2, 0x80008000; + A0 -= R2.H * R2.L (W32); + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x3c30c800 | _VS | _AV0S | _AV0 | _AC1 | _CC); + + dmm32 ASTAT, (0x6c200880 | _VS | _AV1S | _AC1 | _AC0 | _CC | _AN); + dmm32 A0.x, 0x560a1c52; + dmm32 A0.x, 0xffffffbb; + imm32 R5, 0x8000ffff; + A0 = R5.H * R5.H (W32); + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x6c200880 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _AN); + + dmm32 ASTAT, (0x58908a90 | _VS | _AC1 | _AC0 | _AQ); + dmm32 A0.w, 0x00c5a4e0; + dmm32 A0.x, 0x00000000; + imm32 R0, 0xffffb33a; + imm32 R2, 0xffffb33a; + imm32 R3, 0xb33a4cc6; + R2 = (A0 -= R0.L * R3.H) (FU); + checkreg R2, 0x00000000; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x58908a90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x2cc00c90 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY); + dmm32 A0.w, 0x00a38000; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x2aa2ffff; + imm32 R1, 0xff5c711e; + imm32 R4, 0x2913dc90; + R0 = (A0 -= R4.L * R1.L) (IU); + checkreg R0, 0x00000000; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x2cc00c90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x3880c280 | _VS | _AC1 | _AZ); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + imm32 R4, 0x139ad315; + imm32 R6, 0x7fff0000; + R4.L = (A0 -= R6.H * R6.H) (FU); + checkreg R4, 0x139a0000; + checkreg ASTAT, (0x3880c280 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AZ); + + dmm32 ASTAT, (0x48408290 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0x6b426a69; + dmm32 A0.x, 0xffffffba; + imm32 R0, 0x24038000; + imm32 R2, 0xf62c7780; + imm32 R3, 0x5a64f8e8; + R2.L = (A0 -= R3.L * R0.L) (IH); + checkreg R2, 0xf62c8000; + checkreg A0.w, 0x80000000; + checkreg A0.x, 0xffffffff; + checkreg ASTAT, (0x48408290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x7c00c210 | _VS | _AC1 | _AN); + dmm32 A1.w, 0x730173e9; + dmm32 A1.x, 0xffffffae; + imm32 R4, 0x8000ffff; + imm32 R5, 0x738559e8; + R5.H = (A1 -= R4.L * R5.L) (M, IH); + checkreg R5, 0x800059e8; + checkreg A1.w, 0x80000000; + checkreg A1.x, 0xffffffff; + checkreg ASTAT, (0x7c00c210 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY | _AN); + + dmm32 ASTAT, (0x4830c400 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AZ); + dmm32 A0.w, 0x033a05f0; + dmm32 A0.x, 0x00000000; + imm32 R3, 0x5992dd5a; + imm32 R4, 0x098a889e; + imm32 R6, 0x8000de08; + R6.L = (A0 -= R4.L * R3.H) (TFU); + checkreg R6, 0x80000000; + checkreg A0.w, 0x00000000; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x4830c400 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _CC | _V_COPY | _AZ); + + pass diff --git a/sim/testsuite/sim/bfin/random_0010.S b/sim/testsuite/sim/bfin/random_0010.S new file mode 100644 index 0000000..c434edb --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0010.S @@ -0,0 +1,78 @@ +# Test logical left shift (vector) insns with larger shift values +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x30400e90 | _VS | _AV0S | _AC1 | _AQ | _AN); + imm32 R5, 0xb0b40000; + imm32 R6, 0xf43a5d3c; + R6 = R5 << 0x19 (V, S); + checkreg R6, 0xff610000; + checkreg ASTAT, (0x30400e90 | _VS | _AV0S | _AC1 | _AQ | _AN | _AZ); + + dmm32 ASTAT, (0x34104410 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN); + imm32 R2, 0xff2abd08; + imm32 R5, 0xf610ffff; + R2 = R5 << 0x11 (V, S); + checkreg R2, 0xffffffff; + checkreg ASTAT, (0x34104410 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN); + + dmm32 ASTAT, (0x6cd0c680 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + imm32 R0, 0x760ecf8e; + imm32 R1, 0x3f5c8af5; + R0 = R1 << 0x17 (V, S); + checkreg R0, 0x001fffc5; + checkreg ASTAT, (0x6cd0c680 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x44a04280 | _AV1S | _AV1 | _AC1 | _AC0 | _CC); + imm32 R4, 0x520cb3d4; + imm32 R6, 0x67141e28; + R6 = R4 << 0x14 (V, S); + checkreg R6, 0x0005fffb; + checkreg ASTAT, (0x44a04280 | _AV1S | _AV1 | _AC1 | _AC0 | _CC | _AN); + + dmm32 ASTAT, (0x14600c10 | _VS | _AV1S | _AC1 | _AC0 | _AN); + imm32 R3, 0x40407f7e; + imm32 R4, 0xc081e040; + R3 = R4 << 0x1a (V, S); + checkreg R3, 0xff02ff81; + checkreg ASTAT, (0x14600c10 | _VS | _AV1S | _AC1 | _AC0 | _AN); + + dmm32 ASTAT, (0x04f00490 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY); + imm32 R5, 0x63654235; + imm32 R7, 0x00008000; + R5 = R7 << 0x18 (V, S); + checkreg R5, 0x0000ff80; + checkreg ASTAT, (0x04f00490 | _VS | _AV0S | _AC1 | _AQ | _AN | _AZ); + + dmm32 ASTAT, (0x3830ca90 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AN); + imm32 R1, 0x40000000; + imm32 R2, 0x7fffffff; + R1 = R2 << 0x16 (V, S); + checkreg R1, 0x001fffff; + checkreg ASTAT, (0x3830ca90 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN); + + dmm32 ASTAT, (0x24e08890 | _VS | _AV0S | _AC1 | _CC | _AN | _AZ); + imm32 R2, 0xfffe0000; + imm32 R3, 0xd9d90000; + R2 = R3 << 0x19 (V, S); + checkreg R2, 0xffb30000; + checkreg ASTAT, (0x24e08890 | _VS | _AV0S | _AC1 | _CC | _AN | _AZ); + + dmm32 ASTAT, (0x30f0c200 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AZ); + imm32 R0, 0x32590000; + imm32 R2, 0x708bb53f; + R0 = R2 << 0x1c (V, S); + checkreg R0, 0x0708fb53; + checkreg ASTAT, (0x30f0c200 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x4cc00080 | _VS | _V | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN); + imm32 R3, 0x3563cfa3; + imm32 R7, 0x027e2255; + R7 = R3 << 0x1f (V, S); + checkreg R7, 0x1ab1e7d1; + checkreg ASTAT, (0x4cc00080 | _VS | _AC1 | _AQ | _AC0_COPY | _AN); + + pass diff --git a/sim/testsuite/sim/bfin/random_0011.S b/sim/testsuite/sim/bfin/random_0011.S new file mode 100644 index 0000000..0b0ccac --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0011.S @@ -0,0 +1,102 @@ +# test acc shifts larger than they should be, and ASTAT flags +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x7cc0c090 | _VS | _V | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ); + dmm32 A0.w, 0x1890bdbc; + dmm32 A0.x, 0x00000079; + A0 = A0 << 0x2; + checkreg A0.w, 0x6242f6f0; + checkreg A0.x, 0xffffffe4; + checkreg ASTAT, (0x7cc0c090 | _VS | _V | _AC1 | _AQ | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x50508600 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); + dmm32 A1.w, 0x02fe375e; + dmm32 A1.x, 0x00000000; + A1 = A1 >> 0x21; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0xffffffaf; + checkreg ASTAT, (0x50508600 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x7c800a10 | _VS | _AV0S | _AV0 | _AC1); + dmm32 A0.w, 0x00000000; + dmm32 A0.x, 0x00000000; + A0 = A0 << 0x1f; + checkreg ASTAT, (0x7c800a10 | _VS | _AV0S | _AC1 | _AZ); + + dmm32 ASTAT, (0x4440c080 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x2e4b0bba; + dmm32 A0.x, 0xffffff8c; + A0 = A0 >> 0x25; + checkreg A0.w, 0xd0000000; + checkreg A0.x, 0x0000005d; + checkreg ASTAT, (0x4440c080 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x4c90c680 | _VS | _AV1S | _AV0S | _AC0 | _CC); + dmm32 A1.w, 0x3ae26599; + dmm32 A1.x, 0xfffffff3; + A1 = A1 >> 0x25; + checkreg A1.w, 0xc8000000; + checkreg A1.x, 0x0000002c; + checkreg ASTAT, (0x4c90c680 | _VS | _AV1S | _AV0S | _AC0 | _CC); + + dmm32 ASTAT, (0x3c204000 | _AV1 | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC); + dmm32 A1.w, 0x1686a378; + dmm32 A1.x, 0x0000006a; + A1 = A1 >> 0x16; + checkreg A1.w, 0x0001a85a; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x3c204000 | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC); + + dmm32 ASTAT, (0x30500800 | _VS | _AV0S | _AQ); + dmm32 A1.w, 0x6575285f; + dmm32 A1.x, 0x00000000; + A1 = A1 >> 0x2e; + checkreg A1.w, 0xa17c0000; + checkreg A1.x, 0xffffffd4; + checkreg ASTAT, (0x30500800 | _VS | _AV0S | _AQ | _AN); + + dmm32 ASTAT, (0x70c04010 | _VS | _AV0S | _AQ | _CC); + dmm32 A1.w, 0x0c7da4e2; + dmm32 A1.x, 0x00000000; + A1 = A1 >> 0x29; + checkreg A1.w, 0x71000000; + checkreg A1.x, 0xffffffd2; + checkreg ASTAT, (0x70c04010 | _VS | _AV0S | _AQ | _CC | _AN); + + dmm32 ASTAT, (0x74000600 | _VS | _AC1 | _AQ); + dmm32 A0.w, 0xd0e47afa; + dmm32 A0.x, 0x00000006; + A0 = A0 >> 0x32; + checkreg A0.w, 0x1ebe8000; + checkreg A0.x, 0x00000039; + checkreg ASTAT, (0x74000600 | _VS | _AC1 | _AQ); + + dmm32 ASTAT, (0x4ce08200 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ); + dmm32 A1.w, 0x1b158860; + dmm32 A1.x, 0x00000068; + A1 = A1 >> 0x21; + checkreg A1.w, 0x00000000; + checkreg A1.x, 0x00000030; + checkreg ASTAT, (0x4ce08200 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ); + + dmm32 ASTAT, (0x48c00610 | _VS | _AV1S | _AQ | _CC | _AN); + dmm32 A1.w, 0x0a2c41e4; + dmm32 A1.x, 0x00000000; + A1 = A1 >> 0x25; + checkreg A1.w, 0x20000000; + checkreg A1.x, 0x0000000f; + checkreg ASTAT, (0x48c00610 | _VS | _AV1S | _AQ | _CC); + + dmm32 ASTAT, (0x08700400 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY | _AZ); + dmm32 A0.w, 0xec125059; + dmm32 A0.x, 0xffffffff; + A0 = A0 >> 0x32; + checkreg A0.w, 0x94164000; + checkreg A0.x, 0x00000004; + checkreg ASTAT, (0x08700400 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY); + + pass diff --git a/sim/testsuite/sim/bfin/random_0012.S b/sim/testsuite/sim/bfin/random_0012.S new file mode 100644 index 0000000..cedf359 --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0012.S @@ -0,0 +1,52 @@ +# test VIT_MAX behavior when high Acc bits are set +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x5860c690 | _VS | _AV0S | _AC1 | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0xd81562e8; + dmm32 A0.x, 0xffffffff; + imm32 R4, 0x15c2d815; + imm32 R5, 0xc9bd3a6b; + R4.L = VIT_MAX (R5) (ASR); + checkreg R4, 0x15c23a6b; + checkreg A0.w, 0x6c0ab174; + checkreg A0.x, 0x0000007f; + checkreg ASTAT, (0x5860c690 | _VS | _AV0S | _AC1 | _AQ | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x48308090 | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x715cf6e6; + dmm32 A0.x, 0xffffffb6; + imm32 R3, 0x3a89c7ed; + imm32 R4, 0x4819bbf9; + R3.L = VIT_MAX (R4) (ASR); + checkreg R3, 0x3a89bbf9; + checkreg A0.w, 0x38ae7b73; + checkreg A0.x, 0x0000005b; + checkreg ASTAT, (0x48308090 | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x18104c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); + dmm32 A0.w, 0xea06f130; + dmm32 A0.x, 0xffffffff; + imm32 R2, 0x62ce98f1; + imm32 R5, 0x045415f9; + R2.L = VIT_MAX (R5) (ASR); + checkreg R2, 0x62ce15f9; + checkreg A0.w, 0x75037898; + checkreg A0.x, 0x0000007f; + checkreg ASTAT, (0x18104c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x0090ce10 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A0.w, 0xffffffff; + dmm32 A0.x, 0xffffffff; + imm32 R0, 0xc9647fff; + imm32 R6, 0x1d4baeb8; + R6.L = VIT_MAX (R0) (ASR); + checkreg R6, 0x1d4bc964; + checkreg A0.w, 0xffffffff; + checkreg A0.x, 0x0000007f; + checkreg ASTAT, (0x0090ce10 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN); + + pass diff --git a/sim/testsuite/sim/bfin/random_0013.S b/sim/testsuite/sim/bfin/random_0013.S new file mode 100644 index 0000000..9a427b3 --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0013.S @@ -0,0 +1,417 @@ +# Ensure that dsp insns with IH modifiers saturate first, then round +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x24304400 | _VS | _AV1S | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ); + dmm32 A0.w, 0x3883de11; + dmm32 A0.x, 0x00000025; + imm32 R2, 0xeb641947; + imm32 R3, 0x66d10863; + imm32 R5, 0x00d44f5a; + R5.L = (A0 += R3.L * R2.L) (IH); + checkreg R5, 0x00d47fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x24304400 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x04b04e10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0x1e069e1a; + dmm32 A0.x, 0xfffffff5; + imm32 R3, 0xffff0001; + R3.L = A0 (IH); + checkreg R3, 0xffff8000; + checkreg ASTAT, (0x04b04e10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x14f08600 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x766c79cc; + dmm32 A0.x, 0xffffffd9; + imm32 R4, 0x14801bff; + R4.L = A0 (IH); + checkreg R4, 0x14808000; + checkreg ASTAT, (0x14f08600 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x6060c600 | _VS | _AV1S | _AV0S | _AC1 | _V_COPY | _AN | _AZ); + dmm32 A0.w, 0x1e7461de; + dmm32 A0.x, 0xffffff91; + imm32 R6, 0x1ba08a9e; + R6.L = A0 (IH); + checkreg R6, 0x1ba08000; + checkreg ASTAT, (0x6060c600 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AN); + + dmm32 ASTAT, (0x28700e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ); + dmm32 A0.w, 0xfb5acc4e; + dmm32 A0.x, 0xfffffffe; + imm32 R4, 0x15baf604; + R4.L = A0 (IH); + checkreg R4, 0x15ba8000; + checkreg ASTAT, (0x28700e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x24708610 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A0.w, 0x0de70c92; + dmm32 A0.x, 0xffffffde; + imm32 R3, 0x0f323c4c; + R3.L = A0 (IH); + checkreg R3, 0x0f328000; + checkreg ASTAT, (0x24708610 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x6800c880 | _AV1 | _AV0 | _AQ | _AZ); + dmm32 A0.w, 0x482bfb59; + dmm32 A0.x, 0x0000005e; + imm32 R6, 0x4616e4ad; + imm32 R7, 0x4a88b2b1; + R6.L = (A0 += R6.H * R7.L) (IH); + checkreg R6, 0x46167fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x6800c880 | _VS | _V | _AV1 | _AV0S | _AV0 | _AQ | _V_COPY | _AZ); + + dmm32 ASTAT, (0x44d08280 | _VS | _V | _AQ | _V_COPY | _AZ); + dmm32 A0.w, 0xf29e3a4c; + dmm32 A0.x, 0x0000003b; + imm32 R2, 0x004027d0; + imm32 R4, 0x44761fd1; + imm32 R7, 0x7fff0001; + R7.L = (A0 -= R4.H * R2.H) (IH); + checkreg R7, 0x7fff7fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x44d08280 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AZ); + + dmm32 ASTAT, (0x18a00680 | _VS | _AV1S | _AQ | _CC); + dmm32 A0.w, 0x174c203a; + dmm32 A0.x, 0x00000060; + imm32 R3, 0x1f100000; + R3.L = A0 (IH); + checkreg R3, 0x1f107fff; + checkreg ASTAT, (0x18a00680 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x38e04090 | _VS | _AV0S | _AQ | _AN | _AZ); + dmm32 A0.w, 0x5db9b913; + dmm32 A0.x, 0x00000048; + imm32 R0, 0xd513ffff; + imm32 R2, 0xfcee02ff; + R0.L = (A0 -= R2.H * R0.H) (IH); + checkreg R0, 0xd5137fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x38e04090 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x2030c680 | _VS | _V | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x113de06e; + dmm32 A0.x, 0x00000006; + imm32 R3, 0x3de9b335; + R3.L = A0 (IH); + checkreg R3, 0x3de97fff; + checkreg ASTAT, (0x2030c680 | _VS | _V | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x14300210 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x3219dde5; + dmm32 A0.x, 0xfffffffe; + imm32 R2, 0x8000ffde; + R2.L = A0 (IH); + checkreg R2, 0x80008000; + checkreg ASTAT, (0x14300210 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x5c304e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x500d8a96; + dmm32 A0.x, 0x00000071; + imm32 R2, 0x47bc6a2d; + R2.L = A0 (IH); + checkreg R2, 0x47bc7fff; + checkreg ASTAT, (0x5c304e10 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x40d04410 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0xed76198b; + dmm32 A0.x, 0xffffffdd; + imm32 R4, 0x485f8000; + R4.L = A0 (IH); + checkreg ASTAT, (0x40d04410 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x34f00290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0xc0000000; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x80008000; + imm32 R3, 0x2cb77eda; + R0.L = (A0 += R3.H * R3.H) (IH); + checkreg R0, 0x80007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x34f00290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x2490c610 | _VS | _V | _V_COPY | _AN); + dmm32 A0.w, 0xc2375c00; + dmm32 A0.x, 0x00000000; + imm32 R0, 0x8000ffff; + imm32 R1, 0xac86b35f; + imm32 R6, 0x3cb137de; + R0.L = (A0 -= R6.H * R1.H) (IH); + checkreg R0, 0x80007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x2490c610 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AN); + + dmm32 ASTAT, (0x3000c810 | _VS | _AC0 | _AQ | _CC | _AN); + dmm32 A0.w, 0x44fe7a9d; + dmm32 A0.x, 0x0000006e; + imm32 R2, 0xbb4f8000; + imm32 R4, 0xfe2d7fff; + imm32 R7, 0x5da7ea43; + R7.L = (A0 += R4.L * R2.L) (IH); + checkreg R7, 0x5da77fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x3000c810 | _VS | _V | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x1c708000 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AZ); + dmm32 A0.w, 0x6ad001aa; + dmm32 A0.x, 0x0000002a; + imm32 R6, 0x7fff65d9; + R6.L = A0 (IH); + checkreg R6, 0x7fff7fff; + checkreg ASTAT, (0x1c708000 | _VS | _V | _AV1S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x1430cc80 | _AV0S | _AC0 | _AQ | _AN | _AZ); + dmm32 A0.w, 0x5c04c87a; + dmm32 A0.x, 0x00000002; + imm32 R1, 0x6752c24c; + imm32 R7, 0x21f7c24f; + R1.L = (A0 -= R1.H * R7.H) (IH); + checkreg R1, 0x67527fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x1430cc80 | _VS | _V | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x44500c80 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + dmm32 A0.w, 0x603980cf; + dmm32 A0.x, 0xffffffff; + imm32 R3, 0xffffffff; + R3.L = A0 (IH); + checkreg R3, 0xffff8000; + checkreg ASTAT, (0x44500c80 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x70508c90 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY); + dmm32 A0.w, 0x097b558d; + dmm32 A0.x, 0x00000005; + imm32 R1, 0x80002c0a; + R1.L = A0 (IH); + checkreg R1, 0x80007fff; + checkreg ASTAT, (0x70508c90 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY); + + dmm32 ASTAT, (0x1820c410 | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ); + dmm32 A0.w, 0x69470e6b; + dmm32 A0.x, 0x0000005a; + imm32 R1, 0x3a0e82ef; + imm32 R4, 0x2c0af024; + imm32 R6, 0x5a301523; + R1.L = (A0 += R6.L * R4.L) (IH); + checkreg R1, 0x3a0e7fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x1820c410 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x14a04e10 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0xaaa829c8; + dmm32 A0.x, 0x0000000f; + imm32 R3, 0x901b7fff; + imm32 R4, 0xf8d50755; + imm32 R6, 0x0a98c742; + R4.L = (A0 += R3.L * R6.L) (IH); + checkreg R4, 0xf8d57fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x14a04e10 | _VS | _V | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x7c70c800 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY); + dmm32 A0.w, 0x3875c265; + dmm32 A0.x, 0x0000000e; + imm32 R0, 0x8000af00; + imm32 R3, 0x071fe97d; + imm32 R5, 0x72d82b4b; + R0.L = (A0 += R3.H * R5.H) (IH); + checkreg R0, 0x80007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x7c70c800 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x04508a80 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY); + dmm32 A0.w, 0x5055d0b1; + dmm32 A0.x, 0x00000009; + imm32 R2, 0x7b9b1a96; + imm32 R4, 0x56a17f45; + R4.L = (A0 -= R4.L * R2.L) (IH); + checkreg R4, 0x56a17fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x04508a80 | _VS | _V | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x60408c90 | _VS | _AV1 | _CC | _AC0_COPY); + dmm32 A1.w, 0x4d722bbd; + dmm32 A1.x, 0x0000000a; + imm32 R1, 0x31c46841; + imm32 R4, 0xe31521b2; + imm32 R6, 0x49d747d4; + R6.H = (A1 -= R1.L * R4.L) (M, IH); + checkreg R6, 0x7fff47d4; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x60408c90 | _VS | _V | _AV1S | _AV1 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x7c808690 | _VS | _AV1S | _AC1 | _AC0 | _AC0_COPY); + dmm32 A0.w, 0x48379e0d; + dmm32 A0.x, 0x00000061; + imm32 R0, 0x272c8000; + imm32 R4, 0x7fff7fff; + R0.L = (A0 += R4.L * R4.H) (IH); + checkreg R0, 0x272c7fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x7c808690 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x10308800 | _VS | _AC1 | _AC0 | _AQ | _AN); + dmm32 A1.w, 0x9ddbf339; + dmm32 A1.x, 0x00000010; + imm32 R1, 0x00679160; + imm32 R5, 0x1fa0ffff; + imm32 R6, 0x4312c2cd; + R6.H = (A1 -= R1.L * R5.H) (IH); + checkreg R6, 0x7fffc2cd; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x10308800 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x3040ca90 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC | _AN | _AZ); + dmm32 A0.w, 0x2d631ab7; + dmm32 A0.x, 0x00000066; + imm32 R5, 0x325c8000; + R5.L = A0 (IH); + checkreg R5, 0x325c7fff; + checkreg ASTAT, (0x3040ca90 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x5ca08c90 | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + dmm32 A0.w, 0x86fce74b; + dmm32 A0.x, 0x0000007f; + imm32 R1, 0x3e9e0014; + imm32 R7, 0x6d73d06c; + R7.L = (A0 += R1.L * R7.H) (IH); + checkreg R7, 0x6d737fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x5ca08c90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x50e0c880 | _VS | _AC1); + dmm32 A0.w, 0x9e40a194; + dmm32 A0.x, 0x00000000; + imm32 R5, 0x6ba7ac29; + imm32 R6, 0x50a97ffe; + R5.L = (A0 += R6.L * R5.H) (IH); + checkreg R5, 0x6ba77fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x50e0c880 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY); + + dmm32 ASTAT, (0x3ce0c810 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0x9abe32ae; + dmm32 A0.x, 0xffffffc2; + imm32 R2, 0x8000e9a0; + R2.L = A0 (IH); + checkreg R2, 0x80008000; + checkreg ASTAT, (0x3ce0c810 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x6090c010 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY); + dmm32 A0.w, 0x53e97a53; + dmm32 A0.x, 0x0000004d; + imm32 R1, 0x289e2e4e; + R1.L = A0 (IH); + checkreg R1, 0x289e7fff; + checkreg ASTAT, (0x6090c010 | _VS | _V | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x34708800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN); + dmm32 A0.w, 0x1035b3fa; + dmm32 A0.x, 0x00000001; + imm32 R1, 0xec227fff; + R1.L = A0 (IH); + checkreg ASTAT, (0x34708800 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x30200c00 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _V_COPY); + imm32 R1, 0x30d07fff; + imm32 R2, 0x007f1105; + imm32 R4, 0x7fffffff; + R1.H = R2.L * R4.L (M, IH); + checkreg R1, 0x11057fff; + checkreg ASTAT, (0x30200c00 | _VS | _AV1S | _AV0S | _AV0 | _AC1); + + dmm32 ASTAT, (0x1c008200 | _VS | _V | _AV1S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); + dmm32 A0.w, 0x46ccaead; + dmm32 A0.x, 0x0000006b; + imm32 R4, 0x80003753; + imm32 R5, 0x128216a3; + imm32 R6, 0x7c3455c4; + R4.L = (A0 += R5.L * R6.H) (IH); + checkreg R4, 0x80007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x1c008200 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ); + + dmm32 ASTAT, (0x14304e10 | _VS | _AV0S | _AV0 | _AC0); + dmm32 A0.w, 0x7fc17d70; + dmm32 A0.x, 0x0000000f; + imm32 R3, 0x5cb72991; + imm32 R4, 0x3a823142; + imm32 R7, 0xde5bf5a2; + R7.L = (A0 += R4.H * R3.H) (IH); + checkreg R7, 0xde5b7fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x14304e10 | _VS | _V | _AV0S | _AV0 | _AC0 | _V_COPY); + + dmm32 ASTAT, (0x10900290 | _VS | _V | _AQ | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0x7fb16a1d; + dmm32 A0.x, 0x00000052; + imm32 R0, 0x1e4a7fff; + imm32 R2, 0x62b886f4; + imm32 R3, 0x80004104; + R3.L = (A0 -= R2.H * R0.H) (IH); + checkreg R3, 0x80007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x10900290 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x18608400 | _VS | _AV1S | _AQ | _AC0_COPY | _AN); + dmm32 A1.w, 0x62fcbde0; + dmm32 A1.x, 0x0000006a; + imm32 R2, 0x60339fcc; + imm32 R3, 0x5fa9f612; + imm32 R4, 0x6f006000; + R2.H = (A1 += R3.L * R4.H) (IH); + checkreg R2, 0x7fff9fcc; + checkreg A1.w, 0x7fffffff; + checkreg A1.x, 0x00000000; + checkreg ASTAT, (0x18608400 | _VS | _V | _AV1S | _AV1 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x60100210 | _VS | _V | _CC | _V_COPY | _AN); + dmm32 A0.w, 0x52a9b75e; + dmm32 A0.x, 0x00000003; + imm32 R0, 0xffff349c; + imm32 R6, 0x0084550f; + R0.L = (A0 += R6.L * R0.H) (IH); + checkreg R0, 0xffff7fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x60100210 | _VS | _V | _AV0S | _AV0 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x7840cc10 | _VS | _V | _AV0 | _AC1 | _V_COPY | _AN | _AZ); + dmm32 A0.w, 0x22aa6b49; + dmm32 A0.x, 0x0000006a; + imm32 R1, 0x17528642; + imm32 R5, 0x8000a49b; + imm32 R6, 0x03ec4bb6; + R5.L = (A0 -= R1.H * R6.H) (IH); + checkreg R5, 0x80007fff; + checkreg A0.w, 0x7fffffff; + checkreg A0.x, 0x00000000; + checkreg ASTAT, (0x7840cc10 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN | _AZ); + + pass diff --git a/sim/testsuite/sim/bfin/random_0031.S b/sim/testsuite/sim/bfin/random_0031.S new file mode 100644 index 0000000..4a849e1 --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0031.S @@ -0,0 +1,185 @@ +# Check that VS in ASTAT is set with add/sub insns (and not just V) +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x2810c010 | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + imm32 R0, 0x27f3a149; + imm32 R3, 0x3cae7c58; + imm32 R4, 0x33c97634; + R3.H = R0.L - R4.H (NS); + checkreg R3, 0x6d807c58; + checkreg ASTAT, (0x2810c010 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x64c00680 | _AQ | _AC0_COPY); + imm32 R1, 0x1b7b025c; + imm32 R5, 0x1ba46ce6; + R5.L = R5.L + R1.H (NS); + checkreg R5, 0x1ba48861; + checkreg ASTAT, (0x64c00680 | _VS | _V | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x68b04200 | _AV1S | _AV0 | _AC0 | _AQ | _AN); + imm32 R3, 0x4b91870f; + imm32 R6, 0x5972bae0; + imm32 R7, 0x31f7dfb7; + R7.H = R6.L + R3.L (S); + checkreg R7, 0x8000dfb7; + checkreg ASTAT, (0x68b04200 | _VS | _V | _AV1S | _AV0 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x78208e90 | _CC | _AN); + imm32 R3, 0x40b63bc7; + imm32 R5, 0x49c89df9; + R3.H = R5.L - R3.H (NS); + checkreg R3, 0x5d433bc7; + checkreg ASTAT, (0x78208e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x00904680 | _AV1S | _AV1 | _AV0 | _AC1 | _AQ | _AZ); + imm32 R2, 0x23a2c115; + imm32 R4, 0x6977581e; + imm32 R6, 0x41900942; + R4.L = R2.L - R6.H (NS); + checkreg R4, 0x69777f85; + checkreg ASTAT, (0x00904680 | _VS | _V | _AV1S | _AV1 | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x78d08210 | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ); + imm32 R0, 0x4317139e; + imm32 R1, 0x49ed40d6; + R0.L = R1.L + R0.H (NS); + checkreg R0, 0x431783ed; + checkreg ASTAT, (0x78d08210 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AN); + + dmm32 ASTAT, (0x58d00e10 | _AV1 | _AQ | _CC); + imm32 R0, 0x09ea77a2; + imm32 R1, 0x6ccd0b05; + imm32 R2, 0x761c63af; + R1.H = R0.L + R2.H (NS); + checkreg R1, 0xedbe0b05; + checkreg ASTAT, (0x58d00e10 | _VS | _V | _AV1 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x30c08000 | _AC0 | _AQ | _AC0_COPY); + imm32 R4, 0x36d243cb; + imm32 R5, 0xcd127add; + R4.H = R5.L + R4.L (NS); + checkreg R4, 0xbea843cb; + checkreg ASTAT, (0x30c08000 | _VS | _V | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x74108400 | _V | _AV1 | _AC1 | _AC0 | _AC0_COPY); + imm32 R0, 0x4e1893ea; + imm32 R1, 0x13cf5cc8; + imm32 R3, 0x7441949e; + R1.L = R0.L - R3.H (NS); + checkreg R1, 0x13cf1fa9; + checkreg ASTAT, (0x74108400 | _VS | _V | _AV1 | _AC1 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x7420ce10 | _AV1S | _AV1 | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN | _AZ); + imm32 R4, 0x532c8fb1; + imm32 R6, 0x582420d2; + R6.H = R4.L - R4.H (NS); + checkreg R6, 0x3c8520d2; + checkreg ASTAT, (0x7420ce10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x74704010 | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY); + imm32 R3, 0x6f6a7429; + imm32 R5, 0x2ea5c47e; + R5.H = R5.L - R3.H (NS); + checkreg R5, 0x5514c47e; + checkreg ASTAT, (0x74704010 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x0ce08490 | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AZ); + imm32 R1, 0xfd18a0b0; + imm32 R4, 0x259e2151; + R4.L = R1.L - R4.H (NS); + checkreg R4, 0x259e7b12; + checkreg ASTAT, (0x0ce08490 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x54b08810 | _V | _AV1S | _AV0S | _AC0_COPY | _AN); + imm32 R3, 0x7a763675; + imm32 R6, 0x23c4a335; + R3.L = R6.L + R6.L (NS); + checkreg R3, 0x7a76466a; + checkreg ASTAT, (0x54b08810 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x70f0c080 | _AV1S | _AV0S | _AC0); + imm32 R4, 0x55fab7e4; + imm32 R5, 0x7dbd9b06; + R5.H = R5.L - R4.H (S); + checkreg R5, 0x80009b06; + checkreg ASTAT, (0x70f0c080 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x5ce04680 | _AV0 | _AC0 | _V_COPY | _AC0_COPY | _AN); + imm32 R0, 0x19cacbdb; + imm32 R2, 0x151cb293; + imm32 R4, 0x571c351a; + R0.H = R4.L - R2.L (S); + checkreg R0, 0x7fffcbdb; + checkreg ASTAT, (0x5ce04680 | _VS | _V | _AV0 | _V_COPY); + + dmm32 ASTAT, (0x0c604a00 | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AZ); + imm32 R3, 0x5432c45d; + imm32 R6, 0x62519952; + R3.L = R6.L + R6.L (S); + checkreg R3, 0x54328000; + checkreg ASTAT, (0x0c604a00 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x58708c90 | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN | _AZ); + imm32 R0, 0x1f3f3c0e; + imm32 R4, 0x5fae58d2; + R0.H = R0.L + R4.L (NS); + checkreg R0, 0x94e03c0e; + checkreg ASTAT, (0x58708c90 | _VS | _V | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x34b00a00 | _V | _AV1S | _AC1 | _CC | _V_COPY | _AZ); + imm32 R3, 0x6ea226dc; + imm32 R4, 0x045c6d64; + imm32 R7, 0x7e599a25; + R7.L = R3.L + R4.L (NS); + checkreg R7, 0x7e599440; + checkreg ASTAT, (0x34b00a00 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x40a0c010 | _AV1S | _AC0); + imm32 R2, 0x641501ef; + imm32 R7, 0x3acb49aa; + R2.H = R7.L + R7.H (NS); + checkreg R2, 0x847501ef; + checkreg ASTAT, (0x40a0c010 | _VS | _V | _AV1S | _V_COPY | _AN); + + dmm32 ASTAT, (0x78f04090 | _AV1S | _AC1 | _AQ | _CC | _AZ); + imm32 R2, 0x65681fdf; + imm32 R3, 0x5fffe0d3; + imm32 R5, 0x37df99cd; + R2.H = R5.L - R3.H (NS); + checkreg R2, 0x39ce1fdf; + checkreg ASTAT, (0x78f04090 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x0cc04e10 | _AV1S | _AQ | _CC); + imm32 R3, 0x571977df; + imm32 R4, 0x029671d0; + R3.L = R4.L + R3.H (NS); + checkreg R3, 0x5719c8e9; + checkreg ASTAT, (0x0cc04e10 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AN); + + dmm32 ASTAT, (0x00104880 | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN); + imm32 R0, 0x4c98aa07; + imm32 R4, 0x5e9da59f; + R4.H = R0.L + R0.L (S); + checkreg R4, 0x8000a59f; + checkreg ASTAT, (0x00104880 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x08008c00 | _AV1S | _AV0S | _AV0 | _CC | _AC0_COPY); + imm32 R4, 0x58ee2400; + imm32 R6, 0x2e97af3e; + R4.L = R6.L + R6.L (NS); + checkreg R4, 0x58ee5e7c; + checkreg ASTAT, (0x08008c00 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x2ce0c290 | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN); + imm32 R2, 0x2d467e64; + imm32 R6, 0x31aeb601; + imm32 R7, 0x1523a746; + R7.L = R2.L - R6.L (S); + checkreg R7, 0x15237fff; + checkreg ASTAT, (0x2ce0c290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY); + + pass diff --git a/sim/testsuite/sim/bfin/random_0033.S b/sim/testsuite/sim/bfin/random_0033.S new file mode 100644 index 0000000..4835396 --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0033.S @@ -0,0 +1,64 @@ +# Verify registers saturate and ASTAT bits are updated correctly +# with the RND12 subtract insn +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x24a00410 | _VS | _AV1S | _AV0 | _AC0 | _AC0_COPY | _AN); + imm32 R5, 0x0fb35119; + imm32 R6, 0xffffffff; + imm32 R7, 0x80000000; + R6.H = R5 - R7 (RND12); + checkreg R6, 0x7fffffff; + checkreg ASTAT, (0x24a00410 | _VS | _V | _AV1S | _AV0 | _AC0 | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x08c08000 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + imm32 R3, 0x80003f8f; + imm32 R5, 0x6267c92c; + imm32 R6, 0x80000000; + R5.L = R3 - R6 (RND12); + checkreg R5, 0x62670004; + checkreg ASTAT, (0x08c08000 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY); + + dmm32 ASTAT, (0x04200c10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY); + imm32 R1, 0x7fff0000; + imm32 R5, 0x80000000; + R1.L = R5 - R5 (RND12); + checkreg ASTAT, (0x04200c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AZ); + checkreg R1, 0x7fff0000; + checkreg R5, 0x80000000; + + dmm32 ASTAT, (0x40600e90 | _VS | _AV1S | _AV0S | _AQ | _CC); + imm32 R1, 0x80000000; + imm32 R5, 0x00008000; + imm32 R6, 0x00000000; + R5.L = R6 - R1 (RND12); + checkreg R5, 0x00007fff; + checkreg ASTAT, (0x40600e90 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY); + + dmm32 ASTAT, (0x68300880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ); + imm32 R1, 0xf8ed0000; + imm32 R6, 0x80000000; + R1.H = R1 - R6 (RND12); + checkreg R1, 0x7fff0000; + checkreg ASTAT, (0x68300880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x70d0c410 | _VS | _AV0S | _AQ); + imm32 R0, 0x80000000; + imm32 R1, 0x71455f95; + imm32 R4, 0xd4871012; + R4.H = R1 - R0 (RND12); + checkreg R4, 0x7fff1012; + checkreg ASTAT, (0x70d0c410 | _VS | _V | _AV0S | _AQ | _V_COPY); + + dmm32 ASTAT, (0x34500e00 | _VS | _AV0S | _AC1 | _CC | _AZ); + imm32 R2, 0x00000000; + imm32 R5, 0x00000000; + imm32 R6, 0x80000000; + R2.L = R5 - R6 (RND12); + checkreg R2, 0x00007fff; + checkreg ASTAT, (0x34500e00 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY); + + pass diff --git a/sim/testsuite/sim/bfin/random_0034.S b/sim/testsuite/sim/bfin/random_0034.S new file mode 100644 index 0000000..7aeaadb --- /dev/null +++ b/sim/testsuite/sim/bfin/random_0034.S @@ -0,0 +1,129 @@ +# Verify sign extension behavior with simultaneous acc additions, and +# verify that no ASTAT bits get changed as a result +# mach: bfin +#include "test.h" +.include "testutils.inc" + + start + + dmm32 ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ); + dmm32 A0.w, 0x589145b7; + dmm32 A0.x, 0xffffffee; + dmm32 A1.w, 0x0b247b05; + dmm32 A1.x, 0x0000005a; + imm32 R3, 0x1e414332; + imm32 R4, 0x351715b7; + R3 = A1.L + A1.H, R4 = A0.L + A0.H; + checkreg R3, 0x00008629; + checkreg R4, 0x00009e48; + checkreg ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ); + + dmm32 ASTAT, (0x40e0cc00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); + dmm32 A0.w, 0xb2c58001; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xe999dc28; + dmm32 A1.x, 0xffffffff; + imm32 R0, 0xe58d5ffa; + imm32 R4, 0x7fff7fff; + R0 = A1.L + A1.H, R4 = A0.L + A0.H; + checkreg R0, 0xffffc5c1; + checkreg R4, 0xffff32c6; + checkreg ASTAT, (0x40e0cc00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY); + + dmm32 ASTAT, (0x3420ca80 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC); + dmm32 A0.w, 0xeff48350; + dmm32 A0.x, 0xffffffff; + dmm32 A1.w, 0x5a3f623a; + dmm32 A1.x, 0xffffffff; + imm32 R4, 0xffff152f; + imm32 R6, 0xdd13218a; + R4 = A1.L + A1.H, R6 = A0.L + A0.H; + checkreg R4, 0x0000bc79; + checkreg R6, 0xffff7344; + checkreg ASTAT, (0x3420ca80 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC); + + dmm32 ASTAT, (0x10204880 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AN); + dmm32 A0.w, 0x6da679bb; + dmm32 A0.x, 0xffffff96; + dmm32 A1.w, 0x1f5fb024; + dmm32 A1.x, 0x00000000; + imm32 R3, 0x3ebf8000; + imm32 R6, 0x025f2e8c; + R6 = A1.L + A1.H, R3 = A0.L + A0.H; + checkreg R3, 0x0000e761; + checkreg R6, 0xffffcf83; + checkreg ASTAT, (0x10204880 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AN); + + dmm32 ASTAT, (0x6ca00c90 | _V | _AV1S | _AV1 | _AC0_COPY | _AN | _AZ); + dmm32 A0.w, 0x59abaa84; + dmm32 A0.x, 0xffffffe1; + dmm32 A1.w, 0x71541efe; + dmm32 A1.x, 0x00000009; + imm32 R0, 0x2c41e797; + imm32 R5, 0x7bfa5e8a; + R0 = A1.L + A1.H, R5 = A0.L + A0.H; + checkreg R0, 0x00009052; + checkreg R5, 0x0000042f; + checkreg ASTAT, (0x6ca00c90 | _V | _AV1S | _AV1 | _AC0_COPY | _AN | _AZ); + + dmm32 ASTAT, (0x1c50c290 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AN); + dmm32 A0.w, 0xffffffff; + dmm32 A0.x, 0xffffffff; + dmm32 A1.w, 0xc49ca8db; + dmm32 A1.x, 0xffffffff; + imm32 R3, 0x0f62ffff; + imm32 R4, 0x09505188; + R4 = A1.L + A1.H, R3 = A0.L + A0.H; + checkreg R3, 0xfffffffe; + checkreg R4, 0xffff6d77; + checkreg ASTAT, (0x1c50c290 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AN); + + dmm32 ASTAT, (0x70e04a90 | _VS | _AV0S | _AQ); + dmm32 A0.w, 0xd827823e; + dmm32 A0.x, 0xffffffff; + dmm32 A1.w, 0x303d11ba; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x80007fff; + imm32 R6, 0xffc4feb3; + R6 = A1.L + A1.H, R1 = A0.L + A0.H; + checkreg R1, 0xffff5a65; + checkreg R6, 0x000041f7; + checkreg ASTAT, (0x70e04a90 | _VS | _AV0S | _AQ); + + dmm32 ASTAT, (0x5c80c200 | _VS | _AV0S | _AQ | _AC0_COPY | _AN); + dmm32 A0.w, 0x97049850; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0xffffa014; + dmm32 A1.x, 0xffffffff; + imm32 R0, 0x04828378; + imm32 R5, 0x3d9effff; + R0 = A1.L + A1.H, R5 = A0.L + A0.H; + checkreg R0, 0xffffa013; + checkreg R5, 0xffff2f54; + checkreg ASTAT, (0x5c80c200 | _VS | _AV0S | _AQ | _AC0_COPY | _AN); + + dmm32 ASTAT, (0x6c604600 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AZ); + dmm32 A0.w, 0xac43c455; + dmm32 A0.x, 0x00000000; + dmm32 A1.w, 0x03de6f39; + dmm32 A1.x, 0x00000000; + imm32 R0, 0x5bbfd2d1; + imm32 R3, 0x22425ebc; + R3 = A1.L + A1.H, R0 = A0.L + A0.H; + checkreg R0, 0xffff7098; + checkreg R3, 0x00007317; + checkreg ASTAT, (0x6c604600 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AZ); + + dmm32 ASTAT, (0x7cd04280 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + dmm32 A0.w, 0xb63ac8f5; + dmm32 A0.x, 0xffffffe0; + dmm32 A1.w, 0x358b94e8; + dmm32 A1.x, 0x00000000; + imm32 R1, 0x80007fff; + imm32 R6, 0x4f4a8883; + R6 = A1.L + A1.H, R1 = A0.L + A0.H; + checkreg R1, 0xffff7f2f; + checkreg R6, 0xffffca73; + checkreg ASTAT, (0x7cd04280 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN); + + pass diff --git a/sim/testsuite/sim/bfin/run-tests.sh b/sim/testsuite/sim/bfin/run-tests.sh new file mode 100644 index 0000000..2b6181b --- /dev/null +++ b/sim/testsuite/sim/bfin/run-tests.sh @@ -0,0 +1,225 @@ +#!/bin/sh + +usage() { + cat <<-EOF + Usage: $0 [-rs] [-rj ] [-rh ] [tests] + + If no tests are specified, all tests are processed. + + Options: + -rs Run on simulator + -rj Run on board via JTAG + -rh Run on board ip + EOF + exit ${0:-1} +} + +: ${MAKE:=make} +boardip= +boardjtag= +run_sim=false +run_jtag=false +run_host=false +while [ -n "$1" ] ; do + case $1 in + -rs) run_sim=true;; + -rj) boardjtag=$2; shift; run_jtag=true;; + -rh) boardip=$2; shift; run_host=true;; + -*) usage;; + *) break;; + esac + shift +done +${run_jtag} || ${run_host} || ${run_sim} || run_sim=true + +if ${run_host} && [ -z "${boardip}" ] ; then + usage +fi + +dorsh() { + # rsh sucks and does not pass up its exit status, so we have to: + # on board: + # - send all output to stdout + # - send exit status to stderr + # on host: + # - swap stdout and stderr + # - pass exit status to `exit` + # - send stderr back to stdout and up + (exit \ + $(rsh -l root $boardip \ + '(/tmp/'$1') 2>&1; ret=$?; echo $ret 1>&2; [ $ret -eq 0 ] && rm -f /tmp/'$1 \ + 3>&1 1>&2 2>&3) \ + 2>&1) 2>&1 +} + +dojtag() { + if grep -q CHECKREG ${1%.x} ; then + echo "DBGA does not work via JTAG" + exit 77 + fi + + cat <<-EOF > commands + target remote localhost:2000 + load + + b *_pass + commands + exit 0 + end + + b *_fail + commands + exit 1 + end + + # we're executing at EVT1, so this doesn't really help ... + set ((long *)0xFFE02000)[3] = _fail + set ((long *)0xFFE02000)[5] = _fail + + c + EOF + bfin-elf-gdb -x commands "$1" + ret=$? + rm -f commands + exit ${ret} +} + +testit() { + + local name=$1 x=$2 y=`echo $2 | sed 's:\.[xX]$::'` out rsh_out addr + shift; shift + local fail=`grep xfail ${y}` + if [ "${name}" = "HOST" -a ! -f $x ] ; then + return + fi + printf '%-5s %-40s' ${name} ${x} + out=`"$@" ${x} 2>&1` + (pf "${out}") + if [ $? -ne 0 ] ; then + if [ "${name}" = "SIM" ] ; then + tmp=`echo ${out} | awk '{print $3}' | sed 's/://'` + tmp1=`expr index "${out}" "program stopped with signal 4"` + if [ ${tmp1} -eq 1 ] ; then + printf 'illegal instruction\n' + elif [ -n "${tmp}" ] ; then + printf 'FAIL at line ' + addr=`echo $out | sed 's:^[A-Za-z ]*::' | sed 's:^0x[0-9][0-9] ::' | sed 's:^[A-Za-z ]*::' | awk '{print $1}'` + bfin-elf-addr2line -e ${x} ${addr} | awk -F "/" '{print $NF}' + fi + elif [ "${name}" = "HOST" ] ; then + rsh_out=`rsh -l root $boardip '/bin/dmesg -c | /bin/grep -e DBGA -e "FAULT "'` + tmp=`echo ${rsh_out} | sed 's:\].*$::' | awk '{print $NF}' | awk -F ":" '{print $NF}'` + if [ -n "${tmp}" ] ; then + echo "${rsh_out}" + printf 'FAIL at line ' + bfin-elf-addr2line -e ${x} $(echo ${rsh_out} | sed 's:\].*$::' | awk '{print $NF}') | awk -F "/" '{print $NF}' + fi + fi + ret=$(( ret + 1 )) + if [ -z "${fail}" ] ; then + unexpected_fail=$(( unexpected_fail + 1 )) + echo "!!!Expected Pass, but fail" + fi + else + if [ ! -z "${fail}" ] ; then + unexpected_pass=$(( unexpected_pass + 1 )) + echo "!!!Expected fail, but pass" + else + expected_pass=$(( expected_pass + 1 )) + fi + fi +} + +pf() { + local ret=$? + if [ ${ret} -eq 0 ] ; then + echo "PASS" + elif [ ${ret} -eq 77 ] ; then + echo "SKIP $*" + else + echo "FAIL! $*" + exit 1 + fi +} + +[ $# -eq 0 ] && set -- *.[Ss] +bins_hw=$( (${run_sim} || ${run_jtag}) && printf '%s.x ' "$@") +if ${run_host} ; then + for files in $@ + do + tmp=`grep -e CYCLES -e TESTSET -e CLI -e STI -e RTX -e RTI -e SEQSTAT $files -l` + if [ -z "${tmp}" ] ; then + bins_host=`echo "${bins_host} ${files}.X"` + else + echo "skipping ${files}, since it isn't userspace friendly" + fi + done +fi +if [ -n "${bins_hw}" ] ; then + bins_all="${bins_hw}" +fi + +if [ -n "${bins_host}" ] ; then + bins_all="${bins_all} ${bins_host}" +fi + +if [ -z "${bins_all}" ] ; then + exit +fi + +printf 'Compiling tests: ' +${MAKE} -s -j ${bins_all} +pf + +if ${run_jtag} ; then + printf 'Setting up gdbproxy (see gdbproxy.log): ' + killall -q bfin-gdbproxy + bfin-gdbproxy -q bfin --reset --board=${boardjtag} --init-sdram >gdbproxy.log 2>&1 & + t=0 + while [ ${t} -lt 5 ] ; do + if netstat -nap 2>&1 | grep -q ^tcp.*:2000.*gdbproxy ; then + break + else + : $(( t += 1 )) + sleep 1 + fi + done + pf +fi + +if ${run_host} ; then + printf 'Uploading tests to board "%s": ' "${boardip}" + rcp ${bins_host} root@${boardip}:/tmp/ + pf + rsh -l root $boardip '/bin/dmesg -c' > /dev/null +fi + +ret=0 +unexpected_fail=0 +unexpected_pass=0 +expected_pass=0 +for s in "$@" ; do + ${run_sim} && testit SIM ${s}.x bfin-elf-run `sed -n '/^# sim:/s|^[^:]*:||p' ${s}` + ${run_jtag} && testit JTAG ${s}.x dojtag + ${run_host} && testit HOST ${s}.X dorsh +done + +killall -q bfin-gdbproxy +if [ ${ret} -eq 0 ] ; then + rm -f gdbproxy.log + ${MAKE} -s clean & + exit 0 +else + echo number of failures ${ret} + if [ ${unexpected_pass} -gt 0 ] ; then + echo "Unexpected passes: ${unexpected_pass}" + fi + if [ ${unexpected_fail} -gt 0 ] ; then + echo "Unexpected fails: ${unexpected_fail}" + fi + if [ ${expected_pass} -gt 0 ] ; then + echo "passes : ${expected_pass}" + fi + exit 1 +fi + diff --git a/sim/testsuite/sim/bfin/s0.s b/sim/testsuite/sim/bfin/s0.s new file mode 100644 index 0000000..8fa53f2 --- /dev/null +++ b/sim/testsuite/sim/bfin/s0.s @@ -0,0 +1,12 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 10; + P0 = R0; + LSETUP ( ls0 , ls0 ) LC0 = P0; +ls0: + R0 += -1; + DBGA ( R0.L , 0 ); + pass diff --git a/sim/testsuite/sim/bfin/s1.s b/sim/testsuite/sim/bfin/s1.s new file mode 100644 index 0000000..262dc06 --- /dev/null +++ b/sim/testsuite/sim/bfin/s1.s @@ -0,0 +1,25 @@ +# mach: bfin + +.include "testutils.inc" + start + + R0 = 1; + R1 = 2; + R2 = 3; + R4 = 4; + P1 = R1; + LSETUP ( ls0 , ls0 ) LC0 = P1; + R5 = 5; + R6 = 6; + R7 = 7; + +ls0: R1 += 1; + + DBGA ( R1.L , 4 ); + P1 = R1; + LSETUP ( ls1 , ls1 ) LC1 = P1; +ls1: R1 += 1; + + DBGA ( R1.L , 8 ); + + pass diff --git a/sim/testsuite/sim/bfin/s10.s b/sim/testsuite/sim/bfin/s10.s new file mode 100644 index 0000000..503cabf --- /dev/null +++ b/sim/testsuite/sim/bfin/s10.s @@ -0,0 +1,77 @@ +// Shifter test program. +// Test instructions +// RL0 = SIGNBITS R1; +// RL0 = SIGNBITS RL1; +// RL0 = SIGNBITS RH1; + +# mach: bfin + +.include "testutils.inc" + start + + +// on 32-b word + + R1.L = 0xffff; + R1.H = 0x7fff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0000 ); + + R1.L = 0xffff; + R1.H = 0x30ff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0001 ); + + R1.L = 0xff0f; + R1.H = 0x10ff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0002 ); + + R1.L = 0xff0f; + R1.H = 0xe0ff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0002 ); + + R1.L = 0x0001; + R1.H = 0x0000; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0001e ); + + R1.L = 0xfffe; + R1.H = 0xffff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0001e ); + + R1.L = 0xffff; // return largest norm for -1 + R1.H = 0xffff; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x0001f ); + + R1.L = 0; // return largest norm for zero + R1.H = 0; + R0.L = SIGNBITS R1; + DBGA ( R0.L , 0x001f ); + +// on 16-b word + + R1.L = 0x7fff; + R1.H = 0xffff; + R0.L = SIGNBITS R1.L; + DBGA ( R0.L , 0x0000 ); + + R1.L = 0x0fff; + R1.H = 0x0001; + R0.L = SIGNBITS R1.H; + DBGA ( R0.L , 0x000e ); + + R1.L = 0x0fff; + R1.H = 0xffff; + R0.L = SIGNBITS R1.H; + DBGA ( R0.L , 0x000f ); + + R1.L = 0x0fff; + R1.H = 0xfffe; + R0.L = SIGNBITS R1.H; + DBGA ( R0.L , 0x000e ); + + pass diff --git a/sim/testsuite/sim/bfin/s11.s b/sim/testsuite/sim/bfin/s11.s new file mode 100644 index 0000000..16a57eb --- /dev/null +++ b/sim/testsuite/sim/bfin/s11.s @@ -0,0 +1,177 @@ +# mach: bfin + +// Shift test program. +// Test instructions +// RL0 = CC = BXOR (A0 AND R1) << 1; +// RL0 = CC = BXOR A0 AND R1; +// A0 <<=1 (BXOR A0 AND A1 CC); +// RL3 = CC = BXOR A0 AND A1 CC; + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + +// RL0 = CC = BXOR (A0 AND R1) << 1; + R0.L = 0x1000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + R1.L = 0xffff; + R1.H = 0xffff; + R2.L = CC = BXORSHIFT( A0 , R1 ); + R0 = A0.w; + DBGA ( R0.L , 0x2000 ); + DBGA ( R0.H , 0x0000 ); + R0.L = A0.x; + DBGA ( R0.L , 0x0000 ); + R0 = CC; + DBGA ( R0.L , 0x0001 ); + DBGA ( R0.H , 0x0000 ); + DBGA ( R2.L , 0x0001 ); + + R0.L = 0x1000; + R0.H = 0x0001; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + R1.L = 0xffff; + R1.H = 0xffff; + R2.L = CC = BXORSHIFT( A0 , R1 ); + R0 = A0.w; + DBGA ( R0.L , 0x2000 ); + DBGA ( R0.H , 0x0002 ); + R0.L = A0.x; + DBGA ( R0.L , 0x0000 ); + R0 = CC; + DBGA ( R0.L , 0x0000 ); + DBGA ( R0.H , 0x0000 ); + DBGA ( R2.L , 0x0000 ); + + R0.L = 0xffff; + R0.H = 0xffff; + A0.w = R0; + R0.L = 0x00ff; + A0.x = R0.L; + R1.L = 0xffff; + R1.H = 0xffff; + R2.L = CC = BXORSHIFT( A0 , R1 ); + R0 = A0.w; + DBGA ( R0.L , 0xfffe ); + DBGA ( R0.H , 0xffff ); + R0.L = A0.x; + DBGA ( R0.L , 0xffff ); + R0 = CC; + DBGA ( R0.L , 0x0001 ); + DBGA ( R0.H , 0x0000 ); + DBGA ( R2.L , 0x0001 ); + +// no + R0.L = 0xffff; + R0.H = 0xffff; + A0.w = R0; + R0.L = 0x00ff; + A0.x = R0.L; + R1.L = 0xffff; + R1.H = 0xffff; + R2.L = CC = BXOR( A0 , R1 ); + R0 = A0.w; + DBGA ( R0.L , 0xffff ); + DBGA ( R0.H , 0xffff ); + R0.L = A0.x; + DBGA ( R0.L , 0xffff ); + R0 = CC; + DBGA ( R0.L , 0x0000 ); + DBGA ( R0.H , 0x0000 ); + DBGA ( R2.H , 0x0000 ); + +// A0 <<=1 (BXOR A0 AND A1 CC); + + R0.L = 0x1000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + R0.L = 0xffff; + R0.H = 0xffff; + A1.w = R0; + R0.L = 0x00ff; + A1.x = R0.L; + R0.L = 0x0000; + R0.H = 0x0000; + CC = R0; + A0 = BXORSHIFT( A0 , A1, CC ); + R0 = A0.w; + DBGA ( R0.L , 0x2001 ); + DBGA ( R0.H , 0x0000 ); + R0.L = A0.x; + DBGA ( R0.L , 0x0000 ); + + R0.L = 0x1000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + R0.L = 0x0fff; + R0.H = 0xffff; + A1.w = R0; + R0.L = 0x00ff; + A1.x = R0.L; + R0.L = 0x0000; + R0.H = 0x0000; + CC = R0; + A0 = BXORSHIFT( A0 , A1, CC ); + R0 = A0.w; + DBGA ( R0.L , 0x2000 ); + DBGA ( R0.H , 0x0000 ); + R0.L = A0.x; + DBGA ( R0.L , 0x0000 ); + + R0.L = 0x1000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + R0.L = 0xffff; + R0.H = 0xffff; + A1.w = R0; + R0.L = 0x00ff; + A1.x = R0.L; + R0.L = 0x0001; + R0.H = 0x0000; + CC = R0; + A0 = BXORSHIFT( A0 , A1, CC ); + R0 = A0.w; + DBGA ( R0.L , 0x2000 ); + DBGA ( R0.H , 0x0000 ); + R0.L = A0.x; + DBGA ( R0.L , 0x0000 ); + +// no + + R0.L = 0x1000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0.L; + R0.L = 0xffff; + R0.H = 0xffff; + A1.w = R0; + R0.L = 0x00ff; + A1.x = R0.L; + R0.L = 0x0000; + R0.H = 0x0000; + CC = R0; + R2.L = CC = BXOR( A0 , A1, CC ); + R0 = A0.w; + DBGA ( R0.L , 0x1000 ); + DBGA ( R0.H , 0x0000 ); + R0.L = A0.x; + DBGA ( R0.L , 0x0000 ); + DBGA ( R2.L , 0x0001 ); + R0 = CC; + DBGA ( R0.L , 0x0001 ); + + pass diff --git a/sim/testsuite/sim/bfin/s12.s b/sim/testsuite/sim/bfin/s12.s new file mode 100644 index 0000000..2f66798 --- /dev/null +++ b/sim/testsuite/sim/bfin/s12.s @@ -0,0 +1,84 @@ +// Shifter test program. +// Test instructions +// RL5 = EXPADJ R4 BY RL2; +# mach: bfin + +.include "testutils.inc" + start + + + R0.L = 30; // large norm of small value + R0.H = 1; // make sure high half is not used + R1.L = 0x0000; + R1.H = 0x1000; // small norm (2) of large value + R7.L = EXPADJ( R1 , R0.L ); + DBGA ( R7.L , 0x0002 ); + + R0.L = 3; // small norm of large value + R0.H = 1; // make sure high half is not used + R1.L = 0x0000; + R1.H = 0xff00; // small norm (2) of large value + R7.L = EXPADJ( R1 , R0.L ); + DBGA ( R7.L , 0x0003 ); + + R0.L = 3; + R0.H = 1; + R1.L = 0xffff; + R1.H = 0xffff; + R7.L = EXPADJ( R1 , R0.L ); + DBGA ( R7.L , 0x0003 ); + + R0.L = 31; + R0.H = 1; + R1.L = 0x0000; // norm=0 + R1.H = 0x8000; + R7.L = EXPADJ( R1 , R0.L ); + DBGA ( R7.L , 0x0000 ); + +// RL5 = EXPADJ/EXPADJ R4 BY RL2; + + R0.L = 15; + R1.L = 0x0800; + R1.H = 0x1000; + R7.L = EXPADJ( R1 , R0.L ) (V); + DBGA ( R7.L , 0x0002 ); + + R0.L = 15; + R1.L = 0x1000; + R1.H = 0x0800; + R7.L = EXPADJ( R1 , R0.L ) (V); + DBGA ( R7.L , 0x0002 ); + + R0.L = 1; + R1.L = 0x0800; + R1.H = 0x1000; + R7.L = EXPADJ( R1 , R0.L ) (V); + DBGA ( R7.L , 0x0001 ); + + R0.L = 14; + R1.L = 0xff00; + R1.H = 0xfff0; + R7.L = EXPADJ( R1 , R0.L ) (V); + DBGA ( R7.L , 0x0007 ); + +// RL5 = EXPADJ RL4 BY RL2; + + R0.L = 14; + R1.L = 0xff00; + R1.H = 0x1000; + R7.L = EXPADJ( R1.L , R0.L ); + DBGA ( R7.L , 0x0007 ); + + R0.L = 3; + R1.L = 0xff00; + R1.H = 0x1000; + R7.L = EXPADJ( R1.L , R0.L ); + DBGA ( R7.L , 0x0003 ); + + R0.L = 14; + R1.L = 0x1000; + R1.H = 0xff00; + R7.L = EXPADJ( R1.H , R0.L ); + DBGA ( R7.L , 0x0007 ); + + pass diff --git a/sim/testsuite/sim/bfin/s13.s b/sim/testsuite/sim/bfin/s13.s new file mode 100644 index 0000000..22b77b7 --- /dev/null +++ b/sim/testsuite/sim/bfin/s13.s @@ -0,0 +1,215 @@ +// Test rl3 = ashift (rh0 by r5; +// Test rl3 = lshift (rh0 by r5); +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + + R0 = 0; + ASTAT = R0; + R0.L = 0x1; + R0.H = 0x1; + R5.L = 4; + R7.L = ASHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x0010 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R0.L = 0x8000; + R0.H = 0x1; + R5.L = -4; + R5.H = 0; + R7.L = ASHIFT R0.L BY R5.L; + DBGA ( R7.L , 0xf800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R0.L = 0x0; + R0.H = 0x1; + R5.L = 0; + R5.H = 0; + R7.L = ASHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R5.L = -4; + R5.H = 0; + R7.H = ASHIFT R0.H BY R5.L; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0xf800 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R5.L = -4; + R5.H = 0; + R7.L = ASHIFT R0.H BY R5.L; + DBGA ( R7.L , 0xf800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0xffff; + R5.L = 31; // should accept mag of +31 + R5.H = 0; + R7.L = ASHIFT R0.H BY R5.L; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x0100; + R5.L = 63; // mag of 63 will appear as -1 since 6 bits are masked + R5.H = 0; + R7.L = ASHIFT R0.H BY R5.L; + DBGA ( R7.L , 0x0080 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic shifts + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R5.L = -4; + R5.H = 0; + R7.L = LSHIFT R0.H BY R5.L; + DBGA ( R7.L , 0x0800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x1; + R5.L = 4; + R5.H = 0; + R7.H = LSHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0010 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x0; + R0.H = 0x0; + R5.L = 0; + R5.H = 0; + R7.L = LSHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x1; + R0.H = 0x0; + R5.L = 15; + R5.H = 0; + R7.L = LSHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x0100; + R0.H = 0x0; + R5.L = 63; // mag of 63 will appear as -1 since 6 bits are masked + R5.H = 0; + R7.L = LSHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x0080 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x0100; + R0.H = 0x0; + R5.L = 31; // should accept mag of +31 + R5.H = 0; + R7.L = LSHIFT R0.L BY R5.L; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/sim/bfin/s14.s b/sim/testsuite/sim/bfin/s14.s new file mode 100644 index 0000000..99814ee --- /dev/null +++ b/sim/testsuite/sim/bfin/s14.s @@ -0,0 +1,350 @@ +// reg-based SHIFT test program. +// Test r4 = ASHIFT (r2 by rl3); +// Test r4 = LSHIFT (r2 by rl3); +# mach: bfin + +.include "testutils.inc" + start + + + R0.L = 0x0001; + R0.H = 0x8000; + +// arithmetic +// left by 31 +// 8000 0001 -> 8000 0000 + R7 = 0; + ASTAT = R7; + R3.L = 31; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 32 +// 8000 0001 -> 8000 0000 + R7 = 0; + ASTAT = R7; + R3.L = 32; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 40 +// 8000 0001 -> 8000 0000 + R7 = 0; + ASTAT = R7; + R3.L = 40; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0xFF80 ); + DBGA ( R6.H , 0xFFFF ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by -32 +// 8000 0001 -> 8000 0000 + R7 = 0; + ASTAT = R7; + R3.L = -32; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 63 (off scale) +// 8000 0001 -> 0000 0000 + R7 = 0; + ASTAT = R7; + R0.L = 1; + R0.H = 0; + R3.L = 63; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 255 looks like -1 (mask 7 bits) +// 8000 0001 -> 0000 0000 + R7 = 0; + ASTAT = R7; + R0.L = 0x0100; + R0.H = 0; + R3.L = 255; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0080 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 +// 8000 0001 -> 0000 0002 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = 1; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 1 +// 8000 0001 -> 0000 0002 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = -1; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xc000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by -31 +// 8000 0001 -> ffff ffff + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = -31; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// left by largest positive magnitude of 31 (0x1f) +// 8000 0001 -> 8000 0000 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = 31; + R3.H = 0; + R6 = ASHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// left by 1 +// 8000 0001 -> 0000 0002 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = 1; + R3.H = 0; + R6 = LSHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// right by 1 +// 8000 0001 -> 4000 0000 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = -1; + R3.H = 0; + R6 = LSHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0001 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = -31; + R3.H = 0; + R6 = LSHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// right by -32 +// 8000 0001 -> 0000 0001 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = -32; + R3.H = 0; + R6 = LSHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// by +40 +// 8000 0001 -> 0000 0001 + R0.L = 0x0001; + R0.H = 0x8000; + R3.L = 40; + R3.H = 0; + R6 = LSHIFT R0 BY R3.L; + DBGA ( R6.L , 0x0080 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// rot +// left by 1 +// 8000 0001 -> 0000 0002 cc=1 + R7 = 0; + CC = R7; + R6 = ROT R0 BY 1; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; DBGA ( R7.L , 0x0001 ); + +// rot +// right by -1 +// 8000 0001 -> 4000 0000 cc=1 + R7 = 0; + CC = R7; + R6 = ROT R0 BY -1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + R7 = CC; DBGA ( R7.L , 0x0001 ); + +// rot +// right by largest positive magnitude of 31 +// 8000 0001 -> a000 0000 cc=0 + R7 = 0; + CC = R7; + R6 = ROT R0 BY 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xa000 ); + R7 = CC; DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest positive magnitude of 31 with cc=1 +// 8000 0001 cc=1 -> a000 0000 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xe000 ); + R7 = CC; DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0005 cc=0 + R7 = 0; + CC = R7; + R6 = ROT R0 BY -31; + DBGA ( R6.L , 0x0005 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 with cc=1 +// 8000 0001 cc=1 -> 0000 0007 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY -31; + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; DBGA ( R7.L , 0x0000 ); + +// rot +// left by 7 +// 8000 0001 cc=1 -> 0000 00e0 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 7; + DBGA ( R6.L , 0x00e0 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; DBGA ( R7.L , 0x0000 ); + +// rot by zero +// 8000 0001 -> 8000 000 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 0; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x8000 ); + R7 = CC; DBGA ( R7.L , 0x0001 ); + +// 0 by 1 + R7 = 0; + R0 = 0; + ASTAT = R7; + R6 = R0 << 1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/sim/bfin/s15.s b/sim/testsuite/sim/bfin/s15.s new file mode 100644 index 0000000..9c32d48 --- /dev/null +++ b/sim/testsuite/sim/bfin/s15.s @@ -0,0 +1,149 @@ +// reg-based SHIFT test program. +# mach: bfin + +.include "testutils.inc" + start + + +// Test FEXT with no sign extension + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0810; // pos=8 len=16 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x34de ); + DBGA ( R7.H , 0 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0814; // pos=8 len=20 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x34de ); + DBGA ( R7.H , 0x0002 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0800; // pos=8 len=0 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x0001; // pos=0 len=1 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x1 ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x0101; // pos=1 len=1 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x1810; // pos=24 len=16 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x00ff ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x0020; // pos=0 len=32 is like pos=0 len=0 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x0 ); + DBGA ( R7.H , 0x0 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x2020; // pos=32 len=32 is like pos=0 len=0 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x1f01; // pos=31 len=1 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0x1 ); + DBGA ( R7.H , 0 ); + + R0.L = 0xfff1; + R0.H = 0xffff; + R1.L = 0x1000; // pos=16 len=0 + R7 = EXTRACT( R0, R1.L ) (Z); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + +// Test FEXT with sign extension + + R0.L = 0xdead; + R0.H = 0x12f4; + R1.L = 0x0810; // pos=8 len=16 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0xf4de ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0810; // pos=8 len=16 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0x34de ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xdead; + R0.H = 0xf234; + R1.L = 0x1f01; // pos=31 len=1 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdead; + R0.H = 0xf234; + R1.L = 0x1f02; // pos=31 len=2 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x101f; // pos=16 len=31 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x1001; // pos=16 len=1 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R1.L = 0x1000; // pos=16 len=0 + R7 = EXTRACT( R0, R1.L ) (X); + DBGA ( R7.L , 0 ); + DBGA ( R7.H , 0 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/sim/bfin/s16.s b/sim/testsuite/sim/bfin/s16.s new file mode 100644 index 0000000..6741cf3 --- /dev/null +++ b/sim/testsuite/sim/bfin/s16.s @@ -0,0 +1,170 @@ +// reg-based SHIFT test program. +# mach: bfin + +.include "testutils.inc" + start + + +// Test FDEP with no sign extension + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c08; // pos=12 len=8 + R1.H = 0x00ff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0x123f ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c04; // pos=12 len=4 + R1.H = 0x00ff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0x1234 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c05; // pos=12 len=5 + R1.H = 0x00ff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0x1235 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0010; // pos=0 len=16 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x1234 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0011; // pos=0 len=17 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x1234 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0114; // pos=1 len=20 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x1235 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x001f; // pos=0 len=31 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xffff ); + DBGA ( R7.H , 0x1234 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x1c04; // pos=28 len=4 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xdead ); + DBGA ( R7.H , 0xf234 ); + + R0.L = 0xdead; + R0.H = 0x0234; + R1.L = 0x1d04; // pos=29 len=4 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xdead ); + DBGA ( R7.H , 0xe234 ); + + R0.L = 0xdead; + R0.H = 0x0234; + R1.L = 0x1f04; // pos=31 len=4 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xdead ); + DBGA ( R7.H , 0x8234 ); + + R0.L = 0xdead; + R0.H = 0x0234; + R1.L = 0x2004; // pos=32 len=4, same as pos=0 len=4 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ); + DBGA ( R7.L , 0xdeaf ); + DBGA ( R7.H , 0x0234 ); + +// Test FDEP with sign extension + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c08; // pos=12 len=8 + R1.H = 0x00ff; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdead; + R0.H = 0x1234; + R1.L = 0x0c08; // pos=12 len=8 + R1.H = 0x007f; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0xfead ); + DBGA ( R7.H , 0x0007 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0110; // pos=1 len=16 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0101; // pos=1 len=1 + R1.H = 0xffff; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0102; // pos=1 len=2 + R1.H = 0x0001; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0x0002 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0002; // pos=0 len=2 + R1.H = 0x0001; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0xdea0; + R0.H = 0x1234; + R1.L = 0x0000; // pos=0 len=0 + R1.H = 0x000f; + R7 = DEPOSIT( R0, R1 ) (X); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/sim/bfin/s17.s b/sim/testsuite/sim/bfin/s17.s new file mode 100644 index 0000000..530a93b --- /dev/null +++ b/sim/testsuite/sim/bfin/s17.s @@ -0,0 +1,46 @@ +// shifter test program. +// Test instructions ONES +# mach: bfin + +.include "testutils.inc" + start + + + R7 = 0; + ASTAT = R7; + R0.L = 0x1; + R0.H = 0x0; + R7.L = ONES R0; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0.L = 0x0000; + R0.H = 0x8000; + R7.L = ONES R0; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + + R0.L = 0x0001; + R0.H = 0x8000; + R7.L = ONES R0; + DBGA ( R7.L , 0x0002 ); + DBGA ( R7.H , 0x0000 ); + + R0.L = 0xffff; + R0.H = 0xffff; + R7.L = ONES R0; + DBGA ( R7.L , 0x0020 ); + DBGA ( R7.H , 0x0000 ); + + R0.L = 0x0000; + R0.H = 0x0000; + R7.L = ONES R0; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + + pass diff --git a/sim/testsuite/sim/bfin/s18.s b/sim/testsuite/sim/bfin/s18.s new file mode 100644 index 0000000..6f26cc8 --- /dev/null +++ b/sim/testsuite/sim/bfin/s18.s @@ -0,0 +1,132 @@ +// Immediate dual 16b SHIFT test program. +// Test r4 = ASHIFT/ASHIFT (r2 by 10); +// Test r4 = ASHIFT/ASHIFT (r2 by 10) S; +// Test r4 = LSHIFT/LSHIFT (r2 by 10); +# mach: bfin + +.include "testutils.inc" + start + + +// arithmetic +// left by largest positive magnitude of 15 (0xf) +// 8001 -> 8000 + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R6 = R0 << 15 (V); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by largest positive magnitude of 15 (0xf) with saturation + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R6 = R0 << 15 (V , S); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R6 = R0 << 1 (V); + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0200 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 saturating + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R6 = R0 << 1 (V , S); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x0200 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 15 saturating + R7 = 0; + ASTAT = R7; + R0.L = 0xfff0; + R0.H = 0x0000; + R6 = R0 << 15 (V , S); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 15 + R7 = 0; + ASTAT = R7; + R0.L = 0x8000; + R0.H = 0x0100; + R6 = R0 >>> 15 (V); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 15 (sat has no effect) + R7 = 0; + ASTAT = R7; + R0.L = 0x8000; + R0.H = 0x0100; + R6 = R0 >>> 15 (V); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// right by 15 + R7 = 0; + ASTAT = R7; + R0.L = 0x8000; + R0.H = 0x0100; + R6 = R0 >> 15 (V); + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/sim/bfin/s19.s b/sim/testsuite/sim/bfin/s19.s new file mode 100644 index 0000000..8e37ca2 --- /dev/null +++ b/sim/testsuite/sim/bfin/s19.s @@ -0,0 +1,140 @@ +// REG-BASED dual 16b SHIFT test program. +// Test r4 = ASHIFT/ASHIFT (r2 by rl1); +// Test r4 = ASHIFT/ASHIFT (r2 by rl1) S; +// Test r4 = LSHIFT/LSHIFT (r2 by rl1); +# mach: bfin + +.include "testutils.inc" + start + + +// arithmetic +// left by largest positive magnitude of 15 (0xf) +// 8001 -> 8000 + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R1.L = 15; + R6 = ASHIFT R0 BY R1.L (V); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by largest positive magnitude of 15 (0xf) with saturation + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R1.L = 15; + R6 = ASHIFT R0 BY R1.L (V , S); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x7fff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R1.L = 1; + R6 = ASHIFT R0 BY R1.L (V); + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0200 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 saturating + R7 = 0; + ASTAT = R7; + R0.L = 0x8001; + R0.H = 0x0100; + R1.L = 1; + R6 = ASHIFT R0 BY R1.L (V , S); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x0200 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 15 saturating + R7 = 0; + ASTAT = R7; + R0.L = 0xfff0; + R0.H = 0x0000; + R1.L = 15; + R6 = ASHIFT R0 BY R1.L (V , S); + DBGA ( R6.L , 0x8000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 15 + R7 = 0; + ASTAT = R7; + R0.L = 0x8000; + R0.H = 0x0100; + R1.L = -15; + R6 = ASHIFT R0 BY R1.L (V); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 15 (sat has no effect) + R7 = 0; + ASTAT = R7; + R0.L = 0x8000; + R0.H = 0x0100; + R1.L = -15; + R6 = ASHIFT R0 BY R1.L (V , S); + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic +// right by 15 + R7 = 0; + ASTAT = R7; + R0.L = 0x8000; + R0.H = 0x0100; + R1.L = -15; + R6 = LSHIFT R0 BY R1.L (V); + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/sim/bfin/s2.s b/sim/testsuite/sim/bfin/s2.s new file mode 100644 index 0000000..4b8ab2d --- /dev/null +++ b/sim/testsuite/sim/bfin/s2.s @@ -0,0 +1,47 @@ +# mach: bfin + +.include "testutils.inc" + start + +// Test pc relative indirect branches. + P4 = 0; + loadsym P1 jtab; + +LL1: + P2 = P1 + ( P4 << 1 ); + R0 = W [ P2 ] (Z); + P0 = R0; + R2 = P4; + +jp: + JUMP ( PC + P0 ); + + DBGA ( R2.L , 0 ); + JUMP.L done; + + DBGA ( R2.L , 1 ); + JUMP.L done; + + DBGA ( R2.L , 2 ); + JUMP.L done; + + DBGA ( R2.L , 3 ); + JUMP.L done; + + DBGA ( R2.L , 4 ); + JUMP.L done; + +done: + P4 += 1; + CC = P4 < 4 (IU); + IF CC JUMP LL1; + pass + + .data + +jtab: + .dw 2; //.dw (2+0*8) + .dw 10; //.dw (2+1*8) + .dw 18; //.dw (2+2*8) + .dw 26; //.dw (2+3*8) + .dw 34; //.dw (2+4*8) diff --git a/sim/testsuite/sim/bfin/s20.s b/sim/testsuite/sim/bfin/s20.s new file mode 100644 index 0000000..7f97d22 --- /dev/null +++ b/sim/testsuite/sim/bfin/s20.s @@ -0,0 +1,25 @@ +// Test byte-align instructions +# mach: bfin + +.include "testutils.inc" + start + + + R0.L = 0xabcd; + R0.H = 0x1234; + R1.L = 0x4567; + R1.H = 0xdead; + + R2 = ALIGN8 ( R1 , R0 ); + DBGA ( R2.L , 0x34ab ); + DBGA ( R2.H , 0x6712 ); + + R2 = ALIGN16 ( R1 , R0 ); + DBGA ( R2.L , 0x1234 ); + DBGA ( R2.H , 0x4567 ); + + R2 = ALIGN24 ( R1 , R0 ); + DBGA ( R2.L , 0x6712 ); + DBGA ( R2.H , 0xad45 ); + + pass diff --git a/sim/testsuite/sim/bfin/s21.s b/sim/testsuite/sim/bfin/s21.s new file mode 100644 index 0000000..b528dd9 --- /dev/null +++ b/sim/testsuite/sim/bfin/s21.s @@ -0,0 +1,298 @@ +// Copyright (c) 1997,1998,1999 Analog Devices Inc., All Rights Reserved +// Test A0 = ROT (A0 by imm6); +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT = R0; + A0 = A1 = 0; + +// rot +// left by 1 +// 00 8000 0001 -> 01 0000 0002 cc=0 + R0.L = 0x0001; + R0.H = 0x8000; + R7 = 0; + CC = R7; + A1 = A0 = 0; + A0.w = R0; + A0 = ROT A0 BY 1; + R1 = A0.w; + DBGA ( R1.L , 0x0002 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0001 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by 1 +// 80 0000 0001 -> 00 0000 0002 cc=1 + R7 = 0; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 1; + R1 = A0.w; + DBGA ( R1.L , 0x0002 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// left by 1 with cc=1 +// 80 8000 0001 -> 01 0000 0003 cc=1 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x8000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 1; + R1 = A0.w; + DBGA ( R1.L , 0x0003 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0001 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// left by 2 with cc=1 +// 80 0000 0001 -> 00 0000 0007 cc=0 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 2; + R1 = A0.w; + DBGA ( R1.L , 0x0007 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by 3 with cc=0 + R7 = 0; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 3; + R1 = A0.w; + DBGA ( R1.L , 0x000a ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by largest positive magnitude of 31 +// 80 0000 0001 -> 00 a000 0000 cc=0 + R7 = 0; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY 31; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0xa000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by 1 +// 80 0000 0001 -> 40 0000 0000 cc=1 + R7 = 0; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY -1; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0040 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by 1 +// 80 0000 0001 -> c0 0000 0000 cc=1 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY -1; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0xffc0 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by 2 +// 80 0000 0001 -> e0 0000 0000 cc=0 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY -2; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0x0000 ); + R1.L = A0.x; + DBGA ( R1.L , 0xffe0 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by 9 +// 80 0000 0001 -> 01 c000 0000 cc=0 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + A0 = ROT A0 BY -9; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0xc000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0001 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by 9 with reg +// 80 0000 0001 -> 01 c000 0000 cc=0 + R7 = 1; + CC = R7; + R0.L = 0x0001; + R0.H = 0x0000; + R1.L = 0x0080; + A1 = A0 = 0; + A0.w = R0; + A0.x = R1.L; + R5 = -9; + A0 = ROT A0 BY R5.L; + R1 = A0.w; + DBGA ( R1.L , 0x0000 ); + DBGA ( R1.H , 0xc000 ); + R1.L = A0.x; + DBGA ( R1.L , 0x0001 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot left by 4 with cc=1 + R0.L = 0x789a; + R0.H = 0x3456; + A0.w = R0; + R0.L = 0x12; + A0.x = R0; + + R0 = 1; + CC = R0; + + A0 = ROT A0 BY 4; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x4567 ); DBGA ( R4.L , 0x89a8 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0023 ); + +// rot left by 28 with cc=1 + R0.L = 0x789a; + R0.H = 0x3456; + A0.w = R0; + R0.L = 0x12; + A0.x = R0; + + R0 = 1; + CC = R0; + + A0 = ROT A0 BY 28; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xa891 ); DBGA ( R4.L , 0xa2b3 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff89 ); + +// rot right by 4 with cc=1 + R0.L = 0x789a; + R0.H = 0x3456; + A0.w = R0; + R0.L = 0x12; + A0.x = R0; + + R0 = 1; + CC = R0; + + A0 = ROT A0 BY -4; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x2345 ); DBGA ( R4.L , 0x6789 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0051 ); + +// rot right by 8 with cc=1 + R0.L = 0x789a; + R0.H = 0x3456; + A0.w = R0; + R0.L = 0x12; + A0.x = R0; + + R0 = 1; + CC = R0; + + A0 = ROT A0 BY -28; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0xcf13 ); DBGA ( R4.L , 0x5123 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff8a ); + + pass diff --git a/sim/testsuite/sim/bfin/s3.s b/sim/testsuite/sim/bfin/s3.s new file mode 100644 index 0000000..d3178a4 --- /dev/null +++ b/sim/testsuite/sim/bfin/s3.s @@ -0,0 +1,88 @@ +// SHIFT test program. +// Test A0 = ASHIFT (A0 by r3); +# mach: bfin + +.include "testutils.inc" + start + +// load r0=0x0000001f +// load r1=0x00000020 +// load r2=0x00000000 +// load r3=0x00000000 +// load r4=0x00000001 +// load r5=0x00000080 + loadsym P0, data0; + P1 = P0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + +// left by largest positive magnitude of 31 (0x1f) +// A0: 80 0000 0001 -> 80 0000 0000 + R7 = 0; + ASTAT = R7; + A0.w = R4; + A0.x = R5.L; + A0 = ASHIFT A0 BY R0.L; + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + DBGA ( R7.L , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// left by largest positive magnitude + 1 = 32 (0x20), which is -32 +// A0: 80 0000 0001 -> + R7 = 0; + ASTAT = R7; + A0.w = R4; + A0.x = R5.L; + A0 = ASHIFT A0 BY R1.L; + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0xff80 ); + DBGA ( R6.H , 0xffff ); + DBGA ( R7.L , 0xffff ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// by -1 +// A0: 80 0000 0001 -> c0 0000 0000 + A0.w = R4; + A0.x = R5.L; + + R3.L = 0x00ff; + + A0 = ASHIFT A0 BY R3.L; + R6 = A0.w; + R7.L = A0.x; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xffc0 ); + + pass + + .data +data0: + .dw 0x001f + .dw 0x0000 + .dw 0x0020 + .dw 0x0000 + .dw 0x0059 + .dw 0x0000 + .dw 0x005a + .dw 0x0000 + .dw 0x0001 + .dw 0x0000 + .dw 0x0080 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/s30.s b/sim/testsuite/sim/bfin/s30.s new file mode 100644 index 0000000..4ec6ef4 --- /dev/null +++ b/sim/testsuite/sim/bfin/s30.s @@ -0,0 +1,152 @@ +// Test signbits40 +# mach: bfin + +.include "testutils.inc" + start + + +// positive value in accum, smaller than 1.0 + A1 = A0 = 0; + R0.L = 0xffff; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0x8000 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); + +// neg value in accum, larger than -1.0 + A1 = A0 = 0; + R0.L = 0x0000; + R0.H = 0xffff; + A0.w = R0; + R0.L = 0x00ff; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); + +// positive value in accum, larger than 1.0 + A1 = A0 = 0; + R0.L = 0xffff; + R0.H = 0xffff; + A0.w = R0; + R0.L = 0x000f; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0xffff ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); + +// negative value in accum, smaller than -1.0 + A1 = A0 = 0; + R0.L = 0x0000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x0080; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); + +// no normalization + A1 = A0 = 0; + R0.L = 0xfffa; + R0.H = 0x7fff; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0xfffa ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); + +// no normalization (-1.0) + A1 = A0 = 0; + R0.L = 0x0000; + R0.H = 0x8000; + A0.w = R0; + R0.L = 0x00ff; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); + +// norm by 1 + A1 = A0 = 0; + R0.L = 0x0000; + R0.H = 0x8000; + A0.w = R0; + R0.L = 0x0000; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x4000 ); DBGA ( R4.L , 0x0000 ); + DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 ); + +// norm by 1 + A1 = A0 = 0; + R0.L = 0x0000; + R0.H = 0x0000; + A0.w = R0; + R0.L = 0x00ff; + A0.x = R0; + + R5.L = SIGNBITS A0; + _DBG R5; + A0 = ASHIFT A0 BY R5.L; + _DBG A0; + + R4 = A0.w; + R5 = A0.x; + DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 ); + DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff ); + + pass diff --git a/sim/testsuite/sim/bfin/s4.s b/sim/testsuite/sim/bfin/s4.s new file mode 100644 index 0000000..784c57d --- /dev/null +++ b/sim/testsuite/sim/bfin/s4.s @@ -0,0 +1,214 @@ +// Immediate SHIFT test program. +// Test r4 = ASHIFT (r2 by 10); +// Test r4 = LSHIFT (r2 by 10); +// Test r4 = ROT (r2 by 10); +# mach: bfin + +.include "testutils.inc" + start + + + init_r_regs 0; + ASTAT = R0; + +// load r0=0x80000001 +// load r1=0x00000000 +// load r2=0x00000000 +// load r3=0x00000000 +// load r4=0x00000000 +// load r5=0x00000000 + loadsym P0, data0; + R0 = [ P0 ++ ]; + R1 = [ P0 ++ ]; + R2 = [ P0 ++ ]; + R3 = [ P0 ++ ]; + R4 = [ P0 ++ ]; + R5 = [ P0 ++ ]; + +// arithmetic +// left by largest positive magnitude of 31 (0x1f) +// 8000 0001 -> 8000 0000 + R7 = 0; + ASTAT = R7; + R6 = R0 << 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// left by 1 +// 8000 0001 -> 0000 0002 + R6 = R0 << 1; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by 1 +// 8000 0001 -> c000 0000 + R7 = 0; + ASTAT = R7; + R6 = R0 >>> 1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xc000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// arithmetic +// right by largest negative magnitude of -31 +// 8000 0001 -> ffff ffff + R6 = R0 >>> 31; + DBGA ( R6.L , 0xffff ); + DBGA ( R6.H , 0xffff ); + +// logic +// left by largest positive magnitude of 31 (0x1f) +// 8000 0001 -> 8000 0000 + R6 = R0 << 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x8000 ); + +// logic +// left by 1 +// 8000 0001 -> 0000 0002 + R6 = R0 << 1; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + +// logic +// right by 1 +// 8000 0001 -> 4000 0000 + R6 = R0 >> 1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + +// logic +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0001 + R6 = R0 >> 31; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x0000 ); + +// rot +// left by 1 +// 8000 0001 -> 0000 0002 cc=1 + R7 = 0; + CC = R7; + R6 = ROT R0 BY 1; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by -1 +// 8000 0001 -> 4000 0000 cc=1 + R7 = 0; + CC = R7; + R6 = ROT R0 BY -1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by largest positive magnitude of 31 +// 8000 0001 -> a000 0000 cc=0 + R7 = 0; + CC = R7; + R6 = ROT R0 BY 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xa000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest positive magnitude of 31 with cc=1 +// 8000 0001 cc=1 -> a000 0000 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 31; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xe000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0005 cc=0 + R7 = 0; + CC = R7; + R6 = ROT R0 BY -31; + DBGA ( R6.L , 0x0005 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 with cc=1 +// 8000 0001 cc=1 -> 0000 0007 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY -31; + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by 7 +// 8000 0001 cc=1 -> 0000 00e0 cc=0 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 7; + DBGA ( R6.L , 0x00e0 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot by zero +// 8000 0001 -> 8000 000 + R7 = 1; + CC = R7; + R6 = ROT R0 BY 0; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x8000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// 0 by 1 + R7 = 0; + R0 = 0; + ASTAT = R7; + R6 = R0 << 1; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass + + .data +data0: + .dw 0x0001 + .dw 0x8000 + .dd 0x0000 + .dd 0x0 + .dd 0x0 + .dd 0x0 + .dd 0x0 + .dd 0x0 diff --git a/sim/testsuite/sim/bfin/s5.s b/sim/testsuite/sim/bfin/s5.s new file mode 100644 index 0000000..7f38cd4 --- /dev/null +++ b/sim/testsuite/sim/bfin/s5.s @@ -0,0 +1,118 @@ +// Test r4 = ROT (r2 by r3); +# mach: bfin + +.include "testutils.inc" + start + + + R0.L = 0x0001; + R0.H = 0x8000; + +// rot +// left by 1 +// 8000 0001 -> 0000 0002 cc=1 + R7 = 0; + CC = R7; + R1 = 1; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by -1 +// 8000 0001 -> 4000 0000 cc=1 + R7 = 0; + CC = R7; + R1.L = 0xffff; // check alternate mechanism for immediates + R1.H = 0xffff; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x4000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot +// right by largest positive magnitude of 31 +// 8000 0001 -> a000 0000 cc=0 + R7 = 0; + CC = R7; + R1 = 31; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xa000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest positive magnitude of 31 with cc=1 +// 8000 0001 cc=1 -> a000 0000 cc=0 + R7 = 1; + CC = R7; + R1 = 31; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0xe000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 +// 8000 0001 -> 0000 0005 cc=0 + R7 = 0; + CC = R7; + R1 = -31; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0005 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// right by largest negative magnitude of -31 with cc=1 +// 8000 0001 cc=1 -> 0000 0007 cc=0 + R7 = 1; + CC = R7; + R1 = -31; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot +// left by 7 +// 8000 0001 cc=1 -> 0000 00e0 cc=0 + R7 = 1; + CC = R7; + R1 = 7; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x00e0 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0000 ); + +// rot by zero +// 8000 0001 -> 8000 0000 + R7 = 1; + CC = R7; + R1 = 0; + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0001 ); + DBGA ( R6.H , 0x8000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + +// rot by 0b1100 0001 is the same as by 1 (mask 6 bits) +// 8000 0001 -> 0000 0002 cc=1 + R7 = 0; + CC = R7; + R1 = 0xc1 (X); + R6 = ROT R0 BY R1.L; + DBGA ( R6.L , 0x0002 ); + DBGA ( R6.H , 0x0000 ); + R7 = CC; + DBGA ( R7.L , 0x0001 ); + + pass diff --git a/sim/testsuite/sim/bfin/s6.s b/sim/testsuite/sim/bfin/s6.s new file mode 100644 index 0000000..6fc9a2b --- /dev/null +++ b/sim/testsuite/sim/bfin/s6.s @@ -0,0 +1,83 @@ +// Test r4 = VMAX/VMAX (r5,r1) A0<<2; +# mach: bfin + +.include "testutils.inc" + start + + +// Both max values are in high half, hence both bits +// into A0 are 1 + A0 = 0; + R1.L = 0x2; // max in r1 is 3 + R1.H = 0x3; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASL); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0003 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// max value in r1 is in low, so second bit into A0 is zero + A0 = 0; + R1.L = 0x3; // max in r1 is 3 + R1.H = 0x2; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASL); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0002 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// both max values in low, so both bits into A0 are zero + R0.L = 0x8000; + R0.H = 0x0; + A0.w = R0; + R1.L = 0x3; // max in r1 is 3 + R1.H = 0x2; + + R0.L = 0x7; // max in r0 is 7 + R0.H = 0x6; + + R6 = VIT_MAX( R1 , R0 ) (ASL); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0002 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// Test for correct max when one value overflows + A0 = 0; + R1.L = 0x7fff; // max in r1 is 0x8001 (overflowed) + R1.H = 0x8001; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASL); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x8001 ); + R7 = A0.w; + DBGA ( R7.L , 0x0003 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + + pass diff --git a/sim/testsuite/sim/bfin/s7.s b/sim/testsuite/sim/bfin/s7.s new file mode 100644 index 0000000..0cda60e --- /dev/null +++ b/sim/testsuite/sim/bfin/s7.s @@ -0,0 +1,83 @@ +// Test r4 = VMAX/VMAX (r5,r1) A0>>2; +# mach: bfin + +.include "testutils.inc" + start + + +// Both max values are in high half, hence both bits +// into A0 are 1 + A0 = 0; + R1.L = 0x2; // max in r1 is 3 + R1.H = 0x3; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASR); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0xc000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// max value in r1 is in low, so second bit into A0 is zero + A0 = 0; + R1.L = 0x3; // max in r1 is 3 + R1.H = 0x2; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASR); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x4000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// both max values in low, so both bits into A0 are zero + R0.L = 0x8000; + R0.H = 0x0; + A0.w = R0; + R1.L = 0x3; // max in r1 is 3 + R1.H = 0x2; + + R0.L = 0x7; // max in r0 is 7 + R0.H = 0x6; + + R6 = VIT_MAX( R1 , R0 ) (ASR); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x2000 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// Test for correct max when one value overflows + A0 = 0; + R1.L = 0x7fff; // max in r1 is 0x8001 (overflowed) + R1.H = 0x8001; + + R0.L = 0x6; // max in r0 is 7 + R0.H = 0x7; + + R6 = VIT_MAX( R1 , R0 ) (ASR); + + DBGA ( R6.L , 0x0007 ); + DBGA ( R6.H , 0x8001 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0xc000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + + pass diff --git a/sim/testsuite/sim/bfin/s8.s b/sim/testsuite/sim/bfin/s8.s new file mode 100644 index 0000000..46d156e --- /dev/null +++ b/sim/testsuite/sim/bfin/s8.s @@ -0,0 +1,55 @@ +// Test rl4 = VMAX r5 A0<<1; +// Test rl4 = VMAX r5 A0>>1; +# mach: bfin + +.include "testutils.inc" + start + + +// max value in high half, hence bit into A0 is one + A0 = 0; + R1.L = 0x2; // max in r1 is 3 + R1.H = 0x3; + + R6.L = VIT_MAX( R1 ) (ASL); + + DBGA ( R6.L , 0x0003 ); + R7 = A0.w; + DBGA ( R7.L , 0x0001 ); + DBGA ( R7.H , 0x0000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + +// max value in low half, hence bit into A0 is zero + R0.L = 0x8000; + R0.H = 0x8000; + A0.w = R0; + R1.L = 0x8001; // max in r1 is 8001 + R1.H = 0x7f00; + + R6.L = VIT_MAX( R1 ) (ASL); + + DBGA ( R6.L , 0x8001 ); + R7 = A0.w; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0001 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0001 ); + +// max value in high half, hence bit into A0 is one + R0.L = 0x8000; + R0.H = 0x0000; + A0.w = R0; + R1.L = 0x7fff; // max in r1 is 8001 + R1.H = 0x8001; + + R6.L = VIT_MAX( R1 ) (ASR); + + DBGA ( R6.L , 0x8001 ); + R7 = A0.w; + DBGA ( R7.L , 0x4000 ); + DBGA ( R7.H , 0x8000 ); + R7.L = A0.x; + DBGA ( R7.L , 0x0000 ); + + pass diff --git a/sim/testsuite/sim/bfin/s9.s b/sim/testsuite/sim/bfin/s9.s new file mode 100644 index 0000000..7293e3a --- /dev/null +++ b/sim/testsuite/sim/bfin/s9.s @@ -0,0 +1,134 @@ +// Test rl3 = ashift (rh0 by 7); +// Test rl3 = lshift (rh0 by 7); +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + + R0 = 0; + ASTAT = R0; + R0.L = 0x1; + R0.H = 0x1; + R7.L = R0.L << 4; + DBGA ( R7.L , 0x0010 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R0.L = 0x8000; + R0.H = 0x1; + R7.L = R0.L >>> 4; + DBGA ( R7.L , 0xf800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R0.L = 0x0; + R0.H = 0x1; + R7.L = R0.L << 0; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R7.H = R0.H >>> 4; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0xf800 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R7.L = R0.H >>> 4; + DBGA ( R7.L , 0xf800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + +// logic shifts + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x8000; + R7.L = R0.H >> 4; + DBGA ( R7.L , 0x0800 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 0; + R0.L = 0x1; + R0.H = 0x1; + R7.H = R0.L << 4; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0010 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x0; + R0.H = 0x0; + R7.L = R0.L << 0; + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + R0 = 0; + ASTAT = R0; + R7 = 1; + R0.L = 0x1; + R0.H = 0x0; + R7.L = R0.L << 15; + DBGA ( R7.L , 0x8000 ); + DBGA ( R7.H , 0x0000 ); + CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); + CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); + CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); + + pass diff --git a/sim/testsuite/sim/bfin/saatest.s b/sim/testsuite/sim/bfin/saatest.s new file mode 100644 index 0000000..3957627 --- /dev/null +++ b/sim/testsuite/sim/bfin/saatest.s @@ -0,0 +1,222 @@ +# mach: bfin + +.include "testutils.inc" + start + + + I0 = 0 (X); + I1 = 0 (X); + A0 = A1 = 0; + init_r_regs 0; + ASTAT = R0; + +// This section of code will test the SAA instructions and sum of accumulators; + + loadsym I0, tstvecI; + + R0 = [ I0 ++ ]; + R2 = [ I0 ++ ]; + +// +++++++++++++++ TG11.001 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 15 15 15 15 // +// r1 ==> 0 0 0 0 // +// // +// Output:r2 ==> 0 0 0 30 // +// r3 ==> 0 0 0 30 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + SAA ( R1:0 , R3:2 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x001e ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x001e ); + DBGA ( R7.H , 0x0000 ); + + A1 = A0 = 0; + +// +++++++++++++++ TG11.002 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 15 15 15 15 // +// r1 ==> 0 0 0 0 // +// // +// Output:r2 ==> 0 0 0 30 // +// r3 ==> 0 0 0 30 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + SAA ( R1:0 , R3:2 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x001e ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x001e ); + DBGA ( R7.H , 0x0000 ); + + A1 = A0 = 0; + +// +++++++++++++++ TG11.003 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 240 240 240 240 // +// r1 ==> 0 0 0 0 // +// // +// Output:r2 ==> 0 480 // +// r3 ==> 0 480 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + R0 = [ I0 ++ ]; + R2 = [ I0 ++ ]; + + SAA ( R3:2 , R1:0 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x01e0 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x01e0 ); + DBGA ( R7.H , 0x0000 ); + + A1 = A0 = 0; + +// +++++++++++++++ TG11.004 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 240 240 240 240 // +// r1 ==> 0 0 0 0 // +// // +// Output:r2 ==> 0 480 // +// r3 ==> 0 480 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + SAA ( R1:0 , R3:2 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x01e0 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x01e0 ); + DBGA ( R7.H , 0x0000 ); + + A1 = A0 = 0; +// +++++++++++++++ TG11.005 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 0 0 0 0 // +// r1 ==> 0 0 0 0 // +// // +// Output:r2 ==> 0 0 // +// r3 ==> 0 0 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + R0 = [ I0 ++ ]; + R2 = [ I0 ++ ]; + + SAA ( R1:0 , R3:2 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + +// +++++++++++++++ TG11.006 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 255 255 255 255 // +// r1 ==> 255 255 255 255 // +// // +// Output:r2 ==> 0 0 // +// r3 ==> 0 0 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + SAA ( R3:2 , R1:0 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x0000 ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0x0000 ); + DBGA ( R7.H , 0x0000 ); + + A1 = A0 = 0; + +// +++++++++++++++ TG12.001 +++++++++++++ // +// // +// HH HL LH LL // +// Input: r0 ==> 255 255 255 255 // +// r1 ==> 255 255 255 255 // +// // +// Output:r2 ==> 0 0 // +// r3 ==> 0 0 // +// ++++++++++++++++++++++++++++++++++++++++++ // + + loadsym I0, tstvecK; + B0 = I0; + L0.L = 4; + loadsym I1, tstvecJ; + B1 = I1; + L1.L = 4; + + P0 = 64 (X); + R0 = [ I0 ++ ]; + R2 = [ I1 ++ ]; + LSETUP ( l$1 , l$1 ) LC0 = P0; +l$1: + SAA ( R1:0 , R3:2 ) || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; + + R2 = A1.L + A1.H, R3 = A0.L + A0.H; + R7 = R2 + R3 (NS); + DBGA ( R7.L , 0xff00 ); + DBGA ( R7.H , 0x0000 ); + + R5.L = 0xfffa; + A1 = R5; + R5.H = 0xfff0; + A0 = R5; + + loadsym I0, tstvecI; + R0 = [ I0 ++ ]; + R2 = [ I0 ++ ]; + SAA ( R1:0 , R3:2 ); + R6 = A1.L + A1.H, R7 = A0.L + A0.H; + DBGA ( R6.L , 0x000e ); + DBGA ( R6.H , 0x0000 ); + DBGA ( R7.L , 0xfffe ); + DBGA ( R7.H , 0xffff ); + + pass + + .data +tstvecI: + .dw 0x0000 + .dw 0x0000 + .dw 0x0f0f + .dw 0x0f0f + .dw 0x0000 + .dw 0x0000 + .dw 0xf0f0 + .dw 0xf0f0 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0xffff + .dw 0xffff + .dw 0xffff + .dw 0xffff + + .data +tstvecJ: + .dw 0xffff + .dw 0xffff + .dw 0xffff + .dw 0xffff + .dw 0xffff + .dw 0xffff + .dw 0xffff + .dw 0xffff + + .data +tstvecK: + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 + .dw 0x0000 diff --git a/sim/testsuite/sim/bfin/se_all16bitopcodes.S b/sim/testsuite/sim/bfin/se_all16bitopcodes.S new file mode 100644 index 0000000..a87d287 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_all16bitopcodes.S @@ -0,0 +1,444 @@ +/* + * Blackfin testcase for testing illegal/legal 16-bit opcodes from userspace + * we track all instructions which cause some sort of exception when run from + * userspace, this is normally EXCAUSE : + * - 0x21 : illegal instruction + * - 0x22 : illegal instruction combination + * - 0x2e : use of supervisor resource from userspace + * and walk every instruction from 0x0000 to 0xbfff + */ + +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + /* Set up exception handler */ + imm32 P4, EVT3; + loadsym R1, _evx; + [P4] = R1; + + /* set up the _location */ + loadsym P0, _location + loadsym P1, _table; + [P0] = P1; + + /* Enable single stepping */ + R0 = 1; + SYSCFG = R0; + + /* Lower to the code we want to single step through */ + loadsym R1, _usr; + RETI = R1; + + /* set up pointers to valid data (32Meg), to reduce address violations */ + init_p_regs 0x2000000; + init_i_regs 0x2000000; + init_b_regs 0x2000000; + init_l_regs 0; + imm32 fp, 0x2000000; + usp = p0; + + RTI; + + .align 4; +_usr: + .dd 0x0000; + jump fail_lvl; + +_evx: + /* Make sure exception reason is single step */ + R3 = SEQSTAT; + R4 = 0x3f; + R3 = R3 & R4; + + /* find a match */ + loadsym P0, _usr; + loadsym P2, _location; + P1 = [P2]; + R0 = W[P0]; + +_match: + R7 = W[P1++]; + R6 = W[P1++]; + R5 = W[P1++]; + + /* is this the end of the table? */ + R4 = 0; + CC = R4 == R7; + IF CC jump _legal_instruction; + + /* is the opcode (R0) greater than the 2nd entry in the table (R6) */ + /* if so look at the next line in the table */ + CC = R6 < R0; + if CC jump _match; + + /* is the opcode (R0) smaller than the first entry in the table (R7) */ + /* this means it's somewhere between the two lines, and should be legal */ + CC = R7 <= R0; + if !CC jump _legal_instruction; + + /* is the current EXCAUSE (R3), the same as the table (R5) */ + /* if not, fail */ + CC = R3 == R5 + if !CC jump fail_lvl; + +_match_done: + /* back up, and store the location to search next */ + R0 = P1; + /* 3 back, * word/byte) */ + R0 += (-3 * 2); + [P2] = R0; + + /* it matches, so fall through */ + jump _next_instruction; + +_legal_instruction: + R4 = 0x10; + CC = R3 == R4; + IF !CC JUMP fail_lvl; + /* it wasn't in the list, and was a single step, so fall through */ + +_next_instruction: + /* increment, and go again. */ + loadsym P0, _usr; + R0 = W[P0]; + R0 += 1; + W[P0] = R0; + R1 = 0xC000 (Z); + CC = R1 == R0; + IF CC JUMP pass_lvl; + + /* Make sure the opcode isn't in a write buffer */ + SSYNC; + + loadsym R1, _usr + RETX = R1; + + /* set up pointers to valid data (32Meg), to reduce address violations */ + init_p_regs 0x2000000; + init_i_regs 0x2000000; + init_b_regs 0x2000000; + init_l_regs 0; + imm32 fp, 0x2000000; + usp = p0; + RETS = p0; + RETN = p0; + RETE = p0; + RETI = p0; + RTX; + +pass_lvl: + dbg_pass; +fail_lvl: + dbg_fail; + + + /* this table must be sorted, and end with zero */ + .data + .align 4; +_location: + .dd 0 +_table: + /* start end SEQSTAT */ + .dw 0x0001, 0x000f, 0x21 + .dw 0x0011, 0x0013, 0x2e +.ifndef BFIN_JTAG + .dw 0x0014, 0x0014, 0x2e /* anomaly - RTX works when emulator attached */ +.endif + .dw 0x0015, 0x001F, 0x21 + .dw 0x0021, 0x0022, 0x21 + .dw 0x0026, 0x0026, 0x21 +.ifndef BFIN_JTAG + .dw 0x0027, 0x0027, 0x21 /* anomaly 492 - unknown */ +.endif + .dw 0x0028, 0x002F, 0x21 + .dw 0x0030, 0x0037, 0x2e + .dw 0x0038, 0x003F, 0x21 + .dw 0x0040, 0x0047, 0x2e + .dw 0x0048, 0x004F, 0x21 + .dw 0x0058, 0x005F, 0x21 + .dw 0x0068, 0x006F, 0x21 + .dw 0x0078, 0x007F, 0x21 + .dw 0x0088, 0x008F, 0x21 + .dw 0x0090, 0x009F, 0x2E + .dw 0x00a0, 0x00a0, 0x00 + .dw 0x00a1, 0x00a1, 0x01 + .dw 0x00a2, 0x00a2, 0x02 + .dw 0x00a3, 0x00a3, 0x03 + .dw 0x00a4, 0x00a4, 0x04 + .dw 0x00a5, 0x00a5, 0x05 + .dw 0x00a6, 0x00a6, 0x06 + .dw 0x00a7, 0x00a7, 0x07 + .dw 0x00a8, 0x00a8, 0x08 + .dw 0x00a9, 0x00a9, 0x09 + .dw 0x00aa, 0x00aa, 0x0a + .dw 0x00ab, 0x00ab, 0x0b + .dw 0x00ac, 0x00ac, 0x0c + .dw 0x00ad, 0x00ad, 0x0d + .dw 0x00ae, 0x00ae, 0x0e + .dw 0x00af, 0x00af, 0x0f + .dw 0x00b6, 0x010f, 0x21 + .dw 0x0124, 0x0124, 0x21 +.ifndef BFIN_JTAG + .dw 0x0125, 0x0125, 0x21 /* anomaly 492 res = [SP++] */ +.endif + .dw 0x0128, 0x012F, 0x21 + .dw 0x0138, 0x0138, 0x22 + .dw 0x0139, 0x013F, 0x2E + .dw 0x0164, 0x0164, 0x21 +.ifndef BFIN_JTAG + .dw 0x0165, 0x0165, 0x21 /* anomaly 492 [--SP] = res */ +.endif + .dw 0x0168, 0x016F, 0x21 + .dw 0x0178, 0x017F, 0x2E + .dw 0x0180, 0x01FF, 0x21 + .dw 0x0210, 0x0217, 0x21 +.ifndef BFIN_JTAG + .dw 0x0219, 0x021F, 0x21 /* anomaly 492 CC = !CC opcode is 0000 0010 0001 1xxx */ +.endif + .dw 0x0220, 0x023F, 0x21 + .dw 0x0280, 0x02FF, 0x21 + .dw 0x0305, 0x0305, 0x21 + .dw 0x0325, 0x0325, 0x21 + .dw 0x0345, 0x0345, 0x21 + .dw 0x0365, 0x0365, 0x21 + .dw 0x0385, 0x0385, 0x21 + .dw 0x03a5, 0x03a5, 0x21 + .dw 0x03c5, 0x03c5, 0x21 + .dw 0x03e5, 0x03e5, 0x21 + .dw 0x0400, 0x047F, 0x21 + .dw 0x0486, 0x04Bf, 0x21 + .dw 0x04c6, 0x04FF, 0x21 + .dw 0x0501, 0x0507, 0x21 + .dw 0x0509, 0x050F, 0x21 + .dw 0x0511, 0x0517, 0x21 + .dw 0x0519, 0x051F, 0x21 + .dw 0x0521, 0x0527, 0x21 + .dw 0x0529, 0x052F, 0x21 + .dw 0x0531, 0x0537, 0x21 + .dw 0x0539, 0x053F, 0x21 + .dw 0x0541, 0x0547, 0x21 + .dw 0x0549, 0x054F, 0x21 + .dw 0x0551, 0x0557, 0x21 + .dw 0x0559, 0x055F, 0x21 + .dw 0x0561, 0x0567, 0x21 + .dw 0x0569, 0x056F, 0x21 + .dw 0x0571, 0x0577, 0x21 + .dw 0x0579, 0x057F, 0x21 + .dw 0x0586, 0x0587, 0x21 + .dw 0x058e, 0x058F, 0x21 + .dw 0x0596, 0x0597, 0x21 + .dw 0x059e, 0x059f, 0x21 + .dw 0x05a6, 0x05a7, 0x21 + .dw 0x05ae, 0x05af, 0x21 + .dw 0x05b6, 0x05b7, 0x21 + .dw 0x05be, 0x05bf, 0x21 + .dw 0x05c6, 0x05c7, 0x21 + .dw 0x05ce, 0x05cf, 0x21 + .dw 0x05d6, 0x05d7, 0x21 + .dw 0x05de, 0x05df, 0x21 + .dw 0x05e6, 0x05e7, 0x21 + .dw 0x05ee, 0x05ef, 0x21 + .dw 0x05f6, 0x05f7, 0x21 + .dw 0x05fe, 0x05ff, 0x21 + .dw 0x0a81, 0x0aff, 0x21 + .dw 0x0b01, 0x0b7f, 0x21 + .dw 0x0b81, 0x0bff, 0x21 + .dw 0x0e80, 0x0fff, 0x21 + .dw 0x3104, 0x3105, 0x21 + .dw 0x310c, 0x310d, 0x21 + .dw 0x3114, 0x3115, 0x21 + .dw 0x311c, 0x311d, 0x21 + .dw 0x3124, 0x3125, 0x21 + .dw 0x312c, 0x312d, 0x21 + .dw 0x3134, 0x3135, 0x21 + .dw 0x313c, 0x313d, 0x21 + .dw 0x3140, 0x317F, 0x21 + .dw 0x31c0, 0x31ff, 0x2E + .dw 0x3304, 0x3305, 0x21 + .dw 0x330c, 0x330d, 0x21 + .dw 0x3314, 0x3315, 0x21 + .dw 0x331c, 0x331d, 0x21 + .dw 0x3324, 0x3325, 0x21 + .dw 0x332c, 0x332d, 0x21 + .dw 0x3334, 0x3335, 0x21 + .dw 0x333c, 0x333d, 0x21 + .dw 0x3340, 0x337f, 0x21 + .dw 0x33c0, 0x33ff, 0x2e + .dw 0x3504, 0x3507, 0x21 + .dw 0x350c, 0x350F, 0x21 + .dw 0x3514, 0x3517, 0x21 + .dw 0x351c, 0x351F, 0x21 + .dw 0x3524, 0x3527, 0x21 + .dw 0x352c, 0x352f, 0x21 + .dw 0x3534, 0x3537, 0x21 + .dw 0x353c, 0x353f, 0x21 + .dw 0x3540, 0x35c6, 0x21 + .dw 0x35c7, 0x35c7, 0x2e + .dw 0x35c8, 0x35ce, 0x21 + .dw 0x35cf, 0x35cf, 0x2e + .dw 0x35d0, 0x35d6, 0x21 + .dw 0x35d7, 0x35d7, 0x2e + .dw 0x35d8, 0x35de, 0x21 + .dw 0x35df, 0x35df, 0x2e + .dw 0x35e0, 0x35e6, 0x21 + .dw 0x35e7, 0x35e7, 0x2e + .dw 0x35e8, 0x35ee, 0x21 + .dw 0x35ef, 0x35ef, 0x2e + .dw 0x35f0, 0x35f6, 0x21 + .dw 0x35f7, 0x35f7, 0x2e + .dw 0x35f8, 0x35fe, 0x21 + .dw 0x35ff, 0x35ff, 0x2e + .dw 0x3704, 0x3707, 0x21 + .dw 0x370c, 0x370f, 0x21 + .dw 0x3714, 0x3717, 0x21 + .dw 0x371c, 0x371f, 0x21 + .dw 0x3724, 0x3727, 0x21 + .dw 0x372c, 0x372f, 0x21 + .dw 0x3734, 0x3737, 0x21 + .dw 0x373c, 0x37c6, 0x21 + .dw 0x37c7, 0x37c7, 0x2e + .dw 0x37c8, 0x37ce, 0x21 + .dw 0x37cf, 0x37cf, 0x2e + .dw 0x37d0, 0x37d6, 0x21 + .dw 0x37d7, 0x37d7, 0x2e + .dw 0x37d8, 0x37de, 0x21 + .dw 0x37df, 0x37df, 0x2e + .dw 0x37e0, 0x37e6, 0x21 + .dw 0x37e7, 0x37e7, 0x2e + .dw 0x37e8, 0x37ee, 0x21 + .dw 0x37ef, 0x37ef, 0x2e + .dw 0x37f0, 0x37f6, 0x21 + .dw 0x37f7, 0x37f7, 0x2e + .dw 0x37f8, 0x37fe, 0x21 + .dw 0x37ff, 0x37ff, 0x2e + .dw 0x3820, 0x382f, 0x21 + .dw 0x3860, 0x386f, 0x21 + .dw 0x38a0, 0x38af, 0x21 + .dw 0x38b0, 0x38bf, 0x21 + .dw 0x38e0, 0x38ef, 0x21 + .dw 0x38f0, 0x38ff, 0x21 + .dw 0x3904, 0x3907, 0x21 + .dw 0x390c, 0x390f, 0x21 + .dw 0x3914, 0x3917, 0x21 + .dw 0x391c, 0x392f, 0x21 + .dw 0x3934, 0x3937, 0x21 + .dw 0x393c, 0x39bf, 0x21 + .dw 0x397f, 0x397f, 0x2e + .dw 0x3980, 0x39bf, 0x21 + .dw 0x39c0, 0x39c0, 0x2e + .dw 0x39c1, 0x39c7, 0x21 + .dw 0x39c8, 0x39c8, 0x2e + .dw 0x39c9, 0x39cf, 0x21 + .dw 0x39d0, 0x39d0, 0x2e + .dw 0x39d1, 0x39d7, 0x21 + .dw 0x39d8, 0x39d8, 0x2e + .dw 0x39d9, 0x39ef, 0x21 + .dw 0x39f0, 0x39f0, 0x2e + .dw 0x39f1, 0x39f6, 0x21 + .dw 0x39f7, 0x39f8, 0x2e + .dw 0x39f9, 0x39fe, 0x21 + .dw 0x39ff, 0x39ff, 0x2e + .dw 0x3a00, 0x3bff, 0x21 + .dw 0x3c80, 0x3cff, 0x21 + .dw 0x3d04, 0x3d07, 0x21 + .dw 0x3d0c, 0x3d0f, 0x21 + .dw 0x3d14, 0x3d17, 0x21 + .dw 0x3d1c, 0x3d1f, 0x21 + .dw 0x3d24, 0x3d27, 0x21 + .dw 0x3d2c, 0x3d2f, 0x21 + .dw 0x3d34, 0x3d37, 0x21 + .dw 0x3d3c, 0x3dbf, 0X21 + .dw 0x3dc0, 0x3dc0, 0x2e + .dw 0x3dc1, 0x3dc6, 0x21 + .dw 0x3dc7, 0x3dc8, 0x2e + .dw 0x3dc9, 0x3dce, 0x21 + .dw 0x3dcf, 0x3dd0, 0x2e + .dw 0x3dd1, 0x3dd6, 0x21 + .dw 0x3dd7, 0x3dd8, 0x2e + .dw 0x3dd9, 0x3dde, 0x21 + .dw 0x3ddf, 0x3de0, 0x2e + .dw 0x3de1, 0x3de6, 0x21 + .dw 0x3de7, 0x3de8, 0x2e + .dw 0x3de9, 0x3dee, 0x21 + .dw 0x3def, 0x3df0, 0x2e + .dw 0x3df1, 0x3df6, 0x21 + .dw 0x3df7, 0x3df8, 0x2e + .dw 0x3df9, 0x3dfe, 0x21 + .dw 0x3dff, 0x3e7f, 0x2e + .dw 0x3e80, 0x3eb7, 0x21 + .dw 0x3eb8, 0x3ebf, 0x2e + .dw 0x3ec0, 0x3ef7, 0x21 + .dw 0x3ef8, 0x3f03, 0x2e + .dw 0x3f04, 0x3f07, 0x21 + .dw 0x3f08, 0x3f0b, 0x2e + .dw 0x3f0c, 0x3f0f, 0x21 + .dw 0x3f10, 0x3f13, 0x2e + .dw 0x3f14, 0x3f17, 0x21 + .dw 0x3f18, 0x3f1b, 0x2e + .dw 0x3f1c, 0x3f1f, 0x21 + .dw 0x3f20, 0x3f23, 0x2e + .dw 0x3f24, 0x3f27, 0x21 + .dw 0x3f28, 0x3f2b, 0x2e + .dw 0x3f2c, 0x3f2f, 0x21 + .dw 0x3f30, 0x3f33, 0x2e + .dw 0x3f34, 0x3f37, 0x21 + .dw 0x3f38, 0x3f3b, 0x2e + .dw 0x3f3c, 0x3f3d, 0x21 + .dw 0x3f3e, 0x3f3f, 0x2e + .dw 0x3f40, 0x3fb7, 0x21 + .dw 0x3fb8, 0x3fc0, 0x2e + .dw 0x3fc1, 0x3fc6, 0x21 + .dw 0x3fc7, 0x3fc8, 0x2e + .dw 0x3fc9, 0x3fce, 0x21 + .dw 0x3fcf, 0x3fd0, 0x2e + .dw 0x3fd1, 0x3fd6, 0x21 + .dw 0x3fd7, 0x3fd8, 0x2e + .dw 0x3fd9, 0x3fde, 0x21 + .dw 0x3fdf, 0x3fe0, 0x2e + .dw 0x3fe1, 0x3fe6, 0x21 + .dw 0x3fe7, 0x3fe8, 0x2e + .dw 0x3fe9, 0x3fee, 0x21 + .dw 0x3fef, 0x3ff0, 0x2e + .dw 0x3ff1, 0x3ff6, 0x21 + .dw 0x3ff7, 0x3fff, 0x2e + .dw 0x4180, 0x41FF, 0x21 + .dw 0x4480, 0x44bF, 0x21 + .dw 0x4600, 0x47FF, 0x21 + .dw 0x7000, 0x7FFF, 0x21 + .dw 0x9040, 0x9040, 0x22 + .dw 0x9049, 0x9049, 0x22 + .dw 0x9052, 0x9052, 0x22 + .dw 0x905b, 0x905b, 0x22 + .dw 0x9064, 0x9064, 0x22 + .dw 0x906d, 0x906d, 0x22 + .dw 0x9076, 0x9076, 0x22 + .dw 0x907f, 0x907f, 0x22 + .dw 0x90c0, 0x90c0, 0x22 + .dw 0x90c9, 0x90c9, 0x22 + .dw 0x90d2, 0x90d2, 0x22 + .dw 0x90db, 0x90db, 0x22 + .dw 0x90e4, 0x90e4, 0x22 + .dw 0x90ed, 0x90ed, 0x22 + .dw 0x90f6, 0x90f6, 0x22 + .dw 0x90ff, 0x90ff, 0x22 + .dw 0x9180, 0x91ff, 0x21 + .dw 0x9380, 0x93ff, 0x21 + .dw 0x9580, 0x95ff, 0x21 + .dw 0x9640, 0x967f, 0x21 + .dw 0x96c0, 0x96ff, 0x21 + .dw 0x9740, 0x97ff, 0x21 + .dw 0x9980, 0x99ff, 0x21 + .dw 0x9a40, 0x9a7f, 0x21 + .dw 0x9ac0, 0x9aff, 0x21 + .dw 0x9b40, 0x9bff, 0x21 + .dw 0x9c60, 0x9c7f, 0x21 + .dw 0x9ce0, 0x9cff, 0x21 + .dw 0x9d60, 0x9d7f, 0x21 + .dw 0x9ef0, 0x9eff, 0x21 + .dw 0x9f70, 0x9f7f, 0x21 + .dw 0x0000, 0x0000, 0x00 diff --git a/sim/testsuite/sim/bfin/se_all32bitopcodes.S b/sim/testsuite/sim/bfin/se_all32bitopcodes.S new file mode 100644 index 0000000..be3b395 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_all32bitopcodes.S @@ -0,0 +1,34304 @@ +/* + * Blackfin testcase for testing illegal/legal 32-bit opcodes from userspace + * we track all instructions which cause some sort of exception when run from + * userspace, this is normally EXCAUSE : + * - 0x21 : illegal instruction + * - 0x22 : illegal instruction combination + * - 0x2e : use of supervisor resource from userspace + * and walk every instruction from 0x00000000 to 0xffffffff (and have 0xc000 set) + */ + +# don't try to run normally as it takes way too long in sim +# mach: none +# sim: --environment operating +# xfail: too many invalid insns are decoded as valid + +#include "test.h" + .include "testutils.inc" + + start + + /* Set up exception handler */ + imm32 P4, EVT3; + loadsym R1, _evx; + [P4] = R1; + + /* set up the _location */ + loadsym P0, _location + loadsym P1, _table; + [P0] = P1; + + /* Enable single stepping */ + R0 = 1; + SYSCFG = R0; + + /* Lower to the code we want to single step through */ + loadsym P1, _usr; + RETI = P1; + + /* set up pointers to valid data (32Meg), to reduce address violations */ + .macro reset_regs + imm32 r0, 0x2000000; + l0 = 0; l1 = 0; l2 = 0; l3 = 0; + p0 = r0; p1 = r0; p2 = r0; p3 = r0; p4 = r0; p5 = r0; + usp = r0; fp = r0; + i0 = r0; i1 = r0; i2 = r0; i3 = r0; + b0 = r0; b1 = r0; b2 = r0; b3 = r0; + .endm + reset_regs + + RTI; + + .align 4; +_evx: + /* Make sure exception reason is single step */ + R3 = SEQSTAT; + R4 = 0x3f; + R3 = R3 & R4; + + /* find a match */ + loadsym P5, _usr; + loadsym P4, _location; + R2 = [P5]; + P1 = [P4]; + R0 = R2 << 16; + R1 = R2 >> 16; + R0 = R0 | R1; + +_match: + P2 = P1; + R7 = [P1++]; + R6 = [P1++]; + R5 = [P1++]; + + /* is this the end of the table? */ + R4 = 0; + CC = R4 == R7; + IF CC jump _new_instruction; + + /* is the opcode (R0) greater than the 2nd entry in the table (R6) */ + /* if so look at the next line in the table */ + CC = R6 < R0; + if CC jump _match; + + /* is the opcode (R0) smaller than the first entry in the table (R7) */ + /* this means it's somewhere between the two lines, and should be legal */ + CC = R7 <= R0; + if !CC jump _legal_instruction; + + /* is the current EXCAUSE (R3), the same as the table (R5) */ + /* if not, fail */ + CC = R3 == R5 + if !CC jump fail_lvl; + +_match_done: + /* back up, and store the location to search next */ + [P4] = P2; + + /* it matches, so fall through */ + jump _next_instruction; + +_new_instruction: + jump fail_lvl; + + /* output the insn (R0) and excause (R3) if diff from last */ + loadsym P0, _last_excause; + R2 = [P0]; + CC = R2 == R3; + IF CC jump _next_instruction; + [P0] = R3; + +.ifdef BFIN_JTAG_xxxxx + R1 = R0; + R0 = 0x8; + call __emu_out; + R0 = R1; + call __emu_out; + R0 = R3; + call __emu_out; +.else + loadsym P0, _next_location; + P1 = [P0]; + [P1++] = R0; + [P1++] = R3; + [P0] = P1; +.endif + + jump _next_instruction; + +_legal_instruction: + R4 = 0x10; + CC = R3 == R4; + IF !CC JUMP fail_lvl; + /* it wasn't in the list, and was a single step, so fall through */ + +_next_instruction: + /* increment, and go again. */ + R0 = R2; + + /* Is this the last insn we'll execute ? */ + imm32 R1, 0xfffff7ff; + CC = R1 == R0; + IF CC JUMP pass_lvl; + + /* cut across the opcode space in an efficient manner: + * increment the high 16bits first since the low 16bits encode + * the type of insn ... */ + imm32 R1, 0x10000; + R0 = R1 + R0; + CC = R1 < R0 (IU); + IF CC jump 1f (bp); + + R0 += 1; + /* skip any 16bit insn chunks */ + R1 = R0; + R1.L = 0xC000; + CC = R0 < R1 (IU); + IF CC R0 = R1; +1: + + /* skip parallel insns */ + R1 = R0; + R1.L = 0xe800; /* allow linkage insns */ + CC = R0 == R1; + IF CC jump 1f; + CC = BITTST (R0, 11); + IF !CC jump 1f (bp); + R1 = 0x800; + R0 = R0 + R1; +1: + + [P5] = R0; + + /* Make sure the opcode isn't in a write buffer */ + SSYNC; + + R1 = P5; + RETX = R1; + + /* set up pointers to valid data (32Meg), to reduce address violations */ + reset_regs + RETS = r0; + RETN = r0; + RETE = r0; + RETI = r0; + + RTX; + +pass_lvl: + dbg_pass; +fail_lvl: + dbg_fail; + + .section .text.usr + .align 4 +_usr: + .dw 0xc000; + .dw 0x0000; + loadsym P0, fail_lvl; + JUMP (P0); + + /* this table must be sorted, and end with zero */ + .data + .align 4; +_last_excause: + .dd 0xffff +_next_location: + .dd _table_end +_location: + .dd 0 +_table: + /* start end SEQSTAT */ + .dw 0x1a00, 0xc000, 0x1fff, 0xc000, 0x21, 0 + .dw 0x3a00, 0xc000, 0x3fff, 0xc000, 0x21, 0 + .dw 0x5a00, 0xc000, 0x5fff, 0xc000, 0x21, 0 + .dw 0x7a00, 0xc000, 0x7fff, 0xc000, 0x21, 0 + .dw 0x9a00, 0xc000, 0x9fff, 0xc000, 0x21, 0 + .dw 0xba00, 0xc000, 0xbfff, 0xc000, 0x21, 0 + .dw 0xda00, 0xc000, 0xdfff, 0xc000, 0x21, 0 + .dw 0xfa00, 0xc000, 0xffff, 0xc000, 0x21, 0 + .dw 0x1a00, 0xc001, 0x1fff, 0xc001, 0x21, 0 + .dw 0x3a00, 0xc001, 0x3fff, 0xc001, 0x21, 0 + .dw 0x5a00, 0xc001, 0x5fff, 0xc001, 0x21, 0 + .dw 0x7a00, 0xc001, 0x7fff, 0xc001, 0x21, 0 + .dw 0x9a00, 0xc001, 0x9fff, 0xc001, 0x21, 0 + .dw 0xba00, 0xc001, 0xbfff, 0xc001, 0x21, 0 + .dw 0xda00, 0xc001, 0xdfff, 0xc001, 0x21, 0 + .dw 0xfa00, 0xc001, 0xffff, 0xc001, 0x21, 0 + .dw 0x1a00, 0xc002, 0x1fff, 0xc002, 0x21, 0 + .dw 0x3a00, 0xc002, 0x3fff, 0xc002, 0x21, 0 + .dw 0x5a00, 0xc002, 0x5fff, 0xc002, 0x21, 0 + .dw 0x7a00, 0xc002, 0x7fff, 0xc002, 0x21, 0 + .dw 0x9a00, 0xc002, 0x9fff, 0xc002, 0x21, 0 + .dw 0xba00, 0xc002, 0xbfff, 0xc002, 0x21, 0 + .dw 0xda00, 0xc002, 0xdfff, 0xc002, 0x21, 0 + .dw 0xfa00, 0xc002, 0xffff, 0xc002, 0x21, 0 + .dw 0x1a00, 0xc003, 0x1fff, 0xc003, 0x21, 0 + .dw 0x3a00, 0xc003, 0xffff, 0xc003, 0x21, 0 + .dw 0x1a00, 0xc004, 0x1fff, 0xc004, 0x21, 0 + .dw 0x3a00, 0xc004, 0x3fff, 0xc004, 0x21, 0 + .dw 0x5a00, 0xc004, 0x5fff, 0xc004, 0x21, 0 + .dw 0x7a00, 0xc004, 0x7fff, 0xc004, 0x21, 0 + .dw 0x9a00, 0xc004, 0x9fff, 0xc004, 0x21, 0 + .dw 0xba00, 0xc004, 0xbfff, 0xc004, 0x21, 0 + .dw 0xda00, 0xc004, 0xdfff, 0xc004, 0x21, 0 + .dw 0xfa00, 0xc004, 0xffff, 0xc004, 0x21, 0 + .dw 0x1a00, 0xc005, 0x1fff, 0xc005, 0x21, 0 + .dw 0x3a00, 0xc005, 0x3fff, 0xc005, 0x21, 0 + .dw 0x5a00, 0xc005, 0x5fff, 0xc005, 0x21, 0 + .dw 0x7a00, 0xc005, 0x7fff, 0xc005, 0x21, 0 + .dw 0x9a00, 0xc005, 0x9fff, 0xc005, 0x21, 0 + .dw 0xba00, 0xc005, 0xbfff, 0xc005, 0x21, 0 + .dw 0xda00, 0xc005, 0xdfff, 0xc005, 0x21, 0 + .dw 0xfa00, 0xc005, 0xffff, 0xc005, 0x21, 0 + .dw 0x1a00, 0xc006, 0x1fff, 0xc006, 0x21, 0 + .dw 0x3a00, 0xc006, 0x3fff, 0xc006, 0x21, 0 + .dw 0x5a00, 0xc006, 0x5fff, 0xc006, 0x21, 0 + .dw 0x7a00, 0xc006, 0x7fff, 0xc006, 0x21, 0 + .dw 0x9a00, 0xc006, 0x9fff, 0xc006, 0x21, 0 + .dw 0xba00, 0xc006, 0xbfff, 0xc006, 0x21, 0 + .dw 0xda00, 0xc006, 0xdfff, 0xc006, 0x21, 0 + .dw 0xfa00, 0xc006, 0xffff, 0xc006, 0x21, 0 + .dw 0x1a00, 0xc007, 0x1fff, 0xc007, 0x21, 0 + .dw 0x3a00, 0xc007, 0x1fff, 0xc008, 0x21, 0 + .dw 0x2040, 0xc008, 0x207f, 0xc008, 0x21, 0 + .dw 0x20c0, 0xc008, 0x20ff, 0xc008, 0x21, 0 + .dw 0x2140, 0xc008, 0x217f, 0xc008, 0x21, 0 + .dw 0x21c0, 0xc008, 0x21ff, 0xc008, 0x21, 0 + .dw 0x2240, 0xc008, 0x227f, 0xc008, 0x21, 0 + .dw 0x22c0, 0xc008, 0x22ff, 0xc008, 0x21, 0 + .dw 0x2340, 0xc008, 0x237f, 0xc008, 0x21, 0 + .dw 0x23c0, 0xc008, 0x23ff, 0xc008, 0x21, 0 + .dw 0x2440, 0xc008, 0x247f, 0xc008, 0x21, 0 + .dw 0x24c0, 0xc008, 0x24ff, 0xc008, 0x21, 0 + .dw 0x2540, 0xc008, 0x257f, 0xc008, 0x21, 0 + .dw 0x25c0, 0xc008, 0x25ff, 0xc008, 0x21, 0 + .dw 0x2640, 0xc008, 0x267f, 0xc008, 0x21, 0 + .dw 0x26c0, 0xc008, 0x26ff, 0xc008, 0x21, 0 + .dw 0x2740, 0xc008, 0x277f, 0xc008, 0x21, 0 + .dw 0x27c0, 0xc008, 0x27ff, 0xc008, 0x21, 0 + .dw 0x2840, 0xc008, 0x287f, 0xc008, 0x21, 0 + .dw 0x28c0, 0xc008, 0x28ff, 0xc008, 0x21, 0 + .dw 0x2940, 0xc008, 0x297f, 0xc008, 0x21, 0 + .dw 0x29c0, 0xc008, 0x29ff, 0xc008, 0x21, 0 + .dw 0x2a40, 0xc008, 0x2a7f, 0xc008, 0x21, 0 + .dw 0x2ac0, 0xc008, 0x2aff, 0xc008, 0x21, 0 + .dw 0x2b40, 0xc008, 0x2b7f, 0xc008, 0x21, 0 + .dw 0x2bc0, 0xc008, 0x2bff, 0xc008, 0x21, 0 + .dw 0x2c40, 0xc008, 0x2c7f, 0xc008, 0x21, 0 + .dw 0x2cc0, 0xc008, 0x2cff, 0xc008, 0x21, 0 + .dw 0x2d40, 0xc008, 0x2d7f, 0xc008, 0x21, 0 + .dw 0x2dc0, 0xc008, 0x2dff, 0xc008, 0x21, 0 + .dw 0x2e40, 0xc008, 0x2e7f, 0xc008, 0x21, 0 + .dw 0x2ec0, 0xc008, 0x2eff, 0xc008, 0x21, 0 + .dw 0x2f40, 0xc008, 0x2f7f, 0xc008, 0x21, 0 + .dw 0x2fc0, 0xc008, 0x2fff, 0xc008, 0x21, 0 + .dw 0x3040, 0xc008, 0x307f, 0xc008, 0x21, 0 + .dw 0x30c0, 0xc008, 0x30ff, 0xc008, 0x21, 0 + .dw 0x3140, 0xc008, 0x317f, 0xc008, 0x21, 0 + .dw 0x31c0, 0xc008, 0x31ff, 0xc008, 0x21, 0 + .dw 0x3240, 0xc008, 0x327f, 0xc008, 0x21, 0 + .dw 0x32c0, 0xc008, 0x32ff, 0xc008, 0x21, 0 + .dw 0x3340, 0xc008, 0x337f, 0xc008, 0x21, 0 + .dw 0x33c0, 0xc008, 0x33ff, 0xc008, 0x21, 0 + .dw 0x3440, 0xc008, 0x347f, 0xc008, 0x21, 0 + .dw 0x34c0, 0xc008, 0x34ff, 0xc008, 0x21, 0 + .dw 0x3540, 0xc008, 0x357f, 0xc008, 0x21, 0 + .dw 0x35c0, 0xc008, 0x35ff, 0xc008, 0x21, 0 + .dw 0x3640, 0xc008, 0x367f, 0xc008, 0x21, 0 + .dw 0x36c0, 0xc008, 0x36ff, 0xc008, 0x21, 0 + .dw 0x3740, 0xc008, 0x377f, 0xc008, 0x21, 0 + .dw 0x37c0, 0xc008, 0x37ff, 0xc008, 0x21, 0 + .dw 0x3840, 0xc008, 0x387f, 0xc008, 0x21, 0 + .dw 0x38c0, 0xc008, 0x38ff, 0xc008, 0x21, 0 + .dw 0x3940, 0xc008, 0x397f, 0xc008, 0x21, 0 + .dw 0x39c0, 0xc008, 0x5fff, 0xc008, 0x21, 0 + .dw 0x6040, 0xc008, 0x607f, 0xc008, 0x21, 0 + .dw 0x60c0, 0xc008, 0x60ff, 0xc008, 0x21, 0 + .dw 0x6140, 0xc008, 0x617f, 0xc008, 0x21, 0 + .dw 0x61c0, 0xc008, 0x61ff, 0xc008, 0x21, 0 + .dw 0x6240, 0xc008, 0x627f, 0xc008, 0x21, 0 + .dw 0x62c0, 0xc008, 0x62ff, 0xc008, 0x21, 0 + .dw 0x6340, 0xc008, 0x637f, 0xc008, 0x21, 0 + .dw 0x63c0, 0xc008, 0x63ff, 0xc008, 0x21, 0 + .dw 0x6440, 0xc008, 0x647f, 0xc008, 0x21, 0 + .dw 0x64c0, 0xc008, 0x64ff, 0xc008, 0x21, 0 + .dw 0x6540, 0xc008, 0x657f, 0xc008, 0x21, 0 + .dw 0x65c0, 0xc008, 0x65ff, 0xc008, 0x21, 0 + .dw 0x6640, 0xc008, 0x667f, 0xc008, 0x21, 0 + .dw 0x66c0, 0xc008, 0x66ff, 0xc008, 0x21, 0 + .dw 0x6740, 0xc008, 0x677f, 0xc008, 0x21, 0 + .dw 0x67c0, 0xc008, 0x67ff, 0xc008, 0x21, 0 + .dw 0x6840, 0xc008, 0x687f, 0xc008, 0x21, 0 + .dw 0x68c0, 0xc008, 0x68ff, 0xc008, 0x21, 0 + .dw 0x6940, 0xc008, 0x697f, 0xc008, 0x21, 0 + .dw 0x69c0, 0xc008, 0x69ff, 0xc008, 0x21, 0 + .dw 0x6a40, 0xc008, 0x6a7f, 0xc008, 0x21, 0 + .dw 0x6ac0, 0xc008, 0x6aff, 0xc008, 0x21, 0 + .dw 0x6b40, 0xc008, 0x6b7f, 0xc008, 0x21, 0 + .dw 0x6bc0, 0xc008, 0x6bff, 0xc008, 0x21, 0 + .dw 0x6c40, 0xc008, 0x6c7f, 0xc008, 0x21, 0 + .dw 0x6cc0, 0xc008, 0x6cff, 0xc008, 0x21, 0 + .dw 0x6d40, 0xc008, 0x6d7f, 0xc008, 0x21, 0 + .dw 0x6dc0, 0xc008, 0x6dff, 0xc008, 0x21, 0 + .dw 0x6e40, 0xc008, 0x6e7f, 0xc008, 0x21, 0 + .dw 0x6ec0, 0xc008, 0x6eff, 0xc008, 0x21, 0 + .dw 0x6f40, 0xc008, 0x6f7f, 0xc008, 0x21, 0 + .dw 0x6fc0, 0xc008, 0x6fff, 0xc008, 0x21, 0 + .dw 0x7040, 0xc008, 0x707f, 0xc008, 0x21, 0 + .dw 0x70c0, 0xc008, 0x70ff, 0xc008, 0x21, 0 + .dw 0x7140, 0xc008, 0x717f, 0xc008, 0x21, 0 + .dw 0x71c0, 0xc008, 0x71ff, 0xc008, 0x21, 0 + .dw 0x7240, 0xc008, 0x727f, 0xc008, 0x21, 0 + .dw 0x72c0, 0xc008, 0x72ff, 0xc008, 0x21, 0 + .dw 0x7340, 0xc008, 0x737f, 0xc008, 0x21, 0 + .dw 0x73c0, 0xc008, 0x73ff, 0xc008, 0x21, 0 + .dw 0x7440, 0xc008, 0x747f, 0xc008, 0x21, 0 + .dw 0x74c0, 0xc008, 0x74ff, 0xc008, 0x21, 0 + .dw 0x7540, 0xc008, 0x757f, 0xc008, 0x21, 0 + .dw 0x75c0, 0xc008, 0x75ff, 0xc008, 0x21, 0 + .dw 0x7640, 0xc008, 0x767f, 0xc008, 0x21, 0 + .dw 0x76c0, 0xc008, 0x76ff, 0xc008, 0x21, 0 + .dw 0x7740, 0xc008, 0x777f, 0xc008, 0x21, 0 + .dw 0x77c0, 0xc008, 0x77ff, 0xc008, 0x21, 0 + .dw 0x7840, 0xc008, 0x787f, 0xc008, 0x21, 0 + .dw 0x78c0, 0xc008, 0x78ff, 0xc008, 0x21, 0 + .dw 0x7940, 0xc008, 0x797f, 0xc008, 0x21, 0 + .dw 0x79c0, 0xc008, 0x9fff, 0xc008, 0x21, 0 + .dw 0xa040, 0xc008, 0xa07f, 0xc008, 0x21, 0 + .dw 0xa0c0, 0xc008, 0xa0ff, 0xc008, 0x21, 0 + .dw 0xa140, 0xc008, 0xa17f, 0xc008, 0x21, 0 + .dw 0xa1c0, 0xc008, 0xa1ff, 0xc008, 0x21, 0 + .dw 0xa240, 0xc008, 0xa27f, 0xc008, 0x21, 0 + .dw 0xa2c0, 0xc008, 0xa2ff, 0xc008, 0x21, 0 + .dw 0xa340, 0xc008, 0xa37f, 0xc008, 0x21, 0 + .dw 0xa3c0, 0xc008, 0xa3ff, 0xc008, 0x21, 0 + .dw 0xa440, 0xc008, 0xa47f, 0xc008, 0x21, 0 + .dw 0xa4c0, 0xc008, 0xa4ff, 0xc008, 0x21, 0 + .dw 0xa540, 0xc008, 0xa57f, 0xc008, 0x21, 0 + .dw 0xa5c0, 0xc008, 0xa5ff, 0xc008, 0x21, 0 + .dw 0xa640, 0xc008, 0xa67f, 0xc008, 0x21, 0 + .dw 0xa6c0, 0xc008, 0xa6ff, 0xc008, 0x21, 0 + .dw 0xa740, 0xc008, 0xa77f, 0xc008, 0x21, 0 + .dw 0xa7c0, 0xc008, 0xa7ff, 0xc008, 0x21, 0 + .dw 0xa840, 0xc008, 0xa87f, 0xc008, 0x21, 0 + .dw 0xa8c0, 0xc008, 0xa8ff, 0xc008, 0x21, 0 + .dw 0xa940, 0xc008, 0xa97f, 0xc008, 0x21, 0 + .dw 0xa9c0, 0xc008, 0xa9ff, 0xc008, 0x21, 0 + .dw 0xaa40, 0xc008, 0xaa7f, 0xc008, 0x21, 0 + .dw 0xaac0, 0xc008, 0xaaff, 0xc008, 0x21, 0 + .dw 0xab40, 0xc008, 0xab7f, 0xc008, 0x21, 0 + .dw 0xabc0, 0xc008, 0xabff, 0xc008, 0x21, 0 + .dw 0xac40, 0xc008, 0xac7f, 0xc008, 0x21, 0 + .dw 0xacc0, 0xc008, 0xacff, 0xc008, 0x21, 0 + .dw 0xad40, 0xc008, 0xad7f, 0xc008, 0x21, 0 + .dw 0xadc0, 0xc008, 0xadff, 0xc008, 0x21, 0 + .dw 0xae40, 0xc008, 0xae7f, 0xc008, 0x21, 0 + .dw 0xaec0, 0xc008, 0xaeff, 0xc008, 0x21, 0 + .dw 0xaf40, 0xc008, 0xaf7f, 0xc008, 0x21, 0 + .dw 0xafc0, 0xc008, 0xafff, 0xc008, 0x21, 0 + .dw 0xb040, 0xc008, 0xb07f, 0xc008, 0x21, 0 + .dw 0xb0c0, 0xc008, 0xb0ff, 0xc008, 0x21, 0 + .dw 0xb140, 0xc008, 0xb17f, 0xc008, 0x21, 0 + .dw 0xb1c0, 0xc008, 0xb1ff, 0xc008, 0x21, 0 + .dw 0xb240, 0xc008, 0xb27f, 0xc008, 0x21, 0 + .dw 0xb2c0, 0xc008, 0xb2ff, 0xc008, 0x21, 0 + .dw 0xb340, 0xc008, 0xb37f, 0xc008, 0x21, 0 + .dw 0xb3c0, 0xc008, 0xb3ff, 0xc008, 0x21, 0 + .dw 0xb440, 0xc008, 0xb47f, 0xc008, 0x21, 0 + .dw 0xb4c0, 0xc008, 0xb4ff, 0xc008, 0x21, 0 + .dw 0xb540, 0xc008, 0xb57f, 0xc008, 0x21, 0 + .dw 0xb5c0, 0xc008, 0xb5ff, 0xc008, 0x21, 0 + .dw 0xb640, 0xc008, 0xb67f, 0xc008, 0x21, 0 + .dw 0xb6c0, 0xc008, 0xb6ff, 0xc008, 0x21, 0 + .dw 0xb740, 0xc008, 0xb77f, 0xc008, 0x21, 0 + .dw 0xb7c0, 0xc008, 0xb7ff, 0xc008, 0x21, 0 + .dw 0xb840, 0xc008, 0xb87f, 0xc008, 0x21, 0 + .dw 0xb8c0, 0xc008, 0xb8ff, 0xc008, 0x21, 0 + .dw 0xb940, 0xc008, 0xb97f, 0xc008, 0x21, 0 + .dw 0xb9c0, 0xc008, 0xdfff, 0xc008, 0x21, 0 + .dw 0xe040, 0xc008, 0xe07f, 0xc008, 0x21, 0 + .dw 0xe0c0, 0xc008, 0xe0ff, 0xc008, 0x21, 0 + .dw 0xe140, 0xc008, 0xe17f, 0xc008, 0x21, 0 + .dw 0xe1c0, 0xc008, 0xe1ff, 0xc008, 0x21, 0 + .dw 0xe240, 0xc008, 0xe27f, 0xc008, 0x21, 0 + .dw 0xe2c0, 0xc008, 0xe2ff, 0xc008, 0x21, 0 + .dw 0xe340, 0xc008, 0xe37f, 0xc008, 0x21, 0 + .dw 0xe3c0, 0xc008, 0xe3ff, 0xc008, 0x21, 0 + .dw 0xe440, 0xc008, 0xe47f, 0xc008, 0x21, 0 + .dw 0xe4c0, 0xc008, 0xe4ff, 0xc008, 0x21, 0 + .dw 0xe540, 0xc008, 0xe57f, 0xc008, 0x21, 0 + .dw 0xe5c0, 0xc008, 0xe5ff, 0xc008, 0x21, 0 + .dw 0xe640, 0xc008, 0xe67f, 0xc008, 0x21, 0 + .dw 0xe6c0, 0xc008, 0xe6ff, 0xc008, 0x21, 0 + .dw 0xe740, 0xc008, 0xe77f, 0xc008, 0x21, 0 + .dw 0xe7c0, 0xc008, 0xe7ff, 0xc008, 0x21, 0 + .dw 0xe840, 0xc008, 0xe87f, 0xc008, 0x21, 0 + .dw 0xe8c0, 0xc008, 0xe8ff, 0xc008, 0x21, 0 + .dw 0xe940, 0xc008, 0xe97f, 0xc008, 0x21, 0 + .dw 0xe9c0, 0xc008, 0xe9ff, 0xc008, 0x21, 0 + .dw 0xea40, 0xc008, 0xea7f, 0xc008, 0x21, 0 + .dw 0xeac0, 0xc008, 0xeaff, 0xc008, 0x21, 0 + .dw 0xeb40, 0xc008, 0xeb7f, 0xc008, 0x21, 0 + .dw 0xebc0, 0xc008, 0xebff, 0xc008, 0x21, 0 + .dw 0xec40, 0xc008, 0xec7f, 0xc008, 0x21, 0 + .dw 0xecc0, 0xc008, 0xecff, 0xc008, 0x21, 0 + .dw 0xed40, 0xc008, 0xed7f, 0xc008, 0x21, 0 + .dw 0xedc0, 0xc008, 0xedff, 0xc008, 0x21, 0 + .dw 0xee40, 0xc008, 0xee7f, 0xc008, 0x21, 0 + .dw 0xeec0, 0xc008, 0xeeff, 0xc008, 0x21, 0 + .dw 0xef40, 0xc008, 0xef7f, 0xc008, 0x21, 0 + .dw 0xefc0, 0xc008, 0xefff, 0xc008, 0x21, 0 + .dw 0xf040, 0xc008, 0xf07f, 0xc008, 0x21, 0 + .dw 0xf0c0, 0xc008, 0xf0ff, 0xc008, 0x21, 0 + .dw 0xf140, 0xc008, 0xf17f, 0xc008, 0x21, 0 + .dw 0xf1c0, 0xc008, 0xf1ff, 0xc008, 0x21, 0 + .dw 0xf240, 0xc008, 0xf27f, 0xc008, 0x21, 0 + .dw 0xf2c0, 0xc008, 0xf2ff, 0xc008, 0x21, 0 + .dw 0xf340, 0xc008, 0xf37f, 0xc008, 0x21, 0 + .dw 0xf3c0, 0xc008, 0xf3ff, 0xc008, 0x21, 0 + .dw 0xf440, 0xc008, 0xf47f, 0xc008, 0x21, 0 + .dw 0xf4c0, 0xc008, 0xf4ff, 0xc008, 0x21, 0 + .dw 0xf540, 0xc008, 0xf57f, 0xc008, 0x21, 0 + .dw 0xf5c0, 0xc008, 0xf5ff, 0xc008, 0x21, 0 + .dw 0xf640, 0xc008, 0xf67f, 0xc008, 0x21, 0 + .dw 0xf6c0, 0xc008, 0xf6ff, 0xc008, 0x21, 0 + .dw 0xf740, 0xc008, 0xf77f, 0xc008, 0x21, 0 + .dw 0xf7c0, 0xc008, 0xf7ff, 0xc008, 0x21, 0 + .dw 0xf840, 0xc008, 0xf87f, 0xc008, 0x21, 0 + .dw 0xf8c0, 0xc008, 0xf8ff, 0xc008, 0x21, 0 + .dw 0xf940, 0xc008, 0xf97f, 0xc008, 0x21, 0 + .dw 0xf9c0, 0xc008, 0x1fff, 0xc009, 0x21, 0 + .dw 0x2040, 0xc009, 0x207f, 0xc009, 0x21, 0 + .dw 0x20c0, 0xc009, 0x20ff, 0xc009, 0x21, 0 + .dw 0x2140, 0xc009, 0x217f, 0xc009, 0x21, 0 + .dw 0x21c0, 0xc009, 0x21ff, 0xc009, 0x21, 0 + .dw 0x2240, 0xc009, 0x227f, 0xc009, 0x21, 0 + .dw 0x22c0, 0xc009, 0x22ff, 0xc009, 0x21, 0 + .dw 0x2340, 0xc009, 0x237f, 0xc009, 0x21, 0 + .dw 0x23c0, 0xc009, 0x23ff, 0xc009, 0x21, 0 + .dw 0x2440, 0xc009, 0x247f, 0xc009, 0x21, 0 + .dw 0x24c0, 0xc009, 0x24ff, 0xc009, 0x21, 0 + .dw 0x2540, 0xc009, 0x257f, 0xc009, 0x21, 0 + .dw 0x25c0, 0xc009, 0x25ff, 0xc009, 0x21, 0 + .dw 0x2640, 0xc009, 0x267f, 0xc009, 0x21, 0 + .dw 0x26c0, 0xc009, 0x26ff, 0xc009, 0x21, 0 + .dw 0x2740, 0xc009, 0x277f, 0xc009, 0x21, 0 + .dw 0x27c0, 0xc009, 0x27ff, 0xc009, 0x21, 0 + .dw 0x2840, 0xc009, 0x287f, 0xc009, 0x21, 0 + .dw 0x28c0, 0xc009, 0x28ff, 0xc009, 0x21, 0 + .dw 0x2940, 0xc009, 0x297f, 0xc009, 0x21, 0 + .dw 0x29c0, 0xc009, 0x29ff, 0xc009, 0x21, 0 + .dw 0x2a40, 0xc009, 0x2a7f, 0xc009, 0x21, 0 + .dw 0x2ac0, 0xc009, 0x2aff, 0xc009, 0x21, 0 + .dw 0x2b40, 0xc009, 0x2b7f, 0xc009, 0x21, 0 + .dw 0x2bc0, 0xc009, 0x2bff, 0xc009, 0x21, 0 + .dw 0x2c40, 0xc009, 0x2c7f, 0xc009, 0x21, 0 + .dw 0x2cc0, 0xc009, 0x2cff, 0xc009, 0x21, 0 + .dw 0x2d40, 0xc009, 0x2d7f, 0xc009, 0x21, 0 + .dw 0x2dc0, 0xc009, 0x2dff, 0xc009, 0x21, 0 + .dw 0x2e40, 0xc009, 0x2e7f, 0xc009, 0x21, 0 + .dw 0x2ec0, 0xc009, 0x2eff, 0xc009, 0x21, 0 + .dw 0x2f40, 0xc009, 0x2f7f, 0xc009, 0x21, 0 + .dw 0x2fc0, 0xc009, 0x2fff, 0xc009, 0x21, 0 + .dw 0x3040, 0xc009, 0x307f, 0xc009, 0x21, 0 + .dw 0x30c0, 0xc009, 0x30ff, 0xc009, 0x21, 0 + .dw 0x3140, 0xc009, 0x317f, 0xc009, 0x21, 0 + .dw 0x31c0, 0xc009, 0x31ff, 0xc009, 0x21, 0 + .dw 0x3240, 0xc009, 0x327f, 0xc009, 0x21, 0 + .dw 0x32c0, 0xc009, 0x32ff, 0xc009, 0x21, 0 + .dw 0x3340, 0xc009, 0x337f, 0xc009, 0x21, 0 + .dw 0x33c0, 0xc009, 0x33ff, 0xc009, 0x21, 0 + .dw 0x3440, 0xc009, 0x347f, 0xc009, 0x21, 0 + .dw 0x34c0, 0xc009, 0x34ff, 0xc009, 0x21, 0 + .dw 0x3540, 0xc009, 0x357f, 0xc009, 0x21, 0 + .dw 0x35c0, 0xc009, 0x35ff, 0xc009, 0x21, 0 + .dw 0x3640, 0xc009, 0x367f, 0xc009, 0x21, 0 + .dw 0x36c0, 0xc009, 0x36ff, 0xc009, 0x21, 0 + .dw 0x3740, 0xc009, 0x377f, 0xc009, 0x21, 0 + .dw 0x37c0, 0xc009, 0x37ff, 0xc009, 0x21, 0 + .dw 0x3840, 0xc009, 0x387f, 0xc009, 0x21, 0 + .dw 0x38c0, 0xc009, 0x38ff, 0xc009, 0x21, 0 + .dw 0x3940, 0xc009, 0x397f, 0xc009, 0x21, 0 + .dw 0x39c0, 0xc009, 0x5fff, 0xc009, 0x21, 0 + .dw 0x6040, 0xc009, 0x607f, 0xc009, 0x21, 0 + .dw 0x60c0, 0xc009, 0x60ff, 0xc009, 0x21, 0 + .dw 0x6140, 0xc009, 0x617f, 0xc009, 0x21, 0 + .dw 0x61c0, 0xc009, 0x61ff, 0xc009, 0x21, 0 + .dw 0x6240, 0xc009, 0x627f, 0xc009, 0x21, 0 + .dw 0x62c0, 0xc009, 0x62ff, 0xc009, 0x21, 0 + .dw 0x6340, 0xc009, 0x637f, 0xc009, 0x21, 0 + .dw 0x63c0, 0xc009, 0x63ff, 0xc009, 0x21, 0 + .dw 0x6440, 0xc009, 0x647f, 0xc009, 0x21, 0 + .dw 0x64c0, 0xc009, 0x64ff, 0xc009, 0x21, 0 + .dw 0x6540, 0xc009, 0x657f, 0xc009, 0x21, 0 + .dw 0x65c0, 0xc009, 0x65ff, 0xc009, 0x21, 0 + .dw 0x6640, 0xc009, 0x667f, 0xc009, 0x21, 0 + .dw 0x66c0, 0xc009, 0x66ff, 0xc009, 0x21, 0 + .dw 0x6740, 0xc009, 0x677f, 0xc009, 0x21, 0 + .dw 0x67c0, 0xc009, 0x67ff, 0xc009, 0x21, 0 + .dw 0x6840, 0xc009, 0x687f, 0xc009, 0x21, 0 + .dw 0x68c0, 0xc009, 0x68ff, 0xc009, 0x21, 0 + .dw 0x6940, 0xc009, 0x697f, 0xc009, 0x21, 0 + .dw 0x69c0, 0xc009, 0x69ff, 0xc009, 0x21, 0 + .dw 0x6a40, 0xc009, 0x6a7f, 0xc009, 0x21, 0 + .dw 0x6ac0, 0xc009, 0x6aff, 0xc009, 0x21, 0 + .dw 0x6b40, 0xc009, 0x6b7f, 0xc009, 0x21, 0 + .dw 0x6bc0, 0xc009, 0x6bff, 0xc009, 0x21, 0 + .dw 0x6c40, 0xc009, 0x6c7f, 0xc009, 0x21, 0 + .dw 0x6cc0, 0xc009, 0x6cff, 0xc009, 0x21, 0 + .dw 0x6d40, 0xc009, 0x6d7f, 0xc009, 0x21, 0 + .dw 0x6dc0, 0xc009, 0x6dff, 0xc009, 0x21, 0 + .dw 0x6e40, 0xc009, 0x6e7f, 0xc009, 0x21, 0 + .dw 0x6ec0, 0xc009, 0x6eff, 0xc009, 0x21, 0 + .dw 0x6f40, 0xc009, 0x6f7f, 0xc009, 0x21, 0 + .dw 0x6fc0, 0xc009, 0x6fff, 0xc009, 0x21, 0 + .dw 0x7040, 0xc009, 0x707f, 0xc009, 0x21, 0 + .dw 0x70c0, 0xc009, 0x70ff, 0xc009, 0x21, 0 + .dw 0x7140, 0xc009, 0x717f, 0xc009, 0x21, 0 + .dw 0x71c0, 0xc009, 0x71ff, 0xc009, 0x21, 0 + .dw 0x7240, 0xc009, 0x727f, 0xc009, 0x21, 0 + .dw 0x72c0, 0xc009, 0x72ff, 0xc009, 0x21, 0 + .dw 0x7340, 0xc009, 0x737f, 0xc009, 0x21, 0 + .dw 0x73c0, 0xc009, 0x73ff, 0xc009, 0x21, 0 + .dw 0x7440, 0xc009, 0x747f, 0xc009, 0x21, 0 + .dw 0x74c0, 0xc009, 0x74ff, 0xc009, 0x21, 0 + .dw 0x7540, 0xc009, 0x757f, 0xc009, 0x21, 0 + .dw 0x75c0, 0xc009, 0x75ff, 0xc009, 0x21, 0 + .dw 0x7640, 0xc009, 0x767f, 0xc009, 0x21, 0 + .dw 0x76c0, 0xc009, 0x76ff, 0xc009, 0x21, 0 + .dw 0x7740, 0xc009, 0x777f, 0xc009, 0x21, 0 + .dw 0x77c0, 0xc009, 0x77ff, 0xc009, 0x21, 0 + .dw 0x7840, 0xc009, 0x787f, 0xc009, 0x21, 0 + .dw 0x78c0, 0xc009, 0x78ff, 0xc009, 0x21, 0 + .dw 0x7940, 0xc009, 0x797f, 0xc009, 0x21, 0 + .dw 0x79c0, 0xc009, 0x9fff, 0xc009, 0x21, 0 + .dw 0xa040, 0xc009, 0xa07f, 0xc009, 0x21, 0 + .dw 0xa0c0, 0xc009, 0xa0ff, 0xc009, 0x21, 0 + .dw 0xa140, 0xc009, 0xa17f, 0xc009, 0x21, 0 + .dw 0xa1c0, 0xc009, 0xa1ff, 0xc009, 0x21, 0 + .dw 0xa240, 0xc009, 0xa27f, 0xc009, 0x21, 0 + .dw 0xa2c0, 0xc009, 0xa2ff, 0xc009, 0x21, 0 + .dw 0xa340, 0xc009, 0xa37f, 0xc009, 0x21, 0 + .dw 0xa3c0, 0xc009, 0xa3ff, 0xc009, 0x21, 0 + .dw 0xa440, 0xc009, 0xa47f, 0xc009, 0x21, 0 + .dw 0xa4c0, 0xc009, 0xa4ff, 0xc009, 0x21, 0 + .dw 0xa540, 0xc009, 0xa57f, 0xc009, 0x21, 0 + .dw 0xa5c0, 0xc009, 0xa5ff, 0xc009, 0x21, 0 + .dw 0xa640, 0xc009, 0xa67f, 0xc009, 0x21, 0 + .dw 0xa6c0, 0xc009, 0xa6ff, 0xc009, 0x21, 0 + .dw 0xa740, 0xc009, 0xa77f, 0xc009, 0x21, 0 + .dw 0xa7c0, 0xc009, 0xa7ff, 0xc009, 0x21, 0 + .dw 0xa840, 0xc009, 0xa87f, 0xc009, 0x21, 0 + .dw 0xa8c0, 0xc009, 0xa8ff, 0xc009, 0x21, 0 + .dw 0xa940, 0xc009, 0xa97f, 0xc009, 0x21, 0 + .dw 0xa9c0, 0xc009, 0xa9ff, 0xc009, 0x21, 0 + .dw 0xaa40, 0xc009, 0xaa7f, 0xc009, 0x21, 0 + .dw 0xaac0, 0xc009, 0xaaff, 0xc009, 0x21, 0 + .dw 0xab40, 0xc009, 0xab7f, 0xc009, 0x21, 0 + .dw 0xabc0, 0xc009, 0xabff, 0xc009, 0x21, 0 + .dw 0xac40, 0xc009, 0xac7f, 0xc009, 0x21, 0 + .dw 0xacc0, 0xc009, 0xacff, 0xc009, 0x21, 0 + .dw 0xad40, 0xc009, 0xad7f, 0xc009, 0x21, 0 + .dw 0xadc0, 0xc009, 0xadff, 0xc009, 0x21, 0 + .dw 0xae40, 0xc009, 0xae7f, 0xc009, 0x21, 0 + .dw 0xaec0, 0xc009, 0xaeff, 0xc009, 0x21, 0 + .dw 0xaf40, 0xc009, 0xaf7f, 0xc009, 0x21, 0 + .dw 0xafc0, 0xc009, 0xafff, 0xc009, 0x21, 0 + .dw 0xb040, 0xc009, 0xb07f, 0xc009, 0x21, 0 + .dw 0xb0c0, 0xc009, 0xb0ff, 0xc009, 0x21, 0 + .dw 0xb140, 0xc009, 0xb17f, 0xc009, 0x21, 0 + .dw 0xb1c0, 0xc009, 0xb1ff, 0xc009, 0x21, 0 + .dw 0xb240, 0xc009, 0xb27f, 0xc009, 0x21, 0 + .dw 0xb2c0, 0xc009, 0xb2ff, 0xc009, 0x21, 0 + .dw 0xb340, 0xc009, 0xb37f, 0xc009, 0x21, 0 + .dw 0xb3c0, 0xc009, 0xb3ff, 0xc009, 0x21, 0 + .dw 0xb440, 0xc009, 0xb47f, 0xc009, 0x21, 0 + .dw 0xb4c0, 0xc009, 0xb4ff, 0xc009, 0x21, 0 + .dw 0xb540, 0xc009, 0xb57f, 0xc009, 0x21, 0 + .dw 0xb5c0, 0xc009, 0xb5ff, 0xc009, 0x21, 0 + .dw 0xb640, 0xc009, 0xb67f, 0xc009, 0x21, 0 + .dw 0xb6c0, 0xc009, 0xb6ff, 0xc009, 0x21, 0 + .dw 0xb740, 0xc009, 0xb77f, 0xc009, 0x21, 0 + .dw 0xb7c0, 0xc009, 0xb7ff, 0xc009, 0x21, 0 + .dw 0xb840, 0xc009, 0xb87f, 0xc009, 0x21, 0 + .dw 0xb8c0, 0xc009, 0xb8ff, 0xc009, 0x21, 0 + .dw 0xb940, 0xc009, 0xb97f, 0xc009, 0x21, 0 + .dw 0xb9c0, 0xc009, 0xdfff, 0xc009, 0x21, 0 + .dw 0xe040, 0xc009, 0xe07f, 0xc009, 0x21, 0 + .dw 0xe0c0, 0xc009, 0xe0ff, 0xc009, 0x21, 0 + .dw 0xe140, 0xc009, 0xe17f, 0xc009, 0x21, 0 + .dw 0xe1c0, 0xc009, 0xe1ff, 0xc009, 0x21, 0 + .dw 0xe240, 0xc009, 0xe27f, 0xc009, 0x21, 0 + .dw 0xe2c0, 0xc009, 0xe2ff, 0xc009, 0x21, 0 + .dw 0xe340, 0xc009, 0xe37f, 0xc009, 0x21, 0 + .dw 0xe3c0, 0xc009, 0xe3ff, 0xc009, 0x21, 0 + .dw 0xe440, 0xc009, 0xe47f, 0xc009, 0x21, 0 + .dw 0xe4c0, 0xc009, 0xe4ff, 0xc009, 0x21, 0 + .dw 0xe540, 0xc009, 0xe57f, 0xc009, 0x21, 0 + .dw 0xe5c0, 0xc009, 0xe5ff, 0xc009, 0x21, 0 + .dw 0xe640, 0xc009, 0xe67f, 0xc009, 0x21, 0 + .dw 0xe6c0, 0xc009, 0xe6ff, 0xc009, 0x21, 0 + .dw 0xe740, 0xc009, 0xe77f, 0xc009, 0x21, 0 + .dw 0xe7c0, 0xc009, 0xe7ff, 0xc009, 0x21, 0 + .dw 0xe840, 0xc009, 0xe87f, 0xc009, 0x21, 0 + .dw 0xe8c0, 0xc009, 0xe8ff, 0xc009, 0x21, 0 + .dw 0xe940, 0xc009, 0xe97f, 0xc009, 0x21, 0 + .dw 0xe9c0, 0xc009, 0xe9ff, 0xc009, 0x21, 0 + .dw 0xea40, 0xc009, 0xea7f, 0xc009, 0x21, 0 + .dw 0xeac0, 0xc009, 0xeaff, 0xc009, 0x21, 0 + .dw 0xeb40, 0xc009, 0xeb7f, 0xc009, 0x21, 0 + .dw 0xebc0, 0xc009, 0xebff, 0xc009, 0x21, 0 + .dw 0xec40, 0xc009, 0xec7f, 0xc009, 0x21, 0 + .dw 0xecc0, 0xc009, 0xecff, 0xc009, 0x21, 0 + .dw 0xed40, 0xc009, 0xed7f, 0xc009, 0x21, 0 + .dw 0xedc0, 0xc009, 0xedff, 0xc009, 0x21, 0 + .dw 0xee40, 0xc009, 0xee7f, 0xc009, 0x21, 0 + .dw 0xeec0, 0xc009, 0xeeff, 0xc009, 0x21, 0 + .dw 0xef40, 0xc009, 0xef7f, 0xc009, 0x21, 0 + .dw 0xefc0, 0xc009, 0xefff, 0xc009, 0x21, 0 + .dw 0xf040, 0xc009, 0xf07f, 0xc009, 0x21, 0 + .dw 0xf0c0, 0xc009, 0xf0ff, 0xc009, 0x21, 0 + .dw 0xf140, 0xc009, 0xf17f, 0xc009, 0x21, 0 + .dw 0xf1c0, 0xc009, 0xf1ff, 0xc009, 0x21, 0 + .dw 0xf240, 0xc009, 0xf27f, 0xc009, 0x21, 0 + .dw 0xf2c0, 0xc009, 0xf2ff, 0xc009, 0x21, 0 + .dw 0xf340, 0xc009, 0xf37f, 0xc009, 0x21, 0 + .dw 0xf3c0, 0xc009, 0xf3ff, 0xc009, 0x21, 0 + .dw 0xf440, 0xc009, 0xf47f, 0xc009, 0x21, 0 + .dw 0xf4c0, 0xc009, 0xf4ff, 0xc009, 0x21, 0 + .dw 0xf540, 0xc009, 0xf57f, 0xc009, 0x21, 0 + .dw 0xf5c0, 0xc009, 0xf5ff, 0xc009, 0x21, 0 + .dw 0xf640, 0xc009, 0xf67f, 0xc009, 0x21, 0 + .dw 0xf6c0, 0xc009, 0xf6ff, 0xc009, 0x21, 0 + .dw 0xf740, 0xc009, 0xf77f, 0xc009, 0x21, 0 + .dw 0xf7c0, 0xc009, 0xf7ff, 0xc009, 0x21, 0 + .dw 0xf840, 0xc009, 0xf87f, 0xc009, 0x21, 0 + .dw 0xf8c0, 0xc009, 0xf8ff, 0xc009, 0x21, 0 + .dw 0xf940, 0xc009, 0xf97f, 0xc009, 0x21, 0 + .dw 0xf9c0, 0xc009, 0x1fff, 0xc00a, 0x21, 0 + .dw 0x2040, 0xc00a, 0x207f, 0xc00a, 0x21, 0 + .dw 0x20c0, 0xc00a, 0x20ff, 0xc00a, 0x21, 0 + .dw 0x2140, 0xc00a, 0x217f, 0xc00a, 0x21, 0 + .dw 0x21c0, 0xc00a, 0x21ff, 0xc00a, 0x21, 0 + .dw 0x2240, 0xc00a, 0x227f, 0xc00a, 0x21, 0 + .dw 0x22c0, 0xc00a, 0x22ff, 0xc00a, 0x21, 0 + .dw 0x2340, 0xc00a, 0x237f, 0xc00a, 0x21, 0 + .dw 0x23c0, 0xc00a, 0x23ff, 0xc00a, 0x21, 0 + .dw 0x2440, 0xc00a, 0x247f, 0xc00a, 0x21, 0 + .dw 0x24c0, 0xc00a, 0x24ff, 0xc00a, 0x21, 0 + .dw 0x2540, 0xc00a, 0x257f, 0xc00a, 0x21, 0 + .dw 0x25c0, 0xc00a, 0x25ff, 0xc00a, 0x21, 0 + .dw 0x2640, 0xc00a, 0x267f, 0xc00a, 0x21, 0 + .dw 0x26c0, 0xc00a, 0x26ff, 0xc00a, 0x21, 0 + .dw 0x2740, 0xc00a, 0x277f, 0xc00a, 0x21, 0 + .dw 0x27c0, 0xc00a, 0x27ff, 0xc00a, 0x21, 0 + .dw 0x2840, 0xc00a, 0x287f, 0xc00a, 0x21, 0 + .dw 0x28c0, 0xc00a, 0x28ff, 0xc00a, 0x21, 0 + .dw 0x2940, 0xc00a, 0x297f, 0xc00a, 0x21, 0 + .dw 0x29c0, 0xc00a, 0x29ff, 0xc00a, 0x21, 0 + .dw 0x2a40, 0xc00a, 0x2a7f, 0xc00a, 0x21, 0 + .dw 0x2ac0, 0xc00a, 0x2aff, 0xc00a, 0x21, 0 + .dw 0x2b40, 0xc00a, 0x2b7f, 0xc00a, 0x21, 0 + .dw 0x2bc0, 0xc00a, 0x2bff, 0xc00a, 0x21, 0 + .dw 0x2c40, 0xc00a, 0x2c7f, 0xc00a, 0x21, 0 + .dw 0x2cc0, 0xc00a, 0x2cff, 0xc00a, 0x21, 0 + .dw 0x2d40, 0xc00a, 0x2d7f, 0xc00a, 0x21, 0 + .dw 0x2dc0, 0xc00a, 0x2dff, 0xc00a, 0x21, 0 + .dw 0x2e40, 0xc00a, 0x2e7f, 0xc00a, 0x21, 0 + .dw 0x2ec0, 0xc00a, 0x2eff, 0xc00a, 0x21, 0 + .dw 0x2f40, 0xc00a, 0x2f7f, 0xc00a, 0x21, 0 + .dw 0x2fc0, 0xc00a, 0x2fff, 0xc00a, 0x21, 0 + .dw 0x3040, 0xc00a, 0x307f, 0xc00a, 0x21, 0 + .dw 0x30c0, 0xc00a, 0x30ff, 0xc00a, 0x21, 0 + .dw 0x3140, 0xc00a, 0x317f, 0xc00a, 0x21, 0 + .dw 0x31c0, 0xc00a, 0x31ff, 0xc00a, 0x21, 0 + .dw 0x3240, 0xc00a, 0x327f, 0xc00a, 0x21, 0 + .dw 0x32c0, 0xc00a, 0x32ff, 0xc00a, 0x21, 0 + .dw 0x3340, 0xc00a, 0x337f, 0xc00a, 0x21, 0 + .dw 0x33c0, 0xc00a, 0x33ff, 0xc00a, 0x21, 0 + .dw 0x3440, 0xc00a, 0x347f, 0xc00a, 0x21, 0 + .dw 0x34c0, 0xc00a, 0x34ff, 0xc00a, 0x21, 0 + .dw 0x3540, 0xc00a, 0x357f, 0xc00a, 0x21, 0 + .dw 0x35c0, 0xc00a, 0x35ff, 0xc00a, 0x21, 0 + .dw 0x3640, 0xc00a, 0x367f, 0xc00a, 0x21, 0 + .dw 0x36c0, 0xc00a, 0x36ff, 0xc00a, 0x21, 0 + .dw 0x3740, 0xc00a, 0x377f, 0xc00a, 0x21, 0 + .dw 0x37c0, 0xc00a, 0x37ff, 0xc00a, 0x21, 0 + .dw 0x3840, 0xc00a, 0x387f, 0xc00a, 0x21, 0 + .dw 0x38c0, 0xc00a, 0x38ff, 0xc00a, 0x21, 0 + .dw 0x3940, 0xc00a, 0x397f, 0xc00a, 0x21, 0 + .dw 0x39c0, 0xc00a, 0x5fff, 0xc00a, 0x21, 0 + .dw 0x6040, 0xc00a, 0x607f, 0xc00a, 0x21, 0 + .dw 0x60c0, 0xc00a, 0x60ff, 0xc00a, 0x21, 0 + .dw 0x6140, 0xc00a, 0x617f, 0xc00a, 0x21, 0 + .dw 0x61c0, 0xc00a, 0x61ff, 0xc00a, 0x21, 0 + .dw 0x6240, 0xc00a, 0x627f, 0xc00a, 0x21, 0 + .dw 0x62c0, 0xc00a, 0x62ff, 0xc00a, 0x21, 0 + .dw 0x6340, 0xc00a, 0x637f, 0xc00a, 0x21, 0 + .dw 0x63c0, 0xc00a, 0x63ff, 0xc00a, 0x21, 0 + .dw 0x6440, 0xc00a, 0x647f, 0xc00a, 0x21, 0 + .dw 0x64c0, 0xc00a, 0x64ff, 0xc00a, 0x21, 0 + .dw 0x6540, 0xc00a, 0x657f, 0xc00a, 0x21, 0 + .dw 0x65c0, 0xc00a, 0x65ff, 0xc00a, 0x21, 0 + .dw 0x6640, 0xc00a, 0x667f, 0xc00a, 0x21, 0 + .dw 0x66c0, 0xc00a, 0x66ff, 0xc00a, 0x21, 0 + .dw 0x6740, 0xc00a, 0x677f, 0xc00a, 0x21, 0 + .dw 0x67c0, 0xc00a, 0x67ff, 0xc00a, 0x21, 0 + .dw 0x6840, 0xc00a, 0x687f, 0xc00a, 0x21, 0 + .dw 0x68c0, 0xc00a, 0x68ff, 0xc00a, 0x21, 0 + .dw 0x6940, 0xc00a, 0x697f, 0xc00a, 0x21, 0 + .dw 0x69c0, 0xc00a, 0x69ff, 0xc00a, 0x21, 0 + .dw 0x6a40, 0xc00a, 0x6a7f, 0xc00a, 0x21, 0 + .dw 0x6ac0, 0xc00a, 0x6aff, 0xc00a, 0x21, 0 + .dw 0x6b40, 0xc00a, 0x6b7f, 0xc00a, 0x21, 0 + .dw 0x6bc0, 0xc00a, 0x6bff, 0xc00a, 0x21, 0 + .dw 0x6c40, 0xc00a, 0x6c7f, 0xc00a, 0x21, 0 + .dw 0x6cc0, 0xc00a, 0x6cff, 0xc00a, 0x21, 0 + .dw 0x6d40, 0xc00a, 0x6d7f, 0xc00a, 0x21, 0 + .dw 0x6dc0, 0xc00a, 0x6dff, 0xc00a, 0x21, 0 + .dw 0x6e40, 0xc00a, 0x6e7f, 0xc00a, 0x21, 0 + .dw 0x6ec0, 0xc00a, 0x6eff, 0xc00a, 0x21, 0 + .dw 0x6f40, 0xc00a, 0x6f7f, 0xc00a, 0x21, 0 + .dw 0x6fc0, 0xc00a, 0x6fff, 0xc00a, 0x21, 0 + .dw 0x7040, 0xc00a, 0x707f, 0xc00a, 0x21, 0 + .dw 0x70c0, 0xc00a, 0x70ff, 0xc00a, 0x21, 0 + .dw 0x7140, 0xc00a, 0x717f, 0xc00a, 0x21, 0 + .dw 0x71c0, 0xc00a, 0x71ff, 0xc00a, 0x21, 0 + .dw 0x7240, 0xc00a, 0x727f, 0xc00a, 0x21, 0 + .dw 0x72c0, 0xc00a, 0x72ff, 0xc00a, 0x21, 0 + .dw 0x7340, 0xc00a, 0x737f, 0xc00a, 0x21, 0 + .dw 0x73c0, 0xc00a, 0x73ff, 0xc00a, 0x21, 0 + .dw 0x7440, 0xc00a, 0x747f, 0xc00a, 0x21, 0 + .dw 0x74c0, 0xc00a, 0x74ff, 0xc00a, 0x21, 0 + .dw 0x7540, 0xc00a, 0x757f, 0xc00a, 0x21, 0 + .dw 0x75c0, 0xc00a, 0x75ff, 0xc00a, 0x21, 0 + .dw 0x7640, 0xc00a, 0x767f, 0xc00a, 0x21, 0 + .dw 0x76c0, 0xc00a, 0x76ff, 0xc00a, 0x21, 0 + .dw 0x7740, 0xc00a, 0x777f, 0xc00a, 0x21, 0 + .dw 0x77c0, 0xc00a, 0x77ff, 0xc00a, 0x21, 0 + .dw 0x7840, 0xc00a, 0x787f, 0xc00a, 0x21, 0 + .dw 0x78c0, 0xc00a, 0x78ff, 0xc00a, 0x21, 0 + .dw 0x7940, 0xc00a, 0x797f, 0xc00a, 0x21, 0 + .dw 0x79c0, 0xc00a, 0x9fff, 0xc00a, 0x21, 0 + .dw 0xa040, 0xc00a, 0xa07f, 0xc00a, 0x21, 0 + .dw 0xa0c0, 0xc00a, 0xa0ff, 0xc00a, 0x21, 0 + .dw 0xa140, 0xc00a, 0xa17f, 0xc00a, 0x21, 0 + .dw 0xa1c0, 0xc00a, 0xa1ff, 0xc00a, 0x21, 0 + .dw 0xa240, 0xc00a, 0xa27f, 0xc00a, 0x21, 0 + .dw 0xa2c0, 0xc00a, 0xa2ff, 0xc00a, 0x21, 0 + .dw 0xa340, 0xc00a, 0xa37f, 0xc00a, 0x21, 0 + .dw 0xa3c0, 0xc00a, 0xa3ff, 0xc00a, 0x21, 0 + .dw 0xa440, 0xc00a, 0xa47f, 0xc00a, 0x21, 0 + .dw 0xa4c0, 0xc00a, 0xa4ff, 0xc00a, 0x21, 0 + .dw 0xa540, 0xc00a, 0xa57f, 0xc00a, 0x21, 0 + .dw 0xa5c0, 0xc00a, 0xa5ff, 0xc00a, 0x21, 0 + .dw 0xa640, 0xc00a, 0xa67f, 0xc00a, 0x21, 0 + .dw 0xa6c0, 0xc00a, 0xa6ff, 0xc00a, 0x21, 0 + .dw 0xa740, 0xc00a, 0xa77f, 0xc00a, 0x21, 0 + .dw 0xa7c0, 0xc00a, 0xa7ff, 0xc00a, 0x21, 0 + .dw 0xa840, 0xc00a, 0xa87f, 0xc00a, 0x21, 0 + .dw 0xa8c0, 0xc00a, 0xa8ff, 0xc00a, 0x21, 0 + .dw 0xa940, 0xc00a, 0xa97f, 0xc00a, 0x21, 0 + .dw 0xa9c0, 0xc00a, 0xa9ff, 0xc00a, 0x21, 0 + .dw 0xaa40, 0xc00a, 0xaa7f, 0xc00a, 0x21, 0 + .dw 0xaac0, 0xc00a, 0xaaff, 0xc00a, 0x21, 0 + .dw 0xab40, 0xc00a, 0xab7f, 0xc00a, 0x21, 0 + .dw 0xabc0, 0xc00a, 0xabff, 0xc00a, 0x21, 0 + .dw 0xac40, 0xc00a, 0xac7f, 0xc00a, 0x21, 0 + .dw 0xacc0, 0xc00a, 0xacff, 0xc00a, 0x21, 0 + .dw 0xad40, 0xc00a, 0xad7f, 0xc00a, 0x21, 0 + .dw 0xadc0, 0xc00a, 0xadff, 0xc00a, 0x21, 0 + .dw 0xae40, 0xc00a, 0xae7f, 0xc00a, 0x21, 0 + .dw 0xaec0, 0xc00a, 0xaeff, 0xc00a, 0x21, 0 + .dw 0xaf40, 0xc00a, 0xaf7f, 0xc00a, 0x21, 0 + .dw 0xafc0, 0xc00a, 0xafff, 0xc00a, 0x21, 0 + .dw 0xb040, 0xc00a, 0xb07f, 0xc00a, 0x21, 0 + .dw 0xb0c0, 0xc00a, 0xb0ff, 0xc00a, 0x21, 0 + .dw 0xb140, 0xc00a, 0xb17f, 0xc00a, 0x21, 0 + .dw 0xb1c0, 0xc00a, 0xb1ff, 0xc00a, 0x21, 0 + .dw 0xb240, 0xc00a, 0xb27f, 0xc00a, 0x21, 0 + .dw 0xb2c0, 0xc00a, 0xb2ff, 0xc00a, 0x21, 0 + .dw 0xb340, 0xc00a, 0xb37f, 0xc00a, 0x21, 0 + .dw 0xb3c0, 0xc00a, 0xb3ff, 0xc00a, 0x21, 0 + .dw 0xb440, 0xc00a, 0xb47f, 0xc00a, 0x21, 0 + .dw 0xb4c0, 0xc00a, 0xb4ff, 0xc00a, 0x21, 0 + .dw 0xb540, 0xc00a, 0xb57f, 0xc00a, 0x21, 0 + .dw 0xb5c0, 0xc00a, 0xb5ff, 0xc00a, 0x21, 0 + .dw 0xb640, 0xc00a, 0xb67f, 0xc00a, 0x21, 0 + .dw 0xb6c0, 0xc00a, 0xb6ff, 0xc00a, 0x21, 0 + .dw 0xb740, 0xc00a, 0xb77f, 0xc00a, 0x21, 0 + .dw 0xb7c0, 0xc00a, 0xb7ff, 0xc00a, 0x21, 0 + .dw 0xb840, 0xc00a, 0xb87f, 0xc00a, 0x21, 0 + .dw 0xb8c0, 0xc00a, 0xb8ff, 0xc00a, 0x21, 0 + .dw 0xb940, 0xc00a, 0xb97f, 0xc00a, 0x21, 0 + .dw 0xb9c0, 0xc00a, 0xdfff, 0xc00a, 0x21, 0 + .dw 0xe040, 0xc00a, 0xe07f, 0xc00a, 0x21, 0 + .dw 0xe0c0, 0xc00a, 0xe0ff, 0xc00a, 0x21, 0 + .dw 0xe140, 0xc00a, 0xe17f, 0xc00a, 0x21, 0 + .dw 0xe1c0, 0xc00a, 0xe1ff, 0xc00a, 0x21, 0 + .dw 0xe240, 0xc00a, 0xe27f, 0xc00a, 0x21, 0 + .dw 0xe2c0, 0xc00a, 0xe2ff, 0xc00a, 0x21, 0 + .dw 0xe340, 0xc00a, 0xe37f, 0xc00a, 0x21, 0 + .dw 0xe3c0, 0xc00a, 0xe3ff, 0xc00a, 0x21, 0 + .dw 0xe440, 0xc00a, 0xe47f, 0xc00a, 0x21, 0 + .dw 0xe4c0, 0xc00a, 0xe4ff, 0xc00a, 0x21, 0 + .dw 0xe540, 0xc00a, 0xe57f, 0xc00a, 0x21, 0 + .dw 0xe5c0, 0xc00a, 0xe5ff, 0xc00a, 0x21, 0 + .dw 0xe640, 0xc00a, 0xe67f, 0xc00a, 0x21, 0 + .dw 0xe6c0, 0xc00a, 0xe6ff, 0xc00a, 0x21, 0 + .dw 0xe740, 0xc00a, 0xe77f, 0xc00a, 0x21, 0 + .dw 0xe7c0, 0xc00a, 0xe7ff, 0xc00a, 0x21, 0 + .dw 0xe840, 0xc00a, 0xe87f, 0xc00a, 0x21, 0 + .dw 0xe8c0, 0xc00a, 0xe8ff, 0xc00a, 0x21, 0 + .dw 0xe940, 0xc00a, 0xe97f, 0xc00a, 0x21, 0 + .dw 0xe9c0, 0xc00a, 0xe9ff, 0xc00a, 0x21, 0 + .dw 0xea40, 0xc00a, 0xea7f, 0xc00a, 0x21, 0 + .dw 0xeac0, 0xc00a, 0xeaff, 0xc00a, 0x21, 0 + .dw 0xeb40, 0xc00a, 0xeb7f, 0xc00a, 0x21, 0 + .dw 0xebc0, 0xc00a, 0xebff, 0xc00a, 0x21, 0 + .dw 0xec40, 0xc00a, 0xec7f, 0xc00a, 0x21, 0 + .dw 0xecc0, 0xc00a, 0xecff, 0xc00a, 0x21, 0 + .dw 0xed40, 0xc00a, 0xed7f, 0xc00a, 0x21, 0 + .dw 0xedc0, 0xc00a, 0xedff, 0xc00a, 0x21, 0 + .dw 0xee40, 0xc00a, 0xee7f, 0xc00a, 0x21, 0 + .dw 0xeec0, 0xc00a, 0xeeff, 0xc00a, 0x21, 0 + .dw 0xef40, 0xc00a, 0xef7f, 0xc00a, 0x21, 0 + .dw 0xefc0, 0xc00a, 0xefff, 0xc00a, 0x21, 0 + .dw 0xf040, 0xc00a, 0xf07f, 0xc00a, 0x21, 0 + .dw 0xf0c0, 0xc00a, 0xf0ff, 0xc00a, 0x21, 0 + .dw 0xf140, 0xc00a, 0xf17f, 0xc00a, 0x21, 0 + .dw 0xf1c0, 0xc00a, 0xf1ff, 0xc00a, 0x21, 0 + .dw 0xf240, 0xc00a, 0xf27f, 0xc00a, 0x21, 0 + .dw 0xf2c0, 0xc00a, 0xf2ff, 0xc00a, 0x21, 0 + .dw 0xf340, 0xc00a, 0xf37f, 0xc00a, 0x21, 0 + .dw 0xf3c0, 0xc00a, 0xf3ff, 0xc00a, 0x21, 0 + .dw 0xf440, 0xc00a, 0xf47f, 0xc00a, 0x21, 0 + .dw 0xf4c0, 0xc00a, 0xf4ff, 0xc00a, 0x21, 0 + .dw 0xf540, 0xc00a, 0xf57f, 0xc00a, 0x21, 0 + .dw 0xf5c0, 0xc00a, 0xf5ff, 0xc00a, 0x21, 0 + .dw 0xf640, 0xc00a, 0xf67f, 0xc00a, 0x21, 0 + .dw 0xf6c0, 0xc00a, 0xf6ff, 0xc00a, 0x21, 0 + .dw 0xf740, 0xc00a, 0xf77f, 0xc00a, 0x21, 0 + .dw 0xf7c0, 0xc00a, 0xf7ff, 0xc00a, 0x21, 0 + .dw 0xf840, 0xc00a, 0xf87f, 0xc00a, 0x21, 0 + .dw 0xf8c0, 0xc00a, 0xf8ff, 0xc00a, 0x21, 0 + .dw 0xf940, 0xc00a, 0xf97f, 0xc00a, 0x21, 0 + .dw 0xf9c0, 0xc00a, 0x1fff, 0xc00b, 0x21, 0 + .dw 0x2040, 0xc00b, 0x207f, 0xc00b, 0x21, 0 + .dw 0x20c0, 0xc00b, 0x20ff, 0xc00b, 0x21, 0 + .dw 0x2140, 0xc00b, 0x217f, 0xc00b, 0x21, 0 + .dw 0x21c0, 0xc00b, 0x21ff, 0xc00b, 0x21, 0 + .dw 0x2240, 0xc00b, 0x227f, 0xc00b, 0x21, 0 + .dw 0x22c0, 0xc00b, 0x22ff, 0xc00b, 0x21, 0 + .dw 0x2340, 0xc00b, 0x237f, 0xc00b, 0x21, 0 + .dw 0x23c0, 0xc00b, 0x23ff, 0xc00b, 0x21, 0 + .dw 0x2440, 0xc00b, 0x247f, 0xc00b, 0x21, 0 + .dw 0x24c0, 0xc00b, 0x24ff, 0xc00b, 0x21, 0 + .dw 0x2540, 0xc00b, 0x257f, 0xc00b, 0x21, 0 + .dw 0x25c0, 0xc00b, 0x25ff, 0xc00b, 0x21, 0 + .dw 0x2640, 0xc00b, 0x267f, 0xc00b, 0x21, 0 + .dw 0x26c0, 0xc00b, 0x26ff, 0xc00b, 0x21, 0 + .dw 0x2740, 0xc00b, 0x277f, 0xc00b, 0x21, 0 + .dw 0x27c0, 0xc00b, 0x27ff, 0xc00b, 0x21, 0 + .dw 0x2840, 0xc00b, 0x287f, 0xc00b, 0x21, 0 + .dw 0x28c0, 0xc00b, 0x28ff, 0xc00b, 0x21, 0 + .dw 0x2940, 0xc00b, 0x297f, 0xc00b, 0x21, 0 + .dw 0x29c0, 0xc00b, 0x29ff, 0xc00b, 0x21, 0 + .dw 0x2a40, 0xc00b, 0x2a7f, 0xc00b, 0x21, 0 + .dw 0x2ac0, 0xc00b, 0x2aff, 0xc00b, 0x21, 0 + .dw 0x2b40, 0xc00b, 0x2b7f, 0xc00b, 0x21, 0 + .dw 0x2bc0, 0xc00b, 0x2bff, 0xc00b, 0x21, 0 + .dw 0x2c40, 0xc00b, 0x2c7f, 0xc00b, 0x21, 0 + .dw 0x2cc0, 0xc00b, 0x2cff, 0xc00b, 0x21, 0 + .dw 0x2d40, 0xc00b, 0x2d7f, 0xc00b, 0x21, 0 + .dw 0x2dc0, 0xc00b, 0x2dff, 0xc00b, 0x21, 0 + .dw 0x2e40, 0xc00b, 0x2e7f, 0xc00b, 0x21, 0 + .dw 0x2ec0, 0xc00b, 0x2eff, 0xc00b, 0x21, 0 + .dw 0x2f40, 0xc00b, 0x2f7f, 0xc00b, 0x21, 0 + .dw 0x2fc0, 0xc00b, 0x2fff, 0xc00b, 0x21, 0 + .dw 0x3040, 0xc00b, 0x307f, 0xc00b, 0x21, 0 + .dw 0x30c0, 0xc00b, 0x30ff, 0xc00b, 0x21, 0 + .dw 0x3140, 0xc00b, 0x317f, 0xc00b, 0x21, 0 + .dw 0x31c0, 0xc00b, 0x31ff, 0xc00b, 0x21, 0 + .dw 0x3240, 0xc00b, 0x327f, 0xc00b, 0x21, 0 + .dw 0x32c0, 0xc00b, 0x32ff, 0xc00b, 0x21, 0 + .dw 0x3340, 0xc00b, 0x337f, 0xc00b, 0x21, 0 + .dw 0x33c0, 0xc00b, 0x33ff, 0xc00b, 0x21, 0 + .dw 0x3440, 0xc00b, 0x347f, 0xc00b, 0x21, 0 + .dw 0x34c0, 0xc00b, 0x34ff, 0xc00b, 0x21, 0 + .dw 0x3540, 0xc00b, 0x357f, 0xc00b, 0x21, 0 + .dw 0x35c0, 0xc00b, 0x35ff, 0xc00b, 0x21, 0 + .dw 0x3640, 0xc00b, 0x367f, 0xc00b, 0x21, 0 + .dw 0x36c0, 0xc00b, 0x36ff, 0xc00b, 0x21, 0 + .dw 0x3740, 0xc00b, 0x377f, 0xc00b, 0x21, 0 + .dw 0x37c0, 0xc00b, 0x37ff, 0xc00b, 0x21, 0 + .dw 0x3840, 0xc00b, 0x387f, 0xc00b, 0x21, 0 + .dw 0x38c0, 0xc00b, 0x38ff, 0xc00b, 0x21, 0 + .dw 0x3940, 0xc00b, 0x397f, 0xc00b, 0x21, 0 + .dw 0x39c0, 0xc00b, 0xffff, 0xc00b, 0x21, 0 + .dw 0x0040, 0xc00c, 0x007f, 0xc00c, 0x21, 0 + .dw 0x00c0, 0xc00c, 0x00ff, 0xc00c, 0x21, 0 + .dw 0x0140, 0xc00c, 0x017f, 0xc00c, 0x21, 0 + .dw 0x01c0, 0xc00c, 0x01ff, 0xc00c, 0x21, 0 + .dw 0x0240, 0xc00c, 0x027f, 0xc00c, 0x21, 0 + .dw 0x02c0, 0xc00c, 0x02ff, 0xc00c, 0x21, 0 + .dw 0x0340, 0xc00c, 0x037f, 0xc00c, 0x21, 0 + .dw 0x03c0, 0xc00c, 0x03ff, 0xc00c, 0x21, 0 + .dw 0x0440, 0xc00c, 0x047f, 0xc00c, 0x21, 0 + .dw 0x04c0, 0xc00c, 0x04ff, 0xc00c, 0x21, 0 + .dw 0x0540, 0xc00c, 0x057f, 0xc00c, 0x21, 0 + .dw 0x05c0, 0xc00c, 0x05ff, 0xc00c, 0x21, 0 + .dw 0x0640, 0xc00c, 0x067f, 0xc00c, 0x21, 0 + .dw 0x06c0, 0xc00c, 0x06ff, 0xc00c, 0x21, 0 + .dw 0x0740, 0xc00c, 0x077f, 0xc00c, 0x21, 0 + .dw 0x07c0, 0xc00c, 0x07ff, 0xc00c, 0x21, 0 + .dw 0x0840, 0xc00c, 0x087f, 0xc00c, 0x21, 0 + .dw 0x08c0, 0xc00c, 0x08ff, 0xc00c, 0x21, 0 + .dw 0x0940, 0xc00c, 0x097f, 0xc00c, 0x21, 0 + .dw 0x09c0, 0xc00c, 0x09ff, 0xc00c, 0x21, 0 + .dw 0x0a40, 0xc00c, 0x0a7f, 0xc00c, 0x21, 0 + .dw 0x0ac0, 0xc00c, 0x0aff, 0xc00c, 0x21, 0 + .dw 0x0b40, 0xc00c, 0x0b7f, 0xc00c, 0x21, 0 + .dw 0x0bc0, 0xc00c, 0x0bff, 0xc00c, 0x21, 0 + .dw 0x0c40, 0xc00c, 0x0c7f, 0xc00c, 0x21, 0 + .dw 0x0cc0, 0xc00c, 0x0cff, 0xc00c, 0x21, 0 + .dw 0x0d40, 0xc00c, 0x0d7f, 0xc00c, 0x21, 0 + .dw 0x0dc0, 0xc00c, 0x0dff, 0xc00c, 0x21, 0 + .dw 0x0e40, 0xc00c, 0x0e7f, 0xc00c, 0x21, 0 + .dw 0x0ec0, 0xc00c, 0x0eff, 0xc00c, 0x21, 0 + .dw 0x0f40, 0xc00c, 0x0f7f, 0xc00c, 0x21, 0 + .dw 0x0fc0, 0xc00c, 0x0fff, 0xc00c, 0x21, 0 + .dw 0x1040, 0xc00c, 0x107f, 0xc00c, 0x21, 0 + .dw 0x10c0, 0xc00c, 0x10ff, 0xc00c, 0x21, 0 + .dw 0x1140, 0xc00c, 0x117f, 0xc00c, 0x21, 0 + .dw 0x11c0, 0xc00c, 0x11ff, 0xc00c, 0x21, 0 + .dw 0x1240, 0xc00c, 0x127f, 0xc00c, 0x21, 0 + .dw 0x12c0, 0xc00c, 0x12ff, 0xc00c, 0x21, 0 + .dw 0x1340, 0xc00c, 0x137f, 0xc00c, 0x21, 0 + .dw 0x13c0, 0xc00c, 0x13ff, 0xc00c, 0x21, 0 + .dw 0x1440, 0xc00c, 0x147f, 0xc00c, 0x21, 0 + .dw 0x14c0, 0xc00c, 0x14ff, 0xc00c, 0x21, 0 + .dw 0x1540, 0xc00c, 0x157f, 0xc00c, 0x21, 0 + .dw 0x15c0, 0xc00c, 0x15ff, 0xc00c, 0x21, 0 + .dw 0x1640, 0xc00c, 0x167f, 0xc00c, 0x21, 0 + .dw 0x16c0, 0xc00c, 0x16ff, 0xc00c, 0x21, 0 + .dw 0x1740, 0xc00c, 0x177f, 0xc00c, 0x21, 0 + .dw 0x17c0, 0xc00c, 0x17ff, 0xc00c, 0x21, 0 + .dw 0x1840, 0xc00c, 0x187f, 0xc00c, 0x21, 0 + .dw 0x18c0, 0xc00c, 0x18ff, 0xc00c, 0x21, 0 + .dw 0x1940, 0xc00c, 0x197f, 0xc00c, 0x21, 0 + .dw 0x19c0, 0xc00c, 0x1fff, 0xc00c, 0x21, 0 + .dw 0x2040, 0xc00c, 0x207f, 0xc00c, 0x21, 0 + .dw 0x20c0, 0xc00c, 0x20ff, 0xc00c, 0x21, 0 + .dw 0x2140, 0xc00c, 0x217f, 0xc00c, 0x21, 0 + .dw 0x21c0, 0xc00c, 0x21ff, 0xc00c, 0x21, 0 + .dw 0x2240, 0xc00c, 0x227f, 0xc00c, 0x21, 0 + .dw 0x22c0, 0xc00c, 0x22ff, 0xc00c, 0x21, 0 + .dw 0x2340, 0xc00c, 0x237f, 0xc00c, 0x21, 0 + .dw 0x23c0, 0xc00c, 0x23ff, 0xc00c, 0x21, 0 + .dw 0x2440, 0xc00c, 0x247f, 0xc00c, 0x21, 0 + .dw 0x24c0, 0xc00c, 0x24ff, 0xc00c, 0x21, 0 + .dw 0x2540, 0xc00c, 0x257f, 0xc00c, 0x21, 0 + .dw 0x25c0, 0xc00c, 0x25ff, 0xc00c, 0x21, 0 + .dw 0x2640, 0xc00c, 0x267f, 0xc00c, 0x21, 0 + .dw 0x26c0, 0xc00c, 0x26ff, 0xc00c, 0x21, 0 + .dw 0x2740, 0xc00c, 0x277f, 0xc00c, 0x21, 0 + .dw 0x27c0, 0xc00c, 0x27ff, 0xc00c, 0x21, 0 + .dw 0x2840, 0xc00c, 0x287f, 0xc00c, 0x21, 0 + .dw 0x28c0, 0xc00c, 0x28ff, 0xc00c, 0x21, 0 + .dw 0x2940, 0xc00c, 0x297f, 0xc00c, 0x21, 0 + .dw 0x29c0, 0xc00c, 0x29ff, 0xc00c, 0x21, 0 + .dw 0x2a40, 0xc00c, 0x2a7f, 0xc00c, 0x21, 0 + .dw 0x2ac0, 0xc00c, 0x2aff, 0xc00c, 0x21, 0 + .dw 0x2b40, 0xc00c, 0x2b7f, 0xc00c, 0x21, 0 + .dw 0x2bc0, 0xc00c, 0x2bff, 0xc00c, 0x21, 0 + .dw 0x2c40, 0xc00c, 0x2c7f, 0xc00c, 0x21, 0 + .dw 0x2cc0, 0xc00c, 0x2cff, 0xc00c, 0x21, 0 + .dw 0x2d40, 0xc00c, 0x2d7f, 0xc00c, 0x21, 0 + .dw 0x2dc0, 0xc00c, 0x2dff, 0xc00c, 0x21, 0 + .dw 0x2e40, 0xc00c, 0x2e7f, 0xc00c, 0x21, 0 + .dw 0x2ec0, 0xc00c, 0x2eff, 0xc00c, 0x21, 0 + .dw 0x2f40, 0xc00c, 0x2f7f, 0xc00c, 0x21, 0 + .dw 0x2fc0, 0xc00c, 0x2fff, 0xc00c, 0x21, 0 + .dw 0x3040, 0xc00c, 0x307f, 0xc00c, 0x21, 0 + .dw 0x30c0, 0xc00c, 0x30ff, 0xc00c, 0x21, 0 + .dw 0x3140, 0xc00c, 0x317f, 0xc00c, 0x21, 0 + .dw 0x31c0, 0xc00c, 0x31ff, 0xc00c, 0x21, 0 + .dw 0x3240, 0xc00c, 0x327f, 0xc00c, 0x21, 0 + .dw 0x32c0, 0xc00c, 0x32ff, 0xc00c, 0x21, 0 + .dw 0x3340, 0xc00c, 0x337f, 0xc00c, 0x21, 0 + .dw 0x33c0, 0xc00c, 0x33ff, 0xc00c, 0x21, 0 + .dw 0x3440, 0xc00c, 0x347f, 0xc00c, 0x21, 0 + .dw 0x34c0, 0xc00c, 0x34ff, 0xc00c, 0x21, 0 + .dw 0x3540, 0xc00c, 0x357f, 0xc00c, 0x21, 0 + .dw 0x35c0, 0xc00c, 0x35ff, 0xc00c, 0x21, 0 + .dw 0x3640, 0xc00c, 0x367f, 0xc00c, 0x21, 0 + .dw 0x36c0, 0xc00c, 0x36ff, 0xc00c, 0x21, 0 + .dw 0x3740, 0xc00c, 0x377f, 0xc00c, 0x21, 0 + .dw 0x37c0, 0xc00c, 0x37ff, 0xc00c, 0x21, 0 + .dw 0x3840, 0xc00c, 0x387f, 0xc00c, 0x21, 0 + .dw 0x38c0, 0xc00c, 0x38ff, 0xc00c, 0x21, 0 + .dw 0x3940, 0xc00c, 0x397f, 0xc00c, 0x21, 0 + .dw 0x39c0, 0xc00c, 0x3fff, 0xc00c, 0x21, 0 + .dw 0x4040, 0xc00c, 0x407f, 0xc00c, 0x21, 0 + .dw 0x40c0, 0xc00c, 0x40ff, 0xc00c, 0x21, 0 + .dw 0x4140, 0xc00c, 0x417f, 0xc00c, 0x21, 0 + .dw 0x41c0, 0xc00c, 0x41ff, 0xc00c, 0x21, 0 + .dw 0x4240, 0xc00c, 0x427f, 0xc00c, 0x21, 0 + .dw 0x42c0, 0xc00c, 0x42ff, 0xc00c, 0x21, 0 + .dw 0x4340, 0xc00c, 0x437f, 0xc00c, 0x21, 0 + .dw 0x43c0, 0xc00c, 0x43ff, 0xc00c, 0x21, 0 + .dw 0x4440, 0xc00c, 0x447f, 0xc00c, 0x21, 0 + .dw 0x44c0, 0xc00c, 0x44ff, 0xc00c, 0x21, 0 + .dw 0x4540, 0xc00c, 0x457f, 0xc00c, 0x21, 0 + .dw 0x45c0, 0xc00c, 0x45ff, 0xc00c, 0x21, 0 + .dw 0x4640, 0xc00c, 0x467f, 0xc00c, 0x21, 0 + .dw 0x46c0, 0xc00c, 0x46ff, 0xc00c, 0x21, 0 + .dw 0x4740, 0xc00c, 0x477f, 0xc00c, 0x21, 0 + .dw 0x47c0, 0xc00c, 0x47ff, 0xc00c, 0x21, 0 + .dw 0x4840, 0xc00c, 0x487f, 0xc00c, 0x21, 0 + .dw 0x48c0, 0xc00c, 0x48ff, 0xc00c, 0x21, 0 + .dw 0x4940, 0xc00c, 0x497f, 0xc00c, 0x21, 0 + .dw 0x49c0, 0xc00c, 0x49ff, 0xc00c, 0x21, 0 + .dw 0x4a40, 0xc00c, 0x4a7f, 0xc00c, 0x21, 0 + .dw 0x4ac0, 0xc00c, 0x4aff, 0xc00c, 0x21, 0 + .dw 0x4b40, 0xc00c, 0x4b7f, 0xc00c, 0x21, 0 + .dw 0x4bc0, 0xc00c, 0x4bff, 0xc00c, 0x21, 0 + .dw 0x4c40, 0xc00c, 0x4c7f, 0xc00c, 0x21, 0 + .dw 0x4cc0, 0xc00c, 0x4cff, 0xc00c, 0x21, 0 + .dw 0x4d40, 0xc00c, 0x4d7f, 0xc00c, 0x21, 0 + .dw 0x4dc0, 0xc00c, 0x4dff, 0xc00c, 0x21, 0 + .dw 0x4e40, 0xc00c, 0x4e7f, 0xc00c, 0x21, 0 + .dw 0x4ec0, 0xc00c, 0x4eff, 0xc00c, 0x21, 0 + .dw 0x4f40, 0xc00c, 0x4f7f, 0xc00c, 0x21, 0 + .dw 0x4fc0, 0xc00c, 0x4fff, 0xc00c, 0x21, 0 + .dw 0x5040, 0xc00c, 0x507f, 0xc00c, 0x21, 0 + .dw 0x50c0, 0xc00c, 0x50ff, 0xc00c, 0x21, 0 + .dw 0x5140, 0xc00c, 0x517f, 0xc00c, 0x21, 0 + .dw 0x51c0, 0xc00c, 0x51ff, 0xc00c, 0x21, 0 + .dw 0x5240, 0xc00c, 0x527f, 0xc00c, 0x21, 0 + .dw 0x52c0, 0xc00c, 0x52ff, 0xc00c, 0x21, 0 + .dw 0x5340, 0xc00c, 0x537f, 0xc00c, 0x21, 0 + .dw 0x53c0, 0xc00c, 0x53ff, 0xc00c, 0x21, 0 + .dw 0x5440, 0xc00c, 0x547f, 0xc00c, 0x21, 0 + .dw 0x54c0, 0xc00c, 0x54ff, 0xc00c, 0x21, 0 + .dw 0x5540, 0xc00c, 0x557f, 0xc00c, 0x21, 0 + .dw 0x55c0, 0xc00c, 0x55ff, 0xc00c, 0x21, 0 + .dw 0x5640, 0xc00c, 0x567f, 0xc00c, 0x21, 0 + .dw 0x56c0, 0xc00c, 0x56ff, 0xc00c, 0x21, 0 + .dw 0x5740, 0xc00c, 0x577f, 0xc00c, 0x21, 0 + .dw 0x57c0, 0xc00c, 0x57ff, 0xc00c, 0x21, 0 + .dw 0x5840, 0xc00c, 0x587f, 0xc00c, 0x21, 0 + .dw 0x58c0, 0xc00c, 0x58ff, 0xc00c, 0x21, 0 + .dw 0x5940, 0xc00c, 0x597f, 0xc00c, 0x21, 0 + .dw 0x59c0, 0xc00c, 0x5fff, 0xc00c, 0x21, 0 + .dw 0x6040, 0xc00c, 0x607f, 0xc00c, 0x21, 0 + .dw 0x60c0, 0xc00c, 0x60ff, 0xc00c, 0x21, 0 + .dw 0x6140, 0xc00c, 0x617f, 0xc00c, 0x21, 0 + .dw 0x61c0, 0xc00c, 0x61ff, 0xc00c, 0x21, 0 + .dw 0x6240, 0xc00c, 0x627f, 0xc00c, 0x21, 0 + .dw 0x62c0, 0xc00c, 0x62ff, 0xc00c, 0x21, 0 + .dw 0x6340, 0xc00c, 0x637f, 0xc00c, 0x21, 0 + .dw 0x63c0, 0xc00c, 0x63ff, 0xc00c, 0x21, 0 + .dw 0x6440, 0xc00c, 0x647f, 0xc00c, 0x21, 0 + .dw 0x64c0, 0xc00c, 0x64ff, 0xc00c, 0x21, 0 + .dw 0x6540, 0xc00c, 0x657f, 0xc00c, 0x21, 0 + .dw 0x65c0, 0xc00c, 0x65ff, 0xc00c, 0x21, 0 + .dw 0x6640, 0xc00c, 0x667f, 0xc00c, 0x21, 0 + .dw 0x66c0, 0xc00c, 0x66ff, 0xc00c, 0x21, 0 + .dw 0x6740, 0xc00c, 0x677f, 0xc00c, 0x21, 0 + .dw 0x67c0, 0xc00c, 0x67ff, 0xc00c, 0x21, 0 + .dw 0x6840, 0xc00c, 0x687f, 0xc00c, 0x21, 0 + .dw 0x68c0, 0xc00c, 0x68ff, 0xc00c, 0x21, 0 + .dw 0x6940, 0xc00c, 0x697f, 0xc00c, 0x21, 0 + .dw 0x69c0, 0xc00c, 0x69ff, 0xc00c, 0x21, 0 + .dw 0x6a40, 0xc00c, 0x6a7f, 0xc00c, 0x21, 0 + .dw 0x6ac0, 0xc00c, 0x6aff, 0xc00c, 0x21, 0 + .dw 0x6b40, 0xc00c, 0x6b7f, 0xc00c, 0x21, 0 + .dw 0x6bc0, 0xc00c, 0x6bff, 0xc00c, 0x21, 0 + .dw 0x6c40, 0xc00c, 0x6c7f, 0xc00c, 0x21, 0 + .dw 0x6cc0, 0xc00c, 0x6cff, 0xc00c, 0x21, 0 + .dw 0x6d40, 0xc00c, 0x6d7f, 0xc00c, 0x21, 0 + .dw 0x6dc0, 0xc00c, 0x6dff, 0xc00c, 0x21, 0 + .dw 0x6e40, 0xc00c, 0x6e7f, 0xc00c, 0x21, 0 + .dw 0x6ec0, 0xc00c, 0x6eff, 0xc00c, 0x21, 0 + .dw 0x6f40, 0xc00c, 0x6f7f, 0xc00c, 0x21, 0 + .dw 0x6fc0, 0xc00c, 0x6fff, 0xc00c, 0x21, 0 + .dw 0x7040, 0xc00c, 0x707f, 0xc00c, 0x21, 0 + .dw 0x70c0, 0xc00c, 0x70ff, 0xc00c, 0x21, 0 + .dw 0x7140, 0xc00c, 0x717f, 0xc00c, 0x21, 0 + .dw 0x71c0, 0xc00c, 0x71ff, 0xc00c, 0x21, 0 + .dw 0x7240, 0xc00c, 0x727f, 0xc00c, 0x21, 0 + .dw 0x72c0, 0xc00c, 0x72ff, 0xc00c, 0x21, 0 + .dw 0x7340, 0xc00c, 0x737f, 0xc00c, 0x21, 0 + .dw 0x73c0, 0xc00c, 0x73ff, 0xc00c, 0x21, 0 + .dw 0x7440, 0xc00c, 0x747f, 0xc00c, 0x21, 0 + .dw 0x74c0, 0xc00c, 0x74ff, 0xc00c, 0x21, 0 + .dw 0x7540, 0xc00c, 0x757f, 0xc00c, 0x21, 0 + .dw 0x75c0, 0xc00c, 0x75ff, 0xc00c, 0x21, 0 + .dw 0x7640, 0xc00c, 0x767f, 0xc00c, 0x21, 0 + .dw 0x76c0, 0xc00c, 0x76ff, 0xc00c, 0x21, 0 + .dw 0x7740, 0xc00c, 0x777f, 0xc00c, 0x21, 0 + .dw 0x77c0, 0xc00c, 0x77ff, 0xc00c, 0x21, 0 + .dw 0x7840, 0xc00c, 0x787f, 0xc00c, 0x21, 0 + .dw 0x78c0, 0xc00c, 0x78ff, 0xc00c, 0x21, 0 + .dw 0x7940, 0xc00c, 0x797f, 0xc00c, 0x21, 0 + .dw 0x79c0, 0xc00c, 0x7fff, 0xc00c, 0x21, 0 + .dw 0x8040, 0xc00c, 0x807f, 0xc00c, 0x21, 0 + .dw 0x80c0, 0xc00c, 0x80ff, 0xc00c, 0x21, 0 + .dw 0x8140, 0xc00c, 0x817f, 0xc00c, 0x21, 0 + .dw 0x81c0, 0xc00c, 0x81ff, 0xc00c, 0x21, 0 + .dw 0x8240, 0xc00c, 0x827f, 0xc00c, 0x21, 0 + .dw 0x82c0, 0xc00c, 0x82ff, 0xc00c, 0x21, 0 + .dw 0x8340, 0xc00c, 0x837f, 0xc00c, 0x21, 0 + .dw 0x83c0, 0xc00c, 0x83ff, 0xc00c, 0x21, 0 + .dw 0x8440, 0xc00c, 0x847f, 0xc00c, 0x21, 0 + .dw 0x84c0, 0xc00c, 0x84ff, 0xc00c, 0x21, 0 + .dw 0x8540, 0xc00c, 0x857f, 0xc00c, 0x21, 0 + .dw 0x85c0, 0xc00c, 0x85ff, 0xc00c, 0x21, 0 + .dw 0x8640, 0xc00c, 0x867f, 0xc00c, 0x21, 0 + .dw 0x86c0, 0xc00c, 0x86ff, 0xc00c, 0x21, 0 + .dw 0x8740, 0xc00c, 0x877f, 0xc00c, 0x21, 0 + .dw 0x87c0, 0xc00c, 0x87ff, 0xc00c, 0x21, 0 + .dw 0x8840, 0xc00c, 0x887f, 0xc00c, 0x21, 0 + .dw 0x88c0, 0xc00c, 0x88ff, 0xc00c, 0x21, 0 + .dw 0x8940, 0xc00c, 0x897f, 0xc00c, 0x21, 0 + .dw 0x89c0, 0xc00c, 0x89ff, 0xc00c, 0x21, 0 + .dw 0x8a40, 0xc00c, 0x8a7f, 0xc00c, 0x21, 0 + .dw 0x8ac0, 0xc00c, 0x8aff, 0xc00c, 0x21, 0 + .dw 0x8b40, 0xc00c, 0x8b7f, 0xc00c, 0x21, 0 + .dw 0x8bc0, 0xc00c, 0x8bff, 0xc00c, 0x21, 0 + .dw 0x8c40, 0xc00c, 0x8c7f, 0xc00c, 0x21, 0 + .dw 0x8cc0, 0xc00c, 0x8cff, 0xc00c, 0x21, 0 + .dw 0x8d40, 0xc00c, 0x8d7f, 0xc00c, 0x21, 0 + .dw 0x8dc0, 0xc00c, 0x8dff, 0xc00c, 0x21, 0 + .dw 0x8e40, 0xc00c, 0x8e7f, 0xc00c, 0x21, 0 + .dw 0x8ec0, 0xc00c, 0x8eff, 0xc00c, 0x21, 0 + .dw 0x8f40, 0xc00c, 0x8f7f, 0xc00c, 0x21, 0 + .dw 0x8fc0, 0xc00c, 0x8fff, 0xc00c, 0x21, 0 + .dw 0x9040, 0xc00c, 0x907f, 0xc00c, 0x21, 0 + .dw 0x90c0, 0xc00c, 0x90ff, 0xc00c, 0x21, 0 + .dw 0x9140, 0xc00c, 0x917f, 0xc00c, 0x21, 0 + .dw 0x91c0, 0xc00c, 0x91ff, 0xc00c, 0x21, 0 + .dw 0x9240, 0xc00c, 0x927f, 0xc00c, 0x21, 0 + .dw 0x92c0, 0xc00c, 0x92ff, 0xc00c, 0x21, 0 + .dw 0x9340, 0xc00c, 0x937f, 0xc00c, 0x21, 0 + .dw 0x93c0, 0xc00c, 0x93ff, 0xc00c, 0x21, 0 + .dw 0x9440, 0xc00c, 0x947f, 0xc00c, 0x21, 0 + .dw 0x94c0, 0xc00c, 0x94ff, 0xc00c, 0x21, 0 + .dw 0x9540, 0xc00c, 0x957f, 0xc00c, 0x21, 0 + .dw 0x95c0, 0xc00c, 0x95ff, 0xc00c, 0x21, 0 + .dw 0x9640, 0xc00c, 0x967f, 0xc00c, 0x21, 0 + .dw 0x96c0, 0xc00c, 0x96ff, 0xc00c, 0x21, 0 + .dw 0x9740, 0xc00c, 0x977f, 0xc00c, 0x21, 0 + .dw 0x97c0, 0xc00c, 0x97ff, 0xc00c, 0x21, 0 + .dw 0x9840, 0xc00c, 0x987f, 0xc00c, 0x21, 0 + .dw 0x98c0, 0xc00c, 0x98ff, 0xc00c, 0x21, 0 + .dw 0x9940, 0xc00c, 0x997f, 0xc00c, 0x21, 0 + .dw 0x99c0, 0xc00c, 0x9fff, 0xc00c, 0x21, 0 + .dw 0xa040, 0xc00c, 0xa07f, 0xc00c, 0x21, 0 + .dw 0xa0c0, 0xc00c, 0xa0ff, 0xc00c, 0x21, 0 + .dw 0xa140, 0xc00c, 0xa17f, 0xc00c, 0x21, 0 + .dw 0xa1c0, 0xc00c, 0xa1ff, 0xc00c, 0x21, 0 + .dw 0xa240, 0xc00c, 0xa27f, 0xc00c, 0x21, 0 + .dw 0xa2c0, 0xc00c, 0xa2ff, 0xc00c, 0x21, 0 + .dw 0xa340, 0xc00c, 0xa37f, 0xc00c, 0x21, 0 + .dw 0xa3c0, 0xc00c, 0xa3ff, 0xc00c, 0x21, 0 + .dw 0xa440, 0xc00c, 0xa47f, 0xc00c, 0x21, 0 + .dw 0xa4c0, 0xc00c, 0xa4ff, 0xc00c, 0x21, 0 + .dw 0xa540, 0xc00c, 0xa57f, 0xc00c, 0x21, 0 + .dw 0xa5c0, 0xc00c, 0xa5ff, 0xc00c, 0x21, 0 + .dw 0xa640, 0xc00c, 0xa67f, 0xc00c, 0x21, 0 + .dw 0xa6c0, 0xc00c, 0xa6ff, 0xc00c, 0x21, 0 + .dw 0xa740, 0xc00c, 0xa77f, 0xc00c, 0x21, 0 + .dw 0xa7c0, 0xc00c, 0xa7ff, 0xc00c, 0x21, 0 + .dw 0xa840, 0xc00c, 0xa87f, 0xc00c, 0x21, 0 + .dw 0xa8c0, 0xc00c, 0xa8ff, 0xc00c, 0x21, 0 + .dw 0xa940, 0xc00c, 0xa97f, 0xc00c, 0x21, 0 + .dw 0xa9c0, 0xc00c, 0xa9ff, 0xc00c, 0x21, 0 + .dw 0xaa40, 0xc00c, 0xaa7f, 0xc00c, 0x21, 0 + .dw 0xaac0, 0xc00c, 0xaaff, 0xc00c, 0x21, 0 + .dw 0xab40, 0xc00c, 0xab7f, 0xc00c, 0x21, 0 + .dw 0xabc0, 0xc00c, 0xabff, 0xc00c, 0x21, 0 + .dw 0xac40, 0xc00c, 0xac7f, 0xc00c, 0x21, 0 + .dw 0xacc0, 0xc00c, 0xacff, 0xc00c, 0x21, 0 + .dw 0xad40, 0xc00c, 0xad7f, 0xc00c, 0x21, 0 + .dw 0xadc0, 0xc00c, 0xadff, 0xc00c, 0x21, 0 + .dw 0xae40, 0xc00c, 0xae7f, 0xc00c, 0x21, 0 + .dw 0xaec0, 0xc00c, 0xaeff, 0xc00c, 0x21, 0 + .dw 0xaf40, 0xc00c, 0xaf7f, 0xc00c, 0x21, 0 + .dw 0xafc0, 0xc00c, 0xafff, 0xc00c, 0x21, 0 + .dw 0xb040, 0xc00c, 0xb07f, 0xc00c, 0x21, 0 + .dw 0xb0c0, 0xc00c, 0xb0ff, 0xc00c, 0x21, 0 + .dw 0xb140, 0xc00c, 0xb17f, 0xc00c, 0x21, 0 + .dw 0xb1c0, 0xc00c, 0xb1ff, 0xc00c, 0x21, 0 + .dw 0xb240, 0xc00c, 0xb27f, 0xc00c, 0x21, 0 + .dw 0xb2c0, 0xc00c, 0xb2ff, 0xc00c, 0x21, 0 + .dw 0xb340, 0xc00c, 0xb37f, 0xc00c, 0x21, 0 + .dw 0xb3c0, 0xc00c, 0xb3ff, 0xc00c, 0x21, 0 + .dw 0xb440, 0xc00c, 0xb47f, 0xc00c, 0x21, 0 + .dw 0xb4c0, 0xc00c, 0xb4ff, 0xc00c, 0x21, 0 + .dw 0xb540, 0xc00c, 0xb57f, 0xc00c, 0x21, 0 + .dw 0xb5c0, 0xc00c, 0xb5ff, 0xc00c, 0x21, 0 + .dw 0xb640, 0xc00c, 0xb67f, 0xc00c, 0x21, 0 + .dw 0xb6c0, 0xc00c, 0xb6ff, 0xc00c, 0x21, 0 + .dw 0xb740, 0xc00c, 0xb77f, 0xc00c, 0x21, 0 + .dw 0xb7c0, 0xc00c, 0xb7ff, 0xc00c, 0x21, 0 + .dw 0xb840, 0xc00c, 0xb87f, 0xc00c, 0x21, 0 + .dw 0xb8c0, 0xc00c, 0xb8ff, 0xc00c, 0x21, 0 + .dw 0xb940, 0xc00c, 0xb97f, 0xc00c, 0x21, 0 + .dw 0xb9c0, 0xc00c, 0xbfff, 0xc00c, 0x21, 0 + .dw 0xc040, 0xc00c, 0xc07f, 0xc00c, 0x21, 0 + .dw 0xc0c0, 0xc00c, 0xc0ff, 0xc00c, 0x21, 0 + .dw 0xc140, 0xc00c, 0xc17f, 0xc00c, 0x21, 0 + .dw 0xc1c0, 0xc00c, 0xc1ff, 0xc00c, 0x21, 0 + .dw 0xc240, 0xc00c, 0xc27f, 0xc00c, 0x21, 0 + .dw 0xc2c0, 0xc00c, 0xc2ff, 0xc00c, 0x21, 0 + .dw 0xc340, 0xc00c, 0xc37f, 0xc00c, 0x21, 0 + .dw 0xc3c0, 0xc00c, 0xc3ff, 0xc00c, 0x21, 0 + .dw 0xc440, 0xc00c, 0xc47f, 0xc00c, 0x21, 0 + .dw 0xc4c0, 0xc00c, 0xc4ff, 0xc00c, 0x21, 0 + .dw 0xc540, 0xc00c, 0xc57f, 0xc00c, 0x21, 0 + .dw 0xc5c0, 0xc00c, 0xc5ff, 0xc00c, 0x21, 0 + .dw 0xc640, 0xc00c, 0xc67f, 0xc00c, 0x21, 0 + .dw 0xc6c0, 0xc00c, 0xc6ff, 0xc00c, 0x21, 0 + .dw 0xc740, 0xc00c, 0xc77f, 0xc00c, 0x21, 0 + .dw 0xc7c0, 0xc00c, 0xc7ff, 0xc00c, 0x21, 0 + .dw 0xc840, 0xc00c, 0xc87f, 0xc00c, 0x21, 0 + .dw 0xc8c0, 0xc00c, 0xc8ff, 0xc00c, 0x21, 0 + .dw 0xc940, 0xc00c, 0xc97f, 0xc00c, 0x21, 0 + .dw 0xc9c0, 0xc00c, 0xc9ff, 0xc00c, 0x21, 0 + .dw 0xca40, 0xc00c, 0xca7f, 0xc00c, 0x21, 0 + .dw 0xcac0, 0xc00c, 0xcaff, 0xc00c, 0x21, 0 + .dw 0xcb40, 0xc00c, 0xcb7f, 0xc00c, 0x21, 0 + .dw 0xcbc0, 0xc00c, 0xcbff, 0xc00c, 0x21, 0 + .dw 0xcc40, 0xc00c, 0xcc7f, 0xc00c, 0x21, 0 + .dw 0xccc0, 0xc00c, 0xccff, 0xc00c, 0x21, 0 + .dw 0xcd40, 0xc00c, 0xcd7f, 0xc00c, 0x21, 0 + .dw 0xcdc0, 0xc00c, 0xcdff, 0xc00c, 0x21, 0 + .dw 0xce40, 0xc00c, 0xce7f, 0xc00c, 0x21, 0 + .dw 0xcec0, 0xc00c, 0xceff, 0xc00c, 0x21, 0 + .dw 0xcf40, 0xc00c, 0xcf7f, 0xc00c, 0x21, 0 + .dw 0xcfc0, 0xc00c, 0xcfff, 0xc00c, 0x21, 0 + .dw 0xd040, 0xc00c, 0xd07f, 0xc00c, 0x21, 0 + .dw 0xd0c0, 0xc00c, 0xd0ff, 0xc00c, 0x21, 0 + .dw 0xd140, 0xc00c, 0xd17f, 0xc00c, 0x21, 0 + .dw 0xd1c0, 0xc00c, 0xd1ff, 0xc00c, 0x21, 0 + .dw 0xd240, 0xc00c, 0xd27f, 0xc00c, 0x21, 0 + .dw 0xd2c0, 0xc00c, 0xd2ff, 0xc00c, 0x21, 0 + .dw 0xd340, 0xc00c, 0xd37f, 0xc00c, 0x21, 0 + .dw 0xd3c0, 0xc00c, 0xd3ff, 0xc00c, 0x21, 0 + .dw 0xd440, 0xc00c, 0xd47f, 0xc00c, 0x21, 0 + .dw 0xd4c0, 0xc00c, 0xd4ff, 0xc00c, 0x21, 0 + .dw 0xd540, 0xc00c, 0xd57f, 0xc00c, 0x21, 0 + .dw 0xd5c0, 0xc00c, 0xd5ff, 0xc00c, 0x21, 0 + .dw 0xd640, 0xc00c, 0xd67f, 0xc00c, 0x21, 0 + .dw 0xd6c0, 0xc00c, 0xd6ff, 0xc00c, 0x21, 0 + .dw 0xd740, 0xc00c, 0xd77f, 0xc00c, 0x21, 0 + .dw 0xd7c0, 0xc00c, 0xd7ff, 0xc00c, 0x21, 0 + .dw 0xd840, 0xc00c, 0xd87f, 0xc00c, 0x21, 0 + .dw 0xd8c0, 0xc00c, 0xd8ff, 0xc00c, 0x21, 0 + .dw 0xd940, 0xc00c, 0xd97f, 0xc00c, 0x21, 0 + .dw 0xd9c0, 0xc00c, 0xdfff, 0xc00c, 0x21, 0 + .dw 0xe040, 0xc00c, 0xe07f, 0xc00c, 0x21, 0 + .dw 0xe0c0, 0xc00c, 0xe0ff, 0xc00c, 0x21, 0 + .dw 0xe140, 0xc00c, 0xe17f, 0xc00c, 0x21, 0 + .dw 0xe1c0, 0xc00c, 0xe1ff, 0xc00c, 0x21, 0 + .dw 0xe240, 0xc00c, 0xe27f, 0xc00c, 0x21, 0 + .dw 0xe2c0, 0xc00c, 0xe2ff, 0xc00c, 0x21, 0 + .dw 0xe340, 0xc00c, 0xe37f, 0xc00c, 0x21, 0 + .dw 0xe3c0, 0xc00c, 0xe3ff, 0xc00c, 0x21, 0 + .dw 0xe440, 0xc00c, 0xe47f, 0xc00c, 0x21, 0 + .dw 0xe4c0, 0xc00c, 0xe4ff, 0xc00c, 0x21, 0 + .dw 0xe540, 0xc00c, 0xe57f, 0xc00c, 0x21, 0 + .dw 0xe5c0, 0xc00c, 0xe5ff, 0xc00c, 0x21, 0 + .dw 0xe640, 0xc00c, 0xe67f, 0xc00c, 0x21, 0 + .dw 0xe6c0, 0xc00c, 0xe6ff, 0xc00c, 0x21, 0 + .dw 0xe740, 0xc00c, 0xe77f, 0xc00c, 0x21, 0 + .dw 0xe7c0, 0xc00c, 0xe7ff, 0xc00c, 0x21, 0 + .dw 0xe840, 0xc00c, 0xe87f, 0xc00c, 0x21, 0 + .dw 0xe8c0, 0xc00c, 0xe8ff, 0xc00c, 0x21, 0 + .dw 0xe940, 0xc00c, 0xe97f, 0xc00c, 0x21, 0 + .dw 0xe9c0, 0xc00c, 0xe9ff, 0xc00c, 0x21, 0 + .dw 0xea40, 0xc00c, 0xea7f, 0xc00c, 0x21, 0 + .dw 0xeac0, 0xc00c, 0xeaff, 0xc00c, 0x21, 0 + .dw 0xeb40, 0xc00c, 0xeb7f, 0xc00c, 0x21, 0 + .dw 0xebc0, 0xc00c, 0xebff, 0xc00c, 0x21, 0 + .dw 0xec40, 0xc00c, 0xec7f, 0xc00c, 0x21, 0 + .dw 0xecc0, 0xc00c, 0xecff, 0xc00c, 0x21, 0 + .dw 0xed40, 0xc00c, 0xed7f, 0xc00c, 0x21, 0 + .dw 0xedc0, 0xc00c, 0xedff, 0xc00c, 0x21, 0 + .dw 0xee40, 0xc00c, 0xee7f, 0xc00c, 0x21, 0 + .dw 0xeec0, 0xc00c, 0xeeff, 0xc00c, 0x21, 0 + .dw 0xef40, 0xc00c, 0xef7f, 0xc00c, 0x21, 0 + .dw 0xefc0, 0xc00c, 0xefff, 0xc00c, 0x21, 0 + .dw 0xf040, 0xc00c, 0xf07f, 0xc00c, 0x21, 0 + .dw 0xf0c0, 0xc00c, 0xf0ff, 0xc00c, 0x21, 0 + .dw 0xf140, 0xc00c, 0xf17f, 0xc00c, 0x21, 0 + .dw 0xf1c0, 0xc00c, 0xf1ff, 0xc00c, 0x21, 0 + .dw 0xf240, 0xc00c, 0xf27f, 0xc00c, 0x21, 0 + .dw 0xf2c0, 0xc00c, 0xf2ff, 0xc00c, 0x21, 0 + .dw 0xf340, 0xc00c, 0xf37f, 0xc00c, 0x21, 0 + .dw 0xf3c0, 0xc00c, 0xf3ff, 0xc00c, 0x21, 0 + .dw 0xf440, 0xc00c, 0xf47f, 0xc00c, 0x21, 0 + .dw 0xf4c0, 0xc00c, 0xf4ff, 0xc00c, 0x21, 0 + .dw 0xf540, 0xc00c, 0xf57f, 0xc00c, 0x21, 0 + .dw 0xf5c0, 0xc00c, 0xf5ff, 0xc00c, 0x21, 0 + .dw 0xf640, 0xc00c, 0xf67f, 0xc00c, 0x21, 0 + .dw 0xf6c0, 0xc00c, 0xf6ff, 0xc00c, 0x21, 0 + .dw 0xf740, 0xc00c, 0xf77f, 0xc00c, 0x21, 0 + .dw 0xf7c0, 0xc00c, 0xf7ff, 0xc00c, 0x21, 0 + .dw 0xf840, 0xc00c, 0xf87f, 0xc00c, 0x21, 0 + .dw 0xf8c0, 0xc00c, 0xf8ff, 0xc00c, 0x21, 0 + .dw 0xf940, 0xc00c, 0xf97f, 0xc00c, 0x21, 0 + .dw 0xf9c0, 0xc00c, 0xffff, 0xc00c, 0x21, 0 + .dw 0x0040, 0xc00d, 0x007f, 0xc00d, 0x21, 0 + .dw 0x00c0, 0xc00d, 0x00ff, 0xc00d, 0x21, 0 + .dw 0x0140, 0xc00d, 0x017f, 0xc00d, 0x21, 0 + .dw 0x01c0, 0xc00d, 0x01ff, 0xc00d, 0x21, 0 + .dw 0x0240, 0xc00d, 0x027f, 0xc00d, 0x21, 0 + .dw 0x02c0, 0xc00d, 0x02ff, 0xc00d, 0x21, 0 + .dw 0x0340, 0xc00d, 0x037f, 0xc00d, 0x21, 0 + .dw 0x03c0, 0xc00d, 0x03ff, 0xc00d, 0x21, 0 + .dw 0x0440, 0xc00d, 0x047f, 0xc00d, 0x21, 0 + .dw 0x04c0, 0xc00d, 0x04ff, 0xc00d, 0x21, 0 + .dw 0x0540, 0xc00d, 0x057f, 0xc00d, 0x21, 0 + .dw 0x05c0, 0xc00d, 0x05ff, 0xc00d, 0x21, 0 + .dw 0x0640, 0xc00d, 0x067f, 0xc00d, 0x21, 0 + .dw 0x06c0, 0xc00d, 0x06ff, 0xc00d, 0x21, 0 + .dw 0x0740, 0xc00d, 0x077f, 0xc00d, 0x21, 0 + .dw 0x07c0, 0xc00d, 0x07ff, 0xc00d, 0x21, 0 + .dw 0x0840, 0xc00d, 0x087f, 0xc00d, 0x21, 0 + .dw 0x08c0, 0xc00d, 0x08ff, 0xc00d, 0x21, 0 + .dw 0x0940, 0xc00d, 0x097f, 0xc00d, 0x21, 0 + .dw 0x09c0, 0xc00d, 0x09ff, 0xc00d, 0x21, 0 + .dw 0x0a40, 0xc00d, 0x0a7f, 0xc00d, 0x21, 0 + .dw 0x0ac0, 0xc00d, 0x0aff, 0xc00d, 0x21, 0 + .dw 0x0b40, 0xc00d, 0x0b7f, 0xc00d, 0x21, 0 + .dw 0x0bc0, 0xc00d, 0x0bff, 0xc00d, 0x21, 0 + .dw 0x0c40, 0xc00d, 0x0c7f, 0xc00d, 0x21, 0 + .dw 0x0cc0, 0xc00d, 0x0cff, 0xc00d, 0x21, 0 + .dw 0x0d40, 0xc00d, 0x0d7f, 0xc00d, 0x21, 0 + .dw 0x0dc0, 0xc00d, 0x0dff, 0xc00d, 0x21, 0 + .dw 0x0e40, 0xc00d, 0x0e7f, 0xc00d, 0x21, 0 + .dw 0x0ec0, 0xc00d, 0x0eff, 0xc00d, 0x21, 0 + .dw 0x0f40, 0xc00d, 0x0f7f, 0xc00d, 0x21, 0 + .dw 0x0fc0, 0xc00d, 0x0fff, 0xc00d, 0x21, 0 + .dw 0x1040, 0xc00d, 0x107f, 0xc00d, 0x21, 0 + .dw 0x10c0, 0xc00d, 0x10ff, 0xc00d, 0x21, 0 + .dw 0x1140, 0xc00d, 0x117f, 0xc00d, 0x21, 0 + .dw 0x11c0, 0xc00d, 0x11ff, 0xc00d, 0x21, 0 + .dw 0x1240, 0xc00d, 0x127f, 0xc00d, 0x21, 0 + .dw 0x12c0, 0xc00d, 0x12ff, 0xc00d, 0x21, 0 + .dw 0x1340, 0xc00d, 0x137f, 0xc00d, 0x21, 0 + .dw 0x13c0, 0xc00d, 0x13ff, 0xc00d, 0x21, 0 + .dw 0x1440, 0xc00d, 0x147f, 0xc00d, 0x21, 0 + .dw 0x14c0, 0xc00d, 0x14ff, 0xc00d, 0x21, 0 + .dw 0x1540, 0xc00d, 0x157f, 0xc00d, 0x21, 0 + .dw 0x15c0, 0xc00d, 0x15ff, 0xc00d, 0x21, 0 + .dw 0x1640, 0xc00d, 0x167f, 0xc00d, 0x21, 0 + .dw 0x16c0, 0xc00d, 0x16ff, 0xc00d, 0x21, 0 + .dw 0x1740, 0xc00d, 0x177f, 0xc00d, 0x21, 0 + .dw 0x17c0, 0xc00d, 0x17ff, 0xc00d, 0x21, 0 + .dw 0x1840, 0xc00d, 0x187f, 0xc00d, 0x21, 0 + .dw 0x18c0, 0xc00d, 0x18ff, 0xc00d, 0x21, 0 + .dw 0x1940, 0xc00d, 0x197f, 0xc00d, 0x21, 0 + .dw 0x19c0, 0xc00d, 0x1fff, 0xc00d, 0x21, 0 + .dw 0x2040, 0xc00d, 0x207f, 0xc00d, 0x21, 0 + .dw 0x20c0, 0xc00d, 0x20ff, 0xc00d, 0x21, 0 + .dw 0x2140, 0xc00d, 0x217f, 0xc00d, 0x21, 0 + .dw 0x21c0, 0xc00d, 0x21ff, 0xc00d, 0x21, 0 + .dw 0x2240, 0xc00d, 0x227f, 0xc00d, 0x21, 0 + .dw 0x22c0, 0xc00d, 0x22ff, 0xc00d, 0x21, 0 + .dw 0x2340, 0xc00d, 0x237f, 0xc00d, 0x21, 0 + .dw 0x23c0, 0xc00d, 0x23ff, 0xc00d, 0x21, 0 + .dw 0x2440, 0xc00d, 0x247f, 0xc00d, 0x21, 0 + .dw 0x24c0, 0xc00d, 0x24ff, 0xc00d, 0x21, 0 + .dw 0x2540, 0xc00d, 0x257f, 0xc00d, 0x21, 0 + .dw 0x25c0, 0xc00d, 0x25ff, 0xc00d, 0x21, 0 + .dw 0x2640, 0xc00d, 0x267f, 0xc00d, 0x21, 0 + .dw 0x26c0, 0xc00d, 0x26ff, 0xc00d, 0x21, 0 + .dw 0x2740, 0xc00d, 0x277f, 0xc00d, 0x21, 0 + .dw 0x27c0, 0xc00d, 0x27ff, 0xc00d, 0x21, 0 + .dw 0x2840, 0xc00d, 0x287f, 0xc00d, 0x21, 0 + .dw 0x28c0, 0xc00d, 0x28ff, 0xc00d, 0x21, 0 + .dw 0x2940, 0xc00d, 0x297f, 0xc00d, 0x21, 0 + .dw 0x29c0, 0xc00d, 0x29ff, 0xc00d, 0x21, 0 + .dw 0x2a40, 0xc00d, 0x2a7f, 0xc00d, 0x21, 0 + .dw 0x2ac0, 0xc00d, 0x2aff, 0xc00d, 0x21, 0 + .dw 0x2b40, 0xc00d, 0x2b7f, 0xc00d, 0x21, 0 + .dw 0x2bc0, 0xc00d, 0x2bff, 0xc00d, 0x21, 0 + .dw 0x2c40, 0xc00d, 0x2c7f, 0xc00d, 0x21, 0 + .dw 0x2cc0, 0xc00d, 0x2cff, 0xc00d, 0x21, 0 + .dw 0x2d40, 0xc00d, 0x2d7f, 0xc00d, 0x21, 0 + .dw 0x2dc0, 0xc00d, 0x2dff, 0xc00d, 0x21, 0 + .dw 0x2e40, 0xc00d, 0x2e7f, 0xc00d, 0x21, 0 + .dw 0x2ec0, 0xc00d, 0x2eff, 0xc00d, 0x21, 0 + .dw 0x2f40, 0xc00d, 0x2f7f, 0xc00d, 0x21, 0 + .dw 0x2fc0, 0xc00d, 0x2fff, 0xc00d, 0x21, 0 + .dw 0x3040, 0xc00d, 0x307f, 0xc00d, 0x21, 0 + .dw 0x30c0, 0xc00d, 0x30ff, 0xc00d, 0x21, 0 + .dw 0x3140, 0xc00d, 0x317f, 0xc00d, 0x21, 0 + .dw 0x31c0, 0xc00d, 0x31ff, 0xc00d, 0x21, 0 + .dw 0x3240, 0xc00d, 0x327f, 0xc00d, 0x21, 0 + .dw 0x32c0, 0xc00d, 0x32ff, 0xc00d, 0x21, 0 + .dw 0x3340, 0xc00d, 0x337f, 0xc00d, 0x21, 0 + .dw 0x33c0, 0xc00d, 0x33ff, 0xc00d, 0x21, 0 + .dw 0x3440, 0xc00d, 0x347f, 0xc00d, 0x21, 0 + .dw 0x34c0, 0xc00d, 0x34ff, 0xc00d, 0x21, 0 + .dw 0x3540, 0xc00d, 0x357f, 0xc00d, 0x21, 0 + .dw 0x35c0, 0xc00d, 0x35ff, 0xc00d, 0x21, 0 + .dw 0x3640, 0xc00d, 0x367f, 0xc00d, 0x21, 0 + .dw 0x36c0, 0xc00d, 0x36ff, 0xc00d, 0x21, 0 + .dw 0x3740, 0xc00d, 0x377f, 0xc00d, 0x21, 0 + .dw 0x37c0, 0xc00d, 0x37ff, 0xc00d, 0x21, 0 + .dw 0x3840, 0xc00d, 0x387f, 0xc00d, 0x21, 0 + .dw 0x38c0, 0xc00d, 0x38ff, 0xc00d, 0x21, 0 + .dw 0x3940, 0xc00d, 0x397f, 0xc00d, 0x21, 0 + .dw 0x39c0, 0xc00d, 0x3fff, 0xc00d, 0x21, 0 + .dw 0x4040, 0xc00d, 0x407f, 0xc00d, 0x21, 0 + .dw 0x40c0, 0xc00d, 0x40ff, 0xc00d, 0x21, 0 + .dw 0x4140, 0xc00d, 0x417f, 0xc00d, 0x21, 0 + .dw 0x41c0, 0xc00d, 0x41ff, 0xc00d, 0x21, 0 + .dw 0x4240, 0xc00d, 0x427f, 0xc00d, 0x21, 0 + .dw 0x42c0, 0xc00d, 0x42ff, 0xc00d, 0x21, 0 + .dw 0x4340, 0xc00d, 0x437f, 0xc00d, 0x21, 0 + .dw 0x43c0, 0xc00d, 0x43ff, 0xc00d, 0x21, 0 + .dw 0x4440, 0xc00d, 0x447f, 0xc00d, 0x21, 0 + .dw 0x44c0, 0xc00d, 0x44ff, 0xc00d, 0x21, 0 + .dw 0x4540, 0xc00d, 0x457f, 0xc00d, 0x21, 0 + .dw 0x45c0, 0xc00d, 0x45ff, 0xc00d, 0x21, 0 + .dw 0x4640, 0xc00d, 0x467f, 0xc00d, 0x21, 0 + .dw 0x46c0, 0xc00d, 0x46ff, 0xc00d, 0x21, 0 + .dw 0x4740, 0xc00d, 0x477f, 0xc00d, 0x21, 0 + .dw 0x47c0, 0xc00d, 0x47ff, 0xc00d, 0x21, 0 + .dw 0x4840, 0xc00d, 0x487f, 0xc00d, 0x21, 0 + .dw 0x48c0, 0xc00d, 0x48ff, 0xc00d, 0x21, 0 + .dw 0x4940, 0xc00d, 0x497f, 0xc00d, 0x21, 0 + .dw 0x49c0, 0xc00d, 0x49ff, 0xc00d, 0x21, 0 + .dw 0x4a40, 0xc00d, 0x4a7f, 0xc00d, 0x21, 0 + .dw 0x4ac0, 0xc00d, 0x4aff, 0xc00d, 0x21, 0 + .dw 0x4b40, 0xc00d, 0x4b7f, 0xc00d, 0x21, 0 + .dw 0x4bc0, 0xc00d, 0x4bff, 0xc00d, 0x21, 0 + .dw 0x4c40, 0xc00d, 0x4c7f, 0xc00d, 0x21, 0 + .dw 0x4cc0, 0xc00d, 0x4cff, 0xc00d, 0x21, 0 + .dw 0x4d40, 0xc00d, 0x4d7f, 0xc00d, 0x21, 0 + .dw 0x4dc0, 0xc00d, 0x4dff, 0xc00d, 0x21, 0 + .dw 0x4e40, 0xc00d, 0x4e7f, 0xc00d, 0x21, 0 + .dw 0x4ec0, 0xc00d, 0x4eff, 0xc00d, 0x21, 0 + .dw 0x4f40, 0xc00d, 0x4f7f, 0xc00d, 0x21, 0 + .dw 0x4fc0, 0xc00d, 0x4fff, 0xc00d, 0x21, 0 + .dw 0x5040, 0xc00d, 0x507f, 0xc00d, 0x21, 0 + .dw 0x50c0, 0xc00d, 0x50ff, 0xc00d, 0x21, 0 + .dw 0x5140, 0xc00d, 0x517f, 0xc00d, 0x21, 0 + .dw 0x51c0, 0xc00d, 0x51ff, 0xc00d, 0x21, 0 + .dw 0x5240, 0xc00d, 0x527f, 0xc00d, 0x21, 0 + .dw 0x52c0, 0xc00d, 0x52ff, 0xc00d, 0x21, 0 + .dw 0x5340, 0xc00d, 0x537f, 0xc00d, 0x21, 0 + .dw 0x53c0, 0xc00d, 0x53ff, 0xc00d, 0x21, 0 + .dw 0x5440, 0xc00d, 0x547f, 0xc00d, 0x21, 0 + .dw 0x54c0, 0xc00d, 0x54ff, 0xc00d, 0x21, 0 + .dw 0x5540, 0xc00d, 0x557f, 0xc00d, 0x21, 0 + .dw 0x55c0, 0xc00d, 0x55ff, 0xc00d, 0x21, 0 + .dw 0x5640, 0xc00d, 0x567f, 0xc00d, 0x21, 0 + .dw 0x56c0, 0xc00d, 0x56ff, 0xc00d, 0x21, 0 + .dw 0x5740, 0xc00d, 0x577f, 0xc00d, 0x21, 0 + .dw 0x57c0, 0xc00d, 0x57ff, 0xc00d, 0x21, 0 + .dw 0x5840, 0xc00d, 0x587f, 0xc00d, 0x21, 0 + .dw 0x58c0, 0xc00d, 0x58ff, 0xc00d, 0x21, 0 + .dw 0x5940, 0xc00d, 0x597f, 0xc00d, 0x21, 0 + .dw 0x59c0, 0xc00d, 0x5fff, 0xc00d, 0x21, 0 + .dw 0x6040, 0xc00d, 0x607f, 0xc00d, 0x21, 0 + .dw 0x60c0, 0xc00d, 0x60ff, 0xc00d, 0x21, 0 + .dw 0x6140, 0xc00d, 0x617f, 0xc00d, 0x21, 0 + .dw 0x61c0, 0xc00d, 0x61ff, 0xc00d, 0x21, 0 + .dw 0x6240, 0xc00d, 0x627f, 0xc00d, 0x21, 0 + .dw 0x62c0, 0xc00d, 0x62ff, 0xc00d, 0x21, 0 + .dw 0x6340, 0xc00d, 0x637f, 0xc00d, 0x21, 0 + .dw 0x63c0, 0xc00d, 0x63ff, 0xc00d, 0x21, 0 + .dw 0x6440, 0xc00d, 0x647f, 0xc00d, 0x21, 0 + .dw 0x64c0, 0xc00d, 0x64ff, 0xc00d, 0x21, 0 + .dw 0x6540, 0xc00d, 0x657f, 0xc00d, 0x21, 0 + .dw 0x65c0, 0xc00d, 0x65ff, 0xc00d, 0x21, 0 + .dw 0x6640, 0xc00d, 0x667f, 0xc00d, 0x21, 0 + .dw 0x66c0, 0xc00d, 0x66ff, 0xc00d, 0x21, 0 + .dw 0x6740, 0xc00d, 0x677f, 0xc00d, 0x21, 0 + .dw 0x67c0, 0xc00d, 0x67ff, 0xc00d, 0x21, 0 + .dw 0x6840, 0xc00d, 0x687f, 0xc00d, 0x21, 0 + .dw 0x68c0, 0xc00d, 0x68ff, 0xc00d, 0x21, 0 + .dw 0x6940, 0xc00d, 0x697f, 0xc00d, 0x21, 0 + .dw 0x69c0, 0xc00d, 0x69ff, 0xc00d, 0x21, 0 + .dw 0x6a40, 0xc00d, 0x6a7f, 0xc00d, 0x21, 0 + .dw 0x6ac0, 0xc00d, 0x6aff, 0xc00d, 0x21, 0 + .dw 0x6b40, 0xc00d, 0x6b7f, 0xc00d, 0x21, 0 + .dw 0x6bc0, 0xc00d, 0x6bff, 0xc00d, 0x21, 0 + .dw 0x6c40, 0xc00d, 0x6c7f, 0xc00d, 0x21, 0 + .dw 0x6cc0, 0xc00d, 0x6cff, 0xc00d, 0x21, 0 + .dw 0x6d40, 0xc00d, 0x6d7f, 0xc00d, 0x21, 0 + .dw 0x6dc0, 0xc00d, 0x6dff, 0xc00d, 0x21, 0 + .dw 0x6e40, 0xc00d, 0x6e7f, 0xc00d, 0x21, 0 + .dw 0x6ec0, 0xc00d, 0x6eff, 0xc00d, 0x21, 0 + .dw 0x6f40, 0xc00d, 0x6f7f, 0xc00d, 0x21, 0 + .dw 0x6fc0, 0xc00d, 0x6fff, 0xc00d, 0x21, 0 + .dw 0x7040, 0xc00d, 0x707f, 0xc00d, 0x21, 0 + .dw 0x70c0, 0xc00d, 0x70ff, 0xc00d, 0x21, 0 + .dw 0x7140, 0xc00d, 0x717f, 0xc00d, 0x21, 0 + .dw 0x71c0, 0xc00d, 0x71ff, 0xc00d, 0x21, 0 + .dw 0x7240, 0xc00d, 0x727f, 0xc00d, 0x21, 0 + .dw 0x72c0, 0xc00d, 0x72ff, 0xc00d, 0x21, 0 + .dw 0x7340, 0xc00d, 0x737f, 0xc00d, 0x21, 0 + .dw 0x73c0, 0xc00d, 0x73ff, 0xc00d, 0x21, 0 + .dw 0x7440, 0xc00d, 0x747f, 0xc00d, 0x21, 0 + .dw 0x74c0, 0xc00d, 0x74ff, 0xc00d, 0x21, 0 + .dw 0x7540, 0xc00d, 0x757f, 0xc00d, 0x21, 0 + .dw 0x75c0, 0xc00d, 0x75ff, 0xc00d, 0x21, 0 + .dw 0x7640, 0xc00d, 0x767f, 0xc00d, 0x21, 0 + .dw 0x76c0, 0xc00d, 0x76ff, 0xc00d, 0x21, 0 + .dw 0x7740, 0xc00d, 0x777f, 0xc00d, 0x21, 0 + .dw 0x77c0, 0xc00d, 0x77ff, 0xc00d, 0x21, 0 + .dw 0x7840, 0xc00d, 0x787f, 0xc00d, 0x21, 0 + .dw 0x78c0, 0xc00d, 0x78ff, 0xc00d, 0x21, 0 + .dw 0x7940, 0xc00d, 0x797f, 0xc00d, 0x21, 0 + .dw 0x79c0, 0xc00d, 0x7fff, 0xc00d, 0x21, 0 + .dw 0x8040, 0xc00d, 0x807f, 0xc00d, 0x21, 0 + .dw 0x80c0, 0xc00d, 0x80ff, 0xc00d, 0x21, 0 + .dw 0x8140, 0xc00d, 0x817f, 0xc00d, 0x21, 0 + .dw 0x81c0, 0xc00d, 0x81ff, 0xc00d, 0x21, 0 + .dw 0x8240, 0xc00d, 0x827f, 0xc00d, 0x21, 0 + .dw 0x82c0, 0xc00d, 0x82ff, 0xc00d, 0x21, 0 + .dw 0x8340, 0xc00d, 0x837f, 0xc00d, 0x21, 0 + .dw 0x83c0, 0xc00d, 0x83ff, 0xc00d, 0x21, 0 + .dw 0x8440, 0xc00d, 0x847f, 0xc00d, 0x21, 0 + .dw 0x84c0, 0xc00d, 0x84ff, 0xc00d, 0x21, 0 + .dw 0x8540, 0xc00d, 0x857f, 0xc00d, 0x21, 0 + .dw 0x85c0, 0xc00d, 0x85ff, 0xc00d, 0x21, 0 + .dw 0x8640, 0xc00d, 0x867f, 0xc00d, 0x21, 0 + .dw 0x86c0, 0xc00d, 0x86ff, 0xc00d, 0x21, 0 + .dw 0x8740, 0xc00d, 0x877f, 0xc00d, 0x21, 0 + .dw 0x87c0, 0xc00d, 0x87ff, 0xc00d, 0x21, 0 + .dw 0x8840, 0xc00d, 0x887f, 0xc00d, 0x21, 0 + .dw 0x88c0, 0xc00d, 0x88ff, 0xc00d, 0x21, 0 + .dw 0x8940, 0xc00d, 0x897f, 0xc00d, 0x21, 0 + .dw 0x89c0, 0xc00d, 0x89ff, 0xc00d, 0x21, 0 + .dw 0x8a40, 0xc00d, 0x8a7f, 0xc00d, 0x21, 0 + .dw 0x8ac0, 0xc00d, 0x8aff, 0xc00d, 0x21, 0 + .dw 0x8b40, 0xc00d, 0x8b7f, 0xc00d, 0x21, 0 + .dw 0x8bc0, 0xc00d, 0x8bff, 0xc00d, 0x21, 0 + .dw 0x8c40, 0xc00d, 0x8c7f, 0xc00d, 0x21, 0 + .dw 0x8cc0, 0xc00d, 0x8cff, 0xc00d, 0x21, 0 + .dw 0x8d40, 0xc00d, 0x8d7f, 0xc00d, 0x21, 0 + .dw 0x8dc0, 0xc00d, 0x8dff, 0xc00d, 0x21, 0 + .dw 0x8e40, 0xc00d, 0x8e7f, 0xc00d, 0x21, 0 + .dw 0x8ec0, 0xc00d, 0x8eff, 0xc00d, 0x21, 0 + .dw 0x8f40, 0xc00d, 0x8f7f, 0xc00d, 0x21, 0 + .dw 0x8fc0, 0xc00d, 0x8fff, 0xc00d, 0x21, 0 + .dw 0x9040, 0xc00d, 0x907f, 0xc00d, 0x21, 0 + .dw 0x90c0, 0xc00d, 0x90ff, 0xc00d, 0x21, 0 + .dw 0x9140, 0xc00d, 0x917f, 0xc00d, 0x21, 0 + .dw 0x91c0, 0xc00d, 0x91ff, 0xc00d, 0x21, 0 + .dw 0x9240, 0xc00d, 0x927f, 0xc00d, 0x21, 0 + .dw 0x92c0, 0xc00d, 0x92ff, 0xc00d, 0x21, 0 + .dw 0x9340, 0xc00d, 0x937f, 0xc00d, 0x21, 0 + .dw 0x93c0, 0xc00d, 0x93ff, 0xc00d, 0x21, 0 + .dw 0x9440, 0xc00d, 0x947f, 0xc00d, 0x21, 0 + .dw 0x94c0, 0xc00d, 0x94ff, 0xc00d, 0x21, 0 + .dw 0x9540, 0xc00d, 0x957f, 0xc00d, 0x21, 0 + .dw 0x95c0, 0xc00d, 0x95ff, 0xc00d, 0x21, 0 + .dw 0x9640, 0xc00d, 0x967f, 0xc00d, 0x21, 0 + .dw 0x96c0, 0xc00d, 0x96ff, 0xc00d, 0x21, 0 + .dw 0x9740, 0xc00d, 0x977f, 0xc00d, 0x21, 0 + .dw 0x97c0, 0xc00d, 0x97ff, 0xc00d, 0x21, 0 + .dw 0x9840, 0xc00d, 0x987f, 0xc00d, 0x21, 0 + .dw 0x98c0, 0xc00d, 0x98ff, 0xc00d, 0x21, 0 + .dw 0x9940, 0xc00d, 0x997f, 0xc00d, 0x21, 0 + .dw 0x99c0, 0xc00d, 0x9fff, 0xc00d, 0x21, 0 + .dw 0xa040, 0xc00d, 0xa07f, 0xc00d, 0x21, 0 + .dw 0xa0c0, 0xc00d, 0xa0ff, 0xc00d, 0x21, 0 + .dw 0xa140, 0xc00d, 0xa17f, 0xc00d, 0x21, 0 + .dw 0xa1c0, 0xc00d, 0xa1ff, 0xc00d, 0x21, 0 + .dw 0xa240, 0xc00d, 0xa27f, 0xc00d, 0x21, 0 + .dw 0xa2c0, 0xc00d, 0xa2ff, 0xc00d, 0x21, 0 + .dw 0xa340, 0xc00d, 0xa37f, 0xc00d, 0x21, 0 + .dw 0xa3c0, 0xc00d, 0xa3ff, 0xc00d, 0x21, 0 + .dw 0xa440, 0xc00d, 0xa47f, 0xc00d, 0x21, 0 + .dw 0xa4c0, 0xc00d, 0xa4ff, 0xc00d, 0x21, 0 + .dw 0xa540, 0xc00d, 0xa57f, 0xc00d, 0x21, 0 + .dw 0xa5c0, 0xc00d, 0xa5ff, 0xc00d, 0x21, 0 + .dw 0xa640, 0xc00d, 0xa67f, 0xc00d, 0x21, 0 + .dw 0xa6c0, 0xc00d, 0xa6ff, 0xc00d, 0x21, 0 + .dw 0xa740, 0xc00d, 0xa77f, 0xc00d, 0x21, 0 + .dw 0xa7c0, 0xc00d, 0xa7ff, 0xc00d, 0x21, 0 + .dw 0xa840, 0xc00d, 0xa87f, 0xc00d, 0x21, 0 + .dw 0xa8c0, 0xc00d, 0xa8ff, 0xc00d, 0x21, 0 + .dw 0xa940, 0xc00d, 0xa97f, 0xc00d, 0x21, 0 + .dw 0xa9c0, 0xc00d, 0xa9ff, 0xc00d, 0x21, 0 + .dw 0xaa40, 0xc00d, 0xaa7f, 0xc00d, 0x21, 0 + .dw 0xaac0, 0xc00d, 0xaaff, 0xc00d, 0x21, 0 + .dw 0xab40, 0xc00d, 0xab7f, 0xc00d, 0x21, 0 + .dw 0xabc0, 0xc00d, 0xabff, 0xc00d, 0x21, 0 + .dw 0xac40, 0xc00d, 0xac7f, 0xc00d, 0x21, 0 + .dw 0xacc0, 0xc00d, 0xacff, 0xc00d, 0x21, 0 + .dw 0xad40, 0xc00d, 0xad7f, 0xc00d, 0x21, 0 + .dw 0xadc0, 0xc00d, 0xadff, 0xc00d, 0x21, 0 + .dw 0xae40, 0xc00d, 0xae7f, 0xc00d, 0x21, 0 + .dw 0xaec0, 0xc00d, 0xaeff, 0xc00d, 0x21, 0 + .dw 0xaf40, 0xc00d, 0xaf7f, 0xc00d, 0x21, 0 + .dw 0xafc0, 0xc00d, 0xafff, 0xc00d, 0x21, 0 + .dw 0xb040, 0xc00d, 0xb07f, 0xc00d, 0x21, 0 + .dw 0xb0c0, 0xc00d, 0xb0ff, 0xc00d, 0x21, 0 + .dw 0xb140, 0xc00d, 0xb17f, 0xc00d, 0x21, 0 + .dw 0xb1c0, 0xc00d, 0xb1ff, 0xc00d, 0x21, 0 + .dw 0xb240, 0xc00d, 0xb27f, 0xc00d, 0x21, 0 + .dw 0xb2c0, 0xc00d, 0xb2ff, 0xc00d, 0x21, 0 + .dw 0xb340, 0xc00d, 0xb37f, 0xc00d, 0x21, 0 + .dw 0xb3c0, 0xc00d, 0xb3ff, 0xc00d, 0x21, 0 + .dw 0xb440, 0xc00d, 0xb47f, 0xc00d, 0x21, 0 + .dw 0xb4c0, 0xc00d, 0xb4ff, 0xc00d, 0x21, 0 + .dw 0xb540, 0xc00d, 0xb57f, 0xc00d, 0x21, 0 + .dw 0xb5c0, 0xc00d, 0xb5ff, 0xc00d, 0x21, 0 + .dw 0xb640, 0xc00d, 0xb67f, 0xc00d, 0x21, 0 + .dw 0xb6c0, 0xc00d, 0xb6ff, 0xc00d, 0x21, 0 + .dw 0xb740, 0xc00d, 0xb77f, 0xc00d, 0x21, 0 + .dw 0xb7c0, 0xc00d, 0xb7ff, 0xc00d, 0x21, 0 + .dw 0xb840, 0xc00d, 0xb87f, 0xc00d, 0x21, 0 + .dw 0xb8c0, 0xc00d, 0xb8ff, 0xc00d, 0x21, 0 + .dw 0xb940, 0xc00d, 0xb97f, 0xc00d, 0x21, 0 + .dw 0xb9c0, 0xc00d, 0xbfff, 0xc00d, 0x21, 0 + .dw 0xc040, 0xc00d, 0xc07f, 0xc00d, 0x21, 0 + .dw 0xc0c0, 0xc00d, 0xc0ff, 0xc00d, 0x21, 0 + .dw 0xc140, 0xc00d, 0xc17f, 0xc00d, 0x21, 0 + .dw 0xc1c0, 0xc00d, 0xc1ff, 0xc00d, 0x21, 0 + .dw 0xc240, 0xc00d, 0xc27f, 0xc00d, 0x21, 0 + .dw 0xc2c0, 0xc00d, 0xc2ff, 0xc00d, 0x21, 0 + .dw 0xc340, 0xc00d, 0xc37f, 0xc00d, 0x21, 0 + .dw 0xc3c0, 0xc00d, 0xc3ff, 0xc00d, 0x21, 0 + .dw 0xc440, 0xc00d, 0xc47f, 0xc00d, 0x21, 0 + .dw 0xc4c0, 0xc00d, 0xc4ff, 0xc00d, 0x21, 0 + .dw 0xc540, 0xc00d, 0xc57f, 0xc00d, 0x21, 0 + .dw 0xc5c0, 0xc00d, 0xc5ff, 0xc00d, 0x21, 0 + .dw 0xc640, 0xc00d, 0xc67f, 0xc00d, 0x21, 0 + .dw 0xc6c0, 0xc00d, 0xc6ff, 0xc00d, 0x21, 0 + .dw 0xc740, 0xc00d, 0xc77f, 0xc00d, 0x21, 0 + .dw 0xc7c0, 0xc00d, 0xc7ff, 0xc00d, 0x21, 0 + .dw 0xc840, 0xc00d, 0xc87f, 0xc00d, 0x21, 0 + .dw 0xc8c0, 0xc00d, 0xc8ff, 0xc00d, 0x21, 0 + .dw 0xc940, 0xc00d, 0xc97f, 0xc00d, 0x21, 0 + .dw 0xc9c0, 0xc00d, 0xc9ff, 0xc00d, 0x21, 0 + .dw 0xca40, 0xc00d, 0xca7f, 0xc00d, 0x21, 0 + .dw 0xcac0, 0xc00d, 0xcaff, 0xc00d, 0x21, 0 + .dw 0xcb40, 0xc00d, 0xcb7f, 0xc00d, 0x21, 0 + .dw 0xcbc0, 0xc00d, 0xcbff, 0xc00d, 0x21, 0 + .dw 0xcc40, 0xc00d, 0xcc7f, 0xc00d, 0x21, 0 + .dw 0xccc0, 0xc00d, 0xccff, 0xc00d, 0x21, 0 + .dw 0xcd40, 0xc00d, 0xcd7f, 0xc00d, 0x21, 0 + .dw 0xcdc0, 0xc00d, 0xcdff, 0xc00d, 0x21, 0 + .dw 0xce40, 0xc00d, 0xce7f, 0xc00d, 0x21, 0 + .dw 0xcec0, 0xc00d, 0xceff, 0xc00d, 0x21, 0 + .dw 0xcf40, 0xc00d, 0xcf7f, 0xc00d, 0x21, 0 + .dw 0xcfc0, 0xc00d, 0xcfff, 0xc00d, 0x21, 0 + .dw 0xd040, 0xc00d, 0xd07f, 0xc00d, 0x21, 0 + .dw 0xd0c0, 0xc00d, 0xd0ff, 0xc00d, 0x21, 0 + .dw 0xd140, 0xc00d, 0xd17f, 0xc00d, 0x21, 0 + .dw 0xd1c0, 0xc00d, 0xd1ff, 0xc00d, 0x21, 0 + .dw 0xd240, 0xc00d, 0xd27f, 0xc00d, 0x21, 0 + .dw 0xd2c0, 0xc00d, 0xd2ff, 0xc00d, 0x21, 0 + .dw 0xd340, 0xc00d, 0xd37f, 0xc00d, 0x21, 0 + .dw 0xd3c0, 0xc00d, 0xd3ff, 0xc00d, 0x21, 0 + .dw 0xd440, 0xc00d, 0xd47f, 0xc00d, 0x21, 0 + .dw 0xd4c0, 0xc00d, 0xd4ff, 0xc00d, 0x21, 0 + .dw 0xd540, 0xc00d, 0xd57f, 0xc00d, 0x21, 0 + .dw 0xd5c0, 0xc00d, 0xd5ff, 0xc00d, 0x21, 0 + .dw 0xd640, 0xc00d, 0xd67f, 0xc00d, 0x21, 0 + .dw 0xd6c0, 0xc00d, 0xd6ff, 0xc00d, 0x21, 0 + .dw 0xd740, 0xc00d, 0xd77f, 0xc00d, 0x21, 0 + .dw 0xd7c0, 0xc00d, 0xd7ff, 0xc00d, 0x21, 0 + .dw 0xd840, 0xc00d, 0xd87f, 0xc00d, 0x21, 0 + .dw 0xd8c0, 0xc00d, 0xd8ff, 0xc00d, 0x21, 0 + .dw 0xd940, 0xc00d, 0xd97f, 0xc00d, 0x21, 0 + .dw 0xd9c0, 0xc00d, 0xdfff, 0xc00d, 0x21, 0 + .dw 0xe040, 0xc00d, 0xe07f, 0xc00d, 0x21, 0 + .dw 0xe0c0, 0xc00d, 0xe0ff, 0xc00d, 0x21, 0 + .dw 0xe140, 0xc00d, 0xe17f, 0xc00d, 0x21, 0 + .dw 0xe1c0, 0xc00d, 0xe1ff, 0xc00d, 0x21, 0 + .dw 0xe240, 0xc00d, 0xe27f, 0xc00d, 0x21, 0 + .dw 0xe2c0, 0xc00d, 0xe2ff, 0xc00d, 0x21, 0 + .dw 0xe340, 0xc00d, 0xe37f, 0xc00d, 0x21, 0 + .dw 0xe3c0, 0xc00d, 0xe3ff, 0xc00d, 0x21, 0 + .dw 0xe440, 0xc00d, 0xe47f, 0xc00d, 0x21, 0 + .dw 0xe4c0, 0xc00d, 0xe4ff, 0xc00d, 0x21, 0 + .dw 0xe540, 0xc00d, 0xe57f, 0xc00d, 0x21, 0 + .dw 0xe5c0, 0xc00d, 0xe5ff, 0xc00d, 0x21, 0 + .dw 0xe640, 0xc00d, 0xe67f, 0xc00d, 0x21, 0 + .dw 0xe6c0, 0xc00d, 0xe6ff, 0xc00d, 0x21, 0 + .dw 0xe740, 0xc00d, 0xe77f, 0xc00d, 0x21, 0 + .dw 0xe7c0, 0xc00d, 0xe7ff, 0xc00d, 0x21, 0 + .dw 0xe840, 0xc00d, 0xe87f, 0xc00d, 0x21, 0 + .dw 0xe8c0, 0xc00d, 0xe8ff, 0xc00d, 0x21, 0 + .dw 0xe940, 0xc00d, 0xe97f, 0xc00d, 0x21, 0 + .dw 0xe9c0, 0xc00d, 0xe9ff, 0xc00d, 0x21, 0 + .dw 0xea40, 0xc00d, 0xea7f, 0xc00d, 0x21, 0 + .dw 0xeac0, 0xc00d, 0xeaff, 0xc00d, 0x21, 0 + .dw 0xeb40, 0xc00d, 0xeb7f, 0xc00d, 0x21, 0 + .dw 0xebc0, 0xc00d, 0xebff, 0xc00d, 0x21, 0 + .dw 0xec40, 0xc00d, 0xec7f, 0xc00d, 0x21, 0 + .dw 0xecc0, 0xc00d, 0xecff, 0xc00d, 0x21, 0 + .dw 0xed40, 0xc00d, 0xed7f, 0xc00d, 0x21, 0 + .dw 0xedc0, 0xc00d, 0xedff, 0xc00d, 0x21, 0 + .dw 0xee40, 0xc00d, 0xee7f, 0xc00d, 0x21, 0 + .dw 0xeec0, 0xc00d, 0xeeff, 0xc00d, 0x21, 0 + .dw 0xef40, 0xc00d, 0xef7f, 0xc00d, 0x21, 0 + .dw 0xefc0, 0xc00d, 0xefff, 0xc00d, 0x21, 0 + .dw 0xf040, 0xc00d, 0xf07f, 0xc00d, 0x21, 0 + .dw 0xf0c0, 0xc00d, 0xf0ff, 0xc00d, 0x21, 0 + .dw 0xf140, 0xc00d, 0xf17f, 0xc00d, 0x21, 0 + .dw 0xf1c0, 0xc00d, 0xf1ff, 0xc00d, 0x21, 0 + .dw 0xf240, 0xc00d, 0xf27f, 0xc00d, 0x21, 0 + .dw 0xf2c0, 0xc00d, 0xf2ff, 0xc00d, 0x21, 0 + .dw 0xf340, 0xc00d, 0xf37f, 0xc00d, 0x21, 0 + .dw 0xf3c0, 0xc00d, 0xf3ff, 0xc00d, 0x21, 0 + .dw 0xf440, 0xc00d, 0xf47f, 0xc00d, 0x21, 0 + .dw 0xf4c0, 0xc00d, 0xf4ff, 0xc00d, 0x21, 0 + .dw 0xf540, 0xc00d, 0xf57f, 0xc00d, 0x21, 0 + .dw 0xf5c0, 0xc00d, 0xf5ff, 0xc00d, 0x21, 0 + .dw 0xf640, 0xc00d, 0xf67f, 0xc00d, 0x21, 0 + .dw 0xf6c0, 0xc00d, 0xf6ff, 0xc00d, 0x21, 0 + .dw 0xf740, 0xc00d, 0xf77f, 0xc00d, 0x21, 0 + .dw 0xf7c0, 0xc00d, 0xf7ff, 0xc00d, 0x21, 0 + .dw 0xf840, 0xc00d, 0xf87f, 0xc00d, 0x21, 0 + .dw 0xf8c0, 0xc00d, 0xf8ff, 0xc00d, 0x21, 0 + .dw 0xf940, 0xc00d, 0xf97f, 0xc00d, 0x21, 0 + .dw 0xf9c0, 0xc00d, 0xffff, 0xc00d, 0x21, 0 + .dw 0x0040, 0xc00e, 0x007f, 0xc00e, 0x21, 0 + .dw 0x00c0, 0xc00e, 0x00ff, 0xc00e, 0x21, 0 + .dw 0x0140, 0xc00e, 0x017f, 0xc00e, 0x21, 0 + .dw 0x01c0, 0xc00e, 0x01ff, 0xc00e, 0x21, 0 + .dw 0x0240, 0xc00e, 0x027f, 0xc00e, 0x21, 0 + .dw 0x02c0, 0xc00e, 0x02ff, 0xc00e, 0x21, 0 + .dw 0x0340, 0xc00e, 0x037f, 0xc00e, 0x21, 0 + .dw 0x03c0, 0xc00e, 0x03ff, 0xc00e, 0x21, 0 + .dw 0x0440, 0xc00e, 0x047f, 0xc00e, 0x21, 0 + .dw 0x04c0, 0xc00e, 0x04ff, 0xc00e, 0x21, 0 + .dw 0x0540, 0xc00e, 0x057f, 0xc00e, 0x21, 0 + .dw 0x05c0, 0xc00e, 0x05ff, 0xc00e, 0x21, 0 + .dw 0x0640, 0xc00e, 0x067f, 0xc00e, 0x21, 0 + .dw 0x06c0, 0xc00e, 0x06ff, 0xc00e, 0x21, 0 + .dw 0x0740, 0xc00e, 0x077f, 0xc00e, 0x21, 0 + .dw 0x07c0, 0xc00e, 0x07ff, 0xc00e, 0x21, 0 + .dw 0x0840, 0xc00e, 0x087f, 0xc00e, 0x21, 0 + .dw 0x08c0, 0xc00e, 0x08ff, 0xc00e, 0x21, 0 + .dw 0x0940, 0xc00e, 0x097f, 0xc00e, 0x21, 0 + .dw 0x09c0, 0xc00e, 0x09ff, 0xc00e, 0x21, 0 + .dw 0x0a40, 0xc00e, 0x0a7f, 0xc00e, 0x21, 0 + .dw 0x0ac0, 0xc00e, 0x0aff, 0xc00e, 0x21, 0 + .dw 0x0b40, 0xc00e, 0x0b7f, 0xc00e, 0x21, 0 + .dw 0x0bc0, 0xc00e, 0x0bff, 0xc00e, 0x21, 0 + .dw 0x0c40, 0xc00e, 0x0c7f, 0xc00e, 0x21, 0 + .dw 0x0cc0, 0xc00e, 0x0cff, 0xc00e, 0x21, 0 + .dw 0x0d40, 0xc00e, 0x0d7f, 0xc00e, 0x21, 0 + .dw 0x0dc0, 0xc00e, 0x0dff, 0xc00e, 0x21, 0 + .dw 0x0e40, 0xc00e, 0x0e7f, 0xc00e, 0x21, 0 + .dw 0x0ec0, 0xc00e, 0x0eff, 0xc00e, 0x21, 0 + .dw 0x0f40, 0xc00e, 0x0f7f, 0xc00e, 0x21, 0 + .dw 0x0fc0, 0xc00e, 0x0fff, 0xc00e, 0x21, 0 + .dw 0x1040, 0xc00e, 0x107f, 0xc00e, 0x21, 0 + .dw 0x10c0, 0xc00e, 0x10ff, 0xc00e, 0x21, 0 + .dw 0x1140, 0xc00e, 0x117f, 0xc00e, 0x21, 0 + .dw 0x11c0, 0xc00e, 0x11ff, 0xc00e, 0x21, 0 + .dw 0x1240, 0xc00e, 0x127f, 0xc00e, 0x21, 0 + .dw 0x12c0, 0xc00e, 0x12ff, 0xc00e, 0x21, 0 + .dw 0x1340, 0xc00e, 0x137f, 0xc00e, 0x21, 0 + .dw 0x13c0, 0xc00e, 0x13ff, 0xc00e, 0x21, 0 + .dw 0x1440, 0xc00e, 0x147f, 0xc00e, 0x21, 0 + .dw 0x14c0, 0xc00e, 0x14ff, 0xc00e, 0x21, 0 + .dw 0x1540, 0xc00e, 0x157f, 0xc00e, 0x21, 0 + .dw 0x15c0, 0xc00e, 0x15ff, 0xc00e, 0x21, 0 + .dw 0x1640, 0xc00e, 0x167f, 0xc00e, 0x21, 0 + .dw 0x16c0, 0xc00e, 0x16ff, 0xc00e, 0x21, 0 + .dw 0x1740, 0xc00e, 0x177f, 0xc00e, 0x21, 0 + .dw 0x17c0, 0xc00e, 0x17ff, 0xc00e, 0x21, 0 + .dw 0x1840, 0xc00e, 0x187f, 0xc00e, 0x21, 0 + .dw 0x18c0, 0xc00e, 0x18ff, 0xc00e, 0x21, 0 + .dw 0x1940, 0xc00e, 0x197f, 0xc00e, 0x21, 0 + .dw 0x19c0, 0xc00e, 0x1fff, 0xc00e, 0x21, 0 + .dw 0x2040, 0xc00e, 0x207f, 0xc00e, 0x21, 0 + .dw 0x20c0, 0xc00e, 0x20ff, 0xc00e, 0x21, 0 + .dw 0x2140, 0xc00e, 0x217f, 0xc00e, 0x21, 0 + .dw 0x21c0, 0xc00e, 0x21ff, 0xc00e, 0x21, 0 + .dw 0x2240, 0xc00e, 0x227f, 0xc00e, 0x21, 0 + .dw 0x22c0, 0xc00e, 0x22ff, 0xc00e, 0x21, 0 + .dw 0x2340, 0xc00e, 0x237f, 0xc00e, 0x21, 0 + .dw 0x23c0, 0xc00e, 0x23ff, 0xc00e, 0x21, 0 + .dw 0x2440, 0xc00e, 0x247f, 0xc00e, 0x21, 0 + .dw 0x24c0, 0xc00e, 0x24ff, 0xc00e, 0x21, 0 + .dw 0x2540, 0xc00e, 0x257f, 0xc00e, 0x21, 0 + .dw 0x25c0, 0xc00e, 0x25ff, 0xc00e, 0x21, 0 + .dw 0x2640, 0xc00e, 0x267f, 0xc00e, 0x21, 0 + .dw 0x26c0, 0xc00e, 0x26ff, 0xc00e, 0x21, 0 + .dw 0x2740, 0xc00e, 0x277f, 0xc00e, 0x21, 0 + .dw 0x27c0, 0xc00e, 0x27ff, 0xc00e, 0x21, 0 + .dw 0x2840, 0xc00e, 0x287f, 0xc00e, 0x21, 0 + .dw 0x28c0, 0xc00e, 0x28ff, 0xc00e, 0x21, 0 + .dw 0x2940, 0xc00e, 0x297f, 0xc00e, 0x21, 0 + .dw 0x29c0, 0xc00e, 0x29ff, 0xc00e, 0x21, 0 + .dw 0x2a40, 0xc00e, 0x2a7f, 0xc00e, 0x21, 0 + .dw 0x2ac0, 0xc00e, 0x2aff, 0xc00e, 0x21, 0 + .dw 0x2b40, 0xc00e, 0x2b7f, 0xc00e, 0x21, 0 + .dw 0x2bc0, 0xc00e, 0x2bff, 0xc00e, 0x21, 0 + .dw 0x2c40, 0xc00e, 0x2c7f, 0xc00e, 0x21, 0 + .dw 0x2cc0, 0xc00e, 0x2cff, 0xc00e, 0x21, 0 + .dw 0x2d40, 0xc00e, 0x2d7f, 0xc00e, 0x21, 0 + .dw 0x2dc0, 0xc00e, 0x2dff, 0xc00e, 0x21, 0 + .dw 0x2e40, 0xc00e, 0x2e7f, 0xc00e, 0x21, 0 + .dw 0x2ec0, 0xc00e, 0x2eff, 0xc00e, 0x21, 0 + .dw 0x2f40, 0xc00e, 0x2f7f, 0xc00e, 0x21, 0 + .dw 0x2fc0, 0xc00e, 0x2fff, 0xc00e, 0x21, 0 + .dw 0x3040, 0xc00e, 0x307f, 0xc00e, 0x21, 0 + .dw 0x30c0, 0xc00e, 0x30ff, 0xc00e, 0x21, 0 + .dw 0x3140, 0xc00e, 0x317f, 0xc00e, 0x21, 0 + .dw 0x31c0, 0xc00e, 0x31ff, 0xc00e, 0x21, 0 + .dw 0x3240, 0xc00e, 0x327f, 0xc00e, 0x21, 0 + .dw 0x32c0, 0xc00e, 0x32ff, 0xc00e, 0x21, 0 + .dw 0x3340, 0xc00e, 0x337f, 0xc00e, 0x21, 0 + .dw 0x33c0, 0xc00e, 0x33ff, 0xc00e, 0x21, 0 + .dw 0x3440, 0xc00e, 0x347f, 0xc00e, 0x21, 0 + .dw 0x34c0, 0xc00e, 0x34ff, 0xc00e, 0x21, 0 + .dw 0x3540, 0xc00e, 0x357f, 0xc00e, 0x21, 0 + .dw 0x35c0, 0xc00e, 0x35ff, 0xc00e, 0x21, 0 + .dw 0x3640, 0xc00e, 0x367f, 0xc00e, 0x21, 0 + .dw 0x36c0, 0xc00e, 0x36ff, 0xc00e, 0x21, 0 + .dw 0x3740, 0xc00e, 0x377f, 0xc00e, 0x21, 0 + .dw 0x37c0, 0xc00e, 0x37ff, 0xc00e, 0x21, 0 + .dw 0x3840, 0xc00e, 0x387f, 0xc00e, 0x21, 0 + .dw 0x38c0, 0xc00e, 0x38ff, 0xc00e, 0x21, 0 + .dw 0x3940, 0xc00e, 0x397f, 0xc00e, 0x21, 0 + .dw 0x39c0, 0xc00e, 0x3fff, 0xc00e, 0x21, 0 + .dw 0x4040, 0xc00e, 0x407f, 0xc00e, 0x21, 0 + .dw 0x40c0, 0xc00e, 0x40ff, 0xc00e, 0x21, 0 + .dw 0x4140, 0xc00e, 0x417f, 0xc00e, 0x21, 0 + .dw 0x41c0, 0xc00e, 0x41ff, 0xc00e, 0x21, 0 + .dw 0x4240, 0xc00e, 0x427f, 0xc00e, 0x21, 0 + .dw 0x42c0, 0xc00e, 0x42ff, 0xc00e, 0x21, 0 + .dw 0x4340, 0xc00e, 0x437f, 0xc00e, 0x21, 0 + .dw 0x43c0, 0xc00e, 0x43ff, 0xc00e, 0x21, 0 + .dw 0x4440, 0xc00e, 0x447f, 0xc00e, 0x21, 0 + .dw 0x44c0, 0xc00e, 0x44ff, 0xc00e, 0x21, 0 + .dw 0x4540, 0xc00e, 0x457f, 0xc00e, 0x21, 0 + .dw 0x45c0, 0xc00e, 0x45ff, 0xc00e, 0x21, 0 + .dw 0x4640, 0xc00e, 0x467f, 0xc00e, 0x21, 0 + .dw 0x46c0, 0xc00e, 0x46ff, 0xc00e, 0x21, 0 + .dw 0x4740, 0xc00e, 0x477f, 0xc00e, 0x21, 0 + .dw 0x47c0, 0xc00e, 0x47ff, 0xc00e, 0x21, 0 + .dw 0x4840, 0xc00e, 0x487f, 0xc00e, 0x21, 0 + .dw 0x48c0, 0xc00e, 0x48ff, 0xc00e, 0x21, 0 + .dw 0x4940, 0xc00e, 0x497f, 0xc00e, 0x21, 0 + .dw 0x49c0, 0xc00e, 0x49ff, 0xc00e, 0x21, 0 + .dw 0x4a40, 0xc00e, 0x4a7f, 0xc00e, 0x21, 0 + .dw 0x4ac0, 0xc00e, 0x4aff, 0xc00e, 0x21, 0 + .dw 0x4b40, 0xc00e, 0x4b7f, 0xc00e, 0x21, 0 + .dw 0x4bc0, 0xc00e, 0x4bff, 0xc00e, 0x21, 0 + .dw 0x4c40, 0xc00e, 0x4c7f, 0xc00e, 0x21, 0 + .dw 0x4cc0, 0xc00e, 0x4cff, 0xc00e, 0x21, 0 + .dw 0x4d40, 0xc00e, 0x4d7f, 0xc00e, 0x21, 0 + .dw 0x4dc0, 0xc00e, 0x4dff, 0xc00e, 0x21, 0 + .dw 0x4e40, 0xc00e, 0x4e7f, 0xc00e, 0x21, 0 + .dw 0x4ec0, 0xc00e, 0x4eff, 0xc00e, 0x21, 0 + .dw 0x4f40, 0xc00e, 0x4f7f, 0xc00e, 0x21, 0 + .dw 0x4fc0, 0xc00e, 0x4fff, 0xc00e, 0x21, 0 + .dw 0x5040, 0xc00e, 0x507f, 0xc00e, 0x21, 0 + .dw 0x50c0, 0xc00e, 0x50ff, 0xc00e, 0x21, 0 + .dw 0x5140, 0xc00e, 0x517f, 0xc00e, 0x21, 0 + .dw 0x51c0, 0xc00e, 0x51ff, 0xc00e, 0x21, 0 + .dw 0x5240, 0xc00e, 0x527f, 0xc00e, 0x21, 0 + .dw 0x52c0, 0xc00e, 0x52ff, 0xc00e, 0x21, 0 + .dw 0x5340, 0xc00e, 0x537f, 0xc00e, 0x21, 0 + .dw 0x53c0, 0xc00e, 0x53ff, 0xc00e, 0x21, 0 + .dw 0x5440, 0xc00e, 0x547f, 0xc00e, 0x21, 0 + .dw 0x54c0, 0xc00e, 0x54ff, 0xc00e, 0x21, 0 + .dw 0x5540, 0xc00e, 0x557f, 0xc00e, 0x21, 0 + .dw 0x55c0, 0xc00e, 0x55ff, 0xc00e, 0x21, 0 + .dw 0x5640, 0xc00e, 0x567f, 0xc00e, 0x21, 0 + .dw 0x56c0, 0xc00e, 0x56ff, 0xc00e, 0x21, 0 + .dw 0x5740, 0xc00e, 0x577f, 0xc00e, 0x21, 0 + .dw 0x57c0, 0xc00e, 0x57ff, 0xc00e, 0x21, 0 + .dw 0x5840, 0xc00e, 0x587f, 0xc00e, 0x21, 0 + .dw 0x58c0, 0xc00e, 0x58ff, 0xc00e, 0x21, 0 + .dw 0x5940, 0xc00e, 0x597f, 0xc00e, 0x21, 0 + .dw 0x59c0, 0xc00e, 0x5fff, 0xc00e, 0x21, 0 + .dw 0x6040, 0xc00e, 0x607f, 0xc00e, 0x21, 0 + .dw 0x60c0, 0xc00e, 0x60ff, 0xc00e, 0x21, 0 + .dw 0x6140, 0xc00e, 0x617f, 0xc00e, 0x21, 0 + .dw 0x61c0, 0xc00e, 0x61ff, 0xc00e, 0x21, 0 + .dw 0x6240, 0xc00e, 0x627f, 0xc00e, 0x21, 0 + .dw 0x62c0, 0xc00e, 0x62ff, 0xc00e, 0x21, 0 + .dw 0x6340, 0xc00e, 0x637f, 0xc00e, 0x21, 0 + .dw 0x63c0, 0xc00e, 0x63ff, 0xc00e, 0x21, 0 + .dw 0x6440, 0xc00e, 0x647f, 0xc00e, 0x21, 0 + .dw 0x64c0, 0xc00e, 0x64ff, 0xc00e, 0x21, 0 + .dw 0x6540, 0xc00e, 0x657f, 0xc00e, 0x21, 0 + .dw 0x65c0, 0xc00e, 0x65ff, 0xc00e, 0x21, 0 + .dw 0x6640, 0xc00e, 0x667f, 0xc00e, 0x21, 0 + .dw 0x66c0, 0xc00e, 0x66ff, 0xc00e, 0x21, 0 + .dw 0x6740, 0xc00e, 0x677f, 0xc00e, 0x21, 0 + .dw 0x67c0, 0xc00e, 0x67ff, 0xc00e, 0x21, 0 + .dw 0x6840, 0xc00e, 0x687f, 0xc00e, 0x21, 0 + .dw 0x68c0, 0xc00e, 0x68ff, 0xc00e, 0x21, 0 + .dw 0x6940, 0xc00e, 0x697f, 0xc00e, 0x21, 0 + .dw 0x69c0, 0xc00e, 0x69ff, 0xc00e, 0x21, 0 + .dw 0x6a40, 0xc00e, 0x6a7f, 0xc00e, 0x21, 0 + .dw 0x6ac0, 0xc00e, 0x6aff, 0xc00e, 0x21, 0 + .dw 0x6b40, 0xc00e, 0x6b7f, 0xc00e, 0x21, 0 + .dw 0x6bc0, 0xc00e, 0x6bff, 0xc00e, 0x21, 0 + .dw 0x6c40, 0xc00e, 0x6c7f, 0xc00e, 0x21, 0 + .dw 0x6cc0, 0xc00e, 0x6cff, 0xc00e, 0x21, 0 + .dw 0x6d40, 0xc00e, 0x6d7f, 0xc00e, 0x21, 0 + .dw 0x6dc0, 0xc00e, 0x6dff, 0xc00e, 0x21, 0 + .dw 0x6e40, 0xc00e, 0x6e7f, 0xc00e, 0x21, 0 + .dw 0x6ec0, 0xc00e, 0x6eff, 0xc00e, 0x21, 0 + .dw 0x6f40, 0xc00e, 0x6f7f, 0xc00e, 0x21, 0 + .dw 0x6fc0, 0xc00e, 0x6fff, 0xc00e, 0x21, 0 + .dw 0x7040, 0xc00e, 0x707f, 0xc00e, 0x21, 0 + .dw 0x70c0, 0xc00e, 0x70ff, 0xc00e, 0x21, 0 + .dw 0x7140, 0xc00e, 0x717f, 0xc00e, 0x21, 0 + .dw 0x71c0, 0xc00e, 0x71ff, 0xc00e, 0x21, 0 + .dw 0x7240, 0xc00e, 0x727f, 0xc00e, 0x21, 0 + .dw 0x72c0, 0xc00e, 0x72ff, 0xc00e, 0x21, 0 + .dw 0x7340, 0xc00e, 0x737f, 0xc00e, 0x21, 0 + .dw 0x73c0, 0xc00e, 0x73ff, 0xc00e, 0x21, 0 + .dw 0x7440, 0xc00e, 0x747f, 0xc00e, 0x21, 0 + .dw 0x74c0, 0xc00e, 0x74ff, 0xc00e, 0x21, 0 + .dw 0x7540, 0xc00e, 0x757f, 0xc00e, 0x21, 0 + .dw 0x75c0, 0xc00e, 0x75ff, 0xc00e, 0x21, 0 + .dw 0x7640, 0xc00e, 0x767f, 0xc00e, 0x21, 0 + .dw 0x76c0, 0xc00e, 0x76ff, 0xc00e, 0x21, 0 + .dw 0x7740, 0xc00e, 0x777f, 0xc00e, 0x21, 0 + .dw 0x77c0, 0xc00e, 0x77ff, 0xc00e, 0x21, 0 + .dw 0x7840, 0xc00e, 0x787f, 0xc00e, 0x21, 0 + .dw 0x78c0, 0xc00e, 0x78ff, 0xc00e, 0x21, 0 + .dw 0x7940, 0xc00e, 0x797f, 0xc00e, 0x21, 0 + .dw 0x79c0, 0xc00e, 0x7fff, 0xc00e, 0x21, 0 + .dw 0x8040, 0xc00e, 0x807f, 0xc00e, 0x21, 0 + .dw 0x80c0, 0xc00e, 0x80ff, 0xc00e, 0x21, 0 + .dw 0x8140, 0xc00e, 0x817f, 0xc00e, 0x21, 0 + .dw 0x81c0, 0xc00e, 0x81ff, 0xc00e, 0x21, 0 + .dw 0x8240, 0xc00e, 0x827f, 0xc00e, 0x21, 0 + .dw 0x82c0, 0xc00e, 0x82ff, 0xc00e, 0x21, 0 + .dw 0x8340, 0xc00e, 0x837f, 0xc00e, 0x21, 0 + .dw 0x83c0, 0xc00e, 0x83ff, 0xc00e, 0x21, 0 + .dw 0x8440, 0xc00e, 0x847f, 0xc00e, 0x21, 0 + .dw 0x84c0, 0xc00e, 0x84ff, 0xc00e, 0x21, 0 + .dw 0x8540, 0xc00e, 0x857f, 0xc00e, 0x21, 0 + .dw 0x85c0, 0xc00e, 0x85ff, 0xc00e, 0x21, 0 + .dw 0x8640, 0xc00e, 0x867f, 0xc00e, 0x21, 0 + .dw 0x86c0, 0xc00e, 0x86ff, 0xc00e, 0x21, 0 + .dw 0x8740, 0xc00e, 0x877f, 0xc00e, 0x21, 0 + .dw 0x87c0, 0xc00e, 0x87ff, 0xc00e, 0x21, 0 + .dw 0x8840, 0xc00e, 0x887f, 0xc00e, 0x21, 0 + .dw 0x88c0, 0xc00e, 0x88ff, 0xc00e, 0x21, 0 + .dw 0x8940, 0xc00e, 0x897f, 0xc00e, 0x21, 0 + .dw 0x89c0, 0xc00e, 0x89ff, 0xc00e, 0x21, 0 + .dw 0x8a40, 0xc00e, 0x8a7f, 0xc00e, 0x21, 0 + .dw 0x8ac0, 0xc00e, 0x8aff, 0xc00e, 0x21, 0 + .dw 0x8b40, 0xc00e, 0x8b7f, 0xc00e, 0x21, 0 + .dw 0x8bc0, 0xc00e, 0x8bff, 0xc00e, 0x21, 0 + .dw 0x8c40, 0xc00e, 0x8c7f, 0xc00e, 0x21, 0 + .dw 0x8cc0, 0xc00e, 0x8cff, 0xc00e, 0x21, 0 + .dw 0x8d40, 0xc00e, 0x8d7f, 0xc00e, 0x21, 0 + .dw 0x8dc0, 0xc00e, 0x8dff, 0xc00e, 0x21, 0 + .dw 0x8e40, 0xc00e, 0x8e7f, 0xc00e, 0x21, 0 + .dw 0x8ec0, 0xc00e, 0x8eff, 0xc00e, 0x21, 0 + .dw 0x8f40, 0xc00e, 0x8f7f, 0xc00e, 0x21, 0 + .dw 0x8fc0, 0xc00e, 0x8fff, 0xc00e, 0x21, 0 + .dw 0x9040, 0xc00e, 0x907f, 0xc00e, 0x21, 0 + .dw 0x90c0, 0xc00e, 0x90ff, 0xc00e, 0x21, 0 + .dw 0x9140, 0xc00e, 0x917f, 0xc00e, 0x21, 0 + .dw 0x91c0, 0xc00e, 0x91ff, 0xc00e, 0x21, 0 + .dw 0x9240, 0xc00e, 0x927f, 0xc00e, 0x21, 0 + .dw 0x92c0, 0xc00e, 0x92ff, 0xc00e, 0x21, 0 + .dw 0x9340, 0xc00e, 0x937f, 0xc00e, 0x21, 0 + .dw 0x93c0, 0xc00e, 0x93ff, 0xc00e, 0x21, 0 + .dw 0x9440, 0xc00e, 0x947f, 0xc00e, 0x21, 0 + .dw 0x94c0, 0xc00e, 0x94ff, 0xc00e, 0x21, 0 + .dw 0x9540, 0xc00e, 0x957f, 0xc00e, 0x21, 0 + .dw 0x95c0, 0xc00e, 0x95ff, 0xc00e, 0x21, 0 + .dw 0x9640, 0xc00e, 0x967f, 0xc00e, 0x21, 0 + .dw 0x96c0, 0xc00e, 0x96ff, 0xc00e, 0x21, 0 + .dw 0x9740, 0xc00e, 0x977f, 0xc00e, 0x21, 0 + .dw 0x97c0, 0xc00e, 0x97ff, 0xc00e, 0x21, 0 + .dw 0x9840, 0xc00e, 0x987f, 0xc00e, 0x21, 0 + .dw 0x98c0, 0xc00e, 0x98ff, 0xc00e, 0x21, 0 + .dw 0x9940, 0xc00e, 0x997f, 0xc00e, 0x21, 0 + .dw 0x99c0, 0xc00e, 0x9fff, 0xc00e, 0x21, 0 + .dw 0xa040, 0xc00e, 0xa07f, 0xc00e, 0x21, 0 + .dw 0xa0c0, 0xc00e, 0xa0ff, 0xc00e, 0x21, 0 + .dw 0xa140, 0xc00e, 0xa17f, 0xc00e, 0x21, 0 + .dw 0xa1c0, 0xc00e, 0xa1ff, 0xc00e, 0x21, 0 + .dw 0xa240, 0xc00e, 0xa27f, 0xc00e, 0x21, 0 + .dw 0xa2c0, 0xc00e, 0xa2ff, 0xc00e, 0x21, 0 + .dw 0xa340, 0xc00e, 0xa37f, 0xc00e, 0x21, 0 + .dw 0xa3c0, 0xc00e, 0xa3ff, 0xc00e, 0x21, 0 + .dw 0xa440, 0xc00e, 0xa47f, 0xc00e, 0x21, 0 + .dw 0xa4c0, 0xc00e, 0xa4ff, 0xc00e, 0x21, 0 + .dw 0xa540, 0xc00e, 0xa57f, 0xc00e, 0x21, 0 + .dw 0xa5c0, 0xc00e, 0xa5ff, 0xc00e, 0x21, 0 + .dw 0xa640, 0xc00e, 0xa67f, 0xc00e, 0x21, 0 + .dw 0xa6c0, 0xc00e, 0xa6ff, 0xc00e, 0x21, 0 + .dw 0xa740, 0xc00e, 0xa77f, 0xc00e, 0x21, 0 + .dw 0xa7c0, 0xc00e, 0xa7ff, 0xc00e, 0x21, 0 + .dw 0xa840, 0xc00e, 0xa87f, 0xc00e, 0x21, 0 + .dw 0xa8c0, 0xc00e, 0xa8ff, 0xc00e, 0x21, 0 + .dw 0xa940, 0xc00e, 0xa97f, 0xc00e, 0x21, 0 + .dw 0xa9c0, 0xc00e, 0xa9ff, 0xc00e, 0x21, 0 + .dw 0xaa40, 0xc00e, 0xaa7f, 0xc00e, 0x21, 0 + .dw 0xaac0, 0xc00e, 0xaaff, 0xc00e, 0x21, 0 + .dw 0xab40, 0xc00e, 0xab7f, 0xc00e, 0x21, 0 + .dw 0xabc0, 0xc00e, 0xabff, 0xc00e, 0x21, 0 + .dw 0xac40, 0xc00e, 0xac7f, 0xc00e, 0x21, 0 + .dw 0xacc0, 0xc00e, 0xacff, 0xc00e, 0x21, 0 + .dw 0xad40, 0xc00e, 0xad7f, 0xc00e, 0x21, 0 + .dw 0xadc0, 0xc00e, 0xadff, 0xc00e, 0x21, 0 + .dw 0xae40, 0xc00e, 0xae7f, 0xc00e, 0x21, 0 + .dw 0xaec0, 0xc00e, 0xaeff, 0xc00e, 0x21, 0 + .dw 0xaf40, 0xc00e, 0xaf7f, 0xc00e, 0x21, 0 + .dw 0xafc0, 0xc00e, 0xafff, 0xc00e, 0x21, 0 + .dw 0xb040, 0xc00e, 0xb07f, 0xc00e, 0x21, 0 + .dw 0xb0c0, 0xc00e, 0xb0ff, 0xc00e, 0x21, 0 + .dw 0xb140, 0xc00e, 0xb17f, 0xc00e, 0x21, 0 + .dw 0xb1c0, 0xc00e, 0xb1ff, 0xc00e, 0x21, 0 + .dw 0xb240, 0xc00e, 0xb27f, 0xc00e, 0x21, 0 + .dw 0xb2c0, 0xc00e, 0xb2ff, 0xc00e, 0x21, 0 + .dw 0xb340, 0xc00e, 0xb37f, 0xc00e, 0x21, 0 + .dw 0xb3c0, 0xc00e, 0xb3ff, 0xc00e, 0x21, 0 + .dw 0xb440, 0xc00e, 0xb47f, 0xc00e, 0x21, 0 + .dw 0xb4c0, 0xc00e, 0xb4ff, 0xc00e, 0x21, 0 + .dw 0xb540, 0xc00e, 0xb57f, 0xc00e, 0x21, 0 + .dw 0xb5c0, 0xc00e, 0xb5ff, 0xc00e, 0x21, 0 + .dw 0xb640, 0xc00e, 0xb67f, 0xc00e, 0x21, 0 + .dw 0xb6c0, 0xc00e, 0xb6ff, 0xc00e, 0x21, 0 + .dw 0xb740, 0xc00e, 0xb77f, 0xc00e, 0x21, 0 + .dw 0xb7c0, 0xc00e, 0xb7ff, 0xc00e, 0x21, 0 + .dw 0xb840, 0xc00e, 0xb87f, 0xc00e, 0x21, 0 + .dw 0xb8c0, 0xc00e, 0xb8ff, 0xc00e, 0x21, 0 + .dw 0xb940, 0xc00e, 0xb97f, 0xc00e, 0x21, 0 + .dw 0xb9c0, 0xc00e, 0xbfff, 0xc00e, 0x21, 0 + .dw 0xc040, 0xc00e, 0xc07f, 0xc00e, 0x21, 0 + .dw 0xc0c0, 0xc00e, 0xc0ff, 0xc00e, 0x21, 0 + .dw 0xc140, 0xc00e, 0xc17f, 0xc00e, 0x21, 0 + .dw 0xc1c0, 0xc00e, 0xc1ff, 0xc00e, 0x21, 0 + .dw 0xc240, 0xc00e, 0xc27f, 0xc00e, 0x21, 0 + .dw 0xc2c0, 0xc00e, 0xc2ff, 0xc00e, 0x21, 0 + .dw 0xc340, 0xc00e, 0xc37f, 0xc00e, 0x21, 0 + .dw 0xc3c0, 0xc00e, 0xc3ff, 0xc00e, 0x21, 0 + .dw 0xc440, 0xc00e, 0xc47f, 0xc00e, 0x21, 0 + .dw 0xc4c0, 0xc00e, 0xc4ff, 0xc00e, 0x21, 0 + .dw 0xc540, 0xc00e, 0xc57f, 0xc00e, 0x21, 0 + .dw 0xc5c0, 0xc00e, 0xc5ff, 0xc00e, 0x21, 0 + .dw 0xc640, 0xc00e, 0xc67f, 0xc00e, 0x21, 0 + .dw 0xc6c0, 0xc00e, 0xc6ff, 0xc00e, 0x21, 0 + .dw 0xc740, 0xc00e, 0xc77f, 0xc00e, 0x21, 0 + .dw 0xc7c0, 0xc00e, 0xc7ff, 0xc00e, 0x21, 0 + .dw 0xc840, 0xc00e, 0xc87f, 0xc00e, 0x21, 0 + .dw 0xc8c0, 0xc00e, 0xc8ff, 0xc00e, 0x21, 0 + .dw 0xc940, 0xc00e, 0xc97f, 0xc00e, 0x21, 0 + .dw 0xc9c0, 0xc00e, 0xc9ff, 0xc00e, 0x21, 0 + .dw 0xca40, 0xc00e, 0xca7f, 0xc00e, 0x21, 0 + .dw 0xcac0, 0xc00e, 0xcaff, 0xc00e, 0x21, 0 + .dw 0xcb40, 0xc00e, 0xcb7f, 0xc00e, 0x21, 0 + .dw 0xcbc0, 0xc00e, 0xcbff, 0xc00e, 0x21, 0 + .dw 0xcc40, 0xc00e, 0xcc7f, 0xc00e, 0x21, 0 + .dw 0xccc0, 0xc00e, 0xccff, 0xc00e, 0x21, 0 + .dw 0xcd40, 0xc00e, 0xcd7f, 0xc00e, 0x21, 0 + .dw 0xcdc0, 0xc00e, 0xcdff, 0xc00e, 0x21, 0 + .dw 0xce40, 0xc00e, 0xce7f, 0xc00e, 0x21, 0 + .dw 0xcec0, 0xc00e, 0xceff, 0xc00e, 0x21, 0 + .dw 0xcf40, 0xc00e, 0xcf7f, 0xc00e, 0x21, 0 + .dw 0xcfc0, 0xc00e, 0xcfff, 0xc00e, 0x21, 0 + .dw 0xd040, 0xc00e, 0xd07f, 0xc00e, 0x21, 0 + .dw 0xd0c0, 0xc00e, 0xd0ff, 0xc00e, 0x21, 0 + .dw 0xd140, 0xc00e, 0xd17f, 0xc00e, 0x21, 0 + .dw 0xd1c0, 0xc00e, 0xd1ff, 0xc00e, 0x21, 0 + .dw 0xd240, 0xc00e, 0xd27f, 0xc00e, 0x21, 0 + .dw 0xd2c0, 0xc00e, 0xd2ff, 0xc00e, 0x21, 0 + .dw 0xd340, 0xc00e, 0xd37f, 0xc00e, 0x21, 0 + .dw 0xd3c0, 0xc00e, 0xd3ff, 0xc00e, 0x21, 0 + .dw 0xd440, 0xc00e, 0xd47f, 0xc00e, 0x21, 0 + .dw 0xd4c0, 0xc00e, 0xd4ff, 0xc00e, 0x21, 0 + .dw 0xd540, 0xc00e, 0xd57f, 0xc00e, 0x21, 0 + .dw 0xd5c0, 0xc00e, 0xd5ff, 0xc00e, 0x21, 0 + .dw 0xd640, 0xc00e, 0xd67f, 0xc00e, 0x21, 0 + .dw 0xd6c0, 0xc00e, 0xd6ff, 0xc00e, 0x21, 0 + .dw 0xd740, 0xc00e, 0xd77f, 0xc00e, 0x21, 0 + .dw 0xd7c0, 0xc00e, 0xd7ff, 0xc00e, 0x21, 0 + .dw 0xd840, 0xc00e, 0xd87f, 0xc00e, 0x21, 0 + .dw 0xd8c0, 0xc00e, 0xd8ff, 0xc00e, 0x21, 0 + .dw 0xd940, 0xc00e, 0xd97f, 0xc00e, 0x21, 0 + .dw 0xd9c0, 0xc00e, 0xdfff, 0xc00e, 0x21, 0 + .dw 0xe040, 0xc00e, 0xe07f, 0xc00e, 0x21, 0 + .dw 0xe0c0, 0xc00e, 0xe0ff, 0xc00e, 0x21, 0 + .dw 0xe140, 0xc00e, 0xe17f, 0xc00e, 0x21, 0 + .dw 0xe1c0, 0xc00e, 0xe1ff, 0xc00e, 0x21, 0 + .dw 0xe240, 0xc00e, 0xe27f, 0xc00e, 0x21, 0 + .dw 0xe2c0, 0xc00e, 0xe2ff, 0xc00e, 0x21, 0 + .dw 0xe340, 0xc00e, 0xe37f, 0xc00e, 0x21, 0 + .dw 0xe3c0, 0xc00e, 0xe3ff, 0xc00e, 0x21, 0 + .dw 0xe440, 0xc00e, 0xe47f, 0xc00e, 0x21, 0 + .dw 0xe4c0, 0xc00e, 0xe4ff, 0xc00e, 0x21, 0 + .dw 0xe540, 0xc00e, 0xe57f, 0xc00e, 0x21, 0 + .dw 0xe5c0, 0xc00e, 0xe5ff, 0xc00e, 0x21, 0 + .dw 0xe640, 0xc00e, 0xe67f, 0xc00e, 0x21, 0 + .dw 0xe6c0, 0xc00e, 0xe6ff, 0xc00e, 0x21, 0 + .dw 0xe740, 0xc00e, 0xe77f, 0xc00e, 0x21, 0 + .dw 0xe7c0, 0xc00e, 0xe7ff, 0xc00e, 0x21, 0 + .dw 0xe840, 0xc00e, 0xe87f, 0xc00e, 0x21, 0 + .dw 0xe8c0, 0xc00e, 0xe8ff, 0xc00e, 0x21, 0 + .dw 0xe940, 0xc00e, 0xe97f, 0xc00e, 0x21, 0 + .dw 0xe9c0, 0xc00e, 0xe9ff, 0xc00e, 0x21, 0 + .dw 0xea40, 0xc00e, 0xea7f, 0xc00e, 0x21, 0 + .dw 0xeac0, 0xc00e, 0xeaff, 0xc00e, 0x21, 0 + .dw 0xeb40, 0xc00e, 0xeb7f, 0xc00e, 0x21, 0 + .dw 0xebc0, 0xc00e, 0xebff, 0xc00e, 0x21, 0 + .dw 0xec40, 0xc00e, 0xec7f, 0xc00e, 0x21, 0 + .dw 0xecc0, 0xc00e, 0xecff, 0xc00e, 0x21, 0 + .dw 0xed40, 0xc00e, 0xed7f, 0xc00e, 0x21, 0 + .dw 0xedc0, 0xc00e, 0xedff, 0xc00e, 0x21, 0 + .dw 0xee40, 0xc00e, 0xee7f, 0xc00e, 0x21, 0 + .dw 0xeec0, 0xc00e, 0xeeff, 0xc00e, 0x21, 0 + .dw 0xef40, 0xc00e, 0xef7f, 0xc00e, 0x21, 0 + .dw 0xefc0, 0xc00e, 0xefff, 0xc00e, 0x21, 0 + .dw 0xf040, 0xc00e, 0xf07f, 0xc00e, 0x21, 0 + .dw 0xf0c0, 0xc00e, 0xf0ff, 0xc00e, 0x21, 0 + .dw 0xf140, 0xc00e, 0xf17f, 0xc00e, 0x21, 0 + .dw 0xf1c0, 0xc00e, 0xf1ff, 0xc00e, 0x21, 0 + .dw 0xf240, 0xc00e, 0xf27f, 0xc00e, 0x21, 0 + .dw 0xf2c0, 0xc00e, 0xf2ff, 0xc00e, 0x21, 0 + .dw 0xf340, 0xc00e, 0xf37f, 0xc00e, 0x21, 0 + .dw 0xf3c0, 0xc00e, 0xf3ff, 0xc00e, 0x21, 0 + .dw 0xf440, 0xc00e, 0xf47f, 0xc00e, 0x21, 0 + .dw 0xf4c0, 0xc00e, 0xf4ff, 0xc00e, 0x21, 0 + .dw 0xf540, 0xc00e, 0xf57f, 0xc00e, 0x21, 0 + .dw 0xf5c0, 0xc00e, 0xf5ff, 0xc00e, 0x21, 0 + .dw 0xf640, 0xc00e, 0xf67f, 0xc00e, 0x21, 0 + .dw 0xf6c0, 0xc00e, 0xf6ff, 0xc00e, 0x21, 0 + .dw 0xf740, 0xc00e, 0xf77f, 0xc00e, 0x21, 0 + .dw 0xf7c0, 0xc00e, 0xf7ff, 0xc00e, 0x21, 0 + .dw 0xf840, 0xc00e, 0xf87f, 0xc00e, 0x21, 0 + .dw 0xf8c0, 0xc00e, 0xf8ff, 0xc00e, 0x21, 0 + .dw 0xf940, 0xc00e, 0xf97f, 0xc00e, 0x21, 0 + .dw 0xf9c0, 0xc00e, 0xffff, 0xc00e, 0x21, 0 + .dw 0x0040, 0xc00f, 0x007f, 0xc00f, 0x21, 0 + .dw 0x00c0, 0xc00f, 0x00ff, 0xc00f, 0x21, 0 + .dw 0x0140, 0xc00f, 0x017f, 0xc00f, 0x21, 0 + .dw 0x01c0, 0xc00f, 0x01ff, 0xc00f, 0x21, 0 + .dw 0x0240, 0xc00f, 0x027f, 0xc00f, 0x21, 0 + .dw 0x02c0, 0xc00f, 0x02ff, 0xc00f, 0x21, 0 + .dw 0x0340, 0xc00f, 0x037f, 0xc00f, 0x21, 0 + .dw 0x03c0, 0xc00f, 0x03ff, 0xc00f, 0x21, 0 + .dw 0x0440, 0xc00f, 0x047f, 0xc00f, 0x21, 0 + .dw 0x04c0, 0xc00f, 0x04ff, 0xc00f, 0x21, 0 + .dw 0x0540, 0xc00f, 0x057f, 0xc00f, 0x21, 0 + .dw 0x05c0, 0xc00f, 0x05ff, 0xc00f, 0x21, 0 + .dw 0x0640, 0xc00f, 0x067f, 0xc00f, 0x21, 0 + .dw 0x06c0, 0xc00f, 0x06ff, 0xc00f, 0x21, 0 + .dw 0x0740, 0xc00f, 0x077f, 0xc00f, 0x21, 0 + .dw 0x07c0, 0xc00f, 0x07ff, 0xc00f, 0x21, 0 + .dw 0x0840, 0xc00f, 0x087f, 0xc00f, 0x21, 0 + .dw 0x08c0, 0xc00f, 0x08ff, 0xc00f, 0x21, 0 + .dw 0x0940, 0xc00f, 0x097f, 0xc00f, 0x21, 0 + .dw 0x09c0, 0xc00f, 0x09ff, 0xc00f, 0x21, 0 + .dw 0x0a40, 0xc00f, 0x0a7f, 0xc00f, 0x21, 0 + .dw 0x0ac0, 0xc00f, 0x0aff, 0xc00f, 0x21, 0 + .dw 0x0b40, 0xc00f, 0x0b7f, 0xc00f, 0x21, 0 + .dw 0x0bc0, 0xc00f, 0x0bff, 0xc00f, 0x21, 0 + .dw 0x0c40, 0xc00f, 0x0c7f, 0xc00f, 0x21, 0 + .dw 0x0cc0, 0xc00f, 0x0cff, 0xc00f, 0x21, 0 + .dw 0x0d40, 0xc00f, 0x0d7f, 0xc00f, 0x21, 0 + .dw 0x0dc0, 0xc00f, 0x0dff, 0xc00f, 0x21, 0 + .dw 0x0e40, 0xc00f, 0x0e7f, 0xc00f, 0x21, 0 + .dw 0x0ec0, 0xc00f, 0x0eff, 0xc00f, 0x21, 0 + .dw 0x0f40, 0xc00f, 0x0f7f, 0xc00f, 0x21, 0 + .dw 0x0fc0, 0xc00f, 0x0fff, 0xc00f, 0x21, 0 + .dw 0x1040, 0xc00f, 0x107f, 0xc00f, 0x21, 0 + .dw 0x10c0, 0xc00f, 0x10ff, 0xc00f, 0x21, 0 + .dw 0x1140, 0xc00f, 0x117f, 0xc00f, 0x21, 0 + .dw 0x11c0, 0xc00f, 0x11ff, 0xc00f, 0x21, 0 + .dw 0x1240, 0xc00f, 0x127f, 0xc00f, 0x21, 0 + .dw 0x12c0, 0xc00f, 0x12ff, 0xc00f, 0x21, 0 + .dw 0x1340, 0xc00f, 0x137f, 0xc00f, 0x21, 0 + .dw 0x13c0, 0xc00f, 0x13ff, 0xc00f, 0x21, 0 + .dw 0x1440, 0xc00f, 0x147f, 0xc00f, 0x21, 0 + .dw 0x14c0, 0xc00f, 0x14ff, 0xc00f, 0x21, 0 + .dw 0x1540, 0xc00f, 0x157f, 0xc00f, 0x21, 0 + .dw 0x15c0, 0xc00f, 0x15ff, 0xc00f, 0x21, 0 + .dw 0x1640, 0xc00f, 0x167f, 0xc00f, 0x21, 0 + .dw 0x16c0, 0xc00f, 0x16ff, 0xc00f, 0x21, 0 + .dw 0x1740, 0xc00f, 0x177f, 0xc00f, 0x21, 0 + .dw 0x17c0, 0xc00f, 0x17ff, 0xc00f, 0x21, 0 + .dw 0x1840, 0xc00f, 0x187f, 0xc00f, 0x21, 0 + .dw 0x18c0, 0xc00f, 0x18ff, 0xc00f, 0x21, 0 + .dw 0x1940, 0xc00f, 0x197f, 0xc00f, 0x21, 0 + .dw 0x19c0, 0xc00f, 0x1fff, 0xc00f, 0x21, 0 + .dw 0x2040, 0xc00f, 0x207f, 0xc00f, 0x21, 0 + .dw 0x20c0, 0xc00f, 0x20ff, 0xc00f, 0x21, 0 + .dw 0x2140, 0xc00f, 0x217f, 0xc00f, 0x21, 0 + .dw 0x21c0, 0xc00f, 0x21ff, 0xc00f, 0x21, 0 + .dw 0x2240, 0xc00f, 0x227f, 0xc00f, 0x21, 0 + .dw 0x22c0, 0xc00f, 0x22ff, 0xc00f, 0x21, 0 + .dw 0x2340, 0xc00f, 0x237f, 0xc00f, 0x21, 0 + .dw 0x23c0, 0xc00f, 0x23ff, 0xc00f, 0x21, 0 + .dw 0x2440, 0xc00f, 0x247f, 0xc00f, 0x21, 0 + .dw 0x24c0, 0xc00f, 0x24ff, 0xc00f, 0x21, 0 + .dw 0x2540, 0xc00f, 0x257f, 0xc00f, 0x21, 0 + .dw 0x25c0, 0xc00f, 0x25ff, 0xc00f, 0x21, 0 + .dw 0x2640, 0xc00f, 0x267f, 0xc00f, 0x21, 0 + .dw 0x26c0, 0xc00f, 0x26ff, 0xc00f, 0x21, 0 + .dw 0x2740, 0xc00f, 0x277f, 0xc00f, 0x21, 0 + .dw 0x27c0, 0xc00f, 0x27ff, 0xc00f, 0x21, 0 + .dw 0x2840, 0xc00f, 0x287f, 0xc00f, 0x21, 0 + .dw 0x28c0, 0xc00f, 0x28ff, 0xc00f, 0x21, 0 + .dw 0x2940, 0xc00f, 0x297f, 0xc00f, 0x21, 0 + .dw 0x29c0, 0xc00f, 0x29ff, 0xc00f, 0x21, 0 + .dw 0x2a40, 0xc00f, 0x2a7f, 0xc00f, 0x21, 0 + .dw 0x2ac0, 0xc00f, 0x2aff, 0xc00f, 0x21, 0 + .dw 0x2b40, 0xc00f, 0x2b7f, 0xc00f, 0x21, 0 + .dw 0x2bc0, 0xc00f, 0x2bff, 0xc00f, 0x21, 0 + .dw 0x2c40, 0xc00f, 0x2c7f, 0xc00f, 0x21, 0 + .dw 0x2cc0, 0xc00f, 0x2cff, 0xc00f, 0x21, 0 + .dw 0x2d40, 0xc00f, 0x2d7f, 0xc00f, 0x21, 0 + .dw 0x2dc0, 0xc00f, 0x2dff, 0xc00f, 0x21, 0 + .dw 0x2e40, 0xc00f, 0x2e7f, 0xc00f, 0x21, 0 + .dw 0x2ec0, 0xc00f, 0x2eff, 0xc00f, 0x21, 0 + .dw 0x2f40, 0xc00f, 0x2f7f, 0xc00f, 0x21, 0 + .dw 0x2fc0, 0xc00f, 0x2fff, 0xc00f, 0x21, 0 + .dw 0x3040, 0xc00f, 0x307f, 0xc00f, 0x21, 0 + .dw 0x30c0, 0xc00f, 0x30ff, 0xc00f, 0x21, 0 + .dw 0x3140, 0xc00f, 0x317f, 0xc00f, 0x21, 0 + .dw 0x31c0, 0xc00f, 0x31ff, 0xc00f, 0x21, 0 + .dw 0x3240, 0xc00f, 0x327f, 0xc00f, 0x21, 0 + .dw 0x32c0, 0xc00f, 0x32ff, 0xc00f, 0x21, 0 + .dw 0x3340, 0xc00f, 0x337f, 0xc00f, 0x21, 0 + .dw 0x33c0, 0xc00f, 0x33ff, 0xc00f, 0x21, 0 + .dw 0x3440, 0xc00f, 0x347f, 0xc00f, 0x21, 0 + .dw 0x34c0, 0xc00f, 0x34ff, 0xc00f, 0x21, 0 + .dw 0x3540, 0xc00f, 0x357f, 0xc00f, 0x21, 0 + .dw 0x35c0, 0xc00f, 0x35ff, 0xc00f, 0x21, 0 + .dw 0x3640, 0xc00f, 0x367f, 0xc00f, 0x21, 0 + .dw 0x36c0, 0xc00f, 0x36ff, 0xc00f, 0x21, 0 + .dw 0x3740, 0xc00f, 0x377f, 0xc00f, 0x21, 0 + .dw 0x37c0, 0xc00f, 0x37ff, 0xc00f, 0x21, 0 + .dw 0x3840, 0xc00f, 0x387f, 0xc00f, 0x21, 0 + .dw 0x38c0, 0xc00f, 0x38ff, 0xc00f, 0x21, 0 + .dw 0x3940, 0xc00f, 0x397f, 0xc00f, 0x21, 0 + .dw 0x39c0, 0xc00f, 0xffff, 0xc00f, 0x21, 0 + .dw 0x1a00, 0xc010, 0x1fff, 0xc010, 0x21, 0 + .dw 0x3a00, 0xc010, 0x3fff, 0xc010, 0x21, 0 + .dw 0x5a00, 0xc010, 0x5fff, 0xc010, 0x21, 0 + .dw 0x7a00, 0xc010, 0x7fff, 0xc010, 0x21, 0 + .dw 0x9a00, 0xc010, 0x9fff, 0xc010, 0x21, 0 + .dw 0xba00, 0xc010, 0xbfff, 0xc010, 0x21, 0 + .dw 0xda00, 0xc010, 0xdfff, 0xc010, 0x21, 0 + .dw 0xfa00, 0xc010, 0xffff, 0xc010, 0x21, 0 + .dw 0x1a00, 0xc011, 0x1fff, 0xc011, 0x21, 0 + .dw 0x3a00, 0xc011, 0x3fff, 0xc011, 0x21, 0 + .dw 0x5a00, 0xc011, 0x5fff, 0xc011, 0x21, 0 + .dw 0x7a00, 0xc011, 0x7fff, 0xc011, 0x21, 0 + .dw 0x9a00, 0xc011, 0x9fff, 0xc011, 0x21, 0 + .dw 0xba00, 0xc011, 0xbfff, 0xc011, 0x21, 0 + .dw 0xda00, 0xc011, 0xdfff, 0xc011, 0x21, 0 + .dw 0xfa00, 0xc011, 0xffff, 0xc011, 0x21, 0 + .dw 0x1a00, 0xc012, 0x1fff, 0xc012, 0x21, 0 + .dw 0x3a00, 0xc012, 0x3fff, 0xc012, 0x21, 0 + .dw 0x5a00, 0xc012, 0x5fff, 0xc012, 0x21, 0 + .dw 0x7a00, 0xc012, 0x7fff, 0xc012, 0x21, 0 + .dw 0x9a00, 0xc012, 0x9fff, 0xc012, 0x21, 0 + .dw 0xba00, 0xc012, 0xbfff, 0xc012, 0x21, 0 + .dw 0xda00, 0xc012, 0xdfff, 0xc012, 0x21, 0 + .dw 0xfa00, 0xc012, 0xffff, 0xc013, 0x21, 0 + .dw 0x1a00, 0xc014, 0x1fff, 0xc014, 0x21, 0 + .dw 0x3a00, 0xc014, 0x3fff, 0xc014, 0x21, 0 + .dw 0x5a00, 0xc014, 0x5fff, 0xc014, 0x21, 0 + .dw 0x7a00, 0xc014, 0x7fff, 0xc014, 0x21, 0 + .dw 0x9a00, 0xc014, 0x9fff, 0xc014, 0x21, 0 + .dw 0xba00, 0xc014, 0xbfff, 0xc014, 0x21, 0 + .dw 0xda00, 0xc014, 0xdfff, 0xc014, 0x21, 0 + .dw 0xfa00, 0xc014, 0xffff, 0xc014, 0x21, 0 + .dw 0x1a00, 0xc015, 0x1fff, 0xc015, 0x21, 0 + .dw 0x3a00, 0xc015, 0x3fff, 0xc015, 0x21, 0 + .dw 0x5a00, 0xc015, 0x5fff, 0xc015, 0x21, 0 + .dw 0x7a00, 0xc015, 0x7fff, 0xc015, 0x21, 0 + .dw 0x9a00, 0xc015, 0x9fff, 0xc015, 0x21, 0 + .dw 0xba00, 0xc015, 0xbfff, 0xc015, 0x21, 0 + .dw 0xda00, 0xc015, 0xdfff, 0xc015, 0x21, 0 + .dw 0xfa00, 0xc015, 0xffff, 0xc015, 0x21, 0 + .dw 0x1a00, 0xc016, 0x1fff, 0xc016, 0x21, 0 + .dw 0x3a00, 0xc016, 0x3fff, 0xc016, 0x21, 0 + .dw 0x5a00, 0xc016, 0x5fff, 0xc016, 0x21, 0 + .dw 0x7a00, 0xc016, 0x7fff, 0xc016, 0x21, 0 + .dw 0x9a00, 0xc016, 0x9fff, 0xc016, 0x21, 0 + .dw 0xba00, 0xc016, 0xbfff, 0xc016, 0x21, 0 + .dw 0xda00, 0xc016, 0xdfff, 0xc016, 0x21, 0 + .dw 0xfa00, 0xc016, 0xffff, 0xc016, 0x21, 0 + .dw 0x1a00, 0xc017, 0x1fff, 0xc017, 0x21, 0 + .dw 0x3a00, 0xc017, 0x1fff, 0xc018, 0x21, 0 + .dw 0x2040, 0xc018, 0x207f, 0xc018, 0x21, 0 + .dw 0x20c0, 0xc018, 0x20ff, 0xc018, 0x21, 0 + .dw 0x2140, 0xc018, 0x217f, 0xc018, 0x21, 0 + .dw 0x21c0, 0xc018, 0x21ff, 0xc018, 0x21, 0 + .dw 0x2240, 0xc018, 0x227f, 0xc018, 0x21, 0 + .dw 0x22c0, 0xc018, 0x22ff, 0xc018, 0x21, 0 + .dw 0x2340, 0xc018, 0x237f, 0xc018, 0x21, 0 + .dw 0x23c0, 0xc018, 0x23ff, 0xc018, 0x21, 0 + .dw 0x2440, 0xc018, 0x247f, 0xc018, 0x21, 0 + .dw 0x24c0, 0xc018, 0x24ff, 0xc018, 0x21, 0 + .dw 0x2540, 0xc018, 0x257f, 0xc018, 0x21, 0 + .dw 0x25c0, 0xc018, 0x25ff, 0xc018, 0x21, 0 + .dw 0x2640, 0xc018, 0x267f, 0xc018, 0x21, 0 + .dw 0x26c0, 0xc018, 0x26ff, 0xc018, 0x21, 0 + .dw 0x2740, 0xc018, 0x277f, 0xc018, 0x21, 0 + .dw 0x27c0, 0xc018, 0x27ff, 0xc018, 0x21, 0 + .dw 0x2840, 0xc018, 0x287f, 0xc018, 0x21, 0 + .dw 0x28c0, 0xc018, 0x28ff, 0xc018, 0x21, 0 + .dw 0x2940, 0xc018, 0x297f, 0xc018, 0x21, 0 + .dw 0x29c0, 0xc018, 0x29ff, 0xc018, 0x21, 0 + .dw 0x2a40, 0xc018, 0x2a7f, 0xc018, 0x21, 0 + .dw 0x2ac0, 0xc018, 0x2aff, 0xc018, 0x21, 0 + .dw 0x2b40, 0xc018, 0x2b7f, 0xc018, 0x21, 0 + .dw 0x2bc0, 0xc018, 0x2bff, 0xc018, 0x21, 0 + .dw 0x2c40, 0xc018, 0x2c7f, 0xc018, 0x21, 0 + .dw 0x2cc0, 0xc018, 0x2cff, 0xc018, 0x21, 0 + .dw 0x2d40, 0xc018, 0x2d7f, 0xc018, 0x21, 0 + .dw 0x2dc0, 0xc018, 0x2dff, 0xc018, 0x21, 0 + .dw 0x2e40, 0xc018, 0x2e7f, 0xc018, 0x21, 0 + .dw 0x2ec0, 0xc018, 0x2eff, 0xc018, 0x21, 0 + .dw 0x2f40, 0xc018, 0x2f7f, 0xc018, 0x21, 0 + .dw 0x2fc0, 0xc018, 0x2fff, 0xc018, 0x21, 0 + .dw 0x3040, 0xc018, 0x307f, 0xc018, 0x21, 0 + .dw 0x30c0, 0xc018, 0x30ff, 0xc018, 0x21, 0 + .dw 0x3140, 0xc018, 0x317f, 0xc018, 0x21, 0 + .dw 0x31c0, 0xc018, 0x31ff, 0xc018, 0x21, 0 + .dw 0x3240, 0xc018, 0x327f, 0xc018, 0x21, 0 + .dw 0x32c0, 0xc018, 0x32ff, 0xc018, 0x21, 0 + .dw 0x3340, 0xc018, 0x337f, 0xc018, 0x21, 0 + .dw 0x33c0, 0xc018, 0x33ff, 0xc018, 0x21, 0 + .dw 0x3440, 0xc018, 0x347f, 0xc018, 0x21, 0 + .dw 0x34c0, 0xc018, 0x34ff, 0xc018, 0x21, 0 + .dw 0x3540, 0xc018, 0x357f, 0xc018, 0x21, 0 + .dw 0x35c0, 0xc018, 0x35ff, 0xc018, 0x21, 0 + .dw 0x3640, 0xc018, 0x367f, 0xc018, 0x21, 0 + .dw 0x36c0, 0xc018, 0x36ff, 0xc018, 0x21, 0 + .dw 0x3740, 0xc018, 0x377f, 0xc018, 0x21, 0 + .dw 0x37c0, 0xc018, 0x37ff, 0xc018, 0x21, 0 + .dw 0x3840, 0xc018, 0x387f, 0xc018, 0x21, 0 + .dw 0x38c0, 0xc018, 0x38ff, 0xc018, 0x21, 0 + .dw 0x3940, 0xc018, 0x397f, 0xc018, 0x21, 0 + .dw 0x39c0, 0xc018, 0x5fff, 0xc018, 0x21, 0 + .dw 0x6040, 0xc018, 0x607f, 0xc018, 0x21, 0 + .dw 0x60c0, 0xc018, 0x60ff, 0xc018, 0x21, 0 + .dw 0x6140, 0xc018, 0x617f, 0xc018, 0x21, 0 + .dw 0x61c0, 0xc018, 0x61ff, 0xc018, 0x21, 0 + .dw 0x6240, 0xc018, 0x627f, 0xc018, 0x21, 0 + .dw 0x62c0, 0xc018, 0x62ff, 0xc018, 0x21, 0 + .dw 0x6340, 0xc018, 0x637f, 0xc018, 0x21, 0 + .dw 0x63c0, 0xc018, 0x63ff, 0xc018, 0x21, 0 + .dw 0x6440, 0xc018, 0x647f, 0xc018, 0x21, 0 + .dw 0x64c0, 0xc018, 0x64ff, 0xc018, 0x21, 0 + .dw 0x6540, 0xc018, 0x657f, 0xc018, 0x21, 0 + .dw 0x65c0, 0xc018, 0x65ff, 0xc018, 0x21, 0 + .dw 0x6640, 0xc018, 0x667f, 0xc018, 0x21, 0 + .dw 0x66c0, 0xc018, 0x66ff, 0xc018, 0x21, 0 + .dw 0x6740, 0xc018, 0x677f, 0xc018, 0x21, 0 + .dw 0x67c0, 0xc018, 0x67ff, 0xc018, 0x21, 0 + .dw 0x6840, 0xc018, 0x687f, 0xc018, 0x21, 0 + .dw 0x68c0, 0xc018, 0x68ff, 0xc018, 0x21, 0 + .dw 0x6940, 0xc018, 0x697f, 0xc018, 0x21, 0 + .dw 0x69c0, 0xc018, 0x69ff, 0xc018, 0x21, 0 + .dw 0x6a40, 0xc018, 0x6a7f, 0xc018, 0x21, 0 + .dw 0x6ac0, 0xc018, 0x6aff, 0xc018, 0x21, 0 + .dw 0x6b40, 0xc018, 0x6b7f, 0xc018, 0x21, 0 + .dw 0x6bc0, 0xc018, 0x6bff, 0xc018, 0x21, 0 + .dw 0x6c40, 0xc018, 0x6c7f, 0xc018, 0x21, 0 + .dw 0x6cc0, 0xc018, 0x6cff, 0xc018, 0x21, 0 + .dw 0x6d40, 0xc018, 0x6d7f, 0xc018, 0x21, 0 + .dw 0x6dc0, 0xc018, 0x6dff, 0xc018, 0x21, 0 + .dw 0x6e40, 0xc018, 0x6e7f, 0xc018, 0x21, 0 + .dw 0x6ec0, 0xc018, 0x6eff, 0xc018, 0x21, 0 + .dw 0x6f40, 0xc018, 0x6f7f, 0xc018, 0x21, 0 + .dw 0x6fc0, 0xc018, 0x6fff, 0xc018, 0x21, 0 + .dw 0x7040, 0xc018, 0x707f, 0xc018, 0x21, 0 + .dw 0x70c0, 0xc018, 0x70ff, 0xc018, 0x21, 0 + .dw 0x7140, 0xc018, 0x717f, 0xc018, 0x21, 0 + .dw 0x71c0, 0xc018, 0x71ff, 0xc018, 0x21, 0 + .dw 0x7240, 0xc018, 0x727f, 0xc018, 0x21, 0 + .dw 0x72c0, 0xc018, 0x72ff, 0xc018, 0x21, 0 + .dw 0x7340, 0xc018, 0x737f, 0xc018, 0x21, 0 + .dw 0x73c0, 0xc018, 0x73ff, 0xc018, 0x21, 0 + .dw 0x7440, 0xc018, 0x747f, 0xc018, 0x21, 0 + .dw 0x74c0, 0xc018, 0x74ff, 0xc018, 0x21, 0 + .dw 0x7540, 0xc018, 0x757f, 0xc018, 0x21, 0 + .dw 0x75c0, 0xc018, 0x75ff, 0xc018, 0x21, 0 + .dw 0x7640, 0xc018, 0x767f, 0xc018, 0x21, 0 + .dw 0x76c0, 0xc018, 0x76ff, 0xc018, 0x21, 0 + .dw 0x7740, 0xc018, 0x777f, 0xc018, 0x21, 0 + .dw 0x77c0, 0xc018, 0x77ff, 0xc018, 0x21, 0 + .dw 0x7840, 0xc018, 0x787f, 0xc018, 0x21, 0 + .dw 0x78c0, 0xc018, 0x78ff, 0xc018, 0x21, 0 + .dw 0x7940, 0xc018, 0x797f, 0xc018, 0x21, 0 + .dw 0x79c0, 0xc018, 0x9fff, 0xc018, 0x21, 0 + .dw 0xa040, 0xc018, 0xa07f, 0xc018, 0x21, 0 + .dw 0xa0c0, 0xc018, 0xa0ff, 0xc018, 0x21, 0 + .dw 0xa140, 0xc018, 0xa17f, 0xc018, 0x21, 0 + .dw 0xa1c0, 0xc018, 0xa1ff, 0xc018, 0x21, 0 + .dw 0xa240, 0xc018, 0xa27f, 0xc018, 0x21, 0 + .dw 0xa2c0, 0xc018, 0xa2ff, 0xc018, 0x21, 0 + .dw 0xa340, 0xc018, 0xa37f, 0xc018, 0x21, 0 + .dw 0xa3c0, 0xc018, 0xa3ff, 0xc018, 0x21, 0 + .dw 0xa440, 0xc018, 0xa47f, 0xc018, 0x21, 0 + .dw 0xa4c0, 0xc018, 0xa4ff, 0xc018, 0x21, 0 + .dw 0xa540, 0xc018, 0xa57f, 0xc018, 0x21, 0 + .dw 0xa5c0, 0xc018, 0xa5ff, 0xc018, 0x21, 0 + .dw 0xa640, 0xc018, 0xa67f, 0xc018, 0x21, 0 + .dw 0xa6c0, 0xc018, 0xa6ff, 0xc018, 0x21, 0 + .dw 0xa740, 0xc018, 0xa77f, 0xc018, 0x21, 0 + .dw 0xa7c0, 0xc018, 0xa7ff, 0xc018, 0x21, 0 + .dw 0xa840, 0xc018, 0xa87f, 0xc018, 0x21, 0 + .dw 0xa8c0, 0xc018, 0xa8ff, 0xc018, 0x21, 0 + .dw 0xa940, 0xc018, 0xa97f, 0xc018, 0x21, 0 + .dw 0xa9c0, 0xc018, 0xa9ff, 0xc018, 0x21, 0 + .dw 0xaa40, 0xc018, 0xaa7f, 0xc018, 0x21, 0 + .dw 0xaac0, 0xc018, 0xaaff, 0xc018, 0x21, 0 + .dw 0xab40, 0xc018, 0xab7f, 0xc018, 0x21, 0 + .dw 0xabc0, 0xc018, 0xabff, 0xc018, 0x21, 0 + .dw 0xac40, 0xc018, 0xac7f, 0xc018, 0x21, 0 + .dw 0xacc0, 0xc018, 0xacff, 0xc018, 0x21, 0 + .dw 0xad40, 0xc018, 0xad7f, 0xc018, 0x21, 0 + .dw 0xadc0, 0xc018, 0xadff, 0xc018, 0x21, 0 + .dw 0xae40, 0xc018, 0xae7f, 0xc018, 0x21, 0 + .dw 0xaec0, 0xc018, 0xaeff, 0xc018, 0x21, 0 + .dw 0xaf40, 0xc018, 0xaf7f, 0xc018, 0x21, 0 + .dw 0xafc0, 0xc018, 0xafff, 0xc018, 0x21, 0 + .dw 0xb040, 0xc018, 0xb07f, 0xc018, 0x21, 0 + .dw 0xb0c0, 0xc018, 0xb0ff, 0xc018, 0x21, 0 + .dw 0xb140, 0xc018, 0xb17f, 0xc018, 0x21, 0 + .dw 0xb1c0, 0xc018, 0xb1ff, 0xc018, 0x21, 0 + .dw 0xb240, 0xc018, 0xb27f, 0xc018, 0x21, 0 + .dw 0xb2c0, 0xc018, 0xb2ff, 0xc018, 0x21, 0 + .dw 0xb340, 0xc018, 0xb37f, 0xc018, 0x21, 0 + .dw 0xb3c0, 0xc018, 0xb3ff, 0xc018, 0x21, 0 + .dw 0xb440, 0xc018, 0xb47f, 0xc018, 0x21, 0 + .dw 0xb4c0, 0xc018, 0xb4ff, 0xc018, 0x21, 0 + .dw 0xb540, 0xc018, 0xb57f, 0xc018, 0x21, 0 + .dw 0xb5c0, 0xc018, 0xb5ff, 0xc018, 0x21, 0 + .dw 0xb640, 0xc018, 0xb67f, 0xc018, 0x21, 0 + .dw 0xb6c0, 0xc018, 0xb6ff, 0xc018, 0x21, 0 + .dw 0xb740, 0xc018, 0xb77f, 0xc018, 0x21, 0 + .dw 0xb7c0, 0xc018, 0xb7ff, 0xc018, 0x21, 0 + .dw 0xb840, 0xc018, 0xb87f, 0xc018, 0x21, 0 + .dw 0xb8c0, 0xc018, 0xb8ff, 0xc018, 0x21, 0 + .dw 0xb940, 0xc018, 0xb97f, 0xc018, 0x21, 0 + .dw 0xb9c0, 0xc018, 0xdfff, 0xc018, 0x21, 0 + .dw 0xe040, 0xc018, 0xe07f, 0xc018, 0x21, 0 + .dw 0xe0c0, 0xc018, 0xe0ff, 0xc018, 0x21, 0 + .dw 0xe140, 0xc018, 0xe17f, 0xc018, 0x21, 0 + .dw 0xe1c0, 0xc018, 0xe1ff, 0xc018, 0x21, 0 + .dw 0xe240, 0xc018, 0xe27f, 0xc018, 0x21, 0 + .dw 0xe2c0, 0xc018, 0xe2ff, 0xc018, 0x21, 0 + .dw 0xe340, 0xc018, 0xe37f, 0xc018, 0x21, 0 + .dw 0xe3c0, 0xc018, 0xe3ff, 0xc018, 0x21, 0 + .dw 0xe440, 0xc018, 0xe47f, 0xc018, 0x21, 0 + .dw 0xe4c0, 0xc018, 0xe4ff, 0xc018, 0x21, 0 + .dw 0xe540, 0xc018, 0xe57f, 0xc018, 0x21, 0 + .dw 0xe5c0, 0xc018, 0xe5ff, 0xc018, 0x21, 0 + .dw 0xe640, 0xc018, 0xe67f, 0xc018, 0x21, 0 + .dw 0xe6c0, 0xc018, 0xe6ff, 0xc018, 0x21, 0 + .dw 0xe740, 0xc018, 0xe77f, 0xc018, 0x21, 0 + .dw 0xe7c0, 0xc018, 0xe7ff, 0xc018, 0x21, 0 + .dw 0xe840, 0xc018, 0xe87f, 0xc018, 0x21, 0 + .dw 0xe8c0, 0xc018, 0xe8ff, 0xc018, 0x21, 0 + .dw 0xe940, 0xc018, 0xe97f, 0xc018, 0x21, 0 + .dw 0xe9c0, 0xc018, 0xe9ff, 0xc018, 0x21, 0 + .dw 0xea40, 0xc018, 0xea7f, 0xc018, 0x21, 0 + .dw 0xeac0, 0xc018, 0xeaff, 0xc018, 0x21, 0 + .dw 0xeb40, 0xc018, 0xeb7f, 0xc018, 0x21, 0 + .dw 0xebc0, 0xc018, 0xebff, 0xc018, 0x21, 0 + .dw 0xec40, 0xc018, 0xec7f, 0xc018, 0x21, 0 + .dw 0xecc0, 0xc018, 0xecff, 0xc018, 0x21, 0 + .dw 0xed40, 0xc018, 0xed7f, 0xc018, 0x21, 0 + .dw 0xedc0, 0xc018, 0xedff, 0xc018, 0x21, 0 + .dw 0xee40, 0xc018, 0xee7f, 0xc018, 0x21, 0 + .dw 0xeec0, 0xc018, 0xeeff, 0xc018, 0x21, 0 + .dw 0xef40, 0xc018, 0xef7f, 0xc018, 0x21, 0 + .dw 0xefc0, 0xc018, 0xefff, 0xc018, 0x21, 0 + .dw 0xf040, 0xc018, 0xf07f, 0xc018, 0x21, 0 + .dw 0xf0c0, 0xc018, 0xf0ff, 0xc018, 0x21, 0 + .dw 0xf140, 0xc018, 0xf17f, 0xc018, 0x21, 0 + .dw 0xf1c0, 0xc018, 0xf1ff, 0xc018, 0x21, 0 + .dw 0xf240, 0xc018, 0xf27f, 0xc018, 0x21, 0 + .dw 0xf2c0, 0xc018, 0xf2ff, 0xc018, 0x21, 0 + .dw 0xf340, 0xc018, 0xf37f, 0xc018, 0x21, 0 + .dw 0xf3c0, 0xc018, 0xf3ff, 0xc018, 0x21, 0 + .dw 0xf440, 0xc018, 0xf47f, 0xc018, 0x21, 0 + .dw 0xf4c0, 0xc018, 0xf4ff, 0xc018, 0x21, 0 + .dw 0xf540, 0xc018, 0xf57f, 0xc018, 0x21, 0 + .dw 0xf5c0, 0xc018, 0xf5ff, 0xc018, 0x21, 0 + .dw 0xf640, 0xc018, 0xf67f, 0xc018, 0x21, 0 + .dw 0xf6c0, 0xc018, 0xf6ff, 0xc018, 0x21, 0 + .dw 0xf740, 0xc018, 0xf77f, 0xc018, 0x21, 0 + .dw 0xf7c0, 0xc018, 0xf7ff, 0xc018, 0x21, 0 + .dw 0xf840, 0xc018, 0xf87f, 0xc018, 0x21, 0 + .dw 0xf8c0, 0xc018, 0xf8ff, 0xc018, 0x21, 0 + .dw 0xf940, 0xc018, 0xf97f, 0xc018, 0x21, 0 + .dw 0xf9c0, 0xc018, 0x1fff, 0xc019, 0x21, 0 + .dw 0x2040, 0xc019, 0x207f, 0xc019, 0x21, 0 + .dw 0x20c0, 0xc019, 0x20ff, 0xc019, 0x21, 0 + .dw 0x2140, 0xc019, 0x217f, 0xc019, 0x21, 0 + .dw 0x21c0, 0xc019, 0x21ff, 0xc019, 0x21, 0 + .dw 0x2240, 0xc019, 0x227f, 0xc019, 0x21, 0 + .dw 0x22c0, 0xc019, 0x22ff, 0xc019, 0x21, 0 + .dw 0x2340, 0xc019, 0x237f, 0xc019, 0x21, 0 + .dw 0x23c0, 0xc019, 0x23ff, 0xc019, 0x21, 0 + .dw 0x2440, 0xc019, 0x247f, 0xc019, 0x21, 0 + .dw 0x24c0, 0xc019, 0x24ff, 0xc019, 0x21, 0 + .dw 0x2540, 0xc019, 0x257f, 0xc019, 0x21, 0 + .dw 0x25c0, 0xc019, 0x25ff, 0xc019, 0x21, 0 + .dw 0x2640, 0xc019, 0x267f, 0xc019, 0x21, 0 + .dw 0x26c0, 0xc019, 0x26ff, 0xc019, 0x21, 0 + .dw 0x2740, 0xc019, 0x277f, 0xc019, 0x21, 0 + .dw 0x27c0, 0xc019, 0x27ff, 0xc019, 0x21, 0 + .dw 0x2840, 0xc019, 0x287f, 0xc019, 0x21, 0 + .dw 0x28c0, 0xc019, 0x28ff, 0xc019, 0x21, 0 + .dw 0x2940, 0xc019, 0x297f, 0xc019, 0x21, 0 + .dw 0x29c0, 0xc019, 0x29ff, 0xc019, 0x21, 0 + .dw 0x2a40, 0xc019, 0x2a7f, 0xc019, 0x21, 0 + .dw 0x2ac0, 0xc019, 0x2aff, 0xc019, 0x21, 0 + .dw 0x2b40, 0xc019, 0x2b7f, 0xc019, 0x21, 0 + .dw 0x2bc0, 0xc019, 0x2bff, 0xc019, 0x21, 0 + .dw 0x2c40, 0xc019, 0x2c7f, 0xc019, 0x21, 0 + .dw 0x2cc0, 0xc019, 0x2cff, 0xc019, 0x21, 0 + .dw 0x2d40, 0xc019, 0x2d7f, 0xc019, 0x21, 0 + .dw 0x2dc0, 0xc019, 0x2dff, 0xc019, 0x21, 0 + .dw 0x2e40, 0xc019, 0x2e7f, 0xc019, 0x21, 0 + .dw 0x2ec0, 0xc019, 0x2eff, 0xc019, 0x21, 0 + .dw 0x2f40, 0xc019, 0x2f7f, 0xc019, 0x21, 0 + .dw 0x2fc0, 0xc019, 0x2fff, 0xc019, 0x21, 0 + .dw 0x3040, 0xc019, 0x307f, 0xc019, 0x21, 0 + .dw 0x30c0, 0xc019, 0x30ff, 0xc019, 0x21, 0 + .dw 0x3140, 0xc019, 0x317f, 0xc019, 0x21, 0 + .dw 0x31c0, 0xc019, 0x31ff, 0xc019, 0x21, 0 + .dw 0x3240, 0xc019, 0x327f, 0xc019, 0x21, 0 + .dw 0x32c0, 0xc019, 0x32ff, 0xc019, 0x21, 0 + .dw 0x3340, 0xc019, 0x337f, 0xc019, 0x21, 0 + .dw 0x33c0, 0xc019, 0x33ff, 0xc019, 0x21, 0 + .dw 0x3440, 0xc019, 0x347f, 0xc019, 0x21, 0 + .dw 0x34c0, 0xc019, 0x34ff, 0xc019, 0x21, 0 + .dw 0x3540, 0xc019, 0x357f, 0xc019, 0x21, 0 + .dw 0x35c0, 0xc019, 0x35ff, 0xc019, 0x21, 0 + .dw 0x3640, 0xc019, 0x367f, 0xc019, 0x21, 0 + .dw 0x36c0, 0xc019, 0x36ff, 0xc019, 0x21, 0 + .dw 0x3740, 0xc019, 0x377f, 0xc019, 0x21, 0 + .dw 0x37c0, 0xc019, 0x37ff, 0xc019, 0x21, 0 + .dw 0x3840, 0xc019, 0x387f, 0xc019, 0x21, 0 + .dw 0x38c0, 0xc019, 0x38ff, 0xc019, 0x21, 0 + .dw 0x3940, 0xc019, 0x397f, 0xc019, 0x21, 0 + .dw 0x39c0, 0xc019, 0x5fff, 0xc019, 0x21, 0 + .dw 0x6040, 0xc019, 0x607f, 0xc019, 0x21, 0 + .dw 0x60c0, 0xc019, 0x60ff, 0xc019, 0x21, 0 + .dw 0x6140, 0xc019, 0x617f, 0xc019, 0x21, 0 + .dw 0x61c0, 0xc019, 0x61ff, 0xc019, 0x21, 0 + .dw 0x6240, 0xc019, 0x627f, 0xc019, 0x21, 0 + .dw 0x62c0, 0xc019, 0x62ff, 0xc019, 0x21, 0 + .dw 0x6340, 0xc019, 0x637f, 0xc019, 0x21, 0 + .dw 0x63c0, 0xc019, 0x63ff, 0xc019, 0x21, 0 + .dw 0x6440, 0xc019, 0x647f, 0xc019, 0x21, 0 + .dw 0x64c0, 0xc019, 0x64ff, 0xc019, 0x21, 0 + .dw 0x6540, 0xc019, 0x657f, 0xc019, 0x21, 0 + .dw 0x65c0, 0xc019, 0x65ff, 0xc019, 0x21, 0 + .dw 0x6640, 0xc019, 0x667f, 0xc019, 0x21, 0 + .dw 0x66c0, 0xc019, 0x66ff, 0xc019, 0x21, 0 + .dw 0x6740, 0xc019, 0x677f, 0xc019, 0x21, 0 + .dw 0x67c0, 0xc019, 0x67ff, 0xc019, 0x21, 0 + .dw 0x6840, 0xc019, 0x687f, 0xc019, 0x21, 0 + .dw 0x68c0, 0xc019, 0x68ff, 0xc019, 0x21, 0 + .dw 0x6940, 0xc019, 0x697f, 0xc019, 0x21, 0 + .dw 0x69c0, 0xc019, 0x69ff, 0xc019, 0x21, 0 + .dw 0x6a40, 0xc019, 0x6a7f, 0xc019, 0x21, 0 + .dw 0x6ac0, 0xc019, 0x6aff, 0xc019, 0x21, 0 + .dw 0x6b40, 0xc019, 0x6b7f, 0xc019, 0x21, 0 + .dw 0x6bc0, 0xc019, 0x6bff, 0xc019, 0x21, 0 + .dw 0x6c40, 0xc019, 0x6c7f, 0xc019, 0x21, 0 + .dw 0x6cc0, 0xc019, 0x6cff, 0xc019, 0x21, 0 + .dw 0x6d40, 0xc019, 0x6d7f, 0xc019, 0x21, 0 + .dw 0x6dc0, 0xc019, 0x6dff, 0xc019, 0x21, 0 + .dw 0x6e40, 0xc019, 0x6e7f, 0xc019, 0x21, 0 + .dw 0x6ec0, 0xc019, 0x6eff, 0xc019, 0x21, 0 + .dw 0x6f40, 0xc019, 0x6f7f, 0xc019, 0x21, 0 + .dw 0x6fc0, 0xc019, 0x6fff, 0xc019, 0x21, 0 + .dw 0x7040, 0xc019, 0x707f, 0xc019, 0x21, 0 + .dw 0x70c0, 0xc019, 0x70ff, 0xc019, 0x21, 0 + .dw 0x7140, 0xc019, 0x717f, 0xc019, 0x21, 0 + .dw 0x71c0, 0xc019, 0x71ff, 0xc019, 0x21, 0 + .dw 0x7240, 0xc019, 0x727f, 0xc019, 0x21, 0 + .dw 0x72c0, 0xc019, 0x72ff, 0xc019, 0x21, 0 + .dw 0x7340, 0xc019, 0x737f, 0xc019, 0x21, 0 + .dw 0x73c0, 0xc019, 0x73ff, 0xc019, 0x21, 0 + .dw 0x7440, 0xc019, 0x747f, 0xc019, 0x21, 0 + .dw 0x74c0, 0xc019, 0x74ff, 0xc019, 0x21, 0 + .dw 0x7540, 0xc019, 0x757f, 0xc019, 0x21, 0 + .dw 0x75c0, 0xc019, 0x75ff, 0xc019, 0x21, 0 + .dw 0x7640, 0xc019, 0x767f, 0xc019, 0x21, 0 + .dw 0x76c0, 0xc019, 0x76ff, 0xc019, 0x21, 0 + .dw 0x7740, 0xc019, 0x777f, 0xc019, 0x21, 0 + .dw 0x77c0, 0xc019, 0x77ff, 0xc019, 0x21, 0 + .dw 0x7840, 0xc019, 0x787f, 0xc019, 0x21, 0 + .dw 0x78c0, 0xc019, 0x78ff, 0xc019, 0x21, 0 + .dw 0x7940, 0xc019, 0x797f, 0xc019, 0x21, 0 + .dw 0x79c0, 0xc019, 0x9fff, 0xc019, 0x21, 0 + .dw 0xa040, 0xc019, 0xa07f, 0xc019, 0x21, 0 + .dw 0xa0c0, 0xc019, 0xa0ff, 0xc019, 0x21, 0 + .dw 0xa140, 0xc019, 0xa17f, 0xc019, 0x21, 0 + .dw 0xa1c0, 0xc019, 0xa1ff, 0xc019, 0x21, 0 + .dw 0xa240, 0xc019, 0xa27f, 0xc019, 0x21, 0 + .dw 0xa2c0, 0xc019, 0xa2ff, 0xc019, 0x21, 0 + .dw 0xa340, 0xc019, 0xa37f, 0xc019, 0x21, 0 + .dw 0xa3c0, 0xc019, 0xa3ff, 0xc019, 0x21, 0 + .dw 0xa440, 0xc019, 0xa47f, 0xc019, 0x21, 0 + .dw 0xa4c0, 0xc019, 0xa4ff, 0xc019, 0x21, 0 + .dw 0xa540, 0xc019, 0xa57f, 0xc019, 0x21, 0 + .dw 0xa5c0, 0xc019, 0xa5ff, 0xc019, 0x21, 0 + .dw 0xa640, 0xc019, 0xa67f, 0xc019, 0x21, 0 + .dw 0xa6c0, 0xc019, 0xa6ff, 0xc019, 0x21, 0 + .dw 0xa740, 0xc019, 0xa77f, 0xc019, 0x21, 0 + .dw 0xa7c0, 0xc019, 0xa7ff, 0xc019, 0x21, 0 + .dw 0xa840, 0xc019, 0xa87f, 0xc019, 0x21, 0 + .dw 0xa8c0, 0xc019, 0xa8ff, 0xc019, 0x21, 0 + .dw 0xa940, 0xc019, 0xa97f, 0xc019, 0x21, 0 + .dw 0xa9c0, 0xc019, 0xa9ff, 0xc019, 0x21, 0 + .dw 0xaa40, 0xc019, 0xaa7f, 0xc019, 0x21, 0 + .dw 0xaac0, 0xc019, 0xaaff, 0xc019, 0x21, 0 + .dw 0xab40, 0xc019, 0xab7f, 0xc019, 0x21, 0 + .dw 0xabc0, 0xc019, 0xabff, 0xc019, 0x21, 0 + .dw 0xac40, 0xc019, 0xac7f, 0xc019, 0x21, 0 + .dw 0xacc0, 0xc019, 0xacff, 0xc019, 0x21, 0 + .dw 0xad40, 0xc019, 0xad7f, 0xc019, 0x21, 0 + .dw 0xadc0, 0xc019, 0xadff, 0xc019, 0x21, 0 + .dw 0xae40, 0xc019, 0xae7f, 0xc019, 0x21, 0 + .dw 0xaec0, 0xc019, 0xaeff, 0xc019, 0x21, 0 + .dw 0xaf40, 0xc019, 0xaf7f, 0xc019, 0x21, 0 + .dw 0xafc0, 0xc019, 0xafff, 0xc019, 0x21, 0 + .dw 0xb040, 0xc019, 0xb07f, 0xc019, 0x21, 0 + .dw 0xb0c0, 0xc019, 0xb0ff, 0xc019, 0x21, 0 + .dw 0xb140, 0xc019, 0xb17f, 0xc019, 0x21, 0 + .dw 0xb1c0, 0xc019, 0xb1ff, 0xc019, 0x21, 0 + .dw 0xb240, 0xc019, 0xb27f, 0xc019, 0x21, 0 + .dw 0xb2c0, 0xc019, 0xb2ff, 0xc019, 0x21, 0 + .dw 0xb340, 0xc019, 0xb37f, 0xc019, 0x21, 0 + .dw 0xb3c0, 0xc019, 0xb3ff, 0xc019, 0x21, 0 + .dw 0xb440, 0xc019, 0xb47f, 0xc019, 0x21, 0 + .dw 0xb4c0, 0xc019, 0xb4ff, 0xc019, 0x21, 0 + .dw 0xb540, 0xc019, 0xb57f, 0xc019, 0x21, 0 + .dw 0xb5c0, 0xc019, 0xb5ff, 0xc019, 0x21, 0 + .dw 0xb640, 0xc019, 0xb67f, 0xc019, 0x21, 0 + .dw 0xb6c0, 0xc019, 0xb6ff, 0xc019, 0x21, 0 + .dw 0xb740, 0xc019, 0xb77f, 0xc019, 0x21, 0 + .dw 0xb7c0, 0xc019, 0xb7ff, 0xc019, 0x21, 0 + .dw 0xb840, 0xc019, 0xb87f, 0xc019, 0x21, 0 + .dw 0xb8c0, 0xc019, 0xb8ff, 0xc019, 0x21, 0 + .dw 0xb940, 0xc019, 0xb97f, 0xc019, 0x21, 0 + .dw 0xb9c0, 0xc019, 0xdfff, 0xc019, 0x21, 0 + .dw 0xe040, 0xc019, 0xe07f, 0xc019, 0x21, 0 + .dw 0xe0c0, 0xc019, 0xe0ff, 0xc019, 0x21, 0 + .dw 0xe140, 0xc019, 0xe17f, 0xc019, 0x21, 0 + .dw 0xe1c0, 0xc019, 0xe1ff, 0xc019, 0x21, 0 + .dw 0xe240, 0xc019, 0xe27f, 0xc019, 0x21, 0 + .dw 0xe2c0, 0xc019, 0xe2ff, 0xc019, 0x21, 0 + .dw 0xe340, 0xc019, 0xe37f, 0xc019, 0x21, 0 + .dw 0xe3c0, 0xc019, 0xe3ff, 0xc019, 0x21, 0 + .dw 0xe440, 0xc019, 0xe47f, 0xc019, 0x21, 0 + .dw 0xe4c0, 0xc019, 0xe4ff, 0xc019, 0x21, 0 + .dw 0xe540, 0xc019, 0xe57f, 0xc019, 0x21, 0 + .dw 0xe5c0, 0xc019, 0xe5ff, 0xc019, 0x21, 0 + .dw 0xe640, 0xc019, 0xe67f, 0xc019, 0x21, 0 + .dw 0xe6c0, 0xc019, 0xe6ff, 0xc019, 0x21, 0 + .dw 0xe740, 0xc019, 0xe77f, 0xc019, 0x21, 0 + .dw 0xe7c0, 0xc019, 0xe7ff, 0xc019, 0x21, 0 + .dw 0xe840, 0xc019, 0xe87f, 0xc019, 0x21, 0 + .dw 0xe8c0, 0xc019, 0xe8ff, 0xc019, 0x21, 0 + .dw 0xe940, 0xc019, 0xe97f, 0xc019, 0x21, 0 + .dw 0xe9c0, 0xc019, 0xe9ff, 0xc019, 0x21, 0 + .dw 0xea40, 0xc019, 0xea7f, 0xc019, 0x21, 0 + .dw 0xeac0, 0xc019, 0xeaff, 0xc019, 0x21, 0 + .dw 0xeb40, 0xc019, 0xeb7f, 0xc019, 0x21, 0 + .dw 0xebc0, 0xc019, 0xebff, 0xc019, 0x21, 0 + .dw 0xec40, 0xc019, 0xec7f, 0xc019, 0x21, 0 + .dw 0xecc0, 0xc019, 0xecff, 0xc019, 0x21, 0 + .dw 0xed40, 0xc019, 0xed7f, 0xc019, 0x21, 0 + .dw 0xedc0, 0xc019, 0xedff, 0xc019, 0x21, 0 + .dw 0xee40, 0xc019, 0xee7f, 0xc019, 0x21, 0 + .dw 0xeec0, 0xc019, 0xeeff, 0xc019, 0x21, 0 + .dw 0xef40, 0xc019, 0xef7f, 0xc019, 0x21, 0 + .dw 0xefc0, 0xc019, 0xefff, 0xc019, 0x21, 0 + .dw 0xf040, 0xc019, 0xf07f, 0xc019, 0x21, 0 + .dw 0xf0c0, 0xc019, 0xf0ff, 0xc019, 0x21, 0 + .dw 0xf140, 0xc019, 0xf17f, 0xc019, 0x21, 0 + .dw 0xf1c0, 0xc019, 0xf1ff, 0xc019, 0x21, 0 + .dw 0xf240, 0xc019, 0xf27f, 0xc019, 0x21, 0 + .dw 0xf2c0, 0xc019, 0xf2ff, 0xc019, 0x21, 0 + .dw 0xf340, 0xc019, 0xf37f, 0xc019, 0x21, 0 + .dw 0xf3c0, 0xc019, 0xf3ff, 0xc019, 0x21, 0 + .dw 0xf440, 0xc019, 0xf47f, 0xc019, 0x21, 0 + .dw 0xf4c0, 0xc019, 0xf4ff, 0xc019, 0x21, 0 + .dw 0xf540, 0xc019, 0xf57f, 0xc019, 0x21, 0 + .dw 0xf5c0, 0xc019, 0xf5ff, 0xc019, 0x21, 0 + .dw 0xf640, 0xc019, 0xf67f, 0xc019, 0x21, 0 + .dw 0xf6c0, 0xc019, 0xf6ff, 0xc019, 0x21, 0 + .dw 0xf740, 0xc019, 0xf77f, 0xc019, 0x21, 0 + .dw 0xf7c0, 0xc019, 0xf7ff, 0xc019, 0x21, 0 + .dw 0xf840, 0xc019, 0xf87f, 0xc019, 0x21, 0 + .dw 0xf8c0, 0xc019, 0xf8ff, 0xc019, 0x21, 0 + .dw 0xf940, 0xc019, 0xf97f, 0xc019, 0x21, 0 + .dw 0xf9c0, 0xc019, 0x1fff, 0xc01a, 0x21, 0 + .dw 0x2040, 0xc01a, 0x207f, 0xc01a, 0x21, 0 + .dw 0x20c0, 0xc01a, 0x20ff, 0xc01a, 0x21, 0 + .dw 0x2140, 0xc01a, 0x217f, 0xc01a, 0x21, 0 + .dw 0x21c0, 0xc01a, 0x21ff, 0xc01a, 0x21, 0 + .dw 0x2240, 0xc01a, 0x227f, 0xc01a, 0x21, 0 + .dw 0x22c0, 0xc01a, 0x22ff, 0xc01a, 0x21, 0 + .dw 0x2340, 0xc01a, 0x237f, 0xc01a, 0x21, 0 + .dw 0x23c0, 0xc01a, 0x23ff, 0xc01a, 0x21, 0 + .dw 0x2440, 0xc01a, 0x247f, 0xc01a, 0x21, 0 + .dw 0x24c0, 0xc01a, 0x24ff, 0xc01a, 0x21, 0 + .dw 0x2540, 0xc01a, 0x257f, 0xc01a, 0x21, 0 + .dw 0x25c0, 0xc01a, 0x25ff, 0xc01a, 0x21, 0 + .dw 0x2640, 0xc01a, 0x267f, 0xc01a, 0x21, 0 + .dw 0x26c0, 0xc01a, 0x26ff, 0xc01a, 0x21, 0 + .dw 0x2740, 0xc01a, 0x277f, 0xc01a, 0x21, 0 + .dw 0x27c0, 0xc01a, 0x27ff, 0xc01a, 0x21, 0 + .dw 0x2840, 0xc01a, 0x287f, 0xc01a, 0x21, 0 + .dw 0x28c0, 0xc01a, 0x28ff, 0xc01a, 0x21, 0 + .dw 0x2940, 0xc01a, 0x297f, 0xc01a, 0x21, 0 + .dw 0x29c0, 0xc01a, 0x29ff, 0xc01a, 0x21, 0 + .dw 0x2a40, 0xc01a, 0x2a7f, 0xc01a, 0x21, 0 + .dw 0x2ac0, 0xc01a, 0x2aff, 0xc01a, 0x21, 0 + .dw 0x2b40, 0xc01a, 0x2b7f, 0xc01a, 0x21, 0 + .dw 0x2bc0, 0xc01a, 0x2bff, 0xc01a, 0x21, 0 + .dw 0x2c40, 0xc01a, 0x2c7f, 0xc01a, 0x21, 0 + .dw 0x2cc0, 0xc01a, 0x2cff, 0xc01a, 0x21, 0 + .dw 0x2d40, 0xc01a, 0x2d7f, 0xc01a, 0x21, 0 + .dw 0x2dc0, 0xc01a, 0x2dff, 0xc01a, 0x21, 0 + .dw 0x2e40, 0xc01a, 0x2e7f, 0xc01a, 0x21, 0 + .dw 0x2ec0, 0xc01a, 0x2eff, 0xc01a, 0x21, 0 + .dw 0x2f40, 0xc01a, 0x2f7f, 0xc01a, 0x21, 0 + .dw 0x2fc0, 0xc01a, 0x2fff, 0xc01a, 0x21, 0 + .dw 0x3040, 0xc01a, 0x307f, 0xc01a, 0x21, 0 + .dw 0x30c0, 0xc01a, 0x30ff, 0xc01a, 0x21, 0 + .dw 0x3140, 0xc01a, 0x317f, 0xc01a, 0x21, 0 + .dw 0x31c0, 0xc01a, 0x31ff, 0xc01a, 0x21, 0 + .dw 0x3240, 0xc01a, 0x327f, 0xc01a, 0x21, 0 + .dw 0x32c0, 0xc01a, 0x32ff, 0xc01a, 0x21, 0 + .dw 0x3340, 0xc01a, 0x337f, 0xc01a, 0x21, 0 + .dw 0x33c0, 0xc01a, 0x33ff, 0xc01a, 0x21, 0 + .dw 0x3440, 0xc01a, 0x347f, 0xc01a, 0x21, 0 + .dw 0x34c0, 0xc01a, 0x34ff, 0xc01a, 0x21, 0 + .dw 0x3540, 0xc01a, 0x357f, 0xc01a, 0x21, 0 + .dw 0x35c0, 0xc01a, 0x35ff, 0xc01a, 0x21, 0 + .dw 0x3640, 0xc01a, 0x367f, 0xc01a, 0x21, 0 + .dw 0x36c0, 0xc01a, 0x36ff, 0xc01a, 0x21, 0 + .dw 0x3740, 0xc01a, 0x377f, 0xc01a, 0x21, 0 + .dw 0x37c0, 0xc01a, 0x37ff, 0xc01a, 0x21, 0 + .dw 0x3840, 0xc01a, 0x387f, 0xc01a, 0x21, 0 + .dw 0x38c0, 0xc01a, 0x38ff, 0xc01a, 0x21, 0 + .dw 0x3940, 0xc01a, 0x397f, 0xc01a, 0x21, 0 + .dw 0x39c0, 0xc01a, 0x5fff, 0xc01a, 0x21, 0 + .dw 0x6040, 0xc01a, 0x607f, 0xc01a, 0x21, 0 + .dw 0x60c0, 0xc01a, 0x60ff, 0xc01a, 0x21, 0 + .dw 0x6140, 0xc01a, 0x617f, 0xc01a, 0x21, 0 + .dw 0x61c0, 0xc01a, 0x61ff, 0xc01a, 0x21, 0 + .dw 0x6240, 0xc01a, 0x627f, 0xc01a, 0x21, 0 + .dw 0x62c0, 0xc01a, 0x62ff, 0xc01a, 0x21, 0 + .dw 0x6340, 0xc01a, 0x637f, 0xc01a, 0x21, 0 + .dw 0x63c0, 0xc01a, 0x63ff, 0xc01a, 0x21, 0 + .dw 0x6440, 0xc01a, 0x647f, 0xc01a, 0x21, 0 + .dw 0x64c0, 0xc01a, 0x64ff, 0xc01a, 0x21, 0 + .dw 0x6540, 0xc01a, 0x657f, 0xc01a, 0x21, 0 + .dw 0x65c0, 0xc01a, 0x65ff, 0xc01a, 0x21, 0 + .dw 0x6640, 0xc01a, 0x667f, 0xc01a, 0x21, 0 + .dw 0x66c0, 0xc01a, 0x66ff, 0xc01a, 0x21, 0 + .dw 0x6740, 0xc01a, 0x677f, 0xc01a, 0x21, 0 + .dw 0x67c0, 0xc01a, 0x67ff, 0xc01a, 0x21, 0 + .dw 0x6840, 0xc01a, 0x687f, 0xc01a, 0x21, 0 + .dw 0x68c0, 0xc01a, 0x68ff, 0xc01a, 0x21, 0 + .dw 0x6940, 0xc01a, 0x697f, 0xc01a, 0x21, 0 + .dw 0x69c0, 0xc01a, 0x69ff, 0xc01a, 0x21, 0 + .dw 0x6a40, 0xc01a, 0x6a7f, 0xc01a, 0x21, 0 + .dw 0x6ac0, 0xc01a, 0x6aff, 0xc01a, 0x21, 0 + .dw 0x6b40, 0xc01a, 0x6b7f, 0xc01a, 0x21, 0 + .dw 0x6bc0, 0xc01a, 0x6bff, 0xc01a, 0x21, 0 + .dw 0x6c40, 0xc01a, 0x6c7f, 0xc01a, 0x21, 0 + .dw 0x6cc0, 0xc01a, 0x6cff, 0xc01a, 0x21, 0 + .dw 0x6d40, 0xc01a, 0x6d7f, 0xc01a, 0x21, 0 + .dw 0x6dc0, 0xc01a, 0x6dff, 0xc01a, 0x21, 0 + .dw 0x6e40, 0xc01a, 0x6e7f, 0xc01a, 0x21, 0 + .dw 0x6ec0, 0xc01a, 0x6eff, 0xc01a, 0x21, 0 + .dw 0x6f40, 0xc01a, 0x6f7f, 0xc01a, 0x21, 0 + .dw 0x6fc0, 0xc01a, 0x6fff, 0xc01a, 0x21, 0 + .dw 0x7040, 0xc01a, 0x707f, 0xc01a, 0x21, 0 + .dw 0x70c0, 0xc01a, 0x70ff, 0xc01a, 0x21, 0 + .dw 0x7140, 0xc01a, 0x717f, 0xc01a, 0x21, 0 + .dw 0x71c0, 0xc01a, 0x71ff, 0xc01a, 0x21, 0 + .dw 0x7240, 0xc01a, 0x727f, 0xc01a, 0x21, 0 + .dw 0x72c0, 0xc01a, 0x72ff, 0xc01a, 0x21, 0 + .dw 0x7340, 0xc01a, 0x737f, 0xc01a, 0x21, 0 + .dw 0x73c0, 0xc01a, 0x73ff, 0xc01a, 0x21, 0 + .dw 0x7440, 0xc01a, 0x747f, 0xc01a, 0x21, 0 + .dw 0x74c0, 0xc01a, 0x74ff, 0xc01a, 0x21, 0 + .dw 0x7540, 0xc01a, 0x757f, 0xc01a, 0x21, 0 + .dw 0x75c0, 0xc01a, 0x75ff, 0xc01a, 0x21, 0 + .dw 0x7640, 0xc01a, 0x767f, 0xc01a, 0x21, 0 + .dw 0x76c0, 0xc01a, 0x76ff, 0xc01a, 0x21, 0 + .dw 0x7740, 0xc01a, 0x777f, 0xc01a, 0x21, 0 + .dw 0x77c0, 0xc01a, 0x77ff, 0xc01a, 0x21, 0 + .dw 0x7840, 0xc01a, 0x787f, 0xc01a, 0x21, 0 + .dw 0x78c0, 0xc01a, 0x78ff, 0xc01a, 0x21, 0 + .dw 0x7940, 0xc01a, 0x797f, 0xc01a, 0x21, 0 + .dw 0x79c0, 0xc01a, 0x9fff, 0xc01a, 0x21, 0 + .dw 0xa040, 0xc01a, 0xa07f, 0xc01a, 0x21, 0 + .dw 0xa0c0, 0xc01a, 0xa0ff, 0xc01a, 0x21, 0 + .dw 0xa140, 0xc01a, 0xa17f, 0xc01a, 0x21, 0 + .dw 0xa1c0, 0xc01a, 0xa1ff, 0xc01a, 0x21, 0 + .dw 0xa240, 0xc01a, 0xa27f, 0xc01a, 0x21, 0 + .dw 0xa2c0, 0xc01a, 0xa2ff, 0xc01a, 0x21, 0 + .dw 0xa340, 0xc01a, 0xa37f, 0xc01a, 0x21, 0 + .dw 0xa3c0, 0xc01a, 0xa3ff, 0xc01a, 0x21, 0 + .dw 0xa440, 0xc01a, 0xa47f, 0xc01a, 0x21, 0 + .dw 0xa4c0, 0xc01a, 0xa4ff, 0xc01a, 0x21, 0 + .dw 0xa540, 0xc01a, 0xa57f, 0xc01a, 0x21, 0 + .dw 0xa5c0, 0xc01a, 0xa5ff, 0xc01a, 0x21, 0 + .dw 0xa640, 0xc01a, 0xa67f, 0xc01a, 0x21, 0 + .dw 0xa6c0, 0xc01a, 0xa6ff, 0xc01a, 0x21, 0 + .dw 0xa740, 0xc01a, 0xa77f, 0xc01a, 0x21, 0 + .dw 0xa7c0, 0xc01a, 0xa7ff, 0xc01a, 0x21, 0 + .dw 0xa840, 0xc01a, 0xa87f, 0xc01a, 0x21, 0 + .dw 0xa8c0, 0xc01a, 0xa8ff, 0xc01a, 0x21, 0 + .dw 0xa940, 0xc01a, 0xa97f, 0xc01a, 0x21, 0 + .dw 0xa9c0, 0xc01a, 0xa9ff, 0xc01a, 0x21, 0 + .dw 0xaa40, 0xc01a, 0xaa7f, 0xc01a, 0x21, 0 + .dw 0xaac0, 0xc01a, 0xaaff, 0xc01a, 0x21, 0 + .dw 0xab40, 0xc01a, 0xab7f, 0xc01a, 0x21, 0 + .dw 0xabc0, 0xc01a, 0xabff, 0xc01a, 0x21, 0 + .dw 0xac40, 0xc01a, 0xac7f, 0xc01a, 0x21, 0 + .dw 0xacc0, 0xc01a, 0xacff, 0xc01a, 0x21, 0 + .dw 0xad40, 0xc01a, 0xad7f, 0xc01a, 0x21, 0 + .dw 0xadc0, 0xc01a, 0xadff, 0xc01a, 0x21, 0 + .dw 0xae40, 0xc01a, 0xae7f, 0xc01a, 0x21, 0 + .dw 0xaec0, 0xc01a, 0xaeff, 0xc01a, 0x21, 0 + .dw 0xaf40, 0xc01a, 0xaf7f, 0xc01a, 0x21, 0 + .dw 0xafc0, 0xc01a, 0xafff, 0xc01a, 0x21, 0 + .dw 0xb040, 0xc01a, 0xb07f, 0xc01a, 0x21, 0 + .dw 0xb0c0, 0xc01a, 0xb0ff, 0xc01a, 0x21, 0 + .dw 0xb140, 0xc01a, 0xb17f, 0xc01a, 0x21, 0 + .dw 0xb1c0, 0xc01a, 0xb1ff, 0xc01a, 0x21, 0 + .dw 0xb240, 0xc01a, 0xb27f, 0xc01a, 0x21, 0 + .dw 0xb2c0, 0xc01a, 0xb2ff, 0xc01a, 0x21, 0 + .dw 0xb340, 0xc01a, 0xb37f, 0xc01a, 0x21, 0 + .dw 0xb3c0, 0xc01a, 0xb3ff, 0xc01a, 0x21, 0 + .dw 0xb440, 0xc01a, 0xb47f, 0xc01a, 0x21, 0 + .dw 0xb4c0, 0xc01a, 0xb4ff, 0xc01a, 0x21, 0 + .dw 0xb540, 0xc01a, 0xb57f, 0xc01a, 0x21, 0 + .dw 0xb5c0, 0xc01a, 0xb5ff, 0xc01a, 0x21, 0 + .dw 0xb640, 0xc01a, 0xb67f, 0xc01a, 0x21, 0 + .dw 0xb6c0, 0xc01a, 0xb6ff, 0xc01a, 0x21, 0 + .dw 0xb740, 0xc01a, 0xb77f, 0xc01a, 0x21, 0 + .dw 0xb7c0, 0xc01a, 0xb7ff, 0xc01a, 0x21, 0 + .dw 0xb840, 0xc01a, 0xb87f, 0xc01a, 0x21, 0 + .dw 0xb8c0, 0xc01a, 0xb8ff, 0xc01a, 0x21, 0 + .dw 0xb940, 0xc01a, 0xb97f, 0xc01a, 0x21, 0 + .dw 0xb9c0, 0xc01a, 0xdfff, 0xc01a, 0x21, 0 + .dw 0xe040, 0xc01a, 0xe07f, 0xc01a, 0x21, 0 + .dw 0xe0c0, 0xc01a, 0xe0ff, 0xc01a, 0x21, 0 + .dw 0xe140, 0xc01a, 0xe17f, 0xc01a, 0x21, 0 + .dw 0xe1c0, 0xc01a, 0xe1ff, 0xc01a, 0x21, 0 + .dw 0xe240, 0xc01a, 0xe27f, 0xc01a, 0x21, 0 + .dw 0xe2c0, 0xc01a, 0xe2ff, 0xc01a, 0x21, 0 + .dw 0xe340, 0xc01a, 0xe37f, 0xc01a, 0x21, 0 + .dw 0xe3c0, 0xc01a, 0xe3ff, 0xc01a, 0x21, 0 + .dw 0xe440, 0xc01a, 0xe47f, 0xc01a, 0x21, 0 + .dw 0xe4c0, 0xc01a, 0xe4ff, 0xc01a, 0x21, 0 + .dw 0xe540, 0xc01a, 0xe57f, 0xc01a, 0x21, 0 + .dw 0xe5c0, 0xc01a, 0xe5ff, 0xc01a, 0x21, 0 + .dw 0xe640, 0xc01a, 0xe67f, 0xc01a, 0x21, 0 + .dw 0xe6c0, 0xc01a, 0xe6ff, 0xc01a, 0x21, 0 + .dw 0xe740, 0xc01a, 0xe77f, 0xc01a, 0x21, 0 + .dw 0xe7c0, 0xc01a, 0xe7ff, 0xc01a, 0x21, 0 + .dw 0xe840, 0xc01a, 0xe87f, 0xc01a, 0x21, 0 + .dw 0xe8c0, 0xc01a, 0xe8ff, 0xc01a, 0x21, 0 + .dw 0xe940, 0xc01a, 0xe97f, 0xc01a, 0x21, 0 + .dw 0xe9c0, 0xc01a, 0xe9ff, 0xc01a, 0x21, 0 + .dw 0xea40, 0xc01a, 0xea7f, 0xc01a, 0x21, 0 + .dw 0xeac0, 0xc01a, 0xeaff, 0xc01a, 0x21, 0 + .dw 0xeb40, 0xc01a, 0xeb7f, 0xc01a, 0x21, 0 + .dw 0xebc0, 0xc01a, 0xebff, 0xc01a, 0x21, 0 + .dw 0xec40, 0xc01a, 0xec7f, 0xc01a, 0x21, 0 + .dw 0xecc0, 0xc01a, 0xecff, 0xc01a, 0x21, 0 + .dw 0xed40, 0xc01a, 0xed7f, 0xc01a, 0x21, 0 + .dw 0xedc0, 0xc01a, 0xedff, 0xc01a, 0x21, 0 + .dw 0xee40, 0xc01a, 0xee7f, 0xc01a, 0x21, 0 + .dw 0xeec0, 0xc01a, 0xeeff, 0xc01a, 0x21, 0 + .dw 0xef40, 0xc01a, 0xef7f, 0xc01a, 0x21, 0 + .dw 0xefc0, 0xc01a, 0xefff, 0xc01a, 0x21, 0 + .dw 0xf040, 0xc01a, 0xf07f, 0xc01a, 0x21, 0 + .dw 0xf0c0, 0xc01a, 0xf0ff, 0xc01a, 0x21, 0 + .dw 0xf140, 0xc01a, 0xf17f, 0xc01a, 0x21, 0 + .dw 0xf1c0, 0xc01a, 0xf1ff, 0xc01a, 0x21, 0 + .dw 0xf240, 0xc01a, 0xf27f, 0xc01a, 0x21, 0 + .dw 0xf2c0, 0xc01a, 0xf2ff, 0xc01a, 0x21, 0 + .dw 0xf340, 0xc01a, 0xf37f, 0xc01a, 0x21, 0 + .dw 0xf3c0, 0xc01a, 0xf3ff, 0xc01a, 0x21, 0 + .dw 0xf440, 0xc01a, 0xf47f, 0xc01a, 0x21, 0 + .dw 0xf4c0, 0xc01a, 0xf4ff, 0xc01a, 0x21, 0 + .dw 0xf540, 0xc01a, 0xf57f, 0xc01a, 0x21, 0 + .dw 0xf5c0, 0xc01a, 0xf5ff, 0xc01a, 0x21, 0 + .dw 0xf640, 0xc01a, 0xf67f, 0xc01a, 0x21, 0 + .dw 0xf6c0, 0xc01a, 0xf6ff, 0xc01a, 0x21, 0 + .dw 0xf740, 0xc01a, 0xf77f, 0xc01a, 0x21, 0 + .dw 0xf7c0, 0xc01a, 0xf7ff, 0xc01a, 0x21, 0 + .dw 0xf840, 0xc01a, 0xf87f, 0xc01a, 0x21, 0 + .dw 0xf8c0, 0xc01a, 0xf8ff, 0xc01a, 0x21, 0 + .dw 0xf940, 0xc01a, 0xf97f, 0xc01a, 0x21, 0 + .dw 0xf9c0, 0xc01a, 0xffff, 0xc01b, 0x21, 0 + .dw 0x0040, 0xc01c, 0x007f, 0xc01c, 0x21, 0 + .dw 0x00c0, 0xc01c, 0x00ff, 0xc01c, 0x21, 0 + .dw 0x0140, 0xc01c, 0x017f, 0xc01c, 0x21, 0 + .dw 0x01c0, 0xc01c, 0x01ff, 0xc01c, 0x21, 0 + .dw 0x0240, 0xc01c, 0x027f, 0xc01c, 0x21, 0 + .dw 0x02c0, 0xc01c, 0x02ff, 0xc01c, 0x21, 0 + .dw 0x0340, 0xc01c, 0x037f, 0xc01c, 0x21, 0 + .dw 0x03c0, 0xc01c, 0x03ff, 0xc01c, 0x21, 0 + .dw 0x0440, 0xc01c, 0x047f, 0xc01c, 0x21, 0 + .dw 0x04c0, 0xc01c, 0x04ff, 0xc01c, 0x21, 0 + .dw 0x0540, 0xc01c, 0x057f, 0xc01c, 0x21, 0 + .dw 0x05c0, 0xc01c, 0x05ff, 0xc01c, 0x21, 0 + .dw 0x0640, 0xc01c, 0x067f, 0xc01c, 0x21, 0 + .dw 0x06c0, 0xc01c, 0x06ff, 0xc01c, 0x21, 0 + .dw 0x0740, 0xc01c, 0x077f, 0xc01c, 0x21, 0 + .dw 0x07c0, 0xc01c, 0x07ff, 0xc01c, 0x21, 0 + .dw 0x0840, 0xc01c, 0x087f, 0xc01c, 0x21, 0 + .dw 0x08c0, 0xc01c, 0x08ff, 0xc01c, 0x21, 0 + .dw 0x0940, 0xc01c, 0x097f, 0xc01c, 0x21, 0 + .dw 0x09c0, 0xc01c, 0x09ff, 0xc01c, 0x21, 0 + .dw 0x0a40, 0xc01c, 0x0a7f, 0xc01c, 0x21, 0 + .dw 0x0ac0, 0xc01c, 0x0aff, 0xc01c, 0x21, 0 + .dw 0x0b40, 0xc01c, 0x0b7f, 0xc01c, 0x21, 0 + .dw 0x0bc0, 0xc01c, 0x0bff, 0xc01c, 0x21, 0 + .dw 0x0c40, 0xc01c, 0x0c7f, 0xc01c, 0x21, 0 + .dw 0x0cc0, 0xc01c, 0x0cff, 0xc01c, 0x21, 0 + .dw 0x0d40, 0xc01c, 0x0d7f, 0xc01c, 0x21, 0 + .dw 0x0dc0, 0xc01c, 0x0dff, 0xc01c, 0x21, 0 + .dw 0x0e40, 0xc01c, 0x0e7f, 0xc01c, 0x21, 0 + .dw 0x0ec0, 0xc01c, 0x0eff, 0xc01c, 0x21, 0 + .dw 0x0f40, 0xc01c, 0x0f7f, 0xc01c, 0x21, 0 + .dw 0x0fc0, 0xc01c, 0x0fff, 0xc01c, 0x21, 0 + .dw 0x1040, 0xc01c, 0x107f, 0xc01c, 0x21, 0 + .dw 0x10c0, 0xc01c, 0x10ff, 0xc01c, 0x21, 0 + .dw 0x1140, 0xc01c, 0x117f, 0xc01c, 0x21, 0 + .dw 0x11c0, 0xc01c, 0x11ff, 0xc01c, 0x21, 0 + .dw 0x1240, 0xc01c, 0x127f, 0xc01c, 0x21, 0 + .dw 0x12c0, 0xc01c, 0x12ff, 0xc01c, 0x21, 0 + .dw 0x1340, 0xc01c, 0x137f, 0xc01c, 0x21, 0 + .dw 0x13c0, 0xc01c, 0x13ff, 0xc01c, 0x21, 0 + .dw 0x1440, 0xc01c, 0x147f, 0xc01c, 0x21, 0 + .dw 0x14c0, 0xc01c, 0x14ff, 0xc01c, 0x21, 0 + .dw 0x1540, 0xc01c, 0x157f, 0xc01c, 0x21, 0 + .dw 0x15c0, 0xc01c, 0x15ff, 0xc01c, 0x21, 0 + .dw 0x1640, 0xc01c, 0x167f, 0xc01c, 0x21, 0 + .dw 0x16c0, 0xc01c, 0x16ff, 0xc01c, 0x21, 0 + .dw 0x1740, 0xc01c, 0x177f, 0xc01c, 0x21, 0 + .dw 0x17c0, 0xc01c, 0x17ff, 0xc01c, 0x21, 0 + .dw 0x1840, 0xc01c, 0x187f, 0xc01c, 0x21, 0 + .dw 0x18c0, 0xc01c, 0x18ff, 0xc01c, 0x21, 0 + .dw 0x1940, 0xc01c, 0x197f, 0xc01c, 0x21, 0 + .dw 0x19c0, 0xc01c, 0x1fff, 0xc01c, 0x21, 0 + .dw 0x2040, 0xc01c, 0x207f, 0xc01c, 0x21, 0 + .dw 0x20c0, 0xc01c, 0x20ff, 0xc01c, 0x21, 0 + .dw 0x2140, 0xc01c, 0x217f, 0xc01c, 0x21, 0 + .dw 0x21c0, 0xc01c, 0x21ff, 0xc01c, 0x21, 0 + .dw 0x2240, 0xc01c, 0x227f, 0xc01c, 0x21, 0 + .dw 0x22c0, 0xc01c, 0x22ff, 0xc01c, 0x21, 0 + .dw 0x2340, 0xc01c, 0x237f, 0xc01c, 0x21, 0 + .dw 0x23c0, 0xc01c, 0x23ff, 0xc01c, 0x21, 0 + .dw 0x2440, 0xc01c, 0x247f, 0xc01c, 0x21, 0 + .dw 0x24c0, 0xc01c, 0x24ff, 0xc01c, 0x21, 0 + .dw 0x2540, 0xc01c, 0x257f, 0xc01c, 0x21, 0 + .dw 0x25c0, 0xc01c, 0x25ff, 0xc01c, 0x21, 0 + .dw 0x2640, 0xc01c, 0x267f, 0xc01c, 0x21, 0 + .dw 0x26c0, 0xc01c, 0x26ff, 0xc01c, 0x21, 0 + .dw 0x2740, 0xc01c, 0x277f, 0xc01c, 0x21, 0 + .dw 0x27c0, 0xc01c, 0x27ff, 0xc01c, 0x21, 0 + .dw 0x2840, 0xc01c, 0x287f, 0xc01c, 0x21, 0 + .dw 0x28c0, 0xc01c, 0x28ff, 0xc01c, 0x21, 0 + .dw 0x2940, 0xc01c, 0x297f, 0xc01c, 0x21, 0 + .dw 0x29c0, 0xc01c, 0x29ff, 0xc01c, 0x21, 0 + .dw 0x2a40, 0xc01c, 0x2a7f, 0xc01c, 0x21, 0 + .dw 0x2ac0, 0xc01c, 0x2aff, 0xc01c, 0x21, 0 + .dw 0x2b40, 0xc01c, 0x2b7f, 0xc01c, 0x21, 0 + .dw 0x2bc0, 0xc01c, 0x2bff, 0xc01c, 0x21, 0 + .dw 0x2c40, 0xc01c, 0x2c7f, 0xc01c, 0x21, 0 + .dw 0x2cc0, 0xc01c, 0x2cff, 0xc01c, 0x21, 0 + .dw 0x2d40, 0xc01c, 0x2d7f, 0xc01c, 0x21, 0 + .dw 0x2dc0, 0xc01c, 0x2dff, 0xc01c, 0x21, 0 + .dw 0x2e40, 0xc01c, 0x2e7f, 0xc01c, 0x21, 0 + .dw 0x2ec0, 0xc01c, 0x2eff, 0xc01c, 0x21, 0 + .dw 0x2f40, 0xc01c, 0x2f7f, 0xc01c, 0x21, 0 + .dw 0x2fc0, 0xc01c, 0x2fff, 0xc01c, 0x21, 0 + .dw 0x3040, 0xc01c, 0x307f, 0xc01c, 0x21, 0 + .dw 0x30c0, 0xc01c, 0x30ff, 0xc01c, 0x21, 0 + .dw 0x3140, 0xc01c, 0x317f, 0xc01c, 0x21, 0 + .dw 0x31c0, 0xc01c, 0x31ff, 0xc01c, 0x21, 0 + .dw 0x3240, 0xc01c, 0x327f, 0xc01c, 0x21, 0 + .dw 0x32c0, 0xc01c, 0x32ff, 0xc01c, 0x21, 0 + .dw 0x3340, 0xc01c, 0x337f, 0xc01c, 0x21, 0 + .dw 0x33c0, 0xc01c, 0x33ff, 0xc01c, 0x21, 0 + .dw 0x3440, 0xc01c, 0x347f, 0xc01c, 0x21, 0 + .dw 0x34c0, 0xc01c, 0x34ff, 0xc01c, 0x21, 0 + .dw 0x3540, 0xc01c, 0x357f, 0xc01c, 0x21, 0 + .dw 0x35c0, 0xc01c, 0x35ff, 0xc01c, 0x21, 0 + .dw 0x3640, 0xc01c, 0x367f, 0xc01c, 0x21, 0 + .dw 0x36c0, 0xc01c, 0x36ff, 0xc01c, 0x21, 0 + .dw 0x3740, 0xc01c, 0x377f, 0xc01c, 0x21, 0 + .dw 0x37c0, 0xc01c, 0x37ff, 0xc01c, 0x21, 0 + .dw 0x3840, 0xc01c, 0x387f, 0xc01c, 0x21, 0 + .dw 0x38c0, 0xc01c, 0x38ff, 0xc01c, 0x21, 0 + .dw 0x3940, 0xc01c, 0x397f, 0xc01c, 0x21, 0 + .dw 0x39c0, 0xc01c, 0x3fff, 0xc01c, 0x21, 0 + .dw 0x4040, 0xc01c, 0x407f, 0xc01c, 0x21, 0 + .dw 0x40c0, 0xc01c, 0x40ff, 0xc01c, 0x21, 0 + .dw 0x4140, 0xc01c, 0x417f, 0xc01c, 0x21, 0 + .dw 0x41c0, 0xc01c, 0x41ff, 0xc01c, 0x21, 0 + .dw 0x4240, 0xc01c, 0x427f, 0xc01c, 0x21, 0 + .dw 0x42c0, 0xc01c, 0x42ff, 0xc01c, 0x21, 0 + .dw 0x4340, 0xc01c, 0x437f, 0xc01c, 0x21, 0 + .dw 0x43c0, 0xc01c, 0x43ff, 0xc01c, 0x21, 0 + .dw 0x4440, 0xc01c, 0x447f, 0xc01c, 0x21, 0 + .dw 0x44c0, 0xc01c, 0x44ff, 0xc01c, 0x21, 0 + .dw 0x4540, 0xc01c, 0x457f, 0xc01c, 0x21, 0 + .dw 0x45c0, 0xc01c, 0x45ff, 0xc01c, 0x21, 0 + .dw 0x4640, 0xc01c, 0x467f, 0xc01c, 0x21, 0 + .dw 0x46c0, 0xc01c, 0x46ff, 0xc01c, 0x21, 0 + .dw 0x4740, 0xc01c, 0x477f, 0xc01c, 0x21, 0 + .dw 0x47c0, 0xc01c, 0x47ff, 0xc01c, 0x21, 0 + .dw 0x4840, 0xc01c, 0x487f, 0xc01c, 0x21, 0 + .dw 0x48c0, 0xc01c, 0x48ff, 0xc01c, 0x21, 0 + .dw 0x4940, 0xc01c, 0x497f, 0xc01c, 0x21, 0 + .dw 0x49c0, 0xc01c, 0x49ff, 0xc01c, 0x21, 0 + .dw 0x4a40, 0xc01c, 0x4a7f, 0xc01c, 0x21, 0 + .dw 0x4ac0, 0xc01c, 0x4aff, 0xc01c, 0x21, 0 + .dw 0x4b40, 0xc01c, 0x4b7f, 0xc01c, 0x21, 0 + .dw 0x4bc0, 0xc01c, 0x4bff, 0xc01c, 0x21, 0 + .dw 0x4c40, 0xc01c, 0x4c7f, 0xc01c, 0x21, 0 + .dw 0x4cc0, 0xc01c, 0x4cff, 0xc01c, 0x21, 0 + .dw 0x4d40, 0xc01c, 0x4d7f, 0xc01c, 0x21, 0 + .dw 0x4dc0, 0xc01c, 0x4dff, 0xc01c, 0x21, 0 + .dw 0x4e40, 0xc01c, 0x4e7f, 0xc01c, 0x21, 0 + .dw 0x4ec0, 0xc01c, 0x4eff, 0xc01c, 0x21, 0 + .dw 0x4f40, 0xc01c, 0x4f7f, 0xc01c, 0x21, 0 + .dw 0x4fc0, 0xc01c, 0x4fff, 0xc01c, 0x21, 0 + .dw 0x5040, 0xc01c, 0x507f, 0xc01c, 0x21, 0 + .dw 0x50c0, 0xc01c, 0x50ff, 0xc01c, 0x21, 0 + .dw 0x5140, 0xc01c, 0x517f, 0xc01c, 0x21, 0 + .dw 0x51c0, 0xc01c, 0x51ff, 0xc01c, 0x21, 0 + .dw 0x5240, 0xc01c, 0x527f, 0xc01c, 0x21, 0 + .dw 0x52c0, 0xc01c, 0x52ff, 0xc01c, 0x21, 0 + .dw 0x5340, 0xc01c, 0x537f, 0xc01c, 0x21, 0 + .dw 0x53c0, 0xc01c, 0x53ff, 0xc01c, 0x21, 0 + .dw 0x5440, 0xc01c, 0x547f, 0xc01c, 0x21, 0 + .dw 0x54c0, 0xc01c, 0x54ff, 0xc01c, 0x21, 0 + .dw 0x5540, 0xc01c, 0x557f, 0xc01c, 0x21, 0 + .dw 0x55c0, 0xc01c, 0x55ff, 0xc01c, 0x21, 0 + .dw 0x5640, 0xc01c, 0x567f, 0xc01c, 0x21, 0 + .dw 0x56c0, 0xc01c, 0x56ff, 0xc01c, 0x21, 0 + .dw 0x5740, 0xc01c, 0x577f, 0xc01c, 0x21, 0 + .dw 0x57c0, 0xc01c, 0x57ff, 0xc01c, 0x21, 0 + .dw 0x5840, 0xc01c, 0x587f, 0xc01c, 0x21, 0 + .dw 0x58c0, 0xc01c, 0x58ff, 0xc01c, 0x21, 0 + .dw 0x5940, 0xc01c, 0x597f, 0xc01c, 0x21, 0 + .dw 0x59c0, 0xc01c, 0x5fff, 0xc01c, 0x21, 0 + .dw 0x6040, 0xc01c, 0x607f, 0xc01c, 0x21, 0 + .dw 0x60c0, 0xc01c, 0x60ff, 0xc01c, 0x21, 0 + .dw 0x6140, 0xc01c, 0x617f, 0xc01c, 0x21, 0 + .dw 0x61c0, 0xc01c, 0x61ff, 0xc01c, 0x21, 0 + .dw 0x6240, 0xc01c, 0x627f, 0xc01c, 0x21, 0 + .dw 0x62c0, 0xc01c, 0x62ff, 0xc01c, 0x21, 0 + .dw 0x6340, 0xc01c, 0x637f, 0xc01c, 0x21, 0 + .dw 0x63c0, 0xc01c, 0x63ff, 0xc01c, 0x21, 0 + .dw 0x6440, 0xc01c, 0x647f, 0xc01c, 0x21, 0 + .dw 0x64c0, 0xc01c, 0x64ff, 0xc01c, 0x21, 0 + .dw 0x6540, 0xc01c, 0x657f, 0xc01c, 0x21, 0 + .dw 0x65c0, 0xc01c, 0x65ff, 0xc01c, 0x21, 0 + .dw 0x6640, 0xc01c, 0x667f, 0xc01c, 0x21, 0 + .dw 0x66c0, 0xc01c, 0x66ff, 0xc01c, 0x21, 0 + .dw 0x6740, 0xc01c, 0x677f, 0xc01c, 0x21, 0 + .dw 0x67c0, 0xc01c, 0x67ff, 0xc01c, 0x21, 0 + .dw 0x6840, 0xc01c, 0x687f, 0xc01c, 0x21, 0 + .dw 0x68c0, 0xc01c, 0x68ff, 0xc01c, 0x21, 0 + .dw 0x6940, 0xc01c, 0x697f, 0xc01c, 0x21, 0 + .dw 0x69c0, 0xc01c, 0x69ff, 0xc01c, 0x21, 0 + .dw 0x6a40, 0xc01c, 0x6a7f, 0xc01c, 0x21, 0 + .dw 0x6ac0, 0xc01c, 0x6aff, 0xc01c, 0x21, 0 + .dw 0x6b40, 0xc01c, 0x6b7f, 0xc01c, 0x21, 0 + .dw 0x6bc0, 0xc01c, 0x6bff, 0xc01c, 0x21, 0 + .dw 0x6c40, 0xc01c, 0x6c7f, 0xc01c, 0x21, 0 + .dw 0x6cc0, 0xc01c, 0x6cff, 0xc01c, 0x21, 0 + .dw 0x6d40, 0xc01c, 0x6d7f, 0xc01c, 0x21, 0 + .dw 0x6dc0, 0xc01c, 0x6dff, 0xc01c, 0x21, 0 + .dw 0x6e40, 0xc01c, 0x6e7f, 0xc01c, 0x21, 0 + .dw 0x6ec0, 0xc01c, 0x6eff, 0xc01c, 0x21, 0 + .dw 0x6f40, 0xc01c, 0x6f7f, 0xc01c, 0x21, 0 + .dw 0x6fc0, 0xc01c, 0x6fff, 0xc01c, 0x21, 0 + .dw 0x7040, 0xc01c, 0x707f, 0xc01c, 0x21, 0 + .dw 0x70c0, 0xc01c, 0x70ff, 0xc01c, 0x21, 0 + .dw 0x7140, 0xc01c, 0x717f, 0xc01c, 0x21, 0 + .dw 0x71c0, 0xc01c, 0x71ff, 0xc01c, 0x21, 0 + .dw 0x7240, 0xc01c, 0x727f, 0xc01c, 0x21, 0 + .dw 0x72c0, 0xc01c, 0x72ff, 0xc01c, 0x21, 0 + .dw 0x7340, 0xc01c, 0x737f, 0xc01c, 0x21, 0 + .dw 0x73c0, 0xc01c, 0x73ff, 0xc01c, 0x21, 0 + .dw 0x7440, 0xc01c, 0x747f, 0xc01c, 0x21, 0 + .dw 0x74c0, 0xc01c, 0x74ff, 0xc01c, 0x21, 0 + .dw 0x7540, 0xc01c, 0x757f, 0xc01c, 0x21, 0 + .dw 0x75c0, 0xc01c, 0x75ff, 0xc01c, 0x21, 0 + .dw 0x7640, 0xc01c, 0x767f, 0xc01c, 0x21, 0 + .dw 0x76c0, 0xc01c, 0x76ff, 0xc01c, 0x21, 0 + .dw 0x7740, 0xc01c, 0x777f, 0xc01c, 0x21, 0 + .dw 0x77c0, 0xc01c, 0x77ff, 0xc01c, 0x21, 0 + .dw 0x7840, 0xc01c, 0x787f, 0xc01c, 0x21, 0 + .dw 0x78c0, 0xc01c, 0x78ff, 0xc01c, 0x21, 0 + .dw 0x7940, 0xc01c, 0x797f, 0xc01c, 0x21, 0 + .dw 0x79c0, 0xc01c, 0x7fff, 0xc01c, 0x21, 0 + .dw 0x8040, 0xc01c, 0x807f, 0xc01c, 0x21, 0 + .dw 0x80c0, 0xc01c, 0x80ff, 0xc01c, 0x21, 0 + .dw 0x8140, 0xc01c, 0x817f, 0xc01c, 0x21, 0 + .dw 0x81c0, 0xc01c, 0x81ff, 0xc01c, 0x21, 0 + .dw 0x8240, 0xc01c, 0x827f, 0xc01c, 0x21, 0 + .dw 0x82c0, 0xc01c, 0x82ff, 0xc01c, 0x21, 0 + .dw 0x8340, 0xc01c, 0x837f, 0xc01c, 0x21, 0 + .dw 0x83c0, 0xc01c, 0x83ff, 0xc01c, 0x21, 0 + .dw 0x8440, 0xc01c, 0x847f, 0xc01c, 0x21, 0 + .dw 0x84c0, 0xc01c, 0x84ff, 0xc01c, 0x21, 0 + .dw 0x8540, 0xc01c, 0x857f, 0xc01c, 0x21, 0 + .dw 0x85c0, 0xc01c, 0x85ff, 0xc01c, 0x21, 0 + .dw 0x8640, 0xc01c, 0x867f, 0xc01c, 0x21, 0 + .dw 0x86c0, 0xc01c, 0x86ff, 0xc01c, 0x21, 0 + .dw 0x8740, 0xc01c, 0x877f, 0xc01c, 0x21, 0 + .dw 0x87c0, 0xc01c, 0x87ff, 0xc01c, 0x21, 0 + .dw 0x8840, 0xc01c, 0x887f, 0xc01c, 0x21, 0 + .dw 0x88c0, 0xc01c, 0x88ff, 0xc01c, 0x21, 0 + .dw 0x8940, 0xc01c, 0x897f, 0xc01c, 0x21, 0 + .dw 0x89c0, 0xc01c, 0x89ff, 0xc01c, 0x21, 0 + .dw 0x8a40, 0xc01c, 0x8a7f, 0xc01c, 0x21, 0 + .dw 0x8ac0, 0xc01c, 0x8aff, 0xc01c, 0x21, 0 + .dw 0x8b40, 0xc01c, 0x8b7f, 0xc01c, 0x21, 0 + .dw 0x8bc0, 0xc01c, 0x8bff, 0xc01c, 0x21, 0 + .dw 0x8c40, 0xc01c, 0x8c7f, 0xc01c, 0x21, 0 + .dw 0x8cc0, 0xc01c, 0x8cff, 0xc01c, 0x21, 0 + .dw 0x8d40, 0xc01c, 0x8d7f, 0xc01c, 0x21, 0 + .dw 0x8dc0, 0xc01c, 0x8dff, 0xc01c, 0x21, 0 + .dw 0x8e40, 0xc01c, 0x8e7f, 0xc01c, 0x21, 0 + .dw 0x8ec0, 0xc01c, 0x8eff, 0xc01c, 0x21, 0 + .dw 0x8f40, 0xc01c, 0x8f7f, 0xc01c, 0x21, 0 + .dw 0x8fc0, 0xc01c, 0x8fff, 0xc01c, 0x21, 0 + .dw 0x9040, 0xc01c, 0x907f, 0xc01c, 0x21, 0 + .dw 0x90c0, 0xc01c, 0x90ff, 0xc01c, 0x21, 0 + .dw 0x9140, 0xc01c, 0x917f, 0xc01c, 0x21, 0 + .dw 0x91c0, 0xc01c, 0x91ff, 0xc01c, 0x21, 0 + .dw 0x9240, 0xc01c, 0x927f, 0xc01c, 0x21, 0 + .dw 0x92c0, 0xc01c, 0x92ff, 0xc01c, 0x21, 0 + .dw 0x9340, 0xc01c, 0x937f, 0xc01c, 0x21, 0 + .dw 0x93c0, 0xc01c, 0x93ff, 0xc01c, 0x21, 0 + .dw 0x9440, 0xc01c, 0x947f, 0xc01c, 0x21, 0 + .dw 0x94c0, 0xc01c, 0x94ff, 0xc01c, 0x21, 0 + .dw 0x9540, 0xc01c, 0x957f, 0xc01c, 0x21, 0 + .dw 0x95c0, 0xc01c, 0x95ff, 0xc01c, 0x21, 0 + .dw 0x9640, 0xc01c, 0x967f, 0xc01c, 0x21, 0 + .dw 0x96c0, 0xc01c, 0x96ff, 0xc01c, 0x21, 0 + .dw 0x9740, 0xc01c, 0x977f, 0xc01c, 0x21, 0 + .dw 0x97c0, 0xc01c, 0x97ff, 0xc01c, 0x21, 0 + .dw 0x9840, 0xc01c, 0x987f, 0xc01c, 0x21, 0 + .dw 0x98c0, 0xc01c, 0x98ff, 0xc01c, 0x21, 0 + .dw 0x9940, 0xc01c, 0x997f, 0xc01c, 0x21, 0 + .dw 0x99c0, 0xc01c, 0x9fff, 0xc01c, 0x21, 0 + .dw 0xa040, 0xc01c, 0xa07f, 0xc01c, 0x21, 0 + .dw 0xa0c0, 0xc01c, 0xa0ff, 0xc01c, 0x21, 0 + .dw 0xa140, 0xc01c, 0xa17f, 0xc01c, 0x21, 0 + .dw 0xa1c0, 0xc01c, 0xa1ff, 0xc01c, 0x21, 0 + .dw 0xa240, 0xc01c, 0xa27f, 0xc01c, 0x21, 0 + .dw 0xa2c0, 0xc01c, 0xa2ff, 0xc01c, 0x21, 0 + .dw 0xa340, 0xc01c, 0xa37f, 0xc01c, 0x21, 0 + .dw 0xa3c0, 0xc01c, 0xa3ff, 0xc01c, 0x21, 0 + .dw 0xa440, 0xc01c, 0xa47f, 0xc01c, 0x21, 0 + .dw 0xa4c0, 0xc01c, 0xa4ff, 0xc01c, 0x21, 0 + .dw 0xa540, 0xc01c, 0xa57f, 0xc01c, 0x21, 0 + .dw 0xa5c0, 0xc01c, 0xa5ff, 0xc01c, 0x21, 0 + .dw 0xa640, 0xc01c, 0xa67f, 0xc01c, 0x21, 0 + .dw 0xa6c0, 0xc01c, 0xa6ff, 0xc01c, 0x21, 0 + .dw 0xa740, 0xc01c, 0xa77f, 0xc01c, 0x21, 0 + .dw 0xa7c0, 0xc01c, 0xa7ff, 0xc01c, 0x21, 0 + .dw 0xa840, 0xc01c, 0xa87f, 0xc01c, 0x21, 0 + .dw 0xa8c0, 0xc01c, 0xa8ff, 0xc01c, 0x21, 0 + .dw 0xa940, 0xc01c, 0xa97f, 0xc01c, 0x21, 0 + .dw 0xa9c0, 0xc01c, 0xa9ff, 0xc01c, 0x21, 0 + .dw 0xaa40, 0xc01c, 0xaa7f, 0xc01c, 0x21, 0 + .dw 0xaac0, 0xc01c, 0xaaff, 0xc01c, 0x21, 0 + .dw 0xab40, 0xc01c, 0xab7f, 0xc01c, 0x21, 0 + .dw 0xabc0, 0xc01c, 0xabff, 0xc01c, 0x21, 0 + .dw 0xac40, 0xc01c, 0xac7f, 0xc01c, 0x21, 0 + .dw 0xacc0, 0xc01c, 0xacff, 0xc01c, 0x21, 0 + .dw 0xad40, 0xc01c, 0xad7f, 0xc01c, 0x21, 0 + .dw 0xadc0, 0xc01c, 0xadff, 0xc01c, 0x21, 0 + .dw 0xae40, 0xc01c, 0xae7f, 0xc01c, 0x21, 0 + .dw 0xaec0, 0xc01c, 0xaeff, 0xc01c, 0x21, 0 + .dw 0xaf40, 0xc01c, 0xaf7f, 0xc01c, 0x21, 0 + .dw 0xafc0, 0xc01c, 0xafff, 0xc01c, 0x21, 0 + .dw 0xb040, 0xc01c, 0xb07f, 0xc01c, 0x21, 0 + .dw 0xb0c0, 0xc01c, 0xb0ff, 0xc01c, 0x21, 0 + .dw 0xb140, 0xc01c, 0xb17f, 0xc01c, 0x21, 0 + .dw 0xb1c0, 0xc01c, 0xb1ff, 0xc01c, 0x21, 0 + .dw 0xb240, 0xc01c, 0xb27f, 0xc01c, 0x21, 0 + .dw 0xb2c0, 0xc01c, 0xb2ff, 0xc01c, 0x21, 0 + .dw 0xb340, 0xc01c, 0xb37f, 0xc01c, 0x21, 0 + .dw 0xb3c0, 0xc01c, 0xb3ff, 0xc01c, 0x21, 0 + .dw 0xb440, 0xc01c, 0xb47f, 0xc01c, 0x21, 0 + .dw 0xb4c0, 0xc01c, 0xb4ff, 0xc01c, 0x21, 0 + .dw 0xb540, 0xc01c, 0xb57f, 0xc01c, 0x21, 0 + .dw 0xb5c0, 0xc01c, 0xb5ff, 0xc01c, 0x21, 0 + .dw 0xb640, 0xc01c, 0xb67f, 0xc01c, 0x21, 0 + .dw 0xb6c0, 0xc01c, 0xb6ff, 0xc01c, 0x21, 0 + .dw 0xb740, 0xc01c, 0xb77f, 0xc01c, 0x21, 0 + .dw 0xb7c0, 0xc01c, 0xb7ff, 0xc01c, 0x21, 0 + .dw 0xb840, 0xc01c, 0xb87f, 0xc01c, 0x21, 0 + .dw 0xb8c0, 0xc01c, 0xb8ff, 0xc01c, 0x21, 0 + .dw 0xb940, 0xc01c, 0xb97f, 0xc01c, 0x21, 0 + .dw 0xb9c0, 0xc01c, 0xbfff, 0xc01c, 0x21, 0 + .dw 0xc040, 0xc01c, 0xc07f, 0xc01c, 0x21, 0 + .dw 0xc0c0, 0xc01c, 0xc0ff, 0xc01c, 0x21, 0 + .dw 0xc140, 0xc01c, 0xc17f, 0xc01c, 0x21, 0 + .dw 0xc1c0, 0xc01c, 0xc1ff, 0xc01c, 0x21, 0 + .dw 0xc240, 0xc01c, 0xc27f, 0xc01c, 0x21, 0 + .dw 0xc2c0, 0xc01c, 0xc2ff, 0xc01c, 0x21, 0 + .dw 0xc340, 0xc01c, 0xc37f, 0xc01c, 0x21, 0 + .dw 0xc3c0, 0xc01c, 0xc3ff, 0xc01c, 0x21, 0 + .dw 0xc440, 0xc01c, 0xc47f, 0xc01c, 0x21, 0 + .dw 0xc4c0, 0xc01c, 0xc4ff, 0xc01c, 0x21, 0 + .dw 0xc540, 0xc01c, 0xc57f, 0xc01c, 0x21, 0 + .dw 0xc5c0, 0xc01c, 0xc5ff, 0xc01c, 0x21, 0 + .dw 0xc640, 0xc01c, 0xc67f, 0xc01c, 0x21, 0 + .dw 0xc6c0, 0xc01c, 0xc6ff, 0xc01c, 0x21, 0 + .dw 0xc740, 0xc01c, 0xc77f, 0xc01c, 0x21, 0 + .dw 0xc7c0, 0xc01c, 0xc7ff, 0xc01c, 0x21, 0 + .dw 0xc840, 0xc01c, 0xc87f, 0xc01c, 0x21, 0 + .dw 0xc8c0, 0xc01c, 0xc8ff, 0xc01c, 0x21, 0 + .dw 0xc940, 0xc01c, 0xc97f, 0xc01c, 0x21, 0 + .dw 0xc9c0, 0xc01c, 0xc9ff, 0xc01c, 0x21, 0 + .dw 0xca40, 0xc01c, 0xca7f, 0xc01c, 0x21, 0 + .dw 0xcac0, 0xc01c, 0xcaff, 0xc01c, 0x21, 0 + .dw 0xcb40, 0xc01c, 0xcb7f, 0xc01c, 0x21, 0 + .dw 0xcbc0, 0xc01c, 0xcbff, 0xc01c, 0x21, 0 + .dw 0xcc40, 0xc01c, 0xcc7f, 0xc01c, 0x21, 0 + .dw 0xccc0, 0xc01c, 0xccff, 0xc01c, 0x21, 0 + .dw 0xcd40, 0xc01c, 0xcd7f, 0xc01c, 0x21, 0 + .dw 0xcdc0, 0xc01c, 0xcdff, 0xc01c, 0x21, 0 + .dw 0xce40, 0xc01c, 0xce7f, 0xc01c, 0x21, 0 + .dw 0xcec0, 0xc01c, 0xceff, 0xc01c, 0x21, 0 + .dw 0xcf40, 0xc01c, 0xcf7f, 0xc01c, 0x21, 0 + .dw 0xcfc0, 0xc01c, 0xcfff, 0xc01c, 0x21, 0 + .dw 0xd040, 0xc01c, 0xd07f, 0xc01c, 0x21, 0 + .dw 0xd0c0, 0xc01c, 0xd0ff, 0xc01c, 0x21, 0 + .dw 0xd140, 0xc01c, 0xd17f, 0xc01c, 0x21, 0 + .dw 0xd1c0, 0xc01c, 0xd1ff, 0xc01c, 0x21, 0 + .dw 0xd240, 0xc01c, 0xd27f, 0xc01c, 0x21, 0 + .dw 0xd2c0, 0xc01c, 0xd2ff, 0xc01c, 0x21, 0 + .dw 0xd340, 0xc01c, 0xd37f, 0xc01c, 0x21, 0 + .dw 0xd3c0, 0xc01c, 0xd3ff, 0xc01c, 0x21, 0 + .dw 0xd440, 0xc01c, 0xd47f, 0xc01c, 0x21, 0 + .dw 0xd4c0, 0xc01c, 0xd4ff, 0xc01c, 0x21, 0 + .dw 0xd540, 0xc01c, 0xd57f, 0xc01c, 0x21, 0 + .dw 0xd5c0, 0xc01c, 0xd5ff, 0xc01c, 0x21, 0 + .dw 0xd640, 0xc01c, 0xd67f, 0xc01c, 0x21, 0 + .dw 0xd6c0, 0xc01c, 0xd6ff, 0xc01c, 0x21, 0 + .dw 0xd740, 0xc01c, 0xd77f, 0xc01c, 0x21, 0 + .dw 0xd7c0, 0xc01c, 0xd7ff, 0xc01c, 0x21, 0 + .dw 0xd840, 0xc01c, 0xd87f, 0xc01c, 0x21, 0 + .dw 0xd8c0, 0xc01c, 0xd8ff, 0xc01c, 0x21, 0 + .dw 0xd940, 0xc01c, 0xd97f, 0xc01c, 0x21, 0 + .dw 0xd9c0, 0xc01c, 0xdfff, 0xc01c, 0x21, 0 + .dw 0xe040, 0xc01c, 0xe07f, 0xc01c, 0x21, 0 + .dw 0xe0c0, 0xc01c, 0xe0ff, 0xc01c, 0x21, 0 + .dw 0xe140, 0xc01c, 0xe17f, 0xc01c, 0x21, 0 + .dw 0xe1c0, 0xc01c, 0xe1ff, 0xc01c, 0x21, 0 + .dw 0xe240, 0xc01c, 0xe27f, 0xc01c, 0x21, 0 + .dw 0xe2c0, 0xc01c, 0xe2ff, 0xc01c, 0x21, 0 + .dw 0xe340, 0xc01c, 0xe37f, 0xc01c, 0x21, 0 + .dw 0xe3c0, 0xc01c, 0xe3ff, 0xc01c, 0x21, 0 + .dw 0xe440, 0xc01c, 0xe47f, 0xc01c, 0x21, 0 + .dw 0xe4c0, 0xc01c, 0xe4ff, 0xc01c, 0x21, 0 + .dw 0xe540, 0xc01c, 0xe57f, 0xc01c, 0x21, 0 + .dw 0xe5c0, 0xc01c, 0xe5ff, 0xc01c, 0x21, 0 + .dw 0xe640, 0xc01c, 0xe67f, 0xc01c, 0x21, 0 + .dw 0xe6c0, 0xc01c, 0xe6ff, 0xc01c, 0x21, 0 + .dw 0xe740, 0xc01c, 0xe77f, 0xc01c, 0x21, 0 + .dw 0xe7c0, 0xc01c, 0xe7ff, 0xc01c, 0x21, 0 + .dw 0xe840, 0xc01c, 0xe87f, 0xc01c, 0x21, 0 + .dw 0xe8c0, 0xc01c, 0xe8ff, 0xc01c, 0x21, 0 + .dw 0xe940, 0xc01c, 0xe97f, 0xc01c, 0x21, 0 + .dw 0xe9c0, 0xc01c, 0xe9ff, 0xc01c, 0x21, 0 + .dw 0xea40, 0xc01c, 0xea7f, 0xc01c, 0x21, 0 + .dw 0xeac0, 0xc01c, 0xeaff, 0xc01c, 0x21, 0 + .dw 0xeb40, 0xc01c, 0xeb7f, 0xc01c, 0x21, 0 + .dw 0xebc0, 0xc01c, 0xebff, 0xc01c, 0x21, 0 + .dw 0xec40, 0xc01c, 0xec7f, 0xc01c, 0x21, 0 + .dw 0xecc0, 0xc01c, 0xecff, 0xc01c, 0x21, 0 + .dw 0xed40, 0xc01c, 0xed7f, 0xc01c, 0x21, 0 + .dw 0xedc0, 0xc01c, 0xedff, 0xc01c, 0x21, 0 + .dw 0xee40, 0xc01c, 0xee7f, 0xc01c, 0x21, 0 + .dw 0xeec0, 0xc01c, 0xeeff, 0xc01c, 0x21, 0 + .dw 0xef40, 0xc01c, 0xef7f, 0xc01c, 0x21, 0 + .dw 0xefc0, 0xc01c, 0xefff, 0xc01c, 0x21, 0 + .dw 0xf040, 0xc01c, 0xf07f, 0xc01c, 0x21, 0 + .dw 0xf0c0, 0xc01c, 0xf0ff, 0xc01c, 0x21, 0 + .dw 0xf140, 0xc01c, 0xf17f, 0xc01c, 0x21, 0 + .dw 0xf1c0, 0xc01c, 0xf1ff, 0xc01c, 0x21, 0 + .dw 0xf240, 0xc01c, 0xf27f, 0xc01c, 0x21, 0 + .dw 0xf2c0, 0xc01c, 0xf2ff, 0xc01c, 0x21, 0 + .dw 0xf340, 0xc01c, 0xf37f, 0xc01c, 0x21, 0 + .dw 0xf3c0, 0xc01c, 0xf3ff, 0xc01c, 0x21, 0 + .dw 0xf440, 0xc01c, 0xf47f, 0xc01c, 0x21, 0 + .dw 0xf4c0, 0xc01c, 0xf4ff, 0xc01c, 0x21, 0 + .dw 0xf540, 0xc01c, 0xf57f, 0xc01c, 0x21, 0 + .dw 0xf5c0, 0xc01c, 0xf5ff, 0xc01c, 0x21, 0 + .dw 0xf640, 0xc01c, 0xf67f, 0xc01c, 0x21, 0 + .dw 0xf6c0, 0xc01c, 0xf6ff, 0xc01c, 0x21, 0 + .dw 0xf740, 0xc01c, 0xf77f, 0xc01c, 0x21, 0 + .dw 0xf7c0, 0xc01c, 0xf7ff, 0xc01c, 0x21, 0 + .dw 0xf840, 0xc01c, 0xf87f, 0xc01c, 0x21, 0 + .dw 0xf8c0, 0xc01c, 0xf8ff, 0xc01c, 0x21, 0 + .dw 0xf940, 0xc01c, 0xf97f, 0xc01c, 0x21, 0 + .dw 0xf9c0, 0xc01c, 0xffff, 0xc01c, 0x21, 0 + .dw 0x0040, 0xc01d, 0x007f, 0xc01d, 0x21, 0 + .dw 0x00c0, 0xc01d, 0x00ff, 0xc01d, 0x21, 0 + .dw 0x0140, 0xc01d, 0x017f, 0xc01d, 0x21, 0 + .dw 0x01c0, 0xc01d, 0x01ff, 0xc01d, 0x21, 0 + .dw 0x0240, 0xc01d, 0x027f, 0xc01d, 0x21, 0 + .dw 0x02c0, 0xc01d, 0x02ff, 0xc01d, 0x21, 0 + .dw 0x0340, 0xc01d, 0x037f, 0xc01d, 0x21, 0 + .dw 0x03c0, 0xc01d, 0x03ff, 0xc01d, 0x21, 0 + .dw 0x0440, 0xc01d, 0x047f, 0xc01d, 0x21, 0 + .dw 0x04c0, 0xc01d, 0x04ff, 0xc01d, 0x21, 0 + .dw 0x0540, 0xc01d, 0x057f, 0xc01d, 0x21, 0 + .dw 0x05c0, 0xc01d, 0x05ff, 0xc01d, 0x21, 0 + .dw 0x0640, 0xc01d, 0x067f, 0xc01d, 0x21, 0 + .dw 0x06c0, 0xc01d, 0x06ff, 0xc01d, 0x21, 0 + .dw 0x0740, 0xc01d, 0x077f, 0xc01d, 0x21, 0 + .dw 0x07c0, 0xc01d, 0x07ff, 0xc01d, 0x21, 0 + .dw 0x0840, 0xc01d, 0x087f, 0xc01d, 0x21, 0 + .dw 0x08c0, 0xc01d, 0x08ff, 0xc01d, 0x21, 0 + .dw 0x0940, 0xc01d, 0x097f, 0xc01d, 0x21, 0 + .dw 0x09c0, 0xc01d, 0x09ff, 0xc01d, 0x21, 0 + .dw 0x0a40, 0xc01d, 0x0a7f, 0xc01d, 0x21, 0 + .dw 0x0ac0, 0xc01d, 0x0aff, 0xc01d, 0x21, 0 + .dw 0x0b40, 0xc01d, 0x0b7f, 0xc01d, 0x21, 0 + .dw 0x0bc0, 0xc01d, 0x0bff, 0xc01d, 0x21, 0 + .dw 0x0c40, 0xc01d, 0x0c7f, 0xc01d, 0x21, 0 + .dw 0x0cc0, 0xc01d, 0x0cff, 0xc01d, 0x21, 0 + .dw 0x0d40, 0xc01d, 0x0d7f, 0xc01d, 0x21, 0 + .dw 0x0dc0, 0xc01d, 0x0dff, 0xc01d, 0x21, 0 + .dw 0x0e40, 0xc01d, 0x0e7f, 0xc01d, 0x21, 0 + .dw 0x0ec0, 0xc01d, 0x0eff, 0xc01d, 0x21, 0 + .dw 0x0f40, 0xc01d, 0x0f7f, 0xc01d, 0x21, 0 + .dw 0x0fc0, 0xc01d, 0x0fff, 0xc01d, 0x21, 0 + .dw 0x1040, 0xc01d, 0x107f, 0xc01d, 0x21, 0 + .dw 0x10c0, 0xc01d, 0x10ff, 0xc01d, 0x21, 0 + .dw 0x1140, 0xc01d, 0x117f, 0xc01d, 0x21, 0 + .dw 0x11c0, 0xc01d, 0x11ff, 0xc01d, 0x21, 0 + .dw 0x1240, 0xc01d, 0x127f, 0xc01d, 0x21, 0 + .dw 0x12c0, 0xc01d, 0x12ff, 0xc01d, 0x21, 0 + .dw 0x1340, 0xc01d, 0x137f, 0xc01d, 0x21, 0 + .dw 0x13c0, 0xc01d, 0x13ff, 0xc01d, 0x21, 0 + .dw 0x1440, 0xc01d, 0x147f, 0xc01d, 0x21, 0 + .dw 0x14c0, 0xc01d, 0x14ff, 0xc01d, 0x21, 0 + .dw 0x1540, 0xc01d, 0x157f, 0xc01d, 0x21, 0 + .dw 0x15c0, 0xc01d, 0x15ff, 0xc01d, 0x21, 0 + .dw 0x1640, 0xc01d, 0x167f, 0xc01d, 0x21, 0 + .dw 0x16c0, 0xc01d, 0x16ff, 0xc01d, 0x21, 0 + .dw 0x1740, 0xc01d, 0x177f, 0xc01d, 0x21, 0 + .dw 0x17c0, 0xc01d, 0x17ff, 0xc01d, 0x21, 0 + .dw 0x1840, 0xc01d, 0x187f, 0xc01d, 0x21, 0 + .dw 0x18c0, 0xc01d, 0x18ff, 0xc01d, 0x21, 0 + .dw 0x1940, 0xc01d, 0x197f, 0xc01d, 0x21, 0 + .dw 0x19c0, 0xc01d, 0x1fff, 0xc01d, 0x21, 0 + .dw 0x2040, 0xc01d, 0x207f, 0xc01d, 0x21, 0 + .dw 0x20c0, 0xc01d, 0x20ff, 0xc01d, 0x21, 0 + .dw 0x2140, 0xc01d, 0x217f, 0xc01d, 0x21, 0 + .dw 0x21c0, 0xc01d, 0x21ff, 0xc01d, 0x21, 0 + .dw 0x2240, 0xc01d, 0x227f, 0xc01d, 0x21, 0 + .dw 0x22c0, 0xc01d, 0x22ff, 0xc01d, 0x21, 0 + .dw 0x2340, 0xc01d, 0x237f, 0xc01d, 0x21, 0 + .dw 0x23c0, 0xc01d, 0x23ff, 0xc01d, 0x21, 0 + .dw 0x2440, 0xc01d, 0x247f, 0xc01d, 0x21, 0 + .dw 0x24c0, 0xc01d, 0x24ff, 0xc01d, 0x21, 0 + .dw 0x2540, 0xc01d, 0x257f, 0xc01d, 0x21, 0 + .dw 0x25c0, 0xc01d, 0x25ff, 0xc01d, 0x21, 0 + .dw 0x2640, 0xc01d, 0x267f, 0xc01d, 0x21, 0 + .dw 0x26c0, 0xc01d, 0x26ff, 0xc01d, 0x21, 0 + .dw 0x2740, 0xc01d, 0x277f, 0xc01d, 0x21, 0 + .dw 0x27c0, 0xc01d, 0x27ff, 0xc01d, 0x21, 0 + .dw 0x2840, 0xc01d, 0x287f, 0xc01d, 0x21, 0 + .dw 0x28c0, 0xc01d, 0x28ff, 0xc01d, 0x21, 0 + .dw 0x2940, 0xc01d, 0x297f, 0xc01d, 0x21, 0 + .dw 0x29c0, 0xc01d, 0x29ff, 0xc01d, 0x21, 0 + .dw 0x2a40, 0xc01d, 0x2a7f, 0xc01d, 0x21, 0 + .dw 0x2ac0, 0xc01d, 0x2aff, 0xc01d, 0x21, 0 + .dw 0x2b40, 0xc01d, 0x2b7f, 0xc01d, 0x21, 0 + .dw 0x2bc0, 0xc01d, 0x2bff, 0xc01d, 0x21, 0 + .dw 0x2c40, 0xc01d, 0x2c7f, 0xc01d, 0x21, 0 + .dw 0x2cc0, 0xc01d, 0x2cff, 0xc01d, 0x21, 0 + .dw 0x2d40, 0xc01d, 0x2d7f, 0xc01d, 0x21, 0 + .dw 0x2dc0, 0xc01d, 0x2dff, 0xc01d, 0x21, 0 + .dw 0x2e40, 0xc01d, 0x2e7f, 0xc01d, 0x21, 0 + .dw 0x2ec0, 0xc01d, 0x2eff, 0xc01d, 0x21, 0 + .dw 0x2f40, 0xc01d, 0x2f7f, 0xc01d, 0x21, 0 + .dw 0x2fc0, 0xc01d, 0x2fff, 0xc01d, 0x21, 0 + .dw 0x3040, 0xc01d, 0x307f, 0xc01d, 0x21, 0 + .dw 0x30c0, 0xc01d, 0x30ff, 0xc01d, 0x21, 0 + .dw 0x3140, 0xc01d, 0x317f, 0xc01d, 0x21, 0 + .dw 0x31c0, 0xc01d, 0x31ff, 0xc01d, 0x21, 0 + .dw 0x3240, 0xc01d, 0x327f, 0xc01d, 0x21, 0 + .dw 0x32c0, 0xc01d, 0x32ff, 0xc01d, 0x21, 0 + .dw 0x3340, 0xc01d, 0x337f, 0xc01d, 0x21, 0 + .dw 0x33c0, 0xc01d, 0x33ff, 0xc01d, 0x21, 0 + .dw 0x3440, 0xc01d, 0x347f, 0xc01d, 0x21, 0 + .dw 0x34c0, 0xc01d, 0x34ff, 0xc01d, 0x21, 0 + .dw 0x3540, 0xc01d, 0x357f, 0xc01d, 0x21, 0 + .dw 0x35c0, 0xc01d, 0x35ff, 0xc01d, 0x21, 0 + .dw 0x3640, 0xc01d, 0x367f, 0xc01d, 0x21, 0 + .dw 0x36c0, 0xc01d, 0x36ff, 0xc01d, 0x21, 0 + .dw 0x3740, 0xc01d, 0x377f, 0xc01d, 0x21, 0 + .dw 0x37c0, 0xc01d, 0x37ff, 0xc01d, 0x21, 0 + .dw 0x3840, 0xc01d, 0x387f, 0xc01d, 0x21, 0 + .dw 0x38c0, 0xc01d, 0x38ff, 0xc01d, 0x21, 0 + .dw 0x3940, 0xc01d, 0x397f, 0xc01d, 0x21, 0 + .dw 0x39c0, 0xc01d, 0x3fff, 0xc01d, 0x21, 0 + .dw 0x4040, 0xc01d, 0x407f, 0xc01d, 0x21, 0 + .dw 0x40c0, 0xc01d, 0x40ff, 0xc01d, 0x21, 0 + .dw 0x4140, 0xc01d, 0x417f, 0xc01d, 0x21, 0 + .dw 0x41c0, 0xc01d, 0x41ff, 0xc01d, 0x21, 0 + .dw 0x4240, 0xc01d, 0x427f, 0xc01d, 0x21, 0 + .dw 0x42c0, 0xc01d, 0x42ff, 0xc01d, 0x21, 0 + .dw 0x4340, 0xc01d, 0x437f, 0xc01d, 0x21, 0 + .dw 0x43c0, 0xc01d, 0x43ff, 0xc01d, 0x21, 0 + .dw 0x4440, 0xc01d, 0x447f, 0xc01d, 0x21, 0 + .dw 0x44c0, 0xc01d, 0x44ff, 0xc01d, 0x21, 0 + .dw 0x4540, 0xc01d, 0x457f, 0xc01d, 0x21, 0 + .dw 0x45c0, 0xc01d, 0x45ff, 0xc01d, 0x21, 0 + .dw 0x4640, 0xc01d, 0x467f, 0xc01d, 0x21, 0 + .dw 0x46c0, 0xc01d, 0x46ff, 0xc01d, 0x21, 0 + .dw 0x4740, 0xc01d, 0x477f, 0xc01d, 0x21, 0 + .dw 0x47c0, 0xc01d, 0x47ff, 0xc01d, 0x21, 0 + .dw 0x4840, 0xc01d, 0x487f, 0xc01d, 0x21, 0 + .dw 0x48c0, 0xc01d, 0x48ff, 0xc01d, 0x21, 0 + .dw 0x4940, 0xc01d, 0x497f, 0xc01d, 0x21, 0 + .dw 0x49c0, 0xc01d, 0x49ff, 0xc01d, 0x21, 0 + .dw 0x4a40, 0xc01d, 0x4a7f, 0xc01d, 0x21, 0 + .dw 0x4ac0, 0xc01d, 0x4aff, 0xc01d, 0x21, 0 + .dw 0x4b40, 0xc01d, 0x4b7f, 0xc01d, 0x21, 0 + .dw 0x4bc0, 0xc01d, 0x4bff, 0xc01d, 0x21, 0 + .dw 0x4c40, 0xc01d, 0x4c7f, 0xc01d, 0x21, 0 + .dw 0x4cc0, 0xc01d, 0x4cff, 0xc01d, 0x21, 0 + .dw 0x4d40, 0xc01d, 0x4d7f, 0xc01d, 0x21, 0 + .dw 0x4dc0, 0xc01d, 0x4dff, 0xc01d, 0x21, 0 + .dw 0x4e40, 0xc01d, 0x4e7f, 0xc01d, 0x21, 0 + .dw 0x4ec0, 0xc01d, 0x4eff, 0xc01d, 0x21, 0 + .dw 0x4f40, 0xc01d, 0x4f7f, 0xc01d, 0x21, 0 + .dw 0x4fc0, 0xc01d, 0x4fff, 0xc01d, 0x21, 0 + .dw 0x5040, 0xc01d, 0x507f, 0xc01d, 0x21, 0 + .dw 0x50c0, 0xc01d, 0x50ff, 0xc01d, 0x21, 0 + .dw 0x5140, 0xc01d, 0x517f, 0xc01d, 0x21, 0 + .dw 0x51c0, 0xc01d, 0x51ff, 0xc01d, 0x21, 0 + .dw 0x5240, 0xc01d, 0x527f, 0xc01d, 0x21, 0 + .dw 0x52c0, 0xc01d, 0x52ff, 0xc01d, 0x21, 0 + .dw 0x5340, 0xc01d, 0x537f, 0xc01d, 0x21, 0 + .dw 0x53c0, 0xc01d, 0x53ff, 0xc01d, 0x21, 0 + .dw 0x5440, 0xc01d, 0x547f, 0xc01d, 0x21, 0 + .dw 0x54c0, 0xc01d, 0x54ff, 0xc01d, 0x21, 0 + .dw 0x5540, 0xc01d, 0x557f, 0xc01d, 0x21, 0 + .dw 0x55c0, 0xc01d, 0x55ff, 0xc01d, 0x21, 0 + .dw 0x5640, 0xc01d, 0x567f, 0xc01d, 0x21, 0 + .dw 0x56c0, 0xc01d, 0x56ff, 0xc01d, 0x21, 0 + .dw 0x5740, 0xc01d, 0x577f, 0xc01d, 0x21, 0 + .dw 0x57c0, 0xc01d, 0x57ff, 0xc01d, 0x21, 0 + .dw 0x5840, 0xc01d, 0x587f, 0xc01d, 0x21, 0 + .dw 0x58c0, 0xc01d, 0x58ff, 0xc01d, 0x21, 0 + .dw 0x5940, 0xc01d, 0x597f, 0xc01d, 0x21, 0 + .dw 0x59c0, 0xc01d, 0x5fff, 0xc01d, 0x21, 0 + .dw 0x6040, 0xc01d, 0x607f, 0xc01d, 0x21, 0 + .dw 0x60c0, 0xc01d, 0x60ff, 0xc01d, 0x21, 0 + .dw 0x6140, 0xc01d, 0x617f, 0xc01d, 0x21, 0 + .dw 0x61c0, 0xc01d, 0x61ff, 0xc01d, 0x21, 0 + .dw 0x6240, 0xc01d, 0x627f, 0xc01d, 0x21, 0 + .dw 0x62c0, 0xc01d, 0x62ff, 0xc01d, 0x21, 0 + .dw 0x6340, 0xc01d, 0x637f, 0xc01d, 0x21, 0 + .dw 0x63c0, 0xc01d, 0x63ff, 0xc01d, 0x21, 0 + .dw 0x6440, 0xc01d, 0x647f, 0xc01d, 0x21, 0 + .dw 0x64c0, 0xc01d, 0x64ff, 0xc01d, 0x21, 0 + .dw 0x6540, 0xc01d, 0x657f, 0xc01d, 0x21, 0 + .dw 0x65c0, 0xc01d, 0x65ff, 0xc01d, 0x21, 0 + .dw 0x6640, 0xc01d, 0x667f, 0xc01d, 0x21, 0 + .dw 0x66c0, 0xc01d, 0x66ff, 0xc01d, 0x21, 0 + .dw 0x6740, 0xc01d, 0x677f, 0xc01d, 0x21, 0 + .dw 0x67c0, 0xc01d, 0x67ff, 0xc01d, 0x21, 0 + .dw 0x6840, 0xc01d, 0x687f, 0xc01d, 0x21, 0 + .dw 0x68c0, 0xc01d, 0x68ff, 0xc01d, 0x21, 0 + .dw 0x6940, 0xc01d, 0x697f, 0xc01d, 0x21, 0 + .dw 0x69c0, 0xc01d, 0x69ff, 0xc01d, 0x21, 0 + .dw 0x6a40, 0xc01d, 0x6a7f, 0xc01d, 0x21, 0 + .dw 0x6ac0, 0xc01d, 0x6aff, 0xc01d, 0x21, 0 + .dw 0x6b40, 0xc01d, 0x6b7f, 0xc01d, 0x21, 0 + .dw 0x6bc0, 0xc01d, 0x6bff, 0xc01d, 0x21, 0 + .dw 0x6c40, 0xc01d, 0x6c7f, 0xc01d, 0x21, 0 + .dw 0x6cc0, 0xc01d, 0x6cff, 0xc01d, 0x21, 0 + .dw 0x6d40, 0xc01d, 0x6d7f, 0xc01d, 0x21, 0 + .dw 0x6dc0, 0xc01d, 0x6dff, 0xc01d, 0x21, 0 + .dw 0x6e40, 0xc01d, 0x6e7f, 0xc01d, 0x21, 0 + .dw 0x6ec0, 0xc01d, 0x6eff, 0xc01d, 0x21, 0 + .dw 0x6f40, 0xc01d, 0x6f7f, 0xc01d, 0x21, 0 + .dw 0x6fc0, 0xc01d, 0x6fff, 0xc01d, 0x21, 0 + .dw 0x7040, 0xc01d, 0x707f, 0xc01d, 0x21, 0 + .dw 0x70c0, 0xc01d, 0x70ff, 0xc01d, 0x21, 0 + .dw 0x7140, 0xc01d, 0x717f, 0xc01d, 0x21, 0 + .dw 0x71c0, 0xc01d, 0x71ff, 0xc01d, 0x21, 0 + .dw 0x7240, 0xc01d, 0x727f, 0xc01d, 0x21, 0 + .dw 0x72c0, 0xc01d, 0x72ff, 0xc01d, 0x21, 0 + .dw 0x7340, 0xc01d, 0x737f, 0xc01d, 0x21, 0 + .dw 0x73c0, 0xc01d, 0x73ff, 0xc01d, 0x21, 0 + .dw 0x7440, 0xc01d, 0x747f, 0xc01d, 0x21, 0 + .dw 0x74c0, 0xc01d, 0x74ff, 0xc01d, 0x21, 0 + .dw 0x7540, 0xc01d, 0x757f, 0xc01d, 0x21, 0 + .dw 0x75c0, 0xc01d, 0x75ff, 0xc01d, 0x21, 0 + .dw 0x7640, 0xc01d, 0x767f, 0xc01d, 0x21, 0 + .dw 0x76c0, 0xc01d, 0x76ff, 0xc01d, 0x21, 0 + .dw 0x7740, 0xc01d, 0x777f, 0xc01d, 0x21, 0 + .dw 0x77c0, 0xc01d, 0x77ff, 0xc01d, 0x21, 0 + .dw 0x7840, 0xc01d, 0x787f, 0xc01d, 0x21, 0 + .dw 0x78c0, 0xc01d, 0x78ff, 0xc01d, 0x21, 0 + .dw 0x7940, 0xc01d, 0x797f, 0xc01d, 0x21, 0 + .dw 0x79c0, 0xc01d, 0x7fff, 0xc01d, 0x21, 0 + .dw 0x8040, 0xc01d, 0x807f, 0xc01d, 0x21, 0 + .dw 0x80c0, 0xc01d, 0x80ff, 0xc01d, 0x21, 0 + .dw 0x8140, 0xc01d, 0x817f, 0xc01d, 0x21, 0 + .dw 0x81c0, 0xc01d, 0x81ff, 0xc01d, 0x21, 0 + .dw 0x8240, 0xc01d, 0x827f, 0xc01d, 0x21, 0 + .dw 0x82c0, 0xc01d, 0x82ff, 0xc01d, 0x21, 0 + .dw 0x8340, 0xc01d, 0x837f, 0xc01d, 0x21, 0 + .dw 0x83c0, 0xc01d, 0x83ff, 0xc01d, 0x21, 0 + .dw 0x8440, 0xc01d, 0x847f, 0xc01d, 0x21, 0 + .dw 0x84c0, 0xc01d, 0x84ff, 0xc01d, 0x21, 0 + .dw 0x8540, 0xc01d, 0x857f, 0xc01d, 0x21, 0 + .dw 0x85c0, 0xc01d, 0x85ff, 0xc01d, 0x21, 0 + .dw 0x8640, 0xc01d, 0x867f, 0xc01d, 0x21, 0 + .dw 0x86c0, 0xc01d, 0x86ff, 0xc01d, 0x21, 0 + .dw 0x8740, 0xc01d, 0x877f, 0xc01d, 0x21, 0 + .dw 0x87c0, 0xc01d, 0x87ff, 0xc01d, 0x21, 0 + .dw 0x8840, 0xc01d, 0x887f, 0xc01d, 0x21, 0 + .dw 0x88c0, 0xc01d, 0x88ff, 0xc01d, 0x21, 0 + .dw 0x8940, 0xc01d, 0x897f, 0xc01d, 0x21, 0 + .dw 0x89c0, 0xc01d, 0x89ff, 0xc01d, 0x21, 0 + .dw 0x8a40, 0xc01d, 0x8a7f, 0xc01d, 0x21, 0 + .dw 0x8ac0, 0xc01d, 0x8aff, 0xc01d, 0x21, 0 + .dw 0x8b40, 0xc01d, 0x8b7f, 0xc01d, 0x21, 0 + .dw 0x8bc0, 0xc01d, 0x8bff, 0xc01d, 0x21, 0 + .dw 0x8c40, 0xc01d, 0x8c7f, 0xc01d, 0x21, 0 + .dw 0x8cc0, 0xc01d, 0x8cff, 0xc01d, 0x21, 0 + .dw 0x8d40, 0xc01d, 0x8d7f, 0xc01d, 0x21, 0 + .dw 0x8dc0, 0xc01d, 0x8dff, 0xc01d, 0x21, 0 + .dw 0x8e40, 0xc01d, 0x8e7f, 0xc01d, 0x21, 0 + .dw 0x8ec0, 0xc01d, 0x8eff, 0xc01d, 0x21, 0 + .dw 0x8f40, 0xc01d, 0x8f7f, 0xc01d, 0x21, 0 + .dw 0x8fc0, 0xc01d, 0x8fff, 0xc01d, 0x21, 0 + .dw 0x9040, 0xc01d, 0x907f, 0xc01d, 0x21, 0 + .dw 0x90c0, 0xc01d, 0x90ff, 0xc01d, 0x21, 0 + .dw 0x9140, 0xc01d, 0x917f, 0xc01d, 0x21, 0 + .dw 0x91c0, 0xc01d, 0x91ff, 0xc01d, 0x21, 0 + .dw 0x9240, 0xc01d, 0x927f, 0xc01d, 0x21, 0 + .dw 0x92c0, 0xc01d, 0x92ff, 0xc01d, 0x21, 0 + .dw 0x9340, 0xc01d, 0x937f, 0xc01d, 0x21, 0 + .dw 0x93c0, 0xc01d, 0x93ff, 0xc01d, 0x21, 0 + .dw 0x9440, 0xc01d, 0x947f, 0xc01d, 0x21, 0 + .dw 0x94c0, 0xc01d, 0x94ff, 0xc01d, 0x21, 0 + .dw 0x9540, 0xc01d, 0x957f, 0xc01d, 0x21, 0 + .dw 0x95c0, 0xc01d, 0x95ff, 0xc01d, 0x21, 0 + .dw 0x9640, 0xc01d, 0x967f, 0xc01d, 0x21, 0 + .dw 0x96c0, 0xc01d, 0x96ff, 0xc01d, 0x21, 0 + .dw 0x9740, 0xc01d, 0x977f, 0xc01d, 0x21, 0 + .dw 0x97c0, 0xc01d, 0x97ff, 0xc01d, 0x21, 0 + .dw 0x9840, 0xc01d, 0x987f, 0xc01d, 0x21, 0 + .dw 0x98c0, 0xc01d, 0x98ff, 0xc01d, 0x21, 0 + .dw 0x9940, 0xc01d, 0x997f, 0xc01d, 0x21, 0 + .dw 0x99c0, 0xc01d, 0x9fff, 0xc01d, 0x21, 0 + .dw 0xa040, 0xc01d, 0xa07f, 0xc01d, 0x21, 0 + .dw 0xa0c0, 0xc01d, 0xa0ff, 0xc01d, 0x21, 0 + .dw 0xa140, 0xc01d, 0xa17f, 0xc01d, 0x21, 0 + .dw 0xa1c0, 0xc01d, 0xa1ff, 0xc01d, 0x21, 0 + .dw 0xa240, 0xc01d, 0xa27f, 0xc01d, 0x21, 0 + .dw 0xa2c0, 0xc01d, 0xa2ff, 0xc01d, 0x21, 0 + .dw 0xa340, 0xc01d, 0xa37f, 0xc01d, 0x21, 0 + .dw 0xa3c0, 0xc01d, 0xa3ff, 0xc01d, 0x21, 0 + .dw 0xa440, 0xc01d, 0xa47f, 0xc01d, 0x21, 0 + .dw 0xa4c0, 0xc01d, 0xa4ff, 0xc01d, 0x21, 0 + .dw 0xa540, 0xc01d, 0xa57f, 0xc01d, 0x21, 0 + .dw 0xa5c0, 0xc01d, 0xa5ff, 0xc01d, 0x21, 0 + .dw 0xa640, 0xc01d, 0xa67f, 0xc01d, 0x21, 0 + .dw 0xa6c0, 0xc01d, 0xa6ff, 0xc01d, 0x21, 0 + .dw 0xa740, 0xc01d, 0xa77f, 0xc01d, 0x21, 0 + .dw 0xa7c0, 0xc01d, 0xa7ff, 0xc01d, 0x21, 0 + .dw 0xa840, 0xc01d, 0xa87f, 0xc01d, 0x21, 0 + .dw 0xa8c0, 0xc01d, 0xa8ff, 0xc01d, 0x21, 0 + .dw 0xa940, 0xc01d, 0xa97f, 0xc01d, 0x21, 0 + .dw 0xa9c0, 0xc01d, 0xa9ff, 0xc01d, 0x21, 0 + .dw 0xaa40, 0xc01d, 0xaa7f, 0xc01d, 0x21, 0 + .dw 0xaac0, 0xc01d, 0xaaff, 0xc01d, 0x21, 0 + .dw 0xab40, 0xc01d, 0xab7f, 0xc01d, 0x21, 0 + .dw 0xabc0, 0xc01d, 0xabff, 0xc01d, 0x21, 0 + .dw 0xac40, 0xc01d, 0xac7f, 0xc01d, 0x21, 0 + .dw 0xacc0, 0xc01d, 0xacff, 0xc01d, 0x21, 0 + .dw 0xad40, 0xc01d, 0xad7f, 0xc01d, 0x21, 0 + .dw 0xadc0, 0xc01d, 0xadff, 0xc01d, 0x21, 0 + .dw 0xae40, 0xc01d, 0xae7f, 0xc01d, 0x21, 0 + .dw 0xaec0, 0xc01d, 0xaeff, 0xc01d, 0x21, 0 + .dw 0xaf40, 0xc01d, 0xaf7f, 0xc01d, 0x21, 0 + .dw 0xafc0, 0xc01d, 0xafff, 0xc01d, 0x21, 0 + .dw 0xb040, 0xc01d, 0xb07f, 0xc01d, 0x21, 0 + .dw 0xb0c0, 0xc01d, 0xb0ff, 0xc01d, 0x21, 0 + .dw 0xb140, 0xc01d, 0xb17f, 0xc01d, 0x21, 0 + .dw 0xb1c0, 0xc01d, 0xb1ff, 0xc01d, 0x21, 0 + .dw 0xb240, 0xc01d, 0xb27f, 0xc01d, 0x21, 0 + .dw 0xb2c0, 0xc01d, 0xb2ff, 0xc01d, 0x21, 0 + .dw 0xb340, 0xc01d, 0xb37f, 0xc01d, 0x21, 0 + .dw 0xb3c0, 0xc01d, 0xb3ff, 0xc01d, 0x21, 0 + .dw 0xb440, 0xc01d, 0xb47f, 0xc01d, 0x21, 0 + .dw 0xb4c0, 0xc01d, 0xb4ff, 0xc01d, 0x21, 0 + .dw 0xb540, 0xc01d, 0xb57f, 0xc01d, 0x21, 0 + .dw 0xb5c0, 0xc01d, 0xb5ff, 0xc01d, 0x21, 0 + .dw 0xb640, 0xc01d, 0xb67f, 0xc01d, 0x21, 0 + .dw 0xb6c0, 0xc01d, 0xb6ff, 0xc01d, 0x21, 0 + .dw 0xb740, 0xc01d, 0xb77f, 0xc01d, 0x21, 0 + .dw 0xb7c0, 0xc01d, 0xb7ff, 0xc01d, 0x21, 0 + .dw 0xb840, 0xc01d, 0xb87f, 0xc01d, 0x21, 0 + .dw 0xb8c0, 0xc01d, 0xb8ff, 0xc01d, 0x21, 0 + .dw 0xb940, 0xc01d, 0xb97f, 0xc01d, 0x21, 0 + .dw 0xb9c0, 0xc01d, 0xbfff, 0xc01d, 0x21, 0 + .dw 0xc040, 0xc01d, 0xc07f, 0xc01d, 0x21, 0 + .dw 0xc0c0, 0xc01d, 0xc0ff, 0xc01d, 0x21, 0 + .dw 0xc140, 0xc01d, 0xc17f, 0xc01d, 0x21, 0 + .dw 0xc1c0, 0xc01d, 0xc1ff, 0xc01d, 0x21, 0 + .dw 0xc240, 0xc01d, 0xc27f, 0xc01d, 0x21, 0 + .dw 0xc2c0, 0xc01d, 0xc2ff, 0xc01d, 0x21, 0 + .dw 0xc340, 0xc01d, 0xc37f, 0xc01d, 0x21, 0 + .dw 0xc3c0, 0xc01d, 0xc3ff, 0xc01d, 0x21, 0 + .dw 0xc440, 0xc01d, 0xc47f, 0xc01d, 0x21, 0 + .dw 0xc4c0, 0xc01d, 0xc4ff, 0xc01d, 0x21, 0 + .dw 0xc540, 0xc01d, 0xc57f, 0xc01d, 0x21, 0 + .dw 0xc5c0, 0xc01d, 0xc5ff, 0xc01d, 0x21, 0 + .dw 0xc640, 0xc01d, 0xc67f, 0xc01d, 0x21, 0 + .dw 0xc6c0, 0xc01d, 0xc6ff, 0xc01d, 0x21, 0 + .dw 0xc740, 0xc01d, 0xc77f, 0xc01d, 0x21, 0 + .dw 0xc7c0, 0xc01d, 0xc7ff, 0xc01d, 0x21, 0 + .dw 0xc840, 0xc01d, 0xc87f, 0xc01d, 0x21, 0 + .dw 0xc8c0, 0xc01d, 0xc8ff, 0xc01d, 0x21, 0 + .dw 0xc940, 0xc01d, 0xc97f, 0xc01d, 0x21, 0 + .dw 0xc9c0, 0xc01d, 0xc9ff, 0xc01d, 0x21, 0 + .dw 0xca40, 0xc01d, 0xca7f, 0xc01d, 0x21, 0 + .dw 0xcac0, 0xc01d, 0xcaff, 0xc01d, 0x21, 0 + .dw 0xcb40, 0xc01d, 0xcb7f, 0xc01d, 0x21, 0 + .dw 0xcbc0, 0xc01d, 0xcbff, 0xc01d, 0x21, 0 + .dw 0xcc40, 0xc01d, 0xcc7f, 0xc01d, 0x21, 0 + .dw 0xccc0, 0xc01d, 0xccff, 0xc01d, 0x21, 0 + .dw 0xcd40, 0xc01d, 0xcd7f, 0xc01d, 0x21, 0 + .dw 0xcdc0, 0xc01d, 0xcdff, 0xc01d, 0x21, 0 + .dw 0xce40, 0xc01d, 0xce7f, 0xc01d, 0x21, 0 + .dw 0xcec0, 0xc01d, 0xceff, 0xc01d, 0x21, 0 + .dw 0xcf40, 0xc01d, 0xcf7f, 0xc01d, 0x21, 0 + .dw 0xcfc0, 0xc01d, 0xcfff, 0xc01d, 0x21, 0 + .dw 0xd040, 0xc01d, 0xd07f, 0xc01d, 0x21, 0 + .dw 0xd0c0, 0xc01d, 0xd0ff, 0xc01d, 0x21, 0 + .dw 0xd140, 0xc01d, 0xd17f, 0xc01d, 0x21, 0 + .dw 0xd1c0, 0xc01d, 0xd1ff, 0xc01d, 0x21, 0 + .dw 0xd240, 0xc01d, 0xd27f, 0xc01d, 0x21, 0 + .dw 0xd2c0, 0xc01d, 0xd2ff, 0xc01d, 0x21, 0 + .dw 0xd340, 0xc01d, 0xd37f, 0xc01d, 0x21, 0 + .dw 0xd3c0, 0xc01d, 0xd3ff, 0xc01d, 0x21, 0 + .dw 0xd440, 0xc01d, 0xd47f, 0xc01d, 0x21, 0 + .dw 0xd4c0, 0xc01d, 0xd4ff, 0xc01d, 0x21, 0 + .dw 0xd540, 0xc01d, 0xd57f, 0xc01d, 0x21, 0 + .dw 0xd5c0, 0xc01d, 0xd5ff, 0xc01d, 0x21, 0 + .dw 0xd640, 0xc01d, 0xd67f, 0xc01d, 0x21, 0 + .dw 0xd6c0, 0xc01d, 0xd6ff, 0xc01d, 0x21, 0 + .dw 0xd740, 0xc01d, 0xd77f, 0xc01d, 0x21, 0 + .dw 0xd7c0, 0xc01d, 0xd7ff, 0xc01d, 0x21, 0 + .dw 0xd840, 0xc01d, 0xd87f, 0xc01d, 0x21, 0 + .dw 0xd8c0, 0xc01d, 0xd8ff, 0xc01d, 0x21, 0 + .dw 0xd940, 0xc01d, 0xd97f, 0xc01d, 0x21, 0 + .dw 0xd9c0, 0xc01d, 0xdfff, 0xc01d, 0x21, 0 + .dw 0xe040, 0xc01d, 0xe07f, 0xc01d, 0x21, 0 + .dw 0xe0c0, 0xc01d, 0xe0ff, 0xc01d, 0x21, 0 + .dw 0xe140, 0xc01d, 0xe17f, 0xc01d, 0x21, 0 + .dw 0xe1c0, 0xc01d, 0xe1ff, 0xc01d, 0x21, 0 + .dw 0xe240, 0xc01d, 0xe27f, 0xc01d, 0x21, 0 + .dw 0xe2c0, 0xc01d, 0xe2ff, 0xc01d, 0x21, 0 + .dw 0xe340, 0xc01d, 0xe37f, 0xc01d, 0x21, 0 + .dw 0xe3c0, 0xc01d, 0xe3ff, 0xc01d, 0x21, 0 + .dw 0xe440, 0xc01d, 0xe47f, 0xc01d, 0x21, 0 + .dw 0xe4c0, 0xc01d, 0xe4ff, 0xc01d, 0x21, 0 + .dw 0xe540, 0xc01d, 0xe57f, 0xc01d, 0x21, 0 + .dw 0xe5c0, 0xc01d, 0xe5ff, 0xc01d, 0x21, 0 + .dw 0xe640, 0xc01d, 0xe67f, 0xc01d, 0x21, 0 + .dw 0xe6c0, 0xc01d, 0xe6ff, 0xc01d, 0x21, 0 + .dw 0xe740, 0xc01d, 0xe77f, 0xc01d, 0x21, 0 + .dw 0xe7c0, 0xc01d, 0xe7ff, 0xc01d, 0x21, 0 + .dw 0xe840, 0xc01d, 0xe87f, 0xc01d, 0x21, 0 + .dw 0xe8c0, 0xc01d, 0xe8ff, 0xc01d, 0x21, 0 + .dw 0xe940, 0xc01d, 0xe97f, 0xc01d, 0x21, 0 + .dw 0xe9c0, 0xc01d, 0xe9ff, 0xc01d, 0x21, 0 + .dw 0xea40, 0xc01d, 0xea7f, 0xc01d, 0x21, 0 + .dw 0xeac0, 0xc01d, 0xeaff, 0xc01d, 0x21, 0 + .dw 0xeb40, 0xc01d, 0xeb7f, 0xc01d, 0x21, 0 + .dw 0xebc0, 0xc01d, 0xebff, 0xc01d, 0x21, 0 + .dw 0xec40, 0xc01d, 0xec7f, 0xc01d, 0x21, 0 + .dw 0xecc0, 0xc01d, 0xecff, 0xc01d, 0x21, 0 + .dw 0xed40, 0xc01d, 0xed7f, 0xc01d, 0x21, 0 + .dw 0xedc0, 0xc01d, 0xedff, 0xc01d, 0x21, 0 + .dw 0xee40, 0xc01d, 0xee7f, 0xc01d, 0x21, 0 + .dw 0xeec0, 0xc01d, 0xeeff, 0xc01d, 0x21, 0 + .dw 0xef40, 0xc01d, 0xef7f, 0xc01d, 0x21, 0 + .dw 0xefc0, 0xc01d, 0xefff, 0xc01d, 0x21, 0 + .dw 0xf040, 0xc01d, 0xf07f, 0xc01d, 0x21, 0 + .dw 0xf0c0, 0xc01d, 0xf0ff, 0xc01d, 0x21, 0 + .dw 0xf140, 0xc01d, 0xf17f, 0xc01d, 0x21, 0 + .dw 0xf1c0, 0xc01d, 0xf1ff, 0xc01d, 0x21, 0 + .dw 0xf240, 0xc01d, 0xf27f, 0xc01d, 0x21, 0 + .dw 0xf2c0, 0xc01d, 0xf2ff, 0xc01d, 0x21, 0 + .dw 0xf340, 0xc01d, 0xf37f, 0xc01d, 0x21, 0 + .dw 0xf3c0, 0xc01d, 0xf3ff, 0xc01d, 0x21, 0 + .dw 0xf440, 0xc01d, 0xf47f, 0xc01d, 0x21, 0 + .dw 0xf4c0, 0xc01d, 0xf4ff, 0xc01d, 0x21, 0 + .dw 0xf540, 0xc01d, 0xf57f, 0xc01d, 0x21, 0 + .dw 0xf5c0, 0xc01d, 0xf5ff, 0xc01d, 0x21, 0 + .dw 0xf640, 0xc01d, 0xf67f, 0xc01d, 0x21, 0 + .dw 0xf6c0, 0xc01d, 0xf6ff, 0xc01d, 0x21, 0 + .dw 0xf740, 0xc01d, 0xf77f, 0xc01d, 0x21, 0 + .dw 0xf7c0, 0xc01d, 0xf7ff, 0xc01d, 0x21, 0 + .dw 0xf840, 0xc01d, 0xf87f, 0xc01d, 0x21, 0 + .dw 0xf8c0, 0xc01d, 0xf8ff, 0xc01d, 0x21, 0 + .dw 0xf940, 0xc01d, 0xf97f, 0xc01d, 0x21, 0 + .dw 0xf9c0, 0xc01d, 0xffff, 0xc01d, 0x21, 0 + .dw 0x0040, 0xc01e, 0x007f, 0xc01e, 0x21, 0 + .dw 0x00c0, 0xc01e, 0x00ff, 0xc01e, 0x21, 0 + .dw 0x0140, 0xc01e, 0x017f, 0xc01e, 0x21, 0 + .dw 0x01c0, 0xc01e, 0x01ff, 0xc01e, 0x21, 0 + .dw 0x0240, 0xc01e, 0x027f, 0xc01e, 0x21, 0 + .dw 0x02c0, 0xc01e, 0x02ff, 0xc01e, 0x21, 0 + .dw 0x0340, 0xc01e, 0x037f, 0xc01e, 0x21, 0 + .dw 0x03c0, 0xc01e, 0x03ff, 0xc01e, 0x21, 0 + .dw 0x0440, 0xc01e, 0x047f, 0xc01e, 0x21, 0 + .dw 0x04c0, 0xc01e, 0x04ff, 0xc01e, 0x21, 0 + .dw 0x0540, 0xc01e, 0x057f, 0xc01e, 0x21, 0 + .dw 0x05c0, 0xc01e, 0x05ff, 0xc01e, 0x21, 0 + .dw 0x0640, 0xc01e, 0x067f, 0xc01e, 0x21, 0 + .dw 0x06c0, 0xc01e, 0x06ff, 0xc01e, 0x21, 0 + .dw 0x0740, 0xc01e, 0x077f, 0xc01e, 0x21, 0 + .dw 0x07c0, 0xc01e, 0x07ff, 0xc01e, 0x21, 0 + .dw 0x0840, 0xc01e, 0x087f, 0xc01e, 0x21, 0 + .dw 0x08c0, 0xc01e, 0x08ff, 0xc01e, 0x21, 0 + .dw 0x0940, 0xc01e, 0x097f, 0xc01e, 0x21, 0 + .dw 0x09c0, 0xc01e, 0x09ff, 0xc01e, 0x21, 0 + .dw 0x0a40, 0xc01e, 0x0a7f, 0xc01e, 0x21, 0 + .dw 0x0ac0, 0xc01e, 0x0aff, 0xc01e, 0x21, 0 + .dw 0x0b40, 0xc01e, 0x0b7f, 0xc01e, 0x21, 0 + .dw 0x0bc0, 0xc01e, 0x0bff, 0xc01e, 0x21, 0 + .dw 0x0c40, 0xc01e, 0x0c7f, 0xc01e, 0x21, 0 + .dw 0x0cc0, 0xc01e, 0x0cff, 0xc01e, 0x21, 0 + .dw 0x0d40, 0xc01e, 0x0d7f, 0xc01e, 0x21, 0 + .dw 0x0dc0, 0xc01e, 0x0dff, 0xc01e, 0x21, 0 + .dw 0x0e40, 0xc01e, 0x0e7f, 0xc01e, 0x21, 0 + .dw 0x0ec0, 0xc01e, 0x0eff, 0xc01e, 0x21, 0 + .dw 0x0f40, 0xc01e, 0x0f7f, 0xc01e, 0x21, 0 + .dw 0x0fc0, 0xc01e, 0x0fff, 0xc01e, 0x21, 0 + .dw 0x1040, 0xc01e, 0x107f, 0xc01e, 0x21, 0 + .dw 0x10c0, 0xc01e, 0x10ff, 0xc01e, 0x21, 0 + .dw 0x1140, 0xc01e, 0x117f, 0xc01e, 0x21, 0 + .dw 0x11c0, 0xc01e, 0x11ff, 0xc01e, 0x21, 0 + .dw 0x1240, 0xc01e, 0x127f, 0xc01e, 0x21, 0 + .dw 0x12c0, 0xc01e, 0x12ff, 0xc01e, 0x21, 0 + .dw 0x1340, 0xc01e, 0x137f, 0xc01e, 0x21, 0 + .dw 0x13c0, 0xc01e, 0x13ff, 0xc01e, 0x21, 0 + .dw 0x1440, 0xc01e, 0x147f, 0xc01e, 0x21, 0 + .dw 0x14c0, 0xc01e, 0x14ff, 0xc01e, 0x21, 0 + .dw 0x1540, 0xc01e, 0x157f, 0xc01e, 0x21, 0 + .dw 0x15c0, 0xc01e, 0x15ff, 0xc01e, 0x21, 0 + .dw 0x1640, 0xc01e, 0x167f, 0xc01e, 0x21, 0 + .dw 0x16c0, 0xc01e, 0x16ff, 0xc01e, 0x21, 0 + .dw 0x1740, 0xc01e, 0x177f, 0xc01e, 0x21, 0 + .dw 0x17c0, 0xc01e, 0x17ff, 0xc01e, 0x21, 0 + .dw 0x1840, 0xc01e, 0x187f, 0xc01e, 0x21, 0 + .dw 0x18c0, 0xc01e, 0x18ff, 0xc01e, 0x21, 0 + .dw 0x1940, 0xc01e, 0x197f, 0xc01e, 0x21, 0 + .dw 0x19c0, 0xc01e, 0x1fff, 0xc01e, 0x21, 0 + .dw 0x2040, 0xc01e, 0x207f, 0xc01e, 0x21, 0 + .dw 0x20c0, 0xc01e, 0x20ff, 0xc01e, 0x21, 0 + .dw 0x2140, 0xc01e, 0x217f, 0xc01e, 0x21, 0 + .dw 0x21c0, 0xc01e, 0x21ff, 0xc01e, 0x21, 0 + .dw 0x2240, 0xc01e, 0x227f, 0xc01e, 0x21, 0 + .dw 0x22c0, 0xc01e, 0x22ff, 0xc01e, 0x21, 0 + .dw 0x2340, 0xc01e, 0x237f, 0xc01e, 0x21, 0 + .dw 0x23c0, 0xc01e, 0x23ff, 0xc01e, 0x21, 0 + .dw 0x2440, 0xc01e, 0x247f, 0xc01e, 0x21, 0 + .dw 0x24c0, 0xc01e, 0x24ff, 0xc01e, 0x21, 0 + .dw 0x2540, 0xc01e, 0x257f, 0xc01e, 0x21, 0 + .dw 0x25c0, 0xc01e, 0x25ff, 0xc01e, 0x21, 0 + .dw 0x2640, 0xc01e, 0x267f, 0xc01e, 0x21, 0 + .dw 0x26c0, 0xc01e, 0x26ff, 0xc01e, 0x21, 0 + .dw 0x2740, 0xc01e, 0x277f, 0xc01e, 0x21, 0 + .dw 0x27c0, 0xc01e, 0x27ff, 0xc01e, 0x21, 0 + .dw 0x2840, 0xc01e, 0x287f, 0xc01e, 0x21, 0 + .dw 0x28c0, 0xc01e, 0x28ff, 0xc01e, 0x21, 0 + .dw 0x2940, 0xc01e, 0x297f, 0xc01e, 0x21, 0 + .dw 0x29c0, 0xc01e, 0x29ff, 0xc01e, 0x21, 0 + .dw 0x2a40, 0xc01e, 0x2a7f, 0xc01e, 0x21, 0 + .dw 0x2ac0, 0xc01e, 0x2aff, 0xc01e, 0x21, 0 + .dw 0x2b40, 0xc01e, 0x2b7f, 0xc01e, 0x21, 0 + .dw 0x2bc0, 0xc01e, 0x2bff, 0xc01e, 0x21, 0 + .dw 0x2c40, 0xc01e, 0x2c7f, 0xc01e, 0x21, 0 + .dw 0x2cc0, 0xc01e, 0x2cff, 0xc01e, 0x21, 0 + .dw 0x2d40, 0xc01e, 0x2d7f, 0xc01e, 0x21, 0 + .dw 0x2dc0, 0xc01e, 0x2dff, 0xc01e, 0x21, 0 + .dw 0x2e40, 0xc01e, 0x2e7f, 0xc01e, 0x21, 0 + .dw 0x2ec0, 0xc01e, 0x2eff, 0xc01e, 0x21, 0 + .dw 0x2f40, 0xc01e, 0x2f7f, 0xc01e, 0x21, 0 + .dw 0x2fc0, 0xc01e, 0x2fff, 0xc01e, 0x21, 0 + .dw 0x3040, 0xc01e, 0x307f, 0xc01e, 0x21, 0 + .dw 0x30c0, 0xc01e, 0x30ff, 0xc01e, 0x21, 0 + .dw 0x3140, 0xc01e, 0x317f, 0xc01e, 0x21, 0 + .dw 0x31c0, 0xc01e, 0x31ff, 0xc01e, 0x21, 0 + .dw 0x3240, 0xc01e, 0x327f, 0xc01e, 0x21, 0 + .dw 0x32c0, 0xc01e, 0x32ff, 0xc01e, 0x21, 0 + .dw 0x3340, 0xc01e, 0x337f, 0xc01e, 0x21, 0 + .dw 0x33c0, 0xc01e, 0x33ff, 0xc01e, 0x21, 0 + .dw 0x3440, 0xc01e, 0x347f, 0xc01e, 0x21, 0 + .dw 0x34c0, 0xc01e, 0x34ff, 0xc01e, 0x21, 0 + .dw 0x3540, 0xc01e, 0x357f, 0xc01e, 0x21, 0 + .dw 0x35c0, 0xc01e, 0x35ff, 0xc01e, 0x21, 0 + .dw 0x3640, 0xc01e, 0x367f, 0xc01e, 0x21, 0 + .dw 0x36c0, 0xc01e, 0x36ff, 0xc01e, 0x21, 0 + .dw 0x3740, 0xc01e, 0x377f, 0xc01e, 0x21, 0 + .dw 0x37c0, 0xc01e, 0x37ff, 0xc01e, 0x21, 0 + .dw 0x3840, 0xc01e, 0x387f, 0xc01e, 0x21, 0 + .dw 0x38c0, 0xc01e, 0x38ff, 0xc01e, 0x21, 0 + .dw 0x3940, 0xc01e, 0x397f, 0xc01e, 0x21, 0 + .dw 0x39c0, 0xc01e, 0x3fff, 0xc01e, 0x21, 0 + .dw 0x4040, 0xc01e, 0x407f, 0xc01e, 0x21, 0 + .dw 0x40c0, 0xc01e, 0x40ff, 0xc01e, 0x21, 0 + .dw 0x4140, 0xc01e, 0x417f, 0xc01e, 0x21, 0 + .dw 0x41c0, 0xc01e, 0x41ff, 0xc01e, 0x21, 0 + .dw 0x4240, 0xc01e, 0x427f, 0xc01e, 0x21, 0 + .dw 0x42c0, 0xc01e, 0x42ff, 0xc01e, 0x21, 0 + .dw 0x4340, 0xc01e, 0x437f, 0xc01e, 0x21, 0 + .dw 0x43c0, 0xc01e, 0x43ff, 0xc01e, 0x21, 0 + .dw 0x4440, 0xc01e, 0x447f, 0xc01e, 0x21, 0 + .dw 0x44c0, 0xc01e, 0x44ff, 0xc01e, 0x21, 0 + .dw 0x4540, 0xc01e, 0x457f, 0xc01e, 0x21, 0 + .dw 0x45c0, 0xc01e, 0x45ff, 0xc01e, 0x21, 0 + .dw 0x4640, 0xc01e, 0x467f, 0xc01e, 0x21, 0 + .dw 0x46c0, 0xc01e, 0x46ff, 0xc01e, 0x21, 0 + .dw 0x4740, 0xc01e, 0x477f, 0xc01e, 0x21, 0 + .dw 0x47c0, 0xc01e, 0x47ff, 0xc01e, 0x21, 0 + .dw 0x4840, 0xc01e, 0x487f, 0xc01e, 0x21, 0 + .dw 0x48c0, 0xc01e, 0x48ff, 0xc01e, 0x21, 0 + .dw 0x4940, 0xc01e, 0x497f, 0xc01e, 0x21, 0 + .dw 0x49c0, 0xc01e, 0x49ff, 0xc01e, 0x21, 0 + .dw 0x4a40, 0xc01e, 0x4a7f, 0xc01e, 0x21, 0 + .dw 0x4ac0, 0xc01e, 0x4aff, 0xc01e, 0x21, 0 + .dw 0x4b40, 0xc01e, 0x4b7f, 0xc01e, 0x21, 0 + .dw 0x4bc0, 0xc01e, 0x4bff, 0xc01e, 0x21, 0 + .dw 0x4c40, 0xc01e, 0x4c7f, 0xc01e, 0x21, 0 + .dw 0x4cc0, 0xc01e, 0x4cff, 0xc01e, 0x21, 0 + .dw 0x4d40, 0xc01e, 0x4d7f, 0xc01e, 0x21, 0 + .dw 0x4dc0, 0xc01e, 0x4dff, 0xc01e, 0x21, 0 + .dw 0x4e40, 0xc01e, 0x4e7f, 0xc01e, 0x21, 0 + .dw 0x4ec0, 0xc01e, 0x4eff, 0xc01e, 0x21, 0 + .dw 0x4f40, 0xc01e, 0x4f7f, 0xc01e, 0x21, 0 + .dw 0x4fc0, 0xc01e, 0x4fff, 0xc01e, 0x21, 0 + .dw 0x5040, 0xc01e, 0x507f, 0xc01e, 0x21, 0 + .dw 0x50c0, 0xc01e, 0x50ff, 0xc01e, 0x21, 0 + .dw 0x5140, 0xc01e, 0x517f, 0xc01e, 0x21, 0 + .dw 0x51c0, 0xc01e, 0x51ff, 0xc01e, 0x21, 0 + .dw 0x5240, 0xc01e, 0x527f, 0xc01e, 0x21, 0 + .dw 0x52c0, 0xc01e, 0x52ff, 0xc01e, 0x21, 0 + .dw 0x5340, 0xc01e, 0x537f, 0xc01e, 0x21, 0 + .dw 0x53c0, 0xc01e, 0x53ff, 0xc01e, 0x21, 0 + .dw 0x5440, 0xc01e, 0x547f, 0xc01e, 0x21, 0 + .dw 0x54c0, 0xc01e, 0x54ff, 0xc01e, 0x21, 0 + .dw 0x5540, 0xc01e, 0x557f, 0xc01e, 0x21, 0 + .dw 0x55c0, 0xc01e, 0x55ff, 0xc01e, 0x21, 0 + .dw 0x5640, 0xc01e, 0x567f, 0xc01e, 0x21, 0 + .dw 0x56c0, 0xc01e, 0x56ff, 0xc01e, 0x21, 0 + .dw 0x5740, 0xc01e, 0x577f, 0xc01e, 0x21, 0 + .dw 0x57c0, 0xc01e, 0x57ff, 0xc01e, 0x21, 0 + .dw 0x5840, 0xc01e, 0x587f, 0xc01e, 0x21, 0 + .dw 0x58c0, 0xc01e, 0x58ff, 0xc01e, 0x21, 0 + .dw 0x5940, 0xc01e, 0x597f, 0xc01e, 0x21, 0 + .dw 0x59c0, 0xc01e, 0x5fff, 0xc01e, 0x21, 0 + .dw 0x6040, 0xc01e, 0x607f, 0xc01e, 0x21, 0 + .dw 0x60c0, 0xc01e, 0x60ff, 0xc01e, 0x21, 0 + .dw 0x6140, 0xc01e, 0x617f, 0xc01e, 0x21, 0 + .dw 0x61c0, 0xc01e, 0x61ff, 0xc01e, 0x21, 0 + .dw 0x6240, 0xc01e, 0x627f, 0xc01e, 0x21, 0 + .dw 0x62c0, 0xc01e, 0x62ff, 0xc01e, 0x21, 0 + .dw 0x6340, 0xc01e, 0x637f, 0xc01e, 0x21, 0 + .dw 0x63c0, 0xc01e, 0x63ff, 0xc01e, 0x21, 0 + .dw 0x6440, 0xc01e, 0x647f, 0xc01e, 0x21, 0 + .dw 0x64c0, 0xc01e, 0x64ff, 0xc01e, 0x21, 0 + .dw 0x6540, 0xc01e, 0x657f, 0xc01e, 0x21, 0 + .dw 0x65c0, 0xc01e, 0x65ff, 0xc01e, 0x21, 0 + .dw 0x6640, 0xc01e, 0x667f, 0xc01e, 0x21, 0 + .dw 0x66c0, 0xc01e, 0x66ff, 0xc01e, 0x21, 0 + .dw 0x6740, 0xc01e, 0x677f, 0xc01e, 0x21, 0 + .dw 0x67c0, 0xc01e, 0x67ff, 0xc01e, 0x21, 0 + .dw 0x6840, 0xc01e, 0x687f, 0xc01e, 0x21, 0 + .dw 0x68c0, 0xc01e, 0x68ff, 0xc01e, 0x21, 0 + .dw 0x6940, 0xc01e, 0x697f, 0xc01e, 0x21, 0 + .dw 0x69c0, 0xc01e, 0x69ff, 0xc01e, 0x21, 0 + .dw 0x6a40, 0xc01e, 0x6a7f, 0xc01e, 0x21, 0 + .dw 0x6ac0, 0xc01e, 0x6aff, 0xc01e, 0x21, 0 + .dw 0x6b40, 0xc01e, 0x6b7f, 0xc01e, 0x21, 0 + .dw 0x6bc0, 0xc01e, 0x6bff, 0xc01e, 0x21, 0 + .dw 0x6c40, 0xc01e, 0x6c7f, 0xc01e, 0x21, 0 + .dw 0x6cc0, 0xc01e, 0x6cff, 0xc01e, 0x21, 0 + .dw 0x6d40, 0xc01e, 0x6d7f, 0xc01e, 0x21, 0 + .dw 0x6dc0, 0xc01e, 0x6dff, 0xc01e, 0x21, 0 + .dw 0x6e40, 0xc01e, 0x6e7f, 0xc01e, 0x21, 0 + .dw 0x6ec0, 0xc01e, 0x6eff, 0xc01e, 0x21, 0 + .dw 0x6f40, 0xc01e, 0x6f7f, 0xc01e, 0x21, 0 + .dw 0x6fc0, 0xc01e, 0x6fff, 0xc01e, 0x21, 0 + .dw 0x7040, 0xc01e, 0x707f, 0xc01e, 0x21, 0 + .dw 0x70c0, 0xc01e, 0x70ff, 0xc01e, 0x21, 0 + .dw 0x7140, 0xc01e, 0x717f, 0xc01e, 0x21, 0 + .dw 0x71c0, 0xc01e, 0x71ff, 0xc01e, 0x21, 0 + .dw 0x7240, 0xc01e, 0x727f, 0xc01e, 0x21, 0 + .dw 0x72c0, 0xc01e, 0x72ff, 0xc01e, 0x21, 0 + .dw 0x7340, 0xc01e, 0x737f, 0xc01e, 0x21, 0 + .dw 0x73c0, 0xc01e, 0x73ff, 0xc01e, 0x21, 0 + .dw 0x7440, 0xc01e, 0x747f, 0xc01e, 0x21, 0 + .dw 0x74c0, 0xc01e, 0x74ff, 0xc01e, 0x21, 0 + .dw 0x7540, 0xc01e, 0x757f, 0xc01e, 0x21, 0 + .dw 0x75c0, 0xc01e, 0x75ff, 0xc01e, 0x21, 0 + .dw 0x7640, 0xc01e, 0x767f, 0xc01e, 0x21, 0 + .dw 0x76c0, 0xc01e, 0x76ff, 0xc01e, 0x21, 0 + .dw 0x7740, 0xc01e, 0x777f, 0xc01e, 0x21, 0 + .dw 0x77c0, 0xc01e, 0x77ff, 0xc01e, 0x21, 0 + .dw 0x7840, 0xc01e, 0x787f, 0xc01e, 0x21, 0 + .dw 0x78c0, 0xc01e, 0x78ff, 0xc01e, 0x21, 0 + .dw 0x7940, 0xc01e, 0x797f, 0xc01e, 0x21, 0 + .dw 0x79c0, 0xc01e, 0x7fff, 0xc01e, 0x21, 0 + .dw 0x8040, 0xc01e, 0x807f, 0xc01e, 0x21, 0 + .dw 0x80c0, 0xc01e, 0x80ff, 0xc01e, 0x21, 0 + .dw 0x8140, 0xc01e, 0x817f, 0xc01e, 0x21, 0 + .dw 0x81c0, 0xc01e, 0x81ff, 0xc01e, 0x21, 0 + .dw 0x8240, 0xc01e, 0x827f, 0xc01e, 0x21, 0 + .dw 0x82c0, 0xc01e, 0x82ff, 0xc01e, 0x21, 0 + .dw 0x8340, 0xc01e, 0x837f, 0xc01e, 0x21, 0 + .dw 0x83c0, 0xc01e, 0x83ff, 0xc01e, 0x21, 0 + .dw 0x8440, 0xc01e, 0x847f, 0xc01e, 0x21, 0 + .dw 0x84c0, 0xc01e, 0x84ff, 0xc01e, 0x21, 0 + .dw 0x8540, 0xc01e, 0x857f, 0xc01e, 0x21, 0 + .dw 0x85c0, 0xc01e, 0x85ff, 0xc01e, 0x21, 0 + .dw 0x8640, 0xc01e, 0x867f, 0xc01e, 0x21, 0 + .dw 0x86c0, 0xc01e, 0x86ff, 0xc01e, 0x21, 0 + .dw 0x8740, 0xc01e, 0x877f, 0xc01e, 0x21, 0 + .dw 0x87c0, 0xc01e, 0x87ff, 0xc01e, 0x21, 0 + .dw 0x8840, 0xc01e, 0x887f, 0xc01e, 0x21, 0 + .dw 0x88c0, 0xc01e, 0x88ff, 0xc01e, 0x21, 0 + .dw 0x8940, 0xc01e, 0x897f, 0xc01e, 0x21, 0 + .dw 0x89c0, 0xc01e, 0x89ff, 0xc01e, 0x21, 0 + .dw 0x8a40, 0xc01e, 0x8a7f, 0xc01e, 0x21, 0 + .dw 0x8ac0, 0xc01e, 0x8aff, 0xc01e, 0x21, 0 + .dw 0x8b40, 0xc01e, 0x8b7f, 0xc01e, 0x21, 0 + .dw 0x8bc0, 0xc01e, 0x8bff, 0xc01e, 0x21, 0 + .dw 0x8c40, 0xc01e, 0x8c7f, 0xc01e, 0x21, 0 + .dw 0x8cc0, 0xc01e, 0x8cff, 0xc01e, 0x21, 0 + .dw 0x8d40, 0xc01e, 0x8d7f, 0xc01e, 0x21, 0 + .dw 0x8dc0, 0xc01e, 0x8dff, 0xc01e, 0x21, 0 + .dw 0x8e40, 0xc01e, 0x8e7f, 0xc01e, 0x21, 0 + .dw 0x8ec0, 0xc01e, 0x8eff, 0xc01e, 0x21, 0 + .dw 0x8f40, 0xc01e, 0x8f7f, 0xc01e, 0x21, 0 + .dw 0x8fc0, 0xc01e, 0x8fff, 0xc01e, 0x21, 0 + .dw 0x9040, 0xc01e, 0x907f, 0xc01e, 0x21, 0 + .dw 0x90c0, 0xc01e, 0x90ff, 0xc01e, 0x21, 0 + .dw 0x9140, 0xc01e, 0x917f, 0xc01e, 0x21, 0 + .dw 0x91c0, 0xc01e, 0x91ff, 0xc01e, 0x21, 0 + .dw 0x9240, 0xc01e, 0x927f, 0xc01e, 0x21, 0 + .dw 0x92c0, 0xc01e, 0x92ff, 0xc01e, 0x21, 0 + .dw 0x9340, 0xc01e, 0x937f, 0xc01e, 0x21, 0 + .dw 0x93c0, 0xc01e, 0x93ff, 0xc01e, 0x21, 0 + .dw 0x9440, 0xc01e, 0x947f, 0xc01e, 0x21, 0 + .dw 0x94c0, 0xc01e, 0x94ff, 0xc01e, 0x21, 0 + .dw 0x9540, 0xc01e, 0x957f, 0xc01e, 0x21, 0 + .dw 0x95c0, 0xc01e, 0x95ff, 0xc01e, 0x21, 0 + .dw 0x9640, 0xc01e, 0x967f, 0xc01e, 0x21, 0 + .dw 0x96c0, 0xc01e, 0x96ff, 0xc01e, 0x21, 0 + .dw 0x9740, 0xc01e, 0x977f, 0xc01e, 0x21, 0 + .dw 0x97c0, 0xc01e, 0x97ff, 0xc01e, 0x21, 0 + .dw 0x9840, 0xc01e, 0x987f, 0xc01e, 0x21, 0 + .dw 0x98c0, 0xc01e, 0x98ff, 0xc01e, 0x21, 0 + .dw 0x9940, 0xc01e, 0x997f, 0xc01e, 0x21, 0 + .dw 0x99c0, 0xc01e, 0x9fff, 0xc01e, 0x21, 0 + .dw 0xa040, 0xc01e, 0xa07f, 0xc01e, 0x21, 0 + .dw 0xa0c0, 0xc01e, 0xa0ff, 0xc01e, 0x21, 0 + .dw 0xa140, 0xc01e, 0xa17f, 0xc01e, 0x21, 0 + .dw 0xa1c0, 0xc01e, 0xa1ff, 0xc01e, 0x21, 0 + .dw 0xa240, 0xc01e, 0xa27f, 0xc01e, 0x21, 0 + .dw 0xa2c0, 0xc01e, 0xa2ff, 0xc01e, 0x21, 0 + .dw 0xa340, 0xc01e, 0xa37f, 0xc01e, 0x21, 0 + .dw 0xa3c0, 0xc01e, 0xa3ff, 0xc01e, 0x21, 0 + .dw 0xa440, 0xc01e, 0xa47f, 0xc01e, 0x21, 0 + .dw 0xa4c0, 0xc01e, 0xa4ff, 0xc01e, 0x21, 0 + .dw 0xa540, 0xc01e, 0xa57f, 0xc01e, 0x21, 0 + .dw 0xa5c0, 0xc01e, 0xa5ff, 0xc01e, 0x21, 0 + .dw 0xa640, 0xc01e, 0xa67f, 0xc01e, 0x21, 0 + .dw 0xa6c0, 0xc01e, 0xa6ff, 0xc01e, 0x21, 0 + .dw 0xa740, 0xc01e, 0xa77f, 0xc01e, 0x21, 0 + .dw 0xa7c0, 0xc01e, 0xa7ff, 0xc01e, 0x21, 0 + .dw 0xa840, 0xc01e, 0xa87f, 0xc01e, 0x21, 0 + .dw 0xa8c0, 0xc01e, 0xa8ff, 0xc01e, 0x21, 0 + .dw 0xa940, 0xc01e, 0xa97f, 0xc01e, 0x21, 0 + .dw 0xa9c0, 0xc01e, 0xa9ff, 0xc01e, 0x21, 0 + .dw 0xaa40, 0xc01e, 0xaa7f, 0xc01e, 0x21, 0 + .dw 0xaac0, 0xc01e, 0xaaff, 0xc01e, 0x21, 0 + .dw 0xab40, 0xc01e, 0xab7f, 0xc01e, 0x21, 0 + .dw 0xabc0, 0xc01e, 0xabff, 0xc01e, 0x21, 0 + .dw 0xac40, 0xc01e, 0xac7f, 0xc01e, 0x21, 0 + .dw 0xacc0, 0xc01e, 0xacff, 0xc01e, 0x21, 0 + .dw 0xad40, 0xc01e, 0xad7f, 0xc01e, 0x21, 0 + .dw 0xadc0, 0xc01e, 0xadff, 0xc01e, 0x21, 0 + .dw 0xae40, 0xc01e, 0xae7f, 0xc01e, 0x21, 0 + .dw 0xaec0, 0xc01e, 0xaeff, 0xc01e, 0x21, 0 + .dw 0xaf40, 0xc01e, 0xaf7f, 0xc01e, 0x21, 0 + .dw 0xafc0, 0xc01e, 0xafff, 0xc01e, 0x21, 0 + .dw 0xb040, 0xc01e, 0xb07f, 0xc01e, 0x21, 0 + .dw 0xb0c0, 0xc01e, 0xb0ff, 0xc01e, 0x21, 0 + .dw 0xb140, 0xc01e, 0xb17f, 0xc01e, 0x21, 0 + .dw 0xb1c0, 0xc01e, 0xb1ff, 0xc01e, 0x21, 0 + .dw 0xb240, 0xc01e, 0xb27f, 0xc01e, 0x21, 0 + .dw 0xb2c0, 0xc01e, 0xb2ff, 0xc01e, 0x21, 0 + .dw 0xb340, 0xc01e, 0xb37f, 0xc01e, 0x21, 0 + .dw 0xb3c0, 0xc01e, 0xb3ff, 0xc01e, 0x21, 0 + .dw 0xb440, 0xc01e, 0xb47f, 0xc01e, 0x21, 0 + .dw 0xb4c0, 0xc01e, 0xb4ff, 0xc01e, 0x21, 0 + .dw 0xb540, 0xc01e, 0xb57f, 0xc01e, 0x21, 0 + .dw 0xb5c0, 0xc01e, 0xb5ff, 0xc01e, 0x21, 0 + .dw 0xb640, 0xc01e, 0xb67f, 0xc01e, 0x21, 0 + .dw 0xb6c0, 0xc01e, 0xb6ff, 0xc01e, 0x21, 0 + .dw 0xb740, 0xc01e, 0xb77f, 0xc01e, 0x21, 0 + .dw 0xb7c0, 0xc01e, 0xb7ff, 0xc01e, 0x21, 0 + .dw 0xb840, 0xc01e, 0xb87f, 0xc01e, 0x21, 0 + .dw 0xb8c0, 0xc01e, 0xb8ff, 0xc01e, 0x21, 0 + .dw 0xb940, 0xc01e, 0xb97f, 0xc01e, 0x21, 0 + .dw 0xb9c0, 0xc01e, 0xbfff, 0xc01e, 0x21, 0 + .dw 0xc040, 0xc01e, 0xc07f, 0xc01e, 0x21, 0 + .dw 0xc0c0, 0xc01e, 0xc0ff, 0xc01e, 0x21, 0 + .dw 0xc140, 0xc01e, 0xc17f, 0xc01e, 0x21, 0 + .dw 0xc1c0, 0xc01e, 0xc1ff, 0xc01e, 0x21, 0 + .dw 0xc240, 0xc01e, 0xc27f, 0xc01e, 0x21, 0 + .dw 0xc2c0, 0xc01e, 0xc2ff, 0xc01e, 0x21, 0 + .dw 0xc340, 0xc01e, 0xc37f, 0xc01e, 0x21, 0 + .dw 0xc3c0, 0xc01e, 0xc3ff, 0xc01e, 0x21, 0 + .dw 0xc440, 0xc01e, 0xc47f, 0xc01e, 0x21, 0 + .dw 0xc4c0, 0xc01e, 0xc4ff, 0xc01e, 0x21, 0 + .dw 0xc540, 0xc01e, 0xc57f, 0xc01e, 0x21, 0 + .dw 0xc5c0, 0xc01e, 0xc5ff, 0xc01e, 0x21, 0 + .dw 0xc640, 0xc01e, 0xc67f, 0xc01e, 0x21, 0 + .dw 0xc6c0, 0xc01e, 0xc6ff, 0xc01e, 0x21, 0 + .dw 0xc740, 0xc01e, 0xc77f, 0xc01e, 0x21, 0 + .dw 0xc7c0, 0xc01e, 0xc7ff, 0xc01e, 0x21, 0 + .dw 0xc840, 0xc01e, 0xc87f, 0xc01e, 0x21, 0 + .dw 0xc8c0, 0xc01e, 0xc8ff, 0xc01e, 0x21, 0 + .dw 0xc940, 0xc01e, 0xc97f, 0xc01e, 0x21, 0 + .dw 0xc9c0, 0xc01e, 0xc9ff, 0xc01e, 0x21, 0 + .dw 0xca40, 0xc01e, 0xca7f, 0xc01e, 0x21, 0 + .dw 0xcac0, 0xc01e, 0xcaff, 0xc01e, 0x21, 0 + .dw 0xcb40, 0xc01e, 0xcb7f, 0xc01e, 0x21, 0 + .dw 0xcbc0, 0xc01e, 0xcbff, 0xc01e, 0x21, 0 + .dw 0xcc40, 0xc01e, 0xcc7f, 0xc01e, 0x21, 0 + .dw 0xccc0, 0xc01e, 0xccff, 0xc01e, 0x21, 0 + .dw 0xcd40, 0xc01e, 0xcd7f, 0xc01e, 0x21, 0 + .dw 0xcdc0, 0xc01e, 0xcdff, 0xc01e, 0x21, 0 + .dw 0xce40, 0xc01e, 0xce7f, 0xc01e, 0x21, 0 + .dw 0xcec0, 0xc01e, 0xceff, 0xc01e, 0x21, 0 + .dw 0xcf40, 0xc01e, 0xcf7f, 0xc01e, 0x21, 0 + .dw 0xcfc0, 0xc01e, 0xcfff, 0xc01e, 0x21, 0 + .dw 0xd040, 0xc01e, 0xd07f, 0xc01e, 0x21, 0 + .dw 0xd0c0, 0xc01e, 0xd0ff, 0xc01e, 0x21, 0 + .dw 0xd140, 0xc01e, 0xd17f, 0xc01e, 0x21, 0 + .dw 0xd1c0, 0xc01e, 0xd1ff, 0xc01e, 0x21, 0 + .dw 0xd240, 0xc01e, 0xd27f, 0xc01e, 0x21, 0 + .dw 0xd2c0, 0xc01e, 0xd2ff, 0xc01e, 0x21, 0 + .dw 0xd340, 0xc01e, 0xd37f, 0xc01e, 0x21, 0 + .dw 0xd3c0, 0xc01e, 0xd3ff, 0xc01e, 0x21, 0 + .dw 0xd440, 0xc01e, 0xd47f, 0xc01e, 0x21, 0 + .dw 0xd4c0, 0xc01e, 0xd4ff, 0xc01e, 0x21, 0 + .dw 0xd540, 0xc01e, 0xd57f, 0xc01e, 0x21, 0 + .dw 0xd5c0, 0xc01e, 0xd5ff, 0xc01e, 0x21, 0 + .dw 0xd640, 0xc01e, 0xd67f, 0xc01e, 0x21, 0 + .dw 0xd6c0, 0xc01e, 0xd6ff, 0xc01e, 0x21, 0 + .dw 0xd740, 0xc01e, 0xd77f, 0xc01e, 0x21, 0 + .dw 0xd7c0, 0xc01e, 0xd7ff, 0xc01e, 0x21, 0 + .dw 0xd840, 0xc01e, 0xd87f, 0xc01e, 0x21, 0 + .dw 0xd8c0, 0xc01e, 0xd8ff, 0xc01e, 0x21, 0 + .dw 0xd940, 0xc01e, 0xd97f, 0xc01e, 0x21, 0 + .dw 0xd9c0, 0xc01e, 0xdfff, 0xc01e, 0x21, 0 + .dw 0xe040, 0xc01e, 0xe07f, 0xc01e, 0x21, 0 + .dw 0xe0c0, 0xc01e, 0xe0ff, 0xc01e, 0x21, 0 + .dw 0xe140, 0xc01e, 0xe17f, 0xc01e, 0x21, 0 + .dw 0xe1c0, 0xc01e, 0xe1ff, 0xc01e, 0x21, 0 + .dw 0xe240, 0xc01e, 0xe27f, 0xc01e, 0x21, 0 + .dw 0xe2c0, 0xc01e, 0xe2ff, 0xc01e, 0x21, 0 + .dw 0xe340, 0xc01e, 0xe37f, 0xc01e, 0x21, 0 + .dw 0xe3c0, 0xc01e, 0xe3ff, 0xc01e, 0x21, 0 + .dw 0xe440, 0xc01e, 0xe47f, 0xc01e, 0x21, 0 + .dw 0xe4c0, 0xc01e, 0xe4ff, 0xc01e, 0x21, 0 + .dw 0xe540, 0xc01e, 0xe57f, 0xc01e, 0x21, 0 + .dw 0xe5c0, 0xc01e, 0xe5ff, 0xc01e, 0x21, 0 + .dw 0xe640, 0xc01e, 0xe67f, 0xc01e, 0x21, 0 + .dw 0xe6c0, 0xc01e, 0xe6ff, 0xc01e, 0x21, 0 + .dw 0xe740, 0xc01e, 0xe77f, 0xc01e, 0x21, 0 + .dw 0xe7c0, 0xc01e, 0xe7ff, 0xc01e, 0x21, 0 + .dw 0xe840, 0xc01e, 0xe87f, 0xc01e, 0x21, 0 + .dw 0xe8c0, 0xc01e, 0xe8ff, 0xc01e, 0x21, 0 + .dw 0xe940, 0xc01e, 0xe97f, 0xc01e, 0x21, 0 + .dw 0xe9c0, 0xc01e, 0xe9ff, 0xc01e, 0x21, 0 + .dw 0xea40, 0xc01e, 0xea7f, 0xc01e, 0x21, 0 + .dw 0xeac0, 0xc01e, 0xeaff, 0xc01e, 0x21, 0 + .dw 0xeb40, 0xc01e, 0xeb7f, 0xc01e, 0x21, 0 + .dw 0xebc0, 0xc01e, 0xebff, 0xc01e, 0x21, 0 + .dw 0xec40, 0xc01e, 0xec7f, 0xc01e, 0x21, 0 + .dw 0xecc0, 0xc01e, 0xecff, 0xc01e, 0x21, 0 + .dw 0xed40, 0xc01e, 0xed7f, 0xc01e, 0x21, 0 + .dw 0xedc0, 0xc01e, 0xedff, 0xc01e, 0x21, 0 + .dw 0xee40, 0xc01e, 0xee7f, 0xc01e, 0x21, 0 + .dw 0xeec0, 0xc01e, 0xeeff, 0xc01e, 0x21, 0 + .dw 0xef40, 0xc01e, 0xef7f, 0xc01e, 0x21, 0 + .dw 0xefc0, 0xc01e, 0xefff, 0xc01e, 0x21, 0 + .dw 0xf040, 0xc01e, 0xf07f, 0xc01e, 0x21, 0 + .dw 0xf0c0, 0xc01e, 0xf0ff, 0xc01e, 0x21, 0 + .dw 0xf140, 0xc01e, 0xf17f, 0xc01e, 0x21, 0 + .dw 0xf1c0, 0xc01e, 0xf1ff, 0xc01e, 0x21, 0 + .dw 0xf240, 0xc01e, 0xf27f, 0xc01e, 0x21, 0 + .dw 0xf2c0, 0xc01e, 0xf2ff, 0xc01e, 0x21, 0 + .dw 0xf340, 0xc01e, 0xf37f, 0xc01e, 0x21, 0 + .dw 0xf3c0, 0xc01e, 0xf3ff, 0xc01e, 0x21, 0 + .dw 0xf440, 0xc01e, 0xf47f, 0xc01e, 0x21, 0 + .dw 0xf4c0, 0xc01e, 0xf4ff, 0xc01e, 0x21, 0 + .dw 0xf540, 0xc01e, 0xf57f, 0xc01e, 0x21, 0 + .dw 0xf5c0, 0xc01e, 0xf5ff, 0xc01e, 0x21, 0 + .dw 0xf640, 0xc01e, 0xf67f, 0xc01e, 0x21, 0 + .dw 0xf6c0, 0xc01e, 0xf6ff, 0xc01e, 0x21, 0 + .dw 0xf740, 0xc01e, 0xf77f, 0xc01e, 0x21, 0 + .dw 0xf7c0, 0xc01e, 0xf7ff, 0xc01e, 0x21, 0 + .dw 0xf840, 0xc01e, 0xf87f, 0xc01e, 0x21, 0 + .dw 0xf8c0, 0xc01e, 0xf8ff, 0xc01e, 0x21, 0 + .dw 0xf940, 0xc01e, 0xf97f, 0xc01e, 0x21, 0 + .dw 0xf9c0, 0xc01e, 0xffff, 0xc01e, 0x21, 0 + .dw 0x0040, 0xc01f, 0x007f, 0xc01f, 0x21, 0 + .dw 0x00c0, 0xc01f, 0x00ff, 0xc01f, 0x21, 0 + .dw 0x0140, 0xc01f, 0x017f, 0xc01f, 0x21, 0 + .dw 0x01c0, 0xc01f, 0x01ff, 0xc01f, 0x21, 0 + .dw 0x0240, 0xc01f, 0x027f, 0xc01f, 0x21, 0 + .dw 0x02c0, 0xc01f, 0x02ff, 0xc01f, 0x21, 0 + .dw 0x0340, 0xc01f, 0x037f, 0xc01f, 0x21, 0 + .dw 0x03c0, 0xc01f, 0x03ff, 0xc01f, 0x21, 0 + .dw 0x0440, 0xc01f, 0x047f, 0xc01f, 0x21, 0 + .dw 0x04c0, 0xc01f, 0x04ff, 0xc01f, 0x21, 0 + .dw 0x0540, 0xc01f, 0x057f, 0xc01f, 0x21, 0 + .dw 0x05c0, 0xc01f, 0x05ff, 0xc01f, 0x21, 0 + .dw 0x0640, 0xc01f, 0x067f, 0xc01f, 0x21, 0 + .dw 0x06c0, 0xc01f, 0x06ff, 0xc01f, 0x21, 0 + .dw 0x0740, 0xc01f, 0x077f, 0xc01f, 0x21, 0 + .dw 0x07c0, 0xc01f, 0x07ff, 0xc01f, 0x21, 0 + .dw 0x0840, 0xc01f, 0x087f, 0xc01f, 0x21, 0 + .dw 0x08c0, 0xc01f, 0x08ff, 0xc01f, 0x21, 0 + .dw 0x0940, 0xc01f, 0x097f, 0xc01f, 0x21, 0 + .dw 0x09c0, 0xc01f, 0x09ff, 0xc01f, 0x21, 0 + .dw 0x0a40, 0xc01f, 0x0a7f, 0xc01f, 0x21, 0 + .dw 0x0ac0, 0xc01f, 0x0aff, 0xc01f, 0x21, 0 + .dw 0x0b40, 0xc01f, 0x0b7f, 0xc01f, 0x21, 0 + .dw 0x0bc0, 0xc01f, 0x0bff, 0xc01f, 0x21, 0 + .dw 0x0c40, 0xc01f, 0x0c7f, 0xc01f, 0x21, 0 + .dw 0x0cc0, 0xc01f, 0x0cff, 0xc01f, 0x21, 0 + .dw 0x0d40, 0xc01f, 0x0d7f, 0xc01f, 0x21, 0 + .dw 0x0dc0, 0xc01f, 0x0dff, 0xc01f, 0x21, 0 + .dw 0x0e40, 0xc01f, 0x0e7f, 0xc01f, 0x21, 0 + .dw 0x0ec0, 0xc01f, 0x0eff, 0xc01f, 0x21, 0 + .dw 0x0f40, 0xc01f, 0x0f7f, 0xc01f, 0x21, 0 + .dw 0x0fc0, 0xc01f, 0x0fff, 0xc01f, 0x21, 0 + .dw 0x1040, 0xc01f, 0x107f, 0xc01f, 0x21, 0 + .dw 0x10c0, 0xc01f, 0x10ff, 0xc01f, 0x21, 0 + .dw 0x1140, 0xc01f, 0x117f, 0xc01f, 0x21, 0 + .dw 0x11c0, 0xc01f, 0x11ff, 0xc01f, 0x21, 0 + .dw 0x1240, 0xc01f, 0x127f, 0xc01f, 0x21, 0 + .dw 0x12c0, 0xc01f, 0x12ff, 0xc01f, 0x21, 0 + .dw 0x1340, 0xc01f, 0x137f, 0xc01f, 0x21, 0 + .dw 0x13c0, 0xc01f, 0x13ff, 0xc01f, 0x21, 0 + .dw 0x1440, 0xc01f, 0x147f, 0xc01f, 0x21, 0 + .dw 0x14c0, 0xc01f, 0x14ff, 0xc01f, 0x21, 0 + .dw 0x1540, 0xc01f, 0x157f, 0xc01f, 0x21, 0 + .dw 0x15c0, 0xc01f, 0x15ff, 0xc01f, 0x21, 0 + .dw 0x1640, 0xc01f, 0x167f, 0xc01f, 0x21, 0 + .dw 0x16c0, 0xc01f, 0x16ff, 0xc01f, 0x21, 0 + .dw 0x1740, 0xc01f, 0x177f, 0xc01f, 0x21, 0 + .dw 0x17c0, 0xc01f, 0x17ff, 0xc01f, 0x21, 0 + .dw 0x1840, 0xc01f, 0x187f, 0xc01f, 0x21, 0 + .dw 0x18c0, 0xc01f, 0x18ff, 0xc01f, 0x21, 0 + .dw 0x1940, 0xc01f, 0x197f, 0xc01f, 0x21, 0 + .dw 0x19c0, 0xc01f, 0x1fff, 0xc01f, 0x21, 0 + .dw 0x2040, 0xc01f, 0x207f, 0xc01f, 0x21, 0 + .dw 0x20c0, 0xc01f, 0x20ff, 0xc01f, 0x21, 0 + .dw 0x2140, 0xc01f, 0x217f, 0xc01f, 0x21, 0 + .dw 0x21c0, 0xc01f, 0x21ff, 0xc01f, 0x21, 0 + .dw 0x2240, 0xc01f, 0x227f, 0xc01f, 0x21, 0 + .dw 0x22c0, 0xc01f, 0x22ff, 0xc01f, 0x21, 0 + .dw 0x2340, 0xc01f, 0x237f, 0xc01f, 0x21, 0 + .dw 0x23c0, 0xc01f, 0x23ff, 0xc01f, 0x21, 0 + .dw 0x2440, 0xc01f, 0x247f, 0xc01f, 0x21, 0 + .dw 0x24c0, 0xc01f, 0x24ff, 0xc01f, 0x21, 0 + .dw 0x2540, 0xc01f, 0x257f, 0xc01f, 0x21, 0 + .dw 0x25c0, 0xc01f, 0x25ff, 0xc01f, 0x21, 0 + .dw 0x2640, 0xc01f, 0x267f, 0xc01f, 0x21, 0 + .dw 0x26c0, 0xc01f, 0x26ff, 0xc01f, 0x21, 0 + .dw 0x2740, 0xc01f, 0x277f, 0xc01f, 0x21, 0 + .dw 0x27c0, 0xc01f, 0x27ff, 0xc01f, 0x21, 0 + .dw 0x2840, 0xc01f, 0x287f, 0xc01f, 0x21, 0 + .dw 0x28c0, 0xc01f, 0x28ff, 0xc01f, 0x21, 0 + .dw 0x2940, 0xc01f, 0x297f, 0xc01f, 0x21, 0 + .dw 0x29c0, 0xc01f, 0x29ff, 0xc01f, 0x21, 0 + .dw 0x2a40, 0xc01f, 0x2a7f, 0xc01f, 0x21, 0 + .dw 0x2ac0, 0xc01f, 0x2aff, 0xc01f, 0x21, 0 + .dw 0x2b40, 0xc01f, 0x2b7f, 0xc01f, 0x21, 0 + .dw 0x2bc0, 0xc01f, 0x2bff, 0xc01f, 0x21, 0 + .dw 0x2c40, 0xc01f, 0x2c7f, 0xc01f, 0x21, 0 + .dw 0x2cc0, 0xc01f, 0x2cff, 0xc01f, 0x21, 0 + .dw 0x2d40, 0xc01f, 0x2d7f, 0xc01f, 0x21, 0 + .dw 0x2dc0, 0xc01f, 0x2dff, 0xc01f, 0x21, 0 + .dw 0x2e40, 0xc01f, 0x2e7f, 0xc01f, 0x21, 0 + .dw 0x2ec0, 0xc01f, 0x2eff, 0xc01f, 0x21, 0 + .dw 0x2f40, 0xc01f, 0x2f7f, 0xc01f, 0x21, 0 + .dw 0x2fc0, 0xc01f, 0x2fff, 0xc01f, 0x21, 0 + .dw 0x3040, 0xc01f, 0x307f, 0xc01f, 0x21, 0 + .dw 0x30c0, 0xc01f, 0x30ff, 0xc01f, 0x21, 0 + .dw 0x3140, 0xc01f, 0x317f, 0xc01f, 0x21, 0 + .dw 0x31c0, 0xc01f, 0x31ff, 0xc01f, 0x21, 0 + .dw 0x3240, 0xc01f, 0x327f, 0xc01f, 0x21, 0 + .dw 0x32c0, 0xc01f, 0x32ff, 0xc01f, 0x21, 0 + .dw 0x3340, 0xc01f, 0x337f, 0xc01f, 0x21, 0 + .dw 0x33c0, 0xc01f, 0x33ff, 0xc01f, 0x21, 0 + .dw 0x3440, 0xc01f, 0x347f, 0xc01f, 0x21, 0 + .dw 0x34c0, 0xc01f, 0x34ff, 0xc01f, 0x21, 0 + .dw 0x3540, 0xc01f, 0x357f, 0xc01f, 0x21, 0 + .dw 0x35c0, 0xc01f, 0x35ff, 0xc01f, 0x21, 0 + .dw 0x3640, 0xc01f, 0x367f, 0xc01f, 0x21, 0 + .dw 0x36c0, 0xc01f, 0x36ff, 0xc01f, 0x21, 0 + .dw 0x3740, 0xc01f, 0x377f, 0xc01f, 0x21, 0 + .dw 0x37c0, 0xc01f, 0x37ff, 0xc01f, 0x21, 0 + .dw 0x3840, 0xc01f, 0x387f, 0xc01f, 0x21, 0 + .dw 0x38c0, 0xc01f, 0x38ff, 0xc01f, 0x21, 0 + .dw 0x3940, 0xc01f, 0x397f, 0xc01f, 0x21, 0 + .dw 0x39c0, 0xc01f, 0x1fff, 0xc020, 0x21, 0 + .dw 0x3a00, 0xc020, 0x5fff, 0xc020, 0x21, 0 + .dw 0x7a00, 0xc020, 0x9fff, 0xc020, 0x21, 0 + .dw 0xba00, 0xc020, 0xdfff, 0xc020, 0x21, 0 + .dw 0xfa00, 0xc020, 0x1fff, 0xc021, 0x21, 0 + .dw 0x3a00, 0xc021, 0x5fff, 0xc021, 0x21, 0 + .dw 0x7a00, 0xc021, 0x9fff, 0xc021, 0x21, 0 + .dw 0xba00, 0xc021, 0xdfff, 0xc021, 0x21, 0 + .dw 0xfa00, 0xc021, 0x1fff, 0xc022, 0x21, 0 + .dw 0x3a00, 0xc022, 0x5fff, 0xc022, 0x21, 0 + .dw 0x7a00, 0xc022, 0x9fff, 0xc022, 0x21, 0 + .dw 0xba00, 0xc022, 0xdfff, 0xc022, 0x21, 0 + .dw 0xfa00, 0xc022, 0x1fff, 0xc023, 0x21, 0 + .dw 0x3a00, 0xc023, 0xffff, 0xc023, 0x21, 0 + .dw 0x1a00, 0xc024, 0x1fff, 0xc024, 0x21, 0 + .dw 0x3a00, 0xc024, 0x3fff, 0xc024, 0x21, 0 + .dw 0x5a00, 0xc024, 0x5fff, 0xc024, 0x21, 0 + .dw 0x7a00, 0xc024, 0x7fff, 0xc024, 0x21, 0 + .dw 0x9a00, 0xc024, 0x9fff, 0xc024, 0x21, 0 + .dw 0xba00, 0xc024, 0xbfff, 0xc024, 0x21, 0 + .dw 0xda00, 0xc024, 0xdfff, 0xc024, 0x21, 0 + .dw 0xfa00, 0xc024, 0xffff, 0xc024, 0x21, 0 + .dw 0x1a00, 0xc025, 0x1fff, 0xc025, 0x21, 0 + .dw 0x3a00, 0xc025, 0x3fff, 0xc025, 0x21, 0 + .dw 0x5a00, 0xc025, 0x5fff, 0xc025, 0x21, 0 + .dw 0x7a00, 0xc025, 0x7fff, 0xc025, 0x21, 0 + .dw 0x9a00, 0xc025, 0x9fff, 0xc025, 0x21, 0 + .dw 0xba00, 0xc025, 0xbfff, 0xc025, 0x21, 0 + .dw 0xda00, 0xc025, 0xdfff, 0xc025, 0x21, 0 + .dw 0xfa00, 0xc025, 0xffff, 0xc025, 0x21, 0 + .dw 0x1a00, 0xc026, 0x1fff, 0xc026, 0x21, 0 + .dw 0x3a00, 0xc026, 0x3fff, 0xc026, 0x21, 0 + .dw 0x5a00, 0xc026, 0x5fff, 0xc026, 0x21, 0 + .dw 0x7a00, 0xc026, 0x7fff, 0xc026, 0x21, 0 + .dw 0x9a00, 0xc026, 0x9fff, 0xc026, 0x21, 0 + .dw 0xba00, 0xc026, 0xbfff, 0xc026, 0x21, 0 + .dw 0xda00, 0xc026, 0xdfff, 0xc026, 0x21, 0 + .dw 0xfa00, 0xc026, 0xffff, 0xc026, 0x21, 0 + .dw 0x1a00, 0xc027, 0x1fff, 0xc027, 0x21, 0 + .dw 0x3a00, 0xc027, 0x1fff, 0xc028, 0x21, 0 + .dw 0x2040, 0xc028, 0x207f, 0xc028, 0x21, 0 + .dw 0x20c0, 0xc028, 0x20ff, 0xc028, 0x21, 0 + .dw 0x2140, 0xc028, 0x217f, 0xc028, 0x21, 0 + .dw 0x21c0, 0xc028, 0x21ff, 0xc028, 0x21, 0 + .dw 0x2240, 0xc028, 0x227f, 0xc028, 0x21, 0 + .dw 0x22c0, 0xc028, 0x22ff, 0xc028, 0x21, 0 + .dw 0x2340, 0xc028, 0x237f, 0xc028, 0x21, 0 + .dw 0x23c0, 0xc028, 0x23ff, 0xc028, 0x21, 0 + .dw 0x2440, 0xc028, 0x247f, 0xc028, 0x21, 0 + .dw 0x24c0, 0xc028, 0x24ff, 0xc028, 0x21, 0 + .dw 0x2540, 0xc028, 0x257f, 0xc028, 0x21, 0 + .dw 0x25c0, 0xc028, 0x25ff, 0xc028, 0x21, 0 + .dw 0x2640, 0xc028, 0x267f, 0xc028, 0x21, 0 + .dw 0x26c0, 0xc028, 0x26ff, 0xc028, 0x21, 0 + .dw 0x2740, 0xc028, 0x277f, 0xc028, 0x21, 0 + .dw 0x27c0, 0xc028, 0x27ff, 0xc028, 0x21, 0 + .dw 0x2840, 0xc028, 0x287f, 0xc028, 0x21, 0 + .dw 0x28c0, 0xc028, 0x28ff, 0xc028, 0x21, 0 + .dw 0x2940, 0xc028, 0x297f, 0xc028, 0x21, 0 + .dw 0x29c0, 0xc028, 0x29ff, 0xc028, 0x21, 0 + .dw 0x2a40, 0xc028, 0x2a7f, 0xc028, 0x21, 0 + .dw 0x2ac0, 0xc028, 0x2aff, 0xc028, 0x21, 0 + .dw 0x2b40, 0xc028, 0x2b7f, 0xc028, 0x21, 0 + .dw 0x2bc0, 0xc028, 0x2bff, 0xc028, 0x21, 0 + .dw 0x2c40, 0xc028, 0x2c7f, 0xc028, 0x21, 0 + .dw 0x2cc0, 0xc028, 0x2cff, 0xc028, 0x21, 0 + .dw 0x2d40, 0xc028, 0x2d7f, 0xc028, 0x21, 0 + .dw 0x2dc0, 0xc028, 0x2dff, 0xc028, 0x21, 0 + .dw 0x2e40, 0xc028, 0x2e7f, 0xc028, 0x21, 0 + .dw 0x2ec0, 0xc028, 0x2eff, 0xc028, 0x21, 0 + .dw 0x2f40, 0xc028, 0x2f7f, 0xc028, 0x21, 0 + .dw 0x2fc0, 0xc028, 0x2fff, 0xc028, 0x21, 0 + .dw 0x3040, 0xc028, 0x307f, 0xc028, 0x21, 0 + .dw 0x30c0, 0xc028, 0x30ff, 0xc028, 0x21, 0 + .dw 0x3140, 0xc028, 0x317f, 0xc028, 0x21, 0 + .dw 0x31c0, 0xc028, 0x31ff, 0xc028, 0x21, 0 + .dw 0x3240, 0xc028, 0x327f, 0xc028, 0x21, 0 + .dw 0x32c0, 0xc028, 0x32ff, 0xc028, 0x21, 0 + .dw 0x3340, 0xc028, 0x337f, 0xc028, 0x21, 0 + .dw 0x33c0, 0xc028, 0x33ff, 0xc028, 0x21, 0 + .dw 0x3440, 0xc028, 0x347f, 0xc028, 0x21, 0 + .dw 0x34c0, 0xc028, 0x34ff, 0xc028, 0x21, 0 + .dw 0x3540, 0xc028, 0x357f, 0xc028, 0x21, 0 + .dw 0x35c0, 0xc028, 0x35ff, 0xc028, 0x21, 0 + .dw 0x3640, 0xc028, 0x367f, 0xc028, 0x21, 0 + .dw 0x36c0, 0xc028, 0x36ff, 0xc028, 0x21, 0 + .dw 0x3740, 0xc028, 0x377f, 0xc028, 0x21, 0 + .dw 0x37c0, 0xc028, 0x37ff, 0xc028, 0x21, 0 + .dw 0x3840, 0xc028, 0x387f, 0xc028, 0x21, 0 + .dw 0x38c0, 0xc028, 0x38ff, 0xc028, 0x21, 0 + .dw 0x3940, 0xc028, 0x397f, 0xc028, 0x21, 0 + .dw 0x39c0, 0xc028, 0x5fff, 0xc028, 0x21, 0 + .dw 0x6040, 0xc028, 0x607f, 0xc028, 0x21, 0 + .dw 0x60c0, 0xc028, 0x60ff, 0xc028, 0x21, 0 + .dw 0x6140, 0xc028, 0x617f, 0xc028, 0x21, 0 + .dw 0x61c0, 0xc028, 0x61ff, 0xc028, 0x21, 0 + .dw 0x6240, 0xc028, 0x627f, 0xc028, 0x21, 0 + .dw 0x62c0, 0xc028, 0x62ff, 0xc028, 0x21, 0 + .dw 0x6340, 0xc028, 0x637f, 0xc028, 0x21, 0 + .dw 0x63c0, 0xc028, 0x63ff, 0xc028, 0x21, 0 + .dw 0x6440, 0xc028, 0x647f, 0xc028, 0x21, 0 + .dw 0x64c0, 0xc028, 0x64ff, 0xc028, 0x21, 0 + .dw 0x6540, 0xc028, 0x657f, 0xc028, 0x21, 0 + .dw 0x65c0, 0xc028, 0x65ff, 0xc028, 0x21, 0 + .dw 0x6640, 0xc028, 0x667f, 0xc028, 0x21, 0 + .dw 0x66c0, 0xc028, 0x66ff, 0xc028, 0x21, 0 + .dw 0x6740, 0xc028, 0x677f, 0xc028, 0x21, 0 + .dw 0x67c0, 0xc028, 0x67ff, 0xc028, 0x21, 0 + .dw 0x6840, 0xc028, 0x687f, 0xc028, 0x21, 0 + .dw 0x68c0, 0xc028, 0x68ff, 0xc028, 0x21, 0 + .dw 0x6940, 0xc028, 0x697f, 0xc028, 0x21, 0 + .dw 0x69c0, 0xc028, 0x69ff, 0xc028, 0x21, 0 + .dw 0x6a40, 0xc028, 0x6a7f, 0xc028, 0x21, 0 + .dw 0x6ac0, 0xc028, 0x6aff, 0xc028, 0x21, 0 + .dw 0x6b40, 0xc028, 0x6b7f, 0xc028, 0x21, 0 + .dw 0x6bc0, 0xc028, 0x6bff, 0xc028, 0x21, 0 + .dw 0x6c40, 0xc028, 0x6c7f, 0xc028, 0x21, 0 + .dw 0x6cc0, 0xc028, 0x6cff, 0xc028, 0x21, 0 + .dw 0x6d40, 0xc028, 0x6d7f, 0xc028, 0x21, 0 + .dw 0x6dc0, 0xc028, 0x6dff, 0xc028, 0x21, 0 + .dw 0x6e40, 0xc028, 0x6e7f, 0xc028, 0x21, 0 + .dw 0x6ec0, 0xc028, 0x6eff, 0xc028, 0x21, 0 + .dw 0x6f40, 0xc028, 0x6f7f, 0xc028, 0x21, 0 + .dw 0x6fc0, 0xc028, 0x6fff, 0xc028, 0x21, 0 + .dw 0x7040, 0xc028, 0x707f, 0xc028, 0x21, 0 + .dw 0x70c0, 0xc028, 0x70ff, 0xc028, 0x21, 0 + .dw 0x7140, 0xc028, 0x717f, 0xc028, 0x21, 0 + .dw 0x71c0, 0xc028, 0x71ff, 0xc028, 0x21, 0 + .dw 0x7240, 0xc028, 0x727f, 0xc028, 0x21, 0 + .dw 0x72c0, 0xc028, 0x72ff, 0xc028, 0x21, 0 + .dw 0x7340, 0xc028, 0x737f, 0xc028, 0x21, 0 + .dw 0x73c0, 0xc028, 0x73ff, 0xc028, 0x21, 0 + .dw 0x7440, 0xc028, 0x747f, 0xc028, 0x21, 0 + .dw 0x74c0, 0xc028, 0x74ff, 0xc028, 0x21, 0 + .dw 0x7540, 0xc028, 0x757f, 0xc028, 0x21, 0 + .dw 0x75c0, 0xc028, 0x75ff, 0xc028, 0x21, 0 + .dw 0x7640, 0xc028, 0x767f, 0xc028, 0x21, 0 + .dw 0x76c0, 0xc028, 0x76ff, 0xc028, 0x21, 0 + .dw 0x7740, 0xc028, 0x777f, 0xc028, 0x21, 0 + .dw 0x77c0, 0xc028, 0x77ff, 0xc028, 0x21, 0 + .dw 0x7840, 0xc028, 0x787f, 0xc028, 0x21, 0 + .dw 0x78c0, 0xc028, 0x78ff, 0xc028, 0x21, 0 + .dw 0x7940, 0xc028, 0x797f, 0xc028, 0x21, 0 + .dw 0x79c0, 0xc028, 0x9fff, 0xc028, 0x21, 0 + .dw 0xa040, 0xc028, 0xa07f, 0xc028, 0x21, 0 + .dw 0xa0c0, 0xc028, 0xa0ff, 0xc028, 0x21, 0 + .dw 0xa140, 0xc028, 0xa17f, 0xc028, 0x21, 0 + .dw 0xa1c0, 0xc028, 0xa1ff, 0xc028, 0x21, 0 + .dw 0xa240, 0xc028, 0xa27f, 0xc028, 0x21, 0 + .dw 0xa2c0, 0xc028, 0xa2ff, 0xc028, 0x21, 0 + .dw 0xa340, 0xc028, 0xa37f, 0xc028, 0x21, 0 + .dw 0xa3c0, 0xc028, 0xa3ff, 0xc028, 0x21, 0 + .dw 0xa440, 0xc028, 0xa47f, 0xc028, 0x21, 0 + .dw 0xa4c0, 0xc028, 0xa4ff, 0xc028, 0x21, 0 + .dw 0xa540, 0xc028, 0xa57f, 0xc028, 0x21, 0 + .dw 0xa5c0, 0xc028, 0xa5ff, 0xc028, 0x21, 0 + .dw 0xa640, 0xc028, 0xa67f, 0xc028, 0x21, 0 + .dw 0xa6c0, 0xc028, 0xa6ff, 0xc028, 0x21, 0 + .dw 0xa740, 0xc028, 0xa77f, 0xc028, 0x21, 0 + .dw 0xa7c0, 0xc028, 0xa7ff, 0xc028, 0x21, 0 + .dw 0xa840, 0xc028, 0xa87f, 0xc028, 0x21, 0 + .dw 0xa8c0, 0xc028, 0xa8ff, 0xc028, 0x21, 0 + .dw 0xa940, 0xc028, 0xa97f, 0xc028, 0x21, 0 + .dw 0xa9c0, 0xc028, 0xa9ff, 0xc028, 0x21, 0 + .dw 0xaa40, 0xc028, 0xaa7f, 0xc028, 0x21, 0 + .dw 0xaac0, 0xc028, 0xaaff, 0xc028, 0x21, 0 + .dw 0xab40, 0xc028, 0xab7f, 0xc028, 0x21, 0 + .dw 0xabc0, 0xc028, 0xabff, 0xc028, 0x21, 0 + .dw 0xac40, 0xc028, 0xac7f, 0xc028, 0x21, 0 + .dw 0xacc0, 0xc028, 0xacff, 0xc028, 0x21, 0 + .dw 0xad40, 0xc028, 0xad7f, 0xc028, 0x21, 0 + .dw 0xadc0, 0xc028, 0xadff, 0xc028, 0x21, 0 + .dw 0xae40, 0xc028, 0xae7f, 0xc028, 0x21, 0 + .dw 0xaec0, 0xc028, 0xaeff, 0xc028, 0x21, 0 + .dw 0xaf40, 0xc028, 0xaf7f, 0xc028, 0x21, 0 + .dw 0xafc0, 0xc028, 0xafff, 0xc028, 0x21, 0 + .dw 0xb040, 0xc028, 0xb07f, 0xc028, 0x21, 0 + .dw 0xb0c0, 0xc028, 0xb0ff, 0xc028, 0x21, 0 + .dw 0xb140, 0xc028, 0xb17f, 0xc028, 0x21, 0 + .dw 0xb1c0, 0xc028, 0xb1ff, 0xc028, 0x21, 0 + .dw 0xb240, 0xc028, 0xb27f, 0xc028, 0x21, 0 + .dw 0xb2c0, 0xc028, 0xb2ff, 0xc028, 0x21, 0 + .dw 0xb340, 0xc028, 0xb37f, 0xc028, 0x21, 0 + .dw 0xb3c0, 0xc028, 0xb3ff, 0xc028, 0x21, 0 + .dw 0xb440, 0xc028, 0xb47f, 0xc028, 0x21, 0 + .dw 0xb4c0, 0xc028, 0xb4ff, 0xc028, 0x21, 0 + .dw 0xb540, 0xc028, 0xb57f, 0xc028, 0x21, 0 + .dw 0xb5c0, 0xc028, 0xb5ff, 0xc028, 0x21, 0 + .dw 0xb640, 0xc028, 0xb67f, 0xc028, 0x21, 0 + .dw 0xb6c0, 0xc028, 0xb6ff, 0xc028, 0x21, 0 + .dw 0xb740, 0xc028, 0xb77f, 0xc028, 0x21, 0 + .dw 0xb7c0, 0xc028, 0xb7ff, 0xc028, 0x21, 0 + .dw 0xb840, 0xc028, 0xb87f, 0xc028, 0x21, 0 + .dw 0xb8c0, 0xc028, 0xb8ff, 0xc028, 0x21, 0 + .dw 0xb940, 0xc028, 0xb97f, 0xc028, 0x21, 0 + .dw 0xb9c0, 0xc028, 0xdfff, 0xc028, 0x21, 0 + .dw 0xe040, 0xc028, 0xe07f, 0xc028, 0x21, 0 + .dw 0xe0c0, 0xc028, 0xe0ff, 0xc028, 0x21, 0 + .dw 0xe140, 0xc028, 0xe17f, 0xc028, 0x21, 0 + .dw 0xe1c0, 0xc028, 0xe1ff, 0xc028, 0x21, 0 + .dw 0xe240, 0xc028, 0xe27f, 0xc028, 0x21, 0 + .dw 0xe2c0, 0xc028, 0xe2ff, 0xc028, 0x21, 0 + .dw 0xe340, 0xc028, 0xe37f, 0xc028, 0x21, 0 + .dw 0xe3c0, 0xc028, 0xe3ff, 0xc028, 0x21, 0 + .dw 0xe440, 0xc028, 0xe47f, 0xc028, 0x21, 0 + .dw 0xe4c0, 0xc028, 0xe4ff, 0xc028, 0x21, 0 + .dw 0xe540, 0xc028, 0xe57f, 0xc028, 0x21, 0 + .dw 0xe5c0, 0xc028, 0xe5ff, 0xc028, 0x21, 0 + .dw 0xe640, 0xc028, 0xe67f, 0xc028, 0x21, 0 + .dw 0xe6c0, 0xc028, 0xe6ff, 0xc028, 0x21, 0 + .dw 0xe740, 0xc028, 0xe77f, 0xc028, 0x21, 0 + .dw 0xe7c0, 0xc028, 0xe7ff, 0xc028, 0x21, 0 + .dw 0xe840, 0xc028, 0xe87f, 0xc028, 0x21, 0 + .dw 0xe8c0, 0xc028, 0xe8ff, 0xc028, 0x21, 0 + .dw 0xe940, 0xc028, 0xe97f, 0xc028, 0x21, 0 + .dw 0xe9c0, 0xc028, 0xe9ff, 0xc028, 0x21, 0 + .dw 0xea40, 0xc028, 0xea7f, 0xc028, 0x21, 0 + .dw 0xeac0, 0xc028, 0xeaff, 0xc028, 0x21, 0 + .dw 0xeb40, 0xc028, 0xeb7f, 0xc028, 0x21, 0 + .dw 0xebc0, 0xc028, 0xebff, 0xc028, 0x21, 0 + .dw 0xec40, 0xc028, 0xec7f, 0xc028, 0x21, 0 + .dw 0xecc0, 0xc028, 0xecff, 0xc028, 0x21, 0 + .dw 0xed40, 0xc028, 0xed7f, 0xc028, 0x21, 0 + .dw 0xedc0, 0xc028, 0xedff, 0xc028, 0x21, 0 + .dw 0xee40, 0xc028, 0xee7f, 0xc028, 0x21, 0 + .dw 0xeec0, 0xc028, 0xeeff, 0xc028, 0x21, 0 + .dw 0xef40, 0xc028, 0xef7f, 0xc028, 0x21, 0 + .dw 0xefc0, 0xc028, 0xefff, 0xc028, 0x21, 0 + .dw 0xf040, 0xc028, 0xf07f, 0xc028, 0x21, 0 + .dw 0xf0c0, 0xc028, 0xf0ff, 0xc028, 0x21, 0 + .dw 0xf140, 0xc028, 0xf17f, 0xc028, 0x21, 0 + .dw 0xf1c0, 0xc028, 0xf1ff, 0xc028, 0x21, 0 + .dw 0xf240, 0xc028, 0xf27f, 0xc028, 0x21, 0 + .dw 0xf2c0, 0xc028, 0xf2ff, 0xc028, 0x21, 0 + .dw 0xf340, 0xc028, 0xf37f, 0xc028, 0x21, 0 + .dw 0xf3c0, 0xc028, 0xf3ff, 0xc028, 0x21, 0 + .dw 0xf440, 0xc028, 0xf47f, 0xc028, 0x21, 0 + .dw 0xf4c0, 0xc028, 0xf4ff, 0xc028, 0x21, 0 + .dw 0xf540, 0xc028, 0xf57f, 0xc028, 0x21, 0 + .dw 0xf5c0, 0xc028, 0xf5ff, 0xc028, 0x21, 0 + .dw 0xf640, 0xc028, 0xf67f, 0xc028, 0x21, 0 + .dw 0xf6c0, 0xc028, 0xf6ff, 0xc028, 0x21, 0 + .dw 0xf740, 0xc028, 0xf77f, 0xc028, 0x21, 0 + .dw 0xf7c0, 0xc028, 0xf7ff, 0xc028, 0x21, 0 + .dw 0xf840, 0xc028, 0xf87f, 0xc028, 0x21, 0 + .dw 0xf8c0, 0xc028, 0xf8ff, 0xc028, 0x21, 0 + .dw 0xf940, 0xc028, 0xf97f, 0xc028, 0x21, 0 + .dw 0xf9c0, 0xc028, 0x1fff, 0xc029, 0x21, 0 + .dw 0x2040, 0xc029, 0x207f, 0xc029, 0x21, 0 + .dw 0x20c0, 0xc029, 0x20ff, 0xc029, 0x21, 0 + .dw 0x2140, 0xc029, 0x217f, 0xc029, 0x21, 0 + .dw 0x21c0, 0xc029, 0x21ff, 0xc029, 0x21, 0 + .dw 0x2240, 0xc029, 0x227f, 0xc029, 0x21, 0 + .dw 0x22c0, 0xc029, 0x22ff, 0xc029, 0x21, 0 + .dw 0x2340, 0xc029, 0x237f, 0xc029, 0x21, 0 + .dw 0x23c0, 0xc029, 0x23ff, 0xc029, 0x21, 0 + .dw 0x2440, 0xc029, 0x247f, 0xc029, 0x21, 0 + .dw 0x24c0, 0xc029, 0x24ff, 0xc029, 0x21, 0 + .dw 0x2540, 0xc029, 0x257f, 0xc029, 0x21, 0 + .dw 0x25c0, 0xc029, 0x25ff, 0xc029, 0x21, 0 + .dw 0x2640, 0xc029, 0x267f, 0xc029, 0x21, 0 + .dw 0x26c0, 0xc029, 0x26ff, 0xc029, 0x21, 0 + .dw 0x2740, 0xc029, 0x277f, 0xc029, 0x21, 0 + .dw 0x27c0, 0xc029, 0x27ff, 0xc029, 0x21, 0 + .dw 0x2840, 0xc029, 0x287f, 0xc029, 0x21, 0 + .dw 0x28c0, 0xc029, 0x28ff, 0xc029, 0x21, 0 + .dw 0x2940, 0xc029, 0x297f, 0xc029, 0x21, 0 + .dw 0x29c0, 0xc029, 0x29ff, 0xc029, 0x21, 0 + .dw 0x2a40, 0xc029, 0x2a7f, 0xc029, 0x21, 0 + .dw 0x2ac0, 0xc029, 0x2aff, 0xc029, 0x21, 0 + .dw 0x2b40, 0xc029, 0x2b7f, 0xc029, 0x21, 0 + .dw 0x2bc0, 0xc029, 0x2bff, 0xc029, 0x21, 0 + .dw 0x2c40, 0xc029, 0x2c7f, 0xc029, 0x21, 0 + .dw 0x2cc0, 0xc029, 0x2cff, 0xc029, 0x21, 0 + .dw 0x2d40, 0xc029, 0x2d7f, 0xc029, 0x21, 0 + .dw 0x2dc0, 0xc029, 0x2dff, 0xc029, 0x21, 0 + .dw 0x2e40, 0xc029, 0x2e7f, 0xc029, 0x21, 0 + .dw 0x2ec0, 0xc029, 0x2eff, 0xc029, 0x21, 0 + .dw 0x2f40, 0xc029, 0x2f7f, 0xc029, 0x21, 0 + .dw 0x2fc0, 0xc029, 0x2fff, 0xc029, 0x21, 0 + .dw 0x3040, 0xc029, 0x307f, 0xc029, 0x21, 0 + .dw 0x30c0, 0xc029, 0x30ff, 0xc029, 0x21, 0 + .dw 0x3140, 0xc029, 0x317f, 0xc029, 0x21, 0 + .dw 0x31c0, 0xc029, 0x31ff, 0xc029, 0x21, 0 + .dw 0x3240, 0xc029, 0x327f, 0xc029, 0x21, 0 + .dw 0x32c0, 0xc029, 0x32ff, 0xc029, 0x21, 0 + .dw 0x3340, 0xc029, 0x337f, 0xc029, 0x21, 0 + .dw 0x33c0, 0xc029, 0x33ff, 0xc029, 0x21, 0 + .dw 0x3440, 0xc029, 0x347f, 0xc029, 0x21, 0 + .dw 0x34c0, 0xc029, 0x34ff, 0xc029, 0x21, 0 + .dw 0x3540, 0xc029, 0x357f, 0xc029, 0x21, 0 + .dw 0x35c0, 0xc029, 0x35ff, 0xc029, 0x21, 0 + .dw 0x3640, 0xc029, 0x367f, 0xc029, 0x21, 0 + .dw 0x36c0, 0xc029, 0x36ff, 0xc029, 0x21, 0 + .dw 0x3740, 0xc029, 0x377f, 0xc029, 0x21, 0 + .dw 0x37c0, 0xc029, 0x37ff, 0xc029, 0x21, 0 + .dw 0x3840, 0xc029, 0x387f, 0xc029, 0x21, 0 + .dw 0x38c0, 0xc029, 0x38ff, 0xc029, 0x21, 0 + .dw 0x3940, 0xc029, 0x397f, 0xc029, 0x21, 0 + .dw 0x39c0, 0xc029, 0x5fff, 0xc029, 0x21, 0 + .dw 0x6040, 0xc029, 0x607f, 0xc029, 0x21, 0 + .dw 0x60c0, 0xc029, 0x60ff, 0xc029, 0x21, 0 + .dw 0x6140, 0xc029, 0x617f, 0xc029, 0x21, 0 + .dw 0x61c0, 0xc029, 0x61ff, 0xc029, 0x21, 0 + .dw 0x6240, 0xc029, 0x627f, 0xc029, 0x21, 0 + .dw 0x62c0, 0xc029, 0x62ff, 0xc029, 0x21, 0 + .dw 0x6340, 0xc029, 0x637f, 0xc029, 0x21, 0 + .dw 0x63c0, 0xc029, 0x63ff, 0xc029, 0x21, 0 + .dw 0x6440, 0xc029, 0x647f, 0xc029, 0x21, 0 + .dw 0x64c0, 0xc029, 0x64ff, 0xc029, 0x21, 0 + .dw 0x6540, 0xc029, 0x657f, 0xc029, 0x21, 0 + .dw 0x65c0, 0xc029, 0x65ff, 0xc029, 0x21, 0 + .dw 0x6640, 0xc029, 0x667f, 0xc029, 0x21, 0 + .dw 0x66c0, 0xc029, 0x66ff, 0xc029, 0x21, 0 + .dw 0x6740, 0xc029, 0x677f, 0xc029, 0x21, 0 + .dw 0x67c0, 0xc029, 0x67ff, 0xc029, 0x21, 0 + .dw 0x6840, 0xc029, 0x687f, 0xc029, 0x21, 0 + .dw 0x68c0, 0xc029, 0x68ff, 0xc029, 0x21, 0 + .dw 0x6940, 0xc029, 0x697f, 0xc029, 0x21, 0 + .dw 0x69c0, 0xc029, 0x69ff, 0xc029, 0x21, 0 + .dw 0x6a40, 0xc029, 0x6a7f, 0xc029, 0x21, 0 + .dw 0x6ac0, 0xc029, 0x6aff, 0xc029, 0x21, 0 + .dw 0x6b40, 0xc029, 0x6b7f, 0xc029, 0x21, 0 + .dw 0x6bc0, 0xc029, 0x6bff, 0xc029, 0x21, 0 + .dw 0x6c40, 0xc029, 0x6c7f, 0xc029, 0x21, 0 + .dw 0x6cc0, 0xc029, 0x6cff, 0xc029, 0x21, 0 + .dw 0x6d40, 0xc029, 0x6d7f, 0xc029, 0x21, 0 + .dw 0x6dc0, 0xc029, 0x6dff, 0xc029, 0x21, 0 + .dw 0x6e40, 0xc029, 0x6e7f, 0xc029, 0x21, 0 + .dw 0x6ec0, 0xc029, 0x6eff, 0xc029, 0x21, 0 + .dw 0x6f40, 0xc029, 0x6f7f, 0xc029, 0x21, 0 + .dw 0x6fc0, 0xc029, 0x6fff, 0xc029, 0x21, 0 + .dw 0x7040, 0xc029, 0x707f, 0xc029, 0x21, 0 + .dw 0x70c0, 0xc029, 0x70ff, 0xc029, 0x21, 0 + .dw 0x7140, 0xc029, 0x717f, 0xc029, 0x21, 0 + .dw 0x71c0, 0xc029, 0x71ff, 0xc029, 0x21, 0 + .dw 0x7240, 0xc029, 0x727f, 0xc029, 0x21, 0 + .dw 0x72c0, 0xc029, 0x72ff, 0xc029, 0x21, 0 + .dw 0x7340, 0xc029, 0x737f, 0xc029, 0x21, 0 + .dw 0x73c0, 0xc029, 0x73ff, 0xc029, 0x21, 0 + .dw 0x7440, 0xc029, 0x747f, 0xc029, 0x21, 0 + .dw 0x74c0, 0xc029, 0x74ff, 0xc029, 0x21, 0 + .dw 0x7540, 0xc029, 0x757f, 0xc029, 0x21, 0 + .dw 0x75c0, 0xc029, 0x75ff, 0xc029, 0x21, 0 + .dw 0x7640, 0xc029, 0x767f, 0xc029, 0x21, 0 + .dw 0x76c0, 0xc029, 0x76ff, 0xc029, 0x21, 0 + .dw 0x7740, 0xc029, 0x777f, 0xc029, 0x21, 0 + .dw 0x77c0, 0xc029, 0x77ff, 0xc029, 0x21, 0 + .dw 0x7840, 0xc029, 0x787f, 0xc029, 0x21, 0 + .dw 0x78c0, 0xc029, 0x78ff, 0xc029, 0x21, 0 + .dw 0x7940, 0xc029, 0x797f, 0xc029, 0x21, 0 + .dw 0x79c0, 0xc029, 0x9fff, 0xc029, 0x21, 0 + .dw 0xa040, 0xc029, 0xa07f, 0xc029, 0x21, 0 + .dw 0xa0c0, 0xc029, 0xa0ff, 0xc029, 0x21, 0 + .dw 0xa140, 0xc029, 0xa17f, 0xc029, 0x21, 0 + .dw 0xa1c0, 0xc029, 0xa1ff, 0xc029, 0x21, 0 + .dw 0xa240, 0xc029, 0xa27f, 0xc029, 0x21, 0 + .dw 0xa2c0, 0xc029, 0xa2ff, 0xc029, 0x21, 0 + .dw 0xa340, 0xc029, 0xa37f, 0xc029, 0x21, 0 + .dw 0xa3c0, 0xc029, 0xa3ff, 0xc029, 0x21, 0 + .dw 0xa440, 0xc029, 0xa47f, 0xc029, 0x21, 0 + .dw 0xa4c0, 0xc029, 0xa4ff, 0xc029, 0x21, 0 + .dw 0xa540, 0xc029, 0xa57f, 0xc029, 0x21, 0 + .dw 0xa5c0, 0xc029, 0xa5ff, 0xc029, 0x21, 0 + .dw 0xa640, 0xc029, 0xa67f, 0xc029, 0x21, 0 + .dw 0xa6c0, 0xc029, 0xa6ff, 0xc029, 0x21, 0 + .dw 0xa740, 0xc029, 0xa77f, 0xc029, 0x21, 0 + .dw 0xa7c0, 0xc029, 0xa7ff, 0xc029, 0x21, 0 + .dw 0xa840, 0xc029, 0xa87f, 0xc029, 0x21, 0 + .dw 0xa8c0, 0xc029, 0xa8ff, 0xc029, 0x21, 0 + .dw 0xa940, 0xc029, 0xa97f, 0xc029, 0x21, 0 + .dw 0xa9c0, 0xc029, 0xa9ff, 0xc029, 0x21, 0 + .dw 0xaa40, 0xc029, 0xaa7f, 0xc029, 0x21, 0 + .dw 0xaac0, 0xc029, 0xaaff, 0xc029, 0x21, 0 + .dw 0xab40, 0xc029, 0xab7f, 0xc029, 0x21, 0 + .dw 0xabc0, 0xc029, 0xabff, 0xc029, 0x21, 0 + .dw 0xac40, 0xc029, 0xac7f, 0xc029, 0x21, 0 + .dw 0xacc0, 0xc029, 0xacff, 0xc029, 0x21, 0 + .dw 0xad40, 0xc029, 0xad7f, 0xc029, 0x21, 0 + .dw 0xadc0, 0xc029, 0xadff, 0xc029, 0x21, 0 + .dw 0xae40, 0xc029, 0xae7f, 0xc029, 0x21, 0 + .dw 0xaec0, 0xc029, 0xaeff, 0xc029, 0x21, 0 + .dw 0xaf40, 0xc029, 0xaf7f, 0xc029, 0x21, 0 + .dw 0xafc0, 0xc029, 0xafff, 0xc029, 0x21, 0 + .dw 0xb040, 0xc029, 0xb07f, 0xc029, 0x21, 0 + .dw 0xb0c0, 0xc029, 0xb0ff, 0xc029, 0x21, 0 + .dw 0xb140, 0xc029, 0xb17f, 0xc029, 0x21, 0 + .dw 0xb1c0, 0xc029, 0xb1ff, 0xc029, 0x21, 0 + .dw 0xb240, 0xc029, 0xb27f, 0xc029, 0x21, 0 + .dw 0xb2c0, 0xc029, 0xb2ff, 0xc029, 0x21, 0 + .dw 0xb340, 0xc029, 0xb37f, 0xc029, 0x21, 0 + .dw 0xb3c0, 0xc029, 0xb3ff, 0xc029, 0x21, 0 + .dw 0xb440, 0xc029, 0xb47f, 0xc029, 0x21, 0 + .dw 0xb4c0, 0xc029, 0xb4ff, 0xc029, 0x21, 0 + .dw 0xb540, 0xc029, 0xb57f, 0xc029, 0x21, 0 + .dw 0xb5c0, 0xc029, 0xb5ff, 0xc029, 0x21, 0 + .dw 0xb640, 0xc029, 0xb67f, 0xc029, 0x21, 0 + .dw 0xb6c0, 0xc029, 0xb6ff, 0xc029, 0x21, 0 + .dw 0xb740, 0xc029, 0xb77f, 0xc029, 0x21, 0 + .dw 0xb7c0, 0xc029, 0xb7ff, 0xc029, 0x21, 0 + .dw 0xb840, 0xc029, 0xb87f, 0xc029, 0x21, 0 + .dw 0xb8c0, 0xc029, 0xb8ff, 0xc029, 0x21, 0 + .dw 0xb940, 0xc029, 0xb97f, 0xc029, 0x21, 0 + .dw 0xb9c0, 0xc029, 0xdfff, 0xc029, 0x21, 0 + .dw 0xe040, 0xc029, 0xe07f, 0xc029, 0x21, 0 + .dw 0xe0c0, 0xc029, 0xe0ff, 0xc029, 0x21, 0 + .dw 0xe140, 0xc029, 0xe17f, 0xc029, 0x21, 0 + .dw 0xe1c0, 0xc029, 0xe1ff, 0xc029, 0x21, 0 + .dw 0xe240, 0xc029, 0xe27f, 0xc029, 0x21, 0 + .dw 0xe2c0, 0xc029, 0xe2ff, 0xc029, 0x21, 0 + .dw 0xe340, 0xc029, 0xe37f, 0xc029, 0x21, 0 + .dw 0xe3c0, 0xc029, 0xe3ff, 0xc029, 0x21, 0 + .dw 0xe440, 0xc029, 0xe47f, 0xc029, 0x21, 0 + .dw 0xe4c0, 0xc029, 0xe4ff, 0xc029, 0x21, 0 + .dw 0xe540, 0xc029, 0xe57f, 0xc029, 0x21, 0 + .dw 0xe5c0, 0xc029, 0xe5ff, 0xc029, 0x21, 0 + .dw 0xe640, 0xc029, 0xe67f, 0xc029, 0x21, 0 + .dw 0xe6c0, 0xc029, 0xe6ff, 0xc029, 0x21, 0 + .dw 0xe740, 0xc029, 0xe77f, 0xc029, 0x21, 0 + .dw 0xe7c0, 0xc029, 0xe7ff, 0xc029, 0x21, 0 + .dw 0xe840, 0xc029, 0xe87f, 0xc029, 0x21, 0 + .dw 0xe8c0, 0xc029, 0xe8ff, 0xc029, 0x21, 0 + .dw 0xe940, 0xc029, 0xe97f, 0xc029, 0x21, 0 + .dw 0xe9c0, 0xc029, 0xe9ff, 0xc029, 0x21, 0 + .dw 0xea40, 0xc029, 0xea7f, 0xc029, 0x21, 0 + .dw 0xeac0, 0xc029, 0xeaff, 0xc029, 0x21, 0 + .dw 0xeb40, 0xc029, 0xeb7f, 0xc029, 0x21, 0 + .dw 0xebc0, 0xc029, 0xebff, 0xc029, 0x21, 0 + .dw 0xec40, 0xc029, 0xec7f, 0xc029, 0x21, 0 + .dw 0xecc0, 0xc029, 0xecff, 0xc029, 0x21, 0 + .dw 0xed40, 0xc029, 0xed7f, 0xc029, 0x21, 0 + .dw 0xedc0, 0xc029, 0xedff, 0xc029, 0x21, 0 + .dw 0xee40, 0xc029, 0xee7f, 0xc029, 0x21, 0 + .dw 0xeec0, 0xc029, 0xeeff, 0xc029, 0x21, 0 + .dw 0xef40, 0xc029, 0xef7f, 0xc029, 0x21, 0 + .dw 0xefc0, 0xc029, 0xefff, 0xc029, 0x21, 0 + .dw 0xf040, 0xc029, 0xf07f, 0xc029, 0x21, 0 + .dw 0xf0c0, 0xc029, 0xf0ff, 0xc029, 0x21, 0 + .dw 0xf140, 0xc029, 0xf17f, 0xc029, 0x21, 0 + .dw 0xf1c0, 0xc029, 0xf1ff, 0xc029, 0x21, 0 + .dw 0xf240, 0xc029, 0xf27f, 0xc029, 0x21, 0 + .dw 0xf2c0, 0xc029, 0xf2ff, 0xc029, 0x21, 0 + .dw 0xf340, 0xc029, 0xf37f, 0xc029, 0x21, 0 + .dw 0xf3c0, 0xc029, 0xf3ff, 0xc029, 0x21, 0 + .dw 0xf440, 0xc029, 0xf47f, 0xc029, 0x21, 0 + .dw 0xf4c0, 0xc029, 0xf4ff, 0xc029, 0x21, 0 + .dw 0xf540, 0xc029, 0xf57f, 0xc029, 0x21, 0 + .dw 0xf5c0, 0xc029, 0xf5ff, 0xc029, 0x21, 0 + .dw 0xf640, 0xc029, 0xf67f, 0xc029, 0x21, 0 + .dw 0xf6c0, 0xc029, 0xf6ff, 0xc029, 0x21, 0 + .dw 0xf740, 0xc029, 0xf77f, 0xc029, 0x21, 0 + .dw 0xf7c0, 0xc029, 0xf7ff, 0xc029, 0x21, 0 + .dw 0xf840, 0xc029, 0xf87f, 0xc029, 0x21, 0 + .dw 0xf8c0, 0xc029, 0xf8ff, 0xc029, 0x21, 0 + .dw 0xf940, 0xc029, 0xf97f, 0xc029, 0x21, 0 + .dw 0xf9c0, 0xc029, 0x1fff, 0xc02a, 0x21, 0 + .dw 0x2040, 0xc02a, 0x207f, 0xc02a, 0x21, 0 + .dw 0x20c0, 0xc02a, 0x20ff, 0xc02a, 0x21, 0 + .dw 0x2140, 0xc02a, 0x217f, 0xc02a, 0x21, 0 + .dw 0x21c0, 0xc02a, 0x21ff, 0xc02a, 0x21, 0 + .dw 0x2240, 0xc02a, 0x227f, 0xc02a, 0x21, 0 + .dw 0x22c0, 0xc02a, 0x22ff, 0xc02a, 0x21, 0 + .dw 0x2340, 0xc02a, 0x237f, 0xc02a, 0x21, 0 + .dw 0x23c0, 0xc02a, 0x23ff, 0xc02a, 0x21, 0 + .dw 0x2440, 0xc02a, 0x247f, 0xc02a, 0x21, 0 + .dw 0x24c0, 0xc02a, 0x24ff, 0xc02a, 0x21, 0 + .dw 0x2540, 0xc02a, 0x257f, 0xc02a, 0x21, 0 + .dw 0x25c0, 0xc02a, 0x25ff, 0xc02a, 0x21, 0 + .dw 0x2640, 0xc02a, 0x267f, 0xc02a, 0x21, 0 + .dw 0x26c0, 0xc02a, 0x26ff, 0xc02a, 0x21, 0 + .dw 0x2740, 0xc02a, 0x277f, 0xc02a, 0x21, 0 + .dw 0x27c0, 0xc02a, 0x27ff, 0xc02a, 0x21, 0 + .dw 0x2840, 0xc02a, 0x287f, 0xc02a, 0x21, 0 + .dw 0x28c0, 0xc02a, 0x28ff, 0xc02a, 0x21, 0 + .dw 0x2940, 0xc02a, 0x297f, 0xc02a, 0x21, 0 + .dw 0x29c0, 0xc02a, 0x29ff, 0xc02a, 0x21, 0 + .dw 0x2a40, 0xc02a, 0x2a7f, 0xc02a, 0x21, 0 + .dw 0x2ac0, 0xc02a, 0x2aff, 0xc02a, 0x21, 0 + .dw 0x2b40, 0xc02a, 0x2b7f, 0xc02a, 0x21, 0 + .dw 0x2bc0, 0xc02a, 0x2bff, 0xc02a, 0x21, 0 + .dw 0x2c40, 0xc02a, 0x2c7f, 0xc02a, 0x21, 0 + .dw 0x2cc0, 0xc02a, 0x2cff, 0xc02a, 0x21, 0 + .dw 0x2d40, 0xc02a, 0x2d7f, 0xc02a, 0x21, 0 + .dw 0x2dc0, 0xc02a, 0x2dff, 0xc02a, 0x21, 0 + .dw 0x2e40, 0xc02a, 0x2e7f, 0xc02a, 0x21, 0 + .dw 0x2ec0, 0xc02a, 0x2eff, 0xc02a, 0x21, 0 + .dw 0x2f40, 0xc02a, 0x2f7f, 0xc02a, 0x21, 0 + .dw 0x2fc0, 0xc02a, 0x2fff, 0xc02a, 0x21, 0 + .dw 0x3040, 0xc02a, 0x307f, 0xc02a, 0x21, 0 + .dw 0x30c0, 0xc02a, 0x30ff, 0xc02a, 0x21, 0 + .dw 0x3140, 0xc02a, 0x317f, 0xc02a, 0x21, 0 + .dw 0x31c0, 0xc02a, 0x31ff, 0xc02a, 0x21, 0 + .dw 0x3240, 0xc02a, 0x327f, 0xc02a, 0x21, 0 + .dw 0x32c0, 0xc02a, 0x32ff, 0xc02a, 0x21, 0 + .dw 0x3340, 0xc02a, 0x337f, 0xc02a, 0x21, 0 + .dw 0x33c0, 0xc02a, 0x33ff, 0xc02a, 0x21, 0 + .dw 0x3440, 0xc02a, 0x347f, 0xc02a, 0x21, 0 + .dw 0x34c0, 0xc02a, 0x34ff, 0xc02a, 0x21, 0 + .dw 0x3540, 0xc02a, 0x357f, 0xc02a, 0x21, 0 + .dw 0x35c0, 0xc02a, 0x35ff, 0xc02a, 0x21, 0 + .dw 0x3640, 0xc02a, 0x367f, 0xc02a, 0x21, 0 + .dw 0x36c0, 0xc02a, 0x36ff, 0xc02a, 0x21, 0 + .dw 0x3740, 0xc02a, 0x377f, 0xc02a, 0x21, 0 + .dw 0x37c0, 0xc02a, 0x37ff, 0xc02a, 0x21, 0 + .dw 0x3840, 0xc02a, 0x387f, 0xc02a, 0x21, 0 + .dw 0x38c0, 0xc02a, 0x38ff, 0xc02a, 0x21, 0 + .dw 0x3940, 0xc02a, 0x397f, 0xc02a, 0x21, 0 + .dw 0x39c0, 0xc02a, 0x5fff, 0xc02a, 0x21, 0 + .dw 0x6040, 0xc02a, 0x607f, 0xc02a, 0x21, 0 + .dw 0x60c0, 0xc02a, 0x60ff, 0xc02a, 0x21, 0 + .dw 0x6140, 0xc02a, 0x617f, 0xc02a, 0x21, 0 + .dw 0x61c0, 0xc02a, 0x61ff, 0xc02a, 0x21, 0 + .dw 0x6240, 0xc02a, 0x627f, 0xc02a, 0x21, 0 + .dw 0x62c0, 0xc02a, 0x62ff, 0xc02a, 0x21, 0 + .dw 0x6340, 0xc02a, 0x637f, 0xc02a, 0x21, 0 + .dw 0x63c0, 0xc02a, 0x63ff, 0xc02a, 0x21, 0 + .dw 0x6440, 0xc02a, 0x647f, 0xc02a, 0x21, 0 + .dw 0x64c0, 0xc02a, 0x64ff, 0xc02a, 0x21, 0 + .dw 0x6540, 0xc02a, 0x657f, 0xc02a, 0x21, 0 + .dw 0x65c0, 0xc02a, 0x65ff, 0xc02a, 0x21, 0 + .dw 0x6640, 0xc02a, 0x667f, 0xc02a, 0x21, 0 + .dw 0x66c0, 0xc02a, 0x66ff, 0xc02a, 0x21, 0 + .dw 0x6740, 0xc02a, 0x677f, 0xc02a, 0x21, 0 + .dw 0x67c0, 0xc02a, 0x67ff, 0xc02a, 0x21, 0 + .dw 0x6840, 0xc02a, 0x687f, 0xc02a, 0x21, 0 + .dw 0x68c0, 0xc02a, 0x68ff, 0xc02a, 0x21, 0 + .dw 0x6940, 0xc02a, 0x697f, 0xc02a, 0x21, 0 + .dw 0x69c0, 0xc02a, 0x69ff, 0xc02a, 0x21, 0 + .dw 0x6a40, 0xc02a, 0x6a7f, 0xc02a, 0x21, 0 + .dw 0x6ac0, 0xc02a, 0x6aff, 0xc02a, 0x21, 0 + .dw 0x6b40, 0xc02a, 0x6b7f, 0xc02a, 0x21, 0 + .dw 0x6bc0, 0xc02a, 0x6bff, 0xc02a, 0x21, 0 + .dw 0x6c40, 0xc02a, 0x6c7f, 0xc02a, 0x21, 0 + .dw 0x6cc0, 0xc02a, 0x6cff, 0xc02a, 0x21, 0 + .dw 0x6d40, 0xc02a, 0x6d7f, 0xc02a, 0x21, 0 + .dw 0x6dc0, 0xc02a, 0x6dff, 0xc02a, 0x21, 0 + .dw 0x6e40, 0xc02a, 0x6e7f, 0xc02a, 0x21, 0 + .dw 0x6ec0, 0xc02a, 0x6eff, 0xc02a, 0x21, 0 + .dw 0x6f40, 0xc02a, 0x6f7f, 0xc02a, 0x21, 0 + .dw 0x6fc0, 0xc02a, 0x6fff, 0xc02a, 0x21, 0 + .dw 0x7040, 0xc02a, 0x707f, 0xc02a, 0x21, 0 + .dw 0x70c0, 0xc02a, 0x70ff, 0xc02a, 0x21, 0 + .dw 0x7140, 0xc02a, 0x717f, 0xc02a, 0x21, 0 + .dw 0x71c0, 0xc02a, 0x71ff, 0xc02a, 0x21, 0 + .dw 0x7240, 0xc02a, 0x727f, 0xc02a, 0x21, 0 + .dw 0x72c0, 0xc02a, 0x72ff, 0xc02a, 0x21, 0 + .dw 0x7340, 0xc02a, 0x737f, 0xc02a, 0x21, 0 + .dw 0x73c0, 0xc02a, 0x73ff, 0xc02a, 0x21, 0 + .dw 0x7440, 0xc02a, 0x747f, 0xc02a, 0x21, 0 + .dw 0x74c0, 0xc02a, 0x74ff, 0xc02a, 0x21, 0 + .dw 0x7540, 0xc02a, 0x757f, 0xc02a, 0x21, 0 + .dw 0x75c0, 0xc02a, 0x75ff, 0xc02a, 0x21, 0 + .dw 0x7640, 0xc02a, 0x767f, 0xc02a, 0x21, 0 + .dw 0x76c0, 0xc02a, 0x76ff, 0xc02a, 0x21, 0 + .dw 0x7740, 0xc02a, 0x777f, 0xc02a, 0x21, 0 + .dw 0x77c0, 0xc02a, 0x77ff, 0xc02a, 0x21, 0 + .dw 0x7840, 0xc02a, 0x787f, 0xc02a, 0x21, 0 + .dw 0x78c0, 0xc02a, 0x78ff, 0xc02a, 0x21, 0 + .dw 0x7940, 0xc02a, 0x797f, 0xc02a, 0x21, 0 + .dw 0x79c0, 0xc02a, 0x9fff, 0xc02a, 0x21, 0 + .dw 0xa040, 0xc02a, 0xa07f, 0xc02a, 0x21, 0 + .dw 0xa0c0, 0xc02a, 0xa0ff, 0xc02a, 0x21, 0 + .dw 0xa140, 0xc02a, 0xa17f, 0xc02a, 0x21, 0 + .dw 0xa1c0, 0xc02a, 0xa1ff, 0xc02a, 0x21, 0 + .dw 0xa240, 0xc02a, 0xa27f, 0xc02a, 0x21, 0 + .dw 0xa2c0, 0xc02a, 0xa2ff, 0xc02a, 0x21, 0 + .dw 0xa340, 0xc02a, 0xa37f, 0xc02a, 0x21, 0 + .dw 0xa3c0, 0xc02a, 0xa3ff, 0xc02a, 0x21, 0 + .dw 0xa440, 0xc02a, 0xa47f, 0xc02a, 0x21, 0 + .dw 0xa4c0, 0xc02a, 0xa4ff, 0xc02a, 0x21, 0 + .dw 0xa540, 0xc02a, 0xa57f, 0xc02a, 0x21, 0 + .dw 0xa5c0, 0xc02a, 0xa5ff, 0xc02a, 0x21, 0 + .dw 0xa640, 0xc02a, 0xa67f, 0xc02a, 0x21, 0 + .dw 0xa6c0, 0xc02a, 0xa6ff, 0xc02a, 0x21, 0 + .dw 0xa740, 0xc02a, 0xa77f, 0xc02a, 0x21, 0 + .dw 0xa7c0, 0xc02a, 0xa7ff, 0xc02a, 0x21, 0 + .dw 0xa840, 0xc02a, 0xa87f, 0xc02a, 0x21, 0 + .dw 0xa8c0, 0xc02a, 0xa8ff, 0xc02a, 0x21, 0 + .dw 0xa940, 0xc02a, 0xa97f, 0xc02a, 0x21, 0 + .dw 0xa9c0, 0xc02a, 0xa9ff, 0xc02a, 0x21, 0 + .dw 0xaa40, 0xc02a, 0xaa7f, 0xc02a, 0x21, 0 + .dw 0xaac0, 0xc02a, 0xaaff, 0xc02a, 0x21, 0 + .dw 0xab40, 0xc02a, 0xab7f, 0xc02a, 0x21, 0 + .dw 0xabc0, 0xc02a, 0xabff, 0xc02a, 0x21, 0 + .dw 0xac40, 0xc02a, 0xac7f, 0xc02a, 0x21, 0 + .dw 0xacc0, 0xc02a, 0xacff, 0xc02a, 0x21, 0 + .dw 0xad40, 0xc02a, 0xad7f, 0xc02a, 0x21, 0 + .dw 0xadc0, 0xc02a, 0xadff, 0xc02a, 0x21, 0 + .dw 0xae40, 0xc02a, 0xae7f, 0xc02a, 0x21, 0 + .dw 0xaec0, 0xc02a, 0xaeff, 0xc02a, 0x21, 0 + .dw 0xaf40, 0xc02a, 0xaf7f, 0xc02a, 0x21, 0 + .dw 0xafc0, 0xc02a, 0xafff, 0xc02a, 0x21, 0 + .dw 0xb040, 0xc02a, 0xb07f, 0xc02a, 0x21, 0 + .dw 0xb0c0, 0xc02a, 0xb0ff, 0xc02a, 0x21, 0 + .dw 0xb140, 0xc02a, 0xb17f, 0xc02a, 0x21, 0 + .dw 0xb1c0, 0xc02a, 0xb1ff, 0xc02a, 0x21, 0 + .dw 0xb240, 0xc02a, 0xb27f, 0xc02a, 0x21, 0 + .dw 0xb2c0, 0xc02a, 0xb2ff, 0xc02a, 0x21, 0 + .dw 0xb340, 0xc02a, 0xb37f, 0xc02a, 0x21, 0 + .dw 0xb3c0, 0xc02a, 0xb3ff, 0xc02a, 0x21, 0 + .dw 0xb440, 0xc02a, 0xb47f, 0xc02a, 0x21, 0 + .dw 0xb4c0, 0xc02a, 0xb4ff, 0xc02a, 0x21, 0 + .dw 0xb540, 0xc02a, 0xb57f, 0xc02a, 0x21, 0 + .dw 0xb5c0, 0xc02a, 0xb5ff, 0xc02a, 0x21, 0 + .dw 0xb640, 0xc02a, 0xb67f, 0xc02a, 0x21, 0 + .dw 0xb6c0, 0xc02a, 0xb6ff, 0xc02a, 0x21, 0 + .dw 0xb740, 0xc02a, 0xb77f, 0xc02a, 0x21, 0 + .dw 0xb7c0, 0xc02a, 0xb7ff, 0xc02a, 0x21, 0 + .dw 0xb840, 0xc02a, 0xb87f, 0xc02a, 0x21, 0 + .dw 0xb8c0, 0xc02a, 0xb8ff, 0xc02a, 0x21, 0 + .dw 0xb940, 0xc02a, 0xb97f, 0xc02a, 0x21, 0 + .dw 0xb9c0, 0xc02a, 0xdfff, 0xc02a, 0x21, 0 + .dw 0xe040, 0xc02a, 0xe07f, 0xc02a, 0x21, 0 + .dw 0xe0c0, 0xc02a, 0xe0ff, 0xc02a, 0x21, 0 + .dw 0xe140, 0xc02a, 0xe17f, 0xc02a, 0x21, 0 + .dw 0xe1c0, 0xc02a, 0xe1ff, 0xc02a, 0x21, 0 + .dw 0xe240, 0xc02a, 0xe27f, 0xc02a, 0x21, 0 + .dw 0xe2c0, 0xc02a, 0xe2ff, 0xc02a, 0x21, 0 + .dw 0xe340, 0xc02a, 0xe37f, 0xc02a, 0x21, 0 + .dw 0xe3c0, 0xc02a, 0xe3ff, 0xc02a, 0x21, 0 + .dw 0xe440, 0xc02a, 0xe47f, 0xc02a, 0x21, 0 + .dw 0xe4c0, 0xc02a, 0xe4ff, 0xc02a, 0x21, 0 + .dw 0xe540, 0xc02a, 0xe57f, 0xc02a, 0x21, 0 + .dw 0xe5c0, 0xc02a, 0xe5ff, 0xc02a, 0x21, 0 + .dw 0xe640, 0xc02a, 0xe67f, 0xc02a, 0x21, 0 + .dw 0xe6c0, 0xc02a, 0xe6ff, 0xc02a, 0x21, 0 + .dw 0xe740, 0xc02a, 0xe77f, 0xc02a, 0x21, 0 + .dw 0xe7c0, 0xc02a, 0xe7ff, 0xc02a, 0x21, 0 + .dw 0xe840, 0xc02a, 0xe87f, 0xc02a, 0x21, 0 + .dw 0xe8c0, 0xc02a, 0xe8ff, 0xc02a, 0x21, 0 + .dw 0xe940, 0xc02a, 0xe97f, 0xc02a, 0x21, 0 + .dw 0xe9c0, 0xc02a, 0xe9ff, 0xc02a, 0x21, 0 + .dw 0xea40, 0xc02a, 0xea7f, 0xc02a, 0x21, 0 + .dw 0xeac0, 0xc02a, 0xeaff, 0xc02a, 0x21, 0 + .dw 0xeb40, 0xc02a, 0xeb7f, 0xc02a, 0x21, 0 + .dw 0xebc0, 0xc02a, 0xebff, 0xc02a, 0x21, 0 + .dw 0xec40, 0xc02a, 0xec7f, 0xc02a, 0x21, 0 + .dw 0xecc0, 0xc02a, 0xecff, 0xc02a, 0x21, 0 + .dw 0xed40, 0xc02a, 0xed7f, 0xc02a, 0x21, 0 + .dw 0xedc0, 0xc02a, 0xedff, 0xc02a, 0x21, 0 + .dw 0xee40, 0xc02a, 0xee7f, 0xc02a, 0x21, 0 + .dw 0xeec0, 0xc02a, 0xeeff, 0xc02a, 0x21, 0 + .dw 0xef40, 0xc02a, 0xef7f, 0xc02a, 0x21, 0 + .dw 0xefc0, 0xc02a, 0xefff, 0xc02a, 0x21, 0 + .dw 0xf040, 0xc02a, 0xf07f, 0xc02a, 0x21, 0 + .dw 0xf0c0, 0xc02a, 0xf0ff, 0xc02a, 0x21, 0 + .dw 0xf140, 0xc02a, 0xf17f, 0xc02a, 0x21, 0 + .dw 0xf1c0, 0xc02a, 0xf1ff, 0xc02a, 0x21, 0 + .dw 0xf240, 0xc02a, 0xf27f, 0xc02a, 0x21, 0 + .dw 0xf2c0, 0xc02a, 0xf2ff, 0xc02a, 0x21, 0 + .dw 0xf340, 0xc02a, 0xf37f, 0xc02a, 0x21, 0 + .dw 0xf3c0, 0xc02a, 0xf3ff, 0xc02a, 0x21, 0 + .dw 0xf440, 0xc02a, 0xf47f, 0xc02a, 0x21, 0 + .dw 0xf4c0, 0xc02a, 0xf4ff, 0xc02a, 0x21, 0 + .dw 0xf540, 0xc02a, 0xf57f, 0xc02a, 0x21, 0 + .dw 0xf5c0, 0xc02a, 0xf5ff, 0xc02a, 0x21, 0 + .dw 0xf640, 0xc02a, 0xf67f, 0xc02a, 0x21, 0 + .dw 0xf6c0, 0xc02a, 0xf6ff, 0xc02a, 0x21, 0 + .dw 0xf740, 0xc02a, 0xf77f, 0xc02a, 0x21, 0 + .dw 0xf7c0, 0xc02a, 0xf7ff, 0xc02a, 0x21, 0 + .dw 0xf840, 0xc02a, 0xf87f, 0xc02a, 0x21, 0 + .dw 0xf8c0, 0xc02a, 0xf8ff, 0xc02a, 0x21, 0 + .dw 0xf940, 0xc02a, 0xf97f, 0xc02a, 0x21, 0 + .dw 0xf9c0, 0xc02a, 0x1fff, 0xc02b, 0x21, 0 + .dw 0x2040, 0xc02b, 0x207f, 0xc02b, 0x21, 0 + .dw 0x20c0, 0xc02b, 0x20ff, 0xc02b, 0x21, 0 + .dw 0x2140, 0xc02b, 0x217f, 0xc02b, 0x21, 0 + .dw 0x21c0, 0xc02b, 0x21ff, 0xc02b, 0x21, 0 + .dw 0x2240, 0xc02b, 0x227f, 0xc02b, 0x21, 0 + .dw 0x22c0, 0xc02b, 0x22ff, 0xc02b, 0x21, 0 + .dw 0x2340, 0xc02b, 0x237f, 0xc02b, 0x21, 0 + .dw 0x23c0, 0xc02b, 0x23ff, 0xc02b, 0x21, 0 + .dw 0x2440, 0xc02b, 0x247f, 0xc02b, 0x21, 0 + .dw 0x24c0, 0xc02b, 0x24ff, 0xc02b, 0x21, 0 + .dw 0x2540, 0xc02b, 0x257f, 0xc02b, 0x21, 0 + .dw 0x25c0, 0xc02b, 0x25ff, 0xc02b, 0x21, 0 + .dw 0x2640, 0xc02b, 0x267f, 0xc02b, 0x21, 0 + .dw 0x26c0, 0xc02b, 0x26ff, 0xc02b, 0x21, 0 + .dw 0x2740, 0xc02b, 0x277f, 0xc02b, 0x21, 0 + .dw 0x27c0, 0xc02b, 0x27ff, 0xc02b, 0x21, 0 + .dw 0x2840, 0xc02b, 0x287f, 0xc02b, 0x21, 0 + .dw 0x28c0, 0xc02b, 0x28ff, 0xc02b, 0x21, 0 + .dw 0x2940, 0xc02b, 0x297f, 0xc02b, 0x21, 0 + .dw 0x29c0, 0xc02b, 0x29ff, 0xc02b, 0x21, 0 + .dw 0x2a40, 0xc02b, 0x2a7f, 0xc02b, 0x21, 0 + .dw 0x2ac0, 0xc02b, 0x2aff, 0xc02b, 0x21, 0 + .dw 0x2b40, 0xc02b, 0x2b7f, 0xc02b, 0x21, 0 + .dw 0x2bc0, 0xc02b, 0x2bff, 0xc02b, 0x21, 0 + .dw 0x2c40, 0xc02b, 0x2c7f, 0xc02b, 0x21, 0 + .dw 0x2cc0, 0xc02b, 0x2cff, 0xc02b, 0x21, 0 + .dw 0x2d40, 0xc02b, 0x2d7f, 0xc02b, 0x21, 0 + .dw 0x2dc0, 0xc02b, 0x2dff, 0xc02b, 0x21, 0 + .dw 0x2e40, 0xc02b, 0x2e7f, 0xc02b, 0x21, 0 + .dw 0x2ec0, 0xc02b, 0x2eff, 0xc02b, 0x21, 0 + .dw 0x2f40, 0xc02b, 0x2f7f, 0xc02b, 0x21, 0 + .dw 0x2fc0, 0xc02b, 0x2fff, 0xc02b, 0x21, 0 + .dw 0x3040, 0xc02b, 0x307f, 0xc02b, 0x21, 0 + .dw 0x30c0, 0xc02b, 0x30ff, 0xc02b, 0x21, 0 + .dw 0x3140, 0xc02b, 0x317f, 0xc02b, 0x21, 0 + .dw 0x31c0, 0xc02b, 0x31ff, 0xc02b, 0x21, 0 + .dw 0x3240, 0xc02b, 0x327f, 0xc02b, 0x21, 0 + .dw 0x32c0, 0xc02b, 0x32ff, 0xc02b, 0x21, 0 + .dw 0x3340, 0xc02b, 0x337f, 0xc02b, 0x21, 0 + .dw 0x33c0, 0xc02b, 0x33ff, 0xc02b, 0x21, 0 + .dw 0x3440, 0xc02b, 0x347f, 0xc02b, 0x21, 0 + .dw 0x34c0, 0xc02b, 0x34ff, 0xc02b, 0x21, 0 + .dw 0x3540, 0xc02b, 0x357f, 0xc02b, 0x21, 0 + .dw 0x35c0, 0xc02b, 0x35ff, 0xc02b, 0x21, 0 + .dw 0x3640, 0xc02b, 0x367f, 0xc02b, 0x21, 0 + .dw 0x36c0, 0xc02b, 0x36ff, 0xc02b, 0x21, 0 + .dw 0x3740, 0xc02b, 0x377f, 0xc02b, 0x21, 0 + .dw 0x37c0, 0xc02b, 0x37ff, 0xc02b, 0x21, 0 + .dw 0x3840, 0xc02b, 0x387f, 0xc02b, 0x21, 0 + .dw 0x38c0, 0xc02b, 0x38ff, 0xc02b, 0x21, 0 + .dw 0x3940, 0xc02b, 0x397f, 0xc02b, 0x21, 0 + .dw 0x39c0, 0xc02b, 0xffff, 0xc02b, 0x21, 0 + .dw 0x0040, 0xc02c, 0x007f, 0xc02c, 0x21, 0 + .dw 0x00c0, 0xc02c, 0x00ff, 0xc02c, 0x21, 0 + .dw 0x0140, 0xc02c, 0x017f, 0xc02c, 0x21, 0 + .dw 0x01c0, 0xc02c, 0x01ff, 0xc02c, 0x21, 0 + .dw 0x0240, 0xc02c, 0x027f, 0xc02c, 0x21, 0 + .dw 0x02c0, 0xc02c, 0x02ff, 0xc02c, 0x21, 0 + .dw 0x0340, 0xc02c, 0x037f, 0xc02c, 0x21, 0 + .dw 0x03c0, 0xc02c, 0x03ff, 0xc02c, 0x21, 0 + .dw 0x0440, 0xc02c, 0x047f, 0xc02c, 0x21, 0 + .dw 0x04c0, 0xc02c, 0x04ff, 0xc02c, 0x21, 0 + .dw 0x0540, 0xc02c, 0x057f, 0xc02c, 0x21, 0 + .dw 0x05c0, 0xc02c, 0x05ff, 0xc02c, 0x21, 0 + .dw 0x0640, 0xc02c, 0x067f, 0xc02c, 0x21, 0 + .dw 0x06c0, 0xc02c, 0x06ff, 0xc02c, 0x21, 0 + .dw 0x0740, 0xc02c, 0x077f, 0xc02c, 0x21, 0 + .dw 0x07c0, 0xc02c, 0x07ff, 0xc02c, 0x21, 0 + .dw 0x0840, 0xc02c, 0x087f, 0xc02c, 0x21, 0 + .dw 0x08c0, 0xc02c, 0x08ff, 0xc02c, 0x21, 0 + .dw 0x0940, 0xc02c, 0x097f, 0xc02c, 0x21, 0 + .dw 0x09c0, 0xc02c, 0x09ff, 0xc02c, 0x21, 0 + .dw 0x0a40, 0xc02c, 0x0a7f, 0xc02c, 0x21, 0 + .dw 0x0ac0, 0xc02c, 0x0aff, 0xc02c, 0x21, 0 + .dw 0x0b40, 0xc02c, 0x0b7f, 0xc02c, 0x21, 0 + .dw 0x0bc0, 0xc02c, 0x0bff, 0xc02c, 0x21, 0 + .dw 0x0c40, 0xc02c, 0x0c7f, 0xc02c, 0x21, 0 + .dw 0x0cc0, 0xc02c, 0x0cff, 0xc02c, 0x21, 0 + .dw 0x0d40, 0xc02c, 0x0d7f, 0xc02c, 0x21, 0 + .dw 0x0dc0, 0xc02c, 0x0dff, 0xc02c, 0x21, 0 + .dw 0x0e40, 0xc02c, 0x0e7f, 0xc02c, 0x21, 0 + .dw 0x0ec0, 0xc02c, 0x0eff, 0xc02c, 0x21, 0 + .dw 0x0f40, 0xc02c, 0x0f7f, 0xc02c, 0x21, 0 + .dw 0x0fc0, 0xc02c, 0x0fff, 0xc02c, 0x21, 0 + .dw 0x1040, 0xc02c, 0x107f, 0xc02c, 0x21, 0 + .dw 0x10c0, 0xc02c, 0x10ff, 0xc02c, 0x21, 0 + .dw 0x1140, 0xc02c, 0x117f, 0xc02c, 0x21, 0 + .dw 0x11c0, 0xc02c, 0x11ff, 0xc02c, 0x21, 0 + .dw 0x1240, 0xc02c, 0x127f, 0xc02c, 0x21, 0 + .dw 0x12c0, 0xc02c, 0x12ff, 0xc02c, 0x21, 0 + .dw 0x1340, 0xc02c, 0x137f, 0xc02c, 0x21, 0 + .dw 0x13c0, 0xc02c, 0x13ff, 0xc02c, 0x21, 0 + .dw 0x1440, 0xc02c, 0x147f, 0xc02c, 0x21, 0 + .dw 0x14c0, 0xc02c, 0x14ff, 0xc02c, 0x21, 0 + .dw 0x1540, 0xc02c, 0x157f, 0xc02c, 0x21, 0 + .dw 0x15c0, 0xc02c, 0x15ff, 0xc02c, 0x21, 0 + .dw 0x1640, 0xc02c, 0x167f, 0xc02c, 0x21, 0 + .dw 0x16c0, 0xc02c, 0x16ff, 0xc02c, 0x21, 0 + .dw 0x1740, 0xc02c, 0x177f, 0xc02c, 0x21, 0 + .dw 0x17c0, 0xc02c, 0x17ff, 0xc02c, 0x21, 0 + .dw 0x1840, 0xc02c, 0x187f, 0xc02c, 0x21, 0 + .dw 0x18c0, 0xc02c, 0x18ff, 0xc02c, 0x21, 0 + .dw 0x1940, 0xc02c, 0x197f, 0xc02c, 0x21, 0 + .dw 0x19c0, 0xc02c, 0x1fff, 0xc02c, 0x21, 0 + .dw 0x2040, 0xc02c, 0x207f, 0xc02c, 0x21, 0 + .dw 0x20c0, 0xc02c, 0x20ff, 0xc02c, 0x21, 0 + .dw 0x2140, 0xc02c, 0x217f, 0xc02c, 0x21, 0 + .dw 0x21c0, 0xc02c, 0x21ff, 0xc02c, 0x21, 0 + .dw 0x2240, 0xc02c, 0x227f, 0xc02c, 0x21, 0 + .dw 0x22c0, 0xc02c, 0x22ff, 0xc02c, 0x21, 0 + .dw 0x2340, 0xc02c, 0x237f, 0xc02c, 0x21, 0 + .dw 0x23c0, 0xc02c, 0x23ff, 0xc02c, 0x21, 0 + .dw 0x2440, 0xc02c, 0x247f, 0xc02c, 0x21, 0 + .dw 0x24c0, 0xc02c, 0x24ff, 0xc02c, 0x21, 0 + .dw 0x2540, 0xc02c, 0x257f, 0xc02c, 0x21, 0 + .dw 0x25c0, 0xc02c, 0x25ff, 0xc02c, 0x21, 0 + .dw 0x2640, 0xc02c, 0x267f, 0xc02c, 0x21, 0 + .dw 0x26c0, 0xc02c, 0x26ff, 0xc02c, 0x21, 0 + .dw 0x2740, 0xc02c, 0x277f, 0xc02c, 0x21, 0 + .dw 0x27c0, 0xc02c, 0x27ff, 0xc02c, 0x21, 0 + .dw 0x2840, 0xc02c, 0x287f, 0xc02c, 0x21, 0 + .dw 0x28c0, 0xc02c, 0x28ff, 0xc02c, 0x21, 0 + .dw 0x2940, 0xc02c, 0x297f, 0xc02c, 0x21, 0 + .dw 0x29c0, 0xc02c, 0x29ff, 0xc02c, 0x21, 0 + .dw 0x2a40, 0xc02c, 0x2a7f, 0xc02c, 0x21, 0 + .dw 0x2ac0, 0xc02c, 0x2aff, 0xc02c, 0x21, 0 + .dw 0x2b40, 0xc02c, 0x2b7f, 0xc02c, 0x21, 0 + .dw 0x2bc0, 0xc02c, 0x2bff, 0xc02c, 0x21, 0 + .dw 0x2c40, 0xc02c, 0x2c7f, 0xc02c, 0x21, 0 + .dw 0x2cc0, 0xc02c, 0x2cff, 0xc02c, 0x21, 0 + .dw 0x2d40, 0xc02c, 0x2d7f, 0xc02c, 0x21, 0 + .dw 0x2dc0, 0xc02c, 0x2dff, 0xc02c, 0x21, 0 + .dw 0x2e40, 0xc02c, 0x2e7f, 0xc02c, 0x21, 0 + .dw 0x2ec0, 0xc02c, 0x2eff, 0xc02c, 0x21, 0 + .dw 0x2f40, 0xc02c, 0x2f7f, 0xc02c, 0x21, 0 + .dw 0x2fc0, 0xc02c, 0x2fff, 0xc02c, 0x21, 0 + .dw 0x3040, 0xc02c, 0x307f, 0xc02c, 0x21, 0 + .dw 0x30c0, 0xc02c, 0x30ff, 0xc02c, 0x21, 0 + .dw 0x3140, 0xc02c, 0x317f, 0xc02c, 0x21, 0 + .dw 0x31c0, 0xc02c, 0x31ff, 0xc02c, 0x21, 0 + .dw 0x3240, 0xc02c, 0x327f, 0xc02c, 0x21, 0 + .dw 0x32c0, 0xc02c, 0x32ff, 0xc02c, 0x21, 0 + .dw 0x3340, 0xc02c, 0x337f, 0xc02c, 0x21, 0 + .dw 0x33c0, 0xc02c, 0x33ff, 0xc02c, 0x21, 0 + .dw 0x3440, 0xc02c, 0x347f, 0xc02c, 0x21, 0 + .dw 0x34c0, 0xc02c, 0x34ff, 0xc02c, 0x21, 0 + .dw 0x3540, 0xc02c, 0x357f, 0xc02c, 0x21, 0 + .dw 0x35c0, 0xc02c, 0x35ff, 0xc02c, 0x21, 0 + .dw 0x3640, 0xc02c, 0x367f, 0xc02c, 0x21, 0 + .dw 0x36c0, 0xc02c, 0x36ff, 0xc02c, 0x21, 0 + .dw 0x3740, 0xc02c, 0x377f, 0xc02c, 0x21, 0 + .dw 0x37c0, 0xc02c, 0x37ff, 0xc02c, 0x21, 0 + .dw 0x3840, 0xc02c, 0x387f, 0xc02c, 0x21, 0 + .dw 0x38c0, 0xc02c, 0x38ff, 0xc02c, 0x21, 0 + .dw 0x3940, 0xc02c, 0x397f, 0xc02c, 0x21, 0 + .dw 0x39c0, 0xc02c, 0x3fff, 0xc02c, 0x21, 0 + .dw 0x4040, 0xc02c, 0x407f, 0xc02c, 0x21, 0 + .dw 0x40c0, 0xc02c, 0x40ff, 0xc02c, 0x21, 0 + .dw 0x4140, 0xc02c, 0x417f, 0xc02c, 0x21, 0 + .dw 0x41c0, 0xc02c, 0x41ff, 0xc02c, 0x21, 0 + .dw 0x4240, 0xc02c, 0x427f, 0xc02c, 0x21, 0 + .dw 0x42c0, 0xc02c, 0x42ff, 0xc02c, 0x21, 0 + .dw 0x4340, 0xc02c, 0x437f, 0xc02c, 0x21, 0 + .dw 0x43c0, 0xc02c, 0x43ff, 0xc02c, 0x21, 0 + .dw 0x4440, 0xc02c, 0x447f, 0xc02c, 0x21, 0 + .dw 0x44c0, 0xc02c, 0x44ff, 0xc02c, 0x21, 0 + .dw 0x4540, 0xc02c, 0x457f, 0xc02c, 0x21, 0 + .dw 0x45c0, 0xc02c, 0x45ff, 0xc02c, 0x21, 0 + .dw 0x4640, 0xc02c, 0x467f, 0xc02c, 0x21, 0 + .dw 0x46c0, 0xc02c, 0x46ff, 0xc02c, 0x21, 0 + .dw 0x4740, 0xc02c, 0x477f, 0xc02c, 0x21, 0 + .dw 0x47c0, 0xc02c, 0x47ff, 0xc02c, 0x21, 0 + .dw 0x4840, 0xc02c, 0x487f, 0xc02c, 0x21, 0 + .dw 0x48c0, 0xc02c, 0x48ff, 0xc02c, 0x21, 0 + .dw 0x4940, 0xc02c, 0x497f, 0xc02c, 0x21, 0 + .dw 0x49c0, 0xc02c, 0x49ff, 0xc02c, 0x21, 0 + .dw 0x4a40, 0xc02c, 0x4a7f, 0xc02c, 0x21, 0 + .dw 0x4ac0, 0xc02c, 0x4aff, 0xc02c, 0x21, 0 + .dw 0x4b40, 0xc02c, 0x4b7f, 0xc02c, 0x21, 0 + .dw 0x4bc0, 0xc02c, 0x4bff, 0xc02c, 0x21, 0 + .dw 0x4c40, 0xc02c, 0x4c7f, 0xc02c, 0x21, 0 + .dw 0x4cc0, 0xc02c, 0x4cff, 0xc02c, 0x21, 0 + .dw 0x4d40, 0xc02c, 0x4d7f, 0xc02c, 0x21, 0 + .dw 0x4dc0, 0xc02c, 0x4dff, 0xc02c, 0x21, 0 + .dw 0x4e40, 0xc02c, 0x4e7f, 0xc02c, 0x21, 0 + .dw 0x4ec0, 0xc02c, 0x4eff, 0xc02c, 0x21, 0 + .dw 0x4f40, 0xc02c, 0x4f7f, 0xc02c, 0x21, 0 + .dw 0x4fc0, 0xc02c, 0x4fff, 0xc02c, 0x21, 0 + .dw 0x5040, 0xc02c, 0x507f, 0xc02c, 0x21, 0 + .dw 0x50c0, 0xc02c, 0x50ff, 0xc02c, 0x21, 0 + .dw 0x5140, 0xc02c, 0x517f, 0xc02c, 0x21, 0 + .dw 0x51c0, 0xc02c, 0x51ff, 0xc02c, 0x21, 0 + .dw 0x5240, 0xc02c, 0x527f, 0xc02c, 0x21, 0 + .dw 0x52c0, 0xc02c, 0x52ff, 0xc02c, 0x21, 0 + .dw 0x5340, 0xc02c, 0x537f, 0xc02c, 0x21, 0 + .dw 0x53c0, 0xc02c, 0x53ff, 0xc02c, 0x21, 0 + .dw 0x5440, 0xc02c, 0x547f, 0xc02c, 0x21, 0 + .dw 0x54c0, 0xc02c, 0x54ff, 0xc02c, 0x21, 0 + .dw 0x5540, 0xc02c, 0x557f, 0xc02c, 0x21, 0 + .dw 0x55c0, 0xc02c, 0x55ff, 0xc02c, 0x21, 0 + .dw 0x5640, 0xc02c, 0x567f, 0xc02c, 0x21, 0 + .dw 0x56c0, 0xc02c, 0x56ff, 0xc02c, 0x21, 0 + .dw 0x5740, 0xc02c, 0x577f, 0xc02c, 0x21, 0 + .dw 0x57c0, 0xc02c, 0x57ff, 0xc02c, 0x21, 0 + .dw 0x5840, 0xc02c, 0x587f, 0xc02c, 0x21, 0 + .dw 0x58c0, 0xc02c, 0x58ff, 0xc02c, 0x21, 0 + .dw 0x5940, 0xc02c, 0x597f, 0xc02c, 0x21, 0 + .dw 0x59c0, 0xc02c, 0x5fff, 0xc02c, 0x21, 0 + .dw 0x6040, 0xc02c, 0x607f, 0xc02c, 0x21, 0 + .dw 0x60c0, 0xc02c, 0x60ff, 0xc02c, 0x21, 0 + .dw 0x6140, 0xc02c, 0x617f, 0xc02c, 0x21, 0 + .dw 0x61c0, 0xc02c, 0x61ff, 0xc02c, 0x21, 0 + .dw 0x6240, 0xc02c, 0x627f, 0xc02c, 0x21, 0 + .dw 0x62c0, 0xc02c, 0x62ff, 0xc02c, 0x21, 0 + .dw 0x6340, 0xc02c, 0x637f, 0xc02c, 0x21, 0 + .dw 0x63c0, 0xc02c, 0x63ff, 0xc02c, 0x21, 0 + .dw 0x6440, 0xc02c, 0x647f, 0xc02c, 0x21, 0 + .dw 0x64c0, 0xc02c, 0x64ff, 0xc02c, 0x21, 0 + .dw 0x6540, 0xc02c, 0x657f, 0xc02c, 0x21, 0 + .dw 0x65c0, 0xc02c, 0x65ff, 0xc02c, 0x21, 0 + .dw 0x6640, 0xc02c, 0x667f, 0xc02c, 0x21, 0 + .dw 0x66c0, 0xc02c, 0x66ff, 0xc02c, 0x21, 0 + .dw 0x6740, 0xc02c, 0x677f, 0xc02c, 0x21, 0 + .dw 0x67c0, 0xc02c, 0x67ff, 0xc02c, 0x21, 0 + .dw 0x6840, 0xc02c, 0x687f, 0xc02c, 0x21, 0 + .dw 0x68c0, 0xc02c, 0x68ff, 0xc02c, 0x21, 0 + .dw 0x6940, 0xc02c, 0x697f, 0xc02c, 0x21, 0 + .dw 0x69c0, 0xc02c, 0x69ff, 0xc02c, 0x21, 0 + .dw 0x6a40, 0xc02c, 0x6a7f, 0xc02c, 0x21, 0 + .dw 0x6ac0, 0xc02c, 0x6aff, 0xc02c, 0x21, 0 + .dw 0x6b40, 0xc02c, 0x6b7f, 0xc02c, 0x21, 0 + .dw 0x6bc0, 0xc02c, 0x6bff, 0xc02c, 0x21, 0 + .dw 0x6c40, 0xc02c, 0x6c7f, 0xc02c, 0x21, 0 + .dw 0x6cc0, 0xc02c, 0x6cff, 0xc02c, 0x21, 0 + .dw 0x6d40, 0xc02c, 0x6d7f, 0xc02c, 0x21, 0 + .dw 0x6dc0, 0xc02c, 0x6dff, 0xc02c, 0x21, 0 + .dw 0x6e40, 0xc02c, 0x6e7f, 0xc02c, 0x21, 0 + .dw 0x6ec0, 0xc02c, 0x6eff, 0xc02c, 0x21, 0 + .dw 0x6f40, 0xc02c, 0x6f7f, 0xc02c, 0x21, 0 + .dw 0x6fc0, 0xc02c, 0x6fff, 0xc02c, 0x21, 0 + .dw 0x7040, 0xc02c, 0x707f, 0xc02c, 0x21, 0 + .dw 0x70c0, 0xc02c, 0x70ff, 0xc02c, 0x21, 0 + .dw 0x7140, 0xc02c, 0x717f, 0xc02c, 0x21, 0 + .dw 0x71c0, 0xc02c, 0x71ff, 0xc02c, 0x21, 0 + .dw 0x7240, 0xc02c, 0x727f, 0xc02c, 0x21, 0 + .dw 0x72c0, 0xc02c, 0x72ff, 0xc02c, 0x21, 0 + .dw 0x7340, 0xc02c, 0x737f, 0xc02c, 0x21, 0 + .dw 0x73c0, 0xc02c, 0x73ff, 0xc02c, 0x21, 0 + .dw 0x7440, 0xc02c, 0x747f, 0xc02c, 0x21, 0 + .dw 0x74c0, 0xc02c, 0x74ff, 0xc02c, 0x21, 0 + .dw 0x7540, 0xc02c, 0x757f, 0xc02c, 0x21, 0 + .dw 0x75c0, 0xc02c, 0x75ff, 0xc02c, 0x21, 0 + .dw 0x7640, 0xc02c, 0x767f, 0xc02c, 0x21, 0 + .dw 0x76c0, 0xc02c, 0x76ff, 0xc02c, 0x21, 0 + .dw 0x7740, 0xc02c, 0x777f, 0xc02c, 0x21, 0 + .dw 0x77c0, 0xc02c, 0x77ff, 0xc02c, 0x21, 0 + .dw 0x7840, 0xc02c, 0x787f, 0xc02c, 0x21, 0 + .dw 0x78c0, 0xc02c, 0x78ff, 0xc02c, 0x21, 0 + .dw 0x7940, 0xc02c, 0x797f, 0xc02c, 0x21, 0 + .dw 0x79c0, 0xc02c, 0x7fff, 0xc02c, 0x21, 0 + .dw 0x8040, 0xc02c, 0x807f, 0xc02c, 0x21, 0 + .dw 0x80c0, 0xc02c, 0x80ff, 0xc02c, 0x21, 0 + .dw 0x8140, 0xc02c, 0x817f, 0xc02c, 0x21, 0 + .dw 0x81c0, 0xc02c, 0x81ff, 0xc02c, 0x21, 0 + .dw 0x8240, 0xc02c, 0x827f, 0xc02c, 0x21, 0 + .dw 0x82c0, 0xc02c, 0x82ff, 0xc02c, 0x21, 0 + .dw 0x8340, 0xc02c, 0x837f, 0xc02c, 0x21, 0 + .dw 0x83c0, 0xc02c, 0x83ff, 0xc02c, 0x21, 0 + .dw 0x8440, 0xc02c, 0x847f, 0xc02c, 0x21, 0 + .dw 0x84c0, 0xc02c, 0x84ff, 0xc02c, 0x21, 0 + .dw 0x8540, 0xc02c, 0x857f, 0xc02c, 0x21, 0 + .dw 0x85c0, 0xc02c, 0x85ff, 0xc02c, 0x21, 0 + .dw 0x8640, 0xc02c, 0x867f, 0xc02c, 0x21, 0 + .dw 0x86c0, 0xc02c, 0x86ff, 0xc02c, 0x21, 0 + .dw 0x8740, 0xc02c, 0x877f, 0xc02c, 0x21, 0 + .dw 0x87c0, 0xc02c, 0x87ff, 0xc02c, 0x21, 0 + .dw 0x8840, 0xc02c, 0x887f, 0xc02c, 0x21, 0 + .dw 0x88c0, 0xc02c, 0x88ff, 0xc02c, 0x21, 0 + .dw 0x8940, 0xc02c, 0x897f, 0xc02c, 0x21, 0 + .dw 0x89c0, 0xc02c, 0x89ff, 0xc02c, 0x21, 0 + .dw 0x8a40, 0xc02c, 0x8a7f, 0xc02c, 0x21, 0 + .dw 0x8ac0, 0xc02c, 0x8aff, 0xc02c, 0x21, 0 + .dw 0x8b40, 0xc02c, 0x8b7f, 0xc02c, 0x21, 0 + .dw 0x8bc0, 0xc02c, 0x8bff, 0xc02c, 0x21, 0 + .dw 0x8c40, 0xc02c, 0x8c7f, 0xc02c, 0x21, 0 + .dw 0x8cc0, 0xc02c, 0x8cff, 0xc02c, 0x21, 0 + .dw 0x8d40, 0xc02c, 0x8d7f, 0xc02c, 0x21, 0 + .dw 0x8dc0, 0xc02c, 0x8dff, 0xc02c, 0x21, 0 + .dw 0x8e40, 0xc02c, 0x8e7f, 0xc02c, 0x21, 0 + .dw 0x8ec0, 0xc02c, 0x8eff, 0xc02c, 0x21, 0 + .dw 0x8f40, 0xc02c, 0x8f7f, 0xc02c, 0x21, 0 + .dw 0x8fc0, 0xc02c, 0x8fff, 0xc02c, 0x21, 0 + .dw 0x9040, 0xc02c, 0x907f, 0xc02c, 0x21, 0 + .dw 0x90c0, 0xc02c, 0x90ff, 0xc02c, 0x21, 0 + .dw 0x9140, 0xc02c, 0x917f, 0xc02c, 0x21, 0 + .dw 0x91c0, 0xc02c, 0x91ff, 0xc02c, 0x21, 0 + .dw 0x9240, 0xc02c, 0x927f, 0xc02c, 0x21, 0 + .dw 0x92c0, 0xc02c, 0x92ff, 0xc02c, 0x21, 0 + .dw 0x9340, 0xc02c, 0x937f, 0xc02c, 0x21, 0 + .dw 0x93c0, 0xc02c, 0x93ff, 0xc02c, 0x21, 0 + .dw 0x9440, 0xc02c, 0x947f, 0xc02c, 0x21, 0 + .dw 0x94c0, 0xc02c, 0x94ff, 0xc02c, 0x21, 0 + .dw 0x9540, 0xc02c, 0x957f, 0xc02c, 0x21, 0 + .dw 0x95c0, 0xc02c, 0x95ff, 0xc02c, 0x21, 0 + .dw 0x9640, 0xc02c, 0x967f, 0xc02c, 0x21, 0 + .dw 0x96c0, 0xc02c, 0x96ff, 0xc02c, 0x21, 0 + .dw 0x9740, 0xc02c, 0x977f, 0xc02c, 0x21, 0 + .dw 0x97c0, 0xc02c, 0x97ff, 0xc02c, 0x21, 0 + .dw 0x9840, 0xc02c, 0x987f, 0xc02c, 0x21, 0 + .dw 0x98c0, 0xc02c, 0x98ff, 0xc02c, 0x21, 0 + .dw 0x9940, 0xc02c, 0x997f, 0xc02c, 0x21, 0 + .dw 0x99c0, 0xc02c, 0x9fff, 0xc02c, 0x21, 0 + .dw 0xa040, 0xc02c, 0xa07f, 0xc02c, 0x21, 0 + .dw 0xa0c0, 0xc02c, 0xa0ff, 0xc02c, 0x21, 0 + .dw 0xa140, 0xc02c, 0xa17f, 0xc02c, 0x21, 0 + .dw 0xa1c0, 0xc02c, 0xa1ff, 0xc02c, 0x21, 0 + .dw 0xa240, 0xc02c, 0xa27f, 0xc02c, 0x21, 0 + .dw 0xa2c0, 0xc02c, 0xa2ff, 0xc02c, 0x21, 0 + .dw 0xa340, 0xc02c, 0xa37f, 0xc02c, 0x21, 0 + .dw 0xa3c0, 0xc02c, 0xa3ff, 0xc02c, 0x21, 0 + .dw 0xa440, 0xc02c, 0xa47f, 0xc02c, 0x21, 0 + .dw 0xa4c0, 0xc02c, 0xa4ff, 0xc02c, 0x21, 0 + .dw 0xa540, 0xc02c, 0xa57f, 0xc02c, 0x21, 0 + .dw 0xa5c0, 0xc02c, 0xa5ff, 0xc02c, 0x21, 0 + .dw 0xa640, 0xc02c, 0xa67f, 0xc02c, 0x21, 0 + .dw 0xa6c0, 0xc02c, 0xa6ff, 0xc02c, 0x21, 0 + .dw 0xa740, 0xc02c, 0xa77f, 0xc02c, 0x21, 0 + .dw 0xa7c0, 0xc02c, 0xa7ff, 0xc02c, 0x21, 0 + .dw 0xa840, 0xc02c, 0xa87f, 0xc02c, 0x21, 0 + .dw 0xa8c0, 0xc02c, 0xa8ff, 0xc02c, 0x21, 0 + .dw 0xa940, 0xc02c, 0xa97f, 0xc02c, 0x21, 0 + .dw 0xa9c0, 0xc02c, 0xa9ff, 0xc02c, 0x21, 0 + .dw 0xaa40, 0xc02c, 0xaa7f, 0xc02c, 0x21, 0 + .dw 0xaac0, 0xc02c, 0xaaff, 0xc02c, 0x21, 0 + .dw 0xab40, 0xc02c, 0xab7f, 0xc02c, 0x21, 0 + .dw 0xabc0, 0xc02c, 0xabff, 0xc02c, 0x21, 0 + .dw 0xac40, 0xc02c, 0xac7f, 0xc02c, 0x21, 0 + .dw 0xacc0, 0xc02c, 0xacff, 0xc02c, 0x21, 0 + .dw 0xad40, 0xc02c, 0xad7f, 0xc02c, 0x21, 0 + .dw 0xadc0, 0xc02c, 0xadff, 0xc02c, 0x21, 0 + .dw 0xae40, 0xc02c, 0xae7f, 0xc02c, 0x21, 0 + .dw 0xaec0, 0xc02c, 0xaeff, 0xc02c, 0x21, 0 + .dw 0xaf40, 0xc02c, 0xaf7f, 0xc02c, 0x21, 0 + .dw 0xafc0, 0xc02c, 0xafff, 0xc02c, 0x21, 0 + .dw 0xb040, 0xc02c, 0xb07f, 0xc02c, 0x21, 0 + .dw 0xb0c0, 0xc02c, 0xb0ff, 0xc02c, 0x21, 0 + .dw 0xb140, 0xc02c, 0xb17f, 0xc02c, 0x21, 0 + .dw 0xb1c0, 0xc02c, 0xb1ff, 0xc02c, 0x21, 0 + .dw 0xb240, 0xc02c, 0xb27f, 0xc02c, 0x21, 0 + .dw 0xb2c0, 0xc02c, 0xb2ff, 0xc02c, 0x21, 0 + .dw 0xb340, 0xc02c, 0xb37f, 0xc02c, 0x21, 0 + .dw 0xb3c0, 0xc02c, 0xb3ff, 0xc02c, 0x21, 0 + .dw 0xb440, 0xc02c, 0xb47f, 0xc02c, 0x21, 0 + .dw 0xb4c0, 0xc02c, 0xb4ff, 0xc02c, 0x21, 0 + .dw 0xb540, 0xc02c, 0xb57f, 0xc02c, 0x21, 0 + .dw 0xb5c0, 0xc02c, 0xb5ff, 0xc02c, 0x21, 0 + .dw 0xb640, 0xc02c, 0xb67f, 0xc02c, 0x21, 0 + .dw 0xb6c0, 0xc02c, 0xb6ff, 0xc02c, 0x21, 0 + .dw 0xb740, 0xc02c, 0xb77f, 0xc02c, 0x21, 0 + .dw 0xb7c0, 0xc02c, 0xb7ff, 0xc02c, 0x21, 0 + .dw 0xb840, 0xc02c, 0xb87f, 0xc02c, 0x21, 0 + .dw 0xb8c0, 0xc02c, 0xb8ff, 0xc02c, 0x21, 0 + .dw 0xb940, 0xc02c, 0xb97f, 0xc02c, 0x21, 0 + .dw 0xb9c0, 0xc02c, 0xbfff, 0xc02c, 0x21, 0 + .dw 0xc040, 0xc02c, 0xc07f, 0xc02c, 0x21, 0 + .dw 0xc0c0, 0xc02c, 0xc0ff, 0xc02c, 0x21, 0 + .dw 0xc140, 0xc02c, 0xc17f, 0xc02c, 0x21, 0 + .dw 0xc1c0, 0xc02c, 0xc1ff, 0xc02c, 0x21, 0 + .dw 0xc240, 0xc02c, 0xc27f, 0xc02c, 0x21, 0 + .dw 0xc2c0, 0xc02c, 0xc2ff, 0xc02c, 0x21, 0 + .dw 0xc340, 0xc02c, 0xc37f, 0xc02c, 0x21, 0 + .dw 0xc3c0, 0xc02c, 0xc3ff, 0xc02c, 0x21, 0 + .dw 0xc440, 0xc02c, 0xc47f, 0xc02c, 0x21, 0 + .dw 0xc4c0, 0xc02c, 0xc4ff, 0xc02c, 0x21, 0 + .dw 0xc540, 0xc02c, 0xc57f, 0xc02c, 0x21, 0 + .dw 0xc5c0, 0xc02c, 0xc5ff, 0xc02c, 0x21, 0 + .dw 0xc640, 0xc02c, 0xc67f, 0xc02c, 0x21, 0 + .dw 0xc6c0, 0xc02c, 0xc6ff, 0xc02c, 0x21, 0 + .dw 0xc740, 0xc02c, 0xc77f, 0xc02c, 0x21, 0 + .dw 0xc7c0, 0xc02c, 0xc7ff, 0xc02c, 0x21, 0 + .dw 0xc840, 0xc02c, 0xc87f, 0xc02c, 0x21, 0 + .dw 0xc8c0, 0xc02c, 0xc8ff, 0xc02c, 0x21, 0 + .dw 0xc940, 0xc02c, 0xc97f, 0xc02c, 0x21, 0 + .dw 0xc9c0, 0xc02c, 0xc9ff, 0xc02c, 0x21, 0 + .dw 0xca40, 0xc02c, 0xca7f, 0xc02c, 0x21, 0 + .dw 0xcac0, 0xc02c, 0xcaff, 0xc02c, 0x21, 0 + .dw 0xcb40, 0xc02c, 0xcb7f, 0xc02c, 0x21, 0 + .dw 0xcbc0, 0xc02c, 0xcbff, 0xc02c, 0x21, 0 + .dw 0xcc40, 0xc02c, 0xcc7f, 0xc02c, 0x21, 0 + .dw 0xccc0, 0xc02c, 0xccff, 0xc02c, 0x21, 0 + .dw 0xcd40, 0xc02c, 0xcd7f, 0xc02c, 0x21, 0 + .dw 0xcdc0, 0xc02c, 0xcdff, 0xc02c, 0x21, 0 + .dw 0xce40, 0xc02c, 0xce7f, 0xc02c, 0x21, 0 + .dw 0xcec0, 0xc02c, 0xceff, 0xc02c, 0x21, 0 + .dw 0xcf40, 0xc02c, 0xcf7f, 0xc02c, 0x21, 0 + .dw 0xcfc0, 0xc02c, 0xcfff, 0xc02c, 0x21, 0 + .dw 0xd040, 0xc02c, 0xd07f, 0xc02c, 0x21, 0 + .dw 0xd0c0, 0xc02c, 0xd0ff, 0xc02c, 0x21, 0 + .dw 0xd140, 0xc02c, 0xd17f, 0xc02c, 0x21, 0 + .dw 0xd1c0, 0xc02c, 0xd1ff, 0xc02c, 0x21, 0 + .dw 0xd240, 0xc02c, 0xd27f, 0xc02c, 0x21, 0 + .dw 0xd2c0, 0xc02c, 0xd2ff, 0xc02c, 0x21, 0 + .dw 0xd340, 0xc02c, 0xd37f, 0xc02c, 0x21, 0 + .dw 0xd3c0, 0xc02c, 0xd3ff, 0xc02c, 0x21, 0 + .dw 0xd440, 0xc02c, 0xd47f, 0xc02c, 0x21, 0 + .dw 0xd4c0, 0xc02c, 0xd4ff, 0xc02c, 0x21, 0 + .dw 0xd540, 0xc02c, 0xd57f, 0xc02c, 0x21, 0 + .dw 0xd5c0, 0xc02c, 0xd5ff, 0xc02c, 0x21, 0 + .dw 0xd640, 0xc02c, 0xd67f, 0xc02c, 0x21, 0 + .dw 0xd6c0, 0xc02c, 0xd6ff, 0xc02c, 0x21, 0 + .dw 0xd740, 0xc02c, 0xd77f, 0xc02c, 0x21, 0 + .dw 0xd7c0, 0xc02c, 0xd7ff, 0xc02c, 0x21, 0 + .dw 0xd840, 0xc02c, 0xd87f, 0xc02c, 0x21, 0 + .dw 0xd8c0, 0xc02c, 0xd8ff, 0xc02c, 0x21, 0 + .dw 0xd940, 0xc02c, 0xd97f, 0xc02c, 0x21, 0 + .dw 0xd9c0, 0xc02c, 0xdfff, 0xc02c, 0x21, 0 + .dw 0xe040, 0xc02c, 0xe07f, 0xc02c, 0x21, 0 + .dw 0xe0c0, 0xc02c, 0xe0ff, 0xc02c, 0x21, 0 + .dw 0xe140, 0xc02c, 0xe17f, 0xc02c, 0x21, 0 + .dw 0xe1c0, 0xc02c, 0xe1ff, 0xc02c, 0x21, 0 + .dw 0xe240, 0xc02c, 0xe27f, 0xc02c, 0x21, 0 + .dw 0xe2c0, 0xc02c, 0xe2ff, 0xc02c, 0x21, 0 + .dw 0xe340, 0xc02c, 0xe37f, 0xc02c, 0x21, 0 + .dw 0xe3c0, 0xc02c, 0xe3ff, 0xc02c, 0x21, 0 + .dw 0xe440, 0xc02c, 0xe47f, 0xc02c, 0x21, 0 + .dw 0xe4c0, 0xc02c, 0xe4ff, 0xc02c, 0x21, 0 + .dw 0xe540, 0xc02c, 0xe57f, 0xc02c, 0x21, 0 + .dw 0xe5c0, 0xc02c, 0xe5ff, 0xc02c, 0x21, 0 + .dw 0xe640, 0xc02c, 0xe67f, 0xc02c, 0x21, 0 + .dw 0xe6c0, 0xc02c, 0xe6ff, 0xc02c, 0x21, 0 + .dw 0xe740, 0xc02c, 0xe77f, 0xc02c, 0x21, 0 + .dw 0xe7c0, 0xc02c, 0xe7ff, 0xc02c, 0x21, 0 + .dw 0xe840, 0xc02c, 0xe87f, 0xc02c, 0x21, 0 + .dw 0xe8c0, 0xc02c, 0xe8ff, 0xc02c, 0x21, 0 + .dw 0xe940, 0xc02c, 0xe97f, 0xc02c, 0x21, 0 + .dw 0xe9c0, 0xc02c, 0xe9ff, 0xc02c, 0x21, 0 + .dw 0xea40, 0xc02c, 0xea7f, 0xc02c, 0x21, 0 + .dw 0xeac0, 0xc02c, 0xeaff, 0xc02c, 0x21, 0 + .dw 0xeb40, 0xc02c, 0xeb7f, 0xc02c, 0x21, 0 + .dw 0xebc0, 0xc02c, 0xebff, 0xc02c, 0x21, 0 + .dw 0xec40, 0xc02c, 0xec7f, 0xc02c, 0x21, 0 + .dw 0xecc0, 0xc02c, 0xecff, 0xc02c, 0x21, 0 + .dw 0xed40, 0xc02c, 0xed7f, 0xc02c, 0x21, 0 + .dw 0xedc0, 0xc02c, 0xedff, 0xc02c, 0x21, 0 + .dw 0xee40, 0xc02c, 0xee7f, 0xc02c, 0x21, 0 + .dw 0xeec0, 0xc02c, 0xeeff, 0xc02c, 0x21, 0 + .dw 0xef40, 0xc02c, 0xef7f, 0xc02c, 0x21, 0 + .dw 0xefc0, 0xc02c, 0xefff, 0xc02c, 0x21, 0 + .dw 0xf040, 0xc02c, 0xf07f, 0xc02c, 0x21, 0 + .dw 0xf0c0, 0xc02c, 0xf0ff, 0xc02c, 0x21, 0 + .dw 0xf140, 0xc02c, 0xf17f, 0xc02c, 0x21, 0 + .dw 0xf1c0, 0xc02c, 0xf1ff, 0xc02c, 0x21, 0 + .dw 0xf240, 0xc02c, 0xf27f, 0xc02c, 0x21, 0 + .dw 0xf2c0, 0xc02c, 0xf2ff, 0xc02c, 0x21, 0 + .dw 0xf340, 0xc02c, 0xf37f, 0xc02c, 0x21, 0 + .dw 0xf3c0, 0xc02c, 0xf3ff, 0xc02c, 0x21, 0 + .dw 0xf440, 0xc02c, 0xf47f, 0xc02c, 0x21, 0 + .dw 0xf4c0, 0xc02c, 0xf4ff, 0xc02c, 0x21, 0 + .dw 0xf540, 0xc02c, 0xf57f, 0xc02c, 0x21, 0 + .dw 0xf5c0, 0xc02c, 0xf5ff, 0xc02c, 0x21, 0 + .dw 0xf640, 0xc02c, 0xf67f, 0xc02c, 0x21, 0 + .dw 0xf6c0, 0xc02c, 0xf6ff, 0xc02c, 0x21, 0 + .dw 0xf740, 0xc02c, 0xf77f, 0xc02c, 0x21, 0 + .dw 0xf7c0, 0xc02c, 0xf7ff, 0xc02c, 0x21, 0 + .dw 0xf840, 0xc02c, 0xf87f, 0xc02c, 0x21, 0 + .dw 0xf8c0, 0xc02c, 0xf8ff, 0xc02c, 0x21, 0 + .dw 0xf940, 0xc02c, 0xf97f, 0xc02c, 0x21, 0 + .dw 0xf9c0, 0xc02c, 0xffff, 0xc02c, 0x21, 0 + .dw 0x0040, 0xc02d, 0x007f, 0xc02d, 0x21, 0 + .dw 0x00c0, 0xc02d, 0x00ff, 0xc02d, 0x21, 0 + .dw 0x0140, 0xc02d, 0x017f, 0xc02d, 0x21, 0 + .dw 0x01c0, 0xc02d, 0x01ff, 0xc02d, 0x21, 0 + .dw 0x0240, 0xc02d, 0x027f, 0xc02d, 0x21, 0 + .dw 0x02c0, 0xc02d, 0x02ff, 0xc02d, 0x21, 0 + .dw 0x0340, 0xc02d, 0x037f, 0xc02d, 0x21, 0 + .dw 0x03c0, 0xc02d, 0x03ff, 0xc02d, 0x21, 0 + .dw 0x0440, 0xc02d, 0x047f, 0xc02d, 0x21, 0 + .dw 0x04c0, 0xc02d, 0x04ff, 0xc02d, 0x21, 0 + .dw 0x0540, 0xc02d, 0x057f, 0xc02d, 0x21, 0 + .dw 0x05c0, 0xc02d, 0x05ff, 0xc02d, 0x21, 0 + .dw 0x0640, 0xc02d, 0x067f, 0xc02d, 0x21, 0 + .dw 0x06c0, 0xc02d, 0x06ff, 0xc02d, 0x21, 0 + .dw 0x0740, 0xc02d, 0x077f, 0xc02d, 0x21, 0 + .dw 0x07c0, 0xc02d, 0x07ff, 0xc02d, 0x21, 0 + .dw 0x0840, 0xc02d, 0x087f, 0xc02d, 0x21, 0 + .dw 0x08c0, 0xc02d, 0x08ff, 0xc02d, 0x21, 0 + .dw 0x0940, 0xc02d, 0x097f, 0xc02d, 0x21, 0 + .dw 0x09c0, 0xc02d, 0x09ff, 0xc02d, 0x21, 0 + .dw 0x0a40, 0xc02d, 0x0a7f, 0xc02d, 0x21, 0 + .dw 0x0ac0, 0xc02d, 0x0aff, 0xc02d, 0x21, 0 + .dw 0x0b40, 0xc02d, 0x0b7f, 0xc02d, 0x21, 0 + .dw 0x0bc0, 0xc02d, 0x0bff, 0xc02d, 0x21, 0 + .dw 0x0c40, 0xc02d, 0x0c7f, 0xc02d, 0x21, 0 + .dw 0x0cc0, 0xc02d, 0x0cff, 0xc02d, 0x21, 0 + .dw 0x0d40, 0xc02d, 0x0d7f, 0xc02d, 0x21, 0 + .dw 0x0dc0, 0xc02d, 0x0dff, 0xc02d, 0x21, 0 + .dw 0x0e40, 0xc02d, 0x0e7f, 0xc02d, 0x21, 0 + .dw 0x0ec0, 0xc02d, 0x0eff, 0xc02d, 0x21, 0 + .dw 0x0f40, 0xc02d, 0x0f7f, 0xc02d, 0x21, 0 + .dw 0x0fc0, 0xc02d, 0x0fff, 0xc02d, 0x21, 0 + .dw 0x1040, 0xc02d, 0x107f, 0xc02d, 0x21, 0 + .dw 0x10c0, 0xc02d, 0x10ff, 0xc02d, 0x21, 0 + .dw 0x1140, 0xc02d, 0x117f, 0xc02d, 0x21, 0 + .dw 0x11c0, 0xc02d, 0x11ff, 0xc02d, 0x21, 0 + .dw 0x1240, 0xc02d, 0x127f, 0xc02d, 0x21, 0 + .dw 0x12c0, 0xc02d, 0x12ff, 0xc02d, 0x21, 0 + .dw 0x1340, 0xc02d, 0x137f, 0xc02d, 0x21, 0 + .dw 0x13c0, 0xc02d, 0x13ff, 0xc02d, 0x21, 0 + .dw 0x1440, 0xc02d, 0x147f, 0xc02d, 0x21, 0 + .dw 0x14c0, 0xc02d, 0x14ff, 0xc02d, 0x21, 0 + .dw 0x1540, 0xc02d, 0x157f, 0xc02d, 0x21, 0 + .dw 0x15c0, 0xc02d, 0x15ff, 0xc02d, 0x21, 0 + .dw 0x1640, 0xc02d, 0x167f, 0xc02d, 0x21, 0 + .dw 0x16c0, 0xc02d, 0x16ff, 0xc02d, 0x21, 0 + .dw 0x1740, 0xc02d, 0x177f, 0xc02d, 0x21, 0 + .dw 0x17c0, 0xc02d, 0x17ff, 0xc02d, 0x21, 0 + .dw 0x1840, 0xc02d, 0x187f, 0xc02d, 0x21, 0 + .dw 0x18c0, 0xc02d, 0x18ff, 0xc02d, 0x21, 0 + .dw 0x1940, 0xc02d, 0x197f, 0xc02d, 0x21, 0 + .dw 0x19c0, 0xc02d, 0x1fff, 0xc02d, 0x21, 0 + .dw 0x2040, 0xc02d, 0x207f, 0xc02d, 0x21, 0 + .dw 0x20c0, 0xc02d, 0x20ff, 0xc02d, 0x21, 0 + .dw 0x2140, 0xc02d, 0x217f, 0xc02d, 0x21, 0 + .dw 0x21c0, 0xc02d, 0x21ff, 0xc02d, 0x21, 0 + .dw 0x2240, 0xc02d, 0x227f, 0xc02d, 0x21, 0 + .dw 0x22c0, 0xc02d, 0x22ff, 0xc02d, 0x21, 0 + .dw 0x2340, 0xc02d, 0x237f, 0xc02d, 0x21, 0 + .dw 0x23c0, 0xc02d, 0x23ff, 0xc02d, 0x21, 0 + .dw 0x2440, 0xc02d, 0x247f, 0xc02d, 0x21, 0 + .dw 0x24c0, 0xc02d, 0x24ff, 0xc02d, 0x21, 0 + .dw 0x2540, 0xc02d, 0x257f, 0xc02d, 0x21, 0 + .dw 0x25c0, 0xc02d, 0x25ff, 0xc02d, 0x21, 0 + .dw 0x2640, 0xc02d, 0x267f, 0xc02d, 0x21, 0 + .dw 0x26c0, 0xc02d, 0x26ff, 0xc02d, 0x21, 0 + .dw 0x2740, 0xc02d, 0x277f, 0xc02d, 0x21, 0 + .dw 0x27c0, 0xc02d, 0x27ff, 0xc02d, 0x21, 0 + .dw 0x2840, 0xc02d, 0x287f, 0xc02d, 0x21, 0 + .dw 0x28c0, 0xc02d, 0x28ff, 0xc02d, 0x21, 0 + .dw 0x2940, 0xc02d, 0x297f, 0xc02d, 0x21, 0 + .dw 0x29c0, 0xc02d, 0x29ff, 0xc02d, 0x21, 0 + .dw 0x2a40, 0xc02d, 0x2a7f, 0xc02d, 0x21, 0 + .dw 0x2ac0, 0xc02d, 0x2aff, 0xc02d, 0x21, 0 + .dw 0x2b40, 0xc02d, 0x2b7f, 0xc02d, 0x21, 0 + .dw 0x2bc0, 0xc02d, 0x2bff, 0xc02d, 0x21, 0 + .dw 0x2c40, 0xc02d, 0x2c7f, 0xc02d, 0x21, 0 + .dw 0x2cc0, 0xc02d, 0x2cff, 0xc02d, 0x21, 0 + .dw 0x2d40, 0xc02d, 0x2d7f, 0xc02d, 0x21, 0 + .dw 0x2dc0, 0xc02d, 0x2dff, 0xc02d, 0x21, 0 + .dw 0x2e40, 0xc02d, 0x2e7f, 0xc02d, 0x21, 0 + .dw 0x2ec0, 0xc02d, 0x2eff, 0xc02d, 0x21, 0 + .dw 0x2f40, 0xc02d, 0x2f7f, 0xc02d, 0x21, 0 + .dw 0x2fc0, 0xc02d, 0x2fff, 0xc02d, 0x21, 0 + .dw 0x3040, 0xc02d, 0x307f, 0xc02d, 0x21, 0 + .dw 0x30c0, 0xc02d, 0x30ff, 0xc02d, 0x21, 0 + .dw 0x3140, 0xc02d, 0x317f, 0xc02d, 0x21, 0 + .dw 0x31c0, 0xc02d, 0x31ff, 0xc02d, 0x21, 0 + .dw 0x3240, 0xc02d, 0x327f, 0xc02d, 0x21, 0 + .dw 0x32c0, 0xc02d, 0x32ff, 0xc02d, 0x21, 0 + .dw 0x3340, 0xc02d, 0x337f, 0xc02d, 0x21, 0 + .dw 0x33c0, 0xc02d, 0x33ff, 0xc02d, 0x21, 0 + .dw 0x3440, 0xc02d, 0x347f, 0xc02d, 0x21, 0 + .dw 0x34c0, 0xc02d, 0x34ff, 0xc02d, 0x21, 0 + .dw 0x3540, 0xc02d, 0x357f, 0xc02d, 0x21, 0 + .dw 0x35c0, 0xc02d, 0x35ff, 0xc02d, 0x21, 0 + .dw 0x3640, 0xc02d, 0x367f, 0xc02d, 0x21, 0 + .dw 0x36c0, 0xc02d, 0x36ff, 0xc02d, 0x21, 0 + .dw 0x3740, 0xc02d, 0x377f, 0xc02d, 0x21, 0 + .dw 0x37c0, 0xc02d, 0x37ff, 0xc02d, 0x21, 0 + .dw 0x3840, 0xc02d, 0x387f, 0xc02d, 0x21, 0 + .dw 0x38c0, 0xc02d, 0x38ff, 0xc02d, 0x21, 0 + .dw 0x3940, 0xc02d, 0x397f, 0xc02d, 0x21, 0 + .dw 0x39c0, 0xc02d, 0x3fff, 0xc02d, 0x21, 0 + .dw 0x4040, 0xc02d, 0x407f, 0xc02d, 0x21, 0 + .dw 0x40c0, 0xc02d, 0x40ff, 0xc02d, 0x21, 0 + .dw 0x4140, 0xc02d, 0x417f, 0xc02d, 0x21, 0 + .dw 0x41c0, 0xc02d, 0x41ff, 0xc02d, 0x21, 0 + .dw 0x4240, 0xc02d, 0x427f, 0xc02d, 0x21, 0 + .dw 0x42c0, 0xc02d, 0x42ff, 0xc02d, 0x21, 0 + .dw 0x4340, 0xc02d, 0x437f, 0xc02d, 0x21, 0 + .dw 0x43c0, 0xc02d, 0x43ff, 0xc02d, 0x21, 0 + .dw 0x4440, 0xc02d, 0x447f, 0xc02d, 0x21, 0 + .dw 0x44c0, 0xc02d, 0x44ff, 0xc02d, 0x21, 0 + .dw 0x4540, 0xc02d, 0x457f, 0xc02d, 0x21, 0 + .dw 0x45c0, 0xc02d, 0x45ff, 0xc02d, 0x21, 0 + .dw 0x4640, 0xc02d, 0x467f, 0xc02d, 0x21, 0 + .dw 0x46c0, 0xc02d, 0x46ff, 0xc02d, 0x21, 0 + .dw 0x4740, 0xc02d, 0x477f, 0xc02d, 0x21, 0 + .dw 0x47c0, 0xc02d, 0x47ff, 0xc02d, 0x21, 0 + .dw 0x4840, 0xc02d, 0x487f, 0xc02d, 0x21, 0 + .dw 0x48c0, 0xc02d, 0x48ff, 0xc02d, 0x21, 0 + .dw 0x4940, 0xc02d, 0x497f, 0xc02d, 0x21, 0 + .dw 0x49c0, 0xc02d, 0x49ff, 0xc02d, 0x21, 0 + .dw 0x4a40, 0xc02d, 0x4a7f, 0xc02d, 0x21, 0 + .dw 0x4ac0, 0xc02d, 0x4aff, 0xc02d, 0x21, 0 + .dw 0x4b40, 0xc02d, 0x4b7f, 0xc02d, 0x21, 0 + .dw 0x4bc0, 0xc02d, 0x4bff, 0xc02d, 0x21, 0 + .dw 0x4c40, 0xc02d, 0x4c7f, 0xc02d, 0x21, 0 + .dw 0x4cc0, 0xc02d, 0x4cff, 0xc02d, 0x21, 0 + .dw 0x4d40, 0xc02d, 0x4d7f, 0xc02d, 0x21, 0 + .dw 0x4dc0, 0xc02d, 0x4dff, 0xc02d, 0x21, 0 + .dw 0x4e40, 0xc02d, 0x4e7f, 0xc02d, 0x21, 0 + .dw 0x4ec0, 0xc02d, 0x4eff, 0xc02d, 0x21, 0 + .dw 0x4f40, 0xc02d, 0x4f7f, 0xc02d, 0x21, 0 + .dw 0x4fc0, 0xc02d, 0x4fff, 0xc02d, 0x21, 0 + .dw 0x5040, 0xc02d, 0x507f, 0xc02d, 0x21, 0 + .dw 0x50c0, 0xc02d, 0x50ff, 0xc02d, 0x21, 0 + .dw 0x5140, 0xc02d, 0x517f, 0xc02d, 0x21, 0 + .dw 0x51c0, 0xc02d, 0x51ff, 0xc02d, 0x21, 0 + .dw 0x5240, 0xc02d, 0x527f, 0xc02d, 0x21, 0 + .dw 0x52c0, 0xc02d, 0x52ff, 0xc02d, 0x21, 0 + .dw 0x5340, 0xc02d, 0x537f, 0xc02d, 0x21, 0 + .dw 0x53c0, 0xc02d, 0x53ff, 0xc02d, 0x21, 0 + .dw 0x5440, 0xc02d, 0x547f, 0xc02d, 0x21, 0 + .dw 0x54c0, 0xc02d, 0x54ff, 0xc02d, 0x21, 0 + .dw 0x5540, 0xc02d, 0x557f, 0xc02d, 0x21, 0 + .dw 0x55c0, 0xc02d, 0x55ff, 0xc02d, 0x21, 0 + .dw 0x5640, 0xc02d, 0x567f, 0xc02d, 0x21, 0 + .dw 0x56c0, 0xc02d, 0x56ff, 0xc02d, 0x21, 0 + .dw 0x5740, 0xc02d, 0x577f, 0xc02d, 0x21, 0 + .dw 0x57c0, 0xc02d, 0x57ff, 0xc02d, 0x21, 0 + .dw 0x5840, 0xc02d, 0x587f, 0xc02d, 0x21, 0 + .dw 0x58c0, 0xc02d, 0x58ff, 0xc02d, 0x21, 0 + .dw 0x5940, 0xc02d, 0x597f, 0xc02d, 0x21, 0 + .dw 0x59c0, 0xc02d, 0x5fff, 0xc02d, 0x21, 0 + .dw 0x6040, 0xc02d, 0x607f, 0xc02d, 0x21, 0 + .dw 0x60c0, 0xc02d, 0x60ff, 0xc02d, 0x21, 0 + .dw 0x6140, 0xc02d, 0x617f, 0xc02d, 0x21, 0 + .dw 0x61c0, 0xc02d, 0x61ff, 0xc02d, 0x21, 0 + .dw 0x6240, 0xc02d, 0x627f, 0xc02d, 0x21, 0 + .dw 0x62c0, 0xc02d, 0x62ff, 0xc02d, 0x21, 0 + .dw 0x6340, 0xc02d, 0x637f, 0xc02d, 0x21, 0 + .dw 0x63c0, 0xc02d, 0x63ff, 0xc02d, 0x21, 0 + .dw 0x6440, 0xc02d, 0x647f, 0xc02d, 0x21, 0 + .dw 0x64c0, 0xc02d, 0x64ff, 0xc02d, 0x21, 0 + .dw 0x6540, 0xc02d, 0x657f, 0xc02d, 0x21, 0 + .dw 0x65c0, 0xc02d, 0x65ff, 0xc02d, 0x21, 0 + .dw 0x6640, 0xc02d, 0x667f, 0xc02d, 0x21, 0 + .dw 0x66c0, 0xc02d, 0x66ff, 0xc02d, 0x21, 0 + .dw 0x6740, 0xc02d, 0x677f, 0xc02d, 0x21, 0 + .dw 0x67c0, 0xc02d, 0x67ff, 0xc02d, 0x21, 0 + .dw 0x6840, 0xc02d, 0x687f, 0xc02d, 0x21, 0 + .dw 0x68c0, 0xc02d, 0x68ff, 0xc02d, 0x21, 0 + .dw 0x6940, 0xc02d, 0x697f, 0xc02d, 0x21, 0 + .dw 0x69c0, 0xc02d, 0x69ff, 0xc02d, 0x21, 0 + .dw 0x6a40, 0xc02d, 0x6a7f, 0xc02d, 0x21, 0 + .dw 0x6ac0, 0xc02d, 0x6aff, 0xc02d, 0x21, 0 + .dw 0x6b40, 0xc02d, 0x6b7f, 0xc02d, 0x21, 0 + .dw 0x6bc0, 0xc02d, 0x6bff, 0xc02d, 0x21, 0 + .dw 0x6c40, 0xc02d, 0x6c7f, 0xc02d, 0x21, 0 + .dw 0x6cc0, 0xc02d, 0x6cff, 0xc02d, 0x21, 0 + .dw 0x6d40, 0xc02d, 0x6d7f, 0xc02d, 0x21, 0 + .dw 0x6dc0, 0xc02d, 0x6dff, 0xc02d, 0x21, 0 + .dw 0x6e40, 0xc02d, 0x6e7f, 0xc02d, 0x21, 0 + .dw 0x6ec0, 0xc02d, 0x6eff, 0xc02d, 0x21, 0 + .dw 0x6f40, 0xc02d, 0x6f7f, 0xc02d, 0x21, 0 + .dw 0x6fc0, 0xc02d, 0x6fff, 0xc02d, 0x21, 0 + .dw 0x7040, 0xc02d, 0x707f, 0xc02d, 0x21, 0 + .dw 0x70c0, 0xc02d, 0x70ff, 0xc02d, 0x21, 0 + .dw 0x7140, 0xc02d, 0x717f, 0xc02d, 0x21, 0 + .dw 0x71c0, 0xc02d, 0x71ff, 0xc02d, 0x21, 0 + .dw 0x7240, 0xc02d, 0x727f, 0xc02d, 0x21, 0 + .dw 0x72c0, 0xc02d, 0x72ff, 0xc02d, 0x21, 0 + .dw 0x7340, 0xc02d, 0x737f, 0xc02d, 0x21, 0 + .dw 0x73c0, 0xc02d, 0x73ff, 0xc02d, 0x21, 0 + .dw 0x7440, 0xc02d, 0x747f, 0xc02d, 0x21, 0 + .dw 0x74c0, 0xc02d, 0x74ff, 0xc02d, 0x21, 0 + .dw 0x7540, 0xc02d, 0x757f, 0xc02d, 0x21, 0 + .dw 0x75c0, 0xc02d, 0x75ff, 0xc02d, 0x21, 0 + .dw 0x7640, 0xc02d, 0x767f, 0xc02d, 0x21, 0 + .dw 0x76c0, 0xc02d, 0x76ff, 0xc02d, 0x21, 0 + .dw 0x7740, 0xc02d, 0x777f, 0xc02d, 0x21, 0 + .dw 0x77c0, 0xc02d, 0x77ff, 0xc02d, 0x21, 0 + .dw 0x7840, 0xc02d, 0x787f, 0xc02d, 0x21, 0 + .dw 0x78c0, 0xc02d, 0x78ff, 0xc02d, 0x21, 0 + .dw 0x7940, 0xc02d, 0x797f, 0xc02d, 0x21, 0 + .dw 0x79c0, 0xc02d, 0x7fff, 0xc02d, 0x21, 0 + .dw 0x8040, 0xc02d, 0x807f, 0xc02d, 0x21, 0 + .dw 0x80c0, 0xc02d, 0x80ff, 0xc02d, 0x21, 0 + .dw 0x8140, 0xc02d, 0x817f, 0xc02d, 0x21, 0 + .dw 0x81c0, 0xc02d, 0x81ff, 0xc02d, 0x21, 0 + .dw 0x8240, 0xc02d, 0x827f, 0xc02d, 0x21, 0 + .dw 0x82c0, 0xc02d, 0x82ff, 0xc02d, 0x21, 0 + .dw 0x8340, 0xc02d, 0x837f, 0xc02d, 0x21, 0 + .dw 0x83c0, 0xc02d, 0x83ff, 0xc02d, 0x21, 0 + .dw 0x8440, 0xc02d, 0x847f, 0xc02d, 0x21, 0 + .dw 0x84c0, 0xc02d, 0x84ff, 0xc02d, 0x21, 0 + .dw 0x8540, 0xc02d, 0x857f, 0xc02d, 0x21, 0 + .dw 0x85c0, 0xc02d, 0x85ff, 0xc02d, 0x21, 0 + .dw 0x8640, 0xc02d, 0x867f, 0xc02d, 0x21, 0 + .dw 0x86c0, 0xc02d, 0x86ff, 0xc02d, 0x21, 0 + .dw 0x8740, 0xc02d, 0x877f, 0xc02d, 0x21, 0 + .dw 0x87c0, 0xc02d, 0x87ff, 0xc02d, 0x21, 0 + .dw 0x8840, 0xc02d, 0x887f, 0xc02d, 0x21, 0 + .dw 0x88c0, 0xc02d, 0x88ff, 0xc02d, 0x21, 0 + .dw 0x8940, 0xc02d, 0x897f, 0xc02d, 0x21, 0 + .dw 0x89c0, 0xc02d, 0x89ff, 0xc02d, 0x21, 0 + .dw 0x8a40, 0xc02d, 0x8a7f, 0xc02d, 0x21, 0 + .dw 0x8ac0, 0xc02d, 0x8aff, 0xc02d, 0x21, 0 + .dw 0x8b40, 0xc02d, 0x8b7f, 0xc02d, 0x21, 0 + .dw 0x8bc0, 0xc02d, 0x8bff, 0xc02d, 0x21, 0 + .dw 0x8c40, 0xc02d, 0x8c7f, 0xc02d, 0x21, 0 + .dw 0x8cc0, 0xc02d, 0x8cff, 0xc02d, 0x21, 0 + .dw 0x8d40, 0xc02d, 0x8d7f, 0xc02d, 0x21, 0 + .dw 0x8dc0, 0xc02d, 0x8dff, 0xc02d, 0x21, 0 + .dw 0x8e40, 0xc02d, 0x8e7f, 0xc02d, 0x21, 0 + .dw 0x8ec0, 0xc02d, 0x8eff, 0xc02d, 0x21, 0 + .dw 0x8f40, 0xc02d, 0x8f7f, 0xc02d, 0x21, 0 + .dw 0x8fc0, 0xc02d, 0x8fff, 0xc02d, 0x21, 0 + .dw 0x9040, 0xc02d, 0x907f, 0xc02d, 0x21, 0 + .dw 0x90c0, 0xc02d, 0x90ff, 0xc02d, 0x21, 0 + .dw 0x9140, 0xc02d, 0x917f, 0xc02d, 0x21, 0 + .dw 0x91c0, 0xc02d, 0x91ff, 0xc02d, 0x21, 0 + .dw 0x9240, 0xc02d, 0x927f, 0xc02d, 0x21, 0 + .dw 0x92c0, 0xc02d, 0x92ff, 0xc02d, 0x21, 0 + .dw 0x9340, 0xc02d, 0x937f, 0xc02d, 0x21, 0 + .dw 0x93c0, 0xc02d, 0x93ff, 0xc02d, 0x21, 0 + .dw 0x9440, 0xc02d, 0x947f, 0xc02d, 0x21, 0 + .dw 0x94c0, 0xc02d, 0x94ff, 0xc02d, 0x21, 0 + .dw 0x9540, 0xc02d, 0x957f, 0xc02d, 0x21, 0 + .dw 0x95c0, 0xc02d, 0x95ff, 0xc02d, 0x21, 0 + .dw 0x9640, 0xc02d, 0x967f, 0xc02d, 0x21, 0 + .dw 0x96c0, 0xc02d, 0x96ff, 0xc02d, 0x21, 0 + .dw 0x9740, 0xc02d, 0x977f, 0xc02d, 0x21, 0 + .dw 0x97c0, 0xc02d, 0x97ff, 0xc02d, 0x21, 0 + .dw 0x9840, 0xc02d, 0x987f, 0xc02d, 0x21, 0 + .dw 0x98c0, 0xc02d, 0x98ff, 0xc02d, 0x21, 0 + .dw 0x9940, 0xc02d, 0x997f, 0xc02d, 0x21, 0 + .dw 0x99c0, 0xc02d, 0x9fff, 0xc02d, 0x21, 0 + .dw 0xa040, 0xc02d, 0xa07f, 0xc02d, 0x21, 0 + .dw 0xa0c0, 0xc02d, 0xa0ff, 0xc02d, 0x21, 0 + .dw 0xa140, 0xc02d, 0xa17f, 0xc02d, 0x21, 0 + .dw 0xa1c0, 0xc02d, 0xa1ff, 0xc02d, 0x21, 0 + .dw 0xa240, 0xc02d, 0xa27f, 0xc02d, 0x21, 0 + .dw 0xa2c0, 0xc02d, 0xa2ff, 0xc02d, 0x21, 0 + .dw 0xa340, 0xc02d, 0xa37f, 0xc02d, 0x21, 0 + .dw 0xa3c0, 0xc02d, 0xa3ff, 0xc02d, 0x21, 0 + .dw 0xa440, 0xc02d, 0xa47f, 0xc02d, 0x21, 0 + .dw 0xa4c0, 0xc02d, 0xa4ff, 0xc02d, 0x21, 0 + .dw 0xa540, 0xc02d, 0xa57f, 0xc02d, 0x21, 0 + .dw 0xa5c0, 0xc02d, 0xa5ff, 0xc02d, 0x21, 0 + .dw 0xa640, 0xc02d, 0xa67f, 0xc02d, 0x21, 0 + .dw 0xa6c0, 0xc02d, 0xa6ff, 0xc02d, 0x21, 0 + .dw 0xa740, 0xc02d, 0xa77f, 0xc02d, 0x21, 0 + .dw 0xa7c0, 0xc02d, 0xa7ff, 0xc02d, 0x21, 0 + .dw 0xa840, 0xc02d, 0xa87f, 0xc02d, 0x21, 0 + .dw 0xa8c0, 0xc02d, 0xa8ff, 0xc02d, 0x21, 0 + .dw 0xa940, 0xc02d, 0xa97f, 0xc02d, 0x21, 0 + .dw 0xa9c0, 0xc02d, 0xa9ff, 0xc02d, 0x21, 0 + .dw 0xaa40, 0xc02d, 0xaa7f, 0xc02d, 0x21, 0 + .dw 0xaac0, 0xc02d, 0xaaff, 0xc02d, 0x21, 0 + .dw 0xab40, 0xc02d, 0xab7f, 0xc02d, 0x21, 0 + .dw 0xabc0, 0xc02d, 0xabff, 0xc02d, 0x21, 0 + .dw 0xac40, 0xc02d, 0xac7f, 0xc02d, 0x21, 0 + .dw 0xacc0, 0xc02d, 0xacff, 0xc02d, 0x21, 0 + .dw 0xad40, 0xc02d, 0xad7f, 0xc02d, 0x21, 0 + .dw 0xadc0, 0xc02d, 0xadff, 0xc02d, 0x21, 0 + .dw 0xae40, 0xc02d, 0xae7f, 0xc02d, 0x21, 0 + .dw 0xaec0, 0xc02d, 0xaeff, 0xc02d, 0x21, 0 + .dw 0xaf40, 0xc02d, 0xaf7f, 0xc02d, 0x21, 0 + .dw 0xafc0, 0xc02d, 0xafff, 0xc02d, 0x21, 0 + .dw 0xb040, 0xc02d, 0xb07f, 0xc02d, 0x21, 0 + .dw 0xb0c0, 0xc02d, 0xb0ff, 0xc02d, 0x21, 0 + .dw 0xb140, 0xc02d, 0xb17f, 0xc02d, 0x21, 0 + .dw 0xb1c0, 0xc02d, 0xb1ff, 0xc02d, 0x21, 0 + .dw 0xb240, 0xc02d, 0xb27f, 0xc02d, 0x21, 0 + .dw 0xb2c0, 0xc02d, 0xb2ff, 0xc02d, 0x21, 0 + .dw 0xb340, 0xc02d, 0xb37f, 0xc02d, 0x21, 0 + .dw 0xb3c0, 0xc02d, 0xb3ff, 0xc02d, 0x21, 0 + .dw 0xb440, 0xc02d, 0xb47f, 0xc02d, 0x21, 0 + .dw 0xb4c0, 0xc02d, 0xb4ff, 0xc02d, 0x21, 0 + .dw 0xb540, 0xc02d, 0xb57f, 0xc02d, 0x21, 0 + .dw 0xb5c0, 0xc02d, 0xb5ff, 0xc02d, 0x21, 0 + .dw 0xb640, 0xc02d, 0xb67f, 0xc02d, 0x21, 0 + .dw 0xb6c0, 0xc02d, 0xb6ff, 0xc02d, 0x21, 0 + .dw 0xb740, 0xc02d, 0xb77f, 0xc02d, 0x21, 0 + .dw 0xb7c0, 0xc02d, 0xb7ff, 0xc02d, 0x21, 0 + .dw 0xb840, 0xc02d, 0xb87f, 0xc02d, 0x21, 0 + .dw 0xb8c0, 0xc02d, 0xb8ff, 0xc02d, 0x21, 0 + .dw 0xb940, 0xc02d, 0xb97f, 0xc02d, 0x21, 0 + .dw 0xb9c0, 0xc02d, 0xbfff, 0xc02d, 0x21, 0 + .dw 0xc040, 0xc02d, 0xc07f, 0xc02d, 0x21, 0 + .dw 0xc0c0, 0xc02d, 0xc0ff, 0xc02d, 0x21, 0 + .dw 0xc140, 0xc02d, 0xc17f, 0xc02d, 0x21, 0 + .dw 0xc1c0, 0xc02d, 0xc1ff, 0xc02d, 0x21, 0 + .dw 0xc240, 0xc02d, 0xc27f, 0xc02d, 0x21, 0 + .dw 0xc2c0, 0xc02d, 0xc2ff, 0xc02d, 0x21, 0 + .dw 0xc340, 0xc02d, 0xc37f, 0xc02d, 0x21, 0 + .dw 0xc3c0, 0xc02d, 0xc3ff, 0xc02d, 0x21, 0 + .dw 0xc440, 0xc02d, 0xc47f, 0xc02d, 0x21, 0 + .dw 0xc4c0, 0xc02d, 0xc4ff, 0xc02d, 0x21, 0 + .dw 0xc540, 0xc02d, 0xc57f, 0xc02d, 0x21, 0 + .dw 0xc5c0, 0xc02d, 0xc5ff, 0xc02d, 0x21, 0 + .dw 0xc640, 0xc02d, 0xc67f, 0xc02d, 0x21, 0 + .dw 0xc6c0, 0xc02d, 0xc6ff, 0xc02d, 0x21, 0 + .dw 0xc740, 0xc02d, 0xc77f, 0xc02d, 0x21, 0 + .dw 0xc7c0, 0xc02d, 0xc7ff, 0xc02d, 0x21, 0 + .dw 0xc840, 0xc02d, 0xc87f, 0xc02d, 0x21, 0 + .dw 0xc8c0, 0xc02d, 0xc8ff, 0xc02d, 0x21, 0 + .dw 0xc940, 0xc02d, 0xc97f, 0xc02d, 0x21, 0 + .dw 0xc9c0, 0xc02d, 0xc9ff, 0xc02d, 0x21, 0 + .dw 0xca40, 0xc02d, 0xca7f, 0xc02d, 0x21, 0 + .dw 0xcac0, 0xc02d, 0xcaff, 0xc02d, 0x21, 0 + .dw 0xcb40, 0xc02d, 0xcb7f, 0xc02d, 0x21, 0 + .dw 0xcbc0, 0xc02d, 0xcbff, 0xc02d, 0x21, 0 + .dw 0xcc40, 0xc02d, 0xcc7f, 0xc02d, 0x21, 0 + .dw 0xccc0, 0xc02d, 0xccff, 0xc02d, 0x21, 0 + .dw 0xcd40, 0xc02d, 0xcd7f, 0xc02d, 0x21, 0 + .dw 0xcdc0, 0xc02d, 0xcdff, 0xc02d, 0x21, 0 + .dw 0xce40, 0xc02d, 0xce7f, 0xc02d, 0x21, 0 + .dw 0xcec0, 0xc02d, 0xceff, 0xc02d, 0x21, 0 + .dw 0xcf40, 0xc02d, 0xcf7f, 0xc02d, 0x21, 0 + .dw 0xcfc0, 0xc02d, 0xcfff, 0xc02d, 0x21, 0 + .dw 0xd040, 0xc02d, 0xd07f, 0xc02d, 0x21, 0 + .dw 0xd0c0, 0xc02d, 0xd0ff, 0xc02d, 0x21, 0 + .dw 0xd140, 0xc02d, 0xd17f, 0xc02d, 0x21, 0 + .dw 0xd1c0, 0xc02d, 0xd1ff, 0xc02d, 0x21, 0 + .dw 0xd240, 0xc02d, 0xd27f, 0xc02d, 0x21, 0 + .dw 0xd2c0, 0xc02d, 0xd2ff, 0xc02d, 0x21, 0 + .dw 0xd340, 0xc02d, 0xd37f, 0xc02d, 0x21, 0 + .dw 0xd3c0, 0xc02d, 0xd3ff, 0xc02d, 0x21, 0 + .dw 0xd440, 0xc02d, 0xd47f, 0xc02d, 0x21, 0 + .dw 0xd4c0, 0xc02d, 0xd4ff, 0xc02d, 0x21, 0 + .dw 0xd540, 0xc02d, 0xd57f, 0xc02d, 0x21, 0 + .dw 0xd5c0, 0xc02d, 0xd5ff, 0xc02d, 0x21, 0 + .dw 0xd640, 0xc02d, 0xd67f, 0xc02d, 0x21, 0 + .dw 0xd6c0, 0xc02d, 0xd6ff, 0xc02d, 0x21, 0 + .dw 0xd740, 0xc02d, 0xd77f, 0xc02d, 0x21, 0 + .dw 0xd7c0, 0xc02d, 0xd7ff, 0xc02d, 0x21, 0 + .dw 0xd840, 0xc02d, 0xd87f, 0xc02d, 0x21, 0 + .dw 0xd8c0, 0xc02d, 0xd8ff, 0xc02d, 0x21, 0 + .dw 0xd940, 0xc02d, 0xd97f, 0xc02d, 0x21, 0 + .dw 0xd9c0, 0xc02d, 0xdfff, 0xc02d, 0x21, 0 + .dw 0xe040, 0xc02d, 0xe07f, 0xc02d, 0x21, 0 + .dw 0xe0c0, 0xc02d, 0xe0ff, 0xc02d, 0x21, 0 + .dw 0xe140, 0xc02d, 0xe17f, 0xc02d, 0x21, 0 + .dw 0xe1c0, 0xc02d, 0xe1ff, 0xc02d, 0x21, 0 + .dw 0xe240, 0xc02d, 0xe27f, 0xc02d, 0x21, 0 + .dw 0xe2c0, 0xc02d, 0xe2ff, 0xc02d, 0x21, 0 + .dw 0xe340, 0xc02d, 0xe37f, 0xc02d, 0x21, 0 + .dw 0xe3c0, 0xc02d, 0xe3ff, 0xc02d, 0x21, 0 + .dw 0xe440, 0xc02d, 0xe47f, 0xc02d, 0x21, 0 + .dw 0xe4c0, 0xc02d, 0xe4ff, 0xc02d, 0x21, 0 + .dw 0xe540, 0xc02d, 0xe57f, 0xc02d, 0x21, 0 + .dw 0xe5c0, 0xc02d, 0xe5ff, 0xc02d, 0x21, 0 + .dw 0xe640, 0xc02d, 0xe67f, 0xc02d, 0x21, 0 + .dw 0xe6c0, 0xc02d, 0xe6ff, 0xc02d, 0x21, 0 + .dw 0xe740, 0xc02d, 0xe77f, 0xc02d, 0x21, 0 + .dw 0xe7c0, 0xc02d, 0xe7ff, 0xc02d, 0x21, 0 + .dw 0xe840, 0xc02d, 0xe87f, 0xc02d, 0x21, 0 + .dw 0xe8c0, 0xc02d, 0xe8ff, 0xc02d, 0x21, 0 + .dw 0xe940, 0xc02d, 0xe97f, 0xc02d, 0x21, 0 + .dw 0xe9c0, 0xc02d, 0xe9ff, 0xc02d, 0x21, 0 + .dw 0xea40, 0xc02d, 0xea7f, 0xc02d, 0x21, 0 + .dw 0xeac0, 0xc02d, 0xeaff, 0xc02d, 0x21, 0 + .dw 0xeb40, 0xc02d, 0xeb7f, 0xc02d, 0x21, 0 + .dw 0xebc0, 0xc02d, 0xebff, 0xc02d, 0x21, 0 + .dw 0xec40, 0xc02d, 0xec7f, 0xc02d, 0x21, 0 + .dw 0xecc0, 0xc02d, 0xecff, 0xc02d, 0x21, 0 + .dw 0xed40, 0xc02d, 0xed7f, 0xc02d, 0x21, 0 + .dw 0xedc0, 0xc02d, 0xedff, 0xc02d, 0x21, 0 + .dw 0xee40, 0xc02d, 0xee7f, 0xc02d, 0x21, 0 + .dw 0xeec0, 0xc02d, 0xeeff, 0xc02d, 0x21, 0 + .dw 0xef40, 0xc02d, 0xef7f, 0xc02d, 0x21, 0 + .dw 0xefc0, 0xc02d, 0xefff, 0xc02d, 0x21, 0 + .dw 0xf040, 0xc02d, 0xf07f, 0xc02d, 0x21, 0 + .dw 0xf0c0, 0xc02d, 0xf0ff, 0xc02d, 0x21, 0 + .dw 0xf140, 0xc02d, 0xf17f, 0xc02d, 0x21, 0 + .dw 0xf1c0, 0xc02d, 0xf1ff, 0xc02d, 0x21, 0 + .dw 0xf240, 0xc02d, 0xf27f, 0xc02d, 0x21, 0 + .dw 0xf2c0, 0xc02d, 0xf2ff, 0xc02d, 0x21, 0 + .dw 0xf340, 0xc02d, 0xf37f, 0xc02d, 0x21, 0 + .dw 0xf3c0, 0xc02d, 0xf3ff, 0xc02d, 0x21, 0 + .dw 0xf440, 0xc02d, 0xf47f, 0xc02d, 0x21, 0 + .dw 0xf4c0, 0xc02d, 0xf4ff, 0xc02d, 0x21, 0 + .dw 0xf540, 0xc02d, 0xf57f, 0xc02d, 0x21, 0 + .dw 0xf5c0, 0xc02d, 0xf5ff, 0xc02d, 0x21, 0 + .dw 0xf640, 0xc02d, 0xf67f, 0xc02d, 0x21, 0 + .dw 0xf6c0, 0xc02d, 0xf6ff, 0xc02d, 0x21, 0 + .dw 0xf740, 0xc02d, 0xf77f, 0xc02d, 0x21, 0 + .dw 0xf7c0, 0xc02d, 0xf7ff, 0xc02d, 0x21, 0 + .dw 0xf840, 0xc02d, 0xf87f, 0xc02d, 0x21, 0 + .dw 0xf8c0, 0xc02d, 0xf8ff, 0xc02d, 0x21, 0 + .dw 0xf940, 0xc02d, 0xf97f, 0xc02d, 0x21, 0 + .dw 0xf9c0, 0xc02d, 0xffff, 0xc02d, 0x21, 0 + .dw 0x0040, 0xc02e, 0x007f, 0xc02e, 0x21, 0 + .dw 0x00c0, 0xc02e, 0x00ff, 0xc02e, 0x21, 0 + .dw 0x0140, 0xc02e, 0x017f, 0xc02e, 0x21, 0 + .dw 0x01c0, 0xc02e, 0x01ff, 0xc02e, 0x21, 0 + .dw 0x0240, 0xc02e, 0x027f, 0xc02e, 0x21, 0 + .dw 0x02c0, 0xc02e, 0x02ff, 0xc02e, 0x21, 0 + .dw 0x0340, 0xc02e, 0x037f, 0xc02e, 0x21, 0 + .dw 0x03c0, 0xc02e, 0x03ff, 0xc02e, 0x21, 0 + .dw 0x0440, 0xc02e, 0x047f, 0xc02e, 0x21, 0 + .dw 0x04c0, 0xc02e, 0x04ff, 0xc02e, 0x21, 0 + .dw 0x0540, 0xc02e, 0x057f, 0xc02e, 0x21, 0 + .dw 0x05c0, 0xc02e, 0x05ff, 0xc02e, 0x21, 0 + .dw 0x0640, 0xc02e, 0x067f, 0xc02e, 0x21, 0 + .dw 0x06c0, 0xc02e, 0x06ff, 0xc02e, 0x21, 0 + .dw 0x0740, 0xc02e, 0x077f, 0xc02e, 0x21, 0 + .dw 0x07c0, 0xc02e, 0x07ff, 0xc02e, 0x21, 0 + .dw 0x0840, 0xc02e, 0x087f, 0xc02e, 0x21, 0 + .dw 0x08c0, 0xc02e, 0x08ff, 0xc02e, 0x21, 0 + .dw 0x0940, 0xc02e, 0x097f, 0xc02e, 0x21, 0 + .dw 0x09c0, 0xc02e, 0x09ff, 0xc02e, 0x21, 0 + .dw 0x0a40, 0xc02e, 0x0a7f, 0xc02e, 0x21, 0 + .dw 0x0ac0, 0xc02e, 0x0aff, 0xc02e, 0x21, 0 + .dw 0x0b40, 0xc02e, 0x0b7f, 0xc02e, 0x21, 0 + .dw 0x0bc0, 0xc02e, 0x0bff, 0xc02e, 0x21, 0 + .dw 0x0c40, 0xc02e, 0x0c7f, 0xc02e, 0x21, 0 + .dw 0x0cc0, 0xc02e, 0x0cff, 0xc02e, 0x21, 0 + .dw 0x0d40, 0xc02e, 0x0d7f, 0xc02e, 0x21, 0 + .dw 0x0dc0, 0xc02e, 0x0dff, 0xc02e, 0x21, 0 + .dw 0x0e40, 0xc02e, 0x0e7f, 0xc02e, 0x21, 0 + .dw 0x0ec0, 0xc02e, 0x0eff, 0xc02e, 0x21, 0 + .dw 0x0f40, 0xc02e, 0x0f7f, 0xc02e, 0x21, 0 + .dw 0x0fc0, 0xc02e, 0x0fff, 0xc02e, 0x21, 0 + .dw 0x1040, 0xc02e, 0x107f, 0xc02e, 0x21, 0 + .dw 0x10c0, 0xc02e, 0x10ff, 0xc02e, 0x21, 0 + .dw 0x1140, 0xc02e, 0x117f, 0xc02e, 0x21, 0 + .dw 0x11c0, 0xc02e, 0x11ff, 0xc02e, 0x21, 0 + .dw 0x1240, 0xc02e, 0x127f, 0xc02e, 0x21, 0 + .dw 0x12c0, 0xc02e, 0x12ff, 0xc02e, 0x21, 0 + .dw 0x1340, 0xc02e, 0x137f, 0xc02e, 0x21, 0 + .dw 0x13c0, 0xc02e, 0x13ff, 0xc02e, 0x21, 0 + .dw 0x1440, 0xc02e, 0x147f, 0xc02e, 0x21, 0 + .dw 0x14c0, 0xc02e, 0x14ff, 0xc02e, 0x21, 0 + .dw 0x1540, 0xc02e, 0x157f, 0xc02e, 0x21, 0 + .dw 0x15c0, 0xc02e, 0x15ff, 0xc02e, 0x21, 0 + .dw 0x1640, 0xc02e, 0x167f, 0xc02e, 0x21, 0 + .dw 0x16c0, 0xc02e, 0x16ff, 0xc02e, 0x21, 0 + .dw 0x1740, 0xc02e, 0x177f, 0xc02e, 0x21, 0 + .dw 0x17c0, 0xc02e, 0x17ff, 0xc02e, 0x21, 0 + .dw 0x1840, 0xc02e, 0x187f, 0xc02e, 0x21, 0 + .dw 0x18c0, 0xc02e, 0x18ff, 0xc02e, 0x21, 0 + .dw 0x1940, 0xc02e, 0x197f, 0xc02e, 0x21, 0 + .dw 0x19c0, 0xc02e, 0x1fff, 0xc02e, 0x21, 0 + .dw 0x2040, 0xc02e, 0x207f, 0xc02e, 0x21, 0 + .dw 0x20c0, 0xc02e, 0x20ff, 0xc02e, 0x21, 0 + .dw 0x2140, 0xc02e, 0x217f, 0xc02e, 0x21, 0 + .dw 0x21c0, 0xc02e, 0x21ff, 0xc02e, 0x21, 0 + .dw 0x2240, 0xc02e, 0x227f, 0xc02e, 0x21, 0 + .dw 0x22c0, 0xc02e, 0x22ff, 0xc02e, 0x21, 0 + .dw 0x2340, 0xc02e, 0x237f, 0xc02e, 0x21, 0 + .dw 0x23c0, 0xc02e, 0x23ff, 0xc02e, 0x21, 0 + .dw 0x2440, 0xc02e, 0x247f, 0xc02e, 0x21, 0 + .dw 0x24c0, 0xc02e, 0x24ff, 0xc02e, 0x21, 0 + .dw 0x2540, 0xc02e, 0x257f, 0xc02e, 0x21, 0 + .dw 0x25c0, 0xc02e, 0x25ff, 0xc02e, 0x21, 0 + .dw 0x2640, 0xc02e, 0x267f, 0xc02e, 0x21, 0 + .dw 0x26c0, 0xc02e, 0x26ff, 0xc02e, 0x21, 0 + .dw 0x2740, 0xc02e, 0x277f, 0xc02e, 0x21, 0 + .dw 0x27c0, 0xc02e, 0x27ff, 0xc02e, 0x21, 0 + .dw 0x2840, 0xc02e, 0x287f, 0xc02e, 0x21, 0 + .dw 0x28c0, 0xc02e, 0x28ff, 0xc02e, 0x21, 0 + .dw 0x2940, 0xc02e, 0x297f, 0xc02e, 0x21, 0 + .dw 0x29c0, 0xc02e, 0x29ff, 0xc02e, 0x21, 0 + .dw 0x2a40, 0xc02e, 0x2a7f, 0xc02e, 0x21, 0 + .dw 0x2ac0, 0xc02e, 0x2aff, 0xc02e, 0x21, 0 + .dw 0x2b40, 0xc02e, 0x2b7f, 0xc02e, 0x21, 0 + .dw 0x2bc0, 0xc02e, 0x2bff, 0xc02e, 0x21, 0 + .dw 0x2c40, 0xc02e, 0x2c7f, 0xc02e, 0x21, 0 + .dw 0x2cc0, 0xc02e, 0x2cff, 0xc02e, 0x21, 0 + .dw 0x2d40, 0xc02e, 0x2d7f, 0xc02e, 0x21, 0 + .dw 0x2dc0, 0xc02e, 0x2dff, 0xc02e, 0x21, 0 + .dw 0x2e40, 0xc02e, 0x2e7f, 0xc02e, 0x21, 0 + .dw 0x2ec0, 0xc02e, 0x2eff, 0xc02e, 0x21, 0 + .dw 0x2f40, 0xc02e, 0x2f7f, 0xc02e, 0x21, 0 + .dw 0x2fc0, 0xc02e, 0x2fff, 0xc02e, 0x21, 0 + .dw 0x3040, 0xc02e, 0x307f, 0xc02e, 0x21, 0 + .dw 0x30c0, 0xc02e, 0x30ff, 0xc02e, 0x21, 0 + .dw 0x3140, 0xc02e, 0x317f, 0xc02e, 0x21, 0 + .dw 0x31c0, 0xc02e, 0x31ff, 0xc02e, 0x21, 0 + .dw 0x3240, 0xc02e, 0x327f, 0xc02e, 0x21, 0 + .dw 0x32c0, 0xc02e, 0x32ff, 0xc02e, 0x21, 0 + .dw 0x3340, 0xc02e, 0x337f, 0xc02e, 0x21, 0 + .dw 0x33c0, 0xc02e, 0x33ff, 0xc02e, 0x21, 0 + .dw 0x3440, 0xc02e, 0x347f, 0xc02e, 0x21, 0 + .dw 0x34c0, 0xc02e, 0x34ff, 0xc02e, 0x21, 0 + .dw 0x3540, 0xc02e, 0x357f, 0xc02e, 0x21, 0 + .dw 0x35c0, 0xc02e, 0x35ff, 0xc02e, 0x21, 0 + .dw 0x3640, 0xc02e, 0x367f, 0xc02e, 0x21, 0 + .dw 0x36c0, 0xc02e, 0x36ff, 0xc02e, 0x21, 0 + .dw 0x3740, 0xc02e, 0x377f, 0xc02e, 0x21, 0 + .dw 0x37c0, 0xc02e, 0x37ff, 0xc02e, 0x21, 0 + .dw 0x3840, 0xc02e, 0x387f, 0xc02e, 0x21, 0 + .dw 0x38c0, 0xc02e, 0x38ff, 0xc02e, 0x21, 0 + .dw 0x3940, 0xc02e, 0x397f, 0xc02e, 0x21, 0 + .dw 0x39c0, 0xc02e, 0x3fff, 0xc02e, 0x21, 0 + .dw 0x4040, 0xc02e, 0x407f, 0xc02e, 0x21, 0 + .dw 0x40c0, 0xc02e, 0x40ff, 0xc02e, 0x21, 0 + .dw 0x4140, 0xc02e, 0x417f, 0xc02e, 0x21, 0 + .dw 0x41c0, 0xc02e, 0x41ff, 0xc02e, 0x21, 0 + .dw 0x4240, 0xc02e, 0x427f, 0xc02e, 0x21, 0 + .dw 0x42c0, 0xc02e, 0x42ff, 0xc02e, 0x21, 0 + .dw 0x4340, 0xc02e, 0x437f, 0xc02e, 0x21, 0 + .dw 0x43c0, 0xc02e, 0x43ff, 0xc02e, 0x21, 0 + .dw 0x4440, 0xc02e, 0x447f, 0xc02e, 0x21, 0 + .dw 0x44c0, 0xc02e, 0x44ff, 0xc02e, 0x21, 0 + .dw 0x4540, 0xc02e, 0x457f, 0xc02e, 0x21, 0 + .dw 0x45c0, 0xc02e, 0x45ff, 0xc02e, 0x21, 0 + .dw 0x4640, 0xc02e, 0x467f, 0xc02e, 0x21, 0 + .dw 0x46c0, 0xc02e, 0x46ff, 0xc02e, 0x21, 0 + .dw 0x4740, 0xc02e, 0x477f, 0xc02e, 0x21, 0 + .dw 0x47c0, 0xc02e, 0x47ff, 0xc02e, 0x21, 0 + .dw 0x4840, 0xc02e, 0x487f, 0xc02e, 0x21, 0 + .dw 0x48c0, 0xc02e, 0x48ff, 0xc02e, 0x21, 0 + .dw 0x4940, 0xc02e, 0x497f, 0xc02e, 0x21, 0 + .dw 0x49c0, 0xc02e, 0x49ff, 0xc02e, 0x21, 0 + .dw 0x4a40, 0xc02e, 0x4a7f, 0xc02e, 0x21, 0 + .dw 0x4ac0, 0xc02e, 0x4aff, 0xc02e, 0x21, 0 + .dw 0x4b40, 0xc02e, 0x4b7f, 0xc02e, 0x21, 0 + .dw 0x4bc0, 0xc02e, 0x4bff, 0xc02e, 0x21, 0 + .dw 0x4c40, 0xc02e, 0x4c7f, 0xc02e, 0x21, 0 + .dw 0x4cc0, 0xc02e, 0x4cff, 0xc02e, 0x21, 0 + .dw 0x4d40, 0xc02e, 0x4d7f, 0xc02e, 0x21, 0 + .dw 0x4dc0, 0xc02e, 0x4dff, 0xc02e, 0x21, 0 + .dw 0x4e40, 0xc02e, 0x4e7f, 0xc02e, 0x21, 0 + .dw 0x4ec0, 0xc02e, 0x4eff, 0xc02e, 0x21, 0 + .dw 0x4f40, 0xc02e, 0x4f7f, 0xc02e, 0x21, 0 + .dw 0x4fc0, 0xc02e, 0x4fff, 0xc02e, 0x21, 0 + .dw 0x5040, 0xc02e, 0x507f, 0xc02e, 0x21, 0 + .dw 0x50c0, 0xc02e, 0x50ff, 0xc02e, 0x21, 0 + .dw 0x5140, 0xc02e, 0x517f, 0xc02e, 0x21, 0 + .dw 0x51c0, 0xc02e, 0x51ff, 0xc02e, 0x21, 0 + .dw 0x5240, 0xc02e, 0x527f, 0xc02e, 0x21, 0 + .dw 0x52c0, 0xc02e, 0x52ff, 0xc02e, 0x21, 0 + .dw 0x5340, 0xc02e, 0x537f, 0xc02e, 0x21, 0 + .dw 0x53c0, 0xc02e, 0x53ff, 0xc02e, 0x21, 0 + .dw 0x5440, 0xc02e, 0x547f, 0xc02e, 0x21, 0 + .dw 0x54c0, 0xc02e, 0x54ff, 0xc02e, 0x21, 0 + .dw 0x5540, 0xc02e, 0x557f, 0xc02e, 0x21, 0 + .dw 0x55c0, 0xc02e, 0x55ff, 0xc02e, 0x21, 0 + .dw 0x5640, 0xc02e, 0x567f, 0xc02e, 0x21, 0 + .dw 0x56c0, 0xc02e, 0x56ff, 0xc02e, 0x21, 0 + .dw 0x5740, 0xc02e, 0x577f, 0xc02e, 0x21, 0 + .dw 0x57c0, 0xc02e, 0x57ff, 0xc02e, 0x21, 0 + .dw 0x5840, 0xc02e, 0x587f, 0xc02e, 0x21, 0 + .dw 0x58c0, 0xc02e, 0x58ff, 0xc02e, 0x21, 0 + .dw 0x5940, 0xc02e, 0x597f, 0xc02e, 0x21, 0 + .dw 0x59c0, 0xc02e, 0x5fff, 0xc02e, 0x21, 0 + .dw 0x6040, 0xc02e, 0x607f, 0xc02e, 0x21, 0 + .dw 0x60c0, 0xc02e, 0x60ff, 0xc02e, 0x21, 0 + .dw 0x6140, 0xc02e, 0x617f, 0xc02e, 0x21, 0 + .dw 0x61c0, 0xc02e, 0x61ff, 0xc02e, 0x21, 0 + .dw 0x6240, 0xc02e, 0x627f, 0xc02e, 0x21, 0 + .dw 0x62c0, 0xc02e, 0x62ff, 0xc02e, 0x21, 0 + .dw 0x6340, 0xc02e, 0x637f, 0xc02e, 0x21, 0 + .dw 0x63c0, 0xc02e, 0x63ff, 0xc02e, 0x21, 0 + .dw 0x6440, 0xc02e, 0x647f, 0xc02e, 0x21, 0 + .dw 0x64c0, 0xc02e, 0x64ff, 0xc02e, 0x21, 0 + .dw 0x6540, 0xc02e, 0x657f, 0xc02e, 0x21, 0 + .dw 0x65c0, 0xc02e, 0x65ff, 0xc02e, 0x21, 0 + .dw 0x6640, 0xc02e, 0x667f, 0xc02e, 0x21, 0 + .dw 0x66c0, 0xc02e, 0x66ff, 0xc02e, 0x21, 0 + .dw 0x6740, 0xc02e, 0x677f, 0xc02e, 0x21, 0 + .dw 0x67c0, 0xc02e, 0x67ff, 0xc02e, 0x21, 0 + .dw 0x6840, 0xc02e, 0x687f, 0xc02e, 0x21, 0 + .dw 0x68c0, 0xc02e, 0x68ff, 0xc02e, 0x21, 0 + .dw 0x6940, 0xc02e, 0x697f, 0xc02e, 0x21, 0 + .dw 0x69c0, 0xc02e, 0x69ff, 0xc02e, 0x21, 0 + .dw 0x6a40, 0xc02e, 0x6a7f, 0xc02e, 0x21, 0 + .dw 0x6ac0, 0xc02e, 0x6aff, 0xc02e, 0x21, 0 + .dw 0x6b40, 0xc02e, 0x6b7f, 0xc02e, 0x21, 0 + .dw 0x6bc0, 0xc02e, 0x6bff, 0xc02e, 0x21, 0 + .dw 0x6c40, 0xc02e, 0x6c7f, 0xc02e, 0x21, 0 + .dw 0x6cc0, 0xc02e, 0x6cff, 0xc02e, 0x21, 0 + .dw 0x6d40, 0xc02e, 0x6d7f, 0xc02e, 0x21, 0 + .dw 0x6dc0, 0xc02e, 0x6dff, 0xc02e, 0x21, 0 + .dw 0x6e40, 0xc02e, 0x6e7f, 0xc02e, 0x21, 0 + .dw 0x6ec0, 0xc02e, 0x6eff, 0xc02e, 0x21, 0 + .dw 0x6f40, 0xc02e, 0x6f7f, 0xc02e, 0x21, 0 + .dw 0x6fc0, 0xc02e, 0x6fff, 0xc02e, 0x21, 0 + .dw 0x7040, 0xc02e, 0x707f, 0xc02e, 0x21, 0 + .dw 0x70c0, 0xc02e, 0x70ff, 0xc02e, 0x21, 0 + .dw 0x7140, 0xc02e, 0x717f, 0xc02e, 0x21, 0 + .dw 0x71c0, 0xc02e, 0x71ff, 0xc02e, 0x21, 0 + .dw 0x7240, 0xc02e, 0x727f, 0xc02e, 0x21, 0 + .dw 0x72c0, 0xc02e, 0x72ff, 0xc02e, 0x21, 0 + .dw 0x7340, 0xc02e, 0x737f, 0xc02e, 0x21, 0 + .dw 0x73c0, 0xc02e, 0x73ff, 0xc02e, 0x21, 0 + .dw 0x7440, 0xc02e, 0x747f, 0xc02e, 0x21, 0 + .dw 0x74c0, 0xc02e, 0x74ff, 0xc02e, 0x21, 0 + .dw 0x7540, 0xc02e, 0x757f, 0xc02e, 0x21, 0 + .dw 0x75c0, 0xc02e, 0x75ff, 0xc02e, 0x21, 0 + .dw 0x7640, 0xc02e, 0x767f, 0xc02e, 0x21, 0 + .dw 0x76c0, 0xc02e, 0x76ff, 0xc02e, 0x21, 0 + .dw 0x7740, 0xc02e, 0x777f, 0xc02e, 0x21, 0 + .dw 0x77c0, 0xc02e, 0x77ff, 0xc02e, 0x21, 0 + .dw 0x7840, 0xc02e, 0x787f, 0xc02e, 0x21, 0 + .dw 0x78c0, 0xc02e, 0x78ff, 0xc02e, 0x21, 0 + .dw 0x7940, 0xc02e, 0x797f, 0xc02e, 0x21, 0 + .dw 0x79c0, 0xc02e, 0x7fff, 0xc02e, 0x21, 0 + .dw 0x8040, 0xc02e, 0x807f, 0xc02e, 0x21, 0 + .dw 0x80c0, 0xc02e, 0x80ff, 0xc02e, 0x21, 0 + .dw 0x8140, 0xc02e, 0x817f, 0xc02e, 0x21, 0 + .dw 0x81c0, 0xc02e, 0x81ff, 0xc02e, 0x21, 0 + .dw 0x8240, 0xc02e, 0x827f, 0xc02e, 0x21, 0 + .dw 0x82c0, 0xc02e, 0x82ff, 0xc02e, 0x21, 0 + .dw 0x8340, 0xc02e, 0x837f, 0xc02e, 0x21, 0 + .dw 0x83c0, 0xc02e, 0x83ff, 0xc02e, 0x21, 0 + .dw 0x8440, 0xc02e, 0x847f, 0xc02e, 0x21, 0 + .dw 0x84c0, 0xc02e, 0x84ff, 0xc02e, 0x21, 0 + .dw 0x8540, 0xc02e, 0x857f, 0xc02e, 0x21, 0 + .dw 0x85c0, 0xc02e, 0x85ff, 0xc02e, 0x21, 0 + .dw 0x8640, 0xc02e, 0x867f, 0xc02e, 0x21, 0 + .dw 0x86c0, 0xc02e, 0x86ff, 0xc02e, 0x21, 0 + .dw 0x8740, 0xc02e, 0x877f, 0xc02e, 0x21, 0 + .dw 0x87c0, 0xc02e, 0x87ff, 0xc02e, 0x21, 0 + .dw 0x8840, 0xc02e, 0x887f, 0xc02e, 0x21, 0 + .dw 0x88c0, 0xc02e, 0x88ff, 0xc02e, 0x21, 0 + .dw 0x8940, 0xc02e, 0x897f, 0xc02e, 0x21, 0 + .dw 0x89c0, 0xc02e, 0x89ff, 0xc02e, 0x21, 0 + .dw 0x8a40, 0xc02e, 0x8a7f, 0xc02e, 0x21, 0 + .dw 0x8ac0, 0xc02e, 0x8aff, 0xc02e, 0x21, 0 + .dw 0x8b40, 0xc02e, 0x8b7f, 0xc02e, 0x21, 0 + .dw 0x8bc0, 0xc02e, 0x8bff, 0xc02e, 0x21, 0 + .dw 0x8c40, 0xc02e, 0x8c7f, 0xc02e, 0x21, 0 + .dw 0x8cc0, 0xc02e, 0x8cff, 0xc02e, 0x21, 0 + .dw 0x8d40, 0xc02e, 0x8d7f, 0xc02e, 0x21, 0 + .dw 0x8dc0, 0xc02e, 0x8dff, 0xc02e, 0x21, 0 + .dw 0x8e40, 0xc02e, 0x8e7f, 0xc02e, 0x21, 0 + .dw 0x8ec0, 0xc02e, 0x8eff, 0xc02e, 0x21, 0 + .dw 0x8f40, 0xc02e, 0x8f7f, 0xc02e, 0x21, 0 + .dw 0x8fc0, 0xc02e, 0x8fff, 0xc02e, 0x21, 0 + .dw 0x9040, 0xc02e, 0x907f, 0xc02e, 0x21, 0 + .dw 0x90c0, 0xc02e, 0x90ff, 0xc02e, 0x21, 0 + .dw 0x9140, 0xc02e, 0x917f, 0xc02e, 0x21, 0 + .dw 0x91c0, 0xc02e, 0x91ff, 0xc02e, 0x21, 0 + .dw 0x9240, 0xc02e, 0x927f, 0xc02e, 0x21, 0 + .dw 0x92c0, 0xc02e, 0x92ff, 0xc02e, 0x21, 0 + .dw 0x9340, 0xc02e, 0x937f, 0xc02e, 0x21, 0 + .dw 0x93c0, 0xc02e, 0x93ff, 0xc02e, 0x21, 0 + .dw 0x9440, 0xc02e, 0x947f, 0xc02e, 0x21, 0 + .dw 0x94c0, 0xc02e, 0x94ff, 0xc02e, 0x21, 0 + .dw 0x9540, 0xc02e, 0x957f, 0xc02e, 0x21, 0 + .dw 0x95c0, 0xc02e, 0x95ff, 0xc02e, 0x21, 0 + .dw 0x9640, 0xc02e, 0x967f, 0xc02e, 0x21, 0 + .dw 0x96c0, 0xc02e, 0x96ff, 0xc02e, 0x21, 0 + .dw 0x9740, 0xc02e, 0x977f, 0xc02e, 0x21, 0 + .dw 0x97c0, 0xc02e, 0x97ff, 0xc02e, 0x21, 0 + .dw 0x9840, 0xc02e, 0x987f, 0xc02e, 0x21, 0 + .dw 0x98c0, 0xc02e, 0x98ff, 0xc02e, 0x21, 0 + .dw 0x9940, 0xc02e, 0x997f, 0xc02e, 0x21, 0 + .dw 0x99c0, 0xc02e, 0x9fff, 0xc02e, 0x21, 0 + .dw 0xa040, 0xc02e, 0xa07f, 0xc02e, 0x21, 0 + .dw 0xa0c0, 0xc02e, 0xa0ff, 0xc02e, 0x21, 0 + .dw 0xa140, 0xc02e, 0xa17f, 0xc02e, 0x21, 0 + .dw 0xa1c0, 0xc02e, 0xa1ff, 0xc02e, 0x21, 0 + .dw 0xa240, 0xc02e, 0xa27f, 0xc02e, 0x21, 0 + .dw 0xa2c0, 0xc02e, 0xa2ff, 0xc02e, 0x21, 0 + .dw 0xa340, 0xc02e, 0xa37f, 0xc02e, 0x21, 0 + .dw 0xa3c0, 0xc02e, 0xa3ff, 0xc02e, 0x21, 0 + .dw 0xa440, 0xc02e, 0xa47f, 0xc02e, 0x21, 0 + .dw 0xa4c0, 0xc02e, 0xa4ff, 0xc02e, 0x21, 0 + .dw 0xa540, 0xc02e, 0xa57f, 0xc02e, 0x21, 0 + .dw 0xa5c0, 0xc02e, 0xa5ff, 0xc02e, 0x21, 0 + .dw 0xa640, 0xc02e, 0xa67f, 0xc02e, 0x21, 0 + .dw 0xa6c0, 0xc02e, 0xa6ff, 0xc02e, 0x21, 0 + .dw 0xa740, 0xc02e, 0xa77f, 0xc02e, 0x21, 0 + .dw 0xa7c0, 0xc02e, 0xa7ff, 0xc02e, 0x21, 0 + .dw 0xa840, 0xc02e, 0xa87f, 0xc02e, 0x21, 0 + .dw 0xa8c0, 0xc02e, 0xa8ff, 0xc02e, 0x21, 0 + .dw 0xa940, 0xc02e, 0xa97f, 0xc02e, 0x21, 0 + .dw 0xa9c0, 0xc02e, 0xa9ff, 0xc02e, 0x21, 0 + .dw 0xaa40, 0xc02e, 0xaa7f, 0xc02e, 0x21, 0 + .dw 0xaac0, 0xc02e, 0xaaff, 0xc02e, 0x21, 0 + .dw 0xab40, 0xc02e, 0xab7f, 0xc02e, 0x21, 0 + .dw 0xabc0, 0xc02e, 0xabff, 0xc02e, 0x21, 0 + .dw 0xac40, 0xc02e, 0xac7f, 0xc02e, 0x21, 0 + .dw 0xacc0, 0xc02e, 0xacff, 0xc02e, 0x21, 0 + .dw 0xad40, 0xc02e, 0xad7f, 0xc02e, 0x21, 0 + .dw 0xadc0, 0xc02e, 0xadff, 0xc02e, 0x21, 0 + .dw 0xae40, 0xc02e, 0xae7f, 0xc02e, 0x21, 0 + .dw 0xaec0, 0xc02e, 0xaeff, 0xc02e, 0x21, 0 + .dw 0xaf40, 0xc02e, 0xaf7f, 0xc02e, 0x21, 0 + .dw 0xafc0, 0xc02e, 0xafff, 0xc02e, 0x21, 0 + .dw 0xb040, 0xc02e, 0xb07f, 0xc02e, 0x21, 0 + .dw 0xb0c0, 0xc02e, 0xb0ff, 0xc02e, 0x21, 0 + .dw 0xb140, 0xc02e, 0xb17f, 0xc02e, 0x21, 0 + .dw 0xb1c0, 0xc02e, 0xb1ff, 0xc02e, 0x21, 0 + .dw 0xb240, 0xc02e, 0xb27f, 0xc02e, 0x21, 0 + .dw 0xb2c0, 0xc02e, 0xb2ff, 0xc02e, 0x21, 0 + .dw 0xb340, 0xc02e, 0xb37f, 0xc02e, 0x21, 0 + .dw 0xb3c0, 0xc02e, 0xb3ff, 0xc02e, 0x21, 0 + .dw 0xb440, 0xc02e, 0xb47f, 0xc02e, 0x21, 0 + .dw 0xb4c0, 0xc02e, 0xb4ff, 0xc02e, 0x21, 0 + .dw 0xb540, 0xc02e, 0xb57f, 0xc02e, 0x21, 0 + .dw 0xb5c0, 0xc02e, 0xb5ff, 0xc02e, 0x21, 0 + .dw 0xb640, 0xc02e, 0xb67f, 0xc02e, 0x21, 0 + .dw 0xb6c0, 0xc02e, 0xb6ff, 0xc02e, 0x21, 0 + .dw 0xb740, 0xc02e, 0xb77f, 0xc02e, 0x21, 0 + .dw 0xb7c0, 0xc02e, 0xb7ff, 0xc02e, 0x21, 0 + .dw 0xb840, 0xc02e, 0xb87f, 0xc02e, 0x21, 0 + .dw 0xb8c0, 0xc02e, 0xb8ff, 0xc02e, 0x21, 0 + .dw 0xb940, 0xc02e, 0xb97f, 0xc02e, 0x21, 0 + .dw 0xb9c0, 0xc02e, 0xbfff, 0xc02e, 0x21, 0 + .dw 0xc040, 0xc02e, 0xc07f, 0xc02e, 0x21, 0 + .dw 0xc0c0, 0xc02e, 0xc0ff, 0xc02e, 0x21, 0 + .dw 0xc140, 0xc02e, 0xc17f, 0xc02e, 0x21, 0 + .dw 0xc1c0, 0xc02e, 0xc1ff, 0xc02e, 0x21, 0 + .dw 0xc240, 0xc02e, 0xc27f, 0xc02e, 0x21, 0 + .dw 0xc2c0, 0xc02e, 0xc2ff, 0xc02e, 0x21, 0 + .dw 0xc340, 0xc02e, 0xc37f, 0xc02e, 0x21, 0 + .dw 0xc3c0, 0xc02e, 0xc3ff, 0xc02e, 0x21, 0 + .dw 0xc440, 0xc02e, 0xc47f, 0xc02e, 0x21, 0 + .dw 0xc4c0, 0xc02e, 0xc4ff, 0xc02e, 0x21, 0 + .dw 0xc540, 0xc02e, 0xc57f, 0xc02e, 0x21, 0 + .dw 0xc5c0, 0xc02e, 0xc5ff, 0xc02e, 0x21, 0 + .dw 0xc640, 0xc02e, 0xc67f, 0xc02e, 0x21, 0 + .dw 0xc6c0, 0xc02e, 0xc6ff, 0xc02e, 0x21, 0 + .dw 0xc740, 0xc02e, 0xc77f, 0xc02e, 0x21, 0 + .dw 0xc7c0, 0xc02e, 0xc7ff, 0xc02e, 0x21, 0 + .dw 0xc840, 0xc02e, 0xc87f, 0xc02e, 0x21, 0 + .dw 0xc8c0, 0xc02e, 0xc8ff, 0xc02e, 0x21, 0 + .dw 0xc940, 0xc02e, 0xc97f, 0xc02e, 0x21, 0 + .dw 0xc9c0, 0xc02e, 0xc9ff, 0xc02e, 0x21, 0 + .dw 0xca40, 0xc02e, 0xca7f, 0xc02e, 0x21, 0 + .dw 0xcac0, 0xc02e, 0xcaff, 0xc02e, 0x21, 0 + .dw 0xcb40, 0xc02e, 0xcb7f, 0xc02e, 0x21, 0 + .dw 0xcbc0, 0xc02e, 0xcbff, 0xc02e, 0x21, 0 + .dw 0xcc40, 0xc02e, 0xcc7f, 0xc02e, 0x21, 0 + .dw 0xccc0, 0xc02e, 0xccff, 0xc02e, 0x21, 0 + .dw 0xcd40, 0xc02e, 0xcd7f, 0xc02e, 0x21, 0 + .dw 0xcdc0, 0xc02e, 0xcdff, 0xc02e, 0x21, 0 + .dw 0xce40, 0xc02e, 0xce7f, 0xc02e, 0x21, 0 + .dw 0xcec0, 0xc02e, 0xceff, 0xc02e, 0x21, 0 + .dw 0xcf40, 0xc02e, 0xcf7f, 0xc02e, 0x21, 0 + .dw 0xcfc0, 0xc02e, 0xcfff, 0xc02e, 0x21, 0 + .dw 0xd040, 0xc02e, 0xd07f, 0xc02e, 0x21, 0 + .dw 0xd0c0, 0xc02e, 0xd0ff, 0xc02e, 0x21, 0 + .dw 0xd140, 0xc02e, 0xd17f, 0xc02e, 0x21, 0 + .dw 0xd1c0, 0xc02e, 0xd1ff, 0xc02e, 0x21, 0 + .dw 0xd240, 0xc02e, 0xd27f, 0xc02e, 0x21, 0 + .dw 0xd2c0, 0xc02e, 0xd2ff, 0xc02e, 0x21, 0 + .dw 0xd340, 0xc02e, 0xd37f, 0xc02e, 0x21, 0 + .dw 0xd3c0, 0xc02e, 0xd3ff, 0xc02e, 0x21, 0 + .dw 0xd440, 0xc02e, 0xd47f, 0xc02e, 0x21, 0 + .dw 0xd4c0, 0xc02e, 0xd4ff, 0xc02e, 0x21, 0 + .dw 0xd540, 0xc02e, 0xd57f, 0xc02e, 0x21, 0 + .dw 0xd5c0, 0xc02e, 0xd5ff, 0xc02e, 0x21, 0 + .dw 0xd640, 0xc02e, 0xd67f, 0xc02e, 0x21, 0 + .dw 0xd6c0, 0xc02e, 0xd6ff, 0xc02e, 0x21, 0 + .dw 0xd740, 0xc02e, 0xd77f, 0xc02e, 0x21, 0 + .dw 0xd7c0, 0xc02e, 0xd7ff, 0xc02e, 0x21, 0 + .dw 0xd840, 0xc02e, 0xd87f, 0xc02e, 0x21, 0 + .dw 0xd8c0, 0xc02e, 0xd8ff, 0xc02e, 0x21, 0 + .dw 0xd940, 0xc02e, 0xd97f, 0xc02e, 0x21, 0 + .dw 0xd9c0, 0xc02e, 0xdfff, 0xc02e, 0x21, 0 + .dw 0xe040, 0xc02e, 0xe07f, 0xc02e, 0x21, 0 + .dw 0xe0c0, 0xc02e, 0xe0ff, 0xc02e, 0x21, 0 + .dw 0xe140, 0xc02e, 0xe17f, 0xc02e, 0x21, 0 + .dw 0xe1c0, 0xc02e, 0xe1ff, 0xc02e, 0x21, 0 + .dw 0xe240, 0xc02e, 0xe27f, 0xc02e, 0x21, 0 + .dw 0xe2c0, 0xc02e, 0xe2ff, 0xc02e, 0x21, 0 + .dw 0xe340, 0xc02e, 0xe37f, 0xc02e, 0x21, 0 + .dw 0xe3c0, 0xc02e, 0xe3ff, 0xc02e, 0x21, 0 + .dw 0xe440, 0xc02e, 0xe47f, 0xc02e, 0x21, 0 + .dw 0xe4c0, 0xc02e, 0xe4ff, 0xc02e, 0x21, 0 + .dw 0xe540, 0xc02e, 0xe57f, 0xc02e, 0x21, 0 + .dw 0xe5c0, 0xc02e, 0xe5ff, 0xc02e, 0x21, 0 + .dw 0xe640, 0xc02e, 0xe67f, 0xc02e, 0x21, 0 + .dw 0xe6c0, 0xc02e, 0xe6ff, 0xc02e, 0x21, 0 + .dw 0xe740, 0xc02e, 0xe77f, 0xc02e, 0x21, 0 + .dw 0xe7c0, 0xc02e, 0xe7ff, 0xc02e, 0x21, 0 + .dw 0xe840, 0xc02e, 0xe87f, 0xc02e, 0x21, 0 + .dw 0xe8c0, 0xc02e, 0xe8ff, 0xc02e, 0x21, 0 + .dw 0xe940, 0xc02e, 0xe97f, 0xc02e, 0x21, 0 + .dw 0xe9c0, 0xc02e, 0xe9ff, 0xc02e, 0x21, 0 + .dw 0xea40, 0xc02e, 0xea7f, 0xc02e, 0x21, 0 + .dw 0xeac0, 0xc02e, 0xeaff, 0xc02e, 0x21, 0 + .dw 0xeb40, 0xc02e, 0xeb7f, 0xc02e, 0x21, 0 + .dw 0xebc0, 0xc02e, 0xebff, 0xc02e, 0x21, 0 + .dw 0xec40, 0xc02e, 0xec7f, 0xc02e, 0x21, 0 + .dw 0xecc0, 0xc02e, 0xecff, 0xc02e, 0x21, 0 + .dw 0xed40, 0xc02e, 0xed7f, 0xc02e, 0x21, 0 + .dw 0xedc0, 0xc02e, 0xedff, 0xc02e, 0x21, 0 + .dw 0xee40, 0xc02e, 0xee7f, 0xc02e, 0x21, 0 + .dw 0xeec0, 0xc02e, 0xeeff, 0xc02e, 0x21, 0 + .dw 0xef40, 0xc02e, 0xef7f, 0xc02e, 0x21, 0 + .dw 0xefc0, 0xc02e, 0xefff, 0xc02e, 0x21, 0 + .dw 0xf040, 0xc02e, 0xf07f, 0xc02e, 0x21, 0 + .dw 0xf0c0, 0xc02e, 0xf0ff, 0xc02e, 0x21, 0 + .dw 0xf140, 0xc02e, 0xf17f, 0xc02e, 0x21, 0 + .dw 0xf1c0, 0xc02e, 0xf1ff, 0xc02e, 0x21, 0 + .dw 0xf240, 0xc02e, 0xf27f, 0xc02e, 0x21, 0 + .dw 0xf2c0, 0xc02e, 0xf2ff, 0xc02e, 0x21, 0 + .dw 0xf340, 0xc02e, 0xf37f, 0xc02e, 0x21, 0 + .dw 0xf3c0, 0xc02e, 0xf3ff, 0xc02e, 0x21, 0 + .dw 0xf440, 0xc02e, 0xf47f, 0xc02e, 0x21, 0 + .dw 0xf4c0, 0xc02e, 0xf4ff, 0xc02e, 0x21, 0 + .dw 0xf540, 0xc02e, 0xf57f, 0xc02e, 0x21, 0 + .dw 0xf5c0, 0xc02e, 0xf5ff, 0xc02e, 0x21, 0 + .dw 0xf640, 0xc02e, 0xf67f, 0xc02e, 0x21, 0 + .dw 0xf6c0, 0xc02e, 0xf6ff, 0xc02e, 0x21, 0 + .dw 0xf740, 0xc02e, 0xf77f, 0xc02e, 0x21, 0 + .dw 0xf7c0, 0xc02e, 0xf7ff, 0xc02e, 0x21, 0 + .dw 0xf840, 0xc02e, 0xf87f, 0xc02e, 0x21, 0 + .dw 0xf8c0, 0xc02e, 0xf8ff, 0xc02e, 0x21, 0 + .dw 0xf940, 0xc02e, 0xf97f, 0xc02e, 0x21, 0 + .dw 0xf9c0, 0xc02e, 0xffff, 0xc02e, 0x21, 0 + .dw 0x0040, 0xc02f, 0x007f, 0xc02f, 0x21, 0 + .dw 0x00c0, 0xc02f, 0x00ff, 0xc02f, 0x21, 0 + .dw 0x0140, 0xc02f, 0x017f, 0xc02f, 0x21, 0 + .dw 0x01c0, 0xc02f, 0x01ff, 0xc02f, 0x21, 0 + .dw 0x0240, 0xc02f, 0x027f, 0xc02f, 0x21, 0 + .dw 0x02c0, 0xc02f, 0x02ff, 0xc02f, 0x21, 0 + .dw 0x0340, 0xc02f, 0x037f, 0xc02f, 0x21, 0 + .dw 0x03c0, 0xc02f, 0x03ff, 0xc02f, 0x21, 0 + .dw 0x0440, 0xc02f, 0x047f, 0xc02f, 0x21, 0 + .dw 0x04c0, 0xc02f, 0x04ff, 0xc02f, 0x21, 0 + .dw 0x0540, 0xc02f, 0x057f, 0xc02f, 0x21, 0 + .dw 0x05c0, 0xc02f, 0x05ff, 0xc02f, 0x21, 0 + .dw 0x0640, 0xc02f, 0x067f, 0xc02f, 0x21, 0 + .dw 0x06c0, 0xc02f, 0x06ff, 0xc02f, 0x21, 0 + .dw 0x0740, 0xc02f, 0x077f, 0xc02f, 0x21, 0 + .dw 0x07c0, 0xc02f, 0x07ff, 0xc02f, 0x21, 0 + .dw 0x0840, 0xc02f, 0x087f, 0xc02f, 0x21, 0 + .dw 0x08c0, 0xc02f, 0x08ff, 0xc02f, 0x21, 0 + .dw 0x0940, 0xc02f, 0x097f, 0xc02f, 0x21, 0 + .dw 0x09c0, 0xc02f, 0x09ff, 0xc02f, 0x21, 0 + .dw 0x0a40, 0xc02f, 0x0a7f, 0xc02f, 0x21, 0 + .dw 0x0ac0, 0xc02f, 0x0aff, 0xc02f, 0x21, 0 + .dw 0x0b40, 0xc02f, 0x0b7f, 0xc02f, 0x21, 0 + .dw 0x0bc0, 0xc02f, 0x0bff, 0xc02f, 0x21, 0 + .dw 0x0c40, 0xc02f, 0x0c7f, 0xc02f, 0x21, 0 + .dw 0x0cc0, 0xc02f, 0x0cff, 0xc02f, 0x21, 0 + .dw 0x0d40, 0xc02f, 0x0d7f, 0xc02f, 0x21, 0 + .dw 0x0dc0, 0xc02f, 0x0dff, 0xc02f, 0x21, 0 + .dw 0x0e40, 0xc02f, 0x0e7f, 0xc02f, 0x21, 0 + .dw 0x0ec0, 0xc02f, 0x0eff, 0xc02f, 0x21, 0 + .dw 0x0f40, 0xc02f, 0x0f7f, 0xc02f, 0x21, 0 + .dw 0x0fc0, 0xc02f, 0x0fff, 0xc02f, 0x21, 0 + .dw 0x1040, 0xc02f, 0x107f, 0xc02f, 0x21, 0 + .dw 0x10c0, 0xc02f, 0x10ff, 0xc02f, 0x21, 0 + .dw 0x1140, 0xc02f, 0x117f, 0xc02f, 0x21, 0 + .dw 0x11c0, 0xc02f, 0x11ff, 0xc02f, 0x21, 0 + .dw 0x1240, 0xc02f, 0x127f, 0xc02f, 0x21, 0 + .dw 0x12c0, 0xc02f, 0x12ff, 0xc02f, 0x21, 0 + .dw 0x1340, 0xc02f, 0x137f, 0xc02f, 0x21, 0 + .dw 0x13c0, 0xc02f, 0x13ff, 0xc02f, 0x21, 0 + .dw 0x1440, 0xc02f, 0x147f, 0xc02f, 0x21, 0 + .dw 0x14c0, 0xc02f, 0x14ff, 0xc02f, 0x21, 0 + .dw 0x1540, 0xc02f, 0x157f, 0xc02f, 0x21, 0 + .dw 0x15c0, 0xc02f, 0x15ff, 0xc02f, 0x21, 0 + .dw 0x1640, 0xc02f, 0x167f, 0xc02f, 0x21, 0 + .dw 0x16c0, 0xc02f, 0x16ff, 0xc02f, 0x21, 0 + .dw 0x1740, 0xc02f, 0x177f, 0xc02f, 0x21, 0 + .dw 0x17c0, 0xc02f, 0x17ff, 0xc02f, 0x21, 0 + .dw 0x1840, 0xc02f, 0x187f, 0xc02f, 0x21, 0 + .dw 0x18c0, 0xc02f, 0x18ff, 0xc02f, 0x21, 0 + .dw 0x1940, 0xc02f, 0x197f, 0xc02f, 0x21, 0 + .dw 0x19c0, 0xc02f, 0x1fff, 0xc02f, 0x21, 0 + .dw 0x2040, 0xc02f, 0x207f, 0xc02f, 0x21, 0 + .dw 0x20c0, 0xc02f, 0x20ff, 0xc02f, 0x21, 0 + .dw 0x2140, 0xc02f, 0x217f, 0xc02f, 0x21, 0 + .dw 0x21c0, 0xc02f, 0x21ff, 0xc02f, 0x21, 0 + .dw 0x2240, 0xc02f, 0x227f, 0xc02f, 0x21, 0 + .dw 0x22c0, 0xc02f, 0x22ff, 0xc02f, 0x21, 0 + .dw 0x2340, 0xc02f, 0x237f, 0xc02f, 0x21, 0 + .dw 0x23c0, 0xc02f, 0x23ff, 0xc02f, 0x21, 0 + .dw 0x2440, 0xc02f, 0x247f, 0xc02f, 0x21, 0 + .dw 0x24c0, 0xc02f, 0x24ff, 0xc02f, 0x21, 0 + .dw 0x2540, 0xc02f, 0x257f, 0xc02f, 0x21, 0 + .dw 0x25c0, 0xc02f, 0x25ff, 0xc02f, 0x21, 0 + .dw 0x2640, 0xc02f, 0x267f, 0xc02f, 0x21, 0 + .dw 0x26c0, 0xc02f, 0x26ff, 0xc02f, 0x21, 0 + .dw 0x2740, 0xc02f, 0x277f, 0xc02f, 0x21, 0 + .dw 0x27c0, 0xc02f, 0x27ff, 0xc02f, 0x21, 0 + .dw 0x2840, 0xc02f, 0x287f, 0xc02f, 0x21, 0 + .dw 0x28c0, 0xc02f, 0x28ff, 0xc02f, 0x21, 0 + .dw 0x2940, 0xc02f, 0x297f, 0xc02f, 0x21, 0 + .dw 0x29c0, 0xc02f, 0x29ff, 0xc02f, 0x21, 0 + .dw 0x2a40, 0xc02f, 0x2a7f, 0xc02f, 0x21, 0 + .dw 0x2ac0, 0xc02f, 0x2aff, 0xc02f, 0x21, 0 + .dw 0x2b40, 0xc02f, 0x2b7f, 0xc02f, 0x21, 0 + .dw 0x2bc0, 0xc02f, 0x2bff, 0xc02f, 0x21, 0 + .dw 0x2c40, 0xc02f, 0x2c7f, 0xc02f, 0x21, 0 + .dw 0x2cc0, 0xc02f, 0x2cff, 0xc02f, 0x21, 0 + .dw 0x2d40, 0xc02f, 0x2d7f, 0xc02f, 0x21, 0 + .dw 0x2dc0, 0xc02f, 0x2dff, 0xc02f, 0x21, 0 + .dw 0x2e40, 0xc02f, 0x2e7f, 0xc02f, 0x21, 0 + .dw 0x2ec0, 0xc02f, 0x2eff, 0xc02f, 0x21, 0 + .dw 0x2f40, 0xc02f, 0x2f7f, 0xc02f, 0x21, 0 + .dw 0x2fc0, 0xc02f, 0x2fff, 0xc02f, 0x21, 0 + .dw 0x3040, 0xc02f, 0x307f, 0xc02f, 0x21, 0 + .dw 0x30c0, 0xc02f, 0x30ff, 0xc02f, 0x21, 0 + .dw 0x3140, 0xc02f, 0x317f, 0xc02f, 0x21, 0 + .dw 0x31c0, 0xc02f, 0x31ff, 0xc02f, 0x21, 0 + .dw 0x3240, 0xc02f, 0x327f, 0xc02f, 0x21, 0 + .dw 0x32c0, 0xc02f, 0x32ff, 0xc02f, 0x21, 0 + .dw 0x3340, 0xc02f, 0x337f, 0xc02f, 0x21, 0 + .dw 0x33c0, 0xc02f, 0x33ff, 0xc02f, 0x21, 0 + .dw 0x3440, 0xc02f, 0x347f, 0xc02f, 0x21, 0 + .dw 0x34c0, 0xc02f, 0x34ff, 0xc02f, 0x21, 0 + .dw 0x3540, 0xc02f, 0x357f, 0xc02f, 0x21, 0 + .dw 0x35c0, 0xc02f, 0x35ff, 0xc02f, 0x21, 0 + .dw 0x3640, 0xc02f, 0x367f, 0xc02f, 0x21, 0 + .dw 0x36c0, 0xc02f, 0x36ff, 0xc02f, 0x21, 0 + .dw 0x3740, 0xc02f, 0x377f, 0xc02f, 0x21, 0 + .dw 0x37c0, 0xc02f, 0x37ff, 0xc02f, 0x21, 0 + .dw 0x3840, 0xc02f, 0x387f, 0xc02f, 0x21, 0 + .dw 0x38c0, 0xc02f, 0x38ff, 0xc02f, 0x21, 0 + .dw 0x3940, 0xc02f, 0x397f, 0xc02f, 0x21, 0 + .dw 0x39c0, 0xc02f, 0x1fff, 0xc030, 0x21, 0 + .dw 0x3a00, 0xc030, 0x5fff, 0xc030, 0x21, 0 + .dw 0x7a00, 0xc030, 0x9fff, 0xc030, 0x21, 0 + .dw 0xba00, 0xc030, 0xdfff, 0xc030, 0x21, 0 + .dw 0xfa00, 0xc030, 0x1fff, 0xc031, 0x21, 0 + .dw 0x3a00, 0xc031, 0x5fff, 0xc031, 0x21, 0 + .dw 0x7a00, 0xc031, 0x9fff, 0xc031, 0x21, 0 + .dw 0xba00, 0xc031, 0xdfff, 0xc031, 0x21, 0 + .dw 0xfa00, 0xc031, 0x1fff, 0xc032, 0x21, 0 + .dw 0x3a00, 0xc032, 0x5fff, 0xc032, 0x21, 0 + .dw 0x7a00, 0xc032, 0x9fff, 0xc032, 0x21, 0 + .dw 0xba00, 0xc032, 0xdfff, 0xc032, 0x21, 0 + .dw 0xfa00, 0xc032, 0xffff, 0xc033, 0x21, 0 + .dw 0x1a00, 0xc034, 0x1fff, 0xc034, 0x21, 0 + .dw 0x3a00, 0xc034, 0x3fff, 0xc034, 0x21, 0 + .dw 0x5a00, 0xc034, 0x5fff, 0xc034, 0x21, 0 + .dw 0x7a00, 0xc034, 0x7fff, 0xc034, 0x21, 0 + .dw 0x9a00, 0xc034, 0x9fff, 0xc034, 0x21, 0 + .dw 0xba00, 0xc034, 0xbfff, 0xc034, 0x21, 0 + .dw 0xda00, 0xc034, 0xdfff, 0xc034, 0x21, 0 + .dw 0xfa00, 0xc034, 0xffff, 0xc034, 0x21, 0 + .dw 0x1a00, 0xc035, 0x1fff, 0xc035, 0x21, 0 + .dw 0x3a00, 0xc035, 0x3fff, 0xc035, 0x21, 0 + .dw 0x5a00, 0xc035, 0x5fff, 0xc035, 0x21, 0 + .dw 0x7a00, 0xc035, 0x7fff, 0xc035, 0x21, 0 + .dw 0x9a00, 0xc035, 0x9fff, 0xc035, 0x21, 0 + .dw 0xba00, 0xc035, 0xbfff, 0xc035, 0x21, 0 + .dw 0xda00, 0xc035, 0xdfff, 0xc035, 0x21, 0 + .dw 0xfa00, 0xc035, 0xffff, 0xc035, 0x21, 0 + .dw 0x1a00, 0xc036, 0x1fff, 0xc036, 0x21, 0 + .dw 0x3a00, 0xc036, 0x3fff, 0xc036, 0x21, 0 + .dw 0x5a00, 0xc036, 0x5fff, 0xc036, 0x21, 0 + .dw 0x7a00, 0xc036, 0x7fff, 0xc036, 0x21, 0 + .dw 0x9a00, 0xc036, 0x9fff, 0xc036, 0x21, 0 + .dw 0xba00, 0xc036, 0xbfff, 0xc036, 0x21, 0 + .dw 0xda00, 0xc036, 0xdfff, 0xc036, 0x21, 0 + .dw 0xfa00, 0xc036, 0xffff, 0xc036, 0x21, 0 + .dw 0x1a00, 0xc037, 0x1fff, 0xc037, 0x21, 0 + .dw 0x3a00, 0xc037, 0x1fff, 0xc038, 0x21, 0 + .dw 0x2040, 0xc038, 0x207f, 0xc038, 0x21, 0 + .dw 0x20c0, 0xc038, 0x20ff, 0xc038, 0x21, 0 + .dw 0x2140, 0xc038, 0x217f, 0xc038, 0x21, 0 + .dw 0x21c0, 0xc038, 0x21ff, 0xc038, 0x21, 0 + .dw 0x2240, 0xc038, 0x227f, 0xc038, 0x21, 0 + .dw 0x22c0, 0xc038, 0x22ff, 0xc038, 0x21, 0 + .dw 0x2340, 0xc038, 0x237f, 0xc038, 0x21, 0 + .dw 0x23c0, 0xc038, 0x23ff, 0xc038, 0x21, 0 + .dw 0x2440, 0xc038, 0x247f, 0xc038, 0x21, 0 + .dw 0x24c0, 0xc038, 0x24ff, 0xc038, 0x21, 0 + .dw 0x2540, 0xc038, 0x257f, 0xc038, 0x21, 0 + .dw 0x25c0, 0xc038, 0x25ff, 0xc038, 0x21, 0 + .dw 0x2640, 0xc038, 0x267f, 0xc038, 0x21, 0 + .dw 0x26c0, 0xc038, 0x26ff, 0xc038, 0x21, 0 + .dw 0x2740, 0xc038, 0x277f, 0xc038, 0x21, 0 + .dw 0x27c0, 0xc038, 0x27ff, 0xc038, 0x21, 0 + .dw 0x2840, 0xc038, 0x287f, 0xc038, 0x21, 0 + .dw 0x28c0, 0xc038, 0x28ff, 0xc038, 0x21, 0 + .dw 0x2940, 0xc038, 0x297f, 0xc038, 0x21, 0 + .dw 0x29c0, 0xc038, 0x29ff, 0xc038, 0x21, 0 + .dw 0x2a40, 0xc038, 0x2a7f, 0xc038, 0x21, 0 + .dw 0x2ac0, 0xc038, 0x2aff, 0xc038, 0x21, 0 + .dw 0x2b40, 0xc038, 0x2b7f, 0xc038, 0x21, 0 + .dw 0x2bc0, 0xc038, 0x2bff, 0xc038, 0x21, 0 + .dw 0x2c40, 0xc038, 0x2c7f, 0xc038, 0x21, 0 + .dw 0x2cc0, 0xc038, 0x2cff, 0xc038, 0x21, 0 + .dw 0x2d40, 0xc038, 0x2d7f, 0xc038, 0x21, 0 + .dw 0x2dc0, 0xc038, 0x2dff, 0xc038, 0x21, 0 + .dw 0x2e40, 0xc038, 0x2e7f, 0xc038, 0x21, 0 + .dw 0x2ec0, 0xc038, 0x2eff, 0xc038, 0x21, 0 + .dw 0x2f40, 0xc038, 0x2f7f, 0xc038, 0x21, 0 + .dw 0x2fc0, 0xc038, 0x2fff, 0xc038, 0x21, 0 + .dw 0x3040, 0xc038, 0x307f, 0xc038, 0x21, 0 + .dw 0x30c0, 0xc038, 0x30ff, 0xc038, 0x21, 0 + .dw 0x3140, 0xc038, 0x317f, 0xc038, 0x21, 0 + .dw 0x31c0, 0xc038, 0x31ff, 0xc038, 0x21, 0 + .dw 0x3240, 0xc038, 0x327f, 0xc038, 0x21, 0 + .dw 0x32c0, 0xc038, 0x32ff, 0xc038, 0x21, 0 + .dw 0x3340, 0xc038, 0x337f, 0xc038, 0x21, 0 + .dw 0x33c0, 0xc038, 0x33ff, 0xc038, 0x21, 0 + .dw 0x3440, 0xc038, 0x347f, 0xc038, 0x21, 0 + .dw 0x34c0, 0xc038, 0x34ff, 0xc038, 0x21, 0 + .dw 0x3540, 0xc038, 0x357f, 0xc038, 0x21, 0 + .dw 0x35c0, 0xc038, 0x35ff, 0xc038, 0x21, 0 + .dw 0x3640, 0xc038, 0x367f, 0xc038, 0x21, 0 + .dw 0x36c0, 0xc038, 0x36ff, 0xc038, 0x21, 0 + .dw 0x3740, 0xc038, 0x377f, 0xc038, 0x21, 0 + .dw 0x37c0, 0xc038, 0x37ff, 0xc038, 0x21, 0 + .dw 0x3840, 0xc038, 0x387f, 0xc038, 0x21, 0 + .dw 0x38c0, 0xc038, 0x38ff, 0xc038, 0x21, 0 + .dw 0x3940, 0xc038, 0x397f, 0xc038, 0x21, 0 + .dw 0x39c0, 0xc038, 0x5fff, 0xc038, 0x21, 0 + .dw 0x6040, 0xc038, 0x607f, 0xc038, 0x21, 0 + .dw 0x60c0, 0xc038, 0x60ff, 0xc038, 0x21, 0 + .dw 0x6140, 0xc038, 0x617f, 0xc038, 0x21, 0 + .dw 0x61c0, 0xc038, 0x61ff, 0xc038, 0x21, 0 + .dw 0x6240, 0xc038, 0x627f, 0xc038, 0x21, 0 + .dw 0x62c0, 0xc038, 0x62ff, 0xc038, 0x21, 0 + .dw 0x6340, 0xc038, 0x637f, 0xc038, 0x21, 0 + .dw 0x63c0, 0xc038, 0x63ff, 0xc038, 0x21, 0 + .dw 0x6440, 0xc038, 0x647f, 0xc038, 0x21, 0 + .dw 0x64c0, 0xc038, 0x64ff, 0xc038, 0x21, 0 + .dw 0x6540, 0xc038, 0x657f, 0xc038, 0x21, 0 + .dw 0x65c0, 0xc038, 0x65ff, 0xc038, 0x21, 0 + .dw 0x6640, 0xc038, 0x667f, 0xc038, 0x21, 0 + .dw 0x66c0, 0xc038, 0x66ff, 0xc038, 0x21, 0 + .dw 0x6740, 0xc038, 0x677f, 0xc038, 0x21, 0 + .dw 0x67c0, 0xc038, 0x67ff, 0xc038, 0x21, 0 + .dw 0x6840, 0xc038, 0x687f, 0xc038, 0x21, 0 + .dw 0x68c0, 0xc038, 0x68ff, 0xc038, 0x21, 0 + .dw 0x6940, 0xc038, 0x697f, 0xc038, 0x21, 0 + .dw 0x69c0, 0xc038, 0x69ff, 0xc038, 0x21, 0 + .dw 0x6a40, 0xc038, 0x6a7f, 0xc038, 0x21, 0 + .dw 0x6ac0, 0xc038, 0x6aff, 0xc038, 0x21, 0 + .dw 0x6b40, 0xc038, 0x6b7f, 0xc038, 0x21, 0 + .dw 0x6bc0, 0xc038, 0x6bff, 0xc038, 0x21, 0 + .dw 0x6c40, 0xc038, 0x6c7f, 0xc038, 0x21, 0 + .dw 0x6cc0, 0xc038, 0x6cff, 0xc038, 0x21, 0 + .dw 0x6d40, 0xc038, 0x6d7f, 0xc038, 0x21, 0 + .dw 0x6dc0, 0xc038, 0x6dff, 0xc038, 0x21, 0 + .dw 0x6e40, 0xc038, 0x6e7f, 0xc038, 0x21, 0 + .dw 0x6ec0, 0xc038, 0x6eff, 0xc038, 0x21, 0 + .dw 0x6f40, 0xc038, 0x6f7f, 0xc038, 0x21, 0 + .dw 0x6fc0, 0xc038, 0x6fff, 0xc038, 0x21, 0 + .dw 0x7040, 0xc038, 0x707f, 0xc038, 0x21, 0 + .dw 0x70c0, 0xc038, 0x70ff, 0xc038, 0x21, 0 + .dw 0x7140, 0xc038, 0x717f, 0xc038, 0x21, 0 + .dw 0x71c0, 0xc038, 0x71ff, 0xc038, 0x21, 0 + .dw 0x7240, 0xc038, 0x727f, 0xc038, 0x21, 0 + .dw 0x72c0, 0xc038, 0x72ff, 0xc038, 0x21, 0 + .dw 0x7340, 0xc038, 0x737f, 0xc038, 0x21, 0 + .dw 0x73c0, 0xc038, 0x73ff, 0xc038, 0x21, 0 + .dw 0x7440, 0xc038, 0x747f, 0xc038, 0x21, 0 + .dw 0x74c0, 0xc038, 0x74ff, 0xc038, 0x21, 0 + .dw 0x7540, 0xc038, 0x757f, 0xc038, 0x21, 0 + .dw 0x75c0, 0xc038, 0x75ff, 0xc038, 0x21, 0 + .dw 0x7640, 0xc038, 0x767f, 0xc038, 0x21, 0 + .dw 0x76c0, 0xc038, 0x76ff, 0xc038, 0x21, 0 + .dw 0x7740, 0xc038, 0x777f, 0xc038, 0x21, 0 + .dw 0x77c0, 0xc038, 0x77ff, 0xc038, 0x21, 0 + .dw 0x7840, 0xc038, 0x787f, 0xc038, 0x21, 0 + .dw 0x78c0, 0xc038, 0x78ff, 0xc038, 0x21, 0 + .dw 0x7940, 0xc038, 0x797f, 0xc038, 0x21, 0 + .dw 0x79c0, 0xc038, 0x9fff, 0xc038, 0x21, 0 + .dw 0xa040, 0xc038, 0xa07f, 0xc038, 0x21, 0 + .dw 0xa0c0, 0xc038, 0xa0ff, 0xc038, 0x21, 0 + .dw 0xa140, 0xc038, 0xa17f, 0xc038, 0x21, 0 + .dw 0xa1c0, 0xc038, 0xa1ff, 0xc038, 0x21, 0 + .dw 0xa240, 0xc038, 0xa27f, 0xc038, 0x21, 0 + .dw 0xa2c0, 0xc038, 0xa2ff, 0xc038, 0x21, 0 + .dw 0xa340, 0xc038, 0xa37f, 0xc038, 0x21, 0 + .dw 0xa3c0, 0xc038, 0xa3ff, 0xc038, 0x21, 0 + .dw 0xa440, 0xc038, 0xa47f, 0xc038, 0x21, 0 + .dw 0xa4c0, 0xc038, 0xa4ff, 0xc038, 0x21, 0 + .dw 0xa540, 0xc038, 0xa57f, 0xc038, 0x21, 0 + .dw 0xa5c0, 0xc038, 0xa5ff, 0xc038, 0x21, 0 + .dw 0xa640, 0xc038, 0xa67f, 0xc038, 0x21, 0 + .dw 0xa6c0, 0xc038, 0xa6ff, 0xc038, 0x21, 0 + .dw 0xa740, 0xc038, 0xa77f, 0xc038, 0x21, 0 + .dw 0xa7c0, 0xc038, 0xa7ff, 0xc038, 0x21, 0 + .dw 0xa840, 0xc038, 0xa87f, 0xc038, 0x21, 0 + .dw 0xa8c0, 0xc038, 0xa8ff, 0xc038, 0x21, 0 + .dw 0xa940, 0xc038, 0xa97f, 0xc038, 0x21, 0 + .dw 0xa9c0, 0xc038, 0xa9ff, 0xc038, 0x21, 0 + .dw 0xaa40, 0xc038, 0xaa7f, 0xc038, 0x21, 0 + .dw 0xaac0, 0xc038, 0xaaff, 0xc038, 0x21, 0 + .dw 0xab40, 0xc038, 0xab7f, 0xc038, 0x21, 0 + .dw 0xabc0, 0xc038, 0xabff, 0xc038, 0x21, 0 + .dw 0xac40, 0xc038, 0xac7f, 0xc038, 0x21, 0 + .dw 0xacc0, 0xc038, 0xacff, 0xc038, 0x21, 0 + .dw 0xad40, 0xc038, 0xad7f, 0xc038, 0x21, 0 + .dw 0xadc0, 0xc038, 0xadff, 0xc038, 0x21, 0 + .dw 0xae40, 0xc038, 0xae7f, 0xc038, 0x21, 0 + .dw 0xaec0, 0xc038, 0xaeff, 0xc038, 0x21, 0 + .dw 0xaf40, 0xc038, 0xaf7f, 0xc038, 0x21, 0 + .dw 0xafc0, 0xc038, 0xafff, 0xc038, 0x21, 0 + .dw 0xb040, 0xc038, 0xb07f, 0xc038, 0x21, 0 + .dw 0xb0c0, 0xc038, 0xb0ff, 0xc038, 0x21, 0 + .dw 0xb140, 0xc038, 0xb17f, 0xc038, 0x21, 0 + .dw 0xb1c0, 0xc038, 0xb1ff, 0xc038, 0x21, 0 + .dw 0xb240, 0xc038, 0xb27f, 0xc038, 0x21, 0 + .dw 0xb2c0, 0xc038, 0xb2ff, 0xc038, 0x21, 0 + .dw 0xb340, 0xc038, 0xb37f, 0xc038, 0x21, 0 + .dw 0xb3c0, 0xc038, 0xb3ff, 0xc038, 0x21, 0 + .dw 0xb440, 0xc038, 0xb47f, 0xc038, 0x21, 0 + .dw 0xb4c0, 0xc038, 0xb4ff, 0xc038, 0x21, 0 + .dw 0xb540, 0xc038, 0xb57f, 0xc038, 0x21, 0 + .dw 0xb5c0, 0xc038, 0xb5ff, 0xc038, 0x21, 0 + .dw 0xb640, 0xc038, 0xb67f, 0xc038, 0x21, 0 + .dw 0xb6c0, 0xc038, 0xb6ff, 0xc038, 0x21, 0 + .dw 0xb740, 0xc038, 0xb77f, 0xc038, 0x21, 0 + .dw 0xb7c0, 0xc038, 0xb7ff, 0xc038, 0x21, 0 + .dw 0xb840, 0xc038, 0xb87f, 0xc038, 0x21, 0 + .dw 0xb8c0, 0xc038, 0xb8ff, 0xc038, 0x21, 0 + .dw 0xb940, 0xc038, 0xb97f, 0xc038, 0x21, 0 + .dw 0xb9c0, 0xc038, 0xdfff, 0xc038, 0x21, 0 + .dw 0xe040, 0xc038, 0xe07f, 0xc038, 0x21, 0 + .dw 0xe0c0, 0xc038, 0xe0ff, 0xc038, 0x21, 0 + .dw 0xe140, 0xc038, 0xe17f, 0xc038, 0x21, 0 + .dw 0xe1c0, 0xc038, 0xe1ff, 0xc038, 0x21, 0 + .dw 0xe240, 0xc038, 0xe27f, 0xc038, 0x21, 0 + .dw 0xe2c0, 0xc038, 0xe2ff, 0xc038, 0x21, 0 + .dw 0xe340, 0xc038, 0xe37f, 0xc038, 0x21, 0 + .dw 0xe3c0, 0xc038, 0xe3ff, 0xc038, 0x21, 0 + .dw 0xe440, 0xc038, 0xe47f, 0xc038, 0x21, 0 + .dw 0xe4c0, 0xc038, 0xe4ff, 0xc038, 0x21, 0 + .dw 0xe540, 0xc038, 0xe57f, 0xc038, 0x21, 0 + .dw 0xe5c0, 0xc038, 0xe5ff, 0xc038, 0x21, 0 + .dw 0xe640, 0xc038, 0xe67f, 0xc038, 0x21, 0 + .dw 0xe6c0, 0xc038, 0xe6ff, 0xc038, 0x21, 0 + .dw 0xe740, 0xc038, 0xe77f, 0xc038, 0x21, 0 + .dw 0xe7c0, 0xc038, 0xe7ff, 0xc038, 0x21, 0 + .dw 0xe840, 0xc038, 0xe87f, 0xc038, 0x21, 0 + .dw 0xe8c0, 0xc038, 0xe8ff, 0xc038, 0x21, 0 + .dw 0xe940, 0xc038, 0xe97f, 0xc038, 0x21, 0 + .dw 0xe9c0, 0xc038, 0xe9ff, 0xc038, 0x21, 0 + .dw 0xea40, 0xc038, 0xea7f, 0xc038, 0x21, 0 + .dw 0xeac0, 0xc038, 0xeaff, 0xc038, 0x21, 0 + .dw 0xeb40, 0xc038, 0xeb7f, 0xc038, 0x21, 0 + .dw 0xebc0, 0xc038, 0xebff, 0xc038, 0x21, 0 + .dw 0xec40, 0xc038, 0xec7f, 0xc038, 0x21, 0 + .dw 0xecc0, 0xc038, 0xecff, 0xc038, 0x21, 0 + .dw 0xed40, 0xc038, 0xed7f, 0xc038, 0x21, 0 + .dw 0xedc0, 0xc038, 0xedff, 0xc038, 0x21, 0 + .dw 0xee40, 0xc038, 0xee7f, 0xc038, 0x21, 0 + .dw 0xeec0, 0xc038, 0xeeff, 0xc038, 0x21, 0 + .dw 0xef40, 0xc038, 0xef7f, 0xc038, 0x21, 0 + .dw 0xefc0, 0xc038, 0xefff, 0xc038, 0x21, 0 + .dw 0xf040, 0xc038, 0xf07f, 0xc038, 0x21, 0 + .dw 0xf0c0, 0xc038, 0xf0ff, 0xc038, 0x21, 0 + .dw 0xf140, 0xc038, 0xf17f, 0xc038, 0x21, 0 + .dw 0xf1c0, 0xc038, 0xf1ff, 0xc038, 0x21, 0 + .dw 0xf240, 0xc038, 0xf27f, 0xc038, 0x21, 0 + .dw 0xf2c0, 0xc038, 0xf2ff, 0xc038, 0x21, 0 + .dw 0xf340, 0xc038, 0xf37f, 0xc038, 0x21, 0 + .dw 0xf3c0, 0xc038, 0xf3ff, 0xc038, 0x21, 0 + .dw 0xf440, 0xc038, 0xf47f, 0xc038, 0x21, 0 + .dw 0xf4c0, 0xc038, 0xf4ff, 0xc038, 0x21, 0 + .dw 0xf540, 0xc038, 0xf57f, 0xc038, 0x21, 0 + .dw 0xf5c0, 0xc038, 0xf5ff, 0xc038, 0x21, 0 + .dw 0xf640, 0xc038, 0xf67f, 0xc038, 0x21, 0 + .dw 0xf6c0, 0xc038, 0xf6ff, 0xc038, 0x21, 0 + .dw 0xf740, 0xc038, 0xf77f, 0xc038, 0x21, 0 + .dw 0xf7c0, 0xc038, 0xf7ff, 0xc038, 0x21, 0 + .dw 0xf840, 0xc038, 0xf87f, 0xc038, 0x21, 0 + .dw 0xf8c0, 0xc038, 0xf8ff, 0xc038, 0x21, 0 + .dw 0xf940, 0xc038, 0xf97f, 0xc038, 0x21, 0 + .dw 0xf9c0, 0xc038, 0x1fff, 0xc039, 0x21, 0 + .dw 0x2040, 0xc039, 0x207f, 0xc039, 0x21, 0 + .dw 0x20c0, 0xc039, 0x20ff, 0xc039, 0x21, 0 + .dw 0x2140, 0xc039, 0x217f, 0xc039, 0x21, 0 + .dw 0x21c0, 0xc039, 0x21ff, 0xc039, 0x21, 0 + .dw 0x2240, 0xc039, 0x227f, 0xc039, 0x21, 0 + .dw 0x22c0, 0xc039, 0x22ff, 0xc039, 0x21, 0 + .dw 0x2340, 0xc039, 0x237f, 0xc039, 0x21, 0 + .dw 0x23c0, 0xc039, 0x23ff, 0xc039, 0x21, 0 + .dw 0x2440, 0xc039, 0x247f, 0xc039, 0x21, 0 + .dw 0x24c0, 0xc039, 0x24ff, 0xc039, 0x21, 0 + .dw 0x2540, 0xc039, 0x257f, 0xc039, 0x21, 0 + .dw 0x25c0, 0xc039, 0x25ff, 0xc039, 0x21, 0 + .dw 0x2640, 0xc039, 0x267f, 0xc039, 0x21, 0 + .dw 0x26c0, 0xc039, 0x26ff, 0xc039, 0x21, 0 + .dw 0x2740, 0xc039, 0x277f, 0xc039, 0x21, 0 + .dw 0x27c0, 0xc039, 0x27ff, 0xc039, 0x21, 0 + .dw 0x2840, 0xc039, 0x287f, 0xc039, 0x21, 0 + .dw 0x28c0, 0xc039, 0x28ff, 0xc039, 0x21, 0 + .dw 0x2940, 0xc039, 0x297f, 0xc039, 0x21, 0 + .dw 0x29c0, 0xc039, 0x29ff, 0xc039, 0x21, 0 + .dw 0x2a40, 0xc039, 0x2a7f, 0xc039, 0x21, 0 + .dw 0x2ac0, 0xc039, 0x2aff, 0xc039, 0x21, 0 + .dw 0x2b40, 0xc039, 0x2b7f, 0xc039, 0x21, 0 + .dw 0x2bc0, 0xc039, 0x2bff, 0xc039, 0x21, 0 + .dw 0x2c40, 0xc039, 0x2c7f, 0xc039, 0x21, 0 + .dw 0x2cc0, 0xc039, 0x2cff, 0xc039, 0x21, 0 + .dw 0x2d40, 0xc039, 0x2d7f, 0xc039, 0x21, 0 + .dw 0x2dc0, 0xc039, 0x2dff, 0xc039, 0x21, 0 + .dw 0x2e40, 0xc039, 0x2e7f, 0xc039, 0x21, 0 + .dw 0x2ec0, 0xc039, 0x2eff, 0xc039, 0x21, 0 + .dw 0x2f40, 0xc039, 0x2f7f, 0xc039, 0x21, 0 + .dw 0x2fc0, 0xc039, 0x2fff, 0xc039, 0x21, 0 + .dw 0x3040, 0xc039, 0x307f, 0xc039, 0x21, 0 + .dw 0x30c0, 0xc039, 0x30ff, 0xc039, 0x21, 0 + .dw 0x3140, 0xc039, 0x317f, 0xc039, 0x21, 0 + .dw 0x31c0, 0xc039, 0x31ff, 0xc039, 0x21, 0 + .dw 0x3240, 0xc039, 0x327f, 0xc039, 0x21, 0 + .dw 0x32c0, 0xc039, 0x32ff, 0xc039, 0x21, 0 + .dw 0x3340, 0xc039, 0x337f, 0xc039, 0x21, 0 + .dw 0x33c0, 0xc039, 0x33ff, 0xc039, 0x21, 0 + .dw 0x3440, 0xc039, 0x347f, 0xc039, 0x21, 0 + .dw 0x34c0, 0xc039, 0x34ff, 0xc039, 0x21, 0 + .dw 0x3540, 0xc039, 0x357f, 0xc039, 0x21, 0 + .dw 0x35c0, 0xc039, 0x35ff, 0xc039, 0x21, 0 + .dw 0x3640, 0xc039, 0x367f, 0xc039, 0x21, 0 + .dw 0x36c0, 0xc039, 0x36ff, 0xc039, 0x21, 0 + .dw 0x3740, 0xc039, 0x377f, 0xc039, 0x21, 0 + .dw 0x37c0, 0xc039, 0x37ff, 0xc039, 0x21, 0 + .dw 0x3840, 0xc039, 0x387f, 0xc039, 0x21, 0 + .dw 0x38c0, 0xc039, 0x38ff, 0xc039, 0x21, 0 + .dw 0x3940, 0xc039, 0x397f, 0xc039, 0x21, 0 + .dw 0x39c0, 0xc039, 0x5fff, 0xc039, 0x21, 0 + .dw 0x6040, 0xc039, 0x607f, 0xc039, 0x21, 0 + .dw 0x60c0, 0xc039, 0x60ff, 0xc039, 0x21, 0 + .dw 0x6140, 0xc039, 0x617f, 0xc039, 0x21, 0 + .dw 0x61c0, 0xc039, 0x61ff, 0xc039, 0x21, 0 + .dw 0x6240, 0xc039, 0x627f, 0xc039, 0x21, 0 + .dw 0x62c0, 0xc039, 0x62ff, 0xc039, 0x21, 0 + .dw 0x6340, 0xc039, 0x637f, 0xc039, 0x21, 0 + .dw 0x63c0, 0xc039, 0x63ff, 0xc039, 0x21, 0 + .dw 0x6440, 0xc039, 0x647f, 0xc039, 0x21, 0 + .dw 0x64c0, 0xc039, 0x64ff, 0xc039, 0x21, 0 + .dw 0x6540, 0xc039, 0x657f, 0xc039, 0x21, 0 + .dw 0x65c0, 0xc039, 0x65ff, 0xc039, 0x21, 0 + .dw 0x6640, 0xc039, 0x667f, 0xc039, 0x21, 0 + .dw 0x66c0, 0xc039, 0x66ff, 0xc039, 0x21, 0 + .dw 0x6740, 0xc039, 0x677f, 0xc039, 0x21, 0 + .dw 0x67c0, 0xc039, 0x67ff, 0xc039, 0x21, 0 + .dw 0x6840, 0xc039, 0x687f, 0xc039, 0x21, 0 + .dw 0x68c0, 0xc039, 0x68ff, 0xc039, 0x21, 0 + .dw 0x6940, 0xc039, 0x697f, 0xc039, 0x21, 0 + .dw 0x69c0, 0xc039, 0x69ff, 0xc039, 0x21, 0 + .dw 0x6a40, 0xc039, 0x6a7f, 0xc039, 0x21, 0 + .dw 0x6ac0, 0xc039, 0x6aff, 0xc039, 0x21, 0 + .dw 0x6b40, 0xc039, 0x6b7f, 0xc039, 0x21, 0 + .dw 0x6bc0, 0xc039, 0x6bff, 0xc039, 0x21, 0 + .dw 0x6c40, 0xc039, 0x6c7f, 0xc039, 0x21, 0 + .dw 0x6cc0, 0xc039, 0x6cff, 0xc039, 0x21, 0 + .dw 0x6d40, 0xc039, 0x6d7f, 0xc039, 0x21, 0 + .dw 0x6dc0, 0xc039, 0x6dff, 0xc039, 0x21, 0 + .dw 0x6e40, 0xc039, 0x6e7f, 0xc039, 0x21, 0 + .dw 0x6ec0, 0xc039, 0x6eff, 0xc039, 0x21, 0 + .dw 0x6f40, 0xc039, 0x6f7f, 0xc039, 0x21, 0 + .dw 0x6fc0, 0xc039, 0x6fff, 0xc039, 0x21, 0 + .dw 0x7040, 0xc039, 0x707f, 0xc039, 0x21, 0 + .dw 0x70c0, 0xc039, 0x70ff, 0xc039, 0x21, 0 + .dw 0x7140, 0xc039, 0x717f, 0xc039, 0x21, 0 + .dw 0x71c0, 0xc039, 0x71ff, 0xc039, 0x21, 0 + .dw 0x7240, 0xc039, 0x727f, 0xc039, 0x21, 0 + .dw 0x72c0, 0xc039, 0x72ff, 0xc039, 0x21, 0 + .dw 0x7340, 0xc039, 0x737f, 0xc039, 0x21, 0 + .dw 0x73c0, 0xc039, 0x73ff, 0xc039, 0x21, 0 + .dw 0x7440, 0xc039, 0x747f, 0xc039, 0x21, 0 + .dw 0x74c0, 0xc039, 0x74ff, 0xc039, 0x21, 0 + .dw 0x7540, 0xc039, 0x757f, 0xc039, 0x21, 0 + .dw 0x75c0, 0xc039, 0x75ff, 0xc039, 0x21, 0 + .dw 0x7640, 0xc039, 0x767f, 0xc039, 0x21, 0 + .dw 0x76c0, 0xc039, 0x76ff, 0xc039, 0x21, 0 + .dw 0x7740, 0xc039, 0x777f, 0xc039, 0x21, 0 + .dw 0x77c0, 0xc039, 0x77ff, 0xc039, 0x21, 0 + .dw 0x7840, 0xc039, 0x787f, 0xc039, 0x21, 0 + .dw 0x78c0, 0xc039, 0x78ff, 0xc039, 0x21, 0 + .dw 0x7940, 0xc039, 0x797f, 0xc039, 0x21, 0 + .dw 0x79c0, 0xc039, 0x9fff, 0xc039, 0x21, 0 + .dw 0xa040, 0xc039, 0xa07f, 0xc039, 0x21, 0 + .dw 0xa0c0, 0xc039, 0xa0ff, 0xc039, 0x21, 0 + .dw 0xa140, 0xc039, 0xa17f, 0xc039, 0x21, 0 + .dw 0xa1c0, 0xc039, 0xa1ff, 0xc039, 0x21, 0 + .dw 0xa240, 0xc039, 0xa27f, 0xc039, 0x21, 0 + .dw 0xa2c0, 0xc039, 0xa2ff, 0xc039, 0x21, 0 + .dw 0xa340, 0xc039, 0xa37f, 0xc039, 0x21, 0 + .dw 0xa3c0, 0xc039, 0xa3ff, 0xc039, 0x21, 0 + .dw 0xa440, 0xc039, 0xa47f, 0xc039, 0x21, 0 + .dw 0xa4c0, 0xc039, 0xa4ff, 0xc039, 0x21, 0 + .dw 0xa540, 0xc039, 0xa57f, 0xc039, 0x21, 0 + .dw 0xa5c0, 0xc039, 0xa5ff, 0xc039, 0x21, 0 + .dw 0xa640, 0xc039, 0xa67f, 0xc039, 0x21, 0 + .dw 0xa6c0, 0xc039, 0xa6ff, 0xc039, 0x21, 0 + .dw 0xa740, 0xc039, 0xa77f, 0xc039, 0x21, 0 + .dw 0xa7c0, 0xc039, 0xa7ff, 0xc039, 0x21, 0 + .dw 0xa840, 0xc039, 0xa87f, 0xc039, 0x21, 0 + .dw 0xa8c0, 0xc039, 0xa8ff, 0xc039, 0x21, 0 + .dw 0xa940, 0xc039, 0xa97f, 0xc039, 0x21, 0 + .dw 0xa9c0, 0xc039, 0xa9ff, 0xc039, 0x21, 0 + .dw 0xaa40, 0xc039, 0xaa7f, 0xc039, 0x21, 0 + .dw 0xaac0, 0xc039, 0xaaff, 0xc039, 0x21, 0 + .dw 0xab40, 0xc039, 0xab7f, 0xc039, 0x21, 0 + .dw 0xabc0, 0xc039, 0xabff, 0xc039, 0x21, 0 + .dw 0xac40, 0xc039, 0xac7f, 0xc039, 0x21, 0 + .dw 0xacc0, 0xc039, 0xacff, 0xc039, 0x21, 0 + .dw 0xad40, 0xc039, 0xad7f, 0xc039, 0x21, 0 + .dw 0xadc0, 0xc039, 0xadff, 0xc039, 0x21, 0 + .dw 0xae40, 0xc039, 0xae7f, 0xc039, 0x21, 0 + .dw 0xaec0, 0xc039, 0xaeff, 0xc039, 0x21, 0 + .dw 0xaf40, 0xc039, 0xaf7f, 0xc039, 0x21, 0 + .dw 0xafc0, 0xc039, 0xafff, 0xc039, 0x21, 0 + .dw 0xb040, 0xc039, 0xb07f, 0xc039, 0x21, 0 + .dw 0xb0c0, 0xc039, 0xb0ff, 0xc039, 0x21, 0 + .dw 0xb140, 0xc039, 0xb17f, 0xc039, 0x21, 0 + .dw 0xb1c0, 0xc039, 0xb1ff, 0xc039, 0x21, 0 + .dw 0xb240, 0xc039, 0xb27f, 0xc039, 0x21, 0 + .dw 0xb2c0, 0xc039, 0xb2ff, 0xc039, 0x21, 0 + .dw 0xb340, 0xc039, 0xb37f, 0xc039, 0x21, 0 + .dw 0xb3c0, 0xc039, 0xb3ff, 0xc039, 0x21, 0 + .dw 0xb440, 0xc039, 0xb47f, 0xc039, 0x21, 0 + .dw 0xb4c0, 0xc039, 0xb4ff, 0xc039, 0x21, 0 + .dw 0xb540, 0xc039, 0xb57f, 0xc039, 0x21, 0 + .dw 0xb5c0, 0xc039, 0xb5ff, 0xc039, 0x21, 0 + .dw 0xb640, 0xc039, 0xb67f, 0xc039, 0x21, 0 + .dw 0xb6c0, 0xc039, 0xb6ff, 0xc039, 0x21, 0 + .dw 0xb740, 0xc039, 0xb77f, 0xc039, 0x21, 0 + .dw 0xb7c0, 0xc039, 0xb7ff, 0xc039, 0x21, 0 + .dw 0xb840, 0xc039, 0xb87f, 0xc039, 0x21, 0 + .dw 0xb8c0, 0xc039, 0xb8ff, 0xc039, 0x21, 0 + .dw 0xb940, 0xc039, 0xb97f, 0xc039, 0x21, 0 + .dw 0xb9c0, 0xc039, 0xdfff, 0xc039, 0x21, 0 + .dw 0xe040, 0xc039, 0xe07f, 0xc039, 0x21, 0 + .dw 0xe0c0, 0xc039, 0xe0ff, 0xc039, 0x21, 0 + .dw 0xe140, 0xc039, 0xe17f, 0xc039, 0x21, 0 + .dw 0xe1c0, 0xc039, 0xe1ff, 0xc039, 0x21, 0 + .dw 0xe240, 0xc039, 0xe27f, 0xc039, 0x21, 0 + .dw 0xe2c0, 0xc039, 0xe2ff, 0xc039, 0x21, 0 + .dw 0xe340, 0xc039, 0xe37f, 0xc039, 0x21, 0 + .dw 0xe3c0, 0xc039, 0xe3ff, 0xc039, 0x21, 0 + .dw 0xe440, 0xc039, 0xe47f, 0xc039, 0x21, 0 + .dw 0xe4c0, 0xc039, 0xe4ff, 0xc039, 0x21, 0 + .dw 0xe540, 0xc039, 0xe57f, 0xc039, 0x21, 0 + .dw 0xe5c0, 0xc039, 0xe5ff, 0xc039, 0x21, 0 + .dw 0xe640, 0xc039, 0xe67f, 0xc039, 0x21, 0 + .dw 0xe6c0, 0xc039, 0xe6ff, 0xc039, 0x21, 0 + .dw 0xe740, 0xc039, 0xe77f, 0xc039, 0x21, 0 + .dw 0xe7c0, 0xc039, 0xe7ff, 0xc039, 0x21, 0 + .dw 0xe840, 0xc039, 0xe87f, 0xc039, 0x21, 0 + .dw 0xe8c0, 0xc039, 0xe8ff, 0xc039, 0x21, 0 + .dw 0xe940, 0xc039, 0xe97f, 0xc039, 0x21, 0 + .dw 0xe9c0, 0xc039, 0xe9ff, 0xc039, 0x21, 0 + .dw 0xea40, 0xc039, 0xea7f, 0xc039, 0x21, 0 + .dw 0xeac0, 0xc039, 0xeaff, 0xc039, 0x21, 0 + .dw 0xeb40, 0xc039, 0xeb7f, 0xc039, 0x21, 0 + .dw 0xebc0, 0xc039, 0xebff, 0xc039, 0x21, 0 + .dw 0xec40, 0xc039, 0xec7f, 0xc039, 0x21, 0 + .dw 0xecc0, 0xc039, 0xecff, 0xc039, 0x21, 0 + .dw 0xed40, 0xc039, 0xed7f, 0xc039, 0x21, 0 + .dw 0xedc0, 0xc039, 0xedff, 0xc039, 0x21, 0 + .dw 0xee40, 0xc039, 0xee7f, 0xc039, 0x21, 0 + .dw 0xeec0, 0xc039, 0xeeff, 0xc039, 0x21, 0 + .dw 0xef40, 0xc039, 0xef7f, 0xc039, 0x21, 0 + .dw 0xefc0, 0xc039, 0xefff, 0xc039, 0x21, 0 + .dw 0xf040, 0xc039, 0xf07f, 0xc039, 0x21, 0 + .dw 0xf0c0, 0xc039, 0xf0ff, 0xc039, 0x21, 0 + .dw 0xf140, 0xc039, 0xf17f, 0xc039, 0x21, 0 + .dw 0xf1c0, 0xc039, 0xf1ff, 0xc039, 0x21, 0 + .dw 0xf240, 0xc039, 0xf27f, 0xc039, 0x21, 0 + .dw 0xf2c0, 0xc039, 0xf2ff, 0xc039, 0x21, 0 + .dw 0xf340, 0xc039, 0xf37f, 0xc039, 0x21, 0 + .dw 0xf3c0, 0xc039, 0xf3ff, 0xc039, 0x21, 0 + .dw 0xf440, 0xc039, 0xf47f, 0xc039, 0x21, 0 + .dw 0xf4c0, 0xc039, 0xf4ff, 0xc039, 0x21, 0 + .dw 0xf540, 0xc039, 0xf57f, 0xc039, 0x21, 0 + .dw 0xf5c0, 0xc039, 0xf5ff, 0xc039, 0x21, 0 + .dw 0xf640, 0xc039, 0xf67f, 0xc039, 0x21, 0 + .dw 0xf6c0, 0xc039, 0xf6ff, 0xc039, 0x21, 0 + .dw 0xf740, 0xc039, 0xf77f, 0xc039, 0x21, 0 + .dw 0xf7c0, 0xc039, 0xf7ff, 0xc039, 0x21, 0 + .dw 0xf840, 0xc039, 0xf87f, 0xc039, 0x21, 0 + .dw 0xf8c0, 0xc039, 0xf8ff, 0xc039, 0x21, 0 + .dw 0xf940, 0xc039, 0xf97f, 0xc039, 0x21, 0 + .dw 0xf9c0, 0xc039, 0x1fff, 0xc03a, 0x21, 0 + .dw 0x2040, 0xc03a, 0x207f, 0xc03a, 0x21, 0 + .dw 0x20c0, 0xc03a, 0x20ff, 0xc03a, 0x21, 0 + .dw 0x2140, 0xc03a, 0x217f, 0xc03a, 0x21, 0 + .dw 0x21c0, 0xc03a, 0x21ff, 0xc03a, 0x21, 0 + .dw 0x2240, 0xc03a, 0x227f, 0xc03a, 0x21, 0 + .dw 0x22c0, 0xc03a, 0x22ff, 0xc03a, 0x21, 0 + .dw 0x2340, 0xc03a, 0x237f, 0xc03a, 0x21, 0 + .dw 0x23c0, 0xc03a, 0x23ff, 0xc03a, 0x21, 0 + .dw 0x2440, 0xc03a, 0x247f, 0xc03a, 0x21, 0 + .dw 0x24c0, 0xc03a, 0x24ff, 0xc03a, 0x21, 0 + .dw 0x2540, 0xc03a, 0x257f, 0xc03a, 0x21, 0 + .dw 0x25c0, 0xc03a, 0x25ff, 0xc03a, 0x21, 0 + .dw 0x2640, 0xc03a, 0x267f, 0xc03a, 0x21, 0 + .dw 0x26c0, 0xc03a, 0x26ff, 0xc03a, 0x21, 0 + .dw 0x2740, 0xc03a, 0x277f, 0xc03a, 0x21, 0 + .dw 0x27c0, 0xc03a, 0x27ff, 0xc03a, 0x21, 0 + .dw 0x2840, 0xc03a, 0x287f, 0xc03a, 0x21, 0 + .dw 0x28c0, 0xc03a, 0x28ff, 0xc03a, 0x21, 0 + .dw 0x2940, 0xc03a, 0x297f, 0xc03a, 0x21, 0 + .dw 0x29c0, 0xc03a, 0x29ff, 0xc03a, 0x21, 0 + .dw 0x2a40, 0xc03a, 0x2a7f, 0xc03a, 0x21, 0 + .dw 0x2ac0, 0xc03a, 0x2aff, 0xc03a, 0x21, 0 + .dw 0x2b40, 0xc03a, 0x2b7f, 0xc03a, 0x21, 0 + .dw 0x2bc0, 0xc03a, 0x2bff, 0xc03a, 0x21, 0 + .dw 0x2c40, 0xc03a, 0x2c7f, 0xc03a, 0x21, 0 + .dw 0x2cc0, 0xc03a, 0x2cff, 0xc03a, 0x21, 0 + .dw 0x2d40, 0xc03a, 0x2d7f, 0xc03a, 0x21, 0 + .dw 0x2dc0, 0xc03a, 0x2dff, 0xc03a, 0x21, 0 + .dw 0x2e40, 0xc03a, 0x2e7f, 0xc03a, 0x21, 0 + .dw 0x2ec0, 0xc03a, 0x2eff, 0xc03a, 0x21, 0 + .dw 0x2f40, 0xc03a, 0x2f7f, 0xc03a, 0x21, 0 + .dw 0x2fc0, 0xc03a, 0x2fff, 0xc03a, 0x21, 0 + .dw 0x3040, 0xc03a, 0x307f, 0xc03a, 0x21, 0 + .dw 0x30c0, 0xc03a, 0x30ff, 0xc03a, 0x21, 0 + .dw 0x3140, 0xc03a, 0x317f, 0xc03a, 0x21, 0 + .dw 0x31c0, 0xc03a, 0x31ff, 0xc03a, 0x21, 0 + .dw 0x3240, 0xc03a, 0x327f, 0xc03a, 0x21, 0 + .dw 0x32c0, 0xc03a, 0x32ff, 0xc03a, 0x21, 0 + .dw 0x3340, 0xc03a, 0x337f, 0xc03a, 0x21, 0 + .dw 0x33c0, 0xc03a, 0x33ff, 0xc03a, 0x21, 0 + .dw 0x3440, 0xc03a, 0x347f, 0xc03a, 0x21, 0 + .dw 0x34c0, 0xc03a, 0x34ff, 0xc03a, 0x21, 0 + .dw 0x3540, 0xc03a, 0x357f, 0xc03a, 0x21, 0 + .dw 0x35c0, 0xc03a, 0x35ff, 0xc03a, 0x21, 0 + .dw 0x3640, 0xc03a, 0x367f, 0xc03a, 0x21, 0 + .dw 0x36c0, 0xc03a, 0x36ff, 0xc03a, 0x21, 0 + .dw 0x3740, 0xc03a, 0x377f, 0xc03a, 0x21, 0 + .dw 0x37c0, 0xc03a, 0x37ff, 0xc03a, 0x21, 0 + .dw 0x3840, 0xc03a, 0x387f, 0xc03a, 0x21, 0 + .dw 0x38c0, 0xc03a, 0x38ff, 0xc03a, 0x21, 0 + .dw 0x3940, 0xc03a, 0x397f, 0xc03a, 0x21, 0 + .dw 0x39c0, 0xc03a, 0x5fff, 0xc03a, 0x21, 0 + .dw 0x6040, 0xc03a, 0x607f, 0xc03a, 0x21, 0 + .dw 0x60c0, 0xc03a, 0x60ff, 0xc03a, 0x21, 0 + .dw 0x6140, 0xc03a, 0x617f, 0xc03a, 0x21, 0 + .dw 0x61c0, 0xc03a, 0x61ff, 0xc03a, 0x21, 0 + .dw 0x6240, 0xc03a, 0x627f, 0xc03a, 0x21, 0 + .dw 0x62c0, 0xc03a, 0x62ff, 0xc03a, 0x21, 0 + .dw 0x6340, 0xc03a, 0x637f, 0xc03a, 0x21, 0 + .dw 0x63c0, 0xc03a, 0x63ff, 0xc03a, 0x21, 0 + .dw 0x6440, 0xc03a, 0x647f, 0xc03a, 0x21, 0 + .dw 0x64c0, 0xc03a, 0x64ff, 0xc03a, 0x21, 0 + .dw 0x6540, 0xc03a, 0x657f, 0xc03a, 0x21, 0 + .dw 0x65c0, 0xc03a, 0x65ff, 0xc03a, 0x21, 0 + .dw 0x6640, 0xc03a, 0x667f, 0xc03a, 0x21, 0 + .dw 0x66c0, 0xc03a, 0x66ff, 0xc03a, 0x21, 0 + .dw 0x6740, 0xc03a, 0x677f, 0xc03a, 0x21, 0 + .dw 0x67c0, 0xc03a, 0x67ff, 0xc03a, 0x21, 0 + .dw 0x6840, 0xc03a, 0x687f, 0xc03a, 0x21, 0 + .dw 0x68c0, 0xc03a, 0x68ff, 0xc03a, 0x21, 0 + .dw 0x6940, 0xc03a, 0x697f, 0xc03a, 0x21, 0 + .dw 0x69c0, 0xc03a, 0x69ff, 0xc03a, 0x21, 0 + .dw 0x6a40, 0xc03a, 0x6a7f, 0xc03a, 0x21, 0 + .dw 0x6ac0, 0xc03a, 0x6aff, 0xc03a, 0x21, 0 + .dw 0x6b40, 0xc03a, 0x6b7f, 0xc03a, 0x21, 0 + .dw 0x6bc0, 0xc03a, 0x6bff, 0xc03a, 0x21, 0 + .dw 0x6c40, 0xc03a, 0x6c7f, 0xc03a, 0x21, 0 + .dw 0x6cc0, 0xc03a, 0x6cff, 0xc03a, 0x21, 0 + .dw 0x6d40, 0xc03a, 0x6d7f, 0xc03a, 0x21, 0 + .dw 0x6dc0, 0xc03a, 0x6dff, 0xc03a, 0x21, 0 + .dw 0x6e40, 0xc03a, 0x6e7f, 0xc03a, 0x21, 0 + .dw 0x6ec0, 0xc03a, 0x6eff, 0xc03a, 0x21, 0 + .dw 0x6f40, 0xc03a, 0x6f7f, 0xc03a, 0x21, 0 + .dw 0x6fc0, 0xc03a, 0x6fff, 0xc03a, 0x21, 0 + .dw 0x7040, 0xc03a, 0x707f, 0xc03a, 0x21, 0 + .dw 0x70c0, 0xc03a, 0x70ff, 0xc03a, 0x21, 0 + .dw 0x7140, 0xc03a, 0x717f, 0xc03a, 0x21, 0 + .dw 0x71c0, 0xc03a, 0x71ff, 0xc03a, 0x21, 0 + .dw 0x7240, 0xc03a, 0x727f, 0xc03a, 0x21, 0 + .dw 0x72c0, 0xc03a, 0x72ff, 0xc03a, 0x21, 0 + .dw 0x7340, 0xc03a, 0x737f, 0xc03a, 0x21, 0 + .dw 0x73c0, 0xc03a, 0x73ff, 0xc03a, 0x21, 0 + .dw 0x7440, 0xc03a, 0x747f, 0xc03a, 0x21, 0 + .dw 0x74c0, 0xc03a, 0x74ff, 0xc03a, 0x21, 0 + .dw 0x7540, 0xc03a, 0x757f, 0xc03a, 0x21, 0 + .dw 0x75c0, 0xc03a, 0x75ff, 0xc03a, 0x21, 0 + .dw 0x7640, 0xc03a, 0x767f, 0xc03a, 0x21, 0 + .dw 0x76c0, 0xc03a, 0x76ff, 0xc03a, 0x21, 0 + .dw 0x7740, 0xc03a, 0x777f, 0xc03a, 0x21, 0 + .dw 0x77c0, 0xc03a, 0x77ff, 0xc03a, 0x21, 0 + .dw 0x7840, 0xc03a, 0x787f, 0xc03a, 0x21, 0 + .dw 0x78c0, 0xc03a, 0x78ff, 0xc03a, 0x21, 0 + .dw 0x7940, 0xc03a, 0x797f, 0xc03a, 0x21, 0 + .dw 0x79c0, 0xc03a, 0x9fff, 0xc03a, 0x21, 0 + .dw 0xa040, 0xc03a, 0xa07f, 0xc03a, 0x21, 0 + .dw 0xa0c0, 0xc03a, 0xa0ff, 0xc03a, 0x21, 0 + .dw 0xa140, 0xc03a, 0xa17f, 0xc03a, 0x21, 0 + .dw 0xa1c0, 0xc03a, 0xa1ff, 0xc03a, 0x21, 0 + .dw 0xa240, 0xc03a, 0xa27f, 0xc03a, 0x21, 0 + .dw 0xa2c0, 0xc03a, 0xa2ff, 0xc03a, 0x21, 0 + .dw 0xa340, 0xc03a, 0xa37f, 0xc03a, 0x21, 0 + .dw 0xa3c0, 0xc03a, 0xa3ff, 0xc03a, 0x21, 0 + .dw 0xa440, 0xc03a, 0xa47f, 0xc03a, 0x21, 0 + .dw 0xa4c0, 0xc03a, 0xa4ff, 0xc03a, 0x21, 0 + .dw 0xa540, 0xc03a, 0xa57f, 0xc03a, 0x21, 0 + .dw 0xa5c0, 0xc03a, 0xa5ff, 0xc03a, 0x21, 0 + .dw 0xa640, 0xc03a, 0xa67f, 0xc03a, 0x21, 0 + .dw 0xa6c0, 0xc03a, 0xa6ff, 0xc03a, 0x21, 0 + .dw 0xa740, 0xc03a, 0xa77f, 0xc03a, 0x21, 0 + .dw 0xa7c0, 0xc03a, 0xa7ff, 0xc03a, 0x21, 0 + .dw 0xa840, 0xc03a, 0xa87f, 0xc03a, 0x21, 0 + .dw 0xa8c0, 0xc03a, 0xa8ff, 0xc03a, 0x21, 0 + .dw 0xa940, 0xc03a, 0xa97f, 0xc03a, 0x21, 0 + .dw 0xa9c0, 0xc03a, 0xa9ff, 0xc03a, 0x21, 0 + .dw 0xaa40, 0xc03a, 0xaa7f, 0xc03a, 0x21, 0 + .dw 0xaac0, 0xc03a, 0xaaff, 0xc03a, 0x21, 0 + .dw 0xab40, 0xc03a, 0xab7f, 0xc03a, 0x21, 0 + .dw 0xabc0, 0xc03a, 0xabff, 0xc03a, 0x21, 0 + .dw 0xac40, 0xc03a, 0xac7f, 0xc03a, 0x21, 0 + .dw 0xacc0, 0xc03a, 0xacff, 0xc03a, 0x21, 0 + .dw 0xad40, 0xc03a, 0xad7f, 0xc03a, 0x21, 0 + .dw 0xadc0, 0xc03a, 0xadff, 0xc03a, 0x21, 0 + .dw 0xae40, 0xc03a, 0xae7f, 0xc03a, 0x21, 0 + .dw 0xaec0, 0xc03a, 0xaeff, 0xc03a, 0x21, 0 + .dw 0xaf40, 0xc03a, 0xaf7f, 0xc03a, 0x21, 0 + .dw 0xafc0, 0xc03a, 0xafff, 0xc03a, 0x21, 0 + .dw 0xb040, 0xc03a, 0xb07f, 0xc03a, 0x21, 0 + .dw 0xb0c0, 0xc03a, 0xb0ff, 0xc03a, 0x21, 0 + .dw 0xb140, 0xc03a, 0xb17f, 0xc03a, 0x21, 0 + .dw 0xb1c0, 0xc03a, 0xb1ff, 0xc03a, 0x21, 0 + .dw 0xb240, 0xc03a, 0xb27f, 0xc03a, 0x21, 0 + .dw 0xb2c0, 0xc03a, 0xb2ff, 0xc03a, 0x21, 0 + .dw 0xb340, 0xc03a, 0xb37f, 0xc03a, 0x21, 0 + .dw 0xb3c0, 0xc03a, 0xb3ff, 0xc03a, 0x21, 0 + .dw 0xb440, 0xc03a, 0xb47f, 0xc03a, 0x21, 0 + .dw 0xb4c0, 0xc03a, 0xb4ff, 0xc03a, 0x21, 0 + .dw 0xb540, 0xc03a, 0xb57f, 0xc03a, 0x21, 0 + .dw 0xb5c0, 0xc03a, 0xb5ff, 0xc03a, 0x21, 0 + .dw 0xb640, 0xc03a, 0xb67f, 0xc03a, 0x21, 0 + .dw 0xb6c0, 0xc03a, 0xb6ff, 0xc03a, 0x21, 0 + .dw 0xb740, 0xc03a, 0xb77f, 0xc03a, 0x21, 0 + .dw 0xb7c0, 0xc03a, 0xb7ff, 0xc03a, 0x21, 0 + .dw 0xb840, 0xc03a, 0xb87f, 0xc03a, 0x21, 0 + .dw 0xb8c0, 0xc03a, 0xb8ff, 0xc03a, 0x21, 0 + .dw 0xb940, 0xc03a, 0xb97f, 0xc03a, 0x21, 0 + .dw 0xb9c0, 0xc03a, 0xdfff, 0xc03a, 0x21, 0 + .dw 0xe040, 0xc03a, 0xe07f, 0xc03a, 0x21, 0 + .dw 0xe0c0, 0xc03a, 0xe0ff, 0xc03a, 0x21, 0 + .dw 0xe140, 0xc03a, 0xe17f, 0xc03a, 0x21, 0 + .dw 0xe1c0, 0xc03a, 0xe1ff, 0xc03a, 0x21, 0 + .dw 0xe240, 0xc03a, 0xe27f, 0xc03a, 0x21, 0 + .dw 0xe2c0, 0xc03a, 0xe2ff, 0xc03a, 0x21, 0 + .dw 0xe340, 0xc03a, 0xe37f, 0xc03a, 0x21, 0 + .dw 0xe3c0, 0xc03a, 0xe3ff, 0xc03a, 0x21, 0 + .dw 0xe440, 0xc03a, 0xe47f, 0xc03a, 0x21, 0 + .dw 0xe4c0, 0xc03a, 0xe4ff, 0xc03a, 0x21, 0 + .dw 0xe540, 0xc03a, 0xe57f, 0xc03a, 0x21, 0 + .dw 0xe5c0, 0xc03a, 0xe5ff, 0xc03a, 0x21, 0 + .dw 0xe640, 0xc03a, 0xe67f, 0xc03a, 0x21, 0 + .dw 0xe6c0, 0xc03a, 0xe6ff, 0xc03a, 0x21, 0 + .dw 0xe740, 0xc03a, 0xe77f, 0xc03a, 0x21, 0 + .dw 0xe7c0, 0xc03a, 0xe7ff, 0xc03a, 0x21, 0 + .dw 0xe840, 0xc03a, 0xe87f, 0xc03a, 0x21, 0 + .dw 0xe8c0, 0xc03a, 0xe8ff, 0xc03a, 0x21, 0 + .dw 0xe940, 0xc03a, 0xe97f, 0xc03a, 0x21, 0 + .dw 0xe9c0, 0xc03a, 0xe9ff, 0xc03a, 0x21, 0 + .dw 0xea40, 0xc03a, 0xea7f, 0xc03a, 0x21, 0 + .dw 0xeac0, 0xc03a, 0xeaff, 0xc03a, 0x21, 0 + .dw 0xeb40, 0xc03a, 0xeb7f, 0xc03a, 0x21, 0 + .dw 0xebc0, 0xc03a, 0xebff, 0xc03a, 0x21, 0 + .dw 0xec40, 0xc03a, 0xec7f, 0xc03a, 0x21, 0 + .dw 0xecc0, 0xc03a, 0xecff, 0xc03a, 0x21, 0 + .dw 0xed40, 0xc03a, 0xed7f, 0xc03a, 0x21, 0 + .dw 0xedc0, 0xc03a, 0xedff, 0xc03a, 0x21, 0 + .dw 0xee40, 0xc03a, 0xee7f, 0xc03a, 0x21, 0 + .dw 0xeec0, 0xc03a, 0xeeff, 0xc03a, 0x21, 0 + .dw 0xef40, 0xc03a, 0xef7f, 0xc03a, 0x21, 0 + .dw 0xefc0, 0xc03a, 0xefff, 0xc03a, 0x21, 0 + .dw 0xf040, 0xc03a, 0xf07f, 0xc03a, 0x21, 0 + .dw 0xf0c0, 0xc03a, 0xf0ff, 0xc03a, 0x21, 0 + .dw 0xf140, 0xc03a, 0xf17f, 0xc03a, 0x21, 0 + .dw 0xf1c0, 0xc03a, 0xf1ff, 0xc03a, 0x21, 0 + .dw 0xf240, 0xc03a, 0xf27f, 0xc03a, 0x21, 0 + .dw 0xf2c0, 0xc03a, 0xf2ff, 0xc03a, 0x21, 0 + .dw 0xf340, 0xc03a, 0xf37f, 0xc03a, 0x21, 0 + .dw 0xf3c0, 0xc03a, 0xf3ff, 0xc03a, 0x21, 0 + .dw 0xf440, 0xc03a, 0xf47f, 0xc03a, 0x21, 0 + .dw 0xf4c0, 0xc03a, 0xf4ff, 0xc03a, 0x21, 0 + .dw 0xf540, 0xc03a, 0xf57f, 0xc03a, 0x21, 0 + .dw 0xf5c0, 0xc03a, 0xf5ff, 0xc03a, 0x21, 0 + .dw 0xf640, 0xc03a, 0xf67f, 0xc03a, 0x21, 0 + .dw 0xf6c0, 0xc03a, 0xf6ff, 0xc03a, 0x21, 0 + .dw 0xf740, 0xc03a, 0xf77f, 0xc03a, 0x21, 0 + .dw 0xf7c0, 0xc03a, 0xf7ff, 0xc03a, 0x21, 0 + .dw 0xf840, 0xc03a, 0xf87f, 0xc03a, 0x21, 0 + .dw 0xf8c0, 0xc03a, 0xf8ff, 0xc03a, 0x21, 0 + .dw 0xf940, 0xc03a, 0xf97f, 0xc03a, 0x21, 0 + .dw 0xf9c0, 0xc03a, 0xffff, 0xc03b, 0x21, 0 + .dw 0x0040, 0xc03c, 0x007f, 0xc03c, 0x21, 0 + .dw 0x00c0, 0xc03c, 0x00ff, 0xc03c, 0x21, 0 + .dw 0x0140, 0xc03c, 0x017f, 0xc03c, 0x21, 0 + .dw 0x01c0, 0xc03c, 0x01ff, 0xc03c, 0x21, 0 + .dw 0x0240, 0xc03c, 0x027f, 0xc03c, 0x21, 0 + .dw 0x02c0, 0xc03c, 0x02ff, 0xc03c, 0x21, 0 + .dw 0x0340, 0xc03c, 0x037f, 0xc03c, 0x21, 0 + .dw 0x03c0, 0xc03c, 0x03ff, 0xc03c, 0x21, 0 + .dw 0x0440, 0xc03c, 0x047f, 0xc03c, 0x21, 0 + .dw 0x04c0, 0xc03c, 0x04ff, 0xc03c, 0x21, 0 + .dw 0x0540, 0xc03c, 0x057f, 0xc03c, 0x21, 0 + .dw 0x05c0, 0xc03c, 0x05ff, 0xc03c, 0x21, 0 + .dw 0x0640, 0xc03c, 0x067f, 0xc03c, 0x21, 0 + .dw 0x06c0, 0xc03c, 0x06ff, 0xc03c, 0x21, 0 + .dw 0x0740, 0xc03c, 0x077f, 0xc03c, 0x21, 0 + .dw 0x07c0, 0xc03c, 0x07ff, 0xc03c, 0x21, 0 + .dw 0x0840, 0xc03c, 0x087f, 0xc03c, 0x21, 0 + .dw 0x08c0, 0xc03c, 0x08ff, 0xc03c, 0x21, 0 + .dw 0x0940, 0xc03c, 0x097f, 0xc03c, 0x21, 0 + .dw 0x09c0, 0xc03c, 0x09ff, 0xc03c, 0x21, 0 + .dw 0x0a40, 0xc03c, 0x0a7f, 0xc03c, 0x21, 0 + .dw 0x0ac0, 0xc03c, 0x0aff, 0xc03c, 0x21, 0 + .dw 0x0b40, 0xc03c, 0x0b7f, 0xc03c, 0x21, 0 + .dw 0x0bc0, 0xc03c, 0x0bff, 0xc03c, 0x21, 0 + .dw 0x0c40, 0xc03c, 0x0c7f, 0xc03c, 0x21, 0 + .dw 0x0cc0, 0xc03c, 0x0cff, 0xc03c, 0x21, 0 + .dw 0x0d40, 0xc03c, 0x0d7f, 0xc03c, 0x21, 0 + .dw 0x0dc0, 0xc03c, 0x0dff, 0xc03c, 0x21, 0 + .dw 0x0e40, 0xc03c, 0x0e7f, 0xc03c, 0x21, 0 + .dw 0x0ec0, 0xc03c, 0x0eff, 0xc03c, 0x21, 0 + .dw 0x0f40, 0xc03c, 0x0f7f, 0xc03c, 0x21, 0 + .dw 0x0fc0, 0xc03c, 0x0fff, 0xc03c, 0x21, 0 + .dw 0x1040, 0xc03c, 0x107f, 0xc03c, 0x21, 0 + .dw 0x10c0, 0xc03c, 0x10ff, 0xc03c, 0x21, 0 + .dw 0x1140, 0xc03c, 0x117f, 0xc03c, 0x21, 0 + .dw 0x11c0, 0xc03c, 0x11ff, 0xc03c, 0x21, 0 + .dw 0x1240, 0xc03c, 0x127f, 0xc03c, 0x21, 0 + .dw 0x12c0, 0xc03c, 0x12ff, 0xc03c, 0x21, 0 + .dw 0x1340, 0xc03c, 0x137f, 0xc03c, 0x21, 0 + .dw 0x13c0, 0xc03c, 0x13ff, 0xc03c, 0x21, 0 + .dw 0x1440, 0xc03c, 0x147f, 0xc03c, 0x21, 0 + .dw 0x14c0, 0xc03c, 0x14ff, 0xc03c, 0x21, 0 + .dw 0x1540, 0xc03c, 0x157f, 0xc03c, 0x21, 0 + .dw 0x15c0, 0xc03c, 0x15ff, 0xc03c, 0x21, 0 + .dw 0x1640, 0xc03c, 0x167f, 0xc03c, 0x21, 0 + .dw 0x16c0, 0xc03c, 0x16ff, 0xc03c, 0x21, 0 + .dw 0x1740, 0xc03c, 0x177f, 0xc03c, 0x21, 0 + .dw 0x17c0, 0xc03c, 0x17ff, 0xc03c, 0x21, 0 + .dw 0x1840, 0xc03c, 0x187f, 0xc03c, 0x21, 0 + .dw 0x18c0, 0xc03c, 0x18ff, 0xc03c, 0x21, 0 + .dw 0x1940, 0xc03c, 0x197f, 0xc03c, 0x21, 0 + .dw 0x19c0, 0xc03c, 0x1fff, 0xc03c, 0x21, 0 + .dw 0x2040, 0xc03c, 0x207f, 0xc03c, 0x21, 0 + .dw 0x20c0, 0xc03c, 0x20ff, 0xc03c, 0x21, 0 + .dw 0x2140, 0xc03c, 0x217f, 0xc03c, 0x21, 0 + .dw 0x21c0, 0xc03c, 0x21ff, 0xc03c, 0x21, 0 + .dw 0x2240, 0xc03c, 0x227f, 0xc03c, 0x21, 0 + .dw 0x22c0, 0xc03c, 0x22ff, 0xc03c, 0x21, 0 + .dw 0x2340, 0xc03c, 0x237f, 0xc03c, 0x21, 0 + .dw 0x23c0, 0xc03c, 0x23ff, 0xc03c, 0x21, 0 + .dw 0x2440, 0xc03c, 0x247f, 0xc03c, 0x21, 0 + .dw 0x24c0, 0xc03c, 0x24ff, 0xc03c, 0x21, 0 + .dw 0x2540, 0xc03c, 0x257f, 0xc03c, 0x21, 0 + .dw 0x25c0, 0xc03c, 0x25ff, 0xc03c, 0x21, 0 + .dw 0x2640, 0xc03c, 0x267f, 0xc03c, 0x21, 0 + .dw 0x26c0, 0xc03c, 0x26ff, 0xc03c, 0x21, 0 + .dw 0x2740, 0xc03c, 0x277f, 0xc03c, 0x21, 0 + .dw 0x27c0, 0xc03c, 0x27ff, 0xc03c, 0x21, 0 + .dw 0x2840, 0xc03c, 0x287f, 0xc03c, 0x21, 0 + .dw 0x28c0, 0xc03c, 0x28ff, 0xc03c, 0x21, 0 + .dw 0x2940, 0xc03c, 0x297f, 0xc03c, 0x21, 0 + .dw 0x29c0, 0xc03c, 0x29ff, 0xc03c, 0x21, 0 + .dw 0x2a40, 0xc03c, 0x2a7f, 0xc03c, 0x21, 0 + .dw 0x2ac0, 0xc03c, 0x2aff, 0xc03c, 0x21, 0 + .dw 0x2b40, 0xc03c, 0x2b7f, 0xc03c, 0x21, 0 + .dw 0x2bc0, 0xc03c, 0x2bff, 0xc03c, 0x21, 0 + .dw 0x2c40, 0xc03c, 0x2c7f, 0xc03c, 0x21, 0 + .dw 0x2cc0, 0xc03c, 0x2cff, 0xc03c, 0x21, 0 + .dw 0x2d40, 0xc03c, 0x2d7f, 0xc03c, 0x21, 0 + .dw 0x2dc0, 0xc03c, 0x2dff, 0xc03c, 0x21, 0 + .dw 0x2e40, 0xc03c, 0x2e7f, 0xc03c, 0x21, 0 + .dw 0x2ec0, 0xc03c, 0x2eff, 0xc03c, 0x21, 0 + .dw 0x2f40, 0xc03c, 0x2f7f, 0xc03c, 0x21, 0 + .dw 0x2fc0, 0xc03c, 0x2fff, 0xc03c, 0x21, 0 + .dw 0x3040, 0xc03c, 0x307f, 0xc03c, 0x21, 0 + .dw 0x30c0, 0xc03c, 0x30ff, 0xc03c, 0x21, 0 + .dw 0x3140, 0xc03c, 0x317f, 0xc03c, 0x21, 0 + .dw 0x31c0, 0xc03c, 0x31ff, 0xc03c, 0x21, 0 + .dw 0x3240, 0xc03c, 0x327f, 0xc03c, 0x21, 0 + .dw 0x32c0, 0xc03c, 0x32ff, 0xc03c, 0x21, 0 + .dw 0x3340, 0xc03c, 0x337f, 0xc03c, 0x21, 0 + .dw 0x33c0, 0xc03c, 0x33ff, 0xc03c, 0x21, 0 + .dw 0x3440, 0xc03c, 0x347f, 0xc03c, 0x21, 0 + .dw 0x34c0, 0xc03c, 0x34ff, 0xc03c, 0x21, 0 + .dw 0x3540, 0xc03c, 0x357f, 0xc03c, 0x21, 0 + .dw 0x35c0, 0xc03c, 0x35ff, 0xc03c, 0x21, 0 + .dw 0x3640, 0xc03c, 0x367f, 0xc03c, 0x21, 0 + .dw 0x36c0, 0xc03c, 0x36ff, 0xc03c, 0x21, 0 + .dw 0x3740, 0xc03c, 0x377f, 0xc03c, 0x21, 0 + .dw 0x37c0, 0xc03c, 0x37ff, 0xc03c, 0x21, 0 + .dw 0x3840, 0xc03c, 0x387f, 0xc03c, 0x21, 0 + .dw 0x38c0, 0xc03c, 0x38ff, 0xc03c, 0x21, 0 + .dw 0x3940, 0xc03c, 0x397f, 0xc03c, 0x21, 0 + .dw 0x39c0, 0xc03c, 0x3fff, 0xc03c, 0x21, 0 + .dw 0x4040, 0xc03c, 0x407f, 0xc03c, 0x21, 0 + .dw 0x40c0, 0xc03c, 0x40ff, 0xc03c, 0x21, 0 + .dw 0x4140, 0xc03c, 0x417f, 0xc03c, 0x21, 0 + .dw 0x41c0, 0xc03c, 0x41ff, 0xc03c, 0x21, 0 + .dw 0x4240, 0xc03c, 0x427f, 0xc03c, 0x21, 0 + .dw 0x42c0, 0xc03c, 0x42ff, 0xc03c, 0x21, 0 + .dw 0x4340, 0xc03c, 0x437f, 0xc03c, 0x21, 0 + .dw 0x43c0, 0xc03c, 0x43ff, 0xc03c, 0x21, 0 + .dw 0x4440, 0xc03c, 0x447f, 0xc03c, 0x21, 0 + .dw 0x44c0, 0xc03c, 0x44ff, 0xc03c, 0x21, 0 + .dw 0x4540, 0xc03c, 0x457f, 0xc03c, 0x21, 0 + .dw 0x45c0, 0xc03c, 0x45ff, 0xc03c, 0x21, 0 + .dw 0x4640, 0xc03c, 0x467f, 0xc03c, 0x21, 0 + .dw 0x46c0, 0xc03c, 0x46ff, 0xc03c, 0x21, 0 + .dw 0x4740, 0xc03c, 0x477f, 0xc03c, 0x21, 0 + .dw 0x47c0, 0xc03c, 0x47ff, 0xc03c, 0x21, 0 + .dw 0x4840, 0xc03c, 0x487f, 0xc03c, 0x21, 0 + .dw 0x48c0, 0xc03c, 0x48ff, 0xc03c, 0x21, 0 + .dw 0x4940, 0xc03c, 0x497f, 0xc03c, 0x21, 0 + .dw 0x49c0, 0xc03c, 0x49ff, 0xc03c, 0x21, 0 + .dw 0x4a40, 0xc03c, 0x4a7f, 0xc03c, 0x21, 0 + .dw 0x4ac0, 0xc03c, 0x4aff, 0xc03c, 0x21, 0 + .dw 0x4b40, 0xc03c, 0x4b7f, 0xc03c, 0x21, 0 + .dw 0x4bc0, 0xc03c, 0x4bff, 0xc03c, 0x21, 0 + .dw 0x4c40, 0xc03c, 0x4c7f, 0xc03c, 0x21, 0 + .dw 0x4cc0, 0xc03c, 0x4cff, 0xc03c, 0x21, 0 + .dw 0x4d40, 0xc03c, 0x4d7f, 0xc03c, 0x21, 0 + .dw 0x4dc0, 0xc03c, 0x4dff, 0xc03c, 0x21, 0 + .dw 0x4e40, 0xc03c, 0x4e7f, 0xc03c, 0x21, 0 + .dw 0x4ec0, 0xc03c, 0x4eff, 0xc03c, 0x21, 0 + .dw 0x4f40, 0xc03c, 0x4f7f, 0xc03c, 0x21, 0 + .dw 0x4fc0, 0xc03c, 0x4fff, 0xc03c, 0x21, 0 + .dw 0x5040, 0xc03c, 0x507f, 0xc03c, 0x21, 0 + .dw 0x50c0, 0xc03c, 0x50ff, 0xc03c, 0x21, 0 + .dw 0x5140, 0xc03c, 0x517f, 0xc03c, 0x21, 0 + .dw 0x51c0, 0xc03c, 0x51ff, 0xc03c, 0x21, 0 + .dw 0x5240, 0xc03c, 0x527f, 0xc03c, 0x21, 0 + .dw 0x52c0, 0xc03c, 0x52ff, 0xc03c, 0x21, 0 + .dw 0x5340, 0xc03c, 0x537f, 0xc03c, 0x21, 0 + .dw 0x53c0, 0xc03c, 0x53ff, 0xc03c, 0x21, 0 + .dw 0x5440, 0xc03c, 0x547f, 0xc03c, 0x21, 0 + .dw 0x54c0, 0xc03c, 0x54ff, 0xc03c, 0x21, 0 + .dw 0x5540, 0xc03c, 0x557f, 0xc03c, 0x21, 0 + .dw 0x55c0, 0xc03c, 0x55ff, 0xc03c, 0x21, 0 + .dw 0x5640, 0xc03c, 0x567f, 0xc03c, 0x21, 0 + .dw 0x56c0, 0xc03c, 0x56ff, 0xc03c, 0x21, 0 + .dw 0x5740, 0xc03c, 0x577f, 0xc03c, 0x21, 0 + .dw 0x57c0, 0xc03c, 0x57ff, 0xc03c, 0x21, 0 + .dw 0x5840, 0xc03c, 0x587f, 0xc03c, 0x21, 0 + .dw 0x58c0, 0xc03c, 0x58ff, 0xc03c, 0x21, 0 + .dw 0x5940, 0xc03c, 0x597f, 0xc03c, 0x21, 0 + .dw 0x59c0, 0xc03c, 0x5fff, 0xc03c, 0x21, 0 + .dw 0x6040, 0xc03c, 0x607f, 0xc03c, 0x21, 0 + .dw 0x60c0, 0xc03c, 0x60ff, 0xc03c, 0x21, 0 + .dw 0x6140, 0xc03c, 0x617f, 0xc03c, 0x21, 0 + .dw 0x61c0, 0xc03c, 0x61ff, 0xc03c, 0x21, 0 + .dw 0x6240, 0xc03c, 0x627f, 0xc03c, 0x21, 0 + .dw 0x62c0, 0xc03c, 0x62ff, 0xc03c, 0x21, 0 + .dw 0x6340, 0xc03c, 0x637f, 0xc03c, 0x21, 0 + .dw 0x63c0, 0xc03c, 0x63ff, 0xc03c, 0x21, 0 + .dw 0x6440, 0xc03c, 0x647f, 0xc03c, 0x21, 0 + .dw 0x64c0, 0xc03c, 0x64ff, 0xc03c, 0x21, 0 + .dw 0x6540, 0xc03c, 0x657f, 0xc03c, 0x21, 0 + .dw 0x65c0, 0xc03c, 0x65ff, 0xc03c, 0x21, 0 + .dw 0x6640, 0xc03c, 0x667f, 0xc03c, 0x21, 0 + .dw 0x66c0, 0xc03c, 0x66ff, 0xc03c, 0x21, 0 + .dw 0x6740, 0xc03c, 0x677f, 0xc03c, 0x21, 0 + .dw 0x67c0, 0xc03c, 0x67ff, 0xc03c, 0x21, 0 + .dw 0x6840, 0xc03c, 0x687f, 0xc03c, 0x21, 0 + .dw 0x68c0, 0xc03c, 0x68ff, 0xc03c, 0x21, 0 + .dw 0x6940, 0xc03c, 0x697f, 0xc03c, 0x21, 0 + .dw 0x69c0, 0xc03c, 0x69ff, 0xc03c, 0x21, 0 + .dw 0x6a40, 0xc03c, 0x6a7f, 0xc03c, 0x21, 0 + .dw 0x6ac0, 0xc03c, 0x6aff, 0xc03c, 0x21, 0 + .dw 0x6b40, 0xc03c, 0x6b7f, 0xc03c, 0x21, 0 + .dw 0x6bc0, 0xc03c, 0x6bff, 0xc03c, 0x21, 0 + .dw 0x6c40, 0xc03c, 0x6c7f, 0xc03c, 0x21, 0 + .dw 0x6cc0, 0xc03c, 0x6cff, 0xc03c, 0x21, 0 + .dw 0x6d40, 0xc03c, 0x6d7f, 0xc03c, 0x21, 0 + .dw 0x6dc0, 0xc03c, 0x6dff, 0xc03c, 0x21, 0 + .dw 0x6e40, 0xc03c, 0x6e7f, 0xc03c, 0x21, 0 + .dw 0x6ec0, 0xc03c, 0x6eff, 0xc03c, 0x21, 0 + .dw 0x6f40, 0xc03c, 0x6f7f, 0xc03c, 0x21, 0 + .dw 0x6fc0, 0xc03c, 0x6fff, 0xc03c, 0x21, 0 + .dw 0x7040, 0xc03c, 0x707f, 0xc03c, 0x21, 0 + .dw 0x70c0, 0xc03c, 0x70ff, 0xc03c, 0x21, 0 + .dw 0x7140, 0xc03c, 0x717f, 0xc03c, 0x21, 0 + .dw 0x71c0, 0xc03c, 0x71ff, 0xc03c, 0x21, 0 + .dw 0x7240, 0xc03c, 0x727f, 0xc03c, 0x21, 0 + .dw 0x72c0, 0xc03c, 0x72ff, 0xc03c, 0x21, 0 + .dw 0x7340, 0xc03c, 0x737f, 0xc03c, 0x21, 0 + .dw 0x73c0, 0xc03c, 0x73ff, 0xc03c, 0x21, 0 + .dw 0x7440, 0xc03c, 0x747f, 0xc03c, 0x21, 0 + .dw 0x74c0, 0xc03c, 0x74ff, 0xc03c, 0x21, 0 + .dw 0x7540, 0xc03c, 0x757f, 0xc03c, 0x21, 0 + .dw 0x75c0, 0xc03c, 0x75ff, 0xc03c, 0x21, 0 + .dw 0x7640, 0xc03c, 0x767f, 0xc03c, 0x21, 0 + .dw 0x76c0, 0xc03c, 0x76ff, 0xc03c, 0x21, 0 + .dw 0x7740, 0xc03c, 0x777f, 0xc03c, 0x21, 0 + .dw 0x77c0, 0xc03c, 0x77ff, 0xc03c, 0x21, 0 + .dw 0x7840, 0xc03c, 0x787f, 0xc03c, 0x21, 0 + .dw 0x78c0, 0xc03c, 0x78ff, 0xc03c, 0x21, 0 + .dw 0x7940, 0xc03c, 0x797f, 0xc03c, 0x21, 0 + .dw 0x79c0, 0xc03c, 0x7fff, 0xc03c, 0x21, 0 + .dw 0x8040, 0xc03c, 0x807f, 0xc03c, 0x21, 0 + .dw 0x80c0, 0xc03c, 0x80ff, 0xc03c, 0x21, 0 + .dw 0x8140, 0xc03c, 0x817f, 0xc03c, 0x21, 0 + .dw 0x81c0, 0xc03c, 0x81ff, 0xc03c, 0x21, 0 + .dw 0x8240, 0xc03c, 0x827f, 0xc03c, 0x21, 0 + .dw 0x82c0, 0xc03c, 0x82ff, 0xc03c, 0x21, 0 + .dw 0x8340, 0xc03c, 0x837f, 0xc03c, 0x21, 0 + .dw 0x83c0, 0xc03c, 0x83ff, 0xc03c, 0x21, 0 + .dw 0x8440, 0xc03c, 0x847f, 0xc03c, 0x21, 0 + .dw 0x84c0, 0xc03c, 0x84ff, 0xc03c, 0x21, 0 + .dw 0x8540, 0xc03c, 0x857f, 0xc03c, 0x21, 0 + .dw 0x85c0, 0xc03c, 0x85ff, 0xc03c, 0x21, 0 + .dw 0x8640, 0xc03c, 0x867f, 0xc03c, 0x21, 0 + .dw 0x86c0, 0xc03c, 0x86ff, 0xc03c, 0x21, 0 + .dw 0x8740, 0xc03c, 0x877f, 0xc03c, 0x21, 0 + .dw 0x87c0, 0xc03c, 0x87ff, 0xc03c, 0x21, 0 + .dw 0x8840, 0xc03c, 0x887f, 0xc03c, 0x21, 0 + .dw 0x88c0, 0xc03c, 0x88ff, 0xc03c, 0x21, 0 + .dw 0x8940, 0xc03c, 0x897f, 0xc03c, 0x21, 0 + .dw 0x89c0, 0xc03c, 0x89ff, 0xc03c, 0x21, 0 + .dw 0x8a40, 0xc03c, 0x8a7f, 0xc03c, 0x21, 0 + .dw 0x8ac0, 0xc03c, 0x8aff, 0xc03c, 0x21, 0 + .dw 0x8b40, 0xc03c, 0x8b7f, 0xc03c, 0x21, 0 + .dw 0x8bc0, 0xc03c, 0x8bff, 0xc03c, 0x21, 0 + .dw 0x8c40, 0xc03c, 0x8c7f, 0xc03c, 0x21, 0 + .dw 0x8cc0, 0xc03c, 0x8cff, 0xc03c, 0x21, 0 + .dw 0x8d40, 0xc03c, 0x8d7f, 0xc03c, 0x21, 0 + .dw 0x8dc0, 0xc03c, 0x8dff, 0xc03c, 0x21, 0 + .dw 0x8e40, 0xc03c, 0x8e7f, 0xc03c, 0x21, 0 + .dw 0x8ec0, 0xc03c, 0x8eff, 0xc03c, 0x21, 0 + .dw 0x8f40, 0xc03c, 0x8f7f, 0xc03c, 0x21, 0 + .dw 0x8fc0, 0xc03c, 0x8fff, 0xc03c, 0x21, 0 + .dw 0x9040, 0xc03c, 0x907f, 0xc03c, 0x21, 0 + .dw 0x90c0, 0xc03c, 0x90ff, 0xc03c, 0x21, 0 + .dw 0x9140, 0xc03c, 0x917f, 0xc03c, 0x21, 0 + .dw 0x91c0, 0xc03c, 0x91ff, 0xc03c, 0x21, 0 + .dw 0x9240, 0xc03c, 0x927f, 0xc03c, 0x21, 0 + .dw 0x92c0, 0xc03c, 0x92ff, 0xc03c, 0x21, 0 + .dw 0x9340, 0xc03c, 0x937f, 0xc03c, 0x21, 0 + .dw 0x93c0, 0xc03c, 0x93ff, 0xc03c, 0x21, 0 + .dw 0x9440, 0xc03c, 0x947f, 0xc03c, 0x21, 0 + .dw 0x94c0, 0xc03c, 0x94ff, 0xc03c, 0x21, 0 + .dw 0x9540, 0xc03c, 0x957f, 0xc03c, 0x21, 0 + .dw 0x95c0, 0xc03c, 0x95ff, 0xc03c, 0x21, 0 + .dw 0x9640, 0xc03c, 0x967f, 0xc03c, 0x21, 0 + .dw 0x96c0, 0xc03c, 0x96ff, 0xc03c, 0x21, 0 + .dw 0x9740, 0xc03c, 0x977f, 0xc03c, 0x21, 0 + .dw 0x97c0, 0xc03c, 0x97ff, 0xc03c, 0x21, 0 + .dw 0x9840, 0xc03c, 0x987f, 0xc03c, 0x21, 0 + .dw 0x98c0, 0xc03c, 0x98ff, 0xc03c, 0x21, 0 + .dw 0x9940, 0xc03c, 0x997f, 0xc03c, 0x21, 0 + .dw 0x99c0, 0xc03c, 0x9fff, 0xc03c, 0x21, 0 + .dw 0xa040, 0xc03c, 0xa07f, 0xc03c, 0x21, 0 + .dw 0xa0c0, 0xc03c, 0xa0ff, 0xc03c, 0x21, 0 + .dw 0xa140, 0xc03c, 0xa17f, 0xc03c, 0x21, 0 + .dw 0xa1c0, 0xc03c, 0xa1ff, 0xc03c, 0x21, 0 + .dw 0xa240, 0xc03c, 0xa27f, 0xc03c, 0x21, 0 + .dw 0xa2c0, 0xc03c, 0xa2ff, 0xc03c, 0x21, 0 + .dw 0xa340, 0xc03c, 0xa37f, 0xc03c, 0x21, 0 + .dw 0xa3c0, 0xc03c, 0xa3ff, 0xc03c, 0x21, 0 + .dw 0xa440, 0xc03c, 0xa47f, 0xc03c, 0x21, 0 + .dw 0xa4c0, 0xc03c, 0xa4ff, 0xc03c, 0x21, 0 + .dw 0xa540, 0xc03c, 0xa57f, 0xc03c, 0x21, 0 + .dw 0xa5c0, 0xc03c, 0xa5ff, 0xc03c, 0x21, 0 + .dw 0xa640, 0xc03c, 0xa67f, 0xc03c, 0x21, 0 + .dw 0xa6c0, 0xc03c, 0xa6ff, 0xc03c, 0x21, 0 + .dw 0xa740, 0xc03c, 0xa77f, 0xc03c, 0x21, 0 + .dw 0xa7c0, 0xc03c, 0xa7ff, 0xc03c, 0x21, 0 + .dw 0xa840, 0xc03c, 0xa87f, 0xc03c, 0x21, 0 + .dw 0xa8c0, 0xc03c, 0xa8ff, 0xc03c, 0x21, 0 + .dw 0xa940, 0xc03c, 0xa97f, 0xc03c, 0x21, 0 + .dw 0xa9c0, 0xc03c, 0xa9ff, 0xc03c, 0x21, 0 + .dw 0xaa40, 0xc03c, 0xaa7f, 0xc03c, 0x21, 0 + .dw 0xaac0, 0xc03c, 0xaaff, 0xc03c, 0x21, 0 + .dw 0xab40, 0xc03c, 0xab7f, 0xc03c, 0x21, 0 + .dw 0xabc0, 0xc03c, 0xabff, 0xc03c, 0x21, 0 + .dw 0xac40, 0xc03c, 0xac7f, 0xc03c, 0x21, 0 + .dw 0xacc0, 0xc03c, 0xacff, 0xc03c, 0x21, 0 + .dw 0xad40, 0xc03c, 0xad7f, 0xc03c, 0x21, 0 + .dw 0xadc0, 0xc03c, 0xadff, 0xc03c, 0x21, 0 + .dw 0xae40, 0xc03c, 0xae7f, 0xc03c, 0x21, 0 + .dw 0xaec0, 0xc03c, 0xaeff, 0xc03c, 0x21, 0 + .dw 0xaf40, 0xc03c, 0xaf7f, 0xc03c, 0x21, 0 + .dw 0xafc0, 0xc03c, 0xafff, 0xc03c, 0x21, 0 + .dw 0xb040, 0xc03c, 0xb07f, 0xc03c, 0x21, 0 + .dw 0xb0c0, 0xc03c, 0xb0ff, 0xc03c, 0x21, 0 + .dw 0xb140, 0xc03c, 0xb17f, 0xc03c, 0x21, 0 + .dw 0xb1c0, 0xc03c, 0xb1ff, 0xc03c, 0x21, 0 + .dw 0xb240, 0xc03c, 0xb27f, 0xc03c, 0x21, 0 + .dw 0xb2c0, 0xc03c, 0xb2ff, 0xc03c, 0x21, 0 + .dw 0xb340, 0xc03c, 0xb37f, 0xc03c, 0x21, 0 + .dw 0xb3c0, 0xc03c, 0xb3ff, 0xc03c, 0x21, 0 + .dw 0xb440, 0xc03c, 0xb47f, 0xc03c, 0x21, 0 + .dw 0xb4c0, 0xc03c, 0xb4ff, 0xc03c, 0x21, 0 + .dw 0xb540, 0xc03c, 0xb57f, 0xc03c, 0x21, 0 + .dw 0xb5c0, 0xc03c, 0xb5ff, 0xc03c, 0x21, 0 + .dw 0xb640, 0xc03c, 0xb67f, 0xc03c, 0x21, 0 + .dw 0xb6c0, 0xc03c, 0xb6ff, 0xc03c, 0x21, 0 + .dw 0xb740, 0xc03c, 0xb77f, 0xc03c, 0x21, 0 + .dw 0xb7c0, 0xc03c, 0xb7ff, 0xc03c, 0x21, 0 + .dw 0xb840, 0xc03c, 0xb87f, 0xc03c, 0x21, 0 + .dw 0xb8c0, 0xc03c, 0xb8ff, 0xc03c, 0x21, 0 + .dw 0xb940, 0xc03c, 0xb97f, 0xc03c, 0x21, 0 + .dw 0xb9c0, 0xc03c, 0xbfff, 0xc03c, 0x21, 0 + .dw 0xc040, 0xc03c, 0xc07f, 0xc03c, 0x21, 0 + .dw 0xc0c0, 0xc03c, 0xc0ff, 0xc03c, 0x21, 0 + .dw 0xc140, 0xc03c, 0xc17f, 0xc03c, 0x21, 0 + .dw 0xc1c0, 0xc03c, 0xc1ff, 0xc03c, 0x21, 0 + .dw 0xc240, 0xc03c, 0xc27f, 0xc03c, 0x21, 0 + .dw 0xc2c0, 0xc03c, 0xc2ff, 0xc03c, 0x21, 0 + .dw 0xc340, 0xc03c, 0xc37f, 0xc03c, 0x21, 0 + .dw 0xc3c0, 0xc03c, 0xc3ff, 0xc03c, 0x21, 0 + .dw 0xc440, 0xc03c, 0xc47f, 0xc03c, 0x21, 0 + .dw 0xc4c0, 0xc03c, 0xc4ff, 0xc03c, 0x21, 0 + .dw 0xc540, 0xc03c, 0xc57f, 0xc03c, 0x21, 0 + .dw 0xc5c0, 0xc03c, 0xc5ff, 0xc03c, 0x21, 0 + .dw 0xc640, 0xc03c, 0xc67f, 0xc03c, 0x21, 0 + .dw 0xc6c0, 0xc03c, 0xc6ff, 0xc03c, 0x21, 0 + .dw 0xc740, 0xc03c, 0xc77f, 0xc03c, 0x21, 0 + .dw 0xc7c0, 0xc03c, 0xc7ff, 0xc03c, 0x21, 0 + .dw 0xc840, 0xc03c, 0xc87f, 0xc03c, 0x21, 0 + .dw 0xc8c0, 0xc03c, 0xc8ff, 0xc03c, 0x21, 0 + .dw 0xc940, 0xc03c, 0xc97f, 0xc03c, 0x21, 0 + .dw 0xc9c0, 0xc03c, 0xc9ff, 0xc03c, 0x21, 0 + .dw 0xca40, 0xc03c, 0xca7f, 0xc03c, 0x21, 0 + .dw 0xcac0, 0xc03c, 0xcaff, 0xc03c, 0x21, 0 + .dw 0xcb40, 0xc03c, 0xcb7f, 0xc03c, 0x21, 0 + .dw 0xcbc0, 0xc03c, 0xcbff, 0xc03c, 0x21, 0 + .dw 0xcc40, 0xc03c, 0xcc7f, 0xc03c, 0x21, 0 + .dw 0xccc0, 0xc03c, 0xccff, 0xc03c, 0x21, 0 + .dw 0xcd40, 0xc03c, 0xcd7f, 0xc03c, 0x21, 0 + .dw 0xcdc0, 0xc03c, 0xcdff, 0xc03c, 0x21, 0 + .dw 0xce40, 0xc03c, 0xce7f, 0xc03c, 0x21, 0 + .dw 0xcec0, 0xc03c, 0xceff, 0xc03c, 0x21, 0 + .dw 0xcf40, 0xc03c, 0xcf7f, 0xc03c, 0x21, 0 + .dw 0xcfc0, 0xc03c, 0xcfff, 0xc03c, 0x21, 0 + .dw 0xd040, 0xc03c, 0xd07f, 0xc03c, 0x21, 0 + .dw 0xd0c0, 0xc03c, 0xd0ff, 0xc03c, 0x21, 0 + .dw 0xd140, 0xc03c, 0xd17f, 0xc03c, 0x21, 0 + .dw 0xd1c0, 0xc03c, 0xd1ff, 0xc03c, 0x21, 0 + .dw 0xd240, 0xc03c, 0xd27f, 0xc03c, 0x21, 0 + .dw 0xd2c0, 0xc03c, 0xd2ff, 0xc03c, 0x21, 0 + .dw 0xd340, 0xc03c, 0xd37f, 0xc03c, 0x21, 0 + .dw 0xd3c0, 0xc03c, 0xd3ff, 0xc03c, 0x21, 0 + .dw 0xd440, 0xc03c, 0xd47f, 0xc03c, 0x21, 0 + .dw 0xd4c0, 0xc03c, 0xd4ff, 0xc03c, 0x21, 0 + .dw 0xd540, 0xc03c, 0xd57f, 0xc03c, 0x21, 0 + .dw 0xd5c0, 0xc03c, 0xd5ff, 0xc03c, 0x21, 0 + .dw 0xd640, 0xc03c, 0xd67f, 0xc03c, 0x21, 0 + .dw 0xd6c0, 0xc03c, 0xd6ff, 0xc03c, 0x21, 0 + .dw 0xd740, 0xc03c, 0xd77f, 0xc03c, 0x21, 0 + .dw 0xd7c0, 0xc03c, 0xd7ff, 0xc03c, 0x21, 0 + .dw 0xd840, 0xc03c, 0xd87f, 0xc03c, 0x21, 0 + .dw 0xd8c0, 0xc03c, 0xd8ff, 0xc03c, 0x21, 0 + .dw 0xd940, 0xc03c, 0xd97f, 0xc03c, 0x21, 0 + .dw 0xd9c0, 0xc03c, 0xdfff, 0xc03c, 0x21, 0 + .dw 0xe040, 0xc03c, 0xe07f, 0xc03c, 0x21, 0 + .dw 0xe0c0, 0xc03c, 0xe0ff, 0xc03c, 0x21, 0 + .dw 0xe140, 0xc03c, 0xe17f, 0xc03c, 0x21, 0 + .dw 0xe1c0, 0xc03c, 0xe1ff, 0xc03c, 0x21, 0 + .dw 0xe240, 0xc03c, 0xe27f, 0xc03c, 0x21, 0 + .dw 0xe2c0, 0xc03c, 0xe2ff, 0xc03c, 0x21, 0 + .dw 0xe340, 0xc03c, 0xe37f, 0xc03c, 0x21, 0 + .dw 0xe3c0, 0xc03c, 0xe3ff, 0xc03c, 0x21, 0 + .dw 0xe440, 0xc03c, 0xe47f, 0xc03c, 0x21, 0 + .dw 0xe4c0, 0xc03c, 0xe4ff, 0xc03c, 0x21, 0 + .dw 0xe540, 0xc03c, 0xe57f, 0xc03c, 0x21, 0 + .dw 0xe5c0, 0xc03c, 0xe5ff, 0xc03c, 0x21, 0 + .dw 0xe640, 0xc03c, 0xe67f, 0xc03c, 0x21, 0 + .dw 0xe6c0, 0xc03c, 0xe6ff, 0xc03c, 0x21, 0 + .dw 0xe740, 0xc03c, 0xe77f, 0xc03c, 0x21, 0 + .dw 0xe7c0, 0xc03c, 0xe7ff, 0xc03c, 0x21, 0 + .dw 0xe840, 0xc03c, 0xe87f, 0xc03c, 0x21, 0 + .dw 0xe8c0, 0xc03c, 0xe8ff, 0xc03c, 0x21, 0 + .dw 0xe940, 0xc03c, 0xe97f, 0xc03c, 0x21, 0 + .dw 0xe9c0, 0xc03c, 0xe9ff, 0xc03c, 0x21, 0 + .dw 0xea40, 0xc03c, 0xea7f, 0xc03c, 0x21, 0 + .dw 0xeac0, 0xc03c, 0xeaff, 0xc03c, 0x21, 0 + .dw 0xeb40, 0xc03c, 0xeb7f, 0xc03c, 0x21, 0 + .dw 0xebc0, 0xc03c, 0xebff, 0xc03c, 0x21, 0 + .dw 0xec40, 0xc03c, 0xec7f, 0xc03c, 0x21, 0 + .dw 0xecc0, 0xc03c, 0xecff, 0xc03c, 0x21, 0 + .dw 0xed40, 0xc03c, 0xed7f, 0xc03c, 0x21, 0 + .dw 0xedc0, 0xc03c, 0xedff, 0xc03c, 0x21, 0 + .dw 0xee40, 0xc03c, 0xee7f, 0xc03c, 0x21, 0 + .dw 0xeec0, 0xc03c, 0xeeff, 0xc03c, 0x21, 0 + .dw 0xef40, 0xc03c, 0xef7f, 0xc03c, 0x21, 0 + .dw 0xefc0, 0xc03c, 0xefff, 0xc03c, 0x21, 0 + .dw 0xf040, 0xc03c, 0xf07f, 0xc03c, 0x21, 0 + .dw 0xf0c0, 0xc03c, 0xf0ff, 0xc03c, 0x21, 0 + .dw 0xf140, 0xc03c, 0xf17f, 0xc03c, 0x21, 0 + .dw 0xf1c0, 0xc03c, 0xf1ff, 0xc03c, 0x21, 0 + .dw 0xf240, 0xc03c, 0xf27f, 0xc03c, 0x21, 0 + .dw 0xf2c0, 0xc03c, 0xf2ff, 0xc03c, 0x21, 0 + .dw 0xf340, 0xc03c, 0xf37f, 0xc03c, 0x21, 0 + .dw 0xf3c0, 0xc03c, 0xf3ff, 0xc03c, 0x21, 0 + .dw 0xf440, 0xc03c, 0xf47f, 0xc03c, 0x21, 0 + .dw 0xf4c0, 0xc03c, 0xf4ff, 0xc03c, 0x21, 0 + .dw 0xf540, 0xc03c, 0xf57f, 0xc03c, 0x21, 0 + .dw 0xf5c0, 0xc03c, 0xf5ff, 0xc03c, 0x21, 0 + .dw 0xf640, 0xc03c, 0xf67f, 0xc03c, 0x21, 0 + .dw 0xf6c0, 0xc03c, 0xf6ff, 0xc03c, 0x21, 0 + .dw 0xf740, 0xc03c, 0xf77f, 0xc03c, 0x21, 0 + .dw 0xf7c0, 0xc03c, 0xf7ff, 0xc03c, 0x21, 0 + .dw 0xf840, 0xc03c, 0xf87f, 0xc03c, 0x21, 0 + .dw 0xf8c0, 0xc03c, 0xf8ff, 0xc03c, 0x21, 0 + .dw 0xf940, 0xc03c, 0xf97f, 0xc03c, 0x21, 0 + .dw 0xf9c0, 0xc03c, 0xffff, 0xc03c, 0x21, 0 + .dw 0x0040, 0xc03d, 0x007f, 0xc03d, 0x21, 0 + .dw 0x00c0, 0xc03d, 0x00ff, 0xc03d, 0x21, 0 + .dw 0x0140, 0xc03d, 0x017f, 0xc03d, 0x21, 0 + .dw 0x01c0, 0xc03d, 0x01ff, 0xc03d, 0x21, 0 + .dw 0x0240, 0xc03d, 0x027f, 0xc03d, 0x21, 0 + .dw 0x02c0, 0xc03d, 0x02ff, 0xc03d, 0x21, 0 + .dw 0x0340, 0xc03d, 0x037f, 0xc03d, 0x21, 0 + .dw 0x03c0, 0xc03d, 0x03ff, 0xc03d, 0x21, 0 + .dw 0x0440, 0xc03d, 0x047f, 0xc03d, 0x21, 0 + .dw 0x04c0, 0xc03d, 0x04ff, 0xc03d, 0x21, 0 + .dw 0x0540, 0xc03d, 0x057f, 0xc03d, 0x21, 0 + .dw 0x05c0, 0xc03d, 0x05ff, 0xc03d, 0x21, 0 + .dw 0x0640, 0xc03d, 0x067f, 0xc03d, 0x21, 0 + .dw 0x06c0, 0xc03d, 0x06ff, 0xc03d, 0x21, 0 + .dw 0x0740, 0xc03d, 0x077f, 0xc03d, 0x21, 0 + .dw 0x07c0, 0xc03d, 0x07ff, 0xc03d, 0x21, 0 + .dw 0x0840, 0xc03d, 0x087f, 0xc03d, 0x21, 0 + .dw 0x08c0, 0xc03d, 0x08ff, 0xc03d, 0x21, 0 + .dw 0x0940, 0xc03d, 0x097f, 0xc03d, 0x21, 0 + .dw 0x09c0, 0xc03d, 0x09ff, 0xc03d, 0x21, 0 + .dw 0x0a40, 0xc03d, 0x0a7f, 0xc03d, 0x21, 0 + .dw 0x0ac0, 0xc03d, 0x0aff, 0xc03d, 0x21, 0 + .dw 0x0b40, 0xc03d, 0x0b7f, 0xc03d, 0x21, 0 + .dw 0x0bc0, 0xc03d, 0x0bff, 0xc03d, 0x21, 0 + .dw 0x0c40, 0xc03d, 0x0c7f, 0xc03d, 0x21, 0 + .dw 0x0cc0, 0xc03d, 0x0cff, 0xc03d, 0x21, 0 + .dw 0x0d40, 0xc03d, 0x0d7f, 0xc03d, 0x21, 0 + .dw 0x0dc0, 0xc03d, 0x0dff, 0xc03d, 0x21, 0 + .dw 0x0e40, 0xc03d, 0x0e7f, 0xc03d, 0x21, 0 + .dw 0x0ec0, 0xc03d, 0x0eff, 0xc03d, 0x21, 0 + .dw 0x0f40, 0xc03d, 0x0f7f, 0xc03d, 0x21, 0 + .dw 0x0fc0, 0xc03d, 0x0fff, 0xc03d, 0x21, 0 + .dw 0x1040, 0xc03d, 0x107f, 0xc03d, 0x21, 0 + .dw 0x10c0, 0xc03d, 0x10ff, 0xc03d, 0x21, 0 + .dw 0x1140, 0xc03d, 0x117f, 0xc03d, 0x21, 0 + .dw 0x11c0, 0xc03d, 0x11ff, 0xc03d, 0x21, 0 + .dw 0x1240, 0xc03d, 0x127f, 0xc03d, 0x21, 0 + .dw 0x12c0, 0xc03d, 0x12ff, 0xc03d, 0x21, 0 + .dw 0x1340, 0xc03d, 0x137f, 0xc03d, 0x21, 0 + .dw 0x13c0, 0xc03d, 0x13ff, 0xc03d, 0x21, 0 + .dw 0x1440, 0xc03d, 0x147f, 0xc03d, 0x21, 0 + .dw 0x14c0, 0xc03d, 0x14ff, 0xc03d, 0x21, 0 + .dw 0x1540, 0xc03d, 0x157f, 0xc03d, 0x21, 0 + .dw 0x15c0, 0xc03d, 0x15ff, 0xc03d, 0x21, 0 + .dw 0x1640, 0xc03d, 0x167f, 0xc03d, 0x21, 0 + .dw 0x16c0, 0xc03d, 0x16ff, 0xc03d, 0x21, 0 + .dw 0x1740, 0xc03d, 0x177f, 0xc03d, 0x21, 0 + .dw 0x17c0, 0xc03d, 0x17ff, 0xc03d, 0x21, 0 + .dw 0x1840, 0xc03d, 0x187f, 0xc03d, 0x21, 0 + .dw 0x18c0, 0xc03d, 0x18ff, 0xc03d, 0x21, 0 + .dw 0x1940, 0xc03d, 0x197f, 0xc03d, 0x21, 0 + .dw 0x19c0, 0xc03d, 0x1fff, 0xc03d, 0x21, 0 + .dw 0x2040, 0xc03d, 0x207f, 0xc03d, 0x21, 0 + .dw 0x20c0, 0xc03d, 0x20ff, 0xc03d, 0x21, 0 + .dw 0x2140, 0xc03d, 0x217f, 0xc03d, 0x21, 0 + .dw 0x21c0, 0xc03d, 0x21ff, 0xc03d, 0x21, 0 + .dw 0x2240, 0xc03d, 0x227f, 0xc03d, 0x21, 0 + .dw 0x22c0, 0xc03d, 0x22ff, 0xc03d, 0x21, 0 + .dw 0x2340, 0xc03d, 0x237f, 0xc03d, 0x21, 0 + .dw 0x23c0, 0xc03d, 0x23ff, 0xc03d, 0x21, 0 + .dw 0x2440, 0xc03d, 0x247f, 0xc03d, 0x21, 0 + .dw 0x24c0, 0xc03d, 0x24ff, 0xc03d, 0x21, 0 + .dw 0x2540, 0xc03d, 0x257f, 0xc03d, 0x21, 0 + .dw 0x25c0, 0xc03d, 0x25ff, 0xc03d, 0x21, 0 + .dw 0x2640, 0xc03d, 0x267f, 0xc03d, 0x21, 0 + .dw 0x26c0, 0xc03d, 0x26ff, 0xc03d, 0x21, 0 + .dw 0x2740, 0xc03d, 0x277f, 0xc03d, 0x21, 0 + .dw 0x27c0, 0xc03d, 0x27ff, 0xc03d, 0x21, 0 + .dw 0x2840, 0xc03d, 0x287f, 0xc03d, 0x21, 0 + .dw 0x28c0, 0xc03d, 0x28ff, 0xc03d, 0x21, 0 + .dw 0x2940, 0xc03d, 0x297f, 0xc03d, 0x21, 0 + .dw 0x29c0, 0xc03d, 0x29ff, 0xc03d, 0x21, 0 + .dw 0x2a40, 0xc03d, 0x2a7f, 0xc03d, 0x21, 0 + .dw 0x2ac0, 0xc03d, 0x2aff, 0xc03d, 0x21, 0 + .dw 0x2b40, 0xc03d, 0x2b7f, 0xc03d, 0x21, 0 + .dw 0x2bc0, 0xc03d, 0x2bff, 0xc03d, 0x21, 0 + .dw 0x2c40, 0xc03d, 0x2c7f, 0xc03d, 0x21, 0 + .dw 0x2cc0, 0xc03d, 0x2cff, 0xc03d, 0x21, 0 + .dw 0x2d40, 0xc03d, 0x2d7f, 0xc03d, 0x21, 0 + .dw 0x2dc0, 0xc03d, 0x2dff, 0xc03d, 0x21, 0 + .dw 0x2e40, 0xc03d, 0x2e7f, 0xc03d, 0x21, 0 + .dw 0x2ec0, 0xc03d, 0x2eff, 0xc03d, 0x21, 0 + .dw 0x2f40, 0xc03d, 0x2f7f, 0xc03d, 0x21, 0 + .dw 0x2fc0, 0xc03d, 0x2fff, 0xc03d, 0x21, 0 + .dw 0x3040, 0xc03d, 0x307f, 0xc03d, 0x21, 0 + .dw 0x30c0, 0xc03d, 0x30ff, 0xc03d, 0x21, 0 + .dw 0x3140, 0xc03d, 0x317f, 0xc03d, 0x21, 0 + .dw 0x31c0, 0xc03d, 0x31ff, 0xc03d, 0x21, 0 + .dw 0x3240, 0xc03d, 0x327f, 0xc03d, 0x21, 0 + .dw 0x32c0, 0xc03d, 0x32ff, 0xc03d, 0x21, 0 + .dw 0x3340, 0xc03d, 0x337f, 0xc03d, 0x21, 0 + .dw 0x33c0, 0xc03d, 0x33ff, 0xc03d, 0x21, 0 + .dw 0x3440, 0xc03d, 0x347f, 0xc03d, 0x21, 0 + .dw 0x34c0, 0xc03d, 0x34ff, 0xc03d, 0x21, 0 + .dw 0x3540, 0xc03d, 0x357f, 0xc03d, 0x21, 0 + .dw 0x35c0, 0xc03d, 0x35ff, 0xc03d, 0x21, 0 + .dw 0x3640, 0xc03d, 0x367f, 0xc03d, 0x21, 0 + .dw 0x36c0, 0xc03d, 0x36ff, 0xc03d, 0x21, 0 + .dw 0x3740, 0xc03d, 0x377f, 0xc03d, 0x21, 0 + .dw 0x37c0, 0xc03d, 0x37ff, 0xc03d, 0x21, 0 + .dw 0x3840, 0xc03d, 0x387f, 0xc03d, 0x21, 0 + .dw 0x38c0, 0xc03d, 0x38ff, 0xc03d, 0x21, 0 + .dw 0x3940, 0xc03d, 0x397f, 0xc03d, 0x21, 0 + .dw 0x39c0, 0xc03d, 0x3fff, 0xc03d, 0x21, 0 + .dw 0x4040, 0xc03d, 0x407f, 0xc03d, 0x21, 0 + .dw 0x40c0, 0xc03d, 0x40ff, 0xc03d, 0x21, 0 + .dw 0x4140, 0xc03d, 0x417f, 0xc03d, 0x21, 0 + .dw 0x41c0, 0xc03d, 0x41ff, 0xc03d, 0x21, 0 + .dw 0x4240, 0xc03d, 0x427f, 0xc03d, 0x21, 0 + .dw 0x42c0, 0xc03d, 0x42ff, 0xc03d, 0x21, 0 + .dw 0x4340, 0xc03d, 0x437f, 0xc03d, 0x21, 0 + .dw 0x43c0, 0xc03d, 0x43ff, 0xc03d, 0x21, 0 + .dw 0x4440, 0xc03d, 0x447f, 0xc03d, 0x21, 0 + .dw 0x44c0, 0xc03d, 0x44ff, 0xc03d, 0x21, 0 + .dw 0x4540, 0xc03d, 0x457f, 0xc03d, 0x21, 0 + .dw 0x45c0, 0xc03d, 0x45ff, 0xc03d, 0x21, 0 + .dw 0x4640, 0xc03d, 0x467f, 0xc03d, 0x21, 0 + .dw 0x46c0, 0xc03d, 0x46ff, 0xc03d, 0x21, 0 + .dw 0x4740, 0xc03d, 0x477f, 0xc03d, 0x21, 0 + .dw 0x47c0, 0xc03d, 0x47ff, 0xc03d, 0x21, 0 + .dw 0x4840, 0xc03d, 0x487f, 0xc03d, 0x21, 0 + .dw 0x48c0, 0xc03d, 0x48ff, 0xc03d, 0x21, 0 + .dw 0x4940, 0xc03d, 0x497f, 0xc03d, 0x21, 0 + .dw 0x49c0, 0xc03d, 0x49ff, 0xc03d, 0x21, 0 + .dw 0x4a40, 0xc03d, 0x4a7f, 0xc03d, 0x21, 0 + .dw 0x4ac0, 0xc03d, 0x4aff, 0xc03d, 0x21, 0 + .dw 0x4b40, 0xc03d, 0x4b7f, 0xc03d, 0x21, 0 + .dw 0x4bc0, 0xc03d, 0x4bff, 0xc03d, 0x21, 0 + .dw 0x4c40, 0xc03d, 0x4c7f, 0xc03d, 0x21, 0 + .dw 0x4cc0, 0xc03d, 0x4cff, 0xc03d, 0x21, 0 + .dw 0x4d40, 0xc03d, 0x4d7f, 0xc03d, 0x21, 0 + .dw 0x4dc0, 0xc03d, 0x4dff, 0xc03d, 0x21, 0 + .dw 0x4e40, 0xc03d, 0x4e7f, 0xc03d, 0x21, 0 + .dw 0x4ec0, 0xc03d, 0x4eff, 0xc03d, 0x21, 0 + .dw 0x4f40, 0xc03d, 0x4f7f, 0xc03d, 0x21, 0 + .dw 0x4fc0, 0xc03d, 0x4fff, 0xc03d, 0x21, 0 + .dw 0x5040, 0xc03d, 0x507f, 0xc03d, 0x21, 0 + .dw 0x50c0, 0xc03d, 0x50ff, 0xc03d, 0x21, 0 + .dw 0x5140, 0xc03d, 0x517f, 0xc03d, 0x21, 0 + .dw 0x51c0, 0xc03d, 0x51ff, 0xc03d, 0x21, 0 + .dw 0x5240, 0xc03d, 0x527f, 0xc03d, 0x21, 0 + .dw 0x52c0, 0xc03d, 0x52ff, 0xc03d, 0x21, 0 + .dw 0x5340, 0xc03d, 0x537f, 0xc03d, 0x21, 0 + .dw 0x53c0, 0xc03d, 0x53ff, 0xc03d, 0x21, 0 + .dw 0x5440, 0xc03d, 0x547f, 0xc03d, 0x21, 0 + .dw 0x54c0, 0xc03d, 0x54ff, 0xc03d, 0x21, 0 + .dw 0x5540, 0xc03d, 0x557f, 0xc03d, 0x21, 0 + .dw 0x55c0, 0xc03d, 0x55ff, 0xc03d, 0x21, 0 + .dw 0x5640, 0xc03d, 0x567f, 0xc03d, 0x21, 0 + .dw 0x56c0, 0xc03d, 0x56ff, 0xc03d, 0x21, 0 + .dw 0x5740, 0xc03d, 0x577f, 0xc03d, 0x21, 0 + .dw 0x57c0, 0xc03d, 0x57ff, 0xc03d, 0x21, 0 + .dw 0x5840, 0xc03d, 0x587f, 0xc03d, 0x21, 0 + .dw 0x58c0, 0xc03d, 0x58ff, 0xc03d, 0x21, 0 + .dw 0x5940, 0xc03d, 0x597f, 0xc03d, 0x21, 0 + .dw 0x59c0, 0xc03d, 0x5fff, 0xc03d, 0x21, 0 + .dw 0x6040, 0xc03d, 0x607f, 0xc03d, 0x21, 0 + .dw 0x60c0, 0xc03d, 0x60ff, 0xc03d, 0x21, 0 + .dw 0x6140, 0xc03d, 0x617f, 0xc03d, 0x21, 0 + .dw 0x61c0, 0xc03d, 0x61ff, 0xc03d, 0x21, 0 + .dw 0x6240, 0xc03d, 0x627f, 0xc03d, 0x21, 0 + .dw 0x62c0, 0xc03d, 0x62ff, 0xc03d, 0x21, 0 + .dw 0x6340, 0xc03d, 0x637f, 0xc03d, 0x21, 0 + .dw 0x63c0, 0xc03d, 0x63ff, 0xc03d, 0x21, 0 + .dw 0x6440, 0xc03d, 0x647f, 0xc03d, 0x21, 0 + .dw 0x64c0, 0xc03d, 0x64ff, 0xc03d, 0x21, 0 + .dw 0x6540, 0xc03d, 0x657f, 0xc03d, 0x21, 0 + .dw 0x65c0, 0xc03d, 0x65ff, 0xc03d, 0x21, 0 + .dw 0x6640, 0xc03d, 0x667f, 0xc03d, 0x21, 0 + .dw 0x66c0, 0xc03d, 0x66ff, 0xc03d, 0x21, 0 + .dw 0x6740, 0xc03d, 0x677f, 0xc03d, 0x21, 0 + .dw 0x67c0, 0xc03d, 0x67ff, 0xc03d, 0x21, 0 + .dw 0x6840, 0xc03d, 0x687f, 0xc03d, 0x21, 0 + .dw 0x68c0, 0xc03d, 0x68ff, 0xc03d, 0x21, 0 + .dw 0x6940, 0xc03d, 0x697f, 0xc03d, 0x21, 0 + .dw 0x69c0, 0xc03d, 0x69ff, 0xc03d, 0x21, 0 + .dw 0x6a40, 0xc03d, 0x6a7f, 0xc03d, 0x21, 0 + .dw 0x6ac0, 0xc03d, 0x6aff, 0xc03d, 0x21, 0 + .dw 0x6b40, 0xc03d, 0x6b7f, 0xc03d, 0x21, 0 + .dw 0x6bc0, 0xc03d, 0x6bff, 0xc03d, 0x21, 0 + .dw 0x6c40, 0xc03d, 0x6c7f, 0xc03d, 0x21, 0 + .dw 0x6cc0, 0xc03d, 0x6cff, 0xc03d, 0x21, 0 + .dw 0x6d40, 0xc03d, 0x6d7f, 0xc03d, 0x21, 0 + .dw 0x6dc0, 0xc03d, 0x6dff, 0xc03d, 0x21, 0 + .dw 0x6e40, 0xc03d, 0x6e7f, 0xc03d, 0x21, 0 + .dw 0x6ec0, 0xc03d, 0x6eff, 0xc03d, 0x21, 0 + .dw 0x6f40, 0xc03d, 0x6f7f, 0xc03d, 0x21, 0 + .dw 0x6fc0, 0xc03d, 0x6fff, 0xc03d, 0x21, 0 + .dw 0x7040, 0xc03d, 0x707f, 0xc03d, 0x21, 0 + .dw 0x70c0, 0xc03d, 0x70ff, 0xc03d, 0x21, 0 + .dw 0x7140, 0xc03d, 0x717f, 0xc03d, 0x21, 0 + .dw 0x71c0, 0xc03d, 0x71ff, 0xc03d, 0x21, 0 + .dw 0x7240, 0xc03d, 0x727f, 0xc03d, 0x21, 0 + .dw 0x72c0, 0xc03d, 0x72ff, 0xc03d, 0x21, 0 + .dw 0x7340, 0xc03d, 0x737f, 0xc03d, 0x21, 0 + .dw 0x73c0, 0xc03d, 0x73ff, 0xc03d, 0x21, 0 + .dw 0x7440, 0xc03d, 0x747f, 0xc03d, 0x21, 0 + .dw 0x74c0, 0xc03d, 0x74ff, 0xc03d, 0x21, 0 + .dw 0x7540, 0xc03d, 0x757f, 0xc03d, 0x21, 0 + .dw 0x75c0, 0xc03d, 0x75ff, 0xc03d, 0x21, 0 + .dw 0x7640, 0xc03d, 0x767f, 0xc03d, 0x21, 0 + .dw 0x76c0, 0xc03d, 0x76ff, 0xc03d, 0x21, 0 + .dw 0x7740, 0xc03d, 0x777f, 0xc03d, 0x21, 0 + .dw 0x77c0, 0xc03d, 0x77ff, 0xc03d, 0x21, 0 + .dw 0x7840, 0xc03d, 0x787f, 0xc03d, 0x21, 0 + .dw 0x78c0, 0xc03d, 0x78ff, 0xc03d, 0x21, 0 + .dw 0x7940, 0xc03d, 0x797f, 0xc03d, 0x21, 0 + .dw 0x79c0, 0xc03d, 0x7fff, 0xc03d, 0x21, 0 + .dw 0x8040, 0xc03d, 0x807f, 0xc03d, 0x21, 0 + .dw 0x80c0, 0xc03d, 0x80ff, 0xc03d, 0x21, 0 + .dw 0x8140, 0xc03d, 0x817f, 0xc03d, 0x21, 0 + .dw 0x81c0, 0xc03d, 0x81ff, 0xc03d, 0x21, 0 + .dw 0x8240, 0xc03d, 0x827f, 0xc03d, 0x21, 0 + .dw 0x82c0, 0xc03d, 0x82ff, 0xc03d, 0x21, 0 + .dw 0x8340, 0xc03d, 0x837f, 0xc03d, 0x21, 0 + .dw 0x83c0, 0xc03d, 0x83ff, 0xc03d, 0x21, 0 + .dw 0x8440, 0xc03d, 0x847f, 0xc03d, 0x21, 0 + .dw 0x84c0, 0xc03d, 0x84ff, 0xc03d, 0x21, 0 + .dw 0x8540, 0xc03d, 0x857f, 0xc03d, 0x21, 0 + .dw 0x85c0, 0xc03d, 0x85ff, 0xc03d, 0x21, 0 + .dw 0x8640, 0xc03d, 0x867f, 0xc03d, 0x21, 0 + .dw 0x86c0, 0xc03d, 0x86ff, 0xc03d, 0x21, 0 + .dw 0x8740, 0xc03d, 0x877f, 0xc03d, 0x21, 0 + .dw 0x87c0, 0xc03d, 0x87ff, 0xc03d, 0x21, 0 + .dw 0x8840, 0xc03d, 0x887f, 0xc03d, 0x21, 0 + .dw 0x88c0, 0xc03d, 0x88ff, 0xc03d, 0x21, 0 + .dw 0x8940, 0xc03d, 0x897f, 0xc03d, 0x21, 0 + .dw 0x89c0, 0xc03d, 0x89ff, 0xc03d, 0x21, 0 + .dw 0x8a40, 0xc03d, 0x8a7f, 0xc03d, 0x21, 0 + .dw 0x8ac0, 0xc03d, 0x8aff, 0xc03d, 0x21, 0 + .dw 0x8b40, 0xc03d, 0x8b7f, 0xc03d, 0x21, 0 + .dw 0x8bc0, 0xc03d, 0x8bff, 0xc03d, 0x21, 0 + .dw 0x8c40, 0xc03d, 0x8c7f, 0xc03d, 0x21, 0 + .dw 0x8cc0, 0xc03d, 0x8cff, 0xc03d, 0x21, 0 + .dw 0x8d40, 0xc03d, 0x8d7f, 0xc03d, 0x21, 0 + .dw 0x8dc0, 0xc03d, 0x8dff, 0xc03d, 0x21, 0 + .dw 0x8e40, 0xc03d, 0x8e7f, 0xc03d, 0x21, 0 + .dw 0x8ec0, 0xc03d, 0x8eff, 0xc03d, 0x21, 0 + .dw 0x8f40, 0xc03d, 0x8f7f, 0xc03d, 0x21, 0 + .dw 0x8fc0, 0xc03d, 0x8fff, 0xc03d, 0x21, 0 + .dw 0x9040, 0xc03d, 0x907f, 0xc03d, 0x21, 0 + .dw 0x90c0, 0xc03d, 0x90ff, 0xc03d, 0x21, 0 + .dw 0x9140, 0xc03d, 0x917f, 0xc03d, 0x21, 0 + .dw 0x91c0, 0xc03d, 0x91ff, 0xc03d, 0x21, 0 + .dw 0x9240, 0xc03d, 0x927f, 0xc03d, 0x21, 0 + .dw 0x92c0, 0xc03d, 0x92ff, 0xc03d, 0x21, 0 + .dw 0x9340, 0xc03d, 0x937f, 0xc03d, 0x21, 0 + .dw 0x93c0, 0xc03d, 0x93ff, 0xc03d, 0x21, 0 + .dw 0x9440, 0xc03d, 0x947f, 0xc03d, 0x21, 0 + .dw 0x94c0, 0xc03d, 0x94ff, 0xc03d, 0x21, 0 + .dw 0x9540, 0xc03d, 0x957f, 0xc03d, 0x21, 0 + .dw 0x95c0, 0xc03d, 0x95ff, 0xc03d, 0x21, 0 + .dw 0x9640, 0xc03d, 0x967f, 0xc03d, 0x21, 0 + .dw 0x96c0, 0xc03d, 0x96ff, 0xc03d, 0x21, 0 + .dw 0x9740, 0xc03d, 0x977f, 0xc03d, 0x21, 0 + .dw 0x97c0, 0xc03d, 0x97ff, 0xc03d, 0x21, 0 + .dw 0x9840, 0xc03d, 0x987f, 0xc03d, 0x21, 0 + .dw 0x98c0, 0xc03d, 0x98ff, 0xc03d, 0x21, 0 + .dw 0x9940, 0xc03d, 0x997f, 0xc03d, 0x21, 0 + .dw 0x99c0, 0xc03d, 0x9fff, 0xc03d, 0x21, 0 + .dw 0xa040, 0xc03d, 0xa07f, 0xc03d, 0x21, 0 + .dw 0xa0c0, 0xc03d, 0xa0ff, 0xc03d, 0x21, 0 + .dw 0xa140, 0xc03d, 0xa17f, 0xc03d, 0x21, 0 + .dw 0xa1c0, 0xc03d, 0xa1ff, 0xc03d, 0x21, 0 + .dw 0xa240, 0xc03d, 0xa27f, 0xc03d, 0x21, 0 + .dw 0xa2c0, 0xc03d, 0xa2ff, 0xc03d, 0x21, 0 + .dw 0xa340, 0xc03d, 0xa37f, 0xc03d, 0x21, 0 + .dw 0xa3c0, 0xc03d, 0xa3ff, 0xc03d, 0x21, 0 + .dw 0xa440, 0xc03d, 0xa47f, 0xc03d, 0x21, 0 + .dw 0xa4c0, 0xc03d, 0xa4ff, 0xc03d, 0x21, 0 + .dw 0xa540, 0xc03d, 0xa57f, 0xc03d, 0x21, 0 + .dw 0xa5c0, 0xc03d, 0xa5ff, 0xc03d, 0x21, 0 + .dw 0xa640, 0xc03d, 0xa67f, 0xc03d, 0x21, 0 + .dw 0xa6c0, 0xc03d, 0xa6ff, 0xc03d, 0x21, 0 + .dw 0xa740, 0xc03d, 0xa77f, 0xc03d, 0x21, 0 + .dw 0xa7c0, 0xc03d, 0xa7ff, 0xc03d, 0x21, 0 + .dw 0xa840, 0xc03d, 0xa87f, 0xc03d, 0x21, 0 + .dw 0xa8c0, 0xc03d, 0xa8ff, 0xc03d, 0x21, 0 + .dw 0xa940, 0xc03d, 0xa97f, 0xc03d, 0x21, 0 + .dw 0xa9c0, 0xc03d, 0xa9ff, 0xc03d, 0x21, 0 + .dw 0xaa40, 0xc03d, 0xaa7f, 0xc03d, 0x21, 0 + .dw 0xaac0, 0xc03d, 0xaaff, 0xc03d, 0x21, 0 + .dw 0xab40, 0xc03d, 0xab7f, 0xc03d, 0x21, 0 + .dw 0xabc0, 0xc03d, 0xabff, 0xc03d, 0x21, 0 + .dw 0xac40, 0xc03d, 0xac7f, 0xc03d, 0x21, 0 + .dw 0xacc0, 0xc03d, 0xacff, 0xc03d, 0x21, 0 + .dw 0xad40, 0xc03d, 0xad7f, 0xc03d, 0x21, 0 + .dw 0xadc0, 0xc03d, 0xadff, 0xc03d, 0x21, 0 + .dw 0xae40, 0xc03d, 0xae7f, 0xc03d, 0x21, 0 + .dw 0xaec0, 0xc03d, 0xaeff, 0xc03d, 0x21, 0 + .dw 0xaf40, 0xc03d, 0xaf7f, 0xc03d, 0x21, 0 + .dw 0xafc0, 0xc03d, 0xafff, 0xc03d, 0x21, 0 + .dw 0xb040, 0xc03d, 0xb07f, 0xc03d, 0x21, 0 + .dw 0xb0c0, 0xc03d, 0xb0ff, 0xc03d, 0x21, 0 + .dw 0xb140, 0xc03d, 0xb17f, 0xc03d, 0x21, 0 + .dw 0xb1c0, 0xc03d, 0xb1ff, 0xc03d, 0x21, 0 + .dw 0xb240, 0xc03d, 0xb27f, 0xc03d, 0x21, 0 + .dw 0xb2c0, 0xc03d, 0xb2ff, 0xc03d, 0x21, 0 + .dw 0xb340, 0xc03d, 0xb37f, 0xc03d, 0x21, 0 + .dw 0xb3c0, 0xc03d, 0xb3ff, 0xc03d, 0x21, 0 + .dw 0xb440, 0xc03d, 0xb47f, 0xc03d, 0x21, 0 + .dw 0xb4c0, 0xc03d, 0xb4ff, 0xc03d, 0x21, 0 + .dw 0xb540, 0xc03d, 0xb57f, 0xc03d, 0x21, 0 + .dw 0xb5c0, 0xc03d, 0xb5ff, 0xc03d, 0x21, 0 + .dw 0xb640, 0xc03d, 0xb67f, 0xc03d, 0x21, 0 + .dw 0xb6c0, 0xc03d, 0xb6ff, 0xc03d, 0x21, 0 + .dw 0xb740, 0xc03d, 0xb77f, 0xc03d, 0x21, 0 + .dw 0xb7c0, 0xc03d, 0xb7ff, 0xc03d, 0x21, 0 + .dw 0xb840, 0xc03d, 0xb87f, 0xc03d, 0x21, 0 + .dw 0xb8c0, 0xc03d, 0xb8ff, 0xc03d, 0x21, 0 + .dw 0xb940, 0xc03d, 0xb97f, 0xc03d, 0x21, 0 + .dw 0xb9c0, 0xc03d, 0xbfff, 0xc03d, 0x21, 0 + .dw 0xc040, 0xc03d, 0xc07f, 0xc03d, 0x21, 0 + .dw 0xc0c0, 0xc03d, 0xc0ff, 0xc03d, 0x21, 0 + .dw 0xc140, 0xc03d, 0xc17f, 0xc03d, 0x21, 0 + .dw 0xc1c0, 0xc03d, 0xc1ff, 0xc03d, 0x21, 0 + .dw 0xc240, 0xc03d, 0xc27f, 0xc03d, 0x21, 0 + .dw 0xc2c0, 0xc03d, 0xc2ff, 0xc03d, 0x21, 0 + .dw 0xc340, 0xc03d, 0xc37f, 0xc03d, 0x21, 0 + .dw 0xc3c0, 0xc03d, 0xc3ff, 0xc03d, 0x21, 0 + .dw 0xc440, 0xc03d, 0xc47f, 0xc03d, 0x21, 0 + .dw 0xc4c0, 0xc03d, 0xc4ff, 0xc03d, 0x21, 0 + .dw 0xc540, 0xc03d, 0xc57f, 0xc03d, 0x21, 0 + .dw 0xc5c0, 0xc03d, 0xc5ff, 0xc03d, 0x21, 0 + .dw 0xc640, 0xc03d, 0xc67f, 0xc03d, 0x21, 0 + .dw 0xc6c0, 0xc03d, 0xc6ff, 0xc03d, 0x21, 0 + .dw 0xc740, 0xc03d, 0xc77f, 0xc03d, 0x21, 0 + .dw 0xc7c0, 0xc03d, 0xc7ff, 0xc03d, 0x21, 0 + .dw 0xc840, 0xc03d, 0xc87f, 0xc03d, 0x21, 0 + .dw 0xc8c0, 0xc03d, 0xc8ff, 0xc03d, 0x21, 0 + .dw 0xc940, 0xc03d, 0xc97f, 0xc03d, 0x21, 0 + .dw 0xc9c0, 0xc03d, 0xc9ff, 0xc03d, 0x21, 0 + .dw 0xca40, 0xc03d, 0xca7f, 0xc03d, 0x21, 0 + .dw 0xcac0, 0xc03d, 0xcaff, 0xc03d, 0x21, 0 + .dw 0xcb40, 0xc03d, 0xcb7f, 0xc03d, 0x21, 0 + .dw 0xcbc0, 0xc03d, 0xcbff, 0xc03d, 0x21, 0 + .dw 0xcc40, 0xc03d, 0xcc7f, 0xc03d, 0x21, 0 + .dw 0xccc0, 0xc03d, 0xccff, 0xc03d, 0x21, 0 + .dw 0xcd40, 0xc03d, 0xcd7f, 0xc03d, 0x21, 0 + .dw 0xcdc0, 0xc03d, 0xcdff, 0xc03d, 0x21, 0 + .dw 0xce40, 0xc03d, 0xce7f, 0xc03d, 0x21, 0 + .dw 0xcec0, 0xc03d, 0xceff, 0xc03d, 0x21, 0 + .dw 0xcf40, 0xc03d, 0xcf7f, 0xc03d, 0x21, 0 + .dw 0xcfc0, 0xc03d, 0xcfff, 0xc03d, 0x21, 0 + .dw 0xd040, 0xc03d, 0xd07f, 0xc03d, 0x21, 0 + .dw 0xd0c0, 0xc03d, 0xd0ff, 0xc03d, 0x21, 0 + .dw 0xd140, 0xc03d, 0xd17f, 0xc03d, 0x21, 0 + .dw 0xd1c0, 0xc03d, 0xd1ff, 0xc03d, 0x21, 0 + .dw 0xd240, 0xc03d, 0xd27f, 0xc03d, 0x21, 0 + .dw 0xd2c0, 0xc03d, 0xd2ff, 0xc03d, 0x21, 0 + .dw 0xd340, 0xc03d, 0xd37f, 0xc03d, 0x21, 0 + .dw 0xd3c0, 0xc03d, 0xd3ff, 0xc03d, 0x21, 0 + .dw 0xd440, 0xc03d, 0xd47f, 0xc03d, 0x21, 0 + .dw 0xd4c0, 0xc03d, 0xd4ff, 0xc03d, 0x21, 0 + .dw 0xd540, 0xc03d, 0xd57f, 0xc03d, 0x21, 0 + .dw 0xd5c0, 0xc03d, 0xd5ff, 0xc03d, 0x21, 0 + .dw 0xd640, 0xc03d, 0xd67f, 0xc03d, 0x21, 0 + .dw 0xd6c0, 0xc03d, 0xd6ff, 0xc03d, 0x21, 0 + .dw 0xd740, 0xc03d, 0xd77f, 0xc03d, 0x21, 0 + .dw 0xd7c0, 0xc03d, 0xd7ff, 0xc03d, 0x21, 0 + .dw 0xd840, 0xc03d, 0xd87f, 0xc03d, 0x21, 0 + .dw 0xd8c0, 0xc03d, 0xd8ff, 0xc03d, 0x21, 0 + .dw 0xd940, 0xc03d, 0xd97f, 0xc03d, 0x21, 0 + .dw 0xd9c0, 0xc03d, 0xdfff, 0xc03d, 0x21, 0 + .dw 0xe040, 0xc03d, 0xe07f, 0xc03d, 0x21, 0 + .dw 0xe0c0, 0xc03d, 0xe0ff, 0xc03d, 0x21, 0 + .dw 0xe140, 0xc03d, 0xe17f, 0xc03d, 0x21, 0 + .dw 0xe1c0, 0xc03d, 0xe1ff, 0xc03d, 0x21, 0 + .dw 0xe240, 0xc03d, 0xe27f, 0xc03d, 0x21, 0 + .dw 0xe2c0, 0xc03d, 0xe2ff, 0xc03d, 0x21, 0 + .dw 0xe340, 0xc03d, 0xe37f, 0xc03d, 0x21, 0 + .dw 0xe3c0, 0xc03d, 0xe3ff, 0xc03d, 0x21, 0 + .dw 0xe440, 0xc03d, 0xe47f, 0xc03d, 0x21, 0 + .dw 0xe4c0, 0xc03d, 0xe4ff, 0xc03d, 0x21, 0 + .dw 0xe540, 0xc03d, 0xe57f, 0xc03d, 0x21, 0 + .dw 0xe5c0, 0xc03d, 0xe5ff, 0xc03d, 0x21, 0 + .dw 0xe640, 0xc03d, 0xe67f, 0xc03d, 0x21, 0 + .dw 0xe6c0, 0xc03d, 0xe6ff, 0xc03d, 0x21, 0 + .dw 0xe740, 0xc03d, 0xe77f, 0xc03d, 0x21, 0 + .dw 0xe7c0, 0xc03d, 0xe7ff, 0xc03d, 0x21, 0 + .dw 0xe840, 0xc03d, 0xe87f, 0xc03d, 0x21, 0 + .dw 0xe8c0, 0xc03d, 0xe8ff, 0xc03d, 0x21, 0 + .dw 0xe940, 0xc03d, 0xe97f, 0xc03d, 0x21, 0 + .dw 0xe9c0, 0xc03d, 0xe9ff, 0xc03d, 0x21, 0 + .dw 0xea40, 0xc03d, 0xea7f, 0xc03d, 0x21, 0 + .dw 0xeac0, 0xc03d, 0xeaff, 0xc03d, 0x21, 0 + .dw 0xeb40, 0xc03d, 0xeb7f, 0xc03d, 0x21, 0 + .dw 0xebc0, 0xc03d, 0xebff, 0xc03d, 0x21, 0 + .dw 0xec40, 0xc03d, 0xec7f, 0xc03d, 0x21, 0 + .dw 0xecc0, 0xc03d, 0xecff, 0xc03d, 0x21, 0 + .dw 0xed40, 0xc03d, 0xed7f, 0xc03d, 0x21, 0 + .dw 0xedc0, 0xc03d, 0xedff, 0xc03d, 0x21, 0 + .dw 0xee40, 0xc03d, 0xee7f, 0xc03d, 0x21, 0 + .dw 0xeec0, 0xc03d, 0xeeff, 0xc03d, 0x21, 0 + .dw 0xef40, 0xc03d, 0xef7f, 0xc03d, 0x21, 0 + .dw 0xefc0, 0xc03d, 0xefff, 0xc03d, 0x21, 0 + .dw 0xf040, 0xc03d, 0xf07f, 0xc03d, 0x21, 0 + .dw 0xf0c0, 0xc03d, 0xf0ff, 0xc03d, 0x21, 0 + .dw 0xf140, 0xc03d, 0xf17f, 0xc03d, 0x21, 0 + .dw 0xf1c0, 0xc03d, 0xf1ff, 0xc03d, 0x21, 0 + .dw 0xf240, 0xc03d, 0xf27f, 0xc03d, 0x21, 0 + .dw 0xf2c0, 0xc03d, 0xf2ff, 0xc03d, 0x21, 0 + .dw 0xf340, 0xc03d, 0xf37f, 0xc03d, 0x21, 0 + .dw 0xf3c0, 0xc03d, 0xf3ff, 0xc03d, 0x21, 0 + .dw 0xf440, 0xc03d, 0xf47f, 0xc03d, 0x21, 0 + .dw 0xf4c0, 0xc03d, 0xf4ff, 0xc03d, 0x21, 0 + .dw 0xf540, 0xc03d, 0xf57f, 0xc03d, 0x21, 0 + .dw 0xf5c0, 0xc03d, 0xf5ff, 0xc03d, 0x21, 0 + .dw 0xf640, 0xc03d, 0xf67f, 0xc03d, 0x21, 0 + .dw 0xf6c0, 0xc03d, 0xf6ff, 0xc03d, 0x21, 0 + .dw 0xf740, 0xc03d, 0xf77f, 0xc03d, 0x21, 0 + .dw 0xf7c0, 0xc03d, 0xf7ff, 0xc03d, 0x21, 0 + .dw 0xf840, 0xc03d, 0xf87f, 0xc03d, 0x21, 0 + .dw 0xf8c0, 0xc03d, 0xf8ff, 0xc03d, 0x21, 0 + .dw 0xf940, 0xc03d, 0xf97f, 0xc03d, 0x21, 0 + .dw 0xf9c0, 0xc03d, 0xffff, 0xc03d, 0x21, 0 + .dw 0x0040, 0xc03e, 0x007f, 0xc03e, 0x21, 0 + .dw 0x00c0, 0xc03e, 0x00ff, 0xc03e, 0x21, 0 + .dw 0x0140, 0xc03e, 0x017f, 0xc03e, 0x21, 0 + .dw 0x01c0, 0xc03e, 0x01ff, 0xc03e, 0x21, 0 + .dw 0x0240, 0xc03e, 0x027f, 0xc03e, 0x21, 0 + .dw 0x02c0, 0xc03e, 0x02ff, 0xc03e, 0x21, 0 + .dw 0x0340, 0xc03e, 0x037f, 0xc03e, 0x21, 0 + .dw 0x03c0, 0xc03e, 0x03ff, 0xc03e, 0x21, 0 + .dw 0x0440, 0xc03e, 0x047f, 0xc03e, 0x21, 0 + .dw 0x04c0, 0xc03e, 0x04ff, 0xc03e, 0x21, 0 + .dw 0x0540, 0xc03e, 0x057f, 0xc03e, 0x21, 0 + .dw 0x05c0, 0xc03e, 0x05ff, 0xc03e, 0x21, 0 + .dw 0x0640, 0xc03e, 0x067f, 0xc03e, 0x21, 0 + .dw 0x06c0, 0xc03e, 0x06ff, 0xc03e, 0x21, 0 + .dw 0x0740, 0xc03e, 0x077f, 0xc03e, 0x21, 0 + .dw 0x07c0, 0xc03e, 0x07ff, 0xc03e, 0x21, 0 + .dw 0x0840, 0xc03e, 0x087f, 0xc03e, 0x21, 0 + .dw 0x08c0, 0xc03e, 0x08ff, 0xc03e, 0x21, 0 + .dw 0x0940, 0xc03e, 0x097f, 0xc03e, 0x21, 0 + .dw 0x09c0, 0xc03e, 0x09ff, 0xc03e, 0x21, 0 + .dw 0x0a40, 0xc03e, 0x0a7f, 0xc03e, 0x21, 0 + .dw 0x0ac0, 0xc03e, 0x0aff, 0xc03e, 0x21, 0 + .dw 0x0b40, 0xc03e, 0x0b7f, 0xc03e, 0x21, 0 + .dw 0x0bc0, 0xc03e, 0x0bff, 0xc03e, 0x21, 0 + .dw 0x0c40, 0xc03e, 0x0c7f, 0xc03e, 0x21, 0 + .dw 0x0cc0, 0xc03e, 0x0cff, 0xc03e, 0x21, 0 + .dw 0x0d40, 0xc03e, 0x0d7f, 0xc03e, 0x21, 0 + .dw 0x0dc0, 0xc03e, 0x0dff, 0xc03e, 0x21, 0 + .dw 0x0e40, 0xc03e, 0x0e7f, 0xc03e, 0x21, 0 + .dw 0x0ec0, 0xc03e, 0x0eff, 0xc03e, 0x21, 0 + .dw 0x0f40, 0xc03e, 0x0f7f, 0xc03e, 0x21, 0 + .dw 0x0fc0, 0xc03e, 0x0fff, 0xc03e, 0x21, 0 + .dw 0x1040, 0xc03e, 0x107f, 0xc03e, 0x21, 0 + .dw 0x10c0, 0xc03e, 0x10ff, 0xc03e, 0x21, 0 + .dw 0x1140, 0xc03e, 0x117f, 0xc03e, 0x21, 0 + .dw 0x11c0, 0xc03e, 0x11ff, 0xc03e, 0x21, 0 + .dw 0x1240, 0xc03e, 0x127f, 0xc03e, 0x21, 0 + .dw 0x12c0, 0xc03e, 0x12ff, 0xc03e, 0x21, 0 + .dw 0x1340, 0xc03e, 0x137f, 0xc03e, 0x21, 0 + .dw 0x13c0, 0xc03e, 0x13ff, 0xc03e, 0x21, 0 + .dw 0x1440, 0xc03e, 0x147f, 0xc03e, 0x21, 0 + .dw 0x14c0, 0xc03e, 0x14ff, 0xc03e, 0x21, 0 + .dw 0x1540, 0xc03e, 0x157f, 0xc03e, 0x21, 0 + .dw 0x15c0, 0xc03e, 0x15ff, 0xc03e, 0x21, 0 + .dw 0x1640, 0xc03e, 0x167f, 0xc03e, 0x21, 0 + .dw 0x16c0, 0xc03e, 0x16ff, 0xc03e, 0x21, 0 + .dw 0x1740, 0xc03e, 0x177f, 0xc03e, 0x21, 0 + .dw 0x17c0, 0xc03e, 0x17ff, 0xc03e, 0x21, 0 + .dw 0x1840, 0xc03e, 0x187f, 0xc03e, 0x21, 0 + .dw 0x18c0, 0xc03e, 0x18ff, 0xc03e, 0x21, 0 + .dw 0x1940, 0xc03e, 0x197f, 0xc03e, 0x21, 0 + .dw 0x19c0, 0xc03e, 0x1fff, 0xc03e, 0x21, 0 + .dw 0x2040, 0xc03e, 0x207f, 0xc03e, 0x21, 0 + .dw 0x20c0, 0xc03e, 0x20ff, 0xc03e, 0x21, 0 + .dw 0x2140, 0xc03e, 0x217f, 0xc03e, 0x21, 0 + .dw 0x21c0, 0xc03e, 0x21ff, 0xc03e, 0x21, 0 + .dw 0x2240, 0xc03e, 0x227f, 0xc03e, 0x21, 0 + .dw 0x22c0, 0xc03e, 0x22ff, 0xc03e, 0x21, 0 + .dw 0x2340, 0xc03e, 0x237f, 0xc03e, 0x21, 0 + .dw 0x23c0, 0xc03e, 0x23ff, 0xc03e, 0x21, 0 + .dw 0x2440, 0xc03e, 0x247f, 0xc03e, 0x21, 0 + .dw 0x24c0, 0xc03e, 0x24ff, 0xc03e, 0x21, 0 + .dw 0x2540, 0xc03e, 0x257f, 0xc03e, 0x21, 0 + .dw 0x25c0, 0xc03e, 0x25ff, 0xc03e, 0x21, 0 + .dw 0x2640, 0xc03e, 0x267f, 0xc03e, 0x21, 0 + .dw 0x26c0, 0xc03e, 0x26ff, 0xc03e, 0x21, 0 + .dw 0x2740, 0xc03e, 0x277f, 0xc03e, 0x21, 0 + .dw 0x27c0, 0xc03e, 0x27ff, 0xc03e, 0x21, 0 + .dw 0x2840, 0xc03e, 0x287f, 0xc03e, 0x21, 0 + .dw 0x28c0, 0xc03e, 0x28ff, 0xc03e, 0x21, 0 + .dw 0x2940, 0xc03e, 0x297f, 0xc03e, 0x21, 0 + .dw 0x29c0, 0xc03e, 0x29ff, 0xc03e, 0x21, 0 + .dw 0x2a40, 0xc03e, 0x2a7f, 0xc03e, 0x21, 0 + .dw 0x2ac0, 0xc03e, 0x2aff, 0xc03e, 0x21, 0 + .dw 0x2b40, 0xc03e, 0x2b7f, 0xc03e, 0x21, 0 + .dw 0x2bc0, 0xc03e, 0x2bff, 0xc03e, 0x21, 0 + .dw 0x2c40, 0xc03e, 0x2c7f, 0xc03e, 0x21, 0 + .dw 0x2cc0, 0xc03e, 0x2cff, 0xc03e, 0x21, 0 + .dw 0x2d40, 0xc03e, 0x2d7f, 0xc03e, 0x21, 0 + .dw 0x2dc0, 0xc03e, 0x2dff, 0xc03e, 0x21, 0 + .dw 0x2e40, 0xc03e, 0x2e7f, 0xc03e, 0x21, 0 + .dw 0x2ec0, 0xc03e, 0x2eff, 0xc03e, 0x21, 0 + .dw 0x2f40, 0xc03e, 0x2f7f, 0xc03e, 0x21, 0 + .dw 0x2fc0, 0xc03e, 0x2fff, 0xc03e, 0x21, 0 + .dw 0x3040, 0xc03e, 0x307f, 0xc03e, 0x21, 0 + .dw 0x30c0, 0xc03e, 0x30ff, 0xc03e, 0x21, 0 + .dw 0x3140, 0xc03e, 0x317f, 0xc03e, 0x21, 0 + .dw 0x31c0, 0xc03e, 0x31ff, 0xc03e, 0x21, 0 + .dw 0x3240, 0xc03e, 0x327f, 0xc03e, 0x21, 0 + .dw 0x32c0, 0xc03e, 0x32ff, 0xc03e, 0x21, 0 + .dw 0x3340, 0xc03e, 0x337f, 0xc03e, 0x21, 0 + .dw 0x33c0, 0xc03e, 0x33ff, 0xc03e, 0x21, 0 + .dw 0x3440, 0xc03e, 0x347f, 0xc03e, 0x21, 0 + .dw 0x34c0, 0xc03e, 0x34ff, 0xc03e, 0x21, 0 + .dw 0x3540, 0xc03e, 0x357f, 0xc03e, 0x21, 0 + .dw 0x35c0, 0xc03e, 0x35ff, 0xc03e, 0x21, 0 + .dw 0x3640, 0xc03e, 0x367f, 0xc03e, 0x21, 0 + .dw 0x36c0, 0xc03e, 0x36ff, 0xc03e, 0x21, 0 + .dw 0x3740, 0xc03e, 0x377f, 0xc03e, 0x21, 0 + .dw 0x37c0, 0xc03e, 0x37ff, 0xc03e, 0x21, 0 + .dw 0x3840, 0xc03e, 0x387f, 0xc03e, 0x21, 0 + .dw 0x38c0, 0xc03e, 0x38ff, 0xc03e, 0x21, 0 + .dw 0x3940, 0xc03e, 0x397f, 0xc03e, 0x21, 0 + .dw 0x39c0, 0xc03e, 0x3fff, 0xc03e, 0x21, 0 + .dw 0x4040, 0xc03e, 0x407f, 0xc03e, 0x21, 0 + .dw 0x40c0, 0xc03e, 0x40ff, 0xc03e, 0x21, 0 + .dw 0x4140, 0xc03e, 0x417f, 0xc03e, 0x21, 0 + .dw 0x41c0, 0xc03e, 0x41ff, 0xc03e, 0x21, 0 + .dw 0x4240, 0xc03e, 0x427f, 0xc03e, 0x21, 0 + .dw 0x42c0, 0xc03e, 0x42ff, 0xc03e, 0x21, 0 + .dw 0x4340, 0xc03e, 0x437f, 0xc03e, 0x21, 0 + .dw 0x43c0, 0xc03e, 0x43ff, 0xc03e, 0x21, 0 + .dw 0x4440, 0xc03e, 0x447f, 0xc03e, 0x21, 0 + .dw 0x44c0, 0xc03e, 0x44ff, 0xc03e, 0x21, 0 + .dw 0x4540, 0xc03e, 0x457f, 0xc03e, 0x21, 0 + .dw 0x45c0, 0xc03e, 0x45ff, 0xc03e, 0x21, 0 + .dw 0x4640, 0xc03e, 0x467f, 0xc03e, 0x21, 0 + .dw 0x46c0, 0xc03e, 0x46ff, 0xc03e, 0x21, 0 + .dw 0x4740, 0xc03e, 0x477f, 0xc03e, 0x21, 0 + .dw 0x47c0, 0xc03e, 0x47ff, 0xc03e, 0x21, 0 + .dw 0x4840, 0xc03e, 0x487f, 0xc03e, 0x21, 0 + .dw 0x48c0, 0xc03e, 0x48ff, 0xc03e, 0x21, 0 + .dw 0x4940, 0xc03e, 0x497f, 0xc03e, 0x21, 0 + .dw 0x49c0, 0xc03e, 0x49ff, 0xc03e, 0x21, 0 + .dw 0x4a40, 0xc03e, 0x4a7f, 0xc03e, 0x21, 0 + .dw 0x4ac0, 0xc03e, 0x4aff, 0xc03e, 0x21, 0 + .dw 0x4b40, 0xc03e, 0x4b7f, 0xc03e, 0x21, 0 + .dw 0x4bc0, 0xc03e, 0x4bff, 0xc03e, 0x21, 0 + .dw 0x4c40, 0xc03e, 0x4c7f, 0xc03e, 0x21, 0 + .dw 0x4cc0, 0xc03e, 0x4cff, 0xc03e, 0x21, 0 + .dw 0x4d40, 0xc03e, 0x4d7f, 0xc03e, 0x21, 0 + .dw 0x4dc0, 0xc03e, 0x4dff, 0xc03e, 0x21, 0 + .dw 0x4e40, 0xc03e, 0x4e7f, 0xc03e, 0x21, 0 + .dw 0x4ec0, 0xc03e, 0x4eff, 0xc03e, 0x21, 0 + .dw 0x4f40, 0xc03e, 0x4f7f, 0xc03e, 0x21, 0 + .dw 0x4fc0, 0xc03e, 0x4fff, 0xc03e, 0x21, 0 + .dw 0x5040, 0xc03e, 0x507f, 0xc03e, 0x21, 0 + .dw 0x50c0, 0xc03e, 0x50ff, 0xc03e, 0x21, 0 + .dw 0x5140, 0xc03e, 0x517f, 0xc03e, 0x21, 0 + .dw 0x51c0, 0xc03e, 0x51ff, 0xc03e, 0x21, 0 + .dw 0x5240, 0xc03e, 0x527f, 0xc03e, 0x21, 0 + .dw 0x52c0, 0xc03e, 0x52ff, 0xc03e, 0x21, 0 + .dw 0x5340, 0xc03e, 0x537f, 0xc03e, 0x21, 0 + .dw 0x53c0, 0xc03e, 0x53ff, 0xc03e, 0x21, 0 + .dw 0x5440, 0xc03e, 0x547f, 0xc03e, 0x21, 0 + .dw 0x54c0, 0xc03e, 0x54ff, 0xc03e, 0x21, 0 + .dw 0x5540, 0xc03e, 0x557f, 0xc03e, 0x21, 0 + .dw 0x55c0, 0xc03e, 0x55ff, 0xc03e, 0x21, 0 + .dw 0x5640, 0xc03e, 0x567f, 0xc03e, 0x21, 0 + .dw 0x56c0, 0xc03e, 0x56ff, 0xc03e, 0x21, 0 + .dw 0x5740, 0xc03e, 0x577f, 0xc03e, 0x21, 0 + .dw 0x57c0, 0xc03e, 0x57ff, 0xc03e, 0x21, 0 + .dw 0x5840, 0xc03e, 0x587f, 0xc03e, 0x21, 0 + .dw 0x58c0, 0xc03e, 0x58ff, 0xc03e, 0x21, 0 + .dw 0x5940, 0xc03e, 0x597f, 0xc03e, 0x21, 0 + .dw 0x59c0, 0xc03e, 0x5fff, 0xc03e, 0x21, 0 + .dw 0x6040, 0xc03e, 0x607f, 0xc03e, 0x21, 0 + .dw 0x60c0, 0xc03e, 0x60ff, 0xc03e, 0x21, 0 + .dw 0x6140, 0xc03e, 0x617f, 0xc03e, 0x21, 0 + .dw 0x61c0, 0xc03e, 0x61ff, 0xc03e, 0x21, 0 + .dw 0x6240, 0xc03e, 0x627f, 0xc03e, 0x21, 0 + .dw 0x62c0, 0xc03e, 0x62ff, 0xc03e, 0x21, 0 + .dw 0x6340, 0xc03e, 0x637f, 0xc03e, 0x21, 0 + .dw 0x63c0, 0xc03e, 0x63ff, 0xc03e, 0x21, 0 + .dw 0x6440, 0xc03e, 0x647f, 0xc03e, 0x21, 0 + .dw 0x64c0, 0xc03e, 0x64ff, 0xc03e, 0x21, 0 + .dw 0x6540, 0xc03e, 0x657f, 0xc03e, 0x21, 0 + .dw 0x65c0, 0xc03e, 0x65ff, 0xc03e, 0x21, 0 + .dw 0x6640, 0xc03e, 0x667f, 0xc03e, 0x21, 0 + .dw 0x66c0, 0xc03e, 0x66ff, 0xc03e, 0x21, 0 + .dw 0x6740, 0xc03e, 0x677f, 0xc03e, 0x21, 0 + .dw 0x67c0, 0xc03e, 0x67ff, 0xc03e, 0x21, 0 + .dw 0x6840, 0xc03e, 0x687f, 0xc03e, 0x21, 0 + .dw 0x68c0, 0xc03e, 0x68ff, 0xc03e, 0x21, 0 + .dw 0x6940, 0xc03e, 0x697f, 0xc03e, 0x21, 0 + .dw 0x69c0, 0xc03e, 0x69ff, 0xc03e, 0x21, 0 + .dw 0x6a40, 0xc03e, 0x6a7f, 0xc03e, 0x21, 0 + .dw 0x6ac0, 0xc03e, 0x6aff, 0xc03e, 0x21, 0 + .dw 0x6b40, 0xc03e, 0x6b7f, 0xc03e, 0x21, 0 + .dw 0x6bc0, 0xc03e, 0x6bff, 0xc03e, 0x21, 0 + .dw 0x6c40, 0xc03e, 0x6c7f, 0xc03e, 0x21, 0 + .dw 0x6cc0, 0xc03e, 0x6cff, 0xc03e, 0x21, 0 + .dw 0x6d40, 0xc03e, 0x6d7f, 0xc03e, 0x21, 0 + .dw 0x6dc0, 0xc03e, 0x6dff, 0xc03e, 0x21, 0 + .dw 0x6e40, 0xc03e, 0x6e7f, 0xc03e, 0x21, 0 + .dw 0x6ec0, 0xc03e, 0x6eff, 0xc03e, 0x21, 0 + .dw 0x6f40, 0xc03e, 0x6f7f, 0xc03e, 0x21, 0 + .dw 0x6fc0, 0xc03e, 0x6fff, 0xc03e, 0x21, 0 + .dw 0x7040, 0xc03e, 0x707f, 0xc03e, 0x21, 0 + .dw 0x70c0, 0xc03e, 0x70ff, 0xc03e, 0x21, 0 + .dw 0x7140, 0xc03e, 0x717f, 0xc03e, 0x21, 0 + .dw 0x71c0, 0xc03e, 0x71ff, 0xc03e, 0x21, 0 + .dw 0x7240, 0xc03e, 0x727f, 0xc03e, 0x21, 0 + .dw 0x72c0, 0xc03e, 0x72ff, 0xc03e, 0x21, 0 + .dw 0x7340, 0xc03e, 0x737f, 0xc03e, 0x21, 0 + .dw 0x73c0, 0xc03e, 0x73ff, 0xc03e, 0x21, 0 + .dw 0x7440, 0xc03e, 0x747f, 0xc03e, 0x21, 0 + .dw 0x74c0, 0xc03e, 0x74ff, 0xc03e, 0x21, 0 + .dw 0x7540, 0xc03e, 0x757f, 0xc03e, 0x21, 0 + .dw 0x75c0, 0xc03e, 0x75ff, 0xc03e, 0x21, 0 + .dw 0x7640, 0xc03e, 0x767f, 0xc03e, 0x21, 0 + .dw 0x76c0, 0xc03e, 0x76ff, 0xc03e, 0x21, 0 + .dw 0x7740, 0xc03e, 0x777f, 0xc03e, 0x21, 0 + .dw 0x77c0, 0xc03e, 0x77ff, 0xc03e, 0x21, 0 + .dw 0x7840, 0xc03e, 0x787f, 0xc03e, 0x21, 0 + .dw 0x78c0, 0xc03e, 0x78ff, 0xc03e, 0x21, 0 + .dw 0x7940, 0xc03e, 0x797f, 0xc03e, 0x21, 0 + .dw 0x79c0, 0xc03e, 0x7fff, 0xc03e, 0x21, 0 + .dw 0x8040, 0xc03e, 0x807f, 0xc03e, 0x21, 0 + .dw 0x80c0, 0xc03e, 0x80ff, 0xc03e, 0x21, 0 + .dw 0x8140, 0xc03e, 0x817f, 0xc03e, 0x21, 0 + .dw 0x81c0, 0xc03e, 0x81ff, 0xc03e, 0x21, 0 + .dw 0x8240, 0xc03e, 0x827f, 0xc03e, 0x21, 0 + .dw 0x82c0, 0xc03e, 0x82ff, 0xc03e, 0x21, 0 + .dw 0x8340, 0xc03e, 0x837f, 0xc03e, 0x21, 0 + .dw 0x83c0, 0xc03e, 0x83ff, 0xc03e, 0x21, 0 + .dw 0x8440, 0xc03e, 0x847f, 0xc03e, 0x21, 0 + .dw 0x84c0, 0xc03e, 0x84ff, 0xc03e, 0x21, 0 + .dw 0x8540, 0xc03e, 0x857f, 0xc03e, 0x21, 0 + .dw 0x85c0, 0xc03e, 0x85ff, 0xc03e, 0x21, 0 + .dw 0x8640, 0xc03e, 0x867f, 0xc03e, 0x21, 0 + .dw 0x86c0, 0xc03e, 0x86ff, 0xc03e, 0x21, 0 + .dw 0x8740, 0xc03e, 0x877f, 0xc03e, 0x21, 0 + .dw 0x87c0, 0xc03e, 0x87ff, 0xc03e, 0x21, 0 + .dw 0x8840, 0xc03e, 0x887f, 0xc03e, 0x21, 0 + .dw 0x88c0, 0xc03e, 0x88ff, 0xc03e, 0x21, 0 + .dw 0x8940, 0xc03e, 0x897f, 0xc03e, 0x21, 0 + .dw 0x89c0, 0xc03e, 0x89ff, 0xc03e, 0x21, 0 + .dw 0x8a40, 0xc03e, 0x8a7f, 0xc03e, 0x21, 0 + .dw 0x8ac0, 0xc03e, 0x8aff, 0xc03e, 0x21, 0 + .dw 0x8b40, 0xc03e, 0x8b7f, 0xc03e, 0x21, 0 + .dw 0x8bc0, 0xc03e, 0x8bff, 0xc03e, 0x21, 0 + .dw 0x8c40, 0xc03e, 0x8c7f, 0xc03e, 0x21, 0 + .dw 0x8cc0, 0xc03e, 0x8cff, 0xc03e, 0x21, 0 + .dw 0x8d40, 0xc03e, 0x8d7f, 0xc03e, 0x21, 0 + .dw 0x8dc0, 0xc03e, 0x8dff, 0xc03e, 0x21, 0 + .dw 0x8e40, 0xc03e, 0x8e7f, 0xc03e, 0x21, 0 + .dw 0x8ec0, 0xc03e, 0x8eff, 0xc03e, 0x21, 0 + .dw 0x8f40, 0xc03e, 0x8f7f, 0xc03e, 0x21, 0 + .dw 0x8fc0, 0xc03e, 0x8fff, 0xc03e, 0x21, 0 + .dw 0x9040, 0xc03e, 0x907f, 0xc03e, 0x21, 0 + .dw 0x90c0, 0xc03e, 0x90ff, 0xc03e, 0x21, 0 + .dw 0x9140, 0xc03e, 0x917f, 0xc03e, 0x21, 0 + .dw 0x91c0, 0xc03e, 0x91ff, 0xc03e, 0x21, 0 + .dw 0x9240, 0xc03e, 0x927f, 0xc03e, 0x21, 0 + .dw 0x92c0, 0xc03e, 0x92ff, 0xc03e, 0x21, 0 + .dw 0x9340, 0xc03e, 0x937f, 0xc03e, 0x21, 0 + .dw 0x93c0, 0xc03e, 0x93ff, 0xc03e, 0x21, 0 + .dw 0x9440, 0xc03e, 0x947f, 0xc03e, 0x21, 0 + .dw 0x94c0, 0xc03e, 0x94ff, 0xc03e, 0x21, 0 + .dw 0x9540, 0xc03e, 0x957f, 0xc03e, 0x21, 0 + .dw 0x95c0, 0xc03e, 0x95ff, 0xc03e, 0x21, 0 + .dw 0x9640, 0xc03e, 0x967f, 0xc03e, 0x21, 0 + .dw 0x96c0, 0xc03e, 0x96ff, 0xc03e, 0x21, 0 + .dw 0x9740, 0xc03e, 0x977f, 0xc03e, 0x21, 0 + .dw 0x97c0, 0xc03e, 0x97ff, 0xc03e, 0x21, 0 + .dw 0x9840, 0xc03e, 0x987f, 0xc03e, 0x21, 0 + .dw 0x98c0, 0xc03e, 0x98ff, 0xc03e, 0x21, 0 + .dw 0x9940, 0xc03e, 0x997f, 0xc03e, 0x21, 0 + .dw 0x99c0, 0xc03e, 0x9fff, 0xc03e, 0x21, 0 + .dw 0xa040, 0xc03e, 0xa07f, 0xc03e, 0x21, 0 + .dw 0xa0c0, 0xc03e, 0xa0ff, 0xc03e, 0x21, 0 + .dw 0xa140, 0xc03e, 0xa17f, 0xc03e, 0x21, 0 + .dw 0xa1c0, 0xc03e, 0xa1ff, 0xc03e, 0x21, 0 + .dw 0xa240, 0xc03e, 0xa27f, 0xc03e, 0x21, 0 + .dw 0xa2c0, 0xc03e, 0xa2ff, 0xc03e, 0x21, 0 + .dw 0xa340, 0xc03e, 0xa37f, 0xc03e, 0x21, 0 + .dw 0xa3c0, 0xc03e, 0xa3ff, 0xc03e, 0x21, 0 + .dw 0xa440, 0xc03e, 0xa47f, 0xc03e, 0x21, 0 + .dw 0xa4c0, 0xc03e, 0xa4ff, 0xc03e, 0x21, 0 + .dw 0xa540, 0xc03e, 0xa57f, 0xc03e, 0x21, 0 + .dw 0xa5c0, 0xc03e, 0xa5ff, 0xc03e, 0x21, 0 + .dw 0xa640, 0xc03e, 0xa67f, 0xc03e, 0x21, 0 + .dw 0xa6c0, 0xc03e, 0xa6ff, 0xc03e, 0x21, 0 + .dw 0xa740, 0xc03e, 0xa77f, 0xc03e, 0x21, 0 + .dw 0xa7c0, 0xc03e, 0xa7ff, 0xc03e, 0x21, 0 + .dw 0xa840, 0xc03e, 0xa87f, 0xc03e, 0x21, 0 + .dw 0xa8c0, 0xc03e, 0xa8ff, 0xc03e, 0x21, 0 + .dw 0xa940, 0xc03e, 0xa97f, 0xc03e, 0x21, 0 + .dw 0xa9c0, 0xc03e, 0xa9ff, 0xc03e, 0x21, 0 + .dw 0xaa40, 0xc03e, 0xaa7f, 0xc03e, 0x21, 0 + .dw 0xaac0, 0xc03e, 0xaaff, 0xc03e, 0x21, 0 + .dw 0xab40, 0xc03e, 0xab7f, 0xc03e, 0x21, 0 + .dw 0xabc0, 0xc03e, 0xabff, 0xc03e, 0x21, 0 + .dw 0xac40, 0xc03e, 0xac7f, 0xc03e, 0x21, 0 + .dw 0xacc0, 0xc03e, 0xacff, 0xc03e, 0x21, 0 + .dw 0xad40, 0xc03e, 0xad7f, 0xc03e, 0x21, 0 + .dw 0xadc0, 0xc03e, 0xadff, 0xc03e, 0x21, 0 + .dw 0xae40, 0xc03e, 0xae7f, 0xc03e, 0x21, 0 + .dw 0xaec0, 0xc03e, 0xaeff, 0xc03e, 0x21, 0 + .dw 0xaf40, 0xc03e, 0xaf7f, 0xc03e, 0x21, 0 + .dw 0xafc0, 0xc03e, 0xafff, 0xc03e, 0x21, 0 + .dw 0xb040, 0xc03e, 0xb07f, 0xc03e, 0x21, 0 + .dw 0xb0c0, 0xc03e, 0xb0ff, 0xc03e, 0x21, 0 + .dw 0xb140, 0xc03e, 0xb17f, 0xc03e, 0x21, 0 + .dw 0xb1c0, 0xc03e, 0xb1ff, 0xc03e, 0x21, 0 + .dw 0xb240, 0xc03e, 0xb27f, 0xc03e, 0x21, 0 + .dw 0xb2c0, 0xc03e, 0xb2ff, 0xc03e, 0x21, 0 + .dw 0xb340, 0xc03e, 0xb37f, 0xc03e, 0x21, 0 + .dw 0xb3c0, 0xc03e, 0xb3ff, 0xc03e, 0x21, 0 + .dw 0xb440, 0xc03e, 0xb47f, 0xc03e, 0x21, 0 + .dw 0xb4c0, 0xc03e, 0xb4ff, 0xc03e, 0x21, 0 + .dw 0xb540, 0xc03e, 0xb57f, 0xc03e, 0x21, 0 + .dw 0xb5c0, 0xc03e, 0xb5ff, 0xc03e, 0x21, 0 + .dw 0xb640, 0xc03e, 0xb67f, 0xc03e, 0x21, 0 + .dw 0xb6c0, 0xc03e, 0xb6ff, 0xc03e, 0x21, 0 + .dw 0xb740, 0xc03e, 0xb77f, 0xc03e, 0x21, 0 + .dw 0xb7c0, 0xc03e, 0xb7ff, 0xc03e, 0x21, 0 + .dw 0xb840, 0xc03e, 0xb87f, 0xc03e, 0x21, 0 + .dw 0xb8c0, 0xc03e, 0xb8ff, 0xc03e, 0x21, 0 + .dw 0xb940, 0xc03e, 0xb97f, 0xc03e, 0x21, 0 + .dw 0xb9c0, 0xc03e, 0xbfff, 0xc03e, 0x21, 0 + .dw 0xc040, 0xc03e, 0xc07f, 0xc03e, 0x21, 0 + .dw 0xc0c0, 0xc03e, 0xc0ff, 0xc03e, 0x21, 0 + .dw 0xc140, 0xc03e, 0xc17f, 0xc03e, 0x21, 0 + .dw 0xc1c0, 0xc03e, 0xc1ff, 0xc03e, 0x21, 0 + .dw 0xc240, 0xc03e, 0xc27f, 0xc03e, 0x21, 0 + .dw 0xc2c0, 0xc03e, 0xc2ff, 0xc03e, 0x21, 0 + .dw 0xc340, 0xc03e, 0xc37f, 0xc03e, 0x21, 0 + .dw 0xc3c0, 0xc03e, 0xc3ff, 0xc03e, 0x21, 0 + .dw 0xc440, 0xc03e, 0xc47f, 0xc03e, 0x21, 0 + .dw 0xc4c0, 0xc03e, 0xc4ff, 0xc03e, 0x21, 0 + .dw 0xc540, 0xc03e, 0xc57f, 0xc03e, 0x21, 0 + .dw 0xc5c0, 0xc03e, 0xc5ff, 0xc03e, 0x21, 0 + .dw 0xc640, 0xc03e, 0xc67f, 0xc03e, 0x21, 0 + .dw 0xc6c0, 0xc03e, 0xc6ff, 0xc03e, 0x21, 0 + .dw 0xc740, 0xc03e, 0xc77f, 0xc03e, 0x21, 0 + .dw 0xc7c0, 0xc03e, 0xc7ff, 0xc03e, 0x21, 0 + .dw 0xc840, 0xc03e, 0xc87f, 0xc03e, 0x21, 0 + .dw 0xc8c0, 0xc03e, 0xc8ff, 0xc03e, 0x21, 0 + .dw 0xc940, 0xc03e, 0xc97f, 0xc03e, 0x21, 0 + .dw 0xc9c0, 0xc03e, 0xc9ff, 0xc03e, 0x21, 0 + .dw 0xca40, 0xc03e, 0xca7f, 0xc03e, 0x21, 0 + .dw 0xcac0, 0xc03e, 0xcaff, 0xc03e, 0x21, 0 + .dw 0xcb40, 0xc03e, 0xcb7f, 0xc03e, 0x21, 0 + .dw 0xcbc0, 0xc03e, 0xcbff, 0xc03e, 0x21, 0 + .dw 0xcc40, 0xc03e, 0xcc7f, 0xc03e, 0x21, 0 + .dw 0xccc0, 0xc03e, 0xccff, 0xc03e, 0x21, 0 + .dw 0xcd40, 0xc03e, 0xcd7f, 0xc03e, 0x21, 0 + .dw 0xcdc0, 0xc03e, 0xcdff, 0xc03e, 0x21, 0 + .dw 0xce40, 0xc03e, 0xce7f, 0xc03e, 0x21, 0 + .dw 0xcec0, 0xc03e, 0xceff, 0xc03e, 0x21, 0 + .dw 0xcf40, 0xc03e, 0xcf7f, 0xc03e, 0x21, 0 + .dw 0xcfc0, 0xc03e, 0xcfff, 0xc03e, 0x21, 0 + .dw 0xd040, 0xc03e, 0xd07f, 0xc03e, 0x21, 0 + .dw 0xd0c0, 0xc03e, 0xd0ff, 0xc03e, 0x21, 0 + .dw 0xd140, 0xc03e, 0xd17f, 0xc03e, 0x21, 0 + .dw 0xd1c0, 0xc03e, 0xd1ff, 0xc03e, 0x21, 0 + .dw 0xd240, 0xc03e, 0xd27f, 0xc03e, 0x21, 0 + .dw 0xd2c0, 0xc03e, 0xd2ff, 0xc03e, 0x21, 0 + .dw 0xd340, 0xc03e, 0xd37f, 0xc03e, 0x21, 0 + .dw 0xd3c0, 0xc03e, 0xd3ff, 0xc03e, 0x21, 0 + .dw 0xd440, 0xc03e, 0xd47f, 0xc03e, 0x21, 0 + .dw 0xd4c0, 0xc03e, 0xd4ff, 0xc03e, 0x21, 0 + .dw 0xd540, 0xc03e, 0xd57f, 0xc03e, 0x21, 0 + .dw 0xd5c0, 0xc03e, 0xd5ff, 0xc03e, 0x21, 0 + .dw 0xd640, 0xc03e, 0xd67f, 0xc03e, 0x21, 0 + .dw 0xd6c0, 0xc03e, 0xd6ff, 0xc03e, 0x21, 0 + .dw 0xd740, 0xc03e, 0xd77f, 0xc03e, 0x21, 0 + .dw 0xd7c0, 0xc03e, 0xd7ff, 0xc03e, 0x21, 0 + .dw 0xd840, 0xc03e, 0xd87f, 0xc03e, 0x21, 0 + .dw 0xd8c0, 0xc03e, 0xd8ff, 0xc03e, 0x21, 0 + .dw 0xd940, 0xc03e, 0xd97f, 0xc03e, 0x21, 0 + .dw 0xd9c0, 0xc03e, 0xdfff, 0xc03e, 0x21, 0 + .dw 0xe040, 0xc03e, 0xe07f, 0xc03e, 0x21, 0 + .dw 0xe0c0, 0xc03e, 0xe0ff, 0xc03e, 0x21, 0 + .dw 0xe140, 0xc03e, 0xe17f, 0xc03e, 0x21, 0 + .dw 0xe1c0, 0xc03e, 0xe1ff, 0xc03e, 0x21, 0 + .dw 0xe240, 0xc03e, 0xe27f, 0xc03e, 0x21, 0 + .dw 0xe2c0, 0xc03e, 0xe2ff, 0xc03e, 0x21, 0 + .dw 0xe340, 0xc03e, 0xe37f, 0xc03e, 0x21, 0 + .dw 0xe3c0, 0xc03e, 0xe3ff, 0xc03e, 0x21, 0 + .dw 0xe440, 0xc03e, 0xe47f, 0xc03e, 0x21, 0 + .dw 0xe4c0, 0xc03e, 0xe4ff, 0xc03e, 0x21, 0 + .dw 0xe540, 0xc03e, 0xe57f, 0xc03e, 0x21, 0 + .dw 0xe5c0, 0xc03e, 0xe5ff, 0xc03e, 0x21, 0 + .dw 0xe640, 0xc03e, 0xe67f, 0xc03e, 0x21, 0 + .dw 0xe6c0, 0xc03e, 0xe6ff, 0xc03e, 0x21, 0 + .dw 0xe740, 0xc03e, 0xe77f, 0xc03e, 0x21, 0 + .dw 0xe7c0, 0xc03e, 0xe7ff, 0xc03e, 0x21, 0 + .dw 0xe840, 0xc03e, 0xe87f, 0xc03e, 0x21, 0 + .dw 0xe8c0, 0xc03e, 0xe8ff, 0xc03e, 0x21, 0 + .dw 0xe940, 0xc03e, 0xe97f, 0xc03e, 0x21, 0 + .dw 0xe9c0, 0xc03e, 0xe9ff, 0xc03e, 0x21, 0 + .dw 0xea40, 0xc03e, 0xea7f, 0xc03e, 0x21, 0 + .dw 0xeac0, 0xc03e, 0xeaff, 0xc03e, 0x21, 0 + .dw 0xeb40, 0xc03e, 0xeb7f, 0xc03e, 0x21, 0 + .dw 0xebc0, 0xc03e, 0xebff, 0xc03e, 0x21, 0 + .dw 0xec40, 0xc03e, 0xec7f, 0xc03e, 0x21, 0 + .dw 0xecc0, 0xc03e, 0xecff, 0xc03e, 0x21, 0 + .dw 0xed40, 0xc03e, 0xed7f, 0xc03e, 0x21, 0 + .dw 0xedc0, 0xc03e, 0xedff, 0xc03e, 0x21, 0 + .dw 0xee40, 0xc03e, 0xee7f, 0xc03e, 0x21, 0 + .dw 0xeec0, 0xc03e, 0xeeff, 0xc03e, 0x21, 0 + .dw 0xef40, 0xc03e, 0xef7f, 0xc03e, 0x21, 0 + .dw 0xefc0, 0xc03e, 0xefff, 0xc03e, 0x21, 0 + .dw 0xf040, 0xc03e, 0xf07f, 0xc03e, 0x21, 0 + .dw 0xf0c0, 0xc03e, 0xf0ff, 0xc03e, 0x21, 0 + .dw 0xf140, 0xc03e, 0xf17f, 0xc03e, 0x21, 0 + .dw 0xf1c0, 0xc03e, 0xf1ff, 0xc03e, 0x21, 0 + .dw 0xf240, 0xc03e, 0xf27f, 0xc03e, 0x21, 0 + .dw 0xf2c0, 0xc03e, 0xf2ff, 0xc03e, 0x21, 0 + .dw 0xf340, 0xc03e, 0xf37f, 0xc03e, 0x21, 0 + .dw 0xf3c0, 0xc03e, 0xf3ff, 0xc03e, 0x21, 0 + .dw 0xf440, 0xc03e, 0xf47f, 0xc03e, 0x21, 0 + .dw 0xf4c0, 0xc03e, 0xf4ff, 0xc03e, 0x21, 0 + .dw 0xf540, 0xc03e, 0xf57f, 0xc03e, 0x21, 0 + .dw 0xf5c0, 0xc03e, 0xf5ff, 0xc03e, 0x21, 0 + .dw 0xf640, 0xc03e, 0xf67f, 0xc03e, 0x21, 0 + .dw 0xf6c0, 0xc03e, 0xf6ff, 0xc03e, 0x21, 0 + .dw 0xf740, 0xc03e, 0xf77f, 0xc03e, 0x21, 0 + .dw 0xf7c0, 0xc03e, 0xf7ff, 0xc03e, 0x21, 0 + .dw 0xf840, 0xc03e, 0xf87f, 0xc03e, 0x21, 0 + .dw 0xf8c0, 0xc03e, 0xf8ff, 0xc03e, 0x21, 0 + .dw 0xf940, 0xc03e, 0xf97f, 0xc03e, 0x21, 0 + .dw 0xf9c0, 0xc03e, 0xffff, 0xc03e, 0x21, 0 + .dw 0x0040, 0xc03f, 0x007f, 0xc03f, 0x21, 0 + .dw 0x00c0, 0xc03f, 0x00ff, 0xc03f, 0x21, 0 + .dw 0x0140, 0xc03f, 0x017f, 0xc03f, 0x21, 0 + .dw 0x01c0, 0xc03f, 0x01ff, 0xc03f, 0x21, 0 + .dw 0x0240, 0xc03f, 0x027f, 0xc03f, 0x21, 0 + .dw 0x02c0, 0xc03f, 0x02ff, 0xc03f, 0x21, 0 + .dw 0x0340, 0xc03f, 0x037f, 0xc03f, 0x21, 0 + .dw 0x03c0, 0xc03f, 0x03ff, 0xc03f, 0x21, 0 + .dw 0x0440, 0xc03f, 0x047f, 0xc03f, 0x21, 0 + .dw 0x04c0, 0xc03f, 0x04ff, 0xc03f, 0x21, 0 + .dw 0x0540, 0xc03f, 0x057f, 0xc03f, 0x21, 0 + .dw 0x05c0, 0xc03f, 0x05ff, 0xc03f, 0x21, 0 + .dw 0x0640, 0xc03f, 0x067f, 0xc03f, 0x21, 0 + .dw 0x06c0, 0xc03f, 0x06ff, 0xc03f, 0x21, 0 + .dw 0x0740, 0xc03f, 0x077f, 0xc03f, 0x21, 0 + .dw 0x07c0, 0xc03f, 0x07ff, 0xc03f, 0x21, 0 + .dw 0x0840, 0xc03f, 0x087f, 0xc03f, 0x21, 0 + .dw 0x08c0, 0xc03f, 0x08ff, 0xc03f, 0x21, 0 + .dw 0x0940, 0xc03f, 0x097f, 0xc03f, 0x21, 0 + .dw 0x09c0, 0xc03f, 0x09ff, 0xc03f, 0x21, 0 + .dw 0x0a40, 0xc03f, 0x0a7f, 0xc03f, 0x21, 0 + .dw 0x0ac0, 0xc03f, 0x0aff, 0xc03f, 0x21, 0 + .dw 0x0b40, 0xc03f, 0x0b7f, 0xc03f, 0x21, 0 + .dw 0x0bc0, 0xc03f, 0x0bff, 0xc03f, 0x21, 0 + .dw 0x0c40, 0xc03f, 0x0c7f, 0xc03f, 0x21, 0 + .dw 0x0cc0, 0xc03f, 0x0cff, 0xc03f, 0x21, 0 + .dw 0x0d40, 0xc03f, 0x0d7f, 0xc03f, 0x21, 0 + .dw 0x0dc0, 0xc03f, 0x0dff, 0xc03f, 0x21, 0 + .dw 0x0e40, 0xc03f, 0x0e7f, 0xc03f, 0x21, 0 + .dw 0x0ec0, 0xc03f, 0x0eff, 0xc03f, 0x21, 0 + .dw 0x0f40, 0xc03f, 0x0f7f, 0xc03f, 0x21, 0 + .dw 0x0fc0, 0xc03f, 0x0fff, 0xc03f, 0x21, 0 + .dw 0x1040, 0xc03f, 0x107f, 0xc03f, 0x21, 0 + .dw 0x10c0, 0xc03f, 0x10ff, 0xc03f, 0x21, 0 + .dw 0x1140, 0xc03f, 0x117f, 0xc03f, 0x21, 0 + .dw 0x11c0, 0xc03f, 0x11ff, 0xc03f, 0x21, 0 + .dw 0x1240, 0xc03f, 0x127f, 0xc03f, 0x21, 0 + .dw 0x12c0, 0xc03f, 0x12ff, 0xc03f, 0x21, 0 + .dw 0x1340, 0xc03f, 0x137f, 0xc03f, 0x21, 0 + .dw 0x13c0, 0xc03f, 0x13ff, 0xc03f, 0x21, 0 + .dw 0x1440, 0xc03f, 0x147f, 0xc03f, 0x21, 0 + .dw 0x14c0, 0xc03f, 0x14ff, 0xc03f, 0x21, 0 + .dw 0x1540, 0xc03f, 0x157f, 0xc03f, 0x21, 0 + .dw 0x15c0, 0xc03f, 0x15ff, 0xc03f, 0x21, 0 + .dw 0x1640, 0xc03f, 0x167f, 0xc03f, 0x21, 0 + .dw 0x16c0, 0xc03f, 0x16ff, 0xc03f, 0x21, 0 + .dw 0x1740, 0xc03f, 0x177f, 0xc03f, 0x21, 0 + .dw 0x17c0, 0xc03f, 0x17ff, 0xc03f, 0x21, 0 + .dw 0x1840, 0xc03f, 0x187f, 0xc03f, 0x21, 0 + .dw 0x18c0, 0xc03f, 0x18ff, 0xc03f, 0x21, 0 + .dw 0x1940, 0xc03f, 0x197f, 0xc03f, 0x21, 0 + .dw 0x19c0, 0xc03f, 0x1fff, 0xc03f, 0x21, 0 + .dw 0x2040, 0xc03f, 0x207f, 0xc03f, 0x21, 0 + .dw 0x20c0, 0xc03f, 0x20ff, 0xc03f, 0x21, 0 + .dw 0x2140, 0xc03f, 0x217f, 0xc03f, 0x21, 0 + .dw 0x21c0, 0xc03f, 0x21ff, 0xc03f, 0x21, 0 + .dw 0x2240, 0xc03f, 0x227f, 0xc03f, 0x21, 0 + .dw 0x22c0, 0xc03f, 0x22ff, 0xc03f, 0x21, 0 + .dw 0x2340, 0xc03f, 0x237f, 0xc03f, 0x21, 0 + .dw 0x23c0, 0xc03f, 0x23ff, 0xc03f, 0x21, 0 + .dw 0x2440, 0xc03f, 0x247f, 0xc03f, 0x21, 0 + .dw 0x24c0, 0xc03f, 0x24ff, 0xc03f, 0x21, 0 + .dw 0x2540, 0xc03f, 0x257f, 0xc03f, 0x21, 0 + .dw 0x25c0, 0xc03f, 0x25ff, 0xc03f, 0x21, 0 + .dw 0x2640, 0xc03f, 0x267f, 0xc03f, 0x21, 0 + .dw 0x26c0, 0xc03f, 0x26ff, 0xc03f, 0x21, 0 + .dw 0x2740, 0xc03f, 0x277f, 0xc03f, 0x21, 0 + .dw 0x27c0, 0xc03f, 0x27ff, 0xc03f, 0x21, 0 + .dw 0x2840, 0xc03f, 0x287f, 0xc03f, 0x21, 0 + .dw 0x28c0, 0xc03f, 0x28ff, 0xc03f, 0x21, 0 + .dw 0x2940, 0xc03f, 0x297f, 0xc03f, 0x21, 0 + .dw 0x29c0, 0xc03f, 0x29ff, 0xc03f, 0x21, 0 + .dw 0x2a40, 0xc03f, 0x2a7f, 0xc03f, 0x21, 0 + .dw 0x2ac0, 0xc03f, 0x2aff, 0xc03f, 0x21, 0 + .dw 0x2b40, 0xc03f, 0x2b7f, 0xc03f, 0x21, 0 + .dw 0x2bc0, 0xc03f, 0x2bff, 0xc03f, 0x21, 0 + .dw 0x2c40, 0xc03f, 0x2c7f, 0xc03f, 0x21, 0 + .dw 0x2cc0, 0xc03f, 0x2cff, 0xc03f, 0x21, 0 + .dw 0x2d40, 0xc03f, 0x2d7f, 0xc03f, 0x21, 0 + .dw 0x2dc0, 0xc03f, 0x2dff, 0xc03f, 0x21, 0 + .dw 0x2e40, 0xc03f, 0x2e7f, 0xc03f, 0x21, 0 + .dw 0x2ec0, 0xc03f, 0x2eff, 0xc03f, 0x21, 0 + .dw 0x2f40, 0xc03f, 0x2f7f, 0xc03f, 0x21, 0 + .dw 0x2fc0, 0xc03f, 0x2fff, 0xc03f, 0x21, 0 + .dw 0x3040, 0xc03f, 0x307f, 0xc03f, 0x21, 0 + .dw 0x30c0, 0xc03f, 0x30ff, 0xc03f, 0x21, 0 + .dw 0x3140, 0xc03f, 0x317f, 0xc03f, 0x21, 0 + .dw 0x31c0, 0xc03f, 0x31ff, 0xc03f, 0x21, 0 + .dw 0x3240, 0xc03f, 0x327f, 0xc03f, 0x21, 0 + .dw 0x32c0, 0xc03f, 0x32ff, 0xc03f, 0x21, 0 + .dw 0x3340, 0xc03f, 0x337f, 0xc03f, 0x21, 0 + .dw 0x33c0, 0xc03f, 0x33ff, 0xc03f, 0x21, 0 + .dw 0x3440, 0xc03f, 0x347f, 0xc03f, 0x21, 0 + .dw 0x34c0, 0xc03f, 0x34ff, 0xc03f, 0x21, 0 + .dw 0x3540, 0xc03f, 0x357f, 0xc03f, 0x21, 0 + .dw 0x35c0, 0xc03f, 0x35ff, 0xc03f, 0x21, 0 + .dw 0x3640, 0xc03f, 0x367f, 0xc03f, 0x21, 0 + .dw 0x36c0, 0xc03f, 0x36ff, 0xc03f, 0x21, 0 + .dw 0x3740, 0xc03f, 0x377f, 0xc03f, 0x21, 0 + .dw 0x37c0, 0xc03f, 0x37ff, 0xc03f, 0x21, 0 + .dw 0x3840, 0xc03f, 0x387f, 0xc03f, 0x21, 0 + .dw 0x38c0, 0xc03f, 0x38ff, 0xc03f, 0x21, 0 + .dw 0x3940, 0xc03f, 0x397f, 0xc03f, 0x21, 0 + .dw 0x39c0, 0xc03f, 0x1fff, 0xc040, 0x21, 0 + .dw 0x3a00, 0xc040, 0x5fff, 0xc040, 0x21, 0 + .dw 0x7a00, 0xc040, 0x9fff, 0xc040, 0x21, 0 + .dw 0xba00, 0xc040, 0xdfff, 0xc040, 0x21, 0 + .dw 0xfa00, 0xc040, 0x1fff, 0xc041, 0x21, 0 + .dw 0x3a00, 0xc041, 0x5fff, 0xc041, 0x21, 0 + .dw 0x7a00, 0xc041, 0x9fff, 0xc041, 0x21, 0 + .dw 0xba00, 0xc041, 0xdfff, 0xc041, 0x21, 0 + .dw 0xfa00, 0xc041, 0x1fff, 0xc042, 0x21, 0 + .dw 0x3a00, 0xc042, 0x5fff, 0xc042, 0x21, 0 + .dw 0x7a00, 0xc042, 0x9fff, 0xc042, 0x21, 0 + .dw 0xba00, 0xc042, 0xdfff, 0xc042, 0x21, 0 + .dw 0xfa00, 0xc042, 0x1fff, 0xc043, 0x21, 0 + .dw 0x3a00, 0xc043, 0xffff, 0xc043, 0x21, 0 + .dw 0x1a00, 0xc044, 0x1fff, 0xc044, 0x21, 0 + .dw 0x3a00, 0xc044, 0x3fff, 0xc044, 0x21, 0 + .dw 0x5a00, 0xc044, 0x5fff, 0xc044, 0x21, 0 + .dw 0x7a00, 0xc044, 0x7fff, 0xc044, 0x21, 0 + .dw 0x9a00, 0xc044, 0x9fff, 0xc044, 0x21, 0 + .dw 0xba00, 0xc044, 0xbfff, 0xc044, 0x21, 0 + .dw 0xda00, 0xc044, 0xdfff, 0xc044, 0x21, 0 + .dw 0xfa00, 0xc044, 0xffff, 0xc044, 0x21, 0 + .dw 0x1a00, 0xc045, 0x1fff, 0xc045, 0x21, 0 + .dw 0x3a00, 0xc045, 0x3fff, 0xc045, 0x21, 0 + .dw 0x5a00, 0xc045, 0x5fff, 0xc045, 0x21, 0 + .dw 0x7a00, 0xc045, 0x7fff, 0xc045, 0x21, 0 + .dw 0x9a00, 0xc045, 0x9fff, 0xc045, 0x21, 0 + .dw 0xba00, 0xc045, 0xbfff, 0xc045, 0x21, 0 + .dw 0xda00, 0xc045, 0xdfff, 0xc045, 0x21, 0 + .dw 0xfa00, 0xc045, 0xffff, 0xc045, 0x21, 0 + .dw 0x1a00, 0xc046, 0x1fff, 0xc046, 0x21, 0 + .dw 0x3a00, 0xc046, 0x3fff, 0xc046, 0x21, 0 + .dw 0x5a00, 0xc046, 0x5fff, 0xc046, 0x21, 0 + .dw 0x7a00, 0xc046, 0x7fff, 0xc046, 0x21, 0 + .dw 0x9a00, 0xc046, 0x9fff, 0xc046, 0x21, 0 + .dw 0xba00, 0xc046, 0xbfff, 0xc046, 0x21, 0 + .dw 0xda00, 0xc046, 0xdfff, 0xc046, 0x21, 0 + .dw 0xfa00, 0xc046, 0xffff, 0xc046, 0x21, 0 + .dw 0x1a00, 0xc047, 0x1fff, 0xc047, 0x21, 0 + .dw 0x3a00, 0xc047, 0x1fff, 0xc050, 0x21, 0 + .dw 0x3a00, 0xc050, 0x5fff, 0xc050, 0x21, 0 + .dw 0x7a00, 0xc050, 0x9fff, 0xc050, 0x21, 0 + .dw 0xba00, 0xc050, 0xdfff, 0xc050, 0x21, 0 + .dw 0xfa00, 0xc050, 0x1fff, 0xc051, 0x21, 0 + .dw 0x3a00, 0xc051, 0x5fff, 0xc051, 0x21, 0 + .dw 0x7a00, 0xc051, 0x9fff, 0xc051, 0x21, 0 + .dw 0xba00, 0xc051, 0xdfff, 0xc051, 0x21, 0 + .dw 0xfa00, 0xc051, 0x1fff, 0xc052, 0x21, 0 + .dw 0x3a00, 0xc052, 0x5fff, 0xc052, 0x21, 0 + .dw 0x7a00, 0xc052, 0x9fff, 0xc052, 0x21, 0 + .dw 0xba00, 0xc052, 0xdfff, 0xc052, 0x21, 0 + .dw 0xfa00, 0xc052, 0xffff, 0xc053, 0x21, 0 + .dw 0x1a00, 0xc054, 0x1fff, 0xc054, 0x21, 0 + .dw 0x3a00, 0xc054, 0x3fff, 0xc054, 0x21, 0 + .dw 0x5a00, 0xc054, 0x5fff, 0xc054, 0x21, 0 + .dw 0x7a00, 0xc054, 0x7fff, 0xc054, 0x21, 0 + .dw 0x9a00, 0xc054, 0x9fff, 0xc054, 0x21, 0 + .dw 0xba00, 0xc054, 0xbfff, 0xc054, 0x21, 0 + .dw 0xda00, 0xc054, 0xdfff, 0xc054, 0x21, 0 + .dw 0xfa00, 0xc054, 0xffff, 0xc054, 0x21, 0 + .dw 0x1a00, 0xc055, 0x1fff, 0xc055, 0x21, 0 + .dw 0x3a00, 0xc055, 0x3fff, 0xc055, 0x21, 0 + .dw 0x5a00, 0xc055, 0x5fff, 0xc055, 0x21, 0 + .dw 0x7a00, 0xc055, 0x7fff, 0xc055, 0x21, 0 + .dw 0x9a00, 0xc055, 0x9fff, 0xc055, 0x21, 0 + .dw 0xba00, 0xc055, 0xbfff, 0xc055, 0x21, 0 + .dw 0xda00, 0xc055, 0xdfff, 0xc055, 0x21, 0 + .dw 0xfa00, 0xc055, 0xffff, 0xc055, 0x21, 0 + .dw 0x1a00, 0xc056, 0x1fff, 0xc056, 0x21, 0 + .dw 0x3a00, 0xc056, 0x3fff, 0xc056, 0x21, 0 + .dw 0x5a00, 0xc056, 0x5fff, 0xc056, 0x21, 0 + .dw 0x7a00, 0xc056, 0x7fff, 0xc056, 0x21, 0 + .dw 0x9a00, 0xc056, 0x9fff, 0xc056, 0x21, 0 + .dw 0xba00, 0xc056, 0xbfff, 0xc056, 0x21, 0 + .dw 0xda00, 0xc056, 0xdfff, 0xc056, 0x21, 0 + .dw 0xfa00, 0xc056, 0xffff, 0xc056, 0x21, 0 + .dw 0x1a00, 0xc057, 0x1fff, 0xc057, 0x21, 0 + .dw 0x3a00, 0xc057, 0xffff, 0xc05f, 0x21, 0 + .dw 0x1a00, 0xc060, 0x3fff, 0xc060, 0x21, 0 + .dw 0x5a00, 0xc060, 0x7fff, 0xc060, 0x21, 0 + .dw 0x9a00, 0xc060, 0xbfff, 0xc060, 0x21, 0 + .dw 0xda00, 0xc060, 0xffff, 0xc060, 0x21, 0 + .dw 0x1a00, 0xc061, 0x3fff, 0xc061, 0x21, 0 + .dw 0x5a00, 0xc061, 0x7fff, 0xc061, 0x21, 0 + .dw 0x9a00, 0xc061, 0xbfff, 0xc061, 0x21, 0 + .dw 0xda00, 0xc061, 0xffff, 0xc061, 0x21, 0 + .dw 0x1a00, 0xc062, 0x3fff, 0xc062, 0x21, 0 + .dw 0x5a00, 0xc062, 0x7fff, 0xc062, 0x21, 0 + .dw 0x9a00, 0xc062, 0xbfff, 0xc062, 0x21, 0 + .dw 0xda00, 0xc062, 0xffff, 0xc062, 0x21, 0 + .dw 0x1a00, 0xc063, 0xffff, 0xc06f, 0x21, 0 + .dw 0x1a00, 0xc070, 0x3fff, 0xc070, 0x21, 0 + .dw 0x5a00, 0xc070, 0x7fff, 0xc070, 0x21, 0 + .dw 0x9a00, 0xc070, 0xbfff, 0xc070, 0x21, 0 + .dw 0xda00, 0xc070, 0xffff, 0xc070, 0x21, 0 + .dw 0x1a00, 0xc071, 0x3fff, 0xc071, 0x21, 0 + .dw 0x5a00, 0xc071, 0x7fff, 0xc071, 0x21, 0 + .dw 0x9a00, 0xc071, 0xbfff, 0xc071, 0x21, 0 + .dw 0xda00, 0xc071, 0xffff, 0xc071, 0x21, 0 + .dw 0x1a00, 0xc072, 0x3fff, 0xc072, 0x21, 0 + .dw 0x5a00, 0xc072, 0x7fff, 0xc072, 0x21, 0 + .dw 0x9a00, 0xc072, 0xbfff, 0xc072, 0x21, 0 + .dw 0xda00, 0xc072, 0xffff, 0xc07f, 0x21, 0 + .dw 0x1a00, 0xc080, 0x1fff, 0xc080, 0x21, 0 + .dw 0x3a00, 0xc080, 0x3fff, 0xc080, 0x21, 0 + .dw 0x5a00, 0xc080, 0x5fff, 0xc080, 0x21, 0 + .dw 0x7a00, 0xc080, 0x7fff, 0xc080, 0x21, 0 + .dw 0x9a00, 0xc080, 0x9fff, 0xc080, 0x21, 0 + .dw 0xba00, 0xc080, 0xbfff, 0xc080, 0x21, 0 + .dw 0xda00, 0xc080, 0xdfff, 0xc080, 0x21, 0 + .dw 0xfa00, 0xc080, 0xffff, 0xc080, 0x21, 0 + .dw 0x1a00, 0xc081, 0x1fff, 0xc081, 0x21, 0 + .dw 0x3a00, 0xc081, 0x3fff, 0xc081, 0x21, 0 + .dw 0x5a00, 0xc081, 0x5fff, 0xc081, 0x21, 0 + .dw 0x7a00, 0xc081, 0x7fff, 0xc081, 0x21, 0 + .dw 0x9a00, 0xc081, 0x9fff, 0xc081, 0x21, 0 + .dw 0xba00, 0xc081, 0xbfff, 0xc081, 0x21, 0 + .dw 0xda00, 0xc081, 0xdfff, 0xc081, 0x21, 0 + .dw 0xfa00, 0xc081, 0xffff, 0xc081, 0x21, 0 + .dw 0x1a00, 0xc082, 0x1fff, 0xc082, 0x21, 0 + .dw 0x3a00, 0xc082, 0x3fff, 0xc082, 0x21, 0 + .dw 0x5a00, 0xc082, 0x5fff, 0xc082, 0x21, 0 + .dw 0x7a00, 0xc082, 0x7fff, 0xc082, 0x21, 0 + .dw 0x9a00, 0xc082, 0x9fff, 0xc082, 0x21, 0 + .dw 0xba00, 0xc082, 0xbfff, 0xc082, 0x21, 0 + .dw 0xda00, 0xc082, 0xdfff, 0xc082, 0x21, 0 + .dw 0xfa00, 0xc082, 0xffff, 0xc082, 0x21, 0 + .dw 0x1a00, 0xc083, 0x1fff, 0xc083, 0x21, 0 + .dw 0x3a00, 0xc083, 0xffff, 0xc083, 0x21, 0 + .dw 0x1a00, 0xc084, 0x1fff, 0xc084, 0x21, 0 + .dw 0x3a00, 0xc084, 0x3fff, 0xc084, 0x21, 0 + .dw 0x5a00, 0xc084, 0x5fff, 0xc084, 0x21, 0 + .dw 0x7a00, 0xc084, 0x7fff, 0xc084, 0x21, 0 + .dw 0x9a00, 0xc084, 0x9fff, 0xc084, 0x21, 0 + .dw 0xba00, 0xc084, 0xbfff, 0xc084, 0x21, 0 + .dw 0xda00, 0xc084, 0xdfff, 0xc084, 0x21, 0 + .dw 0xfa00, 0xc084, 0xffff, 0xc084, 0x21, 0 + .dw 0x1a00, 0xc085, 0x1fff, 0xc085, 0x21, 0 + .dw 0x3a00, 0xc085, 0x3fff, 0xc085, 0x21, 0 + .dw 0x5a00, 0xc085, 0x5fff, 0xc085, 0x21, 0 + .dw 0x7a00, 0xc085, 0x7fff, 0xc085, 0x21, 0 + .dw 0x9a00, 0xc085, 0x9fff, 0xc085, 0x21, 0 + .dw 0xba00, 0xc085, 0xbfff, 0xc085, 0x21, 0 + .dw 0xda00, 0xc085, 0xdfff, 0xc085, 0x21, 0 + .dw 0xfa00, 0xc085, 0xffff, 0xc085, 0x21, 0 + .dw 0x1a00, 0xc086, 0x1fff, 0xc086, 0x21, 0 + .dw 0x3a00, 0xc086, 0x3fff, 0xc086, 0x21, 0 + .dw 0x5a00, 0xc086, 0x5fff, 0xc086, 0x21, 0 + .dw 0x7a00, 0xc086, 0x7fff, 0xc086, 0x21, 0 + .dw 0x9a00, 0xc086, 0x9fff, 0xc086, 0x21, 0 + .dw 0xba00, 0xc086, 0xbfff, 0xc086, 0x21, 0 + .dw 0xda00, 0xc086, 0xdfff, 0xc086, 0x21, 0 + .dw 0xfa00, 0xc086, 0xffff, 0xc086, 0x21, 0 + .dw 0x1a00, 0xc087, 0x1fff, 0xc087, 0x21, 0 + .dw 0x3a00, 0xc087, 0x1fff, 0xc088, 0x21, 0 + .dw 0x2040, 0xc088, 0x207f, 0xc088, 0x21, 0 + .dw 0x20c0, 0xc088, 0x20ff, 0xc088, 0x21, 0 + .dw 0x2140, 0xc088, 0x217f, 0xc088, 0x21, 0 + .dw 0x21c0, 0xc088, 0x21ff, 0xc088, 0x21, 0 + .dw 0x2240, 0xc088, 0x227f, 0xc088, 0x21, 0 + .dw 0x22c0, 0xc088, 0x22ff, 0xc088, 0x21, 0 + .dw 0x2340, 0xc088, 0x237f, 0xc088, 0x21, 0 + .dw 0x23c0, 0xc088, 0x23ff, 0xc088, 0x21, 0 + .dw 0x2440, 0xc088, 0x247f, 0xc088, 0x21, 0 + .dw 0x24c0, 0xc088, 0x24ff, 0xc088, 0x21, 0 + .dw 0x2540, 0xc088, 0x257f, 0xc088, 0x21, 0 + .dw 0x25c0, 0xc088, 0x25ff, 0xc088, 0x21, 0 + .dw 0x2640, 0xc088, 0x267f, 0xc088, 0x21, 0 + .dw 0x26c0, 0xc088, 0x26ff, 0xc088, 0x21, 0 + .dw 0x2740, 0xc088, 0x277f, 0xc088, 0x21, 0 + .dw 0x27c0, 0xc088, 0x27ff, 0xc088, 0x21, 0 + .dw 0x2840, 0xc088, 0x287f, 0xc088, 0x21, 0 + .dw 0x28c0, 0xc088, 0x28ff, 0xc088, 0x21, 0 + .dw 0x2940, 0xc088, 0x297f, 0xc088, 0x21, 0 + .dw 0x29c0, 0xc088, 0x29ff, 0xc088, 0x21, 0 + .dw 0x2a40, 0xc088, 0x2a7f, 0xc088, 0x21, 0 + .dw 0x2ac0, 0xc088, 0x2aff, 0xc088, 0x21, 0 + .dw 0x2b40, 0xc088, 0x2b7f, 0xc088, 0x21, 0 + .dw 0x2bc0, 0xc088, 0x2bff, 0xc088, 0x21, 0 + .dw 0x2c40, 0xc088, 0x2c7f, 0xc088, 0x21, 0 + .dw 0x2cc0, 0xc088, 0x2cff, 0xc088, 0x21, 0 + .dw 0x2d40, 0xc088, 0x2d7f, 0xc088, 0x21, 0 + .dw 0x2dc0, 0xc088, 0x2dff, 0xc088, 0x21, 0 + .dw 0x2e40, 0xc088, 0x2e7f, 0xc088, 0x21, 0 + .dw 0x2ec0, 0xc088, 0x2eff, 0xc088, 0x21, 0 + .dw 0x2f40, 0xc088, 0x2f7f, 0xc088, 0x21, 0 + .dw 0x2fc0, 0xc088, 0x2fff, 0xc088, 0x21, 0 + .dw 0x3040, 0xc088, 0x307f, 0xc088, 0x21, 0 + .dw 0x30c0, 0xc088, 0x30ff, 0xc088, 0x21, 0 + .dw 0x3140, 0xc088, 0x317f, 0xc088, 0x21, 0 + .dw 0x31c0, 0xc088, 0x31ff, 0xc088, 0x21, 0 + .dw 0x3240, 0xc088, 0x327f, 0xc088, 0x21, 0 + .dw 0x32c0, 0xc088, 0x32ff, 0xc088, 0x21, 0 + .dw 0x3340, 0xc088, 0x337f, 0xc088, 0x21, 0 + .dw 0x33c0, 0xc088, 0x33ff, 0xc088, 0x21, 0 + .dw 0x3440, 0xc088, 0x347f, 0xc088, 0x21, 0 + .dw 0x34c0, 0xc088, 0x34ff, 0xc088, 0x21, 0 + .dw 0x3540, 0xc088, 0x357f, 0xc088, 0x21, 0 + .dw 0x35c0, 0xc088, 0x35ff, 0xc088, 0x21, 0 + .dw 0x3640, 0xc088, 0x367f, 0xc088, 0x21, 0 + .dw 0x36c0, 0xc088, 0x36ff, 0xc088, 0x21, 0 + .dw 0x3740, 0xc088, 0x377f, 0xc088, 0x21, 0 + .dw 0x37c0, 0xc088, 0x37ff, 0xc088, 0x21, 0 + .dw 0x3840, 0xc088, 0x387f, 0xc088, 0x21, 0 + .dw 0x38c0, 0xc088, 0x38ff, 0xc088, 0x21, 0 + .dw 0x3940, 0xc088, 0x397f, 0xc088, 0x21, 0 + .dw 0x39c0, 0xc088, 0x5fff, 0xc088, 0x21, 0 + .dw 0x6040, 0xc088, 0x607f, 0xc088, 0x21, 0 + .dw 0x60c0, 0xc088, 0x60ff, 0xc088, 0x21, 0 + .dw 0x6140, 0xc088, 0x617f, 0xc088, 0x21, 0 + .dw 0x61c0, 0xc088, 0x61ff, 0xc088, 0x21, 0 + .dw 0x6240, 0xc088, 0x627f, 0xc088, 0x21, 0 + .dw 0x62c0, 0xc088, 0x62ff, 0xc088, 0x21, 0 + .dw 0x6340, 0xc088, 0x637f, 0xc088, 0x21, 0 + .dw 0x63c0, 0xc088, 0x63ff, 0xc088, 0x21, 0 + .dw 0x6440, 0xc088, 0x647f, 0xc088, 0x21, 0 + .dw 0x64c0, 0xc088, 0x64ff, 0xc088, 0x21, 0 + .dw 0x6540, 0xc088, 0x657f, 0xc088, 0x21, 0 + .dw 0x65c0, 0xc088, 0x65ff, 0xc088, 0x21, 0 + .dw 0x6640, 0xc088, 0x667f, 0xc088, 0x21, 0 + .dw 0x66c0, 0xc088, 0x66ff, 0xc088, 0x21, 0 + .dw 0x6740, 0xc088, 0x677f, 0xc088, 0x21, 0 + .dw 0x67c0, 0xc088, 0x67ff, 0xc088, 0x21, 0 + .dw 0x6840, 0xc088, 0x687f, 0xc088, 0x21, 0 + .dw 0x68c0, 0xc088, 0x68ff, 0xc088, 0x21, 0 + .dw 0x6940, 0xc088, 0x697f, 0xc088, 0x21, 0 + .dw 0x69c0, 0xc088, 0x69ff, 0xc088, 0x21, 0 + .dw 0x6a40, 0xc088, 0x6a7f, 0xc088, 0x21, 0 + .dw 0x6ac0, 0xc088, 0x6aff, 0xc088, 0x21, 0 + .dw 0x6b40, 0xc088, 0x6b7f, 0xc088, 0x21, 0 + .dw 0x6bc0, 0xc088, 0x6bff, 0xc088, 0x21, 0 + .dw 0x6c40, 0xc088, 0x6c7f, 0xc088, 0x21, 0 + .dw 0x6cc0, 0xc088, 0x6cff, 0xc088, 0x21, 0 + .dw 0x6d40, 0xc088, 0x6d7f, 0xc088, 0x21, 0 + .dw 0x6dc0, 0xc088, 0x6dff, 0xc088, 0x21, 0 + .dw 0x6e40, 0xc088, 0x6e7f, 0xc088, 0x21, 0 + .dw 0x6ec0, 0xc088, 0x6eff, 0xc088, 0x21, 0 + .dw 0x6f40, 0xc088, 0x6f7f, 0xc088, 0x21, 0 + .dw 0x6fc0, 0xc088, 0x6fff, 0xc088, 0x21, 0 + .dw 0x7040, 0xc088, 0x707f, 0xc088, 0x21, 0 + .dw 0x70c0, 0xc088, 0x70ff, 0xc088, 0x21, 0 + .dw 0x7140, 0xc088, 0x717f, 0xc088, 0x21, 0 + .dw 0x71c0, 0xc088, 0x71ff, 0xc088, 0x21, 0 + .dw 0x7240, 0xc088, 0x727f, 0xc088, 0x21, 0 + .dw 0x72c0, 0xc088, 0x72ff, 0xc088, 0x21, 0 + .dw 0x7340, 0xc088, 0x737f, 0xc088, 0x21, 0 + .dw 0x73c0, 0xc088, 0x73ff, 0xc088, 0x21, 0 + .dw 0x7440, 0xc088, 0x747f, 0xc088, 0x21, 0 + .dw 0x74c0, 0xc088, 0x74ff, 0xc088, 0x21, 0 + .dw 0x7540, 0xc088, 0x757f, 0xc088, 0x21, 0 + .dw 0x75c0, 0xc088, 0x75ff, 0xc088, 0x21, 0 + .dw 0x7640, 0xc088, 0x767f, 0xc088, 0x21, 0 + .dw 0x76c0, 0xc088, 0x76ff, 0xc088, 0x21, 0 + .dw 0x7740, 0xc088, 0x777f, 0xc088, 0x21, 0 + .dw 0x77c0, 0xc088, 0x77ff, 0xc088, 0x21, 0 + .dw 0x7840, 0xc088, 0x787f, 0xc088, 0x21, 0 + .dw 0x78c0, 0xc088, 0x78ff, 0xc088, 0x21, 0 + .dw 0x7940, 0xc088, 0x797f, 0xc088, 0x21, 0 + .dw 0x79c0, 0xc088, 0x9fff, 0xc088, 0x21, 0 + .dw 0xa040, 0xc088, 0xa07f, 0xc088, 0x21, 0 + .dw 0xa0c0, 0xc088, 0xa0ff, 0xc088, 0x21, 0 + .dw 0xa140, 0xc088, 0xa17f, 0xc088, 0x21, 0 + .dw 0xa1c0, 0xc088, 0xa1ff, 0xc088, 0x21, 0 + .dw 0xa240, 0xc088, 0xa27f, 0xc088, 0x21, 0 + .dw 0xa2c0, 0xc088, 0xa2ff, 0xc088, 0x21, 0 + .dw 0xa340, 0xc088, 0xa37f, 0xc088, 0x21, 0 + .dw 0xa3c0, 0xc088, 0xa3ff, 0xc088, 0x21, 0 + .dw 0xa440, 0xc088, 0xa47f, 0xc088, 0x21, 0 + .dw 0xa4c0, 0xc088, 0xa4ff, 0xc088, 0x21, 0 + .dw 0xa540, 0xc088, 0xa57f, 0xc088, 0x21, 0 + .dw 0xa5c0, 0xc088, 0xa5ff, 0xc088, 0x21, 0 + .dw 0xa640, 0xc088, 0xa67f, 0xc088, 0x21, 0 + .dw 0xa6c0, 0xc088, 0xa6ff, 0xc088, 0x21, 0 + .dw 0xa740, 0xc088, 0xa77f, 0xc088, 0x21, 0 + .dw 0xa7c0, 0xc088, 0xa7ff, 0xc088, 0x21, 0 + .dw 0xa840, 0xc088, 0xa87f, 0xc088, 0x21, 0 + .dw 0xa8c0, 0xc088, 0xa8ff, 0xc088, 0x21, 0 + .dw 0xa940, 0xc088, 0xa97f, 0xc088, 0x21, 0 + .dw 0xa9c0, 0xc088, 0xa9ff, 0xc088, 0x21, 0 + .dw 0xaa40, 0xc088, 0xaa7f, 0xc088, 0x21, 0 + .dw 0xaac0, 0xc088, 0xaaff, 0xc088, 0x21, 0 + .dw 0xab40, 0xc088, 0xab7f, 0xc088, 0x21, 0 + .dw 0xabc0, 0xc088, 0xabff, 0xc088, 0x21, 0 + .dw 0xac40, 0xc088, 0xac7f, 0xc088, 0x21, 0 + .dw 0xacc0, 0xc088, 0xacff, 0xc088, 0x21, 0 + .dw 0xad40, 0xc088, 0xad7f, 0xc088, 0x21, 0 + .dw 0xadc0, 0xc088, 0xadff, 0xc088, 0x21, 0 + .dw 0xae40, 0xc088, 0xae7f, 0xc088, 0x21, 0 + .dw 0xaec0, 0xc088, 0xaeff, 0xc088, 0x21, 0 + .dw 0xaf40, 0xc088, 0xaf7f, 0xc088, 0x21, 0 + .dw 0xafc0, 0xc088, 0xafff, 0xc088, 0x21, 0 + .dw 0xb040, 0xc088, 0xb07f, 0xc088, 0x21, 0 + .dw 0xb0c0, 0xc088, 0xb0ff, 0xc088, 0x21, 0 + .dw 0xb140, 0xc088, 0xb17f, 0xc088, 0x21, 0 + .dw 0xb1c0, 0xc088, 0xb1ff, 0xc088, 0x21, 0 + .dw 0xb240, 0xc088, 0xb27f, 0xc088, 0x21, 0 + .dw 0xb2c0, 0xc088, 0xb2ff, 0xc088, 0x21, 0 + .dw 0xb340, 0xc088, 0xb37f, 0xc088, 0x21, 0 + .dw 0xb3c0, 0xc088, 0xb3ff, 0xc088, 0x21, 0 + .dw 0xb440, 0xc088, 0xb47f, 0xc088, 0x21, 0 + .dw 0xb4c0, 0xc088, 0xb4ff, 0xc088, 0x21, 0 + .dw 0xb540, 0xc088, 0xb57f, 0xc088, 0x21, 0 + .dw 0xb5c0, 0xc088, 0xb5ff, 0xc088, 0x21, 0 + .dw 0xb640, 0xc088, 0xb67f, 0xc088, 0x21, 0 + .dw 0xb6c0, 0xc088, 0xb6ff, 0xc088, 0x21, 0 + .dw 0xb740, 0xc088, 0xb77f, 0xc088, 0x21, 0 + .dw 0xb7c0, 0xc088, 0xb7ff, 0xc088, 0x21, 0 + .dw 0xb840, 0xc088, 0xb87f, 0xc088, 0x21, 0 + .dw 0xb8c0, 0xc088, 0xb8ff, 0xc088, 0x21, 0 + .dw 0xb940, 0xc088, 0xb97f, 0xc088, 0x21, 0 + .dw 0xb9c0, 0xc088, 0xdfff, 0xc088, 0x21, 0 + .dw 0xe040, 0xc088, 0xe07f, 0xc088, 0x21, 0 + .dw 0xe0c0, 0xc088, 0xe0ff, 0xc088, 0x21, 0 + .dw 0xe140, 0xc088, 0xe17f, 0xc088, 0x21, 0 + .dw 0xe1c0, 0xc088, 0xe1ff, 0xc088, 0x21, 0 + .dw 0xe240, 0xc088, 0xe27f, 0xc088, 0x21, 0 + .dw 0xe2c0, 0xc088, 0xe2ff, 0xc088, 0x21, 0 + .dw 0xe340, 0xc088, 0xe37f, 0xc088, 0x21, 0 + .dw 0xe3c0, 0xc088, 0xe3ff, 0xc088, 0x21, 0 + .dw 0xe440, 0xc088, 0xe47f, 0xc088, 0x21, 0 + .dw 0xe4c0, 0xc088, 0xe4ff, 0xc088, 0x21, 0 + .dw 0xe540, 0xc088, 0xe57f, 0xc088, 0x21, 0 + .dw 0xe5c0, 0xc088, 0xe5ff, 0xc088, 0x21, 0 + .dw 0xe640, 0xc088, 0xe67f, 0xc088, 0x21, 0 + .dw 0xe6c0, 0xc088, 0xe6ff, 0xc088, 0x21, 0 + .dw 0xe740, 0xc088, 0xe77f, 0xc088, 0x21, 0 + .dw 0xe7c0, 0xc088, 0xe7ff, 0xc088, 0x21, 0 + .dw 0xe840, 0xc088, 0xe87f, 0xc088, 0x21, 0 + .dw 0xe8c0, 0xc088, 0xe8ff, 0xc088, 0x21, 0 + .dw 0xe940, 0xc088, 0xe97f, 0xc088, 0x21, 0 + .dw 0xe9c0, 0xc088, 0xe9ff, 0xc088, 0x21, 0 + .dw 0xea40, 0xc088, 0xea7f, 0xc088, 0x21, 0 + .dw 0xeac0, 0xc088, 0xeaff, 0xc088, 0x21, 0 + .dw 0xeb40, 0xc088, 0xeb7f, 0xc088, 0x21, 0 + .dw 0xebc0, 0xc088, 0xebff, 0xc088, 0x21, 0 + .dw 0xec40, 0xc088, 0xec7f, 0xc088, 0x21, 0 + .dw 0xecc0, 0xc088, 0xecff, 0xc088, 0x21, 0 + .dw 0xed40, 0xc088, 0xed7f, 0xc088, 0x21, 0 + .dw 0xedc0, 0xc088, 0xedff, 0xc088, 0x21, 0 + .dw 0xee40, 0xc088, 0xee7f, 0xc088, 0x21, 0 + .dw 0xeec0, 0xc088, 0xeeff, 0xc088, 0x21, 0 + .dw 0xef40, 0xc088, 0xef7f, 0xc088, 0x21, 0 + .dw 0xefc0, 0xc088, 0xefff, 0xc088, 0x21, 0 + .dw 0xf040, 0xc088, 0xf07f, 0xc088, 0x21, 0 + .dw 0xf0c0, 0xc088, 0xf0ff, 0xc088, 0x21, 0 + .dw 0xf140, 0xc088, 0xf17f, 0xc088, 0x21, 0 + .dw 0xf1c0, 0xc088, 0xf1ff, 0xc088, 0x21, 0 + .dw 0xf240, 0xc088, 0xf27f, 0xc088, 0x21, 0 + .dw 0xf2c0, 0xc088, 0xf2ff, 0xc088, 0x21, 0 + .dw 0xf340, 0xc088, 0xf37f, 0xc088, 0x21, 0 + .dw 0xf3c0, 0xc088, 0xf3ff, 0xc088, 0x21, 0 + .dw 0xf440, 0xc088, 0xf47f, 0xc088, 0x21, 0 + .dw 0xf4c0, 0xc088, 0xf4ff, 0xc088, 0x21, 0 + .dw 0xf540, 0xc088, 0xf57f, 0xc088, 0x21, 0 + .dw 0xf5c0, 0xc088, 0xf5ff, 0xc088, 0x21, 0 + .dw 0xf640, 0xc088, 0xf67f, 0xc088, 0x21, 0 + .dw 0xf6c0, 0xc088, 0xf6ff, 0xc088, 0x21, 0 + .dw 0xf740, 0xc088, 0xf77f, 0xc088, 0x21, 0 + .dw 0xf7c0, 0xc088, 0xf7ff, 0xc088, 0x21, 0 + .dw 0xf840, 0xc088, 0xf87f, 0xc088, 0x21, 0 + .dw 0xf8c0, 0xc088, 0xf8ff, 0xc088, 0x21, 0 + .dw 0xf940, 0xc088, 0xf97f, 0xc088, 0x21, 0 + .dw 0xf9c0, 0xc088, 0x1fff, 0xc089, 0x21, 0 + .dw 0x2040, 0xc089, 0x207f, 0xc089, 0x21, 0 + .dw 0x20c0, 0xc089, 0x20ff, 0xc089, 0x21, 0 + .dw 0x2140, 0xc089, 0x217f, 0xc089, 0x21, 0 + .dw 0x21c0, 0xc089, 0x21ff, 0xc089, 0x21, 0 + .dw 0x2240, 0xc089, 0x227f, 0xc089, 0x21, 0 + .dw 0x22c0, 0xc089, 0x22ff, 0xc089, 0x21, 0 + .dw 0x2340, 0xc089, 0x237f, 0xc089, 0x21, 0 + .dw 0x23c0, 0xc089, 0x23ff, 0xc089, 0x21, 0 + .dw 0x2440, 0xc089, 0x247f, 0xc089, 0x21, 0 + .dw 0x24c0, 0xc089, 0x24ff, 0xc089, 0x21, 0 + .dw 0x2540, 0xc089, 0x257f, 0xc089, 0x21, 0 + .dw 0x25c0, 0xc089, 0x25ff, 0xc089, 0x21, 0 + .dw 0x2640, 0xc089, 0x267f, 0xc089, 0x21, 0 + .dw 0x26c0, 0xc089, 0x26ff, 0xc089, 0x21, 0 + .dw 0x2740, 0xc089, 0x277f, 0xc089, 0x21, 0 + .dw 0x27c0, 0xc089, 0x27ff, 0xc089, 0x21, 0 + .dw 0x2840, 0xc089, 0x287f, 0xc089, 0x21, 0 + .dw 0x28c0, 0xc089, 0x28ff, 0xc089, 0x21, 0 + .dw 0x2940, 0xc089, 0x297f, 0xc089, 0x21, 0 + .dw 0x29c0, 0xc089, 0x29ff, 0xc089, 0x21, 0 + .dw 0x2a40, 0xc089, 0x2a7f, 0xc089, 0x21, 0 + .dw 0x2ac0, 0xc089, 0x2aff, 0xc089, 0x21, 0 + .dw 0x2b40, 0xc089, 0x2b7f, 0xc089, 0x21, 0 + .dw 0x2bc0, 0xc089, 0x2bff, 0xc089, 0x21, 0 + .dw 0x2c40, 0xc089, 0x2c7f, 0xc089, 0x21, 0 + .dw 0x2cc0, 0xc089, 0x2cff, 0xc089, 0x21, 0 + .dw 0x2d40, 0xc089, 0x2d7f, 0xc089, 0x21, 0 + .dw 0x2dc0, 0xc089, 0x2dff, 0xc089, 0x21, 0 + .dw 0x2e40, 0xc089, 0x2e7f, 0xc089, 0x21, 0 + .dw 0x2ec0, 0xc089, 0x2eff, 0xc089, 0x21, 0 + .dw 0x2f40, 0xc089, 0x2f7f, 0xc089, 0x21, 0 + .dw 0x2fc0, 0xc089, 0x2fff, 0xc089, 0x21, 0 + .dw 0x3040, 0xc089, 0x307f, 0xc089, 0x21, 0 + .dw 0x30c0, 0xc089, 0x30ff, 0xc089, 0x21, 0 + .dw 0x3140, 0xc089, 0x317f, 0xc089, 0x21, 0 + .dw 0x31c0, 0xc089, 0x31ff, 0xc089, 0x21, 0 + .dw 0x3240, 0xc089, 0x327f, 0xc089, 0x21, 0 + .dw 0x32c0, 0xc089, 0x32ff, 0xc089, 0x21, 0 + .dw 0x3340, 0xc089, 0x337f, 0xc089, 0x21, 0 + .dw 0x33c0, 0xc089, 0x33ff, 0xc089, 0x21, 0 + .dw 0x3440, 0xc089, 0x347f, 0xc089, 0x21, 0 + .dw 0x34c0, 0xc089, 0x34ff, 0xc089, 0x21, 0 + .dw 0x3540, 0xc089, 0x357f, 0xc089, 0x21, 0 + .dw 0x35c0, 0xc089, 0x35ff, 0xc089, 0x21, 0 + .dw 0x3640, 0xc089, 0x367f, 0xc089, 0x21, 0 + .dw 0x36c0, 0xc089, 0x36ff, 0xc089, 0x21, 0 + .dw 0x3740, 0xc089, 0x377f, 0xc089, 0x21, 0 + .dw 0x37c0, 0xc089, 0x37ff, 0xc089, 0x21, 0 + .dw 0x3840, 0xc089, 0x387f, 0xc089, 0x21, 0 + .dw 0x38c0, 0xc089, 0x38ff, 0xc089, 0x21, 0 + .dw 0x3940, 0xc089, 0x397f, 0xc089, 0x21, 0 + .dw 0x39c0, 0xc089, 0x5fff, 0xc089, 0x21, 0 + .dw 0x6040, 0xc089, 0x607f, 0xc089, 0x21, 0 + .dw 0x60c0, 0xc089, 0x60ff, 0xc089, 0x21, 0 + .dw 0x6140, 0xc089, 0x617f, 0xc089, 0x21, 0 + .dw 0x61c0, 0xc089, 0x61ff, 0xc089, 0x21, 0 + .dw 0x6240, 0xc089, 0x627f, 0xc089, 0x21, 0 + .dw 0x62c0, 0xc089, 0x62ff, 0xc089, 0x21, 0 + .dw 0x6340, 0xc089, 0x637f, 0xc089, 0x21, 0 + .dw 0x63c0, 0xc089, 0x63ff, 0xc089, 0x21, 0 + .dw 0x6440, 0xc089, 0x647f, 0xc089, 0x21, 0 + .dw 0x64c0, 0xc089, 0x64ff, 0xc089, 0x21, 0 + .dw 0x6540, 0xc089, 0x657f, 0xc089, 0x21, 0 + .dw 0x65c0, 0xc089, 0x65ff, 0xc089, 0x21, 0 + .dw 0x6640, 0xc089, 0x667f, 0xc089, 0x21, 0 + .dw 0x66c0, 0xc089, 0x66ff, 0xc089, 0x21, 0 + .dw 0x6740, 0xc089, 0x677f, 0xc089, 0x21, 0 + .dw 0x67c0, 0xc089, 0x67ff, 0xc089, 0x21, 0 + .dw 0x6840, 0xc089, 0x687f, 0xc089, 0x21, 0 + .dw 0x68c0, 0xc089, 0x68ff, 0xc089, 0x21, 0 + .dw 0x6940, 0xc089, 0x697f, 0xc089, 0x21, 0 + .dw 0x69c0, 0xc089, 0x69ff, 0xc089, 0x21, 0 + .dw 0x6a40, 0xc089, 0x6a7f, 0xc089, 0x21, 0 + .dw 0x6ac0, 0xc089, 0x6aff, 0xc089, 0x21, 0 + .dw 0x6b40, 0xc089, 0x6b7f, 0xc089, 0x21, 0 + .dw 0x6bc0, 0xc089, 0x6bff, 0xc089, 0x21, 0 + .dw 0x6c40, 0xc089, 0x6c7f, 0xc089, 0x21, 0 + .dw 0x6cc0, 0xc089, 0x6cff, 0xc089, 0x21, 0 + .dw 0x6d40, 0xc089, 0x6d7f, 0xc089, 0x21, 0 + .dw 0x6dc0, 0xc089, 0x6dff, 0xc089, 0x21, 0 + .dw 0x6e40, 0xc089, 0x6e7f, 0xc089, 0x21, 0 + .dw 0x6ec0, 0xc089, 0x6eff, 0xc089, 0x21, 0 + .dw 0x6f40, 0xc089, 0x6f7f, 0xc089, 0x21, 0 + .dw 0x6fc0, 0xc089, 0x6fff, 0xc089, 0x21, 0 + .dw 0x7040, 0xc089, 0x707f, 0xc089, 0x21, 0 + .dw 0x70c0, 0xc089, 0x70ff, 0xc089, 0x21, 0 + .dw 0x7140, 0xc089, 0x717f, 0xc089, 0x21, 0 + .dw 0x71c0, 0xc089, 0x71ff, 0xc089, 0x21, 0 + .dw 0x7240, 0xc089, 0x727f, 0xc089, 0x21, 0 + .dw 0x72c0, 0xc089, 0x72ff, 0xc089, 0x21, 0 + .dw 0x7340, 0xc089, 0x737f, 0xc089, 0x21, 0 + .dw 0x73c0, 0xc089, 0x73ff, 0xc089, 0x21, 0 + .dw 0x7440, 0xc089, 0x747f, 0xc089, 0x21, 0 + .dw 0x74c0, 0xc089, 0x74ff, 0xc089, 0x21, 0 + .dw 0x7540, 0xc089, 0x757f, 0xc089, 0x21, 0 + .dw 0x75c0, 0xc089, 0x75ff, 0xc089, 0x21, 0 + .dw 0x7640, 0xc089, 0x767f, 0xc089, 0x21, 0 + .dw 0x76c0, 0xc089, 0x76ff, 0xc089, 0x21, 0 + .dw 0x7740, 0xc089, 0x777f, 0xc089, 0x21, 0 + .dw 0x77c0, 0xc089, 0x77ff, 0xc089, 0x21, 0 + .dw 0x7840, 0xc089, 0x787f, 0xc089, 0x21, 0 + .dw 0x78c0, 0xc089, 0x78ff, 0xc089, 0x21, 0 + .dw 0x7940, 0xc089, 0x797f, 0xc089, 0x21, 0 + .dw 0x79c0, 0xc089, 0x9fff, 0xc089, 0x21, 0 + .dw 0xa040, 0xc089, 0xa07f, 0xc089, 0x21, 0 + .dw 0xa0c0, 0xc089, 0xa0ff, 0xc089, 0x21, 0 + .dw 0xa140, 0xc089, 0xa17f, 0xc089, 0x21, 0 + .dw 0xa1c0, 0xc089, 0xa1ff, 0xc089, 0x21, 0 + .dw 0xa240, 0xc089, 0xa27f, 0xc089, 0x21, 0 + .dw 0xa2c0, 0xc089, 0xa2ff, 0xc089, 0x21, 0 + .dw 0xa340, 0xc089, 0xa37f, 0xc089, 0x21, 0 + .dw 0xa3c0, 0xc089, 0xa3ff, 0xc089, 0x21, 0 + .dw 0xa440, 0xc089, 0xa47f, 0xc089, 0x21, 0 + .dw 0xa4c0, 0xc089, 0xa4ff, 0xc089, 0x21, 0 + .dw 0xa540, 0xc089, 0xa57f, 0xc089, 0x21, 0 + .dw 0xa5c0, 0xc089, 0xa5ff, 0xc089, 0x21, 0 + .dw 0xa640, 0xc089, 0xa67f, 0xc089, 0x21, 0 + .dw 0xa6c0, 0xc089, 0xa6ff, 0xc089, 0x21, 0 + .dw 0xa740, 0xc089, 0xa77f, 0xc089, 0x21, 0 + .dw 0xa7c0, 0xc089, 0xa7ff, 0xc089, 0x21, 0 + .dw 0xa840, 0xc089, 0xa87f, 0xc089, 0x21, 0 + .dw 0xa8c0, 0xc089, 0xa8ff, 0xc089, 0x21, 0 + .dw 0xa940, 0xc089, 0xa97f, 0xc089, 0x21, 0 + .dw 0xa9c0, 0xc089, 0xa9ff, 0xc089, 0x21, 0 + .dw 0xaa40, 0xc089, 0xaa7f, 0xc089, 0x21, 0 + .dw 0xaac0, 0xc089, 0xaaff, 0xc089, 0x21, 0 + .dw 0xab40, 0xc089, 0xab7f, 0xc089, 0x21, 0 + .dw 0xabc0, 0xc089, 0xabff, 0xc089, 0x21, 0 + .dw 0xac40, 0xc089, 0xac7f, 0xc089, 0x21, 0 + .dw 0xacc0, 0xc089, 0xacff, 0xc089, 0x21, 0 + .dw 0xad40, 0xc089, 0xad7f, 0xc089, 0x21, 0 + .dw 0xadc0, 0xc089, 0xadff, 0xc089, 0x21, 0 + .dw 0xae40, 0xc089, 0xae7f, 0xc089, 0x21, 0 + .dw 0xaec0, 0xc089, 0xaeff, 0xc089, 0x21, 0 + .dw 0xaf40, 0xc089, 0xaf7f, 0xc089, 0x21, 0 + .dw 0xafc0, 0xc089, 0xafff, 0xc089, 0x21, 0 + .dw 0xb040, 0xc089, 0xb07f, 0xc089, 0x21, 0 + .dw 0xb0c0, 0xc089, 0xb0ff, 0xc089, 0x21, 0 + .dw 0xb140, 0xc089, 0xb17f, 0xc089, 0x21, 0 + .dw 0xb1c0, 0xc089, 0xb1ff, 0xc089, 0x21, 0 + .dw 0xb240, 0xc089, 0xb27f, 0xc089, 0x21, 0 + .dw 0xb2c0, 0xc089, 0xb2ff, 0xc089, 0x21, 0 + .dw 0xb340, 0xc089, 0xb37f, 0xc089, 0x21, 0 + .dw 0xb3c0, 0xc089, 0xb3ff, 0xc089, 0x21, 0 + .dw 0xb440, 0xc089, 0xb47f, 0xc089, 0x21, 0 + .dw 0xb4c0, 0xc089, 0xb4ff, 0xc089, 0x21, 0 + .dw 0xb540, 0xc089, 0xb57f, 0xc089, 0x21, 0 + .dw 0xb5c0, 0xc089, 0xb5ff, 0xc089, 0x21, 0 + .dw 0xb640, 0xc089, 0xb67f, 0xc089, 0x21, 0 + .dw 0xb6c0, 0xc089, 0xb6ff, 0xc089, 0x21, 0 + .dw 0xb740, 0xc089, 0xb77f, 0xc089, 0x21, 0 + .dw 0xb7c0, 0xc089, 0xb7ff, 0xc089, 0x21, 0 + .dw 0xb840, 0xc089, 0xb87f, 0xc089, 0x21, 0 + .dw 0xb8c0, 0xc089, 0xb8ff, 0xc089, 0x21, 0 + .dw 0xb940, 0xc089, 0xb97f, 0xc089, 0x21, 0 + .dw 0xb9c0, 0xc089, 0xdfff, 0xc089, 0x21, 0 + .dw 0xe040, 0xc089, 0xe07f, 0xc089, 0x21, 0 + .dw 0xe0c0, 0xc089, 0xe0ff, 0xc089, 0x21, 0 + .dw 0xe140, 0xc089, 0xe17f, 0xc089, 0x21, 0 + .dw 0xe1c0, 0xc089, 0xe1ff, 0xc089, 0x21, 0 + .dw 0xe240, 0xc089, 0xe27f, 0xc089, 0x21, 0 + .dw 0xe2c0, 0xc089, 0xe2ff, 0xc089, 0x21, 0 + .dw 0xe340, 0xc089, 0xe37f, 0xc089, 0x21, 0 + .dw 0xe3c0, 0xc089, 0xe3ff, 0xc089, 0x21, 0 + .dw 0xe440, 0xc089, 0xe47f, 0xc089, 0x21, 0 + .dw 0xe4c0, 0xc089, 0xe4ff, 0xc089, 0x21, 0 + .dw 0xe540, 0xc089, 0xe57f, 0xc089, 0x21, 0 + .dw 0xe5c0, 0xc089, 0xe5ff, 0xc089, 0x21, 0 + .dw 0xe640, 0xc089, 0xe67f, 0xc089, 0x21, 0 + .dw 0xe6c0, 0xc089, 0xe6ff, 0xc089, 0x21, 0 + .dw 0xe740, 0xc089, 0xe77f, 0xc089, 0x21, 0 + .dw 0xe7c0, 0xc089, 0xe7ff, 0xc089, 0x21, 0 + .dw 0xe840, 0xc089, 0xe87f, 0xc089, 0x21, 0 + .dw 0xe8c0, 0xc089, 0xe8ff, 0xc089, 0x21, 0 + .dw 0xe940, 0xc089, 0xe97f, 0xc089, 0x21, 0 + .dw 0xe9c0, 0xc089, 0xe9ff, 0xc089, 0x21, 0 + .dw 0xea40, 0xc089, 0xea7f, 0xc089, 0x21, 0 + .dw 0xeac0, 0xc089, 0xeaff, 0xc089, 0x21, 0 + .dw 0xeb40, 0xc089, 0xeb7f, 0xc089, 0x21, 0 + .dw 0xebc0, 0xc089, 0xebff, 0xc089, 0x21, 0 + .dw 0xec40, 0xc089, 0xec7f, 0xc089, 0x21, 0 + .dw 0xecc0, 0xc089, 0xecff, 0xc089, 0x21, 0 + .dw 0xed40, 0xc089, 0xed7f, 0xc089, 0x21, 0 + .dw 0xedc0, 0xc089, 0xedff, 0xc089, 0x21, 0 + .dw 0xee40, 0xc089, 0xee7f, 0xc089, 0x21, 0 + .dw 0xeec0, 0xc089, 0xeeff, 0xc089, 0x21, 0 + .dw 0xef40, 0xc089, 0xef7f, 0xc089, 0x21, 0 + .dw 0xefc0, 0xc089, 0xefff, 0xc089, 0x21, 0 + .dw 0xf040, 0xc089, 0xf07f, 0xc089, 0x21, 0 + .dw 0xf0c0, 0xc089, 0xf0ff, 0xc089, 0x21, 0 + .dw 0xf140, 0xc089, 0xf17f, 0xc089, 0x21, 0 + .dw 0xf1c0, 0xc089, 0xf1ff, 0xc089, 0x21, 0 + .dw 0xf240, 0xc089, 0xf27f, 0xc089, 0x21, 0 + .dw 0xf2c0, 0xc089, 0xf2ff, 0xc089, 0x21, 0 + .dw 0xf340, 0xc089, 0xf37f, 0xc089, 0x21, 0 + .dw 0xf3c0, 0xc089, 0xf3ff, 0xc089, 0x21, 0 + .dw 0xf440, 0xc089, 0xf47f, 0xc089, 0x21, 0 + .dw 0xf4c0, 0xc089, 0xf4ff, 0xc089, 0x21, 0 + .dw 0xf540, 0xc089, 0xf57f, 0xc089, 0x21, 0 + .dw 0xf5c0, 0xc089, 0xf5ff, 0xc089, 0x21, 0 + .dw 0xf640, 0xc089, 0xf67f, 0xc089, 0x21, 0 + .dw 0xf6c0, 0xc089, 0xf6ff, 0xc089, 0x21, 0 + .dw 0xf740, 0xc089, 0xf77f, 0xc089, 0x21, 0 + .dw 0xf7c0, 0xc089, 0xf7ff, 0xc089, 0x21, 0 + .dw 0xf840, 0xc089, 0xf87f, 0xc089, 0x21, 0 + .dw 0xf8c0, 0xc089, 0xf8ff, 0xc089, 0x21, 0 + .dw 0xf940, 0xc089, 0xf97f, 0xc089, 0x21, 0 + .dw 0xf9c0, 0xc089, 0x1fff, 0xc08a, 0x21, 0 + .dw 0x2040, 0xc08a, 0x207f, 0xc08a, 0x21, 0 + .dw 0x20c0, 0xc08a, 0x20ff, 0xc08a, 0x21, 0 + .dw 0x2140, 0xc08a, 0x217f, 0xc08a, 0x21, 0 + .dw 0x21c0, 0xc08a, 0x21ff, 0xc08a, 0x21, 0 + .dw 0x2240, 0xc08a, 0x227f, 0xc08a, 0x21, 0 + .dw 0x22c0, 0xc08a, 0x22ff, 0xc08a, 0x21, 0 + .dw 0x2340, 0xc08a, 0x237f, 0xc08a, 0x21, 0 + .dw 0x23c0, 0xc08a, 0x23ff, 0xc08a, 0x21, 0 + .dw 0x2440, 0xc08a, 0x247f, 0xc08a, 0x21, 0 + .dw 0x24c0, 0xc08a, 0x24ff, 0xc08a, 0x21, 0 + .dw 0x2540, 0xc08a, 0x257f, 0xc08a, 0x21, 0 + .dw 0x25c0, 0xc08a, 0x25ff, 0xc08a, 0x21, 0 + .dw 0x2640, 0xc08a, 0x267f, 0xc08a, 0x21, 0 + .dw 0x26c0, 0xc08a, 0x26ff, 0xc08a, 0x21, 0 + .dw 0x2740, 0xc08a, 0x277f, 0xc08a, 0x21, 0 + .dw 0x27c0, 0xc08a, 0x27ff, 0xc08a, 0x21, 0 + .dw 0x2840, 0xc08a, 0x287f, 0xc08a, 0x21, 0 + .dw 0x28c0, 0xc08a, 0x28ff, 0xc08a, 0x21, 0 + .dw 0x2940, 0xc08a, 0x297f, 0xc08a, 0x21, 0 + .dw 0x29c0, 0xc08a, 0x29ff, 0xc08a, 0x21, 0 + .dw 0x2a40, 0xc08a, 0x2a7f, 0xc08a, 0x21, 0 + .dw 0x2ac0, 0xc08a, 0x2aff, 0xc08a, 0x21, 0 + .dw 0x2b40, 0xc08a, 0x2b7f, 0xc08a, 0x21, 0 + .dw 0x2bc0, 0xc08a, 0x2bff, 0xc08a, 0x21, 0 + .dw 0x2c40, 0xc08a, 0x2c7f, 0xc08a, 0x21, 0 + .dw 0x2cc0, 0xc08a, 0x2cff, 0xc08a, 0x21, 0 + .dw 0x2d40, 0xc08a, 0x2d7f, 0xc08a, 0x21, 0 + .dw 0x2dc0, 0xc08a, 0x2dff, 0xc08a, 0x21, 0 + .dw 0x2e40, 0xc08a, 0x2e7f, 0xc08a, 0x21, 0 + .dw 0x2ec0, 0xc08a, 0x2eff, 0xc08a, 0x21, 0 + .dw 0x2f40, 0xc08a, 0x2f7f, 0xc08a, 0x21, 0 + .dw 0x2fc0, 0xc08a, 0x2fff, 0xc08a, 0x21, 0 + .dw 0x3040, 0xc08a, 0x307f, 0xc08a, 0x21, 0 + .dw 0x30c0, 0xc08a, 0x30ff, 0xc08a, 0x21, 0 + .dw 0x3140, 0xc08a, 0x317f, 0xc08a, 0x21, 0 + .dw 0x31c0, 0xc08a, 0x31ff, 0xc08a, 0x21, 0 + .dw 0x3240, 0xc08a, 0x327f, 0xc08a, 0x21, 0 + .dw 0x32c0, 0xc08a, 0x32ff, 0xc08a, 0x21, 0 + .dw 0x3340, 0xc08a, 0x337f, 0xc08a, 0x21, 0 + .dw 0x33c0, 0xc08a, 0x33ff, 0xc08a, 0x21, 0 + .dw 0x3440, 0xc08a, 0x347f, 0xc08a, 0x21, 0 + .dw 0x34c0, 0xc08a, 0x34ff, 0xc08a, 0x21, 0 + .dw 0x3540, 0xc08a, 0x357f, 0xc08a, 0x21, 0 + .dw 0x35c0, 0xc08a, 0x35ff, 0xc08a, 0x21, 0 + .dw 0x3640, 0xc08a, 0x367f, 0xc08a, 0x21, 0 + .dw 0x36c0, 0xc08a, 0x36ff, 0xc08a, 0x21, 0 + .dw 0x3740, 0xc08a, 0x377f, 0xc08a, 0x21, 0 + .dw 0x37c0, 0xc08a, 0x37ff, 0xc08a, 0x21, 0 + .dw 0x3840, 0xc08a, 0x387f, 0xc08a, 0x21, 0 + .dw 0x38c0, 0xc08a, 0x38ff, 0xc08a, 0x21, 0 + .dw 0x3940, 0xc08a, 0x397f, 0xc08a, 0x21, 0 + .dw 0x39c0, 0xc08a, 0x5fff, 0xc08a, 0x21, 0 + .dw 0x6040, 0xc08a, 0x607f, 0xc08a, 0x21, 0 + .dw 0x60c0, 0xc08a, 0x60ff, 0xc08a, 0x21, 0 + .dw 0x6140, 0xc08a, 0x617f, 0xc08a, 0x21, 0 + .dw 0x61c0, 0xc08a, 0x61ff, 0xc08a, 0x21, 0 + .dw 0x6240, 0xc08a, 0x627f, 0xc08a, 0x21, 0 + .dw 0x62c0, 0xc08a, 0x62ff, 0xc08a, 0x21, 0 + .dw 0x6340, 0xc08a, 0x637f, 0xc08a, 0x21, 0 + .dw 0x63c0, 0xc08a, 0x63ff, 0xc08a, 0x21, 0 + .dw 0x6440, 0xc08a, 0x647f, 0xc08a, 0x21, 0 + .dw 0x64c0, 0xc08a, 0x64ff, 0xc08a, 0x21, 0 + .dw 0x6540, 0xc08a, 0x657f, 0xc08a, 0x21, 0 + .dw 0x65c0, 0xc08a, 0x65ff, 0xc08a, 0x21, 0 + .dw 0x6640, 0xc08a, 0x667f, 0xc08a, 0x21, 0 + .dw 0x66c0, 0xc08a, 0x66ff, 0xc08a, 0x21, 0 + .dw 0x6740, 0xc08a, 0x677f, 0xc08a, 0x21, 0 + .dw 0x67c0, 0xc08a, 0x67ff, 0xc08a, 0x21, 0 + .dw 0x6840, 0xc08a, 0x687f, 0xc08a, 0x21, 0 + .dw 0x68c0, 0xc08a, 0x68ff, 0xc08a, 0x21, 0 + .dw 0x6940, 0xc08a, 0x697f, 0xc08a, 0x21, 0 + .dw 0x69c0, 0xc08a, 0x69ff, 0xc08a, 0x21, 0 + .dw 0x6a40, 0xc08a, 0x6a7f, 0xc08a, 0x21, 0 + .dw 0x6ac0, 0xc08a, 0x6aff, 0xc08a, 0x21, 0 + .dw 0x6b40, 0xc08a, 0x6b7f, 0xc08a, 0x21, 0 + .dw 0x6bc0, 0xc08a, 0x6bff, 0xc08a, 0x21, 0 + .dw 0x6c40, 0xc08a, 0x6c7f, 0xc08a, 0x21, 0 + .dw 0x6cc0, 0xc08a, 0x6cff, 0xc08a, 0x21, 0 + .dw 0x6d40, 0xc08a, 0x6d7f, 0xc08a, 0x21, 0 + .dw 0x6dc0, 0xc08a, 0x6dff, 0xc08a, 0x21, 0 + .dw 0x6e40, 0xc08a, 0x6e7f, 0xc08a, 0x21, 0 + .dw 0x6ec0, 0xc08a, 0x6eff, 0xc08a, 0x21, 0 + .dw 0x6f40, 0xc08a, 0x6f7f, 0xc08a, 0x21, 0 + .dw 0x6fc0, 0xc08a, 0x6fff, 0xc08a, 0x21, 0 + .dw 0x7040, 0xc08a, 0x707f, 0xc08a, 0x21, 0 + .dw 0x70c0, 0xc08a, 0x70ff, 0xc08a, 0x21, 0 + .dw 0x7140, 0xc08a, 0x717f, 0xc08a, 0x21, 0 + .dw 0x71c0, 0xc08a, 0x71ff, 0xc08a, 0x21, 0 + .dw 0x7240, 0xc08a, 0x727f, 0xc08a, 0x21, 0 + .dw 0x72c0, 0xc08a, 0x72ff, 0xc08a, 0x21, 0 + .dw 0x7340, 0xc08a, 0x737f, 0xc08a, 0x21, 0 + .dw 0x73c0, 0xc08a, 0x73ff, 0xc08a, 0x21, 0 + .dw 0x7440, 0xc08a, 0x747f, 0xc08a, 0x21, 0 + .dw 0x74c0, 0xc08a, 0x74ff, 0xc08a, 0x21, 0 + .dw 0x7540, 0xc08a, 0x757f, 0xc08a, 0x21, 0 + .dw 0x75c0, 0xc08a, 0x75ff, 0xc08a, 0x21, 0 + .dw 0x7640, 0xc08a, 0x767f, 0xc08a, 0x21, 0 + .dw 0x76c0, 0xc08a, 0x76ff, 0xc08a, 0x21, 0 + .dw 0x7740, 0xc08a, 0x777f, 0xc08a, 0x21, 0 + .dw 0x77c0, 0xc08a, 0x77ff, 0xc08a, 0x21, 0 + .dw 0x7840, 0xc08a, 0x787f, 0xc08a, 0x21, 0 + .dw 0x78c0, 0xc08a, 0x78ff, 0xc08a, 0x21, 0 + .dw 0x7940, 0xc08a, 0x797f, 0xc08a, 0x21, 0 + .dw 0x79c0, 0xc08a, 0x9fff, 0xc08a, 0x21, 0 + .dw 0xa040, 0xc08a, 0xa07f, 0xc08a, 0x21, 0 + .dw 0xa0c0, 0xc08a, 0xa0ff, 0xc08a, 0x21, 0 + .dw 0xa140, 0xc08a, 0xa17f, 0xc08a, 0x21, 0 + .dw 0xa1c0, 0xc08a, 0xa1ff, 0xc08a, 0x21, 0 + .dw 0xa240, 0xc08a, 0xa27f, 0xc08a, 0x21, 0 + .dw 0xa2c0, 0xc08a, 0xa2ff, 0xc08a, 0x21, 0 + .dw 0xa340, 0xc08a, 0xa37f, 0xc08a, 0x21, 0 + .dw 0xa3c0, 0xc08a, 0xa3ff, 0xc08a, 0x21, 0 + .dw 0xa440, 0xc08a, 0xa47f, 0xc08a, 0x21, 0 + .dw 0xa4c0, 0xc08a, 0xa4ff, 0xc08a, 0x21, 0 + .dw 0xa540, 0xc08a, 0xa57f, 0xc08a, 0x21, 0 + .dw 0xa5c0, 0xc08a, 0xa5ff, 0xc08a, 0x21, 0 + .dw 0xa640, 0xc08a, 0xa67f, 0xc08a, 0x21, 0 + .dw 0xa6c0, 0xc08a, 0xa6ff, 0xc08a, 0x21, 0 + .dw 0xa740, 0xc08a, 0xa77f, 0xc08a, 0x21, 0 + .dw 0xa7c0, 0xc08a, 0xa7ff, 0xc08a, 0x21, 0 + .dw 0xa840, 0xc08a, 0xa87f, 0xc08a, 0x21, 0 + .dw 0xa8c0, 0xc08a, 0xa8ff, 0xc08a, 0x21, 0 + .dw 0xa940, 0xc08a, 0xa97f, 0xc08a, 0x21, 0 + .dw 0xa9c0, 0xc08a, 0xa9ff, 0xc08a, 0x21, 0 + .dw 0xaa40, 0xc08a, 0xaa7f, 0xc08a, 0x21, 0 + .dw 0xaac0, 0xc08a, 0xaaff, 0xc08a, 0x21, 0 + .dw 0xab40, 0xc08a, 0xab7f, 0xc08a, 0x21, 0 + .dw 0xabc0, 0xc08a, 0xabff, 0xc08a, 0x21, 0 + .dw 0xac40, 0xc08a, 0xac7f, 0xc08a, 0x21, 0 + .dw 0xacc0, 0xc08a, 0xacff, 0xc08a, 0x21, 0 + .dw 0xad40, 0xc08a, 0xad7f, 0xc08a, 0x21, 0 + .dw 0xadc0, 0xc08a, 0xadff, 0xc08a, 0x21, 0 + .dw 0xae40, 0xc08a, 0xae7f, 0xc08a, 0x21, 0 + .dw 0xaec0, 0xc08a, 0xaeff, 0xc08a, 0x21, 0 + .dw 0xaf40, 0xc08a, 0xaf7f, 0xc08a, 0x21, 0 + .dw 0xafc0, 0xc08a, 0xafff, 0xc08a, 0x21, 0 + .dw 0xb040, 0xc08a, 0xb07f, 0xc08a, 0x21, 0 + .dw 0xb0c0, 0xc08a, 0xb0ff, 0xc08a, 0x21, 0 + .dw 0xb140, 0xc08a, 0xb17f, 0xc08a, 0x21, 0 + .dw 0xb1c0, 0xc08a, 0xb1ff, 0xc08a, 0x21, 0 + .dw 0xb240, 0xc08a, 0xb27f, 0xc08a, 0x21, 0 + .dw 0xb2c0, 0xc08a, 0xb2ff, 0xc08a, 0x21, 0 + .dw 0xb340, 0xc08a, 0xb37f, 0xc08a, 0x21, 0 + .dw 0xb3c0, 0xc08a, 0xb3ff, 0xc08a, 0x21, 0 + .dw 0xb440, 0xc08a, 0xb47f, 0xc08a, 0x21, 0 + .dw 0xb4c0, 0xc08a, 0xb4ff, 0xc08a, 0x21, 0 + .dw 0xb540, 0xc08a, 0xb57f, 0xc08a, 0x21, 0 + .dw 0xb5c0, 0xc08a, 0xb5ff, 0xc08a, 0x21, 0 + .dw 0xb640, 0xc08a, 0xb67f, 0xc08a, 0x21, 0 + .dw 0xb6c0, 0xc08a, 0xb6ff, 0xc08a, 0x21, 0 + .dw 0xb740, 0xc08a, 0xb77f, 0xc08a, 0x21, 0 + .dw 0xb7c0, 0xc08a, 0xb7ff, 0xc08a, 0x21, 0 + .dw 0xb840, 0xc08a, 0xb87f, 0xc08a, 0x21, 0 + .dw 0xb8c0, 0xc08a, 0xb8ff, 0xc08a, 0x21, 0 + .dw 0xb940, 0xc08a, 0xb97f, 0xc08a, 0x21, 0 + .dw 0xb9c0, 0xc08a, 0xdfff, 0xc08a, 0x21, 0 + .dw 0xe040, 0xc08a, 0xe07f, 0xc08a, 0x21, 0 + .dw 0xe0c0, 0xc08a, 0xe0ff, 0xc08a, 0x21, 0 + .dw 0xe140, 0xc08a, 0xe17f, 0xc08a, 0x21, 0 + .dw 0xe1c0, 0xc08a, 0xe1ff, 0xc08a, 0x21, 0 + .dw 0xe240, 0xc08a, 0xe27f, 0xc08a, 0x21, 0 + .dw 0xe2c0, 0xc08a, 0xe2ff, 0xc08a, 0x21, 0 + .dw 0xe340, 0xc08a, 0xe37f, 0xc08a, 0x21, 0 + .dw 0xe3c0, 0xc08a, 0xe3ff, 0xc08a, 0x21, 0 + .dw 0xe440, 0xc08a, 0xe47f, 0xc08a, 0x21, 0 + .dw 0xe4c0, 0xc08a, 0xe4ff, 0xc08a, 0x21, 0 + .dw 0xe540, 0xc08a, 0xe57f, 0xc08a, 0x21, 0 + .dw 0xe5c0, 0xc08a, 0xe5ff, 0xc08a, 0x21, 0 + .dw 0xe640, 0xc08a, 0xe67f, 0xc08a, 0x21, 0 + .dw 0xe6c0, 0xc08a, 0xe6ff, 0xc08a, 0x21, 0 + .dw 0xe740, 0xc08a, 0xe77f, 0xc08a, 0x21, 0 + .dw 0xe7c0, 0xc08a, 0xe7ff, 0xc08a, 0x21, 0 + .dw 0xe840, 0xc08a, 0xe87f, 0xc08a, 0x21, 0 + .dw 0xe8c0, 0xc08a, 0xe8ff, 0xc08a, 0x21, 0 + .dw 0xe940, 0xc08a, 0xe97f, 0xc08a, 0x21, 0 + .dw 0xe9c0, 0xc08a, 0xe9ff, 0xc08a, 0x21, 0 + .dw 0xea40, 0xc08a, 0xea7f, 0xc08a, 0x21, 0 + .dw 0xeac0, 0xc08a, 0xeaff, 0xc08a, 0x21, 0 + .dw 0xeb40, 0xc08a, 0xeb7f, 0xc08a, 0x21, 0 + .dw 0xebc0, 0xc08a, 0xebff, 0xc08a, 0x21, 0 + .dw 0xec40, 0xc08a, 0xec7f, 0xc08a, 0x21, 0 + .dw 0xecc0, 0xc08a, 0xecff, 0xc08a, 0x21, 0 + .dw 0xed40, 0xc08a, 0xed7f, 0xc08a, 0x21, 0 + .dw 0xedc0, 0xc08a, 0xedff, 0xc08a, 0x21, 0 + .dw 0xee40, 0xc08a, 0xee7f, 0xc08a, 0x21, 0 + .dw 0xeec0, 0xc08a, 0xeeff, 0xc08a, 0x21, 0 + .dw 0xef40, 0xc08a, 0xef7f, 0xc08a, 0x21, 0 + .dw 0xefc0, 0xc08a, 0xefff, 0xc08a, 0x21, 0 + .dw 0xf040, 0xc08a, 0xf07f, 0xc08a, 0x21, 0 + .dw 0xf0c0, 0xc08a, 0xf0ff, 0xc08a, 0x21, 0 + .dw 0xf140, 0xc08a, 0xf17f, 0xc08a, 0x21, 0 + .dw 0xf1c0, 0xc08a, 0xf1ff, 0xc08a, 0x21, 0 + .dw 0xf240, 0xc08a, 0xf27f, 0xc08a, 0x21, 0 + .dw 0xf2c0, 0xc08a, 0xf2ff, 0xc08a, 0x21, 0 + .dw 0xf340, 0xc08a, 0xf37f, 0xc08a, 0x21, 0 + .dw 0xf3c0, 0xc08a, 0xf3ff, 0xc08a, 0x21, 0 + .dw 0xf440, 0xc08a, 0xf47f, 0xc08a, 0x21, 0 + .dw 0xf4c0, 0xc08a, 0xf4ff, 0xc08a, 0x21, 0 + .dw 0xf540, 0xc08a, 0xf57f, 0xc08a, 0x21, 0 + .dw 0xf5c0, 0xc08a, 0xf5ff, 0xc08a, 0x21, 0 + .dw 0xf640, 0xc08a, 0xf67f, 0xc08a, 0x21, 0 + .dw 0xf6c0, 0xc08a, 0xf6ff, 0xc08a, 0x21, 0 + .dw 0xf740, 0xc08a, 0xf77f, 0xc08a, 0x21, 0 + .dw 0xf7c0, 0xc08a, 0xf7ff, 0xc08a, 0x21, 0 + .dw 0xf840, 0xc08a, 0xf87f, 0xc08a, 0x21, 0 + .dw 0xf8c0, 0xc08a, 0xf8ff, 0xc08a, 0x21, 0 + .dw 0xf940, 0xc08a, 0xf97f, 0xc08a, 0x21, 0 + .dw 0xf9c0, 0xc08a, 0x1fff, 0xc08b, 0x21, 0 + .dw 0x2040, 0xc08b, 0x207f, 0xc08b, 0x21, 0 + .dw 0x20c0, 0xc08b, 0x20ff, 0xc08b, 0x21, 0 + .dw 0x2140, 0xc08b, 0x217f, 0xc08b, 0x21, 0 + .dw 0x21c0, 0xc08b, 0x21ff, 0xc08b, 0x21, 0 + .dw 0x2240, 0xc08b, 0x227f, 0xc08b, 0x21, 0 + .dw 0x22c0, 0xc08b, 0x22ff, 0xc08b, 0x21, 0 + .dw 0x2340, 0xc08b, 0x237f, 0xc08b, 0x21, 0 + .dw 0x23c0, 0xc08b, 0x23ff, 0xc08b, 0x21, 0 + .dw 0x2440, 0xc08b, 0x247f, 0xc08b, 0x21, 0 + .dw 0x24c0, 0xc08b, 0x24ff, 0xc08b, 0x21, 0 + .dw 0x2540, 0xc08b, 0x257f, 0xc08b, 0x21, 0 + .dw 0x25c0, 0xc08b, 0x25ff, 0xc08b, 0x21, 0 + .dw 0x2640, 0xc08b, 0x267f, 0xc08b, 0x21, 0 + .dw 0x26c0, 0xc08b, 0x26ff, 0xc08b, 0x21, 0 + .dw 0x2740, 0xc08b, 0x277f, 0xc08b, 0x21, 0 + .dw 0x27c0, 0xc08b, 0x27ff, 0xc08b, 0x21, 0 + .dw 0x2840, 0xc08b, 0x287f, 0xc08b, 0x21, 0 + .dw 0x28c0, 0xc08b, 0x28ff, 0xc08b, 0x21, 0 + .dw 0x2940, 0xc08b, 0x297f, 0xc08b, 0x21, 0 + .dw 0x29c0, 0xc08b, 0x29ff, 0xc08b, 0x21, 0 + .dw 0x2a40, 0xc08b, 0x2a7f, 0xc08b, 0x21, 0 + .dw 0x2ac0, 0xc08b, 0x2aff, 0xc08b, 0x21, 0 + .dw 0x2b40, 0xc08b, 0x2b7f, 0xc08b, 0x21, 0 + .dw 0x2bc0, 0xc08b, 0x2bff, 0xc08b, 0x21, 0 + .dw 0x2c40, 0xc08b, 0x2c7f, 0xc08b, 0x21, 0 + .dw 0x2cc0, 0xc08b, 0x2cff, 0xc08b, 0x21, 0 + .dw 0x2d40, 0xc08b, 0x2d7f, 0xc08b, 0x21, 0 + .dw 0x2dc0, 0xc08b, 0x2dff, 0xc08b, 0x21, 0 + .dw 0x2e40, 0xc08b, 0x2e7f, 0xc08b, 0x21, 0 + .dw 0x2ec0, 0xc08b, 0x2eff, 0xc08b, 0x21, 0 + .dw 0x2f40, 0xc08b, 0x2f7f, 0xc08b, 0x21, 0 + .dw 0x2fc0, 0xc08b, 0x2fff, 0xc08b, 0x21, 0 + .dw 0x3040, 0xc08b, 0x307f, 0xc08b, 0x21, 0 + .dw 0x30c0, 0xc08b, 0x30ff, 0xc08b, 0x21, 0 + .dw 0x3140, 0xc08b, 0x317f, 0xc08b, 0x21, 0 + .dw 0x31c0, 0xc08b, 0x31ff, 0xc08b, 0x21, 0 + .dw 0x3240, 0xc08b, 0x327f, 0xc08b, 0x21, 0 + .dw 0x32c0, 0xc08b, 0x32ff, 0xc08b, 0x21, 0 + .dw 0x3340, 0xc08b, 0x337f, 0xc08b, 0x21, 0 + .dw 0x33c0, 0xc08b, 0x33ff, 0xc08b, 0x21, 0 + .dw 0x3440, 0xc08b, 0x347f, 0xc08b, 0x21, 0 + .dw 0x34c0, 0xc08b, 0x34ff, 0xc08b, 0x21, 0 + .dw 0x3540, 0xc08b, 0x357f, 0xc08b, 0x21, 0 + .dw 0x35c0, 0xc08b, 0x35ff, 0xc08b, 0x21, 0 + .dw 0x3640, 0xc08b, 0x367f, 0xc08b, 0x21, 0 + .dw 0x36c0, 0xc08b, 0x36ff, 0xc08b, 0x21, 0 + .dw 0x3740, 0xc08b, 0x377f, 0xc08b, 0x21, 0 + .dw 0x37c0, 0xc08b, 0x37ff, 0xc08b, 0x21, 0 + .dw 0x3840, 0xc08b, 0x387f, 0xc08b, 0x21, 0 + .dw 0x38c0, 0xc08b, 0x38ff, 0xc08b, 0x21, 0 + .dw 0x3940, 0xc08b, 0x397f, 0xc08b, 0x21, 0 + .dw 0x39c0, 0xc08b, 0xffff, 0xc08b, 0x21, 0 + .dw 0x0040, 0xc08c, 0x007f, 0xc08c, 0x21, 0 + .dw 0x00c0, 0xc08c, 0x00ff, 0xc08c, 0x21, 0 + .dw 0x0140, 0xc08c, 0x017f, 0xc08c, 0x21, 0 + .dw 0x01c0, 0xc08c, 0x01ff, 0xc08c, 0x21, 0 + .dw 0x0240, 0xc08c, 0x027f, 0xc08c, 0x21, 0 + .dw 0x02c0, 0xc08c, 0x02ff, 0xc08c, 0x21, 0 + .dw 0x0340, 0xc08c, 0x037f, 0xc08c, 0x21, 0 + .dw 0x03c0, 0xc08c, 0x03ff, 0xc08c, 0x21, 0 + .dw 0x0440, 0xc08c, 0x047f, 0xc08c, 0x21, 0 + .dw 0x04c0, 0xc08c, 0x04ff, 0xc08c, 0x21, 0 + .dw 0x0540, 0xc08c, 0x057f, 0xc08c, 0x21, 0 + .dw 0x05c0, 0xc08c, 0x05ff, 0xc08c, 0x21, 0 + .dw 0x0640, 0xc08c, 0x067f, 0xc08c, 0x21, 0 + .dw 0x06c0, 0xc08c, 0x06ff, 0xc08c, 0x21, 0 + .dw 0x0740, 0xc08c, 0x077f, 0xc08c, 0x21, 0 + .dw 0x07c0, 0xc08c, 0x07ff, 0xc08c, 0x21, 0 + .dw 0x0840, 0xc08c, 0x087f, 0xc08c, 0x21, 0 + .dw 0x08c0, 0xc08c, 0x08ff, 0xc08c, 0x21, 0 + .dw 0x0940, 0xc08c, 0x097f, 0xc08c, 0x21, 0 + .dw 0x09c0, 0xc08c, 0x09ff, 0xc08c, 0x21, 0 + .dw 0x0a40, 0xc08c, 0x0a7f, 0xc08c, 0x21, 0 + .dw 0x0ac0, 0xc08c, 0x0aff, 0xc08c, 0x21, 0 + .dw 0x0b40, 0xc08c, 0x0b7f, 0xc08c, 0x21, 0 + .dw 0x0bc0, 0xc08c, 0x0bff, 0xc08c, 0x21, 0 + .dw 0x0c40, 0xc08c, 0x0c7f, 0xc08c, 0x21, 0 + .dw 0x0cc0, 0xc08c, 0x0cff, 0xc08c, 0x21, 0 + .dw 0x0d40, 0xc08c, 0x0d7f, 0xc08c, 0x21, 0 + .dw 0x0dc0, 0xc08c, 0x0dff, 0xc08c, 0x21, 0 + .dw 0x0e40, 0xc08c, 0x0e7f, 0xc08c, 0x21, 0 + .dw 0x0ec0, 0xc08c, 0x0eff, 0xc08c, 0x21, 0 + .dw 0x0f40, 0xc08c, 0x0f7f, 0xc08c, 0x21, 0 + .dw 0x0fc0, 0xc08c, 0x0fff, 0xc08c, 0x21, 0 + .dw 0x1040, 0xc08c, 0x107f, 0xc08c, 0x21, 0 + .dw 0x10c0, 0xc08c, 0x10ff, 0xc08c, 0x21, 0 + .dw 0x1140, 0xc08c, 0x117f, 0xc08c, 0x21, 0 + .dw 0x11c0, 0xc08c, 0x11ff, 0xc08c, 0x21, 0 + .dw 0x1240, 0xc08c, 0x127f, 0xc08c, 0x21, 0 + .dw 0x12c0, 0xc08c, 0x12ff, 0xc08c, 0x21, 0 + .dw 0x1340, 0xc08c, 0x137f, 0xc08c, 0x21, 0 + .dw 0x13c0, 0xc08c, 0x13ff, 0xc08c, 0x21, 0 + .dw 0x1440, 0xc08c, 0x147f, 0xc08c, 0x21, 0 + .dw 0x14c0, 0xc08c, 0x14ff, 0xc08c, 0x21, 0 + .dw 0x1540, 0xc08c, 0x157f, 0xc08c, 0x21, 0 + .dw 0x15c0, 0xc08c, 0x15ff, 0xc08c, 0x21, 0 + .dw 0x1640, 0xc08c, 0x167f, 0xc08c, 0x21, 0 + .dw 0x16c0, 0xc08c, 0x16ff, 0xc08c, 0x21, 0 + .dw 0x1740, 0xc08c, 0x177f, 0xc08c, 0x21, 0 + .dw 0x17c0, 0xc08c, 0x17ff, 0xc08c, 0x21, 0 + .dw 0x1840, 0xc08c, 0x187f, 0xc08c, 0x21, 0 + .dw 0x18c0, 0xc08c, 0x18ff, 0xc08c, 0x21, 0 + .dw 0x1940, 0xc08c, 0x197f, 0xc08c, 0x21, 0 + .dw 0x19c0, 0xc08c, 0x1fff, 0xc08c, 0x21, 0 + .dw 0x2040, 0xc08c, 0x207f, 0xc08c, 0x21, 0 + .dw 0x20c0, 0xc08c, 0x20ff, 0xc08c, 0x21, 0 + .dw 0x2140, 0xc08c, 0x217f, 0xc08c, 0x21, 0 + .dw 0x21c0, 0xc08c, 0x21ff, 0xc08c, 0x21, 0 + .dw 0x2240, 0xc08c, 0x227f, 0xc08c, 0x21, 0 + .dw 0x22c0, 0xc08c, 0x22ff, 0xc08c, 0x21, 0 + .dw 0x2340, 0xc08c, 0x237f, 0xc08c, 0x21, 0 + .dw 0x23c0, 0xc08c, 0x23ff, 0xc08c, 0x21, 0 + .dw 0x2440, 0xc08c, 0x247f, 0xc08c, 0x21, 0 + .dw 0x24c0, 0xc08c, 0x24ff, 0xc08c, 0x21, 0 + .dw 0x2540, 0xc08c, 0x257f, 0xc08c, 0x21, 0 + .dw 0x25c0, 0xc08c, 0x25ff, 0xc08c, 0x21, 0 + .dw 0x2640, 0xc08c, 0x267f, 0xc08c, 0x21, 0 + .dw 0x26c0, 0xc08c, 0x26ff, 0xc08c, 0x21, 0 + .dw 0x2740, 0xc08c, 0x277f, 0xc08c, 0x21, 0 + .dw 0x27c0, 0xc08c, 0x27ff, 0xc08c, 0x21, 0 + .dw 0x2840, 0xc08c, 0x287f, 0xc08c, 0x21, 0 + .dw 0x28c0, 0xc08c, 0x28ff, 0xc08c, 0x21, 0 + .dw 0x2940, 0xc08c, 0x297f, 0xc08c, 0x21, 0 + .dw 0x29c0, 0xc08c, 0x29ff, 0xc08c, 0x21, 0 + .dw 0x2a40, 0xc08c, 0x2a7f, 0xc08c, 0x21, 0 + .dw 0x2ac0, 0xc08c, 0x2aff, 0xc08c, 0x21, 0 + .dw 0x2b40, 0xc08c, 0x2b7f, 0xc08c, 0x21, 0 + .dw 0x2bc0, 0xc08c, 0x2bff, 0xc08c, 0x21, 0 + .dw 0x2c40, 0xc08c, 0x2c7f, 0xc08c, 0x21, 0 + .dw 0x2cc0, 0xc08c, 0x2cff, 0xc08c, 0x21, 0 + .dw 0x2d40, 0xc08c, 0x2d7f, 0xc08c, 0x21, 0 + .dw 0x2dc0, 0xc08c, 0x2dff, 0xc08c, 0x21, 0 + .dw 0x2e40, 0xc08c, 0x2e7f, 0xc08c, 0x21, 0 + .dw 0x2ec0, 0xc08c, 0x2eff, 0xc08c, 0x21, 0 + .dw 0x2f40, 0xc08c, 0x2f7f, 0xc08c, 0x21, 0 + .dw 0x2fc0, 0xc08c, 0x2fff, 0xc08c, 0x21, 0 + .dw 0x3040, 0xc08c, 0x307f, 0xc08c, 0x21, 0 + .dw 0x30c0, 0xc08c, 0x30ff, 0xc08c, 0x21, 0 + .dw 0x3140, 0xc08c, 0x317f, 0xc08c, 0x21, 0 + .dw 0x31c0, 0xc08c, 0x31ff, 0xc08c, 0x21, 0 + .dw 0x3240, 0xc08c, 0x327f, 0xc08c, 0x21, 0 + .dw 0x32c0, 0xc08c, 0x32ff, 0xc08c, 0x21, 0 + .dw 0x3340, 0xc08c, 0x337f, 0xc08c, 0x21, 0 + .dw 0x33c0, 0xc08c, 0x33ff, 0xc08c, 0x21, 0 + .dw 0x3440, 0xc08c, 0x347f, 0xc08c, 0x21, 0 + .dw 0x34c0, 0xc08c, 0x34ff, 0xc08c, 0x21, 0 + .dw 0x3540, 0xc08c, 0x357f, 0xc08c, 0x21, 0 + .dw 0x35c0, 0xc08c, 0x35ff, 0xc08c, 0x21, 0 + .dw 0x3640, 0xc08c, 0x367f, 0xc08c, 0x21, 0 + .dw 0x36c0, 0xc08c, 0x36ff, 0xc08c, 0x21, 0 + .dw 0x3740, 0xc08c, 0x377f, 0xc08c, 0x21, 0 + .dw 0x37c0, 0xc08c, 0x37ff, 0xc08c, 0x21, 0 + .dw 0x3840, 0xc08c, 0x387f, 0xc08c, 0x21, 0 + .dw 0x38c0, 0xc08c, 0x38ff, 0xc08c, 0x21, 0 + .dw 0x3940, 0xc08c, 0x397f, 0xc08c, 0x21, 0 + .dw 0x39c0, 0xc08c, 0x3fff, 0xc08c, 0x21, 0 + .dw 0x4040, 0xc08c, 0x407f, 0xc08c, 0x21, 0 + .dw 0x40c0, 0xc08c, 0x40ff, 0xc08c, 0x21, 0 + .dw 0x4140, 0xc08c, 0x417f, 0xc08c, 0x21, 0 + .dw 0x41c0, 0xc08c, 0x41ff, 0xc08c, 0x21, 0 + .dw 0x4240, 0xc08c, 0x427f, 0xc08c, 0x21, 0 + .dw 0x42c0, 0xc08c, 0x42ff, 0xc08c, 0x21, 0 + .dw 0x4340, 0xc08c, 0x437f, 0xc08c, 0x21, 0 + .dw 0x43c0, 0xc08c, 0x43ff, 0xc08c, 0x21, 0 + .dw 0x4440, 0xc08c, 0x447f, 0xc08c, 0x21, 0 + .dw 0x44c0, 0xc08c, 0x44ff, 0xc08c, 0x21, 0 + .dw 0x4540, 0xc08c, 0x457f, 0xc08c, 0x21, 0 + .dw 0x45c0, 0xc08c, 0x45ff, 0xc08c, 0x21, 0 + .dw 0x4640, 0xc08c, 0x467f, 0xc08c, 0x21, 0 + .dw 0x46c0, 0xc08c, 0x46ff, 0xc08c, 0x21, 0 + .dw 0x4740, 0xc08c, 0x477f, 0xc08c, 0x21, 0 + .dw 0x47c0, 0xc08c, 0x47ff, 0xc08c, 0x21, 0 + .dw 0x4840, 0xc08c, 0x487f, 0xc08c, 0x21, 0 + .dw 0x48c0, 0xc08c, 0x48ff, 0xc08c, 0x21, 0 + .dw 0x4940, 0xc08c, 0x497f, 0xc08c, 0x21, 0 + .dw 0x49c0, 0xc08c, 0x49ff, 0xc08c, 0x21, 0 + .dw 0x4a40, 0xc08c, 0x4a7f, 0xc08c, 0x21, 0 + .dw 0x4ac0, 0xc08c, 0x4aff, 0xc08c, 0x21, 0 + .dw 0x4b40, 0xc08c, 0x4b7f, 0xc08c, 0x21, 0 + .dw 0x4bc0, 0xc08c, 0x4bff, 0xc08c, 0x21, 0 + .dw 0x4c40, 0xc08c, 0x4c7f, 0xc08c, 0x21, 0 + .dw 0x4cc0, 0xc08c, 0x4cff, 0xc08c, 0x21, 0 + .dw 0x4d40, 0xc08c, 0x4d7f, 0xc08c, 0x21, 0 + .dw 0x4dc0, 0xc08c, 0x4dff, 0xc08c, 0x21, 0 + .dw 0x4e40, 0xc08c, 0x4e7f, 0xc08c, 0x21, 0 + .dw 0x4ec0, 0xc08c, 0x4eff, 0xc08c, 0x21, 0 + .dw 0x4f40, 0xc08c, 0x4f7f, 0xc08c, 0x21, 0 + .dw 0x4fc0, 0xc08c, 0x4fff, 0xc08c, 0x21, 0 + .dw 0x5040, 0xc08c, 0x507f, 0xc08c, 0x21, 0 + .dw 0x50c0, 0xc08c, 0x50ff, 0xc08c, 0x21, 0 + .dw 0x5140, 0xc08c, 0x517f, 0xc08c, 0x21, 0 + .dw 0x51c0, 0xc08c, 0x51ff, 0xc08c, 0x21, 0 + .dw 0x5240, 0xc08c, 0x527f, 0xc08c, 0x21, 0 + .dw 0x52c0, 0xc08c, 0x52ff, 0xc08c, 0x21, 0 + .dw 0x5340, 0xc08c, 0x537f, 0xc08c, 0x21, 0 + .dw 0x53c0, 0xc08c, 0x53ff, 0xc08c, 0x21, 0 + .dw 0x5440, 0xc08c, 0x547f, 0xc08c, 0x21, 0 + .dw 0x54c0, 0xc08c, 0x54ff, 0xc08c, 0x21, 0 + .dw 0x5540, 0xc08c, 0x557f, 0xc08c, 0x21, 0 + .dw 0x55c0, 0xc08c, 0x55ff, 0xc08c, 0x21, 0 + .dw 0x5640, 0xc08c, 0x567f, 0xc08c, 0x21, 0 + .dw 0x56c0, 0xc08c, 0x56ff, 0xc08c, 0x21, 0 + .dw 0x5740, 0xc08c, 0x577f, 0xc08c, 0x21, 0 + .dw 0x57c0, 0xc08c, 0x57ff, 0xc08c, 0x21, 0 + .dw 0x5840, 0xc08c, 0x587f, 0xc08c, 0x21, 0 + .dw 0x58c0, 0xc08c, 0x58ff, 0xc08c, 0x21, 0 + .dw 0x5940, 0xc08c, 0x597f, 0xc08c, 0x21, 0 + .dw 0x59c0, 0xc08c, 0x5fff, 0xc08c, 0x21, 0 + .dw 0x6040, 0xc08c, 0x607f, 0xc08c, 0x21, 0 + .dw 0x60c0, 0xc08c, 0x60ff, 0xc08c, 0x21, 0 + .dw 0x6140, 0xc08c, 0x617f, 0xc08c, 0x21, 0 + .dw 0x61c0, 0xc08c, 0x61ff, 0xc08c, 0x21, 0 + .dw 0x6240, 0xc08c, 0x627f, 0xc08c, 0x21, 0 + .dw 0x62c0, 0xc08c, 0x62ff, 0xc08c, 0x21, 0 + .dw 0x6340, 0xc08c, 0x637f, 0xc08c, 0x21, 0 + .dw 0x63c0, 0xc08c, 0x63ff, 0xc08c, 0x21, 0 + .dw 0x6440, 0xc08c, 0x647f, 0xc08c, 0x21, 0 + .dw 0x64c0, 0xc08c, 0x64ff, 0xc08c, 0x21, 0 + .dw 0x6540, 0xc08c, 0x657f, 0xc08c, 0x21, 0 + .dw 0x65c0, 0xc08c, 0x65ff, 0xc08c, 0x21, 0 + .dw 0x6640, 0xc08c, 0x667f, 0xc08c, 0x21, 0 + .dw 0x66c0, 0xc08c, 0x66ff, 0xc08c, 0x21, 0 + .dw 0x6740, 0xc08c, 0x677f, 0xc08c, 0x21, 0 + .dw 0x67c0, 0xc08c, 0x67ff, 0xc08c, 0x21, 0 + .dw 0x6840, 0xc08c, 0x687f, 0xc08c, 0x21, 0 + .dw 0x68c0, 0xc08c, 0x68ff, 0xc08c, 0x21, 0 + .dw 0x6940, 0xc08c, 0x697f, 0xc08c, 0x21, 0 + .dw 0x69c0, 0xc08c, 0x69ff, 0xc08c, 0x21, 0 + .dw 0x6a40, 0xc08c, 0x6a7f, 0xc08c, 0x21, 0 + .dw 0x6ac0, 0xc08c, 0x6aff, 0xc08c, 0x21, 0 + .dw 0x6b40, 0xc08c, 0x6b7f, 0xc08c, 0x21, 0 + .dw 0x6bc0, 0xc08c, 0x6bff, 0xc08c, 0x21, 0 + .dw 0x6c40, 0xc08c, 0x6c7f, 0xc08c, 0x21, 0 + .dw 0x6cc0, 0xc08c, 0x6cff, 0xc08c, 0x21, 0 + .dw 0x6d40, 0xc08c, 0x6d7f, 0xc08c, 0x21, 0 + .dw 0x6dc0, 0xc08c, 0x6dff, 0xc08c, 0x21, 0 + .dw 0x6e40, 0xc08c, 0x6e7f, 0xc08c, 0x21, 0 + .dw 0x6ec0, 0xc08c, 0x6eff, 0xc08c, 0x21, 0 + .dw 0x6f40, 0xc08c, 0x6f7f, 0xc08c, 0x21, 0 + .dw 0x6fc0, 0xc08c, 0x6fff, 0xc08c, 0x21, 0 + .dw 0x7040, 0xc08c, 0x707f, 0xc08c, 0x21, 0 + .dw 0x70c0, 0xc08c, 0x70ff, 0xc08c, 0x21, 0 + .dw 0x7140, 0xc08c, 0x717f, 0xc08c, 0x21, 0 + .dw 0x71c0, 0xc08c, 0x71ff, 0xc08c, 0x21, 0 + .dw 0x7240, 0xc08c, 0x727f, 0xc08c, 0x21, 0 + .dw 0x72c0, 0xc08c, 0x72ff, 0xc08c, 0x21, 0 + .dw 0x7340, 0xc08c, 0x737f, 0xc08c, 0x21, 0 + .dw 0x73c0, 0xc08c, 0x73ff, 0xc08c, 0x21, 0 + .dw 0x7440, 0xc08c, 0x747f, 0xc08c, 0x21, 0 + .dw 0x74c0, 0xc08c, 0x74ff, 0xc08c, 0x21, 0 + .dw 0x7540, 0xc08c, 0x757f, 0xc08c, 0x21, 0 + .dw 0x75c0, 0xc08c, 0x75ff, 0xc08c, 0x21, 0 + .dw 0x7640, 0xc08c, 0x767f, 0xc08c, 0x21, 0 + .dw 0x76c0, 0xc08c, 0x76ff, 0xc08c, 0x21, 0 + .dw 0x7740, 0xc08c, 0x777f, 0xc08c, 0x21, 0 + .dw 0x77c0, 0xc08c, 0x77ff, 0xc08c, 0x21, 0 + .dw 0x7840, 0xc08c, 0x787f, 0xc08c, 0x21, 0 + .dw 0x78c0, 0xc08c, 0x78ff, 0xc08c, 0x21, 0 + .dw 0x7940, 0xc08c, 0x797f, 0xc08c, 0x21, 0 + .dw 0x79c0, 0xc08c, 0x7fff, 0xc08c, 0x21, 0 + .dw 0x8040, 0xc08c, 0x807f, 0xc08c, 0x21, 0 + .dw 0x80c0, 0xc08c, 0x80ff, 0xc08c, 0x21, 0 + .dw 0x8140, 0xc08c, 0x817f, 0xc08c, 0x21, 0 + .dw 0x81c0, 0xc08c, 0x81ff, 0xc08c, 0x21, 0 + .dw 0x8240, 0xc08c, 0x827f, 0xc08c, 0x21, 0 + .dw 0x82c0, 0xc08c, 0x82ff, 0xc08c, 0x21, 0 + .dw 0x8340, 0xc08c, 0x837f, 0xc08c, 0x21, 0 + .dw 0x83c0, 0xc08c, 0x83ff, 0xc08c, 0x21, 0 + .dw 0x8440, 0xc08c, 0x847f, 0xc08c, 0x21, 0 + .dw 0x84c0, 0xc08c, 0x84ff, 0xc08c, 0x21, 0 + .dw 0x8540, 0xc08c, 0x857f, 0xc08c, 0x21, 0 + .dw 0x85c0, 0xc08c, 0x85ff, 0xc08c, 0x21, 0 + .dw 0x8640, 0xc08c, 0x867f, 0xc08c, 0x21, 0 + .dw 0x86c0, 0xc08c, 0x86ff, 0xc08c, 0x21, 0 + .dw 0x8740, 0xc08c, 0x877f, 0xc08c, 0x21, 0 + .dw 0x87c0, 0xc08c, 0x87ff, 0xc08c, 0x21, 0 + .dw 0x8840, 0xc08c, 0x887f, 0xc08c, 0x21, 0 + .dw 0x88c0, 0xc08c, 0x88ff, 0xc08c, 0x21, 0 + .dw 0x8940, 0xc08c, 0x897f, 0xc08c, 0x21, 0 + .dw 0x89c0, 0xc08c, 0x89ff, 0xc08c, 0x21, 0 + .dw 0x8a40, 0xc08c, 0x8a7f, 0xc08c, 0x21, 0 + .dw 0x8ac0, 0xc08c, 0x8aff, 0xc08c, 0x21, 0 + .dw 0x8b40, 0xc08c, 0x8b7f, 0xc08c, 0x21, 0 + .dw 0x8bc0, 0xc08c, 0x8bff, 0xc08c, 0x21, 0 + .dw 0x8c40, 0xc08c, 0x8c7f, 0xc08c, 0x21, 0 + .dw 0x8cc0, 0xc08c, 0x8cff, 0xc08c, 0x21, 0 + .dw 0x8d40, 0xc08c, 0x8d7f, 0xc08c, 0x21, 0 + .dw 0x8dc0, 0xc08c, 0x8dff, 0xc08c, 0x21, 0 + .dw 0x8e40, 0xc08c, 0x8e7f, 0xc08c, 0x21, 0 + .dw 0x8ec0, 0xc08c, 0x8eff, 0xc08c, 0x21, 0 + .dw 0x8f40, 0xc08c, 0x8f7f, 0xc08c, 0x21, 0 + .dw 0x8fc0, 0xc08c, 0x8fff, 0xc08c, 0x21, 0 + .dw 0x9040, 0xc08c, 0x907f, 0xc08c, 0x21, 0 + .dw 0x90c0, 0xc08c, 0x90ff, 0xc08c, 0x21, 0 + .dw 0x9140, 0xc08c, 0x917f, 0xc08c, 0x21, 0 + .dw 0x91c0, 0xc08c, 0x91ff, 0xc08c, 0x21, 0 + .dw 0x9240, 0xc08c, 0x927f, 0xc08c, 0x21, 0 + .dw 0x92c0, 0xc08c, 0x92ff, 0xc08c, 0x21, 0 + .dw 0x9340, 0xc08c, 0x937f, 0xc08c, 0x21, 0 + .dw 0x93c0, 0xc08c, 0x93ff, 0xc08c, 0x21, 0 + .dw 0x9440, 0xc08c, 0x947f, 0xc08c, 0x21, 0 + .dw 0x94c0, 0xc08c, 0x94ff, 0xc08c, 0x21, 0 + .dw 0x9540, 0xc08c, 0x957f, 0xc08c, 0x21, 0 + .dw 0x95c0, 0xc08c, 0x95ff, 0xc08c, 0x21, 0 + .dw 0x9640, 0xc08c, 0x967f, 0xc08c, 0x21, 0 + .dw 0x96c0, 0xc08c, 0x96ff, 0xc08c, 0x21, 0 + .dw 0x9740, 0xc08c, 0x977f, 0xc08c, 0x21, 0 + .dw 0x97c0, 0xc08c, 0x97ff, 0xc08c, 0x21, 0 + .dw 0x9840, 0xc08c, 0x987f, 0xc08c, 0x21, 0 + .dw 0x98c0, 0xc08c, 0x98ff, 0xc08c, 0x21, 0 + .dw 0x9940, 0xc08c, 0x997f, 0xc08c, 0x21, 0 + .dw 0x99c0, 0xc08c, 0x9fff, 0xc08c, 0x21, 0 + .dw 0xa040, 0xc08c, 0xa07f, 0xc08c, 0x21, 0 + .dw 0xa0c0, 0xc08c, 0xa0ff, 0xc08c, 0x21, 0 + .dw 0xa140, 0xc08c, 0xa17f, 0xc08c, 0x21, 0 + .dw 0xa1c0, 0xc08c, 0xa1ff, 0xc08c, 0x21, 0 + .dw 0xa240, 0xc08c, 0xa27f, 0xc08c, 0x21, 0 + .dw 0xa2c0, 0xc08c, 0xa2ff, 0xc08c, 0x21, 0 + .dw 0xa340, 0xc08c, 0xa37f, 0xc08c, 0x21, 0 + .dw 0xa3c0, 0xc08c, 0xa3ff, 0xc08c, 0x21, 0 + .dw 0xa440, 0xc08c, 0xa47f, 0xc08c, 0x21, 0 + .dw 0xa4c0, 0xc08c, 0xa4ff, 0xc08c, 0x21, 0 + .dw 0xa540, 0xc08c, 0xa57f, 0xc08c, 0x21, 0 + .dw 0xa5c0, 0xc08c, 0xa5ff, 0xc08c, 0x21, 0 + .dw 0xa640, 0xc08c, 0xa67f, 0xc08c, 0x21, 0 + .dw 0xa6c0, 0xc08c, 0xa6ff, 0xc08c, 0x21, 0 + .dw 0xa740, 0xc08c, 0xa77f, 0xc08c, 0x21, 0 + .dw 0xa7c0, 0xc08c, 0xa7ff, 0xc08c, 0x21, 0 + .dw 0xa840, 0xc08c, 0xa87f, 0xc08c, 0x21, 0 + .dw 0xa8c0, 0xc08c, 0xa8ff, 0xc08c, 0x21, 0 + .dw 0xa940, 0xc08c, 0xa97f, 0xc08c, 0x21, 0 + .dw 0xa9c0, 0xc08c, 0xa9ff, 0xc08c, 0x21, 0 + .dw 0xaa40, 0xc08c, 0xaa7f, 0xc08c, 0x21, 0 + .dw 0xaac0, 0xc08c, 0xaaff, 0xc08c, 0x21, 0 + .dw 0xab40, 0xc08c, 0xab7f, 0xc08c, 0x21, 0 + .dw 0xabc0, 0xc08c, 0xabff, 0xc08c, 0x21, 0 + .dw 0xac40, 0xc08c, 0xac7f, 0xc08c, 0x21, 0 + .dw 0xacc0, 0xc08c, 0xacff, 0xc08c, 0x21, 0 + .dw 0xad40, 0xc08c, 0xad7f, 0xc08c, 0x21, 0 + .dw 0xadc0, 0xc08c, 0xadff, 0xc08c, 0x21, 0 + .dw 0xae40, 0xc08c, 0xae7f, 0xc08c, 0x21, 0 + .dw 0xaec0, 0xc08c, 0xaeff, 0xc08c, 0x21, 0 + .dw 0xaf40, 0xc08c, 0xaf7f, 0xc08c, 0x21, 0 + .dw 0xafc0, 0xc08c, 0xafff, 0xc08c, 0x21, 0 + .dw 0xb040, 0xc08c, 0xb07f, 0xc08c, 0x21, 0 + .dw 0xb0c0, 0xc08c, 0xb0ff, 0xc08c, 0x21, 0 + .dw 0xb140, 0xc08c, 0xb17f, 0xc08c, 0x21, 0 + .dw 0xb1c0, 0xc08c, 0xb1ff, 0xc08c, 0x21, 0 + .dw 0xb240, 0xc08c, 0xb27f, 0xc08c, 0x21, 0 + .dw 0xb2c0, 0xc08c, 0xb2ff, 0xc08c, 0x21, 0 + .dw 0xb340, 0xc08c, 0xb37f, 0xc08c, 0x21, 0 + .dw 0xb3c0, 0xc08c, 0xb3ff, 0xc08c, 0x21, 0 + .dw 0xb440, 0xc08c, 0xb47f, 0xc08c, 0x21, 0 + .dw 0xb4c0, 0xc08c, 0xb4ff, 0xc08c, 0x21, 0 + .dw 0xb540, 0xc08c, 0xb57f, 0xc08c, 0x21, 0 + .dw 0xb5c0, 0xc08c, 0xb5ff, 0xc08c, 0x21, 0 + .dw 0xb640, 0xc08c, 0xb67f, 0xc08c, 0x21, 0 + .dw 0xb6c0, 0xc08c, 0xb6ff, 0xc08c, 0x21, 0 + .dw 0xb740, 0xc08c, 0xb77f, 0xc08c, 0x21, 0 + .dw 0xb7c0, 0xc08c, 0xb7ff, 0xc08c, 0x21, 0 + .dw 0xb840, 0xc08c, 0xb87f, 0xc08c, 0x21, 0 + .dw 0xb8c0, 0xc08c, 0xb8ff, 0xc08c, 0x21, 0 + .dw 0xb940, 0xc08c, 0xb97f, 0xc08c, 0x21, 0 + .dw 0xb9c0, 0xc08c, 0xbfff, 0xc08c, 0x21, 0 + .dw 0xc040, 0xc08c, 0xc07f, 0xc08c, 0x21, 0 + .dw 0xc0c0, 0xc08c, 0xc0ff, 0xc08c, 0x21, 0 + .dw 0xc140, 0xc08c, 0xc17f, 0xc08c, 0x21, 0 + .dw 0xc1c0, 0xc08c, 0xc1ff, 0xc08c, 0x21, 0 + .dw 0xc240, 0xc08c, 0xc27f, 0xc08c, 0x21, 0 + .dw 0xc2c0, 0xc08c, 0xc2ff, 0xc08c, 0x21, 0 + .dw 0xc340, 0xc08c, 0xc37f, 0xc08c, 0x21, 0 + .dw 0xc3c0, 0xc08c, 0xc3ff, 0xc08c, 0x21, 0 + .dw 0xc440, 0xc08c, 0xc47f, 0xc08c, 0x21, 0 + .dw 0xc4c0, 0xc08c, 0xc4ff, 0xc08c, 0x21, 0 + .dw 0xc540, 0xc08c, 0xc57f, 0xc08c, 0x21, 0 + .dw 0xc5c0, 0xc08c, 0xc5ff, 0xc08c, 0x21, 0 + .dw 0xc640, 0xc08c, 0xc67f, 0xc08c, 0x21, 0 + .dw 0xc6c0, 0xc08c, 0xc6ff, 0xc08c, 0x21, 0 + .dw 0xc740, 0xc08c, 0xc77f, 0xc08c, 0x21, 0 + .dw 0xc7c0, 0xc08c, 0xc7ff, 0xc08c, 0x21, 0 + .dw 0xc840, 0xc08c, 0xc87f, 0xc08c, 0x21, 0 + .dw 0xc8c0, 0xc08c, 0xc8ff, 0xc08c, 0x21, 0 + .dw 0xc940, 0xc08c, 0xc97f, 0xc08c, 0x21, 0 + .dw 0xc9c0, 0xc08c, 0xc9ff, 0xc08c, 0x21, 0 + .dw 0xca40, 0xc08c, 0xca7f, 0xc08c, 0x21, 0 + .dw 0xcac0, 0xc08c, 0xcaff, 0xc08c, 0x21, 0 + .dw 0xcb40, 0xc08c, 0xcb7f, 0xc08c, 0x21, 0 + .dw 0xcbc0, 0xc08c, 0xcbff, 0xc08c, 0x21, 0 + .dw 0xcc40, 0xc08c, 0xcc7f, 0xc08c, 0x21, 0 + .dw 0xccc0, 0xc08c, 0xccff, 0xc08c, 0x21, 0 + .dw 0xcd40, 0xc08c, 0xcd7f, 0xc08c, 0x21, 0 + .dw 0xcdc0, 0xc08c, 0xcdff, 0xc08c, 0x21, 0 + .dw 0xce40, 0xc08c, 0xce7f, 0xc08c, 0x21, 0 + .dw 0xcec0, 0xc08c, 0xceff, 0xc08c, 0x21, 0 + .dw 0xcf40, 0xc08c, 0xcf7f, 0xc08c, 0x21, 0 + .dw 0xcfc0, 0xc08c, 0xcfff, 0xc08c, 0x21, 0 + .dw 0xd040, 0xc08c, 0xd07f, 0xc08c, 0x21, 0 + .dw 0xd0c0, 0xc08c, 0xd0ff, 0xc08c, 0x21, 0 + .dw 0xd140, 0xc08c, 0xd17f, 0xc08c, 0x21, 0 + .dw 0xd1c0, 0xc08c, 0xd1ff, 0xc08c, 0x21, 0 + .dw 0xd240, 0xc08c, 0xd27f, 0xc08c, 0x21, 0 + .dw 0xd2c0, 0xc08c, 0xd2ff, 0xc08c, 0x21, 0 + .dw 0xd340, 0xc08c, 0xd37f, 0xc08c, 0x21, 0 + .dw 0xd3c0, 0xc08c, 0xd3ff, 0xc08c, 0x21, 0 + .dw 0xd440, 0xc08c, 0xd47f, 0xc08c, 0x21, 0 + .dw 0xd4c0, 0xc08c, 0xd4ff, 0xc08c, 0x21, 0 + .dw 0xd540, 0xc08c, 0xd57f, 0xc08c, 0x21, 0 + .dw 0xd5c0, 0xc08c, 0xd5ff, 0xc08c, 0x21, 0 + .dw 0xd640, 0xc08c, 0xd67f, 0xc08c, 0x21, 0 + .dw 0xd6c0, 0xc08c, 0xd6ff, 0xc08c, 0x21, 0 + .dw 0xd740, 0xc08c, 0xd77f, 0xc08c, 0x21, 0 + .dw 0xd7c0, 0xc08c, 0xd7ff, 0xc08c, 0x21, 0 + .dw 0xd840, 0xc08c, 0xd87f, 0xc08c, 0x21, 0 + .dw 0xd8c0, 0xc08c, 0xd8ff, 0xc08c, 0x21, 0 + .dw 0xd940, 0xc08c, 0xd97f, 0xc08c, 0x21, 0 + .dw 0xd9c0, 0xc08c, 0xdfff, 0xc08c, 0x21, 0 + .dw 0xe040, 0xc08c, 0xe07f, 0xc08c, 0x21, 0 + .dw 0xe0c0, 0xc08c, 0xe0ff, 0xc08c, 0x21, 0 + .dw 0xe140, 0xc08c, 0xe17f, 0xc08c, 0x21, 0 + .dw 0xe1c0, 0xc08c, 0xe1ff, 0xc08c, 0x21, 0 + .dw 0xe240, 0xc08c, 0xe27f, 0xc08c, 0x21, 0 + .dw 0xe2c0, 0xc08c, 0xe2ff, 0xc08c, 0x21, 0 + .dw 0xe340, 0xc08c, 0xe37f, 0xc08c, 0x21, 0 + .dw 0xe3c0, 0xc08c, 0xe3ff, 0xc08c, 0x21, 0 + .dw 0xe440, 0xc08c, 0xe47f, 0xc08c, 0x21, 0 + .dw 0xe4c0, 0xc08c, 0xe4ff, 0xc08c, 0x21, 0 + .dw 0xe540, 0xc08c, 0xe57f, 0xc08c, 0x21, 0 + .dw 0xe5c0, 0xc08c, 0xe5ff, 0xc08c, 0x21, 0 + .dw 0xe640, 0xc08c, 0xe67f, 0xc08c, 0x21, 0 + .dw 0xe6c0, 0xc08c, 0xe6ff, 0xc08c, 0x21, 0 + .dw 0xe740, 0xc08c, 0xe77f, 0xc08c, 0x21, 0 + .dw 0xe7c0, 0xc08c, 0xe7ff, 0xc08c, 0x21, 0 + .dw 0xe840, 0xc08c, 0xe87f, 0xc08c, 0x21, 0 + .dw 0xe8c0, 0xc08c, 0xe8ff, 0xc08c, 0x21, 0 + .dw 0xe940, 0xc08c, 0xe97f, 0xc08c, 0x21, 0 + .dw 0xe9c0, 0xc08c, 0xe9ff, 0xc08c, 0x21, 0 + .dw 0xea40, 0xc08c, 0xea7f, 0xc08c, 0x21, 0 + .dw 0xeac0, 0xc08c, 0xeaff, 0xc08c, 0x21, 0 + .dw 0xeb40, 0xc08c, 0xeb7f, 0xc08c, 0x21, 0 + .dw 0xebc0, 0xc08c, 0xebff, 0xc08c, 0x21, 0 + .dw 0xec40, 0xc08c, 0xec7f, 0xc08c, 0x21, 0 + .dw 0xecc0, 0xc08c, 0xecff, 0xc08c, 0x21, 0 + .dw 0xed40, 0xc08c, 0xed7f, 0xc08c, 0x21, 0 + .dw 0xedc0, 0xc08c, 0xedff, 0xc08c, 0x21, 0 + .dw 0xee40, 0xc08c, 0xee7f, 0xc08c, 0x21, 0 + .dw 0xeec0, 0xc08c, 0xeeff, 0xc08c, 0x21, 0 + .dw 0xef40, 0xc08c, 0xef7f, 0xc08c, 0x21, 0 + .dw 0xefc0, 0xc08c, 0xefff, 0xc08c, 0x21, 0 + .dw 0xf040, 0xc08c, 0xf07f, 0xc08c, 0x21, 0 + .dw 0xf0c0, 0xc08c, 0xf0ff, 0xc08c, 0x21, 0 + .dw 0xf140, 0xc08c, 0xf17f, 0xc08c, 0x21, 0 + .dw 0xf1c0, 0xc08c, 0xf1ff, 0xc08c, 0x21, 0 + .dw 0xf240, 0xc08c, 0xf27f, 0xc08c, 0x21, 0 + .dw 0xf2c0, 0xc08c, 0xf2ff, 0xc08c, 0x21, 0 + .dw 0xf340, 0xc08c, 0xf37f, 0xc08c, 0x21, 0 + .dw 0xf3c0, 0xc08c, 0xf3ff, 0xc08c, 0x21, 0 + .dw 0xf440, 0xc08c, 0xf47f, 0xc08c, 0x21, 0 + .dw 0xf4c0, 0xc08c, 0xf4ff, 0xc08c, 0x21, 0 + .dw 0xf540, 0xc08c, 0xf57f, 0xc08c, 0x21, 0 + .dw 0xf5c0, 0xc08c, 0xf5ff, 0xc08c, 0x21, 0 + .dw 0xf640, 0xc08c, 0xf67f, 0xc08c, 0x21, 0 + .dw 0xf6c0, 0xc08c, 0xf6ff, 0xc08c, 0x21, 0 + .dw 0xf740, 0xc08c, 0xf77f, 0xc08c, 0x21, 0 + .dw 0xf7c0, 0xc08c, 0xf7ff, 0xc08c, 0x21, 0 + .dw 0xf840, 0xc08c, 0xf87f, 0xc08c, 0x21, 0 + .dw 0xf8c0, 0xc08c, 0xf8ff, 0xc08c, 0x21, 0 + .dw 0xf940, 0xc08c, 0xf97f, 0xc08c, 0x21, 0 + .dw 0xf9c0, 0xc08c, 0xffff, 0xc08c, 0x21, 0 + .dw 0x0040, 0xc08d, 0x007f, 0xc08d, 0x21, 0 + .dw 0x00c0, 0xc08d, 0x00ff, 0xc08d, 0x21, 0 + .dw 0x0140, 0xc08d, 0x017f, 0xc08d, 0x21, 0 + .dw 0x01c0, 0xc08d, 0x01ff, 0xc08d, 0x21, 0 + .dw 0x0240, 0xc08d, 0x027f, 0xc08d, 0x21, 0 + .dw 0x02c0, 0xc08d, 0x02ff, 0xc08d, 0x21, 0 + .dw 0x0340, 0xc08d, 0x037f, 0xc08d, 0x21, 0 + .dw 0x03c0, 0xc08d, 0x03ff, 0xc08d, 0x21, 0 + .dw 0x0440, 0xc08d, 0x047f, 0xc08d, 0x21, 0 + .dw 0x04c0, 0xc08d, 0x04ff, 0xc08d, 0x21, 0 + .dw 0x0540, 0xc08d, 0x057f, 0xc08d, 0x21, 0 + .dw 0x05c0, 0xc08d, 0x05ff, 0xc08d, 0x21, 0 + .dw 0x0640, 0xc08d, 0x067f, 0xc08d, 0x21, 0 + .dw 0x06c0, 0xc08d, 0x06ff, 0xc08d, 0x21, 0 + .dw 0x0740, 0xc08d, 0x077f, 0xc08d, 0x21, 0 + .dw 0x07c0, 0xc08d, 0x07ff, 0xc08d, 0x21, 0 + .dw 0x0840, 0xc08d, 0x087f, 0xc08d, 0x21, 0 + .dw 0x08c0, 0xc08d, 0x08ff, 0xc08d, 0x21, 0 + .dw 0x0940, 0xc08d, 0x097f, 0xc08d, 0x21, 0 + .dw 0x09c0, 0xc08d, 0x09ff, 0xc08d, 0x21, 0 + .dw 0x0a40, 0xc08d, 0x0a7f, 0xc08d, 0x21, 0 + .dw 0x0ac0, 0xc08d, 0x0aff, 0xc08d, 0x21, 0 + .dw 0x0b40, 0xc08d, 0x0b7f, 0xc08d, 0x21, 0 + .dw 0x0bc0, 0xc08d, 0x0bff, 0xc08d, 0x21, 0 + .dw 0x0c40, 0xc08d, 0x0c7f, 0xc08d, 0x21, 0 + .dw 0x0cc0, 0xc08d, 0x0cff, 0xc08d, 0x21, 0 + .dw 0x0d40, 0xc08d, 0x0d7f, 0xc08d, 0x21, 0 + .dw 0x0dc0, 0xc08d, 0x0dff, 0xc08d, 0x21, 0 + .dw 0x0e40, 0xc08d, 0x0e7f, 0xc08d, 0x21, 0 + .dw 0x0ec0, 0xc08d, 0x0eff, 0xc08d, 0x21, 0 + .dw 0x0f40, 0xc08d, 0x0f7f, 0xc08d, 0x21, 0 + .dw 0x0fc0, 0xc08d, 0x0fff, 0xc08d, 0x21, 0 + .dw 0x1040, 0xc08d, 0x107f, 0xc08d, 0x21, 0 + .dw 0x10c0, 0xc08d, 0x10ff, 0xc08d, 0x21, 0 + .dw 0x1140, 0xc08d, 0x117f, 0xc08d, 0x21, 0 + .dw 0x11c0, 0xc08d, 0x11ff, 0xc08d, 0x21, 0 + .dw 0x1240, 0xc08d, 0x127f, 0xc08d, 0x21, 0 + .dw 0x12c0, 0xc08d, 0x12ff, 0xc08d, 0x21, 0 + .dw 0x1340, 0xc08d, 0x137f, 0xc08d, 0x21, 0 + .dw 0x13c0, 0xc08d, 0x13ff, 0xc08d, 0x21, 0 + .dw 0x1440, 0xc08d, 0x147f, 0xc08d, 0x21, 0 + .dw 0x14c0, 0xc08d, 0x14ff, 0xc08d, 0x21, 0 + .dw 0x1540, 0xc08d, 0x157f, 0xc08d, 0x21, 0 + .dw 0x15c0, 0xc08d, 0x15ff, 0xc08d, 0x21, 0 + .dw 0x1640, 0xc08d, 0x167f, 0xc08d, 0x21, 0 + .dw 0x16c0, 0xc08d, 0x16ff, 0xc08d, 0x21, 0 + .dw 0x1740, 0xc08d, 0x177f, 0xc08d, 0x21, 0 + .dw 0x17c0, 0xc08d, 0x17ff, 0xc08d, 0x21, 0 + .dw 0x1840, 0xc08d, 0x187f, 0xc08d, 0x21, 0 + .dw 0x18c0, 0xc08d, 0x18ff, 0xc08d, 0x21, 0 + .dw 0x1940, 0xc08d, 0x197f, 0xc08d, 0x21, 0 + .dw 0x19c0, 0xc08d, 0x1fff, 0xc08d, 0x21, 0 + .dw 0x2040, 0xc08d, 0x207f, 0xc08d, 0x21, 0 + .dw 0x20c0, 0xc08d, 0x20ff, 0xc08d, 0x21, 0 + .dw 0x2140, 0xc08d, 0x217f, 0xc08d, 0x21, 0 + .dw 0x21c0, 0xc08d, 0x21ff, 0xc08d, 0x21, 0 + .dw 0x2240, 0xc08d, 0x227f, 0xc08d, 0x21, 0 + .dw 0x22c0, 0xc08d, 0x22ff, 0xc08d, 0x21, 0 + .dw 0x2340, 0xc08d, 0x237f, 0xc08d, 0x21, 0 + .dw 0x23c0, 0xc08d, 0x23ff, 0xc08d, 0x21, 0 + .dw 0x2440, 0xc08d, 0x247f, 0xc08d, 0x21, 0 + .dw 0x24c0, 0xc08d, 0x24ff, 0xc08d, 0x21, 0 + .dw 0x2540, 0xc08d, 0x257f, 0xc08d, 0x21, 0 + .dw 0x25c0, 0xc08d, 0x25ff, 0xc08d, 0x21, 0 + .dw 0x2640, 0xc08d, 0x267f, 0xc08d, 0x21, 0 + .dw 0x26c0, 0xc08d, 0x26ff, 0xc08d, 0x21, 0 + .dw 0x2740, 0xc08d, 0x277f, 0xc08d, 0x21, 0 + .dw 0x27c0, 0xc08d, 0x27ff, 0xc08d, 0x21, 0 + .dw 0x2840, 0xc08d, 0x287f, 0xc08d, 0x21, 0 + .dw 0x28c0, 0xc08d, 0x28ff, 0xc08d, 0x21, 0 + .dw 0x2940, 0xc08d, 0x297f, 0xc08d, 0x21, 0 + .dw 0x29c0, 0xc08d, 0x29ff, 0xc08d, 0x21, 0 + .dw 0x2a40, 0xc08d, 0x2a7f, 0xc08d, 0x21, 0 + .dw 0x2ac0, 0xc08d, 0x2aff, 0xc08d, 0x21, 0 + .dw 0x2b40, 0xc08d, 0x2b7f, 0xc08d, 0x21, 0 + .dw 0x2bc0, 0xc08d, 0x2bff, 0xc08d, 0x21, 0 + .dw 0x2c40, 0xc08d, 0x2c7f, 0xc08d, 0x21, 0 + .dw 0x2cc0, 0xc08d, 0x2cff, 0xc08d, 0x21, 0 + .dw 0x2d40, 0xc08d, 0x2d7f, 0xc08d, 0x21, 0 + .dw 0x2dc0, 0xc08d, 0x2dff, 0xc08d, 0x21, 0 + .dw 0x2e40, 0xc08d, 0x2e7f, 0xc08d, 0x21, 0 + .dw 0x2ec0, 0xc08d, 0x2eff, 0xc08d, 0x21, 0 + .dw 0x2f40, 0xc08d, 0x2f7f, 0xc08d, 0x21, 0 + .dw 0x2fc0, 0xc08d, 0x2fff, 0xc08d, 0x21, 0 + .dw 0x3040, 0xc08d, 0x307f, 0xc08d, 0x21, 0 + .dw 0x30c0, 0xc08d, 0x30ff, 0xc08d, 0x21, 0 + .dw 0x3140, 0xc08d, 0x317f, 0xc08d, 0x21, 0 + .dw 0x31c0, 0xc08d, 0x31ff, 0xc08d, 0x21, 0 + .dw 0x3240, 0xc08d, 0x327f, 0xc08d, 0x21, 0 + .dw 0x32c0, 0xc08d, 0x32ff, 0xc08d, 0x21, 0 + .dw 0x3340, 0xc08d, 0x337f, 0xc08d, 0x21, 0 + .dw 0x33c0, 0xc08d, 0x33ff, 0xc08d, 0x21, 0 + .dw 0x3440, 0xc08d, 0x347f, 0xc08d, 0x21, 0 + .dw 0x34c0, 0xc08d, 0x34ff, 0xc08d, 0x21, 0 + .dw 0x3540, 0xc08d, 0x357f, 0xc08d, 0x21, 0 + .dw 0x35c0, 0xc08d, 0x35ff, 0xc08d, 0x21, 0 + .dw 0x3640, 0xc08d, 0x367f, 0xc08d, 0x21, 0 + .dw 0x36c0, 0xc08d, 0x36ff, 0xc08d, 0x21, 0 + .dw 0x3740, 0xc08d, 0x377f, 0xc08d, 0x21, 0 + .dw 0x37c0, 0xc08d, 0x37ff, 0xc08d, 0x21, 0 + .dw 0x3840, 0xc08d, 0x387f, 0xc08d, 0x21, 0 + .dw 0x38c0, 0xc08d, 0x38ff, 0xc08d, 0x21, 0 + .dw 0x3940, 0xc08d, 0x397f, 0xc08d, 0x21, 0 + .dw 0x39c0, 0xc08d, 0x3fff, 0xc08d, 0x21, 0 + .dw 0x4040, 0xc08d, 0x407f, 0xc08d, 0x21, 0 + .dw 0x40c0, 0xc08d, 0x40ff, 0xc08d, 0x21, 0 + .dw 0x4140, 0xc08d, 0x417f, 0xc08d, 0x21, 0 + .dw 0x41c0, 0xc08d, 0x41ff, 0xc08d, 0x21, 0 + .dw 0x4240, 0xc08d, 0x427f, 0xc08d, 0x21, 0 + .dw 0x42c0, 0xc08d, 0x42ff, 0xc08d, 0x21, 0 + .dw 0x4340, 0xc08d, 0x437f, 0xc08d, 0x21, 0 + .dw 0x43c0, 0xc08d, 0x43ff, 0xc08d, 0x21, 0 + .dw 0x4440, 0xc08d, 0x447f, 0xc08d, 0x21, 0 + .dw 0x44c0, 0xc08d, 0x44ff, 0xc08d, 0x21, 0 + .dw 0x4540, 0xc08d, 0x457f, 0xc08d, 0x21, 0 + .dw 0x45c0, 0xc08d, 0x45ff, 0xc08d, 0x21, 0 + .dw 0x4640, 0xc08d, 0x467f, 0xc08d, 0x21, 0 + .dw 0x46c0, 0xc08d, 0x46ff, 0xc08d, 0x21, 0 + .dw 0x4740, 0xc08d, 0x477f, 0xc08d, 0x21, 0 + .dw 0x47c0, 0xc08d, 0x47ff, 0xc08d, 0x21, 0 + .dw 0x4840, 0xc08d, 0x487f, 0xc08d, 0x21, 0 + .dw 0x48c0, 0xc08d, 0x48ff, 0xc08d, 0x21, 0 + .dw 0x4940, 0xc08d, 0x497f, 0xc08d, 0x21, 0 + .dw 0x49c0, 0xc08d, 0x49ff, 0xc08d, 0x21, 0 + .dw 0x4a40, 0xc08d, 0x4a7f, 0xc08d, 0x21, 0 + .dw 0x4ac0, 0xc08d, 0x4aff, 0xc08d, 0x21, 0 + .dw 0x4b40, 0xc08d, 0x4b7f, 0xc08d, 0x21, 0 + .dw 0x4bc0, 0xc08d, 0x4bff, 0xc08d, 0x21, 0 + .dw 0x4c40, 0xc08d, 0x4c7f, 0xc08d, 0x21, 0 + .dw 0x4cc0, 0xc08d, 0x4cff, 0xc08d, 0x21, 0 + .dw 0x4d40, 0xc08d, 0x4d7f, 0xc08d, 0x21, 0 + .dw 0x4dc0, 0xc08d, 0x4dff, 0xc08d, 0x21, 0 + .dw 0x4e40, 0xc08d, 0x4e7f, 0xc08d, 0x21, 0 + .dw 0x4ec0, 0xc08d, 0x4eff, 0xc08d, 0x21, 0 + .dw 0x4f40, 0xc08d, 0x4f7f, 0xc08d, 0x21, 0 + .dw 0x4fc0, 0xc08d, 0x4fff, 0xc08d, 0x21, 0 + .dw 0x5040, 0xc08d, 0x507f, 0xc08d, 0x21, 0 + .dw 0x50c0, 0xc08d, 0x50ff, 0xc08d, 0x21, 0 + .dw 0x5140, 0xc08d, 0x517f, 0xc08d, 0x21, 0 + .dw 0x51c0, 0xc08d, 0x51ff, 0xc08d, 0x21, 0 + .dw 0x5240, 0xc08d, 0x527f, 0xc08d, 0x21, 0 + .dw 0x52c0, 0xc08d, 0x52ff, 0xc08d, 0x21, 0 + .dw 0x5340, 0xc08d, 0x537f, 0xc08d, 0x21, 0 + .dw 0x53c0, 0xc08d, 0x53ff, 0xc08d, 0x21, 0 + .dw 0x5440, 0xc08d, 0x547f, 0xc08d, 0x21, 0 + .dw 0x54c0, 0xc08d, 0x54ff, 0xc08d, 0x21, 0 + .dw 0x5540, 0xc08d, 0x557f, 0xc08d, 0x21, 0 + .dw 0x55c0, 0xc08d, 0x55ff, 0xc08d, 0x21, 0 + .dw 0x5640, 0xc08d, 0x567f, 0xc08d, 0x21, 0 + .dw 0x56c0, 0xc08d, 0x56ff, 0xc08d, 0x21, 0 + .dw 0x5740, 0xc08d, 0x577f, 0xc08d, 0x21, 0 + .dw 0x57c0, 0xc08d, 0x57ff, 0xc08d, 0x21, 0 + .dw 0x5840, 0xc08d, 0x587f, 0xc08d, 0x21, 0 + .dw 0x58c0, 0xc08d, 0x58ff, 0xc08d, 0x21, 0 + .dw 0x5940, 0xc08d, 0x597f, 0xc08d, 0x21, 0 + .dw 0x59c0, 0xc08d, 0x5fff, 0xc08d, 0x21, 0 + .dw 0x6040, 0xc08d, 0x607f, 0xc08d, 0x21, 0 + .dw 0x60c0, 0xc08d, 0x60ff, 0xc08d, 0x21, 0 + .dw 0x6140, 0xc08d, 0x617f, 0xc08d, 0x21, 0 + .dw 0x61c0, 0xc08d, 0x61ff, 0xc08d, 0x21, 0 + .dw 0x6240, 0xc08d, 0x627f, 0xc08d, 0x21, 0 + .dw 0x62c0, 0xc08d, 0x62ff, 0xc08d, 0x21, 0 + .dw 0x6340, 0xc08d, 0x637f, 0xc08d, 0x21, 0 + .dw 0x63c0, 0xc08d, 0x63ff, 0xc08d, 0x21, 0 + .dw 0x6440, 0xc08d, 0x647f, 0xc08d, 0x21, 0 + .dw 0x64c0, 0xc08d, 0x64ff, 0xc08d, 0x21, 0 + .dw 0x6540, 0xc08d, 0x657f, 0xc08d, 0x21, 0 + .dw 0x65c0, 0xc08d, 0x65ff, 0xc08d, 0x21, 0 + .dw 0x6640, 0xc08d, 0x667f, 0xc08d, 0x21, 0 + .dw 0x66c0, 0xc08d, 0x66ff, 0xc08d, 0x21, 0 + .dw 0x6740, 0xc08d, 0x677f, 0xc08d, 0x21, 0 + .dw 0x67c0, 0xc08d, 0x67ff, 0xc08d, 0x21, 0 + .dw 0x6840, 0xc08d, 0x687f, 0xc08d, 0x21, 0 + .dw 0x68c0, 0xc08d, 0x68ff, 0xc08d, 0x21, 0 + .dw 0x6940, 0xc08d, 0x697f, 0xc08d, 0x21, 0 + .dw 0x69c0, 0xc08d, 0x69ff, 0xc08d, 0x21, 0 + .dw 0x6a40, 0xc08d, 0x6a7f, 0xc08d, 0x21, 0 + .dw 0x6ac0, 0xc08d, 0x6aff, 0xc08d, 0x21, 0 + .dw 0x6b40, 0xc08d, 0x6b7f, 0xc08d, 0x21, 0 + .dw 0x6bc0, 0xc08d, 0x6bff, 0xc08d, 0x21, 0 + .dw 0x6c40, 0xc08d, 0x6c7f, 0xc08d, 0x21, 0 + .dw 0x6cc0, 0xc08d, 0x6cff, 0xc08d, 0x21, 0 + .dw 0x6d40, 0xc08d, 0x6d7f, 0xc08d, 0x21, 0 + .dw 0x6dc0, 0xc08d, 0x6dff, 0xc08d, 0x21, 0 + .dw 0x6e40, 0xc08d, 0x6e7f, 0xc08d, 0x21, 0 + .dw 0x6ec0, 0xc08d, 0x6eff, 0xc08d, 0x21, 0 + .dw 0x6f40, 0xc08d, 0x6f7f, 0xc08d, 0x21, 0 + .dw 0x6fc0, 0xc08d, 0x6fff, 0xc08d, 0x21, 0 + .dw 0x7040, 0xc08d, 0x707f, 0xc08d, 0x21, 0 + .dw 0x70c0, 0xc08d, 0x70ff, 0xc08d, 0x21, 0 + .dw 0x7140, 0xc08d, 0x717f, 0xc08d, 0x21, 0 + .dw 0x71c0, 0xc08d, 0x71ff, 0xc08d, 0x21, 0 + .dw 0x7240, 0xc08d, 0x727f, 0xc08d, 0x21, 0 + .dw 0x72c0, 0xc08d, 0x72ff, 0xc08d, 0x21, 0 + .dw 0x7340, 0xc08d, 0x737f, 0xc08d, 0x21, 0 + .dw 0x73c0, 0xc08d, 0x73ff, 0xc08d, 0x21, 0 + .dw 0x7440, 0xc08d, 0x747f, 0xc08d, 0x21, 0 + .dw 0x74c0, 0xc08d, 0x74ff, 0xc08d, 0x21, 0 + .dw 0x7540, 0xc08d, 0x757f, 0xc08d, 0x21, 0 + .dw 0x75c0, 0xc08d, 0x75ff, 0xc08d, 0x21, 0 + .dw 0x7640, 0xc08d, 0x767f, 0xc08d, 0x21, 0 + .dw 0x76c0, 0xc08d, 0x76ff, 0xc08d, 0x21, 0 + .dw 0x7740, 0xc08d, 0x777f, 0xc08d, 0x21, 0 + .dw 0x77c0, 0xc08d, 0x77ff, 0xc08d, 0x21, 0 + .dw 0x7840, 0xc08d, 0x787f, 0xc08d, 0x21, 0 + .dw 0x78c0, 0xc08d, 0x78ff, 0xc08d, 0x21, 0 + .dw 0x7940, 0xc08d, 0x797f, 0xc08d, 0x21, 0 + .dw 0x79c0, 0xc08d, 0x7fff, 0xc08d, 0x21, 0 + .dw 0x8040, 0xc08d, 0x807f, 0xc08d, 0x21, 0 + .dw 0x80c0, 0xc08d, 0x80ff, 0xc08d, 0x21, 0 + .dw 0x8140, 0xc08d, 0x817f, 0xc08d, 0x21, 0 + .dw 0x81c0, 0xc08d, 0x81ff, 0xc08d, 0x21, 0 + .dw 0x8240, 0xc08d, 0x827f, 0xc08d, 0x21, 0 + .dw 0x82c0, 0xc08d, 0x82ff, 0xc08d, 0x21, 0 + .dw 0x8340, 0xc08d, 0x837f, 0xc08d, 0x21, 0 + .dw 0x83c0, 0xc08d, 0x83ff, 0xc08d, 0x21, 0 + .dw 0x8440, 0xc08d, 0x847f, 0xc08d, 0x21, 0 + .dw 0x84c0, 0xc08d, 0x84ff, 0xc08d, 0x21, 0 + .dw 0x8540, 0xc08d, 0x857f, 0xc08d, 0x21, 0 + .dw 0x85c0, 0xc08d, 0x85ff, 0xc08d, 0x21, 0 + .dw 0x8640, 0xc08d, 0x867f, 0xc08d, 0x21, 0 + .dw 0x86c0, 0xc08d, 0x86ff, 0xc08d, 0x21, 0 + .dw 0x8740, 0xc08d, 0x877f, 0xc08d, 0x21, 0 + .dw 0x87c0, 0xc08d, 0x87ff, 0xc08d, 0x21, 0 + .dw 0x8840, 0xc08d, 0x887f, 0xc08d, 0x21, 0 + .dw 0x88c0, 0xc08d, 0x88ff, 0xc08d, 0x21, 0 + .dw 0x8940, 0xc08d, 0x897f, 0xc08d, 0x21, 0 + .dw 0x89c0, 0xc08d, 0x89ff, 0xc08d, 0x21, 0 + .dw 0x8a40, 0xc08d, 0x8a7f, 0xc08d, 0x21, 0 + .dw 0x8ac0, 0xc08d, 0x8aff, 0xc08d, 0x21, 0 + .dw 0x8b40, 0xc08d, 0x8b7f, 0xc08d, 0x21, 0 + .dw 0x8bc0, 0xc08d, 0x8bff, 0xc08d, 0x21, 0 + .dw 0x8c40, 0xc08d, 0x8c7f, 0xc08d, 0x21, 0 + .dw 0x8cc0, 0xc08d, 0x8cff, 0xc08d, 0x21, 0 + .dw 0x8d40, 0xc08d, 0x8d7f, 0xc08d, 0x21, 0 + .dw 0x8dc0, 0xc08d, 0x8dff, 0xc08d, 0x21, 0 + .dw 0x8e40, 0xc08d, 0x8e7f, 0xc08d, 0x21, 0 + .dw 0x8ec0, 0xc08d, 0x8eff, 0xc08d, 0x21, 0 + .dw 0x8f40, 0xc08d, 0x8f7f, 0xc08d, 0x21, 0 + .dw 0x8fc0, 0xc08d, 0x8fff, 0xc08d, 0x21, 0 + .dw 0x9040, 0xc08d, 0x907f, 0xc08d, 0x21, 0 + .dw 0x90c0, 0xc08d, 0x90ff, 0xc08d, 0x21, 0 + .dw 0x9140, 0xc08d, 0x917f, 0xc08d, 0x21, 0 + .dw 0x91c0, 0xc08d, 0x91ff, 0xc08d, 0x21, 0 + .dw 0x9240, 0xc08d, 0x927f, 0xc08d, 0x21, 0 + .dw 0x92c0, 0xc08d, 0x92ff, 0xc08d, 0x21, 0 + .dw 0x9340, 0xc08d, 0x937f, 0xc08d, 0x21, 0 + .dw 0x93c0, 0xc08d, 0x93ff, 0xc08d, 0x21, 0 + .dw 0x9440, 0xc08d, 0x947f, 0xc08d, 0x21, 0 + .dw 0x94c0, 0xc08d, 0x94ff, 0xc08d, 0x21, 0 + .dw 0x9540, 0xc08d, 0x957f, 0xc08d, 0x21, 0 + .dw 0x95c0, 0xc08d, 0x95ff, 0xc08d, 0x21, 0 + .dw 0x9640, 0xc08d, 0x967f, 0xc08d, 0x21, 0 + .dw 0x96c0, 0xc08d, 0x96ff, 0xc08d, 0x21, 0 + .dw 0x9740, 0xc08d, 0x977f, 0xc08d, 0x21, 0 + .dw 0x97c0, 0xc08d, 0x97ff, 0xc08d, 0x21, 0 + .dw 0x9840, 0xc08d, 0x987f, 0xc08d, 0x21, 0 + .dw 0x98c0, 0xc08d, 0x98ff, 0xc08d, 0x21, 0 + .dw 0x9940, 0xc08d, 0x997f, 0xc08d, 0x21, 0 + .dw 0x99c0, 0xc08d, 0x9fff, 0xc08d, 0x21, 0 + .dw 0xa040, 0xc08d, 0xa07f, 0xc08d, 0x21, 0 + .dw 0xa0c0, 0xc08d, 0xa0ff, 0xc08d, 0x21, 0 + .dw 0xa140, 0xc08d, 0xa17f, 0xc08d, 0x21, 0 + .dw 0xa1c0, 0xc08d, 0xa1ff, 0xc08d, 0x21, 0 + .dw 0xa240, 0xc08d, 0xa27f, 0xc08d, 0x21, 0 + .dw 0xa2c0, 0xc08d, 0xa2ff, 0xc08d, 0x21, 0 + .dw 0xa340, 0xc08d, 0xa37f, 0xc08d, 0x21, 0 + .dw 0xa3c0, 0xc08d, 0xa3ff, 0xc08d, 0x21, 0 + .dw 0xa440, 0xc08d, 0xa47f, 0xc08d, 0x21, 0 + .dw 0xa4c0, 0xc08d, 0xa4ff, 0xc08d, 0x21, 0 + .dw 0xa540, 0xc08d, 0xa57f, 0xc08d, 0x21, 0 + .dw 0xa5c0, 0xc08d, 0xa5ff, 0xc08d, 0x21, 0 + .dw 0xa640, 0xc08d, 0xa67f, 0xc08d, 0x21, 0 + .dw 0xa6c0, 0xc08d, 0xa6ff, 0xc08d, 0x21, 0 + .dw 0xa740, 0xc08d, 0xa77f, 0xc08d, 0x21, 0 + .dw 0xa7c0, 0xc08d, 0xa7ff, 0xc08d, 0x21, 0 + .dw 0xa840, 0xc08d, 0xa87f, 0xc08d, 0x21, 0 + .dw 0xa8c0, 0xc08d, 0xa8ff, 0xc08d, 0x21, 0 + .dw 0xa940, 0xc08d, 0xa97f, 0xc08d, 0x21, 0 + .dw 0xa9c0, 0xc08d, 0xa9ff, 0xc08d, 0x21, 0 + .dw 0xaa40, 0xc08d, 0xaa7f, 0xc08d, 0x21, 0 + .dw 0xaac0, 0xc08d, 0xaaff, 0xc08d, 0x21, 0 + .dw 0xab40, 0xc08d, 0xab7f, 0xc08d, 0x21, 0 + .dw 0xabc0, 0xc08d, 0xabff, 0xc08d, 0x21, 0 + .dw 0xac40, 0xc08d, 0xac7f, 0xc08d, 0x21, 0 + .dw 0xacc0, 0xc08d, 0xacff, 0xc08d, 0x21, 0 + .dw 0xad40, 0xc08d, 0xad7f, 0xc08d, 0x21, 0 + .dw 0xadc0, 0xc08d, 0xadff, 0xc08d, 0x21, 0 + .dw 0xae40, 0xc08d, 0xae7f, 0xc08d, 0x21, 0 + .dw 0xaec0, 0xc08d, 0xaeff, 0xc08d, 0x21, 0 + .dw 0xaf40, 0xc08d, 0xaf7f, 0xc08d, 0x21, 0 + .dw 0xafc0, 0xc08d, 0xafff, 0xc08d, 0x21, 0 + .dw 0xb040, 0xc08d, 0xb07f, 0xc08d, 0x21, 0 + .dw 0xb0c0, 0xc08d, 0xb0ff, 0xc08d, 0x21, 0 + .dw 0xb140, 0xc08d, 0xb17f, 0xc08d, 0x21, 0 + .dw 0xb1c0, 0xc08d, 0xb1ff, 0xc08d, 0x21, 0 + .dw 0xb240, 0xc08d, 0xb27f, 0xc08d, 0x21, 0 + .dw 0xb2c0, 0xc08d, 0xb2ff, 0xc08d, 0x21, 0 + .dw 0xb340, 0xc08d, 0xb37f, 0xc08d, 0x21, 0 + .dw 0xb3c0, 0xc08d, 0xb3ff, 0xc08d, 0x21, 0 + .dw 0xb440, 0xc08d, 0xb47f, 0xc08d, 0x21, 0 + .dw 0xb4c0, 0xc08d, 0xb4ff, 0xc08d, 0x21, 0 + .dw 0xb540, 0xc08d, 0xb57f, 0xc08d, 0x21, 0 + .dw 0xb5c0, 0xc08d, 0xb5ff, 0xc08d, 0x21, 0 + .dw 0xb640, 0xc08d, 0xb67f, 0xc08d, 0x21, 0 + .dw 0xb6c0, 0xc08d, 0xb6ff, 0xc08d, 0x21, 0 + .dw 0xb740, 0xc08d, 0xb77f, 0xc08d, 0x21, 0 + .dw 0xb7c0, 0xc08d, 0xb7ff, 0xc08d, 0x21, 0 + .dw 0xb840, 0xc08d, 0xb87f, 0xc08d, 0x21, 0 + .dw 0xb8c0, 0xc08d, 0xb8ff, 0xc08d, 0x21, 0 + .dw 0xb940, 0xc08d, 0xb97f, 0xc08d, 0x21, 0 + .dw 0xb9c0, 0xc08d, 0xbfff, 0xc08d, 0x21, 0 + .dw 0xc040, 0xc08d, 0xc07f, 0xc08d, 0x21, 0 + .dw 0xc0c0, 0xc08d, 0xc0ff, 0xc08d, 0x21, 0 + .dw 0xc140, 0xc08d, 0xc17f, 0xc08d, 0x21, 0 + .dw 0xc1c0, 0xc08d, 0xc1ff, 0xc08d, 0x21, 0 + .dw 0xc240, 0xc08d, 0xc27f, 0xc08d, 0x21, 0 + .dw 0xc2c0, 0xc08d, 0xc2ff, 0xc08d, 0x21, 0 + .dw 0xc340, 0xc08d, 0xc37f, 0xc08d, 0x21, 0 + .dw 0xc3c0, 0xc08d, 0xc3ff, 0xc08d, 0x21, 0 + .dw 0xc440, 0xc08d, 0xc47f, 0xc08d, 0x21, 0 + .dw 0xc4c0, 0xc08d, 0xc4ff, 0xc08d, 0x21, 0 + .dw 0xc540, 0xc08d, 0xc57f, 0xc08d, 0x21, 0 + .dw 0xc5c0, 0xc08d, 0xc5ff, 0xc08d, 0x21, 0 + .dw 0xc640, 0xc08d, 0xc67f, 0xc08d, 0x21, 0 + .dw 0xc6c0, 0xc08d, 0xc6ff, 0xc08d, 0x21, 0 + .dw 0xc740, 0xc08d, 0xc77f, 0xc08d, 0x21, 0 + .dw 0xc7c0, 0xc08d, 0xc7ff, 0xc08d, 0x21, 0 + .dw 0xc840, 0xc08d, 0xc87f, 0xc08d, 0x21, 0 + .dw 0xc8c0, 0xc08d, 0xc8ff, 0xc08d, 0x21, 0 + .dw 0xc940, 0xc08d, 0xc97f, 0xc08d, 0x21, 0 + .dw 0xc9c0, 0xc08d, 0xc9ff, 0xc08d, 0x21, 0 + .dw 0xca40, 0xc08d, 0xca7f, 0xc08d, 0x21, 0 + .dw 0xcac0, 0xc08d, 0xcaff, 0xc08d, 0x21, 0 + .dw 0xcb40, 0xc08d, 0xcb7f, 0xc08d, 0x21, 0 + .dw 0xcbc0, 0xc08d, 0xcbff, 0xc08d, 0x21, 0 + .dw 0xcc40, 0xc08d, 0xcc7f, 0xc08d, 0x21, 0 + .dw 0xccc0, 0xc08d, 0xccff, 0xc08d, 0x21, 0 + .dw 0xcd40, 0xc08d, 0xcd7f, 0xc08d, 0x21, 0 + .dw 0xcdc0, 0xc08d, 0xcdff, 0xc08d, 0x21, 0 + .dw 0xce40, 0xc08d, 0xce7f, 0xc08d, 0x21, 0 + .dw 0xcec0, 0xc08d, 0xceff, 0xc08d, 0x21, 0 + .dw 0xcf40, 0xc08d, 0xcf7f, 0xc08d, 0x21, 0 + .dw 0xcfc0, 0xc08d, 0xcfff, 0xc08d, 0x21, 0 + .dw 0xd040, 0xc08d, 0xd07f, 0xc08d, 0x21, 0 + .dw 0xd0c0, 0xc08d, 0xd0ff, 0xc08d, 0x21, 0 + .dw 0xd140, 0xc08d, 0xd17f, 0xc08d, 0x21, 0 + .dw 0xd1c0, 0xc08d, 0xd1ff, 0xc08d, 0x21, 0 + .dw 0xd240, 0xc08d, 0xd27f, 0xc08d, 0x21, 0 + .dw 0xd2c0, 0xc08d, 0xd2ff, 0xc08d, 0x21, 0 + .dw 0xd340, 0xc08d, 0xd37f, 0xc08d, 0x21, 0 + .dw 0xd3c0, 0xc08d, 0xd3ff, 0xc08d, 0x21, 0 + .dw 0xd440, 0xc08d, 0xd47f, 0xc08d, 0x21, 0 + .dw 0xd4c0, 0xc08d, 0xd4ff, 0xc08d, 0x21, 0 + .dw 0xd540, 0xc08d, 0xd57f, 0xc08d, 0x21, 0 + .dw 0xd5c0, 0xc08d, 0xd5ff, 0xc08d, 0x21, 0 + .dw 0xd640, 0xc08d, 0xd67f, 0xc08d, 0x21, 0 + .dw 0xd6c0, 0xc08d, 0xd6ff, 0xc08d, 0x21, 0 + .dw 0xd740, 0xc08d, 0xd77f, 0xc08d, 0x21, 0 + .dw 0xd7c0, 0xc08d, 0xd7ff, 0xc08d, 0x21, 0 + .dw 0xd840, 0xc08d, 0xd87f, 0xc08d, 0x21, 0 + .dw 0xd8c0, 0xc08d, 0xd8ff, 0xc08d, 0x21, 0 + .dw 0xd940, 0xc08d, 0xd97f, 0xc08d, 0x21, 0 + .dw 0xd9c0, 0xc08d, 0xdfff, 0xc08d, 0x21, 0 + .dw 0xe040, 0xc08d, 0xe07f, 0xc08d, 0x21, 0 + .dw 0xe0c0, 0xc08d, 0xe0ff, 0xc08d, 0x21, 0 + .dw 0xe140, 0xc08d, 0xe17f, 0xc08d, 0x21, 0 + .dw 0xe1c0, 0xc08d, 0xe1ff, 0xc08d, 0x21, 0 + .dw 0xe240, 0xc08d, 0xe27f, 0xc08d, 0x21, 0 + .dw 0xe2c0, 0xc08d, 0xe2ff, 0xc08d, 0x21, 0 + .dw 0xe340, 0xc08d, 0xe37f, 0xc08d, 0x21, 0 + .dw 0xe3c0, 0xc08d, 0xe3ff, 0xc08d, 0x21, 0 + .dw 0xe440, 0xc08d, 0xe47f, 0xc08d, 0x21, 0 + .dw 0xe4c0, 0xc08d, 0xe4ff, 0xc08d, 0x21, 0 + .dw 0xe540, 0xc08d, 0xe57f, 0xc08d, 0x21, 0 + .dw 0xe5c0, 0xc08d, 0xe5ff, 0xc08d, 0x21, 0 + .dw 0xe640, 0xc08d, 0xe67f, 0xc08d, 0x21, 0 + .dw 0xe6c0, 0xc08d, 0xe6ff, 0xc08d, 0x21, 0 + .dw 0xe740, 0xc08d, 0xe77f, 0xc08d, 0x21, 0 + .dw 0xe7c0, 0xc08d, 0xe7ff, 0xc08d, 0x21, 0 + .dw 0xe840, 0xc08d, 0xe87f, 0xc08d, 0x21, 0 + .dw 0xe8c0, 0xc08d, 0xe8ff, 0xc08d, 0x21, 0 + .dw 0xe940, 0xc08d, 0xe97f, 0xc08d, 0x21, 0 + .dw 0xe9c0, 0xc08d, 0xe9ff, 0xc08d, 0x21, 0 + .dw 0xea40, 0xc08d, 0xea7f, 0xc08d, 0x21, 0 + .dw 0xeac0, 0xc08d, 0xeaff, 0xc08d, 0x21, 0 + .dw 0xeb40, 0xc08d, 0xeb7f, 0xc08d, 0x21, 0 + .dw 0xebc0, 0xc08d, 0xebff, 0xc08d, 0x21, 0 + .dw 0xec40, 0xc08d, 0xec7f, 0xc08d, 0x21, 0 + .dw 0xecc0, 0xc08d, 0xecff, 0xc08d, 0x21, 0 + .dw 0xed40, 0xc08d, 0xed7f, 0xc08d, 0x21, 0 + .dw 0xedc0, 0xc08d, 0xedff, 0xc08d, 0x21, 0 + .dw 0xee40, 0xc08d, 0xee7f, 0xc08d, 0x21, 0 + .dw 0xeec0, 0xc08d, 0xeeff, 0xc08d, 0x21, 0 + .dw 0xef40, 0xc08d, 0xef7f, 0xc08d, 0x21, 0 + .dw 0xefc0, 0xc08d, 0xefff, 0xc08d, 0x21, 0 + .dw 0xf040, 0xc08d, 0xf07f, 0xc08d, 0x21, 0 + .dw 0xf0c0, 0xc08d, 0xf0ff, 0xc08d, 0x21, 0 + .dw 0xf140, 0xc08d, 0xf17f, 0xc08d, 0x21, 0 + .dw 0xf1c0, 0xc08d, 0xf1ff, 0xc08d, 0x21, 0 + .dw 0xf240, 0xc08d, 0xf27f, 0xc08d, 0x21, 0 + .dw 0xf2c0, 0xc08d, 0xf2ff, 0xc08d, 0x21, 0 + .dw 0xf340, 0xc08d, 0xf37f, 0xc08d, 0x21, 0 + .dw 0xf3c0, 0xc08d, 0xf3ff, 0xc08d, 0x21, 0 + .dw 0xf440, 0xc08d, 0xf47f, 0xc08d, 0x21, 0 + .dw 0xf4c0, 0xc08d, 0xf4ff, 0xc08d, 0x21, 0 + .dw 0xf540, 0xc08d, 0xf57f, 0xc08d, 0x21, 0 + .dw 0xf5c0, 0xc08d, 0xf5ff, 0xc08d, 0x21, 0 + .dw 0xf640, 0xc08d, 0xf67f, 0xc08d, 0x21, 0 + .dw 0xf6c0, 0xc08d, 0xf6ff, 0xc08d, 0x21, 0 + .dw 0xf740, 0xc08d, 0xf77f, 0xc08d, 0x21, 0 + .dw 0xf7c0, 0xc08d, 0xf7ff, 0xc08d, 0x21, 0 + .dw 0xf840, 0xc08d, 0xf87f, 0xc08d, 0x21, 0 + .dw 0xf8c0, 0xc08d, 0xf8ff, 0xc08d, 0x21, 0 + .dw 0xf940, 0xc08d, 0xf97f, 0xc08d, 0x21, 0 + .dw 0xf9c0, 0xc08d, 0xffff, 0xc08d, 0x21, 0 + .dw 0x0040, 0xc08e, 0x007f, 0xc08e, 0x21, 0 + .dw 0x00c0, 0xc08e, 0x00ff, 0xc08e, 0x21, 0 + .dw 0x0140, 0xc08e, 0x017f, 0xc08e, 0x21, 0 + .dw 0x01c0, 0xc08e, 0x01ff, 0xc08e, 0x21, 0 + .dw 0x0240, 0xc08e, 0x027f, 0xc08e, 0x21, 0 + .dw 0x02c0, 0xc08e, 0x02ff, 0xc08e, 0x21, 0 + .dw 0x0340, 0xc08e, 0x037f, 0xc08e, 0x21, 0 + .dw 0x03c0, 0xc08e, 0x03ff, 0xc08e, 0x21, 0 + .dw 0x0440, 0xc08e, 0x047f, 0xc08e, 0x21, 0 + .dw 0x04c0, 0xc08e, 0x04ff, 0xc08e, 0x21, 0 + .dw 0x0540, 0xc08e, 0x057f, 0xc08e, 0x21, 0 + .dw 0x05c0, 0xc08e, 0x05ff, 0xc08e, 0x21, 0 + .dw 0x0640, 0xc08e, 0x067f, 0xc08e, 0x21, 0 + .dw 0x06c0, 0xc08e, 0x06ff, 0xc08e, 0x21, 0 + .dw 0x0740, 0xc08e, 0x077f, 0xc08e, 0x21, 0 + .dw 0x07c0, 0xc08e, 0x07ff, 0xc08e, 0x21, 0 + .dw 0x0840, 0xc08e, 0x087f, 0xc08e, 0x21, 0 + .dw 0x08c0, 0xc08e, 0x08ff, 0xc08e, 0x21, 0 + .dw 0x0940, 0xc08e, 0x097f, 0xc08e, 0x21, 0 + .dw 0x09c0, 0xc08e, 0x09ff, 0xc08e, 0x21, 0 + .dw 0x0a40, 0xc08e, 0x0a7f, 0xc08e, 0x21, 0 + .dw 0x0ac0, 0xc08e, 0x0aff, 0xc08e, 0x21, 0 + .dw 0x0b40, 0xc08e, 0x0b7f, 0xc08e, 0x21, 0 + .dw 0x0bc0, 0xc08e, 0x0bff, 0xc08e, 0x21, 0 + .dw 0x0c40, 0xc08e, 0x0c7f, 0xc08e, 0x21, 0 + .dw 0x0cc0, 0xc08e, 0x0cff, 0xc08e, 0x21, 0 + .dw 0x0d40, 0xc08e, 0x0d7f, 0xc08e, 0x21, 0 + .dw 0x0dc0, 0xc08e, 0x0dff, 0xc08e, 0x21, 0 + .dw 0x0e40, 0xc08e, 0x0e7f, 0xc08e, 0x21, 0 + .dw 0x0ec0, 0xc08e, 0x0eff, 0xc08e, 0x21, 0 + .dw 0x0f40, 0xc08e, 0x0f7f, 0xc08e, 0x21, 0 + .dw 0x0fc0, 0xc08e, 0x0fff, 0xc08e, 0x21, 0 + .dw 0x1040, 0xc08e, 0x107f, 0xc08e, 0x21, 0 + .dw 0x10c0, 0xc08e, 0x10ff, 0xc08e, 0x21, 0 + .dw 0x1140, 0xc08e, 0x117f, 0xc08e, 0x21, 0 + .dw 0x11c0, 0xc08e, 0x11ff, 0xc08e, 0x21, 0 + .dw 0x1240, 0xc08e, 0x127f, 0xc08e, 0x21, 0 + .dw 0x12c0, 0xc08e, 0x12ff, 0xc08e, 0x21, 0 + .dw 0x1340, 0xc08e, 0x137f, 0xc08e, 0x21, 0 + .dw 0x13c0, 0xc08e, 0x13ff, 0xc08e, 0x21, 0 + .dw 0x1440, 0xc08e, 0x147f, 0xc08e, 0x21, 0 + .dw 0x14c0, 0xc08e, 0x14ff, 0xc08e, 0x21, 0 + .dw 0x1540, 0xc08e, 0x157f, 0xc08e, 0x21, 0 + .dw 0x15c0, 0xc08e, 0x15ff, 0xc08e, 0x21, 0 + .dw 0x1640, 0xc08e, 0x167f, 0xc08e, 0x21, 0 + .dw 0x16c0, 0xc08e, 0x16ff, 0xc08e, 0x21, 0 + .dw 0x1740, 0xc08e, 0x177f, 0xc08e, 0x21, 0 + .dw 0x17c0, 0xc08e, 0x17ff, 0xc08e, 0x21, 0 + .dw 0x1840, 0xc08e, 0x187f, 0xc08e, 0x21, 0 + .dw 0x18c0, 0xc08e, 0x18ff, 0xc08e, 0x21, 0 + .dw 0x1940, 0xc08e, 0x197f, 0xc08e, 0x21, 0 + .dw 0x19c0, 0xc08e, 0x1fff, 0xc08e, 0x21, 0 + .dw 0x2040, 0xc08e, 0x207f, 0xc08e, 0x21, 0 + .dw 0x20c0, 0xc08e, 0x20ff, 0xc08e, 0x21, 0 + .dw 0x2140, 0xc08e, 0x217f, 0xc08e, 0x21, 0 + .dw 0x21c0, 0xc08e, 0x21ff, 0xc08e, 0x21, 0 + .dw 0x2240, 0xc08e, 0x227f, 0xc08e, 0x21, 0 + .dw 0x22c0, 0xc08e, 0x22ff, 0xc08e, 0x21, 0 + .dw 0x2340, 0xc08e, 0x237f, 0xc08e, 0x21, 0 + .dw 0x23c0, 0xc08e, 0x23ff, 0xc08e, 0x21, 0 + .dw 0x2440, 0xc08e, 0x247f, 0xc08e, 0x21, 0 + .dw 0x24c0, 0xc08e, 0x24ff, 0xc08e, 0x21, 0 + .dw 0x2540, 0xc08e, 0x257f, 0xc08e, 0x21, 0 + .dw 0x25c0, 0xc08e, 0x25ff, 0xc08e, 0x21, 0 + .dw 0x2640, 0xc08e, 0x267f, 0xc08e, 0x21, 0 + .dw 0x26c0, 0xc08e, 0x26ff, 0xc08e, 0x21, 0 + .dw 0x2740, 0xc08e, 0x277f, 0xc08e, 0x21, 0 + .dw 0x27c0, 0xc08e, 0x27ff, 0xc08e, 0x21, 0 + .dw 0x2840, 0xc08e, 0x287f, 0xc08e, 0x21, 0 + .dw 0x28c0, 0xc08e, 0x28ff, 0xc08e, 0x21, 0 + .dw 0x2940, 0xc08e, 0x297f, 0xc08e, 0x21, 0 + .dw 0x29c0, 0xc08e, 0x29ff, 0xc08e, 0x21, 0 + .dw 0x2a40, 0xc08e, 0x2a7f, 0xc08e, 0x21, 0 + .dw 0x2ac0, 0xc08e, 0x2aff, 0xc08e, 0x21, 0 + .dw 0x2b40, 0xc08e, 0x2b7f, 0xc08e, 0x21, 0 + .dw 0x2bc0, 0xc08e, 0x2bff, 0xc08e, 0x21, 0 + .dw 0x2c40, 0xc08e, 0x2c7f, 0xc08e, 0x21, 0 + .dw 0x2cc0, 0xc08e, 0x2cff, 0xc08e, 0x21, 0 + .dw 0x2d40, 0xc08e, 0x2d7f, 0xc08e, 0x21, 0 + .dw 0x2dc0, 0xc08e, 0x2dff, 0xc08e, 0x21, 0 + .dw 0x2e40, 0xc08e, 0x2e7f, 0xc08e, 0x21, 0 + .dw 0x2ec0, 0xc08e, 0x2eff, 0xc08e, 0x21, 0 + .dw 0x2f40, 0xc08e, 0x2f7f, 0xc08e, 0x21, 0 + .dw 0x2fc0, 0xc08e, 0x2fff, 0xc08e, 0x21, 0 + .dw 0x3040, 0xc08e, 0x307f, 0xc08e, 0x21, 0 + .dw 0x30c0, 0xc08e, 0x30ff, 0xc08e, 0x21, 0 + .dw 0x3140, 0xc08e, 0x317f, 0xc08e, 0x21, 0 + .dw 0x31c0, 0xc08e, 0x31ff, 0xc08e, 0x21, 0 + .dw 0x3240, 0xc08e, 0x327f, 0xc08e, 0x21, 0 + .dw 0x32c0, 0xc08e, 0x32ff, 0xc08e, 0x21, 0 + .dw 0x3340, 0xc08e, 0x337f, 0xc08e, 0x21, 0 + .dw 0x33c0, 0xc08e, 0x33ff, 0xc08e, 0x21, 0 + .dw 0x3440, 0xc08e, 0x347f, 0xc08e, 0x21, 0 + .dw 0x34c0, 0xc08e, 0x34ff, 0xc08e, 0x21, 0 + .dw 0x3540, 0xc08e, 0x357f, 0xc08e, 0x21, 0 + .dw 0x35c0, 0xc08e, 0x35ff, 0xc08e, 0x21, 0 + .dw 0x3640, 0xc08e, 0x367f, 0xc08e, 0x21, 0 + .dw 0x36c0, 0xc08e, 0x36ff, 0xc08e, 0x21, 0 + .dw 0x3740, 0xc08e, 0x377f, 0xc08e, 0x21, 0 + .dw 0x37c0, 0xc08e, 0x37ff, 0xc08e, 0x21, 0 + .dw 0x3840, 0xc08e, 0x387f, 0xc08e, 0x21, 0 + .dw 0x38c0, 0xc08e, 0x38ff, 0xc08e, 0x21, 0 + .dw 0x3940, 0xc08e, 0x397f, 0xc08e, 0x21, 0 + .dw 0x39c0, 0xc08e, 0x3fff, 0xc08e, 0x21, 0 + .dw 0x4040, 0xc08e, 0x407f, 0xc08e, 0x21, 0 + .dw 0x40c0, 0xc08e, 0x40ff, 0xc08e, 0x21, 0 + .dw 0x4140, 0xc08e, 0x417f, 0xc08e, 0x21, 0 + .dw 0x41c0, 0xc08e, 0x41ff, 0xc08e, 0x21, 0 + .dw 0x4240, 0xc08e, 0x427f, 0xc08e, 0x21, 0 + .dw 0x42c0, 0xc08e, 0x42ff, 0xc08e, 0x21, 0 + .dw 0x4340, 0xc08e, 0x437f, 0xc08e, 0x21, 0 + .dw 0x43c0, 0xc08e, 0x43ff, 0xc08e, 0x21, 0 + .dw 0x4440, 0xc08e, 0x447f, 0xc08e, 0x21, 0 + .dw 0x44c0, 0xc08e, 0x44ff, 0xc08e, 0x21, 0 + .dw 0x4540, 0xc08e, 0x457f, 0xc08e, 0x21, 0 + .dw 0x45c0, 0xc08e, 0x45ff, 0xc08e, 0x21, 0 + .dw 0x4640, 0xc08e, 0x467f, 0xc08e, 0x21, 0 + .dw 0x46c0, 0xc08e, 0x46ff, 0xc08e, 0x21, 0 + .dw 0x4740, 0xc08e, 0x477f, 0xc08e, 0x21, 0 + .dw 0x47c0, 0xc08e, 0x47ff, 0xc08e, 0x21, 0 + .dw 0x4840, 0xc08e, 0x487f, 0xc08e, 0x21, 0 + .dw 0x48c0, 0xc08e, 0x48ff, 0xc08e, 0x21, 0 + .dw 0x4940, 0xc08e, 0x497f, 0xc08e, 0x21, 0 + .dw 0x49c0, 0xc08e, 0x49ff, 0xc08e, 0x21, 0 + .dw 0x4a40, 0xc08e, 0x4a7f, 0xc08e, 0x21, 0 + .dw 0x4ac0, 0xc08e, 0x4aff, 0xc08e, 0x21, 0 + .dw 0x4b40, 0xc08e, 0x4b7f, 0xc08e, 0x21, 0 + .dw 0x4bc0, 0xc08e, 0x4bff, 0xc08e, 0x21, 0 + .dw 0x4c40, 0xc08e, 0x4c7f, 0xc08e, 0x21, 0 + .dw 0x4cc0, 0xc08e, 0x4cff, 0xc08e, 0x21, 0 + .dw 0x4d40, 0xc08e, 0x4d7f, 0xc08e, 0x21, 0 + .dw 0x4dc0, 0xc08e, 0x4dff, 0xc08e, 0x21, 0 + .dw 0x4e40, 0xc08e, 0x4e7f, 0xc08e, 0x21, 0 + .dw 0x4ec0, 0xc08e, 0x4eff, 0xc08e, 0x21, 0 + .dw 0x4f40, 0xc08e, 0x4f7f, 0xc08e, 0x21, 0 + .dw 0x4fc0, 0xc08e, 0x4fff, 0xc08e, 0x21, 0 + .dw 0x5040, 0xc08e, 0x507f, 0xc08e, 0x21, 0 + .dw 0x50c0, 0xc08e, 0x50ff, 0xc08e, 0x21, 0 + .dw 0x5140, 0xc08e, 0x517f, 0xc08e, 0x21, 0 + .dw 0x51c0, 0xc08e, 0x51ff, 0xc08e, 0x21, 0 + .dw 0x5240, 0xc08e, 0x527f, 0xc08e, 0x21, 0 + .dw 0x52c0, 0xc08e, 0x52ff, 0xc08e, 0x21, 0 + .dw 0x5340, 0xc08e, 0x537f, 0xc08e, 0x21, 0 + .dw 0x53c0, 0xc08e, 0x53ff, 0xc08e, 0x21, 0 + .dw 0x5440, 0xc08e, 0x547f, 0xc08e, 0x21, 0 + .dw 0x54c0, 0xc08e, 0x54ff, 0xc08e, 0x21, 0 + .dw 0x5540, 0xc08e, 0x557f, 0xc08e, 0x21, 0 + .dw 0x55c0, 0xc08e, 0x55ff, 0xc08e, 0x21, 0 + .dw 0x5640, 0xc08e, 0x567f, 0xc08e, 0x21, 0 + .dw 0x56c0, 0xc08e, 0x56ff, 0xc08e, 0x21, 0 + .dw 0x5740, 0xc08e, 0x577f, 0xc08e, 0x21, 0 + .dw 0x57c0, 0xc08e, 0x57ff, 0xc08e, 0x21, 0 + .dw 0x5840, 0xc08e, 0x587f, 0xc08e, 0x21, 0 + .dw 0x58c0, 0xc08e, 0x58ff, 0xc08e, 0x21, 0 + .dw 0x5940, 0xc08e, 0x597f, 0xc08e, 0x21, 0 + .dw 0x59c0, 0xc08e, 0x5fff, 0xc08e, 0x21, 0 + .dw 0x6040, 0xc08e, 0x607f, 0xc08e, 0x21, 0 + .dw 0x60c0, 0xc08e, 0x60ff, 0xc08e, 0x21, 0 + .dw 0x6140, 0xc08e, 0x617f, 0xc08e, 0x21, 0 + .dw 0x61c0, 0xc08e, 0x61ff, 0xc08e, 0x21, 0 + .dw 0x6240, 0xc08e, 0x627f, 0xc08e, 0x21, 0 + .dw 0x62c0, 0xc08e, 0x62ff, 0xc08e, 0x21, 0 + .dw 0x6340, 0xc08e, 0x637f, 0xc08e, 0x21, 0 + .dw 0x63c0, 0xc08e, 0x63ff, 0xc08e, 0x21, 0 + .dw 0x6440, 0xc08e, 0x647f, 0xc08e, 0x21, 0 + .dw 0x64c0, 0xc08e, 0x64ff, 0xc08e, 0x21, 0 + .dw 0x6540, 0xc08e, 0x657f, 0xc08e, 0x21, 0 + .dw 0x65c0, 0xc08e, 0x65ff, 0xc08e, 0x21, 0 + .dw 0x6640, 0xc08e, 0x667f, 0xc08e, 0x21, 0 + .dw 0x66c0, 0xc08e, 0x66ff, 0xc08e, 0x21, 0 + .dw 0x6740, 0xc08e, 0x677f, 0xc08e, 0x21, 0 + .dw 0x67c0, 0xc08e, 0x67ff, 0xc08e, 0x21, 0 + .dw 0x6840, 0xc08e, 0x687f, 0xc08e, 0x21, 0 + .dw 0x68c0, 0xc08e, 0x68ff, 0xc08e, 0x21, 0 + .dw 0x6940, 0xc08e, 0x697f, 0xc08e, 0x21, 0 + .dw 0x69c0, 0xc08e, 0x69ff, 0xc08e, 0x21, 0 + .dw 0x6a40, 0xc08e, 0x6a7f, 0xc08e, 0x21, 0 + .dw 0x6ac0, 0xc08e, 0x6aff, 0xc08e, 0x21, 0 + .dw 0x6b40, 0xc08e, 0x6b7f, 0xc08e, 0x21, 0 + .dw 0x6bc0, 0xc08e, 0x6bff, 0xc08e, 0x21, 0 + .dw 0x6c40, 0xc08e, 0x6c7f, 0xc08e, 0x21, 0 + .dw 0x6cc0, 0xc08e, 0x6cff, 0xc08e, 0x21, 0 + .dw 0x6d40, 0xc08e, 0x6d7f, 0xc08e, 0x21, 0 + .dw 0x6dc0, 0xc08e, 0x6dff, 0xc08e, 0x21, 0 + .dw 0x6e40, 0xc08e, 0x6e7f, 0xc08e, 0x21, 0 + .dw 0x6ec0, 0xc08e, 0x6eff, 0xc08e, 0x21, 0 + .dw 0x6f40, 0xc08e, 0x6f7f, 0xc08e, 0x21, 0 + .dw 0x6fc0, 0xc08e, 0x6fff, 0xc08e, 0x21, 0 + .dw 0x7040, 0xc08e, 0x707f, 0xc08e, 0x21, 0 + .dw 0x70c0, 0xc08e, 0x70ff, 0xc08e, 0x21, 0 + .dw 0x7140, 0xc08e, 0x717f, 0xc08e, 0x21, 0 + .dw 0x71c0, 0xc08e, 0x71ff, 0xc08e, 0x21, 0 + .dw 0x7240, 0xc08e, 0x727f, 0xc08e, 0x21, 0 + .dw 0x72c0, 0xc08e, 0x72ff, 0xc08e, 0x21, 0 + .dw 0x7340, 0xc08e, 0x737f, 0xc08e, 0x21, 0 + .dw 0x73c0, 0xc08e, 0x73ff, 0xc08e, 0x21, 0 + .dw 0x7440, 0xc08e, 0x747f, 0xc08e, 0x21, 0 + .dw 0x74c0, 0xc08e, 0x74ff, 0xc08e, 0x21, 0 + .dw 0x7540, 0xc08e, 0x757f, 0xc08e, 0x21, 0 + .dw 0x75c0, 0xc08e, 0x75ff, 0xc08e, 0x21, 0 + .dw 0x7640, 0xc08e, 0x767f, 0xc08e, 0x21, 0 + .dw 0x76c0, 0xc08e, 0x76ff, 0xc08e, 0x21, 0 + .dw 0x7740, 0xc08e, 0x777f, 0xc08e, 0x21, 0 + .dw 0x77c0, 0xc08e, 0x77ff, 0xc08e, 0x21, 0 + .dw 0x7840, 0xc08e, 0x787f, 0xc08e, 0x21, 0 + .dw 0x78c0, 0xc08e, 0x78ff, 0xc08e, 0x21, 0 + .dw 0x7940, 0xc08e, 0x797f, 0xc08e, 0x21, 0 + .dw 0x79c0, 0xc08e, 0x7fff, 0xc08e, 0x21, 0 + .dw 0x8040, 0xc08e, 0x807f, 0xc08e, 0x21, 0 + .dw 0x80c0, 0xc08e, 0x80ff, 0xc08e, 0x21, 0 + .dw 0x8140, 0xc08e, 0x817f, 0xc08e, 0x21, 0 + .dw 0x81c0, 0xc08e, 0x81ff, 0xc08e, 0x21, 0 + .dw 0x8240, 0xc08e, 0x827f, 0xc08e, 0x21, 0 + .dw 0x82c0, 0xc08e, 0x82ff, 0xc08e, 0x21, 0 + .dw 0x8340, 0xc08e, 0x837f, 0xc08e, 0x21, 0 + .dw 0x83c0, 0xc08e, 0x83ff, 0xc08e, 0x21, 0 + .dw 0x8440, 0xc08e, 0x847f, 0xc08e, 0x21, 0 + .dw 0x84c0, 0xc08e, 0x84ff, 0xc08e, 0x21, 0 + .dw 0x8540, 0xc08e, 0x857f, 0xc08e, 0x21, 0 + .dw 0x85c0, 0xc08e, 0x85ff, 0xc08e, 0x21, 0 + .dw 0x8640, 0xc08e, 0x867f, 0xc08e, 0x21, 0 + .dw 0x86c0, 0xc08e, 0x86ff, 0xc08e, 0x21, 0 + .dw 0x8740, 0xc08e, 0x877f, 0xc08e, 0x21, 0 + .dw 0x87c0, 0xc08e, 0x87ff, 0xc08e, 0x21, 0 + .dw 0x8840, 0xc08e, 0x887f, 0xc08e, 0x21, 0 + .dw 0x88c0, 0xc08e, 0x88ff, 0xc08e, 0x21, 0 + .dw 0x8940, 0xc08e, 0x897f, 0xc08e, 0x21, 0 + .dw 0x89c0, 0xc08e, 0x89ff, 0xc08e, 0x21, 0 + .dw 0x8a40, 0xc08e, 0x8a7f, 0xc08e, 0x21, 0 + .dw 0x8ac0, 0xc08e, 0x8aff, 0xc08e, 0x21, 0 + .dw 0x8b40, 0xc08e, 0x8b7f, 0xc08e, 0x21, 0 + .dw 0x8bc0, 0xc08e, 0x8bff, 0xc08e, 0x21, 0 + .dw 0x8c40, 0xc08e, 0x8c7f, 0xc08e, 0x21, 0 + .dw 0x8cc0, 0xc08e, 0x8cff, 0xc08e, 0x21, 0 + .dw 0x8d40, 0xc08e, 0x8d7f, 0xc08e, 0x21, 0 + .dw 0x8dc0, 0xc08e, 0x8dff, 0xc08e, 0x21, 0 + .dw 0x8e40, 0xc08e, 0x8e7f, 0xc08e, 0x21, 0 + .dw 0x8ec0, 0xc08e, 0x8eff, 0xc08e, 0x21, 0 + .dw 0x8f40, 0xc08e, 0x8f7f, 0xc08e, 0x21, 0 + .dw 0x8fc0, 0xc08e, 0x8fff, 0xc08e, 0x21, 0 + .dw 0x9040, 0xc08e, 0x907f, 0xc08e, 0x21, 0 + .dw 0x90c0, 0xc08e, 0x90ff, 0xc08e, 0x21, 0 + .dw 0x9140, 0xc08e, 0x917f, 0xc08e, 0x21, 0 + .dw 0x91c0, 0xc08e, 0x91ff, 0xc08e, 0x21, 0 + .dw 0x9240, 0xc08e, 0x927f, 0xc08e, 0x21, 0 + .dw 0x92c0, 0xc08e, 0x92ff, 0xc08e, 0x21, 0 + .dw 0x9340, 0xc08e, 0x937f, 0xc08e, 0x21, 0 + .dw 0x93c0, 0xc08e, 0x93ff, 0xc08e, 0x21, 0 + .dw 0x9440, 0xc08e, 0x947f, 0xc08e, 0x21, 0 + .dw 0x94c0, 0xc08e, 0x94ff, 0xc08e, 0x21, 0 + .dw 0x9540, 0xc08e, 0x957f, 0xc08e, 0x21, 0 + .dw 0x95c0, 0xc08e, 0x95ff, 0xc08e, 0x21, 0 + .dw 0x9640, 0xc08e, 0x967f, 0xc08e, 0x21, 0 + .dw 0x96c0, 0xc08e, 0x96ff, 0xc08e, 0x21, 0 + .dw 0x9740, 0xc08e, 0x977f, 0xc08e, 0x21, 0 + .dw 0x97c0, 0xc08e, 0x97ff, 0xc08e, 0x21, 0 + .dw 0x9840, 0xc08e, 0x987f, 0xc08e, 0x21, 0 + .dw 0x98c0, 0xc08e, 0x98ff, 0xc08e, 0x21, 0 + .dw 0x9940, 0xc08e, 0x997f, 0xc08e, 0x21, 0 + .dw 0x99c0, 0xc08e, 0x9fff, 0xc08e, 0x21, 0 + .dw 0xa040, 0xc08e, 0xa07f, 0xc08e, 0x21, 0 + .dw 0xa0c0, 0xc08e, 0xa0ff, 0xc08e, 0x21, 0 + .dw 0xa140, 0xc08e, 0xa17f, 0xc08e, 0x21, 0 + .dw 0xa1c0, 0xc08e, 0xa1ff, 0xc08e, 0x21, 0 + .dw 0xa240, 0xc08e, 0xa27f, 0xc08e, 0x21, 0 + .dw 0xa2c0, 0xc08e, 0xa2ff, 0xc08e, 0x21, 0 + .dw 0xa340, 0xc08e, 0xa37f, 0xc08e, 0x21, 0 + .dw 0xa3c0, 0xc08e, 0xa3ff, 0xc08e, 0x21, 0 + .dw 0xa440, 0xc08e, 0xa47f, 0xc08e, 0x21, 0 + .dw 0xa4c0, 0xc08e, 0xa4ff, 0xc08e, 0x21, 0 + .dw 0xa540, 0xc08e, 0xa57f, 0xc08e, 0x21, 0 + .dw 0xa5c0, 0xc08e, 0xa5ff, 0xc08e, 0x21, 0 + .dw 0xa640, 0xc08e, 0xa67f, 0xc08e, 0x21, 0 + .dw 0xa6c0, 0xc08e, 0xa6ff, 0xc08e, 0x21, 0 + .dw 0xa740, 0xc08e, 0xa77f, 0xc08e, 0x21, 0 + .dw 0xa7c0, 0xc08e, 0xa7ff, 0xc08e, 0x21, 0 + .dw 0xa840, 0xc08e, 0xa87f, 0xc08e, 0x21, 0 + .dw 0xa8c0, 0xc08e, 0xa8ff, 0xc08e, 0x21, 0 + .dw 0xa940, 0xc08e, 0xa97f, 0xc08e, 0x21, 0 + .dw 0xa9c0, 0xc08e, 0xa9ff, 0xc08e, 0x21, 0 + .dw 0xaa40, 0xc08e, 0xaa7f, 0xc08e, 0x21, 0 + .dw 0xaac0, 0xc08e, 0xaaff, 0xc08e, 0x21, 0 + .dw 0xab40, 0xc08e, 0xab7f, 0xc08e, 0x21, 0 + .dw 0xabc0, 0xc08e, 0xabff, 0xc08e, 0x21, 0 + .dw 0xac40, 0xc08e, 0xac7f, 0xc08e, 0x21, 0 + .dw 0xacc0, 0xc08e, 0xacff, 0xc08e, 0x21, 0 + .dw 0xad40, 0xc08e, 0xad7f, 0xc08e, 0x21, 0 + .dw 0xadc0, 0xc08e, 0xadff, 0xc08e, 0x21, 0 + .dw 0xae40, 0xc08e, 0xae7f, 0xc08e, 0x21, 0 + .dw 0xaec0, 0xc08e, 0xaeff, 0xc08e, 0x21, 0 + .dw 0xaf40, 0xc08e, 0xaf7f, 0xc08e, 0x21, 0 + .dw 0xafc0, 0xc08e, 0xafff, 0xc08e, 0x21, 0 + .dw 0xb040, 0xc08e, 0xb07f, 0xc08e, 0x21, 0 + .dw 0xb0c0, 0xc08e, 0xb0ff, 0xc08e, 0x21, 0 + .dw 0xb140, 0xc08e, 0xb17f, 0xc08e, 0x21, 0 + .dw 0xb1c0, 0xc08e, 0xb1ff, 0xc08e, 0x21, 0 + .dw 0xb240, 0xc08e, 0xb27f, 0xc08e, 0x21, 0 + .dw 0xb2c0, 0xc08e, 0xb2ff, 0xc08e, 0x21, 0 + .dw 0xb340, 0xc08e, 0xb37f, 0xc08e, 0x21, 0 + .dw 0xb3c0, 0xc08e, 0xb3ff, 0xc08e, 0x21, 0 + .dw 0xb440, 0xc08e, 0xb47f, 0xc08e, 0x21, 0 + .dw 0xb4c0, 0xc08e, 0xb4ff, 0xc08e, 0x21, 0 + .dw 0xb540, 0xc08e, 0xb57f, 0xc08e, 0x21, 0 + .dw 0xb5c0, 0xc08e, 0xb5ff, 0xc08e, 0x21, 0 + .dw 0xb640, 0xc08e, 0xb67f, 0xc08e, 0x21, 0 + .dw 0xb6c0, 0xc08e, 0xb6ff, 0xc08e, 0x21, 0 + .dw 0xb740, 0xc08e, 0xb77f, 0xc08e, 0x21, 0 + .dw 0xb7c0, 0xc08e, 0xb7ff, 0xc08e, 0x21, 0 + .dw 0xb840, 0xc08e, 0xb87f, 0xc08e, 0x21, 0 + .dw 0xb8c0, 0xc08e, 0xb8ff, 0xc08e, 0x21, 0 + .dw 0xb940, 0xc08e, 0xb97f, 0xc08e, 0x21, 0 + .dw 0xb9c0, 0xc08e, 0xbfff, 0xc08e, 0x21, 0 + .dw 0xc040, 0xc08e, 0xc07f, 0xc08e, 0x21, 0 + .dw 0xc0c0, 0xc08e, 0xc0ff, 0xc08e, 0x21, 0 + .dw 0xc140, 0xc08e, 0xc17f, 0xc08e, 0x21, 0 + .dw 0xc1c0, 0xc08e, 0xc1ff, 0xc08e, 0x21, 0 + .dw 0xc240, 0xc08e, 0xc27f, 0xc08e, 0x21, 0 + .dw 0xc2c0, 0xc08e, 0xc2ff, 0xc08e, 0x21, 0 + .dw 0xc340, 0xc08e, 0xc37f, 0xc08e, 0x21, 0 + .dw 0xc3c0, 0xc08e, 0xc3ff, 0xc08e, 0x21, 0 + .dw 0xc440, 0xc08e, 0xc47f, 0xc08e, 0x21, 0 + .dw 0xc4c0, 0xc08e, 0xc4ff, 0xc08e, 0x21, 0 + .dw 0xc540, 0xc08e, 0xc57f, 0xc08e, 0x21, 0 + .dw 0xc5c0, 0xc08e, 0xc5ff, 0xc08e, 0x21, 0 + .dw 0xc640, 0xc08e, 0xc67f, 0xc08e, 0x21, 0 + .dw 0xc6c0, 0xc08e, 0xc6ff, 0xc08e, 0x21, 0 + .dw 0xc740, 0xc08e, 0xc77f, 0xc08e, 0x21, 0 + .dw 0xc7c0, 0xc08e, 0xc7ff, 0xc08e, 0x21, 0 + .dw 0xc840, 0xc08e, 0xc87f, 0xc08e, 0x21, 0 + .dw 0xc8c0, 0xc08e, 0xc8ff, 0xc08e, 0x21, 0 + .dw 0xc940, 0xc08e, 0xc97f, 0xc08e, 0x21, 0 + .dw 0xc9c0, 0xc08e, 0xc9ff, 0xc08e, 0x21, 0 + .dw 0xca40, 0xc08e, 0xca7f, 0xc08e, 0x21, 0 + .dw 0xcac0, 0xc08e, 0xcaff, 0xc08e, 0x21, 0 + .dw 0xcb40, 0xc08e, 0xcb7f, 0xc08e, 0x21, 0 + .dw 0xcbc0, 0xc08e, 0xcbff, 0xc08e, 0x21, 0 + .dw 0xcc40, 0xc08e, 0xcc7f, 0xc08e, 0x21, 0 + .dw 0xccc0, 0xc08e, 0xccff, 0xc08e, 0x21, 0 + .dw 0xcd40, 0xc08e, 0xcd7f, 0xc08e, 0x21, 0 + .dw 0xcdc0, 0xc08e, 0xcdff, 0xc08e, 0x21, 0 + .dw 0xce40, 0xc08e, 0xce7f, 0xc08e, 0x21, 0 + .dw 0xcec0, 0xc08e, 0xceff, 0xc08e, 0x21, 0 + .dw 0xcf40, 0xc08e, 0xcf7f, 0xc08e, 0x21, 0 + .dw 0xcfc0, 0xc08e, 0xcfff, 0xc08e, 0x21, 0 + .dw 0xd040, 0xc08e, 0xd07f, 0xc08e, 0x21, 0 + .dw 0xd0c0, 0xc08e, 0xd0ff, 0xc08e, 0x21, 0 + .dw 0xd140, 0xc08e, 0xd17f, 0xc08e, 0x21, 0 + .dw 0xd1c0, 0xc08e, 0xd1ff, 0xc08e, 0x21, 0 + .dw 0xd240, 0xc08e, 0xd27f, 0xc08e, 0x21, 0 + .dw 0xd2c0, 0xc08e, 0xd2ff, 0xc08e, 0x21, 0 + .dw 0xd340, 0xc08e, 0xd37f, 0xc08e, 0x21, 0 + .dw 0xd3c0, 0xc08e, 0xd3ff, 0xc08e, 0x21, 0 + .dw 0xd440, 0xc08e, 0xd47f, 0xc08e, 0x21, 0 + .dw 0xd4c0, 0xc08e, 0xd4ff, 0xc08e, 0x21, 0 + .dw 0xd540, 0xc08e, 0xd57f, 0xc08e, 0x21, 0 + .dw 0xd5c0, 0xc08e, 0xd5ff, 0xc08e, 0x21, 0 + .dw 0xd640, 0xc08e, 0xd67f, 0xc08e, 0x21, 0 + .dw 0xd6c0, 0xc08e, 0xd6ff, 0xc08e, 0x21, 0 + .dw 0xd740, 0xc08e, 0xd77f, 0xc08e, 0x21, 0 + .dw 0xd7c0, 0xc08e, 0xd7ff, 0xc08e, 0x21, 0 + .dw 0xd840, 0xc08e, 0xd87f, 0xc08e, 0x21, 0 + .dw 0xd8c0, 0xc08e, 0xd8ff, 0xc08e, 0x21, 0 + .dw 0xd940, 0xc08e, 0xd97f, 0xc08e, 0x21, 0 + .dw 0xd9c0, 0xc08e, 0xdfff, 0xc08e, 0x21, 0 + .dw 0xe040, 0xc08e, 0xe07f, 0xc08e, 0x21, 0 + .dw 0xe0c0, 0xc08e, 0xe0ff, 0xc08e, 0x21, 0 + .dw 0xe140, 0xc08e, 0xe17f, 0xc08e, 0x21, 0 + .dw 0xe1c0, 0xc08e, 0xe1ff, 0xc08e, 0x21, 0 + .dw 0xe240, 0xc08e, 0xe27f, 0xc08e, 0x21, 0 + .dw 0xe2c0, 0xc08e, 0xe2ff, 0xc08e, 0x21, 0 + .dw 0xe340, 0xc08e, 0xe37f, 0xc08e, 0x21, 0 + .dw 0xe3c0, 0xc08e, 0xe3ff, 0xc08e, 0x21, 0 + .dw 0xe440, 0xc08e, 0xe47f, 0xc08e, 0x21, 0 + .dw 0xe4c0, 0xc08e, 0xe4ff, 0xc08e, 0x21, 0 + .dw 0xe540, 0xc08e, 0xe57f, 0xc08e, 0x21, 0 + .dw 0xe5c0, 0xc08e, 0xe5ff, 0xc08e, 0x21, 0 + .dw 0xe640, 0xc08e, 0xe67f, 0xc08e, 0x21, 0 + .dw 0xe6c0, 0xc08e, 0xe6ff, 0xc08e, 0x21, 0 + .dw 0xe740, 0xc08e, 0xe77f, 0xc08e, 0x21, 0 + .dw 0xe7c0, 0xc08e, 0xe7ff, 0xc08e, 0x21, 0 + .dw 0xe840, 0xc08e, 0xe87f, 0xc08e, 0x21, 0 + .dw 0xe8c0, 0xc08e, 0xe8ff, 0xc08e, 0x21, 0 + .dw 0xe940, 0xc08e, 0xe97f, 0xc08e, 0x21, 0 + .dw 0xe9c0, 0xc08e, 0xe9ff, 0xc08e, 0x21, 0 + .dw 0xea40, 0xc08e, 0xea7f, 0xc08e, 0x21, 0 + .dw 0xeac0, 0xc08e, 0xeaff, 0xc08e, 0x21, 0 + .dw 0xeb40, 0xc08e, 0xeb7f, 0xc08e, 0x21, 0 + .dw 0xebc0, 0xc08e, 0xebff, 0xc08e, 0x21, 0 + .dw 0xec40, 0xc08e, 0xec7f, 0xc08e, 0x21, 0 + .dw 0xecc0, 0xc08e, 0xecff, 0xc08e, 0x21, 0 + .dw 0xed40, 0xc08e, 0xed7f, 0xc08e, 0x21, 0 + .dw 0xedc0, 0xc08e, 0xedff, 0xc08e, 0x21, 0 + .dw 0xee40, 0xc08e, 0xee7f, 0xc08e, 0x21, 0 + .dw 0xeec0, 0xc08e, 0xeeff, 0xc08e, 0x21, 0 + .dw 0xef40, 0xc08e, 0xef7f, 0xc08e, 0x21, 0 + .dw 0xefc0, 0xc08e, 0xefff, 0xc08e, 0x21, 0 + .dw 0xf040, 0xc08e, 0xf07f, 0xc08e, 0x21, 0 + .dw 0xf0c0, 0xc08e, 0xf0ff, 0xc08e, 0x21, 0 + .dw 0xf140, 0xc08e, 0xf17f, 0xc08e, 0x21, 0 + .dw 0xf1c0, 0xc08e, 0xf1ff, 0xc08e, 0x21, 0 + .dw 0xf240, 0xc08e, 0xf27f, 0xc08e, 0x21, 0 + .dw 0xf2c0, 0xc08e, 0xf2ff, 0xc08e, 0x21, 0 + .dw 0xf340, 0xc08e, 0xf37f, 0xc08e, 0x21, 0 + .dw 0xf3c0, 0xc08e, 0xf3ff, 0xc08e, 0x21, 0 + .dw 0xf440, 0xc08e, 0xf47f, 0xc08e, 0x21, 0 + .dw 0xf4c0, 0xc08e, 0xf4ff, 0xc08e, 0x21, 0 + .dw 0xf540, 0xc08e, 0xf57f, 0xc08e, 0x21, 0 + .dw 0xf5c0, 0xc08e, 0xf5ff, 0xc08e, 0x21, 0 + .dw 0xf640, 0xc08e, 0xf67f, 0xc08e, 0x21, 0 + .dw 0xf6c0, 0xc08e, 0xf6ff, 0xc08e, 0x21, 0 + .dw 0xf740, 0xc08e, 0xf77f, 0xc08e, 0x21, 0 + .dw 0xf7c0, 0xc08e, 0xf7ff, 0xc08e, 0x21, 0 + .dw 0xf840, 0xc08e, 0xf87f, 0xc08e, 0x21, 0 + .dw 0xf8c0, 0xc08e, 0xf8ff, 0xc08e, 0x21, 0 + .dw 0xf940, 0xc08e, 0xf97f, 0xc08e, 0x21, 0 + .dw 0xf9c0, 0xc08e, 0xffff, 0xc08e, 0x21, 0 + .dw 0x0040, 0xc08f, 0x007f, 0xc08f, 0x21, 0 + .dw 0x00c0, 0xc08f, 0x00ff, 0xc08f, 0x21, 0 + .dw 0x0140, 0xc08f, 0x017f, 0xc08f, 0x21, 0 + .dw 0x01c0, 0xc08f, 0x01ff, 0xc08f, 0x21, 0 + .dw 0x0240, 0xc08f, 0x027f, 0xc08f, 0x21, 0 + .dw 0x02c0, 0xc08f, 0x02ff, 0xc08f, 0x21, 0 + .dw 0x0340, 0xc08f, 0x037f, 0xc08f, 0x21, 0 + .dw 0x03c0, 0xc08f, 0x03ff, 0xc08f, 0x21, 0 + .dw 0x0440, 0xc08f, 0x047f, 0xc08f, 0x21, 0 + .dw 0x04c0, 0xc08f, 0x04ff, 0xc08f, 0x21, 0 + .dw 0x0540, 0xc08f, 0x057f, 0xc08f, 0x21, 0 + .dw 0x05c0, 0xc08f, 0x05ff, 0xc08f, 0x21, 0 + .dw 0x0640, 0xc08f, 0x067f, 0xc08f, 0x21, 0 + .dw 0x06c0, 0xc08f, 0x06ff, 0xc08f, 0x21, 0 + .dw 0x0740, 0xc08f, 0x077f, 0xc08f, 0x21, 0 + .dw 0x07c0, 0xc08f, 0x07ff, 0xc08f, 0x21, 0 + .dw 0x0840, 0xc08f, 0x087f, 0xc08f, 0x21, 0 + .dw 0x08c0, 0xc08f, 0x08ff, 0xc08f, 0x21, 0 + .dw 0x0940, 0xc08f, 0x097f, 0xc08f, 0x21, 0 + .dw 0x09c0, 0xc08f, 0x09ff, 0xc08f, 0x21, 0 + .dw 0x0a40, 0xc08f, 0x0a7f, 0xc08f, 0x21, 0 + .dw 0x0ac0, 0xc08f, 0x0aff, 0xc08f, 0x21, 0 + .dw 0x0b40, 0xc08f, 0x0b7f, 0xc08f, 0x21, 0 + .dw 0x0bc0, 0xc08f, 0x0bff, 0xc08f, 0x21, 0 + .dw 0x0c40, 0xc08f, 0x0c7f, 0xc08f, 0x21, 0 + .dw 0x0cc0, 0xc08f, 0x0cff, 0xc08f, 0x21, 0 + .dw 0x0d40, 0xc08f, 0x0d7f, 0xc08f, 0x21, 0 + .dw 0x0dc0, 0xc08f, 0x0dff, 0xc08f, 0x21, 0 + .dw 0x0e40, 0xc08f, 0x0e7f, 0xc08f, 0x21, 0 + .dw 0x0ec0, 0xc08f, 0x0eff, 0xc08f, 0x21, 0 + .dw 0x0f40, 0xc08f, 0x0f7f, 0xc08f, 0x21, 0 + .dw 0x0fc0, 0xc08f, 0x0fff, 0xc08f, 0x21, 0 + .dw 0x1040, 0xc08f, 0x107f, 0xc08f, 0x21, 0 + .dw 0x10c0, 0xc08f, 0x10ff, 0xc08f, 0x21, 0 + .dw 0x1140, 0xc08f, 0x117f, 0xc08f, 0x21, 0 + .dw 0x11c0, 0xc08f, 0x11ff, 0xc08f, 0x21, 0 + .dw 0x1240, 0xc08f, 0x127f, 0xc08f, 0x21, 0 + .dw 0x12c0, 0xc08f, 0x12ff, 0xc08f, 0x21, 0 + .dw 0x1340, 0xc08f, 0x137f, 0xc08f, 0x21, 0 + .dw 0x13c0, 0xc08f, 0x13ff, 0xc08f, 0x21, 0 + .dw 0x1440, 0xc08f, 0x147f, 0xc08f, 0x21, 0 + .dw 0x14c0, 0xc08f, 0x14ff, 0xc08f, 0x21, 0 + .dw 0x1540, 0xc08f, 0x157f, 0xc08f, 0x21, 0 + .dw 0x15c0, 0xc08f, 0x15ff, 0xc08f, 0x21, 0 + .dw 0x1640, 0xc08f, 0x167f, 0xc08f, 0x21, 0 + .dw 0x16c0, 0xc08f, 0x16ff, 0xc08f, 0x21, 0 + .dw 0x1740, 0xc08f, 0x177f, 0xc08f, 0x21, 0 + .dw 0x17c0, 0xc08f, 0x17ff, 0xc08f, 0x21, 0 + .dw 0x1840, 0xc08f, 0x187f, 0xc08f, 0x21, 0 + .dw 0x18c0, 0xc08f, 0x18ff, 0xc08f, 0x21, 0 + .dw 0x1940, 0xc08f, 0x197f, 0xc08f, 0x21, 0 + .dw 0x19c0, 0xc08f, 0x1fff, 0xc08f, 0x21, 0 + .dw 0x2040, 0xc08f, 0x207f, 0xc08f, 0x21, 0 + .dw 0x20c0, 0xc08f, 0x20ff, 0xc08f, 0x21, 0 + .dw 0x2140, 0xc08f, 0x217f, 0xc08f, 0x21, 0 + .dw 0x21c0, 0xc08f, 0x21ff, 0xc08f, 0x21, 0 + .dw 0x2240, 0xc08f, 0x227f, 0xc08f, 0x21, 0 + .dw 0x22c0, 0xc08f, 0x22ff, 0xc08f, 0x21, 0 + .dw 0x2340, 0xc08f, 0x237f, 0xc08f, 0x21, 0 + .dw 0x23c0, 0xc08f, 0x23ff, 0xc08f, 0x21, 0 + .dw 0x2440, 0xc08f, 0x247f, 0xc08f, 0x21, 0 + .dw 0x24c0, 0xc08f, 0x24ff, 0xc08f, 0x21, 0 + .dw 0x2540, 0xc08f, 0x257f, 0xc08f, 0x21, 0 + .dw 0x25c0, 0xc08f, 0x25ff, 0xc08f, 0x21, 0 + .dw 0x2640, 0xc08f, 0x267f, 0xc08f, 0x21, 0 + .dw 0x26c0, 0xc08f, 0x26ff, 0xc08f, 0x21, 0 + .dw 0x2740, 0xc08f, 0x277f, 0xc08f, 0x21, 0 + .dw 0x27c0, 0xc08f, 0x27ff, 0xc08f, 0x21, 0 + .dw 0x2840, 0xc08f, 0x287f, 0xc08f, 0x21, 0 + .dw 0x28c0, 0xc08f, 0x28ff, 0xc08f, 0x21, 0 + .dw 0x2940, 0xc08f, 0x297f, 0xc08f, 0x21, 0 + .dw 0x29c0, 0xc08f, 0x29ff, 0xc08f, 0x21, 0 + .dw 0x2a40, 0xc08f, 0x2a7f, 0xc08f, 0x21, 0 + .dw 0x2ac0, 0xc08f, 0x2aff, 0xc08f, 0x21, 0 + .dw 0x2b40, 0xc08f, 0x2b7f, 0xc08f, 0x21, 0 + .dw 0x2bc0, 0xc08f, 0x2bff, 0xc08f, 0x21, 0 + .dw 0x2c40, 0xc08f, 0x2c7f, 0xc08f, 0x21, 0 + .dw 0x2cc0, 0xc08f, 0x2cff, 0xc08f, 0x21, 0 + .dw 0x2d40, 0xc08f, 0x2d7f, 0xc08f, 0x21, 0 + .dw 0x2dc0, 0xc08f, 0x2dff, 0xc08f, 0x21, 0 + .dw 0x2e40, 0xc08f, 0x2e7f, 0xc08f, 0x21, 0 + .dw 0x2ec0, 0xc08f, 0x2eff, 0xc08f, 0x21, 0 + .dw 0x2f40, 0xc08f, 0x2f7f, 0xc08f, 0x21, 0 + .dw 0x2fc0, 0xc08f, 0x2fff, 0xc08f, 0x21, 0 + .dw 0x3040, 0xc08f, 0x307f, 0xc08f, 0x21, 0 + .dw 0x30c0, 0xc08f, 0x30ff, 0xc08f, 0x21, 0 + .dw 0x3140, 0xc08f, 0x317f, 0xc08f, 0x21, 0 + .dw 0x31c0, 0xc08f, 0x31ff, 0xc08f, 0x21, 0 + .dw 0x3240, 0xc08f, 0x327f, 0xc08f, 0x21, 0 + .dw 0x32c0, 0xc08f, 0x32ff, 0xc08f, 0x21, 0 + .dw 0x3340, 0xc08f, 0x337f, 0xc08f, 0x21, 0 + .dw 0x33c0, 0xc08f, 0x33ff, 0xc08f, 0x21, 0 + .dw 0x3440, 0xc08f, 0x347f, 0xc08f, 0x21, 0 + .dw 0x34c0, 0xc08f, 0x34ff, 0xc08f, 0x21, 0 + .dw 0x3540, 0xc08f, 0x357f, 0xc08f, 0x21, 0 + .dw 0x35c0, 0xc08f, 0x35ff, 0xc08f, 0x21, 0 + .dw 0x3640, 0xc08f, 0x367f, 0xc08f, 0x21, 0 + .dw 0x36c0, 0xc08f, 0x36ff, 0xc08f, 0x21, 0 + .dw 0x3740, 0xc08f, 0x377f, 0xc08f, 0x21, 0 + .dw 0x37c0, 0xc08f, 0x37ff, 0xc08f, 0x21, 0 + .dw 0x3840, 0xc08f, 0x387f, 0xc08f, 0x21, 0 + .dw 0x38c0, 0xc08f, 0x38ff, 0xc08f, 0x21, 0 + .dw 0x3940, 0xc08f, 0x397f, 0xc08f, 0x21, 0 + .dw 0x39c0, 0xc08f, 0xffff, 0xc08f, 0x21, 0 + .dw 0x1a00, 0xc090, 0x1fff, 0xc090, 0x21, 0 + .dw 0x3a00, 0xc090, 0x3fff, 0xc090, 0x21, 0 + .dw 0x5a00, 0xc090, 0x5fff, 0xc090, 0x21, 0 + .dw 0x7a00, 0xc090, 0x7fff, 0xc090, 0x21, 0 + .dw 0x9a00, 0xc090, 0x9fff, 0xc090, 0x21, 0 + .dw 0xba00, 0xc090, 0xbfff, 0xc090, 0x21, 0 + .dw 0xda00, 0xc090, 0xdfff, 0xc090, 0x21, 0 + .dw 0xfa00, 0xc090, 0xffff, 0xc090, 0x21, 0 + .dw 0x1a00, 0xc091, 0x1fff, 0xc091, 0x21, 0 + .dw 0x3a00, 0xc091, 0x3fff, 0xc091, 0x21, 0 + .dw 0x5a00, 0xc091, 0x5fff, 0xc091, 0x21, 0 + .dw 0x7a00, 0xc091, 0x7fff, 0xc091, 0x21, 0 + .dw 0x9a00, 0xc091, 0x9fff, 0xc091, 0x21, 0 + .dw 0xba00, 0xc091, 0xbfff, 0xc091, 0x21, 0 + .dw 0xda00, 0xc091, 0xdfff, 0xc091, 0x21, 0 + .dw 0xfa00, 0xc091, 0xffff, 0xc091, 0x21, 0 + .dw 0x1a00, 0xc092, 0x1fff, 0xc092, 0x21, 0 + .dw 0x3a00, 0xc092, 0x3fff, 0xc092, 0x21, 0 + .dw 0x5a00, 0xc092, 0x5fff, 0xc092, 0x21, 0 + .dw 0x7a00, 0xc092, 0x7fff, 0xc092, 0x21, 0 + .dw 0x9a00, 0xc092, 0x9fff, 0xc092, 0x21, 0 + .dw 0xba00, 0xc092, 0xbfff, 0xc092, 0x21, 0 + .dw 0xda00, 0xc092, 0xdfff, 0xc092, 0x21, 0 + .dw 0xfa00, 0xc092, 0xffff, 0xc093, 0x21, 0 + .dw 0x1a00, 0xc094, 0x1fff, 0xc094, 0x21, 0 + .dw 0x3a00, 0xc094, 0x3fff, 0xc094, 0x21, 0 + .dw 0x5a00, 0xc094, 0x5fff, 0xc094, 0x21, 0 + .dw 0x7a00, 0xc094, 0x7fff, 0xc094, 0x21, 0 + .dw 0x9a00, 0xc094, 0x9fff, 0xc094, 0x21, 0 + .dw 0xba00, 0xc094, 0xbfff, 0xc094, 0x21, 0 + .dw 0xda00, 0xc094, 0xdfff, 0xc094, 0x21, 0 + .dw 0xfa00, 0xc094, 0xffff, 0xc094, 0x21, 0 + .dw 0x1a00, 0xc095, 0x1fff, 0xc095, 0x21, 0 + .dw 0x3a00, 0xc095, 0x3fff, 0xc095, 0x21, 0 + .dw 0x5a00, 0xc095, 0x5fff, 0xc095, 0x21, 0 + .dw 0x7a00, 0xc095, 0x7fff, 0xc095, 0x21, 0 + .dw 0x9a00, 0xc095, 0x9fff, 0xc095, 0x21, 0 + .dw 0xba00, 0xc095, 0xbfff, 0xc095, 0x21, 0 + .dw 0xda00, 0xc095, 0xdfff, 0xc095, 0x21, 0 + .dw 0xfa00, 0xc095, 0xffff, 0xc095, 0x21, 0 + .dw 0x1a00, 0xc096, 0x1fff, 0xc096, 0x21, 0 + .dw 0x3a00, 0xc096, 0x3fff, 0xc096, 0x21, 0 + .dw 0x5a00, 0xc096, 0x5fff, 0xc096, 0x21, 0 + .dw 0x7a00, 0xc096, 0x7fff, 0xc096, 0x21, 0 + .dw 0x9a00, 0xc096, 0x9fff, 0xc096, 0x21, 0 + .dw 0xba00, 0xc096, 0xbfff, 0xc096, 0x21, 0 + .dw 0xda00, 0xc096, 0xdfff, 0xc096, 0x21, 0 + .dw 0xfa00, 0xc096, 0xffff, 0xc096, 0x21, 0 + .dw 0x1a00, 0xc097, 0x1fff, 0xc097, 0x21, 0 + .dw 0x3a00, 0xc097, 0x1fff, 0xc098, 0x21, 0 + .dw 0x2040, 0xc098, 0x207f, 0xc098, 0x21, 0 + .dw 0x20c0, 0xc098, 0x20ff, 0xc098, 0x21, 0 + .dw 0x2140, 0xc098, 0x217f, 0xc098, 0x21, 0 + .dw 0x21c0, 0xc098, 0x21ff, 0xc098, 0x21, 0 + .dw 0x2240, 0xc098, 0x227f, 0xc098, 0x21, 0 + .dw 0x22c0, 0xc098, 0x22ff, 0xc098, 0x21, 0 + .dw 0x2340, 0xc098, 0x237f, 0xc098, 0x21, 0 + .dw 0x23c0, 0xc098, 0x23ff, 0xc098, 0x21, 0 + .dw 0x2440, 0xc098, 0x247f, 0xc098, 0x21, 0 + .dw 0x24c0, 0xc098, 0x24ff, 0xc098, 0x21, 0 + .dw 0x2540, 0xc098, 0x257f, 0xc098, 0x21, 0 + .dw 0x25c0, 0xc098, 0x25ff, 0xc098, 0x21, 0 + .dw 0x2640, 0xc098, 0x267f, 0xc098, 0x21, 0 + .dw 0x26c0, 0xc098, 0x26ff, 0xc098, 0x21, 0 + .dw 0x2740, 0xc098, 0x277f, 0xc098, 0x21, 0 + .dw 0x27c0, 0xc098, 0x27ff, 0xc098, 0x21, 0 + .dw 0x2840, 0xc098, 0x287f, 0xc098, 0x21, 0 + .dw 0x28c0, 0xc098, 0x28ff, 0xc098, 0x21, 0 + .dw 0x2940, 0xc098, 0x297f, 0xc098, 0x21, 0 + .dw 0x29c0, 0xc098, 0x29ff, 0xc098, 0x21, 0 + .dw 0x2a40, 0xc098, 0x2a7f, 0xc098, 0x21, 0 + .dw 0x2ac0, 0xc098, 0x2aff, 0xc098, 0x21, 0 + .dw 0x2b40, 0xc098, 0x2b7f, 0xc098, 0x21, 0 + .dw 0x2bc0, 0xc098, 0x2bff, 0xc098, 0x21, 0 + .dw 0x2c40, 0xc098, 0x2c7f, 0xc098, 0x21, 0 + .dw 0x2cc0, 0xc098, 0x2cff, 0xc098, 0x21, 0 + .dw 0x2d40, 0xc098, 0x2d7f, 0xc098, 0x21, 0 + .dw 0x2dc0, 0xc098, 0x2dff, 0xc098, 0x21, 0 + .dw 0x2e40, 0xc098, 0x2e7f, 0xc098, 0x21, 0 + .dw 0x2ec0, 0xc098, 0x2eff, 0xc098, 0x21, 0 + .dw 0x2f40, 0xc098, 0x2f7f, 0xc098, 0x21, 0 + .dw 0x2fc0, 0xc098, 0x2fff, 0xc098, 0x21, 0 + .dw 0x3040, 0xc098, 0x307f, 0xc098, 0x21, 0 + .dw 0x30c0, 0xc098, 0x30ff, 0xc098, 0x21, 0 + .dw 0x3140, 0xc098, 0x317f, 0xc098, 0x21, 0 + .dw 0x31c0, 0xc098, 0x31ff, 0xc098, 0x21, 0 + .dw 0x3240, 0xc098, 0x327f, 0xc098, 0x21, 0 + .dw 0x32c0, 0xc098, 0x32ff, 0xc098, 0x21, 0 + .dw 0x3340, 0xc098, 0x337f, 0xc098, 0x21, 0 + .dw 0x33c0, 0xc098, 0x33ff, 0xc098, 0x21, 0 + .dw 0x3440, 0xc098, 0x347f, 0xc098, 0x21, 0 + .dw 0x34c0, 0xc098, 0x34ff, 0xc098, 0x21, 0 + .dw 0x3540, 0xc098, 0x357f, 0xc098, 0x21, 0 + .dw 0x35c0, 0xc098, 0x35ff, 0xc098, 0x21, 0 + .dw 0x3640, 0xc098, 0x367f, 0xc098, 0x21, 0 + .dw 0x36c0, 0xc098, 0x36ff, 0xc098, 0x21, 0 + .dw 0x3740, 0xc098, 0x377f, 0xc098, 0x21, 0 + .dw 0x37c0, 0xc098, 0x37ff, 0xc098, 0x21, 0 + .dw 0x3840, 0xc098, 0x387f, 0xc098, 0x21, 0 + .dw 0x38c0, 0xc098, 0x38ff, 0xc098, 0x21, 0 + .dw 0x3940, 0xc098, 0x397f, 0xc098, 0x21, 0 + .dw 0x39c0, 0xc098, 0x5fff, 0xc098, 0x21, 0 + .dw 0x6040, 0xc098, 0x607f, 0xc098, 0x21, 0 + .dw 0x60c0, 0xc098, 0x60ff, 0xc098, 0x21, 0 + .dw 0x6140, 0xc098, 0x617f, 0xc098, 0x21, 0 + .dw 0x61c0, 0xc098, 0x61ff, 0xc098, 0x21, 0 + .dw 0x6240, 0xc098, 0x627f, 0xc098, 0x21, 0 + .dw 0x62c0, 0xc098, 0x62ff, 0xc098, 0x21, 0 + .dw 0x6340, 0xc098, 0x637f, 0xc098, 0x21, 0 + .dw 0x63c0, 0xc098, 0x63ff, 0xc098, 0x21, 0 + .dw 0x6440, 0xc098, 0x647f, 0xc098, 0x21, 0 + .dw 0x64c0, 0xc098, 0x64ff, 0xc098, 0x21, 0 + .dw 0x6540, 0xc098, 0x657f, 0xc098, 0x21, 0 + .dw 0x65c0, 0xc098, 0x65ff, 0xc098, 0x21, 0 + .dw 0x6640, 0xc098, 0x667f, 0xc098, 0x21, 0 + .dw 0x66c0, 0xc098, 0x66ff, 0xc098, 0x21, 0 + .dw 0x6740, 0xc098, 0x677f, 0xc098, 0x21, 0 + .dw 0x67c0, 0xc098, 0x67ff, 0xc098, 0x21, 0 + .dw 0x6840, 0xc098, 0x687f, 0xc098, 0x21, 0 + .dw 0x68c0, 0xc098, 0x68ff, 0xc098, 0x21, 0 + .dw 0x6940, 0xc098, 0x697f, 0xc098, 0x21, 0 + .dw 0x69c0, 0xc098, 0x69ff, 0xc098, 0x21, 0 + .dw 0x6a40, 0xc098, 0x6a7f, 0xc098, 0x21, 0 + .dw 0x6ac0, 0xc098, 0x6aff, 0xc098, 0x21, 0 + .dw 0x6b40, 0xc098, 0x6b7f, 0xc098, 0x21, 0 + .dw 0x6bc0, 0xc098, 0x6bff, 0xc098, 0x21, 0 + .dw 0x6c40, 0xc098, 0x6c7f, 0xc098, 0x21, 0 + .dw 0x6cc0, 0xc098, 0x6cff, 0xc098, 0x21, 0 + .dw 0x6d40, 0xc098, 0x6d7f, 0xc098, 0x21, 0 + .dw 0x6dc0, 0xc098, 0x6dff, 0xc098, 0x21, 0 + .dw 0x6e40, 0xc098, 0x6e7f, 0xc098, 0x21, 0 + .dw 0x6ec0, 0xc098, 0x6eff, 0xc098, 0x21, 0 + .dw 0x6f40, 0xc098, 0x6f7f, 0xc098, 0x21, 0 + .dw 0x6fc0, 0xc098, 0x6fff, 0xc098, 0x21, 0 + .dw 0x7040, 0xc098, 0x707f, 0xc098, 0x21, 0 + .dw 0x70c0, 0xc098, 0x70ff, 0xc098, 0x21, 0 + .dw 0x7140, 0xc098, 0x717f, 0xc098, 0x21, 0 + .dw 0x71c0, 0xc098, 0x71ff, 0xc098, 0x21, 0 + .dw 0x7240, 0xc098, 0x727f, 0xc098, 0x21, 0 + .dw 0x72c0, 0xc098, 0x72ff, 0xc098, 0x21, 0 + .dw 0x7340, 0xc098, 0x737f, 0xc098, 0x21, 0 + .dw 0x73c0, 0xc098, 0x73ff, 0xc098, 0x21, 0 + .dw 0x7440, 0xc098, 0x747f, 0xc098, 0x21, 0 + .dw 0x74c0, 0xc098, 0x74ff, 0xc098, 0x21, 0 + .dw 0x7540, 0xc098, 0x757f, 0xc098, 0x21, 0 + .dw 0x75c0, 0xc098, 0x75ff, 0xc098, 0x21, 0 + .dw 0x7640, 0xc098, 0x767f, 0xc098, 0x21, 0 + .dw 0x76c0, 0xc098, 0x76ff, 0xc098, 0x21, 0 + .dw 0x7740, 0xc098, 0x777f, 0xc098, 0x21, 0 + .dw 0x77c0, 0xc098, 0x77ff, 0xc098, 0x21, 0 + .dw 0x7840, 0xc098, 0x787f, 0xc098, 0x21, 0 + .dw 0x78c0, 0xc098, 0x78ff, 0xc098, 0x21, 0 + .dw 0x7940, 0xc098, 0x797f, 0xc098, 0x21, 0 + .dw 0x79c0, 0xc098, 0x9fff, 0xc098, 0x21, 0 + .dw 0xa040, 0xc098, 0xa07f, 0xc098, 0x21, 0 + .dw 0xa0c0, 0xc098, 0xa0ff, 0xc098, 0x21, 0 + .dw 0xa140, 0xc098, 0xa17f, 0xc098, 0x21, 0 + .dw 0xa1c0, 0xc098, 0xa1ff, 0xc098, 0x21, 0 + .dw 0xa240, 0xc098, 0xa27f, 0xc098, 0x21, 0 + .dw 0xa2c0, 0xc098, 0xa2ff, 0xc098, 0x21, 0 + .dw 0xa340, 0xc098, 0xa37f, 0xc098, 0x21, 0 + .dw 0xa3c0, 0xc098, 0xa3ff, 0xc098, 0x21, 0 + .dw 0xa440, 0xc098, 0xa47f, 0xc098, 0x21, 0 + .dw 0xa4c0, 0xc098, 0xa4ff, 0xc098, 0x21, 0 + .dw 0xa540, 0xc098, 0xa57f, 0xc098, 0x21, 0 + .dw 0xa5c0, 0xc098, 0xa5ff, 0xc098, 0x21, 0 + .dw 0xa640, 0xc098, 0xa67f, 0xc098, 0x21, 0 + .dw 0xa6c0, 0xc098, 0xa6ff, 0xc098, 0x21, 0 + .dw 0xa740, 0xc098, 0xa77f, 0xc098, 0x21, 0 + .dw 0xa7c0, 0xc098, 0xa7ff, 0xc098, 0x21, 0 + .dw 0xa840, 0xc098, 0xa87f, 0xc098, 0x21, 0 + .dw 0xa8c0, 0xc098, 0xa8ff, 0xc098, 0x21, 0 + .dw 0xa940, 0xc098, 0xa97f, 0xc098, 0x21, 0 + .dw 0xa9c0, 0xc098, 0xa9ff, 0xc098, 0x21, 0 + .dw 0xaa40, 0xc098, 0xaa7f, 0xc098, 0x21, 0 + .dw 0xaac0, 0xc098, 0xaaff, 0xc098, 0x21, 0 + .dw 0xab40, 0xc098, 0xab7f, 0xc098, 0x21, 0 + .dw 0xabc0, 0xc098, 0xabff, 0xc098, 0x21, 0 + .dw 0xac40, 0xc098, 0xac7f, 0xc098, 0x21, 0 + .dw 0xacc0, 0xc098, 0xacff, 0xc098, 0x21, 0 + .dw 0xad40, 0xc098, 0xad7f, 0xc098, 0x21, 0 + .dw 0xadc0, 0xc098, 0xadff, 0xc098, 0x21, 0 + .dw 0xae40, 0xc098, 0xae7f, 0xc098, 0x21, 0 + .dw 0xaec0, 0xc098, 0xaeff, 0xc098, 0x21, 0 + .dw 0xaf40, 0xc098, 0xaf7f, 0xc098, 0x21, 0 + .dw 0xafc0, 0xc098, 0xafff, 0xc098, 0x21, 0 + .dw 0xb040, 0xc098, 0xb07f, 0xc098, 0x21, 0 + .dw 0xb0c0, 0xc098, 0xb0ff, 0xc098, 0x21, 0 + .dw 0xb140, 0xc098, 0xb17f, 0xc098, 0x21, 0 + .dw 0xb1c0, 0xc098, 0xb1ff, 0xc098, 0x21, 0 + .dw 0xb240, 0xc098, 0xb27f, 0xc098, 0x21, 0 + .dw 0xb2c0, 0xc098, 0xb2ff, 0xc098, 0x21, 0 + .dw 0xb340, 0xc098, 0xb37f, 0xc098, 0x21, 0 + .dw 0xb3c0, 0xc098, 0xb3ff, 0xc098, 0x21, 0 + .dw 0xb440, 0xc098, 0xb47f, 0xc098, 0x21, 0 + .dw 0xb4c0, 0xc098, 0xb4ff, 0xc098, 0x21, 0 + .dw 0xb540, 0xc098, 0xb57f, 0xc098, 0x21, 0 + .dw 0xb5c0, 0xc098, 0xb5ff, 0xc098, 0x21, 0 + .dw 0xb640, 0xc098, 0xb67f, 0xc098, 0x21, 0 + .dw 0xb6c0, 0xc098, 0xb6ff, 0xc098, 0x21, 0 + .dw 0xb740, 0xc098, 0xb77f, 0xc098, 0x21, 0 + .dw 0xb7c0, 0xc098, 0xb7ff, 0xc098, 0x21, 0 + .dw 0xb840, 0xc098, 0xb87f, 0xc098, 0x21, 0 + .dw 0xb8c0, 0xc098, 0xb8ff, 0xc098, 0x21, 0 + .dw 0xb940, 0xc098, 0xb97f, 0xc098, 0x21, 0 + .dw 0xb9c0, 0xc098, 0xdfff, 0xc098, 0x21, 0 + .dw 0xe040, 0xc098, 0xe07f, 0xc098, 0x21, 0 + .dw 0xe0c0, 0xc098, 0xe0ff, 0xc098, 0x21, 0 + .dw 0xe140, 0xc098, 0xe17f, 0xc098, 0x21, 0 + .dw 0xe1c0, 0xc098, 0xe1ff, 0xc098, 0x21, 0 + .dw 0xe240, 0xc098, 0xe27f, 0xc098, 0x21, 0 + .dw 0xe2c0, 0xc098, 0xe2ff, 0xc098, 0x21, 0 + .dw 0xe340, 0xc098, 0xe37f, 0xc098, 0x21, 0 + .dw 0xe3c0, 0xc098, 0xe3ff, 0xc098, 0x21, 0 + .dw 0xe440, 0xc098, 0xe47f, 0xc098, 0x21, 0 + .dw 0xe4c0, 0xc098, 0xe4ff, 0xc098, 0x21, 0 + .dw 0xe540, 0xc098, 0xe57f, 0xc098, 0x21, 0 + .dw 0xe5c0, 0xc098, 0xe5ff, 0xc098, 0x21, 0 + .dw 0xe640, 0xc098, 0xe67f, 0xc098, 0x21, 0 + .dw 0xe6c0, 0xc098, 0xe6ff, 0xc098, 0x21, 0 + .dw 0xe740, 0xc098, 0xe77f, 0xc098, 0x21, 0 + .dw 0xe7c0, 0xc098, 0xe7ff, 0xc098, 0x21, 0 + .dw 0xe840, 0xc098, 0xe87f, 0xc098, 0x21, 0 + .dw 0xe8c0, 0xc098, 0xe8ff, 0xc098, 0x21, 0 + .dw 0xe940, 0xc098, 0xe97f, 0xc098, 0x21, 0 + .dw 0xe9c0, 0xc098, 0xe9ff, 0xc098, 0x21, 0 + .dw 0xea40, 0xc098, 0xea7f, 0xc098, 0x21, 0 + .dw 0xeac0, 0xc098, 0xeaff, 0xc098, 0x21, 0 + .dw 0xeb40, 0xc098, 0xeb7f, 0xc098, 0x21, 0 + .dw 0xebc0, 0xc098, 0xebff, 0xc098, 0x21, 0 + .dw 0xec40, 0xc098, 0xec7f, 0xc098, 0x21, 0 + .dw 0xecc0, 0xc098, 0xecff, 0xc098, 0x21, 0 + .dw 0xed40, 0xc098, 0xed7f, 0xc098, 0x21, 0 + .dw 0xedc0, 0xc098, 0xedff, 0xc098, 0x21, 0 + .dw 0xee40, 0xc098, 0xee7f, 0xc098, 0x21, 0 + .dw 0xeec0, 0xc098, 0xeeff, 0xc098, 0x21, 0 + .dw 0xef40, 0xc098, 0xef7f, 0xc098, 0x21, 0 + .dw 0xefc0, 0xc098, 0xefff, 0xc098, 0x21, 0 + .dw 0xf040, 0xc098, 0xf07f, 0xc098, 0x21, 0 + .dw 0xf0c0, 0xc098, 0xf0ff, 0xc098, 0x21, 0 + .dw 0xf140, 0xc098, 0xf17f, 0xc098, 0x21, 0 + .dw 0xf1c0, 0xc098, 0xf1ff, 0xc098, 0x21, 0 + .dw 0xf240, 0xc098, 0xf27f, 0xc098, 0x21, 0 + .dw 0xf2c0, 0xc098, 0xf2ff, 0xc098, 0x21, 0 + .dw 0xf340, 0xc098, 0xf37f, 0xc098, 0x21, 0 + .dw 0xf3c0, 0xc098, 0xf3ff, 0xc098, 0x21, 0 + .dw 0xf440, 0xc098, 0xf47f, 0xc098, 0x21, 0 + .dw 0xf4c0, 0xc098, 0xf4ff, 0xc098, 0x21, 0 + .dw 0xf540, 0xc098, 0xf57f, 0xc098, 0x21, 0 + .dw 0xf5c0, 0xc098, 0xf5ff, 0xc098, 0x21, 0 + .dw 0xf640, 0xc098, 0xf67f, 0xc098, 0x21, 0 + .dw 0xf6c0, 0xc098, 0xf6ff, 0xc098, 0x21, 0 + .dw 0xf740, 0xc098, 0xf77f, 0xc098, 0x21, 0 + .dw 0xf7c0, 0xc098, 0xf7ff, 0xc098, 0x21, 0 + .dw 0xf840, 0xc098, 0xf87f, 0xc098, 0x21, 0 + .dw 0xf8c0, 0xc098, 0xf8ff, 0xc098, 0x21, 0 + .dw 0xf940, 0xc098, 0xf97f, 0xc098, 0x21, 0 + .dw 0xf9c0, 0xc098, 0x1fff, 0xc099, 0x21, 0 + .dw 0x2040, 0xc099, 0x207f, 0xc099, 0x21, 0 + .dw 0x20c0, 0xc099, 0x20ff, 0xc099, 0x21, 0 + .dw 0x2140, 0xc099, 0x217f, 0xc099, 0x21, 0 + .dw 0x21c0, 0xc099, 0x21ff, 0xc099, 0x21, 0 + .dw 0x2240, 0xc099, 0x227f, 0xc099, 0x21, 0 + .dw 0x22c0, 0xc099, 0x22ff, 0xc099, 0x21, 0 + .dw 0x2340, 0xc099, 0x237f, 0xc099, 0x21, 0 + .dw 0x23c0, 0xc099, 0x23ff, 0xc099, 0x21, 0 + .dw 0x2440, 0xc099, 0x247f, 0xc099, 0x21, 0 + .dw 0x24c0, 0xc099, 0x24ff, 0xc099, 0x21, 0 + .dw 0x2540, 0xc099, 0x257f, 0xc099, 0x21, 0 + .dw 0x25c0, 0xc099, 0x25ff, 0xc099, 0x21, 0 + .dw 0x2640, 0xc099, 0x267f, 0xc099, 0x21, 0 + .dw 0x26c0, 0xc099, 0x26ff, 0xc099, 0x21, 0 + .dw 0x2740, 0xc099, 0x277f, 0xc099, 0x21, 0 + .dw 0x27c0, 0xc099, 0x27ff, 0xc099, 0x21, 0 + .dw 0x2840, 0xc099, 0x287f, 0xc099, 0x21, 0 + .dw 0x28c0, 0xc099, 0x28ff, 0xc099, 0x21, 0 + .dw 0x2940, 0xc099, 0x297f, 0xc099, 0x21, 0 + .dw 0x29c0, 0xc099, 0x29ff, 0xc099, 0x21, 0 + .dw 0x2a40, 0xc099, 0x2a7f, 0xc099, 0x21, 0 + .dw 0x2ac0, 0xc099, 0x2aff, 0xc099, 0x21, 0 + .dw 0x2b40, 0xc099, 0x2b7f, 0xc099, 0x21, 0 + .dw 0x2bc0, 0xc099, 0x2bff, 0xc099, 0x21, 0 + .dw 0x2c40, 0xc099, 0x2c7f, 0xc099, 0x21, 0 + .dw 0x2cc0, 0xc099, 0x2cff, 0xc099, 0x21, 0 + .dw 0x2d40, 0xc099, 0x2d7f, 0xc099, 0x21, 0 + .dw 0x2dc0, 0xc099, 0x2dff, 0xc099, 0x21, 0 + .dw 0x2e40, 0xc099, 0x2e7f, 0xc099, 0x21, 0 + .dw 0x2ec0, 0xc099, 0x2eff, 0xc099, 0x21, 0 + .dw 0x2f40, 0xc099, 0x2f7f, 0xc099, 0x21, 0 + .dw 0x2fc0, 0xc099, 0x2fff, 0xc099, 0x21, 0 + .dw 0x3040, 0xc099, 0x307f, 0xc099, 0x21, 0 + .dw 0x30c0, 0xc099, 0x30ff, 0xc099, 0x21, 0 + .dw 0x3140, 0xc099, 0x317f, 0xc099, 0x21, 0 + .dw 0x31c0, 0xc099, 0x31ff, 0xc099, 0x21, 0 + .dw 0x3240, 0xc099, 0x327f, 0xc099, 0x21, 0 + .dw 0x32c0, 0xc099, 0x32ff, 0xc099, 0x21, 0 + .dw 0x3340, 0xc099, 0x337f, 0xc099, 0x21, 0 + .dw 0x33c0, 0xc099, 0x33ff, 0xc099, 0x21, 0 + .dw 0x3440, 0xc099, 0x347f, 0xc099, 0x21, 0 + .dw 0x34c0, 0xc099, 0x34ff, 0xc099, 0x21, 0 + .dw 0x3540, 0xc099, 0x357f, 0xc099, 0x21, 0 + .dw 0x35c0, 0xc099, 0x35ff, 0xc099, 0x21, 0 + .dw 0x3640, 0xc099, 0x367f, 0xc099, 0x21, 0 + .dw 0x36c0, 0xc099, 0x36ff, 0xc099, 0x21, 0 + .dw 0x3740, 0xc099, 0x377f, 0xc099, 0x21, 0 + .dw 0x37c0, 0xc099, 0x37ff, 0xc099, 0x21, 0 + .dw 0x3840, 0xc099, 0x387f, 0xc099, 0x21, 0 + .dw 0x38c0, 0xc099, 0x38ff, 0xc099, 0x21, 0 + .dw 0x3940, 0xc099, 0x397f, 0xc099, 0x21, 0 + .dw 0x39c0, 0xc099, 0x5fff, 0xc099, 0x21, 0 + .dw 0x6040, 0xc099, 0x607f, 0xc099, 0x21, 0 + .dw 0x60c0, 0xc099, 0x60ff, 0xc099, 0x21, 0 + .dw 0x6140, 0xc099, 0x617f, 0xc099, 0x21, 0 + .dw 0x61c0, 0xc099, 0x61ff, 0xc099, 0x21, 0 + .dw 0x6240, 0xc099, 0x627f, 0xc099, 0x21, 0 + .dw 0x62c0, 0xc099, 0x62ff, 0xc099, 0x21, 0 + .dw 0x6340, 0xc099, 0x637f, 0xc099, 0x21, 0 + .dw 0x63c0, 0xc099, 0x63ff, 0xc099, 0x21, 0 + .dw 0x6440, 0xc099, 0x647f, 0xc099, 0x21, 0 + .dw 0x64c0, 0xc099, 0x64ff, 0xc099, 0x21, 0 + .dw 0x6540, 0xc099, 0x657f, 0xc099, 0x21, 0 + .dw 0x65c0, 0xc099, 0x65ff, 0xc099, 0x21, 0 + .dw 0x6640, 0xc099, 0x667f, 0xc099, 0x21, 0 + .dw 0x66c0, 0xc099, 0x66ff, 0xc099, 0x21, 0 + .dw 0x6740, 0xc099, 0x677f, 0xc099, 0x21, 0 + .dw 0x67c0, 0xc099, 0x67ff, 0xc099, 0x21, 0 + .dw 0x6840, 0xc099, 0x687f, 0xc099, 0x21, 0 + .dw 0x68c0, 0xc099, 0x68ff, 0xc099, 0x21, 0 + .dw 0x6940, 0xc099, 0x697f, 0xc099, 0x21, 0 + .dw 0x69c0, 0xc099, 0x69ff, 0xc099, 0x21, 0 + .dw 0x6a40, 0xc099, 0x6a7f, 0xc099, 0x21, 0 + .dw 0x6ac0, 0xc099, 0x6aff, 0xc099, 0x21, 0 + .dw 0x6b40, 0xc099, 0x6b7f, 0xc099, 0x21, 0 + .dw 0x6bc0, 0xc099, 0x6bff, 0xc099, 0x21, 0 + .dw 0x6c40, 0xc099, 0x6c7f, 0xc099, 0x21, 0 + .dw 0x6cc0, 0xc099, 0x6cff, 0xc099, 0x21, 0 + .dw 0x6d40, 0xc099, 0x6d7f, 0xc099, 0x21, 0 + .dw 0x6dc0, 0xc099, 0x6dff, 0xc099, 0x21, 0 + .dw 0x6e40, 0xc099, 0x6e7f, 0xc099, 0x21, 0 + .dw 0x6ec0, 0xc099, 0x6eff, 0xc099, 0x21, 0 + .dw 0x6f40, 0xc099, 0x6f7f, 0xc099, 0x21, 0 + .dw 0x6fc0, 0xc099, 0x6fff, 0xc099, 0x21, 0 + .dw 0x7040, 0xc099, 0x707f, 0xc099, 0x21, 0 + .dw 0x70c0, 0xc099, 0x70ff, 0xc099, 0x21, 0 + .dw 0x7140, 0xc099, 0x717f, 0xc099, 0x21, 0 + .dw 0x71c0, 0xc099, 0x71ff, 0xc099, 0x21, 0 + .dw 0x7240, 0xc099, 0x727f, 0xc099, 0x21, 0 + .dw 0x72c0, 0xc099, 0x72ff, 0xc099, 0x21, 0 + .dw 0x7340, 0xc099, 0x737f, 0xc099, 0x21, 0 + .dw 0x73c0, 0xc099, 0x73ff, 0xc099, 0x21, 0 + .dw 0x7440, 0xc099, 0x747f, 0xc099, 0x21, 0 + .dw 0x74c0, 0xc099, 0x74ff, 0xc099, 0x21, 0 + .dw 0x7540, 0xc099, 0x757f, 0xc099, 0x21, 0 + .dw 0x75c0, 0xc099, 0x75ff, 0xc099, 0x21, 0 + .dw 0x7640, 0xc099, 0x767f, 0xc099, 0x21, 0 + .dw 0x76c0, 0xc099, 0x76ff, 0xc099, 0x21, 0 + .dw 0x7740, 0xc099, 0x777f, 0xc099, 0x21, 0 + .dw 0x77c0, 0xc099, 0x77ff, 0xc099, 0x21, 0 + .dw 0x7840, 0xc099, 0x787f, 0xc099, 0x21, 0 + .dw 0x78c0, 0xc099, 0x78ff, 0xc099, 0x21, 0 + .dw 0x7940, 0xc099, 0x797f, 0xc099, 0x21, 0 + .dw 0x79c0, 0xc099, 0x9fff, 0xc099, 0x21, 0 + .dw 0xa040, 0xc099, 0xa07f, 0xc099, 0x21, 0 + .dw 0xa0c0, 0xc099, 0xa0ff, 0xc099, 0x21, 0 + .dw 0xa140, 0xc099, 0xa17f, 0xc099, 0x21, 0 + .dw 0xa1c0, 0xc099, 0xa1ff, 0xc099, 0x21, 0 + .dw 0xa240, 0xc099, 0xa27f, 0xc099, 0x21, 0 + .dw 0xa2c0, 0xc099, 0xa2ff, 0xc099, 0x21, 0 + .dw 0xa340, 0xc099, 0xa37f, 0xc099, 0x21, 0 + .dw 0xa3c0, 0xc099, 0xa3ff, 0xc099, 0x21, 0 + .dw 0xa440, 0xc099, 0xa47f, 0xc099, 0x21, 0 + .dw 0xa4c0, 0xc099, 0xa4ff, 0xc099, 0x21, 0 + .dw 0xa540, 0xc099, 0xa57f, 0xc099, 0x21, 0 + .dw 0xa5c0, 0xc099, 0xa5ff, 0xc099, 0x21, 0 + .dw 0xa640, 0xc099, 0xa67f, 0xc099, 0x21, 0 + .dw 0xa6c0, 0xc099, 0xa6ff, 0xc099, 0x21, 0 + .dw 0xa740, 0xc099, 0xa77f, 0xc099, 0x21, 0 + .dw 0xa7c0, 0xc099, 0xa7ff, 0xc099, 0x21, 0 + .dw 0xa840, 0xc099, 0xa87f, 0xc099, 0x21, 0 + .dw 0xa8c0, 0xc099, 0xa8ff, 0xc099, 0x21, 0 + .dw 0xa940, 0xc099, 0xa97f, 0xc099, 0x21, 0 + .dw 0xa9c0, 0xc099, 0xa9ff, 0xc099, 0x21, 0 + .dw 0xaa40, 0xc099, 0xaa7f, 0xc099, 0x21, 0 + .dw 0xaac0, 0xc099, 0xaaff, 0xc099, 0x21, 0 + .dw 0xab40, 0xc099, 0xab7f, 0xc099, 0x21, 0 + .dw 0xabc0, 0xc099, 0xabff, 0xc099, 0x21, 0 + .dw 0xac40, 0xc099, 0xac7f, 0xc099, 0x21, 0 + .dw 0xacc0, 0xc099, 0xacff, 0xc099, 0x21, 0 + .dw 0xad40, 0xc099, 0xad7f, 0xc099, 0x21, 0 + .dw 0xadc0, 0xc099, 0xadff, 0xc099, 0x21, 0 + .dw 0xae40, 0xc099, 0xae7f, 0xc099, 0x21, 0 + .dw 0xaec0, 0xc099, 0xaeff, 0xc099, 0x21, 0 + .dw 0xaf40, 0xc099, 0xaf7f, 0xc099, 0x21, 0 + .dw 0xafc0, 0xc099, 0xafff, 0xc099, 0x21, 0 + .dw 0xb040, 0xc099, 0xb07f, 0xc099, 0x21, 0 + .dw 0xb0c0, 0xc099, 0xb0ff, 0xc099, 0x21, 0 + .dw 0xb140, 0xc099, 0xb17f, 0xc099, 0x21, 0 + .dw 0xb1c0, 0xc099, 0xb1ff, 0xc099, 0x21, 0 + .dw 0xb240, 0xc099, 0xb27f, 0xc099, 0x21, 0 + .dw 0xb2c0, 0xc099, 0xb2ff, 0xc099, 0x21, 0 + .dw 0xb340, 0xc099, 0xb37f, 0xc099, 0x21, 0 + .dw 0xb3c0, 0xc099, 0xb3ff, 0xc099, 0x21, 0 + .dw 0xb440, 0xc099, 0xb47f, 0xc099, 0x21, 0 + .dw 0xb4c0, 0xc099, 0xb4ff, 0xc099, 0x21, 0 + .dw 0xb540, 0xc099, 0xb57f, 0xc099, 0x21, 0 + .dw 0xb5c0, 0xc099, 0xb5ff, 0xc099, 0x21, 0 + .dw 0xb640, 0xc099, 0xb67f, 0xc099, 0x21, 0 + .dw 0xb6c0, 0xc099, 0xb6ff, 0xc099, 0x21, 0 + .dw 0xb740, 0xc099, 0xb77f, 0xc099, 0x21, 0 + .dw 0xb7c0, 0xc099, 0xb7ff, 0xc099, 0x21, 0 + .dw 0xb840, 0xc099, 0xb87f, 0xc099, 0x21, 0 + .dw 0xb8c0, 0xc099, 0xb8ff, 0xc099, 0x21, 0 + .dw 0xb940, 0xc099, 0xb97f, 0xc099, 0x21, 0 + .dw 0xb9c0, 0xc099, 0xdfff, 0xc099, 0x21, 0 + .dw 0xe040, 0xc099, 0xe07f, 0xc099, 0x21, 0 + .dw 0xe0c0, 0xc099, 0xe0ff, 0xc099, 0x21, 0 + .dw 0xe140, 0xc099, 0xe17f, 0xc099, 0x21, 0 + .dw 0xe1c0, 0xc099, 0xe1ff, 0xc099, 0x21, 0 + .dw 0xe240, 0xc099, 0xe27f, 0xc099, 0x21, 0 + .dw 0xe2c0, 0xc099, 0xe2ff, 0xc099, 0x21, 0 + .dw 0xe340, 0xc099, 0xe37f, 0xc099, 0x21, 0 + .dw 0xe3c0, 0xc099, 0xe3ff, 0xc099, 0x21, 0 + .dw 0xe440, 0xc099, 0xe47f, 0xc099, 0x21, 0 + .dw 0xe4c0, 0xc099, 0xe4ff, 0xc099, 0x21, 0 + .dw 0xe540, 0xc099, 0xe57f, 0xc099, 0x21, 0 + .dw 0xe5c0, 0xc099, 0xe5ff, 0xc099, 0x21, 0 + .dw 0xe640, 0xc099, 0xe67f, 0xc099, 0x21, 0 + .dw 0xe6c0, 0xc099, 0xe6ff, 0xc099, 0x21, 0 + .dw 0xe740, 0xc099, 0xe77f, 0xc099, 0x21, 0 + .dw 0xe7c0, 0xc099, 0xe7ff, 0xc099, 0x21, 0 + .dw 0xe840, 0xc099, 0xe87f, 0xc099, 0x21, 0 + .dw 0xe8c0, 0xc099, 0xe8ff, 0xc099, 0x21, 0 + .dw 0xe940, 0xc099, 0xe97f, 0xc099, 0x21, 0 + .dw 0xe9c0, 0xc099, 0xe9ff, 0xc099, 0x21, 0 + .dw 0xea40, 0xc099, 0xea7f, 0xc099, 0x21, 0 + .dw 0xeac0, 0xc099, 0xeaff, 0xc099, 0x21, 0 + .dw 0xeb40, 0xc099, 0xeb7f, 0xc099, 0x21, 0 + .dw 0xebc0, 0xc099, 0xebff, 0xc099, 0x21, 0 + .dw 0xec40, 0xc099, 0xec7f, 0xc099, 0x21, 0 + .dw 0xecc0, 0xc099, 0xecff, 0xc099, 0x21, 0 + .dw 0xed40, 0xc099, 0xed7f, 0xc099, 0x21, 0 + .dw 0xedc0, 0xc099, 0xedff, 0xc099, 0x21, 0 + .dw 0xee40, 0xc099, 0xee7f, 0xc099, 0x21, 0 + .dw 0xeec0, 0xc099, 0xeeff, 0xc099, 0x21, 0 + .dw 0xef40, 0xc099, 0xef7f, 0xc099, 0x21, 0 + .dw 0xefc0, 0xc099, 0xefff, 0xc099, 0x21, 0 + .dw 0xf040, 0xc099, 0xf07f, 0xc099, 0x21, 0 + .dw 0xf0c0, 0xc099, 0xf0ff, 0xc099, 0x21, 0 + .dw 0xf140, 0xc099, 0xf17f, 0xc099, 0x21, 0 + .dw 0xf1c0, 0xc099, 0xf1ff, 0xc099, 0x21, 0 + .dw 0xf240, 0xc099, 0xf27f, 0xc099, 0x21, 0 + .dw 0xf2c0, 0xc099, 0xf2ff, 0xc099, 0x21, 0 + .dw 0xf340, 0xc099, 0xf37f, 0xc099, 0x21, 0 + .dw 0xf3c0, 0xc099, 0xf3ff, 0xc099, 0x21, 0 + .dw 0xf440, 0xc099, 0xf47f, 0xc099, 0x21, 0 + .dw 0xf4c0, 0xc099, 0xf4ff, 0xc099, 0x21, 0 + .dw 0xf540, 0xc099, 0xf57f, 0xc099, 0x21, 0 + .dw 0xf5c0, 0xc099, 0xf5ff, 0xc099, 0x21, 0 + .dw 0xf640, 0xc099, 0xf67f, 0xc099, 0x21, 0 + .dw 0xf6c0, 0xc099, 0xf6ff, 0xc099, 0x21, 0 + .dw 0xf740, 0xc099, 0xf77f, 0xc099, 0x21, 0 + .dw 0xf7c0, 0xc099, 0xf7ff, 0xc099, 0x21, 0 + .dw 0xf840, 0xc099, 0xf87f, 0xc099, 0x21, 0 + .dw 0xf8c0, 0xc099, 0xf8ff, 0xc099, 0x21, 0 + .dw 0xf940, 0xc099, 0xf97f, 0xc099, 0x21, 0 + .dw 0xf9c0, 0xc099, 0x1fff, 0xc09a, 0x21, 0 + .dw 0x2040, 0xc09a, 0x207f, 0xc09a, 0x21, 0 + .dw 0x20c0, 0xc09a, 0x20ff, 0xc09a, 0x21, 0 + .dw 0x2140, 0xc09a, 0x217f, 0xc09a, 0x21, 0 + .dw 0x21c0, 0xc09a, 0x21ff, 0xc09a, 0x21, 0 + .dw 0x2240, 0xc09a, 0x227f, 0xc09a, 0x21, 0 + .dw 0x22c0, 0xc09a, 0x22ff, 0xc09a, 0x21, 0 + .dw 0x2340, 0xc09a, 0x237f, 0xc09a, 0x21, 0 + .dw 0x23c0, 0xc09a, 0x23ff, 0xc09a, 0x21, 0 + .dw 0x2440, 0xc09a, 0x247f, 0xc09a, 0x21, 0 + .dw 0x24c0, 0xc09a, 0x24ff, 0xc09a, 0x21, 0 + .dw 0x2540, 0xc09a, 0x257f, 0xc09a, 0x21, 0 + .dw 0x25c0, 0xc09a, 0x25ff, 0xc09a, 0x21, 0 + .dw 0x2640, 0xc09a, 0x267f, 0xc09a, 0x21, 0 + .dw 0x26c0, 0xc09a, 0x26ff, 0xc09a, 0x21, 0 + .dw 0x2740, 0xc09a, 0x277f, 0xc09a, 0x21, 0 + .dw 0x27c0, 0xc09a, 0x27ff, 0xc09a, 0x21, 0 + .dw 0x2840, 0xc09a, 0x287f, 0xc09a, 0x21, 0 + .dw 0x28c0, 0xc09a, 0x28ff, 0xc09a, 0x21, 0 + .dw 0x2940, 0xc09a, 0x297f, 0xc09a, 0x21, 0 + .dw 0x29c0, 0xc09a, 0x29ff, 0xc09a, 0x21, 0 + .dw 0x2a40, 0xc09a, 0x2a7f, 0xc09a, 0x21, 0 + .dw 0x2ac0, 0xc09a, 0x2aff, 0xc09a, 0x21, 0 + .dw 0x2b40, 0xc09a, 0x2b7f, 0xc09a, 0x21, 0 + .dw 0x2bc0, 0xc09a, 0x2bff, 0xc09a, 0x21, 0 + .dw 0x2c40, 0xc09a, 0x2c7f, 0xc09a, 0x21, 0 + .dw 0x2cc0, 0xc09a, 0x2cff, 0xc09a, 0x21, 0 + .dw 0x2d40, 0xc09a, 0x2d7f, 0xc09a, 0x21, 0 + .dw 0x2dc0, 0xc09a, 0x2dff, 0xc09a, 0x21, 0 + .dw 0x2e40, 0xc09a, 0x2e7f, 0xc09a, 0x21, 0 + .dw 0x2ec0, 0xc09a, 0x2eff, 0xc09a, 0x21, 0 + .dw 0x2f40, 0xc09a, 0x2f7f, 0xc09a, 0x21, 0 + .dw 0x2fc0, 0xc09a, 0x2fff, 0xc09a, 0x21, 0 + .dw 0x3040, 0xc09a, 0x307f, 0xc09a, 0x21, 0 + .dw 0x30c0, 0xc09a, 0x30ff, 0xc09a, 0x21, 0 + .dw 0x3140, 0xc09a, 0x317f, 0xc09a, 0x21, 0 + .dw 0x31c0, 0xc09a, 0x31ff, 0xc09a, 0x21, 0 + .dw 0x3240, 0xc09a, 0x327f, 0xc09a, 0x21, 0 + .dw 0x32c0, 0xc09a, 0x32ff, 0xc09a, 0x21, 0 + .dw 0x3340, 0xc09a, 0x337f, 0xc09a, 0x21, 0 + .dw 0x33c0, 0xc09a, 0x33ff, 0xc09a, 0x21, 0 + .dw 0x3440, 0xc09a, 0x347f, 0xc09a, 0x21, 0 + .dw 0x34c0, 0xc09a, 0x34ff, 0xc09a, 0x21, 0 + .dw 0x3540, 0xc09a, 0x357f, 0xc09a, 0x21, 0 + .dw 0x35c0, 0xc09a, 0x35ff, 0xc09a, 0x21, 0 + .dw 0x3640, 0xc09a, 0x367f, 0xc09a, 0x21, 0 + .dw 0x36c0, 0xc09a, 0x36ff, 0xc09a, 0x21, 0 + .dw 0x3740, 0xc09a, 0x377f, 0xc09a, 0x21, 0 + .dw 0x37c0, 0xc09a, 0x37ff, 0xc09a, 0x21, 0 + .dw 0x3840, 0xc09a, 0x387f, 0xc09a, 0x21, 0 + .dw 0x38c0, 0xc09a, 0x38ff, 0xc09a, 0x21, 0 + .dw 0x3940, 0xc09a, 0x397f, 0xc09a, 0x21, 0 + .dw 0x39c0, 0xc09a, 0x5fff, 0xc09a, 0x21, 0 + .dw 0x6040, 0xc09a, 0x607f, 0xc09a, 0x21, 0 + .dw 0x60c0, 0xc09a, 0x60ff, 0xc09a, 0x21, 0 + .dw 0x6140, 0xc09a, 0x617f, 0xc09a, 0x21, 0 + .dw 0x61c0, 0xc09a, 0x61ff, 0xc09a, 0x21, 0 + .dw 0x6240, 0xc09a, 0x627f, 0xc09a, 0x21, 0 + .dw 0x62c0, 0xc09a, 0x62ff, 0xc09a, 0x21, 0 + .dw 0x6340, 0xc09a, 0x637f, 0xc09a, 0x21, 0 + .dw 0x63c0, 0xc09a, 0x63ff, 0xc09a, 0x21, 0 + .dw 0x6440, 0xc09a, 0x647f, 0xc09a, 0x21, 0 + .dw 0x64c0, 0xc09a, 0x64ff, 0xc09a, 0x21, 0 + .dw 0x6540, 0xc09a, 0x657f, 0xc09a, 0x21, 0 + .dw 0x65c0, 0xc09a, 0x65ff, 0xc09a, 0x21, 0 + .dw 0x6640, 0xc09a, 0x667f, 0xc09a, 0x21, 0 + .dw 0x66c0, 0xc09a, 0x66ff, 0xc09a, 0x21, 0 + .dw 0x6740, 0xc09a, 0x677f, 0xc09a, 0x21, 0 + .dw 0x67c0, 0xc09a, 0x67ff, 0xc09a, 0x21, 0 + .dw 0x6840, 0xc09a, 0x687f, 0xc09a, 0x21, 0 + .dw 0x68c0, 0xc09a, 0x68ff, 0xc09a, 0x21, 0 + .dw 0x6940, 0xc09a, 0x697f, 0xc09a, 0x21, 0 + .dw 0x69c0, 0xc09a, 0x69ff, 0xc09a, 0x21, 0 + .dw 0x6a40, 0xc09a, 0x6a7f, 0xc09a, 0x21, 0 + .dw 0x6ac0, 0xc09a, 0x6aff, 0xc09a, 0x21, 0 + .dw 0x6b40, 0xc09a, 0x6b7f, 0xc09a, 0x21, 0 + .dw 0x6bc0, 0xc09a, 0x6bff, 0xc09a, 0x21, 0 + .dw 0x6c40, 0xc09a, 0x6c7f, 0xc09a, 0x21, 0 + .dw 0x6cc0, 0xc09a, 0x6cff, 0xc09a, 0x21, 0 + .dw 0x6d40, 0xc09a, 0x6d7f, 0xc09a, 0x21, 0 + .dw 0x6dc0, 0xc09a, 0x6dff, 0xc09a, 0x21, 0 + .dw 0x6e40, 0xc09a, 0x6e7f, 0xc09a, 0x21, 0 + .dw 0x6ec0, 0xc09a, 0x6eff, 0xc09a, 0x21, 0 + .dw 0x6f40, 0xc09a, 0x6f7f, 0xc09a, 0x21, 0 + .dw 0x6fc0, 0xc09a, 0x6fff, 0xc09a, 0x21, 0 + .dw 0x7040, 0xc09a, 0x707f, 0xc09a, 0x21, 0 + .dw 0x70c0, 0xc09a, 0x70ff, 0xc09a, 0x21, 0 + .dw 0x7140, 0xc09a, 0x717f, 0xc09a, 0x21, 0 + .dw 0x71c0, 0xc09a, 0x71ff, 0xc09a, 0x21, 0 + .dw 0x7240, 0xc09a, 0x727f, 0xc09a, 0x21, 0 + .dw 0x72c0, 0xc09a, 0x72ff, 0xc09a, 0x21, 0 + .dw 0x7340, 0xc09a, 0x737f, 0xc09a, 0x21, 0 + .dw 0x73c0, 0xc09a, 0x73ff, 0xc09a, 0x21, 0 + .dw 0x7440, 0xc09a, 0x747f, 0xc09a, 0x21, 0 + .dw 0x74c0, 0xc09a, 0x74ff, 0xc09a, 0x21, 0 + .dw 0x7540, 0xc09a, 0x757f, 0xc09a, 0x21, 0 + .dw 0x75c0, 0xc09a, 0x75ff, 0xc09a, 0x21, 0 + .dw 0x7640, 0xc09a, 0x767f, 0xc09a, 0x21, 0 + .dw 0x76c0, 0xc09a, 0x76ff, 0xc09a, 0x21, 0 + .dw 0x7740, 0xc09a, 0x777f, 0xc09a, 0x21, 0 + .dw 0x77c0, 0xc09a, 0x77ff, 0xc09a, 0x21, 0 + .dw 0x7840, 0xc09a, 0x787f, 0xc09a, 0x21, 0 + .dw 0x78c0, 0xc09a, 0x78ff, 0xc09a, 0x21, 0 + .dw 0x7940, 0xc09a, 0x797f, 0xc09a, 0x21, 0 + .dw 0x79c0, 0xc09a, 0x9fff, 0xc09a, 0x21, 0 + .dw 0xa040, 0xc09a, 0xa07f, 0xc09a, 0x21, 0 + .dw 0xa0c0, 0xc09a, 0xa0ff, 0xc09a, 0x21, 0 + .dw 0xa140, 0xc09a, 0xa17f, 0xc09a, 0x21, 0 + .dw 0xa1c0, 0xc09a, 0xa1ff, 0xc09a, 0x21, 0 + .dw 0xa240, 0xc09a, 0xa27f, 0xc09a, 0x21, 0 + .dw 0xa2c0, 0xc09a, 0xa2ff, 0xc09a, 0x21, 0 + .dw 0xa340, 0xc09a, 0xa37f, 0xc09a, 0x21, 0 + .dw 0xa3c0, 0xc09a, 0xa3ff, 0xc09a, 0x21, 0 + .dw 0xa440, 0xc09a, 0xa47f, 0xc09a, 0x21, 0 + .dw 0xa4c0, 0xc09a, 0xa4ff, 0xc09a, 0x21, 0 + .dw 0xa540, 0xc09a, 0xa57f, 0xc09a, 0x21, 0 + .dw 0xa5c0, 0xc09a, 0xa5ff, 0xc09a, 0x21, 0 + .dw 0xa640, 0xc09a, 0xa67f, 0xc09a, 0x21, 0 + .dw 0xa6c0, 0xc09a, 0xa6ff, 0xc09a, 0x21, 0 + .dw 0xa740, 0xc09a, 0xa77f, 0xc09a, 0x21, 0 + .dw 0xa7c0, 0xc09a, 0xa7ff, 0xc09a, 0x21, 0 + .dw 0xa840, 0xc09a, 0xa87f, 0xc09a, 0x21, 0 + .dw 0xa8c0, 0xc09a, 0xa8ff, 0xc09a, 0x21, 0 + .dw 0xa940, 0xc09a, 0xa97f, 0xc09a, 0x21, 0 + .dw 0xa9c0, 0xc09a, 0xa9ff, 0xc09a, 0x21, 0 + .dw 0xaa40, 0xc09a, 0xaa7f, 0xc09a, 0x21, 0 + .dw 0xaac0, 0xc09a, 0xaaff, 0xc09a, 0x21, 0 + .dw 0xab40, 0xc09a, 0xab7f, 0xc09a, 0x21, 0 + .dw 0xabc0, 0xc09a, 0xabff, 0xc09a, 0x21, 0 + .dw 0xac40, 0xc09a, 0xac7f, 0xc09a, 0x21, 0 + .dw 0xacc0, 0xc09a, 0xacff, 0xc09a, 0x21, 0 + .dw 0xad40, 0xc09a, 0xad7f, 0xc09a, 0x21, 0 + .dw 0xadc0, 0xc09a, 0xadff, 0xc09a, 0x21, 0 + .dw 0xae40, 0xc09a, 0xae7f, 0xc09a, 0x21, 0 + .dw 0xaec0, 0xc09a, 0xaeff, 0xc09a, 0x21, 0 + .dw 0xaf40, 0xc09a, 0xaf7f, 0xc09a, 0x21, 0 + .dw 0xafc0, 0xc09a, 0xafff, 0xc09a, 0x21, 0 + .dw 0xb040, 0xc09a, 0xb07f, 0xc09a, 0x21, 0 + .dw 0xb0c0, 0xc09a, 0xb0ff, 0xc09a, 0x21, 0 + .dw 0xb140, 0xc09a, 0xb17f, 0xc09a, 0x21, 0 + .dw 0xb1c0, 0xc09a, 0xb1ff, 0xc09a, 0x21, 0 + .dw 0xb240, 0xc09a, 0xb27f, 0xc09a, 0x21, 0 + .dw 0xb2c0, 0xc09a, 0xb2ff, 0xc09a, 0x21, 0 + .dw 0xb340, 0xc09a, 0xb37f, 0xc09a, 0x21, 0 + .dw 0xb3c0, 0xc09a, 0xb3ff, 0xc09a, 0x21, 0 + .dw 0xb440, 0xc09a, 0xb47f, 0xc09a, 0x21, 0 + .dw 0xb4c0, 0xc09a, 0xb4ff, 0xc09a, 0x21, 0 + .dw 0xb540, 0xc09a, 0xb57f, 0xc09a, 0x21, 0 + .dw 0xb5c0, 0xc09a, 0xb5ff, 0xc09a, 0x21, 0 + .dw 0xb640, 0xc09a, 0xb67f, 0xc09a, 0x21, 0 + .dw 0xb6c0, 0xc09a, 0xb6ff, 0xc09a, 0x21, 0 + .dw 0xb740, 0xc09a, 0xb77f, 0xc09a, 0x21, 0 + .dw 0xb7c0, 0xc09a, 0xb7ff, 0xc09a, 0x21, 0 + .dw 0xb840, 0xc09a, 0xb87f, 0xc09a, 0x21, 0 + .dw 0xb8c0, 0xc09a, 0xb8ff, 0xc09a, 0x21, 0 + .dw 0xb940, 0xc09a, 0xb97f, 0xc09a, 0x21, 0 + .dw 0xb9c0, 0xc09a, 0xdfff, 0xc09a, 0x21, 0 + .dw 0xe040, 0xc09a, 0xe07f, 0xc09a, 0x21, 0 + .dw 0xe0c0, 0xc09a, 0xe0ff, 0xc09a, 0x21, 0 + .dw 0xe140, 0xc09a, 0xe17f, 0xc09a, 0x21, 0 + .dw 0xe1c0, 0xc09a, 0xe1ff, 0xc09a, 0x21, 0 + .dw 0xe240, 0xc09a, 0xe27f, 0xc09a, 0x21, 0 + .dw 0xe2c0, 0xc09a, 0xe2ff, 0xc09a, 0x21, 0 + .dw 0xe340, 0xc09a, 0xe37f, 0xc09a, 0x21, 0 + .dw 0xe3c0, 0xc09a, 0xe3ff, 0xc09a, 0x21, 0 + .dw 0xe440, 0xc09a, 0xe47f, 0xc09a, 0x21, 0 + .dw 0xe4c0, 0xc09a, 0xe4ff, 0xc09a, 0x21, 0 + .dw 0xe540, 0xc09a, 0xe57f, 0xc09a, 0x21, 0 + .dw 0xe5c0, 0xc09a, 0xe5ff, 0xc09a, 0x21, 0 + .dw 0xe640, 0xc09a, 0xe67f, 0xc09a, 0x21, 0 + .dw 0xe6c0, 0xc09a, 0xe6ff, 0xc09a, 0x21, 0 + .dw 0xe740, 0xc09a, 0xe77f, 0xc09a, 0x21, 0 + .dw 0xe7c0, 0xc09a, 0xe7ff, 0xc09a, 0x21, 0 + .dw 0xe840, 0xc09a, 0xe87f, 0xc09a, 0x21, 0 + .dw 0xe8c0, 0xc09a, 0xe8ff, 0xc09a, 0x21, 0 + .dw 0xe940, 0xc09a, 0xe97f, 0xc09a, 0x21, 0 + .dw 0xe9c0, 0xc09a, 0xe9ff, 0xc09a, 0x21, 0 + .dw 0xea40, 0xc09a, 0xea7f, 0xc09a, 0x21, 0 + .dw 0xeac0, 0xc09a, 0xeaff, 0xc09a, 0x21, 0 + .dw 0xeb40, 0xc09a, 0xeb7f, 0xc09a, 0x21, 0 + .dw 0xebc0, 0xc09a, 0xebff, 0xc09a, 0x21, 0 + .dw 0xec40, 0xc09a, 0xec7f, 0xc09a, 0x21, 0 + .dw 0xecc0, 0xc09a, 0xecff, 0xc09a, 0x21, 0 + .dw 0xed40, 0xc09a, 0xed7f, 0xc09a, 0x21, 0 + .dw 0xedc0, 0xc09a, 0xedff, 0xc09a, 0x21, 0 + .dw 0xee40, 0xc09a, 0xee7f, 0xc09a, 0x21, 0 + .dw 0xeec0, 0xc09a, 0xeeff, 0xc09a, 0x21, 0 + .dw 0xef40, 0xc09a, 0xef7f, 0xc09a, 0x21, 0 + .dw 0xefc0, 0xc09a, 0xefff, 0xc09a, 0x21, 0 + .dw 0xf040, 0xc09a, 0xf07f, 0xc09a, 0x21, 0 + .dw 0xf0c0, 0xc09a, 0xf0ff, 0xc09a, 0x21, 0 + .dw 0xf140, 0xc09a, 0xf17f, 0xc09a, 0x21, 0 + .dw 0xf1c0, 0xc09a, 0xf1ff, 0xc09a, 0x21, 0 + .dw 0xf240, 0xc09a, 0xf27f, 0xc09a, 0x21, 0 + .dw 0xf2c0, 0xc09a, 0xf2ff, 0xc09a, 0x21, 0 + .dw 0xf340, 0xc09a, 0xf37f, 0xc09a, 0x21, 0 + .dw 0xf3c0, 0xc09a, 0xf3ff, 0xc09a, 0x21, 0 + .dw 0xf440, 0xc09a, 0xf47f, 0xc09a, 0x21, 0 + .dw 0xf4c0, 0xc09a, 0xf4ff, 0xc09a, 0x21, 0 + .dw 0xf540, 0xc09a, 0xf57f, 0xc09a, 0x21, 0 + .dw 0xf5c0, 0xc09a, 0xf5ff, 0xc09a, 0x21, 0 + .dw 0xf640, 0xc09a, 0xf67f, 0xc09a, 0x21, 0 + .dw 0xf6c0, 0xc09a, 0xf6ff, 0xc09a, 0x21, 0 + .dw 0xf740, 0xc09a, 0xf77f, 0xc09a, 0x21, 0 + .dw 0xf7c0, 0xc09a, 0xf7ff, 0xc09a, 0x21, 0 + .dw 0xf840, 0xc09a, 0xf87f, 0xc09a, 0x21, 0 + .dw 0xf8c0, 0xc09a, 0xf8ff, 0xc09a, 0x21, 0 + .dw 0xf940, 0xc09a, 0xf97f, 0xc09a, 0x21, 0 + .dw 0xf9c0, 0xc09a, 0xffff, 0xc09b, 0x21, 0 + .dw 0x0040, 0xc09c, 0x007f, 0xc09c, 0x21, 0 + .dw 0x00c0, 0xc09c, 0x00ff, 0xc09c, 0x21, 0 + .dw 0x0140, 0xc09c, 0x017f, 0xc09c, 0x21, 0 + .dw 0x01c0, 0xc09c, 0x01ff, 0xc09c, 0x21, 0 + .dw 0x0240, 0xc09c, 0x027f, 0xc09c, 0x21, 0 + .dw 0x02c0, 0xc09c, 0x02ff, 0xc09c, 0x21, 0 + .dw 0x0340, 0xc09c, 0x037f, 0xc09c, 0x21, 0 + .dw 0x03c0, 0xc09c, 0x03ff, 0xc09c, 0x21, 0 + .dw 0x0440, 0xc09c, 0x047f, 0xc09c, 0x21, 0 + .dw 0x04c0, 0xc09c, 0x04ff, 0xc09c, 0x21, 0 + .dw 0x0540, 0xc09c, 0x057f, 0xc09c, 0x21, 0 + .dw 0x05c0, 0xc09c, 0x05ff, 0xc09c, 0x21, 0 + .dw 0x0640, 0xc09c, 0x067f, 0xc09c, 0x21, 0 + .dw 0x06c0, 0xc09c, 0x06ff, 0xc09c, 0x21, 0 + .dw 0x0740, 0xc09c, 0x077f, 0xc09c, 0x21, 0 + .dw 0x07c0, 0xc09c, 0x07ff, 0xc09c, 0x21, 0 + .dw 0x0840, 0xc09c, 0x087f, 0xc09c, 0x21, 0 + .dw 0x08c0, 0xc09c, 0x08ff, 0xc09c, 0x21, 0 + .dw 0x0940, 0xc09c, 0x097f, 0xc09c, 0x21, 0 + .dw 0x09c0, 0xc09c, 0x09ff, 0xc09c, 0x21, 0 + .dw 0x0a40, 0xc09c, 0x0a7f, 0xc09c, 0x21, 0 + .dw 0x0ac0, 0xc09c, 0x0aff, 0xc09c, 0x21, 0 + .dw 0x0b40, 0xc09c, 0x0b7f, 0xc09c, 0x21, 0 + .dw 0x0bc0, 0xc09c, 0x0bff, 0xc09c, 0x21, 0 + .dw 0x0c40, 0xc09c, 0x0c7f, 0xc09c, 0x21, 0 + .dw 0x0cc0, 0xc09c, 0x0cff, 0xc09c, 0x21, 0 + .dw 0x0d40, 0xc09c, 0x0d7f, 0xc09c, 0x21, 0 + .dw 0x0dc0, 0xc09c, 0x0dff, 0xc09c, 0x21, 0 + .dw 0x0e40, 0xc09c, 0x0e7f, 0xc09c, 0x21, 0 + .dw 0x0ec0, 0xc09c, 0x0eff, 0xc09c, 0x21, 0 + .dw 0x0f40, 0xc09c, 0x0f7f, 0xc09c, 0x21, 0 + .dw 0x0fc0, 0xc09c, 0x0fff, 0xc09c, 0x21, 0 + .dw 0x1040, 0xc09c, 0x107f, 0xc09c, 0x21, 0 + .dw 0x10c0, 0xc09c, 0x10ff, 0xc09c, 0x21, 0 + .dw 0x1140, 0xc09c, 0x117f, 0xc09c, 0x21, 0 + .dw 0x11c0, 0xc09c, 0x11ff, 0xc09c, 0x21, 0 + .dw 0x1240, 0xc09c, 0x127f, 0xc09c, 0x21, 0 + .dw 0x12c0, 0xc09c, 0x12ff, 0xc09c, 0x21, 0 + .dw 0x1340, 0xc09c, 0x137f, 0xc09c, 0x21, 0 + .dw 0x13c0, 0xc09c, 0x13ff, 0xc09c, 0x21, 0 + .dw 0x1440, 0xc09c, 0x147f, 0xc09c, 0x21, 0 + .dw 0x14c0, 0xc09c, 0x14ff, 0xc09c, 0x21, 0 + .dw 0x1540, 0xc09c, 0x157f, 0xc09c, 0x21, 0 + .dw 0x15c0, 0xc09c, 0x15ff, 0xc09c, 0x21, 0 + .dw 0x1640, 0xc09c, 0x167f, 0xc09c, 0x21, 0 + .dw 0x16c0, 0xc09c, 0x16ff, 0xc09c, 0x21, 0 + .dw 0x1740, 0xc09c, 0x177f, 0xc09c, 0x21, 0 + .dw 0x17c0, 0xc09c, 0x17ff, 0xc09c, 0x21, 0 + .dw 0x1840, 0xc09c, 0x187f, 0xc09c, 0x21, 0 + .dw 0x18c0, 0xc09c, 0x18ff, 0xc09c, 0x21, 0 + .dw 0x1940, 0xc09c, 0x197f, 0xc09c, 0x21, 0 + .dw 0x19c0, 0xc09c, 0x1fff, 0xc09c, 0x21, 0 + .dw 0x2040, 0xc09c, 0x207f, 0xc09c, 0x21, 0 + .dw 0x20c0, 0xc09c, 0x20ff, 0xc09c, 0x21, 0 + .dw 0x2140, 0xc09c, 0x217f, 0xc09c, 0x21, 0 + .dw 0x21c0, 0xc09c, 0x21ff, 0xc09c, 0x21, 0 + .dw 0x2240, 0xc09c, 0x227f, 0xc09c, 0x21, 0 + .dw 0x22c0, 0xc09c, 0x22ff, 0xc09c, 0x21, 0 + .dw 0x2340, 0xc09c, 0x237f, 0xc09c, 0x21, 0 + .dw 0x23c0, 0xc09c, 0x23ff, 0xc09c, 0x21, 0 + .dw 0x2440, 0xc09c, 0x247f, 0xc09c, 0x21, 0 + .dw 0x24c0, 0xc09c, 0x24ff, 0xc09c, 0x21, 0 + .dw 0x2540, 0xc09c, 0x257f, 0xc09c, 0x21, 0 + .dw 0x25c0, 0xc09c, 0x25ff, 0xc09c, 0x21, 0 + .dw 0x2640, 0xc09c, 0x267f, 0xc09c, 0x21, 0 + .dw 0x26c0, 0xc09c, 0x26ff, 0xc09c, 0x21, 0 + .dw 0x2740, 0xc09c, 0x277f, 0xc09c, 0x21, 0 + .dw 0x27c0, 0xc09c, 0x27ff, 0xc09c, 0x21, 0 + .dw 0x2840, 0xc09c, 0x287f, 0xc09c, 0x21, 0 + .dw 0x28c0, 0xc09c, 0x28ff, 0xc09c, 0x21, 0 + .dw 0x2940, 0xc09c, 0x297f, 0xc09c, 0x21, 0 + .dw 0x29c0, 0xc09c, 0x29ff, 0xc09c, 0x21, 0 + .dw 0x2a40, 0xc09c, 0x2a7f, 0xc09c, 0x21, 0 + .dw 0x2ac0, 0xc09c, 0x2aff, 0xc09c, 0x21, 0 + .dw 0x2b40, 0xc09c, 0x2b7f, 0xc09c, 0x21, 0 + .dw 0x2bc0, 0xc09c, 0x2bff, 0xc09c, 0x21, 0 + .dw 0x2c40, 0xc09c, 0x2c7f, 0xc09c, 0x21, 0 + .dw 0x2cc0, 0xc09c, 0x2cff, 0xc09c, 0x21, 0 + .dw 0x2d40, 0xc09c, 0x2d7f, 0xc09c, 0x21, 0 + .dw 0x2dc0, 0xc09c, 0x2dff, 0xc09c, 0x21, 0 + .dw 0x2e40, 0xc09c, 0x2e7f, 0xc09c, 0x21, 0 + .dw 0x2ec0, 0xc09c, 0x2eff, 0xc09c, 0x21, 0 + .dw 0x2f40, 0xc09c, 0x2f7f, 0xc09c, 0x21, 0 + .dw 0x2fc0, 0xc09c, 0x2fff, 0xc09c, 0x21, 0 + .dw 0x3040, 0xc09c, 0x307f, 0xc09c, 0x21, 0 + .dw 0x30c0, 0xc09c, 0x30ff, 0xc09c, 0x21, 0 + .dw 0x3140, 0xc09c, 0x317f, 0xc09c, 0x21, 0 + .dw 0x31c0, 0xc09c, 0x31ff, 0xc09c, 0x21, 0 + .dw 0x3240, 0xc09c, 0x327f, 0xc09c, 0x21, 0 + .dw 0x32c0, 0xc09c, 0x32ff, 0xc09c, 0x21, 0 + .dw 0x3340, 0xc09c, 0x337f, 0xc09c, 0x21, 0 + .dw 0x33c0, 0xc09c, 0x33ff, 0xc09c, 0x21, 0 + .dw 0x3440, 0xc09c, 0x347f, 0xc09c, 0x21, 0 + .dw 0x34c0, 0xc09c, 0x34ff, 0xc09c, 0x21, 0 + .dw 0x3540, 0xc09c, 0x357f, 0xc09c, 0x21, 0 + .dw 0x35c0, 0xc09c, 0x35ff, 0xc09c, 0x21, 0 + .dw 0x3640, 0xc09c, 0x367f, 0xc09c, 0x21, 0 + .dw 0x36c0, 0xc09c, 0x36ff, 0xc09c, 0x21, 0 + .dw 0x3740, 0xc09c, 0x377f, 0xc09c, 0x21, 0 + .dw 0x37c0, 0xc09c, 0x37ff, 0xc09c, 0x21, 0 + .dw 0x3840, 0xc09c, 0x387f, 0xc09c, 0x21, 0 + .dw 0x38c0, 0xc09c, 0x38ff, 0xc09c, 0x21, 0 + .dw 0x3940, 0xc09c, 0x397f, 0xc09c, 0x21, 0 + .dw 0x39c0, 0xc09c, 0x3fff, 0xc09c, 0x21, 0 + .dw 0x4040, 0xc09c, 0x407f, 0xc09c, 0x21, 0 + .dw 0x40c0, 0xc09c, 0x40ff, 0xc09c, 0x21, 0 + .dw 0x4140, 0xc09c, 0x417f, 0xc09c, 0x21, 0 + .dw 0x41c0, 0xc09c, 0x41ff, 0xc09c, 0x21, 0 + .dw 0x4240, 0xc09c, 0x427f, 0xc09c, 0x21, 0 + .dw 0x42c0, 0xc09c, 0x42ff, 0xc09c, 0x21, 0 + .dw 0x4340, 0xc09c, 0x437f, 0xc09c, 0x21, 0 + .dw 0x43c0, 0xc09c, 0x43ff, 0xc09c, 0x21, 0 + .dw 0x4440, 0xc09c, 0x447f, 0xc09c, 0x21, 0 + .dw 0x44c0, 0xc09c, 0x44ff, 0xc09c, 0x21, 0 + .dw 0x4540, 0xc09c, 0x457f, 0xc09c, 0x21, 0 + .dw 0x45c0, 0xc09c, 0x45ff, 0xc09c, 0x21, 0 + .dw 0x4640, 0xc09c, 0x467f, 0xc09c, 0x21, 0 + .dw 0x46c0, 0xc09c, 0x46ff, 0xc09c, 0x21, 0 + .dw 0x4740, 0xc09c, 0x477f, 0xc09c, 0x21, 0 + .dw 0x47c0, 0xc09c, 0x47ff, 0xc09c, 0x21, 0 + .dw 0x4840, 0xc09c, 0x487f, 0xc09c, 0x21, 0 + .dw 0x48c0, 0xc09c, 0x48ff, 0xc09c, 0x21, 0 + .dw 0x4940, 0xc09c, 0x497f, 0xc09c, 0x21, 0 + .dw 0x49c0, 0xc09c, 0x49ff, 0xc09c, 0x21, 0 + .dw 0x4a40, 0xc09c, 0x4a7f, 0xc09c, 0x21, 0 + .dw 0x4ac0, 0xc09c, 0x4aff, 0xc09c, 0x21, 0 + .dw 0x4b40, 0xc09c, 0x4b7f, 0xc09c, 0x21, 0 + .dw 0x4bc0, 0xc09c, 0x4bff, 0xc09c, 0x21, 0 + .dw 0x4c40, 0xc09c, 0x4c7f, 0xc09c, 0x21, 0 + .dw 0x4cc0, 0xc09c, 0x4cff, 0xc09c, 0x21, 0 + .dw 0x4d40, 0xc09c, 0x4d7f, 0xc09c, 0x21, 0 + .dw 0x4dc0, 0xc09c, 0x4dff, 0xc09c, 0x21, 0 + .dw 0x4e40, 0xc09c, 0x4e7f, 0xc09c, 0x21, 0 + .dw 0x4ec0, 0xc09c, 0x4eff, 0xc09c, 0x21, 0 + .dw 0x4f40, 0xc09c, 0x4f7f, 0xc09c, 0x21, 0 + .dw 0x4fc0, 0xc09c, 0x4fff, 0xc09c, 0x21, 0 + .dw 0x5040, 0xc09c, 0x507f, 0xc09c, 0x21, 0 + .dw 0x50c0, 0xc09c, 0x50ff, 0xc09c, 0x21, 0 + .dw 0x5140, 0xc09c, 0x517f, 0xc09c, 0x21, 0 + .dw 0x51c0, 0xc09c, 0x51ff, 0xc09c, 0x21, 0 + .dw 0x5240, 0xc09c, 0x527f, 0xc09c, 0x21, 0 + .dw 0x52c0, 0xc09c, 0x52ff, 0xc09c, 0x21, 0 + .dw 0x5340, 0xc09c, 0x537f, 0xc09c, 0x21, 0 + .dw 0x53c0, 0xc09c, 0x53ff, 0xc09c, 0x21, 0 + .dw 0x5440, 0xc09c, 0x547f, 0xc09c, 0x21, 0 + .dw 0x54c0, 0xc09c, 0x54ff, 0xc09c, 0x21, 0 + .dw 0x5540, 0xc09c, 0x557f, 0xc09c, 0x21, 0 + .dw 0x55c0, 0xc09c, 0x55ff, 0xc09c, 0x21, 0 + .dw 0x5640, 0xc09c, 0x567f, 0xc09c, 0x21, 0 + .dw 0x56c0, 0xc09c, 0x56ff, 0xc09c, 0x21, 0 + .dw 0x5740, 0xc09c, 0x577f, 0xc09c, 0x21, 0 + .dw 0x57c0, 0xc09c, 0x57ff, 0xc09c, 0x21, 0 + .dw 0x5840, 0xc09c, 0x587f, 0xc09c, 0x21, 0 + .dw 0x58c0, 0xc09c, 0x58ff, 0xc09c, 0x21, 0 + .dw 0x5940, 0xc09c, 0x597f, 0xc09c, 0x21, 0 + .dw 0x59c0, 0xc09c, 0x5fff, 0xc09c, 0x21, 0 + .dw 0x6040, 0xc09c, 0x607f, 0xc09c, 0x21, 0 + .dw 0x60c0, 0xc09c, 0x60ff, 0xc09c, 0x21, 0 + .dw 0x6140, 0xc09c, 0x617f, 0xc09c, 0x21, 0 + .dw 0x61c0, 0xc09c, 0x61ff, 0xc09c, 0x21, 0 + .dw 0x6240, 0xc09c, 0x627f, 0xc09c, 0x21, 0 + .dw 0x62c0, 0xc09c, 0x62ff, 0xc09c, 0x21, 0 + .dw 0x6340, 0xc09c, 0x637f, 0xc09c, 0x21, 0 + .dw 0x63c0, 0xc09c, 0x63ff, 0xc09c, 0x21, 0 + .dw 0x6440, 0xc09c, 0x647f, 0xc09c, 0x21, 0 + .dw 0x64c0, 0xc09c, 0x64ff, 0xc09c, 0x21, 0 + .dw 0x6540, 0xc09c, 0x657f, 0xc09c, 0x21, 0 + .dw 0x65c0, 0xc09c, 0x65ff, 0xc09c, 0x21, 0 + .dw 0x6640, 0xc09c, 0x667f, 0xc09c, 0x21, 0 + .dw 0x66c0, 0xc09c, 0x66ff, 0xc09c, 0x21, 0 + .dw 0x6740, 0xc09c, 0x677f, 0xc09c, 0x21, 0 + .dw 0x67c0, 0xc09c, 0x67ff, 0xc09c, 0x21, 0 + .dw 0x6840, 0xc09c, 0x687f, 0xc09c, 0x21, 0 + .dw 0x68c0, 0xc09c, 0x68ff, 0xc09c, 0x21, 0 + .dw 0x6940, 0xc09c, 0x697f, 0xc09c, 0x21, 0 + .dw 0x69c0, 0xc09c, 0x69ff, 0xc09c, 0x21, 0 + .dw 0x6a40, 0xc09c, 0x6a7f, 0xc09c, 0x21, 0 + .dw 0x6ac0, 0xc09c, 0x6aff, 0xc09c, 0x21, 0 + .dw 0x6b40, 0xc09c, 0x6b7f, 0xc09c, 0x21, 0 + .dw 0x6bc0, 0xc09c, 0x6bff, 0xc09c, 0x21, 0 + .dw 0x6c40, 0xc09c, 0x6c7f, 0xc09c, 0x21, 0 + .dw 0x6cc0, 0xc09c, 0x6cff, 0xc09c, 0x21, 0 + .dw 0x6d40, 0xc09c, 0x6d7f, 0xc09c, 0x21, 0 + .dw 0x6dc0, 0xc09c, 0x6dff, 0xc09c, 0x21, 0 + .dw 0x6e40, 0xc09c, 0x6e7f, 0xc09c, 0x21, 0 + .dw 0x6ec0, 0xc09c, 0x6eff, 0xc09c, 0x21, 0 + .dw 0x6f40, 0xc09c, 0x6f7f, 0xc09c, 0x21, 0 + .dw 0x6fc0, 0xc09c, 0x6fff, 0xc09c, 0x21, 0 + .dw 0x7040, 0xc09c, 0x707f, 0xc09c, 0x21, 0 + .dw 0x70c0, 0xc09c, 0x70ff, 0xc09c, 0x21, 0 + .dw 0x7140, 0xc09c, 0x717f, 0xc09c, 0x21, 0 + .dw 0x71c0, 0xc09c, 0x71ff, 0xc09c, 0x21, 0 + .dw 0x7240, 0xc09c, 0x727f, 0xc09c, 0x21, 0 + .dw 0x72c0, 0xc09c, 0x72ff, 0xc09c, 0x21, 0 + .dw 0x7340, 0xc09c, 0x737f, 0xc09c, 0x21, 0 + .dw 0x73c0, 0xc09c, 0x73ff, 0xc09c, 0x21, 0 + .dw 0x7440, 0xc09c, 0x747f, 0xc09c, 0x21, 0 + .dw 0x74c0, 0xc09c, 0x74ff, 0xc09c, 0x21, 0 + .dw 0x7540, 0xc09c, 0x757f, 0xc09c, 0x21, 0 + .dw 0x75c0, 0xc09c, 0x75ff, 0xc09c, 0x21, 0 + .dw 0x7640, 0xc09c, 0x767f, 0xc09c, 0x21, 0 + .dw 0x76c0, 0xc09c, 0x76ff, 0xc09c, 0x21, 0 + .dw 0x7740, 0xc09c, 0x777f, 0xc09c, 0x21, 0 + .dw 0x77c0, 0xc09c, 0x77ff, 0xc09c, 0x21, 0 + .dw 0x7840, 0xc09c, 0x787f, 0xc09c, 0x21, 0 + .dw 0x78c0, 0xc09c, 0x78ff, 0xc09c, 0x21, 0 + .dw 0x7940, 0xc09c, 0x797f, 0xc09c, 0x21, 0 + .dw 0x79c0, 0xc09c, 0x7fff, 0xc09c, 0x21, 0 + .dw 0x8040, 0xc09c, 0x807f, 0xc09c, 0x21, 0 + .dw 0x80c0, 0xc09c, 0x80ff, 0xc09c, 0x21, 0 + .dw 0x8140, 0xc09c, 0x817f, 0xc09c, 0x21, 0 + .dw 0x81c0, 0xc09c, 0x81ff, 0xc09c, 0x21, 0 + .dw 0x8240, 0xc09c, 0x827f, 0xc09c, 0x21, 0 + .dw 0x82c0, 0xc09c, 0x82ff, 0xc09c, 0x21, 0 + .dw 0x8340, 0xc09c, 0x837f, 0xc09c, 0x21, 0 + .dw 0x83c0, 0xc09c, 0x83ff, 0xc09c, 0x21, 0 + .dw 0x8440, 0xc09c, 0x847f, 0xc09c, 0x21, 0 + .dw 0x84c0, 0xc09c, 0x84ff, 0xc09c, 0x21, 0 + .dw 0x8540, 0xc09c, 0x857f, 0xc09c, 0x21, 0 + .dw 0x85c0, 0xc09c, 0x85ff, 0xc09c, 0x21, 0 + .dw 0x8640, 0xc09c, 0x867f, 0xc09c, 0x21, 0 + .dw 0x86c0, 0xc09c, 0x86ff, 0xc09c, 0x21, 0 + .dw 0x8740, 0xc09c, 0x877f, 0xc09c, 0x21, 0 + .dw 0x87c0, 0xc09c, 0x87ff, 0xc09c, 0x21, 0 + .dw 0x8840, 0xc09c, 0x887f, 0xc09c, 0x21, 0 + .dw 0x88c0, 0xc09c, 0x88ff, 0xc09c, 0x21, 0 + .dw 0x8940, 0xc09c, 0x897f, 0xc09c, 0x21, 0 + .dw 0x89c0, 0xc09c, 0x89ff, 0xc09c, 0x21, 0 + .dw 0x8a40, 0xc09c, 0x8a7f, 0xc09c, 0x21, 0 + .dw 0x8ac0, 0xc09c, 0x8aff, 0xc09c, 0x21, 0 + .dw 0x8b40, 0xc09c, 0x8b7f, 0xc09c, 0x21, 0 + .dw 0x8bc0, 0xc09c, 0x8bff, 0xc09c, 0x21, 0 + .dw 0x8c40, 0xc09c, 0x8c7f, 0xc09c, 0x21, 0 + .dw 0x8cc0, 0xc09c, 0x8cff, 0xc09c, 0x21, 0 + .dw 0x8d40, 0xc09c, 0x8d7f, 0xc09c, 0x21, 0 + .dw 0x8dc0, 0xc09c, 0x8dff, 0xc09c, 0x21, 0 + .dw 0x8e40, 0xc09c, 0x8e7f, 0xc09c, 0x21, 0 + .dw 0x8ec0, 0xc09c, 0x8eff, 0xc09c, 0x21, 0 + .dw 0x8f40, 0xc09c, 0x8f7f, 0xc09c, 0x21, 0 + .dw 0x8fc0, 0xc09c, 0x8fff, 0xc09c, 0x21, 0 + .dw 0x9040, 0xc09c, 0x907f, 0xc09c, 0x21, 0 + .dw 0x90c0, 0xc09c, 0x90ff, 0xc09c, 0x21, 0 + .dw 0x9140, 0xc09c, 0x917f, 0xc09c, 0x21, 0 + .dw 0x91c0, 0xc09c, 0x91ff, 0xc09c, 0x21, 0 + .dw 0x9240, 0xc09c, 0x927f, 0xc09c, 0x21, 0 + .dw 0x92c0, 0xc09c, 0x92ff, 0xc09c, 0x21, 0 + .dw 0x9340, 0xc09c, 0x937f, 0xc09c, 0x21, 0 + .dw 0x93c0, 0xc09c, 0x93ff, 0xc09c, 0x21, 0 + .dw 0x9440, 0xc09c, 0x947f, 0xc09c, 0x21, 0 + .dw 0x94c0, 0xc09c, 0x94ff, 0xc09c, 0x21, 0 + .dw 0x9540, 0xc09c, 0x957f, 0xc09c, 0x21, 0 + .dw 0x95c0, 0xc09c, 0x95ff, 0xc09c, 0x21, 0 + .dw 0x9640, 0xc09c, 0x967f, 0xc09c, 0x21, 0 + .dw 0x96c0, 0xc09c, 0x96ff, 0xc09c, 0x21, 0 + .dw 0x9740, 0xc09c, 0x977f, 0xc09c, 0x21, 0 + .dw 0x97c0, 0xc09c, 0x97ff, 0xc09c, 0x21, 0 + .dw 0x9840, 0xc09c, 0x987f, 0xc09c, 0x21, 0 + .dw 0x98c0, 0xc09c, 0x98ff, 0xc09c, 0x21, 0 + .dw 0x9940, 0xc09c, 0x997f, 0xc09c, 0x21, 0 + .dw 0x99c0, 0xc09c, 0x9fff, 0xc09c, 0x21, 0 + .dw 0xa040, 0xc09c, 0xa07f, 0xc09c, 0x21, 0 + .dw 0xa0c0, 0xc09c, 0xa0ff, 0xc09c, 0x21, 0 + .dw 0xa140, 0xc09c, 0xa17f, 0xc09c, 0x21, 0 + .dw 0xa1c0, 0xc09c, 0xa1ff, 0xc09c, 0x21, 0 + .dw 0xa240, 0xc09c, 0xa27f, 0xc09c, 0x21, 0 + .dw 0xa2c0, 0xc09c, 0xa2ff, 0xc09c, 0x21, 0 + .dw 0xa340, 0xc09c, 0xa37f, 0xc09c, 0x21, 0 + .dw 0xa3c0, 0xc09c, 0xa3ff, 0xc09c, 0x21, 0 + .dw 0xa440, 0xc09c, 0xa47f, 0xc09c, 0x21, 0 + .dw 0xa4c0, 0xc09c, 0xa4ff, 0xc09c, 0x21, 0 + .dw 0xa540, 0xc09c, 0xa57f, 0xc09c, 0x21, 0 + .dw 0xa5c0, 0xc09c, 0xa5ff, 0xc09c, 0x21, 0 + .dw 0xa640, 0xc09c, 0xa67f, 0xc09c, 0x21, 0 + .dw 0xa6c0, 0xc09c, 0xa6ff, 0xc09c, 0x21, 0 + .dw 0xa740, 0xc09c, 0xa77f, 0xc09c, 0x21, 0 + .dw 0xa7c0, 0xc09c, 0xa7ff, 0xc09c, 0x21, 0 + .dw 0xa840, 0xc09c, 0xa87f, 0xc09c, 0x21, 0 + .dw 0xa8c0, 0xc09c, 0xa8ff, 0xc09c, 0x21, 0 + .dw 0xa940, 0xc09c, 0xa97f, 0xc09c, 0x21, 0 + .dw 0xa9c0, 0xc09c, 0xa9ff, 0xc09c, 0x21, 0 + .dw 0xaa40, 0xc09c, 0xaa7f, 0xc09c, 0x21, 0 + .dw 0xaac0, 0xc09c, 0xaaff, 0xc09c, 0x21, 0 + .dw 0xab40, 0xc09c, 0xab7f, 0xc09c, 0x21, 0 + .dw 0xabc0, 0xc09c, 0xabff, 0xc09c, 0x21, 0 + .dw 0xac40, 0xc09c, 0xac7f, 0xc09c, 0x21, 0 + .dw 0xacc0, 0xc09c, 0xacff, 0xc09c, 0x21, 0 + .dw 0xad40, 0xc09c, 0xad7f, 0xc09c, 0x21, 0 + .dw 0xadc0, 0xc09c, 0xadff, 0xc09c, 0x21, 0 + .dw 0xae40, 0xc09c, 0xae7f, 0xc09c, 0x21, 0 + .dw 0xaec0, 0xc09c, 0xaeff, 0xc09c, 0x21, 0 + .dw 0xaf40, 0xc09c, 0xaf7f, 0xc09c, 0x21, 0 + .dw 0xafc0, 0xc09c, 0xafff, 0xc09c, 0x21, 0 + .dw 0xb040, 0xc09c, 0xb07f, 0xc09c, 0x21, 0 + .dw 0xb0c0, 0xc09c, 0xb0ff, 0xc09c, 0x21, 0 + .dw 0xb140, 0xc09c, 0xb17f, 0xc09c, 0x21, 0 + .dw 0xb1c0, 0xc09c, 0xb1ff, 0xc09c, 0x21, 0 + .dw 0xb240, 0xc09c, 0xb27f, 0xc09c, 0x21, 0 + .dw 0xb2c0, 0xc09c, 0xb2ff, 0xc09c, 0x21, 0 + .dw 0xb340, 0xc09c, 0xb37f, 0xc09c, 0x21, 0 + .dw 0xb3c0, 0xc09c, 0xb3ff, 0xc09c, 0x21, 0 + .dw 0xb440, 0xc09c, 0xb47f, 0xc09c, 0x21, 0 + .dw 0xb4c0, 0xc09c, 0xb4ff, 0xc09c, 0x21, 0 + .dw 0xb540, 0xc09c, 0xb57f, 0xc09c, 0x21, 0 + .dw 0xb5c0, 0xc09c, 0xb5ff, 0xc09c, 0x21, 0 + .dw 0xb640, 0xc09c, 0xb67f, 0xc09c, 0x21, 0 + .dw 0xb6c0, 0xc09c, 0xb6ff, 0xc09c, 0x21, 0 + .dw 0xb740, 0xc09c, 0xb77f, 0xc09c, 0x21, 0 + .dw 0xb7c0, 0xc09c, 0xb7ff, 0xc09c, 0x21, 0 + .dw 0xb840, 0xc09c, 0xb87f, 0xc09c, 0x21, 0 + .dw 0xb8c0, 0xc09c, 0xb8ff, 0xc09c, 0x21, 0 + .dw 0xb940, 0xc09c, 0xb97f, 0xc09c, 0x21, 0 + .dw 0xb9c0, 0xc09c, 0xbfff, 0xc09c, 0x21, 0 + .dw 0xc040, 0xc09c, 0xc07f, 0xc09c, 0x21, 0 + .dw 0xc0c0, 0xc09c, 0xc0ff, 0xc09c, 0x21, 0 + .dw 0xc140, 0xc09c, 0xc17f, 0xc09c, 0x21, 0 + .dw 0xc1c0, 0xc09c, 0xc1ff, 0xc09c, 0x21, 0 + .dw 0xc240, 0xc09c, 0xc27f, 0xc09c, 0x21, 0 + .dw 0xc2c0, 0xc09c, 0xc2ff, 0xc09c, 0x21, 0 + .dw 0xc340, 0xc09c, 0xc37f, 0xc09c, 0x21, 0 + .dw 0xc3c0, 0xc09c, 0xc3ff, 0xc09c, 0x21, 0 + .dw 0xc440, 0xc09c, 0xc47f, 0xc09c, 0x21, 0 + .dw 0xc4c0, 0xc09c, 0xc4ff, 0xc09c, 0x21, 0 + .dw 0xc540, 0xc09c, 0xc57f, 0xc09c, 0x21, 0 + .dw 0xc5c0, 0xc09c, 0xc5ff, 0xc09c, 0x21, 0 + .dw 0xc640, 0xc09c, 0xc67f, 0xc09c, 0x21, 0 + .dw 0xc6c0, 0xc09c, 0xc6ff, 0xc09c, 0x21, 0 + .dw 0xc740, 0xc09c, 0xc77f, 0xc09c, 0x21, 0 + .dw 0xc7c0, 0xc09c, 0xc7ff, 0xc09c, 0x21, 0 + .dw 0xc840, 0xc09c, 0xc87f, 0xc09c, 0x21, 0 + .dw 0xc8c0, 0xc09c, 0xc8ff, 0xc09c, 0x21, 0 + .dw 0xc940, 0xc09c, 0xc97f, 0xc09c, 0x21, 0 + .dw 0xc9c0, 0xc09c, 0xc9ff, 0xc09c, 0x21, 0 + .dw 0xca40, 0xc09c, 0xca7f, 0xc09c, 0x21, 0 + .dw 0xcac0, 0xc09c, 0xcaff, 0xc09c, 0x21, 0 + .dw 0xcb40, 0xc09c, 0xcb7f, 0xc09c, 0x21, 0 + .dw 0xcbc0, 0xc09c, 0xcbff, 0xc09c, 0x21, 0 + .dw 0xcc40, 0xc09c, 0xcc7f, 0xc09c, 0x21, 0 + .dw 0xccc0, 0xc09c, 0xccff, 0xc09c, 0x21, 0 + .dw 0xcd40, 0xc09c, 0xcd7f, 0xc09c, 0x21, 0 + .dw 0xcdc0, 0xc09c, 0xcdff, 0xc09c, 0x21, 0 + .dw 0xce40, 0xc09c, 0xce7f, 0xc09c, 0x21, 0 + .dw 0xcec0, 0xc09c, 0xceff, 0xc09c, 0x21, 0 + .dw 0xcf40, 0xc09c, 0xcf7f, 0xc09c, 0x21, 0 + .dw 0xcfc0, 0xc09c, 0xcfff, 0xc09c, 0x21, 0 + .dw 0xd040, 0xc09c, 0xd07f, 0xc09c, 0x21, 0 + .dw 0xd0c0, 0xc09c, 0xd0ff, 0xc09c, 0x21, 0 + .dw 0xd140, 0xc09c, 0xd17f, 0xc09c, 0x21, 0 + .dw 0xd1c0, 0xc09c, 0xd1ff, 0xc09c, 0x21, 0 + .dw 0xd240, 0xc09c, 0xd27f, 0xc09c, 0x21, 0 + .dw 0xd2c0, 0xc09c, 0xd2ff, 0xc09c, 0x21, 0 + .dw 0xd340, 0xc09c, 0xd37f, 0xc09c, 0x21, 0 + .dw 0xd3c0, 0xc09c, 0xd3ff, 0xc09c, 0x21, 0 + .dw 0xd440, 0xc09c, 0xd47f, 0xc09c, 0x21, 0 + .dw 0xd4c0, 0xc09c, 0xd4ff, 0xc09c, 0x21, 0 + .dw 0xd540, 0xc09c, 0xd57f, 0xc09c, 0x21, 0 + .dw 0xd5c0, 0xc09c, 0xd5ff, 0xc09c, 0x21, 0 + .dw 0xd640, 0xc09c, 0xd67f, 0xc09c, 0x21, 0 + .dw 0xd6c0, 0xc09c, 0xd6ff, 0xc09c, 0x21, 0 + .dw 0xd740, 0xc09c, 0xd77f, 0xc09c, 0x21, 0 + .dw 0xd7c0, 0xc09c, 0xd7ff, 0xc09c, 0x21, 0 + .dw 0xd840, 0xc09c, 0xd87f, 0xc09c, 0x21, 0 + .dw 0xd8c0, 0xc09c, 0xd8ff, 0xc09c, 0x21, 0 + .dw 0xd940, 0xc09c, 0xd97f, 0xc09c, 0x21, 0 + .dw 0xd9c0, 0xc09c, 0xdfff, 0xc09c, 0x21, 0 + .dw 0xe040, 0xc09c, 0xe07f, 0xc09c, 0x21, 0 + .dw 0xe0c0, 0xc09c, 0xe0ff, 0xc09c, 0x21, 0 + .dw 0xe140, 0xc09c, 0xe17f, 0xc09c, 0x21, 0 + .dw 0xe1c0, 0xc09c, 0xe1ff, 0xc09c, 0x21, 0 + .dw 0xe240, 0xc09c, 0xe27f, 0xc09c, 0x21, 0 + .dw 0xe2c0, 0xc09c, 0xe2ff, 0xc09c, 0x21, 0 + .dw 0xe340, 0xc09c, 0xe37f, 0xc09c, 0x21, 0 + .dw 0xe3c0, 0xc09c, 0xe3ff, 0xc09c, 0x21, 0 + .dw 0xe440, 0xc09c, 0xe47f, 0xc09c, 0x21, 0 + .dw 0xe4c0, 0xc09c, 0xe4ff, 0xc09c, 0x21, 0 + .dw 0xe540, 0xc09c, 0xe57f, 0xc09c, 0x21, 0 + .dw 0xe5c0, 0xc09c, 0xe5ff, 0xc09c, 0x21, 0 + .dw 0xe640, 0xc09c, 0xe67f, 0xc09c, 0x21, 0 + .dw 0xe6c0, 0xc09c, 0xe6ff, 0xc09c, 0x21, 0 + .dw 0xe740, 0xc09c, 0xe77f, 0xc09c, 0x21, 0 + .dw 0xe7c0, 0xc09c, 0xe7ff, 0xc09c, 0x21, 0 + .dw 0xe840, 0xc09c, 0xe87f, 0xc09c, 0x21, 0 + .dw 0xe8c0, 0xc09c, 0xe8ff, 0xc09c, 0x21, 0 + .dw 0xe940, 0xc09c, 0xe97f, 0xc09c, 0x21, 0 + .dw 0xe9c0, 0xc09c, 0xe9ff, 0xc09c, 0x21, 0 + .dw 0xea40, 0xc09c, 0xea7f, 0xc09c, 0x21, 0 + .dw 0xeac0, 0xc09c, 0xeaff, 0xc09c, 0x21, 0 + .dw 0xeb40, 0xc09c, 0xeb7f, 0xc09c, 0x21, 0 + .dw 0xebc0, 0xc09c, 0xebff, 0xc09c, 0x21, 0 + .dw 0xec40, 0xc09c, 0xec7f, 0xc09c, 0x21, 0 + .dw 0xecc0, 0xc09c, 0xecff, 0xc09c, 0x21, 0 + .dw 0xed40, 0xc09c, 0xed7f, 0xc09c, 0x21, 0 + .dw 0xedc0, 0xc09c, 0xedff, 0xc09c, 0x21, 0 + .dw 0xee40, 0xc09c, 0xee7f, 0xc09c, 0x21, 0 + .dw 0xeec0, 0xc09c, 0xeeff, 0xc09c, 0x21, 0 + .dw 0xef40, 0xc09c, 0xef7f, 0xc09c, 0x21, 0 + .dw 0xefc0, 0xc09c, 0xefff, 0xc09c, 0x21, 0 + .dw 0xf040, 0xc09c, 0xf07f, 0xc09c, 0x21, 0 + .dw 0xf0c0, 0xc09c, 0xf0ff, 0xc09c, 0x21, 0 + .dw 0xf140, 0xc09c, 0xf17f, 0xc09c, 0x21, 0 + .dw 0xf1c0, 0xc09c, 0xf1ff, 0xc09c, 0x21, 0 + .dw 0xf240, 0xc09c, 0xf27f, 0xc09c, 0x21, 0 + .dw 0xf2c0, 0xc09c, 0xf2ff, 0xc09c, 0x21, 0 + .dw 0xf340, 0xc09c, 0xf37f, 0xc09c, 0x21, 0 + .dw 0xf3c0, 0xc09c, 0xf3ff, 0xc09c, 0x21, 0 + .dw 0xf440, 0xc09c, 0xf47f, 0xc09c, 0x21, 0 + .dw 0xf4c0, 0xc09c, 0xf4ff, 0xc09c, 0x21, 0 + .dw 0xf540, 0xc09c, 0xf57f, 0xc09c, 0x21, 0 + .dw 0xf5c0, 0xc09c, 0xf5ff, 0xc09c, 0x21, 0 + .dw 0xf640, 0xc09c, 0xf67f, 0xc09c, 0x21, 0 + .dw 0xf6c0, 0xc09c, 0xf6ff, 0xc09c, 0x21, 0 + .dw 0xf740, 0xc09c, 0xf77f, 0xc09c, 0x21, 0 + .dw 0xf7c0, 0xc09c, 0xf7ff, 0xc09c, 0x21, 0 + .dw 0xf840, 0xc09c, 0xf87f, 0xc09c, 0x21, 0 + .dw 0xf8c0, 0xc09c, 0xf8ff, 0xc09c, 0x21, 0 + .dw 0xf940, 0xc09c, 0xf97f, 0xc09c, 0x21, 0 + .dw 0xf9c0, 0xc09c, 0xffff, 0xc09c, 0x21, 0 + .dw 0x0040, 0xc09d, 0x007f, 0xc09d, 0x21, 0 + .dw 0x00c0, 0xc09d, 0x00ff, 0xc09d, 0x21, 0 + .dw 0x0140, 0xc09d, 0x017f, 0xc09d, 0x21, 0 + .dw 0x01c0, 0xc09d, 0x01ff, 0xc09d, 0x21, 0 + .dw 0x0240, 0xc09d, 0x027f, 0xc09d, 0x21, 0 + .dw 0x02c0, 0xc09d, 0x02ff, 0xc09d, 0x21, 0 + .dw 0x0340, 0xc09d, 0x037f, 0xc09d, 0x21, 0 + .dw 0x03c0, 0xc09d, 0x03ff, 0xc09d, 0x21, 0 + .dw 0x0440, 0xc09d, 0x047f, 0xc09d, 0x21, 0 + .dw 0x04c0, 0xc09d, 0x04ff, 0xc09d, 0x21, 0 + .dw 0x0540, 0xc09d, 0x057f, 0xc09d, 0x21, 0 + .dw 0x05c0, 0xc09d, 0x05ff, 0xc09d, 0x21, 0 + .dw 0x0640, 0xc09d, 0x067f, 0xc09d, 0x21, 0 + .dw 0x06c0, 0xc09d, 0x06ff, 0xc09d, 0x21, 0 + .dw 0x0740, 0xc09d, 0x077f, 0xc09d, 0x21, 0 + .dw 0x07c0, 0xc09d, 0x07ff, 0xc09d, 0x21, 0 + .dw 0x0840, 0xc09d, 0x087f, 0xc09d, 0x21, 0 + .dw 0x08c0, 0xc09d, 0x08ff, 0xc09d, 0x21, 0 + .dw 0x0940, 0xc09d, 0x097f, 0xc09d, 0x21, 0 + .dw 0x09c0, 0xc09d, 0x09ff, 0xc09d, 0x21, 0 + .dw 0x0a40, 0xc09d, 0x0a7f, 0xc09d, 0x21, 0 + .dw 0x0ac0, 0xc09d, 0x0aff, 0xc09d, 0x21, 0 + .dw 0x0b40, 0xc09d, 0x0b7f, 0xc09d, 0x21, 0 + .dw 0x0bc0, 0xc09d, 0x0bff, 0xc09d, 0x21, 0 + .dw 0x0c40, 0xc09d, 0x0c7f, 0xc09d, 0x21, 0 + .dw 0x0cc0, 0xc09d, 0x0cff, 0xc09d, 0x21, 0 + .dw 0x0d40, 0xc09d, 0x0d7f, 0xc09d, 0x21, 0 + .dw 0x0dc0, 0xc09d, 0x0dff, 0xc09d, 0x21, 0 + .dw 0x0e40, 0xc09d, 0x0e7f, 0xc09d, 0x21, 0 + .dw 0x0ec0, 0xc09d, 0x0eff, 0xc09d, 0x21, 0 + .dw 0x0f40, 0xc09d, 0x0f7f, 0xc09d, 0x21, 0 + .dw 0x0fc0, 0xc09d, 0x0fff, 0xc09d, 0x21, 0 + .dw 0x1040, 0xc09d, 0x107f, 0xc09d, 0x21, 0 + .dw 0x10c0, 0xc09d, 0x10ff, 0xc09d, 0x21, 0 + .dw 0x1140, 0xc09d, 0x117f, 0xc09d, 0x21, 0 + .dw 0x11c0, 0xc09d, 0x11ff, 0xc09d, 0x21, 0 + .dw 0x1240, 0xc09d, 0x127f, 0xc09d, 0x21, 0 + .dw 0x12c0, 0xc09d, 0x12ff, 0xc09d, 0x21, 0 + .dw 0x1340, 0xc09d, 0x137f, 0xc09d, 0x21, 0 + .dw 0x13c0, 0xc09d, 0x13ff, 0xc09d, 0x21, 0 + .dw 0x1440, 0xc09d, 0x147f, 0xc09d, 0x21, 0 + .dw 0x14c0, 0xc09d, 0x14ff, 0xc09d, 0x21, 0 + .dw 0x1540, 0xc09d, 0x157f, 0xc09d, 0x21, 0 + .dw 0x15c0, 0xc09d, 0x15ff, 0xc09d, 0x21, 0 + .dw 0x1640, 0xc09d, 0x167f, 0xc09d, 0x21, 0 + .dw 0x16c0, 0xc09d, 0x16ff, 0xc09d, 0x21, 0 + .dw 0x1740, 0xc09d, 0x177f, 0xc09d, 0x21, 0 + .dw 0x17c0, 0xc09d, 0x17ff, 0xc09d, 0x21, 0 + .dw 0x1840, 0xc09d, 0x187f, 0xc09d, 0x21, 0 + .dw 0x18c0, 0xc09d, 0x18ff, 0xc09d, 0x21, 0 + .dw 0x1940, 0xc09d, 0x197f, 0xc09d, 0x21, 0 + .dw 0x19c0, 0xc09d, 0x1fff, 0xc09d, 0x21, 0 + .dw 0x2040, 0xc09d, 0x207f, 0xc09d, 0x21, 0 + .dw 0x20c0, 0xc09d, 0x20ff, 0xc09d, 0x21, 0 + .dw 0x2140, 0xc09d, 0x217f, 0xc09d, 0x21, 0 + .dw 0x21c0, 0xc09d, 0x21ff, 0xc09d, 0x21, 0 + .dw 0x2240, 0xc09d, 0x227f, 0xc09d, 0x21, 0 + .dw 0x22c0, 0xc09d, 0x22ff, 0xc09d, 0x21, 0 + .dw 0x2340, 0xc09d, 0x237f, 0xc09d, 0x21, 0 + .dw 0x23c0, 0xc09d, 0x23ff, 0xc09d, 0x21, 0 + .dw 0x2440, 0xc09d, 0x247f, 0xc09d, 0x21, 0 + .dw 0x24c0, 0xc09d, 0x24ff, 0xc09d, 0x21, 0 + .dw 0x2540, 0xc09d, 0x257f, 0xc09d, 0x21, 0 + .dw 0x25c0, 0xc09d, 0x25ff, 0xc09d, 0x21, 0 + .dw 0x2640, 0xc09d, 0x267f, 0xc09d, 0x21, 0 + .dw 0x26c0, 0xc09d, 0x26ff, 0xc09d, 0x21, 0 + .dw 0x2740, 0xc09d, 0x277f, 0xc09d, 0x21, 0 + .dw 0x27c0, 0xc09d, 0x27ff, 0xc09d, 0x21, 0 + .dw 0x2840, 0xc09d, 0x287f, 0xc09d, 0x21, 0 + .dw 0x28c0, 0xc09d, 0x28ff, 0xc09d, 0x21, 0 + .dw 0x2940, 0xc09d, 0x297f, 0xc09d, 0x21, 0 + .dw 0x29c0, 0xc09d, 0x29ff, 0xc09d, 0x21, 0 + .dw 0x2a40, 0xc09d, 0x2a7f, 0xc09d, 0x21, 0 + .dw 0x2ac0, 0xc09d, 0x2aff, 0xc09d, 0x21, 0 + .dw 0x2b40, 0xc09d, 0x2b7f, 0xc09d, 0x21, 0 + .dw 0x2bc0, 0xc09d, 0x2bff, 0xc09d, 0x21, 0 + .dw 0x2c40, 0xc09d, 0x2c7f, 0xc09d, 0x21, 0 + .dw 0x2cc0, 0xc09d, 0x2cff, 0xc09d, 0x21, 0 + .dw 0x2d40, 0xc09d, 0x2d7f, 0xc09d, 0x21, 0 + .dw 0x2dc0, 0xc09d, 0x2dff, 0xc09d, 0x21, 0 + .dw 0x2e40, 0xc09d, 0x2e7f, 0xc09d, 0x21, 0 + .dw 0x2ec0, 0xc09d, 0x2eff, 0xc09d, 0x21, 0 + .dw 0x2f40, 0xc09d, 0x2f7f, 0xc09d, 0x21, 0 + .dw 0x2fc0, 0xc09d, 0x2fff, 0xc09d, 0x21, 0 + .dw 0x3040, 0xc09d, 0x307f, 0xc09d, 0x21, 0 + .dw 0x30c0, 0xc09d, 0x30ff, 0xc09d, 0x21, 0 + .dw 0x3140, 0xc09d, 0x317f, 0xc09d, 0x21, 0 + .dw 0x31c0, 0xc09d, 0x31ff, 0xc09d, 0x21, 0 + .dw 0x3240, 0xc09d, 0x327f, 0xc09d, 0x21, 0 + .dw 0x32c0, 0xc09d, 0x32ff, 0xc09d, 0x21, 0 + .dw 0x3340, 0xc09d, 0x337f, 0xc09d, 0x21, 0 + .dw 0x33c0, 0xc09d, 0x33ff, 0xc09d, 0x21, 0 + .dw 0x3440, 0xc09d, 0x347f, 0xc09d, 0x21, 0 + .dw 0x34c0, 0xc09d, 0x34ff, 0xc09d, 0x21, 0 + .dw 0x3540, 0xc09d, 0x357f, 0xc09d, 0x21, 0 + .dw 0x35c0, 0xc09d, 0x35ff, 0xc09d, 0x21, 0 + .dw 0x3640, 0xc09d, 0x367f, 0xc09d, 0x21, 0 + .dw 0x36c0, 0xc09d, 0x36ff, 0xc09d, 0x21, 0 + .dw 0x3740, 0xc09d, 0x377f, 0xc09d, 0x21, 0 + .dw 0x37c0, 0xc09d, 0x37ff, 0xc09d, 0x21, 0 + .dw 0x3840, 0xc09d, 0x387f, 0xc09d, 0x21, 0 + .dw 0x38c0, 0xc09d, 0x38ff, 0xc09d, 0x21, 0 + .dw 0x3940, 0xc09d, 0x397f, 0xc09d, 0x21, 0 + .dw 0x39c0, 0xc09d, 0x3fff, 0xc09d, 0x21, 0 + .dw 0x4040, 0xc09d, 0x407f, 0xc09d, 0x21, 0 + .dw 0x40c0, 0xc09d, 0x40ff, 0xc09d, 0x21, 0 + .dw 0x4140, 0xc09d, 0x417f, 0xc09d, 0x21, 0 + .dw 0x41c0, 0xc09d, 0x41ff, 0xc09d, 0x21, 0 + .dw 0x4240, 0xc09d, 0x427f, 0xc09d, 0x21, 0 + .dw 0x42c0, 0xc09d, 0x42ff, 0xc09d, 0x21, 0 + .dw 0x4340, 0xc09d, 0x437f, 0xc09d, 0x21, 0 + .dw 0x43c0, 0xc09d, 0x43ff, 0xc09d, 0x21, 0 + .dw 0x4440, 0xc09d, 0x447f, 0xc09d, 0x21, 0 + .dw 0x44c0, 0xc09d, 0x44ff, 0xc09d, 0x21, 0 + .dw 0x4540, 0xc09d, 0x457f, 0xc09d, 0x21, 0 + .dw 0x45c0, 0xc09d, 0x45ff, 0xc09d, 0x21, 0 + .dw 0x4640, 0xc09d, 0x467f, 0xc09d, 0x21, 0 + .dw 0x46c0, 0xc09d, 0x46ff, 0xc09d, 0x21, 0 + .dw 0x4740, 0xc09d, 0x477f, 0xc09d, 0x21, 0 + .dw 0x47c0, 0xc09d, 0x47ff, 0xc09d, 0x21, 0 + .dw 0x4840, 0xc09d, 0x487f, 0xc09d, 0x21, 0 + .dw 0x48c0, 0xc09d, 0x48ff, 0xc09d, 0x21, 0 + .dw 0x4940, 0xc09d, 0x497f, 0xc09d, 0x21, 0 + .dw 0x49c0, 0xc09d, 0x49ff, 0xc09d, 0x21, 0 + .dw 0x4a40, 0xc09d, 0x4a7f, 0xc09d, 0x21, 0 + .dw 0x4ac0, 0xc09d, 0x4aff, 0xc09d, 0x21, 0 + .dw 0x4b40, 0xc09d, 0x4b7f, 0xc09d, 0x21, 0 + .dw 0x4bc0, 0xc09d, 0x4bff, 0xc09d, 0x21, 0 + .dw 0x4c40, 0xc09d, 0x4c7f, 0xc09d, 0x21, 0 + .dw 0x4cc0, 0xc09d, 0x4cff, 0xc09d, 0x21, 0 + .dw 0x4d40, 0xc09d, 0x4d7f, 0xc09d, 0x21, 0 + .dw 0x4dc0, 0xc09d, 0x4dff, 0xc09d, 0x21, 0 + .dw 0x4e40, 0xc09d, 0x4e7f, 0xc09d, 0x21, 0 + .dw 0x4ec0, 0xc09d, 0x4eff, 0xc09d, 0x21, 0 + .dw 0x4f40, 0xc09d, 0x4f7f, 0xc09d, 0x21, 0 + .dw 0x4fc0, 0xc09d, 0x4fff, 0xc09d, 0x21, 0 + .dw 0x5040, 0xc09d, 0x507f, 0xc09d, 0x21, 0 + .dw 0x50c0, 0xc09d, 0x50ff, 0xc09d, 0x21, 0 + .dw 0x5140, 0xc09d, 0x517f, 0xc09d, 0x21, 0 + .dw 0x51c0, 0xc09d, 0x51ff, 0xc09d, 0x21, 0 + .dw 0x5240, 0xc09d, 0x527f, 0xc09d, 0x21, 0 + .dw 0x52c0, 0xc09d, 0x52ff, 0xc09d, 0x21, 0 + .dw 0x5340, 0xc09d, 0x537f, 0xc09d, 0x21, 0 + .dw 0x53c0, 0xc09d, 0x53ff, 0xc09d, 0x21, 0 + .dw 0x5440, 0xc09d, 0x547f, 0xc09d, 0x21, 0 + .dw 0x54c0, 0xc09d, 0x54ff, 0xc09d, 0x21, 0 + .dw 0x5540, 0xc09d, 0x557f, 0xc09d, 0x21, 0 + .dw 0x55c0, 0xc09d, 0x55ff, 0xc09d, 0x21, 0 + .dw 0x5640, 0xc09d, 0x567f, 0xc09d, 0x21, 0 + .dw 0x56c0, 0xc09d, 0x56ff, 0xc09d, 0x21, 0 + .dw 0x5740, 0xc09d, 0x577f, 0xc09d, 0x21, 0 + .dw 0x57c0, 0xc09d, 0x57ff, 0xc09d, 0x21, 0 + .dw 0x5840, 0xc09d, 0x587f, 0xc09d, 0x21, 0 + .dw 0x58c0, 0xc09d, 0x58ff, 0xc09d, 0x21, 0 + .dw 0x5940, 0xc09d, 0x597f, 0xc09d, 0x21, 0 + .dw 0x59c0, 0xc09d, 0x5fff, 0xc09d, 0x21, 0 + .dw 0x6040, 0xc09d, 0x607f, 0xc09d, 0x21, 0 + .dw 0x60c0, 0xc09d, 0x60ff, 0xc09d, 0x21, 0 + .dw 0x6140, 0xc09d, 0x617f, 0xc09d, 0x21, 0 + .dw 0x61c0, 0xc09d, 0x61ff, 0xc09d, 0x21, 0 + .dw 0x6240, 0xc09d, 0x627f, 0xc09d, 0x21, 0 + .dw 0x62c0, 0xc09d, 0x62ff, 0xc09d, 0x21, 0 + .dw 0x6340, 0xc09d, 0x637f, 0xc09d, 0x21, 0 + .dw 0x63c0, 0xc09d, 0x63ff, 0xc09d, 0x21, 0 + .dw 0x6440, 0xc09d, 0x647f, 0xc09d, 0x21, 0 + .dw 0x64c0, 0xc09d, 0x64ff, 0xc09d, 0x21, 0 + .dw 0x6540, 0xc09d, 0x657f, 0xc09d, 0x21, 0 + .dw 0x65c0, 0xc09d, 0x65ff, 0xc09d, 0x21, 0 + .dw 0x6640, 0xc09d, 0x667f, 0xc09d, 0x21, 0 + .dw 0x66c0, 0xc09d, 0x66ff, 0xc09d, 0x21, 0 + .dw 0x6740, 0xc09d, 0x677f, 0xc09d, 0x21, 0 + .dw 0x67c0, 0xc09d, 0x67ff, 0xc09d, 0x21, 0 + .dw 0x6840, 0xc09d, 0x687f, 0xc09d, 0x21, 0 + .dw 0x68c0, 0xc09d, 0x68ff, 0xc09d, 0x21, 0 + .dw 0x6940, 0xc09d, 0x697f, 0xc09d, 0x21, 0 + .dw 0x69c0, 0xc09d, 0x69ff, 0xc09d, 0x21, 0 + .dw 0x6a40, 0xc09d, 0x6a7f, 0xc09d, 0x21, 0 + .dw 0x6ac0, 0xc09d, 0x6aff, 0xc09d, 0x21, 0 + .dw 0x6b40, 0xc09d, 0x6b7f, 0xc09d, 0x21, 0 + .dw 0x6bc0, 0xc09d, 0x6bff, 0xc09d, 0x21, 0 + .dw 0x6c40, 0xc09d, 0x6c7f, 0xc09d, 0x21, 0 + .dw 0x6cc0, 0xc09d, 0x6cff, 0xc09d, 0x21, 0 + .dw 0x6d40, 0xc09d, 0x6d7f, 0xc09d, 0x21, 0 + .dw 0x6dc0, 0xc09d, 0x6dff, 0xc09d, 0x21, 0 + .dw 0x6e40, 0xc09d, 0x6e7f, 0xc09d, 0x21, 0 + .dw 0x6ec0, 0xc09d, 0x6eff, 0xc09d, 0x21, 0 + .dw 0x6f40, 0xc09d, 0x6f7f, 0xc09d, 0x21, 0 + .dw 0x6fc0, 0xc09d, 0x6fff, 0xc09d, 0x21, 0 + .dw 0x7040, 0xc09d, 0x707f, 0xc09d, 0x21, 0 + .dw 0x70c0, 0xc09d, 0x70ff, 0xc09d, 0x21, 0 + .dw 0x7140, 0xc09d, 0x717f, 0xc09d, 0x21, 0 + .dw 0x71c0, 0xc09d, 0x71ff, 0xc09d, 0x21, 0 + .dw 0x7240, 0xc09d, 0x727f, 0xc09d, 0x21, 0 + .dw 0x72c0, 0xc09d, 0x72ff, 0xc09d, 0x21, 0 + .dw 0x7340, 0xc09d, 0x737f, 0xc09d, 0x21, 0 + .dw 0x73c0, 0xc09d, 0x73ff, 0xc09d, 0x21, 0 + .dw 0x7440, 0xc09d, 0x747f, 0xc09d, 0x21, 0 + .dw 0x74c0, 0xc09d, 0x74ff, 0xc09d, 0x21, 0 + .dw 0x7540, 0xc09d, 0x757f, 0xc09d, 0x21, 0 + .dw 0x75c0, 0xc09d, 0x75ff, 0xc09d, 0x21, 0 + .dw 0x7640, 0xc09d, 0x767f, 0xc09d, 0x21, 0 + .dw 0x76c0, 0xc09d, 0x76ff, 0xc09d, 0x21, 0 + .dw 0x7740, 0xc09d, 0x777f, 0xc09d, 0x21, 0 + .dw 0x77c0, 0xc09d, 0x77ff, 0xc09d, 0x21, 0 + .dw 0x7840, 0xc09d, 0x787f, 0xc09d, 0x21, 0 + .dw 0x78c0, 0xc09d, 0x78ff, 0xc09d, 0x21, 0 + .dw 0x7940, 0xc09d, 0x797f, 0xc09d, 0x21, 0 + .dw 0x79c0, 0xc09d, 0x7fff, 0xc09d, 0x21, 0 + .dw 0x8040, 0xc09d, 0x807f, 0xc09d, 0x21, 0 + .dw 0x80c0, 0xc09d, 0x80ff, 0xc09d, 0x21, 0 + .dw 0x8140, 0xc09d, 0x817f, 0xc09d, 0x21, 0 + .dw 0x81c0, 0xc09d, 0x81ff, 0xc09d, 0x21, 0 + .dw 0x8240, 0xc09d, 0x827f, 0xc09d, 0x21, 0 + .dw 0x82c0, 0xc09d, 0x82ff, 0xc09d, 0x21, 0 + .dw 0x8340, 0xc09d, 0x837f, 0xc09d, 0x21, 0 + .dw 0x83c0, 0xc09d, 0x83ff, 0xc09d, 0x21, 0 + .dw 0x8440, 0xc09d, 0x847f, 0xc09d, 0x21, 0 + .dw 0x84c0, 0xc09d, 0x84ff, 0xc09d, 0x21, 0 + .dw 0x8540, 0xc09d, 0x857f, 0xc09d, 0x21, 0 + .dw 0x85c0, 0xc09d, 0x85ff, 0xc09d, 0x21, 0 + .dw 0x8640, 0xc09d, 0x867f, 0xc09d, 0x21, 0 + .dw 0x86c0, 0xc09d, 0x86ff, 0xc09d, 0x21, 0 + .dw 0x8740, 0xc09d, 0x877f, 0xc09d, 0x21, 0 + .dw 0x87c0, 0xc09d, 0x87ff, 0xc09d, 0x21, 0 + .dw 0x8840, 0xc09d, 0x887f, 0xc09d, 0x21, 0 + .dw 0x88c0, 0xc09d, 0x88ff, 0xc09d, 0x21, 0 + .dw 0x8940, 0xc09d, 0x897f, 0xc09d, 0x21, 0 + .dw 0x89c0, 0xc09d, 0x89ff, 0xc09d, 0x21, 0 + .dw 0x8a40, 0xc09d, 0x8a7f, 0xc09d, 0x21, 0 + .dw 0x8ac0, 0xc09d, 0x8aff, 0xc09d, 0x21, 0 + .dw 0x8b40, 0xc09d, 0x8b7f, 0xc09d, 0x21, 0 + .dw 0x8bc0, 0xc09d, 0x8bff, 0xc09d, 0x21, 0 + .dw 0x8c40, 0xc09d, 0x8c7f, 0xc09d, 0x21, 0 + .dw 0x8cc0, 0xc09d, 0x8cff, 0xc09d, 0x21, 0 + .dw 0x8d40, 0xc09d, 0x8d7f, 0xc09d, 0x21, 0 + .dw 0x8dc0, 0xc09d, 0x8dff, 0xc09d, 0x21, 0 + .dw 0x8e40, 0xc09d, 0x8e7f, 0xc09d, 0x21, 0 + .dw 0x8ec0, 0xc09d, 0x8eff, 0xc09d, 0x21, 0 + .dw 0x8f40, 0xc09d, 0x8f7f, 0xc09d, 0x21, 0 + .dw 0x8fc0, 0xc09d, 0x8fff, 0xc09d, 0x21, 0 + .dw 0x9040, 0xc09d, 0x907f, 0xc09d, 0x21, 0 + .dw 0x90c0, 0xc09d, 0x90ff, 0xc09d, 0x21, 0 + .dw 0x9140, 0xc09d, 0x917f, 0xc09d, 0x21, 0 + .dw 0x91c0, 0xc09d, 0x91ff, 0xc09d, 0x21, 0 + .dw 0x9240, 0xc09d, 0x927f, 0xc09d, 0x21, 0 + .dw 0x92c0, 0xc09d, 0x92ff, 0xc09d, 0x21, 0 + .dw 0x9340, 0xc09d, 0x937f, 0xc09d, 0x21, 0 + .dw 0x93c0, 0xc09d, 0x93ff, 0xc09d, 0x21, 0 + .dw 0x9440, 0xc09d, 0x947f, 0xc09d, 0x21, 0 + .dw 0x94c0, 0xc09d, 0x94ff, 0xc09d, 0x21, 0 + .dw 0x9540, 0xc09d, 0x957f, 0xc09d, 0x21, 0 + .dw 0x95c0, 0xc09d, 0x95ff, 0xc09d, 0x21, 0 + .dw 0x9640, 0xc09d, 0x967f, 0xc09d, 0x21, 0 + .dw 0x96c0, 0xc09d, 0x96ff, 0xc09d, 0x21, 0 + .dw 0x9740, 0xc09d, 0x977f, 0xc09d, 0x21, 0 + .dw 0x97c0, 0xc09d, 0x97ff, 0xc09d, 0x21, 0 + .dw 0x9840, 0xc09d, 0x987f, 0xc09d, 0x21, 0 + .dw 0x98c0, 0xc09d, 0x98ff, 0xc09d, 0x21, 0 + .dw 0x9940, 0xc09d, 0x997f, 0xc09d, 0x21, 0 + .dw 0x99c0, 0xc09d, 0x9fff, 0xc09d, 0x21, 0 + .dw 0xa040, 0xc09d, 0xa07f, 0xc09d, 0x21, 0 + .dw 0xa0c0, 0xc09d, 0xa0ff, 0xc09d, 0x21, 0 + .dw 0xa140, 0xc09d, 0xa17f, 0xc09d, 0x21, 0 + .dw 0xa1c0, 0xc09d, 0xa1ff, 0xc09d, 0x21, 0 + .dw 0xa240, 0xc09d, 0xa27f, 0xc09d, 0x21, 0 + .dw 0xa2c0, 0xc09d, 0xa2ff, 0xc09d, 0x21, 0 + .dw 0xa340, 0xc09d, 0xa37f, 0xc09d, 0x21, 0 + .dw 0xa3c0, 0xc09d, 0xa3ff, 0xc09d, 0x21, 0 + .dw 0xa440, 0xc09d, 0xa47f, 0xc09d, 0x21, 0 + .dw 0xa4c0, 0xc09d, 0xa4ff, 0xc09d, 0x21, 0 + .dw 0xa540, 0xc09d, 0xa57f, 0xc09d, 0x21, 0 + .dw 0xa5c0, 0xc09d, 0xa5ff, 0xc09d, 0x21, 0 + .dw 0xa640, 0xc09d, 0xa67f, 0xc09d, 0x21, 0 + .dw 0xa6c0, 0xc09d, 0xa6ff, 0xc09d, 0x21, 0 + .dw 0xa740, 0xc09d, 0xa77f, 0xc09d, 0x21, 0 + .dw 0xa7c0, 0xc09d, 0xa7ff, 0xc09d, 0x21, 0 + .dw 0xa840, 0xc09d, 0xa87f, 0xc09d, 0x21, 0 + .dw 0xa8c0, 0xc09d, 0xa8ff, 0xc09d, 0x21, 0 + .dw 0xa940, 0xc09d, 0xa97f, 0xc09d, 0x21, 0 + .dw 0xa9c0, 0xc09d, 0xa9ff, 0xc09d, 0x21, 0 + .dw 0xaa40, 0xc09d, 0xaa7f, 0xc09d, 0x21, 0 + .dw 0xaac0, 0xc09d, 0xaaff, 0xc09d, 0x21, 0 + .dw 0xab40, 0xc09d, 0xab7f, 0xc09d, 0x21, 0 + .dw 0xabc0, 0xc09d, 0xabff, 0xc09d, 0x21, 0 + .dw 0xac40, 0xc09d, 0xac7f, 0xc09d, 0x21, 0 + .dw 0xacc0, 0xc09d, 0xacff, 0xc09d, 0x21, 0 + .dw 0xad40, 0xc09d, 0xad7f, 0xc09d, 0x21, 0 + .dw 0xadc0, 0xc09d, 0xadff, 0xc09d, 0x21, 0 + .dw 0xae40, 0xc09d, 0xae7f, 0xc09d, 0x21, 0 + .dw 0xaec0, 0xc09d, 0xaeff, 0xc09d, 0x21, 0 + .dw 0xaf40, 0xc09d, 0xaf7f, 0xc09d, 0x21, 0 + .dw 0xafc0, 0xc09d, 0xafff, 0xc09d, 0x21, 0 + .dw 0xb040, 0xc09d, 0xb07f, 0xc09d, 0x21, 0 + .dw 0xb0c0, 0xc09d, 0xb0ff, 0xc09d, 0x21, 0 + .dw 0xb140, 0xc09d, 0xb17f, 0xc09d, 0x21, 0 + .dw 0xb1c0, 0xc09d, 0xb1ff, 0xc09d, 0x21, 0 + .dw 0xb240, 0xc09d, 0xb27f, 0xc09d, 0x21, 0 + .dw 0xb2c0, 0xc09d, 0xb2ff, 0xc09d, 0x21, 0 + .dw 0xb340, 0xc09d, 0xb37f, 0xc09d, 0x21, 0 + .dw 0xb3c0, 0xc09d, 0xb3ff, 0xc09d, 0x21, 0 + .dw 0xb440, 0xc09d, 0xb47f, 0xc09d, 0x21, 0 + .dw 0xb4c0, 0xc09d, 0xb4ff, 0xc09d, 0x21, 0 + .dw 0xb540, 0xc09d, 0xb57f, 0xc09d, 0x21, 0 + .dw 0xb5c0, 0xc09d, 0xb5ff, 0xc09d, 0x21, 0 + .dw 0xb640, 0xc09d, 0xb67f, 0xc09d, 0x21, 0 + .dw 0xb6c0, 0xc09d, 0xb6ff, 0xc09d, 0x21, 0 + .dw 0xb740, 0xc09d, 0xb77f, 0xc09d, 0x21, 0 + .dw 0xb7c0, 0xc09d, 0xb7ff, 0xc09d, 0x21, 0 + .dw 0xb840, 0xc09d, 0xb87f, 0xc09d, 0x21, 0 + .dw 0xb8c0, 0xc09d, 0xb8ff, 0xc09d, 0x21, 0 + .dw 0xb940, 0xc09d, 0xb97f, 0xc09d, 0x21, 0 + .dw 0xb9c0, 0xc09d, 0xbfff, 0xc09d, 0x21, 0 + .dw 0xc040, 0xc09d, 0xc07f, 0xc09d, 0x21, 0 + .dw 0xc0c0, 0xc09d, 0xc0ff, 0xc09d, 0x21, 0 + .dw 0xc140, 0xc09d, 0xc17f, 0xc09d, 0x21, 0 + .dw 0xc1c0, 0xc09d, 0xc1ff, 0xc09d, 0x21, 0 + .dw 0xc240, 0xc09d, 0xc27f, 0xc09d, 0x21, 0 + .dw 0xc2c0, 0xc09d, 0xc2ff, 0xc09d, 0x21, 0 + .dw 0xc340, 0xc09d, 0xc37f, 0xc09d, 0x21, 0 + .dw 0xc3c0, 0xc09d, 0xc3ff, 0xc09d, 0x21, 0 + .dw 0xc440, 0xc09d, 0xc47f, 0xc09d, 0x21, 0 + .dw 0xc4c0, 0xc09d, 0xc4ff, 0xc09d, 0x21, 0 + .dw 0xc540, 0xc09d, 0xc57f, 0xc09d, 0x21, 0 + .dw 0xc5c0, 0xc09d, 0xc5ff, 0xc09d, 0x21, 0 + .dw 0xc640, 0xc09d, 0xc67f, 0xc09d, 0x21, 0 + .dw 0xc6c0, 0xc09d, 0xc6ff, 0xc09d, 0x21, 0 + .dw 0xc740, 0xc09d, 0xc77f, 0xc09d, 0x21, 0 + .dw 0xc7c0, 0xc09d, 0xc7ff, 0xc09d, 0x21, 0 + .dw 0xc840, 0xc09d, 0xc87f, 0xc09d, 0x21, 0 + .dw 0xc8c0, 0xc09d, 0xc8ff, 0xc09d, 0x21, 0 + .dw 0xc940, 0xc09d, 0xc97f, 0xc09d, 0x21, 0 + .dw 0xc9c0, 0xc09d, 0xc9ff, 0xc09d, 0x21, 0 + .dw 0xca40, 0xc09d, 0xca7f, 0xc09d, 0x21, 0 + .dw 0xcac0, 0xc09d, 0xcaff, 0xc09d, 0x21, 0 + .dw 0xcb40, 0xc09d, 0xcb7f, 0xc09d, 0x21, 0 + .dw 0xcbc0, 0xc09d, 0xcbff, 0xc09d, 0x21, 0 + .dw 0xcc40, 0xc09d, 0xcc7f, 0xc09d, 0x21, 0 + .dw 0xccc0, 0xc09d, 0xccff, 0xc09d, 0x21, 0 + .dw 0xcd40, 0xc09d, 0xcd7f, 0xc09d, 0x21, 0 + .dw 0xcdc0, 0xc09d, 0xcdff, 0xc09d, 0x21, 0 + .dw 0xce40, 0xc09d, 0xce7f, 0xc09d, 0x21, 0 + .dw 0xcec0, 0xc09d, 0xceff, 0xc09d, 0x21, 0 + .dw 0xcf40, 0xc09d, 0xcf7f, 0xc09d, 0x21, 0 + .dw 0xcfc0, 0xc09d, 0xcfff, 0xc09d, 0x21, 0 + .dw 0xd040, 0xc09d, 0xd07f, 0xc09d, 0x21, 0 + .dw 0xd0c0, 0xc09d, 0xd0ff, 0xc09d, 0x21, 0 + .dw 0xd140, 0xc09d, 0xd17f, 0xc09d, 0x21, 0 + .dw 0xd1c0, 0xc09d, 0xd1ff, 0xc09d, 0x21, 0 + .dw 0xd240, 0xc09d, 0xd27f, 0xc09d, 0x21, 0 + .dw 0xd2c0, 0xc09d, 0xd2ff, 0xc09d, 0x21, 0 + .dw 0xd340, 0xc09d, 0xd37f, 0xc09d, 0x21, 0 + .dw 0xd3c0, 0xc09d, 0xd3ff, 0xc09d, 0x21, 0 + .dw 0xd440, 0xc09d, 0xd47f, 0xc09d, 0x21, 0 + .dw 0xd4c0, 0xc09d, 0xd4ff, 0xc09d, 0x21, 0 + .dw 0xd540, 0xc09d, 0xd57f, 0xc09d, 0x21, 0 + .dw 0xd5c0, 0xc09d, 0xd5ff, 0xc09d, 0x21, 0 + .dw 0xd640, 0xc09d, 0xd67f, 0xc09d, 0x21, 0 + .dw 0xd6c0, 0xc09d, 0xd6ff, 0xc09d, 0x21, 0 + .dw 0xd740, 0xc09d, 0xd77f, 0xc09d, 0x21, 0 + .dw 0xd7c0, 0xc09d, 0xd7ff, 0xc09d, 0x21, 0 + .dw 0xd840, 0xc09d, 0xd87f, 0xc09d, 0x21, 0 + .dw 0xd8c0, 0xc09d, 0xd8ff, 0xc09d, 0x21, 0 + .dw 0xd940, 0xc09d, 0xd97f, 0xc09d, 0x21, 0 + .dw 0xd9c0, 0xc09d, 0xdfff, 0xc09d, 0x21, 0 + .dw 0xe040, 0xc09d, 0xe07f, 0xc09d, 0x21, 0 + .dw 0xe0c0, 0xc09d, 0xe0ff, 0xc09d, 0x21, 0 + .dw 0xe140, 0xc09d, 0xe17f, 0xc09d, 0x21, 0 + .dw 0xe1c0, 0xc09d, 0xe1ff, 0xc09d, 0x21, 0 + .dw 0xe240, 0xc09d, 0xe27f, 0xc09d, 0x21, 0 + .dw 0xe2c0, 0xc09d, 0xe2ff, 0xc09d, 0x21, 0 + .dw 0xe340, 0xc09d, 0xe37f, 0xc09d, 0x21, 0 + .dw 0xe3c0, 0xc09d, 0xe3ff, 0xc09d, 0x21, 0 + .dw 0xe440, 0xc09d, 0xe47f, 0xc09d, 0x21, 0 + .dw 0xe4c0, 0xc09d, 0xe4ff, 0xc09d, 0x21, 0 + .dw 0xe540, 0xc09d, 0xe57f, 0xc09d, 0x21, 0 + .dw 0xe5c0, 0xc09d, 0xe5ff, 0xc09d, 0x21, 0 + .dw 0xe640, 0xc09d, 0xe67f, 0xc09d, 0x21, 0 + .dw 0xe6c0, 0xc09d, 0xe6ff, 0xc09d, 0x21, 0 + .dw 0xe740, 0xc09d, 0xe77f, 0xc09d, 0x21, 0 + .dw 0xe7c0, 0xc09d, 0xe7ff, 0xc09d, 0x21, 0 + .dw 0xe840, 0xc09d, 0xe87f, 0xc09d, 0x21, 0 + .dw 0xe8c0, 0xc09d, 0xe8ff, 0xc09d, 0x21, 0 + .dw 0xe940, 0xc09d, 0xe97f, 0xc09d, 0x21, 0 + .dw 0xe9c0, 0xc09d, 0xe9ff, 0xc09d, 0x21, 0 + .dw 0xea40, 0xc09d, 0xea7f, 0xc09d, 0x21, 0 + .dw 0xeac0, 0xc09d, 0xeaff, 0xc09d, 0x21, 0 + .dw 0xeb40, 0xc09d, 0xeb7f, 0xc09d, 0x21, 0 + .dw 0xebc0, 0xc09d, 0xebff, 0xc09d, 0x21, 0 + .dw 0xec40, 0xc09d, 0xec7f, 0xc09d, 0x21, 0 + .dw 0xecc0, 0xc09d, 0xecff, 0xc09d, 0x21, 0 + .dw 0xed40, 0xc09d, 0xed7f, 0xc09d, 0x21, 0 + .dw 0xedc0, 0xc09d, 0xedff, 0xc09d, 0x21, 0 + .dw 0xee40, 0xc09d, 0xee7f, 0xc09d, 0x21, 0 + .dw 0xeec0, 0xc09d, 0xeeff, 0xc09d, 0x21, 0 + .dw 0xef40, 0xc09d, 0xef7f, 0xc09d, 0x21, 0 + .dw 0xefc0, 0xc09d, 0xefff, 0xc09d, 0x21, 0 + .dw 0xf040, 0xc09d, 0xf07f, 0xc09d, 0x21, 0 + .dw 0xf0c0, 0xc09d, 0xf0ff, 0xc09d, 0x21, 0 + .dw 0xf140, 0xc09d, 0xf17f, 0xc09d, 0x21, 0 + .dw 0xf1c0, 0xc09d, 0xf1ff, 0xc09d, 0x21, 0 + .dw 0xf240, 0xc09d, 0xf27f, 0xc09d, 0x21, 0 + .dw 0xf2c0, 0xc09d, 0xf2ff, 0xc09d, 0x21, 0 + .dw 0xf340, 0xc09d, 0xf37f, 0xc09d, 0x21, 0 + .dw 0xf3c0, 0xc09d, 0xf3ff, 0xc09d, 0x21, 0 + .dw 0xf440, 0xc09d, 0xf47f, 0xc09d, 0x21, 0 + .dw 0xf4c0, 0xc09d, 0xf4ff, 0xc09d, 0x21, 0 + .dw 0xf540, 0xc09d, 0xf57f, 0xc09d, 0x21, 0 + .dw 0xf5c0, 0xc09d, 0xf5ff, 0xc09d, 0x21, 0 + .dw 0xf640, 0xc09d, 0xf67f, 0xc09d, 0x21, 0 + .dw 0xf6c0, 0xc09d, 0xf6ff, 0xc09d, 0x21, 0 + .dw 0xf740, 0xc09d, 0xf77f, 0xc09d, 0x21, 0 + .dw 0xf7c0, 0xc09d, 0xf7ff, 0xc09d, 0x21, 0 + .dw 0xf840, 0xc09d, 0xf87f, 0xc09d, 0x21, 0 + .dw 0xf8c0, 0xc09d, 0xf8ff, 0xc09d, 0x21, 0 + .dw 0xf940, 0xc09d, 0xf97f, 0xc09d, 0x21, 0 + .dw 0xf9c0, 0xc09d, 0xffff, 0xc09d, 0x21, 0 + .dw 0x0040, 0xc09e, 0x007f, 0xc09e, 0x21, 0 + .dw 0x00c0, 0xc09e, 0x00ff, 0xc09e, 0x21, 0 + .dw 0x0140, 0xc09e, 0x017f, 0xc09e, 0x21, 0 + .dw 0x01c0, 0xc09e, 0x01ff, 0xc09e, 0x21, 0 + .dw 0x0240, 0xc09e, 0x027f, 0xc09e, 0x21, 0 + .dw 0x02c0, 0xc09e, 0x02ff, 0xc09e, 0x21, 0 + .dw 0x0340, 0xc09e, 0x037f, 0xc09e, 0x21, 0 + .dw 0x03c0, 0xc09e, 0x03ff, 0xc09e, 0x21, 0 + .dw 0x0440, 0xc09e, 0x047f, 0xc09e, 0x21, 0 + .dw 0x04c0, 0xc09e, 0x04ff, 0xc09e, 0x21, 0 + .dw 0x0540, 0xc09e, 0x057f, 0xc09e, 0x21, 0 + .dw 0x05c0, 0xc09e, 0x05ff, 0xc09e, 0x21, 0 + .dw 0x0640, 0xc09e, 0x067f, 0xc09e, 0x21, 0 + .dw 0x06c0, 0xc09e, 0x06ff, 0xc09e, 0x21, 0 + .dw 0x0740, 0xc09e, 0x077f, 0xc09e, 0x21, 0 + .dw 0x07c0, 0xc09e, 0x07ff, 0xc09e, 0x21, 0 + .dw 0x0840, 0xc09e, 0x087f, 0xc09e, 0x21, 0 + .dw 0x08c0, 0xc09e, 0x08ff, 0xc09e, 0x21, 0 + .dw 0x0940, 0xc09e, 0x097f, 0xc09e, 0x21, 0 + .dw 0x09c0, 0xc09e, 0x09ff, 0xc09e, 0x21, 0 + .dw 0x0a40, 0xc09e, 0x0a7f, 0xc09e, 0x21, 0 + .dw 0x0ac0, 0xc09e, 0x0aff, 0xc09e, 0x21, 0 + .dw 0x0b40, 0xc09e, 0x0b7f, 0xc09e, 0x21, 0 + .dw 0x0bc0, 0xc09e, 0x0bff, 0xc09e, 0x21, 0 + .dw 0x0c40, 0xc09e, 0x0c7f, 0xc09e, 0x21, 0 + .dw 0x0cc0, 0xc09e, 0x0cff, 0xc09e, 0x21, 0 + .dw 0x0d40, 0xc09e, 0x0d7f, 0xc09e, 0x21, 0 + .dw 0x0dc0, 0xc09e, 0x0dff, 0xc09e, 0x21, 0 + .dw 0x0e40, 0xc09e, 0x0e7f, 0xc09e, 0x21, 0 + .dw 0x0ec0, 0xc09e, 0x0eff, 0xc09e, 0x21, 0 + .dw 0x0f40, 0xc09e, 0x0f7f, 0xc09e, 0x21, 0 + .dw 0x0fc0, 0xc09e, 0x0fff, 0xc09e, 0x21, 0 + .dw 0x1040, 0xc09e, 0x107f, 0xc09e, 0x21, 0 + .dw 0x10c0, 0xc09e, 0x10ff, 0xc09e, 0x21, 0 + .dw 0x1140, 0xc09e, 0x117f, 0xc09e, 0x21, 0 + .dw 0x11c0, 0xc09e, 0x11ff, 0xc09e, 0x21, 0 + .dw 0x1240, 0xc09e, 0x127f, 0xc09e, 0x21, 0 + .dw 0x12c0, 0xc09e, 0x12ff, 0xc09e, 0x21, 0 + .dw 0x1340, 0xc09e, 0x137f, 0xc09e, 0x21, 0 + .dw 0x13c0, 0xc09e, 0x13ff, 0xc09e, 0x21, 0 + .dw 0x1440, 0xc09e, 0x147f, 0xc09e, 0x21, 0 + .dw 0x14c0, 0xc09e, 0x14ff, 0xc09e, 0x21, 0 + .dw 0x1540, 0xc09e, 0x157f, 0xc09e, 0x21, 0 + .dw 0x15c0, 0xc09e, 0x15ff, 0xc09e, 0x21, 0 + .dw 0x1640, 0xc09e, 0x167f, 0xc09e, 0x21, 0 + .dw 0x16c0, 0xc09e, 0x16ff, 0xc09e, 0x21, 0 + .dw 0x1740, 0xc09e, 0x177f, 0xc09e, 0x21, 0 + .dw 0x17c0, 0xc09e, 0x17ff, 0xc09e, 0x21, 0 + .dw 0x1840, 0xc09e, 0x187f, 0xc09e, 0x21, 0 + .dw 0x18c0, 0xc09e, 0x18ff, 0xc09e, 0x21, 0 + .dw 0x1940, 0xc09e, 0x197f, 0xc09e, 0x21, 0 + .dw 0x19c0, 0xc09e, 0x1fff, 0xc09e, 0x21, 0 + .dw 0x2040, 0xc09e, 0x207f, 0xc09e, 0x21, 0 + .dw 0x20c0, 0xc09e, 0x20ff, 0xc09e, 0x21, 0 + .dw 0x2140, 0xc09e, 0x217f, 0xc09e, 0x21, 0 + .dw 0x21c0, 0xc09e, 0x21ff, 0xc09e, 0x21, 0 + .dw 0x2240, 0xc09e, 0x227f, 0xc09e, 0x21, 0 + .dw 0x22c0, 0xc09e, 0x22ff, 0xc09e, 0x21, 0 + .dw 0x2340, 0xc09e, 0x237f, 0xc09e, 0x21, 0 + .dw 0x23c0, 0xc09e, 0x23ff, 0xc09e, 0x21, 0 + .dw 0x2440, 0xc09e, 0x247f, 0xc09e, 0x21, 0 + .dw 0x24c0, 0xc09e, 0x24ff, 0xc09e, 0x21, 0 + .dw 0x2540, 0xc09e, 0x257f, 0xc09e, 0x21, 0 + .dw 0x25c0, 0xc09e, 0x25ff, 0xc09e, 0x21, 0 + .dw 0x2640, 0xc09e, 0x267f, 0xc09e, 0x21, 0 + .dw 0x26c0, 0xc09e, 0x26ff, 0xc09e, 0x21, 0 + .dw 0x2740, 0xc09e, 0x277f, 0xc09e, 0x21, 0 + .dw 0x27c0, 0xc09e, 0x27ff, 0xc09e, 0x21, 0 + .dw 0x2840, 0xc09e, 0x287f, 0xc09e, 0x21, 0 + .dw 0x28c0, 0xc09e, 0x28ff, 0xc09e, 0x21, 0 + .dw 0x2940, 0xc09e, 0x297f, 0xc09e, 0x21, 0 + .dw 0x29c0, 0xc09e, 0x29ff, 0xc09e, 0x21, 0 + .dw 0x2a40, 0xc09e, 0x2a7f, 0xc09e, 0x21, 0 + .dw 0x2ac0, 0xc09e, 0x2aff, 0xc09e, 0x21, 0 + .dw 0x2b40, 0xc09e, 0x2b7f, 0xc09e, 0x21, 0 + .dw 0x2bc0, 0xc09e, 0x2bff, 0xc09e, 0x21, 0 + .dw 0x2c40, 0xc09e, 0x2c7f, 0xc09e, 0x21, 0 + .dw 0x2cc0, 0xc09e, 0x2cff, 0xc09e, 0x21, 0 + .dw 0x2d40, 0xc09e, 0x2d7f, 0xc09e, 0x21, 0 + .dw 0x2dc0, 0xc09e, 0x2dff, 0xc09e, 0x21, 0 + .dw 0x2e40, 0xc09e, 0x2e7f, 0xc09e, 0x21, 0 + .dw 0x2ec0, 0xc09e, 0x2eff, 0xc09e, 0x21, 0 + .dw 0x2f40, 0xc09e, 0x2f7f, 0xc09e, 0x21, 0 + .dw 0x2fc0, 0xc09e, 0x2fff, 0xc09e, 0x21, 0 + .dw 0x3040, 0xc09e, 0x307f, 0xc09e, 0x21, 0 + .dw 0x30c0, 0xc09e, 0x30ff, 0xc09e, 0x21, 0 + .dw 0x3140, 0xc09e, 0x317f, 0xc09e, 0x21, 0 + .dw 0x31c0, 0xc09e, 0x31ff, 0xc09e, 0x21, 0 + .dw 0x3240, 0xc09e, 0x327f, 0xc09e, 0x21, 0 + .dw 0x32c0, 0xc09e, 0x32ff, 0xc09e, 0x21, 0 + .dw 0x3340, 0xc09e, 0x337f, 0xc09e, 0x21, 0 + .dw 0x33c0, 0xc09e, 0x33ff, 0xc09e, 0x21, 0 + .dw 0x3440, 0xc09e, 0x347f, 0xc09e, 0x21, 0 + .dw 0x34c0, 0xc09e, 0x34ff, 0xc09e, 0x21, 0 + .dw 0x3540, 0xc09e, 0x357f, 0xc09e, 0x21, 0 + .dw 0x35c0, 0xc09e, 0x35ff, 0xc09e, 0x21, 0 + .dw 0x3640, 0xc09e, 0x367f, 0xc09e, 0x21, 0 + .dw 0x36c0, 0xc09e, 0x36ff, 0xc09e, 0x21, 0 + .dw 0x3740, 0xc09e, 0x377f, 0xc09e, 0x21, 0 + .dw 0x37c0, 0xc09e, 0x37ff, 0xc09e, 0x21, 0 + .dw 0x3840, 0xc09e, 0x387f, 0xc09e, 0x21, 0 + .dw 0x38c0, 0xc09e, 0x38ff, 0xc09e, 0x21, 0 + .dw 0x3940, 0xc09e, 0x397f, 0xc09e, 0x21, 0 + .dw 0x39c0, 0xc09e, 0x3fff, 0xc09e, 0x21, 0 + .dw 0x4040, 0xc09e, 0x407f, 0xc09e, 0x21, 0 + .dw 0x40c0, 0xc09e, 0x40ff, 0xc09e, 0x21, 0 + .dw 0x4140, 0xc09e, 0x417f, 0xc09e, 0x21, 0 + .dw 0x41c0, 0xc09e, 0x41ff, 0xc09e, 0x21, 0 + .dw 0x4240, 0xc09e, 0x427f, 0xc09e, 0x21, 0 + .dw 0x42c0, 0xc09e, 0x42ff, 0xc09e, 0x21, 0 + .dw 0x4340, 0xc09e, 0x437f, 0xc09e, 0x21, 0 + .dw 0x43c0, 0xc09e, 0x43ff, 0xc09e, 0x21, 0 + .dw 0x4440, 0xc09e, 0x447f, 0xc09e, 0x21, 0 + .dw 0x44c0, 0xc09e, 0x44ff, 0xc09e, 0x21, 0 + .dw 0x4540, 0xc09e, 0x457f, 0xc09e, 0x21, 0 + .dw 0x45c0, 0xc09e, 0x45ff, 0xc09e, 0x21, 0 + .dw 0x4640, 0xc09e, 0x467f, 0xc09e, 0x21, 0 + .dw 0x46c0, 0xc09e, 0x46ff, 0xc09e, 0x21, 0 + .dw 0x4740, 0xc09e, 0x477f, 0xc09e, 0x21, 0 + .dw 0x47c0, 0xc09e, 0x47ff, 0xc09e, 0x21, 0 + .dw 0x4840, 0xc09e, 0x487f, 0xc09e, 0x21, 0 + .dw 0x48c0, 0xc09e, 0x48ff, 0xc09e, 0x21, 0 + .dw 0x4940, 0xc09e, 0x497f, 0xc09e, 0x21, 0 + .dw 0x49c0, 0xc09e, 0x49ff, 0xc09e, 0x21, 0 + .dw 0x4a40, 0xc09e, 0x4a7f, 0xc09e, 0x21, 0 + .dw 0x4ac0, 0xc09e, 0x4aff, 0xc09e, 0x21, 0 + .dw 0x4b40, 0xc09e, 0x4b7f, 0xc09e, 0x21, 0 + .dw 0x4bc0, 0xc09e, 0x4bff, 0xc09e, 0x21, 0 + .dw 0x4c40, 0xc09e, 0x4c7f, 0xc09e, 0x21, 0 + .dw 0x4cc0, 0xc09e, 0x4cff, 0xc09e, 0x21, 0 + .dw 0x4d40, 0xc09e, 0x4d7f, 0xc09e, 0x21, 0 + .dw 0x4dc0, 0xc09e, 0x4dff, 0xc09e, 0x21, 0 + .dw 0x4e40, 0xc09e, 0x4e7f, 0xc09e, 0x21, 0 + .dw 0x4ec0, 0xc09e, 0x4eff, 0xc09e, 0x21, 0 + .dw 0x4f40, 0xc09e, 0x4f7f, 0xc09e, 0x21, 0 + .dw 0x4fc0, 0xc09e, 0x4fff, 0xc09e, 0x21, 0 + .dw 0x5040, 0xc09e, 0x507f, 0xc09e, 0x21, 0 + .dw 0x50c0, 0xc09e, 0x50ff, 0xc09e, 0x21, 0 + .dw 0x5140, 0xc09e, 0x517f, 0xc09e, 0x21, 0 + .dw 0x51c0, 0xc09e, 0x51ff, 0xc09e, 0x21, 0 + .dw 0x5240, 0xc09e, 0x527f, 0xc09e, 0x21, 0 + .dw 0x52c0, 0xc09e, 0x52ff, 0xc09e, 0x21, 0 + .dw 0x5340, 0xc09e, 0x537f, 0xc09e, 0x21, 0 + .dw 0x53c0, 0xc09e, 0x53ff, 0xc09e, 0x21, 0 + .dw 0x5440, 0xc09e, 0x547f, 0xc09e, 0x21, 0 + .dw 0x54c0, 0xc09e, 0x54ff, 0xc09e, 0x21, 0 + .dw 0x5540, 0xc09e, 0x557f, 0xc09e, 0x21, 0 + .dw 0x55c0, 0xc09e, 0x55ff, 0xc09e, 0x21, 0 + .dw 0x5640, 0xc09e, 0x567f, 0xc09e, 0x21, 0 + .dw 0x56c0, 0xc09e, 0x56ff, 0xc09e, 0x21, 0 + .dw 0x5740, 0xc09e, 0x577f, 0xc09e, 0x21, 0 + .dw 0x57c0, 0xc09e, 0x57ff, 0xc09e, 0x21, 0 + .dw 0x5840, 0xc09e, 0x587f, 0xc09e, 0x21, 0 + .dw 0x58c0, 0xc09e, 0x58ff, 0xc09e, 0x21, 0 + .dw 0x5940, 0xc09e, 0x597f, 0xc09e, 0x21, 0 + .dw 0x59c0, 0xc09e, 0x5fff, 0xc09e, 0x21, 0 + .dw 0x6040, 0xc09e, 0x607f, 0xc09e, 0x21, 0 + .dw 0x60c0, 0xc09e, 0x60ff, 0xc09e, 0x21, 0 + .dw 0x6140, 0xc09e, 0x617f, 0xc09e, 0x21, 0 + .dw 0x61c0, 0xc09e, 0x61ff, 0xc09e, 0x21, 0 + .dw 0x6240, 0xc09e, 0x627f, 0xc09e, 0x21, 0 + .dw 0x62c0, 0xc09e, 0x62ff, 0xc09e, 0x21, 0 + .dw 0x6340, 0xc09e, 0x637f, 0xc09e, 0x21, 0 + .dw 0x63c0, 0xc09e, 0x63ff, 0xc09e, 0x21, 0 + .dw 0x6440, 0xc09e, 0x647f, 0xc09e, 0x21, 0 + .dw 0x64c0, 0xc09e, 0x64ff, 0xc09e, 0x21, 0 + .dw 0x6540, 0xc09e, 0x657f, 0xc09e, 0x21, 0 + .dw 0x65c0, 0xc09e, 0x65ff, 0xc09e, 0x21, 0 + .dw 0x6640, 0xc09e, 0x667f, 0xc09e, 0x21, 0 + .dw 0x66c0, 0xc09e, 0x66ff, 0xc09e, 0x21, 0 + .dw 0x6740, 0xc09e, 0x677f, 0xc09e, 0x21, 0 + .dw 0x67c0, 0xc09e, 0x67ff, 0xc09e, 0x21, 0 + .dw 0x6840, 0xc09e, 0x687f, 0xc09e, 0x21, 0 + .dw 0x68c0, 0xc09e, 0x68ff, 0xc09e, 0x21, 0 + .dw 0x6940, 0xc09e, 0x697f, 0xc09e, 0x21, 0 + .dw 0x69c0, 0xc09e, 0x69ff, 0xc09e, 0x21, 0 + .dw 0x6a40, 0xc09e, 0x6a7f, 0xc09e, 0x21, 0 + .dw 0x6ac0, 0xc09e, 0x6aff, 0xc09e, 0x21, 0 + .dw 0x6b40, 0xc09e, 0x6b7f, 0xc09e, 0x21, 0 + .dw 0x6bc0, 0xc09e, 0x6bff, 0xc09e, 0x21, 0 + .dw 0x6c40, 0xc09e, 0x6c7f, 0xc09e, 0x21, 0 + .dw 0x6cc0, 0xc09e, 0x6cff, 0xc09e, 0x21, 0 + .dw 0x6d40, 0xc09e, 0x6d7f, 0xc09e, 0x21, 0 + .dw 0x6dc0, 0xc09e, 0x6dff, 0xc09e, 0x21, 0 + .dw 0x6e40, 0xc09e, 0x6e7f, 0xc09e, 0x21, 0 + .dw 0x6ec0, 0xc09e, 0x6eff, 0xc09e, 0x21, 0 + .dw 0x6f40, 0xc09e, 0x6f7f, 0xc09e, 0x21, 0 + .dw 0x6fc0, 0xc09e, 0x6fff, 0xc09e, 0x21, 0 + .dw 0x7040, 0xc09e, 0x707f, 0xc09e, 0x21, 0 + .dw 0x70c0, 0xc09e, 0x70ff, 0xc09e, 0x21, 0 + .dw 0x7140, 0xc09e, 0x717f, 0xc09e, 0x21, 0 + .dw 0x71c0, 0xc09e, 0x71ff, 0xc09e, 0x21, 0 + .dw 0x7240, 0xc09e, 0x727f, 0xc09e, 0x21, 0 + .dw 0x72c0, 0xc09e, 0x72ff, 0xc09e, 0x21, 0 + .dw 0x7340, 0xc09e, 0x737f, 0xc09e, 0x21, 0 + .dw 0x73c0, 0xc09e, 0x73ff, 0xc09e, 0x21, 0 + .dw 0x7440, 0xc09e, 0x747f, 0xc09e, 0x21, 0 + .dw 0x74c0, 0xc09e, 0x74ff, 0xc09e, 0x21, 0 + .dw 0x7540, 0xc09e, 0x757f, 0xc09e, 0x21, 0 + .dw 0x75c0, 0xc09e, 0x75ff, 0xc09e, 0x21, 0 + .dw 0x7640, 0xc09e, 0x767f, 0xc09e, 0x21, 0 + .dw 0x76c0, 0xc09e, 0x76ff, 0xc09e, 0x21, 0 + .dw 0x7740, 0xc09e, 0x777f, 0xc09e, 0x21, 0 + .dw 0x77c0, 0xc09e, 0x77ff, 0xc09e, 0x21, 0 + .dw 0x7840, 0xc09e, 0x787f, 0xc09e, 0x21, 0 + .dw 0x78c0, 0xc09e, 0x78ff, 0xc09e, 0x21, 0 + .dw 0x7940, 0xc09e, 0x797f, 0xc09e, 0x21, 0 + .dw 0x79c0, 0xc09e, 0x7fff, 0xc09e, 0x21, 0 + .dw 0x8040, 0xc09e, 0x807f, 0xc09e, 0x21, 0 + .dw 0x80c0, 0xc09e, 0x80ff, 0xc09e, 0x21, 0 + .dw 0x8140, 0xc09e, 0x817f, 0xc09e, 0x21, 0 + .dw 0x81c0, 0xc09e, 0x81ff, 0xc09e, 0x21, 0 + .dw 0x8240, 0xc09e, 0x827f, 0xc09e, 0x21, 0 + .dw 0x82c0, 0xc09e, 0x82ff, 0xc09e, 0x21, 0 + .dw 0x8340, 0xc09e, 0x837f, 0xc09e, 0x21, 0 + .dw 0x83c0, 0xc09e, 0x83ff, 0xc09e, 0x21, 0 + .dw 0x8440, 0xc09e, 0x847f, 0xc09e, 0x21, 0 + .dw 0x84c0, 0xc09e, 0x84ff, 0xc09e, 0x21, 0 + .dw 0x8540, 0xc09e, 0x857f, 0xc09e, 0x21, 0 + .dw 0x85c0, 0xc09e, 0x85ff, 0xc09e, 0x21, 0 + .dw 0x8640, 0xc09e, 0x867f, 0xc09e, 0x21, 0 + .dw 0x86c0, 0xc09e, 0x86ff, 0xc09e, 0x21, 0 + .dw 0x8740, 0xc09e, 0x877f, 0xc09e, 0x21, 0 + .dw 0x87c0, 0xc09e, 0x87ff, 0xc09e, 0x21, 0 + .dw 0x8840, 0xc09e, 0x887f, 0xc09e, 0x21, 0 + .dw 0x88c0, 0xc09e, 0x88ff, 0xc09e, 0x21, 0 + .dw 0x8940, 0xc09e, 0x897f, 0xc09e, 0x21, 0 + .dw 0x89c0, 0xc09e, 0x89ff, 0xc09e, 0x21, 0 + .dw 0x8a40, 0xc09e, 0x8a7f, 0xc09e, 0x21, 0 + .dw 0x8ac0, 0xc09e, 0x8aff, 0xc09e, 0x21, 0 + .dw 0x8b40, 0xc09e, 0x8b7f, 0xc09e, 0x21, 0 + .dw 0x8bc0, 0xc09e, 0x8bff, 0xc09e, 0x21, 0 + .dw 0x8c40, 0xc09e, 0x8c7f, 0xc09e, 0x21, 0 + .dw 0x8cc0, 0xc09e, 0x8cff, 0xc09e, 0x21, 0 + .dw 0x8d40, 0xc09e, 0x8d7f, 0xc09e, 0x21, 0 + .dw 0x8dc0, 0xc09e, 0x8dff, 0xc09e, 0x21, 0 + .dw 0x8e40, 0xc09e, 0x8e7f, 0xc09e, 0x21, 0 + .dw 0x8ec0, 0xc09e, 0x8eff, 0xc09e, 0x21, 0 + .dw 0x8f40, 0xc09e, 0x8f7f, 0xc09e, 0x21, 0 + .dw 0x8fc0, 0xc09e, 0x8fff, 0xc09e, 0x21, 0 + .dw 0x9040, 0xc09e, 0x907f, 0xc09e, 0x21, 0 + .dw 0x90c0, 0xc09e, 0x90ff, 0xc09e, 0x21, 0 + .dw 0x9140, 0xc09e, 0x917f, 0xc09e, 0x21, 0 + .dw 0x91c0, 0xc09e, 0x91ff, 0xc09e, 0x21, 0 + .dw 0x9240, 0xc09e, 0x927f, 0xc09e, 0x21, 0 + .dw 0x92c0, 0xc09e, 0x92ff, 0xc09e, 0x21, 0 + .dw 0x9340, 0xc09e, 0x937f, 0xc09e, 0x21, 0 + .dw 0x93c0, 0xc09e, 0x93ff, 0xc09e, 0x21, 0 + .dw 0x9440, 0xc09e, 0x947f, 0xc09e, 0x21, 0 + .dw 0x94c0, 0xc09e, 0x94ff, 0xc09e, 0x21, 0 + .dw 0x9540, 0xc09e, 0x957f, 0xc09e, 0x21, 0 + .dw 0x95c0, 0xc09e, 0x95ff, 0xc09e, 0x21, 0 + .dw 0x9640, 0xc09e, 0x967f, 0xc09e, 0x21, 0 + .dw 0x96c0, 0xc09e, 0x96ff, 0xc09e, 0x21, 0 + .dw 0x9740, 0xc09e, 0x977f, 0xc09e, 0x21, 0 + .dw 0x97c0, 0xc09e, 0x97ff, 0xc09e, 0x21, 0 + .dw 0x9840, 0xc09e, 0x987f, 0xc09e, 0x21, 0 + .dw 0x98c0, 0xc09e, 0x98ff, 0xc09e, 0x21, 0 + .dw 0x9940, 0xc09e, 0x997f, 0xc09e, 0x21, 0 + .dw 0x99c0, 0xc09e, 0x9fff, 0xc09e, 0x21, 0 + .dw 0xa040, 0xc09e, 0xa07f, 0xc09e, 0x21, 0 + .dw 0xa0c0, 0xc09e, 0xa0ff, 0xc09e, 0x21, 0 + .dw 0xa140, 0xc09e, 0xa17f, 0xc09e, 0x21, 0 + .dw 0xa1c0, 0xc09e, 0xa1ff, 0xc09e, 0x21, 0 + .dw 0xa240, 0xc09e, 0xa27f, 0xc09e, 0x21, 0 + .dw 0xa2c0, 0xc09e, 0xa2ff, 0xc09e, 0x21, 0 + .dw 0xa340, 0xc09e, 0xa37f, 0xc09e, 0x21, 0 + .dw 0xa3c0, 0xc09e, 0xa3ff, 0xc09e, 0x21, 0 + .dw 0xa440, 0xc09e, 0xa47f, 0xc09e, 0x21, 0 + .dw 0xa4c0, 0xc09e, 0xa4ff, 0xc09e, 0x21, 0 + .dw 0xa540, 0xc09e, 0xa57f, 0xc09e, 0x21, 0 + .dw 0xa5c0, 0xc09e, 0xa5ff, 0xc09e, 0x21, 0 + .dw 0xa640, 0xc09e, 0xa67f, 0xc09e, 0x21, 0 + .dw 0xa6c0, 0xc09e, 0xa6ff, 0xc09e, 0x21, 0 + .dw 0xa740, 0xc09e, 0xa77f, 0xc09e, 0x21, 0 + .dw 0xa7c0, 0xc09e, 0xa7ff, 0xc09e, 0x21, 0 + .dw 0xa840, 0xc09e, 0xa87f, 0xc09e, 0x21, 0 + .dw 0xa8c0, 0xc09e, 0xa8ff, 0xc09e, 0x21, 0 + .dw 0xa940, 0xc09e, 0xa97f, 0xc09e, 0x21, 0 + .dw 0xa9c0, 0xc09e, 0xa9ff, 0xc09e, 0x21, 0 + .dw 0xaa40, 0xc09e, 0xaa7f, 0xc09e, 0x21, 0 + .dw 0xaac0, 0xc09e, 0xaaff, 0xc09e, 0x21, 0 + .dw 0xab40, 0xc09e, 0xab7f, 0xc09e, 0x21, 0 + .dw 0xabc0, 0xc09e, 0xabff, 0xc09e, 0x21, 0 + .dw 0xac40, 0xc09e, 0xac7f, 0xc09e, 0x21, 0 + .dw 0xacc0, 0xc09e, 0xacff, 0xc09e, 0x21, 0 + .dw 0xad40, 0xc09e, 0xad7f, 0xc09e, 0x21, 0 + .dw 0xadc0, 0xc09e, 0xadff, 0xc09e, 0x21, 0 + .dw 0xae40, 0xc09e, 0xae7f, 0xc09e, 0x21, 0 + .dw 0xaec0, 0xc09e, 0xaeff, 0xc09e, 0x21, 0 + .dw 0xaf40, 0xc09e, 0xaf7f, 0xc09e, 0x21, 0 + .dw 0xafc0, 0xc09e, 0xafff, 0xc09e, 0x21, 0 + .dw 0xb040, 0xc09e, 0xb07f, 0xc09e, 0x21, 0 + .dw 0xb0c0, 0xc09e, 0xb0ff, 0xc09e, 0x21, 0 + .dw 0xb140, 0xc09e, 0xb17f, 0xc09e, 0x21, 0 + .dw 0xb1c0, 0xc09e, 0xb1ff, 0xc09e, 0x21, 0 + .dw 0xb240, 0xc09e, 0xb27f, 0xc09e, 0x21, 0 + .dw 0xb2c0, 0xc09e, 0xb2ff, 0xc09e, 0x21, 0 + .dw 0xb340, 0xc09e, 0xb37f, 0xc09e, 0x21, 0 + .dw 0xb3c0, 0xc09e, 0xb3ff, 0xc09e, 0x21, 0 + .dw 0xb440, 0xc09e, 0xb47f, 0xc09e, 0x21, 0 + .dw 0xb4c0, 0xc09e, 0xb4ff, 0xc09e, 0x21, 0 + .dw 0xb540, 0xc09e, 0xb57f, 0xc09e, 0x21, 0 + .dw 0xb5c0, 0xc09e, 0xb5ff, 0xc09e, 0x21, 0 + .dw 0xb640, 0xc09e, 0xb67f, 0xc09e, 0x21, 0 + .dw 0xb6c0, 0xc09e, 0xb6ff, 0xc09e, 0x21, 0 + .dw 0xb740, 0xc09e, 0xb77f, 0xc09e, 0x21, 0 + .dw 0xb7c0, 0xc09e, 0xb7ff, 0xc09e, 0x21, 0 + .dw 0xb840, 0xc09e, 0xb87f, 0xc09e, 0x21, 0 + .dw 0xb8c0, 0xc09e, 0xb8ff, 0xc09e, 0x21, 0 + .dw 0xb940, 0xc09e, 0xb97f, 0xc09e, 0x21, 0 + .dw 0xb9c0, 0xc09e, 0xbfff, 0xc09e, 0x21, 0 + .dw 0xc040, 0xc09e, 0xc07f, 0xc09e, 0x21, 0 + .dw 0xc0c0, 0xc09e, 0xc0ff, 0xc09e, 0x21, 0 + .dw 0xc140, 0xc09e, 0xc17f, 0xc09e, 0x21, 0 + .dw 0xc1c0, 0xc09e, 0xc1ff, 0xc09e, 0x21, 0 + .dw 0xc240, 0xc09e, 0xc27f, 0xc09e, 0x21, 0 + .dw 0xc2c0, 0xc09e, 0xc2ff, 0xc09e, 0x21, 0 + .dw 0xc340, 0xc09e, 0xc37f, 0xc09e, 0x21, 0 + .dw 0xc3c0, 0xc09e, 0xc3ff, 0xc09e, 0x21, 0 + .dw 0xc440, 0xc09e, 0xc47f, 0xc09e, 0x21, 0 + .dw 0xc4c0, 0xc09e, 0xc4ff, 0xc09e, 0x21, 0 + .dw 0xc540, 0xc09e, 0xc57f, 0xc09e, 0x21, 0 + .dw 0xc5c0, 0xc09e, 0xc5ff, 0xc09e, 0x21, 0 + .dw 0xc640, 0xc09e, 0xc67f, 0xc09e, 0x21, 0 + .dw 0xc6c0, 0xc09e, 0xc6ff, 0xc09e, 0x21, 0 + .dw 0xc740, 0xc09e, 0xc77f, 0xc09e, 0x21, 0 + .dw 0xc7c0, 0xc09e, 0xc7ff, 0xc09e, 0x21, 0 + .dw 0xc840, 0xc09e, 0xc87f, 0xc09e, 0x21, 0 + .dw 0xc8c0, 0xc09e, 0xc8ff, 0xc09e, 0x21, 0 + .dw 0xc940, 0xc09e, 0xc97f, 0xc09e, 0x21, 0 + .dw 0xc9c0, 0xc09e, 0xc9ff, 0xc09e, 0x21, 0 + .dw 0xca40, 0xc09e, 0xca7f, 0xc09e, 0x21, 0 + .dw 0xcac0, 0xc09e, 0xcaff, 0xc09e, 0x21, 0 + .dw 0xcb40, 0xc09e, 0xcb7f, 0xc09e, 0x21, 0 + .dw 0xcbc0, 0xc09e, 0xcbff, 0xc09e, 0x21, 0 + .dw 0xcc40, 0xc09e, 0xcc7f, 0xc09e, 0x21, 0 + .dw 0xccc0, 0xc09e, 0xccff, 0xc09e, 0x21, 0 + .dw 0xcd40, 0xc09e, 0xcd7f, 0xc09e, 0x21, 0 + .dw 0xcdc0, 0xc09e, 0xcdff, 0xc09e, 0x21, 0 + .dw 0xce40, 0xc09e, 0xce7f, 0xc09e, 0x21, 0 + .dw 0xcec0, 0xc09e, 0xceff, 0xc09e, 0x21, 0 + .dw 0xcf40, 0xc09e, 0xcf7f, 0xc09e, 0x21, 0 + .dw 0xcfc0, 0xc09e, 0xcfff, 0xc09e, 0x21, 0 + .dw 0xd040, 0xc09e, 0xd07f, 0xc09e, 0x21, 0 + .dw 0xd0c0, 0xc09e, 0xd0ff, 0xc09e, 0x21, 0 + .dw 0xd140, 0xc09e, 0xd17f, 0xc09e, 0x21, 0 + .dw 0xd1c0, 0xc09e, 0xd1ff, 0xc09e, 0x21, 0 + .dw 0xd240, 0xc09e, 0xd27f, 0xc09e, 0x21, 0 + .dw 0xd2c0, 0xc09e, 0xd2ff, 0xc09e, 0x21, 0 + .dw 0xd340, 0xc09e, 0xd37f, 0xc09e, 0x21, 0 + .dw 0xd3c0, 0xc09e, 0xd3ff, 0xc09e, 0x21, 0 + .dw 0xd440, 0xc09e, 0xd47f, 0xc09e, 0x21, 0 + .dw 0xd4c0, 0xc09e, 0xd4ff, 0xc09e, 0x21, 0 + .dw 0xd540, 0xc09e, 0xd57f, 0xc09e, 0x21, 0 + .dw 0xd5c0, 0xc09e, 0xd5ff, 0xc09e, 0x21, 0 + .dw 0xd640, 0xc09e, 0xd67f, 0xc09e, 0x21, 0 + .dw 0xd6c0, 0xc09e, 0xd6ff, 0xc09e, 0x21, 0 + .dw 0xd740, 0xc09e, 0xd77f, 0xc09e, 0x21, 0 + .dw 0xd7c0, 0xc09e, 0xd7ff, 0xc09e, 0x21, 0 + .dw 0xd840, 0xc09e, 0xd87f, 0xc09e, 0x21, 0 + .dw 0xd8c0, 0xc09e, 0xd8ff, 0xc09e, 0x21, 0 + .dw 0xd940, 0xc09e, 0xd97f, 0xc09e, 0x21, 0 + .dw 0xd9c0, 0xc09e, 0xdfff, 0xc09e, 0x21, 0 + .dw 0xe040, 0xc09e, 0xe07f, 0xc09e, 0x21, 0 + .dw 0xe0c0, 0xc09e, 0xe0ff, 0xc09e, 0x21, 0 + .dw 0xe140, 0xc09e, 0xe17f, 0xc09e, 0x21, 0 + .dw 0xe1c0, 0xc09e, 0xe1ff, 0xc09e, 0x21, 0 + .dw 0xe240, 0xc09e, 0xe27f, 0xc09e, 0x21, 0 + .dw 0xe2c0, 0xc09e, 0xe2ff, 0xc09e, 0x21, 0 + .dw 0xe340, 0xc09e, 0xe37f, 0xc09e, 0x21, 0 + .dw 0xe3c0, 0xc09e, 0xe3ff, 0xc09e, 0x21, 0 + .dw 0xe440, 0xc09e, 0xe47f, 0xc09e, 0x21, 0 + .dw 0xe4c0, 0xc09e, 0xe4ff, 0xc09e, 0x21, 0 + .dw 0xe540, 0xc09e, 0xe57f, 0xc09e, 0x21, 0 + .dw 0xe5c0, 0xc09e, 0xe5ff, 0xc09e, 0x21, 0 + .dw 0xe640, 0xc09e, 0xe67f, 0xc09e, 0x21, 0 + .dw 0xe6c0, 0xc09e, 0xe6ff, 0xc09e, 0x21, 0 + .dw 0xe740, 0xc09e, 0xe77f, 0xc09e, 0x21, 0 + .dw 0xe7c0, 0xc09e, 0xe7ff, 0xc09e, 0x21, 0 + .dw 0xe840, 0xc09e, 0xe87f, 0xc09e, 0x21, 0 + .dw 0xe8c0, 0xc09e, 0xe8ff, 0xc09e, 0x21, 0 + .dw 0xe940, 0xc09e, 0xe97f, 0xc09e, 0x21, 0 + .dw 0xe9c0, 0xc09e, 0xe9ff, 0xc09e, 0x21, 0 + .dw 0xea40, 0xc09e, 0xea7f, 0xc09e, 0x21, 0 + .dw 0xeac0, 0xc09e, 0xeaff, 0xc09e, 0x21, 0 + .dw 0xeb40, 0xc09e, 0xeb7f, 0xc09e, 0x21, 0 + .dw 0xebc0, 0xc09e, 0xebff, 0xc09e, 0x21, 0 + .dw 0xec40, 0xc09e, 0xec7f, 0xc09e, 0x21, 0 + .dw 0xecc0, 0xc09e, 0xecff, 0xc09e, 0x21, 0 + .dw 0xed40, 0xc09e, 0xed7f, 0xc09e, 0x21, 0 + .dw 0xedc0, 0xc09e, 0xedff, 0xc09e, 0x21, 0 + .dw 0xee40, 0xc09e, 0xee7f, 0xc09e, 0x21, 0 + .dw 0xeec0, 0xc09e, 0xeeff, 0xc09e, 0x21, 0 + .dw 0xef40, 0xc09e, 0xef7f, 0xc09e, 0x21, 0 + .dw 0xefc0, 0xc09e, 0xefff, 0xc09e, 0x21, 0 + .dw 0xf040, 0xc09e, 0xf07f, 0xc09e, 0x21, 0 + .dw 0xf0c0, 0xc09e, 0xf0ff, 0xc09e, 0x21, 0 + .dw 0xf140, 0xc09e, 0xf17f, 0xc09e, 0x21, 0 + .dw 0xf1c0, 0xc09e, 0xf1ff, 0xc09e, 0x21, 0 + .dw 0xf240, 0xc09e, 0xf27f, 0xc09e, 0x21, 0 + .dw 0xf2c0, 0xc09e, 0xf2ff, 0xc09e, 0x21, 0 + .dw 0xf340, 0xc09e, 0xf37f, 0xc09e, 0x21, 0 + .dw 0xf3c0, 0xc09e, 0xf3ff, 0xc09e, 0x21, 0 + .dw 0xf440, 0xc09e, 0xf47f, 0xc09e, 0x21, 0 + .dw 0xf4c0, 0xc09e, 0xf4ff, 0xc09e, 0x21, 0 + .dw 0xf540, 0xc09e, 0xf57f, 0xc09e, 0x21, 0 + .dw 0xf5c0, 0xc09e, 0xf5ff, 0xc09e, 0x21, 0 + .dw 0xf640, 0xc09e, 0xf67f, 0xc09e, 0x21, 0 + .dw 0xf6c0, 0xc09e, 0xf6ff, 0xc09e, 0x21, 0 + .dw 0xf740, 0xc09e, 0xf77f, 0xc09e, 0x21, 0 + .dw 0xf7c0, 0xc09e, 0xf7ff, 0xc09e, 0x21, 0 + .dw 0xf840, 0xc09e, 0xf87f, 0xc09e, 0x21, 0 + .dw 0xf8c0, 0xc09e, 0xf8ff, 0xc09e, 0x21, 0 + .dw 0xf940, 0xc09e, 0xf97f, 0xc09e, 0x21, 0 + .dw 0xf9c0, 0xc09e, 0xffff, 0xc09e, 0x21, 0 + .dw 0x0040, 0xc09f, 0x007f, 0xc09f, 0x21, 0 + .dw 0x00c0, 0xc09f, 0x00ff, 0xc09f, 0x21, 0 + .dw 0x0140, 0xc09f, 0x017f, 0xc09f, 0x21, 0 + .dw 0x01c0, 0xc09f, 0x01ff, 0xc09f, 0x21, 0 + .dw 0x0240, 0xc09f, 0x027f, 0xc09f, 0x21, 0 + .dw 0x02c0, 0xc09f, 0x02ff, 0xc09f, 0x21, 0 + .dw 0x0340, 0xc09f, 0x037f, 0xc09f, 0x21, 0 + .dw 0x03c0, 0xc09f, 0x03ff, 0xc09f, 0x21, 0 + .dw 0x0440, 0xc09f, 0x047f, 0xc09f, 0x21, 0 + .dw 0x04c0, 0xc09f, 0x04ff, 0xc09f, 0x21, 0 + .dw 0x0540, 0xc09f, 0x057f, 0xc09f, 0x21, 0 + .dw 0x05c0, 0xc09f, 0x05ff, 0xc09f, 0x21, 0 + .dw 0x0640, 0xc09f, 0x067f, 0xc09f, 0x21, 0 + .dw 0x06c0, 0xc09f, 0x06ff, 0xc09f, 0x21, 0 + .dw 0x0740, 0xc09f, 0x077f, 0xc09f, 0x21, 0 + .dw 0x07c0, 0xc09f, 0x07ff, 0xc09f, 0x21, 0 + .dw 0x0840, 0xc09f, 0x087f, 0xc09f, 0x21, 0 + .dw 0x08c0, 0xc09f, 0x08ff, 0xc09f, 0x21, 0 + .dw 0x0940, 0xc09f, 0x097f, 0xc09f, 0x21, 0 + .dw 0x09c0, 0xc09f, 0x09ff, 0xc09f, 0x21, 0 + .dw 0x0a40, 0xc09f, 0x0a7f, 0xc09f, 0x21, 0 + .dw 0x0ac0, 0xc09f, 0x0aff, 0xc09f, 0x21, 0 + .dw 0x0b40, 0xc09f, 0x0b7f, 0xc09f, 0x21, 0 + .dw 0x0bc0, 0xc09f, 0x0bff, 0xc09f, 0x21, 0 + .dw 0x0c40, 0xc09f, 0x0c7f, 0xc09f, 0x21, 0 + .dw 0x0cc0, 0xc09f, 0x0cff, 0xc09f, 0x21, 0 + .dw 0x0d40, 0xc09f, 0x0d7f, 0xc09f, 0x21, 0 + .dw 0x0dc0, 0xc09f, 0x0dff, 0xc09f, 0x21, 0 + .dw 0x0e40, 0xc09f, 0x0e7f, 0xc09f, 0x21, 0 + .dw 0x0ec0, 0xc09f, 0x0eff, 0xc09f, 0x21, 0 + .dw 0x0f40, 0xc09f, 0x0f7f, 0xc09f, 0x21, 0 + .dw 0x0fc0, 0xc09f, 0x0fff, 0xc09f, 0x21, 0 + .dw 0x1040, 0xc09f, 0x107f, 0xc09f, 0x21, 0 + .dw 0x10c0, 0xc09f, 0x10ff, 0xc09f, 0x21, 0 + .dw 0x1140, 0xc09f, 0x117f, 0xc09f, 0x21, 0 + .dw 0x11c0, 0xc09f, 0x11ff, 0xc09f, 0x21, 0 + .dw 0x1240, 0xc09f, 0x127f, 0xc09f, 0x21, 0 + .dw 0x12c0, 0xc09f, 0x12ff, 0xc09f, 0x21, 0 + .dw 0x1340, 0xc09f, 0x137f, 0xc09f, 0x21, 0 + .dw 0x13c0, 0xc09f, 0x13ff, 0xc09f, 0x21, 0 + .dw 0x1440, 0xc09f, 0x147f, 0xc09f, 0x21, 0 + .dw 0x14c0, 0xc09f, 0x14ff, 0xc09f, 0x21, 0 + .dw 0x1540, 0xc09f, 0x157f, 0xc09f, 0x21, 0 + .dw 0x15c0, 0xc09f, 0x15ff, 0xc09f, 0x21, 0 + .dw 0x1640, 0xc09f, 0x167f, 0xc09f, 0x21, 0 + .dw 0x16c0, 0xc09f, 0x16ff, 0xc09f, 0x21, 0 + .dw 0x1740, 0xc09f, 0x177f, 0xc09f, 0x21, 0 + .dw 0x17c0, 0xc09f, 0x17ff, 0xc09f, 0x21, 0 + .dw 0x1840, 0xc09f, 0x187f, 0xc09f, 0x21, 0 + .dw 0x18c0, 0xc09f, 0x18ff, 0xc09f, 0x21, 0 + .dw 0x1940, 0xc09f, 0x197f, 0xc09f, 0x21, 0 + .dw 0x19c0, 0xc09f, 0x1fff, 0xc09f, 0x21, 0 + .dw 0x2040, 0xc09f, 0x207f, 0xc09f, 0x21, 0 + .dw 0x20c0, 0xc09f, 0x20ff, 0xc09f, 0x21, 0 + .dw 0x2140, 0xc09f, 0x217f, 0xc09f, 0x21, 0 + .dw 0x21c0, 0xc09f, 0x21ff, 0xc09f, 0x21, 0 + .dw 0x2240, 0xc09f, 0x227f, 0xc09f, 0x21, 0 + .dw 0x22c0, 0xc09f, 0x22ff, 0xc09f, 0x21, 0 + .dw 0x2340, 0xc09f, 0x237f, 0xc09f, 0x21, 0 + .dw 0x23c0, 0xc09f, 0x23ff, 0xc09f, 0x21, 0 + .dw 0x2440, 0xc09f, 0x247f, 0xc09f, 0x21, 0 + .dw 0x24c0, 0xc09f, 0x24ff, 0xc09f, 0x21, 0 + .dw 0x2540, 0xc09f, 0x257f, 0xc09f, 0x21, 0 + .dw 0x25c0, 0xc09f, 0x25ff, 0xc09f, 0x21, 0 + .dw 0x2640, 0xc09f, 0x267f, 0xc09f, 0x21, 0 + .dw 0x26c0, 0xc09f, 0x26ff, 0xc09f, 0x21, 0 + .dw 0x2740, 0xc09f, 0x277f, 0xc09f, 0x21, 0 + .dw 0x27c0, 0xc09f, 0x27ff, 0xc09f, 0x21, 0 + .dw 0x2840, 0xc09f, 0x287f, 0xc09f, 0x21, 0 + .dw 0x28c0, 0xc09f, 0x28ff, 0xc09f, 0x21, 0 + .dw 0x2940, 0xc09f, 0x297f, 0xc09f, 0x21, 0 + .dw 0x29c0, 0xc09f, 0x29ff, 0xc09f, 0x21, 0 + .dw 0x2a40, 0xc09f, 0x2a7f, 0xc09f, 0x21, 0 + .dw 0x2ac0, 0xc09f, 0x2aff, 0xc09f, 0x21, 0 + .dw 0x2b40, 0xc09f, 0x2b7f, 0xc09f, 0x21, 0 + .dw 0x2bc0, 0xc09f, 0x2bff, 0xc09f, 0x21, 0 + .dw 0x2c40, 0xc09f, 0x2c7f, 0xc09f, 0x21, 0 + .dw 0x2cc0, 0xc09f, 0x2cff, 0xc09f, 0x21, 0 + .dw 0x2d40, 0xc09f, 0x2d7f, 0xc09f, 0x21, 0 + .dw 0x2dc0, 0xc09f, 0x2dff, 0xc09f, 0x21, 0 + .dw 0x2e40, 0xc09f, 0x2e7f, 0xc09f, 0x21, 0 + .dw 0x2ec0, 0xc09f, 0x2eff, 0xc09f, 0x21, 0 + .dw 0x2f40, 0xc09f, 0x2f7f, 0xc09f, 0x21, 0 + .dw 0x2fc0, 0xc09f, 0x2fff, 0xc09f, 0x21, 0 + .dw 0x3040, 0xc09f, 0x307f, 0xc09f, 0x21, 0 + .dw 0x30c0, 0xc09f, 0x30ff, 0xc09f, 0x21, 0 + .dw 0x3140, 0xc09f, 0x317f, 0xc09f, 0x21, 0 + .dw 0x31c0, 0xc09f, 0x31ff, 0xc09f, 0x21, 0 + .dw 0x3240, 0xc09f, 0x327f, 0xc09f, 0x21, 0 + .dw 0x32c0, 0xc09f, 0x32ff, 0xc09f, 0x21, 0 + .dw 0x3340, 0xc09f, 0x337f, 0xc09f, 0x21, 0 + .dw 0x33c0, 0xc09f, 0x33ff, 0xc09f, 0x21, 0 + .dw 0x3440, 0xc09f, 0x347f, 0xc09f, 0x21, 0 + .dw 0x34c0, 0xc09f, 0x34ff, 0xc09f, 0x21, 0 + .dw 0x3540, 0xc09f, 0x357f, 0xc09f, 0x21, 0 + .dw 0x35c0, 0xc09f, 0x35ff, 0xc09f, 0x21, 0 + .dw 0x3640, 0xc09f, 0x367f, 0xc09f, 0x21, 0 + .dw 0x36c0, 0xc09f, 0x36ff, 0xc09f, 0x21, 0 + .dw 0x3740, 0xc09f, 0x377f, 0xc09f, 0x21, 0 + .dw 0x37c0, 0xc09f, 0x37ff, 0xc09f, 0x21, 0 + .dw 0x3840, 0xc09f, 0x387f, 0xc09f, 0x21, 0 + .dw 0x38c0, 0xc09f, 0x38ff, 0xc09f, 0x21, 0 + .dw 0x3940, 0xc09f, 0x397f, 0xc09f, 0x21, 0 + .dw 0x39c0, 0xc09f, 0x1fff, 0xc0c0, 0x21, 0 + .dw 0x3a00, 0xc0c0, 0x5fff, 0xc0c0, 0x21, 0 + .dw 0x7a00, 0xc0c0, 0x9fff, 0xc0c0, 0x21, 0 + .dw 0xba00, 0xc0c0, 0xdfff, 0xc0c0, 0x21, 0 + .dw 0xfa00, 0xc0c0, 0x1fff, 0xc0c1, 0x21, 0 + .dw 0x3a00, 0xc0c1, 0x5fff, 0xc0c1, 0x21, 0 + .dw 0x7a00, 0xc0c1, 0x9fff, 0xc0c1, 0x21, 0 + .dw 0xba00, 0xc0c1, 0xdfff, 0xc0c1, 0x21, 0 + .dw 0xfa00, 0xc0c1, 0x1fff, 0xc0c2, 0x21, 0 + .dw 0x3a00, 0xc0c2, 0x5fff, 0xc0c2, 0x21, 0 + .dw 0x7a00, 0xc0c2, 0x9fff, 0xc0c2, 0x21, 0 + .dw 0xba00, 0xc0c2, 0xdfff, 0xc0c2, 0x21, 0 + .dw 0xfa00, 0xc0c2, 0x1fff, 0xc0c3, 0x21, 0 + .dw 0x3a00, 0xc0c3, 0xffff, 0xc0c3, 0x21, 0 + .dw 0x1a00, 0xc0c4, 0x1fff, 0xc0c4, 0x21, 0 + .dw 0x3a00, 0xc0c4, 0x3fff, 0xc0c4, 0x21, 0 + .dw 0x5a00, 0xc0c4, 0x5fff, 0xc0c4, 0x21, 0 + .dw 0x7a00, 0xc0c4, 0x7fff, 0xc0c4, 0x21, 0 + .dw 0x9a00, 0xc0c4, 0x9fff, 0xc0c4, 0x21, 0 + .dw 0xba00, 0xc0c4, 0xbfff, 0xc0c4, 0x21, 0 + .dw 0xda00, 0xc0c4, 0xdfff, 0xc0c4, 0x21, 0 + .dw 0xfa00, 0xc0c4, 0xffff, 0xc0c4, 0x21, 0 + .dw 0x1a00, 0xc0c5, 0x1fff, 0xc0c5, 0x21, 0 + .dw 0x3a00, 0xc0c5, 0x3fff, 0xc0c5, 0x21, 0 + .dw 0x5a00, 0xc0c5, 0x5fff, 0xc0c5, 0x21, 0 + .dw 0x7a00, 0xc0c5, 0x7fff, 0xc0c5, 0x21, 0 + .dw 0x9a00, 0xc0c5, 0x9fff, 0xc0c5, 0x21, 0 + .dw 0xba00, 0xc0c5, 0xbfff, 0xc0c5, 0x21, 0 + .dw 0xda00, 0xc0c5, 0xdfff, 0xc0c5, 0x21, 0 + .dw 0xfa00, 0xc0c5, 0xffff, 0xc0c5, 0x21, 0 + .dw 0x1a00, 0xc0c6, 0x1fff, 0xc0c6, 0x21, 0 + .dw 0x3a00, 0xc0c6, 0x3fff, 0xc0c6, 0x21, 0 + .dw 0x5a00, 0xc0c6, 0x5fff, 0xc0c6, 0x21, 0 + .dw 0x7a00, 0xc0c6, 0x7fff, 0xc0c6, 0x21, 0 + .dw 0x9a00, 0xc0c6, 0x9fff, 0xc0c6, 0x21, 0 + .dw 0xba00, 0xc0c6, 0xbfff, 0xc0c6, 0x21, 0 + .dw 0xda00, 0xc0c6, 0xdfff, 0xc0c6, 0x21, 0 + .dw 0xfa00, 0xc0c6, 0xffff, 0xc0c6, 0x21, 0 + .dw 0x1a00, 0xc0c7, 0x1fff, 0xc0c7, 0x21, 0 + .dw 0x3a00, 0xc0c7, 0x1fff, 0xc0d0, 0x21, 0 + .dw 0x3a00, 0xc0d0, 0x5fff, 0xc0d0, 0x21, 0 + .dw 0x7a00, 0xc0d0, 0x9fff, 0xc0d0, 0x21, 0 + .dw 0xba00, 0xc0d0, 0xdfff, 0xc0d0, 0x21, 0 + .dw 0xfa00, 0xc0d0, 0x1fff, 0xc0d1, 0x21, 0 + .dw 0x3a00, 0xc0d1, 0x5fff, 0xc0d1, 0x21, 0 + .dw 0x7a00, 0xc0d1, 0x9fff, 0xc0d1, 0x21, 0 + .dw 0xba00, 0xc0d1, 0xdfff, 0xc0d1, 0x21, 0 + .dw 0xfa00, 0xc0d1, 0x1fff, 0xc0d2, 0x21, 0 + .dw 0x3a00, 0xc0d2, 0x5fff, 0xc0d2, 0x21, 0 + .dw 0x7a00, 0xc0d2, 0x9fff, 0xc0d2, 0x21, 0 + .dw 0xba00, 0xc0d2, 0xdfff, 0xc0d2, 0x21, 0 + .dw 0xfa00, 0xc0d2, 0xffff, 0xc0d3, 0x21, 0 + .dw 0x1a00, 0xc0d4, 0x1fff, 0xc0d4, 0x21, 0 + .dw 0x3a00, 0xc0d4, 0x3fff, 0xc0d4, 0x21, 0 + .dw 0x5a00, 0xc0d4, 0x5fff, 0xc0d4, 0x21, 0 + .dw 0x7a00, 0xc0d4, 0x7fff, 0xc0d4, 0x21, 0 + .dw 0x9a00, 0xc0d4, 0x9fff, 0xc0d4, 0x21, 0 + .dw 0xba00, 0xc0d4, 0xbfff, 0xc0d4, 0x21, 0 + .dw 0xda00, 0xc0d4, 0xdfff, 0xc0d4, 0x21, 0 + .dw 0xfa00, 0xc0d4, 0xffff, 0xc0d4, 0x21, 0 + .dw 0x1a00, 0xc0d5, 0x1fff, 0xc0d5, 0x21, 0 + .dw 0x3a00, 0xc0d5, 0x3fff, 0xc0d5, 0x21, 0 + .dw 0x5a00, 0xc0d5, 0x5fff, 0xc0d5, 0x21, 0 + .dw 0x7a00, 0xc0d5, 0x7fff, 0xc0d5, 0x21, 0 + .dw 0x9a00, 0xc0d5, 0x9fff, 0xc0d5, 0x21, 0 + .dw 0xba00, 0xc0d5, 0xbfff, 0xc0d5, 0x21, 0 + .dw 0xda00, 0xc0d5, 0xdfff, 0xc0d5, 0x21, 0 + .dw 0xfa00, 0xc0d5, 0xffff, 0xc0d5, 0x21, 0 + .dw 0x1a00, 0xc0d6, 0x1fff, 0xc0d6, 0x21, 0 + .dw 0x3a00, 0xc0d6, 0x3fff, 0xc0d6, 0x21, 0 + .dw 0x5a00, 0xc0d6, 0x5fff, 0xc0d6, 0x21, 0 + .dw 0x7a00, 0xc0d6, 0x7fff, 0xc0d6, 0x21, 0 + .dw 0x9a00, 0xc0d6, 0x9fff, 0xc0d6, 0x21, 0 + .dw 0xba00, 0xc0d6, 0xbfff, 0xc0d6, 0x21, 0 + .dw 0xda00, 0xc0d6, 0xdfff, 0xc0d6, 0x21, 0 + .dw 0xfa00, 0xc0d6, 0xffff, 0xc0d6, 0x21, 0 + .dw 0x1a00, 0xc0d7, 0x1fff, 0xc0d7, 0x21, 0 + .dw 0x3a00, 0xc0d7, 0xffff, 0xc0ff, 0x21, 0 + .dw 0x1a00, 0xc100, 0x1fff, 0xc100, 0x21, 0 + .dw 0x3a00, 0xc100, 0x3fff, 0xc100, 0x21, 0 + .dw 0x5a00, 0xc100, 0x5fff, 0xc100, 0x21, 0 + .dw 0x7a00, 0xc100, 0x7fff, 0xc100, 0x21, 0 + .dw 0x9a00, 0xc100, 0x9fff, 0xc100, 0x21, 0 + .dw 0xba00, 0xc100, 0xbfff, 0xc100, 0x21, 0 + .dw 0xda00, 0xc100, 0xdfff, 0xc100, 0x21, 0 + .dw 0xfa00, 0xc100, 0xffff, 0xc100, 0x21, 0 + .dw 0x1a00, 0xc101, 0x1fff, 0xc101, 0x21, 0 + .dw 0x3a00, 0xc101, 0x3fff, 0xc101, 0x21, 0 + .dw 0x5a00, 0xc101, 0x5fff, 0xc101, 0x21, 0 + .dw 0x7a00, 0xc101, 0x7fff, 0xc101, 0x21, 0 + .dw 0x9a00, 0xc101, 0x9fff, 0xc101, 0x21, 0 + .dw 0xba00, 0xc101, 0xbfff, 0xc101, 0x21, 0 + .dw 0xda00, 0xc101, 0xdfff, 0xc101, 0x21, 0 + .dw 0xfa00, 0xc101, 0xffff, 0xc101, 0x21, 0 + .dw 0x1a00, 0xc102, 0x1fff, 0xc102, 0x21, 0 + .dw 0x3a00, 0xc102, 0x3fff, 0xc102, 0x21, 0 + .dw 0x5a00, 0xc102, 0x5fff, 0xc102, 0x21, 0 + .dw 0x7a00, 0xc102, 0x7fff, 0xc102, 0x21, 0 + .dw 0x9a00, 0xc102, 0x9fff, 0xc102, 0x21, 0 + .dw 0xba00, 0xc102, 0xbfff, 0xc102, 0x21, 0 + .dw 0xda00, 0xc102, 0xdfff, 0xc102, 0x21, 0 + .dw 0xfa00, 0xc102, 0xffff, 0xc102, 0x21, 0 + .dw 0x1a00, 0xc103, 0x1fff, 0xc103, 0x21, 0 + .dw 0x3a00, 0xc103, 0xffff, 0xc103, 0x21, 0 + .dw 0x1a00, 0xc104, 0x1fff, 0xc104, 0x21, 0 + .dw 0x3a00, 0xc104, 0x3fff, 0xc104, 0x21, 0 + .dw 0x5a00, 0xc104, 0x5fff, 0xc104, 0x21, 0 + .dw 0x7a00, 0xc104, 0x7fff, 0xc104, 0x21, 0 + .dw 0x9a00, 0xc104, 0x9fff, 0xc104, 0x21, 0 + .dw 0xba00, 0xc104, 0xbfff, 0xc104, 0x21, 0 + .dw 0xda00, 0xc104, 0xdfff, 0xc104, 0x21, 0 + .dw 0xfa00, 0xc104, 0xffff, 0xc104, 0x21, 0 + .dw 0x1a00, 0xc105, 0x1fff, 0xc105, 0x21, 0 + .dw 0x3a00, 0xc105, 0x3fff, 0xc105, 0x21, 0 + .dw 0x5a00, 0xc105, 0x5fff, 0xc105, 0x21, 0 + .dw 0x7a00, 0xc105, 0x7fff, 0xc105, 0x21, 0 + .dw 0x9a00, 0xc105, 0x9fff, 0xc105, 0x21, 0 + .dw 0xba00, 0xc105, 0xbfff, 0xc105, 0x21, 0 + .dw 0xda00, 0xc105, 0xdfff, 0xc105, 0x21, 0 + .dw 0xfa00, 0xc105, 0xffff, 0xc105, 0x21, 0 + .dw 0x1a00, 0xc106, 0x1fff, 0xc106, 0x21, 0 + .dw 0x3a00, 0xc106, 0x3fff, 0xc106, 0x21, 0 + .dw 0x5a00, 0xc106, 0x5fff, 0xc106, 0x21, 0 + .dw 0x7a00, 0xc106, 0x7fff, 0xc106, 0x21, 0 + .dw 0x9a00, 0xc106, 0x9fff, 0xc106, 0x21, 0 + .dw 0xba00, 0xc106, 0xbfff, 0xc106, 0x21, 0 + .dw 0xda00, 0xc106, 0xdfff, 0xc106, 0x21, 0 + .dw 0xfa00, 0xc106, 0xffff, 0xc106, 0x21, 0 + .dw 0x1a00, 0xc107, 0x1fff, 0xc107, 0x21, 0 + .dw 0x3a00, 0xc107, 0x1fff, 0xc108, 0x21, 0 + .dw 0x2040, 0xc108, 0x207f, 0xc108, 0x21, 0 + .dw 0x20c0, 0xc108, 0x20ff, 0xc108, 0x21, 0 + .dw 0x2140, 0xc108, 0x217f, 0xc108, 0x21, 0 + .dw 0x21c0, 0xc108, 0x21ff, 0xc108, 0x21, 0 + .dw 0x2240, 0xc108, 0x227f, 0xc108, 0x21, 0 + .dw 0x22c0, 0xc108, 0x22ff, 0xc108, 0x21, 0 + .dw 0x2340, 0xc108, 0x237f, 0xc108, 0x21, 0 + .dw 0x23c0, 0xc108, 0x23ff, 0xc108, 0x21, 0 + .dw 0x2440, 0xc108, 0x247f, 0xc108, 0x21, 0 + .dw 0x24c0, 0xc108, 0x24ff, 0xc108, 0x21, 0 + .dw 0x2540, 0xc108, 0x257f, 0xc108, 0x21, 0 + .dw 0x25c0, 0xc108, 0x25ff, 0xc108, 0x21, 0 + .dw 0x2640, 0xc108, 0x267f, 0xc108, 0x21, 0 + .dw 0x26c0, 0xc108, 0x26ff, 0xc108, 0x21, 0 + .dw 0x2740, 0xc108, 0x277f, 0xc108, 0x21, 0 + .dw 0x27c0, 0xc108, 0x27ff, 0xc108, 0x21, 0 + .dw 0x2840, 0xc108, 0x287f, 0xc108, 0x21, 0 + .dw 0x28c0, 0xc108, 0x28ff, 0xc108, 0x21, 0 + .dw 0x2940, 0xc108, 0x297f, 0xc108, 0x21, 0 + .dw 0x29c0, 0xc108, 0x29ff, 0xc108, 0x21, 0 + .dw 0x2a40, 0xc108, 0x2a7f, 0xc108, 0x21, 0 + .dw 0x2ac0, 0xc108, 0x2aff, 0xc108, 0x21, 0 + .dw 0x2b40, 0xc108, 0x2b7f, 0xc108, 0x21, 0 + .dw 0x2bc0, 0xc108, 0x2bff, 0xc108, 0x21, 0 + .dw 0x2c40, 0xc108, 0x2c7f, 0xc108, 0x21, 0 + .dw 0x2cc0, 0xc108, 0x2cff, 0xc108, 0x21, 0 + .dw 0x2d40, 0xc108, 0x2d7f, 0xc108, 0x21, 0 + .dw 0x2dc0, 0xc108, 0x2dff, 0xc108, 0x21, 0 + .dw 0x2e40, 0xc108, 0x2e7f, 0xc108, 0x21, 0 + .dw 0x2ec0, 0xc108, 0x2eff, 0xc108, 0x21, 0 + .dw 0x2f40, 0xc108, 0x2f7f, 0xc108, 0x21, 0 + .dw 0x2fc0, 0xc108, 0x2fff, 0xc108, 0x21, 0 + .dw 0x3040, 0xc108, 0x307f, 0xc108, 0x21, 0 + .dw 0x30c0, 0xc108, 0x30ff, 0xc108, 0x21, 0 + .dw 0x3140, 0xc108, 0x317f, 0xc108, 0x21, 0 + .dw 0x31c0, 0xc108, 0x31ff, 0xc108, 0x21, 0 + .dw 0x3240, 0xc108, 0x327f, 0xc108, 0x21, 0 + .dw 0x32c0, 0xc108, 0x32ff, 0xc108, 0x21, 0 + .dw 0x3340, 0xc108, 0x337f, 0xc108, 0x21, 0 + .dw 0x33c0, 0xc108, 0x33ff, 0xc108, 0x21, 0 + .dw 0x3440, 0xc108, 0x347f, 0xc108, 0x21, 0 + .dw 0x34c0, 0xc108, 0x34ff, 0xc108, 0x21, 0 + .dw 0x3540, 0xc108, 0x357f, 0xc108, 0x21, 0 + .dw 0x35c0, 0xc108, 0x35ff, 0xc108, 0x21, 0 + .dw 0x3640, 0xc108, 0x367f, 0xc108, 0x21, 0 + .dw 0x36c0, 0xc108, 0x36ff, 0xc108, 0x21, 0 + .dw 0x3740, 0xc108, 0x377f, 0xc108, 0x21, 0 + .dw 0x37c0, 0xc108, 0x37ff, 0xc108, 0x21, 0 + .dw 0x3840, 0xc108, 0x387f, 0xc108, 0x21, 0 + .dw 0x38c0, 0xc108, 0x38ff, 0xc108, 0x21, 0 + .dw 0x3940, 0xc108, 0x397f, 0xc108, 0x21, 0 + .dw 0x39c0, 0xc108, 0x5fff, 0xc108, 0x21, 0 + .dw 0x6040, 0xc108, 0x607f, 0xc108, 0x21, 0 + .dw 0x60c0, 0xc108, 0x60ff, 0xc108, 0x21, 0 + .dw 0x6140, 0xc108, 0x617f, 0xc108, 0x21, 0 + .dw 0x61c0, 0xc108, 0x61ff, 0xc108, 0x21, 0 + .dw 0x6240, 0xc108, 0x627f, 0xc108, 0x21, 0 + .dw 0x62c0, 0xc108, 0x62ff, 0xc108, 0x21, 0 + .dw 0x6340, 0xc108, 0x637f, 0xc108, 0x21, 0 + .dw 0x63c0, 0xc108, 0x63ff, 0xc108, 0x21, 0 + .dw 0x6440, 0xc108, 0x647f, 0xc108, 0x21, 0 + .dw 0x64c0, 0xc108, 0x64ff, 0xc108, 0x21, 0 + .dw 0x6540, 0xc108, 0x657f, 0xc108, 0x21, 0 + .dw 0x65c0, 0xc108, 0x65ff, 0xc108, 0x21, 0 + .dw 0x6640, 0xc108, 0x667f, 0xc108, 0x21, 0 + .dw 0x66c0, 0xc108, 0x66ff, 0xc108, 0x21, 0 + .dw 0x6740, 0xc108, 0x677f, 0xc108, 0x21, 0 + .dw 0x67c0, 0xc108, 0x67ff, 0xc108, 0x21, 0 + .dw 0x6840, 0xc108, 0x687f, 0xc108, 0x21, 0 + .dw 0x68c0, 0xc108, 0x68ff, 0xc108, 0x21, 0 + .dw 0x6940, 0xc108, 0x697f, 0xc108, 0x21, 0 + .dw 0x69c0, 0xc108, 0x69ff, 0xc108, 0x21, 0 + .dw 0x6a40, 0xc108, 0x6a7f, 0xc108, 0x21, 0 + .dw 0x6ac0, 0xc108, 0x6aff, 0xc108, 0x21, 0 + .dw 0x6b40, 0xc108, 0x6b7f, 0xc108, 0x21, 0 + .dw 0x6bc0, 0xc108, 0x6bff, 0xc108, 0x21, 0 + .dw 0x6c40, 0xc108, 0x6c7f, 0xc108, 0x21, 0 + .dw 0x6cc0, 0xc108, 0x6cff, 0xc108, 0x21, 0 + .dw 0x6d40, 0xc108, 0x6d7f, 0xc108, 0x21, 0 + .dw 0x6dc0, 0xc108, 0x6dff, 0xc108, 0x21, 0 + .dw 0x6e40, 0xc108, 0x6e7f, 0xc108, 0x21, 0 + .dw 0x6ec0, 0xc108, 0x6eff, 0xc108, 0x21, 0 + .dw 0x6f40, 0xc108, 0x6f7f, 0xc108, 0x21, 0 + .dw 0x6fc0, 0xc108, 0x6fff, 0xc108, 0x21, 0 + .dw 0x7040, 0xc108, 0x707f, 0xc108, 0x21, 0 + .dw 0x70c0, 0xc108, 0x70ff, 0xc108, 0x21, 0 + .dw 0x7140, 0xc108, 0x717f, 0xc108, 0x21, 0 + .dw 0x71c0, 0xc108, 0x71ff, 0xc108, 0x21, 0 + .dw 0x7240, 0xc108, 0x727f, 0xc108, 0x21, 0 + .dw 0x72c0, 0xc108, 0x72ff, 0xc108, 0x21, 0 + .dw 0x7340, 0xc108, 0x737f, 0xc108, 0x21, 0 + .dw 0x73c0, 0xc108, 0x73ff, 0xc108, 0x21, 0 + .dw 0x7440, 0xc108, 0x747f, 0xc108, 0x21, 0 + .dw 0x74c0, 0xc108, 0x74ff, 0xc108, 0x21, 0 + .dw 0x7540, 0xc108, 0x757f, 0xc108, 0x21, 0 + .dw 0x75c0, 0xc108, 0x75ff, 0xc108, 0x21, 0 + .dw 0x7640, 0xc108, 0x767f, 0xc108, 0x21, 0 + .dw 0x76c0, 0xc108, 0x76ff, 0xc108, 0x21, 0 + .dw 0x7740, 0xc108, 0x777f, 0xc108, 0x21, 0 + .dw 0x77c0, 0xc108, 0x77ff, 0xc108, 0x21, 0 + .dw 0x7840, 0xc108, 0x787f, 0xc108, 0x21, 0 + .dw 0x78c0, 0xc108, 0x78ff, 0xc108, 0x21, 0 + .dw 0x7940, 0xc108, 0x797f, 0xc108, 0x21, 0 + .dw 0x79c0, 0xc108, 0x9fff, 0xc108, 0x21, 0 + .dw 0xa040, 0xc108, 0xa07f, 0xc108, 0x21, 0 + .dw 0xa0c0, 0xc108, 0xa0ff, 0xc108, 0x21, 0 + .dw 0xa140, 0xc108, 0xa17f, 0xc108, 0x21, 0 + .dw 0xa1c0, 0xc108, 0xa1ff, 0xc108, 0x21, 0 + .dw 0xa240, 0xc108, 0xa27f, 0xc108, 0x21, 0 + .dw 0xa2c0, 0xc108, 0xa2ff, 0xc108, 0x21, 0 + .dw 0xa340, 0xc108, 0xa37f, 0xc108, 0x21, 0 + .dw 0xa3c0, 0xc108, 0xa3ff, 0xc108, 0x21, 0 + .dw 0xa440, 0xc108, 0xa47f, 0xc108, 0x21, 0 + .dw 0xa4c0, 0xc108, 0xa4ff, 0xc108, 0x21, 0 + .dw 0xa540, 0xc108, 0xa57f, 0xc108, 0x21, 0 + .dw 0xa5c0, 0xc108, 0xa5ff, 0xc108, 0x21, 0 + .dw 0xa640, 0xc108, 0xa67f, 0xc108, 0x21, 0 + .dw 0xa6c0, 0xc108, 0xa6ff, 0xc108, 0x21, 0 + .dw 0xa740, 0xc108, 0xa77f, 0xc108, 0x21, 0 + .dw 0xa7c0, 0xc108, 0xa7ff, 0xc108, 0x21, 0 + .dw 0xa840, 0xc108, 0xa87f, 0xc108, 0x21, 0 + .dw 0xa8c0, 0xc108, 0xa8ff, 0xc108, 0x21, 0 + .dw 0xa940, 0xc108, 0xa97f, 0xc108, 0x21, 0 + .dw 0xa9c0, 0xc108, 0xa9ff, 0xc108, 0x21, 0 + .dw 0xaa40, 0xc108, 0xaa7f, 0xc108, 0x21, 0 + .dw 0xaac0, 0xc108, 0xaaff, 0xc108, 0x21, 0 + .dw 0xab40, 0xc108, 0xab7f, 0xc108, 0x21, 0 + .dw 0xabc0, 0xc108, 0xabff, 0xc108, 0x21, 0 + .dw 0xac40, 0xc108, 0xac7f, 0xc108, 0x21, 0 + .dw 0xacc0, 0xc108, 0xacff, 0xc108, 0x21, 0 + .dw 0xad40, 0xc108, 0xad7f, 0xc108, 0x21, 0 + .dw 0xadc0, 0xc108, 0xadff, 0xc108, 0x21, 0 + .dw 0xae40, 0xc108, 0xae7f, 0xc108, 0x21, 0 + .dw 0xaec0, 0xc108, 0xaeff, 0xc108, 0x21, 0 + .dw 0xaf40, 0xc108, 0xaf7f, 0xc108, 0x21, 0 + .dw 0xafc0, 0xc108, 0xafff, 0xc108, 0x21, 0 + .dw 0xb040, 0xc108, 0xb07f, 0xc108, 0x21, 0 + .dw 0xb0c0, 0xc108, 0xb0ff, 0xc108, 0x21, 0 + .dw 0xb140, 0xc108, 0xb17f, 0xc108, 0x21, 0 + .dw 0xb1c0, 0xc108, 0xb1ff, 0xc108, 0x21, 0 + .dw 0xb240, 0xc108, 0xb27f, 0xc108, 0x21, 0 + .dw 0xb2c0, 0xc108, 0xb2ff, 0xc108, 0x21, 0 + .dw 0xb340, 0xc108, 0xb37f, 0xc108, 0x21, 0 + .dw 0xb3c0, 0xc108, 0xb3ff, 0xc108, 0x21, 0 + .dw 0xb440, 0xc108, 0xb47f, 0xc108, 0x21, 0 + .dw 0xb4c0, 0xc108, 0xb4ff, 0xc108, 0x21, 0 + .dw 0xb540, 0xc108, 0xb57f, 0xc108, 0x21, 0 + .dw 0xb5c0, 0xc108, 0xb5ff, 0xc108, 0x21, 0 + .dw 0xb640, 0xc108, 0xb67f, 0xc108, 0x21, 0 + .dw 0xb6c0, 0xc108, 0xb6ff, 0xc108, 0x21, 0 + .dw 0xb740, 0xc108, 0xb77f, 0xc108, 0x21, 0 + .dw 0xb7c0, 0xc108, 0xb7ff, 0xc108, 0x21, 0 + .dw 0xb840, 0xc108, 0xb87f, 0xc108, 0x21, 0 + .dw 0xb8c0, 0xc108, 0xb8ff, 0xc108, 0x21, 0 + .dw 0xb940, 0xc108, 0xb97f, 0xc108, 0x21, 0 + .dw 0xb9c0, 0xc108, 0xdfff, 0xc108, 0x21, 0 + .dw 0xe040, 0xc108, 0xe07f, 0xc108, 0x21, 0 + .dw 0xe0c0, 0xc108, 0xe0ff, 0xc108, 0x21, 0 + .dw 0xe140, 0xc108, 0xe17f, 0xc108, 0x21, 0 + .dw 0xe1c0, 0xc108, 0xe1ff, 0xc108, 0x21, 0 + .dw 0xe240, 0xc108, 0xe27f, 0xc108, 0x21, 0 + .dw 0xe2c0, 0xc108, 0xe2ff, 0xc108, 0x21, 0 + .dw 0xe340, 0xc108, 0xe37f, 0xc108, 0x21, 0 + .dw 0xe3c0, 0xc108, 0xe3ff, 0xc108, 0x21, 0 + .dw 0xe440, 0xc108, 0xe47f, 0xc108, 0x21, 0 + .dw 0xe4c0, 0xc108, 0xe4ff, 0xc108, 0x21, 0 + .dw 0xe540, 0xc108, 0xe57f, 0xc108, 0x21, 0 + .dw 0xe5c0, 0xc108, 0xe5ff, 0xc108, 0x21, 0 + .dw 0xe640, 0xc108, 0xe67f, 0xc108, 0x21, 0 + .dw 0xe6c0, 0xc108, 0xe6ff, 0xc108, 0x21, 0 + .dw 0xe740, 0xc108, 0xe77f, 0xc108, 0x21, 0 + .dw 0xe7c0, 0xc108, 0xe7ff, 0xc108, 0x21, 0 + .dw 0xe840, 0xc108, 0xe87f, 0xc108, 0x21, 0 + .dw 0xe8c0, 0xc108, 0xe8ff, 0xc108, 0x21, 0 + .dw 0xe940, 0xc108, 0xe97f, 0xc108, 0x21, 0 + .dw 0xe9c0, 0xc108, 0xe9ff, 0xc108, 0x21, 0 + .dw 0xea40, 0xc108, 0xea7f, 0xc108, 0x21, 0 + .dw 0xeac0, 0xc108, 0xeaff, 0xc108, 0x21, 0 + .dw 0xeb40, 0xc108, 0xeb7f, 0xc108, 0x21, 0 + .dw 0xebc0, 0xc108, 0xebff, 0xc108, 0x21, 0 + .dw 0xec40, 0xc108, 0xec7f, 0xc108, 0x21, 0 + .dw 0xecc0, 0xc108, 0xecff, 0xc108, 0x21, 0 + .dw 0xed40, 0xc108, 0xed7f, 0xc108, 0x21, 0 + .dw 0xedc0, 0xc108, 0xedff, 0xc108, 0x21, 0 + .dw 0xee40, 0xc108, 0xee7f, 0xc108, 0x21, 0 + .dw 0xeec0, 0xc108, 0xeeff, 0xc108, 0x21, 0 + .dw 0xef40, 0xc108, 0xef7f, 0xc108, 0x21, 0 + .dw 0xefc0, 0xc108, 0xefff, 0xc108, 0x21, 0 + .dw 0xf040, 0xc108, 0xf07f, 0xc108, 0x21, 0 + .dw 0xf0c0, 0xc108, 0xf0ff, 0xc108, 0x21, 0 + .dw 0xf140, 0xc108, 0xf17f, 0xc108, 0x21, 0 + .dw 0xf1c0, 0xc108, 0xf1ff, 0xc108, 0x21, 0 + .dw 0xf240, 0xc108, 0xf27f, 0xc108, 0x21, 0 + .dw 0xf2c0, 0xc108, 0xf2ff, 0xc108, 0x21, 0 + .dw 0xf340, 0xc108, 0xf37f, 0xc108, 0x21, 0 + .dw 0xf3c0, 0xc108, 0xf3ff, 0xc108, 0x21, 0 + .dw 0xf440, 0xc108, 0xf47f, 0xc108, 0x21, 0 + .dw 0xf4c0, 0xc108, 0xf4ff, 0xc108, 0x21, 0 + .dw 0xf540, 0xc108, 0xf57f, 0xc108, 0x21, 0 + .dw 0xf5c0, 0xc108, 0xf5ff, 0xc108, 0x21, 0 + .dw 0xf640, 0xc108, 0xf67f, 0xc108, 0x21, 0 + .dw 0xf6c0, 0xc108, 0xf6ff, 0xc108, 0x21, 0 + .dw 0xf740, 0xc108, 0xf77f, 0xc108, 0x21, 0 + .dw 0xf7c0, 0xc108, 0xf7ff, 0xc108, 0x21, 0 + .dw 0xf840, 0xc108, 0xf87f, 0xc108, 0x21, 0 + .dw 0xf8c0, 0xc108, 0xf8ff, 0xc108, 0x21, 0 + .dw 0xf940, 0xc108, 0xf97f, 0xc108, 0x21, 0 + .dw 0xf9c0, 0xc108, 0x1fff, 0xc109, 0x21, 0 + .dw 0x2040, 0xc109, 0x207f, 0xc109, 0x21, 0 + .dw 0x20c0, 0xc109, 0x20ff, 0xc109, 0x21, 0 + .dw 0x2140, 0xc109, 0x217f, 0xc109, 0x21, 0 + .dw 0x21c0, 0xc109, 0x21ff, 0xc109, 0x21, 0 + .dw 0x2240, 0xc109, 0x227f, 0xc109, 0x21, 0 + .dw 0x22c0, 0xc109, 0x22ff, 0xc109, 0x21, 0 + .dw 0x2340, 0xc109, 0x237f, 0xc109, 0x21, 0 + .dw 0x23c0, 0xc109, 0x23ff, 0xc109, 0x21, 0 + .dw 0x2440, 0xc109, 0x247f, 0xc109, 0x21, 0 + .dw 0x24c0, 0xc109, 0x24ff, 0xc109, 0x21, 0 + .dw 0x2540, 0xc109, 0x257f, 0xc109, 0x21, 0 + .dw 0x25c0, 0xc109, 0x25ff, 0xc109, 0x21, 0 + .dw 0x2640, 0xc109, 0x267f, 0xc109, 0x21, 0 + .dw 0x26c0, 0xc109, 0x26ff, 0xc109, 0x21, 0 + .dw 0x2740, 0xc109, 0x277f, 0xc109, 0x21, 0 + .dw 0x27c0, 0xc109, 0x27ff, 0xc109, 0x21, 0 + .dw 0x2840, 0xc109, 0x287f, 0xc109, 0x21, 0 + .dw 0x28c0, 0xc109, 0x28ff, 0xc109, 0x21, 0 + .dw 0x2940, 0xc109, 0x297f, 0xc109, 0x21, 0 + .dw 0x29c0, 0xc109, 0x29ff, 0xc109, 0x21, 0 + .dw 0x2a40, 0xc109, 0x2a7f, 0xc109, 0x21, 0 + .dw 0x2ac0, 0xc109, 0x2aff, 0xc109, 0x21, 0 + .dw 0x2b40, 0xc109, 0x2b7f, 0xc109, 0x21, 0 + .dw 0x2bc0, 0xc109, 0x2bff, 0xc109, 0x21, 0 + .dw 0x2c40, 0xc109, 0x2c7f, 0xc109, 0x21, 0 + .dw 0x2cc0, 0xc109, 0x2cff, 0xc109, 0x21, 0 + .dw 0x2d40, 0xc109, 0x2d7f, 0xc109, 0x21, 0 + .dw 0x2dc0, 0xc109, 0x2dff, 0xc109, 0x21, 0 + .dw 0x2e40, 0xc109, 0x2e7f, 0xc109, 0x21, 0 + .dw 0x2ec0, 0xc109, 0x2eff, 0xc109, 0x21, 0 + .dw 0x2f40, 0xc109, 0x2f7f, 0xc109, 0x21, 0 + .dw 0x2fc0, 0xc109, 0x2fff, 0xc109, 0x21, 0 + .dw 0x3040, 0xc109, 0x307f, 0xc109, 0x21, 0 + .dw 0x30c0, 0xc109, 0x30ff, 0xc109, 0x21, 0 + .dw 0x3140, 0xc109, 0x317f, 0xc109, 0x21, 0 + .dw 0x31c0, 0xc109, 0x31ff, 0xc109, 0x21, 0 + .dw 0x3240, 0xc109, 0x327f, 0xc109, 0x21, 0 + .dw 0x32c0, 0xc109, 0x32ff, 0xc109, 0x21, 0 + .dw 0x3340, 0xc109, 0x337f, 0xc109, 0x21, 0 + .dw 0x33c0, 0xc109, 0x33ff, 0xc109, 0x21, 0 + .dw 0x3440, 0xc109, 0x347f, 0xc109, 0x21, 0 + .dw 0x34c0, 0xc109, 0x34ff, 0xc109, 0x21, 0 + .dw 0x3540, 0xc109, 0x357f, 0xc109, 0x21, 0 + .dw 0x35c0, 0xc109, 0x35ff, 0xc109, 0x21, 0 + .dw 0x3640, 0xc109, 0x367f, 0xc109, 0x21, 0 + .dw 0x36c0, 0xc109, 0x36ff, 0xc109, 0x21, 0 + .dw 0x3740, 0xc109, 0x377f, 0xc109, 0x21, 0 + .dw 0x37c0, 0xc109, 0x37ff, 0xc109, 0x21, 0 + .dw 0x3840, 0xc109, 0x387f, 0xc109, 0x21, 0 + .dw 0x38c0, 0xc109, 0x38ff, 0xc109, 0x21, 0 + .dw 0x3940, 0xc109, 0x397f, 0xc109, 0x21, 0 + .dw 0x39c0, 0xc109, 0x5fff, 0xc109, 0x21, 0 + .dw 0x6040, 0xc109, 0x607f, 0xc109, 0x21, 0 + .dw 0x60c0, 0xc109, 0x60ff, 0xc109, 0x21, 0 + .dw 0x6140, 0xc109, 0x617f, 0xc109, 0x21, 0 + .dw 0x61c0, 0xc109, 0x61ff, 0xc109, 0x21, 0 + .dw 0x6240, 0xc109, 0x627f, 0xc109, 0x21, 0 + .dw 0x62c0, 0xc109, 0x62ff, 0xc109, 0x21, 0 + .dw 0x6340, 0xc109, 0x637f, 0xc109, 0x21, 0 + .dw 0x63c0, 0xc109, 0x63ff, 0xc109, 0x21, 0 + .dw 0x6440, 0xc109, 0x647f, 0xc109, 0x21, 0 + .dw 0x64c0, 0xc109, 0x64ff, 0xc109, 0x21, 0 + .dw 0x6540, 0xc109, 0x657f, 0xc109, 0x21, 0 + .dw 0x65c0, 0xc109, 0x65ff, 0xc109, 0x21, 0 + .dw 0x6640, 0xc109, 0x667f, 0xc109, 0x21, 0 + .dw 0x66c0, 0xc109, 0x66ff, 0xc109, 0x21, 0 + .dw 0x6740, 0xc109, 0x677f, 0xc109, 0x21, 0 + .dw 0x67c0, 0xc109, 0x67ff, 0xc109, 0x21, 0 + .dw 0x6840, 0xc109, 0x687f, 0xc109, 0x21, 0 + .dw 0x68c0, 0xc109, 0x68ff, 0xc109, 0x21, 0 + .dw 0x6940, 0xc109, 0x697f, 0xc109, 0x21, 0 + .dw 0x69c0, 0xc109, 0x69ff, 0xc109, 0x21, 0 + .dw 0x6a40, 0xc109, 0x6a7f, 0xc109, 0x21, 0 + .dw 0x6ac0, 0xc109, 0x6aff, 0xc109, 0x21, 0 + .dw 0x6b40, 0xc109, 0x6b7f, 0xc109, 0x21, 0 + .dw 0x6bc0, 0xc109, 0x6bff, 0xc109, 0x21, 0 + .dw 0x6c40, 0xc109, 0x6c7f, 0xc109, 0x21, 0 + .dw 0x6cc0, 0xc109, 0x6cff, 0xc109, 0x21, 0 + .dw 0x6d40, 0xc109, 0x6d7f, 0xc109, 0x21, 0 + .dw 0x6dc0, 0xc109, 0x6dff, 0xc109, 0x21, 0 + .dw 0x6e40, 0xc109, 0x6e7f, 0xc109, 0x21, 0 + .dw 0x6ec0, 0xc109, 0x6eff, 0xc109, 0x21, 0 + .dw 0x6f40, 0xc109, 0x6f7f, 0xc109, 0x21, 0 + .dw 0x6fc0, 0xc109, 0x6fff, 0xc109, 0x21, 0 + .dw 0x7040, 0xc109, 0x707f, 0xc109, 0x21, 0 + .dw 0x70c0, 0xc109, 0x70ff, 0xc109, 0x21, 0 + .dw 0x7140, 0xc109, 0x717f, 0xc109, 0x21, 0 + .dw 0x71c0, 0xc109, 0x71ff, 0xc109, 0x21, 0 + .dw 0x7240, 0xc109, 0x727f, 0xc109, 0x21, 0 + .dw 0x72c0, 0xc109, 0x72ff, 0xc109, 0x21, 0 + .dw 0x7340, 0xc109, 0x737f, 0xc109, 0x21, 0 + .dw 0x73c0, 0xc109, 0x73ff, 0xc109, 0x21, 0 + .dw 0x7440, 0xc109, 0x747f, 0xc109, 0x21, 0 + .dw 0x74c0, 0xc109, 0x74ff, 0xc109, 0x21, 0 + .dw 0x7540, 0xc109, 0x757f, 0xc109, 0x21, 0 + .dw 0x75c0, 0xc109, 0x75ff, 0xc109, 0x21, 0 + .dw 0x7640, 0xc109, 0x767f, 0xc109, 0x21, 0 + .dw 0x76c0, 0xc109, 0x76ff, 0xc109, 0x21, 0 + .dw 0x7740, 0xc109, 0x777f, 0xc109, 0x21, 0 + .dw 0x77c0, 0xc109, 0x77ff, 0xc109, 0x21, 0 + .dw 0x7840, 0xc109, 0x787f, 0xc109, 0x21, 0 + .dw 0x78c0, 0xc109, 0x78ff, 0xc109, 0x21, 0 + .dw 0x7940, 0xc109, 0x797f, 0xc109, 0x21, 0 + .dw 0x79c0, 0xc109, 0x9fff, 0xc109, 0x21, 0 + .dw 0xa040, 0xc109, 0xa07f, 0xc109, 0x21, 0 + .dw 0xa0c0, 0xc109, 0xa0ff, 0xc109, 0x21, 0 + .dw 0xa140, 0xc109, 0xa17f, 0xc109, 0x21, 0 + .dw 0xa1c0, 0xc109, 0xa1ff, 0xc109, 0x21, 0 + .dw 0xa240, 0xc109, 0xa27f, 0xc109, 0x21, 0 + .dw 0xa2c0, 0xc109, 0xa2ff, 0xc109, 0x21, 0 + .dw 0xa340, 0xc109, 0xa37f, 0xc109, 0x21, 0 + .dw 0xa3c0, 0xc109, 0xa3ff, 0xc109, 0x21, 0 + .dw 0xa440, 0xc109, 0xa47f, 0xc109, 0x21, 0 + .dw 0xa4c0, 0xc109, 0xa4ff, 0xc109, 0x21, 0 + .dw 0xa540, 0xc109, 0xa57f, 0xc109, 0x21, 0 + .dw 0xa5c0, 0xc109, 0xa5ff, 0xc109, 0x21, 0 + .dw 0xa640, 0xc109, 0xa67f, 0xc109, 0x21, 0 + .dw 0xa6c0, 0xc109, 0xa6ff, 0xc109, 0x21, 0 + .dw 0xa740, 0xc109, 0xa77f, 0xc109, 0x21, 0 + .dw 0xa7c0, 0xc109, 0xa7ff, 0xc109, 0x21, 0 + .dw 0xa840, 0xc109, 0xa87f, 0xc109, 0x21, 0 + .dw 0xa8c0, 0xc109, 0xa8ff, 0xc109, 0x21, 0 + .dw 0xa940, 0xc109, 0xa97f, 0xc109, 0x21, 0 + .dw 0xa9c0, 0xc109, 0xa9ff, 0xc109, 0x21, 0 + .dw 0xaa40, 0xc109, 0xaa7f, 0xc109, 0x21, 0 + .dw 0xaac0, 0xc109, 0xaaff, 0xc109, 0x21, 0 + .dw 0xab40, 0xc109, 0xab7f, 0xc109, 0x21, 0 + .dw 0xabc0, 0xc109, 0xabff, 0xc109, 0x21, 0 + .dw 0xac40, 0xc109, 0xac7f, 0xc109, 0x21, 0 + .dw 0xacc0, 0xc109, 0xacff, 0xc109, 0x21, 0 + .dw 0xad40, 0xc109, 0xad7f, 0xc109, 0x21, 0 + .dw 0xadc0, 0xc109, 0xadff, 0xc109, 0x21, 0 + .dw 0xae40, 0xc109, 0xae7f, 0xc109, 0x21, 0 + .dw 0xaec0, 0xc109, 0xaeff, 0xc109, 0x21, 0 + .dw 0xaf40, 0xc109, 0xaf7f, 0xc109, 0x21, 0 + .dw 0xafc0, 0xc109, 0xafff, 0xc109, 0x21, 0 + .dw 0xb040, 0xc109, 0xb07f, 0xc109, 0x21, 0 + .dw 0xb0c0, 0xc109, 0xb0ff, 0xc109, 0x21, 0 + .dw 0xb140, 0xc109, 0xb17f, 0xc109, 0x21, 0 + .dw 0xb1c0, 0xc109, 0xb1ff, 0xc109, 0x21, 0 + .dw 0xb240, 0xc109, 0xb27f, 0xc109, 0x21, 0 + .dw 0xb2c0, 0xc109, 0xb2ff, 0xc109, 0x21, 0 + .dw 0xb340, 0xc109, 0xb37f, 0xc109, 0x21, 0 + .dw 0xb3c0, 0xc109, 0xb3ff, 0xc109, 0x21, 0 + .dw 0xb440, 0xc109, 0xb47f, 0xc109, 0x21, 0 + .dw 0xb4c0, 0xc109, 0xb4ff, 0xc109, 0x21, 0 + .dw 0xb540, 0xc109, 0xb57f, 0xc109, 0x21, 0 + .dw 0xb5c0, 0xc109, 0xb5ff, 0xc109, 0x21, 0 + .dw 0xb640, 0xc109, 0xb67f, 0xc109, 0x21, 0 + .dw 0xb6c0, 0xc109, 0xb6ff, 0xc109, 0x21, 0 + .dw 0xb740, 0xc109, 0xb77f, 0xc109, 0x21, 0 + .dw 0xb7c0, 0xc109, 0xb7ff, 0xc109, 0x21, 0 + .dw 0xb840, 0xc109, 0xb87f, 0xc109, 0x21, 0 + .dw 0xb8c0, 0xc109, 0xb8ff, 0xc109, 0x21, 0 + .dw 0xb940, 0xc109, 0xb97f, 0xc109, 0x21, 0 + .dw 0xb9c0, 0xc109, 0xdfff, 0xc109, 0x21, 0 + .dw 0xe040, 0xc109, 0xe07f, 0xc109, 0x21, 0 + .dw 0xe0c0, 0xc109, 0xe0ff, 0xc109, 0x21, 0 + .dw 0xe140, 0xc109, 0xe17f, 0xc109, 0x21, 0 + .dw 0xe1c0, 0xc109, 0xe1ff, 0xc109, 0x21, 0 + .dw 0xe240, 0xc109, 0xe27f, 0xc109, 0x21, 0 + .dw 0xe2c0, 0xc109, 0xe2ff, 0xc109, 0x21, 0 + .dw 0xe340, 0xc109, 0xe37f, 0xc109, 0x21, 0 + .dw 0xe3c0, 0xc109, 0xe3ff, 0xc109, 0x21, 0 + .dw 0xe440, 0xc109, 0xe47f, 0xc109, 0x21, 0 + .dw 0xe4c0, 0xc109, 0xe4ff, 0xc109, 0x21, 0 + .dw 0xe540, 0xc109, 0xe57f, 0xc109, 0x21, 0 + .dw 0xe5c0, 0xc109, 0xe5ff, 0xc109, 0x21, 0 + .dw 0xe640, 0xc109, 0xe67f, 0xc109, 0x21, 0 + .dw 0xe6c0, 0xc109, 0xe6ff, 0xc109, 0x21, 0 + .dw 0xe740, 0xc109, 0xe77f, 0xc109, 0x21, 0 + .dw 0xe7c0, 0xc109, 0xe7ff, 0xc109, 0x21, 0 + .dw 0xe840, 0xc109, 0xe87f, 0xc109, 0x21, 0 + .dw 0xe8c0, 0xc109, 0xe8ff, 0xc109, 0x21, 0 + .dw 0xe940, 0xc109, 0xe97f, 0xc109, 0x21, 0 + .dw 0xe9c0, 0xc109, 0xe9ff, 0xc109, 0x21, 0 + .dw 0xea40, 0xc109, 0xea7f, 0xc109, 0x21, 0 + .dw 0xeac0, 0xc109, 0xeaff, 0xc109, 0x21, 0 + .dw 0xeb40, 0xc109, 0xeb7f, 0xc109, 0x21, 0 + .dw 0xebc0, 0xc109, 0xebff, 0xc109, 0x21, 0 + .dw 0xec40, 0xc109, 0xec7f, 0xc109, 0x21, 0 + .dw 0xecc0, 0xc109, 0xecff, 0xc109, 0x21, 0 + .dw 0xed40, 0xc109, 0xed7f, 0xc109, 0x21, 0 + .dw 0xedc0, 0xc109, 0xedff, 0xc109, 0x21, 0 + .dw 0xee40, 0xc109, 0xee7f, 0xc109, 0x21, 0 + .dw 0xeec0, 0xc109, 0xeeff, 0xc109, 0x21, 0 + .dw 0xef40, 0xc109, 0xef7f, 0xc109, 0x21, 0 + .dw 0xefc0, 0xc109, 0xefff, 0xc109, 0x21, 0 + .dw 0xf040, 0xc109, 0xf07f, 0xc109, 0x21, 0 + .dw 0xf0c0, 0xc109, 0xf0ff, 0xc109, 0x21, 0 + .dw 0xf140, 0xc109, 0xf17f, 0xc109, 0x21, 0 + .dw 0xf1c0, 0xc109, 0xf1ff, 0xc109, 0x21, 0 + .dw 0xf240, 0xc109, 0xf27f, 0xc109, 0x21, 0 + .dw 0xf2c0, 0xc109, 0xf2ff, 0xc109, 0x21, 0 + .dw 0xf340, 0xc109, 0xf37f, 0xc109, 0x21, 0 + .dw 0xf3c0, 0xc109, 0xf3ff, 0xc109, 0x21, 0 + .dw 0xf440, 0xc109, 0xf47f, 0xc109, 0x21, 0 + .dw 0xf4c0, 0xc109, 0xf4ff, 0xc109, 0x21, 0 + .dw 0xf540, 0xc109, 0xf57f, 0xc109, 0x21, 0 + .dw 0xf5c0, 0xc109, 0xf5ff, 0xc109, 0x21, 0 + .dw 0xf640, 0xc109, 0xf67f, 0xc109, 0x21, 0 + .dw 0xf6c0, 0xc109, 0xf6ff, 0xc109, 0x21, 0 + .dw 0xf740, 0xc109, 0xf77f, 0xc109, 0x21, 0 + .dw 0xf7c0, 0xc109, 0xf7ff, 0xc109, 0x21, 0 + .dw 0xf840, 0xc109, 0xf87f, 0xc109, 0x21, 0 + .dw 0xf8c0, 0xc109, 0xf8ff, 0xc109, 0x21, 0 + .dw 0xf940, 0xc109, 0xf97f, 0xc109, 0x21, 0 + .dw 0xf9c0, 0xc109, 0x1fff, 0xc10a, 0x21, 0 + .dw 0x2040, 0xc10a, 0x207f, 0xc10a, 0x21, 0 + .dw 0x20c0, 0xc10a, 0x20ff, 0xc10a, 0x21, 0 + .dw 0x2140, 0xc10a, 0x217f, 0xc10a, 0x21, 0 + .dw 0x21c0, 0xc10a, 0x21ff, 0xc10a, 0x21, 0 + .dw 0x2240, 0xc10a, 0x227f, 0xc10a, 0x21, 0 + .dw 0x22c0, 0xc10a, 0x22ff, 0xc10a, 0x21, 0 + .dw 0x2340, 0xc10a, 0x237f, 0xc10a, 0x21, 0 + .dw 0x23c0, 0xc10a, 0x23ff, 0xc10a, 0x21, 0 + .dw 0x2440, 0xc10a, 0x247f, 0xc10a, 0x21, 0 + .dw 0x24c0, 0xc10a, 0x24ff, 0xc10a, 0x21, 0 + .dw 0x2540, 0xc10a, 0x257f, 0xc10a, 0x21, 0 + .dw 0x25c0, 0xc10a, 0x25ff, 0xc10a, 0x21, 0 + .dw 0x2640, 0xc10a, 0x267f, 0xc10a, 0x21, 0 + .dw 0x26c0, 0xc10a, 0x26ff, 0xc10a, 0x21, 0 + .dw 0x2740, 0xc10a, 0x277f, 0xc10a, 0x21, 0 + .dw 0x27c0, 0xc10a, 0x27ff, 0xc10a, 0x21, 0 + .dw 0x2840, 0xc10a, 0x287f, 0xc10a, 0x21, 0 + .dw 0x28c0, 0xc10a, 0x28ff, 0xc10a, 0x21, 0 + .dw 0x2940, 0xc10a, 0x297f, 0xc10a, 0x21, 0 + .dw 0x29c0, 0xc10a, 0x29ff, 0xc10a, 0x21, 0 + .dw 0x2a40, 0xc10a, 0x2a7f, 0xc10a, 0x21, 0 + .dw 0x2ac0, 0xc10a, 0x2aff, 0xc10a, 0x21, 0 + .dw 0x2b40, 0xc10a, 0x2b7f, 0xc10a, 0x21, 0 + .dw 0x2bc0, 0xc10a, 0x2bff, 0xc10a, 0x21, 0 + .dw 0x2c40, 0xc10a, 0x2c7f, 0xc10a, 0x21, 0 + .dw 0x2cc0, 0xc10a, 0x2cff, 0xc10a, 0x21, 0 + .dw 0x2d40, 0xc10a, 0x2d7f, 0xc10a, 0x21, 0 + .dw 0x2dc0, 0xc10a, 0x2dff, 0xc10a, 0x21, 0 + .dw 0x2e40, 0xc10a, 0x2e7f, 0xc10a, 0x21, 0 + .dw 0x2ec0, 0xc10a, 0x2eff, 0xc10a, 0x21, 0 + .dw 0x2f40, 0xc10a, 0x2f7f, 0xc10a, 0x21, 0 + .dw 0x2fc0, 0xc10a, 0x2fff, 0xc10a, 0x21, 0 + .dw 0x3040, 0xc10a, 0x307f, 0xc10a, 0x21, 0 + .dw 0x30c0, 0xc10a, 0x30ff, 0xc10a, 0x21, 0 + .dw 0x3140, 0xc10a, 0x317f, 0xc10a, 0x21, 0 + .dw 0x31c0, 0xc10a, 0x31ff, 0xc10a, 0x21, 0 + .dw 0x3240, 0xc10a, 0x327f, 0xc10a, 0x21, 0 + .dw 0x32c0, 0xc10a, 0x32ff, 0xc10a, 0x21, 0 + .dw 0x3340, 0xc10a, 0x337f, 0xc10a, 0x21, 0 + .dw 0x33c0, 0xc10a, 0x33ff, 0xc10a, 0x21, 0 + .dw 0x3440, 0xc10a, 0x347f, 0xc10a, 0x21, 0 + .dw 0x34c0, 0xc10a, 0x34ff, 0xc10a, 0x21, 0 + .dw 0x3540, 0xc10a, 0x357f, 0xc10a, 0x21, 0 + .dw 0x35c0, 0xc10a, 0x35ff, 0xc10a, 0x21, 0 + .dw 0x3640, 0xc10a, 0x367f, 0xc10a, 0x21, 0 + .dw 0x36c0, 0xc10a, 0x36ff, 0xc10a, 0x21, 0 + .dw 0x3740, 0xc10a, 0x377f, 0xc10a, 0x21, 0 + .dw 0x37c0, 0xc10a, 0x37ff, 0xc10a, 0x21, 0 + .dw 0x3840, 0xc10a, 0x387f, 0xc10a, 0x21, 0 + .dw 0x38c0, 0xc10a, 0x38ff, 0xc10a, 0x21, 0 + .dw 0x3940, 0xc10a, 0x397f, 0xc10a, 0x21, 0 + .dw 0x39c0, 0xc10a, 0x5fff, 0xc10a, 0x21, 0 + .dw 0x6040, 0xc10a, 0x607f, 0xc10a, 0x21, 0 + .dw 0x60c0, 0xc10a, 0x60ff, 0xc10a, 0x21, 0 + .dw 0x6140, 0xc10a, 0x617f, 0xc10a, 0x21, 0 + .dw 0x61c0, 0xc10a, 0x61ff, 0xc10a, 0x21, 0 + .dw 0x6240, 0xc10a, 0x627f, 0xc10a, 0x21, 0 + .dw 0x62c0, 0xc10a, 0x62ff, 0xc10a, 0x21, 0 + .dw 0x6340, 0xc10a, 0x637f, 0xc10a, 0x21, 0 + .dw 0x63c0, 0xc10a, 0x63ff, 0xc10a, 0x21, 0 + .dw 0x6440, 0xc10a, 0x647f, 0xc10a, 0x21, 0 + .dw 0x64c0, 0xc10a, 0x64ff, 0xc10a, 0x21, 0 + .dw 0x6540, 0xc10a, 0x657f, 0xc10a, 0x21, 0 + .dw 0x65c0, 0xc10a, 0x65ff, 0xc10a, 0x21, 0 + .dw 0x6640, 0xc10a, 0x667f, 0xc10a, 0x21, 0 + .dw 0x66c0, 0xc10a, 0x66ff, 0xc10a, 0x21, 0 + .dw 0x6740, 0xc10a, 0x677f, 0xc10a, 0x21, 0 + .dw 0x67c0, 0xc10a, 0x67ff, 0xc10a, 0x21, 0 + .dw 0x6840, 0xc10a, 0x687f, 0xc10a, 0x21, 0 + .dw 0x68c0, 0xc10a, 0x68ff, 0xc10a, 0x21, 0 + .dw 0x6940, 0xc10a, 0x697f, 0xc10a, 0x21, 0 + .dw 0x69c0, 0xc10a, 0x69ff, 0xc10a, 0x21, 0 + .dw 0x6a40, 0xc10a, 0x6a7f, 0xc10a, 0x21, 0 + .dw 0x6ac0, 0xc10a, 0x6aff, 0xc10a, 0x21, 0 + .dw 0x6b40, 0xc10a, 0x6b7f, 0xc10a, 0x21, 0 + .dw 0x6bc0, 0xc10a, 0x6bff, 0xc10a, 0x21, 0 + .dw 0x6c40, 0xc10a, 0x6c7f, 0xc10a, 0x21, 0 + .dw 0x6cc0, 0xc10a, 0x6cff, 0xc10a, 0x21, 0 + .dw 0x6d40, 0xc10a, 0x6d7f, 0xc10a, 0x21, 0 + .dw 0x6dc0, 0xc10a, 0x6dff, 0xc10a, 0x21, 0 + .dw 0x6e40, 0xc10a, 0x6e7f, 0xc10a, 0x21, 0 + .dw 0x6ec0, 0xc10a, 0x6eff, 0xc10a, 0x21, 0 + .dw 0x6f40, 0xc10a, 0x6f7f, 0xc10a, 0x21, 0 + .dw 0x6fc0, 0xc10a, 0x6fff, 0xc10a, 0x21, 0 + .dw 0x7040, 0xc10a, 0x707f, 0xc10a, 0x21, 0 + .dw 0x70c0, 0xc10a, 0x70ff, 0xc10a, 0x21, 0 + .dw 0x7140, 0xc10a, 0x717f, 0xc10a, 0x21, 0 + .dw 0x71c0, 0xc10a, 0x71ff, 0xc10a, 0x21, 0 + .dw 0x7240, 0xc10a, 0x727f, 0xc10a, 0x21, 0 + .dw 0x72c0, 0xc10a, 0x72ff, 0xc10a, 0x21, 0 + .dw 0x7340, 0xc10a, 0x737f, 0xc10a, 0x21, 0 + .dw 0x73c0, 0xc10a, 0x73ff, 0xc10a, 0x21, 0 + .dw 0x7440, 0xc10a, 0x747f, 0xc10a, 0x21, 0 + .dw 0x74c0, 0xc10a, 0x74ff, 0xc10a, 0x21, 0 + .dw 0x7540, 0xc10a, 0x757f, 0xc10a, 0x21, 0 + .dw 0x75c0, 0xc10a, 0x75ff, 0xc10a, 0x21, 0 + .dw 0x7640, 0xc10a, 0x767f, 0xc10a, 0x21, 0 + .dw 0x76c0, 0xc10a, 0x76ff, 0xc10a, 0x21, 0 + .dw 0x7740, 0xc10a, 0x777f, 0xc10a, 0x21, 0 + .dw 0x77c0, 0xc10a, 0x77ff, 0xc10a, 0x21, 0 + .dw 0x7840, 0xc10a, 0x787f, 0xc10a, 0x21, 0 + .dw 0x78c0, 0xc10a, 0x78ff, 0xc10a, 0x21, 0 + .dw 0x7940, 0xc10a, 0x797f, 0xc10a, 0x21, 0 + .dw 0x79c0, 0xc10a, 0x9fff, 0xc10a, 0x21, 0 + .dw 0xa040, 0xc10a, 0xa07f, 0xc10a, 0x21, 0 + .dw 0xa0c0, 0xc10a, 0xa0ff, 0xc10a, 0x21, 0 + .dw 0xa140, 0xc10a, 0xa17f, 0xc10a, 0x21, 0 + .dw 0xa1c0, 0xc10a, 0xa1ff, 0xc10a, 0x21, 0 + .dw 0xa240, 0xc10a, 0xa27f, 0xc10a, 0x21, 0 + .dw 0xa2c0, 0xc10a, 0xa2ff, 0xc10a, 0x21, 0 + .dw 0xa340, 0xc10a, 0xa37f, 0xc10a, 0x21, 0 + .dw 0xa3c0, 0xc10a, 0xa3ff, 0xc10a, 0x21, 0 + .dw 0xa440, 0xc10a, 0xa47f, 0xc10a, 0x21, 0 + .dw 0xa4c0, 0xc10a, 0xa4ff, 0xc10a, 0x21, 0 + .dw 0xa540, 0xc10a, 0xa57f, 0xc10a, 0x21, 0 + .dw 0xa5c0, 0xc10a, 0xa5ff, 0xc10a, 0x21, 0 + .dw 0xa640, 0xc10a, 0xa67f, 0xc10a, 0x21, 0 + .dw 0xa6c0, 0xc10a, 0xa6ff, 0xc10a, 0x21, 0 + .dw 0xa740, 0xc10a, 0xa77f, 0xc10a, 0x21, 0 + .dw 0xa7c0, 0xc10a, 0xa7ff, 0xc10a, 0x21, 0 + .dw 0xa840, 0xc10a, 0xa87f, 0xc10a, 0x21, 0 + .dw 0xa8c0, 0xc10a, 0xa8ff, 0xc10a, 0x21, 0 + .dw 0xa940, 0xc10a, 0xa97f, 0xc10a, 0x21, 0 + .dw 0xa9c0, 0xc10a, 0xa9ff, 0xc10a, 0x21, 0 + .dw 0xaa40, 0xc10a, 0xaa7f, 0xc10a, 0x21, 0 + .dw 0xaac0, 0xc10a, 0xaaff, 0xc10a, 0x21, 0 + .dw 0xab40, 0xc10a, 0xab7f, 0xc10a, 0x21, 0 + .dw 0xabc0, 0xc10a, 0xabff, 0xc10a, 0x21, 0 + .dw 0xac40, 0xc10a, 0xac7f, 0xc10a, 0x21, 0 + .dw 0xacc0, 0xc10a, 0xacff, 0xc10a, 0x21, 0 + .dw 0xad40, 0xc10a, 0xad7f, 0xc10a, 0x21, 0 + .dw 0xadc0, 0xc10a, 0xadff, 0xc10a, 0x21, 0 + .dw 0xae40, 0xc10a, 0xae7f, 0xc10a, 0x21, 0 + .dw 0xaec0, 0xc10a, 0xaeff, 0xc10a, 0x21, 0 + .dw 0xaf40, 0xc10a, 0xaf7f, 0xc10a, 0x21, 0 + .dw 0xafc0, 0xc10a, 0xafff, 0xc10a, 0x21, 0 + .dw 0xb040, 0xc10a, 0xb07f, 0xc10a, 0x21, 0 + .dw 0xb0c0, 0xc10a, 0xb0ff, 0xc10a, 0x21, 0 + .dw 0xb140, 0xc10a, 0xb17f, 0xc10a, 0x21, 0 + .dw 0xb1c0, 0xc10a, 0xb1ff, 0xc10a, 0x21, 0 + .dw 0xb240, 0xc10a, 0xb27f, 0xc10a, 0x21, 0 + .dw 0xb2c0, 0xc10a, 0xb2ff, 0xc10a, 0x21, 0 + .dw 0xb340, 0xc10a, 0xb37f, 0xc10a, 0x21, 0 + .dw 0xb3c0, 0xc10a, 0xb3ff, 0xc10a, 0x21, 0 + .dw 0xb440, 0xc10a, 0xb47f, 0xc10a, 0x21, 0 + .dw 0xb4c0, 0xc10a, 0xb4ff, 0xc10a, 0x21, 0 + .dw 0xb540, 0xc10a, 0xb57f, 0xc10a, 0x21, 0 + .dw 0xb5c0, 0xc10a, 0xb5ff, 0xc10a, 0x21, 0 + .dw 0xb640, 0xc10a, 0xb67f, 0xc10a, 0x21, 0 + .dw 0xb6c0, 0xc10a, 0xb6ff, 0xc10a, 0x21, 0 + .dw 0xb740, 0xc10a, 0xb77f, 0xc10a, 0x21, 0 + .dw 0xb7c0, 0xc10a, 0xb7ff, 0xc10a, 0x21, 0 + .dw 0xb840, 0xc10a, 0xb87f, 0xc10a, 0x21, 0 + .dw 0xb8c0, 0xc10a, 0xb8ff, 0xc10a, 0x21, 0 + .dw 0xb940, 0xc10a, 0xb97f, 0xc10a, 0x21, 0 + .dw 0xb9c0, 0xc10a, 0xdfff, 0xc10a, 0x21, 0 + .dw 0xe040, 0xc10a, 0xe07f, 0xc10a, 0x21, 0 + .dw 0xe0c0, 0xc10a, 0xe0ff, 0xc10a, 0x21, 0 + .dw 0xe140, 0xc10a, 0xe17f, 0xc10a, 0x21, 0 + .dw 0xe1c0, 0xc10a, 0xe1ff, 0xc10a, 0x21, 0 + .dw 0xe240, 0xc10a, 0xe27f, 0xc10a, 0x21, 0 + .dw 0xe2c0, 0xc10a, 0xe2ff, 0xc10a, 0x21, 0 + .dw 0xe340, 0xc10a, 0xe37f, 0xc10a, 0x21, 0 + .dw 0xe3c0, 0xc10a, 0xe3ff, 0xc10a, 0x21, 0 + .dw 0xe440, 0xc10a, 0xe47f, 0xc10a, 0x21, 0 + .dw 0xe4c0, 0xc10a, 0xe4ff, 0xc10a, 0x21, 0 + .dw 0xe540, 0xc10a, 0xe57f, 0xc10a, 0x21, 0 + .dw 0xe5c0, 0xc10a, 0xe5ff, 0xc10a, 0x21, 0 + .dw 0xe640, 0xc10a, 0xe67f, 0xc10a, 0x21, 0 + .dw 0xe6c0, 0xc10a, 0xe6ff, 0xc10a, 0x21, 0 + .dw 0xe740, 0xc10a, 0xe77f, 0xc10a, 0x21, 0 + .dw 0xe7c0, 0xc10a, 0xe7ff, 0xc10a, 0x21, 0 + .dw 0xe840, 0xc10a, 0xe87f, 0xc10a, 0x21, 0 + .dw 0xe8c0, 0xc10a, 0xe8ff, 0xc10a, 0x21, 0 + .dw 0xe940, 0xc10a, 0xe97f, 0xc10a, 0x21, 0 + .dw 0xe9c0, 0xc10a, 0xe9ff, 0xc10a, 0x21, 0 + .dw 0xea40, 0xc10a, 0xea7f, 0xc10a, 0x21, 0 + .dw 0xeac0, 0xc10a, 0xeaff, 0xc10a, 0x21, 0 + .dw 0xeb40, 0xc10a, 0xeb7f, 0xc10a, 0x21, 0 + .dw 0xebc0, 0xc10a, 0xebff, 0xc10a, 0x21, 0 + .dw 0xec40, 0xc10a, 0xec7f, 0xc10a, 0x21, 0 + .dw 0xecc0, 0xc10a, 0xecff, 0xc10a, 0x21, 0 + .dw 0xed40, 0xc10a, 0xed7f, 0xc10a, 0x21, 0 + .dw 0xedc0, 0xc10a, 0xedff, 0xc10a, 0x21, 0 + .dw 0xee40, 0xc10a, 0xee7f, 0xc10a, 0x21, 0 + .dw 0xeec0, 0xc10a, 0xeeff, 0xc10a, 0x21, 0 + .dw 0xef40, 0xc10a, 0xef7f, 0xc10a, 0x21, 0 + .dw 0xefc0, 0xc10a, 0xefff, 0xc10a, 0x21, 0 + .dw 0xf040, 0xc10a, 0xf07f, 0xc10a, 0x21, 0 + .dw 0xf0c0, 0xc10a, 0xf0ff, 0xc10a, 0x21, 0 + .dw 0xf140, 0xc10a, 0xf17f, 0xc10a, 0x21, 0 + .dw 0xf1c0, 0xc10a, 0xf1ff, 0xc10a, 0x21, 0 + .dw 0xf240, 0xc10a, 0xf27f, 0xc10a, 0x21, 0 + .dw 0xf2c0, 0xc10a, 0xf2ff, 0xc10a, 0x21, 0 + .dw 0xf340, 0xc10a, 0xf37f, 0xc10a, 0x21, 0 + .dw 0xf3c0, 0xc10a, 0xf3ff, 0xc10a, 0x21, 0 + .dw 0xf440, 0xc10a, 0xf47f, 0xc10a, 0x21, 0 + .dw 0xf4c0, 0xc10a, 0xf4ff, 0xc10a, 0x21, 0 + .dw 0xf540, 0xc10a, 0xf57f, 0xc10a, 0x21, 0 + .dw 0xf5c0, 0xc10a, 0xf5ff, 0xc10a, 0x21, 0 + .dw 0xf640, 0xc10a, 0xf67f, 0xc10a, 0x21, 0 + .dw 0xf6c0, 0xc10a, 0xf6ff, 0xc10a, 0x21, 0 + .dw 0xf740, 0xc10a, 0xf77f, 0xc10a, 0x21, 0 + .dw 0xf7c0, 0xc10a, 0xf7ff, 0xc10a, 0x21, 0 + .dw 0xf840, 0xc10a, 0xf87f, 0xc10a, 0x21, 0 + .dw 0xf8c0, 0xc10a, 0xf8ff, 0xc10a, 0x21, 0 + .dw 0xf940, 0xc10a, 0xf97f, 0xc10a, 0x21, 0 + .dw 0xf9c0, 0xc10a, 0x1fff, 0xc10b, 0x21, 0 + .dw 0x2040, 0xc10b, 0x207f, 0xc10b, 0x21, 0 + .dw 0x20c0, 0xc10b, 0x20ff, 0xc10b, 0x21, 0 + .dw 0x2140, 0xc10b, 0x217f, 0xc10b, 0x21, 0 + .dw 0x21c0, 0xc10b, 0x21ff, 0xc10b, 0x21, 0 + .dw 0x2240, 0xc10b, 0x227f, 0xc10b, 0x21, 0 + .dw 0x22c0, 0xc10b, 0x22ff, 0xc10b, 0x21, 0 + .dw 0x2340, 0xc10b, 0x237f, 0xc10b, 0x21, 0 + .dw 0x23c0, 0xc10b, 0x23ff, 0xc10b, 0x21, 0 + .dw 0x2440, 0xc10b, 0x247f, 0xc10b, 0x21, 0 + .dw 0x24c0, 0xc10b, 0x24ff, 0xc10b, 0x21, 0 + .dw 0x2540, 0xc10b, 0x257f, 0xc10b, 0x21, 0 + .dw 0x25c0, 0xc10b, 0x25ff, 0xc10b, 0x21, 0 + .dw 0x2640, 0xc10b, 0x267f, 0xc10b, 0x21, 0 + .dw 0x26c0, 0xc10b, 0x26ff, 0xc10b, 0x21, 0 + .dw 0x2740, 0xc10b, 0x277f, 0xc10b, 0x21, 0 + .dw 0x27c0, 0xc10b, 0x27ff, 0xc10b, 0x21, 0 + .dw 0x2840, 0xc10b, 0x287f, 0xc10b, 0x21, 0 + .dw 0x28c0, 0xc10b, 0x28ff, 0xc10b, 0x21, 0 + .dw 0x2940, 0xc10b, 0x297f, 0xc10b, 0x21, 0 + .dw 0x29c0, 0xc10b, 0x29ff, 0xc10b, 0x21, 0 + .dw 0x2a40, 0xc10b, 0x2a7f, 0xc10b, 0x21, 0 + .dw 0x2ac0, 0xc10b, 0x2aff, 0xc10b, 0x21, 0 + .dw 0x2b40, 0xc10b, 0x2b7f, 0xc10b, 0x21, 0 + .dw 0x2bc0, 0xc10b, 0x2bff, 0xc10b, 0x21, 0 + .dw 0x2c40, 0xc10b, 0x2c7f, 0xc10b, 0x21, 0 + .dw 0x2cc0, 0xc10b, 0x2cff, 0xc10b, 0x21, 0 + .dw 0x2d40, 0xc10b, 0x2d7f, 0xc10b, 0x21, 0 + .dw 0x2dc0, 0xc10b, 0x2dff, 0xc10b, 0x21, 0 + .dw 0x2e40, 0xc10b, 0x2e7f, 0xc10b, 0x21, 0 + .dw 0x2ec0, 0xc10b, 0x2eff, 0xc10b, 0x21, 0 + .dw 0x2f40, 0xc10b, 0x2f7f, 0xc10b, 0x21, 0 + .dw 0x2fc0, 0xc10b, 0x2fff, 0xc10b, 0x21, 0 + .dw 0x3040, 0xc10b, 0x307f, 0xc10b, 0x21, 0 + .dw 0x30c0, 0xc10b, 0x30ff, 0xc10b, 0x21, 0 + .dw 0x3140, 0xc10b, 0x317f, 0xc10b, 0x21, 0 + .dw 0x31c0, 0xc10b, 0x31ff, 0xc10b, 0x21, 0 + .dw 0x3240, 0xc10b, 0x327f, 0xc10b, 0x21, 0 + .dw 0x32c0, 0xc10b, 0x32ff, 0xc10b, 0x21, 0 + .dw 0x3340, 0xc10b, 0x337f, 0xc10b, 0x21, 0 + .dw 0x33c0, 0xc10b, 0x33ff, 0xc10b, 0x21, 0 + .dw 0x3440, 0xc10b, 0x347f, 0xc10b, 0x21, 0 + .dw 0x34c0, 0xc10b, 0x34ff, 0xc10b, 0x21, 0 + .dw 0x3540, 0xc10b, 0x357f, 0xc10b, 0x21, 0 + .dw 0x35c0, 0xc10b, 0x35ff, 0xc10b, 0x21, 0 + .dw 0x3640, 0xc10b, 0x367f, 0xc10b, 0x21, 0 + .dw 0x36c0, 0xc10b, 0x36ff, 0xc10b, 0x21, 0 + .dw 0x3740, 0xc10b, 0x377f, 0xc10b, 0x21, 0 + .dw 0x37c0, 0xc10b, 0x37ff, 0xc10b, 0x21, 0 + .dw 0x3840, 0xc10b, 0x387f, 0xc10b, 0x21, 0 + .dw 0x38c0, 0xc10b, 0x38ff, 0xc10b, 0x21, 0 + .dw 0x3940, 0xc10b, 0x397f, 0xc10b, 0x21, 0 + .dw 0x39c0, 0xc10b, 0xffff, 0xc10b, 0x21, 0 + .dw 0x0040, 0xc10c, 0x007f, 0xc10c, 0x21, 0 + .dw 0x00c0, 0xc10c, 0x00ff, 0xc10c, 0x21, 0 + .dw 0x0140, 0xc10c, 0x017f, 0xc10c, 0x21, 0 + .dw 0x01c0, 0xc10c, 0x01ff, 0xc10c, 0x21, 0 + .dw 0x0240, 0xc10c, 0x027f, 0xc10c, 0x21, 0 + .dw 0x02c0, 0xc10c, 0x02ff, 0xc10c, 0x21, 0 + .dw 0x0340, 0xc10c, 0x037f, 0xc10c, 0x21, 0 + .dw 0x03c0, 0xc10c, 0x03ff, 0xc10c, 0x21, 0 + .dw 0x0440, 0xc10c, 0x047f, 0xc10c, 0x21, 0 + .dw 0x04c0, 0xc10c, 0x04ff, 0xc10c, 0x21, 0 + .dw 0x0540, 0xc10c, 0x057f, 0xc10c, 0x21, 0 + .dw 0x05c0, 0xc10c, 0x05ff, 0xc10c, 0x21, 0 + .dw 0x0640, 0xc10c, 0x067f, 0xc10c, 0x21, 0 + .dw 0x06c0, 0xc10c, 0x06ff, 0xc10c, 0x21, 0 + .dw 0x0740, 0xc10c, 0x077f, 0xc10c, 0x21, 0 + .dw 0x07c0, 0xc10c, 0x07ff, 0xc10c, 0x21, 0 + .dw 0x0840, 0xc10c, 0x087f, 0xc10c, 0x21, 0 + .dw 0x08c0, 0xc10c, 0x08ff, 0xc10c, 0x21, 0 + .dw 0x0940, 0xc10c, 0x097f, 0xc10c, 0x21, 0 + .dw 0x09c0, 0xc10c, 0x09ff, 0xc10c, 0x21, 0 + .dw 0x0a40, 0xc10c, 0x0a7f, 0xc10c, 0x21, 0 + .dw 0x0ac0, 0xc10c, 0x0aff, 0xc10c, 0x21, 0 + .dw 0x0b40, 0xc10c, 0x0b7f, 0xc10c, 0x21, 0 + .dw 0x0bc0, 0xc10c, 0x0bff, 0xc10c, 0x21, 0 + .dw 0x0c40, 0xc10c, 0x0c7f, 0xc10c, 0x21, 0 + .dw 0x0cc0, 0xc10c, 0x0cff, 0xc10c, 0x21, 0 + .dw 0x0d40, 0xc10c, 0x0d7f, 0xc10c, 0x21, 0 + .dw 0x0dc0, 0xc10c, 0x0dff, 0xc10c, 0x21, 0 + .dw 0x0e40, 0xc10c, 0x0e7f, 0xc10c, 0x21, 0 + .dw 0x0ec0, 0xc10c, 0x0eff, 0xc10c, 0x21, 0 + .dw 0x0f40, 0xc10c, 0x0f7f, 0xc10c, 0x21, 0 + .dw 0x0fc0, 0xc10c, 0x0fff, 0xc10c, 0x21, 0 + .dw 0x1040, 0xc10c, 0x107f, 0xc10c, 0x21, 0 + .dw 0x10c0, 0xc10c, 0x10ff, 0xc10c, 0x21, 0 + .dw 0x1140, 0xc10c, 0x117f, 0xc10c, 0x21, 0 + .dw 0x11c0, 0xc10c, 0x11ff, 0xc10c, 0x21, 0 + .dw 0x1240, 0xc10c, 0x127f, 0xc10c, 0x21, 0 + .dw 0x12c0, 0xc10c, 0x12ff, 0xc10c, 0x21, 0 + .dw 0x1340, 0xc10c, 0x137f, 0xc10c, 0x21, 0 + .dw 0x13c0, 0xc10c, 0x13ff, 0xc10c, 0x21, 0 + .dw 0x1440, 0xc10c, 0x147f, 0xc10c, 0x21, 0 + .dw 0x14c0, 0xc10c, 0x14ff, 0xc10c, 0x21, 0 + .dw 0x1540, 0xc10c, 0x157f, 0xc10c, 0x21, 0 + .dw 0x15c0, 0xc10c, 0x15ff, 0xc10c, 0x21, 0 + .dw 0x1640, 0xc10c, 0x167f, 0xc10c, 0x21, 0 + .dw 0x16c0, 0xc10c, 0x16ff, 0xc10c, 0x21, 0 + .dw 0x1740, 0xc10c, 0x177f, 0xc10c, 0x21, 0 + .dw 0x17c0, 0xc10c, 0x17ff, 0xc10c, 0x21, 0 + .dw 0x1840, 0xc10c, 0x187f, 0xc10c, 0x21, 0 + .dw 0x18c0, 0xc10c, 0x18ff, 0xc10c, 0x21, 0 + .dw 0x1940, 0xc10c, 0x197f, 0xc10c, 0x21, 0 + .dw 0x19c0, 0xc10c, 0x1fff, 0xc10c, 0x21, 0 + .dw 0x2040, 0xc10c, 0x207f, 0xc10c, 0x21, 0 + .dw 0x20c0, 0xc10c, 0x20ff, 0xc10c, 0x21, 0 + .dw 0x2140, 0xc10c, 0x217f, 0xc10c, 0x21, 0 + .dw 0x21c0, 0xc10c, 0x21ff, 0xc10c, 0x21, 0 + .dw 0x2240, 0xc10c, 0x227f, 0xc10c, 0x21, 0 + .dw 0x22c0, 0xc10c, 0x22ff, 0xc10c, 0x21, 0 + .dw 0x2340, 0xc10c, 0x237f, 0xc10c, 0x21, 0 + .dw 0x23c0, 0xc10c, 0x23ff, 0xc10c, 0x21, 0 + .dw 0x2440, 0xc10c, 0x247f, 0xc10c, 0x21, 0 + .dw 0x24c0, 0xc10c, 0x24ff, 0xc10c, 0x21, 0 + .dw 0x2540, 0xc10c, 0x257f, 0xc10c, 0x21, 0 + .dw 0x25c0, 0xc10c, 0x25ff, 0xc10c, 0x21, 0 + .dw 0x2640, 0xc10c, 0x267f, 0xc10c, 0x21, 0 + .dw 0x26c0, 0xc10c, 0x26ff, 0xc10c, 0x21, 0 + .dw 0x2740, 0xc10c, 0x277f, 0xc10c, 0x21, 0 + .dw 0x27c0, 0xc10c, 0x27ff, 0xc10c, 0x21, 0 + .dw 0x2840, 0xc10c, 0x287f, 0xc10c, 0x21, 0 + .dw 0x28c0, 0xc10c, 0x28ff, 0xc10c, 0x21, 0 + .dw 0x2940, 0xc10c, 0x297f, 0xc10c, 0x21, 0 + .dw 0x29c0, 0xc10c, 0x29ff, 0xc10c, 0x21, 0 + .dw 0x2a40, 0xc10c, 0x2a7f, 0xc10c, 0x21, 0 + .dw 0x2ac0, 0xc10c, 0x2aff, 0xc10c, 0x21, 0 + .dw 0x2b40, 0xc10c, 0x2b7f, 0xc10c, 0x21, 0 + .dw 0x2bc0, 0xc10c, 0x2bff, 0xc10c, 0x21, 0 + .dw 0x2c40, 0xc10c, 0x2c7f, 0xc10c, 0x21, 0 + .dw 0x2cc0, 0xc10c, 0x2cff, 0xc10c, 0x21, 0 + .dw 0x2d40, 0xc10c, 0x2d7f, 0xc10c, 0x21, 0 + .dw 0x2dc0, 0xc10c, 0x2dff, 0xc10c, 0x21, 0 + .dw 0x2e40, 0xc10c, 0x2e7f, 0xc10c, 0x21, 0 + .dw 0x2ec0, 0xc10c, 0x2eff, 0xc10c, 0x21, 0 + .dw 0x2f40, 0xc10c, 0x2f7f, 0xc10c, 0x21, 0 + .dw 0x2fc0, 0xc10c, 0x2fff, 0xc10c, 0x21, 0 + .dw 0x3040, 0xc10c, 0x307f, 0xc10c, 0x21, 0 + .dw 0x30c0, 0xc10c, 0x30ff, 0xc10c, 0x21, 0 + .dw 0x3140, 0xc10c, 0x317f, 0xc10c, 0x21, 0 + .dw 0x31c0, 0xc10c, 0x31ff, 0xc10c, 0x21, 0 + .dw 0x3240, 0xc10c, 0x327f, 0xc10c, 0x21, 0 + .dw 0x32c0, 0xc10c, 0x32ff, 0xc10c, 0x21, 0 + .dw 0x3340, 0xc10c, 0x337f, 0xc10c, 0x21, 0 + .dw 0x33c0, 0xc10c, 0x33ff, 0xc10c, 0x21, 0 + .dw 0x3440, 0xc10c, 0x347f, 0xc10c, 0x21, 0 + .dw 0x34c0, 0xc10c, 0x34ff, 0xc10c, 0x21, 0 + .dw 0x3540, 0xc10c, 0x357f, 0xc10c, 0x21, 0 + .dw 0x35c0, 0xc10c, 0x35ff, 0xc10c, 0x21, 0 + .dw 0x3640, 0xc10c, 0x367f, 0xc10c, 0x21, 0 + .dw 0x36c0, 0xc10c, 0x36ff, 0xc10c, 0x21, 0 + .dw 0x3740, 0xc10c, 0x377f, 0xc10c, 0x21, 0 + .dw 0x37c0, 0xc10c, 0x37ff, 0xc10c, 0x21, 0 + .dw 0x3840, 0xc10c, 0x387f, 0xc10c, 0x21, 0 + .dw 0x38c0, 0xc10c, 0x38ff, 0xc10c, 0x21, 0 + .dw 0x3940, 0xc10c, 0x397f, 0xc10c, 0x21, 0 + .dw 0x39c0, 0xc10c, 0x3fff, 0xc10c, 0x21, 0 + .dw 0x4040, 0xc10c, 0x407f, 0xc10c, 0x21, 0 + .dw 0x40c0, 0xc10c, 0x40ff, 0xc10c, 0x21, 0 + .dw 0x4140, 0xc10c, 0x417f, 0xc10c, 0x21, 0 + .dw 0x41c0, 0xc10c, 0x41ff, 0xc10c, 0x21, 0 + .dw 0x4240, 0xc10c, 0x427f, 0xc10c, 0x21, 0 + .dw 0x42c0, 0xc10c, 0x42ff, 0xc10c, 0x21, 0 + .dw 0x4340, 0xc10c, 0x437f, 0xc10c, 0x21, 0 + .dw 0x43c0, 0xc10c, 0x43ff, 0xc10c, 0x21, 0 + .dw 0x4440, 0xc10c, 0x447f, 0xc10c, 0x21, 0 + .dw 0x44c0, 0xc10c, 0x44ff, 0xc10c, 0x21, 0 + .dw 0x4540, 0xc10c, 0x457f, 0xc10c, 0x21, 0 + .dw 0x45c0, 0xc10c, 0x45ff, 0xc10c, 0x21, 0 + .dw 0x4640, 0xc10c, 0x467f, 0xc10c, 0x21, 0 + .dw 0x46c0, 0xc10c, 0x46ff, 0xc10c, 0x21, 0 + .dw 0x4740, 0xc10c, 0x477f, 0xc10c, 0x21, 0 + .dw 0x47c0, 0xc10c, 0x47ff, 0xc10c, 0x21, 0 + .dw 0x4840, 0xc10c, 0x487f, 0xc10c, 0x21, 0 + .dw 0x48c0, 0xc10c, 0x48ff, 0xc10c, 0x21, 0 + .dw 0x4940, 0xc10c, 0x497f, 0xc10c, 0x21, 0 + .dw 0x49c0, 0xc10c, 0x49ff, 0xc10c, 0x21, 0 + .dw 0x4a40, 0xc10c, 0x4a7f, 0xc10c, 0x21, 0 + .dw 0x4ac0, 0xc10c, 0x4aff, 0xc10c, 0x21, 0 + .dw 0x4b40, 0xc10c, 0x4b7f, 0xc10c, 0x21, 0 + .dw 0x4bc0, 0xc10c, 0x4bff, 0xc10c, 0x21, 0 + .dw 0x4c40, 0xc10c, 0x4c7f, 0xc10c, 0x21, 0 + .dw 0x4cc0, 0xc10c, 0x4cff, 0xc10c, 0x21, 0 + .dw 0x4d40, 0xc10c, 0x4d7f, 0xc10c, 0x21, 0 + .dw 0x4dc0, 0xc10c, 0x4dff, 0xc10c, 0x21, 0 + .dw 0x4e40, 0xc10c, 0x4e7f, 0xc10c, 0x21, 0 + .dw 0x4ec0, 0xc10c, 0x4eff, 0xc10c, 0x21, 0 + .dw 0x4f40, 0xc10c, 0x4f7f, 0xc10c, 0x21, 0 + .dw 0x4fc0, 0xc10c, 0x4fff, 0xc10c, 0x21, 0 + .dw 0x5040, 0xc10c, 0x507f, 0xc10c, 0x21, 0 + .dw 0x50c0, 0xc10c, 0x50ff, 0xc10c, 0x21, 0 + .dw 0x5140, 0xc10c, 0x517f, 0xc10c, 0x21, 0 + .dw 0x51c0, 0xc10c, 0x51ff, 0xc10c, 0x21, 0 + .dw 0x5240, 0xc10c, 0x527f, 0xc10c, 0x21, 0 + .dw 0x52c0, 0xc10c, 0x52ff, 0xc10c, 0x21, 0 + .dw 0x5340, 0xc10c, 0x537f, 0xc10c, 0x21, 0 + .dw 0x53c0, 0xc10c, 0x53ff, 0xc10c, 0x21, 0 + .dw 0x5440, 0xc10c, 0x547f, 0xc10c, 0x21, 0 + .dw 0x54c0, 0xc10c, 0x54ff, 0xc10c, 0x21, 0 + .dw 0x5540, 0xc10c, 0x557f, 0xc10c, 0x21, 0 + .dw 0x55c0, 0xc10c, 0x55ff, 0xc10c, 0x21, 0 + .dw 0x5640, 0xc10c, 0x567f, 0xc10c, 0x21, 0 + .dw 0x56c0, 0xc10c, 0x56ff, 0xc10c, 0x21, 0 + .dw 0x5740, 0xc10c, 0x577f, 0xc10c, 0x21, 0 + .dw 0x57c0, 0xc10c, 0x57ff, 0xc10c, 0x21, 0 + .dw 0x5840, 0xc10c, 0x587f, 0xc10c, 0x21, 0 + .dw 0x58c0, 0xc10c, 0x58ff, 0xc10c, 0x21, 0 + .dw 0x5940, 0xc10c, 0x597f, 0xc10c, 0x21, 0 + .dw 0x59c0, 0xc10c, 0x5fff, 0xc10c, 0x21, 0 + .dw 0x6040, 0xc10c, 0x607f, 0xc10c, 0x21, 0 + .dw 0x60c0, 0xc10c, 0x60ff, 0xc10c, 0x21, 0 + .dw 0x6140, 0xc10c, 0x617f, 0xc10c, 0x21, 0 + .dw 0x61c0, 0xc10c, 0x61ff, 0xc10c, 0x21, 0 + .dw 0x6240, 0xc10c, 0x627f, 0xc10c, 0x21, 0 + .dw 0x62c0, 0xc10c, 0x62ff, 0xc10c, 0x21, 0 + .dw 0x6340, 0xc10c, 0x637f, 0xc10c, 0x21, 0 + .dw 0x63c0, 0xc10c, 0x63ff, 0xc10c, 0x21, 0 + .dw 0x6440, 0xc10c, 0x647f, 0xc10c, 0x21, 0 + .dw 0x64c0, 0xc10c, 0x64ff, 0xc10c, 0x21, 0 + .dw 0x6540, 0xc10c, 0x657f, 0xc10c, 0x21, 0 + .dw 0x65c0, 0xc10c, 0x65ff, 0xc10c, 0x21, 0 + .dw 0x6640, 0xc10c, 0x667f, 0xc10c, 0x21, 0 + .dw 0x66c0, 0xc10c, 0x66ff, 0xc10c, 0x21, 0 + .dw 0x6740, 0xc10c, 0x677f, 0xc10c, 0x21, 0 + .dw 0x67c0, 0xc10c, 0x67ff, 0xc10c, 0x21, 0 + .dw 0x6840, 0xc10c, 0x687f, 0xc10c, 0x21, 0 + .dw 0x68c0, 0xc10c, 0x68ff, 0xc10c, 0x21, 0 + .dw 0x6940, 0xc10c, 0x697f, 0xc10c, 0x21, 0 + .dw 0x69c0, 0xc10c, 0x69ff, 0xc10c, 0x21, 0 + .dw 0x6a40, 0xc10c, 0x6a7f, 0xc10c, 0x21, 0 + .dw 0x6ac0, 0xc10c, 0x6aff, 0xc10c, 0x21, 0 + .dw 0x6b40, 0xc10c, 0x6b7f, 0xc10c, 0x21, 0 + .dw 0x6bc0, 0xc10c, 0x6bff, 0xc10c, 0x21, 0 + .dw 0x6c40, 0xc10c, 0x6c7f, 0xc10c, 0x21, 0 + .dw 0x6cc0, 0xc10c, 0x6cff, 0xc10c, 0x21, 0 + .dw 0x6d40, 0xc10c, 0x6d7f, 0xc10c, 0x21, 0 + .dw 0x6dc0, 0xc10c, 0x6dff, 0xc10c, 0x21, 0 + .dw 0x6e40, 0xc10c, 0x6e7f, 0xc10c, 0x21, 0 + .dw 0x6ec0, 0xc10c, 0x6eff, 0xc10c, 0x21, 0 + .dw 0x6f40, 0xc10c, 0x6f7f, 0xc10c, 0x21, 0 + .dw 0x6fc0, 0xc10c, 0x6fff, 0xc10c, 0x21, 0 + .dw 0x7040, 0xc10c, 0x707f, 0xc10c, 0x21, 0 + .dw 0x70c0, 0xc10c, 0x70ff, 0xc10c, 0x21, 0 + .dw 0x7140, 0xc10c, 0x717f, 0xc10c, 0x21, 0 + .dw 0x71c0, 0xc10c, 0x71ff, 0xc10c, 0x21, 0 + .dw 0x7240, 0xc10c, 0x727f, 0xc10c, 0x21, 0 + .dw 0x72c0, 0xc10c, 0x72ff, 0xc10c, 0x21, 0 + .dw 0x7340, 0xc10c, 0x737f, 0xc10c, 0x21, 0 + .dw 0x73c0, 0xc10c, 0x73ff, 0xc10c, 0x21, 0 + .dw 0x7440, 0xc10c, 0x747f, 0xc10c, 0x21, 0 + .dw 0x74c0, 0xc10c, 0x74ff, 0xc10c, 0x21, 0 + .dw 0x7540, 0xc10c, 0x757f, 0xc10c, 0x21, 0 + .dw 0x75c0, 0xc10c, 0x75ff, 0xc10c, 0x21, 0 + .dw 0x7640, 0xc10c, 0x767f, 0xc10c, 0x21, 0 + .dw 0x76c0, 0xc10c, 0x76ff, 0xc10c, 0x21, 0 + .dw 0x7740, 0xc10c, 0x777f, 0xc10c, 0x21, 0 + .dw 0x77c0, 0xc10c, 0x77ff, 0xc10c, 0x21, 0 + .dw 0x7840, 0xc10c, 0x787f, 0xc10c, 0x21, 0 + .dw 0x78c0, 0xc10c, 0x78ff, 0xc10c, 0x21, 0 + .dw 0x7940, 0xc10c, 0x797f, 0xc10c, 0x21, 0 + .dw 0x79c0, 0xc10c, 0x7fff, 0xc10c, 0x21, 0 + .dw 0x8040, 0xc10c, 0x807f, 0xc10c, 0x21, 0 + .dw 0x80c0, 0xc10c, 0x80ff, 0xc10c, 0x21, 0 + .dw 0x8140, 0xc10c, 0x817f, 0xc10c, 0x21, 0 + .dw 0x81c0, 0xc10c, 0x81ff, 0xc10c, 0x21, 0 + .dw 0x8240, 0xc10c, 0x827f, 0xc10c, 0x21, 0 + .dw 0x82c0, 0xc10c, 0x82ff, 0xc10c, 0x21, 0 + .dw 0x8340, 0xc10c, 0x837f, 0xc10c, 0x21, 0 + .dw 0x83c0, 0xc10c, 0x83ff, 0xc10c, 0x21, 0 + .dw 0x8440, 0xc10c, 0x847f, 0xc10c, 0x21, 0 + .dw 0x84c0, 0xc10c, 0x84ff, 0xc10c, 0x21, 0 + .dw 0x8540, 0xc10c, 0x857f, 0xc10c, 0x21, 0 + .dw 0x85c0, 0xc10c, 0x85ff, 0xc10c, 0x21, 0 + .dw 0x8640, 0xc10c, 0x867f, 0xc10c, 0x21, 0 + .dw 0x86c0, 0xc10c, 0x86ff, 0xc10c, 0x21, 0 + .dw 0x8740, 0xc10c, 0x877f, 0xc10c, 0x21, 0 + .dw 0x87c0, 0xc10c, 0x87ff, 0xc10c, 0x21, 0 + .dw 0x8840, 0xc10c, 0x887f, 0xc10c, 0x21, 0 + .dw 0x88c0, 0xc10c, 0x88ff, 0xc10c, 0x21, 0 + .dw 0x8940, 0xc10c, 0x897f, 0xc10c, 0x21, 0 + .dw 0x89c0, 0xc10c, 0x89ff, 0xc10c, 0x21, 0 + .dw 0x8a40, 0xc10c, 0x8a7f, 0xc10c, 0x21, 0 + .dw 0x8ac0, 0xc10c, 0x8aff, 0xc10c, 0x21, 0 + .dw 0x8b40, 0xc10c, 0x8b7f, 0xc10c, 0x21, 0 + .dw 0x8bc0, 0xc10c, 0x8bff, 0xc10c, 0x21, 0 + .dw 0x8c40, 0xc10c, 0x8c7f, 0xc10c, 0x21, 0 + .dw 0x8cc0, 0xc10c, 0x8cff, 0xc10c, 0x21, 0 + .dw 0x8d40, 0xc10c, 0x8d7f, 0xc10c, 0x21, 0 + .dw 0x8dc0, 0xc10c, 0x8dff, 0xc10c, 0x21, 0 + .dw 0x8e40, 0xc10c, 0x8e7f, 0xc10c, 0x21, 0 + .dw 0x8ec0, 0xc10c, 0x8eff, 0xc10c, 0x21, 0 + .dw 0x8f40, 0xc10c, 0x8f7f, 0xc10c, 0x21, 0 + .dw 0x8fc0, 0xc10c, 0x8fff, 0xc10c, 0x21, 0 + .dw 0x9040, 0xc10c, 0x907f, 0xc10c, 0x21, 0 + .dw 0x90c0, 0xc10c, 0x90ff, 0xc10c, 0x21, 0 + .dw 0x9140, 0xc10c, 0x917f, 0xc10c, 0x21, 0 + .dw 0x91c0, 0xc10c, 0x91ff, 0xc10c, 0x21, 0 + .dw 0x9240, 0xc10c, 0x927f, 0xc10c, 0x21, 0 + .dw 0x92c0, 0xc10c, 0x92ff, 0xc10c, 0x21, 0 + .dw 0x9340, 0xc10c, 0x937f, 0xc10c, 0x21, 0 + .dw 0x93c0, 0xc10c, 0x93ff, 0xc10c, 0x21, 0 + .dw 0x9440, 0xc10c, 0x947f, 0xc10c, 0x21, 0 + .dw 0x94c0, 0xc10c, 0x94ff, 0xc10c, 0x21, 0 + .dw 0x9540, 0xc10c, 0x957f, 0xc10c, 0x21, 0 + .dw 0x95c0, 0xc10c, 0x95ff, 0xc10c, 0x21, 0 + .dw 0x9640, 0xc10c, 0x967f, 0xc10c, 0x21, 0 + .dw 0x96c0, 0xc10c, 0x96ff, 0xc10c, 0x21, 0 + .dw 0x9740, 0xc10c, 0x977f, 0xc10c, 0x21, 0 + .dw 0x97c0, 0xc10c, 0x97ff, 0xc10c, 0x21, 0 + .dw 0x9840, 0xc10c, 0x987f, 0xc10c, 0x21, 0 + .dw 0x98c0, 0xc10c, 0x98ff, 0xc10c, 0x21, 0 + .dw 0x9940, 0xc10c, 0x997f, 0xc10c, 0x21, 0 + .dw 0x99c0, 0xc10c, 0x9fff, 0xc10c, 0x21, 0 + .dw 0xa040, 0xc10c, 0xa07f, 0xc10c, 0x21, 0 + .dw 0xa0c0, 0xc10c, 0xa0ff, 0xc10c, 0x21, 0 + .dw 0xa140, 0xc10c, 0xa17f, 0xc10c, 0x21, 0 + .dw 0xa1c0, 0xc10c, 0xa1ff, 0xc10c, 0x21, 0 + .dw 0xa240, 0xc10c, 0xa27f, 0xc10c, 0x21, 0 + .dw 0xa2c0, 0xc10c, 0xa2ff, 0xc10c, 0x21, 0 + .dw 0xa340, 0xc10c, 0xa37f, 0xc10c, 0x21, 0 + .dw 0xa3c0, 0xc10c, 0xa3ff, 0xc10c, 0x21, 0 + .dw 0xa440, 0xc10c, 0xa47f, 0xc10c, 0x21, 0 + .dw 0xa4c0, 0xc10c, 0xa4ff, 0xc10c, 0x21, 0 + .dw 0xa540, 0xc10c, 0xa57f, 0xc10c, 0x21, 0 + .dw 0xa5c0, 0xc10c, 0xa5ff, 0xc10c, 0x21, 0 + .dw 0xa640, 0xc10c, 0xa67f, 0xc10c, 0x21, 0 + .dw 0xa6c0, 0xc10c, 0xa6ff, 0xc10c, 0x21, 0 + .dw 0xa740, 0xc10c, 0xa77f, 0xc10c, 0x21, 0 + .dw 0xa7c0, 0xc10c, 0xa7ff, 0xc10c, 0x21, 0 + .dw 0xa840, 0xc10c, 0xa87f, 0xc10c, 0x21, 0 + .dw 0xa8c0, 0xc10c, 0xa8ff, 0xc10c, 0x21, 0 + .dw 0xa940, 0xc10c, 0xa97f, 0xc10c, 0x21, 0 + .dw 0xa9c0, 0xc10c, 0xa9ff, 0xc10c, 0x21, 0 + .dw 0xaa40, 0xc10c, 0xaa7f, 0xc10c, 0x21, 0 + .dw 0xaac0, 0xc10c, 0xaaff, 0xc10c, 0x21, 0 + .dw 0xab40, 0xc10c, 0xab7f, 0xc10c, 0x21, 0 + .dw 0xabc0, 0xc10c, 0xabff, 0xc10c, 0x21, 0 + .dw 0xac40, 0xc10c, 0xac7f, 0xc10c, 0x21, 0 + .dw 0xacc0, 0xc10c, 0xacff, 0xc10c, 0x21, 0 + .dw 0xad40, 0xc10c, 0xad7f, 0xc10c, 0x21, 0 + .dw 0xadc0, 0xc10c, 0xadff, 0xc10c, 0x21, 0 + .dw 0xae40, 0xc10c, 0xae7f, 0xc10c, 0x21, 0 + .dw 0xaec0, 0xc10c, 0xaeff, 0xc10c, 0x21, 0 + .dw 0xaf40, 0xc10c, 0xaf7f, 0xc10c, 0x21, 0 + .dw 0xafc0, 0xc10c, 0xafff, 0xc10c, 0x21, 0 + .dw 0xb040, 0xc10c, 0xb07f, 0xc10c, 0x21, 0 + .dw 0xb0c0, 0xc10c, 0xb0ff, 0xc10c, 0x21, 0 + .dw 0xb140, 0xc10c, 0xb17f, 0xc10c, 0x21, 0 + .dw 0xb1c0, 0xc10c, 0xb1ff, 0xc10c, 0x21, 0 + .dw 0xb240, 0xc10c, 0xb27f, 0xc10c, 0x21, 0 + .dw 0xb2c0, 0xc10c, 0xb2ff, 0xc10c, 0x21, 0 + .dw 0xb340, 0xc10c, 0xb37f, 0xc10c, 0x21, 0 + .dw 0xb3c0, 0xc10c, 0xb3ff, 0xc10c, 0x21, 0 + .dw 0xb440, 0xc10c, 0xb47f, 0xc10c, 0x21, 0 + .dw 0xb4c0, 0xc10c, 0xb4ff, 0xc10c, 0x21, 0 + .dw 0xb540, 0xc10c, 0xb57f, 0xc10c, 0x21, 0 + .dw 0xb5c0, 0xc10c, 0xb5ff, 0xc10c, 0x21, 0 + .dw 0xb640, 0xc10c, 0xb67f, 0xc10c, 0x21, 0 + .dw 0xb6c0, 0xc10c, 0xb6ff, 0xc10c, 0x21, 0 + .dw 0xb740, 0xc10c, 0xb77f, 0xc10c, 0x21, 0 + .dw 0xb7c0, 0xc10c, 0xb7ff, 0xc10c, 0x21, 0 + .dw 0xb840, 0xc10c, 0xb87f, 0xc10c, 0x21, 0 + .dw 0xb8c0, 0xc10c, 0xb8ff, 0xc10c, 0x21, 0 + .dw 0xb940, 0xc10c, 0xb97f, 0xc10c, 0x21, 0 + .dw 0xb9c0, 0xc10c, 0xbfff, 0xc10c, 0x21, 0 + .dw 0xc040, 0xc10c, 0xc07f, 0xc10c, 0x21, 0 + .dw 0xc0c0, 0xc10c, 0xc0ff, 0xc10c, 0x21, 0 + .dw 0xc140, 0xc10c, 0xc17f, 0xc10c, 0x21, 0 + .dw 0xc1c0, 0xc10c, 0xc1ff, 0xc10c, 0x21, 0 + .dw 0xc240, 0xc10c, 0xc27f, 0xc10c, 0x21, 0 + .dw 0xc2c0, 0xc10c, 0xc2ff, 0xc10c, 0x21, 0 + .dw 0xc340, 0xc10c, 0xc37f, 0xc10c, 0x21, 0 + .dw 0xc3c0, 0xc10c, 0xc3ff, 0xc10c, 0x21, 0 + .dw 0xc440, 0xc10c, 0xc47f, 0xc10c, 0x21, 0 + .dw 0xc4c0, 0xc10c, 0xc4ff, 0xc10c, 0x21, 0 + .dw 0xc540, 0xc10c, 0xc57f, 0xc10c, 0x21, 0 + .dw 0xc5c0, 0xc10c, 0xc5ff, 0xc10c, 0x21, 0 + .dw 0xc640, 0xc10c, 0xc67f, 0xc10c, 0x21, 0 + .dw 0xc6c0, 0xc10c, 0xc6ff, 0xc10c, 0x21, 0 + .dw 0xc740, 0xc10c, 0xc77f, 0xc10c, 0x21, 0 + .dw 0xc7c0, 0xc10c, 0xc7ff, 0xc10c, 0x21, 0 + .dw 0xc840, 0xc10c, 0xc87f, 0xc10c, 0x21, 0 + .dw 0xc8c0, 0xc10c, 0xc8ff, 0xc10c, 0x21, 0 + .dw 0xc940, 0xc10c, 0xc97f, 0xc10c, 0x21, 0 + .dw 0xc9c0, 0xc10c, 0xc9ff, 0xc10c, 0x21, 0 + .dw 0xca40, 0xc10c, 0xca7f, 0xc10c, 0x21, 0 + .dw 0xcac0, 0xc10c, 0xcaff, 0xc10c, 0x21, 0 + .dw 0xcb40, 0xc10c, 0xcb7f, 0xc10c, 0x21, 0 + .dw 0xcbc0, 0xc10c, 0xcbff, 0xc10c, 0x21, 0 + .dw 0xcc40, 0xc10c, 0xcc7f, 0xc10c, 0x21, 0 + .dw 0xccc0, 0xc10c, 0xccff, 0xc10c, 0x21, 0 + .dw 0xcd40, 0xc10c, 0xcd7f, 0xc10c, 0x21, 0 + .dw 0xcdc0, 0xc10c, 0xcdff, 0xc10c, 0x21, 0 + .dw 0xce40, 0xc10c, 0xce7f, 0xc10c, 0x21, 0 + .dw 0xcec0, 0xc10c, 0xceff, 0xc10c, 0x21, 0 + .dw 0xcf40, 0xc10c, 0xcf7f, 0xc10c, 0x21, 0 + .dw 0xcfc0, 0xc10c, 0xcfff, 0xc10c, 0x21, 0 + .dw 0xd040, 0xc10c, 0xd07f, 0xc10c, 0x21, 0 + .dw 0xd0c0, 0xc10c, 0xd0ff, 0xc10c, 0x21, 0 + .dw 0xd140, 0xc10c, 0xd17f, 0xc10c, 0x21, 0 + .dw 0xd1c0, 0xc10c, 0xd1ff, 0xc10c, 0x21, 0 + .dw 0xd240, 0xc10c, 0xd27f, 0xc10c, 0x21, 0 + .dw 0xd2c0, 0xc10c, 0xd2ff, 0xc10c, 0x21, 0 + .dw 0xd340, 0xc10c, 0xd37f, 0xc10c, 0x21, 0 + .dw 0xd3c0, 0xc10c, 0xd3ff, 0xc10c, 0x21, 0 + .dw 0xd440, 0xc10c, 0xd47f, 0xc10c, 0x21, 0 + .dw 0xd4c0, 0xc10c, 0xd4ff, 0xc10c, 0x21, 0 + .dw 0xd540, 0xc10c, 0xd57f, 0xc10c, 0x21, 0 + .dw 0xd5c0, 0xc10c, 0xd5ff, 0xc10c, 0x21, 0 + .dw 0xd640, 0xc10c, 0xd67f, 0xc10c, 0x21, 0 + .dw 0xd6c0, 0xc10c, 0xd6ff, 0xc10c, 0x21, 0 + .dw 0xd740, 0xc10c, 0xd77f, 0xc10c, 0x21, 0 + .dw 0xd7c0, 0xc10c, 0xd7ff, 0xc10c, 0x21, 0 + .dw 0xd840, 0xc10c, 0xd87f, 0xc10c, 0x21, 0 + .dw 0xd8c0, 0xc10c, 0xd8ff, 0xc10c, 0x21, 0 + .dw 0xd940, 0xc10c, 0xd97f, 0xc10c, 0x21, 0 + .dw 0xd9c0, 0xc10c, 0xdfff, 0xc10c, 0x21, 0 + .dw 0xe040, 0xc10c, 0xe07f, 0xc10c, 0x21, 0 + .dw 0xe0c0, 0xc10c, 0xe0ff, 0xc10c, 0x21, 0 + .dw 0xe140, 0xc10c, 0xe17f, 0xc10c, 0x21, 0 + .dw 0xe1c0, 0xc10c, 0xe1ff, 0xc10c, 0x21, 0 + .dw 0xe240, 0xc10c, 0xe27f, 0xc10c, 0x21, 0 + .dw 0xe2c0, 0xc10c, 0xe2ff, 0xc10c, 0x21, 0 + .dw 0xe340, 0xc10c, 0xe37f, 0xc10c, 0x21, 0 + .dw 0xe3c0, 0xc10c, 0xe3ff, 0xc10c, 0x21, 0 + .dw 0xe440, 0xc10c, 0xe47f, 0xc10c, 0x21, 0 + .dw 0xe4c0, 0xc10c, 0xe4ff, 0xc10c, 0x21, 0 + .dw 0xe540, 0xc10c, 0xe57f, 0xc10c, 0x21, 0 + .dw 0xe5c0, 0xc10c, 0xe5ff, 0xc10c, 0x21, 0 + .dw 0xe640, 0xc10c, 0xe67f, 0xc10c, 0x21, 0 + .dw 0xe6c0, 0xc10c, 0xe6ff, 0xc10c, 0x21, 0 + .dw 0xe740, 0xc10c, 0xe77f, 0xc10c, 0x21, 0 + .dw 0xe7c0, 0xc10c, 0xe7ff, 0xc10c, 0x21, 0 + .dw 0xe840, 0xc10c, 0xe87f, 0xc10c, 0x21, 0 + .dw 0xe8c0, 0xc10c, 0xe8ff, 0xc10c, 0x21, 0 + .dw 0xe940, 0xc10c, 0xe97f, 0xc10c, 0x21, 0 + .dw 0xe9c0, 0xc10c, 0xe9ff, 0xc10c, 0x21, 0 + .dw 0xea40, 0xc10c, 0xea7f, 0xc10c, 0x21, 0 + .dw 0xeac0, 0xc10c, 0xeaff, 0xc10c, 0x21, 0 + .dw 0xeb40, 0xc10c, 0xeb7f, 0xc10c, 0x21, 0 + .dw 0xebc0, 0xc10c, 0xebff, 0xc10c, 0x21, 0 + .dw 0xec40, 0xc10c, 0xec7f, 0xc10c, 0x21, 0 + .dw 0xecc0, 0xc10c, 0xecff, 0xc10c, 0x21, 0 + .dw 0xed40, 0xc10c, 0xed7f, 0xc10c, 0x21, 0 + .dw 0xedc0, 0xc10c, 0xedff, 0xc10c, 0x21, 0 + .dw 0xee40, 0xc10c, 0xee7f, 0xc10c, 0x21, 0 + .dw 0xeec0, 0xc10c, 0xeeff, 0xc10c, 0x21, 0 + .dw 0xef40, 0xc10c, 0xef7f, 0xc10c, 0x21, 0 + .dw 0xefc0, 0xc10c, 0xefff, 0xc10c, 0x21, 0 + .dw 0xf040, 0xc10c, 0xf07f, 0xc10c, 0x21, 0 + .dw 0xf0c0, 0xc10c, 0xf0ff, 0xc10c, 0x21, 0 + .dw 0xf140, 0xc10c, 0xf17f, 0xc10c, 0x21, 0 + .dw 0xf1c0, 0xc10c, 0xf1ff, 0xc10c, 0x21, 0 + .dw 0xf240, 0xc10c, 0xf27f, 0xc10c, 0x21, 0 + .dw 0xf2c0, 0xc10c, 0xf2ff, 0xc10c, 0x21, 0 + .dw 0xf340, 0xc10c, 0xf37f, 0xc10c, 0x21, 0 + .dw 0xf3c0, 0xc10c, 0xf3ff, 0xc10c, 0x21, 0 + .dw 0xf440, 0xc10c, 0xf47f, 0xc10c, 0x21, 0 + .dw 0xf4c0, 0xc10c, 0xf4ff, 0xc10c, 0x21, 0 + .dw 0xf540, 0xc10c, 0xf57f, 0xc10c, 0x21, 0 + .dw 0xf5c0, 0xc10c, 0xf5ff, 0xc10c, 0x21, 0 + .dw 0xf640, 0xc10c, 0xf67f, 0xc10c, 0x21, 0 + .dw 0xf6c0, 0xc10c, 0xf6ff, 0xc10c, 0x21, 0 + .dw 0xf740, 0xc10c, 0xf77f, 0xc10c, 0x21, 0 + .dw 0xf7c0, 0xc10c, 0xf7ff, 0xc10c, 0x21, 0 + .dw 0xf840, 0xc10c, 0xf87f, 0xc10c, 0x21, 0 + .dw 0xf8c0, 0xc10c, 0xf8ff, 0xc10c, 0x21, 0 + .dw 0xf940, 0xc10c, 0xf97f, 0xc10c, 0x21, 0 + .dw 0xf9c0, 0xc10c, 0xffff, 0xc10c, 0x21, 0 + .dw 0x0040, 0xc10d, 0x007f, 0xc10d, 0x21, 0 + .dw 0x00c0, 0xc10d, 0x00ff, 0xc10d, 0x21, 0 + .dw 0x0140, 0xc10d, 0x017f, 0xc10d, 0x21, 0 + .dw 0x01c0, 0xc10d, 0x01ff, 0xc10d, 0x21, 0 + .dw 0x0240, 0xc10d, 0x027f, 0xc10d, 0x21, 0 + .dw 0x02c0, 0xc10d, 0x02ff, 0xc10d, 0x21, 0 + .dw 0x0340, 0xc10d, 0x037f, 0xc10d, 0x21, 0 + .dw 0x03c0, 0xc10d, 0x03ff, 0xc10d, 0x21, 0 + .dw 0x0440, 0xc10d, 0x047f, 0xc10d, 0x21, 0 + .dw 0x04c0, 0xc10d, 0x04ff, 0xc10d, 0x21, 0 + .dw 0x0540, 0xc10d, 0x057f, 0xc10d, 0x21, 0 + .dw 0x05c0, 0xc10d, 0x05ff, 0xc10d, 0x21, 0 + .dw 0x0640, 0xc10d, 0x067f, 0xc10d, 0x21, 0 + .dw 0x06c0, 0xc10d, 0x06ff, 0xc10d, 0x21, 0 + .dw 0x0740, 0xc10d, 0x077f, 0xc10d, 0x21, 0 + .dw 0x07c0, 0xc10d, 0x07ff, 0xc10d, 0x21, 0 + .dw 0x0840, 0xc10d, 0x087f, 0xc10d, 0x21, 0 + .dw 0x08c0, 0xc10d, 0x08ff, 0xc10d, 0x21, 0 + .dw 0x0940, 0xc10d, 0x097f, 0xc10d, 0x21, 0 + .dw 0x09c0, 0xc10d, 0x09ff, 0xc10d, 0x21, 0 + .dw 0x0a40, 0xc10d, 0x0a7f, 0xc10d, 0x21, 0 + .dw 0x0ac0, 0xc10d, 0x0aff, 0xc10d, 0x21, 0 + .dw 0x0b40, 0xc10d, 0x0b7f, 0xc10d, 0x21, 0 + .dw 0x0bc0, 0xc10d, 0x0bff, 0xc10d, 0x21, 0 + .dw 0x0c40, 0xc10d, 0x0c7f, 0xc10d, 0x21, 0 + .dw 0x0cc0, 0xc10d, 0x0cff, 0xc10d, 0x21, 0 + .dw 0x0d40, 0xc10d, 0x0d7f, 0xc10d, 0x21, 0 + .dw 0x0dc0, 0xc10d, 0x0dff, 0xc10d, 0x21, 0 + .dw 0x0e40, 0xc10d, 0x0e7f, 0xc10d, 0x21, 0 + .dw 0x0ec0, 0xc10d, 0x0eff, 0xc10d, 0x21, 0 + .dw 0x0f40, 0xc10d, 0x0f7f, 0xc10d, 0x21, 0 + .dw 0x0fc0, 0xc10d, 0x0fff, 0xc10d, 0x21, 0 + .dw 0x1040, 0xc10d, 0x107f, 0xc10d, 0x21, 0 + .dw 0x10c0, 0xc10d, 0x10ff, 0xc10d, 0x21, 0 + .dw 0x1140, 0xc10d, 0x117f, 0xc10d, 0x21, 0 + .dw 0x11c0, 0xc10d, 0x11ff, 0xc10d, 0x21, 0 + .dw 0x1240, 0xc10d, 0x127f, 0xc10d, 0x21, 0 + .dw 0x12c0, 0xc10d, 0x12ff, 0xc10d, 0x21, 0 + .dw 0x1340, 0xc10d, 0x137f, 0xc10d, 0x21, 0 + .dw 0x13c0, 0xc10d, 0x13ff, 0xc10d, 0x21, 0 + .dw 0x1440, 0xc10d, 0x147f, 0xc10d, 0x21, 0 + .dw 0x14c0, 0xc10d, 0x14ff, 0xc10d, 0x21, 0 + .dw 0x1540, 0xc10d, 0x157f, 0xc10d, 0x21, 0 + .dw 0x15c0, 0xc10d, 0x15ff, 0xc10d, 0x21, 0 + .dw 0x1640, 0xc10d, 0x167f, 0xc10d, 0x21, 0 + .dw 0x16c0, 0xc10d, 0x16ff, 0xc10d, 0x21, 0 + .dw 0x1740, 0xc10d, 0x177f, 0xc10d, 0x21, 0 + .dw 0x17c0, 0xc10d, 0x17ff, 0xc10d, 0x21, 0 + .dw 0x1840, 0xc10d, 0x187f, 0xc10d, 0x21, 0 + .dw 0x18c0, 0xc10d, 0x18ff, 0xc10d, 0x21, 0 + .dw 0x1940, 0xc10d, 0x197f, 0xc10d, 0x21, 0 + .dw 0x19c0, 0xc10d, 0x1fff, 0xc10d, 0x21, 0 + .dw 0x2040, 0xc10d, 0x207f, 0xc10d, 0x21, 0 + .dw 0x20c0, 0xc10d, 0x20ff, 0xc10d, 0x21, 0 + .dw 0x2140, 0xc10d, 0x217f, 0xc10d, 0x21, 0 + .dw 0x21c0, 0xc10d, 0x21ff, 0xc10d, 0x21, 0 + .dw 0x2240, 0xc10d, 0x227f, 0xc10d, 0x21, 0 + .dw 0x22c0, 0xc10d, 0x22ff, 0xc10d, 0x21, 0 + .dw 0x2340, 0xc10d, 0x237f, 0xc10d, 0x21, 0 + .dw 0x23c0, 0xc10d, 0x23ff, 0xc10d, 0x21, 0 + .dw 0x2440, 0xc10d, 0x247f, 0xc10d, 0x21, 0 + .dw 0x24c0, 0xc10d, 0x24ff, 0xc10d, 0x21, 0 + .dw 0x2540, 0xc10d, 0x257f, 0xc10d, 0x21, 0 + .dw 0x25c0, 0xc10d, 0x25ff, 0xc10d, 0x21, 0 + .dw 0x2640, 0xc10d, 0x267f, 0xc10d, 0x21, 0 + .dw 0x26c0, 0xc10d, 0x26ff, 0xc10d, 0x21, 0 + .dw 0x2740, 0xc10d, 0x277f, 0xc10d, 0x21, 0 + .dw 0x27c0, 0xc10d, 0x27ff, 0xc10d, 0x21, 0 + .dw 0x2840, 0xc10d, 0x287f, 0xc10d, 0x21, 0 + .dw 0x28c0, 0xc10d, 0x28ff, 0xc10d, 0x21, 0 + .dw 0x2940, 0xc10d, 0x297f, 0xc10d, 0x21, 0 + .dw 0x29c0, 0xc10d, 0x29ff, 0xc10d, 0x21, 0 + .dw 0x2a40, 0xc10d, 0x2a7f, 0xc10d, 0x21, 0 + .dw 0x2ac0, 0xc10d, 0x2aff, 0xc10d, 0x21, 0 + .dw 0x2b40, 0xc10d, 0x2b7f, 0xc10d, 0x21, 0 + .dw 0x2bc0, 0xc10d, 0x2bff, 0xc10d, 0x21, 0 + .dw 0x2c40, 0xc10d, 0x2c7f, 0xc10d, 0x21, 0 + .dw 0x2cc0, 0xc10d, 0x2cff, 0xc10d, 0x21, 0 + .dw 0x2d40, 0xc10d, 0x2d7f, 0xc10d, 0x21, 0 + .dw 0x2dc0, 0xc10d, 0x2dff, 0xc10d, 0x21, 0 + .dw 0x2e40, 0xc10d, 0x2e7f, 0xc10d, 0x21, 0 + .dw 0x2ec0, 0xc10d, 0x2eff, 0xc10d, 0x21, 0 + .dw 0x2f40, 0xc10d, 0x2f7f, 0xc10d, 0x21, 0 + .dw 0x2fc0, 0xc10d, 0x2fff, 0xc10d, 0x21, 0 + .dw 0x3040, 0xc10d, 0x307f, 0xc10d, 0x21, 0 + .dw 0x30c0, 0xc10d, 0x30ff, 0xc10d, 0x21, 0 + .dw 0x3140, 0xc10d, 0x317f, 0xc10d, 0x21, 0 + .dw 0x31c0, 0xc10d, 0x31ff, 0xc10d, 0x21, 0 + .dw 0x3240, 0xc10d, 0x327f, 0xc10d, 0x21, 0 + .dw 0x32c0, 0xc10d, 0x32ff, 0xc10d, 0x21, 0 + .dw 0x3340, 0xc10d, 0x337f, 0xc10d, 0x21, 0 + .dw 0x33c0, 0xc10d, 0x33ff, 0xc10d, 0x21, 0 + .dw 0x3440, 0xc10d, 0x347f, 0xc10d, 0x21, 0 + .dw 0x34c0, 0xc10d, 0x34ff, 0xc10d, 0x21, 0 + .dw 0x3540, 0xc10d, 0x357f, 0xc10d, 0x21, 0 + .dw 0x35c0, 0xc10d, 0x35ff, 0xc10d, 0x21, 0 + .dw 0x3640, 0xc10d, 0x367f, 0xc10d, 0x21, 0 + .dw 0x36c0, 0xc10d, 0x36ff, 0xc10d, 0x21, 0 + .dw 0x3740, 0xc10d, 0x377f, 0xc10d, 0x21, 0 + .dw 0x37c0, 0xc10d, 0x37ff, 0xc10d, 0x21, 0 + .dw 0x3840, 0xc10d, 0x387f, 0xc10d, 0x21, 0 + .dw 0x38c0, 0xc10d, 0x38ff, 0xc10d, 0x21, 0 + .dw 0x3940, 0xc10d, 0x397f, 0xc10d, 0x21, 0 + .dw 0x39c0, 0xc10d, 0x3fff, 0xc10d, 0x21, 0 + .dw 0x4040, 0xc10d, 0x407f, 0xc10d, 0x21, 0 + .dw 0x40c0, 0xc10d, 0x40ff, 0xc10d, 0x21, 0 + .dw 0x4140, 0xc10d, 0x417f, 0xc10d, 0x21, 0 + .dw 0x41c0, 0xc10d, 0x41ff, 0xc10d, 0x21, 0 + .dw 0x4240, 0xc10d, 0x427f, 0xc10d, 0x21, 0 + .dw 0x42c0, 0xc10d, 0x42ff, 0xc10d, 0x21, 0 + .dw 0x4340, 0xc10d, 0x437f, 0xc10d, 0x21, 0 + .dw 0x43c0, 0xc10d, 0x43ff, 0xc10d, 0x21, 0 + .dw 0x4440, 0xc10d, 0x447f, 0xc10d, 0x21, 0 + .dw 0x44c0, 0xc10d, 0x44ff, 0xc10d, 0x21, 0 + .dw 0x4540, 0xc10d, 0x457f, 0xc10d, 0x21, 0 + .dw 0x45c0, 0xc10d, 0x45ff, 0xc10d, 0x21, 0 + .dw 0x4640, 0xc10d, 0x467f, 0xc10d, 0x21, 0 + .dw 0x46c0, 0xc10d, 0x46ff, 0xc10d, 0x21, 0 + .dw 0x4740, 0xc10d, 0x477f, 0xc10d, 0x21, 0 + .dw 0x47c0, 0xc10d, 0x47ff, 0xc10d, 0x21, 0 + .dw 0x4840, 0xc10d, 0x487f, 0xc10d, 0x21, 0 + .dw 0x48c0, 0xc10d, 0x48ff, 0xc10d, 0x21, 0 + .dw 0x4940, 0xc10d, 0x497f, 0xc10d, 0x21, 0 + .dw 0x49c0, 0xc10d, 0x49ff, 0xc10d, 0x21, 0 + .dw 0x4a40, 0xc10d, 0x4a7f, 0xc10d, 0x21, 0 + .dw 0x4ac0, 0xc10d, 0x4aff, 0xc10d, 0x21, 0 + .dw 0x4b40, 0xc10d, 0x4b7f, 0xc10d, 0x21, 0 + .dw 0x4bc0, 0xc10d, 0x4bff, 0xc10d, 0x21, 0 + .dw 0x4c40, 0xc10d, 0x4c7f, 0xc10d, 0x21, 0 + .dw 0x4cc0, 0xc10d, 0x4cff, 0xc10d, 0x21, 0 + .dw 0x4d40, 0xc10d, 0x4d7f, 0xc10d, 0x21, 0 + .dw 0x4dc0, 0xc10d, 0x4dff, 0xc10d, 0x21, 0 + .dw 0x4e40, 0xc10d, 0x4e7f, 0xc10d, 0x21, 0 + .dw 0x4ec0, 0xc10d, 0x4eff, 0xc10d, 0x21, 0 + .dw 0x4f40, 0xc10d, 0x4f7f, 0xc10d, 0x21, 0 + .dw 0x4fc0, 0xc10d, 0x4fff, 0xc10d, 0x21, 0 + .dw 0x5040, 0xc10d, 0x507f, 0xc10d, 0x21, 0 + .dw 0x50c0, 0xc10d, 0x50ff, 0xc10d, 0x21, 0 + .dw 0x5140, 0xc10d, 0x517f, 0xc10d, 0x21, 0 + .dw 0x51c0, 0xc10d, 0x51ff, 0xc10d, 0x21, 0 + .dw 0x5240, 0xc10d, 0x527f, 0xc10d, 0x21, 0 + .dw 0x52c0, 0xc10d, 0x52ff, 0xc10d, 0x21, 0 + .dw 0x5340, 0xc10d, 0x537f, 0xc10d, 0x21, 0 + .dw 0x53c0, 0xc10d, 0x53ff, 0xc10d, 0x21, 0 + .dw 0x5440, 0xc10d, 0x547f, 0xc10d, 0x21, 0 + .dw 0x54c0, 0xc10d, 0x54ff, 0xc10d, 0x21, 0 + .dw 0x5540, 0xc10d, 0x557f, 0xc10d, 0x21, 0 + .dw 0x55c0, 0xc10d, 0x55ff, 0xc10d, 0x21, 0 + .dw 0x5640, 0xc10d, 0x567f, 0xc10d, 0x21, 0 + .dw 0x56c0, 0xc10d, 0x56ff, 0xc10d, 0x21, 0 + .dw 0x5740, 0xc10d, 0x577f, 0xc10d, 0x21, 0 + .dw 0x57c0, 0xc10d, 0x57ff, 0xc10d, 0x21, 0 + .dw 0x5840, 0xc10d, 0x587f, 0xc10d, 0x21, 0 + .dw 0x58c0, 0xc10d, 0x58ff, 0xc10d, 0x21, 0 + .dw 0x5940, 0xc10d, 0x597f, 0xc10d, 0x21, 0 + .dw 0x59c0, 0xc10d, 0x5fff, 0xc10d, 0x21, 0 + .dw 0x6040, 0xc10d, 0x607f, 0xc10d, 0x21, 0 + .dw 0x60c0, 0xc10d, 0x60ff, 0xc10d, 0x21, 0 + .dw 0x6140, 0xc10d, 0x617f, 0xc10d, 0x21, 0 + .dw 0x61c0, 0xc10d, 0x61ff, 0xc10d, 0x21, 0 + .dw 0x6240, 0xc10d, 0x627f, 0xc10d, 0x21, 0 + .dw 0x62c0, 0xc10d, 0x62ff, 0xc10d, 0x21, 0 + .dw 0x6340, 0xc10d, 0x637f, 0xc10d, 0x21, 0 + .dw 0x63c0, 0xc10d, 0x63ff, 0xc10d, 0x21, 0 + .dw 0x6440, 0xc10d, 0x647f, 0xc10d, 0x21, 0 + .dw 0x64c0, 0xc10d, 0x64ff, 0xc10d, 0x21, 0 + .dw 0x6540, 0xc10d, 0x657f, 0xc10d, 0x21, 0 + .dw 0x65c0, 0xc10d, 0x65ff, 0xc10d, 0x21, 0 + .dw 0x6640, 0xc10d, 0x667f, 0xc10d, 0x21, 0 + .dw 0x66c0, 0xc10d, 0x66ff, 0xc10d, 0x21, 0 + .dw 0x6740, 0xc10d, 0x677f, 0xc10d, 0x21, 0 + .dw 0x67c0, 0xc10d, 0x67ff, 0xc10d, 0x21, 0 + .dw 0x6840, 0xc10d, 0x687f, 0xc10d, 0x21, 0 + .dw 0x68c0, 0xc10d, 0x68ff, 0xc10d, 0x21, 0 + .dw 0x6940, 0xc10d, 0x697f, 0xc10d, 0x21, 0 + .dw 0x69c0, 0xc10d, 0x69ff, 0xc10d, 0x21, 0 + .dw 0x6a40, 0xc10d, 0x6a7f, 0xc10d, 0x21, 0 + .dw 0x6ac0, 0xc10d, 0x6aff, 0xc10d, 0x21, 0 + .dw 0x6b40, 0xc10d, 0x6b7f, 0xc10d, 0x21, 0 + .dw 0x6bc0, 0xc10d, 0x6bff, 0xc10d, 0x21, 0 + .dw 0x6c40, 0xc10d, 0x6c7f, 0xc10d, 0x21, 0 + .dw 0x6cc0, 0xc10d, 0x6cff, 0xc10d, 0x21, 0 + .dw 0x6d40, 0xc10d, 0x6d7f, 0xc10d, 0x21, 0 + .dw 0x6dc0, 0xc10d, 0x6dff, 0xc10d, 0x21, 0 + .dw 0x6e40, 0xc10d, 0x6e7f, 0xc10d, 0x21, 0 + .dw 0x6ec0, 0xc10d, 0x6eff, 0xc10d, 0x21, 0 + .dw 0x6f40, 0xc10d, 0x6f7f, 0xc10d, 0x21, 0 + .dw 0x6fc0, 0xc10d, 0x6fff, 0xc10d, 0x21, 0 + .dw 0x7040, 0xc10d, 0x707f, 0xc10d, 0x21, 0 + .dw 0x70c0, 0xc10d, 0x70ff, 0xc10d, 0x21, 0 + .dw 0x7140, 0xc10d, 0x717f, 0xc10d, 0x21, 0 + .dw 0x71c0, 0xc10d, 0x71ff, 0xc10d, 0x21, 0 + .dw 0x7240, 0xc10d, 0x727f, 0xc10d, 0x21, 0 + .dw 0x72c0, 0xc10d, 0x72ff, 0xc10d, 0x21, 0 + .dw 0x7340, 0xc10d, 0x737f, 0xc10d, 0x21, 0 + .dw 0x73c0, 0xc10d, 0x73ff, 0xc10d, 0x21, 0 + .dw 0x7440, 0xc10d, 0x747f, 0xc10d, 0x21, 0 + .dw 0x74c0, 0xc10d, 0x74ff, 0xc10d, 0x21, 0 + .dw 0x7540, 0xc10d, 0x757f, 0xc10d, 0x21, 0 + .dw 0x75c0, 0xc10d, 0x75ff, 0xc10d, 0x21, 0 + .dw 0x7640, 0xc10d, 0x767f, 0xc10d, 0x21, 0 + .dw 0x76c0, 0xc10d, 0x76ff, 0xc10d, 0x21, 0 + .dw 0x7740, 0xc10d, 0x777f, 0xc10d, 0x21, 0 + .dw 0x77c0, 0xc10d, 0x77ff, 0xc10d, 0x21, 0 + .dw 0x7840, 0xc10d, 0x787f, 0xc10d, 0x21, 0 + .dw 0x78c0, 0xc10d, 0x78ff, 0xc10d, 0x21, 0 + .dw 0x7940, 0xc10d, 0x797f, 0xc10d, 0x21, 0 + .dw 0x79c0, 0xc10d, 0x7fff, 0xc10d, 0x21, 0 + .dw 0x8040, 0xc10d, 0x807f, 0xc10d, 0x21, 0 + .dw 0x80c0, 0xc10d, 0x80ff, 0xc10d, 0x21, 0 + .dw 0x8140, 0xc10d, 0x817f, 0xc10d, 0x21, 0 + .dw 0x81c0, 0xc10d, 0x81ff, 0xc10d, 0x21, 0 + .dw 0x8240, 0xc10d, 0x827f, 0xc10d, 0x21, 0 + .dw 0x82c0, 0xc10d, 0x82ff, 0xc10d, 0x21, 0 + .dw 0x8340, 0xc10d, 0x837f, 0xc10d, 0x21, 0 + .dw 0x83c0, 0xc10d, 0x83ff, 0xc10d, 0x21, 0 + .dw 0x8440, 0xc10d, 0x847f, 0xc10d, 0x21, 0 + .dw 0x84c0, 0xc10d, 0x84ff, 0xc10d, 0x21, 0 + .dw 0x8540, 0xc10d, 0x857f, 0xc10d, 0x21, 0 + .dw 0x85c0, 0xc10d, 0x85ff, 0xc10d, 0x21, 0 + .dw 0x8640, 0xc10d, 0x867f, 0xc10d, 0x21, 0 + .dw 0x86c0, 0xc10d, 0x86ff, 0xc10d, 0x21, 0 + .dw 0x8740, 0xc10d, 0x877f, 0xc10d, 0x21, 0 + .dw 0x87c0, 0xc10d, 0x87ff, 0xc10d, 0x21, 0 + .dw 0x8840, 0xc10d, 0x887f, 0xc10d, 0x21, 0 + .dw 0x88c0, 0xc10d, 0x88ff, 0xc10d, 0x21, 0 + .dw 0x8940, 0xc10d, 0x897f, 0xc10d, 0x21, 0 + .dw 0x89c0, 0xc10d, 0x89ff, 0xc10d, 0x21, 0 + .dw 0x8a40, 0xc10d, 0x8a7f, 0xc10d, 0x21, 0 + .dw 0x8ac0, 0xc10d, 0x8aff, 0xc10d, 0x21, 0 + .dw 0x8b40, 0xc10d, 0x8b7f, 0xc10d, 0x21, 0 + .dw 0x8bc0, 0xc10d, 0x8bff, 0xc10d, 0x21, 0 + .dw 0x8c40, 0xc10d, 0x8c7f, 0xc10d, 0x21, 0 + .dw 0x8cc0, 0xc10d, 0x8cff, 0xc10d, 0x21, 0 + .dw 0x8d40, 0xc10d, 0x8d7f, 0xc10d, 0x21, 0 + .dw 0x8dc0, 0xc10d, 0x8dff, 0xc10d, 0x21, 0 + .dw 0x8e40, 0xc10d, 0x8e7f, 0xc10d, 0x21, 0 + .dw 0x8ec0, 0xc10d, 0x8eff, 0xc10d, 0x21, 0 + .dw 0x8f40, 0xc10d, 0x8f7f, 0xc10d, 0x21, 0 + .dw 0x8fc0, 0xc10d, 0x8fff, 0xc10d, 0x21, 0 + .dw 0x9040, 0xc10d, 0x907f, 0xc10d, 0x21, 0 + .dw 0x90c0, 0xc10d, 0x90ff, 0xc10d, 0x21, 0 + .dw 0x9140, 0xc10d, 0x917f, 0xc10d, 0x21, 0 + .dw 0x91c0, 0xc10d, 0x91ff, 0xc10d, 0x21, 0 + .dw 0x9240, 0xc10d, 0x927f, 0xc10d, 0x21, 0 + .dw 0x92c0, 0xc10d, 0x92ff, 0xc10d, 0x21, 0 + .dw 0x9340, 0xc10d, 0x937f, 0xc10d, 0x21, 0 + .dw 0x93c0, 0xc10d, 0x93ff, 0xc10d, 0x21, 0 + .dw 0x9440, 0xc10d, 0x947f, 0xc10d, 0x21, 0 + .dw 0x94c0, 0xc10d, 0x94ff, 0xc10d, 0x21, 0 + .dw 0x9540, 0xc10d, 0x957f, 0xc10d, 0x21, 0 + .dw 0x95c0, 0xc10d, 0x95ff, 0xc10d, 0x21, 0 + .dw 0x9640, 0xc10d, 0x967f, 0xc10d, 0x21, 0 + .dw 0x96c0, 0xc10d, 0x96ff, 0xc10d, 0x21, 0 + .dw 0x9740, 0xc10d, 0x977f, 0xc10d, 0x21, 0 + .dw 0x97c0, 0xc10d, 0x97ff, 0xc10d, 0x21, 0 + .dw 0x9840, 0xc10d, 0x987f, 0xc10d, 0x21, 0 + .dw 0x98c0, 0xc10d, 0x98ff, 0xc10d, 0x21, 0 + .dw 0x9940, 0xc10d, 0x997f, 0xc10d, 0x21, 0 + .dw 0x99c0, 0xc10d, 0x9fff, 0xc10d, 0x21, 0 + .dw 0xa040, 0xc10d, 0xa07f, 0xc10d, 0x21, 0 + .dw 0xa0c0, 0xc10d, 0xa0ff, 0xc10d, 0x21, 0 + .dw 0xa140, 0xc10d, 0xa17f, 0xc10d, 0x21, 0 + .dw 0xa1c0, 0xc10d, 0xa1ff, 0xc10d, 0x21, 0 + .dw 0xa240, 0xc10d, 0xa27f, 0xc10d, 0x21, 0 + .dw 0xa2c0, 0xc10d, 0xa2ff, 0xc10d, 0x21, 0 + .dw 0xa340, 0xc10d, 0xa37f, 0xc10d, 0x21, 0 + .dw 0xa3c0, 0xc10d, 0xa3ff, 0xc10d, 0x21, 0 + .dw 0xa440, 0xc10d, 0xa47f, 0xc10d, 0x21, 0 + .dw 0xa4c0, 0xc10d, 0xa4ff, 0xc10d, 0x21, 0 + .dw 0xa540, 0xc10d, 0xa57f, 0xc10d, 0x21, 0 + .dw 0xa5c0, 0xc10d, 0xa5ff, 0xc10d, 0x21, 0 + .dw 0xa640, 0xc10d, 0xa67f, 0xc10d, 0x21, 0 + .dw 0xa6c0, 0xc10d, 0xa6ff, 0xc10d, 0x21, 0 + .dw 0xa740, 0xc10d, 0xa77f, 0xc10d, 0x21, 0 + .dw 0xa7c0, 0xc10d, 0xa7ff, 0xc10d, 0x21, 0 + .dw 0xa840, 0xc10d, 0xa87f, 0xc10d, 0x21, 0 + .dw 0xa8c0, 0xc10d, 0xa8ff, 0xc10d, 0x21, 0 + .dw 0xa940, 0xc10d, 0xa97f, 0xc10d, 0x21, 0 + .dw 0xa9c0, 0xc10d, 0xa9ff, 0xc10d, 0x21, 0 + .dw 0xaa40, 0xc10d, 0xaa7f, 0xc10d, 0x21, 0 + .dw 0xaac0, 0xc10d, 0xaaff, 0xc10d, 0x21, 0 + .dw 0xab40, 0xc10d, 0xab7f, 0xc10d, 0x21, 0 + .dw 0xabc0, 0xc10d, 0xabff, 0xc10d, 0x21, 0 + .dw 0xac40, 0xc10d, 0xac7f, 0xc10d, 0x21, 0 + .dw 0xacc0, 0xc10d, 0xacff, 0xc10d, 0x21, 0 + .dw 0xad40, 0xc10d, 0xad7f, 0xc10d, 0x21, 0 + .dw 0xadc0, 0xc10d, 0xadff, 0xc10d, 0x21, 0 + .dw 0xae40, 0xc10d, 0xae7f, 0xc10d, 0x21, 0 + .dw 0xaec0, 0xc10d, 0xaeff, 0xc10d, 0x21, 0 + .dw 0xaf40, 0xc10d, 0xaf7f, 0xc10d, 0x21, 0 + .dw 0xafc0, 0xc10d, 0xafff, 0xc10d, 0x21, 0 + .dw 0xb040, 0xc10d, 0xb07f, 0xc10d, 0x21, 0 + .dw 0xb0c0, 0xc10d, 0xb0ff, 0xc10d, 0x21, 0 + .dw 0xb140, 0xc10d, 0xb17f, 0xc10d, 0x21, 0 + .dw 0xb1c0, 0xc10d, 0xb1ff, 0xc10d, 0x21, 0 + .dw 0xb240, 0xc10d, 0xb27f, 0xc10d, 0x21, 0 + .dw 0xb2c0, 0xc10d, 0xb2ff, 0xc10d, 0x21, 0 + .dw 0xb340, 0xc10d, 0xb37f, 0xc10d, 0x21, 0 + .dw 0xb3c0, 0xc10d, 0xb3ff, 0xc10d, 0x21, 0 + .dw 0xb440, 0xc10d, 0xb47f, 0xc10d, 0x21, 0 + .dw 0xb4c0, 0xc10d, 0xb4ff, 0xc10d, 0x21, 0 + .dw 0xb540, 0xc10d, 0xb57f, 0xc10d, 0x21, 0 + .dw 0xb5c0, 0xc10d, 0xb5ff, 0xc10d, 0x21, 0 + .dw 0xb640, 0xc10d, 0xb67f, 0xc10d, 0x21, 0 + .dw 0xb6c0, 0xc10d, 0xb6ff, 0xc10d, 0x21, 0 + .dw 0xb740, 0xc10d, 0xb77f, 0xc10d, 0x21, 0 + .dw 0xb7c0, 0xc10d, 0xb7ff, 0xc10d, 0x21, 0 + .dw 0xb840, 0xc10d, 0xb87f, 0xc10d, 0x21, 0 + .dw 0xb8c0, 0xc10d, 0xb8ff, 0xc10d, 0x21, 0 + .dw 0xb940, 0xc10d, 0xb97f, 0xc10d, 0x21, 0 + .dw 0xb9c0, 0xc10d, 0xbfff, 0xc10d, 0x21, 0 + .dw 0xc040, 0xc10d, 0xc07f, 0xc10d, 0x21, 0 + .dw 0xc0c0, 0xc10d, 0xc0ff, 0xc10d, 0x21, 0 + .dw 0xc140, 0xc10d, 0xc17f, 0xc10d, 0x21, 0 + .dw 0xc1c0, 0xc10d, 0xc1ff, 0xc10d, 0x21, 0 + .dw 0xc240, 0xc10d, 0xc27f, 0xc10d, 0x21, 0 + .dw 0xc2c0, 0xc10d, 0xc2ff, 0xc10d, 0x21, 0 + .dw 0xc340, 0xc10d, 0xc37f, 0xc10d, 0x21, 0 + .dw 0xc3c0, 0xc10d, 0xc3ff, 0xc10d, 0x21, 0 + .dw 0xc440, 0xc10d, 0xc47f, 0xc10d, 0x21, 0 + .dw 0xc4c0, 0xc10d, 0xc4ff, 0xc10d, 0x21, 0 + .dw 0xc540, 0xc10d, 0xc57f, 0xc10d, 0x21, 0 + .dw 0xc5c0, 0xc10d, 0xc5ff, 0xc10d, 0x21, 0 + .dw 0xc640, 0xc10d, 0xc67f, 0xc10d, 0x21, 0 + .dw 0xc6c0, 0xc10d, 0xc6ff, 0xc10d, 0x21, 0 + .dw 0xc740, 0xc10d, 0xc77f, 0xc10d, 0x21, 0 + .dw 0xc7c0, 0xc10d, 0xc7ff, 0xc10d, 0x21, 0 + .dw 0xc840, 0xc10d, 0xc87f, 0xc10d, 0x21, 0 + .dw 0xc8c0, 0xc10d, 0xc8ff, 0xc10d, 0x21, 0 + .dw 0xc940, 0xc10d, 0xc97f, 0xc10d, 0x21, 0 + .dw 0xc9c0, 0xc10d, 0xc9ff, 0xc10d, 0x21, 0 + .dw 0xca40, 0xc10d, 0xca7f, 0xc10d, 0x21, 0 + .dw 0xcac0, 0xc10d, 0xcaff, 0xc10d, 0x21, 0 + .dw 0xcb40, 0xc10d, 0xcb7f, 0xc10d, 0x21, 0 + .dw 0xcbc0, 0xc10d, 0xcbff, 0xc10d, 0x21, 0 + .dw 0xcc40, 0xc10d, 0xcc7f, 0xc10d, 0x21, 0 + .dw 0xccc0, 0xc10d, 0xccff, 0xc10d, 0x21, 0 + .dw 0xcd40, 0xc10d, 0xcd7f, 0xc10d, 0x21, 0 + .dw 0xcdc0, 0xc10d, 0xcdff, 0xc10d, 0x21, 0 + .dw 0xce40, 0xc10d, 0xce7f, 0xc10d, 0x21, 0 + .dw 0xcec0, 0xc10d, 0xceff, 0xc10d, 0x21, 0 + .dw 0xcf40, 0xc10d, 0xcf7f, 0xc10d, 0x21, 0 + .dw 0xcfc0, 0xc10d, 0xcfff, 0xc10d, 0x21, 0 + .dw 0xd040, 0xc10d, 0xd07f, 0xc10d, 0x21, 0 + .dw 0xd0c0, 0xc10d, 0xd0ff, 0xc10d, 0x21, 0 + .dw 0xd140, 0xc10d, 0xd17f, 0xc10d, 0x21, 0 + .dw 0xd1c0, 0xc10d, 0xd1ff, 0xc10d, 0x21, 0 + .dw 0xd240, 0xc10d, 0xd27f, 0xc10d, 0x21, 0 + .dw 0xd2c0, 0xc10d, 0xd2ff, 0xc10d, 0x21, 0 + .dw 0xd340, 0xc10d, 0xd37f, 0xc10d, 0x21, 0 + .dw 0xd3c0, 0xc10d, 0xd3ff, 0xc10d, 0x21, 0 + .dw 0xd440, 0xc10d, 0xd47f, 0xc10d, 0x21, 0 + .dw 0xd4c0, 0xc10d, 0xd4ff, 0xc10d, 0x21, 0 + .dw 0xd540, 0xc10d, 0xd57f, 0xc10d, 0x21, 0 + .dw 0xd5c0, 0xc10d, 0xd5ff, 0xc10d, 0x21, 0 + .dw 0xd640, 0xc10d, 0xd67f, 0xc10d, 0x21, 0 + .dw 0xd6c0, 0xc10d, 0xd6ff, 0xc10d, 0x21, 0 + .dw 0xd740, 0xc10d, 0xd77f, 0xc10d, 0x21, 0 + .dw 0xd7c0, 0xc10d, 0xd7ff, 0xc10d, 0x21, 0 + .dw 0xd840, 0xc10d, 0xd87f, 0xc10d, 0x21, 0 + .dw 0xd8c0, 0xc10d, 0xd8ff, 0xc10d, 0x21, 0 + .dw 0xd940, 0xc10d, 0xd97f, 0xc10d, 0x21, 0 + .dw 0xd9c0, 0xc10d, 0xdfff, 0xc10d, 0x21, 0 + .dw 0xe040, 0xc10d, 0xe07f, 0xc10d, 0x21, 0 + .dw 0xe0c0, 0xc10d, 0xe0ff, 0xc10d, 0x21, 0 + .dw 0xe140, 0xc10d, 0xe17f, 0xc10d, 0x21, 0 + .dw 0xe1c0, 0xc10d, 0xe1ff, 0xc10d, 0x21, 0 + .dw 0xe240, 0xc10d, 0xe27f, 0xc10d, 0x21, 0 + .dw 0xe2c0, 0xc10d, 0xe2ff, 0xc10d, 0x21, 0 + .dw 0xe340, 0xc10d, 0xe37f, 0xc10d, 0x21, 0 + .dw 0xe3c0, 0xc10d, 0xe3ff, 0xc10d, 0x21, 0 + .dw 0xe440, 0xc10d, 0xe47f, 0xc10d, 0x21, 0 + .dw 0xe4c0, 0xc10d, 0xe4ff, 0xc10d, 0x21, 0 + .dw 0xe540, 0xc10d, 0xe57f, 0xc10d, 0x21, 0 + .dw 0xe5c0, 0xc10d, 0xe5ff, 0xc10d, 0x21, 0 + .dw 0xe640, 0xc10d, 0xe67f, 0xc10d, 0x21, 0 + .dw 0xe6c0, 0xc10d, 0xe6ff, 0xc10d, 0x21, 0 + .dw 0xe740, 0xc10d, 0xe77f, 0xc10d, 0x21, 0 + .dw 0xe7c0, 0xc10d, 0xe7ff, 0xc10d, 0x21, 0 + .dw 0xe840, 0xc10d, 0xe87f, 0xc10d, 0x21, 0 + .dw 0xe8c0, 0xc10d, 0xe8ff, 0xc10d, 0x21, 0 + .dw 0xe940, 0xc10d, 0xe97f, 0xc10d, 0x21, 0 + .dw 0xe9c0, 0xc10d, 0xe9ff, 0xc10d, 0x21, 0 + .dw 0xea40, 0xc10d, 0xea7f, 0xc10d, 0x21, 0 + .dw 0xeac0, 0xc10d, 0xeaff, 0xc10d, 0x21, 0 + .dw 0xeb40, 0xc10d, 0xeb7f, 0xc10d, 0x21, 0 + .dw 0xebc0, 0xc10d, 0xebff, 0xc10d, 0x21, 0 + .dw 0xec40, 0xc10d, 0xec7f, 0xc10d, 0x21, 0 + .dw 0xecc0, 0xc10d, 0xecff, 0xc10d, 0x21, 0 + .dw 0xed40, 0xc10d, 0xed7f, 0xc10d, 0x21, 0 + .dw 0xedc0, 0xc10d, 0xedff, 0xc10d, 0x21, 0 + .dw 0xee40, 0xc10d, 0xee7f, 0xc10d, 0x21, 0 + .dw 0xeec0, 0xc10d, 0xeeff, 0xc10d, 0x21, 0 + .dw 0xef40, 0xc10d, 0xef7f, 0xc10d, 0x21, 0 + .dw 0xefc0, 0xc10d, 0xefff, 0xc10d, 0x21, 0 + .dw 0xf040, 0xc10d, 0xf07f, 0xc10d, 0x21, 0 + .dw 0xf0c0, 0xc10d, 0xf0ff, 0xc10d, 0x21, 0 + .dw 0xf140, 0xc10d, 0xf17f, 0xc10d, 0x21, 0 + .dw 0xf1c0, 0xc10d, 0xf1ff, 0xc10d, 0x21, 0 + .dw 0xf240, 0xc10d, 0xf27f, 0xc10d, 0x21, 0 + .dw 0xf2c0, 0xc10d, 0xf2ff, 0xc10d, 0x21, 0 + .dw 0xf340, 0xc10d, 0xf37f, 0xc10d, 0x21, 0 + .dw 0xf3c0, 0xc10d, 0xf3ff, 0xc10d, 0x21, 0 + .dw 0xf440, 0xc10d, 0xf47f, 0xc10d, 0x21, 0 + .dw 0xf4c0, 0xc10d, 0xf4ff, 0xc10d, 0x21, 0 + .dw 0xf540, 0xc10d, 0xf57f, 0xc10d, 0x21, 0 + .dw 0xf5c0, 0xc10d, 0xf5ff, 0xc10d, 0x21, 0 + .dw 0xf640, 0xc10d, 0xf67f, 0xc10d, 0x21, 0 + .dw 0xf6c0, 0xc10d, 0xf6ff, 0xc10d, 0x21, 0 + .dw 0xf740, 0xc10d, 0xf77f, 0xc10d, 0x21, 0 + .dw 0xf7c0, 0xc10d, 0xf7ff, 0xc10d, 0x21, 0 + .dw 0xf840, 0xc10d, 0xf87f, 0xc10d, 0x21, 0 + .dw 0xf8c0, 0xc10d, 0xf8ff, 0xc10d, 0x21, 0 + .dw 0xf940, 0xc10d, 0xf97f, 0xc10d, 0x21, 0 + .dw 0xf9c0, 0xc10d, 0xffff, 0xc10d, 0x21, 0 + .dw 0x0040, 0xc10e, 0x007f, 0xc10e, 0x21, 0 + .dw 0x00c0, 0xc10e, 0x00ff, 0xc10e, 0x21, 0 + .dw 0x0140, 0xc10e, 0x017f, 0xc10e, 0x21, 0 + .dw 0x01c0, 0xc10e, 0x01ff, 0xc10e, 0x21, 0 + .dw 0x0240, 0xc10e, 0x027f, 0xc10e, 0x21, 0 + .dw 0x02c0, 0xc10e, 0x02ff, 0xc10e, 0x21, 0 + .dw 0x0340, 0xc10e, 0x037f, 0xc10e, 0x21, 0 + .dw 0x03c0, 0xc10e, 0x03ff, 0xc10e, 0x21, 0 + .dw 0x0440, 0xc10e, 0x047f, 0xc10e, 0x21, 0 + .dw 0x04c0, 0xc10e, 0x04ff, 0xc10e, 0x21, 0 + .dw 0x0540, 0xc10e, 0x057f, 0xc10e, 0x21, 0 + .dw 0x05c0, 0xc10e, 0x05ff, 0xc10e, 0x21, 0 + .dw 0x0640, 0xc10e, 0x067f, 0xc10e, 0x21, 0 + .dw 0x06c0, 0xc10e, 0x06ff, 0xc10e, 0x21, 0 + .dw 0x0740, 0xc10e, 0x077f, 0xc10e, 0x21, 0 + .dw 0x07c0, 0xc10e, 0x07ff, 0xc10e, 0x21, 0 + .dw 0x0840, 0xc10e, 0x087f, 0xc10e, 0x21, 0 + .dw 0x08c0, 0xc10e, 0x08ff, 0xc10e, 0x21, 0 + .dw 0x0940, 0xc10e, 0x097f, 0xc10e, 0x21, 0 + .dw 0x09c0, 0xc10e, 0x09ff, 0xc10e, 0x21, 0 + .dw 0x0a40, 0xc10e, 0x0a7f, 0xc10e, 0x21, 0 + .dw 0x0ac0, 0xc10e, 0x0aff, 0xc10e, 0x21, 0 + .dw 0x0b40, 0xc10e, 0x0b7f, 0xc10e, 0x21, 0 + .dw 0x0bc0, 0xc10e, 0x0bff, 0xc10e, 0x21, 0 + .dw 0x0c40, 0xc10e, 0x0c7f, 0xc10e, 0x21, 0 + .dw 0x0cc0, 0xc10e, 0x0cff, 0xc10e, 0x21, 0 + .dw 0x0d40, 0xc10e, 0x0d7f, 0xc10e, 0x21, 0 + .dw 0x0dc0, 0xc10e, 0x0dff, 0xc10e, 0x21, 0 + .dw 0x0e40, 0xc10e, 0x0e7f, 0xc10e, 0x21, 0 + .dw 0x0ec0, 0xc10e, 0x0eff, 0xc10e, 0x21, 0 + .dw 0x0f40, 0xc10e, 0x0f7f, 0xc10e, 0x21, 0 + .dw 0x0fc0, 0xc10e, 0x0fff, 0xc10e, 0x21, 0 + .dw 0x1040, 0xc10e, 0x107f, 0xc10e, 0x21, 0 + .dw 0x10c0, 0xc10e, 0x10ff, 0xc10e, 0x21, 0 + .dw 0x1140, 0xc10e, 0x117f, 0xc10e, 0x21, 0 + .dw 0x11c0, 0xc10e, 0x11ff, 0xc10e, 0x21, 0 + .dw 0x1240, 0xc10e, 0x127f, 0xc10e, 0x21, 0 + .dw 0x12c0, 0xc10e, 0x12ff, 0xc10e, 0x21, 0 + .dw 0x1340, 0xc10e, 0x137f, 0xc10e, 0x21, 0 + .dw 0x13c0, 0xc10e, 0x13ff, 0xc10e, 0x21, 0 + .dw 0x1440, 0xc10e, 0x147f, 0xc10e, 0x21, 0 + .dw 0x14c0, 0xc10e, 0x14ff, 0xc10e, 0x21, 0 + .dw 0x1540, 0xc10e, 0x157f, 0xc10e, 0x21, 0 + .dw 0x15c0, 0xc10e, 0x15ff, 0xc10e, 0x21, 0 + .dw 0x1640, 0xc10e, 0x167f, 0xc10e, 0x21, 0 + .dw 0x16c0, 0xc10e, 0x16ff, 0xc10e, 0x21, 0 + .dw 0x1740, 0xc10e, 0x177f, 0xc10e, 0x21, 0 + .dw 0x17c0, 0xc10e, 0x17ff, 0xc10e, 0x21, 0 + .dw 0x1840, 0xc10e, 0x187f, 0xc10e, 0x21, 0 + .dw 0x18c0, 0xc10e, 0x18ff, 0xc10e, 0x21, 0 + .dw 0x1940, 0xc10e, 0x197f, 0xc10e, 0x21, 0 + .dw 0x19c0, 0xc10e, 0x1fff, 0xc10e, 0x21, 0 + .dw 0x2040, 0xc10e, 0x207f, 0xc10e, 0x21, 0 + .dw 0x20c0, 0xc10e, 0x20ff, 0xc10e, 0x21, 0 + .dw 0x2140, 0xc10e, 0x217f, 0xc10e, 0x21, 0 + .dw 0x21c0, 0xc10e, 0x21ff, 0xc10e, 0x21, 0 + .dw 0x2240, 0xc10e, 0x227f, 0xc10e, 0x21, 0 + .dw 0x22c0, 0xc10e, 0x22ff, 0xc10e, 0x21, 0 + .dw 0x2340, 0xc10e, 0x237f, 0xc10e, 0x21, 0 + .dw 0x23c0, 0xc10e, 0x23ff, 0xc10e, 0x21, 0 + .dw 0x2440, 0xc10e, 0x247f, 0xc10e, 0x21, 0 + .dw 0x24c0, 0xc10e, 0x24ff, 0xc10e, 0x21, 0 + .dw 0x2540, 0xc10e, 0x257f, 0xc10e, 0x21, 0 + .dw 0x25c0, 0xc10e, 0x25ff, 0xc10e, 0x21, 0 + .dw 0x2640, 0xc10e, 0x267f, 0xc10e, 0x21, 0 + .dw 0x26c0, 0xc10e, 0x26ff, 0xc10e, 0x21, 0 + .dw 0x2740, 0xc10e, 0x277f, 0xc10e, 0x21, 0 + .dw 0x27c0, 0xc10e, 0x27ff, 0xc10e, 0x21, 0 + .dw 0x2840, 0xc10e, 0x287f, 0xc10e, 0x21, 0 + .dw 0x28c0, 0xc10e, 0x28ff, 0xc10e, 0x21, 0 + .dw 0x2940, 0xc10e, 0x297f, 0xc10e, 0x21, 0 + .dw 0x29c0, 0xc10e, 0x29ff, 0xc10e, 0x21, 0 + .dw 0x2a40, 0xc10e, 0x2a7f, 0xc10e, 0x21, 0 + .dw 0x2ac0, 0xc10e, 0x2aff, 0xc10e, 0x21, 0 + .dw 0x2b40, 0xc10e, 0x2b7f, 0xc10e, 0x21, 0 + .dw 0x2bc0, 0xc10e, 0x2bff, 0xc10e, 0x21, 0 + .dw 0x2c40, 0xc10e, 0x2c7f, 0xc10e, 0x21, 0 + .dw 0x2cc0, 0xc10e, 0x2cff, 0xc10e, 0x21, 0 + .dw 0x2d40, 0xc10e, 0x2d7f, 0xc10e, 0x21, 0 + .dw 0x2dc0, 0xc10e, 0x2dff, 0xc10e, 0x21, 0 + .dw 0x2e40, 0xc10e, 0x2e7f, 0xc10e, 0x21, 0 + .dw 0x2ec0, 0xc10e, 0x2eff, 0xc10e, 0x21, 0 + .dw 0x2f40, 0xc10e, 0x2f7f, 0xc10e, 0x21, 0 + .dw 0x2fc0, 0xc10e, 0x2fff, 0xc10e, 0x21, 0 + .dw 0x3040, 0xc10e, 0x307f, 0xc10e, 0x21, 0 + .dw 0x30c0, 0xc10e, 0x30ff, 0xc10e, 0x21, 0 + .dw 0x3140, 0xc10e, 0x317f, 0xc10e, 0x21, 0 + .dw 0x31c0, 0xc10e, 0x31ff, 0xc10e, 0x21, 0 + .dw 0x3240, 0xc10e, 0x327f, 0xc10e, 0x21, 0 + .dw 0x32c0, 0xc10e, 0x32ff, 0xc10e, 0x21, 0 + .dw 0x3340, 0xc10e, 0x337f, 0xc10e, 0x21, 0 + .dw 0x33c0, 0xc10e, 0x33ff, 0xc10e, 0x21, 0 + .dw 0x3440, 0xc10e, 0x347f, 0xc10e, 0x21, 0 + .dw 0x34c0, 0xc10e, 0x34ff, 0xc10e, 0x21, 0 + .dw 0x3540, 0xc10e, 0x357f, 0xc10e, 0x21, 0 + .dw 0x35c0, 0xc10e, 0x35ff, 0xc10e, 0x21, 0 + .dw 0x3640, 0xc10e, 0x367f, 0xc10e, 0x21, 0 + .dw 0x36c0, 0xc10e, 0x36ff, 0xc10e, 0x21, 0 + .dw 0x3740, 0xc10e, 0x377f, 0xc10e, 0x21, 0 + .dw 0x37c0, 0xc10e, 0x37ff, 0xc10e, 0x21, 0 + .dw 0x3840, 0xc10e, 0x387f, 0xc10e, 0x21, 0 + .dw 0x38c0, 0xc10e, 0x38ff, 0xc10e, 0x21, 0 + .dw 0x3940, 0xc10e, 0x397f, 0xc10e, 0x21, 0 + .dw 0x39c0, 0xc10e, 0x3fff, 0xc10e, 0x21, 0 + .dw 0x4040, 0xc10e, 0x407f, 0xc10e, 0x21, 0 + .dw 0x40c0, 0xc10e, 0x40ff, 0xc10e, 0x21, 0 + .dw 0x4140, 0xc10e, 0x417f, 0xc10e, 0x21, 0 + .dw 0x41c0, 0xc10e, 0x41ff, 0xc10e, 0x21, 0 + .dw 0x4240, 0xc10e, 0x427f, 0xc10e, 0x21, 0 + .dw 0x42c0, 0xc10e, 0x42ff, 0xc10e, 0x21, 0 + .dw 0x4340, 0xc10e, 0x437f, 0xc10e, 0x21, 0 + .dw 0x43c0, 0xc10e, 0x43ff, 0xc10e, 0x21, 0 + .dw 0x4440, 0xc10e, 0x447f, 0xc10e, 0x21, 0 + .dw 0x44c0, 0xc10e, 0x44ff, 0xc10e, 0x21, 0 + .dw 0x4540, 0xc10e, 0x457f, 0xc10e, 0x21, 0 + .dw 0x45c0, 0xc10e, 0x45ff, 0xc10e, 0x21, 0 + .dw 0x4640, 0xc10e, 0x467f, 0xc10e, 0x21, 0 + .dw 0x46c0, 0xc10e, 0x46ff, 0xc10e, 0x21, 0 + .dw 0x4740, 0xc10e, 0x477f, 0xc10e, 0x21, 0 + .dw 0x47c0, 0xc10e, 0x47ff, 0xc10e, 0x21, 0 + .dw 0x4840, 0xc10e, 0x487f, 0xc10e, 0x21, 0 + .dw 0x48c0, 0xc10e, 0x48ff, 0xc10e, 0x21, 0 + .dw 0x4940, 0xc10e, 0x497f, 0xc10e, 0x21, 0 + .dw 0x49c0, 0xc10e, 0x49ff, 0xc10e, 0x21, 0 + .dw 0x4a40, 0xc10e, 0x4a7f, 0xc10e, 0x21, 0 + .dw 0x4ac0, 0xc10e, 0x4aff, 0xc10e, 0x21, 0 + .dw 0x4b40, 0xc10e, 0x4b7f, 0xc10e, 0x21, 0 + .dw 0x4bc0, 0xc10e, 0x4bff, 0xc10e, 0x21, 0 + .dw 0x4c40, 0xc10e, 0x4c7f, 0xc10e, 0x21, 0 + .dw 0x4cc0, 0xc10e, 0x4cff, 0xc10e, 0x21, 0 + .dw 0x4d40, 0xc10e, 0x4d7f, 0xc10e, 0x21, 0 + .dw 0x4dc0, 0xc10e, 0x4dff, 0xc10e, 0x21, 0 + .dw 0x4e40, 0xc10e, 0x4e7f, 0xc10e, 0x21, 0 + .dw 0x4ec0, 0xc10e, 0x4eff, 0xc10e, 0x21, 0 + .dw 0x4f40, 0xc10e, 0x4f7f, 0xc10e, 0x21, 0 + .dw 0x4fc0, 0xc10e, 0x4fff, 0xc10e, 0x21, 0 + .dw 0x5040, 0xc10e, 0x507f, 0xc10e, 0x21, 0 + .dw 0x50c0, 0xc10e, 0x50ff, 0xc10e, 0x21, 0 + .dw 0x5140, 0xc10e, 0x517f, 0xc10e, 0x21, 0 + .dw 0x51c0, 0xc10e, 0x51ff, 0xc10e, 0x21, 0 + .dw 0x5240, 0xc10e, 0x527f, 0xc10e, 0x21, 0 + .dw 0x52c0, 0xc10e, 0x52ff, 0xc10e, 0x21, 0 + .dw 0x5340, 0xc10e, 0x537f, 0xc10e, 0x21, 0 + .dw 0x53c0, 0xc10e, 0x53ff, 0xc10e, 0x21, 0 + .dw 0x5440, 0xc10e, 0x547f, 0xc10e, 0x21, 0 + .dw 0x54c0, 0xc10e, 0x54ff, 0xc10e, 0x21, 0 + .dw 0x5540, 0xc10e, 0x557f, 0xc10e, 0x21, 0 + .dw 0x55c0, 0xc10e, 0x55ff, 0xc10e, 0x21, 0 + .dw 0x5640, 0xc10e, 0x567f, 0xc10e, 0x21, 0 + .dw 0x56c0, 0xc10e, 0x56ff, 0xc10e, 0x21, 0 + .dw 0x5740, 0xc10e, 0x577f, 0xc10e, 0x21, 0 + .dw 0x57c0, 0xc10e, 0x57ff, 0xc10e, 0x21, 0 + .dw 0x5840, 0xc10e, 0x587f, 0xc10e, 0x21, 0 + .dw 0x58c0, 0xc10e, 0x58ff, 0xc10e, 0x21, 0 + .dw 0x5940, 0xc10e, 0x597f, 0xc10e, 0x21, 0 + .dw 0x59c0, 0xc10e, 0x5fff, 0xc10e, 0x21, 0 + .dw 0x6040, 0xc10e, 0x607f, 0xc10e, 0x21, 0 + .dw 0x60c0, 0xc10e, 0x60ff, 0xc10e, 0x21, 0 + .dw 0x6140, 0xc10e, 0x617f, 0xc10e, 0x21, 0 + .dw 0x61c0, 0xc10e, 0x61ff, 0xc10e, 0x21, 0 + .dw 0x6240, 0xc10e, 0x627f, 0xc10e, 0x21, 0 + .dw 0x62c0, 0xc10e, 0x62ff, 0xc10e, 0x21, 0 + .dw 0x6340, 0xc10e, 0x637f, 0xc10e, 0x21, 0 + .dw 0x63c0, 0xc10e, 0x63ff, 0xc10e, 0x21, 0 + .dw 0x6440, 0xc10e, 0x647f, 0xc10e, 0x21, 0 + .dw 0x64c0, 0xc10e, 0x64ff, 0xc10e, 0x21, 0 + .dw 0x6540, 0xc10e, 0x657f, 0xc10e, 0x21, 0 + .dw 0x65c0, 0xc10e, 0x65ff, 0xc10e, 0x21, 0 + .dw 0x6640, 0xc10e, 0x667f, 0xc10e, 0x21, 0 + .dw 0x66c0, 0xc10e, 0x66ff, 0xc10e, 0x21, 0 + .dw 0x6740, 0xc10e, 0x677f, 0xc10e, 0x21, 0 + .dw 0x67c0, 0xc10e, 0x67ff, 0xc10e, 0x21, 0 + .dw 0x6840, 0xc10e, 0x687f, 0xc10e, 0x21, 0 + .dw 0x68c0, 0xc10e, 0x68ff, 0xc10e, 0x21, 0 + .dw 0x6940, 0xc10e, 0x697f, 0xc10e, 0x21, 0 + .dw 0x69c0, 0xc10e, 0x69ff, 0xc10e, 0x21, 0 + .dw 0x6a40, 0xc10e, 0x6a7f, 0xc10e, 0x21, 0 + .dw 0x6ac0, 0xc10e, 0x6aff, 0xc10e, 0x21, 0 + .dw 0x6b40, 0xc10e, 0x6b7f, 0xc10e, 0x21, 0 + .dw 0x6bc0, 0xc10e, 0x6bff, 0xc10e, 0x21, 0 + .dw 0x6c40, 0xc10e, 0x6c7f, 0xc10e, 0x21, 0 + .dw 0x6cc0, 0xc10e, 0x6cff, 0xc10e, 0x21, 0 + .dw 0x6d40, 0xc10e, 0x6d7f, 0xc10e, 0x21, 0 + .dw 0x6dc0, 0xc10e, 0x6dff, 0xc10e, 0x21, 0 + .dw 0x6e40, 0xc10e, 0x6e7f, 0xc10e, 0x21, 0 + .dw 0x6ec0, 0xc10e, 0x6eff, 0xc10e, 0x21, 0 + .dw 0x6f40, 0xc10e, 0x6f7f, 0xc10e, 0x21, 0 + .dw 0x6fc0, 0xc10e, 0x6fff, 0xc10e, 0x21, 0 + .dw 0x7040, 0xc10e, 0x707f, 0xc10e, 0x21, 0 + .dw 0x70c0, 0xc10e, 0x70ff, 0xc10e, 0x21, 0 + .dw 0x7140, 0xc10e, 0x717f, 0xc10e, 0x21, 0 + .dw 0x71c0, 0xc10e, 0x71ff, 0xc10e, 0x21, 0 + .dw 0x7240, 0xc10e, 0x727f, 0xc10e, 0x21, 0 + .dw 0x72c0, 0xc10e, 0x72ff, 0xc10e, 0x21, 0 + .dw 0x7340, 0xc10e, 0x737f, 0xc10e, 0x21, 0 + .dw 0x73c0, 0xc10e, 0x73ff, 0xc10e, 0x21, 0 + .dw 0x7440, 0xc10e, 0x747f, 0xc10e, 0x21, 0 + .dw 0x74c0, 0xc10e, 0x74ff, 0xc10e, 0x21, 0 + .dw 0x7540, 0xc10e, 0x757f, 0xc10e, 0x21, 0 + .dw 0x75c0, 0xc10e, 0x75ff, 0xc10e, 0x21, 0 + .dw 0x7640, 0xc10e, 0x767f, 0xc10e, 0x21, 0 + .dw 0x76c0, 0xc10e, 0x76ff, 0xc10e, 0x21, 0 + .dw 0x7740, 0xc10e, 0x777f, 0xc10e, 0x21, 0 + .dw 0x77c0, 0xc10e, 0x77ff, 0xc10e, 0x21, 0 + .dw 0x7840, 0xc10e, 0x787f, 0xc10e, 0x21, 0 + .dw 0x78c0, 0xc10e, 0x78ff, 0xc10e, 0x21, 0 + .dw 0x7940, 0xc10e, 0x797f, 0xc10e, 0x21, 0 + .dw 0x79c0, 0xc10e, 0x7fff, 0xc10e, 0x21, 0 + .dw 0x8040, 0xc10e, 0x807f, 0xc10e, 0x21, 0 + .dw 0x80c0, 0xc10e, 0x80ff, 0xc10e, 0x21, 0 + .dw 0x8140, 0xc10e, 0x817f, 0xc10e, 0x21, 0 + .dw 0x81c0, 0xc10e, 0x81ff, 0xc10e, 0x21, 0 + .dw 0x8240, 0xc10e, 0x827f, 0xc10e, 0x21, 0 + .dw 0x82c0, 0xc10e, 0x82ff, 0xc10e, 0x21, 0 + .dw 0x8340, 0xc10e, 0x837f, 0xc10e, 0x21, 0 + .dw 0x83c0, 0xc10e, 0x83ff, 0xc10e, 0x21, 0 + .dw 0x8440, 0xc10e, 0x847f, 0xc10e, 0x21, 0 + .dw 0x84c0, 0xc10e, 0x84ff, 0xc10e, 0x21, 0 + .dw 0x8540, 0xc10e, 0x857f, 0xc10e, 0x21, 0 + .dw 0x85c0, 0xc10e, 0x85ff, 0xc10e, 0x21, 0 + .dw 0x8640, 0xc10e, 0x867f, 0xc10e, 0x21, 0 + .dw 0x86c0, 0xc10e, 0x86ff, 0xc10e, 0x21, 0 + .dw 0x8740, 0xc10e, 0x877f, 0xc10e, 0x21, 0 + .dw 0x87c0, 0xc10e, 0x87ff, 0xc10e, 0x21, 0 + .dw 0x8840, 0xc10e, 0x887f, 0xc10e, 0x21, 0 + .dw 0x88c0, 0xc10e, 0x88ff, 0xc10e, 0x21, 0 + .dw 0x8940, 0xc10e, 0x897f, 0xc10e, 0x21, 0 + .dw 0x89c0, 0xc10e, 0x89ff, 0xc10e, 0x21, 0 + .dw 0x8a40, 0xc10e, 0x8a7f, 0xc10e, 0x21, 0 + .dw 0x8ac0, 0xc10e, 0x8aff, 0xc10e, 0x21, 0 + .dw 0x8b40, 0xc10e, 0x8b7f, 0xc10e, 0x21, 0 + .dw 0x8bc0, 0xc10e, 0x8bff, 0xc10e, 0x21, 0 + .dw 0x8c40, 0xc10e, 0x8c7f, 0xc10e, 0x21, 0 + .dw 0x8cc0, 0xc10e, 0x8cff, 0xc10e, 0x21, 0 + .dw 0x8d40, 0xc10e, 0x8d7f, 0xc10e, 0x21, 0 + .dw 0x8dc0, 0xc10e, 0x8dff, 0xc10e, 0x21, 0 + .dw 0x8e40, 0xc10e, 0x8e7f, 0xc10e, 0x21, 0 + .dw 0x8ec0, 0xc10e, 0x8eff, 0xc10e, 0x21, 0 + .dw 0x8f40, 0xc10e, 0x8f7f, 0xc10e, 0x21, 0 + .dw 0x8fc0, 0xc10e, 0x8fff, 0xc10e, 0x21, 0 + .dw 0x9040, 0xc10e, 0x907f, 0xc10e, 0x21, 0 + .dw 0x90c0, 0xc10e, 0x90ff, 0xc10e, 0x21, 0 + .dw 0x9140, 0xc10e, 0x917f, 0xc10e, 0x21, 0 + .dw 0x91c0, 0xc10e, 0x91ff, 0xc10e, 0x21, 0 + .dw 0x9240, 0xc10e, 0x927f, 0xc10e, 0x21, 0 + .dw 0x92c0, 0xc10e, 0x92ff, 0xc10e, 0x21, 0 + .dw 0x9340, 0xc10e, 0x937f, 0xc10e, 0x21, 0 + .dw 0x93c0, 0xc10e, 0x93ff, 0xc10e, 0x21, 0 + .dw 0x9440, 0xc10e, 0x947f, 0xc10e, 0x21, 0 + .dw 0x94c0, 0xc10e, 0x94ff, 0xc10e, 0x21, 0 + .dw 0x9540, 0xc10e, 0x957f, 0xc10e, 0x21, 0 + .dw 0x95c0, 0xc10e, 0x95ff, 0xc10e, 0x21, 0 + .dw 0x9640, 0xc10e, 0x967f, 0xc10e, 0x21, 0 + .dw 0x96c0, 0xc10e, 0x96ff, 0xc10e, 0x21, 0 + .dw 0x9740, 0xc10e, 0x977f, 0xc10e, 0x21, 0 + .dw 0x97c0, 0xc10e, 0x97ff, 0xc10e, 0x21, 0 + .dw 0x9840, 0xc10e, 0x987f, 0xc10e, 0x21, 0 + .dw 0x98c0, 0xc10e, 0x98ff, 0xc10e, 0x21, 0 + .dw 0x9940, 0xc10e, 0x997f, 0xc10e, 0x21, 0 + .dw 0x99c0, 0xc10e, 0x9fff, 0xc10e, 0x21, 0 + .dw 0xa040, 0xc10e, 0xa07f, 0xc10e, 0x21, 0 + .dw 0xa0c0, 0xc10e, 0xa0ff, 0xc10e, 0x21, 0 + .dw 0xa140, 0xc10e, 0xa17f, 0xc10e, 0x21, 0 + .dw 0xa1c0, 0xc10e, 0xa1ff, 0xc10e, 0x21, 0 + .dw 0xa240, 0xc10e, 0xa27f, 0xc10e, 0x21, 0 + .dw 0xa2c0, 0xc10e, 0xa2ff, 0xc10e, 0x21, 0 + .dw 0xa340, 0xc10e, 0xa37f, 0xc10e, 0x21, 0 + .dw 0xa3c0, 0xc10e, 0xa3ff, 0xc10e, 0x21, 0 + .dw 0xa440, 0xc10e, 0xa47f, 0xc10e, 0x21, 0 + .dw 0xa4c0, 0xc10e, 0xa4ff, 0xc10e, 0x21, 0 + .dw 0xa540, 0xc10e, 0xa57f, 0xc10e, 0x21, 0 + .dw 0xa5c0, 0xc10e, 0xa5ff, 0xc10e, 0x21, 0 + .dw 0xa640, 0xc10e, 0xa67f, 0xc10e, 0x21, 0 + .dw 0xa6c0, 0xc10e, 0xa6ff, 0xc10e, 0x21, 0 + .dw 0xa740, 0xc10e, 0xa77f, 0xc10e, 0x21, 0 + .dw 0xa7c0, 0xc10e, 0xa7ff, 0xc10e, 0x21, 0 + .dw 0xa840, 0xc10e, 0xa87f, 0xc10e, 0x21, 0 + .dw 0xa8c0, 0xc10e, 0xa8ff, 0xc10e, 0x21, 0 + .dw 0xa940, 0xc10e, 0xa97f, 0xc10e, 0x21, 0 + .dw 0xa9c0, 0xc10e, 0xa9ff, 0xc10e, 0x21, 0 + .dw 0xaa40, 0xc10e, 0xaa7f, 0xc10e, 0x21, 0 + .dw 0xaac0, 0xc10e, 0xaaff, 0xc10e, 0x21, 0 + .dw 0xab40, 0xc10e, 0xab7f, 0xc10e, 0x21, 0 + .dw 0xabc0, 0xc10e, 0xabff, 0xc10e, 0x21, 0 + .dw 0xac40, 0xc10e, 0xac7f, 0xc10e, 0x21, 0 + .dw 0xacc0, 0xc10e, 0xacff, 0xc10e, 0x21, 0 + .dw 0xad40, 0xc10e, 0xad7f, 0xc10e, 0x21, 0 + .dw 0xadc0, 0xc10e, 0xadff, 0xc10e, 0x21, 0 + .dw 0xae40, 0xc10e, 0xae7f, 0xc10e, 0x21, 0 + .dw 0xaec0, 0xc10e, 0xaeff, 0xc10e, 0x21, 0 + .dw 0xaf40, 0xc10e, 0xaf7f, 0xc10e, 0x21, 0 + .dw 0xafc0, 0xc10e, 0xafff, 0xc10e, 0x21, 0 + .dw 0xb040, 0xc10e, 0xb07f, 0xc10e, 0x21, 0 + .dw 0xb0c0, 0xc10e, 0xb0ff, 0xc10e, 0x21, 0 + .dw 0xb140, 0xc10e, 0xb17f, 0xc10e, 0x21, 0 + .dw 0xb1c0, 0xc10e, 0xb1ff, 0xc10e, 0x21, 0 + .dw 0xb240, 0xc10e, 0xb27f, 0xc10e, 0x21, 0 + .dw 0xb2c0, 0xc10e, 0xb2ff, 0xc10e, 0x21, 0 + .dw 0xb340, 0xc10e, 0xb37f, 0xc10e, 0x21, 0 + .dw 0xb3c0, 0xc10e, 0xb3ff, 0xc10e, 0x21, 0 + .dw 0xb440, 0xc10e, 0xb47f, 0xc10e, 0x21, 0 + .dw 0xb4c0, 0xc10e, 0xb4ff, 0xc10e, 0x21, 0 + .dw 0xb540, 0xc10e, 0xb57f, 0xc10e, 0x21, 0 + .dw 0xb5c0, 0xc10e, 0xb5ff, 0xc10e, 0x21, 0 + .dw 0xb640, 0xc10e, 0xb67f, 0xc10e, 0x21, 0 + .dw 0xb6c0, 0xc10e, 0xb6ff, 0xc10e, 0x21, 0 + .dw 0xb740, 0xc10e, 0xb77f, 0xc10e, 0x21, 0 + .dw 0xb7c0, 0xc10e, 0xb7ff, 0xc10e, 0x21, 0 + .dw 0xb840, 0xc10e, 0xb87f, 0xc10e, 0x21, 0 + .dw 0xb8c0, 0xc10e, 0xb8ff, 0xc10e, 0x21, 0 + .dw 0xb940, 0xc10e, 0xb97f, 0xc10e, 0x21, 0 + .dw 0xb9c0, 0xc10e, 0xbfff, 0xc10e, 0x21, 0 + .dw 0xc040, 0xc10e, 0xc07f, 0xc10e, 0x21, 0 + .dw 0xc0c0, 0xc10e, 0xc0ff, 0xc10e, 0x21, 0 + .dw 0xc140, 0xc10e, 0xc17f, 0xc10e, 0x21, 0 + .dw 0xc1c0, 0xc10e, 0xc1ff, 0xc10e, 0x21, 0 + .dw 0xc240, 0xc10e, 0xc27f, 0xc10e, 0x21, 0 + .dw 0xc2c0, 0xc10e, 0xc2ff, 0xc10e, 0x21, 0 + .dw 0xc340, 0xc10e, 0xc37f, 0xc10e, 0x21, 0 + .dw 0xc3c0, 0xc10e, 0xc3ff, 0xc10e, 0x21, 0 + .dw 0xc440, 0xc10e, 0xc47f, 0xc10e, 0x21, 0 + .dw 0xc4c0, 0xc10e, 0xc4ff, 0xc10e, 0x21, 0 + .dw 0xc540, 0xc10e, 0xc57f, 0xc10e, 0x21, 0 + .dw 0xc5c0, 0xc10e, 0xc5ff, 0xc10e, 0x21, 0 + .dw 0xc640, 0xc10e, 0xc67f, 0xc10e, 0x21, 0 + .dw 0xc6c0, 0xc10e, 0xc6ff, 0xc10e, 0x21, 0 + .dw 0xc740, 0xc10e, 0xc77f, 0xc10e, 0x21, 0 + .dw 0xc7c0, 0xc10e, 0xc7ff, 0xc10e, 0x21, 0 + .dw 0xc840, 0xc10e, 0xc87f, 0xc10e, 0x21, 0 + .dw 0xc8c0, 0xc10e, 0xc8ff, 0xc10e, 0x21, 0 + .dw 0xc940, 0xc10e, 0xc97f, 0xc10e, 0x21, 0 + .dw 0xc9c0, 0xc10e, 0xc9ff, 0xc10e, 0x21, 0 + .dw 0xca40, 0xc10e, 0xca7f, 0xc10e, 0x21, 0 + .dw 0xcac0, 0xc10e, 0xcaff, 0xc10e, 0x21, 0 + .dw 0xcb40, 0xc10e, 0xcb7f, 0xc10e, 0x21, 0 + .dw 0xcbc0, 0xc10e, 0xcbff, 0xc10e, 0x21, 0 + .dw 0xcc40, 0xc10e, 0xcc7f, 0xc10e, 0x21, 0 + .dw 0xccc0, 0xc10e, 0xccff, 0xc10e, 0x21, 0 + .dw 0xcd40, 0xc10e, 0xcd7f, 0xc10e, 0x21, 0 + .dw 0xcdc0, 0xc10e, 0xcdff, 0xc10e, 0x21, 0 + .dw 0xce40, 0xc10e, 0xce7f, 0xc10e, 0x21, 0 + .dw 0xcec0, 0xc10e, 0xceff, 0xc10e, 0x21, 0 + .dw 0xcf40, 0xc10e, 0xcf7f, 0xc10e, 0x21, 0 + .dw 0xcfc0, 0xc10e, 0xcfff, 0xc10e, 0x21, 0 + .dw 0xd040, 0xc10e, 0xd07f, 0xc10e, 0x21, 0 + .dw 0xd0c0, 0xc10e, 0xd0ff, 0xc10e, 0x21, 0 + .dw 0xd140, 0xc10e, 0xd17f, 0xc10e, 0x21, 0 + .dw 0xd1c0, 0xc10e, 0xd1ff, 0xc10e, 0x21, 0 + .dw 0xd240, 0xc10e, 0xd27f, 0xc10e, 0x21, 0 + .dw 0xd2c0, 0xc10e, 0xd2ff, 0xc10e, 0x21, 0 + .dw 0xd340, 0xc10e, 0xd37f, 0xc10e, 0x21, 0 + .dw 0xd3c0, 0xc10e, 0xd3ff, 0xc10e, 0x21, 0 + .dw 0xd440, 0xc10e, 0xd47f, 0xc10e, 0x21, 0 + .dw 0xd4c0, 0xc10e, 0xd4ff, 0xc10e, 0x21, 0 + .dw 0xd540, 0xc10e, 0xd57f, 0xc10e, 0x21, 0 + .dw 0xd5c0, 0xc10e, 0xd5ff, 0xc10e, 0x21, 0 + .dw 0xd640, 0xc10e, 0xd67f, 0xc10e, 0x21, 0 + .dw 0xd6c0, 0xc10e, 0xd6ff, 0xc10e, 0x21, 0 + .dw 0xd740, 0xc10e, 0xd77f, 0xc10e, 0x21, 0 + .dw 0xd7c0, 0xc10e, 0xd7ff, 0xc10e, 0x21, 0 + .dw 0xd840, 0xc10e, 0xd87f, 0xc10e, 0x21, 0 + .dw 0xd8c0, 0xc10e, 0xd8ff, 0xc10e, 0x21, 0 + .dw 0xd940, 0xc10e, 0xd97f, 0xc10e, 0x21, 0 + .dw 0xd9c0, 0xc10e, 0xdfff, 0xc10e, 0x21, 0 + .dw 0xe040, 0xc10e, 0xe07f, 0xc10e, 0x21, 0 + .dw 0xe0c0, 0xc10e, 0xe0ff, 0xc10e, 0x21, 0 + .dw 0xe140, 0xc10e, 0xe17f, 0xc10e, 0x21, 0 + .dw 0xe1c0, 0xc10e, 0xe1ff, 0xc10e, 0x21, 0 + .dw 0xe240, 0xc10e, 0xe27f, 0xc10e, 0x21, 0 + .dw 0xe2c0, 0xc10e, 0xe2ff, 0xc10e, 0x21, 0 + .dw 0xe340, 0xc10e, 0xe37f, 0xc10e, 0x21, 0 + .dw 0xe3c0, 0xc10e, 0xe3ff, 0xc10e, 0x21, 0 + .dw 0xe440, 0xc10e, 0xe47f, 0xc10e, 0x21, 0 + .dw 0xe4c0, 0xc10e, 0xe4ff, 0xc10e, 0x21, 0 + .dw 0xe540, 0xc10e, 0xe57f, 0xc10e, 0x21, 0 + .dw 0xe5c0, 0xc10e, 0xe5ff, 0xc10e, 0x21, 0 + .dw 0xe640, 0xc10e, 0xe67f, 0xc10e, 0x21, 0 + .dw 0xe6c0, 0xc10e, 0xe6ff, 0xc10e, 0x21, 0 + .dw 0xe740, 0xc10e, 0xe77f, 0xc10e, 0x21, 0 + .dw 0xe7c0, 0xc10e, 0xe7ff, 0xc10e, 0x21, 0 + .dw 0xe840, 0xc10e, 0xe87f, 0xc10e, 0x21, 0 + .dw 0xe8c0, 0xc10e, 0xe8ff, 0xc10e, 0x21, 0 + .dw 0xe940, 0xc10e, 0xe97f, 0xc10e, 0x21, 0 + .dw 0xe9c0, 0xc10e, 0xe9ff, 0xc10e, 0x21, 0 + .dw 0xea40, 0xc10e, 0xea7f, 0xc10e, 0x21, 0 + .dw 0xeac0, 0xc10e, 0xeaff, 0xc10e, 0x21, 0 + .dw 0xeb40, 0xc10e, 0xeb7f, 0xc10e, 0x21, 0 + .dw 0xebc0, 0xc10e, 0xebff, 0xc10e, 0x21, 0 + .dw 0xec40, 0xc10e, 0xec7f, 0xc10e, 0x21, 0 + .dw 0xecc0, 0xc10e, 0xecff, 0xc10e, 0x21, 0 + .dw 0xed40, 0xc10e, 0xed7f, 0xc10e, 0x21, 0 + .dw 0xedc0, 0xc10e, 0xedff, 0xc10e, 0x21, 0 + .dw 0xee40, 0xc10e, 0xee7f, 0xc10e, 0x21, 0 + .dw 0xeec0, 0xc10e, 0xeeff, 0xc10e, 0x21, 0 + .dw 0xef40, 0xc10e, 0xef7f, 0xc10e, 0x21, 0 + .dw 0xefc0, 0xc10e, 0xefff, 0xc10e, 0x21, 0 + .dw 0xf040, 0xc10e, 0xf07f, 0xc10e, 0x21, 0 + .dw 0xf0c0, 0xc10e, 0xf0ff, 0xc10e, 0x21, 0 + .dw 0xf140, 0xc10e, 0xf17f, 0xc10e, 0x21, 0 + .dw 0xf1c0, 0xc10e, 0xf1ff, 0xc10e, 0x21, 0 + .dw 0xf240, 0xc10e, 0xf27f, 0xc10e, 0x21, 0 + .dw 0xf2c0, 0xc10e, 0xf2ff, 0xc10e, 0x21, 0 + .dw 0xf340, 0xc10e, 0xf37f, 0xc10e, 0x21, 0 + .dw 0xf3c0, 0xc10e, 0xf3ff, 0xc10e, 0x21, 0 + .dw 0xf440, 0xc10e, 0xf47f, 0xc10e, 0x21, 0 + .dw 0xf4c0, 0xc10e, 0xf4ff, 0xc10e, 0x21, 0 + .dw 0xf540, 0xc10e, 0xf57f, 0xc10e, 0x21, 0 + .dw 0xf5c0, 0xc10e, 0xf5ff, 0xc10e, 0x21, 0 + .dw 0xf640, 0xc10e, 0xf67f, 0xc10e, 0x21, 0 + .dw 0xf6c0, 0xc10e, 0xf6ff, 0xc10e, 0x21, 0 + .dw 0xf740, 0xc10e, 0xf77f, 0xc10e, 0x21, 0 + .dw 0xf7c0, 0xc10e, 0xf7ff, 0xc10e, 0x21, 0 + .dw 0xf840, 0xc10e, 0xf87f, 0xc10e, 0x21, 0 + .dw 0xf8c0, 0xc10e, 0xf8ff, 0xc10e, 0x21, 0 + .dw 0xf940, 0xc10e, 0xf97f, 0xc10e, 0x21, 0 + .dw 0xf9c0, 0xc10e, 0xffff, 0xc10e, 0x21, 0 + .dw 0x0040, 0xc10f, 0x007f, 0xc10f, 0x21, 0 + .dw 0x00c0, 0xc10f, 0x00ff, 0xc10f, 0x21, 0 + .dw 0x0140, 0xc10f, 0x017f, 0xc10f, 0x21, 0 + .dw 0x01c0, 0xc10f, 0x01ff, 0xc10f, 0x21, 0 + .dw 0x0240, 0xc10f, 0x027f, 0xc10f, 0x21, 0 + .dw 0x02c0, 0xc10f, 0x02ff, 0xc10f, 0x21, 0 + .dw 0x0340, 0xc10f, 0x037f, 0xc10f, 0x21, 0 + .dw 0x03c0, 0xc10f, 0x03ff, 0xc10f, 0x21, 0 + .dw 0x0440, 0xc10f, 0x047f, 0xc10f, 0x21, 0 + .dw 0x04c0, 0xc10f, 0x04ff, 0xc10f, 0x21, 0 + .dw 0x0540, 0xc10f, 0x057f, 0xc10f, 0x21, 0 + .dw 0x05c0, 0xc10f, 0x05ff, 0xc10f, 0x21, 0 + .dw 0x0640, 0xc10f, 0x067f, 0xc10f, 0x21, 0 + .dw 0x06c0, 0xc10f, 0x06ff, 0xc10f, 0x21, 0 + .dw 0x0740, 0xc10f, 0x077f, 0xc10f, 0x21, 0 + .dw 0x07c0, 0xc10f, 0x07ff, 0xc10f, 0x21, 0 + .dw 0x0840, 0xc10f, 0x087f, 0xc10f, 0x21, 0 + .dw 0x08c0, 0xc10f, 0x08ff, 0xc10f, 0x21, 0 + .dw 0x0940, 0xc10f, 0x097f, 0xc10f, 0x21, 0 + .dw 0x09c0, 0xc10f, 0x09ff, 0xc10f, 0x21, 0 + .dw 0x0a40, 0xc10f, 0x0a7f, 0xc10f, 0x21, 0 + .dw 0x0ac0, 0xc10f, 0x0aff, 0xc10f, 0x21, 0 + .dw 0x0b40, 0xc10f, 0x0b7f, 0xc10f, 0x21, 0 + .dw 0x0bc0, 0xc10f, 0x0bff, 0xc10f, 0x21, 0 + .dw 0x0c40, 0xc10f, 0x0c7f, 0xc10f, 0x21, 0 + .dw 0x0cc0, 0xc10f, 0x0cff, 0xc10f, 0x21, 0 + .dw 0x0d40, 0xc10f, 0x0d7f, 0xc10f, 0x21, 0 + .dw 0x0dc0, 0xc10f, 0x0dff, 0xc10f, 0x21, 0 + .dw 0x0e40, 0xc10f, 0x0e7f, 0xc10f, 0x21, 0 + .dw 0x0ec0, 0xc10f, 0x0eff, 0xc10f, 0x21, 0 + .dw 0x0f40, 0xc10f, 0x0f7f, 0xc10f, 0x21, 0 + .dw 0x0fc0, 0xc10f, 0x0fff, 0xc10f, 0x21, 0 + .dw 0x1040, 0xc10f, 0x107f, 0xc10f, 0x21, 0 + .dw 0x10c0, 0xc10f, 0x10ff, 0xc10f, 0x21, 0 + .dw 0x1140, 0xc10f, 0x117f, 0xc10f, 0x21, 0 + .dw 0x11c0, 0xc10f, 0x11ff, 0xc10f, 0x21, 0 + .dw 0x1240, 0xc10f, 0x127f, 0xc10f, 0x21, 0 + .dw 0x12c0, 0xc10f, 0x12ff, 0xc10f, 0x21, 0 + .dw 0x1340, 0xc10f, 0x137f, 0xc10f, 0x21, 0 + .dw 0x13c0, 0xc10f, 0x13ff, 0xc10f, 0x21, 0 + .dw 0x1440, 0xc10f, 0x147f, 0xc10f, 0x21, 0 + .dw 0x14c0, 0xc10f, 0x14ff, 0xc10f, 0x21, 0 + .dw 0x1540, 0xc10f, 0x157f, 0xc10f, 0x21, 0 + .dw 0x15c0, 0xc10f, 0x15ff, 0xc10f, 0x21, 0 + .dw 0x1640, 0xc10f, 0x167f, 0xc10f, 0x21, 0 + .dw 0x16c0, 0xc10f, 0x16ff, 0xc10f, 0x21, 0 + .dw 0x1740, 0xc10f, 0x177f, 0xc10f, 0x21, 0 + .dw 0x17c0, 0xc10f, 0x17ff, 0xc10f, 0x21, 0 + .dw 0x1840, 0xc10f, 0x187f, 0xc10f, 0x21, 0 + .dw 0x18c0, 0xc10f, 0x18ff, 0xc10f, 0x21, 0 + .dw 0x1940, 0xc10f, 0x197f, 0xc10f, 0x21, 0 + .dw 0x19c0, 0xc10f, 0x1fff, 0xc10f, 0x21, 0 + .dw 0x2040, 0xc10f, 0x207f, 0xc10f, 0x21, 0 + .dw 0x20c0, 0xc10f, 0x20ff, 0xc10f, 0x21, 0 + .dw 0x2140, 0xc10f, 0x217f, 0xc10f, 0x21, 0 + .dw 0x21c0, 0xc10f, 0x21ff, 0xc10f, 0x21, 0 + .dw 0x2240, 0xc10f, 0x227f, 0xc10f, 0x21, 0 + .dw 0x22c0, 0xc10f, 0x22ff, 0xc10f, 0x21, 0 + .dw 0x2340, 0xc10f, 0x237f, 0xc10f, 0x21, 0 + .dw 0x23c0, 0xc10f, 0x23ff, 0xc10f, 0x21, 0 + .dw 0x2440, 0xc10f, 0x247f, 0xc10f, 0x21, 0 + .dw 0x24c0, 0xc10f, 0x24ff, 0xc10f, 0x21, 0 + .dw 0x2540, 0xc10f, 0x257f, 0xc10f, 0x21, 0 + .dw 0x25c0, 0xc10f, 0x25ff, 0xc10f, 0x21, 0 + .dw 0x2640, 0xc10f, 0x267f, 0xc10f, 0x21, 0 + .dw 0x26c0, 0xc10f, 0x26ff, 0xc10f, 0x21, 0 + .dw 0x2740, 0xc10f, 0x277f, 0xc10f, 0x21, 0 + .dw 0x27c0, 0xc10f, 0x27ff, 0xc10f, 0x21, 0 + .dw 0x2840, 0xc10f, 0x287f, 0xc10f, 0x21, 0 + .dw 0x28c0, 0xc10f, 0x28ff, 0xc10f, 0x21, 0 + .dw 0x2940, 0xc10f, 0x297f, 0xc10f, 0x21, 0 + .dw 0x29c0, 0xc10f, 0x29ff, 0xc10f, 0x21, 0 + .dw 0x2a40, 0xc10f, 0x2a7f, 0xc10f, 0x21, 0 + .dw 0x2ac0, 0xc10f, 0x2aff, 0xc10f, 0x21, 0 + .dw 0x2b40, 0xc10f, 0x2b7f, 0xc10f, 0x21, 0 + .dw 0x2bc0, 0xc10f, 0x2bff, 0xc10f, 0x21, 0 + .dw 0x2c40, 0xc10f, 0x2c7f, 0xc10f, 0x21, 0 + .dw 0x2cc0, 0xc10f, 0x2cff, 0xc10f, 0x21, 0 + .dw 0x2d40, 0xc10f, 0x2d7f, 0xc10f, 0x21, 0 + .dw 0x2dc0, 0xc10f, 0x2dff, 0xc10f, 0x21, 0 + .dw 0x2e40, 0xc10f, 0x2e7f, 0xc10f, 0x21, 0 + .dw 0x2ec0, 0xc10f, 0x2eff, 0xc10f, 0x21, 0 + .dw 0x2f40, 0xc10f, 0x2f7f, 0xc10f, 0x21, 0 + .dw 0x2fc0, 0xc10f, 0x2fff, 0xc10f, 0x21, 0 + .dw 0x3040, 0xc10f, 0x307f, 0xc10f, 0x21, 0 + .dw 0x30c0, 0xc10f, 0x30ff, 0xc10f, 0x21, 0 + .dw 0x3140, 0xc10f, 0x317f, 0xc10f, 0x21, 0 + .dw 0x31c0, 0xc10f, 0x31ff, 0xc10f, 0x21, 0 + .dw 0x3240, 0xc10f, 0x327f, 0xc10f, 0x21, 0 + .dw 0x32c0, 0xc10f, 0x32ff, 0xc10f, 0x21, 0 + .dw 0x3340, 0xc10f, 0x337f, 0xc10f, 0x21, 0 + .dw 0x33c0, 0xc10f, 0x33ff, 0xc10f, 0x21, 0 + .dw 0x3440, 0xc10f, 0x347f, 0xc10f, 0x21, 0 + .dw 0x34c0, 0xc10f, 0x34ff, 0xc10f, 0x21, 0 + .dw 0x3540, 0xc10f, 0x357f, 0xc10f, 0x21, 0 + .dw 0x35c0, 0xc10f, 0x35ff, 0xc10f, 0x21, 0 + .dw 0x3640, 0xc10f, 0x367f, 0xc10f, 0x21, 0 + .dw 0x36c0, 0xc10f, 0x36ff, 0xc10f, 0x21, 0 + .dw 0x3740, 0xc10f, 0x377f, 0xc10f, 0x21, 0 + .dw 0x37c0, 0xc10f, 0x37ff, 0xc10f, 0x21, 0 + .dw 0x3840, 0xc10f, 0x387f, 0xc10f, 0x21, 0 + .dw 0x38c0, 0xc10f, 0x38ff, 0xc10f, 0x21, 0 + .dw 0x3940, 0xc10f, 0x397f, 0xc10f, 0x21, 0 + .dw 0x39c0, 0xc10f, 0xffff, 0xc10f, 0x21, 0 + .dw 0x1a00, 0xc110, 0x1fff, 0xc110, 0x21, 0 + .dw 0x3a00, 0xc110, 0x3fff, 0xc110, 0x21, 0 + .dw 0x5a00, 0xc110, 0x5fff, 0xc110, 0x21, 0 + .dw 0x7a00, 0xc110, 0x7fff, 0xc110, 0x21, 0 + .dw 0x9a00, 0xc110, 0x9fff, 0xc110, 0x21, 0 + .dw 0xba00, 0xc110, 0xbfff, 0xc110, 0x21, 0 + .dw 0xda00, 0xc110, 0xdfff, 0xc110, 0x21, 0 + .dw 0xfa00, 0xc110, 0xffff, 0xc110, 0x21, 0 + .dw 0x1a00, 0xc111, 0x1fff, 0xc111, 0x21, 0 + .dw 0x3a00, 0xc111, 0x3fff, 0xc111, 0x21, 0 + .dw 0x5a00, 0xc111, 0x5fff, 0xc111, 0x21, 0 + .dw 0x7a00, 0xc111, 0x7fff, 0xc111, 0x21, 0 + .dw 0x9a00, 0xc111, 0x9fff, 0xc111, 0x21, 0 + .dw 0xba00, 0xc111, 0xbfff, 0xc111, 0x21, 0 + .dw 0xda00, 0xc111, 0xdfff, 0xc111, 0x21, 0 + .dw 0xfa00, 0xc111, 0xffff, 0xc111, 0x21, 0 + .dw 0x1a00, 0xc112, 0x1fff, 0xc112, 0x21, 0 + .dw 0x3a00, 0xc112, 0x3fff, 0xc112, 0x21, 0 + .dw 0x5a00, 0xc112, 0x5fff, 0xc112, 0x21, 0 + .dw 0x7a00, 0xc112, 0x7fff, 0xc112, 0x21, 0 + .dw 0x9a00, 0xc112, 0x9fff, 0xc112, 0x21, 0 + .dw 0xba00, 0xc112, 0xbfff, 0xc112, 0x21, 0 + .dw 0xda00, 0xc112, 0xdfff, 0xc112, 0x21, 0 + .dw 0xfa00, 0xc112, 0xffff, 0xc113, 0x21, 0 + .dw 0x1a00, 0xc114, 0x1fff, 0xc114, 0x21, 0 + .dw 0x3a00, 0xc114, 0x3fff, 0xc114, 0x21, 0 + .dw 0x5a00, 0xc114, 0x5fff, 0xc114, 0x21, 0 + .dw 0x7a00, 0xc114, 0x7fff, 0xc114, 0x21, 0 + .dw 0x9a00, 0xc114, 0x9fff, 0xc114, 0x21, 0 + .dw 0xba00, 0xc114, 0xbfff, 0xc114, 0x21, 0 + .dw 0xda00, 0xc114, 0xdfff, 0xc114, 0x21, 0 + .dw 0xfa00, 0xc114, 0xffff, 0xc114, 0x21, 0 + .dw 0x1a00, 0xc115, 0x1fff, 0xc115, 0x21, 0 + .dw 0x3a00, 0xc115, 0x3fff, 0xc115, 0x21, 0 + .dw 0x5a00, 0xc115, 0x5fff, 0xc115, 0x21, 0 + .dw 0x7a00, 0xc115, 0x7fff, 0xc115, 0x21, 0 + .dw 0x9a00, 0xc115, 0x9fff, 0xc115, 0x21, 0 + .dw 0xba00, 0xc115, 0xbfff, 0xc115, 0x21, 0 + .dw 0xda00, 0xc115, 0xdfff, 0xc115, 0x21, 0 + .dw 0xfa00, 0xc115, 0xffff, 0xc115, 0x21, 0 + .dw 0x1a00, 0xc116, 0x1fff, 0xc116, 0x21, 0 + .dw 0x3a00, 0xc116, 0x3fff, 0xc116, 0x21, 0 + .dw 0x5a00, 0xc116, 0x5fff, 0xc116, 0x21, 0 + .dw 0x7a00, 0xc116, 0x7fff, 0xc116, 0x21, 0 + .dw 0x9a00, 0xc116, 0x9fff, 0xc116, 0x21, 0 + .dw 0xba00, 0xc116, 0xbfff, 0xc116, 0x21, 0 + .dw 0xda00, 0xc116, 0xdfff, 0xc116, 0x21, 0 + .dw 0xfa00, 0xc116, 0xffff, 0xc116, 0x21, 0 + .dw 0x1a00, 0xc117, 0x1fff, 0xc117, 0x21, 0 + .dw 0x3a00, 0xc117, 0x1fff, 0xc118, 0x21, 0 + .dw 0x2040, 0xc118, 0x207f, 0xc118, 0x21, 0 + .dw 0x20c0, 0xc118, 0x20ff, 0xc118, 0x21, 0 + .dw 0x2140, 0xc118, 0x217f, 0xc118, 0x21, 0 + .dw 0x21c0, 0xc118, 0x21ff, 0xc118, 0x21, 0 + .dw 0x2240, 0xc118, 0x227f, 0xc118, 0x21, 0 + .dw 0x22c0, 0xc118, 0x22ff, 0xc118, 0x21, 0 + .dw 0x2340, 0xc118, 0x237f, 0xc118, 0x21, 0 + .dw 0x23c0, 0xc118, 0x23ff, 0xc118, 0x21, 0 + .dw 0x2440, 0xc118, 0x247f, 0xc118, 0x21, 0 + .dw 0x24c0, 0xc118, 0x24ff, 0xc118, 0x21, 0 + .dw 0x2540, 0xc118, 0x257f, 0xc118, 0x21, 0 + .dw 0x25c0, 0xc118, 0x25ff, 0xc118, 0x21, 0 + .dw 0x2640, 0xc118, 0x267f, 0xc118, 0x21, 0 + .dw 0x26c0, 0xc118, 0x26ff, 0xc118, 0x21, 0 + .dw 0x2740, 0xc118, 0x277f, 0xc118, 0x21, 0 + .dw 0x27c0, 0xc118, 0x27ff, 0xc118, 0x21, 0 + .dw 0x2840, 0xc118, 0x287f, 0xc118, 0x21, 0 + .dw 0x28c0, 0xc118, 0x28ff, 0xc118, 0x21, 0 + .dw 0x2940, 0xc118, 0x297f, 0xc118, 0x21, 0 + .dw 0x29c0, 0xc118, 0x29ff, 0xc118, 0x21, 0 + .dw 0x2a40, 0xc118, 0x2a7f, 0xc118, 0x21, 0 + .dw 0x2ac0, 0xc118, 0x2aff, 0xc118, 0x21, 0 + .dw 0x2b40, 0xc118, 0x2b7f, 0xc118, 0x21, 0 + .dw 0x2bc0, 0xc118, 0x2bff, 0xc118, 0x21, 0 + .dw 0x2c40, 0xc118, 0x2c7f, 0xc118, 0x21, 0 + .dw 0x2cc0, 0xc118, 0x2cff, 0xc118, 0x21, 0 + .dw 0x2d40, 0xc118, 0x2d7f, 0xc118, 0x21, 0 + .dw 0x2dc0, 0xc118, 0x2dff, 0xc118, 0x21, 0 + .dw 0x2e40, 0xc118, 0x2e7f, 0xc118, 0x21, 0 + .dw 0x2ec0, 0xc118, 0x2eff, 0xc118, 0x21, 0 + .dw 0x2f40, 0xc118, 0x2f7f, 0xc118, 0x21, 0 + .dw 0x2fc0, 0xc118, 0x2fff, 0xc118, 0x21, 0 + .dw 0x3040, 0xc118, 0x307f, 0xc118, 0x21, 0 + .dw 0x30c0, 0xc118, 0x30ff, 0xc118, 0x21, 0 + .dw 0x3140, 0xc118, 0x317f, 0xc118, 0x21, 0 + .dw 0x31c0, 0xc118, 0x31ff, 0xc118, 0x21, 0 + .dw 0x3240, 0xc118, 0x327f, 0xc118, 0x21, 0 + .dw 0x32c0, 0xc118, 0x32ff, 0xc118, 0x21, 0 + .dw 0x3340, 0xc118, 0x337f, 0xc118, 0x21, 0 + .dw 0x33c0, 0xc118, 0x33ff, 0xc118, 0x21, 0 + .dw 0x3440, 0xc118, 0x347f, 0xc118, 0x21, 0 + .dw 0x34c0, 0xc118, 0x34ff, 0xc118, 0x21, 0 + .dw 0x3540, 0xc118, 0x357f, 0xc118, 0x21, 0 + .dw 0x35c0, 0xc118, 0x35ff, 0xc118, 0x21, 0 + .dw 0x3640, 0xc118, 0x367f, 0xc118, 0x21, 0 + .dw 0x36c0, 0xc118, 0x36ff, 0xc118, 0x21, 0 + .dw 0x3740, 0xc118, 0x377f, 0xc118, 0x21, 0 + .dw 0x37c0, 0xc118, 0x37ff, 0xc118, 0x21, 0 + .dw 0x3840, 0xc118, 0x387f, 0xc118, 0x21, 0 + .dw 0x38c0, 0xc118, 0x38ff, 0xc118, 0x21, 0 + .dw 0x3940, 0xc118, 0x397f, 0xc118, 0x21, 0 + .dw 0x39c0, 0xc118, 0x5fff, 0xc118, 0x21, 0 + .dw 0x6040, 0xc118, 0x607f, 0xc118, 0x21, 0 + .dw 0x60c0, 0xc118, 0x60ff, 0xc118, 0x21, 0 + .dw 0x6140, 0xc118, 0x617f, 0xc118, 0x21, 0 + .dw 0x61c0, 0xc118, 0x61ff, 0xc118, 0x21, 0 + .dw 0x6240, 0xc118, 0x627f, 0xc118, 0x21, 0 + .dw 0x62c0, 0xc118, 0x62ff, 0xc118, 0x21, 0 + .dw 0x6340, 0xc118, 0x637f, 0xc118, 0x21, 0 + .dw 0x63c0, 0xc118, 0x63ff, 0xc118, 0x21, 0 + .dw 0x6440, 0xc118, 0x647f, 0xc118, 0x21, 0 + .dw 0x64c0, 0xc118, 0x64ff, 0xc118, 0x21, 0 + .dw 0x6540, 0xc118, 0x657f, 0xc118, 0x21, 0 + .dw 0x65c0, 0xc118, 0x65ff, 0xc118, 0x21, 0 + .dw 0x6640, 0xc118, 0x667f, 0xc118, 0x21, 0 + .dw 0x66c0, 0xc118, 0x66ff, 0xc118, 0x21, 0 + .dw 0x6740, 0xc118, 0x677f, 0xc118, 0x21, 0 + .dw 0x67c0, 0xc118, 0x67ff, 0xc118, 0x21, 0 + .dw 0x6840, 0xc118, 0x687f, 0xc118, 0x21, 0 + .dw 0x68c0, 0xc118, 0x68ff, 0xc118, 0x21, 0 + .dw 0x6940, 0xc118, 0x697f, 0xc118, 0x21, 0 + .dw 0x69c0, 0xc118, 0x69ff, 0xc118, 0x21, 0 + .dw 0x6a40, 0xc118, 0x6a7f, 0xc118, 0x21, 0 + .dw 0x6ac0, 0xc118, 0x6aff, 0xc118, 0x21, 0 + .dw 0x6b40, 0xc118, 0x6b7f, 0xc118, 0x21, 0 + .dw 0x6bc0, 0xc118, 0x6bff, 0xc118, 0x21, 0 + .dw 0x6c40, 0xc118, 0x6c7f, 0xc118, 0x21, 0 + .dw 0x6cc0, 0xc118, 0x6cff, 0xc118, 0x21, 0 + .dw 0x6d40, 0xc118, 0x6d7f, 0xc118, 0x21, 0 + .dw 0x6dc0, 0xc118, 0x6dff, 0xc118, 0x21, 0 + .dw 0x6e40, 0xc118, 0x6e7f, 0xc118, 0x21, 0 + .dw 0x6ec0, 0xc118, 0x6eff, 0xc118, 0x21, 0 + .dw 0x6f40, 0xc118, 0x6f7f, 0xc118, 0x21, 0 + .dw 0x6fc0, 0xc118, 0x6fff, 0xc118, 0x21, 0 + .dw 0x7040, 0xc118, 0x707f, 0xc118, 0x21, 0 + .dw 0x70c0, 0xc118, 0x70ff, 0xc118, 0x21, 0 + .dw 0x7140, 0xc118, 0x717f, 0xc118, 0x21, 0 + .dw 0x71c0, 0xc118, 0x71ff, 0xc118, 0x21, 0 + .dw 0x7240, 0xc118, 0x727f, 0xc118, 0x21, 0 + .dw 0x72c0, 0xc118, 0x72ff, 0xc118, 0x21, 0 + .dw 0x7340, 0xc118, 0x737f, 0xc118, 0x21, 0 + .dw 0x73c0, 0xc118, 0x73ff, 0xc118, 0x21, 0 + .dw 0x7440, 0xc118, 0x747f, 0xc118, 0x21, 0 + .dw 0x74c0, 0xc118, 0x74ff, 0xc118, 0x21, 0 + .dw 0x7540, 0xc118, 0x757f, 0xc118, 0x21, 0 + .dw 0x75c0, 0xc118, 0x75ff, 0xc118, 0x21, 0 + .dw 0x7640, 0xc118, 0x767f, 0xc118, 0x21, 0 + .dw 0x76c0, 0xc118, 0x76ff, 0xc118, 0x21, 0 + .dw 0x7740, 0xc118, 0x777f, 0xc118, 0x21, 0 + .dw 0x77c0, 0xc118, 0x77ff, 0xc118, 0x21, 0 + .dw 0x7840, 0xc118, 0x787f, 0xc118, 0x21, 0 + .dw 0x78c0, 0xc118, 0x78ff, 0xc118, 0x21, 0 + .dw 0x7940, 0xc118, 0x797f, 0xc118, 0x21, 0 + .dw 0x79c0, 0xc118, 0x9fff, 0xc118, 0x21, 0 + .dw 0xa040, 0xc118, 0xa07f, 0xc118, 0x21, 0 + .dw 0xa0c0, 0xc118, 0xa0ff, 0xc118, 0x21, 0 + .dw 0xa140, 0xc118, 0xa17f, 0xc118, 0x21, 0 + .dw 0xa1c0, 0xc118, 0xa1ff, 0xc118, 0x21, 0 + .dw 0xa240, 0xc118, 0xa27f, 0xc118, 0x21, 0 + .dw 0xa2c0, 0xc118, 0xa2ff, 0xc118, 0x21, 0 + .dw 0xa340, 0xc118, 0xa37f, 0xc118, 0x21, 0 + .dw 0xa3c0, 0xc118, 0xa3ff, 0xc118, 0x21, 0 + .dw 0xa440, 0xc118, 0xa47f, 0xc118, 0x21, 0 + .dw 0xa4c0, 0xc118, 0xa4ff, 0xc118, 0x21, 0 + .dw 0xa540, 0xc118, 0xa57f, 0xc118, 0x21, 0 + .dw 0xa5c0, 0xc118, 0xa5ff, 0xc118, 0x21, 0 + .dw 0xa640, 0xc118, 0xa67f, 0xc118, 0x21, 0 + .dw 0xa6c0, 0xc118, 0xa6ff, 0xc118, 0x21, 0 + .dw 0xa740, 0xc118, 0xa77f, 0xc118, 0x21, 0 + .dw 0xa7c0, 0xc118, 0xa7ff, 0xc118, 0x21, 0 + .dw 0xa840, 0xc118, 0xa87f, 0xc118, 0x21, 0 + .dw 0xa8c0, 0xc118, 0xa8ff, 0xc118, 0x21, 0 + .dw 0xa940, 0xc118, 0xa97f, 0xc118, 0x21, 0 + .dw 0xa9c0, 0xc118, 0xa9ff, 0xc118, 0x21, 0 + .dw 0xaa40, 0xc118, 0xaa7f, 0xc118, 0x21, 0 + .dw 0xaac0, 0xc118, 0xaaff, 0xc118, 0x21, 0 + .dw 0xab40, 0xc118, 0xab7f, 0xc118, 0x21, 0 + .dw 0xabc0, 0xc118, 0xabff, 0xc118, 0x21, 0 + .dw 0xac40, 0xc118, 0xac7f, 0xc118, 0x21, 0 + .dw 0xacc0, 0xc118, 0xacff, 0xc118, 0x21, 0 + .dw 0xad40, 0xc118, 0xad7f, 0xc118, 0x21, 0 + .dw 0xadc0, 0xc118, 0xadff, 0xc118, 0x21, 0 + .dw 0xae40, 0xc118, 0xae7f, 0xc118, 0x21, 0 + .dw 0xaec0, 0xc118, 0xaeff, 0xc118, 0x21, 0 + .dw 0xaf40, 0xc118, 0xaf7f, 0xc118, 0x21, 0 + .dw 0xafc0, 0xc118, 0xafff, 0xc118, 0x21, 0 + .dw 0xb040, 0xc118, 0xb07f, 0xc118, 0x21, 0 + .dw 0xb0c0, 0xc118, 0xb0ff, 0xc118, 0x21, 0 + .dw 0xb140, 0xc118, 0xb17f, 0xc118, 0x21, 0 + .dw 0xb1c0, 0xc118, 0xb1ff, 0xc118, 0x21, 0 + .dw 0xb240, 0xc118, 0xb27f, 0xc118, 0x21, 0 + .dw 0xb2c0, 0xc118, 0xb2ff, 0xc118, 0x21, 0 + .dw 0xb340, 0xc118, 0xb37f, 0xc118, 0x21, 0 + .dw 0xb3c0, 0xc118, 0xb3ff, 0xc118, 0x21, 0 + .dw 0xb440, 0xc118, 0xb47f, 0xc118, 0x21, 0 + .dw 0xb4c0, 0xc118, 0xb4ff, 0xc118, 0x21, 0 + .dw 0xb540, 0xc118, 0xb57f, 0xc118, 0x21, 0 + .dw 0xb5c0, 0xc118, 0xb5ff, 0xc118, 0x21, 0 + .dw 0xb640, 0xc118, 0xb67f, 0xc118, 0x21, 0 + .dw 0xb6c0, 0xc118, 0xb6ff, 0xc118, 0x21, 0 + .dw 0xb740, 0xc118, 0xb77f, 0xc118, 0x21, 0 + .dw 0xb7c0, 0xc118, 0xb7ff, 0xc118, 0x21, 0 + .dw 0xb840, 0xc118, 0xb87f, 0xc118, 0x21, 0 + .dw 0xb8c0, 0xc118, 0xb8ff, 0xc118, 0x21, 0 + .dw 0xb940, 0xc118, 0xb97f, 0xc118, 0x21, 0 + .dw 0xb9c0, 0xc118, 0xdfff, 0xc118, 0x21, 0 + .dw 0xe040, 0xc118, 0xe07f, 0xc118, 0x21, 0 + .dw 0xe0c0, 0xc118, 0xe0ff, 0xc118, 0x21, 0 + .dw 0xe140, 0xc118, 0xe17f, 0xc118, 0x21, 0 + .dw 0xe1c0, 0xc118, 0xe1ff, 0xc118, 0x21, 0 + .dw 0xe240, 0xc118, 0xe27f, 0xc118, 0x21, 0 + .dw 0xe2c0, 0xc118, 0xe2ff, 0xc118, 0x21, 0 + .dw 0xe340, 0xc118, 0xe37f, 0xc118, 0x21, 0 + .dw 0xe3c0, 0xc118, 0xe3ff, 0xc118, 0x21, 0 + .dw 0xe440, 0xc118, 0xe47f, 0xc118, 0x21, 0 + .dw 0xe4c0, 0xc118, 0xe4ff, 0xc118, 0x21, 0 + .dw 0xe540, 0xc118, 0xe57f, 0xc118, 0x21, 0 + .dw 0xe5c0, 0xc118, 0xe5ff, 0xc118, 0x21, 0 + .dw 0xe640, 0xc118, 0xe67f, 0xc118, 0x21, 0 + .dw 0xe6c0, 0xc118, 0xe6ff, 0xc118, 0x21, 0 + .dw 0xe740, 0xc118, 0xe77f, 0xc118, 0x21, 0 + .dw 0xe7c0, 0xc118, 0xe7ff, 0xc118, 0x21, 0 + .dw 0xe840, 0xc118, 0xe87f, 0xc118, 0x21, 0 + .dw 0xe8c0, 0xc118, 0xe8ff, 0xc118, 0x21, 0 + .dw 0xe940, 0xc118, 0xe97f, 0xc118, 0x21, 0 + .dw 0xe9c0, 0xc118, 0xe9ff, 0xc118, 0x21, 0 + .dw 0xea40, 0xc118, 0xea7f, 0xc118, 0x21, 0 + .dw 0xeac0, 0xc118, 0xeaff, 0xc118, 0x21, 0 + .dw 0xeb40, 0xc118, 0xeb7f, 0xc118, 0x21, 0 + .dw 0xebc0, 0xc118, 0xebff, 0xc118, 0x21, 0 + .dw 0xec40, 0xc118, 0xec7f, 0xc118, 0x21, 0 + .dw 0xecc0, 0xc118, 0xecff, 0xc118, 0x21, 0 + .dw 0xed40, 0xc118, 0xed7f, 0xc118, 0x21, 0 + .dw 0xedc0, 0xc118, 0xedff, 0xc118, 0x21, 0 + .dw 0xee40, 0xc118, 0xee7f, 0xc118, 0x21, 0 + .dw 0xeec0, 0xc118, 0xeeff, 0xc118, 0x21, 0 + .dw 0xef40, 0xc118, 0xef7f, 0xc118, 0x21, 0 + .dw 0xefc0, 0xc118, 0xefff, 0xc118, 0x21, 0 + .dw 0xf040, 0xc118, 0xf07f, 0xc118, 0x21, 0 + .dw 0xf0c0, 0xc118, 0xf0ff, 0xc118, 0x21, 0 + .dw 0xf140, 0xc118, 0xf17f, 0xc118, 0x21, 0 + .dw 0xf1c0, 0xc118, 0xf1ff, 0xc118, 0x21, 0 + .dw 0xf240, 0xc118, 0xf27f, 0xc118, 0x21, 0 + .dw 0xf2c0, 0xc118, 0xf2ff, 0xc118, 0x21, 0 + .dw 0xf340, 0xc118, 0xf37f, 0xc118, 0x21, 0 + .dw 0xf3c0, 0xc118, 0xf3ff, 0xc118, 0x21, 0 + .dw 0xf440, 0xc118, 0xf47f, 0xc118, 0x21, 0 + .dw 0xf4c0, 0xc118, 0xf4ff, 0xc118, 0x21, 0 + .dw 0xf540, 0xc118, 0xf57f, 0xc118, 0x21, 0 + .dw 0xf5c0, 0xc118, 0xf5ff, 0xc118, 0x21, 0 + .dw 0xf640, 0xc118, 0xf67f, 0xc118, 0x21, 0 + .dw 0xf6c0, 0xc118, 0xf6ff, 0xc118, 0x21, 0 + .dw 0xf740, 0xc118, 0xf77f, 0xc118, 0x21, 0 + .dw 0xf7c0, 0xc118, 0xf7ff, 0xc118, 0x21, 0 + .dw 0xf840, 0xc118, 0xf87f, 0xc118, 0x21, 0 + .dw 0xf8c0, 0xc118, 0xf8ff, 0xc118, 0x21, 0 + .dw 0xf940, 0xc118, 0xf97f, 0xc118, 0x21, 0 + .dw 0xf9c0, 0xc118, 0x1fff, 0xc119, 0x21, 0 + .dw 0x2040, 0xc119, 0x207f, 0xc119, 0x21, 0 + .dw 0x20c0, 0xc119, 0x20ff, 0xc119, 0x21, 0 + .dw 0x2140, 0xc119, 0x217f, 0xc119, 0x21, 0 + .dw 0x21c0, 0xc119, 0x21ff, 0xc119, 0x21, 0 + .dw 0x2240, 0xc119, 0x227f, 0xc119, 0x21, 0 + .dw 0x22c0, 0xc119, 0x22ff, 0xc119, 0x21, 0 + .dw 0x2340, 0xc119, 0x237f, 0xc119, 0x21, 0 + .dw 0x23c0, 0xc119, 0x23ff, 0xc119, 0x21, 0 + .dw 0x2440, 0xc119, 0x247f, 0xc119, 0x21, 0 + .dw 0x24c0, 0xc119, 0x24ff, 0xc119, 0x21, 0 + .dw 0x2540, 0xc119, 0x257f, 0xc119, 0x21, 0 + .dw 0x25c0, 0xc119, 0x25ff, 0xc119, 0x21, 0 + .dw 0x2640, 0xc119, 0x267f, 0xc119, 0x21, 0 + .dw 0x26c0, 0xc119, 0x26ff, 0xc119, 0x21, 0 + .dw 0x2740, 0xc119, 0x277f, 0xc119, 0x21, 0 + .dw 0x27c0, 0xc119, 0x27ff, 0xc119, 0x21, 0 + .dw 0x2840, 0xc119, 0x287f, 0xc119, 0x21, 0 + .dw 0x28c0, 0xc119, 0x28ff, 0xc119, 0x21, 0 + .dw 0x2940, 0xc119, 0x297f, 0xc119, 0x21, 0 + .dw 0x29c0, 0xc119, 0x29ff, 0xc119, 0x21, 0 + .dw 0x2a40, 0xc119, 0x2a7f, 0xc119, 0x21, 0 + .dw 0x2ac0, 0xc119, 0x2aff, 0xc119, 0x21, 0 + .dw 0x2b40, 0xc119, 0x2b7f, 0xc119, 0x21, 0 + .dw 0x2bc0, 0xc119, 0x2bff, 0xc119, 0x21, 0 + .dw 0x2c40, 0xc119, 0x2c7f, 0xc119, 0x21, 0 + .dw 0x2cc0, 0xc119, 0x2cff, 0xc119, 0x21, 0 + .dw 0x2d40, 0xc119, 0x2d7f, 0xc119, 0x21, 0 + .dw 0x2dc0, 0xc119, 0x2dff, 0xc119, 0x21, 0 + .dw 0x2e40, 0xc119, 0x2e7f, 0xc119, 0x21, 0 + .dw 0x2ec0, 0xc119, 0x2eff, 0xc119, 0x21, 0 + .dw 0x2f40, 0xc119, 0x2f7f, 0xc119, 0x21, 0 + .dw 0x2fc0, 0xc119, 0x2fff, 0xc119, 0x21, 0 + .dw 0x3040, 0xc119, 0x307f, 0xc119, 0x21, 0 + .dw 0x30c0, 0xc119, 0x30ff, 0xc119, 0x21, 0 + .dw 0x3140, 0xc119, 0x317f, 0xc119, 0x21, 0 + .dw 0x31c0, 0xc119, 0x31ff, 0xc119, 0x21, 0 + .dw 0x3240, 0xc119, 0x327f, 0xc119, 0x21, 0 + .dw 0x32c0, 0xc119, 0x32ff, 0xc119, 0x21, 0 + .dw 0x3340, 0xc119, 0x337f, 0xc119, 0x21, 0 + .dw 0x33c0, 0xc119, 0x33ff, 0xc119, 0x21, 0 + .dw 0x3440, 0xc119, 0x347f, 0xc119, 0x21, 0 + .dw 0x34c0, 0xc119, 0x34ff, 0xc119, 0x21, 0 + .dw 0x3540, 0xc119, 0x357f, 0xc119, 0x21, 0 + .dw 0x35c0, 0xc119, 0x35ff, 0xc119, 0x21, 0 + .dw 0x3640, 0xc119, 0x367f, 0xc119, 0x21, 0 + .dw 0x36c0, 0xc119, 0x36ff, 0xc119, 0x21, 0 + .dw 0x3740, 0xc119, 0x377f, 0xc119, 0x21, 0 + .dw 0x37c0, 0xc119, 0x37ff, 0xc119, 0x21, 0 + .dw 0x3840, 0xc119, 0x387f, 0xc119, 0x21, 0 + .dw 0x38c0, 0xc119, 0x38ff, 0xc119, 0x21, 0 + .dw 0x3940, 0xc119, 0x397f, 0xc119, 0x21, 0 + .dw 0x39c0, 0xc119, 0x5fff, 0xc119, 0x21, 0 + .dw 0x6040, 0xc119, 0x607f, 0xc119, 0x21, 0 + .dw 0x60c0, 0xc119, 0x60ff, 0xc119, 0x21, 0 + .dw 0x6140, 0xc119, 0x617f, 0xc119, 0x21, 0 + .dw 0x61c0, 0xc119, 0x61ff, 0xc119, 0x21, 0 + .dw 0x6240, 0xc119, 0x627f, 0xc119, 0x21, 0 + .dw 0x62c0, 0xc119, 0x62ff, 0xc119, 0x21, 0 + .dw 0x6340, 0xc119, 0x637f, 0xc119, 0x21, 0 + .dw 0x63c0, 0xc119, 0x63ff, 0xc119, 0x21, 0 + .dw 0x6440, 0xc119, 0x647f, 0xc119, 0x21, 0 + .dw 0x64c0, 0xc119, 0x64ff, 0xc119, 0x21, 0 + .dw 0x6540, 0xc119, 0x657f, 0xc119, 0x21, 0 + .dw 0x65c0, 0xc119, 0x65ff, 0xc119, 0x21, 0 + .dw 0x6640, 0xc119, 0x667f, 0xc119, 0x21, 0 + .dw 0x66c0, 0xc119, 0x66ff, 0xc119, 0x21, 0 + .dw 0x6740, 0xc119, 0x677f, 0xc119, 0x21, 0 + .dw 0x67c0, 0xc119, 0x67ff, 0xc119, 0x21, 0 + .dw 0x6840, 0xc119, 0x687f, 0xc119, 0x21, 0 + .dw 0x68c0, 0xc119, 0x68ff, 0xc119, 0x21, 0 + .dw 0x6940, 0xc119, 0x697f, 0xc119, 0x21, 0 + .dw 0x69c0, 0xc119, 0x69ff, 0xc119, 0x21, 0 + .dw 0x6a40, 0xc119, 0x6a7f, 0xc119, 0x21, 0 + .dw 0x6ac0, 0xc119, 0x6aff, 0xc119, 0x21, 0 + .dw 0x6b40, 0xc119, 0x6b7f, 0xc119, 0x21, 0 + .dw 0x6bc0, 0xc119, 0x6bff, 0xc119, 0x21, 0 + .dw 0x6c40, 0xc119, 0x6c7f, 0xc119, 0x21, 0 + .dw 0x6cc0, 0xc119, 0x6cff, 0xc119, 0x21, 0 + .dw 0x6d40, 0xc119, 0x6d7f, 0xc119, 0x21, 0 + .dw 0x6dc0, 0xc119, 0x6dff, 0xc119, 0x21, 0 + .dw 0x6e40, 0xc119, 0x6e7f, 0xc119, 0x21, 0 + .dw 0x6ec0, 0xc119, 0x6eff, 0xc119, 0x21, 0 + .dw 0x6f40, 0xc119, 0x6f7f, 0xc119, 0x21, 0 + .dw 0x6fc0, 0xc119, 0x6fff, 0xc119, 0x21, 0 + .dw 0x7040, 0xc119, 0x707f, 0xc119, 0x21, 0 + .dw 0x70c0, 0xc119, 0x70ff, 0xc119, 0x21, 0 + .dw 0x7140, 0xc119, 0x717f, 0xc119, 0x21, 0 + .dw 0x71c0, 0xc119, 0x71ff, 0xc119, 0x21, 0 + .dw 0x7240, 0xc119, 0x727f, 0xc119, 0x21, 0 + .dw 0x72c0, 0xc119, 0x72ff, 0xc119, 0x21, 0 + .dw 0x7340, 0xc119, 0x737f, 0xc119, 0x21, 0 + .dw 0x73c0, 0xc119, 0x73ff, 0xc119, 0x21, 0 + .dw 0x7440, 0xc119, 0x747f, 0xc119, 0x21, 0 + .dw 0x74c0, 0xc119, 0x74ff, 0xc119, 0x21, 0 + .dw 0x7540, 0xc119, 0x757f, 0xc119, 0x21, 0 + .dw 0x75c0, 0xc119, 0x75ff, 0xc119, 0x21, 0 + .dw 0x7640, 0xc119, 0x767f, 0xc119, 0x21, 0 + .dw 0x76c0, 0xc119, 0x76ff, 0xc119, 0x21, 0 + .dw 0x7740, 0xc119, 0x777f, 0xc119, 0x21, 0 + .dw 0x77c0, 0xc119, 0x77ff, 0xc119, 0x21, 0 + .dw 0x7840, 0xc119, 0x787f, 0xc119, 0x21, 0 + .dw 0x78c0, 0xc119, 0x78ff, 0xc119, 0x21, 0 + .dw 0x7940, 0xc119, 0x797f, 0xc119, 0x21, 0 + .dw 0x79c0, 0xc119, 0x9fff, 0xc119, 0x21, 0 + .dw 0xa040, 0xc119, 0xa07f, 0xc119, 0x21, 0 + .dw 0xa0c0, 0xc119, 0xa0ff, 0xc119, 0x21, 0 + .dw 0xa140, 0xc119, 0xa17f, 0xc119, 0x21, 0 + .dw 0xa1c0, 0xc119, 0xa1ff, 0xc119, 0x21, 0 + .dw 0xa240, 0xc119, 0xa27f, 0xc119, 0x21, 0 + .dw 0xa2c0, 0xc119, 0xa2ff, 0xc119, 0x21, 0 + .dw 0xa340, 0xc119, 0xa37f, 0xc119, 0x21, 0 + .dw 0xa3c0, 0xc119, 0xa3ff, 0xc119, 0x21, 0 + .dw 0xa440, 0xc119, 0xa47f, 0xc119, 0x21, 0 + .dw 0xa4c0, 0xc119, 0xa4ff, 0xc119, 0x21, 0 + .dw 0xa540, 0xc119, 0xa57f, 0xc119, 0x21, 0 + .dw 0xa5c0, 0xc119, 0xa5ff, 0xc119, 0x21, 0 + .dw 0xa640, 0xc119, 0xa67f, 0xc119, 0x21, 0 + .dw 0xa6c0, 0xc119, 0xa6ff, 0xc119, 0x21, 0 + .dw 0xa740, 0xc119, 0xa77f, 0xc119, 0x21, 0 + .dw 0xa7c0, 0xc119, 0xa7ff, 0xc119, 0x21, 0 + .dw 0xa840, 0xc119, 0xa87f, 0xc119, 0x21, 0 + .dw 0xa8c0, 0xc119, 0xa8ff, 0xc119, 0x21, 0 + .dw 0xa940, 0xc119, 0xa97f, 0xc119, 0x21, 0 + .dw 0xa9c0, 0xc119, 0xa9ff, 0xc119, 0x21, 0 + .dw 0xaa40, 0xc119, 0xaa7f, 0xc119, 0x21, 0 + .dw 0xaac0, 0xc119, 0xaaff, 0xc119, 0x21, 0 + .dw 0xab40, 0xc119, 0xab7f, 0xc119, 0x21, 0 + .dw 0xabc0, 0xc119, 0xabff, 0xc119, 0x21, 0 + .dw 0xac40, 0xc119, 0xac7f, 0xc119, 0x21, 0 + .dw 0xacc0, 0xc119, 0xacff, 0xc119, 0x21, 0 + .dw 0xad40, 0xc119, 0xad7f, 0xc119, 0x21, 0 + .dw 0xadc0, 0xc119, 0xadff, 0xc119, 0x21, 0 + .dw 0xae40, 0xc119, 0xae7f, 0xc119, 0x21, 0 + .dw 0xaec0, 0xc119, 0xaeff, 0xc119, 0x21, 0 + .dw 0xaf40, 0xc119, 0xaf7f, 0xc119, 0x21, 0 + .dw 0xafc0, 0xc119, 0xafff, 0xc119, 0x21, 0 + .dw 0xb040, 0xc119, 0xb07f, 0xc119, 0x21, 0 + .dw 0xb0c0, 0xc119, 0xb0ff, 0xc119, 0x21, 0 + .dw 0xb140, 0xc119, 0xb17f, 0xc119, 0x21, 0 + .dw 0xb1c0, 0xc119, 0xb1ff, 0xc119, 0x21, 0 + .dw 0xb240, 0xc119, 0xb27f, 0xc119, 0x21, 0 + .dw 0xb2c0, 0xc119, 0xb2ff, 0xc119, 0x21, 0 + .dw 0xb340, 0xc119, 0xb37f, 0xc119, 0x21, 0 + .dw 0xb3c0, 0xc119, 0xb3ff, 0xc119, 0x21, 0 + .dw 0xb440, 0xc119, 0xb47f, 0xc119, 0x21, 0 + .dw 0xb4c0, 0xc119, 0xb4ff, 0xc119, 0x21, 0 + .dw 0xb540, 0xc119, 0xb57f, 0xc119, 0x21, 0 + .dw 0xb5c0, 0xc119, 0xb5ff, 0xc119, 0x21, 0 + .dw 0xb640, 0xc119, 0xb67f, 0xc119, 0x21, 0 + .dw 0xb6c0, 0xc119, 0xb6ff, 0xc119, 0x21, 0 + .dw 0xb740, 0xc119, 0xb77f, 0xc119, 0x21, 0 + .dw 0xb7c0, 0xc119, 0xb7ff, 0xc119, 0x21, 0 + .dw 0xb840, 0xc119, 0xb87f, 0xc119, 0x21, 0 + .dw 0xb8c0, 0xc119, 0xb8ff, 0xc119, 0x21, 0 + .dw 0xb940, 0xc119, 0xb97f, 0xc119, 0x21, 0 + .dw 0xb9c0, 0xc119, 0xdfff, 0xc119, 0x21, 0 + .dw 0xe040, 0xc119, 0xe07f, 0xc119, 0x21, 0 + .dw 0xe0c0, 0xc119, 0xe0ff, 0xc119, 0x21, 0 + .dw 0xe140, 0xc119, 0xe17f, 0xc119, 0x21, 0 + .dw 0xe1c0, 0xc119, 0xe1ff, 0xc119, 0x21, 0 + .dw 0xe240, 0xc119, 0xe27f, 0xc119, 0x21, 0 + .dw 0xe2c0, 0xc119, 0xe2ff, 0xc119, 0x21, 0 + .dw 0xe340, 0xc119, 0xe37f, 0xc119, 0x21, 0 + .dw 0xe3c0, 0xc119, 0xe3ff, 0xc119, 0x21, 0 + .dw 0xe440, 0xc119, 0xe47f, 0xc119, 0x21, 0 + .dw 0xe4c0, 0xc119, 0xe4ff, 0xc119, 0x21, 0 + .dw 0xe540, 0xc119, 0xe57f, 0xc119, 0x21, 0 + .dw 0xe5c0, 0xc119, 0xe5ff, 0xc119, 0x21, 0 + .dw 0xe640, 0xc119, 0xe67f, 0xc119, 0x21, 0 + .dw 0xe6c0, 0xc119, 0xe6ff, 0xc119, 0x21, 0 + .dw 0xe740, 0xc119, 0xe77f, 0xc119, 0x21, 0 + .dw 0xe7c0, 0xc119, 0xe7ff, 0xc119, 0x21, 0 + .dw 0xe840, 0xc119, 0xe87f, 0xc119, 0x21, 0 + .dw 0xe8c0, 0xc119, 0xe8ff, 0xc119, 0x21, 0 + .dw 0xe940, 0xc119, 0xe97f, 0xc119, 0x21, 0 + .dw 0xe9c0, 0xc119, 0xe9ff, 0xc119, 0x21, 0 + .dw 0xea40, 0xc119, 0xea7f, 0xc119, 0x21, 0 + .dw 0xeac0, 0xc119, 0xeaff, 0xc119, 0x21, 0 + .dw 0xeb40, 0xc119, 0xeb7f, 0xc119, 0x21, 0 + .dw 0xebc0, 0xc119, 0xebff, 0xc119, 0x21, 0 + .dw 0xec40, 0xc119, 0xec7f, 0xc119, 0x21, 0 + .dw 0xecc0, 0xc119, 0xecff, 0xc119, 0x21, 0 + .dw 0xed40, 0xc119, 0xed7f, 0xc119, 0x21, 0 + .dw 0xedc0, 0xc119, 0xedff, 0xc119, 0x21, 0 + .dw 0xee40, 0xc119, 0xee7f, 0xc119, 0x21, 0 + .dw 0xeec0, 0xc119, 0xeeff, 0xc119, 0x21, 0 + .dw 0xef40, 0xc119, 0xef7f, 0xc119, 0x21, 0 + .dw 0xefc0, 0xc119, 0xefff, 0xc119, 0x21, 0 + .dw 0xf040, 0xc119, 0xf07f, 0xc119, 0x21, 0 + .dw 0xf0c0, 0xc119, 0xf0ff, 0xc119, 0x21, 0 + .dw 0xf140, 0xc119, 0xf17f, 0xc119, 0x21, 0 + .dw 0xf1c0, 0xc119, 0xf1ff, 0xc119, 0x21, 0 + .dw 0xf240, 0xc119, 0xf27f, 0xc119, 0x21, 0 + .dw 0xf2c0, 0xc119, 0xf2ff, 0xc119, 0x21, 0 + .dw 0xf340, 0xc119, 0xf37f, 0xc119, 0x21, 0 + .dw 0xf3c0, 0xc119, 0xf3ff, 0xc119, 0x21, 0 + .dw 0xf440, 0xc119, 0xf47f, 0xc119, 0x21, 0 + .dw 0xf4c0, 0xc119, 0xf4ff, 0xc119, 0x21, 0 + .dw 0xf540, 0xc119, 0xf57f, 0xc119, 0x21, 0 + .dw 0xf5c0, 0xc119, 0xf5ff, 0xc119, 0x21, 0 + .dw 0xf640, 0xc119, 0xf67f, 0xc119, 0x21, 0 + .dw 0xf6c0, 0xc119, 0xf6ff, 0xc119, 0x21, 0 + .dw 0xf740, 0xc119, 0xf77f, 0xc119, 0x21, 0 + .dw 0xf7c0, 0xc119, 0xf7ff, 0xc119, 0x21, 0 + .dw 0xf840, 0xc119, 0xf87f, 0xc119, 0x21, 0 + .dw 0xf8c0, 0xc119, 0xf8ff, 0xc119, 0x21, 0 + .dw 0xf940, 0xc119, 0xf97f, 0xc119, 0x21, 0 + .dw 0xf9c0, 0xc119, 0x1fff, 0xc11a, 0x21, 0 + .dw 0x2040, 0xc11a, 0x207f, 0xc11a, 0x21, 0 + .dw 0x20c0, 0xc11a, 0x20ff, 0xc11a, 0x21, 0 + .dw 0x2140, 0xc11a, 0x217f, 0xc11a, 0x21, 0 + .dw 0x21c0, 0xc11a, 0x21ff, 0xc11a, 0x21, 0 + .dw 0x2240, 0xc11a, 0x227f, 0xc11a, 0x21, 0 + .dw 0x22c0, 0xc11a, 0x22ff, 0xc11a, 0x21, 0 + .dw 0x2340, 0xc11a, 0x237f, 0xc11a, 0x21, 0 + .dw 0x23c0, 0xc11a, 0x23ff, 0xc11a, 0x21, 0 + .dw 0x2440, 0xc11a, 0x247f, 0xc11a, 0x21, 0 + .dw 0x24c0, 0xc11a, 0x24ff, 0xc11a, 0x21, 0 + .dw 0x2540, 0xc11a, 0x257f, 0xc11a, 0x21, 0 + .dw 0x25c0, 0xc11a, 0x25ff, 0xc11a, 0x21, 0 + .dw 0x2640, 0xc11a, 0x267f, 0xc11a, 0x21, 0 + .dw 0x26c0, 0xc11a, 0x26ff, 0xc11a, 0x21, 0 + .dw 0x2740, 0xc11a, 0x277f, 0xc11a, 0x21, 0 + .dw 0x27c0, 0xc11a, 0x27ff, 0xc11a, 0x21, 0 + .dw 0x2840, 0xc11a, 0x287f, 0xc11a, 0x21, 0 + .dw 0x28c0, 0xc11a, 0x28ff, 0xc11a, 0x21, 0 + .dw 0x2940, 0xc11a, 0x297f, 0xc11a, 0x21, 0 + .dw 0x29c0, 0xc11a, 0x29ff, 0xc11a, 0x21, 0 + .dw 0x2a40, 0xc11a, 0x2a7f, 0xc11a, 0x21, 0 + .dw 0x2ac0, 0xc11a, 0x2aff, 0xc11a, 0x21, 0 + .dw 0x2b40, 0xc11a, 0x2b7f, 0xc11a, 0x21, 0 + .dw 0x2bc0, 0xc11a, 0x2bff, 0xc11a, 0x21, 0 + .dw 0x2c40, 0xc11a, 0x2c7f, 0xc11a, 0x21, 0 + .dw 0x2cc0, 0xc11a, 0x2cff, 0xc11a, 0x21, 0 + .dw 0x2d40, 0xc11a, 0x2d7f, 0xc11a, 0x21, 0 + .dw 0x2dc0, 0xc11a, 0x2dff, 0xc11a, 0x21, 0 + .dw 0x2e40, 0xc11a, 0x2e7f, 0xc11a, 0x21, 0 + .dw 0x2ec0, 0xc11a, 0x2eff, 0xc11a, 0x21, 0 + .dw 0x2f40, 0xc11a, 0x2f7f, 0xc11a, 0x21, 0 + .dw 0x2fc0, 0xc11a, 0x2fff, 0xc11a, 0x21, 0 + .dw 0x3040, 0xc11a, 0x307f, 0xc11a, 0x21, 0 + .dw 0x30c0, 0xc11a, 0x30ff, 0xc11a, 0x21, 0 + .dw 0x3140, 0xc11a, 0x317f, 0xc11a, 0x21, 0 + .dw 0x31c0, 0xc11a, 0x31ff, 0xc11a, 0x21, 0 + .dw 0x3240, 0xc11a, 0x327f, 0xc11a, 0x21, 0 + .dw 0x32c0, 0xc11a, 0x32ff, 0xc11a, 0x21, 0 + .dw 0x3340, 0xc11a, 0x337f, 0xc11a, 0x21, 0 + .dw 0x33c0, 0xc11a, 0x33ff, 0xc11a, 0x21, 0 + .dw 0x3440, 0xc11a, 0x347f, 0xc11a, 0x21, 0 + .dw 0x34c0, 0xc11a, 0x34ff, 0xc11a, 0x21, 0 + .dw 0x3540, 0xc11a, 0x357f, 0xc11a, 0x21, 0 + .dw 0x35c0, 0xc11a, 0x35ff, 0xc11a, 0x21, 0 + .dw 0x3640, 0xc11a, 0x367f, 0xc11a, 0x21, 0 + .dw 0x36c0, 0xc11a, 0x36ff, 0xc11a, 0x21, 0 + .dw 0x3740, 0xc11a, 0x377f, 0xc11a, 0x21, 0 + .dw 0x37c0, 0xc11a, 0x37ff, 0xc11a, 0x21, 0 + .dw 0x3840, 0xc11a, 0x387f, 0xc11a, 0x21, 0 + .dw 0x38c0, 0xc11a, 0x38ff, 0xc11a, 0x21, 0 + .dw 0x3940, 0xc11a, 0x397f, 0xc11a, 0x21, 0 + .dw 0x39c0, 0xc11a, 0x5fff, 0xc11a, 0x21, 0 + .dw 0x6040, 0xc11a, 0x607f, 0xc11a, 0x21, 0 + .dw 0x60c0, 0xc11a, 0x60ff, 0xc11a, 0x21, 0 + .dw 0x6140, 0xc11a, 0x617f, 0xc11a, 0x21, 0 + .dw 0x61c0, 0xc11a, 0x61ff, 0xc11a, 0x21, 0 + .dw 0x6240, 0xc11a, 0x627f, 0xc11a, 0x21, 0 + .dw 0x62c0, 0xc11a, 0x62ff, 0xc11a, 0x21, 0 + .dw 0x6340, 0xc11a, 0x637f, 0xc11a, 0x21, 0 + .dw 0x63c0, 0xc11a, 0x63ff, 0xc11a, 0x21, 0 + .dw 0x6440, 0xc11a, 0x647f, 0xc11a, 0x21, 0 + .dw 0x64c0, 0xc11a, 0x64ff, 0xc11a, 0x21, 0 + .dw 0x6540, 0xc11a, 0x657f, 0xc11a, 0x21, 0 + .dw 0x65c0, 0xc11a, 0x65ff, 0xc11a, 0x21, 0 + .dw 0x6640, 0xc11a, 0x667f, 0xc11a, 0x21, 0 + .dw 0x66c0, 0xc11a, 0x66ff, 0xc11a, 0x21, 0 + .dw 0x6740, 0xc11a, 0x677f, 0xc11a, 0x21, 0 + .dw 0x67c0, 0xc11a, 0x67ff, 0xc11a, 0x21, 0 + .dw 0x6840, 0xc11a, 0x687f, 0xc11a, 0x21, 0 + .dw 0x68c0, 0xc11a, 0x68ff, 0xc11a, 0x21, 0 + .dw 0x6940, 0xc11a, 0x697f, 0xc11a, 0x21, 0 + .dw 0x69c0, 0xc11a, 0x69ff, 0xc11a, 0x21, 0 + .dw 0x6a40, 0xc11a, 0x6a7f, 0xc11a, 0x21, 0 + .dw 0x6ac0, 0xc11a, 0x6aff, 0xc11a, 0x21, 0 + .dw 0x6b40, 0xc11a, 0x6b7f, 0xc11a, 0x21, 0 + .dw 0x6bc0, 0xc11a, 0x6bff, 0xc11a, 0x21, 0 + .dw 0x6c40, 0xc11a, 0x6c7f, 0xc11a, 0x21, 0 + .dw 0x6cc0, 0xc11a, 0x6cff, 0xc11a, 0x21, 0 + .dw 0x6d40, 0xc11a, 0x6d7f, 0xc11a, 0x21, 0 + .dw 0x6dc0, 0xc11a, 0x6dff, 0xc11a, 0x21, 0 + .dw 0x6e40, 0xc11a, 0x6e7f, 0xc11a, 0x21, 0 + .dw 0x6ec0, 0xc11a, 0x6eff, 0xc11a, 0x21, 0 + .dw 0x6f40, 0xc11a, 0x6f7f, 0xc11a, 0x21, 0 + .dw 0x6fc0, 0xc11a, 0x6fff, 0xc11a, 0x21, 0 + .dw 0x7040, 0xc11a, 0x707f, 0xc11a, 0x21, 0 + .dw 0x70c0, 0xc11a, 0x70ff, 0xc11a, 0x21, 0 + .dw 0x7140, 0xc11a, 0x717f, 0xc11a, 0x21, 0 + .dw 0x71c0, 0xc11a, 0x71ff, 0xc11a, 0x21, 0 + .dw 0x7240, 0xc11a, 0x727f, 0xc11a, 0x21, 0 + .dw 0x72c0, 0xc11a, 0x72ff, 0xc11a, 0x21, 0 + .dw 0x7340, 0xc11a, 0x737f, 0xc11a, 0x21, 0 + .dw 0x73c0, 0xc11a, 0x73ff, 0xc11a, 0x21, 0 + .dw 0x7440, 0xc11a, 0x747f, 0xc11a, 0x21, 0 + .dw 0x74c0, 0xc11a, 0x74ff, 0xc11a, 0x21, 0 + .dw 0x7540, 0xc11a, 0x757f, 0xc11a, 0x21, 0 + .dw 0x75c0, 0xc11a, 0x75ff, 0xc11a, 0x21, 0 + .dw 0x7640, 0xc11a, 0x767f, 0xc11a, 0x21, 0 + .dw 0x76c0, 0xc11a, 0x76ff, 0xc11a, 0x21, 0 + .dw 0x7740, 0xc11a, 0x777f, 0xc11a, 0x21, 0 + .dw 0x77c0, 0xc11a, 0x77ff, 0xc11a, 0x21, 0 + .dw 0x7840, 0xc11a, 0x787f, 0xc11a, 0x21, 0 + .dw 0x78c0, 0xc11a, 0x78ff, 0xc11a, 0x21, 0 + .dw 0x7940, 0xc11a, 0x797f, 0xc11a, 0x21, 0 + .dw 0x79c0, 0xc11a, 0x9fff, 0xc11a, 0x21, 0 + .dw 0xa040, 0xc11a, 0xa07f, 0xc11a, 0x21, 0 + .dw 0xa0c0, 0xc11a, 0xa0ff, 0xc11a, 0x21, 0 + .dw 0xa140, 0xc11a, 0xa17f, 0xc11a, 0x21, 0 + .dw 0xa1c0, 0xc11a, 0xa1ff, 0xc11a, 0x21, 0 + .dw 0xa240, 0xc11a, 0xa27f, 0xc11a, 0x21, 0 + .dw 0xa2c0, 0xc11a, 0xa2ff, 0xc11a, 0x21, 0 + .dw 0xa340, 0xc11a, 0xa37f, 0xc11a, 0x21, 0 + .dw 0xa3c0, 0xc11a, 0xa3ff, 0xc11a, 0x21, 0 + .dw 0xa440, 0xc11a, 0xa47f, 0xc11a, 0x21, 0 + .dw 0xa4c0, 0xc11a, 0xa4ff, 0xc11a, 0x21, 0 + .dw 0xa540, 0xc11a, 0xa57f, 0xc11a, 0x21, 0 + .dw 0xa5c0, 0xc11a, 0xa5ff, 0xc11a, 0x21, 0 + .dw 0xa640, 0xc11a, 0xa67f, 0xc11a, 0x21, 0 + .dw 0xa6c0, 0xc11a, 0xa6ff, 0xc11a, 0x21, 0 + .dw 0xa740, 0xc11a, 0xa77f, 0xc11a, 0x21, 0 + .dw 0xa7c0, 0xc11a, 0xa7ff, 0xc11a, 0x21, 0 + .dw 0xa840, 0xc11a, 0xa87f, 0xc11a, 0x21, 0 + .dw 0xa8c0, 0xc11a, 0xa8ff, 0xc11a, 0x21, 0 + .dw 0xa940, 0xc11a, 0xa97f, 0xc11a, 0x21, 0 + .dw 0xa9c0, 0xc11a, 0xa9ff, 0xc11a, 0x21, 0 + .dw 0xaa40, 0xc11a, 0xaa7f, 0xc11a, 0x21, 0 + .dw 0xaac0, 0xc11a, 0xaaff, 0xc11a, 0x21, 0 + .dw 0xab40, 0xc11a, 0xab7f, 0xc11a, 0x21, 0 + .dw 0xabc0, 0xc11a, 0xabff, 0xc11a, 0x21, 0 + .dw 0xac40, 0xc11a, 0xac7f, 0xc11a, 0x21, 0 + .dw 0xacc0, 0xc11a, 0xacff, 0xc11a, 0x21, 0 + .dw 0xad40, 0xc11a, 0xad7f, 0xc11a, 0x21, 0 + .dw 0xadc0, 0xc11a, 0xadff, 0xc11a, 0x21, 0 + .dw 0xae40, 0xc11a, 0xae7f, 0xc11a, 0x21, 0 + .dw 0xaec0, 0xc11a, 0xaeff, 0xc11a, 0x21, 0 + .dw 0xaf40, 0xc11a, 0xaf7f, 0xc11a, 0x21, 0 + .dw 0xafc0, 0xc11a, 0xafff, 0xc11a, 0x21, 0 + .dw 0xb040, 0xc11a, 0xb07f, 0xc11a, 0x21, 0 + .dw 0xb0c0, 0xc11a, 0xb0ff, 0xc11a, 0x21, 0 + .dw 0xb140, 0xc11a, 0xb17f, 0xc11a, 0x21, 0 + .dw 0xb1c0, 0xc11a, 0xb1ff, 0xc11a, 0x21, 0 + .dw 0xb240, 0xc11a, 0xb27f, 0xc11a, 0x21, 0 + .dw 0xb2c0, 0xc11a, 0xb2ff, 0xc11a, 0x21, 0 + .dw 0xb340, 0xc11a, 0xb37f, 0xc11a, 0x21, 0 + .dw 0xb3c0, 0xc11a, 0xb3ff, 0xc11a, 0x21, 0 + .dw 0xb440, 0xc11a, 0xb47f, 0xc11a, 0x21, 0 + .dw 0xb4c0, 0xc11a, 0xb4ff, 0xc11a, 0x21, 0 + .dw 0xb540, 0xc11a, 0xb57f, 0xc11a, 0x21, 0 + .dw 0xb5c0, 0xc11a, 0xb5ff, 0xc11a, 0x21, 0 + .dw 0xb640, 0xc11a, 0xb67f, 0xc11a, 0x21, 0 + .dw 0xb6c0, 0xc11a, 0xb6ff, 0xc11a, 0x21, 0 + .dw 0xb740, 0xc11a, 0xb77f, 0xc11a, 0x21, 0 + .dw 0xb7c0, 0xc11a, 0xb7ff, 0xc11a, 0x21, 0 + .dw 0xb840, 0xc11a, 0xb87f, 0xc11a, 0x21, 0 + .dw 0xb8c0, 0xc11a, 0xb8ff, 0xc11a, 0x21, 0 + .dw 0xb940, 0xc11a, 0xb97f, 0xc11a, 0x21, 0 + .dw 0xb9c0, 0xc11a, 0xdfff, 0xc11a, 0x21, 0 + .dw 0xe040, 0xc11a, 0xe07f, 0xc11a, 0x21, 0 + .dw 0xe0c0, 0xc11a, 0xe0ff, 0xc11a, 0x21, 0 + .dw 0xe140, 0xc11a, 0xe17f, 0xc11a, 0x21, 0 + .dw 0xe1c0, 0xc11a, 0xe1ff, 0xc11a, 0x21, 0 + .dw 0xe240, 0xc11a, 0xe27f, 0xc11a, 0x21, 0 + .dw 0xe2c0, 0xc11a, 0xe2ff, 0xc11a, 0x21, 0 + .dw 0xe340, 0xc11a, 0xe37f, 0xc11a, 0x21, 0 + .dw 0xe3c0, 0xc11a, 0xe3ff, 0xc11a, 0x21, 0 + .dw 0xe440, 0xc11a, 0xe47f, 0xc11a, 0x21, 0 + .dw 0xe4c0, 0xc11a, 0xe4ff, 0xc11a, 0x21, 0 + .dw 0xe540, 0xc11a, 0xe57f, 0xc11a, 0x21, 0 + .dw 0xe5c0, 0xc11a, 0xe5ff, 0xc11a, 0x21, 0 + .dw 0xe640, 0xc11a, 0xe67f, 0xc11a, 0x21, 0 + .dw 0xe6c0, 0xc11a, 0xe6ff, 0xc11a, 0x21, 0 + .dw 0xe740, 0xc11a, 0xe77f, 0xc11a, 0x21, 0 + .dw 0xe7c0, 0xc11a, 0xe7ff, 0xc11a, 0x21, 0 + .dw 0xe840, 0xc11a, 0xe87f, 0xc11a, 0x21, 0 + .dw 0xe8c0, 0xc11a, 0xe8ff, 0xc11a, 0x21, 0 + .dw 0xe940, 0xc11a, 0xe97f, 0xc11a, 0x21, 0 + .dw 0xe9c0, 0xc11a, 0xe9ff, 0xc11a, 0x21, 0 + .dw 0xea40, 0xc11a, 0xea7f, 0xc11a, 0x21, 0 + .dw 0xeac0, 0xc11a, 0xeaff, 0xc11a, 0x21, 0 + .dw 0xeb40, 0xc11a, 0xeb7f, 0xc11a, 0x21, 0 + .dw 0xebc0, 0xc11a, 0xebff, 0xc11a, 0x21, 0 + .dw 0xec40, 0xc11a, 0xec7f, 0xc11a, 0x21, 0 + .dw 0xecc0, 0xc11a, 0xecff, 0xc11a, 0x21, 0 + .dw 0xed40, 0xc11a, 0xed7f, 0xc11a, 0x21, 0 + .dw 0xedc0, 0xc11a, 0xedff, 0xc11a, 0x21, 0 + .dw 0xee40, 0xc11a, 0xee7f, 0xc11a, 0x21, 0 + .dw 0xeec0, 0xc11a, 0xeeff, 0xc11a, 0x21, 0 + .dw 0xef40, 0xc11a, 0xef7f, 0xc11a, 0x21, 0 + .dw 0xefc0, 0xc11a, 0xefff, 0xc11a, 0x21, 0 + .dw 0xf040, 0xc11a, 0xf07f, 0xc11a, 0x21, 0 + .dw 0xf0c0, 0xc11a, 0xf0ff, 0xc11a, 0x21, 0 + .dw 0xf140, 0xc11a, 0xf17f, 0xc11a, 0x21, 0 + .dw 0xf1c0, 0xc11a, 0xf1ff, 0xc11a, 0x21, 0 + .dw 0xf240, 0xc11a, 0xf27f, 0xc11a, 0x21, 0 + .dw 0xf2c0, 0xc11a, 0xf2ff, 0xc11a, 0x21, 0 + .dw 0xf340, 0xc11a, 0xf37f, 0xc11a, 0x21, 0 + .dw 0xf3c0, 0xc11a, 0xf3ff, 0xc11a, 0x21, 0 + .dw 0xf440, 0xc11a, 0xf47f, 0xc11a, 0x21, 0 + .dw 0xf4c0, 0xc11a, 0xf4ff, 0xc11a, 0x21, 0 + .dw 0xf540, 0xc11a, 0xf57f, 0xc11a, 0x21, 0 + .dw 0xf5c0, 0xc11a, 0xf5ff, 0xc11a, 0x21, 0 + .dw 0xf640, 0xc11a, 0xf67f, 0xc11a, 0x21, 0 + .dw 0xf6c0, 0xc11a, 0xf6ff, 0xc11a, 0x21, 0 + .dw 0xf740, 0xc11a, 0xf77f, 0xc11a, 0x21, 0 + .dw 0xf7c0, 0xc11a, 0xf7ff, 0xc11a, 0x21, 0 + .dw 0xf840, 0xc11a, 0xf87f, 0xc11a, 0x21, 0 + .dw 0xf8c0, 0xc11a, 0xf8ff, 0xc11a, 0x21, 0 + .dw 0xf940, 0xc11a, 0xf97f, 0xc11a, 0x21, 0 + .dw 0xf9c0, 0xc11a, 0xffff, 0xc11b, 0x21, 0 + .dw 0x0040, 0xc11c, 0x007f, 0xc11c, 0x21, 0 + .dw 0x00c0, 0xc11c, 0x00ff, 0xc11c, 0x21, 0 + .dw 0x0140, 0xc11c, 0x017f, 0xc11c, 0x21, 0 + .dw 0x01c0, 0xc11c, 0x01ff, 0xc11c, 0x21, 0 + .dw 0x0240, 0xc11c, 0x027f, 0xc11c, 0x21, 0 + .dw 0x02c0, 0xc11c, 0x02ff, 0xc11c, 0x21, 0 + .dw 0x0340, 0xc11c, 0x037f, 0xc11c, 0x21, 0 + .dw 0x03c0, 0xc11c, 0x03ff, 0xc11c, 0x21, 0 + .dw 0x0440, 0xc11c, 0x047f, 0xc11c, 0x21, 0 + .dw 0x04c0, 0xc11c, 0x04ff, 0xc11c, 0x21, 0 + .dw 0x0540, 0xc11c, 0x057f, 0xc11c, 0x21, 0 + .dw 0x05c0, 0xc11c, 0x05ff, 0xc11c, 0x21, 0 + .dw 0x0640, 0xc11c, 0x067f, 0xc11c, 0x21, 0 + .dw 0x06c0, 0xc11c, 0x06ff, 0xc11c, 0x21, 0 + .dw 0x0740, 0xc11c, 0x077f, 0xc11c, 0x21, 0 + .dw 0x07c0, 0xc11c, 0x07ff, 0xc11c, 0x21, 0 + .dw 0x0840, 0xc11c, 0x087f, 0xc11c, 0x21, 0 + .dw 0x08c0, 0xc11c, 0x08ff, 0xc11c, 0x21, 0 + .dw 0x0940, 0xc11c, 0x097f, 0xc11c, 0x21, 0 + .dw 0x09c0, 0xc11c, 0x09ff, 0xc11c, 0x21, 0 + .dw 0x0a40, 0xc11c, 0x0a7f, 0xc11c, 0x21, 0 + .dw 0x0ac0, 0xc11c, 0x0aff, 0xc11c, 0x21, 0 + .dw 0x0b40, 0xc11c, 0x0b7f, 0xc11c, 0x21, 0 + .dw 0x0bc0, 0xc11c, 0x0bff, 0xc11c, 0x21, 0 + .dw 0x0c40, 0xc11c, 0x0c7f, 0xc11c, 0x21, 0 + .dw 0x0cc0, 0xc11c, 0x0cff, 0xc11c, 0x21, 0 + .dw 0x0d40, 0xc11c, 0x0d7f, 0xc11c, 0x21, 0 + .dw 0x0dc0, 0xc11c, 0x0dff, 0xc11c, 0x21, 0 + .dw 0x0e40, 0xc11c, 0x0e7f, 0xc11c, 0x21, 0 + .dw 0x0ec0, 0xc11c, 0x0eff, 0xc11c, 0x21, 0 + .dw 0x0f40, 0xc11c, 0x0f7f, 0xc11c, 0x21, 0 + .dw 0x0fc0, 0xc11c, 0x0fff, 0xc11c, 0x21, 0 + .dw 0x1040, 0xc11c, 0x107f, 0xc11c, 0x21, 0 + .dw 0x10c0, 0xc11c, 0x10ff, 0xc11c, 0x21, 0 + .dw 0x1140, 0xc11c, 0x117f, 0xc11c, 0x21, 0 + .dw 0x11c0, 0xc11c, 0x11ff, 0xc11c, 0x21, 0 + .dw 0x1240, 0xc11c, 0x127f, 0xc11c, 0x21, 0 + .dw 0x12c0, 0xc11c, 0x12ff, 0xc11c, 0x21, 0 + .dw 0x1340, 0xc11c, 0x137f, 0xc11c, 0x21, 0 + .dw 0x13c0, 0xc11c, 0x13ff, 0xc11c, 0x21, 0 + .dw 0x1440, 0xc11c, 0x147f, 0xc11c, 0x21, 0 + .dw 0x14c0, 0xc11c, 0x14ff, 0xc11c, 0x21, 0 + .dw 0x1540, 0xc11c, 0x157f, 0xc11c, 0x21, 0 + .dw 0x15c0, 0xc11c, 0x15ff, 0xc11c, 0x21, 0 + .dw 0x1640, 0xc11c, 0x167f, 0xc11c, 0x21, 0 + .dw 0x16c0, 0xc11c, 0x16ff, 0xc11c, 0x21, 0 + .dw 0x1740, 0xc11c, 0x177f, 0xc11c, 0x21, 0 + .dw 0x17c0, 0xc11c, 0x17ff, 0xc11c, 0x21, 0 + .dw 0x1840, 0xc11c, 0x187f, 0xc11c, 0x21, 0 + .dw 0x18c0, 0xc11c, 0x18ff, 0xc11c, 0x21, 0 + .dw 0x1940, 0xc11c, 0x197f, 0xc11c, 0x21, 0 + .dw 0x19c0, 0xc11c, 0x1fff, 0xc11c, 0x21, 0 + .dw 0x2040, 0xc11c, 0x207f, 0xc11c, 0x21, 0 + .dw 0x20c0, 0xc11c, 0x20ff, 0xc11c, 0x21, 0 + .dw 0x2140, 0xc11c, 0x217f, 0xc11c, 0x21, 0 + .dw 0x21c0, 0xc11c, 0x21ff, 0xc11c, 0x21, 0 + .dw 0x2240, 0xc11c, 0x227f, 0xc11c, 0x21, 0 + .dw 0x22c0, 0xc11c, 0x22ff, 0xc11c, 0x21, 0 + .dw 0x2340, 0xc11c, 0x237f, 0xc11c, 0x21, 0 + .dw 0x23c0, 0xc11c, 0x23ff, 0xc11c, 0x21, 0 + .dw 0x2440, 0xc11c, 0x247f, 0xc11c, 0x21, 0 + .dw 0x24c0, 0xc11c, 0x24ff, 0xc11c, 0x21, 0 + .dw 0x2540, 0xc11c, 0x257f, 0xc11c, 0x21, 0 + .dw 0x25c0, 0xc11c, 0x25ff, 0xc11c, 0x21, 0 + .dw 0x2640, 0xc11c, 0x267f, 0xc11c, 0x21, 0 + .dw 0x26c0, 0xc11c, 0x26ff, 0xc11c, 0x21, 0 + .dw 0x2740, 0xc11c, 0x277f, 0xc11c, 0x21, 0 + .dw 0x27c0, 0xc11c, 0x27ff, 0xc11c, 0x21, 0 + .dw 0x2840, 0xc11c, 0x287f, 0xc11c, 0x21, 0 + .dw 0x28c0, 0xc11c, 0x28ff, 0xc11c, 0x21, 0 + .dw 0x2940, 0xc11c, 0x297f, 0xc11c, 0x21, 0 + .dw 0x29c0, 0xc11c, 0x29ff, 0xc11c, 0x21, 0 + .dw 0x2a40, 0xc11c, 0x2a7f, 0xc11c, 0x21, 0 + .dw 0x2ac0, 0xc11c, 0x2aff, 0xc11c, 0x21, 0 + .dw 0x2b40, 0xc11c, 0x2b7f, 0xc11c, 0x21, 0 + .dw 0x2bc0, 0xc11c, 0x2bff, 0xc11c, 0x21, 0 + .dw 0x2c40, 0xc11c, 0x2c7f, 0xc11c, 0x21, 0 + .dw 0x2cc0, 0xc11c, 0x2cff, 0xc11c, 0x21, 0 + .dw 0x2d40, 0xc11c, 0x2d7f, 0xc11c, 0x21, 0 + .dw 0x2dc0, 0xc11c, 0x2dff, 0xc11c, 0x21, 0 + .dw 0x2e40, 0xc11c, 0x2e7f, 0xc11c, 0x21, 0 + .dw 0x2ec0, 0xc11c, 0x2eff, 0xc11c, 0x21, 0 + .dw 0x2f40, 0xc11c, 0x2f7f, 0xc11c, 0x21, 0 + .dw 0x2fc0, 0xc11c, 0x2fff, 0xc11c, 0x21, 0 + .dw 0x3040, 0xc11c, 0x307f, 0xc11c, 0x21, 0 + .dw 0x30c0, 0xc11c, 0x30ff, 0xc11c, 0x21, 0 + .dw 0x3140, 0xc11c, 0x317f, 0xc11c, 0x21, 0 + .dw 0x31c0, 0xc11c, 0x31ff, 0xc11c, 0x21, 0 + .dw 0x3240, 0xc11c, 0x327f, 0xc11c, 0x21, 0 + .dw 0x32c0, 0xc11c, 0x32ff, 0xc11c, 0x21, 0 + .dw 0x3340, 0xc11c, 0x337f, 0xc11c, 0x21, 0 + .dw 0x33c0, 0xc11c, 0x33ff, 0xc11c, 0x21, 0 + .dw 0x3440, 0xc11c, 0x347f, 0xc11c, 0x21, 0 + .dw 0x34c0, 0xc11c, 0x34ff, 0xc11c, 0x21, 0 + .dw 0x3540, 0xc11c, 0x357f, 0xc11c, 0x21, 0 + .dw 0x35c0, 0xc11c, 0x35ff, 0xc11c, 0x21, 0 + .dw 0x3640, 0xc11c, 0x367f, 0xc11c, 0x21, 0 + .dw 0x36c0, 0xc11c, 0x36ff, 0xc11c, 0x21, 0 + .dw 0x3740, 0xc11c, 0x377f, 0xc11c, 0x21, 0 + .dw 0x37c0, 0xc11c, 0x37ff, 0xc11c, 0x21, 0 + .dw 0x3840, 0xc11c, 0x387f, 0xc11c, 0x21, 0 + .dw 0x38c0, 0xc11c, 0x38ff, 0xc11c, 0x21, 0 + .dw 0x3940, 0xc11c, 0x397f, 0xc11c, 0x21, 0 + .dw 0x39c0, 0xc11c, 0x3fff, 0xc11c, 0x21, 0 + .dw 0x4040, 0xc11c, 0x407f, 0xc11c, 0x21, 0 + .dw 0x40c0, 0xc11c, 0x40ff, 0xc11c, 0x21, 0 + .dw 0x4140, 0xc11c, 0x417f, 0xc11c, 0x21, 0 + .dw 0x41c0, 0xc11c, 0x41ff, 0xc11c, 0x21, 0 + .dw 0x4240, 0xc11c, 0x427f, 0xc11c, 0x21, 0 + .dw 0x42c0, 0xc11c, 0x42ff, 0xc11c, 0x21, 0 + .dw 0x4340, 0xc11c, 0x437f, 0xc11c, 0x21, 0 + .dw 0x43c0, 0xc11c, 0x43ff, 0xc11c, 0x21, 0 + .dw 0x4440, 0xc11c, 0x447f, 0xc11c, 0x21, 0 + .dw 0x44c0, 0xc11c, 0x44ff, 0xc11c, 0x21, 0 + .dw 0x4540, 0xc11c, 0x457f, 0xc11c, 0x21, 0 + .dw 0x45c0, 0xc11c, 0x45ff, 0xc11c, 0x21, 0 + .dw 0x4640, 0xc11c, 0x467f, 0xc11c, 0x21, 0 + .dw 0x46c0, 0xc11c, 0x46ff, 0xc11c, 0x21, 0 + .dw 0x4740, 0xc11c, 0x477f, 0xc11c, 0x21, 0 + .dw 0x47c0, 0xc11c, 0x47ff, 0xc11c, 0x21, 0 + .dw 0x4840, 0xc11c, 0x487f, 0xc11c, 0x21, 0 + .dw 0x48c0, 0xc11c, 0x48ff, 0xc11c, 0x21, 0 + .dw 0x4940, 0xc11c, 0x497f, 0xc11c, 0x21, 0 + .dw 0x49c0, 0xc11c, 0x49ff, 0xc11c, 0x21, 0 + .dw 0x4a40, 0xc11c, 0x4a7f, 0xc11c, 0x21, 0 + .dw 0x4ac0, 0xc11c, 0x4aff, 0xc11c, 0x21, 0 + .dw 0x4b40, 0xc11c, 0x4b7f, 0xc11c, 0x21, 0 + .dw 0x4bc0, 0xc11c, 0x4bff, 0xc11c, 0x21, 0 + .dw 0x4c40, 0xc11c, 0x4c7f, 0xc11c, 0x21, 0 + .dw 0x4cc0, 0xc11c, 0x4cff, 0xc11c, 0x21, 0 + .dw 0x4d40, 0xc11c, 0x4d7f, 0xc11c, 0x21, 0 + .dw 0x4dc0, 0xc11c, 0x4dff, 0xc11c, 0x21, 0 + .dw 0x4e40, 0xc11c, 0x4e7f, 0xc11c, 0x21, 0 + .dw 0x4ec0, 0xc11c, 0x4eff, 0xc11c, 0x21, 0 + .dw 0x4f40, 0xc11c, 0x4f7f, 0xc11c, 0x21, 0 + .dw 0x4fc0, 0xc11c, 0x4fff, 0xc11c, 0x21, 0 + .dw 0x5040, 0xc11c, 0x507f, 0xc11c, 0x21, 0 + .dw 0x50c0, 0xc11c, 0x50ff, 0xc11c, 0x21, 0 + .dw 0x5140, 0xc11c, 0x517f, 0xc11c, 0x21, 0 + .dw 0x51c0, 0xc11c, 0x51ff, 0xc11c, 0x21, 0 + .dw 0x5240, 0xc11c, 0x527f, 0xc11c, 0x21, 0 + .dw 0x52c0, 0xc11c, 0x52ff, 0xc11c, 0x21, 0 + .dw 0x5340, 0xc11c, 0x537f, 0xc11c, 0x21, 0 + .dw 0x53c0, 0xc11c, 0x53ff, 0xc11c, 0x21, 0 + .dw 0x5440, 0xc11c, 0x547f, 0xc11c, 0x21, 0 + .dw 0x54c0, 0xc11c, 0x54ff, 0xc11c, 0x21, 0 + .dw 0x5540, 0xc11c, 0x557f, 0xc11c, 0x21, 0 + .dw 0x55c0, 0xc11c, 0x55ff, 0xc11c, 0x21, 0 + .dw 0x5640, 0xc11c, 0x567f, 0xc11c, 0x21, 0 + .dw 0x56c0, 0xc11c, 0x56ff, 0xc11c, 0x21, 0 + .dw 0x5740, 0xc11c, 0x577f, 0xc11c, 0x21, 0 + .dw 0x57c0, 0xc11c, 0x57ff, 0xc11c, 0x21, 0 + .dw 0x5840, 0xc11c, 0x587f, 0xc11c, 0x21, 0 + .dw 0x58c0, 0xc11c, 0x58ff, 0xc11c, 0x21, 0 + .dw 0x5940, 0xc11c, 0x597f, 0xc11c, 0x21, 0 + .dw 0x59c0, 0xc11c, 0x5fff, 0xc11c, 0x21, 0 + .dw 0x6040, 0xc11c, 0x607f, 0xc11c, 0x21, 0 + .dw 0x60c0, 0xc11c, 0x60ff, 0xc11c, 0x21, 0 + .dw 0x6140, 0xc11c, 0x617f, 0xc11c, 0x21, 0 + .dw 0x61c0, 0xc11c, 0x61ff, 0xc11c, 0x21, 0 + .dw 0x6240, 0xc11c, 0x627f, 0xc11c, 0x21, 0 + .dw 0x62c0, 0xc11c, 0x62ff, 0xc11c, 0x21, 0 + .dw 0x6340, 0xc11c, 0x637f, 0xc11c, 0x21, 0 + .dw 0x63c0, 0xc11c, 0x63ff, 0xc11c, 0x21, 0 + .dw 0x6440, 0xc11c, 0x647f, 0xc11c, 0x21, 0 + .dw 0x64c0, 0xc11c, 0x64ff, 0xc11c, 0x21, 0 + .dw 0x6540, 0xc11c, 0x657f, 0xc11c, 0x21, 0 + .dw 0x65c0, 0xc11c, 0x65ff, 0xc11c, 0x21, 0 + .dw 0x6640, 0xc11c, 0x667f, 0xc11c, 0x21, 0 + .dw 0x66c0, 0xc11c, 0x66ff, 0xc11c, 0x21, 0 + .dw 0x6740, 0xc11c, 0x677f, 0xc11c, 0x21, 0 + .dw 0x67c0, 0xc11c, 0x67ff, 0xc11c, 0x21, 0 + .dw 0x6840, 0xc11c, 0x687f, 0xc11c, 0x21, 0 + .dw 0x68c0, 0xc11c, 0x68ff, 0xc11c, 0x21, 0 + .dw 0x6940, 0xc11c, 0x697f, 0xc11c, 0x21, 0 + .dw 0x69c0, 0xc11c, 0x69ff, 0xc11c, 0x21, 0 + .dw 0x6a40, 0xc11c, 0x6a7f, 0xc11c, 0x21, 0 + .dw 0x6ac0, 0xc11c, 0x6aff, 0xc11c, 0x21, 0 + .dw 0x6b40, 0xc11c, 0x6b7f, 0xc11c, 0x21, 0 + .dw 0x6bc0, 0xc11c, 0x6bff, 0xc11c, 0x21, 0 + .dw 0x6c40, 0xc11c, 0x6c7f, 0xc11c, 0x21, 0 + .dw 0x6cc0, 0xc11c, 0x6cff, 0xc11c, 0x21, 0 + .dw 0x6d40, 0xc11c, 0x6d7f, 0xc11c, 0x21, 0 + .dw 0x6dc0, 0xc11c, 0x6dff, 0xc11c, 0x21, 0 + .dw 0x6e40, 0xc11c, 0x6e7f, 0xc11c, 0x21, 0 + .dw 0x6ec0, 0xc11c, 0x6eff, 0xc11c, 0x21, 0 + .dw 0x6f40, 0xc11c, 0x6f7f, 0xc11c, 0x21, 0 + .dw 0x6fc0, 0xc11c, 0x6fff, 0xc11c, 0x21, 0 + .dw 0x7040, 0xc11c, 0x707f, 0xc11c, 0x21, 0 + .dw 0x70c0, 0xc11c, 0x70ff, 0xc11c, 0x21, 0 + .dw 0x7140, 0xc11c, 0x717f, 0xc11c, 0x21, 0 + .dw 0x71c0, 0xc11c, 0x71ff, 0xc11c, 0x21, 0 + .dw 0x7240, 0xc11c, 0x727f, 0xc11c, 0x21, 0 + .dw 0x72c0, 0xc11c, 0x72ff, 0xc11c, 0x21, 0 + .dw 0x7340, 0xc11c, 0x737f, 0xc11c, 0x21, 0 + .dw 0x73c0, 0xc11c, 0x73ff, 0xc11c, 0x21, 0 + .dw 0x7440, 0xc11c, 0x747f, 0xc11c, 0x21, 0 + .dw 0x74c0, 0xc11c, 0x74ff, 0xc11c, 0x21, 0 + .dw 0x7540, 0xc11c, 0x757f, 0xc11c, 0x21, 0 + .dw 0x75c0, 0xc11c, 0x75ff, 0xc11c, 0x21, 0 + .dw 0x7640, 0xc11c, 0x767f, 0xc11c, 0x21, 0 + .dw 0x76c0, 0xc11c, 0x76ff, 0xc11c, 0x21, 0 + .dw 0x7740, 0xc11c, 0x777f, 0xc11c, 0x21, 0 + .dw 0x77c0, 0xc11c, 0x77ff, 0xc11c, 0x21, 0 + .dw 0x7840, 0xc11c, 0x787f, 0xc11c, 0x21, 0 + .dw 0x78c0, 0xc11c, 0x78ff, 0xc11c, 0x21, 0 + .dw 0x7940, 0xc11c, 0x797f, 0xc11c, 0x21, 0 + .dw 0x79c0, 0xc11c, 0x7fff, 0xc11c, 0x21, 0 + .dw 0x8040, 0xc11c, 0x807f, 0xc11c, 0x21, 0 + .dw 0x80c0, 0xc11c, 0x80ff, 0xc11c, 0x21, 0 + .dw 0x8140, 0xc11c, 0x817f, 0xc11c, 0x21, 0 + .dw 0x81c0, 0xc11c, 0x81ff, 0xc11c, 0x21, 0 + .dw 0x8240, 0xc11c, 0x827f, 0xc11c, 0x21, 0 + .dw 0x82c0, 0xc11c, 0x82ff, 0xc11c, 0x21, 0 + .dw 0x8340, 0xc11c, 0x837f, 0xc11c, 0x21, 0 + .dw 0x83c0, 0xc11c, 0x83ff, 0xc11c, 0x21, 0 + .dw 0x8440, 0xc11c, 0x847f, 0xc11c, 0x21, 0 + .dw 0x84c0, 0xc11c, 0x84ff, 0xc11c, 0x21, 0 + .dw 0x8540, 0xc11c, 0x857f, 0xc11c, 0x21, 0 + .dw 0x85c0, 0xc11c, 0x85ff, 0xc11c, 0x21, 0 + .dw 0x8640, 0xc11c, 0x867f, 0xc11c, 0x21, 0 + .dw 0x86c0, 0xc11c, 0x86ff, 0xc11c, 0x21, 0 + .dw 0x8740, 0xc11c, 0x877f, 0xc11c, 0x21, 0 + .dw 0x87c0, 0xc11c, 0x87ff, 0xc11c, 0x21, 0 + .dw 0x8840, 0xc11c, 0x887f, 0xc11c, 0x21, 0 + .dw 0x88c0, 0xc11c, 0x88ff, 0xc11c, 0x21, 0 + .dw 0x8940, 0xc11c, 0x897f, 0xc11c, 0x21, 0 + .dw 0x89c0, 0xc11c, 0x89ff, 0xc11c, 0x21, 0 + .dw 0x8a40, 0xc11c, 0x8a7f, 0xc11c, 0x21, 0 + .dw 0x8ac0, 0xc11c, 0x8aff, 0xc11c, 0x21, 0 + .dw 0x8b40, 0xc11c, 0x8b7f, 0xc11c, 0x21, 0 + .dw 0x8bc0, 0xc11c, 0x8bff, 0xc11c, 0x21, 0 + .dw 0x8c40, 0xc11c, 0x8c7f, 0xc11c, 0x21, 0 + .dw 0x8cc0, 0xc11c, 0x8cff, 0xc11c, 0x21, 0 + .dw 0x8d40, 0xc11c, 0x8d7f, 0xc11c, 0x21, 0 + .dw 0x8dc0, 0xc11c, 0x8dff, 0xc11c, 0x21, 0 + .dw 0x8e40, 0xc11c, 0x8e7f, 0xc11c, 0x21, 0 + .dw 0x8ec0, 0xc11c, 0x8eff, 0xc11c, 0x21, 0 + .dw 0x8f40, 0xc11c, 0x8f7f, 0xc11c, 0x21, 0 + .dw 0x8fc0, 0xc11c, 0x8fff, 0xc11c, 0x21, 0 + .dw 0x9040, 0xc11c, 0x907f, 0xc11c, 0x21, 0 + .dw 0x90c0, 0xc11c, 0x90ff, 0xc11c, 0x21, 0 + .dw 0x9140, 0xc11c, 0x917f, 0xc11c, 0x21, 0 + .dw 0x91c0, 0xc11c, 0x91ff, 0xc11c, 0x21, 0 + .dw 0x9240, 0xc11c, 0x927f, 0xc11c, 0x21, 0 + .dw 0x92c0, 0xc11c, 0x92ff, 0xc11c, 0x21, 0 + .dw 0x9340, 0xc11c, 0x937f, 0xc11c, 0x21, 0 + .dw 0x93c0, 0xc11c, 0x93ff, 0xc11c, 0x21, 0 + .dw 0x9440, 0xc11c, 0x947f, 0xc11c, 0x21, 0 + .dw 0x94c0, 0xc11c, 0x94ff, 0xc11c, 0x21, 0 + .dw 0x9540, 0xc11c, 0x957f, 0xc11c, 0x21, 0 + .dw 0x95c0, 0xc11c, 0x95ff, 0xc11c, 0x21, 0 + .dw 0x9640, 0xc11c, 0x967f, 0xc11c, 0x21, 0 + .dw 0x96c0, 0xc11c, 0x96ff, 0xc11c, 0x21, 0 + .dw 0x9740, 0xc11c, 0x977f, 0xc11c, 0x21, 0 + .dw 0x97c0, 0xc11c, 0x97ff, 0xc11c, 0x21, 0 + .dw 0x9840, 0xc11c, 0x987f, 0xc11c, 0x21, 0 + .dw 0x98c0, 0xc11c, 0x98ff, 0xc11c, 0x21, 0 + .dw 0x9940, 0xc11c, 0x997f, 0xc11c, 0x21, 0 + .dw 0x99c0, 0xc11c, 0x9fff, 0xc11c, 0x21, 0 + .dw 0xa040, 0xc11c, 0xa07f, 0xc11c, 0x21, 0 + .dw 0xa0c0, 0xc11c, 0xa0ff, 0xc11c, 0x21, 0 + .dw 0xa140, 0xc11c, 0xa17f, 0xc11c, 0x21, 0 + .dw 0xa1c0, 0xc11c, 0xa1ff, 0xc11c, 0x21, 0 + .dw 0xa240, 0xc11c, 0xa27f, 0xc11c, 0x21, 0 + .dw 0xa2c0, 0xc11c, 0xa2ff, 0xc11c, 0x21, 0 + .dw 0xa340, 0xc11c, 0xa37f, 0xc11c, 0x21, 0 + .dw 0xa3c0, 0xc11c, 0xa3ff, 0xc11c, 0x21, 0 + .dw 0xa440, 0xc11c, 0xa47f, 0xc11c, 0x21, 0 + .dw 0xa4c0, 0xc11c, 0xa4ff, 0xc11c, 0x21, 0 + .dw 0xa540, 0xc11c, 0xa57f, 0xc11c, 0x21, 0 + .dw 0xa5c0, 0xc11c, 0xa5ff, 0xc11c, 0x21, 0 + .dw 0xa640, 0xc11c, 0xa67f, 0xc11c, 0x21, 0 + .dw 0xa6c0, 0xc11c, 0xa6ff, 0xc11c, 0x21, 0 + .dw 0xa740, 0xc11c, 0xa77f, 0xc11c, 0x21, 0 + .dw 0xa7c0, 0xc11c, 0xa7ff, 0xc11c, 0x21, 0 + .dw 0xa840, 0xc11c, 0xa87f, 0xc11c, 0x21, 0 + .dw 0xa8c0, 0xc11c, 0xa8ff, 0xc11c, 0x21, 0 + .dw 0xa940, 0xc11c, 0xa97f, 0xc11c, 0x21, 0 + .dw 0xa9c0, 0xc11c, 0xa9ff, 0xc11c, 0x21, 0 + .dw 0xaa40, 0xc11c, 0xaa7f, 0xc11c, 0x21, 0 + .dw 0xaac0, 0xc11c, 0xaaff, 0xc11c, 0x21, 0 + .dw 0xab40, 0xc11c, 0xab7f, 0xc11c, 0x21, 0 + .dw 0xabc0, 0xc11c, 0xabff, 0xc11c, 0x21, 0 + .dw 0xac40, 0xc11c, 0xac7f, 0xc11c, 0x21, 0 + .dw 0xacc0, 0xc11c, 0xacff, 0xc11c, 0x21, 0 + .dw 0xad40, 0xc11c, 0xad7f, 0xc11c, 0x21, 0 + .dw 0xadc0, 0xc11c, 0xadff, 0xc11c, 0x21, 0 + .dw 0xae40, 0xc11c, 0xae7f, 0xc11c, 0x21, 0 + .dw 0xaec0, 0xc11c, 0xaeff, 0xc11c, 0x21, 0 + .dw 0xaf40, 0xc11c, 0xaf7f, 0xc11c, 0x21, 0 + .dw 0xafc0, 0xc11c, 0xafff, 0xc11c, 0x21, 0 + .dw 0xb040, 0xc11c, 0xb07f, 0xc11c, 0x21, 0 + .dw 0xb0c0, 0xc11c, 0xb0ff, 0xc11c, 0x21, 0 + .dw 0xb140, 0xc11c, 0xb17f, 0xc11c, 0x21, 0 + .dw 0xb1c0, 0xc11c, 0xb1ff, 0xc11c, 0x21, 0 + .dw 0xb240, 0xc11c, 0xb27f, 0xc11c, 0x21, 0 + .dw 0xb2c0, 0xc11c, 0xb2ff, 0xc11c, 0x21, 0 + .dw 0xb340, 0xc11c, 0xb37f, 0xc11c, 0x21, 0 + .dw 0xb3c0, 0xc11c, 0xb3ff, 0xc11c, 0x21, 0 + .dw 0xb440, 0xc11c, 0xb47f, 0xc11c, 0x21, 0 + .dw 0xb4c0, 0xc11c, 0xb4ff, 0xc11c, 0x21, 0 + .dw 0xb540, 0xc11c, 0xb57f, 0xc11c, 0x21, 0 + .dw 0xb5c0, 0xc11c, 0xb5ff, 0xc11c, 0x21, 0 + .dw 0xb640, 0xc11c, 0xb67f, 0xc11c, 0x21, 0 + .dw 0xb6c0, 0xc11c, 0xb6ff, 0xc11c, 0x21, 0 + .dw 0xb740, 0xc11c, 0xb77f, 0xc11c, 0x21, 0 + .dw 0xb7c0, 0xc11c, 0xb7ff, 0xc11c, 0x21, 0 + .dw 0xb840, 0xc11c, 0xb87f, 0xc11c, 0x21, 0 + .dw 0xb8c0, 0xc11c, 0xb8ff, 0xc11c, 0x21, 0 + .dw 0xb940, 0xc11c, 0xb97f, 0xc11c, 0x21, 0 + .dw 0xb9c0, 0xc11c, 0xbfff, 0xc11c, 0x21, 0 + .dw 0xc040, 0xc11c, 0xc07f, 0xc11c, 0x21, 0 + .dw 0xc0c0, 0xc11c, 0xc0ff, 0xc11c, 0x21, 0 + .dw 0xc140, 0xc11c, 0xc17f, 0xc11c, 0x21, 0 + .dw 0xc1c0, 0xc11c, 0xc1ff, 0xc11c, 0x21, 0 + .dw 0xc240, 0xc11c, 0xc27f, 0xc11c, 0x21, 0 + .dw 0xc2c0, 0xc11c, 0xc2ff, 0xc11c, 0x21, 0 + .dw 0xc340, 0xc11c, 0xc37f, 0xc11c, 0x21, 0 + .dw 0xc3c0, 0xc11c, 0xc3ff, 0xc11c, 0x21, 0 + .dw 0xc440, 0xc11c, 0xc47f, 0xc11c, 0x21, 0 + .dw 0xc4c0, 0xc11c, 0xc4ff, 0xc11c, 0x21, 0 + .dw 0xc540, 0xc11c, 0xc57f, 0xc11c, 0x21, 0 + .dw 0xc5c0, 0xc11c, 0xc5ff, 0xc11c, 0x21, 0 + .dw 0xc640, 0xc11c, 0xc67f, 0xc11c, 0x21, 0 + .dw 0xc6c0, 0xc11c, 0xc6ff, 0xc11c, 0x21, 0 + .dw 0xc740, 0xc11c, 0xc77f, 0xc11c, 0x21, 0 + .dw 0xc7c0, 0xc11c, 0xc7ff, 0xc11c, 0x21, 0 + .dw 0xc840, 0xc11c, 0xc87f, 0xc11c, 0x21, 0 + .dw 0xc8c0, 0xc11c, 0xc8ff, 0xc11c, 0x21, 0 + .dw 0xc940, 0xc11c, 0xc97f, 0xc11c, 0x21, 0 + .dw 0xc9c0, 0xc11c, 0xc9ff, 0xc11c, 0x21, 0 + .dw 0xca40, 0xc11c, 0xca7f, 0xc11c, 0x21, 0 + .dw 0xcac0, 0xc11c, 0xcaff, 0xc11c, 0x21, 0 + .dw 0xcb40, 0xc11c, 0xcb7f, 0xc11c, 0x21, 0 + .dw 0xcbc0, 0xc11c, 0xcbff, 0xc11c, 0x21, 0 + .dw 0xcc40, 0xc11c, 0xcc7f, 0xc11c, 0x21, 0 + .dw 0xccc0, 0xc11c, 0xccff, 0xc11c, 0x21, 0 + .dw 0xcd40, 0xc11c, 0xcd7f, 0xc11c, 0x21, 0 + .dw 0xcdc0, 0xc11c, 0xcdff, 0xc11c, 0x21, 0 + .dw 0xce40, 0xc11c, 0xce7f, 0xc11c, 0x21, 0 + .dw 0xcec0, 0xc11c, 0xceff, 0xc11c, 0x21, 0 + .dw 0xcf40, 0xc11c, 0xcf7f, 0xc11c, 0x21, 0 + .dw 0xcfc0, 0xc11c, 0xcfff, 0xc11c, 0x21, 0 + .dw 0xd040, 0xc11c, 0xd07f, 0xc11c, 0x21, 0 + .dw 0xd0c0, 0xc11c, 0xd0ff, 0xc11c, 0x21, 0 + .dw 0xd140, 0xc11c, 0xd17f, 0xc11c, 0x21, 0 + .dw 0xd1c0, 0xc11c, 0xd1ff, 0xc11c, 0x21, 0 + .dw 0xd240, 0xc11c, 0xd27f, 0xc11c, 0x21, 0 + .dw 0xd2c0, 0xc11c, 0xd2ff, 0xc11c, 0x21, 0 + .dw 0xd340, 0xc11c, 0xd37f, 0xc11c, 0x21, 0 + .dw 0xd3c0, 0xc11c, 0xd3ff, 0xc11c, 0x21, 0 + .dw 0xd440, 0xc11c, 0xd47f, 0xc11c, 0x21, 0 + .dw 0xd4c0, 0xc11c, 0xd4ff, 0xc11c, 0x21, 0 + .dw 0xd540, 0xc11c, 0xd57f, 0xc11c, 0x21, 0 + .dw 0xd5c0, 0xc11c, 0xd5ff, 0xc11c, 0x21, 0 + .dw 0xd640, 0xc11c, 0xd67f, 0xc11c, 0x21, 0 + .dw 0xd6c0, 0xc11c, 0xd6ff, 0xc11c, 0x21, 0 + .dw 0xd740, 0xc11c, 0xd77f, 0xc11c, 0x21, 0 + .dw 0xd7c0, 0xc11c, 0xd7ff, 0xc11c, 0x21, 0 + .dw 0xd840, 0xc11c, 0xd87f, 0xc11c, 0x21, 0 + .dw 0xd8c0, 0xc11c, 0xd8ff, 0xc11c, 0x21, 0 + .dw 0xd940, 0xc11c, 0xd97f, 0xc11c, 0x21, 0 + .dw 0xd9c0, 0xc11c, 0xdfff, 0xc11c, 0x21, 0 + .dw 0xe040, 0xc11c, 0xe07f, 0xc11c, 0x21, 0 + .dw 0xe0c0, 0xc11c, 0xe0ff, 0xc11c, 0x21, 0 + .dw 0xe140, 0xc11c, 0xe17f, 0xc11c, 0x21, 0 + .dw 0xe1c0, 0xc11c, 0xe1ff, 0xc11c, 0x21, 0 + .dw 0xe240, 0xc11c, 0xe27f, 0xc11c, 0x21, 0 + .dw 0xe2c0, 0xc11c, 0xe2ff, 0xc11c, 0x21, 0 + .dw 0xe340, 0xc11c, 0xe37f, 0xc11c, 0x21, 0 + .dw 0xe3c0, 0xc11c, 0xe3ff, 0xc11c, 0x21, 0 + .dw 0xe440, 0xc11c, 0xe47f, 0xc11c, 0x21, 0 + .dw 0xe4c0, 0xc11c, 0xe4ff, 0xc11c, 0x21, 0 + .dw 0xe540, 0xc11c, 0xe57f, 0xc11c, 0x21, 0 + .dw 0xe5c0, 0xc11c, 0xe5ff, 0xc11c, 0x21, 0 + .dw 0xe640, 0xc11c, 0xe67f, 0xc11c, 0x21, 0 + .dw 0xe6c0, 0xc11c, 0xe6ff, 0xc11c, 0x21, 0 + .dw 0xe740, 0xc11c, 0xe77f, 0xc11c, 0x21, 0 + .dw 0xe7c0, 0xc11c, 0xe7ff, 0xc11c, 0x21, 0 + .dw 0xe840, 0xc11c, 0xe87f, 0xc11c, 0x21, 0 + .dw 0xe8c0, 0xc11c, 0xe8ff, 0xc11c, 0x21, 0 + .dw 0xe940, 0xc11c, 0xe97f, 0xc11c, 0x21, 0 + .dw 0xe9c0, 0xc11c, 0xe9ff, 0xc11c, 0x21, 0 + .dw 0xea40, 0xc11c, 0xea7f, 0xc11c, 0x21, 0 + .dw 0xeac0, 0xc11c, 0xeaff, 0xc11c, 0x21, 0 + .dw 0xeb40, 0xc11c, 0xeb7f, 0xc11c, 0x21, 0 + .dw 0xebc0, 0xc11c, 0xebff, 0xc11c, 0x21, 0 + .dw 0xec40, 0xc11c, 0xec7f, 0xc11c, 0x21, 0 + .dw 0xecc0, 0xc11c, 0xecff, 0xc11c, 0x21, 0 + .dw 0xed40, 0xc11c, 0xed7f, 0xc11c, 0x21, 0 + .dw 0xedc0, 0xc11c, 0xedff, 0xc11c, 0x21, 0 + .dw 0xee40, 0xc11c, 0xee7f, 0xc11c, 0x21, 0 + .dw 0xeec0, 0xc11c, 0xeeff, 0xc11c, 0x21, 0 + .dw 0xef40, 0xc11c, 0xef7f, 0xc11c, 0x21, 0 + .dw 0xefc0, 0xc11c, 0xefff, 0xc11c, 0x21, 0 + .dw 0xf040, 0xc11c, 0xf07f, 0xc11c, 0x21, 0 + .dw 0xf0c0, 0xc11c, 0xf0ff, 0xc11c, 0x21, 0 + .dw 0xf140, 0xc11c, 0xf17f, 0xc11c, 0x21, 0 + .dw 0xf1c0, 0xc11c, 0xf1ff, 0xc11c, 0x21, 0 + .dw 0xf240, 0xc11c, 0xf27f, 0xc11c, 0x21, 0 + .dw 0xf2c0, 0xc11c, 0xf2ff, 0xc11c, 0x21, 0 + .dw 0xf340, 0xc11c, 0xf37f, 0xc11c, 0x21, 0 + .dw 0xf3c0, 0xc11c, 0xf3ff, 0xc11c, 0x21, 0 + .dw 0xf440, 0xc11c, 0xf47f, 0xc11c, 0x21, 0 + .dw 0xf4c0, 0xc11c, 0xf4ff, 0xc11c, 0x21, 0 + .dw 0xf540, 0xc11c, 0xf57f, 0xc11c, 0x21, 0 + .dw 0xf5c0, 0xc11c, 0xf5ff, 0xc11c, 0x21, 0 + .dw 0xf640, 0xc11c, 0xf67f, 0xc11c, 0x21, 0 + .dw 0xf6c0, 0xc11c, 0xf6ff, 0xc11c, 0x21, 0 + .dw 0xf740, 0xc11c, 0xf77f, 0xc11c, 0x21, 0 + .dw 0xf7c0, 0xc11c, 0xf7ff, 0xc11c, 0x21, 0 + .dw 0xf840, 0xc11c, 0xf87f, 0xc11c, 0x21, 0 + .dw 0xf8c0, 0xc11c, 0xf8ff, 0xc11c, 0x21, 0 + .dw 0xf940, 0xc11c, 0xf97f, 0xc11c, 0x21, 0 + .dw 0xf9c0, 0xc11c, 0xffff, 0xc11c, 0x21, 0 + .dw 0x0040, 0xc11d, 0x007f, 0xc11d, 0x21, 0 + .dw 0x00c0, 0xc11d, 0x00ff, 0xc11d, 0x21, 0 + .dw 0x0140, 0xc11d, 0x017f, 0xc11d, 0x21, 0 + .dw 0x01c0, 0xc11d, 0x01ff, 0xc11d, 0x21, 0 + .dw 0x0240, 0xc11d, 0x027f, 0xc11d, 0x21, 0 + .dw 0x02c0, 0xc11d, 0x02ff, 0xc11d, 0x21, 0 + .dw 0x0340, 0xc11d, 0x037f, 0xc11d, 0x21, 0 + .dw 0x03c0, 0xc11d, 0x03ff, 0xc11d, 0x21, 0 + .dw 0x0440, 0xc11d, 0x047f, 0xc11d, 0x21, 0 + .dw 0x04c0, 0xc11d, 0x04ff, 0xc11d, 0x21, 0 + .dw 0x0540, 0xc11d, 0x057f, 0xc11d, 0x21, 0 + .dw 0x05c0, 0xc11d, 0x05ff, 0xc11d, 0x21, 0 + .dw 0x0640, 0xc11d, 0x067f, 0xc11d, 0x21, 0 + .dw 0x06c0, 0xc11d, 0x06ff, 0xc11d, 0x21, 0 + .dw 0x0740, 0xc11d, 0x077f, 0xc11d, 0x21, 0 + .dw 0x07c0, 0xc11d, 0x07ff, 0xc11d, 0x21, 0 + .dw 0x0840, 0xc11d, 0x087f, 0xc11d, 0x21, 0 + .dw 0x08c0, 0xc11d, 0x08ff, 0xc11d, 0x21, 0 + .dw 0x0940, 0xc11d, 0x097f, 0xc11d, 0x21, 0 + .dw 0x09c0, 0xc11d, 0x09ff, 0xc11d, 0x21, 0 + .dw 0x0a40, 0xc11d, 0x0a7f, 0xc11d, 0x21, 0 + .dw 0x0ac0, 0xc11d, 0x0aff, 0xc11d, 0x21, 0 + .dw 0x0b40, 0xc11d, 0x0b7f, 0xc11d, 0x21, 0 + .dw 0x0bc0, 0xc11d, 0x0bff, 0xc11d, 0x21, 0 + .dw 0x0c40, 0xc11d, 0x0c7f, 0xc11d, 0x21, 0 + .dw 0x0cc0, 0xc11d, 0x0cff, 0xc11d, 0x21, 0 + .dw 0x0d40, 0xc11d, 0x0d7f, 0xc11d, 0x21, 0 + .dw 0x0dc0, 0xc11d, 0x0dff, 0xc11d, 0x21, 0 + .dw 0x0e40, 0xc11d, 0x0e7f, 0xc11d, 0x21, 0 + .dw 0x0ec0, 0xc11d, 0x0eff, 0xc11d, 0x21, 0 + .dw 0x0f40, 0xc11d, 0x0f7f, 0xc11d, 0x21, 0 + .dw 0x0fc0, 0xc11d, 0x0fff, 0xc11d, 0x21, 0 + .dw 0x1040, 0xc11d, 0x107f, 0xc11d, 0x21, 0 + .dw 0x10c0, 0xc11d, 0x10ff, 0xc11d, 0x21, 0 + .dw 0x1140, 0xc11d, 0x117f, 0xc11d, 0x21, 0 + .dw 0x11c0, 0xc11d, 0x11ff, 0xc11d, 0x21, 0 + .dw 0x1240, 0xc11d, 0x127f, 0xc11d, 0x21, 0 + .dw 0x12c0, 0xc11d, 0x12ff, 0xc11d, 0x21, 0 + .dw 0x1340, 0xc11d, 0x137f, 0xc11d, 0x21, 0 + .dw 0x13c0, 0xc11d, 0x13ff, 0xc11d, 0x21, 0 + .dw 0x1440, 0xc11d, 0x147f, 0xc11d, 0x21, 0 + .dw 0x14c0, 0xc11d, 0x14ff, 0xc11d, 0x21, 0 + .dw 0x1540, 0xc11d, 0x157f, 0xc11d, 0x21, 0 + .dw 0x15c0, 0xc11d, 0x15ff, 0xc11d, 0x21, 0 + .dw 0x1640, 0xc11d, 0x167f, 0xc11d, 0x21, 0 + .dw 0x16c0, 0xc11d, 0x16ff, 0xc11d, 0x21, 0 + .dw 0x1740, 0xc11d, 0x177f, 0xc11d, 0x21, 0 + .dw 0x17c0, 0xc11d, 0x17ff, 0xc11d, 0x21, 0 + .dw 0x1840, 0xc11d, 0x187f, 0xc11d, 0x21, 0 + .dw 0x18c0, 0xc11d, 0x18ff, 0xc11d, 0x21, 0 + .dw 0x1940, 0xc11d, 0x197f, 0xc11d, 0x21, 0 + .dw 0x19c0, 0xc11d, 0x1fff, 0xc11d, 0x21, 0 + .dw 0x2040, 0xc11d, 0x207f, 0xc11d, 0x21, 0 + .dw 0x20c0, 0xc11d, 0x20ff, 0xc11d, 0x21, 0 + .dw 0x2140, 0xc11d, 0x217f, 0xc11d, 0x21, 0 + .dw 0x21c0, 0xc11d, 0x21ff, 0xc11d, 0x21, 0 + .dw 0x2240, 0xc11d, 0x227f, 0xc11d, 0x21, 0 + .dw 0x22c0, 0xc11d, 0x22ff, 0xc11d, 0x21, 0 + .dw 0x2340, 0xc11d, 0x237f, 0xc11d, 0x21, 0 + .dw 0x23c0, 0xc11d, 0x23ff, 0xc11d, 0x21, 0 + .dw 0x2440, 0xc11d, 0x247f, 0xc11d, 0x21, 0 + .dw 0x24c0, 0xc11d, 0x24ff, 0xc11d, 0x21, 0 + .dw 0x2540, 0xc11d, 0x257f, 0xc11d, 0x21, 0 + .dw 0x25c0, 0xc11d, 0x25ff, 0xc11d, 0x21, 0 + .dw 0x2640, 0xc11d, 0x267f, 0xc11d, 0x21, 0 + .dw 0x26c0, 0xc11d, 0x26ff, 0xc11d, 0x21, 0 + .dw 0x2740, 0xc11d, 0x277f, 0xc11d, 0x21, 0 + .dw 0x27c0, 0xc11d, 0x27ff, 0xc11d, 0x21, 0 + .dw 0x2840, 0xc11d, 0x287f, 0xc11d, 0x21, 0 + .dw 0x28c0, 0xc11d, 0x28ff, 0xc11d, 0x21, 0 + .dw 0x2940, 0xc11d, 0x297f, 0xc11d, 0x21, 0 + .dw 0x29c0, 0xc11d, 0x29ff, 0xc11d, 0x21, 0 + .dw 0x2a40, 0xc11d, 0x2a7f, 0xc11d, 0x21, 0 + .dw 0x2ac0, 0xc11d, 0x2aff, 0xc11d, 0x21, 0 + .dw 0x2b40, 0xc11d, 0x2b7f, 0xc11d, 0x21, 0 + .dw 0x2bc0, 0xc11d, 0x2bff, 0xc11d, 0x21, 0 + .dw 0x2c40, 0xc11d, 0x2c7f, 0xc11d, 0x21, 0 + .dw 0x2cc0, 0xc11d, 0x2cff, 0xc11d, 0x21, 0 + .dw 0x2d40, 0xc11d, 0x2d7f, 0xc11d, 0x21, 0 + .dw 0x2dc0, 0xc11d, 0x2dff, 0xc11d, 0x21, 0 + .dw 0x2e40, 0xc11d, 0x2e7f, 0xc11d, 0x21, 0 + .dw 0x2ec0, 0xc11d, 0x2eff, 0xc11d, 0x21, 0 + .dw 0x2f40, 0xc11d, 0x2f7f, 0xc11d, 0x21, 0 + .dw 0x2fc0, 0xc11d, 0x2fff, 0xc11d, 0x21, 0 + .dw 0x3040, 0xc11d, 0x307f, 0xc11d, 0x21, 0 + .dw 0x30c0, 0xc11d, 0x30ff, 0xc11d, 0x21, 0 + .dw 0x3140, 0xc11d, 0x317f, 0xc11d, 0x21, 0 + .dw 0x31c0, 0xc11d, 0x31ff, 0xc11d, 0x21, 0 + .dw 0x3240, 0xc11d, 0x327f, 0xc11d, 0x21, 0 + .dw 0x32c0, 0xc11d, 0x32ff, 0xc11d, 0x21, 0 + .dw 0x3340, 0xc11d, 0x337f, 0xc11d, 0x21, 0 + .dw 0x33c0, 0xc11d, 0x33ff, 0xc11d, 0x21, 0 + .dw 0x3440, 0xc11d, 0x347f, 0xc11d, 0x21, 0 + .dw 0x34c0, 0xc11d, 0x34ff, 0xc11d, 0x21, 0 + .dw 0x3540, 0xc11d, 0x357f, 0xc11d, 0x21, 0 + .dw 0x35c0, 0xc11d, 0x35ff, 0xc11d, 0x21, 0 + .dw 0x3640, 0xc11d, 0x367f, 0xc11d, 0x21, 0 + .dw 0x36c0, 0xc11d, 0x36ff, 0xc11d, 0x21, 0 + .dw 0x3740, 0xc11d, 0x377f, 0xc11d, 0x21, 0 + .dw 0x37c0, 0xc11d, 0x37ff, 0xc11d, 0x21, 0 + .dw 0x3840, 0xc11d, 0x387f, 0xc11d, 0x21, 0 + .dw 0x38c0, 0xc11d, 0x38ff, 0xc11d, 0x21, 0 + .dw 0x3940, 0xc11d, 0x397f, 0xc11d, 0x21, 0 + .dw 0x39c0, 0xc11d, 0x3fff, 0xc11d, 0x21, 0 + .dw 0x4040, 0xc11d, 0x407f, 0xc11d, 0x21, 0 + .dw 0x40c0, 0xc11d, 0x40ff, 0xc11d, 0x21, 0 + .dw 0x4140, 0xc11d, 0x417f, 0xc11d, 0x21, 0 + .dw 0x41c0, 0xc11d, 0x41ff, 0xc11d, 0x21, 0 + .dw 0x4240, 0xc11d, 0x427f, 0xc11d, 0x21, 0 + .dw 0x42c0, 0xc11d, 0x42ff, 0xc11d, 0x21, 0 + .dw 0x4340, 0xc11d, 0x437f, 0xc11d, 0x21, 0 + .dw 0x43c0, 0xc11d, 0x43ff, 0xc11d, 0x21, 0 + .dw 0x4440, 0xc11d, 0x447f, 0xc11d, 0x21, 0 + .dw 0x44c0, 0xc11d, 0x44ff, 0xc11d, 0x21, 0 + .dw 0x4540, 0xc11d, 0x457f, 0xc11d, 0x21, 0 + .dw 0x45c0, 0xc11d, 0x45ff, 0xc11d, 0x21, 0 + .dw 0x4640, 0xc11d, 0x467f, 0xc11d, 0x21, 0 + .dw 0x46c0, 0xc11d, 0x46ff, 0xc11d, 0x21, 0 + .dw 0x4740, 0xc11d, 0x477f, 0xc11d, 0x21, 0 + .dw 0x47c0, 0xc11d, 0x47ff, 0xc11d, 0x21, 0 + .dw 0x4840, 0xc11d, 0x487f, 0xc11d, 0x21, 0 + .dw 0x48c0, 0xc11d, 0x48ff, 0xc11d, 0x21, 0 + .dw 0x4940, 0xc11d, 0x497f, 0xc11d, 0x21, 0 + .dw 0x49c0, 0xc11d, 0x49ff, 0xc11d, 0x21, 0 + .dw 0x4a40, 0xc11d, 0x4a7f, 0xc11d, 0x21, 0 + .dw 0x4ac0, 0xc11d, 0x4aff, 0xc11d, 0x21, 0 + .dw 0x4b40, 0xc11d, 0x4b7f, 0xc11d, 0x21, 0 + .dw 0x4bc0, 0xc11d, 0x4bff, 0xc11d, 0x21, 0 + .dw 0x4c40, 0xc11d, 0x4c7f, 0xc11d, 0x21, 0 + .dw 0x4cc0, 0xc11d, 0x4cff, 0xc11d, 0x21, 0 + .dw 0x4d40, 0xc11d, 0x4d7f, 0xc11d, 0x21, 0 + .dw 0x4dc0, 0xc11d, 0x4dff, 0xc11d, 0x21, 0 + .dw 0x4e40, 0xc11d, 0x4e7f, 0xc11d, 0x21, 0 + .dw 0x4ec0, 0xc11d, 0x4eff, 0xc11d, 0x21, 0 + .dw 0x4f40, 0xc11d, 0x4f7f, 0xc11d, 0x21, 0 + .dw 0x4fc0, 0xc11d, 0x4fff, 0xc11d, 0x21, 0 + .dw 0x5040, 0xc11d, 0x507f, 0xc11d, 0x21, 0 + .dw 0x50c0, 0xc11d, 0x50ff, 0xc11d, 0x21, 0 + .dw 0x5140, 0xc11d, 0x517f, 0xc11d, 0x21, 0 + .dw 0x51c0, 0xc11d, 0x51ff, 0xc11d, 0x21, 0 + .dw 0x5240, 0xc11d, 0x527f, 0xc11d, 0x21, 0 + .dw 0x52c0, 0xc11d, 0x52ff, 0xc11d, 0x21, 0 + .dw 0x5340, 0xc11d, 0x537f, 0xc11d, 0x21, 0 + .dw 0x53c0, 0xc11d, 0x53ff, 0xc11d, 0x21, 0 + .dw 0x5440, 0xc11d, 0x547f, 0xc11d, 0x21, 0 + .dw 0x54c0, 0xc11d, 0x54ff, 0xc11d, 0x21, 0 + .dw 0x5540, 0xc11d, 0x557f, 0xc11d, 0x21, 0 + .dw 0x55c0, 0xc11d, 0x55ff, 0xc11d, 0x21, 0 + .dw 0x5640, 0xc11d, 0x567f, 0xc11d, 0x21, 0 + .dw 0x56c0, 0xc11d, 0x56ff, 0xc11d, 0x21, 0 + .dw 0x5740, 0xc11d, 0x577f, 0xc11d, 0x21, 0 + .dw 0x57c0, 0xc11d, 0x57ff, 0xc11d, 0x21, 0 + .dw 0x5840, 0xc11d, 0x587f, 0xc11d, 0x21, 0 + .dw 0x58c0, 0xc11d, 0x58ff, 0xc11d, 0x21, 0 + .dw 0x5940, 0xc11d, 0x597f, 0xc11d, 0x21, 0 + .dw 0x59c0, 0xc11d, 0x5fff, 0xc11d, 0x21, 0 + .dw 0x6040, 0xc11d, 0x607f, 0xc11d, 0x21, 0 + .dw 0x60c0, 0xc11d, 0x60ff, 0xc11d, 0x21, 0 + .dw 0x6140, 0xc11d, 0x617f, 0xc11d, 0x21, 0 + .dw 0x61c0, 0xc11d, 0x61ff, 0xc11d, 0x21, 0 + .dw 0x6240, 0xc11d, 0x627f, 0xc11d, 0x21, 0 + .dw 0x62c0, 0xc11d, 0x62ff, 0xc11d, 0x21, 0 + .dw 0x6340, 0xc11d, 0x637f, 0xc11d, 0x21, 0 + .dw 0x63c0, 0xc11d, 0x63ff, 0xc11d, 0x21, 0 + .dw 0x6440, 0xc11d, 0x647f, 0xc11d, 0x21, 0 + .dw 0x64c0, 0xc11d, 0x64ff, 0xc11d, 0x21, 0 + .dw 0x6540, 0xc11d, 0x657f, 0xc11d, 0x21, 0 + .dw 0x65c0, 0xc11d, 0x65ff, 0xc11d, 0x21, 0 + .dw 0x6640, 0xc11d, 0x667f, 0xc11d, 0x21, 0 + .dw 0x66c0, 0xc11d, 0x66ff, 0xc11d, 0x21, 0 + .dw 0x6740, 0xc11d, 0x677f, 0xc11d, 0x21, 0 + .dw 0x67c0, 0xc11d, 0x67ff, 0xc11d, 0x21, 0 + .dw 0x6840, 0xc11d, 0x687f, 0xc11d, 0x21, 0 + .dw 0x68c0, 0xc11d, 0x68ff, 0xc11d, 0x21, 0 + .dw 0x6940, 0xc11d, 0x697f, 0xc11d, 0x21, 0 + .dw 0x69c0, 0xc11d, 0x69ff, 0xc11d, 0x21, 0 + .dw 0x6a40, 0xc11d, 0x6a7f, 0xc11d, 0x21, 0 + .dw 0x6ac0, 0xc11d, 0x6aff, 0xc11d, 0x21, 0 + .dw 0x6b40, 0xc11d, 0x6b7f, 0xc11d, 0x21, 0 + .dw 0x6bc0, 0xc11d, 0x6bff, 0xc11d, 0x21, 0 + .dw 0x6c40, 0xc11d, 0x6c7f, 0xc11d, 0x21, 0 + .dw 0x6cc0, 0xc11d, 0x6cff, 0xc11d, 0x21, 0 + .dw 0x6d40, 0xc11d, 0x6d7f, 0xc11d, 0x21, 0 + .dw 0x6dc0, 0xc11d, 0x6dff, 0xc11d, 0x21, 0 + .dw 0x6e40, 0xc11d, 0x6e7f, 0xc11d, 0x21, 0 + .dw 0x6ec0, 0xc11d, 0x6eff, 0xc11d, 0x21, 0 + .dw 0x6f40, 0xc11d, 0x6f7f, 0xc11d, 0x21, 0 + .dw 0x6fc0, 0xc11d, 0x6fff, 0xc11d, 0x21, 0 + .dw 0x7040, 0xc11d, 0x707f, 0xc11d, 0x21, 0 + .dw 0x70c0, 0xc11d, 0x70ff, 0xc11d, 0x21, 0 + .dw 0x7140, 0xc11d, 0x717f, 0xc11d, 0x21, 0 + .dw 0x71c0, 0xc11d, 0x71ff, 0xc11d, 0x21, 0 + .dw 0x7240, 0xc11d, 0x727f, 0xc11d, 0x21, 0 + .dw 0x72c0, 0xc11d, 0x72ff, 0xc11d, 0x21, 0 + .dw 0x7340, 0xc11d, 0x737f, 0xc11d, 0x21, 0 + .dw 0x73c0, 0xc11d, 0x73ff, 0xc11d, 0x21, 0 + .dw 0x7440, 0xc11d, 0x747f, 0xc11d, 0x21, 0 + .dw 0x74c0, 0xc11d, 0x74ff, 0xc11d, 0x21, 0 + .dw 0x7540, 0xc11d, 0x757f, 0xc11d, 0x21, 0 + .dw 0x75c0, 0xc11d, 0x75ff, 0xc11d, 0x21, 0 + .dw 0x7640, 0xc11d, 0x767f, 0xc11d, 0x21, 0 + .dw 0x76c0, 0xc11d, 0x76ff, 0xc11d, 0x21, 0 + .dw 0x7740, 0xc11d, 0x777f, 0xc11d, 0x21, 0 + .dw 0x77c0, 0xc11d, 0x77ff, 0xc11d, 0x21, 0 + .dw 0x7840, 0xc11d, 0x787f, 0xc11d, 0x21, 0 + .dw 0x78c0, 0xc11d, 0x78ff, 0xc11d, 0x21, 0 + .dw 0x7940, 0xc11d, 0x797f, 0xc11d, 0x21, 0 + .dw 0x79c0, 0xc11d, 0x7fff, 0xc11d, 0x21, 0 + .dw 0x8040, 0xc11d, 0x807f, 0xc11d, 0x21, 0 + .dw 0x80c0, 0xc11d, 0x80ff, 0xc11d, 0x21, 0 + .dw 0x8140, 0xc11d, 0x817f, 0xc11d, 0x21, 0 + .dw 0x81c0, 0xc11d, 0x81ff, 0xc11d, 0x21, 0 + .dw 0x8240, 0xc11d, 0x827f, 0xc11d, 0x21, 0 + .dw 0x82c0, 0xc11d, 0x82ff, 0xc11d, 0x21, 0 + .dw 0x8340, 0xc11d, 0x837f, 0xc11d, 0x21, 0 + .dw 0x83c0, 0xc11d, 0x83ff, 0xc11d, 0x21, 0 + .dw 0x8440, 0xc11d, 0x847f, 0xc11d, 0x21, 0 + .dw 0x84c0, 0xc11d, 0x84ff, 0xc11d, 0x21, 0 + .dw 0x8540, 0xc11d, 0x857f, 0xc11d, 0x21, 0 + .dw 0x85c0, 0xc11d, 0x85ff, 0xc11d, 0x21, 0 + .dw 0x8640, 0xc11d, 0x867f, 0xc11d, 0x21, 0 + .dw 0x86c0, 0xc11d, 0x86ff, 0xc11d, 0x21, 0 + .dw 0x8740, 0xc11d, 0x877f, 0xc11d, 0x21, 0 + .dw 0x87c0, 0xc11d, 0x87ff, 0xc11d, 0x21, 0 + .dw 0x8840, 0xc11d, 0x887f, 0xc11d, 0x21, 0 + .dw 0x88c0, 0xc11d, 0x88ff, 0xc11d, 0x21, 0 + .dw 0x8940, 0xc11d, 0x897f, 0xc11d, 0x21, 0 + .dw 0x89c0, 0xc11d, 0x89ff, 0xc11d, 0x21, 0 + .dw 0x8a40, 0xc11d, 0x8a7f, 0xc11d, 0x21, 0 + .dw 0x8ac0, 0xc11d, 0x8aff, 0xc11d, 0x21, 0 + .dw 0x8b40, 0xc11d, 0x8b7f, 0xc11d, 0x21, 0 + .dw 0x8bc0, 0xc11d, 0x8bff, 0xc11d, 0x21, 0 + .dw 0x8c40, 0xc11d, 0x8c7f, 0xc11d, 0x21, 0 + .dw 0x8cc0, 0xc11d, 0x8cff, 0xc11d, 0x21, 0 + .dw 0x8d40, 0xc11d, 0x8d7f, 0xc11d, 0x21, 0 + .dw 0x8dc0, 0xc11d, 0x8dff, 0xc11d, 0x21, 0 + .dw 0x8e40, 0xc11d, 0x8e7f, 0xc11d, 0x21, 0 + .dw 0x8ec0, 0xc11d, 0x8eff, 0xc11d, 0x21, 0 + .dw 0x8f40, 0xc11d, 0x8f7f, 0xc11d, 0x21, 0 + .dw 0x8fc0, 0xc11d, 0x8fff, 0xc11d, 0x21, 0 + .dw 0x9040, 0xc11d, 0x907f, 0xc11d, 0x21, 0 + .dw 0x90c0, 0xc11d, 0x90ff, 0xc11d, 0x21, 0 + .dw 0x9140, 0xc11d, 0x917f, 0xc11d, 0x21, 0 + .dw 0x91c0, 0xc11d, 0x91ff, 0xc11d, 0x21, 0 + .dw 0x9240, 0xc11d, 0x927f, 0xc11d, 0x21, 0 + .dw 0x92c0, 0xc11d, 0x92ff, 0xc11d, 0x21, 0 + .dw 0x9340, 0xc11d, 0x937f, 0xc11d, 0x21, 0 + .dw 0x93c0, 0xc11d, 0x93ff, 0xc11d, 0x21, 0 + .dw 0x9440, 0xc11d, 0x947f, 0xc11d, 0x21, 0 + .dw 0x94c0, 0xc11d, 0x94ff, 0xc11d, 0x21, 0 + .dw 0x9540, 0xc11d, 0x957f, 0xc11d, 0x21, 0 + .dw 0x95c0, 0xc11d, 0x95ff, 0xc11d, 0x21, 0 + .dw 0x9640, 0xc11d, 0x967f, 0xc11d, 0x21, 0 + .dw 0x96c0, 0xc11d, 0x96ff, 0xc11d, 0x21, 0 + .dw 0x9740, 0xc11d, 0x977f, 0xc11d, 0x21, 0 + .dw 0x97c0, 0xc11d, 0x97ff, 0xc11d, 0x21, 0 + .dw 0x9840, 0xc11d, 0x987f, 0xc11d, 0x21, 0 + .dw 0x98c0, 0xc11d, 0x98ff, 0xc11d, 0x21, 0 + .dw 0x9940, 0xc11d, 0x997f, 0xc11d, 0x21, 0 + .dw 0x99c0, 0xc11d, 0x9fff, 0xc11d, 0x21, 0 + .dw 0xa040, 0xc11d, 0xa07f, 0xc11d, 0x21, 0 + .dw 0xa0c0, 0xc11d, 0xa0ff, 0xc11d, 0x21, 0 + .dw 0xa140, 0xc11d, 0xa17f, 0xc11d, 0x21, 0 + .dw 0xa1c0, 0xc11d, 0xa1ff, 0xc11d, 0x21, 0 + .dw 0xa240, 0xc11d, 0xa27f, 0xc11d, 0x21, 0 + .dw 0xa2c0, 0xc11d, 0xa2ff, 0xc11d, 0x21, 0 + .dw 0xa340, 0xc11d, 0xa37f, 0xc11d, 0x21, 0 + .dw 0xa3c0, 0xc11d, 0xa3ff, 0xc11d, 0x21, 0 + .dw 0xa440, 0xc11d, 0xa47f, 0xc11d, 0x21, 0 + .dw 0xa4c0, 0xc11d, 0xa4ff, 0xc11d, 0x21, 0 + .dw 0xa540, 0xc11d, 0xa57f, 0xc11d, 0x21, 0 + .dw 0xa5c0, 0xc11d, 0xa5ff, 0xc11d, 0x21, 0 + .dw 0xa640, 0xc11d, 0xa67f, 0xc11d, 0x21, 0 + .dw 0xa6c0, 0xc11d, 0xa6ff, 0xc11d, 0x21, 0 + .dw 0xa740, 0xc11d, 0xa77f, 0xc11d, 0x21, 0 + .dw 0xa7c0, 0xc11d, 0xa7ff, 0xc11d, 0x21, 0 + .dw 0xa840, 0xc11d, 0xa87f, 0xc11d, 0x21, 0 + .dw 0xa8c0, 0xc11d, 0xa8ff, 0xc11d, 0x21, 0 + .dw 0xa940, 0xc11d, 0xa97f, 0xc11d, 0x21, 0 + .dw 0xa9c0, 0xc11d, 0xa9ff, 0xc11d, 0x21, 0 + .dw 0xaa40, 0xc11d, 0xaa7f, 0xc11d, 0x21, 0 + .dw 0xaac0, 0xc11d, 0xaaff, 0xc11d, 0x21, 0 + .dw 0xab40, 0xc11d, 0xab7f, 0xc11d, 0x21, 0 + .dw 0xabc0, 0xc11d, 0xabff, 0xc11d, 0x21, 0 + .dw 0xac40, 0xc11d, 0xac7f, 0xc11d, 0x21, 0 + .dw 0xacc0, 0xc11d, 0xacff, 0xc11d, 0x21, 0 + .dw 0xad40, 0xc11d, 0xad7f, 0xc11d, 0x21, 0 + .dw 0xadc0, 0xc11d, 0xadff, 0xc11d, 0x21, 0 + .dw 0xae40, 0xc11d, 0xae7f, 0xc11d, 0x21, 0 + .dw 0xaec0, 0xc11d, 0xaeff, 0xc11d, 0x21, 0 + .dw 0xaf40, 0xc11d, 0xaf7f, 0xc11d, 0x21, 0 + .dw 0xafc0, 0xc11d, 0xafff, 0xc11d, 0x21, 0 + .dw 0xb040, 0xc11d, 0xb07f, 0xc11d, 0x21, 0 + .dw 0xb0c0, 0xc11d, 0xb0ff, 0xc11d, 0x21, 0 + .dw 0xb140, 0xc11d, 0xb17f, 0xc11d, 0x21, 0 + .dw 0xb1c0, 0xc11d, 0xb1ff, 0xc11d, 0x21, 0 + .dw 0xb240, 0xc11d, 0xb27f, 0xc11d, 0x21, 0 + .dw 0xb2c0, 0xc11d, 0xb2ff, 0xc11d, 0x21, 0 + .dw 0xb340, 0xc11d, 0xb37f, 0xc11d, 0x21, 0 + .dw 0xb3c0, 0xc11d, 0xb3ff, 0xc11d, 0x21, 0 + .dw 0xb440, 0xc11d, 0xb47f, 0xc11d, 0x21, 0 + .dw 0xb4c0, 0xc11d, 0xb4ff, 0xc11d, 0x21, 0 + .dw 0xb540, 0xc11d, 0xb57f, 0xc11d, 0x21, 0 + .dw 0xb5c0, 0xc11d, 0xb5ff, 0xc11d, 0x21, 0 + .dw 0xb640, 0xc11d, 0xb67f, 0xc11d, 0x21, 0 + .dw 0xb6c0, 0xc11d, 0xb6ff, 0xc11d, 0x21, 0 + .dw 0xb740, 0xc11d, 0xb77f, 0xc11d, 0x21, 0 + .dw 0xb7c0, 0xc11d, 0xb7ff, 0xc11d, 0x21, 0 + .dw 0xb840, 0xc11d, 0xb87f, 0xc11d, 0x21, 0 + .dw 0xb8c0, 0xc11d, 0xb8ff, 0xc11d, 0x21, 0 + .dw 0xb940, 0xc11d, 0xb97f, 0xc11d, 0x21, 0 + .dw 0xb9c0, 0xc11d, 0xbfff, 0xc11d, 0x21, 0 + .dw 0xc040, 0xc11d, 0xc07f, 0xc11d, 0x21, 0 + .dw 0xc0c0, 0xc11d, 0xc0ff, 0xc11d, 0x21, 0 + .dw 0xc140, 0xc11d, 0xc17f, 0xc11d, 0x21, 0 + .dw 0xc1c0, 0xc11d, 0xc1ff, 0xc11d, 0x21, 0 + .dw 0xc240, 0xc11d, 0xc27f, 0xc11d, 0x21, 0 + .dw 0xc2c0, 0xc11d, 0xc2ff, 0xc11d, 0x21, 0 + .dw 0xc340, 0xc11d, 0xc37f, 0xc11d, 0x21, 0 + .dw 0xc3c0, 0xc11d, 0xc3ff, 0xc11d, 0x21, 0 + .dw 0xc440, 0xc11d, 0xc47f, 0xc11d, 0x21, 0 + .dw 0xc4c0, 0xc11d, 0xc4ff, 0xc11d, 0x21, 0 + .dw 0xc540, 0xc11d, 0xc57f, 0xc11d, 0x21, 0 + .dw 0xc5c0, 0xc11d, 0xc5ff, 0xc11d, 0x21, 0 + .dw 0xc640, 0xc11d, 0xc67f, 0xc11d, 0x21, 0 + .dw 0xc6c0, 0xc11d, 0xc6ff, 0xc11d, 0x21, 0 + .dw 0xc740, 0xc11d, 0xc77f, 0xc11d, 0x21, 0 + .dw 0xc7c0, 0xc11d, 0xc7ff, 0xc11d, 0x21, 0 + .dw 0xc840, 0xc11d, 0xc87f, 0xc11d, 0x21, 0 + .dw 0xc8c0, 0xc11d, 0xc8ff, 0xc11d, 0x21, 0 + .dw 0xc940, 0xc11d, 0xc97f, 0xc11d, 0x21, 0 + .dw 0xc9c0, 0xc11d, 0xc9ff, 0xc11d, 0x21, 0 + .dw 0xca40, 0xc11d, 0xca7f, 0xc11d, 0x21, 0 + .dw 0xcac0, 0xc11d, 0xcaff, 0xc11d, 0x21, 0 + .dw 0xcb40, 0xc11d, 0xcb7f, 0xc11d, 0x21, 0 + .dw 0xcbc0, 0xc11d, 0xcbff, 0xc11d, 0x21, 0 + .dw 0xcc40, 0xc11d, 0xcc7f, 0xc11d, 0x21, 0 + .dw 0xccc0, 0xc11d, 0xccff, 0xc11d, 0x21, 0 + .dw 0xcd40, 0xc11d, 0xcd7f, 0xc11d, 0x21, 0 + .dw 0xcdc0, 0xc11d, 0xcdff, 0xc11d, 0x21, 0 + .dw 0xce40, 0xc11d, 0xce7f, 0xc11d, 0x21, 0 + .dw 0xcec0, 0xc11d, 0xceff, 0xc11d, 0x21, 0 + .dw 0xcf40, 0xc11d, 0xcf7f, 0xc11d, 0x21, 0 + .dw 0xcfc0, 0xc11d, 0xcfff, 0xc11d, 0x21, 0 + .dw 0xd040, 0xc11d, 0xd07f, 0xc11d, 0x21, 0 + .dw 0xd0c0, 0xc11d, 0xd0ff, 0xc11d, 0x21, 0 + .dw 0xd140, 0xc11d, 0xd17f, 0xc11d, 0x21, 0 + .dw 0xd1c0, 0xc11d, 0xd1ff, 0xc11d, 0x21, 0 + .dw 0xd240, 0xc11d, 0xd27f, 0xc11d, 0x21, 0 + .dw 0xd2c0, 0xc11d, 0xd2ff, 0xc11d, 0x21, 0 + .dw 0xd340, 0xc11d, 0xd37f, 0xc11d, 0x21, 0 + .dw 0xd3c0, 0xc11d, 0xd3ff, 0xc11d, 0x21, 0 + .dw 0xd440, 0xc11d, 0xd47f, 0xc11d, 0x21, 0 + .dw 0xd4c0, 0xc11d, 0xd4ff, 0xc11d, 0x21, 0 + .dw 0xd540, 0xc11d, 0xd57f, 0xc11d, 0x21, 0 + .dw 0xd5c0, 0xc11d, 0xd5ff, 0xc11d, 0x21, 0 + .dw 0xd640, 0xc11d, 0xd67f, 0xc11d, 0x21, 0 + .dw 0xd6c0, 0xc11d, 0xd6ff, 0xc11d, 0x21, 0 + .dw 0xd740, 0xc11d, 0xd77f, 0xc11d, 0x21, 0 + .dw 0xd7c0, 0xc11d, 0xd7ff, 0xc11d, 0x21, 0 + .dw 0xd840, 0xc11d, 0xd87f, 0xc11d, 0x21, 0 + .dw 0xd8c0, 0xc11d, 0xd8ff, 0xc11d, 0x21, 0 + .dw 0xd940, 0xc11d, 0xd97f, 0xc11d, 0x21, 0 + .dw 0xd9c0, 0xc11d, 0xdfff, 0xc11d, 0x21, 0 + .dw 0xe040, 0xc11d, 0xe07f, 0xc11d, 0x21, 0 + .dw 0xe0c0, 0xc11d, 0xe0ff, 0xc11d, 0x21, 0 + .dw 0xe140, 0xc11d, 0xe17f, 0xc11d, 0x21, 0 + .dw 0xe1c0, 0xc11d, 0xe1ff, 0xc11d, 0x21, 0 + .dw 0xe240, 0xc11d, 0xe27f, 0xc11d, 0x21, 0 + .dw 0xe2c0, 0xc11d, 0xe2ff, 0xc11d, 0x21, 0 + .dw 0xe340, 0xc11d, 0xe37f, 0xc11d, 0x21, 0 + .dw 0xe3c0, 0xc11d, 0xe3ff, 0xc11d, 0x21, 0 + .dw 0xe440, 0xc11d, 0xe47f, 0xc11d, 0x21, 0 + .dw 0xe4c0, 0xc11d, 0xe4ff, 0xc11d, 0x21, 0 + .dw 0xe540, 0xc11d, 0xe57f, 0xc11d, 0x21, 0 + .dw 0xe5c0, 0xc11d, 0xe5ff, 0xc11d, 0x21, 0 + .dw 0xe640, 0xc11d, 0xe67f, 0xc11d, 0x21, 0 + .dw 0xe6c0, 0xc11d, 0xe6ff, 0xc11d, 0x21, 0 + .dw 0xe740, 0xc11d, 0xe77f, 0xc11d, 0x21, 0 + .dw 0xe7c0, 0xc11d, 0xe7ff, 0xc11d, 0x21, 0 + .dw 0xe840, 0xc11d, 0xe87f, 0xc11d, 0x21, 0 + .dw 0xe8c0, 0xc11d, 0xe8ff, 0xc11d, 0x21, 0 + .dw 0xe940, 0xc11d, 0xe97f, 0xc11d, 0x21, 0 + .dw 0xe9c0, 0xc11d, 0xe9ff, 0xc11d, 0x21, 0 + .dw 0xea40, 0xc11d, 0xea7f, 0xc11d, 0x21, 0 + .dw 0xeac0, 0xc11d, 0xeaff, 0xc11d, 0x21, 0 + .dw 0xeb40, 0xc11d, 0xeb7f, 0xc11d, 0x21, 0 + .dw 0xebc0, 0xc11d, 0xebff, 0xc11d, 0x21, 0 + .dw 0xec40, 0xc11d, 0xec7f, 0xc11d, 0x21, 0 + .dw 0xecc0, 0xc11d, 0xecff, 0xc11d, 0x21, 0 + .dw 0xed40, 0xc11d, 0xed7f, 0xc11d, 0x21, 0 + .dw 0xedc0, 0xc11d, 0xedff, 0xc11d, 0x21, 0 + .dw 0xee40, 0xc11d, 0xee7f, 0xc11d, 0x21, 0 + .dw 0xeec0, 0xc11d, 0xeeff, 0xc11d, 0x21, 0 + .dw 0xef40, 0xc11d, 0xef7f, 0xc11d, 0x21, 0 + .dw 0xefc0, 0xc11d, 0xefff, 0xc11d, 0x21, 0 + .dw 0xf040, 0xc11d, 0xf07f, 0xc11d, 0x21, 0 + .dw 0xf0c0, 0xc11d, 0xf0ff, 0xc11d, 0x21, 0 + .dw 0xf140, 0xc11d, 0xf17f, 0xc11d, 0x21, 0 + .dw 0xf1c0, 0xc11d, 0xf1ff, 0xc11d, 0x21, 0 + .dw 0xf240, 0xc11d, 0xf27f, 0xc11d, 0x21, 0 + .dw 0xf2c0, 0xc11d, 0xf2ff, 0xc11d, 0x21, 0 + .dw 0xf340, 0xc11d, 0xf37f, 0xc11d, 0x21, 0 + .dw 0xf3c0, 0xc11d, 0xf3ff, 0xc11d, 0x21, 0 + .dw 0xf440, 0xc11d, 0xf47f, 0xc11d, 0x21, 0 + .dw 0xf4c0, 0xc11d, 0xf4ff, 0xc11d, 0x21, 0 + .dw 0xf540, 0xc11d, 0xf57f, 0xc11d, 0x21, 0 + .dw 0xf5c0, 0xc11d, 0xf5ff, 0xc11d, 0x21, 0 + .dw 0xf640, 0xc11d, 0xf67f, 0xc11d, 0x21, 0 + .dw 0xf6c0, 0xc11d, 0xf6ff, 0xc11d, 0x21, 0 + .dw 0xf740, 0xc11d, 0xf77f, 0xc11d, 0x21, 0 + .dw 0xf7c0, 0xc11d, 0xf7ff, 0xc11d, 0x21, 0 + .dw 0xf840, 0xc11d, 0xf87f, 0xc11d, 0x21, 0 + .dw 0xf8c0, 0xc11d, 0xf8ff, 0xc11d, 0x21, 0 + .dw 0xf940, 0xc11d, 0xf97f, 0xc11d, 0x21, 0 + .dw 0xf9c0, 0xc11d, 0xffff, 0xc11d, 0x21, 0 + .dw 0x0040, 0xc11e, 0x007f, 0xc11e, 0x21, 0 + .dw 0x00c0, 0xc11e, 0x00ff, 0xc11e, 0x21, 0 + .dw 0x0140, 0xc11e, 0x017f, 0xc11e, 0x21, 0 + .dw 0x01c0, 0xc11e, 0x01ff, 0xc11e, 0x21, 0 + .dw 0x0240, 0xc11e, 0x027f, 0xc11e, 0x21, 0 + .dw 0x02c0, 0xc11e, 0x02ff, 0xc11e, 0x21, 0 + .dw 0x0340, 0xc11e, 0x037f, 0xc11e, 0x21, 0 + .dw 0x03c0, 0xc11e, 0x03ff, 0xc11e, 0x21, 0 + .dw 0x0440, 0xc11e, 0x047f, 0xc11e, 0x21, 0 + .dw 0x04c0, 0xc11e, 0x04ff, 0xc11e, 0x21, 0 + .dw 0x0540, 0xc11e, 0x057f, 0xc11e, 0x21, 0 + .dw 0x05c0, 0xc11e, 0x05ff, 0xc11e, 0x21, 0 + .dw 0x0640, 0xc11e, 0x067f, 0xc11e, 0x21, 0 + .dw 0x06c0, 0xc11e, 0x06ff, 0xc11e, 0x21, 0 + .dw 0x0740, 0xc11e, 0x077f, 0xc11e, 0x21, 0 + .dw 0x07c0, 0xc11e, 0x07ff, 0xc11e, 0x21, 0 + .dw 0x0840, 0xc11e, 0x087f, 0xc11e, 0x21, 0 + .dw 0x08c0, 0xc11e, 0x08ff, 0xc11e, 0x21, 0 + .dw 0x0940, 0xc11e, 0x097f, 0xc11e, 0x21, 0 + .dw 0x09c0, 0xc11e, 0x09ff, 0xc11e, 0x21, 0 + .dw 0x0a40, 0xc11e, 0x0a7f, 0xc11e, 0x21, 0 + .dw 0x0ac0, 0xc11e, 0x0aff, 0xc11e, 0x21, 0 + .dw 0x0b40, 0xc11e, 0x0b7f, 0xc11e, 0x21, 0 + .dw 0x0bc0, 0xc11e, 0x0bff, 0xc11e, 0x21, 0 + .dw 0x0c40, 0xc11e, 0x0c7f, 0xc11e, 0x21, 0 + .dw 0x0cc0, 0xc11e, 0x0cff, 0xc11e, 0x21, 0 + .dw 0x0d40, 0xc11e, 0x0d7f, 0xc11e, 0x21, 0 + .dw 0x0dc0, 0xc11e, 0x0dff, 0xc11e, 0x21, 0 + .dw 0x0e40, 0xc11e, 0x0e7f, 0xc11e, 0x21, 0 + .dw 0x0ec0, 0xc11e, 0x0eff, 0xc11e, 0x21, 0 + .dw 0x0f40, 0xc11e, 0x0f7f, 0xc11e, 0x21, 0 + .dw 0x0fc0, 0xc11e, 0x0fff, 0xc11e, 0x21, 0 + .dw 0x1040, 0xc11e, 0x107f, 0xc11e, 0x21, 0 + .dw 0x10c0, 0xc11e, 0x10ff, 0xc11e, 0x21, 0 + .dw 0x1140, 0xc11e, 0x117f, 0xc11e, 0x21, 0 + .dw 0x11c0, 0xc11e, 0x11ff, 0xc11e, 0x21, 0 + .dw 0x1240, 0xc11e, 0x127f, 0xc11e, 0x21, 0 + .dw 0x12c0, 0xc11e, 0x12ff, 0xc11e, 0x21, 0 + .dw 0x1340, 0xc11e, 0x137f, 0xc11e, 0x21, 0 + .dw 0x13c0, 0xc11e, 0x13ff, 0xc11e, 0x21, 0 + .dw 0x1440, 0xc11e, 0x147f, 0xc11e, 0x21, 0 + .dw 0x14c0, 0xc11e, 0x14ff, 0xc11e, 0x21, 0 + .dw 0x1540, 0xc11e, 0x157f, 0xc11e, 0x21, 0 + .dw 0x15c0, 0xc11e, 0x15ff, 0xc11e, 0x21, 0 + .dw 0x1640, 0xc11e, 0x167f, 0xc11e, 0x21, 0 + .dw 0x16c0, 0xc11e, 0x16ff, 0xc11e, 0x21, 0 + .dw 0x1740, 0xc11e, 0x177f, 0xc11e, 0x21, 0 + .dw 0x17c0, 0xc11e, 0x17ff, 0xc11e, 0x21, 0 + .dw 0x1840, 0xc11e, 0x187f, 0xc11e, 0x21, 0 + .dw 0x18c0, 0xc11e, 0x18ff, 0xc11e, 0x21, 0 + .dw 0x1940, 0xc11e, 0x197f, 0xc11e, 0x21, 0 + .dw 0x19c0, 0xc11e, 0x1fff, 0xc11e, 0x21, 0 + .dw 0x2040, 0xc11e, 0x207f, 0xc11e, 0x21, 0 + .dw 0x20c0, 0xc11e, 0x20ff, 0xc11e, 0x21, 0 + .dw 0x2140, 0xc11e, 0x217f, 0xc11e, 0x21, 0 + .dw 0x21c0, 0xc11e, 0x21ff, 0xc11e, 0x21, 0 + .dw 0x2240, 0xc11e, 0x227f, 0xc11e, 0x21, 0 + .dw 0x22c0, 0xc11e, 0x22ff, 0xc11e, 0x21, 0 + .dw 0x2340, 0xc11e, 0x237f, 0xc11e, 0x21, 0 + .dw 0x23c0, 0xc11e, 0x23ff, 0xc11e, 0x21, 0 + .dw 0x2440, 0xc11e, 0x247f, 0xc11e, 0x21, 0 + .dw 0x24c0, 0xc11e, 0x24ff, 0xc11e, 0x21, 0 + .dw 0x2540, 0xc11e, 0x257f, 0xc11e, 0x21, 0 + .dw 0x25c0, 0xc11e, 0x25ff, 0xc11e, 0x21, 0 + .dw 0x2640, 0xc11e, 0x267f, 0xc11e, 0x21, 0 + .dw 0x26c0, 0xc11e, 0x26ff, 0xc11e, 0x21, 0 + .dw 0x2740, 0xc11e, 0x277f, 0xc11e, 0x21, 0 + .dw 0x27c0, 0xc11e, 0x27ff, 0xc11e, 0x21, 0 + .dw 0x2840, 0xc11e, 0x287f, 0xc11e, 0x21, 0 + .dw 0x28c0, 0xc11e, 0x28ff, 0xc11e, 0x21, 0 + .dw 0x2940, 0xc11e, 0x297f, 0xc11e, 0x21, 0 + .dw 0x29c0, 0xc11e, 0x29ff, 0xc11e, 0x21, 0 + .dw 0x2a40, 0xc11e, 0x2a7f, 0xc11e, 0x21, 0 + .dw 0x2ac0, 0xc11e, 0x2aff, 0xc11e, 0x21, 0 + .dw 0x2b40, 0xc11e, 0x2b7f, 0xc11e, 0x21, 0 + .dw 0x2bc0, 0xc11e, 0x2bff, 0xc11e, 0x21, 0 + .dw 0x2c40, 0xc11e, 0x2c7f, 0xc11e, 0x21, 0 + .dw 0x2cc0, 0xc11e, 0x2cff, 0xc11e, 0x21, 0 + .dw 0x2d40, 0xc11e, 0x2d7f, 0xc11e, 0x21, 0 + .dw 0x2dc0, 0xc11e, 0x2dff, 0xc11e, 0x21, 0 + .dw 0x2e40, 0xc11e, 0x2e7f, 0xc11e, 0x21, 0 + .dw 0x2ec0, 0xc11e, 0x2eff, 0xc11e, 0x21, 0 + .dw 0x2f40, 0xc11e, 0x2f7f, 0xc11e, 0x21, 0 + .dw 0x2fc0, 0xc11e, 0x2fff, 0xc11e, 0x21, 0 + .dw 0x3040, 0xc11e, 0x307f, 0xc11e, 0x21, 0 + .dw 0x30c0, 0xc11e, 0x30ff, 0xc11e, 0x21, 0 + .dw 0x3140, 0xc11e, 0x317f, 0xc11e, 0x21, 0 + .dw 0x31c0, 0xc11e, 0x31ff, 0xc11e, 0x21, 0 + .dw 0x3240, 0xc11e, 0x327f, 0xc11e, 0x21, 0 + .dw 0x32c0, 0xc11e, 0x32ff, 0xc11e, 0x21, 0 + .dw 0x3340, 0xc11e, 0x337f, 0xc11e, 0x21, 0 + .dw 0x33c0, 0xc11e, 0x33ff, 0xc11e, 0x21, 0 + .dw 0x3440, 0xc11e, 0x347f, 0xc11e, 0x21, 0 + .dw 0x34c0, 0xc11e, 0x34ff, 0xc11e, 0x21, 0 + .dw 0x3540, 0xc11e, 0x357f, 0xc11e, 0x21, 0 + .dw 0x35c0, 0xc11e, 0x35ff, 0xc11e, 0x21, 0 + .dw 0x3640, 0xc11e, 0x367f, 0xc11e, 0x21, 0 + .dw 0x36c0, 0xc11e, 0x36ff, 0xc11e, 0x21, 0 + .dw 0x3740, 0xc11e, 0x377f, 0xc11e, 0x21, 0 + .dw 0x37c0, 0xc11e, 0x37ff, 0xc11e, 0x21, 0 + .dw 0x3840, 0xc11e, 0x387f, 0xc11e, 0x21, 0 + .dw 0x38c0, 0xc11e, 0x38ff, 0xc11e, 0x21, 0 + .dw 0x3940, 0xc11e, 0x397f, 0xc11e, 0x21, 0 + .dw 0x39c0, 0xc11e, 0x3fff, 0xc11e, 0x21, 0 + .dw 0x4040, 0xc11e, 0x407f, 0xc11e, 0x21, 0 + .dw 0x40c0, 0xc11e, 0x40ff, 0xc11e, 0x21, 0 + .dw 0x4140, 0xc11e, 0x417f, 0xc11e, 0x21, 0 + .dw 0x41c0, 0xc11e, 0x41ff, 0xc11e, 0x21, 0 + .dw 0x4240, 0xc11e, 0x427f, 0xc11e, 0x21, 0 + .dw 0x42c0, 0xc11e, 0x42ff, 0xc11e, 0x21, 0 + .dw 0x4340, 0xc11e, 0x437f, 0xc11e, 0x21, 0 + .dw 0x43c0, 0xc11e, 0x43ff, 0xc11e, 0x21, 0 + .dw 0x4440, 0xc11e, 0x447f, 0xc11e, 0x21, 0 + .dw 0x44c0, 0xc11e, 0x44ff, 0xc11e, 0x21, 0 + .dw 0x4540, 0xc11e, 0x457f, 0xc11e, 0x21, 0 + .dw 0x45c0, 0xc11e, 0x45ff, 0xc11e, 0x21, 0 + .dw 0x4640, 0xc11e, 0x467f, 0xc11e, 0x21, 0 + .dw 0x46c0, 0xc11e, 0x46ff, 0xc11e, 0x21, 0 + .dw 0x4740, 0xc11e, 0x477f, 0xc11e, 0x21, 0 + .dw 0x47c0, 0xc11e, 0x47ff, 0xc11e, 0x21, 0 + .dw 0x4840, 0xc11e, 0x487f, 0xc11e, 0x21, 0 + .dw 0x48c0, 0xc11e, 0x48ff, 0xc11e, 0x21, 0 + .dw 0x4940, 0xc11e, 0x497f, 0xc11e, 0x21, 0 + .dw 0x49c0, 0xc11e, 0x49ff, 0xc11e, 0x21, 0 + .dw 0x4a40, 0xc11e, 0x4a7f, 0xc11e, 0x21, 0 + .dw 0x4ac0, 0xc11e, 0x4aff, 0xc11e, 0x21, 0 + .dw 0x4b40, 0xc11e, 0x4b7f, 0xc11e, 0x21, 0 + .dw 0x4bc0, 0xc11e, 0x4bff, 0xc11e, 0x21, 0 + .dw 0x4c40, 0xc11e, 0x4c7f, 0xc11e, 0x21, 0 + .dw 0x4cc0, 0xc11e, 0x4cff, 0xc11e, 0x21, 0 + .dw 0x4d40, 0xc11e, 0x4d7f, 0xc11e, 0x21, 0 + .dw 0x4dc0, 0xc11e, 0x4dff, 0xc11e, 0x21, 0 + .dw 0x4e40, 0xc11e, 0x4e7f, 0xc11e, 0x21, 0 + .dw 0x4ec0, 0xc11e, 0x4eff, 0xc11e, 0x21, 0 + .dw 0x4f40, 0xc11e, 0x4f7f, 0xc11e, 0x21, 0 + .dw 0x4fc0, 0xc11e, 0x4fff, 0xc11e, 0x21, 0 + .dw 0x5040, 0xc11e, 0x507f, 0xc11e, 0x21, 0 + .dw 0x50c0, 0xc11e, 0x50ff, 0xc11e, 0x21, 0 + .dw 0x5140, 0xc11e, 0x517f, 0xc11e, 0x21, 0 + .dw 0x51c0, 0xc11e, 0x51ff, 0xc11e, 0x21, 0 + .dw 0x5240, 0xc11e, 0x527f, 0xc11e, 0x21, 0 + .dw 0x52c0, 0xc11e, 0x52ff, 0xc11e, 0x21, 0 + .dw 0x5340, 0xc11e, 0x537f, 0xc11e, 0x21, 0 + .dw 0x53c0, 0xc11e, 0x53ff, 0xc11e, 0x21, 0 + .dw 0x5440, 0xc11e, 0x547f, 0xc11e, 0x21, 0 + .dw 0x54c0, 0xc11e, 0x54ff, 0xc11e, 0x21, 0 + .dw 0x5540, 0xc11e, 0x557f, 0xc11e, 0x21, 0 + .dw 0x55c0, 0xc11e, 0x55ff, 0xc11e, 0x21, 0 + .dw 0x5640, 0xc11e, 0x567f, 0xc11e, 0x21, 0 + .dw 0x56c0, 0xc11e, 0x56ff, 0xc11e, 0x21, 0 + .dw 0x5740, 0xc11e, 0x577f, 0xc11e, 0x21, 0 + .dw 0x57c0, 0xc11e, 0x57ff, 0xc11e, 0x21, 0 + .dw 0x5840, 0xc11e, 0x587f, 0xc11e, 0x21, 0 + .dw 0x58c0, 0xc11e, 0x58ff, 0xc11e, 0x21, 0 + .dw 0x5940, 0xc11e, 0x597f, 0xc11e, 0x21, 0 + .dw 0x59c0, 0xc11e, 0x5fff, 0xc11e, 0x21, 0 + .dw 0x6040, 0xc11e, 0x607f, 0xc11e, 0x21, 0 + .dw 0x60c0, 0xc11e, 0x60ff, 0xc11e, 0x21, 0 + .dw 0x6140, 0xc11e, 0x617f, 0xc11e, 0x21, 0 + .dw 0x61c0, 0xc11e, 0x61ff, 0xc11e, 0x21, 0 + .dw 0x6240, 0xc11e, 0x627f, 0xc11e, 0x21, 0 + .dw 0x62c0, 0xc11e, 0x62ff, 0xc11e, 0x21, 0 + .dw 0x6340, 0xc11e, 0x637f, 0xc11e, 0x21, 0 + .dw 0x63c0, 0xc11e, 0x63ff, 0xc11e, 0x21, 0 + .dw 0x6440, 0xc11e, 0x647f, 0xc11e, 0x21, 0 + .dw 0x64c0, 0xc11e, 0x64ff, 0xc11e, 0x21, 0 + .dw 0x6540, 0xc11e, 0x657f, 0xc11e, 0x21, 0 + .dw 0x65c0, 0xc11e, 0x65ff, 0xc11e, 0x21, 0 + .dw 0x6640, 0xc11e, 0x667f, 0xc11e, 0x21, 0 + .dw 0x66c0, 0xc11e, 0x66ff, 0xc11e, 0x21, 0 + .dw 0x6740, 0xc11e, 0x677f, 0xc11e, 0x21, 0 + .dw 0x67c0, 0xc11e, 0x67ff, 0xc11e, 0x21, 0 + .dw 0x6840, 0xc11e, 0x687f, 0xc11e, 0x21, 0 + .dw 0x68c0, 0xc11e, 0x68ff, 0xc11e, 0x21, 0 + .dw 0x6940, 0xc11e, 0x697f, 0xc11e, 0x21, 0 + .dw 0x69c0, 0xc11e, 0x69ff, 0xc11e, 0x21, 0 + .dw 0x6a40, 0xc11e, 0x6a7f, 0xc11e, 0x21, 0 + .dw 0x6ac0, 0xc11e, 0x6aff, 0xc11e, 0x21, 0 + .dw 0x6b40, 0xc11e, 0x6b7f, 0xc11e, 0x21, 0 + .dw 0x6bc0, 0xc11e, 0x6bff, 0xc11e, 0x21, 0 + .dw 0x6c40, 0xc11e, 0x6c7f, 0xc11e, 0x21, 0 + .dw 0x6cc0, 0xc11e, 0x6cff, 0xc11e, 0x21, 0 + .dw 0x6d40, 0xc11e, 0x6d7f, 0xc11e, 0x21, 0 + .dw 0x6dc0, 0xc11e, 0x6dff, 0xc11e, 0x21, 0 + .dw 0x6e40, 0xc11e, 0x6e7f, 0xc11e, 0x21, 0 + .dw 0x6ec0, 0xc11e, 0x6eff, 0xc11e, 0x21, 0 + .dw 0x6f40, 0xc11e, 0x6f7f, 0xc11e, 0x21, 0 + .dw 0x6fc0, 0xc11e, 0x6fff, 0xc11e, 0x21, 0 + .dw 0x7040, 0xc11e, 0x707f, 0xc11e, 0x21, 0 + .dw 0x70c0, 0xc11e, 0x70ff, 0xc11e, 0x21, 0 + .dw 0x7140, 0xc11e, 0x717f, 0xc11e, 0x21, 0 + .dw 0x71c0, 0xc11e, 0x71ff, 0xc11e, 0x21, 0 + .dw 0x7240, 0xc11e, 0x727f, 0xc11e, 0x21, 0 + .dw 0x72c0, 0xc11e, 0x72ff, 0xc11e, 0x21, 0 + .dw 0x7340, 0xc11e, 0x737f, 0xc11e, 0x21, 0 + .dw 0x73c0, 0xc11e, 0x73ff, 0xc11e, 0x21, 0 + .dw 0x7440, 0xc11e, 0x747f, 0xc11e, 0x21, 0 + .dw 0x74c0, 0xc11e, 0x74ff, 0xc11e, 0x21, 0 + .dw 0x7540, 0xc11e, 0x757f, 0xc11e, 0x21, 0 + .dw 0x75c0, 0xc11e, 0x75ff, 0xc11e, 0x21, 0 + .dw 0x7640, 0xc11e, 0x767f, 0xc11e, 0x21, 0 + .dw 0x76c0, 0xc11e, 0x76ff, 0xc11e, 0x21, 0 + .dw 0x7740, 0xc11e, 0x777f, 0xc11e, 0x21, 0 + .dw 0x77c0, 0xc11e, 0x77ff, 0xc11e, 0x21, 0 + .dw 0x7840, 0xc11e, 0x787f, 0xc11e, 0x21, 0 + .dw 0x78c0, 0xc11e, 0x78ff, 0xc11e, 0x21, 0 + .dw 0x7940, 0xc11e, 0x797f, 0xc11e, 0x21, 0 + .dw 0x79c0, 0xc11e, 0x7fff, 0xc11e, 0x21, 0 + .dw 0x8040, 0xc11e, 0x807f, 0xc11e, 0x21, 0 + .dw 0x80c0, 0xc11e, 0x80ff, 0xc11e, 0x21, 0 + .dw 0x8140, 0xc11e, 0x817f, 0xc11e, 0x21, 0 + .dw 0x81c0, 0xc11e, 0x81ff, 0xc11e, 0x21, 0 + .dw 0x8240, 0xc11e, 0x827f, 0xc11e, 0x21, 0 + .dw 0x82c0, 0xc11e, 0x82ff, 0xc11e, 0x21, 0 + .dw 0x8340, 0xc11e, 0x837f, 0xc11e, 0x21, 0 + .dw 0x83c0, 0xc11e, 0x83ff, 0xc11e, 0x21, 0 + .dw 0x8440, 0xc11e, 0x847f, 0xc11e, 0x21, 0 + .dw 0x84c0, 0xc11e, 0x84ff, 0xc11e, 0x21, 0 + .dw 0x8540, 0xc11e, 0x857f, 0xc11e, 0x21, 0 + .dw 0x85c0, 0xc11e, 0x85ff, 0xc11e, 0x21, 0 + .dw 0x8640, 0xc11e, 0x867f, 0xc11e, 0x21, 0 + .dw 0x86c0, 0xc11e, 0x86ff, 0xc11e, 0x21, 0 + .dw 0x8740, 0xc11e, 0x877f, 0xc11e, 0x21, 0 + .dw 0x87c0, 0xc11e, 0x87ff, 0xc11e, 0x21, 0 + .dw 0x8840, 0xc11e, 0x887f, 0xc11e, 0x21, 0 + .dw 0x88c0, 0xc11e, 0x88ff, 0xc11e, 0x21, 0 + .dw 0x8940, 0xc11e, 0x897f, 0xc11e, 0x21, 0 + .dw 0x89c0, 0xc11e, 0x89ff, 0xc11e, 0x21, 0 + .dw 0x8a40, 0xc11e, 0x8a7f, 0xc11e, 0x21, 0 + .dw 0x8ac0, 0xc11e, 0x8aff, 0xc11e, 0x21, 0 + .dw 0x8b40, 0xc11e, 0x8b7f, 0xc11e, 0x21, 0 + .dw 0x8bc0, 0xc11e, 0x8bff, 0xc11e, 0x21, 0 + .dw 0x8c40, 0xc11e, 0x8c7f, 0xc11e, 0x21, 0 + .dw 0x8cc0, 0xc11e, 0x8cff, 0xc11e, 0x21, 0 + .dw 0x8d40, 0xc11e, 0x8d7f, 0xc11e, 0x21, 0 + .dw 0x8dc0, 0xc11e, 0x8dff, 0xc11e, 0x21, 0 + .dw 0x8e40, 0xc11e, 0x8e7f, 0xc11e, 0x21, 0 + .dw 0x8ec0, 0xc11e, 0x8eff, 0xc11e, 0x21, 0 + .dw 0x8f40, 0xc11e, 0x8f7f, 0xc11e, 0x21, 0 + .dw 0x8fc0, 0xc11e, 0x8fff, 0xc11e, 0x21, 0 + .dw 0x9040, 0xc11e, 0x907f, 0xc11e, 0x21, 0 + .dw 0x90c0, 0xc11e, 0x90ff, 0xc11e, 0x21, 0 + .dw 0x9140, 0xc11e, 0x917f, 0xc11e, 0x21, 0 + .dw 0x91c0, 0xc11e, 0x91ff, 0xc11e, 0x21, 0 + .dw 0x9240, 0xc11e, 0x927f, 0xc11e, 0x21, 0 + .dw 0x92c0, 0xc11e, 0x92ff, 0xc11e, 0x21, 0 + .dw 0x9340, 0xc11e, 0x937f, 0xc11e, 0x21, 0 + .dw 0x93c0, 0xc11e, 0x93ff, 0xc11e, 0x21, 0 + .dw 0x9440, 0xc11e, 0x947f, 0xc11e, 0x21, 0 + .dw 0x94c0, 0xc11e, 0x94ff, 0xc11e, 0x21, 0 + .dw 0x9540, 0xc11e, 0x957f, 0xc11e, 0x21, 0 + .dw 0x95c0, 0xc11e, 0x95ff, 0xc11e, 0x21, 0 + .dw 0x9640, 0xc11e, 0x967f, 0xc11e, 0x21, 0 + .dw 0x96c0, 0xc11e, 0x96ff, 0xc11e, 0x21, 0 + .dw 0x9740, 0xc11e, 0x977f, 0xc11e, 0x21, 0 + .dw 0x97c0, 0xc11e, 0x97ff, 0xc11e, 0x21, 0 + .dw 0x9840, 0xc11e, 0x987f, 0xc11e, 0x21, 0 + .dw 0x98c0, 0xc11e, 0x98ff, 0xc11e, 0x21, 0 + .dw 0x9940, 0xc11e, 0x997f, 0xc11e, 0x21, 0 + .dw 0x99c0, 0xc11e, 0x9fff, 0xc11e, 0x21, 0 + .dw 0xa040, 0xc11e, 0xa07f, 0xc11e, 0x21, 0 + .dw 0xa0c0, 0xc11e, 0xa0ff, 0xc11e, 0x21, 0 + .dw 0xa140, 0xc11e, 0xa17f, 0xc11e, 0x21, 0 + .dw 0xa1c0, 0xc11e, 0xa1ff, 0xc11e, 0x21, 0 + .dw 0xa240, 0xc11e, 0xa27f, 0xc11e, 0x21, 0 + .dw 0xa2c0, 0xc11e, 0xa2ff, 0xc11e, 0x21, 0 + .dw 0xa340, 0xc11e, 0xa37f, 0xc11e, 0x21, 0 + .dw 0xa3c0, 0xc11e, 0xa3ff, 0xc11e, 0x21, 0 + .dw 0xa440, 0xc11e, 0xa47f, 0xc11e, 0x21, 0 + .dw 0xa4c0, 0xc11e, 0xa4ff, 0xc11e, 0x21, 0 + .dw 0xa540, 0xc11e, 0xa57f, 0xc11e, 0x21, 0 + .dw 0xa5c0, 0xc11e, 0xa5ff, 0xc11e, 0x21, 0 + .dw 0xa640, 0xc11e, 0xa67f, 0xc11e, 0x21, 0 + .dw 0xa6c0, 0xc11e, 0xa6ff, 0xc11e, 0x21, 0 + .dw 0xa740, 0xc11e, 0xa77f, 0xc11e, 0x21, 0 + .dw 0xa7c0, 0xc11e, 0xa7ff, 0xc11e, 0x21, 0 + .dw 0xa840, 0xc11e, 0xa87f, 0xc11e, 0x21, 0 + .dw 0xa8c0, 0xc11e, 0xa8ff, 0xc11e, 0x21, 0 + .dw 0xa940, 0xc11e, 0xa97f, 0xc11e, 0x21, 0 + .dw 0xa9c0, 0xc11e, 0xa9ff, 0xc11e, 0x21, 0 + .dw 0xaa40, 0xc11e, 0xaa7f, 0xc11e, 0x21, 0 + .dw 0xaac0, 0xc11e, 0xaaff, 0xc11e, 0x21, 0 + .dw 0xab40, 0xc11e, 0xab7f, 0xc11e, 0x21, 0 + .dw 0xabc0, 0xc11e, 0xabff, 0xc11e, 0x21, 0 + .dw 0xac40, 0xc11e, 0xac7f, 0xc11e, 0x21, 0 + .dw 0xacc0, 0xc11e, 0xacff, 0xc11e, 0x21, 0 + .dw 0xad40, 0xc11e, 0xad7f, 0xc11e, 0x21, 0 + .dw 0xadc0, 0xc11e, 0xadff, 0xc11e, 0x21, 0 + .dw 0xae40, 0xc11e, 0xae7f, 0xc11e, 0x21, 0 + .dw 0xaec0, 0xc11e, 0xaeff, 0xc11e, 0x21, 0 + .dw 0xaf40, 0xc11e, 0xaf7f, 0xc11e, 0x21, 0 + .dw 0xafc0, 0xc11e, 0xafff, 0xc11e, 0x21, 0 + .dw 0xb040, 0xc11e, 0xb07f, 0xc11e, 0x21, 0 + .dw 0xb0c0, 0xc11e, 0xb0ff, 0xc11e, 0x21, 0 + .dw 0xb140, 0xc11e, 0xb17f, 0xc11e, 0x21, 0 + .dw 0xb1c0, 0xc11e, 0xb1ff, 0xc11e, 0x21, 0 + .dw 0xb240, 0xc11e, 0xb27f, 0xc11e, 0x21, 0 + .dw 0xb2c0, 0xc11e, 0xb2ff, 0xc11e, 0x21, 0 + .dw 0xb340, 0xc11e, 0xb37f, 0xc11e, 0x21, 0 + .dw 0xb3c0, 0xc11e, 0xb3ff, 0xc11e, 0x21, 0 + .dw 0xb440, 0xc11e, 0xb47f, 0xc11e, 0x21, 0 + .dw 0xb4c0, 0xc11e, 0xb4ff, 0xc11e, 0x21, 0 + .dw 0xb540, 0xc11e, 0xb57f, 0xc11e, 0x21, 0 + .dw 0xb5c0, 0xc11e, 0xb5ff, 0xc11e, 0x21, 0 + .dw 0xb640, 0xc11e, 0xb67f, 0xc11e, 0x21, 0 + .dw 0xb6c0, 0xc11e, 0xb6ff, 0xc11e, 0x21, 0 + .dw 0xb740, 0xc11e, 0xb77f, 0xc11e, 0x21, 0 + .dw 0xb7c0, 0xc11e, 0xb7ff, 0xc11e, 0x21, 0 + .dw 0xb840, 0xc11e, 0xb87f, 0xc11e, 0x21, 0 + .dw 0xb8c0, 0xc11e, 0xb8ff, 0xc11e, 0x21, 0 + .dw 0xb940, 0xc11e, 0xb97f, 0xc11e, 0x21, 0 + .dw 0xb9c0, 0xc11e, 0xbfff, 0xc11e, 0x21, 0 + .dw 0xc040, 0xc11e, 0xc07f, 0xc11e, 0x21, 0 + .dw 0xc0c0, 0xc11e, 0xc0ff, 0xc11e, 0x21, 0 + .dw 0xc140, 0xc11e, 0xc17f, 0xc11e, 0x21, 0 + .dw 0xc1c0, 0xc11e, 0xc1ff, 0xc11e, 0x21, 0 + .dw 0xc240, 0xc11e, 0xc27f, 0xc11e, 0x21, 0 + .dw 0xc2c0, 0xc11e, 0xc2ff, 0xc11e, 0x21, 0 + .dw 0xc340, 0xc11e, 0xc37f, 0xc11e, 0x21, 0 + .dw 0xc3c0, 0xc11e, 0xc3ff, 0xc11e, 0x21, 0 + .dw 0xc440, 0xc11e, 0xc47f, 0xc11e, 0x21, 0 + .dw 0xc4c0, 0xc11e, 0xc4ff, 0xc11e, 0x21, 0 + .dw 0xc540, 0xc11e, 0xc57f, 0xc11e, 0x21, 0 + .dw 0xc5c0, 0xc11e, 0xc5ff, 0xc11e, 0x21, 0 + .dw 0xc640, 0xc11e, 0xc67f, 0xc11e, 0x21, 0 + .dw 0xc6c0, 0xc11e, 0xc6ff, 0xc11e, 0x21, 0 + .dw 0xc740, 0xc11e, 0xc77f, 0xc11e, 0x21, 0 + .dw 0xc7c0, 0xc11e, 0xc7ff, 0xc11e, 0x21, 0 + .dw 0xc840, 0xc11e, 0xc87f, 0xc11e, 0x21, 0 + .dw 0xc8c0, 0xc11e, 0xc8ff, 0xc11e, 0x21, 0 + .dw 0xc940, 0xc11e, 0xc97f, 0xc11e, 0x21, 0 + .dw 0xc9c0, 0xc11e, 0xc9ff, 0xc11e, 0x21, 0 + .dw 0xca40, 0xc11e, 0xca7f, 0xc11e, 0x21, 0 + .dw 0xcac0, 0xc11e, 0xcaff, 0xc11e, 0x21, 0 + .dw 0xcb40, 0xc11e, 0xcb7f, 0xc11e, 0x21, 0 + .dw 0xcbc0, 0xc11e, 0xcbff, 0xc11e, 0x21, 0 + .dw 0xcc40, 0xc11e, 0xcc7f, 0xc11e, 0x21, 0 + .dw 0xccc0, 0xc11e, 0xccff, 0xc11e, 0x21, 0 + .dw 0xcd40, 0xc11e, 0xcd7f, 0xc11e, 0x21, 0 + .dw 0xcdc0, 0xc11e, 0xcdff, 0xc11e, 0x21, 0 + .dw 0xce40, 0xc11e, 0xce7f, 0xc11e, 0x21, 0 + .dw 0xcec0, 0xc11e, 0xceff, 0xc11e, 0x21, 0 + .dw 0xcf40, 0xc11e, 0xcf7f, 0xc11e, 0x21, 0 + .dw 0xcfc0, 0xc11e, 0xcfff, 0xc11e, 0x21, 0 + .dw 0xd040, 0xc11e, 0xd07f, 0xc11e, 0x21, 0 + .dw 0xd0c0, 0xc11e, 0xd0ff, 0xc11e, 0x21, 0 + .dw 0xd140, 0xc11e, 0xd17f, 0xc11e, 0x21, 0 + .dw 0xd1c0, 0xc11e, 0xd1ff, 0xc11e, 0x21, 0 + .dw 0xd240, 0xc11e, 0xd27f, 0xc11e, 0x21, 0 + .dw 0xd2c0, 0xc11e, 0xd2ff, 0xc11e, 0x21, 0 + .dw 0xd340, 0xc11e, 0xd37f, 0xc11e, 0x21, 0 + .dw 0xd3c0, 0xc11e, 0xd3ff, 0xc11e, 0x21, 0 + .dw 0xd440, 0xc11e, 0xd47f, 0xc11e, 0x21, 0 + .dw 0xd4c0, 0xc11e, 0xd4ff, 0xc11e, 0x21, 0 + .dw 0xd540, 0xc11e, 0xd57f, 0xc11e, 0x21, 0 + .dw 0xd5c0, 0xc11e, 0xd5ff, 0xc11e, 0x21, 0 + .dw 0xd640, 0xc11e, 0xd67f, 0xc11e, 0x21, 0 + .dw 0xd6c0, 0xc11e, 0xd6ff, 0xc11e, 0x21, 0 + .dw 0xd740, 0xc11e, 0xd77f, 0xc11e, 0x21, 0 + .dw 0xd7c0, 0xc11e, 0xd7ff, 0xc11e, 0x21, 0 + .dw 0xd840, 0xc11e, 0xd87f, 0xc11e, 0x21, 0 + .dw 0xd8c0, 0xc11e, 0xd8ff, 0xc11e, 0x21, 0 + .dw 0xd940, 0xc11e, 0xd97f, 0xc11e, 0x21, 0 + .dw 0xd9c0, 0xc11e, 0xdfff, 0xc11e, 0x21, 0 + .dw 0xe040, 0xc11e, 0xe07f, 0xc11e, 0x21, 0 + .dw 0xe0c0, 0xc11e, 0xe0ff, 0xc11e, 0x21, 0 + .dw 0xe140, 0xc11e, 0xe17f, 0xc11e, 0x21, 0 + .dw 0xe1c0, 0xc11e, 0xe1ff, 0xc11e, 0x21, 0 + .dw 0xe240, 0xc11e, 0xe27f, 0xc11e, 0x21, 0 + .dw 0xe2c0, 0xc11e, 0xe2ff, 0xc11e, 0x21, 0 + .dw 0xe340, 0xc11e, 0xe37f, 0xc11e, 0x21, 0 + .dw 0xe3c0, 0xc11e, 0xe3ff, 0xc11e, 0x21, 0 + .dw 0xe440, 0xc11e, 0xe47f, 0xc11e, 0x21, 0 + .dw 0xe4c0, 0xc11e, 0xe4ff, 0xc11e, 0x21, 0 + .dw 0xe540, 0xc11e, 0xe57f, 0xc11e, 0x21, 0 + .dw 0xe5c0, 0xc11e, 0xe5ff, 0xc11e, 0x21, 0 + .dw 0xe640, 0xc11e, 0xe67f, 0xc11e, 0x21, 0 + .dw 0xe6c0, 0xc11e, 0xe6ff, 0xc11e, 0x21, 0 + .dw 0xe740, 0xc11e, 0xe77f, 0xc11e, 0x21, 0 + .dw 0xe7c0, 0xc11e, 0xe7ff, 0xc11e, 0x21, 0 + .dw 0xe840, 0xc11e, 0xe87f, 0xc11e, 0x21, 0 + .dw 0xe8c0, 0xc11e, 0xe8ff, 0xc11e, 0x21, 0 + .dw 0xe940, 0xc11e, 0xe97f, 0xc11e, 0x21, 0 + .dw 0xe9c0, 0xc11e, 0xe9ff, 0xc11e, 0x21, 0 + .dw 0xea40, 0xc11e, 0xea7f, 0xc11e, 0x21, 0 + .dw 0xeac0, 0xc11e, 0xeaff, 0xc11e, 0x21, 0 + .dw 0xeb40, 0xc11e, 0xeb7f, 0xc11e, 0x21, 0 + .dw 0xebc0, 0xc11e, 0xebff, 0xc11e, 0x21, 0 + .dw 0xec40, 0xc11e, 0xec7f, 0xc11e, 0x21, 0 + .dw 0xecc0, 0xc11e, 0xecff, 0xc11e, 0x21, 0 + .dw 0xed40, 0xc11e, 0xed7f, 0xc11e, 0x21, 0 + .dw 0xedc0, 0xc11e, 0xedff, 0xc11e, 0x21, 0 + .dw 0xee40, 0xc11e, 0xee7f, 0xc11e, 0x21, 0 + .dw 0xeec0, 0xc11e, 0xeeff, 0xc11e, 0x21, 0 + .dw 0xef40, 0xc11e, 0xef7f, 0xc11e, 0x21, 0 + .dw 0xefc0, 0xc11e, 0xefff, 0xc11e, 0x21, 0 + .dw 0xf040, 0xc11e, 0xf07f, 0xc11e, 0x21, 0 + .dw 0xf0c0, 0xc11e, 0xf0ff, 0xc11e, 0x21, 0 + .dw 0xf140, 0xc11e, 0xf17f, 0xc11e, 0x21, 0 + .dw 0xf1c0, 0xc11e, 0xf1ff, 0xc11e, 0x21, 0 + .dw 0xf240, 0xc11e, 0xf27f, 0xc11e, 0x21, 0 + .dw 0xf2c0, 0xc11e, 0xf2ff, 0xc11e, 0x21, 0 + .dw 0xf340, 0xc11e, 0xf37f, 0xc11e, 0x21, 0 + .dw 0xf3c0, 0xc11e, 0xf3ff, 0xc11e, 0x21, 0 + .dw 0xf440, 0xc11e, 0xf47f, 0xc11e, 0x21, 0 + .dw 0xf4c0, 0xc11e, 0xf4ff, 0xc11e, 0x21, 0 + .dw 0xf540, 0xc11e, 0xf57f, 0xc11e, 0x21, 0 + .dw 0xf5c0, 0xc11e, 0xf5ff, 0xc11e, 0x21, 0 + .dw 0xf640, 0xc11e, 0xf67f, 0xc11e, 0x21, 0 + .dw 0xf6c0, 0xc11e, 0xf6ff, 0xc11e, 0x21, 0 + .dw 0xf740, 0xc11e, 0xf77f, 0xc11e, 0x21, 0 + .dw 0xf7c0, 0xc11e, 0xf7ff, 0xc11e, 0x21, 0 + .dw 0xf840, 0xc11e, 0xf87f, 0xc11e, 0x21, 0 + .dw 0xf8c0, 0xc11e, 0xf8ff, 0xc11e, 0x21, 0 + .dw 0xf940, 0xc11e, 0xf97f, 0xc11e, 0x21, 0 + .dw 0xf9c0, 0xc11e, 0xffff, 0xc11e, 0x21, 0 + .dw 0x0040, 0xc11f, 0x007f, 0xc11f, 0x21, 0 + .dw 0x00c0, 0xc11f, 0x00ff, 0xc11f, 0x21, 0 + .dw 0x0140, 0xc11f, 0x017f, 0xc11f, 0x21, 0 + .dw 0x01c0, 0xc11f, 0x01ff, 0xc11f, 0x21, 0 + .dw 0x0240, 0xc11f, 0x027f, 0xc11f, 0x21, 0 + .dw 0x02c0, 0xc11f, 0x02ff, 0xc11f, 0x21, 0 + .dw 0x0340, 0xc11f, 0x037f, 0xc11f, 0x21, 0 + .dw 0x03c0, 0xc11f, 0x03ff, 0xc11f, 0x21, 0 + .dw 0x0440, 0xc11f, 0x047f, 0xc11f, 0x21, 0 + .dw 0x04c0, 0xc11f, 0x04ff, 0xc11f, 0x21, 0 + .dw 0x0540, 0xc11f, 0x057f, 0xc11f, 0x21, 0 + .dw 0x05c0, 0xc11f, 0x05ff, 0xc11f, 0x21, 0 + .dw 0x0640, 0xc11f, 0x067f, 0xc11f, 0x21, 0 + .dw 0x06c0, 0xc11f, 0x06ff, 0xc11f, 0x21, 0 + .dw 0x0740, 0xc11f, 0x077f, 0xc11f, 0x21, 0 + .dw 0x07c0, 0xc11f, 0x07ff, 0xc11f, 0x21, 0 + .dw 0x0840, 0xc11f, 0x087f, 0xc11f, 0x21, 0 + .dw 0x08c0, 0xc11f, 0x08ff, 0xc11f, 0x21, 0 + .dw 0x0940, 0xc11f, 0x097f, 0xc11f, 0x21, 0 + .dw 0x09c0, 0xc11f, 0x09ff, 0xc11f, 0x21, 0 + .dw 0x0a40, 0xc11f, 0x0a7f, 0xc11f, 0x21, 0 + .dw 0x0ac0, 0xc11f, 0x0aff, 0xc11f, 0x21, 0 + .dw 0x0b40, 0xc11f, 0x0b7f, 0xc11f, 0x21, 0 + .dw 0x0bc0, 0xc11f, 0x0bff, 0xc11f, 0x21, 0 + .dw 0x0c40, 0xc11f, 0x0c7f, 0xc11f, 0x21, 0 + .dw 0x0cc0, 0xc11f, 0x0cff, 0xc11f, 0x21, 0 + .dw 0x0d40, 0xc11f, 0x0d7f, 0xc11f, 0x21, 0 + .dw 0x0dc0, 0xc11f, 0x0dff, 0xc11f, 0x21, 0 + .dw 0x0e40, 0xc11f, 0x0e7f, 0xc11f, 0x21, 0 + .dw 0x0ec0, 0xc11f, 0x0eff, 0xc11f, 0x21, 0 + .dw 0x0f40, 0xc11f, 0x0f7f, 0xc11f, 0x21, 0 + .dw 0x0fc0, 0xc11f, 0x0fff, 0xc11f, 0x21, 0 + .dw 0x1040, 0xc11f, 0x107f, 0xc11f, 0x21, 0 + .dw 0x10c0, 0xc11f, 0x10ff, 0xc11f, 0x21, 0 + .dw 0x1140, 0xc11f, 0x117f, 0xc11f, 0x21, 0 + .dw 0x11c0, 0xc11f, 0x11ff, 0xc11f, 0x21, 0 + .dw 0x1240, 0xc11f, 0x127f, 0xc11f, 0x21, 0 + .dw 0x12c0, 0xc11f, 0x12ff, 0xc11f, 0x21, 0 + .dw 0x1340, 0xc11f, 0x137f, 0xc11f, 0x21, 0 + .dw 0x13c0, 0xc11f, 0x13ff, 0xc11f, 0x21, 0 + .dw 0x1440, 0xc11f, 0x147f, 0xc11f, 0x21, 0 + .dw 0x14c0, 0xc11f, 0x14ff, 0xc11f, 0x21, 0 + .dw 0x1540, 0xc11f, 0x157f, 0xc11f, 0x21, 0 + .dw 0x15c0, 0xc11f, 0x15ff, 0xc11f, 0x21, 0 + .dw 0x1640, 0xc11f, 0x167f, 0xc11f, 0x21, 0 + .dw 0x16c0, 0xc11f, 0x16ff, 0xc11f, 0x21, 0 + .dw 0x1740, 0xc11f, 0x177f, 0xc11f, 0x21, 0 + .dw 0x17c0, 0xc11f, 0x17ff, 0xc11f, 0x21, 0 + .dw 0x1840, 0xc11f, 0x187f, 0xc11f, 0x21, 0 + .dw 0x18c0, 0xc11f, 0x18ff, 0xc11f, 0x21, 0 + .dw 0x1940, 0xc11f, 0x197f, 0xc11f, 0x21, 0 + .dw 0x19c0, 0xc11f, 0x1fff, 0xc11f, 0x21, 0 + .dw 0x2040, 0xc11f, 0x207f, 0xc11f, 0x21, 0 + .dw 0x20c0, 0xc11f, 0x20ff, 0xc11f, 0x21, 0 + .dw 0x2140, 0xc11f, 0x217f, 0xc11f, 0x21, 0 + .dw 0x21c0, 0xc11f, 0x21ff, 0xc11f, 0x21, 0 + .dw 0x2240, 0xc11f, 0x227f, 0xc11f, 0x21, 0 + .dw 0x22c0, 0xc11f, 0x22ff, 0xc11f, 0x21, 0 + .dw 0x2340, 0xc11f, 0x237f, 0xc11f, 0x21, 0 + .dw 0x23c0, 0xc11f, 0x23ff, 0xc11f, 0x21, 0 + .dw 0x2440, 0xc11f, 0x247f, 0xc11f, 0x21, 0 + .dw 0x24c0, 0xc11f, 0x24ff, 0xc11f, 0x21, 0 + .dw 0x2540, 0xc11f, 0x257f, 0xc11f, 0x21, 0 + .dw 0x25c0, 0xc11f, 0x25ff, 0xc11f, 0x21, 0 + .dw 0x2640, 0xc11f, 0x267f, 0xc11f, 0x21, 0 + .dw 0x26c0, 0xc11f, 0x26ff, 0xc11f, 0x21, 0 + .dw 0x2740, 0xc11f, 0x277f, 0xc11f, 0x21, 0 + .dw 0x27c0, 0xc11f, 0x27ff, 0xc11f, 0x21, 0 + .dw 0x2840, 0xc11f, 0x287f, 0xc11f, 0x21, 0 + .dw 0x28c0, 0xc11f, 0x28ff, 0xc11f, 0x21, 0 + .dw 0x2940, 0xc11f, 0x297f, 0xc11f, 0x21, 0 + .dw 0x29c0, 0xc11f, 0x29ff, 0xc11f, 0x21, 0 + .dw 0x2a40, 0xc11f, 0x2a7f, 0xc11f, 0x21, 0 + .dw 0x2ac0, 0xc11f, 0x2aff, 0xc11f, 0x21, 0 + .dw 0x2b40, 0xc11f, 0x2b7f, 0xc11f, 0x21, 0 + .dw 0x2bc0, 0xc11f, 0x2bff, 0xc11f, 0x21, 0 + .dw 0x2c40, 0xc11f, 0x2c7f, 0xc11f, 0x21, 0 + .dw 0x2cc0, 0xc11f, 0x2cff, 0xc11f, 0x21, 0 + .dw 0x2d40, 0xc11f, 0x2d7f, 0xc11f, 0x21, 0 + .dw 0x2dc0, 0xc11f, 0x2dff, 0xc11f, 0x21, 0 + .dw 0x2e40, 0xc11f, 0x2e7f, 0xc11f, 0x21, 0 + .dw 0x2ec0, 0xc11f, 0x2eff, 0xc11f, 0x21, 0 + .dw 0x2f40, 0xc11f, 0x2f7f, 0xc11f, 0x21, 0 + .dw 0x2fc0, 0xc11f, 0x2fff, 0xc11f, 0x21, 0 + .dw 0x3040, 0xc11f, 0x307f, 0xc11f, 0x21, 0 + .dw 0x30c0, 0xc11f, 0x30ff, 0xc11f, 0x21, 0 + .dw 0x3140, 0xc11f, 0x317f, 0xc11f, 0x21, 0 + .dw 0x31c0, 0xc11f, 0x31ff, 0xc11f, 0x21, 0 + .dw 0x3240, 0xc11f, 0x327f, 0xc11f, 0x21, 0 + .dw 0x32c0, 0xc11f, 0x32ff, 0xc11f, 0x21, 0 + .dw 0x3340, 0xc11f, 0x337f, 0xc11f, 0x21, 0 + .dw 0x33c0, 0xc11f, 0x33ff, 0xc11f, 0x21, 0 + .dw 0x3440, 0xc11f, 0x347f, 0xc11f, 0x21, 0 + .dw 0x34c0, 0xc11f, 0x34ff, 0xc11f, 0x21, 0 + .dw 0x3540, 0xc11f, 0x357f, 0xc11f, 0x21, 0 + .dw 0x35c0, 0xc11f, 0x35ff, 0xc11f, 0x21, 0 + .dw 0x3640, 0xc11f, 0x367f, 0xc11f, 0x21, 0 + .dw 0x36c0, 0xc11f, 0x36ff, 0xc11f, 0x21, 0 + .dw 0x3740, 0xc11f, 0x377f, 0xc11f, 0x21, 0 + .dw 0x37c0, 0xc11f, 0x37ff, 0xc11f, 0x21, 0 + .dw 0x3840, 0xc11f, 0x387f, 0xc11f, 0x21, 0 + .dw 0x38c0, 0xc11f, 0x38ff, 0xc11f, 0x21, 0 + .dw 0x3940, 0xc11f, 0x397f, 0xc11f, 0x21, 0 + .dw 0x39c0, 0xc11f, 0x1fff, 0xc120, 0x21, 0 + .dw 0x3a00, 0xc120, 0x5fff, 0xc120, 0x21, 0 + .dw 0x7a00, 0xc120, 0x9fff, 0xc120, 0x21, 0 + .dw 0xba00, 0xc120, 0xdfff, 0xc120, 0x21, 0 + .dw 0xfa00, 0xc120, 0x1fff, 0xc121, 0x21, 0 + .dw 0x3a00, 0xc121, 0x5fff, 0xc121, 0x21, 0 + .dw 0x7a00, 0xc121, 0x9fff, 0xc121, 0x21, 0 + .dw 0xba00, 0xc121, 0xdfff, 0xc121, 0x21, 0 + .dw 0xfa00, 0xc121, 0x1fff, 0xc122, 0x21, 0 + .dw 0x3a00, 0xc122, 0x5fff, 0xc122, 0x21, 0 + .dw 0x7a00, 0xc122, 0x9fff, 0xc122, 0x21, 0 + .dw 0xba00, 0xc122, 0xdfff, 0xc122, 0x21, 0 + .dw 0xfa00, 0xc122, 0x1fff, 0xc123, 0x21, 0 + .dw 0x3a00, 0xc123, 0xffff, 0xc123, 0x21, 0 + .dw 0x1a00, 0xc124, 0x1fff, 0xc124, 0x21, 0 + .dw 0x3a00, 0xc124, 0x3fff, 0xc124, 0x21, 0 + .dw 0x5a00, 0xc124, 0x5fff, 0xc124, 0x21, 0 + .dw 0x7a00, 0xc124, 0x7fff, 0xc124, 0x21, 0 + .dw 0x9a00, 0xc124, 0x9fff, 0xc124, 0x21, 0 + .dw 0xba00, 0xc124, 0xbfff, 0xc124, 0x21, 0 + .dw 0xda00, 0xc124, 0xdfff, 0xc124, 0x21, 0 + .dw 0xfa00, 0xc124, 0xffff, 0xc124, 0x21, 0 + .dw 0x1a00, 0xc125, 0x1fff, 0xc125, 0x21, 0 + .dw 0x3a00, 0xc125, 0x3fff, 0xc125, 0x21, 0 + .dw 0x5a00, 0xc125, 0x5fff, 0xc125, 0x21, 0 + .dw 0x7a00, 0xc125, 0x7fff, 0xc125, 0x21, 0 + .dw 0x9a00, 0xc125, 0x9fff, 0xc125, 0x21, 0 + .dw 0xba00, 0xc125, 0xbfff, 0xc125, 0x21, 0 + .dw 0xda00, 0xc125, 0xdfff, 0xc125, 0x21, 0 + .dw 0xfa00, 0xc125, 0xffff, 0xc125, 0x21, 0 + .dw 0x1a00, 0xc126, 0x1fff, 0xc126, 0x21, 0 + .dw 0x3a00, 0xc126, 0x3fff, 0xc126, 0x21, 0 + .dw 0x5a00, 0xc126, 0x5fff, 0xc126, 0x21, 0 + .dw 0x7a00, 0xc126, 0x7fff, 0xc126, 0x21, 0 + .dw 0x9a00, 0xc126, 0x9fff, 0xc126, 0x21, 0 + .dw 0xba00, 0xc126, 0xbfff, 0xc126, 0x21, 0 + .dw 0xda00, 0xc126, 0xdfff, 0xc126, 0x21, 0 + .dw 0xfa00, 0xc126, 0xffff, 0xc126, 0x21, 0 + .dw 0x1a00, 0xc127, 0x1fff, 0xc127, 0x21, 0 + .dw 0x3a00, 0xc127, 0x1fff, 0xc128, 0x21, 0 + .dw 0x2040, 0xc128, 0x207f, 0xc128, 0x21, 0 + .dw 0x20c0, 0xc128, 0x20ff, 0xc128, 0x21, 0 + .dw 0x2140, 0xc128, 0x217f, 0xc128, 0x21, 0 + .dw 0x21c0, 0xc128, 0x21ff, 0xc128, 0x21, 0 + .dw 0x2240, 0xc128, 0x227f, 0xc128, 0x21, 0 + .dw 0x22c0, 0xc128, 0x22ff, 0xc128, 0x21, 0 + .dw 0x2340, 0xc128, 0x237f, 0xc128, 0x21, 0 + .dw 0x23c0, 0xc128, 0x23ff, 0xc128, 0x21, 0 + .dw 0x2440, 0xc128, 0x247f, 0xc128, 0x21, 0 + .dw 0x24c0, 0xc128, 0x24ff, 0xc128, 0x21, 0 + .dw 0x2540, 0xc128, 0x257f, 0xc128, 0x21, 0 + .dw 0x25c0, 0xc128, 0x25ff, 0xc128, 0x21, 0 + .dw 0x2640, 0xc128, 0x267f, 0xc128, 0x21, 0 + .dw 0x26c0, 0xc128, 0x26ff, 0xc128, 0x21, 0 + .dw 0x2740, 0xc128, 0x277f, 0xc128, 0x21, 0 + .dw 0x27c0, 0xc128, 0x27ff, 0xc128, 0x21, 0 + .dw 0x2840, 0xc128, 0x287f, 0xc128, 0x21, 0 + .dw 0x28c0, 0xc128, 0x28ff, 0xc128, 0x21, 0 + .dw 0x2940, 0xc128, 0x297f, 0xc128, 0x21, 0 + .dw 0x29c0, 0xc128, 0x29ff, 0xc128, 0x21, 0 + .dw 0x2a40, 0xc128, 0x2a7f, 0xc128, 0x21, 0 + .dw 0x2ac0, 0xc128, 0x2aff, 0xc128, 0x21, 0 + .dw 0x2b40, 0xc128, 0x2b7f, 0xc128, 0x21, 0 + .dw 0x2bc0, 0xc128, 0x2bff, 0xc128, 0x21, 0 + .dw 0x2c40, 0xc128, 0x2c7f, 0xc128, 0x21, 0 + .dw 0x2cc0, 0xc128, 0x2cff, 0xc128, 0x21, 0 + .dw 0x2d40, 0xc128, 0x2d7f, 0xc128, 0x21, 0 + .dw 0x2dc0, 0xc128, 0x2dff, 0xc128, 0x21, 0 + .dw 0x2e40, 0xc128, 0x2e7f, 0xc128, 0x21, 0 + .dw 0x2ec0, 0xc128, 0x2eff, 0xc128, 0x21, 0 + .dw 0x2f40, 0xc128, 0x2f7f, 0xc128, 0x21, 0 + .dw 0x2fc0, 0xc128, 0x2fff, 0xc128, 0x21, 0 + .dw 0x3040, 0xc128, 0x307f, 0xc128, 0x21, 0 + .dw 0x30c0, 0xc128, 0x30ff, 0xc128, 0x21, 0 + .dw 0x3140, 0xc128, 0x317f, 0xc128, 0x21, 0 + .dw 0x31c0, 0xc128, 0x31ff, 0xc128, 0x21, 0 + .dw 0x3240, 0xc128, 0x327f, 0xc128, 0x21, 0 + .dw 0x32c0, 0xc128, 0x32ff, 0xc128, 0x21, 0 + .dw 0x3340, 0xc128, 0x337f, 0xc128, 0x21, 0 + .dw 0x33c0, 0xc128, 0x33ff, 0xc128, 0x21, 0 + .dw 0x3440, 0xc128, 0x347f, 0xc128, 0x21, 0 + .dw 0x34c0, 0xc128, 0x34ff, 0xc128, 0x21, 0 + .dw 0x3540, 0xc128, 0x357f, 0xc128, 0x21, 0 + .dw 0x35c0, 0xc128, 0x35ff, 0xc128, 0x21, 0 + .dw 0x3640, 0xc128, 0x367f, 0xc128, 0x21, 0 + .dw 0x36c0, 0xc128, 0x36ff, 0xc128, 0x21, 0 + .dw 0x3740, 0xc128, 0x377f, 0xc128, 0x21, 0 + .dw 0x37c0, 0xc128, 0x37ff, 0xc128, 0x21, 0 + .dw 0x3840, 0xc128, 0x387f, 0xc128, 0x21, 0 + .dw 0x38c0, 0xc128, 0x38ff, 0xc128, 0x21, 0 + .dw 0x3940, 0xc128, 0x397f, 0xc128, 0x21, 0 + .dw 0x39c0, 0xc128, 0x5fff, 0xc128, 0x21, 0 + .dw 0x6040, 0xc128, 0x607f, 0xc128, 0x21, 0 + .dw 0x60c0, 0xc128, 0x60ff, 0xc128, 0x21, 0 + .dw 0x6140, 0xc128, 0x617f, 0xc128, 0x21, 0 + .dw 0x61c0, 0xc128, 0x61ff, 0xc128, 0x21, 0 + .dw 0x6240, 0xc128, 0x627f, 0xc128, 0x21, 0 + .dw 0x62c0, 0xc128, 0x62ff, 0xc128, 0x21, 0 + .dw 0x6340, 0xc128, 0x637f, 0xc128, 0x21, 0 + .dw 0x63c0, 0xc128, 0x63ff, 0xc128, 0x21, 0 + .dw 0x6440, 0xc128, 0x647f, 0xc128, 0x21, 0 + .dw 0x64c0, 0xc128, 0x64ff, 0xc128, 0x21, 0 + .dw 0x6540, 0xc128, 0x657f, 0xc128, 0x21, 0 + .dw 0x65c0, 0xc128, 0x65ff, 0xc128, 0x21, 0 + .dw 0x6640, 0xc128, 0x667f, 0xc128, 0x21, 0 + .dw 0x66c0, 0xc128, 0x66ff, 0xc128, 0x21, 0 + .dw 0x6740, 0xc128, 0x677f, 0xc128, 0x21, 0 + .dw 0x67c0, 0xc128, 0x67ff, 0xc128, 0x21, 0 + .dw 0x6840, 0xc128, 0x687f, 0xc128, 0x21, 0 + .dw 0x68c0, 0xc128, 0x68ff, 0xc128, 0x21, 0 + .dw 0x6940, 0xc128, 0x697f, 0xc128, 0x21, 0 + .dw 0x69c0, 0xc128, 0x69ff, 0xc128, 0x21, 0 + .dw 0x6a40, 0xc128, 0x6a7f, 0xc128, 0x21, 0 + .dw 0x6ac0, 0xc128, 0x6aff, 0xc128, 0x21, 0 + .dw 0x6b40, 0xc128, 0x6b7f, 0xc128, 0x21, 0 + .dw 0x6bc0, 0xc128, 0x6bff, 0xc128, 0x21, 0 + .dw 0x6c40, 0xc128, 0x6c7f, 0xc128, 0x21, 0 + .dw 0x6cc0, 0xc128, 0x6cff, 0xc128, 0x21, 0 + .dw 0x6d40, 0xc128, 0x6d7f, 0xc128, 0x21, 0 + .dw 0x6dc0, 0xc128, 0x6dff, 0xc128, 0x21, 0 + .dw 0x6e40, 0xc128, 0x6e7f, 0xc128, 0x21, 0 + .dw 0x6ec0, 0xc128, 0x6eff, 0xc128, 0x21, 0 + .dw 0x6f40, 0xc128, 0x6f7f, 0xc128, 0x21, 0 + .dw 0x6fc0, 0xc128, 0x6fff, 0xc128, 0x21, 0 + .dw 0x7040, 0xc128, 0x707f, 0xc128, 0x21, 0 + .dw 0x70c0, 0xc128, 0x70ff, 0xc128, 0x21, 0 + .dw 0x7140, 0xc128, 0x717f, 0xc128, 0x21, 0 + .dw 0x71c0, 0xc128, 0x71ff, 0xc128, 0x21, 0 + .dw 0x7240, 0xc128, 0x727f, 0xc128, 0x21, 0 + .dw 0x72c0, 0xc128, 0x72ff, 0xc128, 0x21, 0 + .dw 0x7340, 0xc128, 0x737f, 0xc128, 0x21, 0 + .dw 0x73c0, 0xc128, 0x73ff, 0xc128, 0x21, 0 + .dw 0x7440, 0xc128, 0x747f, 0xc128, 0x21, 0 + .dw 0x74c0, 0xc128, 0x74ff, 0xc128, 0x21, 0 + .dw 0x7540, 0xc128, 0x757f, 0xc128, 0x21, 0 + .dw 0x75c0, 0xc128, 0x75ff, 0xc128, 0x21, 0 + .dw 0x7640, 0xc128, 0x767f, 0xc128, 0x21, 0 + .dw 0x76c0, 0xc128, 0x76ff, 0xc128, 0x21, 0 + .dw 0x7740, 0xc128, 0x777f, 0xc128, 0x21, 0 + .dw 0x77c0, 0xc128, 0x77ff, 0xc128, 0x21, 0 + .dw 0x7840, 0xc128, 0x787f, 0xc128, 0x21, 0 + .dw 0x78c0, 0xc128, 0x78ff, 0xc128, 0x21, 0 + .dw 0x7940, 0xc128, 0x797f, 0xc128, 0x21, 0 + .dw 0x79c0, 0xc128, 0x9fff, 0xc128, 0x21, 0 + .dw 0xa040, 0xc128, 0xa07f, 0xc128, 0x21, 0 + .dw 0xa0c0, 0xc128, 0xa0ff, 0xc128, 0x21, 0 + .dw 0xa140, 0xc128, 0xa17f, 0xc128, 0x21, 0 + .dw 0xa1c0, 0xc128, 0xa1ff, 0xc128, 0x21, 0 + .dw 0xa240, 0xc128, 0xa27f, 0xc128, 0x21, 0 + .dw 0xa2c0, 0xc128, 0xa2ff, 0xc128, 0x21, 0 + .dw 0xa340, 0xc128, 0xa37f, 0xc128, 0x21, 0 + .dw 0xa3c0, 0xc128, 0xa3ff, 0xc128, 0x21, 0 + .dw 0xa440, 0xc128, 0xa47f, 0xc128, 0x21, 0 + .dw 0xa4c0, 0xc128, 0xa4ff, 0xc128, 0x21, 0 + .dw 0xa540, 0xc128, 0xa57f, 0xc128, 0x21, 0 + .dw 0xa5c0, 0xc128, 0xa5ff, 0xc128, 0x21, 0 + .dw 0xa640, 0xc128, 0xa67f, 0xc128, 0x21, 0 + .dw 0xa6c0, 0xc128, 0xa6ff, 0xc128, 0x21, 0 + .dw 0xa740, 0xc128, 0xa77f, 0xc128, 0x21, 0 + .dw 0xa7c0, 0xc128, 0xa7ff, 0xc128, 0x21, 0 + .dw 0xa840, 0xc128, 0xa87f, 0xc128, 0x21, 0 + .dw 0xa8c0, 0xc128, 0xa8ff, 0xc128, 0x21, 0 + .dw 0xa940, 0xc128, 0xa97f, 0xc128, 0x21, 0 + .dw 0xa9c0, 0xc128, 0xa9ff, 0xc128, 0x21, 0 + .dw 0xaa40, 0xc128, 0xaa7f, 0xc128, 0x21, 0 + .dw 0xaac0, 0xc128, 0xaaff, 0xc128, 0x21, 0 + .dw 0xab40, 0xc128, 0xab7f, 0xc128, 0x21, 0 + .dw 0xabc0, 0xc128, 0xabff, 0xc128, 0x21, 0 + .dw 0xac40, 0xc128, 0xac7f, 0xc128, 0x21, 0 + .dw 0xacc0, 0xc128, 0xacff, 0xc128, 0x21, 0 + .dw 0xad40, 0xc128, 0xad7f, 0xc128, 0x21, 0 + .dw 0xadc0, 0xc128, 0xadff, 0xc128, 0x21, 0 + .dw 0xae40, 0xc128, 0xae7f, 0xc128, 0x21, 0 + .dw 0xaec0, 0xc128, 0xaeff, 0xc128, 0x21, 0 + .dw 0xaf40, 0xc128, 0xaf7f, 0xc128, 0x21, 0 + .dw 0xafc0, 0xc128, 0xafff, 0xc128, 0x21, 0 + .dw 0xb040, 0xc128, 0xb07f, 0xc128, 0x21, 0 + .dw 0xb0c0, 0xc128, 0xb0ff, 0xc128, 0x21, 0 + .dw 0xb140, 0xc128, 0xb17f, 0xc128, 0x21, 0 + .dw 0xb1c0, 0xc128, 0xb1ff, 0xc128, 0x21, 0 + .dw 0xb240, 0xc128, 0xb27f, 0xc128, 0x21, 0 + .dw 0xb2c0, 0xc128, 0xb2ff, 0xc128, 0x21, 0 + .dw 0xb340, 0xc128, 0xb37f, 0xc128, 0x21, 0 + .dw 0xb3c0, 0xc128, 0xb3ff, 0xc128, 0x21, 0 + .dw 0xb440, 0xc128, 0xb47f, 0xc128, 0x21, 0 + .dw 0xb4c0, 0xc128, 0xb4ff, 0xc128, 0x21, 0 + .dw 0xb540, 0xc128, 0xb57f, 0xc128, 0x21, 0 + .dw 0xb5c0, 0xc128, 0xb5ff, 0xc128, 0x21, 0 + .dw 0xb640, 0xc128, 0xb67f, 0xc128, 0x21, 0 + .dw 0xb6c0, 0xc128, 0xb6ff, 0xc128, 0x21, 0 + .dw 0xb740, 0xc128, 0xb77f, 0xc128, 0x21, 0 + .dw 0xb7c0, 0xc128, 0xb7ff, 0xc128, 0x21, 0 + .dw 0xb840, 0xc128, 0xb87f, 0xc128, 0x21, 0 + .dw 0xb8c0, 0xc128, 0xb8ff, 0xc128, 0x21, 0 + .dw 0xb940, 0xc128, 0xb97f, 0xc128, 0x21, 0 + .dw 0xb9c0, 0xc128, 0xdfff, 0xc128, 0x21, 0 + .dw 0xe040, 0xc128, 0xe07f, 0xc128, 0x21, 0 + .dw 0xe0c0, 0xc128, 0xe0ff, 0xc128, 0x21, 0 + .dw 0xe140, 0xc128, 0xe17f, 0xc128, 0x21, 0 + .dw 0xe1c0, 0xc128, 0xe1ff, 0xc128, 0x21, 0 + .dw 0xe240, 0xc128, 0xe27f, 0xc128, 0x21, 0 + .dw 0xe2c0, 0xc128, 0xe2ff, 0xc128, 0x21, 0 + .dw 0xe340, 0xc128, 0xe37f, 0xc128, 0x21, 0 + .dw 0xe3c0, 0xc128, 0xe3ff, 0xc128, 0x21, 0 + .dw 0xe440, 0xc128, 0xe47f, 0xc128, 0x21, 0 + .dw 0xe4c0, 0xc128, 0xe4ff, 0xc128, 0x21, 0 + .dw 0xe540, 0xc128, 0xe57f, 0xc128, 0x21, 0 + .dw 0xe5c0, 0xc128, 0xe5ff, 0xc128, 0x21, 0 + .dw 0xe640, 0xc128, 0xe67f, 0xc128, 0x21, 0 + .dw 0xe6c0, 0xc128, 0xe6ff, 0xc128, 0x21, 0 + .dw 0xe740, 0xc128, 0xe77f, 0xc128, 0x21, 0 + .dw 0xe7c0, 0xc128, 0xe7ff, 0xc128, 0x21, 0 + .dw 0xe840, 0xc128, 0xe87f, 0xc128, 0x21, 0 + .dw 0xe8c0, 0xc128, 0xe8ff, 0xc128, 0x21, 0 + .dw 0xe940, 0xc128, 0xe97f, 0xc128, 0x21, 0 + .dw 0xe9c0, 0xc128, 0xe9ff, 0xc128, 0x21, 0 + .dw 0xea40, 0xc128, 0xea7f, 0xc128, 0x21, 0 + .dw 0xeac0, 0xc128, 0xeaff, 0xc128, 0x21, 0 + .dw 0xeb40, 0xc128, 0xeb7f, 0xc128, 0x21, 0 + .dw 0xebc0, 0xc128, 0xebff, 0xc128, 0x21, 0 + .dw 0xec40, 0xc128, 0xec7f, 0xc128, 0x21, 0 + .dw 0xecc0, 0xc128, 0xecff, 0xc128, 0x21, 0 + .dw 0xed40, 0xc128, 0xed7f, 0xc128, 0x21, 0 + .dw 0xedc0, 0xc128, 0xedff, 0xc128, 0x21, 0 + .dw 0xee40, 0xc128, 0xee7f, 0xc128, 0x21, 0 + .dw 0xeec0, 0xc128, 0xeeff, 0xc128, 0x21, 0 + .dw 0xef40, 0xc128, 0xef7f, 0xc128, 0x21, 0 + .dw 0xefc0, 0xc128, 0xefff, 0xc128, 0x21, 0 + .dw 0xf040, 0xc128, 0xf07f, 0xc128, 0x21, 0 + .dw 0xf0c0, 0xc128, 0xf0ff, 0xc128, 0x21, 0 + .dw 0xf140, 0xc128, 0xf17f, 0xc128, 0x21, 0 + .dw 0xf1c0, 0xc128, 0xf1ff, 0xc128, 0x21, 0 + .dw 0xf240, 0xc128, 0xf27f, 0xc128, 0x21, 0 + .dw 0xf2c0, 0xc128, 0xf2ff, 0xc128, 0x21, 0 + .dw 0xf340, 0xc128, 0xf37f, 0xc128, 0x21, 0 + .dw 0xf3c0, 0xc128, 0xf3ff, 0xc128, 0x21, 0 + .dw 0xf440, 0xc128, 0xf47f, 0xc128, 0x21, 0 + .dw 0xf4c0, 0xc128, 0xf4ff, 0xc128, 0x21, 0 + .dw 0xf540, 0xc128, 0xf57f, 0xc128, 0x21, 0 + .dw 0xf5c0, 0xc128, 0xf5ff, 0xc128, 0x21, 0 + .dw 0xf640, 0xc128, 0xf67f, 0xc128, 0x21, 0 + .dw 0xf6c0, 0xc128, 0xf6ff, 0xc128, 0x21, 0 + .dw 0xf740, 0xc128, 0xf77f, 0xc128, 0x21, 0 + .dw 0xf7c0, 0xc128, 0xf7ff, 0xc128, 0x21, 0 + .dw 0xf840, 0xc128, 0xf87f, 0xc128, 0x21, 0 + .dw 0xf8c0, 0xc128, 0xf8ff, 0xc128, 0x21, 0 + .dw 0xf940, 0xc128, 0xf97f, 0xc128, 0x21, 0 + .dw 0xf9c0, 0xc128, 0x1fff, 0xc129, 0x21, 0 + .dw 0x2040, 0xc129, 0x207f, 0xc129, 0x21, 0 + .dw 0x20c0, 0xc129, 0x20ff, 0xc129, 0x21, 0 + .dw 0x2140, 0xc129, 0x217f, 0xc129, 0x21, 0 + .dw 0x21c0, 0xc129, 0x21ff, 0xc129, 0x21, 0 + .dw 0x2240, 0xc129, 0x227f, 0xc129, 0x21, 0 + .dw 0x22c0, 0xc129, 0x22ff, 0xc129, 0x21, 0 + .dw 0x2340, 0xc129, 0x237f, 0xc129, 0x21, 0 + .dw 0x23c0, 0xc129, 0x23ff, 0xc129, 0x21, 0 + .dw 0x2440, 0xc129, 0x247f, 0xc129, 0x21, 0 + .dw 0x24c0, 0xc129, 0x24ff, 0xc129, 0x21, 0 + .dw 0x2540, 0xc129, 0x257f, 0xc129, 0x21, 0 + .dw 0x25c0, 0xc129, 0x25ff, 0xc129, 0x21, 0 + .dw 0x2640, 0xc129, 0x267f, 0xc129, 0x21, 0 + .dw 0x26c0, 0xc129, 0x26ff, 0xc129, 0x21, 0 + .dw 0x2740, 0xc129, 0x277f, 0xc129, 0x21, 0 + .dw 0x27c0, 0xc129, 0x27ff, 0xc129, 0x21, 0 + .dw 0x2840, 0xc129, 0x287f, 0xc129, 0x21, 0 + .dw 0x28c0, 0xc129, 0x28ff, 0xc129, 0x21, 0 + .dw 0x2940, 0xc129, 0x297f, 0xc129, 0x21, 0 + .dw 0x29c0, 0xc129, 0x29ff, 0xc129, 0x21, 0 + .dw 0x2a40, 0xc129, 0x2a7f, 0xc129, 0x21, 0 + .dw 0x2ac0, 0xc129, 0x2aff, 0xc129, 0x21, 0 + .dw 0x2b40, 0xc129, 0x2b7f, 0xc129, 0x21, 0 + .dw 0x2bc0, 0xc129, 0x2bff, 0xc129, 0x21, 0 + .dw 0x2c40, 0xc129, 0x2c7f, 0xc129, 0x21, 0 + .dw 0x2cc0, 0xc129, 0x2cff, 0xc129, 0x21, 0 + .dw 0x2d40, 0xc129, 0x2d7f, 0xc129, 0x21, 0 + .dw 0x2dc0, 0xc129, 0x2dff, 0xc129, 0x21, 0 + .dw 0x2e40, 0xc129, 0x2e7f, 0xc129, 0x21, 0 + .dw 0x2ec0, 0xc129, 0x2eff, 0xc129, 0x21, 0 + .dw 0x2f40, 0xc129, 0x2f7f, 0xc129, 0x21, 0 + .dw 0x2fc0, 0xc129, 0x2fff, 0xc129, 0x21, 0 + .dw 0x3040, 0xc129, 0x307f, 0xc129, 0x21, 0 + .dw 0x30c0, 0xc129, 0x30ff, 0xc129, 0x21, 0 + .dw 0x3140, 0xc129, 0x317f, 0xc129, 0x21, 0 + .dw 0x31c0, 0xc129, 0x31ff, 0xc129, 0x21, 0 + .dw 0x3240, 0xc129, 0x327f, 0xc129, 0x21, 0 + .dw 0x32c0, 0xc129, 0x32ff, 0xc129, 0x21, 0 + .dw 0x3340, 0xc129, 0x337f, 0xc129, 0x21, 0 + .dw 0x33c0, 0xc129, 0x33ff, 0xc129, 0x21, 0 + .dw 0x3440, 0xc129, 0x347f, 0xc129, 0x21, 0 + .dw 0x34c0, 0xc129, 0x34ff, 0xc129, 0x21, 0 + .dw 0x3540, 0xc129, 0x357f, 0xc129, 0x21, 0 + .dw 0x35c0, 0xc129, 0x35ff, 0xc129, 0x21, 0 + .dw 0x3640, 0xc129, 0x367f, 0xc129, 0x21, 0 + .dw 0x36c0, 0xc129, 0x36ff, 0xc129, 0x21, 0 + .dw 0x3740, 0xc129, 0x377f, 0xc129, 0x21, 0 + .dw 0x37c0, 0xc129, 0x37ff, 0xc129, 0x21, 0 + .dw 0x3840, 0xc129, 0x387f, 0xc129, 0x21, 0 + .dw 0x38c0, 0xc129, 0x38ff, 0xc129, 0x21, 0 + .dw 0x3940, 0xc129, 0x397f, 0xc129, 0x21, 0 + .dw 0x39c0, 0xc129, 0x5fff, 0xc129, 0x21, 0 + .dw 0x6040, 0xc129, 0x607f, 0xc129, 0x21, 0 + .dw 0x60c0, 0xc129, 0x60ff, 0xc129, 0x21, 0 + .dw 0x6140, 0xc129, 0x617f, 0xc129, 0x21, 0 + .dw 0x61c0, 0xc129, 0x61ff, 0xc129, 0x21, 0 + .dw 0x6240, 0xc129, 0x627f, 0xc129, 0x21, 0 + .dw 0x62c0, 0xc129, 0x62ff, 0xc129, 0x21, 0 + .dw 0x6340, 0xc129, 0x637f, 0xc129, 0x21, 0 + .dw 0x63c0, 0xc129, 0x63ff, 0xc129, 0x21, 0 + .dw 0x6440, 0xc129, 0x647f, 0xc129, 0x21, 0 + .dw 0x64c0, 0xc129, 0x64ff, 0xc129, 0x21, 0 + .dw 0x6540, 0xc129, 0x657f, 0xc129, 0x21, 0 + .dw 0x65c0, 0xc129, 0x65ff, 0xc129, 0x21, 0 + .dw 0x6640, 0xc129, 0x667f, 0xc129, 0x21, 0 + .dw 0x66c0, 0xc129, 0x66ff, 0xc129, 0x21, 0 + .dw 0x6740, 0xc129, 0x677f, 0xc129, 0x21, 0 + .dw 0x67c0, 0xc129, 0x67ff, 0xc129, 0x21, 0 + .dw 0x6840, 0xc129, 0x687f, 0xc129, 0x21, 0 + .dw 0x68c0, 0xc129, 0x68ff, 0xc129, 0x21, 0 + .dw 0x6940, 0xc129, 0x697f, 0xc129, 0x21, 0 + .dw 0x69c0, 0xc129, 0x69ff, 0xc129, 0x21, 0 + .dw 0x6a40, 0xc129, 0x6a7f, 0xc129, 0x21, 0 + .dw 0x6ac0, 0xc129, 0x6aff, 0xc129, 0x21, 0 + .dw 0x6b40, 0xc129, 0x6b7f, 0xc129, 0x21, 0 + .dw 0x6bc0, 0xc129, 0x6bff, 0xc129, 0x21, 0 + .dw 0x6c40, 0xc129, 0x6c7f, 0xc129, 0x21, 0 + .dw 0x6cc0, 0xc129, 0x6cff, 0xc129, 0x21, 0 + .dw 0x6d40, 0xc129, 0x6d7f, 0xc129, 0x21, 0 + .dw 0x6dc0, 0xc129, 0x6dff, 0xc129, 0x21, 0 + .dw 0x6e40, 0xc129, 0x6e7f, 0xc129, 0x21, 0 + .dw 0x6ec0, 0xc129, 0x6eff, 0xc129, 0x21, 0 + .dw 0x6f40, 0xc129, 0x6f7f, 0xc129, 0x21, 0 + .dw 0x6fc0, 0xc129, 0x6fff, 0xc129, 0x21, 0 + .dw 0x7040, 0xc129, 0x707f, 0xc129, 0x21, 0 + .dw 0x70c0, 0xc129, 0x70ff, 0xc129, 0x21, 0 + .dw 0x7140, 0xc129, 0x717f, 0xc129, 0x21, 0 + .dw 0x71c0, 0xc129, 0x71ff, 0xc129, 0x21, 0 + .dw 0x7240, 0xc129, 0x727f, 0xc129, 0x21, 0 + .dw 0x72c0, 0xc129, 0x72ff, 0xc129, 0x21, 0 + .dw 0x7340, 0xc129, 0x737f, 0xc129, 0x21, 0 + .dw 0x73c0, 0xc129, 0x73ff, 0xc129, 0x21, 0 + .dw 0x7440, 0xc129, 0x747f, 0xc129, 0x21, 0 + .dw 0x74c0, 0xc129, 0x74ff, 0xc129, 0x21, 0 + .dw 0x7540, 0xc129, 0x757f, 0xc129, 0x21, 0 + .dw 0x75c0, 0xc129, 0x75ff, 0xc129, 0x21, 0 + .dw 0x7640, 0xc129, 0x767f, 0xc129, 0x21, 0 + .dw 0x76c0, 0xc129, 0x76ff, 0xc129, 0x21, 0 + .dw 0x7740, 0xc129, 0x777f, 0xc129, 0x21, 0 + .dw 0x77c0, 0xc129, 0x77ff, 0xc129, 0x21, 0 + .dw 0x7840, 0xc129, 0x787f, 0xc129, 0x21, 0 + .dw 0x78c0, 0xc129, 0x78ff, 0xc129, 0x21, 0 + .dw 0x7940, 0xc129, 0x797f, 0xc129, 0x21, 0 + .dw 0x79c0, 0xc129, 0x9fff, 0xc129, 0x21, 0 + .dw 0xa040, 0xc129, 0xa07f, 0xc129, 0x21, 0 + .dw 0xa0c0, 0xc129, 0xa0ff, 0xc129, 0x21, 0 + .dw 0xa140, 0xc129, 0xa17f, 0xc129, 0x21, 0 + .dw 0xa1c0, 0xc129, 0xa1ff, 0xc129, 0x21, 0 + .dw 0xa240, 0xc129, 0xa27f, 0xc129, 0x21, 0 + .dw 0xa2c0, 0xc129, 0xa2ff, 0xc129, 0x21, 0 + .dw 0xa340, 0xc129, 0xa37f, 0xc129, 0x21, 0 + .dw 0xa3c0, 0xc129, 0xa3ff, 0xc129, 0x21, 0 + .dw 0xa440, 0xc129, 0xa47f, 0xc129, 0x21, 0 + .dw 0xa4c0, 0xc129, 0xa4ff, 0xc129, 0x21, 0 + .dw 0xa540, 0xc129, 0xa57f, 0xc129, 0x21, 0 + .dw 0xa5c0, 0xc129, 0xa5ff, 0xc129, 0x21, 0 + .dw 0xa640, 0xc129, 0xa67f, 0xc129, 0x21, 0 + .dw 0xa6c0, 0xc129, 0xa6ff, 0xc129, 0x21, 0 + .dw 0xa740, 0xc129, 0xa77f, 0xc129, 0x21, 0 + .dw 0xa7c0, 0xc129, 0xa7ff, 0xc129, 0x21, 0 + .dw 0xa840, 0xc129, 0xa87f, 0xc129, 0x21, 0 + .dw 0xa8c0, 0xc129, 0xa8ff, 0xc129, 0x21, 0 + .dw 0xa940, 0xc129, 0xa97f, 0xc129, 0x21, 0 + .dw 0xa9c0, 0xc129, 0xa9ff, 0xc129, 0x21, 0 + .dw 0xaa40, 0xc129, 0xaa7f, 0xc129, 0x21, 0 + .dw 0xaac0, 0xc129, 0xaaff, 0xc129, 0x21, 0 + .dw 0xab40, 0xc129, 0xab7f, 0xc129, 0x21, 0 + .dw 0xabc0, 0xc129, 0xabff, 0xc129, 0x21, 0 + .dw 0xac40, 0xc129, 0xac7f, 0xc129, 0x21, 0 + .dw 0xacc0, 0xc129, 0xacff, 0xc129, 0x21, 0 + .dw 0xad40, 0xc129, 0xad7f, 0xc129, 0x21, 0 + .dw 0xadc0, 0xc129, 0xadff, 0xc129, 0x21, 0 + .dw 0xae40, 0xc129, 0xae7f, 0xc129, 0x21, 0 + .dw 0xaec0, 0xc129, 0xaeff, 0xc129, 0x21, 0 + .dw 0xaf40, 0xc129, 0xaf7f, 0xc129, 0x21, 0 + .dw 0xafc0, 0xc129, 0xafff, 0xc129, 0x21, 0 + .dw 0xb040, 0xc129, 0xb07f, 0xc129, 0x21, 0 + .dw 0xb0c0, 0xc129, 0xb0ff, 0xc129, 0x21, 0 + .dw 0xb140, 0xc129, 0xb17f, 0xc129, 0x21, 0 + .dw 0xb1c0, 0xc129, 0xb1ff, 0xc129, 0x21, 0 + .dw 0xb240, 0xc129, 0xb27f, 0xc129, 0x21, 0 + .dw 0xb2c0, 0xc129, 0xb2ff, 0xc129, 0x21, 0 + .dw 0xb340, 0xc129, 0xb37f, 0xc129, 0x21, 0 + .dw 0xb3c0, 0xc129, 0xb3ff, 0xc129, 0x21, 0 + .dw 0xb440, 0xc129, 0xb47f, 0xc129, 0x21, 0 + .dw 0xb4c0, 0xc129, 0xb4ff, 0xc129, 0x21, 0 + .dw 0xb540, 0xc129, 0xb57f, 0xc129, 0x21, 0 + .dw 0xb5c0, 0xc129, 0xb5ff, 0xc129, 0x21, 0 + .dw 0xb640, 0xc129, 0xb67f, 0xc129, 0x21, 0 + .dw 0xb6c0, 0xc129, 0xb6ff, 0xc129, 0x21, 0 + .dw 0xb740, 0xc129, 0xb77f, 0xc129, 0x21, 0 + .dw 0xb7c0, 0xc129, 0xb7ff, 0xc129, 0x21, 0 + .dw 0xb840, 0xc129, 0xb87f, 0xc129, 0x21, 0 + .dw 0xb8c0, 0xc129, 0xb8ff, 0xc129, 0x21, 0 + .dw 0xb940, 0xc129, 0xb97f, 0xc129, 0x21, 0 + .dw 0xb9c0, 0xc129, 0xdfff, 0xc129, 0x21, 0 + .dw 0xe040, 0xc129, 0xe07f, 0xc129, 0x21, 0 + .dw 0xe0c0, 0xc129, 0xe0ff, 0xc129, 0x21, 0 + .dw 0xe140, 0xc129, 0xe17f, 0xc129, 0x21, 0 + .dw 0xe1c0, 0xc129, 0xe1ff, 0xc129, 0x21, 0 + .dw 0xe240, 0xc129, 0xe27f, 0xc129, 0x21, 0 + .dw 0xe2c0, 0xc129, 0xe2ff, 0xc129, 0x21, 0 + .dw 0xe340, 0xc129, 0xe37f, 0xc129, 0x21, 0 + .dw 0xe3c0, 0xc129, 0xe3ff, 0xc129, 0x21, 0 + .dw 0xe440, 0xc129, 0xe47f, 0xc129, 0x21, 0 + .dw 0xe4c0, 0xc129, 0xe4ff, 0xc129, 0x21, 0 + .dw 0xe540, 0xc129, 0xe57f, 0xc129, 0x21, 0 + .dw 0xe5c0, 0xc129, 0xe5ff, 0xc129, 0x21, 0 + .dw 0xe640, 0xc129, 0xe67f, 0xc129, 0x21, 0 + .dw 0xe6c0, 0xc129, 0xe6ff, 0xc129, 0x21, 0 + .dw 0xe740, 0xc129, 0xe77f, 0xc129, 0x21, 0 + .dw 0xe7c0, 0xc129, 0xe7ff, 0xc129, 0x21, 0 + .dw 0xe840, 0xc129, 0xe87f, 0xc129, 0x21, 0 + .dw 0xe8c0, 0xc129, 0xe8ff, 0xc129, 0x21, 0 + .dw 0xe940, 0xc129, 0xe97f, 0xc129, 0x21, 0 + .dw 0xe9c0, 0xc129, 0xe9ff, 0xc129, 0x21, 0 + .dw 0xea40, 0xc129, 0xea7f, 0xc129, 0x21, 0 + .dw 0xeac0, 0xc129, 0xeaff, 0xc129, 0x21, 0 + .dw 0xeb40, 0xc129, 0xeb7f, 0xc129, 0x21, 0 + .dw 0xebc0, 0xc129, 0xebff, 0xc129, 0x21, 0 + .dw 0xec40, 0xc129, 0xec7f, 0xc129, 0x21, 0 + .dw 0xecc0, 0xc129, 0xecff, 0xc129, 0x21, 0 + .dw 0xed40, 0xc129, 0xed7f, 0xc129, 0x21, 0 + .dw 0xedc0, 0xc129, 0xedff, 0xc129, 0x21, 0 + .dw 0xee40, 0xc129, 0xee7f, 0xc129, 0x21, 0 + .dw 0xeec0, 0xc129, 0xeeff, 0xc129, 0x21, 0 + .dw 0xef40, 0xc129, 0xef7f, 0xc129, 0x21, 0 + .dw 0xefc0, 0xc129, 0xefff, 0xc129, 0x21, 0 + .dw 0xf040, 0xc129, 0xf07f, 0xc129, 0x21, 0 + .dw 0xf0c0, 0xc129, 0xf0ff, 0xc129, 0x21, 0 + .dw 0xf140, 0xc129, 0xf17f, 0xc129, 0x21, 0 + .dw 0xf1c0, 0xc129, 0xf1ff, 0xc129, 0x21, 0 + .dw 0xf240, 0xc129, 0xf27f, 0xc129, 0x21, 0 + .dw 0xf2c0, 0xc129, 0xf2ff, 0xc129, 0x21, 0 + .dw 0xf340, 0xc129, 0xf37f, 0xc129, 0x21, 0 + .dw 0xf3c0, 0xc129, 0xf3ff, 0xc129, 0x21, 0 + .dw 0xf440, 0xc129, 0xf47f, 0xc129, 0x21, 0 + .dw 0xf4c0, 0xc129, 0xf4ff, 0xc129, 0x21, 0 + .dw 0xf540, 0xc129, 0xf57f, 0xc129, 0x21, 0 + .dw 0xf5c0, 0xc129, 0xf5ff, 0xc129, 0x21, 0 + .dw 0xf640, 0xc129, 0xf67f, 0xc129, 0x21, 0 + .dw 0xf6c0, 0xc129, 0xf6ff, 0xc129, 0x21, 0 + .dw 0xf740, 0xc129, 0xf77f, 0xc129, 0x21, 0 + .dw 0xf7c0, 0xc129, 0xf7ff, 0xc129, 0x21, 0 + .dw 0xf840, 0xc129, 0xf87f, 0xc129, 0x21, 0 + .dw 0xf8c0, 0xc129, 0xf8ff, 0xc129, 0x21, 0 + .dw 0xf940, 0xc129, 0xf97f, 0xc129, 0x21, 0 + .dw 0xf9c0, 0xc129, 0x1fff, 0xc12a, 0x21, 0 + .dw 0x2040, 0xc12a, 0x207f, 0xc12a, 0x21, 0 + .dw 0x20c0, 0xc12a, 0x20ff, 0xc12a, 0x21, 0 + .dw 0x2140, 0xc12a, 0x217f, 0xc12a, 0x21, 0 + .dw 0x21c0, 0xc12a, 0x21ff, 0xc12a, 0x21, 0 + .dw 0x2240, 0xc12a, 0x227f, 0xc12a, 0x21, 0 + .dw 0x22c0, 0xc12a, 0x22ff, 0xc12a, 0x21, 0 + .dw 0x2340, 0xc12a, 0x237f, 0xc12a, 0x21, 0 + .dw 0x23c0, 0xc12a, 0x23ff, 0xc12a, 0x21, 0 + .dw 0x2440, 0xc12a, 0x247f, 0xc12a, 0x21, 0 + .dw 0x24c0, 0xc12a, 0x24ff, 0xc12a, 0x21, 0 + .dw 0x2540, 0xc12a, 0x257f, 0xc12a, 0x21, 0 + .dw 0x25c0, 0xc12a, 0x25ff, 0xc12a, 0x21, 0 + .dw 0x2640, 0xc12a, 0x267f, 0xc12a, 0x21, 0 + .dw 0x26c0, 0xc12a, 0x26ff, 0xc12a, 0x21, 0 + .dw 0x2740, 0xc12a, 0x277f, 0xc12a, 0x21, 0 + .dw 0x27c0, 0xc12a, 0x27ff, 0xc12a, 0x21, 0 + .dw 0x2840, 0xc12a, 0x287f, 0xc12a, 0x21, 0 + .dw 0x28c0, 0xc12a, 0x28ff, 0xc12a, 0x21, 0 + .dw 0x2940, 0xc12a, 0x297f, 0xc12a, 0x21, 0 + .dw 0x29c0, 0xc12a, 0x29ff, 0xc12a, 0x21, 0 + .dw 0x2a40, 0xc12a, 0x2a7f, 0xc12a, 0x21, 0 + .dw 0x2ac0, 0xc12a, 0x2aff, 0xc12a, 0x21, 0 + .dw 0x2b40, 0xc12a, 0x2b7f, 0xc12a, 0x21, 0 + .dw 0x2bc0, 0xc12a, 0x2bff, 0xc12a, 0x21, 0 + .dw 0x2c40, 0xc12a, 0x2c7f, 0xc12a, 0x21, 0 + .dw 0x2cc0, 0xc12a, 0x2cff, 0xc12a, 0x21, 0 + .dw 0x2d40, 0xc12a, 0x2d7f, 0xc12a, 0x21, 0 + .dw 0x2dc0, 0xc12a, 0x2dff, 0xc12a, 0x21, 0 + .dw 0x2e40, 0xc12a, 0x2e7f, 0xc12a, 0x21, 0 + .dw 0x2ec0, 0xc12a, 0x2eff, 0xc12a, 0x21, 0 + .dw 0x2f40, 0xc12a, 0x2f7f, 0xc12a, 0x21, 0 + .dw 0x2fc0, 0xc12a, 0x2fff, 0xc12a, 0x21, 0 + .dw 0x3040, 0xc12a, 0x307f, 0xc12a, 0x21, 0 + .dw 0x30c0, 0xc12a, 0x30ff, 0xc12a, 0x21, 0 + .dw 0x3140, 0xc12a, 0x317f, 0xc12a, 0x21, 0 + .dw 0x31c0, 0xc12a, 0x31ff, 0xc12a, 0x21, 0 + .dw 0x3240, 0xc12a, 0x327f, 0xc12a, 0x21, 0 + .dw 0x32c0, 0xc12a, 0x32ff, 0xc12a, 0x21, 0 + .dw 0x3340, 0xc12a, 0x337f, 0xc12a, 0x21, 0 + .dw 0x33c0, 0xc12a, 0x33ff, 0xc12a, 0x21, 0 + .dw 0x3440, 0xc12a, 0x347f, 0xc12a, 0x21, 0 + .dw 0x34c0, 0xc12a, 0x34ff, 0xc12a, 0x21, 0 + .dw 0x3540, 0xc12a, 0x357f, 0xc12a, 0x21, 0 + .dw 0x35c0, 0xc12a, 0x35ff, 0xc12a, 0x21, 0 + .dw 0x3640, 0xc12a, 0x367f, 0xc12a, 0x21, 0 + .dw 0x36c0, 0xc12a, 0x36ff, 0xc12a, 0x21, 0 + .dw 0x3740, 0xc12a, 0x377f, 0xc12a, 0x21, 0 + .dw 0x37c0, 0xc12a, 0x37ff, 0xc12a, 0x21, 0 + .dw 0x3840, 0xc12a, 0x387f, 0xc12a, 0x21, 0 + .dw 0x38c0, 0xc12a, 0x38ff, 0xc12a, 0x21, 0 + .dw 0x3940, 0xc12a, 0x397f, 0xc12a, 0x21, 0 + .dw 0x39c0, 0xc12a, 0x5fff, 0xc12a, 0x21, 0 + .dw 0x6040, 0xc12a, 0x607f, 0xc12a, 0x21, 0 + .dw 0x60c0, 0xc12a, 0x60ff, 0xc12a, 0x21, 0 + .dw 0x6140, 0xc12a, 0x617f, 0xc12a, 0x21, 0 + .dw 0x61c0, 0xc12a, 0x61ff, 0xc12a, 0x21, 0 + .dw 0x6240, 0xc12a, 0x627f, 0xc12a, 0x21, 0 + .dw 0x62c0, 0xc12a, 0x62ff, 0xc12a, 0x21, 0 + .dw 0x6340, 0xc12a, 0x637f, 0xc12a, 0x21, 0 + .dw 0x63c0, 0xc12a, 0x63ff, 0xc12a, 0x21, 0 + .dw 0x6440, 0xc12a, 0x647f, 0xc12a, 0x21, 0 + .dw 0x64c0, 0xc12a, 0x64ff, 0xc12a, 0x21, 0 + .dw 0x6540, 0xc12a, 0x657f, 0xc12a, 0x21, 0 + .dw 0x65c0, 0xc12a, 0x65ff, 0xc12a, 0x21, 0 + .dw 0x6640, 0xc12a, 0x667f, 0xc12a, 0x21, 0 + .dw 0x66c0, 0xc12a, 0x66ff, 0xc12a, 0x21, 0 + .dw 0x6740, 0xc12a, 0x677f, 0xc12a, 0x21, 0 + .dw 0x67c0, 0xc12a, 0x67ff, 0xc12a, 0x21, 0 + .dw 0x6840, 0xc12a, 0x687f, 0xc12a, 0x21, 0 + .dw 0x68c0, 0xc12a, 0x68ff, 0xc12a, 0x21, 0 + .dw 0x6940, 0xc12a, 0x697f, 0xc12a, 0x21, 0 + .dw 0x69c0, 0xc12a, 0x69ff, 0xc12a, 0x21, 0 + .dw 0x6a40, 0xc12a, 0x6a7f, 0xc12a, 0x21, 0 + .dw 0x6ac0, 0xc12a, 0x6aff, 0xc12a, 0x21, 0 + .dw 0x6b40, 0xc12a, 0x6b7f, 0xc12a, 0x21, 0 + .dw 0x6bc0, 0xc12a, 0x6bff, 0xc12a, 0x21, 0 + .dw 0x6c40, 0xc12a, 0x6c7f, 0xc12a, 0x21, 0 + .dw 0x6cc0, 0xc12a, 0x6cff, 0xc12a, 0x21, 0 + .dw 0x6d40, 0xc12a, 0x6d7f, 0xc12a, 0x21, 0 + .dw 0x6dc0, 0xc12a, 0x6dff, 0xc12a, 0x21, 0 + .dw 0x6e40, 0xc12a, 0x6e7f, 0xc12a, 0x21, 0 + .dw 0x6ec0, 0xc12a, 0x6eff, 0xc12a, 0x21, 0 + .dw 0x6f40, 0xc12a, 0x6f7f, 0xc12a, 0x21, 0 + .dw 0x6fc0, 0xc12a, 0x6fff, 0xc12a, 0x21, 0 + .dw 0x7040, 0xc12a, 0x707f, 0xc12a, 0x21, 0 + .dw 0x70c0, 0xc12a, 0x70ff, 0xc12a, 0x21, 0 + .dw 0x7140, 0xc12a, 0x717f, 0xc12a, 0x21, 0 + .dw 0x71c0, 0xc12a, 0x71ff, 0xc12a, 0x21, 0 + .dw 0x7240, 0xc12a, 0x727f, 0xc12a, 0x21, 0 + .dw 0x72c0, 0xc12a, 0x72ff, 0xc12a, 0x21, 0 + .dw 0x7340, 0xc12a, 0x737f, 0xc12a, 0x21, 0 + .dw 0x73c0, 0xc12a, 0x73ff, 0xc12a, 0x21, 0 + .dw 0x7440, 0xc12a, 0x747f, 0xc12a, 0x21, 0 + .dw 0x74c0, 0xc12a, 0x74ff, 0xc12a, 0x21, 0 + .dw 0x7540, 0xc12a, 0x757f, 0xc12a, 0x21, 0 + .dw 0x75c0, 0xc12a, 0x75ff, 0xc12a, 0x21, 0 + .dw 0x7640, 0xc12a, 0x767f, 0xc12a, 0x21, 0 + .dw 0x76c0, 0xc12a, 0x76ff, 0xc12a, 0x21, 0 + .dw 0x7740, 0xc12a, 0x777f, 0xc12a, 0x21, 0 + .dw 0x77c0, 0xc12a, 0x77ff, 0xc12a, 0x21, 0 + .dw 0x7840, 0xc12a, 0x787f, 0xc12a, 0x21, 0 + .dw 0x78c0, 0xc12a, 0x78ff, 0xc12a, 0x21, 0 + .dw 0x7940, 0xc12a, 0x797f, 0xc12a, 0x21, 0 + .dw 0x79c0, 0xc12a, 0x9fff, 0xc12a, 0x21, 0 + .dw 0xa040, 0xc12a, 0xa07f, 0xc12a, 0x21, 0 + .dw 0xa0c0, 0xc12a, 0xa0ff, 0xc12a, 0x21, 0 + .dw 0xa140, 0xc12a, 0xa17f, 0xc12a, 0x21, 0 + .dw 0xa1c0, 0xc12a, 0xa1ff, 0xc12a, 0x21, 0 + .dw 0xa240, 0xc12a, 0xa27f, 0xc12a, 0x21, 0 + .dw 0xa2c0, 0xc12a, 0xa2ff, 0xc12a, 0x21, 0 + .dw 0xa340, 0xc12a, 0xa37f, 0xc12a, 0x21, 0 + .dw 0xa3c0, 0xc12a, 0xa3ff, 0xc12a, 0x21, 0 + .dw 0xa440, 0xc12a, 0xa47f, 0xc12a, 0x21, 0 + .dw 0xa4c0, 0xc12a, 0xa4ff, 0xc12a, 0x21, 0 + .dw 0xa540, 0xc12a, 0xa57f, 0xc12a, 0x21, 0 + .dw 0xa5c0, 0xc12a, 0xa5ff, 0xc12a, 0x21, 0 + .dw 0xa640, 0xc12a, 0xa67f, 0xc12a, 0x21, 0 + .dw 0xa6c0, 0xc12a, 0xa6ff, 0xc12a, 0x21, 0 + .dw 0xa740, 0xc12a, 0xa77f, 0xc12a, 0x21, 0 + .dw 0xa7c0, 0xc12a, 0xa7ff, 0xc12a, 0x21, 0 + .dw 0xa840, 0xc12a, 0xa87f, 0xc12a, 0x21, 0 + .dw 0xa8c0, 0xc12a, 0xa8ff, 0xc12a, 0x21, 0 + .dw 0xa940, 0xc12a, 0xa97f, 0xc12a, 0x21, 0 + .dw 0xa9c0, 0xc12a, 0xa9ff, 0xc12a, 0x21, 0 + .dw 0xaa40, 0xc12a, 0xaa7f, 0xc12a, 0x21, 0 + .dw 0xaac0, 0xc12a, 0xaaff, 0xc12a, 0x21, 0 + .dw 0xab40, 0xc12a, 0xab7f, 0xc12a, 0x21, 0 + .dw 0xabc0, 0xc12a, 0xabff, 0xc12a, 0x21, 0 + .dw 0xac40, 0xc12a, 0xac7f, 0xc12a, 0x21, 0 + .dw 0xacc0, 0xc12a, 0xacff, 0xc12a, 0x21, 0 + .dw 0xad40, 0xc12a, 0xad7f, 0xc12a, 0x21, 0 + .dw 0xadc0, 0xc12a, 0xadff, 0xc12a, 0x21, 0 + .dw 0xae40, 0xc12a, 0xae7f, 0xc12a, 0x21, 0 + .dw 0xaec0, 0xc12a, 0xaeff, 0xc12a, 0x21, 0 + .dw 0xaf40, 0xc12a, 0xaf7f, 0xc12a, 0x21, 0 + .dw 0xafc0, 0xc12a, 0xafff, 0xc12a, 0x21, 0 + .dw 0xb040, 0xc12a, 0xb07f, 0xc12a, 0x21, 0 + .dw 0xb0c0, 0xc12a, 0xb0ff, 0xc12a, 0x21, 0 + .dw 0xb140, 0xc12a, 0xb17f, 0xc12a, 0x21, 0 + .dw 0xb1c0, 0xc12a, 0xb1ff, 0xc12a, 0x21, 0 + .dw 0xb240, 0xc12a, 0xb27f, 0xc12a, 0x21, 0 + .dw 0xb2c0, 0xc12a, 0xb2ff, 0xc12a, 0x21, 0 + .dw 0xb340, 0xc12a, 0xb37f, 0xc12a, 0x21, 0 + .dw 0xb3c0, 0xc12a, 0xb3ff, 0xc12a, 0x21, 0 + .dw 0xb440, 0xc12a, 0xb47f, 0xc12a, 0x21, 0 + .dw 0xb4c0, 0xc12a, 0xb4ff, 0xc12a, 0x21, 0 + .dw 0xb540, 0xc12a, 0xb57f, 0xc12a, 0x21, 0 + .dw 0xb5c0, 0xc12a, 0xb5ff, 0xc12a, 0x21, 0 + .dw 0xb640, 0xc12a, 0xb67f, 0xc12a, 0x21, 0 + .dw 0xb6c0, 0xc12a, 0xb6ff, 0xc12a, 0x21, 0 + .dw 0xb740, 0xc12a, 0xb77f, 0xc12a, 0x21, 0 + .dw 0xb7c0, 0xc12a, 0xb7ff, 0xc12a, 0x21, 0 + .dw 0xb840, 0xc12a, 0xb87f, 0xc12a, 0x21, 0 + .dw 0xb8c0, 0xc12a, 0xb8ff, 0xc12a, 0x21, 0 + .dw 0xb940, 0xc12a, 0xb97f, 0xc12a, 0x21, 0 + .dw 0xb9c0, 0xc12a, 0xdfff, 0xc12a, 0x21, 0 + .dw 0xe040, 0xc12a, 0xe07f, 0xc12a, 0x21, 0 + .dw 0xe0c0, 0xc12a, 0xe0ff, 0xc12a, 0x21, 0 + .dw 0xe140, 0xc12a, 0xe17f, 0xc12a, 0x21, 0 + .dw 0xe1c0, 0xc12a, 0xe1ff, 0xc12a, 0x21, 0 + .dw 0xe240, 0xc12a, 0xe27f, 0xc12a, 0x21, 0 + .dw 0xe2c0, 0xc12a, 0xe2ff, 0xc12a, 0x21, 0 + .dw 0xe340, 0xc12a, 0xe37f, 0xc12a, 0x21, 0 + .dw 0xe3c0, 0xc12a, 0xe3ff, 0xc12a, 0x21, 0 + .dw 0xe440, 0xc12a, 0xe47f, 0xc12a, 0x21, 0 + .dw 0xe4c0, 0xc12a, 0xe4ff, 0xc12a, 0x21, 0 + .dw 0xe540, 0xc12a, 0xe57f, 0xc12a, 0x21, 0 + .dw 0xe5c0, 0xc12a, 0xe5ff, 0xc12a, 0x21, 0 + .dw 0xe640, 0xc12a, 0xe67f, 0xc12a, 0x21, 0 + .dw 0xe6c0, 0xc12a, 0xe6ff, 0xc12a, 0x21, 0 + .dw 0xe740, 0xc12a, 0xe77f, 0xc12a, 0x21, 0 + .dw 0xe7c0, 0xc12a, 0xe7ff, 0xc12a, 0x21, 0 + .dw 0xe840, 0xc12a, 0xe87f, 0xc12a, 0x21, 0 + .dw 0xe8c0, 0xc12a, 0xe8ff, 0xc12a, 0x21, 0 + .dw 0xe940, 0xc12a, 0xe97f, 0xc12a, 0x21, 0 + .dw 0xe9c0, 0xc12a, 0xe9ff, 0xc12a, 0x21, 0 + .dw 0xea40, 0xc12a, 0xea7f, 0xc12a, 0x21, 0 + .dw 0xeac0, 0xc12a, 0xeaff, 0xc12a, 0x21, 0 + .dw 0xeb40, 0xc12a, 0xeb7f, 0xc12a, 0x21, 0 + .dw 0xebc0, 0xc12a, 0xebff, 0xc12a, 0x21, 0 + .dw 0xec40, 0xc12a, 0xec7f, 0xc12a, 0x21, 0 + .dw 0xecc0, 0xc12a, 0xecff, 0xc12a, 0x21, 0 + .dw 0xed40, 0xc12a, 0xed7f, 0xc12a, 0x21, 0 + .dw 0xedc0, 0xc12a, 0xedff, 0xc12a, 0x21, 0 + .dw 0xee40, 0xc12a, 0xee7f, 0xc12a, 0x21, 0 + .dw 0xeec0, 0xc12a, 0xeeff, 0xc12a, 0x21, 0 + .dw 0xef40, 0xc12a, 0xef7f, 0xc12a, 0x21, 0 + .dw 0xefc0, 0xc12a, 0xefff, 0xc12a, 0x21, 0 + .dw 0xf040, 0xc12a, 0xf07f, 0xc12a, 0x21, 0 + .dw 0xf0c0, 0xc12a, 0xf0ff, 0xc12a, 0x21, 0 + .dw 0xf140, 0xc12a, 0xf17f, 0xc12a, 0x21, 0 + .dw 0xf1c0, 0xc12a, 0xf1ff, 0xc12a, 0x21, 0 + .dw 0xf240, 0xc12a, 0xf27f, 0xc12a, 0x21, 0 + .dw 0xf2c0, 0xc12a, 0xf2ff, 0xc12a, 0x21, 0 + .dw 0xf340, 0xc12a, 0xf37f, 0xc12a, 0x21, 0 + .dw 0xf3c0, 0xc12a, 0xf3ff, 0xc12a, 0x21, 0 + .dw 0xf440, 0xc12a, 0xf47f, 0xc12a, 0x21, 0 + .dw 0xf4c0, 0xc12a, 0xf4ff, 0xc12a, 0x21, 0 + .dw 0xf540, 0xc12a, 0xf57f, 0xc12a, 0x21, 0 + .dw 0xf5c0, 0xc12a, 0xf5ff, 0xc12a, 0x21, 0 + .dw 0xf640, 0xc12a, 0xf67f, 0xc12a, 0x21, 0 + .dw 0xf6c0, 0xc12a, 0xf6ff, 0xc12a, 0x21, 0 + .dw 0xf740, 0xc12a, 0xf77f, 0xc12a, 0x21, 0 + .dw 0xf7c0, 0xc12a, 0xf7ff, 0xc12a, 0x21, 0 + .dw 0xf840, 0xc12a, 0xf87f, 0xc12a, 0x21, 0 + .dw 0xf8c0, 0xc12a, 0xf8ff, 0xc12a, 0x21, 0 + .dw 0xf940, 0xc12a, 0xf97f, 0xc12a, 0x21, 0 + .dw 0xf9c0, 0xc12a, 0x1fff, 0xc12b, 0x21, 0 + .dw 0x2040, 0xc12b, 0x207f, 0xc12b, 0x21, 0 + .dw 0x20c0, 0xc12b, 0x20ff, 0xc12b, 0x21, 0 + .dw 0x2140, 0xc12b, 0x217f, 0xc12b, 0x21, 0 + .dw 0x21c0, 0xc12b, 0x21ff, 0xc12b, 0x21, 0 + .dw 0x2240, 0xc12b, 0x227f, 0xc12b, 0x21, 0 + .dw 0x22c0, 0xc12b, 0x22ff, 0xc12b, 0x21, 0 + .dw 0x2340, 0xc12b, 0x237f, 0xc12b, 0x21, 0 + .dw 0x23c0, 0xc12b, 0x23ff, 0xc12b, 0x21, 0 + .dw 0x2440, 0xc12b, 0x247f, 0xc12b, 0x21, 0 + .dw 0x24c0, 0xc12b, 0x24ff, 0xc12b, 0x21, 0 + .dw 0x2540, 0xc12b, 0x257f, 0xc12b, 0x21, 0 + .dw 0x25c0, 0xc12b, 0x25ff, 0xc12b, 0x21, 0 + .dw 0x2640, 0xc12b, 0x267f, 0xc12b, 0x21, 0 + .dw 0x26c0, 0xc12b, 0x26ff, 0xc12b, 0x21, 0 + .dw 0x2740, 0xc12b, 0x277f, 0xc12b, 0x21, 0 + .dw 0x27c0, 0xc12b, 0x27ff, 0xc12b, 0x21, 0 + .dw 0x2840, 0xc12b, 0x287f, 0xc12b, 0x21, 0 + .dw 0x28c0, 0xc12b, 0x28ff, 0xc12b, 0x21, 0 + .dw 0x2940, 0xc12b, 0x297f, 0xc12b, 0x21, 0 + .dw 0x29c0, 0xc12b, 0x29ff, 0xc12b, 0x21, 0 + .dw 0x2a40, 0xc12b, 0x2a7f, 0xc12b, 0x21, 0 + .dw 0x2ac0, 0xc12b, 0x2aff, 0xc12b, 0x21, 0 + .dw 0x2b40, 0xc12b, 0x2b7f, 0xc12b, 0x21, 0 + .dw 0x2bc0, 0xc12b, 0x2bff, 0xc12b, 0x21, 0 + .dw 0x2c40, 0xc12b, 0x2c7f, 0xc12b, 0x21, 0 + .dw 0x2cc0, 0xc12b, 0x2cff, 0xc12b, 0x21, 0 + .dw 0x2d40, 0xc12b, 0x2d7f, 0xc12b, 0x21, 0 + .dw 0x2dc0, 0xc12b, 0x2dff, 0xc12b, 0x21, 0 + .dw 0x2e40, 0xc12b, 0x2e7f, 0xc12b, 0x21, 0 + .dw 0x2ec0, 0xc12b, 0x2eff, 0xc12b, 0x21, 0 + .dw 0x2f40, 0xc12b, 0x2f7f, 0xc12b, 0x21, 0 + .dw 0x2fc0, 0xc12b, 0x2fff, 0xc12b, 0x21, 0 + .dw 0x3040, 0xc12b, 0x307f, 0xc12b, 0x21, 0 + .dw 0x30c0, 0xc12b, 0x30ff, 0xc12b, 0x21, 0 + .dw 0x3140, 0xc12b, 0x317f, 0xc12b, 0x21, 0 + .dw 0x31c0, 0xc12b, 0x31ff, 0xc12b, 0x21, 0 + .dw 0x3240, 0xc12b, 0x327f, 0xc12b, 0x21, 0 + .dw 0x32c0, 0xc12b, 0x32ff, 0xc12b, 0x21, 0 + .dw 0x3340, 0xc12b, 0x337f, 0xc12b, 0x21, 0 + .dw 0x33c0, 0xc12b, 0x33ff, 0xc12b, 0x21, 0 + .dw 0x3440, 0xc12b, 0x347f, 0xc12b, 0x21, 0 + .dw 0x34c0, 0xc12b, 0x34ff, 0xc12b, 0x21, 0 + .dw 0x3540, 0xc12b, 0x357f, 0xc12b, 0x21, 0 + .dw 0x35c0, 0xc12b, 0x35ff, 0xc12b, 0x21, 0 + .dw 0x3640, 0xc12b, 0x367f, 0xc12b, 0x21, 0 + .dw 0x36c0, 0xc12b, 0x36ff, 0xc12b, 0x21, 0 + .dw 0x3740, 0xc12b, 0x377f, 0xc12b, 0x21, 0 + .dw 0x37c0, 0xc12b, 0x37ff, 0xc12b, 0x21, 0 + .dw 0x3840, 0xc12b, 0x387f, 0xc12b, 0x21, 0 + .dw 0x38c0, 0xc12b, 0x38ff, 0xc12b, 0x21, 0 + .dw 0x3940, 0xc12b, 0x397f, 0xc12b, 0x21, 0 + .dw 0x39c0, 0xc12b, 0xffff, 0xc12b, 0x21, 0 + .dw 0x0040, 0xc12c, 0x007f, 0xc12c, 0x21, 0 + .dw 0x00c0, 0xc12c, 0x00ff, 0xc12c, 0x21, 0 + .dw 0x0140, 0xc12c, 0x017f, 0xc12c, 0x21, 0 + .dw 0x01c0, 0xc12c, 0x01ff, 0xc12c, 0x21, 0 + .dw 0x0240, 0xc12c, 0x027f, 0xc12c, 0x21, 0 + .dw 0x02c0, 0xc12c, 0x02ff, 0xc12c, 0x21, 0 + .dw 0x0340, 0xc12c, 0x037f, 0xc12c, 0x21, 0 + .dw 0x03c0, 0xc12c, 0x03ff, 0xc12c, 0x21, 0 + .dw 0x0440, 0xc12c, 0x047f, 0xc12c, 0x21, 0 + .dw 0x04c0, 0xc12c, 0x04ff, 0xc12c, 0x21, 0 + .dw 0x0540, 0xc12c, 0x057f, 0xc12c, 0x21, 0 + .dw 0x05c0, 0xc12c, 0x05ff, 0xc12c, 0x21, 0 + .dw 0x0640, 0xc12c, 0x067f, 0xc12c, 0x21, 0 + .dw 0x06c0, 0xc12c, 0x06ff, 0xc12c, 0x21, 0 + .dw 0x0740, 0xc12c, 0x077f, 0xc12c, 0x21, 0 + .dw 0x07c0, 0xc12c, 0x07ff, 0xc12c, 0x21, 0 + .dw 0x0840, 0xc12c, 0x087f, 0xc12c, 0x21, 0 + .dw 0x08c0, 0xc12c, 0x08ff, 0xc12c, 0x21, 0 + .dw 0x0940, 0xc12c, 0x097f, 0xc12c, 0x21, 0 + .dw 0x09c0, 0xc12c, 0x09ff, 0xc12c, 0x21, 0 + .dw 0x0a40, 0xc12c, 0x0a7f, 0xc12c, 0x21, 0 + .dw 0x0ac0, 0xc12c, 0x0aff, 0xc12c, 0x21, 0 + .dw 0x0b40, 0xc12c, 0x0b7f, 0xc12c, 0x21, 0 + .dw 0x0bc0, 0xc12c, 0x0bff, 0xc12c, 0x21, 0 + .dw 0x0c40, 0xc12c, 0x0c7f, 0xc12c, 0x21, 0 + .dw 0x0cc0, 0xc12c, 0x0cff, 0xc12c, 0x21, 0 + .dw 0x0d40, 0xc12c, 0x0d7f, 0xc12c, 0x21, 0 + .dw 0x0dc0, 0xc12c, 0x0dff, 0xc12c, 0x21, 0 + .dw 0x0e40, 0xc12c, 0x0e7f, 0xc12c, 0x21, 0 + .dw 0x0ec0, 0xc12c, 0x0eff, 0xc12c, 0x21, 0 + .dw 0x0f40, 0xc12c, 0x0f7f, 0xc12c, 0x21, 0 + .dw 0x0fc0, 0xc12c, 0x0fff, 0xc12c, 0x21, 0 + .dw 0x1040, 0xc12c, 0x107f, 0xc12c, 0x21, 0 + .dw 0x10c0, 0xc12c, 0x10ff, 0xc12c, 0x21, 0 + .dw 0x1140, 0xc12c, 0x117f, 0xc12c, 0x21, 0 + .dw 0x11c0, 0xc12c, 0x11ff, 0xc12c, 0x21, 0 + .dw 0x1240, 0xc12c, 0x127f, 0xc12c, 0x21, 0 + .dw 0x12c0, 0xc12c, 0x12ff, 0xc12c, 0x21, 0 + .dw 0x1340, 0xc12c, 0x137f, 0xc12c, 0x21, 0 + .dw 0x13c0, 0xc12c, 0x13ff, 0xc12c, 0x21, 0 + .dw 0x1440, 0xc12c, 0x147f, 0xc12c, 0x21, 0 + .dw 0x14c0, 0xc12c, 0x14ff, 0xc12c, 0x21, 0 + .dw 0x1540, 0xc12c, 0x157f, 0xc12c, 0x21, 0 + .dw 0x15c0, 0xc12c, 0x15ff, 0xc12c, 0x21, 0 + .dw 0x1640, 0xc12c, 0x167f, 0xc12c, 0x21, 0 + .dw 0x16c0, 0xc12c, 0x16ff, 0xc12c, 0x21, 0 + .dw 0x1740, 0xc12c, 0x177f, 0xc12c, 0x21, 0 + .dw 0x17c0, 0xc12c, 0x17ff, 0xc12c, 0x21, 0 + .dw 0x1840, 0xc12c, 0x187f, 0xc12c, 0x21, 0 + .dw 0x18c0, 0xc12c, 0x18ff, 0xc12c, 0x21, 0 + .dw 0x1940, 0xc12c, 0x197f, 0xc12c, 0x21, 0 + .dw 0x19c0, 0xc12c, 0x1fff, 0xc12c, 0x21, 0 + .dw 0x2040, 0xc12c, 0x207f, 0xc12c, 0x21, 0 + .dw 0x20c0, 0xc12c, 0x20ff, 0xc12c, 0x21, 0 + .dw 0x2140, 0xc12c, 0x217f, 0xc12c, 0x21, 0 + .dw 0x21c0, 0xc12c, 0x21ff, 0xc12c, 0x21, 0 + .dw 0x2240, 0xc12c, 0x227f, 0xc12c, 0x21, 0 + .dw 0x22c0, 0xc12c, 0x22ff, 0xc12c, 0x21, 0 + .dw 0x2340, 0xc12c, 0x237f, 0xc12c, 0x21, 0 + .dw 0x23c0, 0xc12c, 0x23ff, 0xc12c, 0x21, 0 + .dw 0x2440, 0xc12c, 0x247f, 0xc12c, 0x21, 0 + .dw 0x24c0, 0xc12c, 0x24ff, 0xc12c, 0x21, 0 + .dw 0x2540, 0xc12c, 0x257f, 0xc12c, 0x21, 0 + .dw 0x25c0, 0xc12c, 0x25ff, 0xc12c, 0x21, 0 + .dw 0x2640, 0xc12c, 0x267f, 0xc12c, 0x21, 0 + .dw 0x26c0, 0xc12c, 0x26ff, 0xc12c, 0x21, 0 + .dw 0x2740, 0xc12c, 0x277f, 0xc12c, 0x21, 0 + .dw 0x27c0, 0xc12c, 0x27ff, 0xc12c, 0x21, 0 + .dw 0x2840, 0xc12c, 0x287f, 0xc12c, 0x21, 0 + .dw 0x28c0, 0xc12c, 0x28ff, 0xc12c, 0x21, 0 + .dw 0x2940, 0xc12c, 0x297f, 0xc12c, 0x21, 0 + .dw 0x29c0, 0xc12c, 0x29ff, 0xc12c, 0x21, 0 + .dw 0x2a40, 0xc12c, 0x2a7f, 0xc12c, 0x21, 0 + .dw 0x2ac0, 0xc12c, 0x2aff, 0xc12c, 0x21, 0 + .dw 0x2b40, 0xc12c, 0x2b7f, 0xc12c, 0x21, 0 + .dw 0x2bc0, 0xc12c, 0x2bff, 0xc12c, 0x21, 0 + .dw 0x2c40, 0xc12c, 0x2c7f, 0xc12c, 0x21, 0 + .dw 0x2cc0, 0xc12c, 0x2cff, 0xc12c, 0x21, 0 + .dw 0x2d40, 0xc12c, 0x2d7f, 0xc12c, 0x21, 0 + .dw 0x2dc0, 0xc12c, 0x2dff, 0xc12c, 0x21, 0 + .dw 0x2e40, 0xc12c, 0x2e7f, 0xc12c, 0x21, 0 + .dw 0x2ec0, 0xc12c, 0x2eff, 0xc12c, 0x21, 0 + .dw 0x2f40, 0xc12c, 0x2f7f, 0xc12c, 0x21, 0 + .dw 0x2fc0, 0xc12c, 0x2fff, 0xc12c, 0x21, 0 + .dw 0x3040, 0xc12c, 0x307f, 0xc12c, 0x21, 0 + .dw 0x30c0, 0xc12c, 0x30ff, 0xc12c, 0x21, 0 + .dw 0x3140, 0xc12c, 0x317f, 0xc12c, 0x21, 0 + .dw 0x31c0, 0xc12c, 0x31ff, 0xc12c, 0x21, 0 + .dw 0x3240, 0xc12c, 0x327f, 0xc12c, 0x21, 0 + .dw 0x32c0, 0xc12c, 0x32ff, 0xc12c, 0x21, 0 + .dw 0x3340, 0xc12c, 0x337f, 0xc12c, 0x21, 0 + .dw 0x33c0, 0xc12c, 0x33ff, 0xc12c, 0x21, 0 + .dw 0x3440, 0xc12c, 0x347f, 0xc12c, 0x21, 0 + .dw 0x34c0, 0xc12c, 0x34ff, 0xc12c, 0x21, 0 + .dw 0x3540, 0xc12c, 0x357f, 0xc12c, 0x21, 0 + .dw 0x35c0, 0xc12c, 0x35ff, 0xc12c, 0x21, 0 + .dw 0x3640, 0xc12c, 0x367f, 0xc12c, 0x21, 0 + .dw 0x36c0, 0xc12c, 0x36ff, 0xc12c, 0x21, 0 + .dw 0x3740, 0xc12c, 0x377f, 0xc12c, 0x21, 0 + .dw 0x37c0, 0xc12c, 0x37ff, 0xc12c, 0x21, 0 + .dw 0x3840, 0xc12c, 0x387f, 0xc12c, 0x21, 0 + .dw 0x38c0, 0xc12c, 0x38ff, 0xc12c, 0x21, 0 + .dw 0x3940, 0xc12c, 0x397f, 0xc12c, 0x21, 0 + .dw 0x39c0, 0xc12c, 0x3fff, 0xc12c, 0x21, 0 + .dw 0x4040, 0xc12c, 0x407f, 0xc12c, 0x21, 0 + .dw 0x40c0, 0xc12c, 0x40ff, 0xc12c, 0x21, 0 + .dw 0x4140, 0xc12c, 0x417f, 0xc12c, 0x21, 0 + .dw 0x41c0, 0xc12c, 0x41ff, 0xc12c, 0x21, 0 + .dw 0x4240, 0xc12c, 0x427f, 0xc12c, 0x21, 0 + .dw 0x42c0, 0xc12c, 0x42ff, 0xc12c, 0x21, 0 + .dw 0x4340, 0xc12c, 0x437f, 0xc12c, 0x21, 0 + .dw 0x43c0, 0xc12c, 0x43ff, 0xc12c, 0x21, 0 + .dw 0x4440, 0xc12c, 0x447f, 0xc12c, 0x21, 0 + .dw 0x44c0, 0xc12c, 0x44ff, 0xc12c, 0x21, 0 + .dw 0x4540, 0xc12c, 0x457f, 0xc12c, 0x21, 0 + .dw 0x45c0, 0xc12c, 0x45ff, 0xc12c, 0x21, 0 + .dw 0x4640, 0xc12c, 0x467f, 0xc12c, 0x21, 0 + .dw 0x46c0, 0xc12c, 0x46ff, 0xc12c, 0x21, 0 + .dw 0x4740, 0xc12c, 0x477f, 0xc12c, 0x21, 0 + .dw 0x47c0, 0xc12c, 0x47ff, 0xc12c, 0x21, 0 + .dw 0x4840, 0xc12c, 0x487f, 0xc12c, 0x21, 0 + .dw 0x48c0, 0xc12c, 0x48ff, 0xc12c, 0x21, 0 + .dw 0x4940, 0xc12c, 0x497f, 0xc12c, 0x21, 0 + .dw 0x49c0, 0xc12c, 0x49ff, 0xc12c, 0x21, 0 + .dw 0x4a40, 0xc12c, 0x4a7f, 0xc12c, 0x21, 0 + .dw 0x4ac0, 0xc12c, 0x4aff, 0xc12c, 0x21, 0 + .dw 0x4b40, 0xc12c, 0x4b7f, 0xc12c, 0x21, 0 + .dw 0x4bc0, 0xc12c, 0x4bff, 0xc12c, 0x21, 0 + .dw 0x4c40, 0xc12c, 0x4c7f, 0xc12c, 0x21, 0 + .dw 0x4cc0, 0xc12c, 0x4cff, 0xc12c, 0x21, 0 + .dw 0x4d40, 0xc12c, 0x4d7f, 0xc12c, 0x21, 0 + .dw 0x4dc0, 0xc12c, 0x4dff, 0xc12c, 0x21, 0 + .dw 0x4e40, 0xc12c, 0x4e7f, 0xc12c, 0x21, 0 + .dw 0x4ec0, 0xc12c, 0x4eff, 0xc12c, 0x21, 0 + .dw 0x4f40, 0xc12c, 0x4f7f, 0xc12c, 0x21, 0 + .dw 0x4fc0, 0xc12c, 0x4fff, 0xc12c, 0x21, 0 + .dw 0x5040, 0xc12c, 0x507f, 0xc12c, 0x21, 0 + .dw 0x50c0, 0xc12c, 0x50ff, 0xc12c, 0x21, 0 + .dw 0x5140, 0xc12c, 0x517f, 0xc12c, 0x21, 0 + .dw 0x51c0, 0xc12c, 0x51ff, 0xc12c, 0x21, 0 + .dw 0x5240, 0xc12c, 0x527f, 0xc12c, 0x21, 0 + .dw 0x52c0, 0xc12c, 0x52ff, 0xc12c, 0x21, 0 + .dw 0x5340, 0xc12c, 0x537f, 0xc12c, 0x21, 0 + .dw 0x53c0, 0xc12c, 0x53ff, 0xc12c, 0x21, 0 + .dw 0x5440, 0xc12c, 0x547f, 0xc12c, 0x21, 0 + .dw 0x54c0, 0xc12c, 0x54ff, 0xc12c, 0x21, 0 + .dw 0x5540, 0xc12c, 0x557f, 0xc12c, 0x21, 0 + .dw 0x55c0, 0xc12c, 0x55ff, 0xc12c, 0x21, 0 + .dw 0x5640, 0xc12c, 0x567f, 0xc12c, 0x21, 0 + .dw 0x56c0, 0xc12c, 0x56ff, 0xc12c, 0x21, 0 + .dw 0x5740, 0xc12c, 0x577f, 0xc12c, 0x21, 0 + .dw 0x57c0, 0xc12c, 0x57ff, 0xc12c, 0x21, 0 + .dw 0x5840, 0xc12c, 0x587f, 0xc12c, 0x21, 0 + .dw 0x58c0, 0xc12c, 0x58ff, 0xc12c, 0x21, 0 + .dw 0x5940, 0xc12c, 0x597f, 0xc12c, 0x21, 0 + .dw 0x59c0, 0xc12c, 0x5fff, 0xc12c, 0x21, 0 + .dw 0x6040, 0xc12c, 0x607f, 0xc12c, 0x21, 0 + .dw 0x60c0, 0xc12c, 0x60ff, 0xc12c, 0x21, 0 + .dw 0x6140, 0xc12c, 0x617f, 0xc12c, 0x21, 0 + .dw 0x61c0, 0xc12c, 0x61ff, 0xc12c, 0x21, 0 + .dw 0x6240, 0xc12c, 0x627f, 0xc12c, 0x21, 0 + .dw 0x62c0, 0xc12c, 0x62ff, 0xc12c, 0x21, 0 + .dw 0x6340, 0xc12c, 0x637f, 0xc12c, 0x21, 0 + .dw 0x63c0, 0xc12c, 0x63ff, 0xc12c, 0x21, 0 + .dw 0x6440, 0xc12c, 0x647f, 0xc12c, 0x21, 0 + .dw 0x64c0, 0xc12c, 0x64ff, 0xc12c, 0x21, 0 + .dw 0x6540, 0xc12c, 0x657f, 0xc12c, 0x21, 0 + .dw 0x65c0, 0xc12c, 0x65ff, 0xc12c, 0x21, 0 + .dw 0x6640, 0xc12c, 0x667f, 0xc12c, 0x21, 0 + .dw 0x66c0, 0xc12c, 0x66ff, 0xc12c, 0x21, 0 + .dw 0x6740, 0xc12c, 0x677f, 0xc12c, 0x21, 0 + .dw 0x67c0, 0xc12c, 0x67ff, 0xc12c, 0x21, 0 + .dw 0x6840, 0xc12c, 0x687f, 0xc12c, 0x21, 0 + .dw 0x68c0, 0xc12c, 0x68ff, 0xc12c, 0x21, 0 + .dw 0x6940, 0xc12c, 0x697f, 0xc12c, 0x21, 0 + .dw 0x69c0, 0xc12c, 0x69ff, 0xc12c, 0x21, 0 + .dw 0x6a40, 0xc12c, 0x6a7f, 0xc12c, 0x21, 0 + .dw 0x6ac0, 0xc12c, 0x6aff, 0xc12c, 0x21, 0 + .dw 0x6b40, 0xc12c, 0x6b7f, 0xc12c, 0x21, 0 + .dw 0x6bc0, 0xc12c, 0x6bff, 0xc12c, 0x21, 0 + .dw 0x6c40, 0xc12c, 0x6c7f, 0xc12c, 0x21, 0 + .dw 0x6cc0, 0xc12c, 0x6cff, 0xc12c, 0x21, 0 + .dw 0x6d40, 0xc12c, 0x6d7f, 0xc12c, 0x21, 0 + .dw 0x6dc0, 0xc12c, 0x6dff, 0xc12c, 0x21, 0 + .dw 0x6e40, 0xc12c, 0x6e7f, 0xc12c, 0x21, 0 + .dw 0x6ec0, 0xc12c, 0x6eff, 0xc12c, 0x21, 0 + .dw 0x6f40, 0xc12c, 0x6f7f, 0xc12c, 0x21, 0 + .dw 0x6fc0, 0xc12c, 0x6fff, 0xc12c, 0x21, 0 + .dw 0x7040, 0xc12c, 0x707f, 0xc12c, 0x21, 0 + .dw 0x70c0, 0xc12c, 0x70ff, 0xc12c, 0x21, 0 + .dw 0x7140, 0xc12c, 0x717f, 0xc12c, 0x21, 0 + .dw 0x71c0, 0xc12c, 0x71ff, 0xc12c, 0x21, 0 + .dw 0x7240, 0xc12c, 0x727f, 0xc12c, 0x21, 0 + .dw 0x72c0, 0xc12c, 0x72ff, 0xc12c, 0x21, 0 + .dw 0x7340, 0xc12c, 0x737f, 0xc12c, 0x21, 0 + .dw 0x73c0, 0xc12c, 0x73ff, 0xc12c, 0x21, 0 + .dw 0x7440, 0xc12c, 0x747f, 0xc12c, 0x21, 0 + .dw 0x74c0, 0xc12c, 0x74ff, 0xc12c, 0x21, 0 + .dw 0x7540, 0xc12c, 0x757f, 0xc12c, 0x21, 0 + .dw 0x75c0, 0xc12c, 0x75ff, 0xc12c, 0x21, 0 + .dw 0x7640, 0xc12c, 0x767f, 0xc12c, 0x21, 0 + .dw 0x76c0, 0xc12c, 0x76ff, 0xc12c, 0x21, 0 + .dw 0x7740, 0xc12c, 0x777f, 0xc12c, 0x21, 0 + .dw 0x77c0, 0xc12c, 0x77ff, 0xc12c, 0x21, 0 + .dw 0x7840, 0xc12c, 0x787f, 0xc12c, 0x21, 0 + .dw 0x78c0, 0xc12c, 0x78ff, 0xc12c, 0x21, 0 + .dw 0x7940, 0xc12c, 0x797f, 0xc12c, 0x21, 0 + .dw 0x79c0, 0xc12c, 0x7fff, 0xc12c, 0x21, 0 + .dw 0x8040, 0xc12c, 0x807f, 0xc12c, 0x21, 0 + .dw 0x80c0, 0xc12c, 0x80ff, 0xc12c, 0x21, 0 + .dw 0x8140, 0xc12c, 0x817f, 0xc12c, 0x21, 0 + .dw 0x81c0, 0xc12c, 0x81ff, 0xc12c, 0x21, 0 + .dw 0x8240, 0xc12c, 0x827f, 0xc12c, 0x21, 0 + .dw 0x82c0, 0xc12c, 0x82ff, 0xc12c, 0x21, 0 + .dw 0x8340, 0xc12c, 0x837f, 0xc12c, 0x21, 0 + .dw 0x83c0, 0xc12c, 0x83ff, 0xc12c, 0x21, 0 + .dw 0x8440, 0xc12c, 0x847f, 0xc12c, 0x21, 0 + .dw 0x84c0, 0xc12c, 0x84ff, 0xc12c, 0x21, 0 + .dw 0x8540, 0xc12c, 0x857f, 0xc12c, 0x21, 0 + .dw 0x85c0, 0xc12c, 0x85ff, 0xc12c, 0x21, 0 + .dw 0x8640, 0xc12c, 0x867f, 0xc12c, 0x21, 0 + .dw 0x86c0, 0xc12c, 0x86ff, 0xc12c, 0x21, 0 + .dw 0x8740, 0xc12c, 0x877f, 0xc12c, 0x21, 0 + .dw 0x87c0, 0xc12c, 0x87ff, 0xc12c, 0x21, 0 + .dw 0x8840, 0xc12c, 0x887f, 0xc12c, 0x21, 0 + .dw 0x88c0, 0xc12c, 0x88ff, 0xc12c, 0x21, 0 + .dw 0x8940, 0xc12c, 0x897f, 0xc12c, 0x21, 0 + .dw 0x89c0, 0xc12c, 0x89ff, 0xc12c, 0x21, 0 + .dw 0x8a40, 0xc12c, 0x8a7f, 0xc12c, 0x21, 0 + .dw 0x8ac0, 0xc12c, 0x8aff, 0xc12c, 0x21, 0 + .dw 0x8b40, 0xc12c, 0x8b7f, 0xc12c, 0x21, 0 + .dw 0x8bc0, 0xc12c, 0x8bff, 0xc12c, 0x21, 0 + .dw 0x8c40, 0xc12c, 0x8c7f, 0xc12c, 0x21, 0 + .dw 0x8cc0, 0xc12c, 0x8cff, 0xc12c, 0x21, 0 + .dw 0x8d40, 0xc12c, 0x8d7f, 0xc12c, 0x21, 0 + .dw 0x8dc0, 0xc12c, 0x8dff, 0xc12c, 0x21, 0 + .dw 0x8e40, 0xc12c, 0x8e7f, 0xc12c, 0x21, 0 + .dw 0x8ec0, 0xc12c, 0x8eff, 0xc12c, 0x21, 0 + .dw 0x8f40, 0xc12c, 0x8f7f, 0xc12c, 0x21, 0 + .dw 0x8fc0, 0xc12c, 0x8fff, 0xc12c, 0x21, 0 + .dw 0x9040, 0xc12c, 0x907f, 0xc12c, 0x21, 0 + .dw 0x90c0, 0xc12c, 0x90ff, 0xc12c, 0x21, 0 + .dw 0x9140, 0xc12c, 0x917f, 0xc12c, 0x21, 0 + .dw 0x91c0, 0xc12c, 0x91ff, 0xc12c, 0x21, 0 + .dw 0x9240, 0xc12c, 0x927f, 0xc12c, 0x21, 0 + .dw 0x92c0, 0xc12c, 0x92ff, 0xc12c, 0x21, 0 + .dw 0x9340, 0xc12c, 0x937f, 0xc12c, 0x21, 0 + .dw 0x93c0, 0xc12c, 0x93ff, 0xc12c, 0x21, 0 + .dw 0x9440, 0xc12c, 0x947f, 0xc12c, 0x21, 0 + .dw 0x94c0, 0xc12c, 0x94ff, 0xc12c, 0x21, 0 + .dw 0x9540, 0xc12c, 0x957f, 0xc12c, 0x21, 0 + .dw 0x95c0, 0xc12c, 0x95ff, 0xc12c, 0x21, 0 + .dw 0x9640, 0xc12c, 0x967f, 0xc12c, 0x21, 0 + .dw 0x96c0, 0xc12c, 0x96ff, 0xc12c, 0x21, 0 + .dw 0x9740, 0xc12c, 0x977f, 0xc12c, 0x21, 0 + .dw 0x97c0, 0xc12c, 0x97ff, 0xc12c, 0x21, 0 + .dw 0x9840, 0xc12c, 0x987f, 0xc12c, 0x21, 0 + .dw 0x98c0, 0xc12c, 0x98ff, 0xc12c, 0x21, 0 + .dw 0x9940, 0xc12c, 0x997f, 0xc12c, 0x21, 0 + .dw 0x99c0, 0xc12c, 0x9fff, 0xc12c, 0x21, 0 + .dw 0xa040, 0xc12c, 0xa07f, 0xc12c, 0x21, 0 + .dw 0xa0c0, 0xc12c, 0xa0ff, 0xc12c, 0x21, 0 + .dw 0xa140, 0xc12c, 0xa17f, 0xc12c, 0x21, 0 + .dw 0xa1c0, 0xc12c, 0xa1ff, 0xc12c, 0x21, 0 + .dw 0xa240, 0xc12c, 0xa27f, 0xc12c, 0x21, 0 + .dw 0xa2c0, 0xc12c, 0xa2ff, 0xc12c, 0x21, 0 + .dw 0xa340, 0xc12c, 0xa37f, 0xc12c, 0x21, 0 + .dw 0xa3c0, 0xc12c, 0xa3ff, 0xc12c, 0x21, 0 + .dw 0xa440, 0xc12c, 0xa47f, 0xc12c, 0x21, 0 + .dw 0xa4c0, 0xc12c, 0xa4ff, 0xc12c, 0x21, 0 + .dw 0xa540, 0xc12c, 0xa57f, 0xc12c, 0x21, 0 + .dw 0xa5c0, 0xc12c, 0xa5ff, 0xc12c, 0x21, 0 + .dw 0xa640, 0xc12c, 0xa67f, 0xc12c, 0x21, 0 + .dw 0xa6c0, 0xc12c, 0xa6ff, 0xc12c, 0x21, 0 + .dw 0xa740, 0xc12c, 0xa77f, 0xc12c, 0x21, 0 + .dw 0xa7c0, 0xc12c, 0xa7ff, 0xc12c, 0x21, 0 + .dw 0xa840, 0xc12c, 0xa87f, 0xc12c, 0x21, 0 + .dw 0xa8c0, 0xc12c, 0xa8ff, 0xc12c, 0x21, 0 + .dw 0xa940, 0xc12c, 0xa97f, 0xc12c, 0x21, 0 + .dw 0xa9c0, 0xc12c, 0xa9ff, 0xc12c, 0x21, 0 + .dw 0xaa40, 0xc12c, 0xaa7f, 0xc12c, 0x21, 0 + .dw 0xaac0, 0xc12c, 0xaaff, 0xc12c, 0x21, 0 + .dw 0xab40, 0xc12c, 0xab7f, 0xc12c, 0x21, 0 + .dw 0xabc0, 0xc12c, 0xabff, 0xc12c, 0x21, 0 + .dw 0xac40, 0xc12c, 0xac7f, 0xc12c, 0x21, 0 + .dw 0xacc0, 0xc12c, 0xacff, 0xc12c, 0x21, 0 + .dw 0xad40, 0xc12c, 0xad7f, 0xc12c, 0x21, 0 + .dw 0xadc0, 0xc12c, 0xadff, 0xc12c, 0x21, 0 + .dw 0xae40, 0xc12c, 0xae7f, 0xc12c, 0x21, 0 + .dw 0xaec0, 0xc12c, 0xaeff, 0xc12c, 0x21, 0 + .dw 0xaf40, 0xc12c, 0xaf7f, 0xc12c, 0x21, 0 + .dw 0xafc0, 0xc12c, 0xafff, 0xc12c, 0x21, 0 + .dw 0xb040, 0xc12c, 0xb07f, 0xc12c, 0x21, 0 + .dw 0xb0c0, 0xc12c, 0xb0ff, 0xc12c, 0x21, 0 + .dw 0xb140, 0xc12c, 0xb17f, 0xc12c, 0x21, 0 + .dw 0xb1c0, 0xc12c, 0xb1ff, 0xc12c, 0x21, 0 + .dw 0xb240, 0xc12c, 0xb27f, 0xc12c, 0x21, 0 + .dw 0xb2c0, 0xc12c, 0xb2ff, 0xc12c, 0x21, 0 + .dw 0xb340, 0xc12c, 0xb37f, 0xc12c, 0x21, 0 + .dw 0xb3c0, 0xc12c, 0xb3ff, 0xc12c, 0x21, 0 + .dw 0xb440, 0xc12c, 0xb47f, 0xc12c, 0x21, 0 + .dw 0xb4c0, 0xc12c, 0xb4ff, 0xc12c, 0x21, 0 + .dw 0xb540, 0xc12c, 0xb57f, 0xc12c, 0x21, 0 + .dw 0xb5c0, 0xc12c, 0xb5ff, 0xc12c, 0x21, 0 + .dw 0xb640, 0xc12c, 0xb67f, 0xc12c, 0x21, 0 + .dw 0xb6c0, 0xc12c, 0xb6ff, 0xc12c, 0x21, 0 + .dw 0xb740, 0xc12c, 0xb77f, 0xc12c, 0x21, 0 + .dw 0xb7c0, 0xc12c, 0xb7ff, 0xc12c, 0x21, 0 + .dw 0xb840, 0xc12c, 0xb87f, 0xc12c, 0x21, 0 + .dw 0xb8c0, 0xc12c, 0xb8ff, 0xc12c, 0x21, 0 + .dw 0xb940, 0xc12c, 0xb97f, 0xc12c, 0x21, 0 + .dw 0xb9c0, 0xc12c, 0xbfff, 0xc12c, 0x21, 0 + .dw 0xc040, 0xc12c, 0xc07f, 0xc12c, 0x21, 0 + .dw 0xc0c0, 0xc12c, 0xc0ff, 0xc12c, 0x21, 0 + .dw 0xc140, 0xc12c, 0xc17f, 0xc12c, 0x21, 0 + .dw 0xc1c0, 0xc12c, 0xc1ff, 0xc12c, 0x21, 0 + .dw 0xc240, 0xc12c, 0xc27f, 0xc12c, 0x21, 0 + .dw 0xc2c0, 0xc12c, 0xc2ff, 0xc12c, 0x21, 0 + .dw 0xc340, 0xc12c, 0xc37f, 0xc12c, 0x21, 0 + .dw 0xc3c0, 0xc12c, 0xc3ff, 0xc12c, 0x21, 0 + .dw 0xc440, 0xc12c, 0xc47f, 0xc12c, 0x21, 0 + .dw 0xc4c0, 0xc12c, 0xc4ff, 0xc12c, 0x21, 0 + .dw 0xc540, 0xc12c, 0xc57f, 0xc12c, 0x21, 0 + .dw 0xc5c0, 0xc12c, 0xc5ff, 0xc12c, 0x21, 0 + .dw 0xc640, 0xc12c, 0xc67f, 0xc12c, 0x21, 0 + .dw 0xc6c0, 0xc12c, 0xc6ff, 0xc12c, 0x21, 0 + .dw 0xc740, 0xc12c, 0xc77f, 0xc12c, 0x21, 0 + .dw 0xc7c0, 0xc12c, 0xc7ff, 0xc12c, 0x21, 0 + .dw 0xc840, 0xc12c, 0xc87f, 0xc12c, 0x21, 0 + .dw 0xc8c0, 0xc12c, 0xc8ff, 0xc12c, 0x21, 0 + .dw 0xc940, 0xc12c, 0xc97f, 0xc12c, 0x21, 0 + .dw 0xc9c0, 0xc12c, 0xc9ff, 0xc12c, 0x21, 0 + .dw 0xca40, 0xc12c, 0xca7f, 0xc12c, 0x21, 0 + .dw 0xcac0, 0xc12c, 0xcaff, 0xc12c, 0x21, 0 + .dw 0xcb40, 0xc12c, 0xcb7f, 0xc12c, 0x21, 0 + .dw 0xcbc0, 0xc12c, 0xcbff, 0xc12c, 0x21, 0 + .dw 0xcc40, 0xc12c, 0xcc7f, 0xc12c, 0x21, 0 + .dw 0xccc0, 0xc12c, 0xccff, 0xc12c, 0x21, 0 + .dw 0xcd40, 0xc12c, 0xcd7f, 0xc12c, 0x21, 0 + .dw 0xcdc0, 0xc12c, 0xcdff, 0xc12c, 0x21, 0 + .dw 0xce40, 0xc12c, 0xce7f, 0xc12c, 0x21, 0 + .dw 0xcec0, 0xc12c, 0xceff, 0xc12c, 0x21, 0 + .dw 0xcf40, 0xc12c, 0xcf7f, 0xc12c, 0x21, 0 + .dw 0xcfc0, 0xc12c, 0xcfff, 0xc12c, 0x21, 0 + .dw 0xd040, 0xc12c, 0xd07f, 0xc12c, 0x21, 0 + .dw 0xd0c0, 0xc12c, 0xd0ff, 0xc12c, 0x21, 0 + .dw 0xd140, 0xc12c, 0xd17f, 0xc12c, 0x21, 0 + .dw 0xd1c0, 0xc12c, 0xd1ff, 0xc12c, 0x21, 0 + .dw 0xd240, 0xc12c, 0xd27f, 0xc12c, 0x21, 0 + .dw 0xd2c0, 0xc12c, 0xd2ff, 0xc12c, 0x21, 0 + .dw 0xd340, 0xc12c, 0xd37f, 0xc12c, 0x21, 0 + .dw 0xd3c0, 0xc12c, 0xd3ff, 0xc12c, 0x21, 0 + .dw 0xd440, 0xc12c, 0xd47f, 0xc12c, 0x21, 0 + .dw 0xd4c0, 0xc12c, 0xd4ff, 0xc12c, 0x21, 0 + .dw 0xd540, 0xc12c, 0xd57f, 0xc12c, 0x21, 0 + .dw 0xd5c0, 0xc12c, 0xd5ff, 0xc12c, 0x21, 0 + .dw 0xd640, 0xc12c, 0xd67f, 0xc12c, 0x21, 0 + .dw 0xd6c0, 0xc12c, 0xd6ff, 0xc12c, 0x21, 0 + .dw 0xd740, 0xc12c, 0xd77f, 0xc12c, 0x21, 0 + .dw 0xd7c0, 0xc12c, 0xd7ff, 0xc12c, 0x21, 0 + .dw 0xd840, 0xc12c, 0xd87f, 0xc12c, 0x21, 0 + .dw 0xd8c0, 0xc12c, 0xd8ff, 0xc12c, 0x21, 0 + .dw 0xd940, 0xc12c, 0xd97f, 0xc12c, 0x21, 0 + .dw 0xd9c0, 0xc12c, 0xdfff, 0xc12c, 0x21, 0 + .dw 0xe040, 0xc12c, 0xe07f, 0xc12c, 0x21, 0 + .dw 0xe0c0, 0xc12c, 0xe0ff, 0xc12c, 0x21, 0 + .dw 0xe140, 0xc12c, 0xe17f, 0xc12c, 0x21, 0 + .dw 0xe1c0, 0xc12c, 0xe1ff, 0xc12c, 0x21, 0 + .dw 0xe240, 0xc12c, 0xe27f, 0xc12c, 0x21, 0 + .dw 0xe2c0, 0xc12c, 0xe2ff, 0xc12c, 0x21, 0 + .dw 0xe340, 0xc12c, 0xe37f, 0xc12c, 0x21, 0 + .dw 0xe3c0, 0xc12c, 0xe3ff, 0xc12c, 0x21, 0 + .dw 0xe440, 0xc12c, 0xe47f, 0xc12c, 0x21, 0 + .dw 0xe4c0, 0xc12c, 0xe4ff, 0xc12c, 0x21, 0 + .dw 0xe540, 0xc12c, 0xe57f, 0xc12c, 0x21, 0 + .dw 0xe5c0, 0xc12c, 0xe5ff, 0xc12c, 0x21, 0 + .dw 0xe640, 0xc12c, 0xe67f, 0xc12c, 0x21, 0 + .dw 0xe6c0, 0xc12c, 0xe6ff, 0xc12c, 0x21, 0 + .dw 0xe740, 0xc12c, 0xe77f, 0xc12c, 0x21, 0 + .dw 0xe7c0, 0xc12c, 0xe7ff, 0xc12c, 0x21, 0 + .dw 0xe840, 0xc12c, 0xe87f, 0xc12c, 0x21, 0 + .dw 0xe8c0, 0xc12c, 0xe8ff, 0xc12c, 0x21, 0 + .dw 0xe940, 0xc12c, 0xe97f, 0xc12c, 0x21, 0 + .dw 0xe9c0, 0xc12c, 0xe9ff, 0xc12c, 0x21, 0 + .dw 0xea40, 0xc12c, 0xea7f, 0xc12c, 0x21, 0 + .dw 0xeac0, 0xc12c, 0xeaff, 0xc12c, 0x21, 0 + .dw 0xeb40, 0xc12c, 0xeb7f, 0xc12c, 0x21, 0 + .dw 0xebc0, 0xc12c, 0xebff, 0xc12c, 0x21, 0 + .dw 0xec40, 0xc12c, 0xec7f, 0xc12c, 0x21, 0 + .dw 0xecc0, 0xc12c, 0xecff, 0xc12c, 0x21, 0 + .dw 0xed40, 0xc12c, 0xed7f, 0xc12c, 0x21, 0 + .dw 0xedc0, 0xc12c, 0xedff, 0xc12c, 0x21, 0 + .dw 0xee40, 0xc12c, 0xee7f, 0xc12c, 0x21, 0 + .dw 0xeec0, 0xc12c, 0xeeff, 0xc12c, 0x21, 0 + .dw 0xef40, 0xc12c, 0xef7f, 0xc12c, 0x21, 0 + .dw 0xefc0, 0xc12c, 0xefff, 0xc12c, 0x21, 0 + .dw 0xf040, 0xc12c, 0xf07f, 0xc12c, 0x21, 0 + .dw 0xf0c0, 0xc12c, 0xf0ff, 0xc12c, 0x21, 0 + .dw 0xf140, 0xc12c, 0xf17f, 0xc12c, 0x21, 0 + .dw 0xf1c0, 0xc12c, 0xf1ff, 0xc12c, 0x21, 0 + .dw 0xf240, 0xc12c, 0xf27f, 0xc12c, 0x21, 0 + .dw 0xf2c0, 0xc12c, 0xf2ff, 0xc12c, 0x21, 0 + .dw 0xf340, 0xc12c, 0xf37f, 0xc12c, 0x21, 0 + .dw 0xf3c0, 0xc12c, 0xf3ff, 0xc12c, 0x21, 0 + .dw 0xf440, 0xc12c, 0xf47f, 0xc12c, 0x21, 0 + .dw 0xf4c0, 0xc12c, 0xf4ff, 0xc12c, 0x21, 0 + .dw 0xf540, 0xc12c, 0xf57f, 0xc12c, 0x21, 0 + .dw 0xf5c0, 0xc12c, 0xf5ff, 0xc12c, 0x21, 0 + .dw 0xf640, 0xc12c, 0xf67f, 0xc12c, 0x21, 0 + .dw 0xf6c0, 0xc12c, 0xf6ff, 0xc12c, 0x21, 0 + .dw 0xf740, 0xc12c, 0xf77f, 0xc12c, 0x21, 0 + .dw 0xf7c0, 0xc12c, 0xf7ff, 0xc12c, 0x21, 0 + .dw 0xf840, 0xc12c, 0xf87f, 0xc12c, 0x21, 0 + .dw 0xf8c0, 0xc12c, 0xf8ff, 0xc12c, 0x21, 0 + .dw 0xf940, 0xc12c, 0xf97f, 0xc12c, 0x21, 0 + .dw 0xf9c0, 0xc12c, 0xffff, 0xc12c, 0x21, 0 + .dw 0x0040, 0xc12d, 0x007f, 0xc12d, 0x21, 0 + .dw 0x00c0, 0xc12d, 0x00ff, 0xc12d, 0x21, 0 + .dw 0x0140, 0xc12d, 0x017f, 0xc12d, 0x21, 0 + .dw 0x01c0, 0xc12d, 0x01ff, 0xc12d, 0x21, 0 + .dw 0x0240, 0xc12d, 0x027f, 0xc12d, 0x21, 0 + .dw 0x02c0, 0xc12d, 0x02ff, 0xc12d, 0x21, 0 + .dw 0x0340, 0xc12d, 0x037f, 0xc12d, 0x21, 0 + .dw 0x03c0, 0xc12d, 0x03ff, 0xc12d, 0x21, 0 + .dw 0x0440, 0xc12d, 0x047f, 0xc12d, 0x21, 0 + .dw 0x04c0, 0xc12d, 0x04ff, 0xc12d, 0x21, 0 + .dw 0x0540, 0xc12d, 0x057f, 0xc12d, 0x21, 0 + .dw 0x05c0, 0xc12d, 0x05ff, 0xc12d, 0x21, 0 + .dw 0x0640, 0xc12d, 0x067f, 0xc12d, 0x21, 0 + .dw 0x06c0, 0xc12d, 0x06ff, 0xc12d, 0x21, 0 + .dw 0x0740, 0xc12d, 0x077f, 0xc12d, 0x21, 0 + .dw 0x07c0, 0xc12d, 0x07ff, 0xc12d, 0x21, 0 + .dw 0x0840, 0xc12d, 0x087f, 0xc12d, 0x21, 0 + .dw 0x08c0, 0xc12d, 0x08ff, 0xc12d, 0x21, 0 + .dw 0x0940, 0xc12d, 0x097f, 0xc12d, 0x21, 0 + .dw 0x09c0, 0xc12d, 0x09ff, 0xc12d, 0x21, 0 + .dw 0x0a40, 0xc12d, 0x0a7f, 0xc12d, 0x21, 0 + .dw 0x0ac0, 0xc12d, 0x0aff, 0xc12d, 0x21, 0 + .dw 0x0b40, 0xc12d, 0x0b7f, 0xc12d, 0x21, 0 + .dw 0x0bc0, 0xc12d, 0x0bff, 0xc12d, 0x21, 0 + .dw 0x0c40, 0xc12d, 0x0c7f, 0xc12d, 0x21, 0 + .dw 0x0cc0, 0xc12d, 0x0cff, 0xc12d, 0x21, 0 + .dw 0x0d40, 0xc12d, 0x0d7f, 0xc12d, 0x21, 0 + .dw 0x0dc0, 0xc12d, 0x0dff, 0xc12d, 0x21, 0 + .dw 0x0e40, 0xc12d, 0x0e7f, 0xc12d, 0x21, 0 + .dw 0x0ec0, 0xc12d, 0x0eff, 0xc12d, 0x21, 0 + .dw 0x0f40, 0xc12d, 0x0f7f, 0xc12d, 0x21, 0 + .dw 0x0fc0, 0xc12d, 0x0fff, 0xc12d, 0x21, 0 + .dw 0x1040, 0xc12d, 0x107f, 0xc12d, 0x21, 0 + .dw 0x10c0, 0xc12d, 0x10ff, 0xc12d, 0x21, 0 + .dw 0x1140, 0xc12d, 0x117f, 0xc12d, 0x21, 0 + .dw 0x11c0, 0xc12d, 0x11ff, 0xc12d, 0x21, 0 + .dw 0x1240, 0xc12d, 0x127f, 0xc12d, 0x21, 0 + .dw 0x12c0, 0xc12d, 0x12ff, 0xc12d, 0x21, 0 + .dw 0x1340, 0xc12d, 0x137f, 0xc12d, 0x21, 0 + .dw 0x13c0, 0xc12d, 0x13ff, 0xc12d, 0x21, 0 + .dw 0x1440, 0xc12d, 0x147f, 0xc12d, 0x21, 0 + .dw 0x14c0, 0xc12d, 0x14ff, 0xc12d, 0x21, 0 + .dw 0x1540, 0xc12d, 0x157f, 0xc12d, 0x21, 0 + .dw 0x15c0, 0xc12d, 0x15ff, 0xc12d, 0x21, 0 + .dw 0x1640, 0xc12d, 0x167f, 0xc12d, 0x21, 0 + .dw 0x16c0, 0xc12d, 0x16ff, 0xc12d, 0x21, 0 + .dw 0x1740, 0xc12d, 0x177f, 0xc12d, 0x21, 0 + .dw 0x17c0, 0xc12d, 0x17ff, 0xc12d, 0x21, 0 + .dw 0x1840, 0xc12d, 0x187f, 0xc12d, 0x21, 0 + .dw 0x18c0, 0xc12d, 0x18ff, 0xc12d, 0x21, 0 + .dw 0x1940, 0xc12d, 0x197f, 0xc12d, 0x21, 0 + .dw 0x19c0, 0xc12d, 0x1fff, 0xc12d, 0x21, 0 + .dw 0x2040, 0xc12d, 0x207f, 0xc12d, 0x21, 0 + .dw 0x20c0, 0xc12d, 0x20ff, 0xc12d, 0x21, 0 + .dw 0x2140, 0xc12d, 0x217f, 0xc12d, 0x21, 0 + .dw 0x21c0, 0xc12d, 0x21ff, 0xc12d, 0x21, 0 + .dw 0x2240, 0xc12d, 0x227f, 0xc12d, 0x21, 0 + .dw 0x22c0, 0xc12d, 0x22ff, 0xc12d, 0x21, 0 + .dw 0x2340, 0xc12d, 0x237f, 0xc12d, 0x21, 0 + .dw 0x23c0, 0xc12d, 0x23ff, 0xc12d, 0x21, 0 + .dw 0x2440, 0xc12d, 0x247f, 0xc12d, 0x21, 0 + .dw 0x24c0, 0xc12d, 0x24ff, 0xc12d, 0x21, 0 + .dw 0x2540, 0xc12d, 0x257f, 0xc12d, 0x21, 0 + .dw 0x25c0, 0xc12d, 0x25ff, 0xc12d, 0x21, 0 + .dw 0x2640, 0xc12d, 0x267f, 0xc12d, 0x21, 0 + .dw 0x26c0, 0xc12d, 0x26ff, 0xc12d, 0x21, 0 + .dw 0x2740, 0xc12d, 0x277f, 0xc12d, 0x21, 0 + .dw 0x27c0, 0xc12d, 0x27ff, 0xc12d, 0x21, 0 + .dw 0x2840, 0xc12d, 0x287f, 0xc12d, 0x21, 0 + .dw 0x28c0, 0xc12d, 0x28ff, 0xc12d, 0x21, 0 + .dw 0x2940, 0xc12d, 0x297f, 0xc12d, 0x21, 0 + .dw 0x29c0, 0xc12d, 0x29ff, 0xc12d, 0x21, 0 + .dw 0x2a40, 0xc12d, 0x2a7f, 0xc12d, 0x21, 0 + .dw 0x2ac0, 0xc12d, 0x2aff, 0xc12d, 0x21, 0 + .dw 0x2b40, 0xc12d, 0x2b7f, 0xc12d, 0x21, 0 + .dw 0x2bc0, 0xc12d, 0x2bff, 0xc12d, 0x21, 0 + .dw 0x2c40, 0xc12d, 0x2c7f, 0xc12d, 0x21, 0 + .dw 0x2cc0, 0xc12d, 0x2cff, 0xc12d, 0x21, 0 + .dw 0x2d40, 0xc12d, 0x2d7f, 0xc12d, 0x21, 0 + .dw 0x2dc0, 0xc12d, 0x2dff, 0xc12d, 0x21, 0 + .dw 0x2e40, 0xc12d, 0x2e7f, 0xc12d, 0x21, 0 + .dw 0x2ec0, 0xc12d, 0x2eff, 0xc12d, 0x21, 0 + .dw 0x2f40, 0xc12d, 0x2f7f, 0xc12d, 0x21, 0 + .dw 0x2fc0, 0xc12d, 0x2fff, 0xc12d, 0x21, 0 + .dw 0x3040, 0xc12d, 0x307f, 0xc12d, 0x21, 0 + .dw 0x30c0, 0xc12d, 0x30ff, 0xc12d, 0x21, 0 + .dw 0x3140, 0xc12d, 0x317f, 0xc12d, 0x21, 0 + .dw 0x31c0, 0xc12d, 0x31ff, 0xc12d, 0x21, 0 + .dw 0x3240, 0xc12d, 0x327f, 0xc12d, 0x21, 0 + .dw 0x32c0, 0xc12d, 0x32ff, 0xc12d, 0x21, 0 + .dw 0x3340, 0xc12d, 0x337f, 0xc12d, 0x21, 0 + .dw 0x33c0, 0xc12d, 0x33ff, 0xc12d, 0x21, 0 + .dw 0x3440, 0xc12d, 0x347f, 0xc12d, 0x21, 0 + .dw 0x34c0, 0xc12d, 0x34ff, 0xc12d, 0x21, 0 + .dw 0x3540, 0xc12d, 0x357f, 0xc12d, 0x21, 0 + .dw 0x35c0, 0xc12d, 0x35ff, 0xc12d, 0x21, 0 + .dw 0x3640, 0xc12d, 0x367f, 0xc12d, 0x21, 0 + .dw 0x36c0, 0xc12d, 0x36ff, 0xc12d, 0x21, 0 + .dw 0x3740, 0xc12d, 0x377f, 0xc12d, 0x21, 0 + .dw 0x37c0, 0xc12d, 0x37ff, 0xc12d, 0x21, 0 + .dw 0x3840, 0xc12d, 0x387f, 0xc12d, 0x21, 0 + .dw 0x38c0, 0xc12d, 0x38ff, 0xc12d, 0x21, 0 + .dw 0x3940, 0xc12d, 0x397f, 0xc12d, 0x21, 0 + .dw 0x39c0, 0xc12d, 0x3fff, 0xc12d, 0x21, 0 + .dw 0x4040, 0xc12d, 0x407f, 0xc12d, 0x21, 0 + .dw 0x40c0, 0xc12d, 0x40ff, 0xc12d, 0x21, 0 + .dw 0x4140, 0xc12d, 0x417f, 0xc12d, 0x21, 0 + .dw 0x41c0, 0xc12d, 0x41ff, 0xc12d, 0x21, 0 + .dw 0x4240, 0xc12d, 0x427f, 0xc12d, 0x21, 0 + .dw 0x42c0, 0xc12d, 0x42ff, 0xc12d, 0x21, 0 + .dw 0x4340, 0xc12d, 0x437f, 0xc12d, 0x21, 0 + .dw 0x43c0, 0xc12d, 0x43ff, 0xc12d, 0x21, 0 + .dw 0x4440, 0xc12d, 0x447f, 0xc12d, 0x21, 0 + .dw 0x44c0, 0xc12d, 0x44ff, 0xc12d, 0x21, 0 + .dw 0x4540, 0xc12d, 0x457f, 0xc12d, 0x21, 0 + .dw 0x45c0, 0xc12d, 0x45ff, 0xc12d, 0x21, 0 + .dw 0x4640, 0xc12d, 0x467f, 0xc12d, 0x21, 0 + .dw 0x46c0, 0xc12d, 0x46ff, 0xc12d, 0x21, 0 + .dw 0x4740, 0xc12d, 0x477f, 0xc12d, 0x21, 0 + .dw 0x47c0, 0xc12d, 0x47ff, 0xc12d, 0x21, 0 + .dw 0x4840, 0xc12d, 0x487f, 0xc12d, 0x21, 0 + .dw 0x48c0, 0xc12d, 0x48ff, 0xc12d, 0x21, 0 + .dw 0x4940, 0xc12d, 0x497f, 0xc12d, 0x21, 0 + .dw 0x49c0, 0xc12d, 0x49ff, 0xc12d, 0x21, 0 + .dw 0x4a40, 0xc12d, 0x4a7f, 0xc12d, 0x21, 0 + .dw 0x4ac0, 0xc12d, 0x4aff, 0xc12d, 0x21, 0 + .dw 0x4b40, 0xc12d, 0x4b7f, 0xc12d, 0x21, 0 + .dw 0x4bc0, 0xc12d, 0x4bff, 0xc12d, 0x21, 0 + .dw 0x4c40, 0xc12d, 0x4c7f, 0xc12d, 0x21, 0 + .dw 0x4cc0, 0xc12d, 0x4cff, 0xc12d, 0x21, 0 + .dw 0x4d40, 0xc12d, 0x4d7f, 0xc12d, 0x21, 0 + .dw 0x4dc0, 0xc12d, 0x4dff, 0xc12d, 0x21, 0 + .dw 0x4e40, 0xc12d, 0x4e7f, 0xc12d, 0x21, 0 + .dw 0x4ec0, 0xc12d, 0x4eff, 0xc12d, 0x21, 0 + .dw 0x4f40, 0xc12d, 0x4f7f, 0xc12d, 0x21, 0 + .dw 0x4fc0, 0xc12d, 0x4fff, 0xc12d, 0x21, 0 + .dw 0x5040, 0xc12d, 0x507f, 0xc12d, 0x21, 0 + .dw 0x50c0, 0xc12d, 0x50ff, 0xc12d, 0x21, 0 + .dw 0x5140, 0xc12d, 0x517f, 0xc12d, 0x21, 0 + .dw 0x51c0, 0xc12d, 0x51ff, 0xc12d, 0x21, 0 + .dw 0x5240, 0xc12d, 0x527f, 0xc12d, 0x21, 0 + .dw 0x52c0, 0xc12d, 0x52ff, 0xc12d, 0x21, 0 + .dw 0x5340, 0xc12d, 0x537f, 0xc12d, 0x21, 0 + .dw 0x53c0, 0xc12d, 0x53ff, 0xc12d, 0x21, 0 + .dw 0x5440, 0xc12d, 0x547f, 0xc12d, 0x21, 0 + .dw 0x54c0, 0xc12d, 0x54ff, 0xc12d, 0x21, 0 + .dw 0x5540, 0xc12d, 0x557f, 0xc12d, 0x21, 0 + .dw 0x55c0, 0xc12d, 0x55ff, 0xc12d, 0x21, 0 + .dw 0x5640, 0xc12d, 0x567f, 0xc12d, 0x21, 0 + .dw 0x56c0, 0xc12d, 0x56ff, 0xc12d, 0x21, 0 + .dw 0x5740, 0xc12d, 0x577f, 0xc12d, 0x21, 0 + .dw 0x57c0, 0xc12d, 0x57ff, 0xc12d, 0x21, 0 + .dw 0x5840, 0xc12d, 0x587f, 0xc12d, 0x21, 0 + .dw 0x58c0, 0xc12d, 0x58ff, 0xc12d, 0x21, 0 + .dw 0x5940, 0xc12d, 0x597f, 0xc12d, 0x21, 0 + .dw 0x59c0, 0xc12d, 0x5fff, 0xc12d, 0x21, 0 + .dw 0x6040, 0xc12d, 0x607f, 0xc12d, 0x21, 0 + .dw 0x60c0, 0xc12d, 0x60ff, 0xc12d, 0x21, 0 + .dw 0x6140, 0xc12d, 0x617f, 0xc12d, 0x21, 0 + .dw 0x61c0, 0xc12d, 0x61ff, 0xc12d, 0x21, 0 + .dw 0x6240, 0xc12d, 0x627f, 0xc12d, 0x21, 0 + .dw 0x62c0, 0xc12d, 0x62ff, 0xc12d, 0x21, 0 + .dw 0x6340, 0xc12d, 0x637f, 0xc12d, 0x21, 0 + .dw 0x63c0, 0xc12d, 0x63ff, 0xc12d, 0x21, 0 + .dw 0x6440, 0xc12d, 0x647f, 0xc12d, 0x21, 0 + .dw 0x64c0, 0xc12d, 0x64ff, 0xc12d, 0x21, 0 + .dw 0x6540, 0xc12d, 0x657f, 0xc12d, 0x21, 0 + .dw 0x65c0, 0xc12d, 0x65ff, 0xc12d, 0x21, 0 + .dw 0x6640, 0xc12d, 0x667f, 0xc12d, 0x21, 0 + .dw 0x66c0, 0xc12d, 0x66ff, 0xc12d, 0x21, 0 + .dw 0x6740, 0xc12d, 0x677f, 0xc12d, 0x21, 0 + .dw 0x67c0, 0xc12d, 0x67ff, 0xc12d, 0x21, 0 + .dw 0x6840, 0xc12d, 0x687f, 0xc12d, 0x21, 0 + .dw 0x68c0, 0xc12d, 0x68ff, 0xc12d, 0x21, 0 + .dw 0x6940, 0xc12d, 0x697f, 0xc12d, 0x21, 0 + .dw 0x69c0, 0xc12d, 0x69ff, 0xc12d, 0x21, 0 + .dw 0x6a40, 0xc12d, 0x6a7f, 0xc12d, 0x21, 0 + .dw 0x6ac0, 0xc12d, 0x6aff, 0xc12d, 0x21, 0 + .dw 0x6b40, 0xc12d, 0x6b7f, 0xc12d, 0x21, 0 + .dw 0x6bc0, 0xc12d, 0x6bff, 0xc12d, 0x21, 0 + .dw 0x6c40, 0xc12d, 0x6c7f, 0xc12d, 0x21, 0 + .dw 0x6cc0, 0xc12d, 0x6cff, 0xc12d, 0x21, 0 + .dw 0x6d40, 0xc12d, 0x6d7f, 0xc12d, 0x21, 0 + .dw 0x6dc0, 0xc12d, 0x6dff, 0xc12d, 0x21, 0 + .dw 0x6e40, 0xc12d, 0x6e7f, 0xc12d, 0x21, 0 + .dw 0x6ec0, 0xc12d, 0x6eff, 0xc12d, 0x21, 0 + .dw 0x6f40, 0xc12d, 0x6f7f, 0xc12d, 0x21, 0 + .dw 0x6fc0, 0xc12d, 0x6fff, 0xc12d, 0x21, 0 + .dw 0x7040, 0xc12d, 0x707f, 0xc12d, 0x21, 0 + .dw 0x70c0, 0xc12d, 0x70ff, 0xc12d, 0x21, 0 + .dw 0x7140, 0xc12d, 0x717f, 0xc12d, 0x21, 0 + .dw 0x71c0, 0xc12d, 0x71ff, 0xc12d, 0x21, 0 + .dw 0x7240, 0xc12d, 0x727f, 0xc12d, 0x21, 0 + .dw 0x72c0, 0xc12d, 0x72ff, 0xc12d, 0x21, 0 + .dw 0x7340, 0xc12d, 0x737f, 0xc12d, 0x21, 0 + .dw 0x73c0, 0xc12d, 0x73ff, 0xc12d, 0x21, 0 + .dw 0x7440, 0xc12d, 0x747f, 0xc12d, 0x21, 0 + .dw 0x74c0, 0xc12d, 0x74ff, 0xc12d, 0x21, 0 + .dw 0x7540, 0xc12d, 0x757f, 0xc12d, 0x21, 0 + .dw 0x75c0, 0xc12d, 0x75ff, 0xc12d, 0x21, 0 + .dw 0x7640, 0xc12d, 0x767f, 0xc12d, 0x21, 0 + .dw 0x76c0, 0xc12d, 0x76ff, 0xc12d, 0x21, 0 + .dw 0x7740, 0xc12d, 0x777f, 0xc12d, 0x21, 0 + .dw 0x77c0, 0xc12d, 0x77ff, 0xc12d, 0x21, 0 + .dw 0x7840, 0xc12d, 0x787f, 0xc12d, 0x21, 0 + .dw 0x78c0, 0xc12d, 0x78ff, 0xc12d, 0x21, 0 + .dw 0x7940, 0xc12d, 0x797f, 0xc12d, 0x21, 0 + .dw 0x79c0, 0xc12d, 0x7fff, 0xc12d, 0x21, 0 + .dw 0x8040, 0xc12d, 0x807f, 0xc12d, 0x21, 0 + .dw 0x80c0, 0xc12d, 0x80ff, 0xc12d, 0x21, 0 + .dw 0x8140, 0xc12d, 0x817f, 0xc12d, 0x21, 0 + .dw 0x81c0, 0xc12d, 0x81ff, 0xc12d, 0x21, 0 + .dw 0x8240, 0xc12d, 0x827f, 0xc12d, 0x21, 0 + .dw 0x82c0, 0xc12d, 0x82ff, 0xc12d, 0x21, 0 + .dw 0x8340, 0xc12d, 0x837f, 0xc12d, 0x21, 0 + .dw 0x83c0, 0xc12d, 0x83ff, 0xc12d, 0x21, 0 + .dw 0x8440, 0xc12d, 0x847f, 0xc12d, 0x21, 0 + .dw 0x84c0, 0xc12d, 0x84ff, 0xc12d, 0x21, 0 + .dw 0x8540, 0xc12d, 0x857f, 0xc12d, 0x21, 0 + .dw 0x85c0, 0xc12d, 0x85ff, 0xc12d, 0x21, 0 + .dw 0x8640, 0xc12d, 0x867f, 0xc12d, 0x21, 0 + .dw 0x86c0, 0xc12d, 0x86ff, 0xc12d, 0x21, 0 + .dw 0x8740, 0xc12d, 0x877f, 0xc12d, 0x21, 0 + .dw 0x87c0, 0xc12d, 0x87ff, 0xc12d, 0x21, 0 + .dw 0x8840, 0xc12d, 0x887f, 0xc12d, 0x21, 0 + .dw 0x88c0, 0xc12d, 0x88ff, 0xc12d, 0x21, 0 + .dw 0x8940, 0xc12d, 0x897f, 0xc12d, 0x21, 0 + .dw 0x89c0, 0xc12d, 0x89ff, 0xc12d, 0x21, 0 + .dw 0x8a40, 0xc12d, 0x8a7f, 0xc12d, 0x21, 0 + .dw 0x8ac0, 0xc12d, 0x8aff, 0xc12d, 0x21, 0 + .dw 0x8b40, 0xc12d, 0x8b7f, 0xc12d, 0x21, 0 + .dw 0x8bc0, 0xc12d, 0x8bff, 0xc12d, 0x21, 0 + .dw 0x8c40, 0xc12d, 0x8c7f, 0xc12d, 0x21, 0 + .dw 0x8cc0, 0xc12d, 0x8cff, 0xc12d, 0x21, 0 + .dw 0x8d40, 0xc12d, 0x8d7f, 0xc12d, 0x21, 0 + .dw 0x8dc0, 0xc12d, 0x8dff, 0xc12d, 0x21, 0 + .dw 0x8e40, 0xc12d, 0x8e7f, 0xc12d, 0x21, 0 + .dw 0x8ec0, 0xc12d, 0x8eff, 0xc12d, 0x21, 0 + .dw 0x8f40, 0xc12d, 0x8f7f, 0xc12d, 0x21, 0 + .dw 0x8fc0, 0xc12d, 0x8fff, 0xc12d, 0x21, 0 + .dw 0x9040, 0xc12d, 0x907f, 0xc12d, 0x21, 0 + .dw 0x90c0, 0xc12d, 0x90ff, 0xc12d, 0x21, 0 + .dw 0x9140, 0xc12d, 0x917f, 0xc12d, 0x21, 0 + .dw 0x91c0, 0xc12d, 0x91ff, 0xc12d, 0x21, 0 + .dw 0x9240, 0xc12d, 0x927f, 0xc12d, 0x21, 0 + .dw 0x92c0, 0xc12d, 0x92ff, 0xc12d, 0x21, 0 + .dw 0x9340, 0xc12d, 0x937f, 0xc12d, 0x21, 0 + .dw 0x93c0, 0xc12d, 0x93ff, 0xc12d, 0x21, 0 + .dw 0x9440, 0xc12d, 0x947f, 0xc12d, 0x21, 0 + .dw 0x94c0, 0xc12d, 0x94ff, 0xc12d, 0x21, 0 + .dw 0x9540, 0xc12d, 0x957f, 0xc12d, 0x21, 0 + .dw 0x95c0, 0xc12d, 0x95ff, 0xc12d, 0x21, 0 + .dw 0x9640, 0xc12d, 0x967f, 0xc12d, 0x21, 0 + .dw 0x96c0, 0xc12d, 0x96ff, 0xc12d, 0x21, 0 + .dw 0x9740, 0xc12d, 0x977f, 0xc12d, 0x21, 0 + .dw 0x97c0, 0xc12d, 0x97ff, 0xc12d, 0x21, 0 + .dw 0x9840, 0xc12d, 0x987f, 0xc12d, 0x21, 0 + .dw 0x98c0, 0xc12d, 0x98ff, 0xc12d, 0x21, 0 + .dw 0x9940, 0xc12d, 0x997f, 0xc12d, 0x21, 0 + .dw 0x99c0, 0xc12d, 0x9fff, 0xc12d, 0x21, 0 + .dw 0xa040, 0xc12d, 0xa07f, 0xc12d, 0x21, 0 + .dw 0xa0c0, 0xc12d, 0xa0ff, 0xc12d, 0x21, 0 + .dw 0xa140, 0xc12d, 0xa17f, 0xc12d, 0x21, 0 + .dw 0xa1c0, 0xc12d, 0xa1ff, 0xc12d, 0x21, 0 + .dw 0xa240, 0xc12d, 0xa27f, 0xc12d, 0x21, 0 + .dw 0xa2c0, 0xc12d, 0xa2ff, 0xc12d, 0x21, 0 + .dw 0xa340, 0xc12d, 0xa37f, 0xc12d, 0x21, 0 + .dw 0xa3c0, 0xc12d, 0xa3ff, 0xc12d, 0x21, 0 + .dw 0xa440, 0xc12d, 0xa47f, 0xc12d, 0x21, 0 + .dw 0xa4c0, 0xc12d, 0xa4ff, 0xc12d, 0x21, 0 + .dw 0xa540, 0xc12d, 0xa57f, 0xc12d, 0x21, 0 + .dw 0xa5c0, 0xc12d, 0xa5ff, 0xc12d, 0x21, 0 + .dw 0xa640, 0xc12d, 0xa67f, 0xc12d, 0x21, 0 + .dw 0xa6c0, 0xc12d, 0xa6ff, 0xc12d, 0x21, 0 + .dw 0xa740, 0xc12d, 0xa77f, 0xc12d, 0x21, 0 + .dw 0xa7c0, 0xc12d, 0xa7ff, 0xc12d, 0x21, 0 + .dw 0xa840, 0xc12d, 0xa87f, 0xc12d, 0x21, 0 + .dw 0xa8c0, 0xc12d, 0xa8ff, 0xc12d, 0x21, 0 + .dw 0xa940, 0xc12d, 0xa97f, 0xc12d, 0x21, 0 + .dw 0xa9c0, 0xc12d, 0xa9ff, 0xc12d, 0x21, 0 + .dw 0xaa40, 0xc12d, 0xaa7f, 0xc12d, 0x21, 0 + .dw 0xaac0, 0xc12d, 0xaaff, 0xc12d, 0x21, 0 + .dw 0xab40, 0xc12d, 0xab7f, 0xc12d, 0x21, 0 + .dw 0xabc0, 0xc12d, 0xabff, 0xc12d, 0x21, 0 + .dw 0xac40, 0xc12d, 0xac7f, 0xc12d, 0x21, 0 + .dw 0xacc0, 0xc12d, 0xacff, 0xc12d, 0x21, 0 + .dw 0xad40, 0xc12d, 0xad7f, 0xc12d, 0x21, 0 + .dw 0xadc0, 0xc12d, 0xadff, 0xc12d, 0x21, 0 + .dw 0xae40, 0xc12d, 0xae7f, 0xc12d, 0x21, 0 + .dw 0xaec0, 0xc12d, 0xaeff, 0xc12d, 0x21, 0 + .dw 0xaf40, 0xc12d, 0xaf7f, 0xc12d, 0x21, 0 + .dw 0xafc0, 0xc12d, 0xafff, 0xc12d, 0x21, 0 + .dw 0xb040, 0xc12d, 0xb07f, 0xc12d, 0x21, 0 + .dw 0xb0c0, 0xc12d, 0xb0ff, 0xc12d, 0x21, 0 + .dw 0xb140, 0xc12d, 0xb17f, 0xc12d, 0x21, 0 + .dw 0xb1c0, 0xc12d, 0xb1ff, 0xc12d, 0x21, 0 + .dw 0xb240, 0xc12d, 0xb27f, 0xc12d, 0x21, 0 + .dw 0xb2c0, 0xc12d, 0xb2ff, 0xc12d, 0x21, 0 + .dw 0xb340, 0xc12d, 0xb37f, 0xc12d, 0x21, 0 + .dw 0xb3c0, 0xc12d, 0xb3ff, 0xc12d, 0x21, 0 + .dw 0xb440, 0xc12d, 0xb47f, 0xc12d, 0x21, 0 + .dw 0xb4c0, 0xc12d, 0xb4ff, 0xc12d, 0x21, 0 + .dw 0xb540, 0xc12d, 0xb57f, 0xc12d, 0x21, 0 + .dw 0xb5c0, 0xc12d, 0xb5ff, 0xc12d, 0x21, 0 + .dw 0xb640, 0xc12d, 0xb67f, 0xc12d, 0x21, 0 + .dw 0xb6c0, 0xc12d, 0xb6ff, 0xc12d, 0x21, 0 + .dw 0xb740, 0xc12d, 0xb77f, 0xc12d, 0x21, 0 + .dw 0xb7c0, 0xc12d, 0xb7ff, 0xc12d, 0x21, 0 + .dw 0xb840, 0xc12d, 0xb87f, 0xc12d, 0x21, 0 + .dw 0xb8c0, 0xc12d, 0xb8ff, 0xc12d, 0x21, 0 + .dw 0xb940, 0xc12d, 0xb97f, 0xc12d, 0x21, 0 + .dw 0xb9c0, 0xc12d, 0xbfff, 0xc12d, 0x21, 0 + .dw 0xc040, 0xc12d, 0xc07f, 0xc12d, 0x21, 0 + .dw 0xc0c0, 0xc12d, 0xc0ff, 0xc12d, 0x21, 0 + .dw 0xc140, 0xc12d, 0xc17f, 0xc12d, 0x21, 0 + .dw 0xc1c0, 0xc12d, 0xc1ff, 0xc12d, 0x21, 0 + .dw 0xc240, 0xc12d, 0xc27f, 0xc12d, 0x21, 0 + .dw 0xc2c0, 0xc12d, 0xc2ff, 0xc12d, 0x21, 0 + .dw 0xc340, 0xc12d, 0xc37f, 0xc12d, 0x21, 0 + .dw 0xc3c0, 0xc12d, 0xc3ff, 0xc12d, 0x21, 0 + .dw 0xc440, 0xc12d, 0xc47f, 0xc12d, 0x21, 0 + .dw 0xc4c0, 0xc12d, 0xc4ff, 0xc12d, 0x21, 0 + .dw 0xc540, 0xc12d, 0xc57f, 0xc12d, 0x21, 0 + .dw 0xc5c0, 0xc12d, 0xc5ff, 0xc12d, 0x21, 0 + .dw 0xc640, 0xc12d, 0xc67f, 0xc12d, 0x21, 0 + .dw 0xc6c0, 0xc12d, 0xc6ff, 0xc12d, 0x21, 0 + .dw 0xc740, 0xc12d, 0xc77f, 0xc12d, 0x21, 0 + .dw 0xc7c0, 0xc12d, 0xc7ff, 0xc12d, 0x21, 0 + .dw 0xc840, 0xc12d, 0xc87f, 0xc12d, 0x21, 0 + .dw 0xc8c0, 0xc12d, 0xc8ff, 0xc12d, 0x21, 0 + .dw 0xc940, 0xc12d, 0xc97f, 0xc12d, 0x21, 0 + .dw 0xc9c0, 0xc12d, 0xc9ff, 0xc12d, 0x21, 0 + .dw 0xca40, 0xc12d, 0xca7f, 0xc12d, 0x21, 0 + .dw 0xcac0, 0xc12d, 0xcaff, 0xc12d, 0x21, 0 + .dw 0xcb40, 0xc12d, 0xcb7f, 0xc12d, 0x21, 0 + .dw 0xcbc0, 0xc12d, 0xcbff, 0xc12d, 0x21, 0 + .dw 0xcc40, 0xc12d, 0xcc7f, 0xc12d, 0x21, 0 + .dw 0xccc0, 0xc12d, 0xccff, 0xc12d, 0x21, 0 + .dw 0xcd40, 0xc12d, 0xcd7f, 0xc12d, 0x21, 0 + .dw 0xcdc0, 0xc12d, 0xcdff, 0xc12d, 0x21, 0 + .dw 0xce40, 0xc12d, 0xce7f, 0xc12d, 0x21, 0 + .dw 0xcec0, 0xc12d, 0xceff, 0xc12d, 0x21, 0 + .dw 0xcf40, 0xc12d, 0xcf7f, 0xc12d, 0x21, 0 + .dw 0xcfc0, 0xc12d, 0xcfff, 0xc12d, 0x21, 0 + .dw 0xd040, 0xc12d, 0xd07f, 0xc12d, 0x21, 0 + .dw 0xd0c0, 0xc12d, 0xd0ff, 0xc12d, 0x21, 0 + .dw 0xd140, 0xc12d, 0xd17f, 0xc12d, 0x21, 0 + .dw 0xd1c0, 0xc12d, 0xd1ff, 0xc12d, 0x21, 0 + .dw 0xd240, 0xc12d, 0xd27f, 0xc12d, 0x21, 0 + .dw 0xd2c0, 0xc12d, 0xd2ff, 0xc12d, 0x21, 0 + .dw 0xd340, 0xc12d, 0xd37f, 0xc12d, 0x21, 0 + .dw 0xd3c0, 0xc12d, 0xd3ff, 0xc12d, 0x21, 0 + .dw 0xd440, 0xc12d, 0xd47f, 0xc12d, 0x21, 0 + .dw 0xd4c0, 0xc12d, 0xd4ff, 0xc12d, 0x21, 0 + .dw 0xd540, 0xc12d, 0xd57f, 0xc12d, 0x21, 0 + .dw 0xd5c0, 0xc12d, 0xd5ff, 0xc12d, 0x21, 0 + .dw 0xd640, 0xc12d, 0xd67f, 0xc12d, 0x21, 0 + .dw 0xd6c0, 0xc12d, 0xd6ff, 0xc12d, 0x21, 0 + .dw 0xd740, 0xc12d, 0xd77f, 0xc12d, 0x21, 0 + .dw 0xd7c0, 0xc12d, 0xd7ff, 0xc12d, 0x21, 0 + .dw 0xd840, 0xc12d, 0xd87f, 0xc12d, 0x21, 0 + .dw 0xd8c0, 0xc12d, 0xd8ff, 0xc12d, 0x21, 0 + .dw 0xd940, 0xc12d, 0xd97f, 0xc12d, 0x21, 0 + .dw 0xd9c0, 0xc12d, 0xdfff, 0xc12d, 0x21, 0 + .dw 0xe040, 0xc12d, 0xe07f, 0xc12d, 0x21, 0 + .dw 0xe0c0, 0xc12d, 0xe0ff, 0xc12d, 0x21, 0 + .dw 0xe140, 0xc12d, 0xe17f, 0xc12d, 0x21, 0 + .dw 0xe1c0, 0xc12d, 0xe1ff, 0xc12d, 0x21, 0 + .dw 0xe240, 0xc12d, 0xe27f, 0xc12d, 0x21, 0 + .dw 0xe2c0, 0xc12d, 0xe2ff, 0xc12d, 0x21, 0 + .dw 0xe340, 0xc12d, 0xe37f, 0xc12d, 0x21, 0 + .dw 0xe3c0, 0xc12d, 0xe3ff, 0xc12d, 0x21, 0 + .dw 0xe440, 0xc12d, 0xe47f, 0xc12d, 0x21, 0 + .dw 0xe4c0, 0xc12d, 0xe4ff, 0xc12d, 0x21, 0 + .dw 0xe540, 0xc12d, 0xe57f, 0xc12d, 0x21, 0 + .dw 0xe5c0, 0xc12d, 0xe5ff, 0xc12d, 0x21, 0 + .dw 0xe640, 0xc12d, 0xe67f, 0xc12d, 0x21, 0 + .dw 0xe6c0, 0xc12d, 0xe6ff, 0xc12d, 0x21, 0 + .dw 0xe740, 0xc12d, 0xe77f, 0xc12d, 0x21, 0 + .dw 0xe7c0, 0xc12d, 0xe7ff, 0xc12d, 0x21, 0 + .dw 0xe840, 0xc12d, 0xe87f, 0xc12d, 0x21, 0 + .dw 0xe8c0, 0xc12d, 0xe8ff, 0xc12d, 0x21, 0 + .dw 0xe940, 0xc12d, 0xe97f, 0xc12d, 0x21, 0 + .dw 0xe9c0, 0xc12d, 0xe9ff, 0xc12d, 0x21, 0 + .dw 0xea40, 0xc12d, 0xea7f, 0xc12d, 0x21, 0 + .dw 0xeac0, 0xc12d, 0xeaff, 0xc12d, 0x21, 0 + .dw 0xeb40, 0xc12d, 0xeb7f, 0xc12d, 0x21, 0 + .dw 0xebc0, 0xc12d, 0xebff, 0xc12d, 0x21, 0 + .dw 0xec40, 0xc12d, 0xec7f, 0xc12d, 0x21, 0 + .dw 0xecc0, 0xc12d, 0xecff, 0xc12d, 0x21, 0 + .dw 0xed40, 0xc12d, 0xed7f, 0xc12d, 0x21, 0 + .dw 0xedc0, 0xc12d, 0xedff, 0xc12d, 0x21, 0 + .dw 0xee40, 0xc12d, 0xee7f, 0xc12d, 0x21, 0 + .dw 0xeec0, 0xc12d, 0xeeff, 0xc12d, 0x21, 0 + .dw 0xef40, 0xc12d, 0xef7f, 0xc12d, 0x21, 0 + .dw 0xefc0, 0xc12d, 0xefff, 0xc12d, 0x21, 0 + .dw 0xf040, 0xc12d, 0xf07f, 0xc12d, 0x21, 0 + .dw 0xf0c0, 0xc12d, 0xf0ff, 0xc12d, 0x21, 0 + .dw 0xf140, 0xc12d, 0xf17f, 0xc12d, 0x21, 0 + .dw 0xf1c0, 0xc12d, 0xf1ff, 0xc12d, 0x21, 0 + .dw 0xf240, 0xc12d, 0xf27f, 0xc12d, 0x21, 0 + .dw 0xf2c0, 0xc12d, 0xf2ff, 0xc12d, 0x21, 0 + .dw 0xf340, 0xc12d, 0xf37f, 0xc12d, 0x21, 0 + .dw 0xf3c0, 0xc12d, 0xf3ff, 0xc12d, 0x21, 0 + .dw 0xf440, 0xc12d, 0xf47f, 0xc12d, 0x21, 0 + .dw 0xf4c0, 0xc12d, 0xf4ff, 0xc12d, 0x21, 0 + .dw 0xf540, 0xc12d, 0xf57f, 0xc12d, 0x21, 0 + .dw 0xf5c0, 0xc12d, 0xf5ff, 0xc12d, 0x21, 0 + .dw 0xf640, 0xc12d, 0xf67f, 0xc12d, 0x21, 0 + .dw 0xf6c0, 0xc12d, 0xf6ff, 0xc12d, 0x21, 0 + .dw 0xf740, 0xc12d, 0xf77f, 0xc12d, 0x21, 0 + .dw 0xf7c0, 0xc12d, 0xf7ff, 0xc12d, 0x21, 0 + .dw 0xf840, 0xc12d, 0xf87f, 0xc12d, 0x21, 0 + .dw 0xf8c0, 0xc12d, 0xf8ff, 0xc12d, 0x21, 0 + .dw 0xf940, 0xc12d, 0xf97f, 0xc12d, 0x21, 0 + .dw 0xf9c0, 0xc12d, 0xffff, 0xc12d, 0x21, 0 + .dw 0x0040, 0xc12e, 0x007f, 0xc12e, 0x21, 0 + .dw 0x00c0, 0xc12e, 0x00ff, 0xc12e, 0x21, 0 + .dw 0x0140, 0xc12e, 0x017f, 0xc12e, 0x21, 0 + .dw 0x01c0, 0xc12e, 0x01ff, 0xc12e, 0x21, 0 + .dw 0x0240, 0xc12e, 0x027f, 0xc12e, 0x21, 0 + .dw 0x02c0, 0xc12e, 0x02ff, 0xc12e, 0x21, 0 + .dw 0x0340, 0xc12e, 0x037f, 0xc12e, 0x21, 0 + .dw 0x03c0, 0xc12e, 0x03ff, 0xc12e, 0x21, 0 + .dw 0x0440, 0xc12e, 0x047f, 0xc12e, 0x21, 0 + .dw 0x04c0, 0xc12e, 0x04ff, 0xc12e, 0x21, 0 + .dw 0x0540, 0xc12e, 0x057f, 0xc12e, 0x21, 0 + .dw 0x05c0, 0xc12e, 0x05ff, 0xc12e, 0x21, 0 + .dw 0x0640, 0xc12e, 0x067f, 0xc12e, 0x21, 0 + .dw 0x06c0, 0xc12e, 0x06ff, 0xc12e, 0x21, 0 + .dw 0x0740, 0xc12e, 0x077f, 0xc12e, 0x21, 0 + .dw 0x07c0, 0xc12e, 0x07ff, 0xc12e, 0x21, 0 + .dw 0x0840, 0xc12e, 0x087f, 0xc12e, 0x21, 0 + .dw 0x08c0, 0xc12e, 0x08ff, 0xc12e, 0x21, 0 + .dw 0x0940, 0xc12e, 0x097f, 0xc12e, 0x21, 0 + .dw 0x09c0, 0xc12e, 0x09ff, 0xc12e, 0x21, 0 + .dw 0x0a40, 0xc12e, 0x0a7f, 0xc12e, 0x21, 0 + .dw 0x0ac0, 0xc12e, 0x0aff, 0xc12e, 0x21, 0 + .dw 0x0b40, 0xc12e, 0x0b7f, 0xc12e, 0x21, 0 + .dw 0x0bc0, 0xc12e, 0x0bff, 0xc12e, 0x21, 0 + .dw 0x0c40, 0xc12e, 0x0c7f, 0xc12e, 0x21, 0 + .dw 0x0cc0, 0xc12e, 0x0cff, 0xc12e, 0x21, 0 + .dw 0x0d40, 0xc12e, 0x0d7f, 0xc12e, 0x21, 0 + .dw 0x0dc0, 0xc12e, 0x0dff, 0xc12e, 0x21, 0 + .dw 0x0e40, 0xc12e, 0x0e7f, 0xc12e, 0x21, 0 + .dw 0x0ec0, 0xc12e, 0x0eff, 0xc12e, 0x21, 0 + .dw 0x0f40, 0xc12e, 0x0f7f, 0xc12e, 0x21, 0 + .dw 0x0fc0, 0xc12e, 0x0fff, 0xc12e, 0x21, 0 + .dw 0x1040, 0xc12e, 0x107f, 0xc12e, 0x21, 0 + .dw 0x10c0, 0xc12e, 0x10ff, 0xc12e, 0x21, 0 + .dw 0x1140, 0xc12e, 0x117f, 0xc12e, 0x21, 0 + .dw 0x11c0, 0xc12e, 0x11ff, 0xc12e, 0x21, 0 + .dw 0x1240, 0xc12e, 0x127f, 0xc12e, 0x21, 0 + .dw 0x12c0, 0xc12e, 0x12ff, 0xc12e, 0x21, 0 + .dw 0x1340, 0xc12e, 0x137f, 0xc12e, 0x21, 0 + .dw 0x13c0, 0xc12e, 0x13ff, 0xc12e, 0x21, 0 + .dw 0x1440, 0xc12e, 0x147f, 0xc12e, 0x21, 0 + .dw 0x14c0, 0xc12e, 0x14ff, 0xc12e, 0x21, 0 + .dw 0x1540, 0xc12e, 0x157f, 0xc12e, 0x21, 0 + .dw 0x15c0, 0xc12e, 0x15ff, 0xc12e, 0x21, 0 + .dw 0x1640, 0xc12e, 0x167f, 0xc12e, 0x21, 0 + .dw 0x16c0, 0xc12e, 0x16ff, 0xc12e, 0x21, 0 + .dw 0x1740, 0xc12e, 0x177f, 0xc12e, 0x21, 0 + .dw 0x17c0, 0xc12e, 0x17ff, 0xc12e, 0x21, 0 + .dw 0x1840, 0xc12e, 0x187f, 0xc12e, 0x21, 0 + .dw 0x18c0, 0xc12e, 0x18ff, 0xc12e, 0x21, 0 + .dw 0x1940, 0xc12e, 0x197f, 0xc12e, 0x21, 0 + .dw 0x19c0, 0xc12e, 0x1fff, 0xc12e, 0x21, 0 + .dw 0x2040, 0xc12e, 0x207f, 0xc12e, 0x21, 0 + .dw 0x20c0, 0xc12e, 0x20ff, 0xc12e, 0x21, 0 + .dw 0x2140, 0xc12e, 0x217f, 0xc12e, 0x21, 0 + .dw 0x21c0, 0xc12e, 0x21ff, 0xc12e, 0x21, 0 + .dw 0x2240, 0xc12e, 0x227f, 0xc12e, 0x21, 0 + .dw 0x22c0, 0xc12e, 0x22ff, 0xc12e, 0x21, 0 + .dw 0x2340, 0xc12e, 0x237f, 0xc12e, 0x21, 0 + .dw 0x23c0, 0xc12e, 0x23ff, 0xc12e, 0x21, 0 + .dw 0x2440, 0xc12e, 0x247f, 0xc12e, 0x21, 0 + .dw 0x24c0, 0xc12e, 0x24ff, 0xc12e, 0x21, 0 + .dw 0x2540, 0xc12e, 0x257f, 0xc12e, 0x21, 0 + .dw 0x25c0, 0xc12e, 0x25ff, 0xc12e, 0x21, 0 + .dw 0x2640, 0xc12e, 0x267f, 0xc12e, 0x21, 0 + .dw 0x26c0, 0xc12e, 0x26ff, 0xc12e, 0x21, 0 + .dw 0x2740, 0xc12e, 0x277f, 0xc12e, 0x21, 0 + .dw 0x27c0, 0xc12e, 0x27ff, 0xc12e, 0x21, 0 + .dw 0x2840, 0xc12e, 0x287f, 0xc12e, 0x21, 0 + .dw 0x28c0, 0xc12e, 0x28ff, 0xc12e, 0x21, 0 + .dw 0x2940, 0xc12e, 0x297f, 0xc12e, 0x21, 0 + .dw 0x29c0, 0xc12e, 0x29ff, 0xc12e, 0x21, 0 + .dw 0x2a40, 0xc12e, 0x2a7f, 0xc12e, 0x21, 0 + .dw 0x2ac0, 0xc12e, 0x2aff, 0xc12e, 0x21, 0 + .dw 0x2b40, 0xc12e, 0x2b7f, 0xc12e, 0x21, 0 + .dw 0x2bc0, 0xc12e, 0x2bff, 0xc12e, 0x21, 0 + .dw 0x2c40, 0xc12e, 0x2c7f, 0xc12e, 0x21, 0 + .dw 0x2cc0, 0xc12e, 0x2cff, 0xc12e, 0x21, 0 + .dw 0x2d40, 0xc12e, 0x2d7f, 0xc12e, 0x21, 0 + .dw 0x2dc0, 0xc12e, 0x2dff, 0xc12e, 0x21, 0 + .dw 0x2e40, 0xc12e, 0x2e7f, 0xc12e, 0x21, 0 + .dw 0x2ec0, 0xc12e, 0x2eff, 0xc12e, 0x21, 0 + .dw 0x2f40, 0xc12e, 0x2f7f, 0xc12e, 0x21, 0 + .dw 0x2fc0, 0xc12e, 0x2fff, 0xc12e, 0x21, 0 + .dw 0x3040, 0xc12e, 0x307f, 0xc12e, 0x21, 0 + .dw 0x30c0, 0xc12e, 0x30ff, 0xc12e, 0x21, 0 + .dw 0x3140, 0xc12e, 0x317f, 0xc12e, 0x21, 0 + .dw 0x31c0, 0xc12e, 0x31ff, 0xc12e, 0x21, 0 + .dw 0x3240, 0xc12e, 0x327f, 0xc12e, 0x21, 0 + .dw 0x32c0, 0xc12e, 0x32ff, 0xc12e, 0x21, 0 + .dw 0x3340, 0xc12e, 0x337f, 0xc12e, 0x21, 0 + .dw 0x33c0, 0xc12e, 0x33ff, 0xc12e, 0x21, 0 + .dw 0x3440, 0xc12e, 0x347f, 0xc12e, 0x21, 0 + .dw 0x34c0, 0xc12e, 0x34ff, 0xc12e, 0x21, 0 + .dw 0x3540, 0xc12e, 0x357f, 0xc12e, 0x21, 0 + .dw 0x35c0, 0xc12e, 0x35ff, 0xc12e, 0x21, 0 + .dw 0x3640, 0xc12e, 0x367f, 0xc12e, 0x21, 0 + .dw 0x36c0, 0xc12e, 0x36ff, 0xc12e, 0x21, 0 + .dw 0x3740, 0xc12e, 0x377f, 0xc12e, 0x21, 0 + .dw 0x37c0, 0xc12e, 0x37ff, 0xc12e, 0x21, 0 + .dw 0x3840, 0xc12e, 0x387f, 0xc12e, 0x21, 0 + .dw 0x38c0, 0xc12e, 0x38ff, 0xc12e, 0x21, 0 + .dw 0x3940, 0xc12e, 0x397f, 0xc12e, 0x21, 0 + .dw 0x39c0, 0xc12e, 0x3fff, 0xc12e, 0x21, 0 + .dw 0x4040, 0xc12e, 0x407f, 0xc12e, 0x21, 0 + .dw 0x40c0, 0xc12e, 0x40ff, 0xc12e, 0x21, 0 + .dw 0x4140, 0xc12e, 0x417f, 0xc12e, 0x21, 0 + .dw 0x41c0, 0xc12e, 0x41ff, 0xc12e, 0x21, 0 + .dw 0x4240, 0xc12e, 0x427f, 0xc12e, 0x21, 0 + .dw 0x42c0, 0xc12e, 0x42ff, 0xc12e, 0x21, 0 + .dw 0x4340, 0xc12e, 0x437f, 0xc12e, 0x21, 0 + .dw 0x43c0, 0xc12e, 0x43ff, 0xc12e, 0x21, 0 + .dw 0x4440, 0xc12e, 0x447f, 0xc12e, 0x21, 0 + .dw 0x44c0, 0xc12e, 0x44ff, 0xc12e, 0x21, 0 + .dw 0x4540, 0xc12e, 0x457f, 0xc12e, 0x21, 0 + .dw 0x45c0, 0xc12e, 0x45ff, 0xc12e, 0x21, 0 + .dw 0x4640, 0xc12e, 0x467f, 0xc12e, 0x21, 0 + .dw 0x46c0, 0xc12e, 0x46ff, 0xc12e, 0x21, 0 + .dw 0x4740, 0xc12e, 0x477f, 0xc12e, 0x21, 0 + .dw 0x47c0, 0xc12e, 0x47ff, 0xc12e, 0x21, 0 + .dw 0x4840, 0xc12e, 0x487f, 0xc12e, 0x21, 0 + .dw 0x48c0, 0xc12e, 0x48ff, 0xc12e, 0x21, 0 + .dw 0x4940, 0xc12e, 0x497f, 0xc12e, 0x21, 0 + .dw 0x49c0, 0xc12e, 0x49ff, 0xc12e, 0x21, 0 + .dw 0x4a40, 0xc12e, 0x4a7f, 0xc12e, 0x21, 0 + .dw 0x4ac0, 0xc12e, 0x4aff, 0xc12e, 0x21, 0 + .dw 0x4b40, 0xc12e, 0x4b7f, 0xc12e, 0x21, 0 + .dw 0x4bc0, 0xc12e, 0x4bff, 0xc12e, 0x21, 0 + .dw 0x4c40, 0xc12e, 0x4c7f, 0xc12e, 0x21, 0 + .dw 0x4cc0, 0xc12e, 0x4cff, 0xc12e, 0x21, 0 + .dw 0x4d40, 0xc12e, 0x4d7f, 0xc12e, 0x21, 0 + .dw 0x4dc0, 0xc12e, 0x4dff, 0xc12e, 0x21, 0 + .dw 0x4e40, 0xc12e, 0x4e7f, 0xc12e, 0x21, 0 + .dw 0x4ec0, 0xc12e, 0x4eff, 0xc12e, 0x21, 0 + .dw 0x4f40, 0xc12e, 0x4f7f, 0xc12e, 0x21, 0 + .dw 0x4fc0, 0xc12e, 0x4fff, 0xc12e, 0x21, 0 + .dw 0x5040, 0xc12e, 0x507f, 0xc12e, 0x21, 0 + .dw 0x50c0, 0xc12e, 0x50ff, 0xc12e, 0x21, 0 + .dw 0x5140, 0xc12e, 0x517f, 0xc12e, 0x21, 0 + .dw 0x51c0, 0xc12e, 0x51ff, 0xc12e, 0x21, 0 + .dw 0x5240, 0xc12e, 0x527f, 0xc12e, 0x21, 0 + .dw 0x52c0, 0xc12e, 0x52ff, 0xc12e, 0x21, 0 + .dw 0x5340, 0xc12e, 0x537f, 0xc12e, 0x21, 0 + .dw 0x53c0, 0xc12e, 0x53ff, 0xc12e, 0x21, 0 + .dw 0x5440, 0xc12e, 0x547f, 0xc12e, 0x21, 0 + .dw 0x54c0, 0xc12e, 0x54ff, 0xc12e, 0x21, 0 + .dw 0x5540, 0xc12e, 0x557f, 0xc12e, 0x21, 0 + .dw 0x55c0, 0xc12e, 0x55ff, 0xc12e, 0x21, 0 + .dw 0x5640, 0xc12e, 0x567f, 0xc12e, 0x21, 0 + .dw 0x56c0, 0xc12e, 0x56ff, 0xc12e, 0x21, 0 + .dw 0x5740, 0xc12e, 0x577f, 0xc12e, 0x21, 0 + .dw 0x57c0, 0xc12e, 0x57ff, 0xc12e, 0x21, 0 + .dw 0x5840, 0xc12e, 0x587f, 0xc12e, 0x21, 0 + .dw 0x58c0, 0xc12e, 0x58ff, 0xc12e, 0x21, 0 + .dw 0x5940, 0xc12e, 0x597f, 0xc12e, 0x21, 0 + .dw 0x59c0, 0xc12e, 0x5fff, 0xc12e, 0x21, 0 + .dw 0x6040, 0xc12e, 0x607f, 0xc12e, 0x21, 0 + .dw 0x60c0, 0xc12e, 0x60ff, 0xc12e, 0x21, 0 + .dw 0x6140, 0xc12e, 0x617f, 0xc12e, 0x21, 0 + .dw 0x61c0, 0xc12e, 0x61ff, 0xc12e, 0x21, 0 + .dw 0x6240, 0xc12e, 0x627f, 0xc12e, 0x21, 0 + .dw 0x62c0, 0xc12e, 0x62ff, 0xc12e, 0x21, 0 + .dw 0x6340, 0xc12e, 0x637f, 0xc12e, 0x21, 0 + .dw 0x63c0, 0xc12e, 0x63ff, 0xc12e, 0x21, 0 + .dw 0x6440, 0xc12e, 0x647f, 0xc12e, 0x21, 0 + .dw 0x64c0, 0xc12e, 0x64ff, 0xc12e, 0x21, 0 + .dw 0x6540, 0xc12e, 0x657f, 0xc12e, 0x21, 0 + .dw 0x65c0, 0xc12e, 0x65ff, 0xc12e, 0x21, 0 + .dw 0x6640, 0xc12e, 0x667f, 0xc12e, 0x21, 0 + .dw 0x66c0, 0xc12e, 0x66ff, 0xc12e, 0x21, 0 + .dw 0x6740, 0xc12e, 0x677f, 0xc12e, 0x21, 0 + .dw 0x67c0, 0xc12e, 0x67ff, 0xc12e, 0x21, 0 + .dw 0x6840, 0xc12e, 0x687f, 0xc12e, 0x21, 0 + .dw 0x68c0, 0xc12e, 0x68ff, 0xc12e, 0x21, 0 + .dw 0x6940, 0xc12e, 0x697f, 0xc12e, 0x21, 0 + .dw 0x69c0, 0xc12e, 0x69ff, 0xc12e, 0x21, 0 + .dw 0x6a40, 0xc12e, 0x6a7f, 0xc12e, 0x21, 0 + .dw 0x6ac0, 0xc12e, 0x6aff, 0xc12e, 0x21, 0 + .dw 0x6b40, 0xc12e, 0x6b7f, 0xc12e, 0x21, 0 + .dw 0x6bc0, 0xc12e, 0x6bff, 0xc12e, 0x21, 0 + .dw 0x6c40, 0xc12e, 0x6c7f, 0xc12e, 0x21, 0 + .dw 0x6cc0, 0xc12e, 0x6cff, 0xc12e, 0x21, 0 + .dw 0x6d40, 0xc12e, 0x6d7f, 0xc12e, 0x21, 0 + .dw 0x6dc0, 0xc12e, 0x6dff, 0xc12e, 0x21, 0 + .dw 0x6e40, 0xc12e, 0x6e7f, 0xc12e, 0x21, 0 + .dw 0x6ec0, 0xc12e, 0x6eff, 0xc12e, 0x21, 0 + .dw 0x6f40, 0xc12e, 0x6f7f, 0xc12e, 0x21, 0 + .dw 0x6fc0, 0xc12e, 0x6fff, 0xc12e, 0x21, 0 + .dw 0x7040, 0xc12e, 0x707f, 0xc12e, 0x21, 0 + .dw 0x70c0, 0xc12e, 0x70ff, 0xc12e, 0x21, 0 + .dw 0x7140, 0xc12e, 0x717f, 0xc12e, 0x21, 0 + .dw 0x71c0, 0xc12e, 0x71ff, 0xc12e, 0x21, 0 + .dw 0x7240, 0xc12e, 0x727f, 0xc12e, 0x21, 0 + .dw 0x72c0, 0xc12e, 0x72ff, 0xc12e, 0x21, 0 + .dw 0x7340, 0xc12e, 0x737f, 0xc12e, 0x21, 0 + .dw 0x73c0, 0xc12e, 0x73ff, 0xc12e, 0x21, 0 + .dw 0x7440, 0xc12e, 0x747f, 0xc12e, 0x21, 0 + .dw 0x74c0, 0xc12e, 0x74ff, 0xc12e, 0x21, 0 + .dw 0x7540, 0xc12e, 0x757f, 0xc12e, 0x21, 0 + .dw 0x75c0, 0xc12e, 0x75ff, 0xc12e, 0x21, 0 + .dw 0x7640, 0xc12e, 0x767f, 0xc12e, 0x21, 0 + .dw 0x76c0, 0xc12e, 0x76ff, 0xc12e, 0x21, 0 + .dw 0x7740, 0xc12e, 0x777f, 0xc12e, 0x21, 0 + .dw 0x77c0, 0xc12e, 0x77ff, 0xc12e, 0x21, 0 + .dw 0x7840, 0xc12e, 0x787f, 0xc12e, 0x21, 0 + .dw 0x78c0, 0xc12e, 0x78ff, 0xc12e, 0x21, 0 + .dw 0x7940, 0xc12e, 0x797f, 0xc12e, 0x21, 0 + .dw 0x79c0, 0xc12e, 0x7fff, 0xc12e, 0x21, 0 + .dw 0x8040, 0xc12e, 0x807f, 0xc12e, 0x21, 0 + .dw 0x80c0, 0xc12e, 0x80ff, 0xc12e, 0x21, 0 + .dw 0x8140, 0xc12e, 0x817f, 0xc12e, 0x21, 0 + .dw 0x81c0, 0xc12e, 0x81ff, 0xc12e, 0x21, 0 + .dw 0x8240, 0xc12e, 0x827f, 0xc12e, 0x21, 0 + .dw 0x82c0, 0xc12e, 0x82ff, 0xc12e, 0x21, 0 + .dw 0x8340, 0xc12e, 0x837f, 0xc12e, 0x21, 0 + .dw 0x83c0, 0xc12e, 0x83ff, 0xc12e, 0x21, 0 + .dw 0x8440, 0xc12e, 0x847f, 0xc12e, 0x21, 0 + .dw 0x84c0, 0xc12e, 0x84ff, 0xc12e, 0x21, 0 + .dw 0x8540, 0xc12e, 0x857f, 0xc12e, 0x21, 0 + .dw 0x85c0, 0xc12e, 0x85ff, 0xc12e, 0x21, 0 + .dw 0x8640, 0xc12e, 0x867f, 0xc12e, 0x21, 0 + .dw 0x86c0, 0xc12e, 0x86ff, 0xc12e, 0x21, 0 + .dw 0x8740, 0xc12e, 0x877f, 0xc12e, 0x21, 0 + .dw 0x87c0, 0xc12e, 0x87ff, 0xc12e, 0x21, 0 + .dw 0x8840, 0xc12e, 0x887f, 0xc12e, 0x21, 0 + .dw 0x88c0, 0xc12e, 0x88ff, 0xc12e, 0x21, 0 + .dw 0x8940, 0xc12e, 0x897f, 0xc12e, 0x21, 0 + .dw 0x89c0, 0xc12e, 0x89ff, 0xc12e, 0x21, 0 + .dw 0x8a40, 0xc12e, 0x8a7f, 0xc12e, 0x21, 0 + .dw 0x8ac0, 0xc12e, 0x8aff, 0xc12e, 0x21, 0 + .dw 0x8b40, 0xc12e, 0x8b7f, 0xc12e, 0x21, 0 + .dw 0x8bc0, 0xc12e, 0x8bff, 0xc12e, 0x21, 0 + .dw 0x8c40, 0xc12e, 0x8c7f, 0xc12e, 0x21, 0 + .dw 0x8cc0, 0xc12e, 0x8cff, 0xc12e, 0x21, 0 + .dw 0x8d40, 0xc12e, 0x8d7f, 0xc12e, 0x21, 0 + .dw 0x8dc0, 0xc12e, 0x8dff, 0xc12e, 0x21, 0 + .dw 0x8e40, 0xc12e, 0x8e7f, 0xc12e, 0x21, 0 + .dw 0x8ec0, 0xc12e, 0x8eff, 0xc12e, 0x21, 0 + .dw 0x8f40, 0xc12e, 0x8f7f, 0xc12e, 0x21, 0 + .dw 0x8fc0, 0xc12e, 0x8fff, 0xc12e, 0x21, 0 + .dw 0x9040, 0xc12e, 0x907f, 0xc12e, 0x21, 0 + .dw 0x90c0, 0xc12e, 0x90ff, 0xc12e, 0x21, 0 + .dw 0x9140, 0xc12e, 0x917f, 0xc12e, 0x21, 0 + .dw 0x91c0, 0xc12e, 0x91ff, 0xc12e, 0x21, 0 + .dw 0x9240, 0xc12e, 0x927f, 0xc12e, 0x21, 0 + .dw 0x92c0, 0xc12e, 0x92ff, 0xc12e, 0x21, 0 + .dw 0x9340, 0xc12e, 0x937f, 0xc12e, 0x21, 0 + .dw 0x93c0, 0xc12e, 0x93ff, 0xc12e, 0x21, 0 + .dw 0x9440, 0xc12e, 0x947f, 0xc12e, 0x21, 0 + .dw 0x94c0, 0xc12e, 0x94ff, 0xc12e, 0x21, 0 + .dw 0x9540, 0xc12e, 0x957f, 0xc12e, 0x21, 0 + .dw 0x95c0, 0xc12e, 0x95ff, 0xc12e, 0x21, 0 + .dw 0x9640, 0xc12e, 0x967f, 0xc12e, 0x21, 0 + .dw 0x96c0, 0xc12e, 0x96ff, 0xc12e, 0x21, 0 + .dw 0x9740, 0xc12e, 0x977f, 0xc12e, 0x21, 0 + .dw 0x97c0, 0xc12e, 0x97ff, 0xc12e, 0x21, 0 + .dw 0x9840, 0xc12e, 0x987f, 0xc12e, 0x21, 0 + .dw 0x98c0, 0xc12e, 0x98ff, 0xc12e, 0x21, 0 + .dw 0x9940, 0xc12e, 0x997f, 0xc12e, 0x21, 0 + .dw 0x99c0, 0xc12e, 0x9fff, 0xc12e, 0x21, 0 + .dw 0xa040, 0xc12e, 0xa07f, 0xc12e, 0x21, 0 + .dw 0xa0c0, 0xc12e, 0xa0ff, 0xc12e, 0x21, 0 + .dw 0xa140, 0xc12e, 0xa17f, 0xc12e, 0x21, 0 + .dw 0xa1c0, 0xc12e, 0xa1ff, 0xc12e, 0x21, 0 + .dw 0xa240, 0xc12e, 0xa27f, 0xc12e, 0x21, 0 + .dw 0xa2c0, 0xc12e, 0xa2ff, 0xc12e, 0x21, 0 + .dw 0xa340, 0xc12e, 0xa37f, 0xc12e, 0x21, 0 + .dw 0xa3c0, 0xc12e, 0xa3ff, 0xc12e, 0x21, 0 + .dw 0xa440, 0xc12e, 0xa47f, 0xc12e, 0x21, 0 + .dw 0xa4c0, 0xc12e, 0xa4ff, 0xc12e, 0x21, 0 + .dw 0xa540, 0xc12e, 0xa57f, 0xc12e, 0x21, 0 + .dw 0xa5c0, 0xc12e, 0xa5ff, 0xc12e, 0x21, 0 + .dw 0xa640, 0xc12e, 0xa67f, 0xc12e, 0x21, 0 + .dw 0xa6c0, 0xc12e, 0xa6ff, 0xc12e, 0x21, 0 + .dw 0xa740, 0xc12e, 0xa77f, 0xc12e, 0x21, 0 + .dw 0xa7c0, 0xc12e, 0xa7ff, 0xc12e, 0x21, 0 + .dw 0xa840, 0xc12e, 0xa87f, 0xc12e, 0x21, 0 + .dw 0xa8c0, 0xc12e, 0xa8ff, 0xc12e, 0x21, 0 + .dw 0xa940, 0xc12e, 0xa97f, 0xc12e, 0x21, 0 + .dw 0xa9c0, 0xc12e, 0xa9ff, 0xc12e, 0x21, 0 + .dw 0xaa40, 0xc12e, 0xaa7f, 0xc12e, 0x21, 0 + .dw 0xaac0, 0xc12e, 0xaaff, 0xc12e, 0x21, 0 + .dw 0xab40, 0xc12e, 0xab7f, 0xc12e, 0x21, 0 + .dw 0xabc0, 0xc12e, 0xabff, 0xc12e, 0x21, 0 + .dw 0xac40, 0xc12e, 0xac7f, 0xc12e, 0x21, 0 + .dw 0xacc0, 0xc12e, 0xacff, 0xc12e, 0x21, 0 + .dw 0xad40, 0xc12e, 0xad7f, 0xc12e, 0x21, 0 + .dw 0xadc0, 0xc12e, 0xadff, 0xc12e, 0x21, 0 + .dw 0xae40, 0xc12e, 0xae7f, 0xc12e, 0x21, 0 + .dw 0xaec0, 0xc12e, 0xaeff, 0xc12e, 0x21, 0 + .dw 0xaf40, 0xc12e, 0xaf7f, 0xc12e, 0x21, 0 + .dw 0xafc0, 0xc12e, 0xafff, 0xc12e, 0x21, 0 + .dw 0xb040, 0xc12e, 0xb07f, 0xc12e, 0x21, 0 + .dw 0xb0c0, 0xc12e, 0xb0ff, 0xc12e, 0x21, 0 + .dw 0xb140, 0xc12e, 0xb17f, 0xc12e, 0x21, 0 + .dw 0xb1c0, 0xc12e, 0xb1ff, 0xc12e, 0x21, 0 + .dw 0xb240, 0xc12e, 0xb27f, 0xc12e, 0x21, 0 + .dw 0xb2c0, 0xc12e, 0xb2ff, 0xc12e, 0x21, 0 + .dw 0xb340, 0xc12e, 0xb37f, 0xc12e, 0x21, 0 + .dw 0xb3c0, 0xc12e, 0xb3ff, 0xc12e, 0x21, 0 + .dw 0xb440, 0xc12e, 0xb47f, 0xc12e, 0x21, 0 + .dw 0xb4c0, 0xc12e, 0xb4ff, 0xc12e, 0x21, 0 + .dw 0xb540, 0xc12e, 0xb57f, 0xc12e, 0x21, 0 + .dw 0xb5c0, 0xc12e, 0xb5ff, 0xc12e, 0x21, 0 + .dw 0xb640, 0xc12e, 0xb67f, 0xc12e, 0x21, 0 + .dw 0xb6c0, 0xc12e, 0xb6ff, 0xc12e, 0x21, 0 + .dw 0xb740, 0xc12e, 0xb77f, 0xc12e, 0x21, 0 + .dw 0xb7c0, 0xc12e, 0xb7ff, 0xc12e, 0x21, 0 + .dw 0xb840, 0xc12e, 0xb87f, 0xc12e, 0x21, 0 + .dw 0xb8c0, 0xc12e, 0xb8ff, 0xc12e, 0x21, 0 + .dw 0xb940, 0xc12e, 0xb97f, 0xc12e, 0x21, 0 + .dw 0xb9c0, 0xc12e, 0xbfff, 0xc12e, 0x21, 0 + .dw 0xc040, 0xc12e, 0xc07f, 0xc12e, 0x21, 0 + .dw 0xc0c0, 0xc12e, 0xc0ff, 0xc12e, 0x21, 0 + .dw 0xc140, 0xc12e, 0xc17f, 0xc12e, 0x21, 0 + .dw 0xc1c0, 0xc12e, 0xc1ff, 0xc12e, 0x21, 0 + .dw 0xc240, 0xc12e, 0xc27f, 0xc12e, 0x21, 0 + .dw 0xc2c0, 0xc12e, 0xc2ff, 0xc12e, 0x21, 0 + .dw 0xc340, 0xc12e, 0xc37f, 0xc12e, 0x21, 0 + .dw 0xc3c0, 0xc12e, 0xc3ff, 0xc12e, 0x21, 0 + .dw 0xc440, 0xc12e, 0xc47f, 0xc12e, 0x21, 0 + .dw 0xc4c0, 0xc12e, 0xc4ff, 0xc12e, 0x21, 0 + .dw 0xc540, 0xc12e, 0xc57f, 0xc12e, 0x21, 0 + .dw 0xc5c0, 0xc12e, 0xc5ff, 0xc12e, 0x21, 0 + .dw 0xc640, 0xc12e, 0xc67f, 0xc12e, 0x21, 0 + .dw 0xc6c0, 0xc12e, 0xc6ff, 0xc12e, 0x21, 0 + .dw 0xc740, 0xc12e, 0xc77f, 0xc12e, 0x21, 0 + .dw 0xc7c0, 0xc12e, 0xc7ff, 0xc12e, 0x21, 0 + .dw 0xc840, 0xc12e, 0xc87f, 0xc12e, 0x21, 0 + .dw 0xc8c0, 0xc12e, 0xc8ff, 0xc12e, 0x21, 0 + .dw 0xc940, 0xc12e, 0xc97f, 0xc12e, 0x21, 0 + .dw 0xc9c0, 0xc12e, 0xc9ff, 0xc12e, 0x21, 0 + .dw 0xca40, 0xc12e, 0xca7f, 0xc12e, 0x21, 0 + .dw 0xcac0, 0xc12e, 0xcaff, 0xc12e, 0x21, 0 + .dw 0xcb40, 0xc12e, 0xcb7f, 0xc12e, 0x21, 0 + .dw 0xcbc0, 0xc12e, 0xcbff, 0xc12e, 0x21, 0 + .dw 0xcc40, 0xc12e, 0xcc7f, 0xc12e, 0x21, 0 + .dw 0xccc0, 0xc12e, 0xccff, 0xc12e, 0x21, 0 + .dw 0xcd40, 0xc12e, 0xcd7f, 0xc12e, 0x21, 0 + .dw 0xcdc0, 0xc12e, 0xcdff, 0xc12e, 0x21, 0 + .dw 0xce40, 0xc12e, 0xce7f, 0xc12e, 0x21, 0 + .dw 0xcec0, 0xc12e, 0xceff, 0xc12e, 0x21, 0 + .dw 0xcf40, 0xc12e, 0xcf7f, 0xc12e, 0x21, 0 + .dw 0xcfc0, 0xc12e, 0xcfff, 0xc12e, 0x21, 0 + .dw 0xd040, 0xc12e, 0xd07f, 0xc12e, 0x21, 0 + .dw 0xd0c0, 0xc12e, 0xd0ff, 0xc12e, 0x21, 0 + .dw 0xd140, 0xc12e, 0xd17f, 0xc12e, 0x21, 0 + .dw 0xd1c0, 0xc12e, 0xd1ff, 0xc12e, 0x21, 0 + .dw 0xd240, 0xc12e, 0xd27f, 0xc12e, 0x21, 0 + .dw 0xd2c0, 0xc12e, 0xd2ff, 0xc12e, 0x21, 0 + .dw 0xd340, 0xc12e, 0xd37f, 0xc12e, 0x21, 0 + .dw 0xd3c0, 0xc12e, 0xd3ff, 0xc12e, 0x21, 0 + .dw 0xd440, 0xc12e, 0xd47f, 0xc12e, 0x21, 0 + .dw 0xd4c0, 0xc12e, 0xd4ff, 0xc12e, 0x21, 0 + .dw 0xd540, 0xc12e, 0xd57f, 0xc12e, 0x21, 0 + .dw 0xd5c0, 0xc12e, 0xd5ff, 0xc12e, 0x21, 0 + .dw 0xd640, 0xc12e, 0xd67f, 0xc12e, 0x21, 0 + .dw 0xd6c0, 0xc12e, 0xd6ff, 0xc12e, 0x21, 0 + .dw 0xd740, 0xc12e, 0xd77f, 0xc12e, 0x21, 0 + .dw 0xd7c0, 0xc12e, 0xd7ff, 0xc12e, 0x21, 0 + .dw 0xd840, 0xc12e, 0xd87f, 0xc12e, 0x21, 0 + .dw 0xd8c0, 0xc12e, 0xd8ff, 0xc12e, 0x21, 0 + .dw 0xd940, 0xc12e, 0xd97f, 0xc12e, 0x21, 0 + .dw 0xd9c0, 0xc12e, 0xdfff, 0xc12e, 0x21, 0 + .dw 0xe040, 0xc12e, 0xe07f, 0xc12e, 0x21, 0 + .dw 0xe0c0, 0xc12e, 0xe0ff, 0xc12e, 0x21, 0 + .dw 0xe140, 0xc12e, 0xe17f, 0xc12e, 0x21, 0 + .dw 0xe1c0, 0xc12e, 0xe1ff, 0xc12e, 0x21, 0 + .dw 0xe240, 0xc12e, 0xe27f, 0xc12e, 0x21, 0 + .dw 0xe2c0, 0xc12e, 0xe2ff, 0xc12e, 0x21, 0 + .dw 0xe340, 0xc12e, 0xe37f, 0xc12e, 0x21, 0 + .dw 0xe3c0, 0xc12e, 0xe3ff, 0xc12e, 0x21, 0 + .dw 0xe440, 0xc12e, 0xe47f, 0xc12e, 0x21, 0 + .dw 0xe4c0, 0xc12e, 0xe4ff, 0xc12e, 0x21, 0 + .dw 0xe540, 0xc12e, 0xe57f, 0xc12e, 0x21, 0 + .dw 0xe5c0, 0xc12e, 0xe5ff, 0xc12e, 0x21, 0 + .dw 0xe640, 0xc12e, 0xe67f, 0xc12e, 0x21, 0 + .dw 0xe6c0, 0xc12e, 0xe6ff, 0xc12e, 0x21, 0 + .dw 0xe740, 0xc12e, 0xe77f, 0xc12e, 0x21, 0 + .dw 0xe7c0, 0xc12e, 0xe7ff, 0xc12e, 0x21, 0 + .dw 0xe840, 0xc12e, 0xe87f, 0xc12e, 0x21, 0 + .dw 0xe8c0, 0xc12e, 0xe8ff, 0xc12e, 0x21, 0 + .dw 0xe940, 0xc12e, 0xe97f, 0xc12e, 0x21, 0 + .dw 0xe9c0, 0xc12e, 0xe9ff, 0xc12e, 0x21, 0 + .dw 0xea40, 0xc12e, 0xea7f, 0xc12e, 0x21, 0 + .dw 0xeac0, 0xc12e, 0xeaff, 0xc12e, 0x21, 0 + .dw 0xeb40, 0xc12e, 0xeb7f, 0xc12e, 0x21, 0 + .dw 0xebc0, 0xc12e, 0xebff, 0xc12e, 0x21, 0 + .dw 0xec40, 0xc12e, 0xec7f, 0xc12e, 0x21, 0 + .dw 0xecc0, 0xc12e, 0xecff, 0xc12e, 0x21, 0 + .dw 0xed40, 0xc12e, 0xed7f, 0xc12e, 0x21, 0 + .dw 0xedc0, 0xc12e, 0xedff, 0xc12e, 0x21, 0 + .dw 0xee40, 0xc12e, 0xee7f, 0xc12e, 0x21, 0 + .dw 0xeec0, 0xc12e, 0xeeff, 0xc12e, 0x21, 0 + .dw 0xef40, 0xc12e, 0xef7f, 0xc12e, 0x21, 0 + .dw 0xefc0, 0xc12e, 0xefff, 0xc12e, 0x21, 0 + .dw 0xf040, 0xc12e, 0xf07f, 0xc12e, 0x21, 0 + .dw 0xf0c0, 0xc12e, 0xf0ff, 0xc12e, 0x21, 0 + .dw 0xf140, 0xc12e, 0xf17f, 0xc12e, 0x21, 0 + .dw 0xf1c0, 0xc12e, 0xf1ff, 0xc12e, 0x21, 0 + .dw 0xf240, 0xc12e, 0xf27f, 0xc12e, 0x21, 0 + .dw 0xf2c0, 0xc12e, 0xf2ff, 0xc12e, 0x21, 0 + .dw 0xf340, 0xc12e, 0xf37f, 0xc12e, 0x21, 0 + .dw 0xf3c0, 0xc12e, 0xf3ff, 0xc12e, 0x21, 0 + .dw 0xf440, 0xc12e, 0xf47f, 0xc12e, 0x21, 0 + .dw 0xf4c0, 0xc12e, 0xf4ff, 0xc12e, 0x21, 0 + .dw 0xf540, 0xc12e, 0xf57f, 0xc12e, 0x21, 0 + .dw 0xf5c0, 0xc12e, 0xf5ff, 0xc12e, 0x21, 0 + .dw 0xf640, 0xc12e, 0xf67f, 0xc12e, 0x21, 0 + .dw 0xf6c0, 0xc12e, 0xf6ff, 0xc12e, 0x21, 0 + .dw 0xf740, 0xc12e, 0xf77f, 0xc12e, 0x21, 0 + .dw 0xf7c0, 0xc12e, 0xf7ff, 0xc12e, 0x21, 0 + .dw 0xf840, 0xc12e, 0xf87f, 0xc12e, 0x21, 0 + .dw 0xf8c0, 0xc12e, 0xf8ff, 0xc12e, 0x21, 0 + .dw 0xf940, 0xc12e, 0xf97f, 0xc12e, 0x21, 0 + .dw 0xf9c0, 0xc12e, 0xffff, 0xc12e, 0x21, 0 + .dw 0x0040, 0xc12f, 0x007f, 0xc12f, 0x21, 0 + .dw 0x00c0, 0xc12f, 0x00ff, 0xc12f, 0x21, 0 + .dw 0x0140, 0xc12f, 0x017f, 0xc12f, 0x21, 0 + .dw 0x01c0, 0xc12f, 0x01ff, 0xc12f, 0x21, 0 + .dw 0x0240, 0xc12f, 0x027f, 0xc12f, 0x21, 0 + .dw 0x02c0, 0xc12f, 0x02ff, 0xc12f, 0x21, 0 + .dw 0x0340, 0xc12f, 0x037f, 0xc12f, 0x21, 0 + .dw 0x03c0, 0xc12f, 0x03ff, 0xc12f, 0x21, 0 + .dw 0x0440, 0xc12f, 0x047f, 0xc12f, 0x21, 0 + .dw 0x04c0, 0xc12f, 0x04ff, 0xc12f, 0x21, 0 + .dw 0x0540, 0xc12f, 0x057f, 0xc12f, 0x21, 0 + .dw 0x05c0, 0xc12f, 0x05ff, 0xc12f, 0x21, 0 + .dw 0x0640, 0xc12f, 0x067f, 0xc12f, 0x21, 0 + .dw 0x06c0, 0xc12f, 0x06ff, 0xc12f, 0x21, 0 + .dw 0x0740, 0xc12f, 0x077f, 0xc12f, 0x21, 0 + .dw 0x07c0, 0xc12f, 0x07ff, 0xc12f, 0x21, 0 + .dw 0x0840, 0xc12f, 0x087f, 0xc12f, 0x21, 0 + .dw 0x08c0, 0xc12f, 0x08ff, 0xc12f, 0x21, 0 + .dw 0x0940, 0xc12f, 0x097f, 0xc12f, 0x21, 0 + .dw 0x09c0, 0xc12f, 0x09ff, 0xc12f, 0x21, 0 + .dw 0x0a40, 0xc12f, 0x0a7f, 0xc12f, 0x21, 0 + .dw 0x0ac0, 0xc12f, 0x0aff, 0xc12f, 0x21, 0 + .dw 0x0b40, 0xc12f, 0x0b7f, 0xc12f, 0x21, 0 + .dw 0x0bc0, 0xc12f, 0x0bff, 0xc12f, 0x21, 0 + .dw 0x0c40, 0xc12f, 0x0c7f, 0xc12f, 0x21, 0 + .dw 0x0cc0, 0xc12f, 0x0cff, 0xc12f, 0x21, 0 + .dw 0x0d40, 0xc12f, 0x0d7f, 0xc12f, 0x21, 0 + .dw 0x0dc0, 0xc12f, 0x0dff, 0xc12f, 0x21, 0 + .dw 0x0e40, 0xc12f, 0x0e7f, 0xc12f, 0x21, 0 + .dw 0x0ec0, 0xc12f, 0x0eff, 0xc12f, 0x21, 0 + .dw 0x0f40, 0xc12f, 0x0f7f, 0xc12f, 0x21, 0 + .dw 0x0fc0, 0xc12f, 0x0fff, 0xc12f, 0x21, 0 + .dw 0x1040, 0xc12f, 0x107f, 0xc12f, 0x21, 0 + .dw 0x10c0, 0xc12f, 0x10ff, 0xc12f, 0x21, 0 + .dw 0x1140, 0xc12f, 0x117f, 0xc12f, 0x21, 0 + .dw 0x11c0, 0xc12f, 0x11ff, 0xc12f, 0x21, 0 + .dw 0x1240, 0xc12f, 0x127f, 0xc12f, 0x21, 0 + .dw 0x12c0, 0xc12f, 0x12ff, 0xc12f, 0x21, 0 + .dw 0x1340, 0xc12f, 0x137f, 0xc12f, 0x21, 0 + .dw 0x13c0, 0xc12f, 0x13ff, 0xc12f, 0x21, 0 + .dw 0x1440, 0xc12f, 0x147f, 0xc12f, 0x21, 0 + .dw 0x14c0, 0xc12f, 0x14ff, 0xc12f, 0x21, 0 + .dw 0x1540, 0xc12f, 0x157f, 0xc12f, 0x21, 0 + .dw 0x15c0, 0xc12f, 0x15ff, 0xc12f, 0x21, 0 + .dw 0x1640, 0xc12f, 0x167f, 0xc12f, 0x21, 0 + .dw 0x16c0, 0xc12f, 0x16ff, 0xc12f, 0x21, 0 + .dw 0x1740, 0xc12f, 0x177f, 0xc12f, 0x21, 0 + .dw 0x17c0, 0xc12f, 0x17ff, 0xc12f, 0x21, 0 + .dw 0x1840, 0xc12f, 0x187f, 0xc12f, 0x21, 0 + .dw 0x18c0, 0xc12f, 0x18ff, 0xc12f, 0x21, 0 + .dw 0x1940, 0xc12f, 0x197f, 0xc12f, 0x21, 0 + .dw 0x19c0, 0xc12f, 0x1fff, 0xc12f, 0x21, 0 + .dw 0x2040, 0xc12f, 0x207f, 0xc12f, 0x21, 0 + .dw 0x20c0, 0xc12f, 0x20ff, 0xc12f, 0x21, 0 + .dw 0x2140, 0xc12f, 0x217f, 0xc12f, 0x21, 0 + .dw 0x21c0, 0xc12f, 0x21ff, 0xc12f, 0x21, 0 + .dw 0x2240, 0xc12f, 0x227f, 0xc12f, 0x21, 0 + .dw 0x22c0, 0xc12f, 0x22ff, 0xc12f, 0x21, 0 + .dw 0x2340, 0xc12f, 0x237f, 0xc12f, 0x21, 0 + .dw 0x23c0, 0xc12f, 0x23ff, 0xc12f, 0x21, 0 + .dw 0x2440, 0xc12f, 0x247f, 0xc12f, 0x21, 0 + .dw 0x24c0, 0xc12f, 0x24ff, 0xc12f, 0x21, 0 + .dw 0x2540, 0xc12f, 0x257f, 0xc12f, 0x21, 0 + .dw 0x25c0, 0xc12f, 0x25ff, 0xc12f, 0x21, 0 + .dw 0x2640, 0xc12f, 0x267f, 0xc12f, 0x21, 0 + .dw 0x26c0, 0xc12f, 0x26ff, 0xc12f, 0x21, 0 + .dw 0x2740, 0xc12f, 0x277f, 0xc12f, 0x21, 0 + .dw 0x27c0, 0xc12f, 0x27ff, 0xc12f, 0x21, 0 + .dw 0x2840, 0xc12f, 0x287f, 0xc12f, 0x21, 0 + .dw 0x28c0, 0xc12f, 0x28ff, 0xc12f, 0x21, 0 + .dw 0x2940, 0xc12f, 0x297f, 0xc12f, 0x21, 0 + .dw 0x29c0, 0xc12f, 0x29ff, 0xc12f, 0x21, 0 + .dw 0x2a40, 0xc12f, 0x2a7f, 0xc12f, 0x21, 0 + .dw 0x2ac0, 0xc12f, 0x2aff, 0xc12f, 0x21, 0 + .dw 0x2b40, 0xc12f, 0x2b7f, 0xc12f, 0x21, 0 + .dw 0x2bc0, 0xc12f, 0x2bff, 0xc12f, 0x21, 0 + .dw 0x2c40, 0xc12f, 0x2c7f, 0xc12f, 0x21, 0 + .dw 0x2cc0, 0xc12f, 0x2cff, 0xc12f, 0x21, 0 + .dw 0x2d40, 0xc12f, 0x2d7f, 0xc12f, 0x21, 0 + .dw 0x2dc0, 0xc12f, 0x2dff, 0xc12f, 0x21, 0 + .dw 0x2e40, 0xc12f, 0x2e7f, 0xc12f, 0x21, 0 + .dw 0x2ec0, 0xc12f, 0x2eff, 0xc12f, 0x21, 0 + .dw 0x2f40, 0xc12f, 0x2f7f, 0xc12f, 0x21, 0 + .dw 0x2fc0, 0xc12f, 0x2fff, 0xc12f, 0x21, 0 + .dw 0x3040, 0xc12f, 0x307f, 0xc12f, 0x21, 0 + .dw 0x30c0, 0xc12f, 0x30ff, 0xc12f, 0x21, 0 + .dw 0x3140, 0xc12f, 0x317f, 0xc12f, 0x21, 0 + .dw 0x31c0, 0xc12f, 0x31ff, 0xc12f, 0x21, 0 + .dw 0x3240, 0xc12f, 0x327f, 0xc12f, 0x21, 0 + .dw 0x32c0, 0xc12f, 0x32ff, 0xc12f, 0x21, 0 + .dw 0x3340, 0xc12f, 0x337f, 0xc12f, 0x21, 0 + .dw 0x33c0, 0xc12f, 0x33ff, 0xc12f, 0x21, 0 + .dw 0x3440, 0xc12f, 0x347f, 0xc12f, 0x21, 0 + .dw 0x34c0, 0xc12f, 0x34ff, 0xc12f, 0x21, 0 + .dw 0x3540, 0xc12f, 0x357f, 0xc12f, 0x21, 0 + .dw 0x35c0, 0xc12f, 0x35ff, 0xc12f, 0x21, 0 + .dw 0x3640, 0xc12f, 0x367f, 0xc12f, 0x21, 0 + .dw 0x36c0, 0xc12f, 0x36ff, 0xc12f, 0x21, 0 + .dw 0x3740, 0xc12f, 0x377f, 0xc12f, 0x21, 0 + .dw 0x37c0, 0xc12f, 0x37ff, 0xc12f, 0x21, 0 + .dw 0x3840, 0xc12f, 0x387f, 0xc12f, 0x21, 0 + .dw 0x38c0, 0xc12f, 0x38ff, 0xc12f, 0x21, 0 + .dw 0x3940, 0xc12f, 0x397f, 0xc12f, 0x21, 0 + .dw 0x39c0, 0xc12f, 0x1fff, 0xc130, 0x21, 0 + .dw 0x3a00, 0xc130, 0x5fff, 0xc130, 0x21, 0 + .dw 0x7a00, 0xc130, 0x9fff, 0xc130, 0x21, 0 + .dw 0xba00, 0xc130, 0xdfff, 0xc130, 0x21, 0 + .dw 0xfa00, 0xc130, 0x1fff, 0xc131, 0x21, 0 + .dw 0x3a00, 0xc131, 0x5fff, 0xc131, 0x21, 0 + .dw 0x7a00, 0xc131, 0x9fff, 0xc131, 0x21, 0 + .dw 0xba00, 0xc131, 0xdfff, 0xc131, 0x21, 0 + .dw 0xfa00, 0xc131, 0x1fff, 0xc132, 0x21, 0 + .dw 0x3a00, 0xc132, 0x5fff, 0xc132, 0x21, 0 + .dw 0x7a00, 0xc132, 0x9fff, 0xc132, 0x21, 0 + .dw 0xba00, 0xc132, 0xdfff, 0xc132, 0x21, 0 + .dw 0xfa00, 0xc132, 0xffff, 0xc133, 0x21, 0 + .dw 0x1a00, 0xc134, 0x1fff, 0xc134, 0x21, 0 + .dw 0x3a00, 0xc134, 0x3fff, 0xc134, 0x21, 0 + .dw 0x5a00, 0xc134, 0x5fff, 0xc134, 0x21, 0 + .dw 0x7a00, 0xc134, 0x7fff, 0xc134, 0x21, 0 + .dw 0x9a00, 0xc134, 0x9fff, 0xc134, 0x21, 0 + .dw 0xba00, 0xc134, 0xbfff, 0xc134, 0x21, 0 + .dw 0xda00, 0xc134, 0xdfff, 0xc134, 0x21, 0 + .dw 0xfa00, 0xc134, 0xffff, 0xc134, 0x21, 0 + .dw 0x1a00, 0xc135, 0x1fff, 0xc135, 0x21, 0 + .dw 0x3a00, 0xc135, 0x3fff, 0xc135, 0x21, 0 + .dw 0x5a00, 0xc135, 0x5fff, 0xc135, 0x21, 0 + .dw 0x7a00, 0xc135, 0x7fff, 0xc135, 0x21, 0 + .dw 0x9a00, 0xc135, 0x9fff, 0xc135, 0x21, 0 + .dw 0xba00, 0xc135, 0xbfff, 0xc135, 0x21, 0 + .dw 0xda00, 0xc135, 0xdfff, 0xc135, 0x21, 0 + .dw 0xfa00, 0xc135, 0xffff, 0xc135, 0x21, 0 + .dw 0x1a00, 0xc136, 0x1fff, 0xc136, 0x21, 0 + .dw 0x3a00, 0xc136, 0x3fff, 0xc136, 0x21, 0 + .dw 0x5a00, 0xc136, 0x5fff, 0xc136, 0x21, 0 + .dw 0x7a00, 0xc136, 0x7fff, 0xc136, 0x21, 0 + .dw 0x9a00, 0xc136, 0x9fff, 0xc136, 0x21, 0 + .dw 0xba00, 0xc136, 0xbfff, 0xc136, 0x21, 0 + .dw 0xda00, 0xc136, 0xdfff, 0xc136, 0x21, 0 + .dw 0xfa00, 0xc136, 0xffff, 0xc136, 0x21, 0 + .dw 0x1a00, 0xc137, 0x1fff, 0xc137, 0x21, 0 + .dw 0x3a00, 0xc137, 0x1fff, 0xc138, 0x21, 0 + .dw 0x2040, 0xc138, 0x207f, 0xc138, 0x21, 0 + .dw 0x20c0, 0xc138, 0x20ff, 0xc138, 0x21, 0 + .dw 0x2140, 0xc138, 0x217f, 0xc138, 0x21, 0 + .dw 0x21c0, 0xc138, 0x21ff, 0xc138, 0x21, 0 + .dw 0x2240, 0xc138, 0x227f, 0xc138, 0x21, 0 + .dw 0x22c0, 0xc138, 0x22ff, 0xc138, 0x21, 0 + .dw 0x2340, 0xc138, 0x237f, 0xc138, 0x21, 0 + .dw 0x23c0, 0xc138, 0x23ff, 0xc138, 0x21, 0 + .dw 0x2440, 0xc138, 0x247f, 0xc138, 0x21, 0 + .dw 0x24c0, 0xc138, 0x24ff, 0xc138, 0x21, 0 + .dw 0x2540, 0xc138, 0x257f, 0xc138, 0x21, 0 + .dw 0x25c0, 0xc138, 0x25ff, 0xc138, 0x21, 0 + .dw 0x2640, 0xc138, 0x267f, 0xc138, 0x21, 0 + .dw 0x26c0, 0xc138, 0x26ff, 0xc138, 0x21, 0 + .dw 0x2740, 0xc138, 0x277f, 0xc138, 0x21, 0 + .dw 0x27c0, 0xc138, 0x27ff, 0xc138, 0x21, 0 + .dw 0x2840, 0xc138, 0x287f, 0xc138, 0x21, 0 + .dw 0x28c0, 0xc138, 0x28ff, 0xc138, 0x21, 0 + .dw 0x2940, 0xc138, 0x297f, 0xc138, 0x21, 0 + .dw 0x29c0, 0xc138, 0x29ff, 0xc138, 0x21, 0 + .dw 0x2a40, 0xc138, 0x2a7f, 0xc138, 0x21, 0 + .dw 0x2ac0, 0xc138, 0x2aff, 0xc138, 0x21, 0 + .dw 0x2b40, 0xc138, 0x2b7f, 0xc138, 0x21, 0 + .dw 0x2bc0, 0xc138, 0x2bff, 0xc138, 0x21, 0 + .dw 0x2c40, 0xc138, 0x2c7f, 0xc138, 0x21, 0 + .dw 0x2cc0, 0xc138, 0x2cff, 0xc138, 0x21, 0 + .dw 0x2d40, 0xc138, 0x2d7f, 0xc138, 0x21, 0 + .dw 0x2dc0, 0xc138, 0x2dff, 0xc138, 0x21, 0 + .dw 0x2e40, 0xc138, 0x2e7f, 0xc138, 0x21, 0 + .dw 0x2ec0, 0xc138, 0x2eff, 0xc138, 0x21, 0 + .dw 0x2f40, 0xc138, 0x2f7f, 0xc138, 0x21, 0 + .dw 0x2fc0, 0xc138, 0x2fff, 0xc138, 0x21, 0 + .dw 0x3040, 0xc138, 0x307f, 0xc138, 0x21, 0 + .dw 0x30c0, 0xc138, 0x30ff, 0xc138, 0x21, 0 + .dw 0x3140, 0xc138, 0x317f, 0xc138, 0x21, 0 + .dw 0x31c0, 0xc138, 0x31ff, 0xc138, 0x21, 0 + .dw 0x3240, 0xc138, 0x327f, 0xc138, 0x21, 0 + .dw 0x32c0, 0xc138, 0x32ff, 0xc138, 0x21, 0 + .dw 0x3340, 0xc138, 0x337f, 0xc138, 0x21, 0 + .dw 0x33c0, 0xc138, 0x33ff, 0xc138, 0x21, 0 + .dw 0x3440, 0xc138, 0x347f, 0xc138, 0x21, 0 + .dw 0x34c0, 0xc138, 0x34ff, 0xc138, 0x21, 0 + .dw 0x3540, 0xc138, 0x357f, 0xc138, 0x21, 0 + .dw 0x35c0, 0xc138, 0x35ff, 0xc138, 0x21, 0 + .dw 0x3640, 0xc138, 0x367f, 0xc138, 0x21, 0 + .dw 0x36c0, 0xc138, 0x36ff, 0xc138, 0x21, 0 + .dw 0x3740, 0xc138, 0x377f, 0xc138, 0x21, 0 + .dw 0x37c0, 0xc138, 0x37ff, 0xc138, 0x21, 0 + .dw 0x3840, 0xc138, 0x387f, 0xc138, 0x21, 0 + .dw 0x38c0, 0xc138, 0x38ff, 0xc138, 0x21, 0 + .dw 0x3940, 0xc138, 0x397f, 0xc138, 0x21, 0 + .dw 0x39c0, 0xc138, 0x5fff, 0xc138, 0x21, 0 + .dw 0x6040, 0xc138, 0x607f, 0xc138, 0x21, 0 + .dw 0x60c0, 0xc138, 0x60ff, 0xc138, 0x21, 0 + .dw 0x6140, 0xc138, 0x617f, 0xc138, 0x21, 0 + .dw 0x61c0, 0xc138, 0x61ff, 0xc138, 0x21, 0 + .dw 0x6240, 0xc138, 0x627f, 0xc138, 0x21, 0 + .dw 0x62c0, 0xc138, 0x62ff, 0xc138, 0x21, 0 + .dw 0x6340, 0xc138, 0x637f, 0xc138, 0x21, 0 + .dw 0x63c0, 0xc138, 0x63ff, 0xc138, 0x21, 0 + .dw 0x6440, 0xc138, 0x647f, 0xc138, 0x21, 0 + .dw 0x64c0, 0xc138, 0x64ff, 0xc138, 0x21, 0 + .dw 0x6540, 0xc138, 0x657f, 0xc138, 0x21, 0 + .dw 0x65c0, 0xc138, 0x65ff, 0xc138, 0x21, 0 + .dw 0x6640, 0xc138, 0x667f, 0xc138, 0x21, 0 + .dw 0x66c0, 0xc138, 0x66ff, 0xc138, 0x21, 0 + .dw 0x6740, 0xc138, 0x677f, 0xc138, 0x21, 0 + .dw 0x67c0, 0xc138, 0x67ff, 0xc138, 0x21, 0 + .dw 0x6840, 0xc138, 0x687f, 0xc138, 0x21, 0 + .dw 0x68c0, 0xc138, 0x68ff, 0xc138, 0x21, 0 + .dw 0x6940, 0xc138, 0x697f, 0xc138, 0x21, 0 + .dw 0x69c0, 0xc138, 0x69ff, 0xc138, 0x21, 0 + .dw 0x6a40, 0xc138, 0x6a7f, 0xc138, 0x21, 0 + .dw 0x6ac0, 0xc138, 0x6aff, 0xc138, 0x21, 0 + .dw 0x6b40, 0xc138, 0x6b7f, 0xc138, 0x21, 0 + .dw 0x6bc0, 0xc138, 0x6bff, 0xc138, 0x21, 0 + .dw 0x6c40, 0xc138, 0x6c7f, 0xc138, 0x21, 0 + .dw 0x6cc0, 0xc138, 0x6cff, 0xc138, 0x21, 0 + .dw 0x6d40, 0xc138, 0x6d7f, 0xc138, 0x21, 0 + .dw 0x6dc0, 0xc138, 0x6dff, 0xc138, 0x21, 0 + .dw 0x6e40, 0xc138, 0x6e7f, 0xc138, 0x21, 0 + .dw 0x6ec0, 0xc138, 0x6eff, 0xc138, 0x21, 0 + .dw 0x6f40, 0xc138, 0x6f7f, 0xc138, 0x21, 0 + .dw 0x6fc0, 0xc138, 0x6fff, 0xc138, 0x21, 0 + .dw 0x7040, 0xc138, 0x707f, 0xc138, 0x21, 0 + .dw 0x70c0, 0xc138, 0x70ff, 0xc138, 0x21, 0 + .dw 0x7140, 0xc138, 0x717f, 0xc138, 0x21, 0 + .dw 0x71c0, 0xc138, 0x71ff, 0xc138, 0x21, 0 + .dw 0x7240, 0xc138, 0x727f, 0xc138, 0x21, 0 + .dw 0x72c0, 0xc138, 0x72ff, 0xc138, 0x21, 0 + .dw 0x7340, 0xc138, 0x737f, 0xc138, 0x21, 0 + .dw 0x73c0, 0xc138, 0x73ff, 0xc138, 0x21, 0 + .dw 0x7440, 0xc138, 0x747f, 0xc138, 0x21, 0 + .dw 0x74c0, 0xc138, 0x74ff, 0xc138, 0x21, 0 + .dw 0x7540, 0xc138, 0x757f, 0xc138, 0x21, 0 + .dw 0x75c0, 0xc138, 0x75ff, 0xc138, 0x21, 0 + .dw 0x7640, 0xc138, 0x767f, 0xc138, 0x21, 0 + .dw 0x76c0, 0xc138, 0x76ff, 0xc138, 0x21, 0 + .dw 0x7740, 0xc138, 0x777f, 0xc138, 0x21, 0 + .dw 0x77c0, 0xc138, 0x77ff, 0xc138, 0x21, 0 + .dw 0x7840, 0xc138, 0x787f, 0xc138, 0x21, 0 + .dw 0x78c0, 0xc138, 0x78ff, 0xc138, 0x21, 0 + .dw 0x7940, 0xc138, 0x797f, 0xc138, 0x21, 0 + .dw 0x79c0, 0xc138, 0x9fff, 0xc138, 0x21, 0 + .dw 0xa040, 0xc138, 0xa07f, 0xc138, 0x21, 0 + .dw 0xa0c0, 0xc138, 0xa0ff, 0xc138, 0x21, 0 + .dw 0xa140, 0xc138, 0xa17f, 0xc138, 0x21, 0 + .dw 0xa1c0, 0xc138, 0xa1ff, 0xc138, 0x21, 0 + .dw 0xa240, 0xc138, 0xa27f, 0xc138, 0x21, 0 + .dw 0xa2c0, 0xc138, 0xa2ff, 0xc138, 0x21, 0 + .dw 0xa340, 0xc138, 0xa37f, 0xc138, 0x21, 0 + .dw 0xa3c0, 0xc138, 0xa3ff, 0xc138, 0x21, 0 + .dw 0xa440, 0xc138, 0xa47f, 0xc138, 0x21, 0 + .dw 0xa4c0, 0xc138, 0xa4ff, 0xc138, 0x21, 0 + .dw 0xa540, 0xc138, 0xa57f, 0xc138, 0x21, 0 + .dw 0xa5c0, 0xc138, 0xa5ff, 0xc138, 0x21, 0 + .dw 0xa640, 0xc138, 0xa67f, 0xc138, 0x21, 0 + .dw 0xa6c0, 0xc138, 0xa6ff, 0xc138, 0x21, 0 + .dw 0xa740, 0xc138, 0xa77f, 0xc138, 0x21, 0 + .dw 0xa7c0, 0xc138, 0xa7ff, 0xc138, 0x21, 0 + .dw 0xa840, 0xc138, 0xa87f, 0xc138, 0x21, 0 + .dw 0xa8c0, 0xc138, 0xa8ff, 0xc138, 0x21, 0 + .dw 0xa940, 0xc138, 0xa97f, 0xc138, 0x21, 0 + .dw 0xa9c0, 0xc138, 0xa9ff, 0xc138, 0x21, 0 + .dw 0xaa40, 0xc138, 0xaa7f, 0xc138, 0x21, 0 + .dw 0xaac0, 0xc138, 0xaaff, 0xc138, 0x21, 0 + .dw 0xab40, 0xc138, 0xab7f, 0xc138, 0x21, 0 + .dw 0xabc0, 0xc138, 0xabff, 0xc138, 0x21, 0 + .dw 0xac40, 0xc138, 0xac7f, 0xc138, 0x21, 0 + .dw 0xacc0, 0xc138, 0xacff, 0xc138, 0x21, 0 + .dw 0xad40, 0xc138, 0xad7f, 0xc138, 0x21, 0 + .dw 0xadc0, 0xc138, 0xadff, 0xc138, 0x21, 0 + .dw 0xae40, 0xc138, 0xae7f, 0xc138, 0x21, 0 + .dw 0xaec0, 0xc138, 0xaeff, 0xc138, 0x21, 0 + .dw 0xaf40, 0xc138, 0xaf7f, 0xc138, 0x21, 0 + .dw 0xafc0, 0xc138, 0xafff, 0xc138, 0x21, 0 + .dw 0xb040, 0xc138, 0xb07f, 0xc138, 0x21, 0 + .dw 0xb0c0, 0xc138, 0xb0ff, 0xc138, 0x21, 0 + .dw 0xb140, 0xc138, 0xb17f, 0xc138, 0x21, 0 + .dw 0xb1c0, 0xc138, 0xb1ff, 0xc138, 0x21, 0 + .dw 0xb240, 0xc138, 0xb27f, 0xc138, 0x21, 0 + .dw 0xb2c0, 0xc138, 0xb2ff, 0xc138, 0x21, 0 + .dw 0xb340, 0xc138, 0xb37f, 0xc138, 0x21, 0 + .dw 0xb3c0, 0xc138, 0xb3ff, 0xc138, 0x21, 0 + .dw 0xb440, 0xc138, 0xb47f, 0xc138, 0x21, 0 + .dw 0xb4c0, 0xc138, 0xb4ff, 0xc138, 0x21, 0 + .dw 0xb540, 0xc138, 0xb57f, 0xc138, 0x21, 0 + .dw 0xb5c0, 0xc138, 0xb5ff, 0xc138, 0x21, 0 + .dw 0xb640, 0xc138, 0xb67f, 0xc138, 0x21, 0 + .dw 0xb6c0, 0xc138, 0xb6ff, 0xc138, 0x21, 0 + .dw 0xb740, 0xc138, 0xb77f, 0xc138, 0x21, 0 + .dw 0xb7c0, 0xc138, 0xb7ff, 0xc138, 0x21, 0 + .dw 0xb840, 0xc138, 0xb87f, 0xc138, 0x21, 0 + .dw 0xb8c0, 0xc138, 0xb8ff, 0xc138, 0x21, 0 + .dw 0xb940, 0xc138, 0xb97f, 0xc138, 0x21, 0 + .dw 0xb9c0, 0xc138, 0xdfff, 0xc138, 0x21, 0 + .dw 0xe040, 0xc138, 0xe07f, 0xc138, 0x21, 0 + .dw 0xe0c0, 0xc138, 0xe0ff, 0xc138, 0x21, 0 + .dw 0xe140, 0xc138, 0xe17f, 0xc138, 0x21, 0 + .dw 0xe1c0, 0xc138, 0xe1ff, 0xc138, 0x21, 0 + .dw 0xe240, 0xc138, 0xe27f, 0xc138, 0x21, 0 + .dw 0xe2c0, 0xc138, 0xe2ff, 0xc138, 0x21, 0 + .dw 0xe340, 0xc138, 0xe37f, 0xc138, 0x21, 0 + .dw 0xe3c0, 0xc138, 0xe3ff, 0xc138, 0x21, 0 + .dw 0xe440, 0xc138, 0xe47f, 0xc138, 0x21, 0 + .dw 0xe4c0, 0xc138, 0xe4ff, 0xc138, 0x21, 0 + .dw 0xe540, 0xc138, 0xe57f, 0xc138, 0x21, 0 + .dw 0xe5c0, 0xc138, 0xe5ff, 0xc138, 0x21, 0 + .dw 0xe640, 0xc138, 0xe67f, 0xc138, 0x21, 0 + .dw 0xe6c0, 0xc138, 0xe6ff, 0xc138, 0x21, 0 + .dw 0xe740, 0xc138, 0xe77f, 0xc138, 0x21, 0 + .dw 0xe7c0, 0xc138, 0xe7ff, 0xc138, 0x21, 0 + .dw 0xe840, 0xc138, 0xe87f, 0xc138, 0x21, 0 + .dw 0xe8c0, 0xc138, 0xe8ff, 0xc138, 0x21, 0 + .dw 0xe940, 0xc138, 0xe97f, 0xc138, 0x21, 0 + .dw 0xe9c0, 0xc138, 0xe9ff, 0xc138, 0x21, 0 + .dw 0xea40, 0xc138, 0xea7f, 0xc138, 0x21, 0 + .dw 0xeac0, 0xc138, 0xeaff, 0xc138, 0x21, 0 + .dw 0xeb40, 0xc138, 0xeb7f, 0xc138, 0x21, 0 + .dw 0xebc0, 0xc138, 0xebff, 0xc138, 0x21, 0 + .dw 0xec40, 0xc138, 0xec7f, 0xc138, 0x21, 0 + .dw 0xecc0, 0xc138, 0xecff, 0xc138, 0x21, 0 + .dw 0xed40, 0xc138, 0xed7f, 0xc138, 0x21, 0 + .dw 0xedc0, 0xc138, 0xedff, 0xc138, 0x21, 0 + .dw 0xee40, 0xc138, 0xee7f, 0xc138, 0x21, 0 + .dw 0xeec0, 0xc138, 0xeeff, 0xc138, 0x21, 0 + .dw 0xef40, 0xc138, 0xef7f, 0xc138, 0x21, 0 + .dw 0xefc0, 0xc138, 0xefff, 0xc138, 0x21, 0 + .dw 0xf040, 0xc138, 0xf07f, 0xc138, 0x21, 0 + .dw 0xf0c0, 0xc138, 0xf0ff, 0xc138, 0x21, 0 + .dw 0xf140, 0xc138, 0xf17f, 0xc138, 0x21, 0 + .dw 0xf1c0, 0xc138, 0xf1ff, 0xc138, 0x21, 0 + .dw 0xf240, 0xc138, 0xf27f, 0xc138, 0x21, 0 + .dw 0xf2c0, 0xc138, 0xf2ff, 0xc138, 0x21, 0 + .dw 0xf340, 0xc138, 0xf37f, 0xc138, 0x21, 0 + .dw 0xf3c0, 0xc138, 0xf3ff, 0xc138, 0x21, 0 + .dw 0xf440, 0xc138, 0xf47f, 0xc138, 0x21, 0 + .dw 0xf4c0, 0xc138, 0xf4ff, 0xc138, 0x21, 0 + .dw 0xf540, 0xc138, 0xf57f, 0xc138, 0x21, 0 + .dw 0xf5c0, 0xc138, 0xf5ff, 0xc138, 0x21, 0 + .dw 0xf640, 0xc138, 0xf67f, 0xc138, 0x21, 0 + .dw 0xf6c0, 0xc138, 0xf6ff, 0xc138, 0x21, 0 + .dw 0xf740, 0xc138, 0xf77f, 0xc138, 0x21, 0 + .dw 0xf7c0, 0xc138, 0xf7ff, 0xc138, 0x21, 0 + .dw 0xf840, 0xc138, 0xf87f, 0xc138, 0x21, 0 + .dw 0xf8c0, 0xc138, 0xf8ff, 0xc138, 0x21, 0 + .dw 0xf940, 0xc138, 0xf97f, 0xc138, 0x21, 0 + .dw 0xf9c0, 0xc138, 0x1fff, 0xc139, 0x21, 0 + .dw 0x2040, 0xc139, 0x207f, 0xc139, 0x21, 0 + .dw 0x20c0, 0xc139, 0x20ff, 0xc139, 0x21, 0 + .dw 0x2140, 0xc139, 0x217f, 0xc139, 0x21, 0 + .dw 0x21c0, 0xc139, 0x21ff, 0xc139, 0x21, 0 + .dw 0x2240, 0xc139, 0x227f, 0xc139, 0x21, 0 + .dw 0x22c0, 0xc139, 0x22ff, 0xc139, 0x21, 0 + .dw 0x2340, 0xc139, 0x237f, 0xc139, 0x21, 0 + .dw 0x23c0, 0xc139, 0x23ff, 0xc139, 0x21, 0 + .dw 0x2440, 0xc139, 0x247f, 0xc139, 0x21, 0 + .dw 0x24c0, 0xc139, 0x24ff, 0xc139, 0x21, 0 + .dw 0x2540, 0xc139, 0x257f, 0xc139, 0x21, 0 + .dw 0x25c0, 0xc139, 0x25ff, 0xc139, 0x21, 0 + .dw 0x2640, 0xc139, 0x267f, 0xc139, 0x21, 0 + .dw 0x26c0, 0xc139, 0x26ff, 0xc139, 0x21, 0 + .dw 0x2740, 0xc139, 0x277f, 0xc139, 0x21, 0 + .dw 0x27c0, 0xc139, 0x27ff, 0xc139, 0x21, 0 + .dw 0x2840, 0xc139, 0x287f, 0xc139, 0x21, 0 + .dw 0x28c0, 0xc139, 0x28ff, 0xc139, 0x21, 0 + .dw 0x2940, 0xc139, 0x297f, 0xc139, 0x21, 0 + .dw 0x29c0, 0xc139, 0x29ff, 0xc139, 0x21, 0 + .dw 0x2a40, 0xc139, 0x2a7f, 0xc139, 0x21, 0 + .dw 0x2ac0, 0xc139, 0x2aff, 0xc139, 0x21, 0 + .dw 0x2b40, 0xc139, 0x2b7f, 0xc139, 0x21, 0 + .dw 0x2bc0, 0xc139, 0x2bff, 0xc139, 0x21, 0 + .dw 0x2c40, 0xc139, 0x2c7f, 0xc139, 0x21, 0 + .dw 0x2cc0, 0xc139, 0x2cff, 0xc139, 0x21, 0 + .dw 0x2d40, 0xc139, 0x2d7f, 0xc139, 0x21, 0 + .dw 0x2dc0, 0xc139, 0x2dff, 0xc139, 0x21, 0 + .dw 0x2e40, 0xc139, 0x2e7f, 0xc139, 0x21, 0 + .dw 0x2ec0, 0xc139, 0x2eff, 0xc139, 0x21, 0 + .dw 0x2f40, 0xc139, 0x2f7f, 0xc139, 0x21, 0 + .dw 0x2fc0, 0xc139, 0x2fff, 0xc139, 0x21, 0 + .dw 0x3040, 0xc139, 0x307f, 0xc139, 0x21, 0 + .dw 0x30c0, 0xc139, 0x30ff, 0xc139, 0x21, 0 + .dw 0x3140, 0xc139, 0x317f, 0xc139, 0x21, 0 + .dw 0x31c0, 0xc139, 0x31ff, 0xc139, 0x21, 0 + .dw 0x3240, 0xc139, 0x327f, 0xc139, 0x21, 0 + .dw 0x32c0, 0xc139, 0x32ff, 0xc139, 0x21, 0 + .dw 0x3340, 0xc139, 0x337f, 0xc139, 0x21, 0 + .dw 0x33c0, 0xc139, 0x33ff, 0xc139, 0x21, 0 + .dw 0x3440, 0xc139, 0x347f, 0xc139, 0x21, 0 + .dw 0x34c0, 0xc139, 0x34ff, 0xc139, 0x21, 0 + .dw 0x3540, 0xc139, 0x357f, 0xc139, 0x21, 0 + .dw 0x35c0, 0xc139, 0x35ff, 0xc139, 0x21, 0 + .dw 0x3640, 0xc139, 0x367f, 0xc139, 0x21, 0 + .dw 0x36c0, 0xc139, 0x36ff, 0xc139, 0x21, 0 + .dw 0x3740, 0xc139, 0x377f, 0xc139, 0x21, 0 + .dw 0x37c0, 0xc139, 0x37ff, 0xc139, 0x21, 0 + .dw 0x3840, 0xc139, 0x387f, 0xc139, 0x21, 0 + .dw 0x38c0, 0xc139, 0x38ff, 0xc139, 0x21, 0 + .dw 0x3940, 0xc139, 0x397f, 0xc139, 0x21, 0 + .dw 0x39c0, 0xc139, 0x5fff, 0xc139, 0x21, 0 + .dw 0x6040, 0xc139, 0x607f, 0xc139, 0x21, 0 + .dw 0x60c0, 0xc139, 0x60ff, 0xc139, 0x21, 0 + .dw 0x6140, 0xc139, 0x617f, 0xc139, 0x21, 0 + .dw 0x61c0, 0xc139, 0x61ff, 0xc139, 0x21, 0 + .dw 0x6240, 0xc139, 0x627f, 0xc139, 0x21, 0 + .dw 0x62c0, 0xc139, 0x62ff, 0xc139, 0x21, 0 + .dw 0x6340, 0xc139, 0x637f, 0xc139, 0x21, 0 + .dw 0x63c0, 0xc139, 0x63ff, 0xc139, 0x21, 0 + .dw 0x6440, 0xc139, 0x647f, 0xc139, 0x21, 0 + .dw 0x64c0, 0xc139, 0x64ff, 0xc139, 0x21, 0 + .dw 0x6540, 0xc139, 0x657f, 0xc139, 0x21, 0 + .dw 0x65c0, 0xc139, 0x65ff, 0xc139, 0x21, 0 + .dw 0x6640, 0xc139, 0x667f, 0xc139, 0x21, 0 + .dw 0x66c0, 0xc139, 0x66ff, 0xc139, 0x21, 0 + .dw 0x6740, 0xc139, 0x677f, 0xc139, 0x21, 0 + .dw 0x67c0, 0xc139, 0x67ff, 0xc139, 0x21, 0 + .dw 0x6840, 0xc139, 0x687f, 0xc139, 0x21, 0 + .dw 0x68c0, 0xc139, 0x68ff, 0xc139, 0x21, 0 + .dw 0x6940, 0xc139, 0x697f, 0xc139, 0x21, 0 + .dw 0x69c0, 0xc139, 0x69ff, 0xc139, 0x21, 0 + .dw 0x6a40, 0xc139, 0x6a7f, 0xc139, 0x21, 0 + .dw 0x6ac0, 0xc139, 0x6aff, 0xc139, 0x21, 0 + .dw 0x6b40, 0xc139, 0x6b7f, 0xc139, 0x21, 0 + .dw 0x6bc0, 0xc139, 0x6bff, 0xc139, 0x21, 0 + .dw 0x6c40, 0xc139, 0x6c7f, 0xc139, 0x21, 0 + .dw 0x6cc0, 0xc139, 0x6cff, 0xc139, 0x21, 0 + .dw 0x6d40, 0xc139, 0x6d7f, 0xc139, 0x21, 0 + .dw 0x6dc0, 0xc139, 0x6dff, 0xc139, 0x21, 0 + .dw 0x6e40, 0xc139, 0x6e7f, 0xc139, 0x21, 0 + .dw 0x6ec0, 0xc139, 0x6eff, 0xc139, 0x21, 0 + .dw 0x6f40, 0xc139, 0x6f7f, 0xc139, 0x21, 0 + .dw 0x6fc0, 0xc139, 0x6fff, 0xc139, 0x21, 0 + .dw 0x7040, 0xc139, 0x707f, 0xc139, 0x21, 0 + .dw 0x70c0, 0xc139, 0x70ff, 0xc139, 0x21, 0 + .dw 0x7140, 0xc139, 0x717f, 0xc139, 0x21, 0 + .dw 0x71c0, 0xc139, 0x71ff, 0xc139, 0x21, 0 + .dw 0x7240, 0xc139, 0x727f, 0xc139, 0x21, 0 + .dw 0x72c0, 0xc139, 0x72ff, 0xc139, 0x21, 0 + .dw 0x7340, 0xc139, 0x737f, 0xc139, 0x21, 0 + .dw 0x73c0, 0xc139, 0x73ff, 0xc139, 0x21, 0 + .dw 0x7440, 0xc139, 0x747f, 0xc139, 0x21, 0 + .dw 0x74c0, 0xc139, 0x74ff, 0xc139, 0x21, 0 + .dw 0x7540, 0xc139, 0x757f, 0xc139, 0x21, 0 + .dw 0x75c0, 0xc139, 0x75ff, 0xc139, 0x21, 0 + .dw 0x7640, 0xc139, 0x767f, 0xc139, 0x21, 0 + .dw 0x76c0, 0xc139, 0x76ff, 0xc139, 0x21, 0 + .dw 0x7740, 0xc139, 0x777f, 0xc139, 0x21, 0 + .dw 0x77c0, 0xc139, 0x77ff, 0xc139, 0x21, 0 + .dw 0x7840, 0xc139, 0x787f, 0xc139, 0x21, 0 + .dw 0x78c0, 0xc139, 0x78ff, 0xc139, 0x21, 0 + .dw 0x7940, 0xc139, 0x797f, 0xc139, 0x21, 0 + .dw 0x79c0, 0xc139, 0x9fff, 0xc139, 0x21, 0 + .dw 0xa040, 0xc139, 0xa07f, 0xc139, 0x21, 0 + .dw 0xa0c0, 0xc139, 0xa0ff, 0xc139, 0x21, 0 + .dw 0xa140, 0xc139, 0xa17f, 0xc139, 0x21, 0 + .dw 0xa1c0, 0xc139, 0xa1ff, 0xc139, 0x21, 0 + .dw 0xa240, 0xc139, 0xa27f, 0xc139, 0x21, 0 + .dw 0xa2c0, 0xc139, 0xa2ff, 0xc139, 0x21, 0 + .dw 0xa340, 0xc139, 0xa37f, 0xc139, 0x21, 0 + .dw 0xa3c0, 0xc139, 0xa3ff, 0xc139, 0x21, 0 + .dw 0xa440, 0xc139, 0xa47f, 0xc139, 0x21, 0 + .dw 0xa4c0, 0xc139, 0xa4ff, 0xc139, 0x21, 0 + .dw 0xa540, 0xc139, 0xa57f, 0xc139, 0x21, 0 + .dw 0xa5c0, 0xc139, 0xa5ff, 0xc139, 0x21, 0 + .dw 0xa640, 0xc139, 0xa67f, 0xc139, 0x21, 0 + .dw 0xa6c0, 0xc139, 0xa6ff, 0xc139, 0x21, 0 + .dw 0xa740, 0xc139, 0xa77f, 0xc139, 0x21, 0 + .dw 0xa7c0, 0xc139, 0xa7ff, 0xc139, 0x21, 0 + .dw 0xa840, 0xc139, 0xa87f, 0xc139, 0x21, 0 + .dw 0xa8c0, 0xc139, 0xa8ff, 0xc139, 0x21, 0 + .dw 0xa940, 0xc139, 0xa97f, 0xc139, 0x21, 0 + .dw 0xa9c0, 0xc139, 0xa9ff, 0xc139, 0x21, 0 + .dw 0xaa40, 0xc139, 0xaa7f, 0xc139, 0x21, 0 + .dw 0xaac0, 0xc139, 0xaaff, 0xc139, 0x21, 0 + .dw 0xab40, 0xc139, 0xab7f, 0xc139, 0x21, 0 + .dw 0xabc0, 0xc139, 0xabff, 0xc139, 0x21, 0 + .dw 0xac40, 0xc139, 0xac7f, 0xc139, 0x21, 0 + .dw 0xacc0, 0xc139, 0xacff, 0xc139, 0x21, 0 + .dw 0xad40, 0xc139, 0xad7f, 0xc139, 0x21, 0 + .dw 0xadc0, 0xc139, 0xadff, 0xc139, 0x21, 0 + .dw 0xae40, 0xc139, 0xae7f, 0xc139, 0x21, 0 + .dw 0xaec0, 0xc139, 0xaeff, 0xc139, 0x21, 0 + .dw 0xaf40, 0xc139, 0xaf7f, 0xc139, 0x21, 0 + .dw 0xafc0, 0xc139, 0xafff, 0xc139, 0x21, 0 + .dw 0xb040, 0xc139, 0xb07f, 0xc139, 0x21, 0 + .dw 0xb0c0, 0xc139, 0xb0ff, 0xc139, 0x21, 0 + .dw 0xb140, 0xc139, 0xb17f, 0xc139, 0x21, 0 + .dw 0xb1c0, 0xc139, 0xb1ff, 0xc139, 0x21, 0 + .dw 0xb240, 0xc139, 0xb27f, 0xc139, 0x21, 0 + .dw 0xb2c0, 0xc139, 0xb2ff, 0xc139, 0x21, 0 + .dw 0xb340, 0xc139, 0xb37f, 0xc139, 0x21, 0 + .dw 0xb3c0, 0xc139, 0xb3ff, 0xc139, 0x21, 0 + .dw 0xb440, 0xc139, 0xb47f, 0xc139, 0x21, 0 + .dw 0xb4c0, 0xc139, 0xb4ff, 0xc139, 0x21, 0 + .dw 0xb540, 0xc139, 0xb57f, 0xc139, 0x21, 0 + .dw 0xb5c0, 0xc139, 0xb5ff, 0xc139, 0x21, 0 + .dw 0xb640, 0xc139, 0xb67f, 0xc139, 0x21, 0 + .dw 0xb6c0, 0xc139, 0xb6ff, 0xc139, 0x21, 0 + .dw 0xb740, 0xc139, 0xb77f, 0xc139, 0x21, 0 + .dw 0xb7c0, 0xc139, 0xb7ff, 0xc139, 0x21, 0 + .dw 0xb840, 0xc139, 0xb87f, 0xc139, 0x21, 0 + .dw 0xb8c0, 0xc139, 0xb8ff, 0xc139, 0x21, 0 + .dw 0xb940, 0xc139, 0xb97f, 0xc139, 0x21, 0 + .dw 0xb9c0, 0xc139, 0xdfff, 0xc139, 0x21, 0 + .dw 0xe040, 0xc139, 0xe07f, 0xc139, 0x21, 0 + .dw 0xe0c0, 0xc139, 0xe0ff, 0xc139, 0x21, 0 + .dw 0xe140, 0xc139, 0xe17f, 0xc139, 0x21, 0 + .dw 0xe1c0, 0xc139, 0xe1ff, 0xc139, 0x21, 0 + .dw 0xe240, 0xc139, 0xe27f, 0xc139, 0x21, 0 + .dw 0xe2c0, 0xc139, 0xe2ff, 0xc139, 0x21, 0 + .dw 0xe340, 0xc139, 0xe37f, 0xc139, 0x21, 0 + .dw 0xe3c0, 0xc139, 0xe3ff, 0xc139, 0x21, 0 + .dw 0xe440, 0xc139, 0xe47f, 0xc139, 0x21, 0 + .dw 0xe4c0, 0xc139, 0xe4ff, 0xc139, 0x21, 0 + .dw 0xe540, 0xc139, 0xe57f, 0xc139, 0x21, 0 + .dw 0xe5c0, 0xc139, 0xe5ff, 0xc139, 0x21, 0 + .dw 0xe640, 0xc139, 0xe67f, 0xc139, 0x21, 0 + .dw 0xe6c0, 0xc139, 0xe6ff, 0xc139, 0x21, 0 + .dw 0xe740, 0xc139, 0xe77f, 0xc139, 0x21, 0 + .dw 0xe7c0, 0xc139, 0xe7ff, 0xc139, 0x21, 0 + .dw 0xe840, 0xc139, 0xe87f, 0xc139, 0x21, 0 + .dw 0xe8c0, 0xc139, 0xe8ff, 0xc139, 0x21, 0 + .dw 0xe940, 0xc139, 0xe97f, 0xc139, 0x21, 0 + .dw 0xe9c0, 0xc139, 0xe9ff, 0xc139, 0x21, 0 + .dw 0xea40, 0xc139, 0xea7f, 0xc139, 0x21, 0 + .dw 0xeac0, 0xc139, 0xeaff, 0xc139, 0x21, 0 + .dw 0xeb40, 0xc139, 0xeb7f, 0xc139, 0x21, 0 + .dw 0xebc0, 0xc139, 0xebff, 0xc139, 0x21, 0 + .dw 0xec40, 0xc139, 0xec7f, 0xc139, 0x21, 0 + .dw 0xecc0, 0xc139, 0xecff, 0xc139, 0x21, 0 + .dw 0xed40, 0xc139, 0xed7f, 0xc139, 0x21, 0 + .dw 0xedc0, 0xc139, 0xedff, 0xc139, 0x21, 0 + .dw 0xee40, 0xc139, 0xee7f, 0xc139, 0x21, 0 + .dw 0xeec0, 0xc139, 0xeeff, 0xc139, 0x21, 0 + .dw 0xef40, 0xc139, 0xef7f, 0xc139, 0x21, 0 + .dw 0xefc0, 0xc139, 0xefff, 0xc139, 0x21, 0 + .dw 0xf040, 0xc139, 0xf07f, 0xc139, 0x21, 0 + .dw 0xf0c0, 0xc139, 0xf0ff, 0xc139, 0x21, 0 + .dw 0xf140, 0xc139, 0xf17f, 0xc139, 0x21, 0 + .dw 0xf1c0, 0xc139, 0xf1ff, 0xc139, 0x21, 0 + .dw 0xf240, 0xc139, 0xf27f, 0xc139, 0x21, 0 + .dw 0xf2c0, 0xc139, 0xf2ff, 0xc139, 0x21, 0 + .dw 0xf340, 0xc139, 0xf37f, 0xc139, 0x21, 0 + .dw 0xf3c0, 0xc139, 0xf3ff, 0xc139, 0x21, 0 + .dw 0xf440, 0xc139, 0xf47f, 0xc139, 0x21, 0 + .dw 0xf4c0, 0xc139, 0xf4ff, 0xc139, 0x21, 0 + .dw 0xf540, 0xc139, 0xf57f, 0xc139, 0x21, 0 + .dw 0xf5c0, 0xc139, 0xf5ff, 0xc139, 0x21, 0 + .dw 0xf640, 0xc139, 0xf67f, 0xc139, 0x21, 0 + .dw 0xf6c0, 0xc139, 0xf6ff, 0xc139, 0x21, 0 + .dw 0xf740, 0xc139, 0xf77f, 0xc139, 0x21, 0 + .dw 0xf7c0, 0xc139, 0xf7ff, 0xc139, 0x21, 0 + .dw 0xf840, 0xc139, 0xf87f, 0xc139, 0x21, 0 + .dw 0xf8c0, 0xc139, 0xf8ff, 0xc139, 0x21, 0 + .dw 0xf940, 0xc139, 0xf97f, 0xc139, 0x21, 0 + .dw 0xf9c0, 0xc139, 0x1fff, 0xc13a, 0x21, 0 + .dw 0x2040, 0xc13a, 0x207f, 0xc13a, 0x21, 0 + .dw 0x20c0, 0xc13a, 0x20ff, 0xc13a, 0x21, 0 + .dw 0x2140, 0xc13a, 0x217f, 0xc13a, 0x21, 0 + .dw 0x21c0, 0xc13a, 0x21ff, 0xc13a, 0x21, 0 + .dw 0x2240, 0xc13a, 0x227f, 0xc13a, 0x21, 0 + .dw 0x22c0, 0xc13a, 0x22ff, 0xc13a, 0x21, 0 + .dw 0x2340, 0xc13a, 0x237f, 0xc13a, 0x21, 0 + .dw 0x23c0, 0xc13a, 0x23ff, 0xc13a, 0x21, 0 + .dw 0x2440, 0xc13a, 0x247f, 0xc13a, 0x21, 0 + .dw 0x24c0, 0xc13a, 0x24ff, 0xc13a, 0x21, 0 + .dw 0x2540, 0xc13a, 0x257f, 0xc13a, 0x21, 0 + .dw 0x25c0, 0xc13a, 0x25ff, 0xc13a, 0x21, 0 + .dw 0x2640, 0xc13a, 0x267f, 0xc13a, 0x21, 0 + .dw 0x26c0, 0xc13a, 0x26ff, 0xc13a, 0x21, 0 + .dw 0x2740, 0xc13a, 0x277f, 0xc13a, 0x21, 0 + .dw 0x27c0, 0xc13a, 0x27ff, 0xc13a, 0x21, 0 + .dw 0x2840, 0xc13a, 0x287f, 0xc13a, 0x21, 0 + .dw 0x28c0, 0xc13a, 0x28ff, 0xc13a, 0x21, 0 + .dw 0x2940, 0xc13a, 0x297f, 0xc13a, 0x21, 0 + .dw 0x29c0, 0xc13a, 0x29ff, 0xc13a, 0x21, 0 + .dw 0x2a40, 0xc13a, 0x2a7f, 0xc13a, 0x21, 0 + .dw 0x2ac0, 0xc13a, 0x2aff, 0xc13a, 0x21, 0 + .dw 0x2b40, 0xc13a, 0x2b7f, 0xc13a, 0x21, 0 + .dw 0x2bc0, 0xc13a, 0x2bff, 0xc13a, 0x21, 0 + .dw 0x2c40, 0xc13a, 0x2c7f, 0xc13a, 0x21, 0 + .dw 0x2cc0, 0xc13a, 0x2cff, 0xc13a, 0x21, 0 + .dw 0x2d40, 0xc13a, 0x2d7f, 0xc13a, 0x21, 0 + .dw 0x2dc0, 0xc13a, 0x2dff, 0xc13a, 0x21, 0 + .dw 0x2e40, 0xc13a, 0x2e7f, 0xc13a, 0x21, 0 + .dw 0x2ec0, 0xc13a, 0x2eff, 0xc13a, 0x21, 0 + .dw 0x2f40, 0xc13a, 0x2f7f, 0xc13a, 0x21, 0 + .dw 0x2fc0, 0xc13a, 0x2fff, 0xc13a, 0x21, 0 + .dw 0x3040, 0xc13a, 0x307f, 0xc13a, 0x21, 0 + .dw 0x30c0, 0xc13a, 0x30ff, 0xc13a, 0x21, 0 + .dw 0x3140, 0xc13a, 0x317f, 0xc13a, 0x21, 0 + .dw 0x31c0, 0xc13a, 0x31ff, 0xc13a, 0x21, 0 + .dw 0x3240, 0xc13a, 0x327f, 0xc13a, 0x21, 0 + .dw 0x32c0, 0xc13a, 0x32ff, 0xc13a, 0x21, 0 + .dw 0x3340, 0xc13a, 0x337f, 0xc13a, 0x21, 0 + .dw 0x33c0, 0xc13a, 0x33ff, 0xc13a, 0x21, 0 + .dw 0x3440, 0xc13a, 0x347f, 0xc13a, 0x21, 0 + .dw 0x34c0, 0xc13a, 0x34ff, 0xc13a, 0x21, 0 + .dw 0x3540, 0xc13a, 0x357f, 0xc13a, 0x21, 0 + .dw 0x35c0, 0xc13a, 0x35ff, 0xc13a, 0x21, 0 + .dw 0x3640, 0xc13a, 0x367f, 0xc13a, 0x21, 0 + .dw 0x36c0, 0xc13a, 0x36ff, 0xc13a, 0x21, 0 + .dw 0x3740, 0xc13a, 0x377f, 0xc13a, 0x21, 0 + .dw 0x37c0, 0xc13a, 0x37ff, 0xc13a, 0x21, 0 + .dw 0x3840, 0xc13a, 0x387f, 0xc13a, 0x21, 0 + .dw 0x38c0, 0xc13a, 0x38ff, 0xc13a, 0x21, 0 + .dw 0x3940, 0xc13a, 0x397f, 0xc13a, 0x21, 0 + .dw 0x39c0, 0xc13a, 0x5fff, 0xc13a, 0x21, 0 + .dw 0x6040, 0xc13a, 0x607f, 0xc13a, 0x21, 0 + .dw 0x60c0, 0xc13a, 0x60ff, 0xc13a, 0x21, 0 + .dw 0x6140, 0xc13a, 0x617f, 0xc13a, 0x21, 0 + .dw 0x61c0, 0xc13a, 0x61ff, 0xc13a, 0x21, 0 + .dw 0x6240, 0xc13a, 0x627f, 0xc13a, 0x21, 0 + .dw 0x62c0, 0xc13a, 0x62ff, 0xc13a, 0x21, 0 + .dw 0x6340, 0xc13a, 0x637f, 0xc13a, 0x21, 0 + .dw 0x63c0, 0xc13a, 0x63ff, 0xc13a, 0x21, 0 + .dw 0x6440, 0xc13a, 0x647f, 0xc13a, 0x21, 0 + .dw 0x64c0, 0xc13a, 0x64ff, 0xc13a, 0x21, 0 + .dw 0x6540, 0xc13a, 0x657f, 0xc13a, 0x21, 0 + .dw 0x65c0, 0xc13a, 0x65ff, 0xc13a, 0x21, 0 + .dw 0x6640, 0xc13a, 0x667f, 0xc13a, 0x21, 0 + .dw 0x66c0, 0xc13a, 0x66ff, 0xc13a, 0x21, 0 + .dw 0x6740, 0xc13a, 0x677f, 0xc13a, 0x21, 0 + .dw 0x67c0, 0xc13a, 0x67ff, 0xc13a, 0x21, 0 + .dw 0x6840, 0xc13a, 0x687f, 0xc13a, 0x21, 0 + .dw 0x68c0, 0xc13a, 0x68ff, 0xc13a, 0x21, 0 + .dw 0x6940, 0xc13a, 0x697f, 0xc13a, 0x21, 0 + .dw 0x69c0, 0xc13a, 0x69ff, 0xc13a, 0x21, 0 + .dw 0x6a40, 0xc13a, 0x6a7f, 0xc13a, 0x21, 0 + .dw 0x6ac0, 0xc13a, 0x6aff, 0xc13a, 0x21, 0 + .dw 0x6b40, 0xc13a, 0x6b7f, 0xc13a, 0x21, 0 + .dw 0x6bc0, 0xc13a, 0x6bff, 0xc13a, 0x21, 0 + .dw 0x6c40, 0xc13a, 0x6c7f, 0xc13a, 0x21, 0 + .dw 0x6cc0, 0xc13a, 0x6cff, 0xc13a, 0x21, 0 + .dw 0x6d40, 0xc13a, 0x6d7f, 0xc13a, 0x21, 0 + .dw 0x6dc0, 0xc13a, 0x6dff, 0xc13a, 0x21, 0 + .dw 0x6e40, 0xc13a, 0x6e7f, 0xc13a, 0x21, 0 + .dw 0x6ec0, 0xc13a, 0x6eff, 0xc13a, 0x21, 0 + .dw 0x6f40, 0xc13a, 0x6f7f, 0xc13a, 0x21, 0 + .dw 0x6fc0, 0xc13a, 0x6fff, 0xc13a, 0x21, 0 + .dw 0x7040, 0xc13a, 0x707f, 0xc13a, 0x21, 0 + .dw 0x70c0, 0xc13a, 0x70ff, 0xc13a, 0x21, 0 + .dw 0x7140, 0xc13a, 0x717f, 0xc13a, 0x21, 0 + .dw 0x71c0, 0xc13a, 0x71ff, 0xc13a, 0x21, 0 + .dw 0x7240, 0xc13a, 0x727f, 0xc13a, 0x21, 0 + .dw 0x72c0, 0xc13a, 0x72ff, 0xc13a, 0x21, 0 + .dw 0x7340, 0xc13a, 0x737f, 0xc13a, 0x21, 0 + .dw 0x73c0, 0xc13a, 0x73ff, 0xc13a, 0x21, 0 + .dw 0x7440, 0xc13a, 0x747f, 0xc13a, 0x21, 0 + .dw 0x74c0, 0xc13a, 0x74ff, 0xc13a, 0x21, 0 + .dw 0x7540, 0xc13a, 0x757f, 0xc13a, 0x21, 0 + .dw 0x75c0, 0xc13a, 0x75ff, 0xc13a, 0x21, 0 + .dw 0x7640, 0xc13a, 0x767f, 0xc13a, 0x21, 0 + .dw 0x76c0, 0xc13a, 0x76ff, 0xc13a, 0x21, 0 + .dw 0x7740, 0xc13a, 0x777f, 0xc13a, 0x21, 0 + .dw 0x77c0, 0xc13a, 0x77ff, 0xc13a, 0x21, 0 + .dw 0x7840, 0xc13a, 0x787f, 0xc13a, 0x21, 0 + .dw 0x78c0, 0xc13a, 0x78ff, 0xc13a, 0x21, 0 + .dw 0x7940, 0xc13a, 0x797f, 0xc13a, 0x21, 0 + .dw 0x79c0, 0xc13a, 0x9fff, 0xc13a, 0x21, 0 + .dw 0xa040, 0xc13a, 0xa07f, 0xc13a, 0x21, 0 + .dw 0xa0c0, 0xc13a, 0xa0ff, 0xc13a, 0x21, 0 + .dw 0xa140, 0xc13a, 0xa17f, 0xc13a, 0x21, 0 + .dw 0xa1c0, 0xc13a, 0xa1ff, 0xc13a, 0x21, 0 + .dw 0xa240, 0xc13a, 0xa27f, 0xc13a, 0x21, 0 + .dw 0xa2c0, 0xc13a, 0xa2ff, 0xc13a, 0x21, 0 + .dw 0xa340, 0xc13a, 0xa37f, 0xc13a, 0x21, 0 + .dw 0xa3c0, 0xc13a, 0xa3ff, 0xc13a, 0x21, 0 + .dw 0xa440, 0xc13a, 0xa47f, 0xc13a, 0x21, 0 + .dw 0xa4c0, 0xc13a, 0xa4ff, 0xc13a, 0x21, 0 + .dw 0xa540, 0xc13a, 0xa57f, 0xc13a, 0x21, 0 + .dw 0xa5c0, 0xc13a, 0xa5ff, 0xc13a, 0x21, 0 + .dw 0xa640, 0xc13a, 0xa67f, 0xc13a, 0x21, 0 + .dw 0xa6c0, 0xc13a, 0xa6ff, 0xc13a, 0x21, 0 + .dw 0xa740, 0xc13a, 0xa77f, 0xc13a, 0x21, 0 + .dw 0xa7c0, 0xc13a, 0xa7ff, 0xc13a, 0x21, 0 + .dw 0xa840, 0xc13a, 0xa87f, 0xc13a, 0x21, 0 + .dw 0xa8c0, 0xc13a, 0xa8ff, 0xc13a, 0x21, 0 + .dw 0xa940, 0xc13a, 0xa97f, 0xc13a, 0x21, 0 + .dw 0xa9c0, 0xc13a, 0xa9ff, 0xc13a, 0x21, 0 + .dw 0xaa40, 0xc13a, 0xaa7f, 0xc13a, 0x21, 0 + .dw 0xaac0, 0xc13a, 0xaaff, 0xc13a, 0x21, 0 + .dw 0xab40, 0xc13a, 0xab7f, 0xc13a, 0x21, 0 + .dw 0xabc0, 0xc13a, 0xabff, 0xc13a, 0x21, 0 + .dw 0xac40, 0xc13a, 0xac7f, 0xc13a, 0x21, 0 + .dw 0xacc0, 0xc13a, 0xacff, 0xc13a, 0x21, 0 + .dw 0xad40, 0xc13a, 0xad7f, 0xc13a, 0x21, 0 + .dw 0xadc0, 0xc13a, 0xadff, 0xc13a, 0x21, 0 + .dw 0xae40, 0xc13a, 0xae7f, 0xc13a, 0x21, 0 + .dw 0xaec0, 0xc13a, 0xaeff, 0xc13a, 0x21, 0 + .dw 0xaf40, 0xc13a, 0xaf7f, 0xc13a, 0x21, 0 + .dw 0xafc0, 0xc13a, 0xafff, 0xc13a, 0x21, 0 + .dw 0xb040, 0xc13a, 0xb07f, 0xc13a, 0x21, 0 + .dw 0xb0c0, 0xc13a, 0xb0ff, 0xc13a, 0x21, 0 + .dw 0xb140, 0xc13a, 0xb17f, 0xc13a, 0x21, 0 + .dw 0xb1c0, 0xc13a, 0xb1ff, 0xc13a, 0x21, 0 + .dw 0xb240, 0xc13a, 0xb27f, 0xc13a, 0x21, 0 + .dw 0xb2c0, 0xc13a, 0xb2ff, 0xc13a, 0x21, 0 + .dw 0xb340, 0xc13a, 0xb37f, 0xc13a, 0x21, 0 + .dw 0xb3c0, 0xc13a, 0xb3ff, 0xc13a, 0x21, 0 + .dw 0xb440, 0xc13a, 0xb47f, 0xc13a, 0x21, 0 + .dw 0xb4c0, 0xc13a, 0xb4ff, 0xc13a, 0x21, 0 + .dw 0xb540, 0xc13a, 0xb57f, 0xc13a, 0x21, 0 + .dw 0xb5c0, 0xc13a, 0xb5ff, 0xc13a, 0x21, 0 + .dw 0xb640, 0xc13a, 0xb67f, 0xc13a, 0x21, 0 + .dw 0xb6c0, 0xc13a, 0xb6ff, 0xc13a, 0x21, 0 + .dw 0xb740, 0xc13a, 0xb77f, 0xc13a, 0x21, 0 + .dw 0xb7c0, 0xc13a, 0xb7ff, 0xc13a, 0x21, 0 + .dw 0xb840, 0xc13a, 0xb87f, 0xc13a, 0x21, 0 + .dw 0xb8c0, 0xc13a, 0xb8ff, 0xc13a, 0x21, 0 + .dw 0xb940, 0xc13a, 0xb97f, 0xc13a, 0x21, 0 + .dw 0xb9c0, 0xc13a, 0xdfff, 0xc13a, 0x21, 0 + .dw 0xe040, 0xc13a, 0xe07f, 0xc13a, 0x21, 0 + .dw 0xe0c0, 0xc13a, 0xe0ff, 0xc13a, 0x21, 0 + .dw 0xe140, 0xc13a, 0xe17f, 0xc13a, 0x21, 0 + .dw 0xe1c0, 0xc13a, 0xe1ff, 0xc13a, 0x21, 0 + .dw 0xe240, 0xc13a, 0xe27f, 0xc13a, 0x21, 0 + .dw 0xe2c0, 0xc13a, 0xe2ff, 0xc13a, 0x21, 0 + .dw 0xe340, 0xc13a, 0xe37f, 0xc13a, 0x21, 0 + .dw 0xe3c0, 0xc13a, 0xe3ff, 0xc13a, 0x21, 0 + .dw 0xe440, 0xc13a, 0xe47f, 0xc13a, 0x21, 0 + .dw 0xe4c0, 0xc13a, 0xe4ff, 0xc13a, 0x21, 0 + .dw 0xe540, 0xc13a, 0xe57f, 0xc13a, 0x21, 0 + .dw 0xe5c0, 0xc13a, 0xe5ff, 0xc13a, 0x21, 0 + .dw 0xe640, 0xc13a, 0xe67f, 0xc13a, 0x21, 0 + .dw 0xe6c0, 0xc13a, 0xe6ff, 0xc13a, 0x21, 0 + .dw 0xe740, 0xc13a, 0xe77f, 0xc13a, 0x21, 0 + .dw 0xe7c0, 0xc13a, 0xe7ff, 0xc13a, 0x21, 0 + .dw 0xe840, 0xc13a, 0xe87f, 0xc13a, 0x21, 0 + .dw 0xe8c0, 0xc13a, 0xe8ff, 0xc13a, 0x21, 0 + .dw 0xe940, 0xc13a, 0xe97f, 0xc13a, 0x21, 0 + .dw 0xe9c0, 0xc13a, 0xe9ff, 0xc13a, 0x21, 0 + .dw 0xea40, 0xc13a, 0xea7f, 0xc13a, 0x21, 0 + .dw 0xeac0, 0xc13a, 0xeaff, 0xc13a, 0x21, 0 + .dw 0xeb40, 0xc13a, 0xeb7f, 0xc13a, 0x21, 0 + .dw 0xebc0, 0xc13a, 0xebff, 0xc13a, 0x21, 0 + .dw 0xec40, 0xc13a, 0xec7f, 0xc13a, 0x21, 0 + .dw 0xecc0, 0xc13a, 0xecff, 0xc13a, 0x21, 0 + .dw 0xed40, 0xc13a, 0xed7f, 0xc13a, 0x21, 0 + .dw 0xedc0, 0xc13a, 0xedff, 0xc13a, 0x21, 0 + .dw 0xee40, 0xc13a, 0xee7f, 0xc13a, 0x21, 0 + .dw 0xeec0, 0xc13a, 0xeeff, 0xc13a, 0x21, 0 + .dw 0xef40, 0xc13a, 0xef7f, 0xc13a, 0x21, 0 + .dw 0xefc0, 0xc13a, 0xefff, 0xc13a, 0x21, 0 + .dw 0xf040, 0xc13a, 0xf07f, 0xc13a, 0x21, 0 + .dw 0xf0c0, 0xc13a, 0xf0ff, 0xc13a, 0x21, 0 + .dw 0xf140, 0xc13a, 0xf17f, 0xc13a, 0x21, 0 + .dw 0xf1c0, 0xc13a, 0xf1ff, 0xc13a, 0x21, 0 + .dw 0xf240, 0xc13a, 0xf27f, 0xc13a, 0x21, 0 + .dw 0xf2c0, 0xc13a, 0xf2ff, 0xc13a, 0x21, 0 + .dw 0xf340, 0xc13a, 0xf37f, 0xc13a, 0x21, 0 + .dw 0xf3c0, 0xc13a, 0xf3ff, 0xc13a, 0x21, 0 + .dw 0xf440, 0xc13a, 0xf47f, 0xc13a, 0x21, 0 + .dw 0xf4c0, 0xc13a, 0xf4ff, 0xc13a, 0x21, 0 + .dw 0xf540, 0xc13a, 0xf57f, 0xc13a, 0x21, 0 + .dw 0xf5c0, 0xc13a, 0xf5ff, 0xc13a, 0x21, 0 + .dw 0xf640, 0xc13a, 0xf67f, 0xc13a, 0x21, 0 + .dw 0xf6c0, 0xc13a, 0xf6ff, 0xc13a, 0x21, 0 + .dw 0xf740, 0xc13a, 0xf77f, 0xc13a, 0x21, 0 + .dw 0xf7c0, 0xc13a, 0xf7ff, 0xc13a, 0x21, 0 + .dw 0xf840, 0xc13a, 0xf87f, 0xc13a, 0x21, 0 + .dw 0xf8c0, 0xc13a, 0xf8ff, 0xc13a, 0x21, 0 + .dw 0xf940, 0xc13a, 0xf97f, 0xc13a, 0x21, 0 + .dw 0xf9c0, 0xc13a, 0xffff, 0xc13b, 0x21, 0 + .dw 0x0040, 0xc13c, 0x007f, 0xc13c, 0x21, 0 + .dw 0x00c0, 0xc13c, 0x00ff, 0xc13c, 0x21, 0 + .dw 0x0140, 0xc13c, 0x017f, 0xc13c, 0x21, 0 + .dw 0x01c0, 0xc13c, 0x01ff, 0xc13c, 0x21, 0 + .dw 0x0240, 0xc13c, 0x027f, 0xc13c, 0x21, 0 + .dw 0x02c0, 0xc13c, 0x02ff, 0xc13c, 0x21, 0 + .dw 0x0340, 0xc13c, 0x037f, 0xc13c, 0x21, 0 + .dw 0x03c0, 0xc13c, 0x03ff, 0xc13c, 0x21, 0 + .dw 0x0440, 0xc13c, 0x047f, 0xc13c, 0x21, 0 + .dw 0x04c0, 0xc13c, 0x04ff, 0xc13c, 0x21, 0 + .dw 0x0540, 0xc13c, 0x057f, 0xc13c, 0x21, 0 + .dw 0x05c0, 0xc13c, 0x05ff, 0xc13c, 0x21, 0 + .dw 0x0640, 0xc13c, 0x067f, 0xc13c, 0x21, 0 + .dw 0x06c0, 0xc13c, 0x06ff, 0xc13c, 0x21, 0 + .dw 0x0740, 0xc13c, 0x077f, 0xc13c, 0x21, 0 + .dw 0x07c0, 0xc13c, 0x07ff, 0xc13c, 0x21, 0 + .dw 0x0840, 0xc13c, 0x087f, 0xc13c, 0x21, 0 + .dw 0x08c0, 0xc13c, 0x08ff, 0xc13c, 0x21, 0 + .dw 0x0940, 0xc13c, 0x097f, 0xc13c, 0x21, 0 + .dw 0x09c0, 0xc13c, 0x09ff, 0xc13c, 0x21, 0 + .dw 0x0a40, 0xc13c, 0x0a7f, 0xc13c, 0x21, 0 + .dw 0x0ac0, 0xc13c, 0x0aff, 0xc13c, 0x21, 0 + .dw 0x0b40, 0xc13c, 0x0b7f, 0xc13c, 0x21, 0 + .dw 0x0bc0, 0xc13c, 0x0bff, 0xc13c, 0x21, 0 + .dw 0x0c40, 0xc13c, 0x0c7f, 0xc13c, 0x21, 0 + .dw 0x0cc0, 0xc13c, 0x0cff, 0xc13c, 0x21, 0 + .dw 0x0d40, 0xc13c, 0x0d7f, 0xc13c, 0x21, 0 + .dw 0x0dc0, 0xc13c, 0x0dff, 0xc13c, 0x21, 0 + .dw 0x0e40, 0xc13c, 0x0e7f, 0xc13c, 0x21, 0 + .dw 0x0ec0, 0xc13c, 0x0eff, 0xc13c, 0x21, 0 + .dw 0x0f40, 0xc13c, 0x0f7f, 0xc13c, 0x21, 0 + .dw 0x0fc0, 0xc13c, 0x0fff, 0xc13c, 0x21, 0 + .dw 0x1040, 0xc13c, 0x107f, 0xc13c, 0x21, 0 + .dw 0x10c0, 0xc13c, 0x10ff, 0xc13c, 0x21, 0 + .dw 0x1140, 0xc13c, 0x117f, 0xc13c, 0x21, 0 + .dw 0x11c0, 0xc13c, 0x11ff, 0xc13c, 0x21, 0 + .dw 0x1240, 0xc13c, 0x127f, 0xc13c, 0x21, 0 + .dw 0x12c0, 0xc13c, 0x12ff, 0xc13c, 0x21, 0 + .dw 0x1340, 0xc13c, 0x137f, 0xc13c, 0x21, 0 + .dw 0x13c0, 0xc13c, 0x13ff, 0xc13c, 0x21, 0 + .dw 0x1440, 0xc13c, 0x147f, 0xc13c, 0x21, 0 + .dw 0x14c0, 0xc13c, 0x14ff, 0xc13c, 0x21, 0 + .dw 0x1540, 0xc13c, 0x157f, 0xc13c, 0x21, 0 + .dw 0x15c0, 0xc13c, 0x15ff, 0xc13c, 0x21, 0 + .dw 0x1640, 0xc13c, 0x167f, 0xc13c, 0x21, 0 + .dw 0x16c0, 0xc13c, 0x16ff, 0xc13c, 0x21, 0 + .dw 0x1740, 0xc13c, 0x177f, 0xc13c, 0x21, 0 + .dw 0x17c0, 0xc13c, 0x17ff, 0xc13c, 0x21, 0 + .dw 0x1840, 0xc13c, 0x187f, 0xc13c, 0x21, 0 + .dw 0x18c0, 0xc13c, 0x18ff, 0xc13c, 0x21, 0 + .dw 0x1940, 0xc13c, 0x197f, 0xc13c, 0x21, 0 + .dw 0x19c0, 0xc13c, 0x1fff, 0xc13c, 0x21, 0 + .dw 0x2040, 0xc13c, 0x207f, 0xc13c, 0x21, 0 + .dw 0x20c0, 0xc13c, 0x20ff, 0xc13c, 0x21, 0 + .dw 0x2140, 0xc13c, 0x217f, 0xc13c, 0x21, 0 + .dw 0x21c0, 0xc13c, 0x21ff, 0xc13c, 0x21, 0 + .dw 0x2240, 0xc13c, 0x227f, 0xc13c, 0x21, 0 + .dw 0x22c0, 0xc13c, 0x22ff, 0xc13c, 0x21, 0 + .dw 0x2340, 0xc13c, 0x237f, 0xc13c, 0x21, 0 + .dw 0x23c0, 0xc13c, 0x23ff, 0xc13c, 0x21, 0 + .dw 0x2440, 0xc13c, 0x247f, 0xc13c, 0x21, 0 + .dw 0x24c0, 0xc13c, 0x24ff, 0xc13c, 0x21, 0 + .dw 0x2540, 0xc13c, 0x257f, 0xc13c, 0x21, 0 + .dw 0x25c0, 0xc13c, 0x25ff, 0xc13c, 0x21, 0 + .dw 0x2640, 0xc13c, 0x267f, 0xc13c, 0x21, 0 + .dw 0x26c0, 0xc13c, 0x26ff, 0xc13c, 0x21, 0 + .dw 0x2740, 0xc13c, 0x277f, 0xc13c, 0x21, 0 + .dw 0x27c0, 0xc13c, 0x27ff, 0xc13c, 0x21, 0 + .dw 0x2840, 0xc13c, 0x287f, 0xc13c, 0x21, 0 + .dw 0x28c0, 0xc13c, 0x28ff, 0xc13c, 0x21, 0 + .dw 0x2940, 0xc13c, 0x297f, 0xc13c, 0x21, 0 + .dw 0x29c0, 0xc13c, 0x29ff, 0xc13c, 0x21, 0 + .dw 0x2a40, 0xc13c, 0x2a7f, 0xc13c, 0x21, 0 + .dw 0x2ac0, 0xc13c, 0x2aff, 0xc13c, 0x21, 0 + .dw 0x2b40, 0xc13c, 0x2b7f, 0xc13c, 0x21, 0 + .dw 0x2bc0, 0xc13c, 0x2bff, 0xc13c, 0x21, 0 + .dw 0x2c40, 0xc13c, 0x2c7f, 0xc13c, 0x21, 0 + .dw 0x2cc0, 0xc13c, 0x2cff, 0xc13c, 0x21, 0 + .dw 0x2d40, 0xc13c, 0x2d7f, 0xc13c, 0x21, 0 + .dw 0x2dc0, 0xc13c, 0x2dff, 0xc13c, 0x21, 0 + .dw 0x2e40, 0xc13c, 0x2e7f, 0xc13c, 0x21, 0 + .dw 0x2ec0, 0xc13c, 0x2eff, 0xc13c, 0x21, 0 + .dw 0x2f40, 0xc13c, 0x2f7f, 0xc13c, 0x21, 0 + .dw 0x2fc0, 0xc13c, 0x2fff, 0xc13c, 0x21, 0 + .dw 0x3040, 0xc13c, 0x307f, 0xc13c, 0x21, 0 + .dw 0x30c0, 0xc13c, 0x30ff, 0xc13c, 0x21, 0 + .dw 0x3140, 0xc13c, 0x317f, 0xc13c, 0x21, 0 + .dw 0x31c0, 0xc13c, 0x31ff, 0xc13c, 0x21, 0 + .dw 0x3240, 0xc13c, 0x327f, 0xc13c, 0x21, 0 + .dw 0x32c0, 0xc13c, 0x32ff, 0xc13c, 0x21, 0 + .dw 0x3340, 0xc13c, 0x337f, 0xc13c, 0x21, 0 + .dw 0x33c0, 0xc13c, 0x33ff, 0xc13c, 0x21, 0 + .dw 0x3440, 0xc13c, 0x347f, 0xc13c, 0x21, 0 + .dw 0x34c0, 0xc13c, 0x34ff, 0xc13c, 0x21, 0 + .dw 0x3540, 0xc13c, 0x357f, 0xc13c, 0x21, 0 + .dw 0x35c0, 0xc13c, 0x35ff, 0xc13c, 0x21, 0 + .dw 0x3640, 0xc13c, 0x367f, 0xc13c, 0x21, 0 + .dw 0x36c0, 0xc13c, 0x36ff, 0xc13c, 0x21, 0 + .dw 0x3740, 0xc13c, 0x377f, 0xc13c, 0x21, 0 + .dw 0x37c0, 0xc13c, 0x37ff, 0xc13c, 0x21, 0 + .dw 0x3840, 0xc13c, 0x387f, 0xc13c, 0x21, 0 + .dw 0x38c0, 0xc13c, 0x38ff, 0xc13c, 0x21, 0 + .dw 0x3940, 0xc13c, 0x397f, 0xc13c, 0x21, 0 + .dw 0x39c0, 0xc13c, 0x3fff, 0xc13c, 0x21, 0 + .dw 0x4040, 0xc13c, 0x407f, 0xc13c, 0x21, 0 + .dw 0x40c0, 0xc13c, 0x40ff, 0xc13c, 0x21, 0 + .dw 0x4140, 0xc13c, 0x417f, 0xc13c, 0x21, 0 + .dw 0x41c0, 0xc13c, 0x41ff, 0xc13c, 0x21, 0 + .dw 0x4240, 0xc13c, 0x427f, 0xc13c, 0x21, 0 + .dw 0x42c0, 0xc13c, 0x42ff, 0xc13c, 0x21, 0 + .dw 0x4340, 0xc13c, 0x437f, 0xc13c, 0x21, 0 + .dw 0x43c0, 0xc13c, 0x43ff, 0xc13c, 0x21, 0 + .dw 0x4440, 0xc13c, 0x447f, 0xc13c, 0x21, 0 + .dw 0x44c0, 0xc13c, 0x44ff, 0xc13c, 0x21, 0 + .dw 0x4540, 0xc13c, 0x457f, 0xc13c, 0x21, 0 + .dw 0x45c0, 0xc13c, 0x45ff, 0xc13c, 0x21, 0 + .dw 0x4640, 0xc13c, 0x467f, 0xc13c, 0x21, 0 + .dw 0x46c0, 0xc13c, 0x46ff, 0xc13c, 0x21, 0 + .dw 0x4740, 0xc13c, 0x477f, 0xc13c, 0x21, 0 + .dw 0x47c0, 0xc13c, 0x47ff, 0xc13c, 0x21, 0 + .dw 0x4840, 0xc13c, 0x487f, 0xc13c, 0x21, 0 + .dw 0x48c0, 0xc13c, 0x48ff, 0xc13c, 0x21, 0 + .dw 0x4940, 0xc13c, 0x497f, 0xc13c, 0x21, 0 + .dw 0x49c0, 0xc13c, 0x49ff, 0xc13c, 0x21, 0 + .dw 0x4a40, 0xc13c, 0x4a7f, 0xc13c, 0x21, 0 + .dw 0x4ac0, 0xc13c, 0x4aff, 0xc13c, 0x21, 0 + .dw 0x4b40, 0xc13c, 0x4b7f, 0xc13c, 0x21, 0 + .dw 0x4bc0, 0xc13c, 0x4bff, 0xc13c, 0x21, 0 + .dw 0x4c40, 0xc13c, 0x4c7f, 0xc13c, 0x21, 0 + .dw 0x4cc0, 0xc13c, 0x4cff, 0xc13c, 0x21, 0 + .dw 0x4d40, 0xc13c, 0x4d7f, 0xc13c, 0x21, 0 + .dw 0x4dc0, 0xc13c, 0x4dff, 0xc13c, 0x21, 0 + .dw 0x4e40, 0xc13c, 0x4e7f, 0xc13c, 0x21, 0 + .dw 0x4ec0, 0xc13c, 0x4eff, 0xc13c, 0x21, 0 + .dw 0x4f40, 0xc13c, 0x4f7f, 0xc13c, 0x21, 0 + .dw 0x4fc0, 0xc13c, 0x4fff, 0xc13c, 0x21, 0 + .dw 0x5040, 0xc13c, 0x507f, 0xc13c, 0x21, 0 + .dw 0x50c0, 0xc13c, 0x50ff, 0xc13c, 0x21, 0 + .dw 0x5140, 0xc13c, 0x517f, 0xc13c, 0x21, 0 + .dw 0x51c0, 0xc13c, 0x51ff, 0xc13c, 0x21, 0 + .dw 0x5240, 0xc13c, 0x527f, 0xc13c, 0x21, 0 + .dw 0x52c0, 0xc13c, 0x52ff, 0xc13c, 0x21, 0 + .dw 0x5340, 0xc13c, 0x537f, 0xc13c, 0x21, 0 + .dw 0x53c0, 0xc13c, 0x53ff, 0xc13c, 0x21, 0 + .dw 0x5440, 0xc13c, 0x547f, 0xc13c, 0x21, 0 + .dw 0x54c0, 0xc13c, 0x54ff, 0xc13c, 0x21, 0 + .dw 0x5540, 0xc13c, 0x557f, 0xc13c, 0x21, 0 + .dw 0x55c0, 0xc13c, 0x55ff, 0xc13c, 0x21, 0 + .dw 0x5640, 0xc13c, 0x567f, 0xc13c, 0x21, 0 + .dw 0x56c0, 0xc13c, 0x56ff, 0xc13c, 0x21, 0 + .dw 0x5740, 0xc13c, 0x577f, 0xc13c, 0x21, 0 + .dw 0x57c0, 0xc13c, 0x57ff, 0xc13c, 0x21, 0 + .dw 0x5840, 0xc13c, 0x587f, 0xc13c, 0x21, 0 + .dw 0x58c0, 0xc13c, 0x58ff, 0xc13c, 0x21, 0 + .dw 0x5940, 0xc13c, 0x597f, 0xc13c, 0x21, 0 + .dw 0x59c0, 0xc13c, 0x5fff, 0xc13c, 0x21, 0 + .dw 0x6040, 0xc13c, 0x607f, 0xc13c, 0x21, 0 + .dw 0x60c0, 0xc13c, 0x60ff, 0xc13c, 0x21, 0 + .dw 0x6140, 0xc13c, 0x617f, 0xc13c, 0x21, 0 + .dw 0x61c0, 0xc13c, 0x61ff, 0xc13c, 0x21, 0 + .dw 0x6240, 0xc13c, 0x627f, 0xc13c, 0x21, 0 + .dw 0x62c0, 0xc13c, 0x62ff, 0xc13c, 0x21, 0 + .dw 0x6340, 0xc13c, 0x637f, 0xc13c, 0x21, 0 + .dw 0x63c0, 0xc13c, 0x63ff, 0xc13c, 0x21, 0 + .dw 0x6440, 0xc13c, 0x647f, 0xc13c, 0x21, 0 + .dw 0x64c0, 0xc13c, 0x64ff, 0xc13c, 0x21, 0 + .dw 0x6540, 0xc13c, 0x657f, 0xc13c, 0x21, 0 + .dw 0x65c0, 0xc13c, 0x65ff, 0xc13c, 0x21, 0 + .dw 0x6640, 0xc13c, 0x667f, 0xc13c, 0x21, 0 + .dw 0x66c0, 0xc13c, 0x66ff, 0xc13c, 0x21, 0 + .dw 0x6740, 0xc13c, 0x677f, 0xc13c, 0x21, 0 + .dw 0x67c0, 0xc13c, 0x67ff, 0xc13c, 0x21, 0 + .dw 0x6840, 0xc13c, 0x687f, 0xc13c, 0x21, 0 + .dw 0x68c0, 0xc13c, 0x68ff, 0xc13c, 0x21, 0 + .dw 0x6940, 0xc13c, 0x697f, 0xc13c, 0x21, 0 + .dw 0x69c0, 0xc13c, 0x69ff, 0xc13c, 0x21, 0 + .dw 0x6a40, 0xc13c, 0x6a7f, 0xc13c, 0x21, 0 + .dw 0x6ac0, 0xc13c, 0x6aff, 0xc13c, 0x21, 0 + .dw 0x6b40, 0xc13c, 0x6b7f, 0xc13c, 0x21, 0 + .dw 0x6bc0, 0xc13c, 0x6bff, 0xc13c, 0x21, 0 + .dw 0x6c40, 0xc13c, 0x6c7f, 0xc13c, 0x21, 0 + .dw 0x6cc0, 0xc13c, 0x6cff, 0xc13c, 0x21, 0 + .dw 0x6d40, 0xc13c, 0x6d7f, 0xc13c, 0x21, 0 + .dw 0x6dc0, 0xc13c, 0x6dff, 0xc13c, 0x21, 0 + .dw 0x6e40, 0xc13c, 0x6e7f, 0xc13c, 0x21, 0 + .dw 0x6ec0, 0xc13c, 0x6eff, 0xc13c, 0x21, 0 + .dw 0x6f40, 0xc13c, 0x6f7f, 0xc13c, 0x21, 0 + .dw 0x6fc0, 0xc13c, 0x6fff, 0xc13c, 0x21, 0 + .dw 0x7040, 0xc13c, 0x707f, 0xc13c, 0x21, 0 + .dw 0x70c0, 0xc13c, 0x70ff, 0xc13c, 0x21, 0 + .dw 0x7140, 0xc13c, 0x717f, 0xc13c, 0x21, 0 + .dw 0x71c0, 0xc13c, 0x71ff, 0xc13c, 0x21, 0 + .dw 0x7240, 0xc13c, 0x727f, 0xc13c, 0x21, 0 + .dw 0x72c0, 0xc13c, 0x72ff, 0xc13c, 0x21, 0 + .dw 0x7340, 0xc13c, 0x737f, 0xc13c, 0x21, 0 + .dw 0x73c0, 0xc13c, 0x73ff, 0xc13c, 0x21, 0 + .dw 0x7440, 0xc13c, 0x747f, 0xc13c, 0x21, 0 + .dw 0x74c0, 0xc13c, 0x74ff, 0xc13c, 0x21, 0 + .dw 0x7540, 0xc13c, 0x757f, 0xc13c, 0x21, 0 + .dw 0x75c0, 0xc13c, 0x75ff, 0xc13c, 0x21, 0 + .dw 0x7640, 0xc13c, 0x767f, 0xc13c, 0x21, 0 + .dw 0x76c0, 0xc13c, 0x76ff, 0xc13c, 0x21, 0 + .dw 0x7740, 0xc13c, 0x777f, 0xc13c, 0x21, 0 + .dw 0x77c0, 0xc13c, 0x77ff, 0xc13c, 0x21, 0 + .dw 0x7840, 0xc13c, 0x787f, 0xc13c, 0x21, 0 + .dw 0x78c0, 0xc13c, 0x78ff, 0xc13c, 0x21, 0 + .dw 0x7940, 0xc13c, 0x797f, 0xc13c, 0x21, 0 + .dw 0x79c0, 0xc13c, 0x7fff, 0xc13c, 0x21, 0 + .dw 0x8040, 0xc13c, 0x807f, 0xc13c, 0x21, 0 + .dw 0x80c0, 0xc13c, 0x80ff, 0xc13c, 0x21, 0 + .dw 0x8140, 0xc13c, 0x817f, 0xc13c, 0x21, 0 + .dw 0x81c0, 0xc13c, 0x81ff, 0xc13c, 0x21, 0 + .dw 0x8240, 0xc13c, 0x827f, 0xc13c, 0x21, 0 + .dw 0x82c0, 0xc13c, 0x82ff, 0xc13c, 0x21, 0 + .dw 0x8340, 0xc13c, 0x837f, 0xc13c, 0x21, 0 + .dw 0x83c0, 0xc13c, 0x83ff, 0xc13c, 0x21, 0 + .dw 0x8440, 0xc13c, 0x847f, 0xc13c, 0x21, 0 + .dw 0x84c0, 0xc13c, 0x84ff, 0xc13c, 0x21, 0 + .dw 0x8540, 0xc13c, 0x857f, 0xc13c, 0x21, 0 + .dw 0x85c0, 0xc13c, 0x85ff, 0xc13c, 0x21, 0 + .dw 0x8640, 0xc13c, 0x867f, 0xc13c, 0x21, 0 + .dw 0x86c0, 0xc13c, 0x86ff, 0xc13c, 0x21, 0 + .dw 0x8740, 0xc13c, 0x877f, 0xc13c, 0x21, 0 + .dw 0x87c0, 0xc13c, 0x87ff, 0xc13c, 0x21, 0 + .dw 0x8840, 0xc13c, 0x887f, 0xc13c, 0x21, 0 + .dw 0x88c0, 0xc13c, 0x88ff, 0xc13c, 0x21, 0 + .dw 0x8940, 0xc13c, 0x897f, 0xc13c, 0x21, 0 + .dw 0x89c0, 0xc13c, 0x89ff, 0xc13c, 0x21, 0 + .dw 0x8a40, 0xc13c, 0x8a7f, 0xc13c, 0x21, 0 + .dw 0x8ac0, 0xc13c, 0x8aff, 0xc13c, 0x21, 0 + .dw 0x8b40, 0xc13c, 0x8b7f, 0xc13c, 0x21, 0 + .dw 0x8bc0, 0xc13c, 0x8bff, 0xc13c, 0x21, 0 + .dw 0x8c40, 0xc13c, 0x8c7f, 0xc13c, 0x21, 0 + .dw 0x8cc0, 0xc13c, 0x8cff, 0xc13c, 0x21, 0 + .dw 0x8d40, 0xc13c, 0x8d7f, 0xc13c, 0x21, 0 + .dw 0x8dc0, 0xc13c, 0x8dff, 0xc13c, 0x21, 0 + .dw 0x8e40, 0xc13c, 0x8e7f, 0xc13c, 0x21, 0 + .dw 0x8ec0, 0xc13c, 0x8eff, 0xc13c, 0x21, 0 + .dw 0x8f40, 0xc13c, 0x8f7f, 0xc13c, 0x21, 0 + .dw 0x8fc0, 0xc13c, 0x8fff, 0xc13c, 0x21, 0 + .dw 0x9040, 0xc13c, 0x907f, 0xc13c, 0x21, 0 + .dw 0x90c0, 0xc13c, 0x90ff, 0xc13c, 0x21, 0 + .dw 0x9140, 0xc13c, 0x917f, 0xc13c, 0x21, 0 + .dw 0x91c0, 0xc13c, 0x91ff, 0xc13c, 0x21, 0 + .dw 0x9240, 0xc13c, 0x927f, 0xc13c, 0x21, 0 + .dw 0x92c0, 0xc13c, 0x92ff, 0xc13c, 0x21, 0 + .dw 0x9340, 0xc13c, 0x937f, 0xc13c, 0x21, 0 + .dw 0x93c0, 0xc13c, 0x93ff, 0xc13c, 0x21, 0 + .dw 0x9440, 0xc13c, 0x947f, 0xc13c, 0x21, 0 + .dw 0x94c0, 0xc13c, 0x94ff, 0xc13c, 0x21, 0 + .dw 0x9540, 0xc13c, 0x957f, 0xc13c, 0x21, 0 + .dw 0x95c0, 0xc13c, 0x95ff, 0xc13c, 0x21, 0 + .dw 0x9640, 0xc13c, 0x967f, 0xc13c, 0x21, 0 + .dw 0x96c0, 0xc13c, 0x96ff, 0xc13c, 0x21, 0 + .dw 0x9740, 0xc13c, 0x977f, 0xc13c, 0x21, 0 + .dw 0x97c0, 0xc13c, 0x97ff, 0xc13c, 0x21, 0 + .dw 0x9840, 0xc13c, 0x987f, 0xc13c, 0x21, 0 + .dw 0x98c0, 0xc13c, 0x98ff, 0xc13c, 0x21, 0 + .dw 0x9940, 0xc13c, 0x997f, 0xc13c, 0x21, 0 + .dw 0x99c0, 0xc13c, 0x9fff, 0xc13c, 0x21, 0 + .dw 0xa040, 0xc13c, 0xa07f, 0xc13c, 0x21, 0 + .dw 0xa0c0, 0xc13c, 0xa0ff, 0xc13c, 0x21, 0 + .dw 0xa140, 0xc13c, 0xa17f, 0xc13c, 0x21, 0 + .dw 0xa1c0, 0xc13c, 0xa1ff, 0xc13c, 0x21, 0 + .dw 0xa240, 0xc13c, 0xa27f, 0xc13c, 0x21, 0 + .dw 0xa2c0, 0xc13c, 0xa2ff, 0xc13c, 0x21, 0 + .dw 0xa340, 0xc13c, 0xa37f, 0xc13c, 0x21, 0 + .dw 0xa3c0, 0xc13c, 0xa3ff, 0xc13c, 0x21, 0 + .dw 0xa440, 0xc13c, 0xa47f, 0xc13c, 0x21, 0 + .dw 0xa4c0, 0xc13c, 0xa4ff, 0xc13c, 0x21, 0 + .dw 0xa540, 0xc13c, 0xa57f, 0xc13c, 0x21, 0 + .dw 0xa5c0, 0xc13c, 0xa5ff, 0xc13c, 0x21, 0 + .dw 0xa640, 0xc13c, 0xa67f, 0xc13c, 0x21, 0 + .dw 0xa6c0, 0xc13c, 0xa6ff, 0xc13c, 0x21, 0 + .dw 0xa740, 0xc13c, 0xa77f, 0xc13c, 0x21, 0 + .dw 0xa7c0, 0xc13c, 0xa7ff, 0xc13c, 0x21, 0 + .dw 0xa840, 0xc13c, 0xa87f, 0xc13c, 0x21, 0 + .dw 0xa8c0, 0xc13c, 0xa8ff, 0xc13c, 0x21, 0 + .dw 0xa940, 0xc13c, 0xa97f, 0xc13c, 0x21, 0 + .dw 0xa9c0, 0xc13c, 0xa9ff, 0xc13c, 0x21, 0 + .dw 0xaa40, 0xc13c, 0xaa7f, 0xc13c, 0x21, 0 + .dw 0xaac0, 0xc13c, 0xaaff, 0xc13c, 0x21, 0 + .dw 0xab40, 0xc13c, 0xab7f, 0xc13c, 0x21, 0 + .dw 0xabc0, 0xc13c, 0xabff, 0xc13c, 0x21, 0 + .dw 0xac40, 0xc13c, 0xac7f, 0xc13c, 0x21, 0 + .dw 0xacc0, 0xc13c, 0xacff, 0xc13c, 0x21, 0 + .dw 0xad40, 0xc13c, 0xad7f, 0xc13c, 0x21, 0 + .dw 0xadc0, 0xc13c, 0xadff, 0xc13c, 0x21, 0 + .dw 0xae40, 0xc13c, 0xae7f, 0xc13c, 0x21, 0 + .dw 0xaec0, 0xc13c, 0xaeff, 0xc13c, 0x21, 0 + .dw 0xaf40, 0xc13c, 0xaf7f, 0xc13c, 0x21, 0 + .dw 0xafc0, 0xc13c, 0xafff, 0xc13c, 0x21, 0 + .dw 0xb040, 0xc13c, 0xb07f, 0xc13c, 0x21, 0 + .dw 0xb0c0, 0xc13c, 0xb0ff, 0xc13c, 0x21, 0 + .dw 0xb140, 0xc13c, 0xb17f, 0xc13c, 0x21, 0 + .dw 0xb1c0, 0xc13c, 0xb1ff, 0xc13c, 0x21, 0 + .dw 0xb240, 0xc13c, 0xb27f, 0xc13c, 0x21, 0 + .dw 0xb2c0, 0xc13c, 0xb2ff, 0xc13c, 0x21, 0 + .dw 0xb340, 0xc13c, 0xb37f, 0xc13c, 0x21, 0 + .dw 0xb3c0, 0xc13c, 0xb3ff, 0xc13c, 0x21, 0 + .dw 0xb440, 0xc13c, 0xb47f, 0xc13c, 0x21, 0 + .dw 0xb4c0, 0xc13c, 0xb4ff, 0xc13c, 0x21, 0 + .dw 0xb540, 0xc13c, 0xb57f, 0xc13c, 0x21, 0 + .dw 0xb5c0, 0xc13c, 0xb5ff, 0xc13c, 0x21, 0 + .dw 0xb640, 0xc13c, 0xb67f, 0xc13c, 0x21, 0 + .dw 0xb6c0, 0xc13c, 0xb6ff, 0xc13c, 0x21, 0 + .dw 0xb740, 0xc13c, 0xb77f, 0xc13c, 0x21, 0 + .dw 0xb7c0, 0xc13c, 0xb7ff, 0xc13c, 0x21, 0 + .dw 0xb840, 0xc13c, 0xb87f, 0xc13c, 0x21, 0 + .dw 0xb8c0, 0xc13c, 0xb8ff, 0xc13c, 0x21, 0 + .dw 0xb940, 0xc13c, 0xb97f, 0xc13c, 0x21, 0 + .dw 0xb9c0, 0xc13c, 0xbfff, 0xc13c, 0x21, 0 + .dw 0xc040, 0xc13c, 0xc07f, 0xc13c, 0x21, 0 + .dw 0xc0c0, 0xc13c, 0xc0ff, 0xc13c, 0x21, 0 + .dw 0xc140, 0xc13c, 0xc17f, 0xc13c, 0x21, 0 + .dw 0xc1c0, 0xc13c, 0xc1ff, 0xc13c, 0x21, 0 + .dw 0xc240, 0xc13c, 0xc27f, 0xc13c, 0x21, 0 + .dw 0xc2c0, 0xc13c, 0xc2ff, 0xc13c, 0x21, 0 + .dw 0xc340, 0xc13c, 0xc37f, 0xc13c, 0x21, 0 + .dw 0xc3c0, 0xc13c, 0xc3ff, 0xc13c, 0x21, 0 + .dw 0xc440, 0xc13c, 0xc47f, 0xc13c, 0x21, 0 + .dw 0xc4c0, 0xc13c, 0xc4ff, 0xc13c, 0x21, 0 + .dw 0xc540, 0xc13c, 0xc57f, 0xc13c, 0x21, 0 + .dw 0xc5c0, 0xc13c, 0xc5ff, 0xc13c, 0x21, 0 + .dw 0xc640, 0xc13c, 0xc67f, 0xc13c, 0x21, 0 + .dw 0xc6c0, 0xc13c, 0xc6ff, 0xc13c, 0x21, 0 + .dw 0xc740, 0xc13c, 0xc77f, 0xc13c, 0x21, 0 + .dw 0xc7c0, 0xc13c, 0xc7ff, 0xc13c, 0x21, 0 + .dw 0xc840, 0xc13c, 0xc87f, 0xc13c, 0x21, 0 + .dw 0xc8c0, 0xc13c, 0xc8ff, 0xc13c, 0x21, 0 + .dw 0xc940, 0xc13c, 0xc97f, 0xc13c, 0x21, 0 + .dw 0xc9c0, 0xc13c, 0xc9ff, 0xc13c, 0x21, 0 + .dw 0xca40, 0xc13c, 0xca7f, 0xc13c, 0x21, 0 + .dw 0xcac0, 0xc13c, 0xcaff, 0xc13c, 0x21, 0 + .dw 0xcb40, 0xc13c, 0xcb7f, 0xc13c, 0x21, 0 + .dw 0xcbc0, 0xc13c, 0xcbff, 0xc13c, 0x21, 0 + .dw 0xcc40, 0xc13c, 0xcc7f, 0xc13c, 0x21, 0 + .dw 0xccc0, 0xc13c, 0xccff, 0xc13c, 0x21, 0 + .dw 0xcd40, 0xc13c, 0xcd7f, 0xc13c, 0x21, 0 + .dw 0xcdc0, 0xc13c, 0xcdff, 0xc13c, 0x21, 0 + .dw 0xce40, 0xc13c, 0xce7f, 0xc13c, 0x21, 0 + .dw 0xcec0, 0xc13c, 0xceff, 0xc13c, 0x21, 0 + .dw 0xcf40, 0xc13c, 0xcf7f, 0xc13c, 0x21, 0 + .dw 0xcfc0, 0xc13c, 0xcfff, 0xc13c, 0x21, 0 + .dw 0xd040, 0xc13c, 0xd07f, 0xc13c, 0x21, 0 + .dw 0xd0c0, 0xc13c, 0xd0ff, 0xc13c, 0x21, 0 + .dw 0xd140, 0xc13c, 0xd17f, 0xc13c, 0x21, 0 + .dw 0xd1c0, 0xc13c, 0xd1ff, 0xc13c, 0x21, 0 + .dw 0xd240, 0xc13c, 0xd27f, 0xc13c, 0x21, 0 + .dw 0xd2c0, 0xc13c, 0xd2ff, 0xc13c, 0x21, 0 + .dw 0xd340, 0xc13c, 0xd37f, 0xc13c, 0x21, 0 + .dw 0xd3c0, 0xc13c, 0xd3ff, 0xc13c, 0x21, 0 + .dw 0xd440, 0xc13c, 0xd47f, 0xc13c, 0x21, 0 + .dw 0xd4c0, 0xc13c, 0xd4ff, 0xc13c, 0x21, 0 + .dw 0xd540, 0xc13c, 0xd57f, 0xc13c, 0x21, 0 + .dw 0xd5c0, 0xc13c, 0xd5ff, 0xc13c, 0x21, 0 + .dw 0xd640, 0xc13c, 0xd67f, 0xc13c, 0x21, 0 + .dw 0xd6c0, 0xc13c, 0xd6ff, 0xc13c, 0x21, 0 + .dw 0xd740, 0xc13c, 0xd77f, 0xc13c, 0x21, 0 + .dw 0xd7c0, 0xc13c, 0xd7ff, 0xc13c, 0x21, 0 + .dw 0xd840, 0xc13c, 0xd87f, 0xc13c, 0x21, 0 + .dw 0xd8c0, 0xc13c, 0xd8ff, 0xc13c, 0x21, 0 + .dw 0xd940, 0xc13c, 0xd97f, 0xc13c, 0x21, 0 + .dw 0xd9c0, 0xc13c, 0xdfff, 0xc13c, 0x21, 0 + .dw 0xe040, 0xc13c, 0xe07f, 0xc13c, 0x21, 0 + .dw 0xe0c0, 0xc13c, 0xe0ff, 0xc13c, 0x21, 0 + .dw 0xe140, 0xc13c, 0xe17f, 0xc13c, 0x21, 0 + .dw 0xe1c0, 0xc13c, 0xe1ff, 0xc13c, 0x21, 0 + .dw 0xe240, 0xc13c, 0xe27f, 0xc13c, 0x21, 0 + .dw 0xe2c0, 0xc13c, 0xe2ff, 0xc13c, 0x21, 0 + .dw 0xe340, 0xc13c, 0xe37f, 0xc13c, 0x21, 0 + .dw 0xe3c0, 0xc13c, 0xe3ff, 0xc13c, 0x21, 0 + .dw 0xe440, 0xc13c, 0xe47f, 0xc13c, 0x21, 0 + .dw 0xe4c0, 0xc13c, 0xe4ff, 0xc13c, 0x21, 0 + .dw 0xe540, 0xc13c, 0xe57f, 0xc13c, 0x21, 0 + .dw 0xe5c0, 0xc13c, 0xe5ff, 0xc13c, 0x21, 0 + .dw 0xe640, 0xc13c, 0xe67f, 0xc13c, 0x21, 0 + .dw 0xe6c0, 0xc13c, 0xe6ff, 0xc13c, 0x21, 0 + .dw 0xe740, 0xc13c, 0xe77f, 0xc13c, 0x21, 0 + .dw 0xe7c0, 0xc13c, 0xe7ff, 0xc13c, 0x21, 0 + .dw 0xe840, 0xc13c, 0xe87f, 0xc13c, 0x21, 0 + .dw 0xe8c0, 0xc13c, 0xe8ff, 0xc13c, 0x21, 0 + .dw 0xe940, 0xc13c, 0xe97f, 0xc13c, 0x21, 0 + .dw 0xe9c0, 0xc13c, 0xe9ff, 0xc13c, 0x21, 0 + .dw 0xea40, 0xc13c, 0xea7f, 0xc13c, 0x21, 0 + .dw 0xeac0, 0xc13c, 0xeaff, 0xc13c, 0x21, 0 + .dw 0xeb40, 0xc13c, 0xeb7f, 0xc13c, 0x21, 0 + .dw 0xebc0, 0xc13c, 0xebff, 0xc13c, 0x21, 0 + .dw 0xec40, 0xc13c, 0xec7f, 0xc13c, 0x21, 0 + .dw 0xecc0, 0xc13c, 0xecff, 0xc13c, 0x21, 0 + .dw 0xed40, 0xc13c, 0xed7f, 0xc13c, 0x21, 0 + .dw 0xedc0, 0xc13c, 0xedff, 0xc13c, 0x21, 0 + .dw 0xee40, 0xc13c, 0xee7f, 0xc13c, 0x21, 0 + .dw 0xeec0, 0xc13c, 0xeeff, 0xc13c, 0x21, 0 + .dw 0xef40, 0xc13c, 0xef7f, 0xc13c, 0x21, 0 + .dw 0xefc0, 0xc13c, 0xefff, 0xc13c, 0x21, 0 + .dw 0xf040, 0xc13c, 0xf07f, 0xc13c, 0x21, 0 + .dw 0xf0c0, 0xc13c, 0xf0ff, 0xc13c, 0x21, 0 + .dw 0xf140, 0xc13c, 0xf17f, 0xc13c, 0x21, 0 + .dw 0xf1c0, 0xc13c, 0xf1ff, 0xc13c, 0x21, 0 + .dw 0xf240, 0xc13c, 0xf27f, 0xc13c, 0x21, 0 + .dw 0xf2c0, 0xc13c, 0xf2ff, 0xc13c, 0x21, 0 + .dw 0xf340, 0xc13c, 0xf37f, 0xc13c, 0x21, 0 + .dw 0xf3c0, 0xc13c, 0xf3ff, 0xc13c, 0x21, 0 + .dw 0xf440, 0xc13c, 0xf47f, 0xc13c, 0x21, 0 + .dw 0xf4c0, 0xc13c, 0xf4ff, 0xc13c, 0x21, 0 + .dw 0xf540, 0xc13c, 0xf57f, 0xc13c, 0x21, 0 + .dw 0xf5c0, 0xc13c, 0xf5ff, 0xc13c, 0x21, 0 + .dw 0xf640, 0xc13c, 0xf67f, 0xc13c, 0x21, 0 + .dw 0xf6c0, 0xc13c, 0xf6ff, 0xc13c, 0x21, 0 + .dw 0xf740, 0xc13c, 0xf77f, 0xc13c, 0x21, 0 + .dw 0xf7c0, 0xc13c, 0xf7ff, 0xc13c, 0x21, 0 + .dw 0xf840, 0xc13c, 0xf87f, 0xc13c, 0x21, 0 + .dw 0xf8c0, 0xc13c, 0xf8ff, 0xc13c, 0x21, 0 + .dw 0xf940, 0xc13c, 0xf97f, 0xc13c, 0x21, 0 + .dw 0xf9c0, 0xc13c, 0xffff, 0xc13c, 0x21, 0 + .dw 0x0040, 0xc13d, 0x007f, 0xc13d, 0x21, 0 + .dw 0x00c0, 0xc13d, 0x00ff, 0xc13d, 0x21, 0 + .dw 0x0140, 0xc13d, 0x017f, 0xc13d, 0x21, 0 + .dw 0x01c0, 0xc13d, 0x01ff, 0xc13d, 0x21, 0 + .dw 0x0240, 0xc13d, 0x027f, 0xc13d, 0x21, 0 + .dw 0x02c0, 0xc13d, 0x02ff, 0xc13d, 0x21, 0 + .dw 0x0340, 0xc13d, 0x037f, 0xc13d, 0x21, 0 + .dw 0x03c0, 0xc13d, 0x03ff, 0xc13d, 0x21, 0 + .dw 0x0440, 0xc13d, 0x047f, 0xc13d, 0x21, 0 + .dw 0x04c0, 0xc13d, 0x04ff, 0xc13d, 0x21, 0 + .dw 0x0540, 0xc13d, 0x057f, 0xc13d, 0x21, 0 + .dw 0x05c0, 0xc13d, 0x05ff, 0xc13d, 0x21, 0 + .dw 0x0640, 0xc13d, 0x067f, 0xc13d, 0x21, 0 + .dw 0x06c0, 0xc13d, 0x06ff, 0xc13d, 0x21, 0 + .dw 0x0740, 0xc13d, 0x077f, 0xc13d, 0x21, 0 + .dw 0x07c0, 0xc13d, 0x07ff, 0xc13d, 0x21, 0 + .dw 0x0840, 0xc13d, 0x087f, 0xc13d, 0x21, 0 + .dw 0x08c0, 0xc13d, 0x08ff, 0xc13d, 0x21, 0 + .dw 0x0940, 0xc13d, 0x097f, 0xc13d, 0x21, 0 + .dw 0x09c0, 0xc13d, 0x09ff, 0xc13d, 0x21, 0 + .dw 0x0a40, 0xc13d, 0x0a7f, 0xc13d, 0x21, 0 + .dw 0x0ac0, 0xc13d, 0x0aff, 0xc13d, 0x21, 0 + .dw 0x0b40, 0xc13d, 0x0b7f, 0xc13d, 0x21, 0 + .dw 0x0bc0, 0xc13d, 0x0bff, 0xc13d, 0x21, 0 + .dw 0x0c40, 0xc13d, 0x0c7f, 0xc13d, 0x21, 0 + .dw 0x0cc0, 0xc13d, 0x0cff, 0xc13d, 0x21, 0 + .dw 0x0d40, 0xc13d, 0x0d7f, 0xc13d, 0x21, 0 + .dw 0x0dc0, 0xc13d, 0x0dff, 0xc13d, 0x21, 0 + .dw 0x0e40, 0xc13d, 0x0e7f, 0xc13d, 0x21, 0 + .dw 0x0ec0, 0xc13d, 0x0eff, 0xc13d, 0x21, 0 + .dw 0x0f40, 0xc13d, 0x0f7f, 0xc13d, 0x21, 0 + .dw 0x0fc0, 0xc13d, 0x0fff, 0xc13d, 0x21, 0 + .dw 0x1040, 0xc13d, 0x107f, 0xc13d, 0x21, 0 + .dw 0x10c0, 0xc13d, 0x10ff, 0xc13d, 0x21, 0 + .dw 0x1140, 0xc13d, 0x117f, 0xc13d, 0x21, 0 + .dw 0x11c0, 0xc13d, 0x11ff, 0xc13d, 0x21, 0 + .dw 0x1240, 0xc13d, 0x127f, 0xc13d, 0x21, 0 + .dw 0x12c0, 0xc13d, 0x12ff, 0xc13d, 0x21, 0 + .dw 0x1340, 0xc13d, 0x137f, 0xc13d, 0x21, 0 + .dw 0x13c0, 0xc13d, 0x13ff, 0xc13d, 0x21, 0 + .dw 0x1440, 0xc13d, 0x147f, 0xc13d, 0x21, 0 + .dw 0x14c0, 0xc13d, 0x14ff, 0xc13d, 0x21, 0 + .dw 0x1540, 0xc13d, 0x157f, 0xc13d, 0x21, 0 + .dw 0x15c0, 0xc13d, 0x15ff, 0xc13d, 0x21, 0 + .dw 0x1640, 0xc13d, 0x167f, 0xc13d, 0x21, 0 + .dw 0x16c0, 0xc13d, 0x16ff, 0xc13d, 0x21, 0 + .dw 0x1740, 0xc13d, 0x177f, 0xc13d, 0x21, 0 + .dw 0x17c0, 0xc13d, 0x17ff, 0xc13d, 0x21, 0 + .dw 0x1840, 0xc13d, 0x187f, 0xc13d, 0x21, 0 + .dw 0x18c0, 0xc13d, 0x18ff, 0xc13d, 0x21, 0 + .dw 0x1940, 0xc13d, 0x197f, 0xc13d, 0x21, 0 + .dw 0x19c0, 0xc13d, 0x1fff, 0xc13d, 0x21, 0 + .dw 0x2040, 0xc13d, 0x207f, 0xc13d, 0x21, 0 + .dw 0x20c0, 0xc13d, 0x20ff, 0xc13d, 0x21, 0 + .dw 0x2140, 0xc13d, 0x217f, 0xc13d, 0x21, 0 + .dw 0x21c0, 0xc13d, 0x21ff, 0xc13d, 0x21, 0 + .dw 0x2240, 0xc13d, 0x227f, 0xc13d, 0x21, 0 + .dw 0x22c0, 0xc13d, 0x22ff, 0xc13d, 0x21, 0 + .dw 0x2340, 0xc13d, 0x237f, 0xc13d, 0x21, 0 + .dw 0x23c0, 0xc13d, 0x23ff, 0xc13d, 0x21, 0 + .dw 0x2440, 0xc13d, 0x247f, 0xc13d, 0x21, 0 + .dw 0x24c0, 0xc13d, 0x24ff, 0xc13d, 0x21, 0 + .dw 0x2540, 0xc13d, 0x257f, 0xc13d, 0x21, 0 + .dw 0x25c0, 0xc13d, 0x25ff, 0xc13d, 0x21, 0 + .dw 0x2640, 0xc13d, 0x267f, 0xc13d, 0x21, 0 + .dw 0x26c0, 0xc13d, 0x26ff, 0xc13d, 0x21, 0 + .dw 0x2740, 0xc13d, 0x277f, 0xc13d, 0x21, 0 + .dw 0x27c0, 0xc13d, 0x27ff, 0xc13d, 0x21, 0 + .dw 0x2840, 0xc13d, 0x287f, 0xc13d, 0x21, 0 + .dw 0x28c0, 0xc13d, 0x28ff, 0xc13d, 0x21, 0 + .dw 0x2940, 0xc13d, 0x297f, 0xc13d, 0x21, 0 + .dw 0x29c0, 0xc13d, 0x29ff, 0xc13d, 0x21, 0 + .dw 0x2a40, 0xc13d, 0x2a7f, 0xc13d, 0x21, 0 + .dw 0x2ac0, 0xc13d, 0x2aff, 0xc13d, 0x21, 0 + .dw 0x2b40, 0xc13d, 0x2b7f, 0xc13d, 0x21, 0 + .dw 0x2bc0, 0xc13d, 0x2bff, 0xc13d, 0x21, 0 + .dw 0x2c40, 0xc13d, 0x2c7f, 0xc13d, 0x21, 0 + .dw 0x2cc0, 0xc13d, 0x2cff, 0xc13d, 0x21, 0 + .dw 0x2d40, 0xc13d, 0x2d7f, 0xc13d, 0x21, 0 + .dw 0x2dc0, 0xc13d, 0x2dff, 0xc13d, 0x21, 0 + .dw 0x2e40, 0xc13d, 0x2e7f, 0xc13d, 0x21, 0 + .dw 0x2ec0, 0xc13d, 0x2eff, 0xc13d, 0x21, 0 + .dw 0x2f40, 0xc13d, 0x2f7f, 0xc13d, 0x21, 0 + .dw 0x2fc0, 0xc13d, 0x2fff, 0xc13d, 0x21, 0 + .dw 0x3040, 0xc13d, 0x307f, 0xc13d, 0x21, 0 + .dw 0x30c0, 0xc13d, 0x30ff, 0xc13d, 0x21, 0 + .dw 0x3140, 0xc13d, 0x317f, 0xc13d, 0x21, 0 + .dw 0x31c0, 0xc13d, 0x31ff, 0xc13d, 0x21, 0 + .dw 0x3240, 0xc13d, 0x327f, 0xc13d, 0x21, 0 + .dw 0x32c0, 0xc13d, 0x32ff, 0xc13d, 0x21, 0 + .dw 0x3340, 0xc13d, 0x337f, 0xc13d, 0x21, 0 + .dw 0x33c0, 0xc13d, 0x33ff, 0xc13d, 0x21, 0 + .dw 0x3440, 0xc13d, 0x347f, 0xc13d, 0x21, 0 + .dw 0x34c0, 0xc13d, 0x34ff, 0xc13d, 0x21, 0 + .dw 0x3540, 0xc13d, 0x357f, 0xc13d, 0x21, 0 + .dw 0x35c0, 0xc13d, 0x35ff, 0xc13d, 0x21, 0 + .dw 0x3640, 0xc13d, 0x367f, 0xc13d, 0x21, 0 + .dw 0x36c0, 0xc13d, 0x36ff, 0xc13d, 0x21, 0 + .dw 0x3740, 0xc13d, 0x377f, 0xc13d, 0x21, 0 + .dw 0x37c0, 0xc13d, 0x37ff, 0xc13d, 0x21, 0 + .dw 0x3840, 0xc13d, 0x387f, 0xc13d, 0x21, 0 + .dw 0x38c0, 0xc13d, 0x38ff, 0xc13d, 0x21, 0 + .dw 0x3940, 0xc13d, 0x397f, 0xc13d, 0x21, 0 + .dw 0x39c0, 0xc13d, 0x3fff, 0xc13d, 0x21, 0 + .dw 0x4040, 0xc13d, 0x407f, 0xc13d, 0x21, 0 + .dw 0x40c0, 0xc13d, 0x40ff, 0xc13d, 0x21, 0 + .dw 0x4140, 0xc13d, 0x417f, 0xc13d, 0x21, 0 + .dw 0x41c0, 0xc13d, 0x41ff, 0xc13d, 0x21, 0 + .dw 0x4240, 0xc13d, 0x427f, 0xc13d, 0x21, 0 + .dw 0x42c0, 0xc13d, 0x42ff, 0xc13d, 0x21, 0 + .dw 0x4340, 0xc13d, 0x437f, 0xc13d, 0x21, 0 + .dw 0x43c0, 0xc13d, 0x43ff, 0xc13d, 0x21, 0 + .dw 0x4440, 0xc13d, 0x447f, 0xc13d, 0x21, 0 + .dw 0x44c0, 0xc13d, 0x44ff, 0xc13d, 0x21, 0 + .dw 0x4540, 0xc13d, 0x457f, 0xc13d, 0x21, 0 + .dw 0x45c0, 0xc13d, 0x45ff, 0xc13d, 0x21, 0 + .dw 0x4640, 0xc13d, 0x467f, 0xc13d, 0x21, 0 + .dw 0x46c0, 0xc13d, 0x46ff, 0xc13d, 0x21, 0 + .dw 0x4740, 0xc13d, 0x477f, 0xc13d, 0x21, 0 + .dw 0x47c0, 0xc13d, 0x47ff, 0xc13d, 0x21, 0 + .dw 0x4840, 0xc13d, 0x487f, 0xc13d, 0x21, 0 + .dw 0x48c0, 0xc13d, 0x48ff, 0xc13d, 0x21, 0 + .dw 0x4940, 0xc13d, 0x497f, 0xc13d, 0x21, 0 + .dw 0x49c0, 0xc13d, 0x49ff, 0xc13d, 0x21, 0 + .dw 0x4a40, 0xc13d, 0x4a7f, 0xc13d, 0x21, 0 + .dw 0x4ac0, 0xc13d, 0x4aff, 0xc13d, 0x21, 0 + .dw 0x4b40, 0xc13d, 0x4b7f, 0xc13d, 0x21, 0 + .dw 0x4bc0, 0xc13d, 0x4bff, 0xc13d, 0x21, 0 + .dw 0x4c40, 0xc13d, 0x4c7f, 0xc13d, 0x21, 0 + .dw 0x4cc0, 0xc13d, 0x4cff, 0xc13d, 0x21, 0 + .dw 0x4d40, 0xc13d, 0x4d7f, 0xc13d, 0x21, 0 + .dw 0x4dc0, 0xc13d, 0x4dff, 0xc13d, 0x21, 0 + .dw 0x4e40, 0xc13d, 0x4e7f, 0xc13d, 0x21, 0 + .dw 0x4ec0, 0xc13d, 0x4eff, 0xc13d, 0x21, 0 + .dw 0x4f40, 0xc13d, 0x4f7f, 0xc13d, 0x21, 0 + .dw 0x4fc0, 0xc13d, 0x4fff, 0xc13d, 0x21, 0 + .dw 0x5040, 0xc13d, 0x507f, 0xc13d, 0x21, 0 + .dw 0x50c0, 0xc13d, 0x50ff, 0xc13d, 0x21, 0 + .dw 0x5140, 0xc13d, 0x517f, 0xc13d, 0x21, 0 + .dw 0x51c0, 0xc13d, 0x51ff, 0xc13d, 0x21, 0 + .dw 0x5240, 0xc13d, 0x527f, 0xc13d, 0x21, 0 + .dw 0x52c0, 0xc13d, 0x52ff, 0xc13d, 0x21, 0 + .dw 0x5340, 0xc13d, 0x537f, 0xc13d, 0x21, 0 + .dw 0x53c0, 0xc13d, 0x53ff, 0xc13d, 0x21, 0 + .dw 0x5440, 0xc13d, 0x547f, 0xc13d, 0x21, 0 + .dw 0x54c0, 0xc13d, 0x54ff, 0xc13d, 0x21, 0 + .dw 0x5540, 0xc13d, 0x557f, 0xc13d, 0x21, 0 + .dw 0x55c0, 0xc13d, 0x55ff, 0xc13d, 0x21, 0 + .dw 0x5640, 0xc13d, 0x567f, 0xc13d, 0x21, 0 + .dw 0x56c0, 0xc13d, 0x56ff, 0xc13d, 0x21, 0 + .dw 0x5740, 0xc13d, 0x577f, 0xc13d, 0x21, 0 + .dw 0x57c0, 0xc13d, 0x57ff, 0xc13d, 0x21, 0 + .dw 0x5840, 0xc13d, 0x587f, 0xc13d, 0x21, 0 + .dw 0x58c0, 0xc13d, 0x58ff, 0xc13d, 0x21, 0 + .dw 0x5940, 0xc13d, 0x597f, 0xc13d, 0x21, 0 + .dw 0x59c0, 0xc13d, 0x5fff, 0xc13d, 0x21, 0 + .dw 0x6040, 0xc13d, 0x607f, 0xc13d, 0x21, 0 + .dw 0x60c0, 0xc13d, 0x60ff, 0xc13d, 0x21, 0 + .dw 0x6140, 0xc13d, 0x617f, 0xc13d, 0x21, 0 + .dw 0x61c0, 0xc13d, 0x61ff, 0xc13d, 0x21, 0 + .dw 0x6240, 0xc13d, 0x627f, 0xc13d, 0x21, 0 + .dw 0x62c0, 0xc13d, 0x62ff, 0xc13d, 0x21, 0 + .dw 0x6340, 0xc13d, 0x637f, 0xc13d, 0x21, 0 + .dw 0x63c0, 0xc13d, 0x63ff, 0xc13d, 0x21, 0 + .dw 0x6440, 0xc13d, 0x647f, 0xc13d, 0x21, 0 + .dw 0x64c0, 0xc13d, 0x64ff, 0xc13d, 0x21, 0 + .dw 0x6540, 0xc13d, 0x657f, 0xc13d, 0x21, 0 + .dw 0x65c0, 0xc13d, 0x65ff, 0xc13d, 0x21, 0 + .dw 0x6640, 0xc13d, 0x667f, 0xc13d, 0x21, 0 + .dw 0x66c0, 0xc13d, 0x66ff, 0xc13d, 0x21, 0 + .dw 0x6740, 0xc13d, 0x677f, 0xc13d, 0x21, 0 + .dw 0x67c0, 0xc13d, 0x67ff, 0xc13d, 0x21, 0 + .dw 0x6840, 0xc13d, 0x687f, 0xc13d, 0x21, 0 + .dw 0x68c0, 0xc13d, 0x68ff, 0xc13d, 0x21, 0 + .dw 0x6940, 0xc13d, 0x697f, 0xc13d, 0x21, 0 + .dw 0x69c0, 0xc13d, 0x69ff, 0xc13d, 0x21, 0 + .dw 0x6a40, 0xc13d, 0x6a7f, 0xc13d, 0x21, 0 + .dw 0x6ac0, 0xc13d, 0x6aff, 0xc13d, 0x21, 0 + .dw 0x6b40, 0xc13d, 0x6b7f, 0xc13d, 0x21, 0 + .dw 0x6bc0, 0xc13d, 0x6bff, 0xc13d, 0x21, 0 + .dw 0x6c40, 0xc13d, 0x6c7f, 0xc13d, 0x21, 0 + .dw 0x6cc0, 0xc13d, 0x6cff, 0xc13d, 0x21, 0 + .dw 0x6d40, 0xc13d, 0x6d7f, 0xc13d, 0x21, 0 + .dw 0x6dc0, 0xc13d, 0x6dff, 0xc13d, 0x21, 0 + .dw 0x6e40, 0xc13d, 0x6e7f, 0xc13d, 0x21, 0 + .dw 0x6ec0, 0xc13d, 0x6eff, 0xc13d, 0x21, 0 + .dw 0x6f40, 0xc13d, 0x6f7f, 0xc13d, 0x21, 0 + .dw 0x6fc0, 0xc13d, 0x6fff, 0xc13d, 0x21, 0 + .dw 0x7040, 0xc13d, 0x707f, 0xc13d, 0x21, 0 + .dw 0x70c0, 0xc13d, 0x70ff, 0xc13d, 0x21, 0 + .dw 0x7140, 0xc13d, 0x717f, 0xc13d, 0x21, 0 + .dw 0x71c0, 0xc13d, 0x71ff, 0xc13d, 0x21, 0 + .dw 0x7240, 0xc13d, 0x727f, 0xc13d, 0x21, 0 + .dw 0x72c0, 0xc13d, 0x72ff, 0xc13d, 0x21, 0 + .dw 0x7340, 0xc13d, 0x737f, 0xc13d, 0x21, 0 + .dw 0x73c0, 0xc13d, 0x73ff, 0xc13d, 0x21, 0 + .dw 0x7440, 0xc13d, 0x747f, 0xc13d, 0x21, 0 + .dw 0x74c0, 0xc13d, 0x74ff, 0xc13d, 0x21, 0 + .dw 0x7540, 0xc13d, 0x757f, 0xc13d, 0x21, 0 + .dw 0x75c0, 0xc13d, 0x75ff, 0xc13d, 0x21, 0 + .dw 0x7640, 0xc13d, 0x767f, 0xc13d, 0x21, 0 + .dw 0x76c0, 0xc13d, 0x76ff, 0xc13d, 0x21, 0 + .dw 0x7740, 0xc13d, 0x777f, 0xc13d, 0x21, 0 + .dw 0x77c0, 0xc13d, 0x77ff, 0xc13d, 0x21, 0 + .dw 0x7840, 0xc13d, 0x787f, 0xc13d, 0x21, 0 + .dw 0x78c0, 0xc13d, 0x78ff, 0xc13d, 0x21, 0 + .dw 0x7940, 0xc13d, 0x797f, 0xc13d, 0x21, 0 + .dw 0x79c0, 0xc13d, 0x7fff, 0xc13d, 0x21, 0 + .dw 0x8040, 0xc13d, 0x807f, 0xc13d, 0x21, 0 + .dw 0x80c0, 0xc13d, 0x80ff, 0xc13d, 0x21, 0 + .dw 0x8140, 0xc13d, 0x817f, 0xc13d, 0x21, 0 + .dw 0x81c0, 0xc13d, 0x81ff, 0xc13d, 0x21, 0 + .dw 0x8240, 0xc13d, 0x827f, 0xc13d, 0x21, 0 + .dw 0x82c0, 0xc13d, 0x82ff, 0xc13d, 0x21, 0 + .dw 0x8340, 0xc13d, 0x837f, 0xc13d, 0x21, 0 + .dw 0x83c0, 0xc13d, 0x83ff, 0xc13d, 0x21, 0 + .dw 0x8440, 0xc13d, 0x847f, 0xc13d, 0x21, 0 + .dw 0x84c0, 0xc13d, 0x84ff, 0xc13d, 0x21, 0 + .dw 0x8540, 0xc13d, 0x857f, 0xc13d, 0x21, 0 + .dw 0x85c0, 0xc13d, 0x85ff, 0xc13d, 0x21, 0 + .dw 0x8640, 0xc13d, 0x867f, 0xc13d, 0x21, 0 + .dw 0x86c0, 0xc13d, 0x86ff, 0xc13d, 0x21, 0 + .dw 0x8740, 0xc13d, 0x877f, 0xc13d, 0x21, 0 + .dw 0x87c0, 0xc13d, 0x87ff, 0xc13d, 0x21, 0 + .dw 0x8840, 0xc13d, 0x887f, 0xc13d, 0x21, 0 + .dw 0x88c0, 0xc13d, 0x88ff, 0xc13d, 0x21, 0 + .dw 0x8940, 0xc13d, 0x897f, 0xc13d, 0x21, 0 + .dw 0x89c0, 0xc13d, 0x89ff, 0xc13d, 0x21, 0 + .dw 0x8a40, 0xc13d, 0x8a7f, 0xc13d, 0x21, 0 + .dw 0x8ac0, 0xc13d, 0x8aff, 0xc13d, 0x21, 0 + .dw 0x8b40, 0xc13d, 0x8b7f, 0xc13d, 0x21, 0 + .dw 0x8bc0, 0xc13d, 0x8bff, 0xc13d, 0x21, 0 + .dw 0x8c40, 0xc13d, 0x8c7f, 0xc13d, 0x21, 0 + .dw 0x8cc0, 0xc13d, 0x8cff, 0xc13d, 0x21, 0 + .dw 0x8d40, 0xc13d, 0x8d7f, 0xc13d, 0x21, 0 + .dw 0x8dc0, 0xc13d, 0x8dff, 0xc13d, 0x21, 0 + .dw 0x8e40, 0xc13d, 0x8e7f, 0xc13d, 0x21, 0 + .dw 0x8ec0, 0xc13d, 0x8eff, 0xc13d, 0x21, 0 + .dw 0x8f40, 0xc13d, 0x8f7f, 0xc13d, 0x21, 0 + .dw 0x8fc0, 0xc13d, 0x8fff, 0xc13d, 0x21, 0 + .dw 0x9040, 0xc13d, 0x907f, 0xc13d, 0x21, 0 + .dw 0x90c0, 0xc13d, 0x90ff, 0xc13d, 0x21, 0 + .dw 0x9140, 0xc13d, 0x917f, 0xc13d, 0x21, 0 + .dw 0x91c0, 0xc13d, 0x91ff, 0xc13d, 0x21, 0 + .dw 0x9240, 0xc13d, 0x927f, 0xc13d, 0x21, 0 + .dw 0x92c0, 0xc13d, 0x92ff, 0xc13d, 0x21, 0 + .dw 0x9340, 0xc13d, 0x937f, 0xc13d, 0x21, 0 + .dw 0x93c0, 0xc13d, 0x93ff, 0xc13d, 0x21, 0 + .dw 0x9440, 0xc13d, 0x947f, 0xc13d, 0x21, 0 + .dw 0x94c0, 0xc13d, 0x94ff, 0xc13d, 0x21, 0 + .dw 0x9540, 0xc13d, 0x957f, 0xc13d, 0x21, 0 + .dw 0x95c0, 0xc13d, 0x95ff, 0xc13d, 0x21, 0 + .dw 0x9640, 0xc13d, 0x967f, 0xc13d, 0x21, 0 + .dw 0x96c0, 0xc13d, 0x96ff, 0xc13d, 0x21, 0 + .dw 0x9740, 0xc13d, 0x977f, 0xc13d, 0x21, 0 + .dw 0x97c0, 0xc13d, 0x97ff, 0xc13d, 0x21, 0 + .dw 0x9840, 0xc13d, 0x987f, 0xc13d, 0x21, 0 + .dw 0x98c0, 0xc13d, 0x98ff, 0xc13d, 0x21, 0 + .dw 0x9940, 0xc13d, 0x997f, 0xc13d, 0x21, 0 + .dw 0x99c0, 0xc13d, 0x9fff, 0xc13d, 0x21, 0 + .dw 0xa040, 0xc13d, 0xa07f, 0xc13d, 0x21, 0 + .dw 0xa0c0, 0xc13d, 0xa0ff, 0xc13d, 0x21, 0 + .dw 0xa140, 0xc13d, 0xa17f, 0xc13d, 0x21, 0 + .dw 0xa1c0, 0xc13d, 0xa1ff, 0xc13d, 0x21, 0 + .dw 0xa240, 0xc13d, 0xa27f, 0xc13d, 0x21, 0 + .dw 0xa2c0, 0xc13d, 0xa2ff, 0xc13d, 0x21, 0 + .dw 0xa340, 0xc13d, 0xa37f, 0xc13d, 0x21, 0 + .dw 0xa3c0, 0xc13d, 0xa3ff, 0xc13d, 0x21, 0 + .dw 0xa440, 0xc13d, 0xa47f, 0xc13d, 0x21, 0 + .dw 0xa4c0, 0xc13d, 0xa4ff, 0xc13d, 0x21, 0 + .dw 0xa540, 0xc13d, 0xa57f, 0xc13d, 0x21, 0 + .dw 0xa5c0, 0xc13d, 0xa5ff, 0xc13d, 0x21, 0 + .dw 0xa640, 0xc13d, 0xa67f, 0xc13d, 0x21, 0 + .dw 0xa6c0, 0xc13d, 0xa6ff, 0xc13d, 0x21, 0 + .dw 0xa740, 0xc13d, 0xa77f, 0xc13d, 0x21, 0 + .dw 0xa7c0, 0xc13d, 0xa7ff, 0xc13d, 0x21, 0 + .dw 0xa840, 0xc13d, 0xa87f, 0xc13d, 0x21, 0 + .dw 0xa8c0, 0xc13d, 0xa8ff, 0xc13d, 0x21, 0 + .dw 0xa940, 0xc13d, 0xa97f, 0xc13d, 0x21, 0 + .dw 0xa9c0, 0xc13d, 0xa9ff, 0xc13d, 0x21, 0 + .dw 0xaa40, 0xc13d, 0xaa7f, 0xc13d, 0x21, 0 + .dw 0xaac0, 0xc13d, 0xaaff, 0xc13d, 0x21, 0 + .dw 0xab40, 0xc13d, 0xab7f, 0xc13d, 0x21, 0 + .dw 0xabc0, 0xc13d, 0xabff, 0xc13d, 0x21, 0 + .dw 0xac40, 0xc13d, 0xac7f, 0xc13d, 0x21, 0 + .dw 0xacc0, 0xc13d, 0xacff, 0xc13d, 0x21, 0 + .dw 0xad40, 0xc13d, 0xad7f, 0xc13d, 0x21, 0 + .dw 0xadc0, 0xc13d, 0xadff, 0xc13d, 0x21, 0 + .dw 0xae40, 0xc13d, 0xae7f, 0xc13d, 0x21, 0 + .dw 0xaec0, 0xc13d, 0xaeff, 0xc13d, 0x21, 0 + .dw 0xaf40, 0xc13d, 0xaf7f, 0xc13d, 0x21, 0 + .dw 0xafc0, 0xc13d, 0xafff, 0xc13d, 0x21, 0 + .dw 0xb040, 0xc13d, 0xb07f, 0xc13d, 0x21, 0 + .dw 0xb0c0, 0xc13d, 0xb0ff, 0xc13d, 0x21, 0 + .dw 0xb140, 0xc13d, 0xb17f, 0xc13d, 0x21, 0 + .dw 0xb1c0, 0xc13d, 0xb1ff, 0xc13d, 0x21, 0 + .dw 0xb240, 0xc13d, 0xb27f, 0xc13d, 0x21, 0 + .dw 0xb2c0, 0xc13d, 0xb2ff, 0xc13d, 0x21, 0 + .dw 0xb340, 0xc13d, 0xb37f, 0xc13d, 0x21, 0 + .dw 0xb3c0, 0xc13d, 0xb3ff, 0xc13d, 0x21, 0 + .dw 0xb440, 0xc13d, 0xb47f, 0xc13d, 0x21, 0 + .dw 0xb4c0, 0xc13d, 0xb4ff, 0xc13d, 0x21, 0 + .dw 0xb540, 0xc13d, 0xb57f, 0xc13d, 0x21, 0 + .dw 0xb5c0, 0xc13d, 0xb5ff, 0xc13d, 0x21, 0 + .dw 0xb640, 0xc13d, 0xb67f, 0xc13d, 0x21, 0 + .dw 0xb6c0, 0xc13d, 0xb6ff, 0xc13d, 0x21, 0 + .dw 0xb740, 0xc13d, 0xb77f, 0xc13d, 0x21, 0 + .dw 0xb7c0, 0xc13d, 0xb7ff, 0xc13d, 0x21, 0 + .dw 0xb840, 0xc13d, 0xb87f, 0xc13d, 0x21, 0 + .dw 0xb8c0, 0xc13d, 0xb8ff, 0xc13d, 0x21, 0 + .dw 0xb940, 0xc13d, 0xb97f, 0xc13d, 0x21, 0 + .dw 0xb9c0, 0xc13d, 0xbfff, 0xc13d, 0x21, 0 + .dw 0xc040, 0xc13d, 0xc07f, 0xc13d, 0x21, 0 + .dw 0xc0c0, 0xc13d, 0xc0ff, 0xc13d, 0x21, 0 + .dw 0xc140, 0xc13d, 0xc17f, 0xc13d, 0x21, 0 + .dw 0xc1c0, 0xc13d, 0xc1ff, 0xc13d, 0x21, 0 + .dw 0xc240, 0xc13d, 0xc27f, 0xc13d, 0x21, 0 + .dw 0xc2c0, 0xc13d, 0xc2ff, 0xc13d, 0x21, 0 + .dw 0xc340, 0xc13d, 0xc37f, 0xc13d, 0x21, 0 + .dw 0xc3c0, 0xc13d, 0xc3ff, 0xc13d, 0x21, 0 + .dw 0xc440, 0xc13d, 0xc47f, 0xc13d, 0x21, 0 + .dw 0xc4c0, 0xc13d, 0xc4ff, 0xc13d, 0x21, 0 + .dw 0xc540, 0xc13d, 0xc57f, 0xc13d, 0x21, 0 + .dw 0xc5c0, 0xc13d, 0xc5ff, 0xc13d, 0x21, 0 + .dw 0xc640, 0xc13d, 0xc67f, 0xc13d, 0x21, 0 + .dw 0xc6c0, 0xc13d, 0xc6ff, 0xc13d, 0x21, 0 + .dw 0xc740, 0xc13d, 0xc77f, 0xc13d, 0x21, 0 + .dw 0xc7c0, 0xc13d, 0xc7ff, 0xc13d, 0x21, 0 + .dw 0xc840, 0xc13d, 0xc87f, 0xc13d, 0x21, 0 + .dw 0xc8c0, 0xc13d, 0xc8ff, 0xc13d, 0x21, 0 + .dw 0xc940, 0xc13d, 0xc97f, 0xc13d, 0x21, 0 + .dw 0xc9c0, 0xc13d, 0xc9ff, 0xc13d, 0x21, 0 + .dw 0xca40, 0xc13d, 0xca7f, 0xc13d, 0x21, 0 + .dw 0xcac0, 0xc13d, 0xcaff, 0xc13d, 0x21, 0 + .dw 0xcb40, 0xc13d, 0xcb7f, 0xc13d, 0x21, 0 + .dw 0xcbc0, 0xc13d, 0xcbff, 0xc13d, 0x21, 0 + .dw 0xcc40, 0xc13d, 0xcc7f, 0xc13d, 0x21, 0 + .dw 0xccc0, 0xc13d, 0xccff, 0xc13d, 0x21, 0 + .dw 0xcd40, 0xc13d, 0xcd7f, 0xc13d, 0x21, 0 + .dw 0xcdc0, 0xc13d, 0xcdff, 0xc13d, 0x21, 0 + .dw 0xce40, 0xc13d, 0xce7f, 0xc13d, 0x21, 0 + .dw 0xcec0, 0xc13d, 0xceff, 0xc13d, 0x21, 0 + .dw 0xcf40, 0xc13d, 0xcf7f, 0xc13d, 0x21, 0 + .dw 0xcfc0, 0xc13d, 0xcfff, 0xc13d, 0x21, 0 + .dw 0xd040, 0xc13d, 0xd07f, 0xc13d, 0x21, 0 + .dw 0xd0c0, 0xc13d, 0xd0ff, 0xc13d, 0x21, 0 + .dw 0xd140, 0xc13d, 0xd17f, 0xc13d, 0x21, 0 + .dw 0xd1c0, 0xc13d, 0xd1ff, 0xc13d, 0x21, 0 + .dw 0xd240, 0xc13d, 0xd27f, 0xc13d, 0x21, 0 + .dw 0xd2c0, 0xc13d, 0xd2ff, 0xc13d, 0x21, 0 + .dw 0xd340, 0xc13d, 0xd37f, 0xc13d, 0x21, 0 + .dw 0xd3c0, 0xc13d, 0xd3ff, 0xc13d, 0x21, 0 + .dw 0xd440, 0xc13d, 0xd47f, 0xc13d, 0x21, 0 + .dw 0xd4c0, 0xc13d, 0xd4ff, 0xc13d, 0x21, 0 + .dw 0xd540, 0xc13d, 0xd57f, 0xc13d, 0x21, 0 + .dw 0xd5c0, 0xc13d, 0xd5ff, 0xc13d, 0x21, 0 + .dw 0xd640, 0xc13d, 0xd67f, 0xc13d, 0x21, 0 + .dw 0xd6c0, 0xc13d, 0xd6ff, 0xc13d, 0x21, 0 + .dw 0xd740, 0xc13d, 0xd77f, 0xc13d, 0x21, 0 + .dw 0xd7c0, 0xc13d, 0xd7ff, 0xc13d, 0x21, 0 + .dw 0xd840, 0xc13d, 0xd87f, 0xc13d, 0x21, 0 + .dw 0xd8c0, 0xc13d, 0xd8ff, 0xc13d, 0x21, 0 + .dw 0xd940, 0xc13d, 0xd97f, 0xc13d, 0x21, 0 + .dw 0xd9c0, 0xc13d, 0xdfff, 0xc13d, 0x21, 0 + .dw 0xe040, 0xc13d, 0xe07f, 0xc13d, 0x21, 0 + .dw 0xe0c0, 0xc13d, 0xe0ff, 0xc13d, 0x21, 0 + .dw 0xe140, 0xc13d, 0xe17f, 0xc13d, 0x21, 0 + .dw 0xe1c0, 0xc13d, 0xe1ff, 0xc13d, 0x21, 0 + .dw 0xe240, 0xc13d, 0xe27f, 0xc13d, 0x21, 0 + .dw 0xe2c0, 0xc13d, 0xe2ff, 0xc13d, 0x21, 0 + .dw 0xe340, 0xc13d, 0xe37f, 0xc13d, 0x21, 0 + .dw 0xe3c0, 0xc13d, 0xe3ff, 0xc13d, 0x21, 0 + .dw 0xe440, 0xc13d, 0xe47f, 0xc13d, 0x21, 0 + .dw 0xe4c0, 0xc13d, 0xe4ff, 0xc13d, 0x21, 0 + .dw 0xe540, 0xc13d, 0xe57f, 0xc13d, 0x21, 0 + .dw 0xe5c0, 0xc13d, 0xe5ff, 0xc13d, 0x21, 0 + .dw 0xe640, 0xc13d, 0xe67f, 0xc13d, 0x21, 0 + .dw 0xe6c0, 0xc13d, 0xe6ff, 0xc13d, 0x21, 0 + .dw 0xe740, 0xc13d, 0xe77f, 0xc13d, 0x21, 0 + .dw 0xe7c0, 0xc13d, 0xe7ff, 0xc13d, 0x21, 0 + .dw 0xe840, 0xc13d, 0xe87f, 0xc13d, 0x21, 0 + .dw 0xe8c0, 0xc13d, 0xe8ff, 0xc13d, 0x21, 0 + .dw 0xe940, 0xc13d, 0xe97f, 0xc13d, 0x21, 0 + .dw 0xe9c0, 0xc13d, 0xe9ff, 0xc13d, 0x21, 0 + .dw 0xea40, 0xc13d, 0xea7f, 0xc13d, 0x21, 0 + .dw 0xeac0, 0xc13d, 0xeaff, 0xc13d, 0x21, 0 + .dw 0xeb40, 0xc13d, 0xeb7f, 0xc13d, 0x21, 0 + .dw 0xebc0, 0xc13d, 0xebff, 0xc13d, 0x21, 0 + .dw 0xec40, 0xc13d, 0xec7f, 0xc13d, 0x21, 0 + .dw 0xecc0, 0xc13d, 0xecff, 0xc13d, 0x21, 0 + .dw 0xed40, 0xc13d, 0xed7f, 0xc13d, 0x21, 0 + .dw 0xedc0, 0xc13d, 0xedff, 0xc13d, 0x21, 0 + .dw 0xee40, 0xc13d, 0xee7f, 0xc13d, 0x21, 0 + .dw 0xeec0, 0xc13d, 0xeeff, 0xc13d, 0x21, 0 + .dw 0xef40, 0xc13d, 0xef7f, 0xc13d, 0x21, 0 + .dw 0xefc0, 0xc13d, 0xefff, 0xc13d, 0x21, 0 + .dw 0xf040, 0xc13d, 0xf07f, 0xc13d, 0x21, 0 + .dw 0xf0c0, 0xc13d, 0xf0ff, 0xc13d, 0x21, 0 + .dw 0xf140, 0xc13d, 0xf17f, 0xc13d, 0x21, 0 + .dw 0xf1c0, 0xc13d, 0xf1ff, 0xc13d, 0x21, 0 + .dw 0xf240, 0xc13d, 0xf27f, 0xc13d, 0x21, 0 + .dw 0xf2c0, 0xc13d, 0xf2ff, 0xc13d, 0x21, 0 + .dw 0xf340, 0xc13d, 0xf37f, 0xc13d, 0x21, 0 + .dw 0xf3c0, 0xc13d, 0xf3ff, 0xc13d, 0x21, 0 + .dw 0xf440, 0xc13d, 0xf47f, 0xc13d, 0x21, 0 + .dw 0xf4c0, 0xc13d, 0xf4ff, 0xc13d, 0x21, 0 + .dw 0xf540, 0xc13d, 0xf57f, 0xc13d, 0x21, 0 + .dw 0xf5c0, 0xc13d, 0xf5ff, 0xc13d, 0x21, 0 + .dw 0xf640, 0xc13d, 0xf67f, 0xc13d, 0x21, 0 + .dw 0xf6c0, 0xc13d, 0xf6ff, 0xc13d, 0x21, 0 + .dw 0xf740, 0xc13d, 0xf77f, 0xc13d, 0x21, 0 + .dw 0xf7c0, 0xc13d, 0xf7ff, 0xc13d, 0x21, 0 + .dw 0xf840, 0xc13d, 0xf87f, 0xc13d, 0x21, 0 + .dw 0xf8c0, 0xc13d, 0xf8ff, 0xc13d, 0x21, 0 + .dw 0xf940, 0xc13d, 0xf97f, 0xc13d, 0x21, 0 + .dw 0xf9c0, 0xc13d, 0xffff, 0xc13d, 0x21, 0 + .dw 0x0040, 0xc13e, 0x007f, 0xc13e, 0x21, 0 + .dw 0x00c0, 0xc13e, 0x00ff, 0xc13e, 0x21, 0 + .dw 0x0140, 0xc13e, 0x017f, 0xc13e, 0x21, 0 + .dw 0x01c0, 0xc13e, 0x01ff, 0xc13e, 0x21, 0 + .dw 0x0240, 0xc13e, 0x027f, 0xc13e, 0x21, 0 + .dw 0x02c0, 0xc13e, 0x02ff, 0xc13e, 0x21, 0 + .dw 0x0340, 0xc13e, 0x037f, 0xc13e, 0x21, 0 + .dw 0x03c0, 0xc13e, 0x03ff, 0xc13e, 0x21, 0 + .dw 0x0440, 0xc13e, 0x047f, 0xc13e, 0x21, 0 + .dw 0x04c0, 0xc13e, 0x04ff, 0xc13e, 0x21, 0 + .dw 0x0540, 0xc13e, 0x057f, 0xc13e, 0x21, 0 + .dw 0x05c0, 0xc13e, 0x05ff, 0xc13e, 0x21, 0 + .dw 0x0640, 0xc13e, 0x067f, 0xc13e, 0x21, 0 + .dw 0x06c0, 0xc13e, 0x06ff, 0xc13e, 0x21, 0 + .dw 0x0740, 0xc13e, 0x077f, 0xc13e, 0x21, 0 + .dw 0x07c0, 0xc13e, 0x07ff, 0xc13e, 0x21, 0 + .dw 0x0840, 0xc13e, 0x087f, 0xc13e, 0x21, 0 + .dw 0x08c0, 0xc13e, 0x08ff, 0xc13e, 0x21, 0 + .dw 0x0940, 0xc13e, 0x097f, 0xc13e, 0x21, 0 + .dw 0x09c0, 0xc13e, 0x09ff, 0xc13e, 0x21, 0 + .dw 0x0a40, 0xc13e, 0x0a7f, 0xc13e, 0x21, 0 + .dw 0x0ac0, 0xc13e, 0x0aff, 0xc13e, 0x21, 0 + .dw 0x0b40, 0xc13e, 0x0b7f, 0xc13e, 0x21, 0 + .dw 0x0bc0, 0xc13e, 0x0bff, 0xc13e, 0x21, 0 + .dw 0x0c40, 0xc13e, 0x0c7f, 0xc13e, 0x21, 0 + .dw 0x0cc0, 0xc13e, 0x0cff, 0xc13e, 0x21, 0 + .dw 0x0d40, 0xc13e, 0x0d7f, 0xc13e, 0x21, 0 + .dw 0x0dc0, 0xc13e, 0x0dff, 0xc13e, 0x21, 0 + .dw 0x0e40, 0xc13e, 0x0e7f, 0xc13e, 0x21, 0 + .dw 0x0ec0, 0xc13e, 0x0eff, 0xc13e, 0x21, 0 + .dw 0x0f40, 0xc13e, 0x0f7f, 0xc13e, 0x21, 0 + .dw 0x0fc0, 0xc13e, 0x0fff, 0xc13e, 0x21, 0 + .dw 0x1040, 0xc13e, 0x107f, 0xc13e, 0x21, 0 + .dw 0x10c0, 0xc13e, 0x10ff, 0xc13e, 0x21, 0 + .dw 0x1140, 0xc13e, 0x117f, 0xc13e, 0x21, 0 + .dw 0x11c0, 0xc13e, 0x11ff, 0xc13e, 0x21, 0 + .dw 0x1240, 0xc13e, 0x127f, 0xc13e, 0x21, 0 + .dw 0x12c0, 0xc13e, 0x12ff, 0xc13e, 0x21, 0 + .dw 0x1340, 0xc13e, 0x137f, 0xc13e, 0x21, 0 + .dw 0x13c0, 0xc13e, 0x13ff, 0xc13e, 0x21, 0 + .dw 0x1440, 0xc13e, 0x147f, 0xc13e, 0x21, 0 + .dw 0x14c0, 0xc13e, 0x14ff, 0xc13e, 0x21, 0 + .dw 0x1540, 0xc13e, 0x157f, 0xc13e, 0x21, 0 + .dw 0x15c0, 0xc13e, 0x15ff, 0xc13e, 0x21, 0 + .dw 0x1640, 0xc13e, 0x167f, 0xc13e, 0x21, 0 + .dw 0x16c0, 0xc13e, 0x16ff, 0xc13e, 0x21, 0 + .dw 0x1740, 0xc13e, 0x177f, 0xc13e, 0x21, 0 + .dw 0x17c0, 0xc13e, 0x17ff, 0xc13e, 0x21, 0 + .dw 0x1840, 0xc13e, 0x187f, 0xc13e, 0x21, 0 + .dw 0x18c0, 0xc13e, 0x18ff, 0xc13e, 0x21, 0 + .dw 0x1940, 0xc13e, 0x197f, 0xc13e, 0x21, 0 + .dw 0x19c0, 0xc13e, 0x1fff, 0xc13e, 0x21, 0 + .dw 0x2040, 0xc13e, 0x207f, 0xc13e, 0x21, 0 + .dw 0x20c0, 0xc13e, 0x20ff, 0xc13e, 0x21, 0 + .dw 0x2140, 0xc13e, 0x217f, 0xc13e, 0x21, 0 + .dw 0x21c0, 0xc13e, 0x21ff, 0xc13e, 0x21, 0 + .dw 0x2240, 0xc13e, 0x227f, 0xc13e, 0x21, 0 + .dw 0x22c0, 0xc13e, 0x22ff, 0xc13e, 0x21, 0 + .dw 0x2340, 0xc13e, 0x237f, 0xc13e, 0x21, 0 + .dw 0x23c0, 0xc13e, 0x23ff, 0xc13e, 0x21, 0 + .dw 0x2440, 0xc13e, 0x247f, 0xc13e, 0x21, 0 + .dw 0x24c0, 0xc13e, 0x24ff, 0xc13e, 0x21, 0 + .dw 0x2540, 0xc13e, 0x257f, 0xc13e, 0x21, 0 + .dw 0x25c0, 0xc13e, 0x25ff, 0xc13e, 0x21, 0 + .dw 0x2640, 0xc13e, 0x267f, 0xc13e, 0x21, 0 + .dw 0x26c0, 0xc13e, 0x26ff, 0xc13e, 0x21, 0 + .dw 0x2740, 0xc13e, 0x277f, 0xc13e, 0x21, 0 + .dw 0x27c0, 0xc13e, 0x27ff, 0xc13e, 0x21, 0 + .dw 0x2840, 0xc13e, 0x287f, 0xc13e, 0x21, 0 + .dw 0x28c0, 0xc13e, 0x28ff, 0xc13e, 0x21, 0 + .dw 0x2940, 0xc13e, 0x297f, 0xc13e, 0x21, 0 + .dw 0x29c0, 0xc13e, 0x29ff, 0xc13e, 0x21, 0 + .dw 0x2a40, 0xc13e, 0x2a7f, 0xc13e, 0x21, 0 + .dw 0x2ac0, 0xc13e, 0x2aff, 0xc13e, 0x21, 0 + .dw 0x2b40, 0xc13e, 0x2b7f, 0xc13e, 0x21, 0 + .dw 0x2bc0, 0xc13e, 0x2bff, 0xc13e, 0x21, 0 + .dw 0x2c40, 0xc13e, 0x2c7f, 0xc13e, 0x21, 0 + .dw 0x2cc0, 0xc13e, 0x2cff, 0xc13e, 0x21, 0 + .dw 0x2d40, 0xc13e, 0x2d7f, 0xc13e, 0x21, 0 + .dw 0x2dc0, 0xc13e, 0x2dff, 0xc13e, 0x21, 0 + .dw 0x2e40, 0xc13e, 0x2e7f, 0xc13e, 0x21, 0 + .dw 0x2ec0, 0xc13e, 0x2eff, 0xc13e, 0x21, 0 + .dw 0x2f40, 0xc13e, 0x2f7f, 0xc13e, 0x21, 0 + .dw 0x2fc0, 0xc13e, 0x2fff, 0xc13e, 0x21, 0 + .dw 0x3040, 0xc13e, 0x307f, 0xc13e, 0x21, 0 + .dw 0x30c0, 0xc13e, 0x30ff, 0xc13e, 0x21, 0 + .dw 0x3140, 0xc13e, 0x317f, 0xc13e, 0x21, 0 + .dw 0x31c0, 0xc13e, 0x31ff, 0xc13e, 0x21, 0 + .dw 0x3240, 0xc13e, 0x327f, 0xc13e, 0x21, 0 + .dw 0x32c0, 0xc13e, 0x32ff, 0xc13e, 0x21, 0 + .dw 0x3340, 0xc13e, 0x337f, 0xc13e, 0x21, 0 + .dw 0x33c0, 0xc13e, 0x33ff, 0xc13e, 0x21, 0 + .dw 0x3440, 0xc13e, 0x347f, 0xc13e, 0x21, 0 + .dw 0x34c0, 0xc13e, 0x34ff, 0xc13e, 0x21, 0 + .dw 0x3540, 0xc13e, 0x357f, 0xc13e, 0x21, 0 + .dw 0x35c0, 0xc13e, 0x35ff, 0xc13e, 0x21, 0 + .dw 0x3640, 0xc13e, 0x367f, 0xc13e, 0x21, 0 + .dw 0x36c0, 0xc13e, 0x36ff, 0xc13e, 0x21, 0 + .dw 0x3740, 0xc13e, 0x377f, 0xc13e, 0x21, 0 + .dw 0x37c0, 0xc13e, 0x37ff, 0xc13e, 0x21, 0 + .dw 0x3840, 0xc13e, 0x387f, 0xc13e, 0x21, 0 + .dw 0x38c0, 0xc13e, 0x38ff, 0xc13e, 0x21, 0 + .dw 0x3940, 0xc13e, 0x397f, 0xc13e, 0x21, 0 + .dw 0x39c0, 0xc13e, 0x3fff, 0xc13e, 0x21, 0 + .dw 0x4040, 0xc13e, 0x407f, 0xc13e, 0x21, 0 + .dw 0x40c0, 0xc13e, 0x40ff, 0xc13e, 0x21, 0 + .dw 0x4140, 0xc13e, 0x417f, 0xc13e, 0x21, 0 + .dw 0x41c0, 0xc13e, 0x41ff, 0xc13e, 0x21, 0 + .dw 0x4240, 0xc13e, 0x427f, 0xc13e, 0x21, 0 + .dw 0x42c0, 0xc13e, 0x42ff, 0xc13e, 0x21, 0 + .dw 0x4340, 0xc13e, 0x437f, 0xc13e, 0x21, 0 + .dw 0x43c0, 0xc13e, 0x43ff, 0xc13e, 0x21, 0 + .dw 0x4440, 0xc13e, 0x447f, 0xc13e, 0x21, 0 + .dw 0x44c0, 0xc13e, 0x44ff, 0xc13e, 0x21, 0 + .dw 0x4540, 0xc13e, 0x457f, 0xc13e, 0x21, 0 + .dw 0x45c0, 0xc13e, 0x45ff, 0xc13e, 0x21, 0 + .dw 0x4640, 0xc13e, 0x467f, 0xc13e, 0x21, 0 + .dw 0x46c0, 0xc13e, 0x46ff, 0xc13e, 0x21, 0 + .dw 0x4740, 0xc13e, 0x477f, 0xc13e, 0x21, 0 + .dw 0x47c0, 0xc13e, 0x47ff, 0xc13e, 0x21, 0 + .dw 0x4840, 0xc13e, 0x487f, 0xc13e, 0x21, 0 + .dw 0x48c0, 0xc13e, 0x48ff, 0xc13e, 0x21, 0 + .dw 0x4940, 0xc13e, 0x497f, 0xc13e, 0x21, 0 + .dw 0x49c0, 0xc13e, 0x49ff, 0xc13e, 0x21, 0 + .dw 0x4a40, 0xc13e, 0x4a7f, 0xc13e, 0x21, 0 + .dw 0x4ac0, 0xc13e, 0x4aff, 0xc13e, 0x21, 0 + .dw 0x4b40, 0xc13e, 0x4b7f, 0xc13e, 0x21, 0 + .dw 0x4bc0, 0xc13e, 0x4bff, 0xc13e, 0x21, 0 + .dw 0x4c40, 0xc13e, 0x4c7f, 0xc13e, 0x21, 0 + .dw 0x4cc0, 0xc13e, 0x4cff, 0xc13e, 0x21, 0 + .dw 0x4d40, 0xc13e, 0x4d7f, 0xc13e, 0x21, 0 + .dw 0x4dc0, 0xc13e, 0x4dff, 0xc13e, 0x21, 0 + .dw 0x4e40, 0xc13e, 0x4e7f, 0xc13e, 0x21, 0 + .dw 0x4ec0, 0xc13e, 0x4eff, 0xc13e, 0x21, 0 + .dw 0x4f40, 0xc13e, 0x4f7f, 0xc13e, 0x21, 0 + .dw 0x4fc0, 0xc13e, 0x4fff, 0xc13e, 0x21, 0 + .dw 0x5040, 0xc13e, 0x507f, 0xc13e, 0x21, 0 + .dw 0x50c0, 0xc13e, 0x50ff, 0xc13e, 0x21, 0 + .dw 0x5140, 0xc13e, 0x517f, 0xc13e, 0x21, 0 + .dw 0x51c0, 0xc13e, 0x51ff, 0xc13e, 0x21, 0 + .dw 0x5240, 0xc13e, 0x527f, 0xc13e, 0x21, 0 + .dw 0x52c0, 0xc13e, 0x52ff, 0xc13e, 0x21, 0 + .dw 0x5340, 0xc13e, 0x537f, 0xc13e, 0x21, 0 + .dw 0x53c0, 0xc13e, 0x53ff, 0xc13e, 0x21, 0 + .dw 0x5440, 0xc13e, 0x547f, 0xc13e, 0x21, 0 + .dw 0x54c0, 0xc13e, 0x54ff, 0xc13e, 0x21, 0 + .dw 0x5540, 0xc13e, 0x557f, 0xc13e, 0x21, 0 + .dw 0x55c0, 0xc13e, 0x55ff, 0xc13e, 0x21, 0 + .dw 0x5640, 0xc13e, 0x567f, 0xc13e, 0x21, 0 + .dw 0x56c0, 0xc13e, 0x56ff, 0xc13e, 0x21, 0 + .dw 0x5740, 0xc13e, 0x577f, 0xc13e, 0x21, 0 + .dw 0x57c0, 0xc13e, 0x57ff, 0xc13e, 0x21, 0 + .dw 0x5840, 0xc13e, 0x587f, 0xc13e, 0x21, 0 + .dw 0x58c0, 0xc13e, 0x58ff, 0xc13e, 0x21, 0 + .dw 0x5940, 0xc13e, 0x597f, 0xc13e, 0x21, 0 + .dw 0x59c0, 0xc13e, 0x5fff, 0xc13e, 0x21, 0 + .dw 0x6040, 0xc13e, 0x607f, 0xc13e, 0x21, 0 + .dw 0x60c0, 0xc13e, 0x60ff, 0xc13e, 0x21, 0 + .dw 0x6140, 0xc13e, 0x617f, 0xc13e, 0x21, 0 + .dw 0x61c0, 0xc13e, 0x61ff, 0xc13e, 0x21, 0 + .dw 0x6240, 0xc13e, 0x627f, 0xc13e, 0x21, 0 + .dw 0x62c0, 0xc13e, 0x62ff, 0xc13e, 0x21, 0 + .dw 0x6340, 0xc13e, 0x637f, 0xc13e, 0x21, 0 + .dw 0x63c0, 0xc13e, 0x63ff, 0xc13e, 0x21, 0 + .dw 0x6440, 0xc13e, 0x647f, 0xc13e, 0x21, 0 + .dw 0x64c0, 0xc13e, 0x64ff, 0xc13e, 0x21, 0 + .dw 0x6540, 0xc13e, 0x657f, 0xc13e, 0x21, 0 + .dw 0x65c0, 0xc13e, 0x65ff, 0xc13e, 0x21, 0 + .dw 0x6640, 0xc13e, 0x667f, 0xc13e, 0x21, 0 + .dw 0x66c0, 0xc13e, 0x66ff, 0xc13e, 0x21, 0 + .dw 0x6740, 0xc13e, 0x677f, 0xc13e, 0x21, 0 + .dw 0x67c0, 0xc13e, 0x67ff, 0xc13e, 0x21, 0 + .dw 0x6840, 0xc13e, 0x687f, 0xc13e, 0x21, 0 + .dw 0x68c0, 0xc13e, 0x68ff, 0xc13e, 0x21, 0 + .dw 0x6940, 0xc13e, 0x697f, 0xc13e, 0x21, 0 + .dw 0x69c0, 0xc13e, 0x69ff, 0xc13e, 0x21, 0 + .dw 0x6a40, 0xc13e, 0x6a7f, 0xc13e, 0x21, 0 + .dw 0x6ac0, 0xc13e, 0x6aff, 0xc13e, 0x21, 0 + .dw 0x6b40, 0xc13e, 0x6b7f, 0xc13e, 0x21, 0 + .dw 0x6bc0, 0xc13e, 0x6bff, 0xc13e, 0x21, 0 + .dw 0x6c40, 0xc13e, 0x6c7f, 0xc13e, 0x21, 0 + .dw 0x6cc0, 0xc13e, 0x6cff, 0xc13e, 0x21, 0 + .dw 0x6d40, 0xc13e, 0x6d7f, 0xc13e, 0x21, 0 + .dw 0x6dc0, 0xc13e, 0x6dff, 0xc13e, 0x21, 0 + .dw 0x6e40, 0xc13e, 0x6e7f, 0xc13e, 0x21, 0 + .dw 0x6ec0, 0xc13e, 0x6eff, 0xc13e, 0x21, 0 + .dw 0x6f40, 0xc13e, 0x6f7f, 0xc13e, 0x21, 0 + .dw 0x6fc0, 0xc13e, 0x6fff, 0xc13e, 0x21, 0 + .dw 0x7040, 0xc13e, 0x707f, 0xc13e, 0x21, 0 + .dw 0x70c0, 0xc13e, 0x70ff, 0xc13e, 0x21, 0 + .dw 0x7140, 0xc13e, 0x717f, 0xc13e, 0x21, 0 + .dw 0x71c0, 0xc13e, 0x71ff, 0xc13e, 0x21, 0 + .dw 0x7240, 0xc13e, 0x727f, 0xc13e, 0x21, 0 + .dw 0x72c0, 0xc13e, 0x72ff, 0xc13e, 0x21, 0 + .dw 0x7340, 0xc13e, 0x737f, 0xc13e, 0x21, 0 + .dw 0x73c0, 0xc13e, 0x73ff, 0xc13e, 0x21, 0 + .dw 0x7440, 0xc13e, 0x747f, 0xc13e, 0x21, 0 + .dw 0x74c0, 0xc13e, 0x74ff, 0xc13e, 0x21, 0 + .dw 0x7540, 0xc13e, 0x757f, 0xc13e, 0x21, 0 + .dw 0x75c0, 0xc13e, 0x75ff, 0xc13e, 0x21, 0 + .dw 0x7640, 0xc13e, 0x767f, 0xc13e, 0x21, 0 + .dw 0x76c0, 0xc13e, 0x76ff, 0xc13e, 0x21, 0 + .dw 0x7740, 0xc13e, 0x777f, 0xc13e, 0x21, 0 + .dw 0x77c0, 0xc13e, 0x77ff, 0xc13e, 0x21, 0 + .dw 0x7840, 0xc13e, 0x787f, 0xc13e, 0x21, 0 + .dw 0x78c0, 0xc13e, 0x78ff, 0xc13e, 0x21, 0 + .dw 0x7940, 0xc13e, 0x797f, 0xc13e, 0x21, 0 + .dw 0x79c0, 0xc13e, 0x7fff, 0xc13e, 0x21, 0 + .dw 0x8040, 0xc13e, 0x807f, 0xc13e, 0x21, 0 + .dw 0x80c0, 0xc13e, 0x80ff, 0xc13e, 0x21, 0 + .dw 0x8140, 0xc13e, 0x817f, 0xc13e, 0x21, 0 + .dw 0x81c0, 0xc13e, 0x81ff, 0xc13e, 0x21, 0 + .dw 0x8240, 0xc13e, 0x827f, 0xc13e, 0x21, 0 + .dw 0x82c0, 0xc13e, 0x82ff, 0xc13e, 0x21, 0 + .dw 0x8340, 0xc13e, 0x837f, 0xc13e, 0x21, 0 + .dw 0x83c0, 0xc13e, 0x83ff, 0xc13e, 0x21, 0 + .dw 0x8440, 0xc13e, 0x847f, 0xc13e, 0x21, 0 + .dw 0x84c0, 0xc13e, 0x84ff, 0xc13e, 0x21, 0 + .dw 0x8540, 0xc13e, 0x857f, 0xc13e, 0x21, 0 + .dw 0x85c0, 0xc13e, 0x85ff, 0xc13e, 0x21, 0 + .dw 0x8640, 0xc13e, 0x867f, 0xc13e, 0x21, 0 + .dw 0x86c0, 0xc13e, 0x86ff, 0xc13e, 0x21, 0 + .dw 0x8740, 0xc13e, 0x877f, 0xc13e, 0x21, 0 + .dw 0x87c0, 0xc13e, 0x87ff, 0xc13e, 0x21, 0 + .dw 0x8840, 0xc13e, 0x887f, 0xc13e, 0x21, 0 + .dw 0x88c0, 0xc13e, 0x88ff, 0xc13e, 0x21, 0 + .dw 0x8940, 0xc13e, 0x897f, 0xc13e, 0x21, 0 + .dw 0x89c0, 0xc13e, 0x89ff, 0xc13e, 0x21, 0 + .dw 0x8a40, 0xc13e, 0x8a7f, 0xc13e, 0x21, 0 + .dw 0x8ac0, 0xc13e, 0x8aff, 0xc13e, 0x21, 0 + .dw 0x8b40, 0xc13e, 0x8b7f, 0xc13e, 0x21, 0 + .dw 0x8bc0, 0xc13e, 0x8bff, 0xc13e, 0x21, 0 + .dw 0x8c40, 0xc13e, 0x8c7f, 0xc13e, 0x21, 0 + .dw 0x8cc0, 0xc13e, 0x8cff, 0xc13e, 0x21, 0 + .dw 0x8d40, 0xc13e, 0x8d7f, 0xc13e, 0x21, 0 + .dw 0x8dc0, 0xc13e, 0x8dff, 0xc13e, 0x21, 0 + .dw 0x8e40, 0xc13e, 0x8e7f, 0xc13e, 0x21, 0 + .dw 0x8ec0, 0xc13e, 0x8eff, 0xc13e, 0x21, 0 + .dw 0x8f40, 0xc13e, 0x8f7f, 0xc13e, 0x21, 0 + .dw 0x8fc0, 0xc13e, 0x8fff, 0xc13e, 0x21, 0 + .dw 0x9040, 0xc13e, 0x907f, 0xc13e, 0x21, 0 + .dw 0x90c0, 0xc13e, 0x90ff, 0xc13e, 0x21, 0 + .dw 0x9140, 0xc13e, 0x917f, 0xc13e, 0x21, 0 + .dw 0x91c0, 0xc13e, 0x91ff, 0xc13e, 0x21, 0 + .dw 0x9240, 0xc13e, 0x927f, 0xc13e, 0x21, 0 + .dw 0x92c0, 0xc13e, 0x92ff, 0xc13e, 0x21, 0 + .dw 0x9340, 0xc13e, 0x937f, 0xc13e, 0x21, 0 + .dw 0x93c0, 0xc13e, 0x93ff, 0xc13e, 0x21, 0 + .dw 0x9440, 0xc13e, 0x947f, 0xc13e, 0x21, 0 + .dw 0x94c0, 0xc13e, 0x94ff, 0xc13e, 0x21, 0 + .dw 0x9540, 0xc13e, 0x957f, 0xc13e, 0x21, 0 + .dw 0x95c0, 0xc13e, 0x95ff, 0xc13e, 0x21, 0 + .dw 0x9640, 0xc13e, 0x967f, 0xc13e, 0x21, 0 + .dw 0x96c0, 0xc13e, 0x96ff, 0xc13e, 0x21, 0 + .dw 0x9740, 0xc13e, 0x977f, 0xc13e, 0x21, 0 + .dw 0x97c0, 0xc13e, 0x97ff, 0xc13e, 0x21, 0 + .dw 0x9840, 0xc13e, 0x987f, 0xc13e, 0x21, 0 + .dw 0x98c0, 0xc13e, 0x98ff, 0xc13e, 0x21, 0 + .dw 0x9940, 0xc13e, 0x997f, 0xc13e, 0x21, 0 + .dw 0x99c0, 0xc13e, 0x9fff, 0xc13e, 0x21, 0 + .dw 0xa040, 0xc13e, 0xa07f, 0xc13e, 0x21, 0 + .dw 0xa0c0, 0xc13e, 0xa0ff, 0xc13e, 0x21, 0 + .dw 0xa140, 0xc13e, 0xa17f, 0xc13e, 0x21, 0 + .dw 0xa1c0, 0xc13e, 0xa1ff, 0xc13e, 0x21, 0 + .dw 0xa240, 0xc13e, 0xa27f, 0xc13e, 0x21, 0 + .dw 0xa2c0, 0xc13e, 0xa2ff, 0xc13e, 0x21, 0 + .dw 0xa340, 0xc13e, 0xa37f, 0xc13e, 0x21, 0 + .dw 0xa3c0, 0xc13e, 0xa3ff, 0xc13e, 0x21, 0 + .dw 0xa440, 0xc13e, 0xa47f, 0xc13e, 0x21, 0 + .dw 0xa4c0, 0xc13e, 0xa4ff, 0xc13e, 0x21, 0 + .dw 0xa540, 0xc13e, 0xa57f, 0xc13e, 0x21, 0 + .dw 0xa5c0, 0xc13e, 0xa5ff, 0xc13e, 0x21, 0 + .dw 0xa640, 0xc13e, 0xa67f, 0xc13e, 0x21, 0 + .dw 0xa6c0, 0xc13e, 0xa6ff, 0xc13e, 0x21, 0 + .dw 0xa740, 0xc13e, 0xa77f, 0xc13e, 0x21, 0 + .dw 0xa7c0, 0xc13e, 0xa7ff, 0xc13e, 0x21, 0 + .dw 0xa840, 0xc13e, 0xa87f, 0xc13e, 0x21, 0 + .dw 0xa8c0, 0xc13e, 0xa8ff, 0xc13e, 0x21, 0 + .dw 0xa940, 0xc13e, 0xa97f, 0xc13e, 0x21, 0 + .dw 0xa9c0, 0xc13e, 0xa9ff, 0xc13e, 0x21, 0 + .dw 0xaa40, 0xc13e, 0xaa7f, 0xc13e, 0x21, 0 + .dw 0xaac0, 0xc13e, 0xaaff, 0xc13e, 0x21, 0 + .dw 0xab40, 0xc13e, 0xab7f, 0xc13e, 0x21, 0 + .dw 0xabc0, 0xc13e, 0xabff, 0xc13e, 0x21, 0 + .dw 0xac40, 0xc13e, 0xac7f, 0xc13e, 0x21, 0 + .dw 0xacc0, 0xc13e, 0xacff, 0xc13e, 0x21, 0 + .dw 0xad40, 0xc13e, 0xad7f, 0xc13e, 0x21, 0 + .dw 0xadc0, 0xc13e, 0xadff, 0xc13e, 0x21, 0 + .dw 0xae40, 0xc13e, 0xae7f, 0xc13e, 0x21, 0 + .dw 0xaec0, 0xc13e, 0xaeff, 0xc13e, 0x21, 0 + .dw 0xaf40, 0xc13e, 0xaf7f, 0xc13e, 0x21, 0 + .dw 0xafc0, 0xc13e, 0xafff, 0xc13e, 0x21, 0 + .dw 0xb040, 0xc13e, 0xb07f, 0xc13e, 0x21, 0 + .dw 0xb0c0, 0xc13e, 0xb0ff, 0xc13e, 0x21, 0 + .dw 0xb140, 0xc13e, 0xb17f, 0xc13e, 0x21, 0 + .dw 0xb1c0, 0xc13e, 0xb1ff, 0xc13e, 0x21, 0 + .dw 0xb240, 0xc13e, 0xb27f, 0xc13e, 0x21, 0 + .dw 0xb2c0, 0xc13e, 0xb2ff, 0xc13e, 0x21, 0 + .dw 0xb340, 0xc13e, 0xb37f, 0xc13e, 0x21, 0 + .dw 0xb3c0, 0xc13e, 0xb3ff, 0xc13e, 0x21, 0 + .dw 0xb440, 0xc13e, 0xb47f, 0xc13e, 0x21, 0 + .dw 0xb4c0, 0xc13e, 0xb4ff, 0xc13e, 0x21, 0 + .dw 0xb540, 0xc13e, 0xb57f, 0xc13e, 0x21, 0 + .dw 0xb5c0, 0xc13e, 0xb5ff, 0xc13e, 0x21, 0 + .dw 0xb640, 0xc13e, 0xb67f, 0xc13e, 0x21, 0 + .dw 0xb6c0, 0xc13e, 0xb6ff, 0xc13e, 0x21, 0 + .dw 0xb740, 0xc13e, 0xb77f, 0xc13e, 0x21, 0 + .dw 0xb7c0, 0xc13e, 0xb7ff, 0xc13e, 0x21, 0 + .dw 0xb840, 0xc13e, 0xb87f, 0xc13e, 0x21, 0 + .dw 0xb8c0, 0xc13e, 0xb8ff, 0xc13e, 0x21, 0 + .dw 0xb940, 0xc13e, 0xb97f, 0xc13e, 0x21, 0 + .dw 0xb9c0, 0xc13e, 0xbfff, 0xc13e, 0x21, 0 + .dw 0xc040, 0xc13e, 0xc07f, 0xc13e, 0x21, 0 + .dw 0xc0c0, 0xc13e, 0xc0ff, 0xc13e, 0x21, 0 + .dw 0xc140, 0xc13e, 0xc17f, 0xc13e, 0x21, 0 + .dw 0xc1c0, 0xc13e, 0xc1ff, 0xc13e, 0x21, 0 + .dw 0xc240, 0xc13e, 0xc27f, 0xc13e, 0x21, 0 + .dw 0xc2c0, 0xc13e, 0xc2ff, 0xc13e, 0x21, 0 + .dw 0xc340, 0xc13e, 0xc37f, 0xc13e, 0x21, 0 + .dw 0xc3c0, 0xc13e, 0xc3ff, 0xc13e, 0x21, 0 + .dw 0xc440, 0xc13e, 0xc47f, 0xc13e, 0x21, 0 + .dw 0xc4c0, 0xc13e, 0xc4ff, 0xc13e, 0x21, 0 + .dw 0xc540, 0xc13e, 0xc57f, 0xc13e, 0x21, 0 + .dw 0xc5c0, 0xc13e, 0xc5ff, 0xc13e, 0x21, 0 + .dw 0xc640, 0xc13e, 0xc67f, 0xc13e, 0x21, 0 + .dw 0xc6c0, 0xc13e, 0xc6ff, 0xc13e, 0x21, 0 + .dw 0xc740, 0xc13e, 0xc77f, 0xc13e, 0x21, 0 + .dw 0xc7c0, 0xc13e, 0xc7ff, 0xc13e, 0x21, 0 + .dw 0xc840, 0xc13e, 0xc87f, 0xc13e, 0x21, 0 + .dw 0xc8c0, 0xc13e, 0xc8ff, 0xc13e, 0x21, 0 + .dw 0xc940, 0xc13e, 0xc97f, 0xc13e, 0x21, 0 + .dw 0xc9c0, 0xc13e, 0xc9ff, 0xc13e, 0x21, 0 + .dw 0xca40, 0xc13e, 0xca7f, 0xc13e, 0x21, 0 + .dw 0xcac0, 0xc13e, 0xcaff, 0xc13e, 0x21, 0 + .dw 0xcb40, 0xc13e, 0xcb7f, 0xc13e, 0x21, 0 + .dw 0xcbc0, 0xc13e, 0xcbff, 0xc13e, 0x21, 0 + .dw 0xcc40, 0xc13e, 0xcc7f, 0xc13e, 0x21, 0 + .dw 0xccc0, 0xc13e, 0xccff, 0xc13e, 0x21, 0 + .dw 0xcd40, 0xc13e, 0xcd7f, 0xc13e, 0x21, 0 + .dw 0xcdc0, 0xc13e, 0xcdff, 0xc13e, 0x21, 0 + .dw 0xce40, 0xc13e, 0xce7f, 0xc13e, 0x21, 0 + .dw 0xcec0, 0xc13e, 0xceff, 0xc13e, 0x21, 0 + .dw 0xcf40, 0xc13e, 0xcf7f, 0xc13e, 0x21, 0 + .dw 0xcfc0, 0xc13e, 0xcfff, 0xc13e, 0x21, 0 + .dw 0xd040, 0xc13e, 0xd07f, 0xc13e, 0x21, 0 + .dw 0xd0c0, 0xc13e, 0xd0ff, 0xc13e, 0x21, 0 + .dw 0xd140, 0xc13e, 0xd17f, 0xc13e, 0x21, 0 + .dw 0xd1c0, 0xc13e, 0xd1ff, 0xc13e, 0x21, 0 + .dw 0xd240, 0xc13e, 0xd27f, 0xc13e, 0x21, 0 + .dw 0xd2c0, 0xc13e, 0xd2ff, 0xc13e, 0x21, 0 + .dw 0xd340, 0xc13e, 0xd37f, 0xc13e, 0x21, 0 + .dw 0xd3c0, 0xc13e, 0xd3ff, 0xc13e, 0x21, 0 + .dw 0xd440, 0xc13e, 0xd47f, 0xc13e, 0x21, 0 + .dw 0xd4c0, 0xc13e, 0xd4ff, 0xc13e, 0x21, 0 + .dw 0xd540, 0xc13e, 0xd57f, 0xc13e, 0x21, 0 + .dw 0xd5c0, 0xc13e, 0xd5ff, 0xc13e, 0x21, 0 + .dw 0xd640, 0xc13e, 0xd67f, 0xc13e, 0x21, 0 + .dw 0xd6c0, 0xc13e, 0xd6ff, 0xc13e, 0x21, 0 + .dw 0xd740, 0xc13e, 0xd77f, 0xc13e, 0x21, 0 + .dw 0xd7c0, 0xc13e, 0xd7ff, 0xc13e, 0x21, 0 + .dw 0xd840, 0xc13e, 0xd87f, 0xc13e, 0x21, 0 + .dw 0xd8c0, 0xc13e, 0xd8ff, 0xc13e, 0x21, 0 + .dw 0xd940, 0xc13e, 0xd97f, 0xc13e, 0x21, 0 + .dw 0xd9c0, 0xc13e, 0xdfff, 0xc13e, 0x21, 0 + .dw 0xe040, 0xc13e, 0xe07f, 0xc13e, 0x21, 0 + .dw 0xe0c0, 0xc13e, 0xe0ff, 0xc13e, 0x21, 0 + .dw 0xe140, 0xc13e, 0xe17f, 0xc13e, 0x21, 0 + .dw 0xe1c0, 0xc13e, 0xe1ff, 0xc13e, 0x21, 0 + .dw 0xe240, 0xc13e, 0xe27f, 0xc13e, 0x21, 0 + .dw 0xe2c0, 0xc13e, 0xe2ff, 0xc13e, 0x21, 0 + .dw 0xe340, 0xc13e, 0xe37f, 0xc13e, 0x21, 0 + .dw 0xe3c0, 0xc13e, 0xe3ff, 0xc13e, 0x21, 0 + .dw 0xe440, 0xc13e, 0xe47f, 0xc13e, 0x21, 0 + .dw 0xe4c0, 0xc13e, 0xe4ff, 0xc13e, 0x21, 0 + .dw 0xe540, 0xc13e, 0xe57f, 0xc13e, 0x21, 0 + .dw 0xe5c0, 0xc13e, 0xe5ff, 0xc13e, 0x21, 0 + .dw 0xe640, 0xc13e, 0xe67f, 0xc13e, 0x21, 0 + .dw 0xe6c0, 0xc13e, 0xe6ff, 0xc13e, 0x21, 0 + .dw 0xe740, 0xc13e, 0xe77f, 0xc13e, 0x21, 0 + .dw 0xe7c0, 0xc13e, 0xe7ff, 0xc13e, 0x21, 0 + .dw 0xe840, 0xc13e, 0xe87f, 0xc13e, 0x21, 0 + .dw 0xe8c0, 0xc13e, 0xe8ff, 0xc13e, 0x21, 0 + .dw 0xe940, 0xc13e, 0xe97f, 0xc13e, 0x21, 0 + .dw 0xe9c0, 0xc13e, 0xe9ff, 0xc13e, 0x21, 0 + .dw 0xea40, 0xc13e, 0xea7f, 0xc13e, 0x21, 0 + .dw 0xeac0, 0xc13e, 0xeaff, 0xc13e, 0x21, 0 + .dw 0xeb40, 0xc13e, 0xeb7f, 0xc13e, 0x21, 0 + .dw 0xebc0, 0xc13e, 0xebff, 0xc13e, 0x21, 0 + .dw 0xec40, 0xc13e, 0xec7f, 0xc13e, 0x21, 0 + .dw 0xecc0, 0xc13e, 0xecff, 0xc13e, 0x21, 0 + .dw 0xed40, 0xc13e, 0xed7f, 0xc13e, 0x21, 0 + .dw 0xedc0, 0xc13e, 0xedff, 0xc13e, 0x21, 0 + .dw 0xee40, 0xc13e, 0xee7f, 0xc13e, 0x21, 0 + .dw 0xeec0, 0xc13e, 0xeeff, 0xc13e, 0x21, 0 + .dw 0xef40, 0xc13e, 0xef7f, 0xc13e, 0x21, 0 + .dw 0xefc0, 0xc13e, 0xefff, 0xc13e, 0x21, 0 + .dw 0xf040, 0xc13e, 0xf07f, 0xc13e, 0x21, 0 + .dw 0xf0c0, 0xc13e, 0xf0ff, 0xc13e, 0x21, 0 + .dw 0xf140, 0xc13e, 0xf17f, 0xc13e, 0x21, 0 + .dw 0xf1c0, 0xc13e, 0xf1ff, 0xc13e, 0x21, 0 + .dw 0xf240, 0xc13e, 0xf27f, 0xc13e, 0x21, 0 + .dw 0xf2c0, 0xc13e, 0xf2ff, 0xc13e, 0x21, 0 + .dw 0xf340, 0xc13e, 0xf37f, 0xc13e, 0x21, 0 + .dw 0xf3c0, 0xc13e, 0xf3ff, 0xc13e, 0x21, 0 + .dw 0xf440, 0xc13e, 0xf47f, 0xc13e, 0x21, 0 + .dw 0xf4c0, 0xc13e, 0xf4ff, 0xc13e, 0x21, 0 + .dw 0xf540, 0xc13e, 0xf57f, 0xc13e, 0x21, 0 + .dw 0xf5c0, 0xc13e, 0xf5ff, 0xc13e, 0x21, 0 + .dw 0xf640, 0xc13e, 0xf67f, 0xc13e, 0x21, 0 + .dw 0xf6c0, 0xc13e, 0xf6ff, 0xc13e, 0x21, 0 + .dw 0xf740, 0xc13e, 0xf77f, 0xc13e, 0x21, 0 + .dw 0xf7c0, 0xc13e, 0xf7ff, 0xc13e, 0x21, 0 + .dw 0xf840, 0xc13e, 0xf87f, 0xc13e, 0x21, 0 + .dw 0xf8c0, 0xc13e, 0xf8ff, 0xc13e, 0x21, 0 + .dw 0xf940, 0xc13e, 0xf97f, 0xc13e, 0x21, 0 + .dw 0xf9c0, 0xc13e, 0xffff, 0xc13e, 0x21, 0 + .dw 0x0040, 0xc13f, 0x007f, 0xc13f, 0x21, 0 + .dw 0x00c0, 0xc13f, 0x00ff, 0xc13f, 0x21, 0 + .dw 0x0140, 0xc13f, 0x017f, 0xc13f, 0x21, 0 + .dw 0x01c0, 0xc13f, 0x01ff, 0xc13f, 0x21, 0 + .dw 0x0240, 0xc13f, 0x027f, 0xc13f, 0x21, 0 + .dw 0x02c0, 0xc13f, 0x02ff, 0xc13f, 0x21, 0 + .dw 0x0340, 0xc13f, 0x037f, 0xc13f, 0x21, 0 + .dw 0x03c0, 0xc13f, 0x03ff, 0xc13f, 0x21, 0 + .dw 0x0440, 0xc13f, 0x047f, 0xc13f, 0x21, 0 + .dw 0x04c0, 0xc13f, 0x04ff, 0xc13f, 0x21, 0 + .dw 0x0540, 0xc13f, 0x057f, 0xc13f, 0x21, 0 + .dw 0x05c0, 0xc13f, 0x05ff, 0xc13f, 0x21, 0 + .dw 0x0640, 0xc13f, 0x067f, 0xc13f, 0x21, 0 + .dw 0x06c0, 0xc13f, 0x06ff, 0xc13f, 0x21, 0 + .dw 0x0740, 0xc13f, 0x077f, 0xc13f, 0x21, 0 + .dw 0x07c0, 0xc13f, 0x07ff, 0xc13f, 0x21, 0 + .dw 0x0840, 0xc13f, 0x087f, 0xc13f, 0x21, 0 + .dw 0x08c0, 0xc13f, 0x08ff, 0xc13f, 0x21, 0 + .dw 0x0940, 0xc13f, 0x097f, 0xc13f, 0x21, 0 + .dw 0x09c0, 0xc13f, 0x09ff, 0xc13f, 0x21, 0 + .dw 0x0a40, 0xc13f, 0x0a7f, 0xc13f, 0x21, 0 + .dw 0x0ac0, 0xc13f, 0x0aff, 0xc13f, 0x21, 0 + .dw 0x0b40, 0xc13f, 0x0b7f, 0xc13f, 0x21, 0 + .dw 0x0bc0, 0xc13f, 0x0bff, 0xc13f, 0x21, 0 + .dw 0x0c40, 0xc13f, 0x0c7f, 0xc13f, 0x21, 0 + .dw 0x0cc0, 0xc13f, 0x0cff, 0xc13f, 0x21, 0 + .dw 0x0d40, 0xc13f, 0x0d7f, 0xc13f, 0x21, 0 + .dw 0x0dc0, 0xc13f, 0x0dff, 0xc13f, 0x21, 0 + .dw 0x0e40, 0xc13f, 0x0e7f, 0xc13f, 0x21, 0 + .dw 0x0ec0, 0xc13f, 0x0eff, 0xc13f, 0x21, 0 + .dw 0x0f40, 0xc13f, 0x0f7f, 0xc13f, 0x21, 0 + .dw 0x0fc0, 0xc13f, 0x0fff, 0xc13f, 0x21, 0 + .dw 0x1040, 0xc13f, 0x107f, 0xc13f, 0x21, 0 + .dw 0x10c0, 0xc13f, 0x10ff, 0xc13f, 0x21, 0 + .dw 0x1140, 0xc13f, 0x117f, 0xc13f, 0x21, 0 + .dw 0x11c0, 0xc13f, 0x11ff, 0xc13f, 0x21, 0 + .dw 0x1240, 0xc13f, 0x127f, 0xc13f, 0x21, 0 + .dw 0x12c0, 0xc13f, 0x12ff, 0xc13f, 0x21, 0 + .dw 0x1340, 0xc13f, 0x137f, 0xc13f, 0x21, 0 + .dw 0x13c0, 0xc13f, 0x13ff, 0xc13f, 0x21, 0 + .dw 0x1440, 0xc13f, 0x147f, 0xc13f, 0x21, 0 + .dw 0x14c0, 0xc13f, 0x14ff, 0xc13f, 0x21, 0 + .dw 0x1540, 0xc13f, 0x157f, 0xc13f, 0x21, 0 + .dw 0x15c0, 0xc13f, 0x15ff, 0xc13f, 0x21, 0 + .dw 0x1640, 0xc13f, 0x167f, 0xc13f, 0x21, 0 + .dw 0x16c0, 0xc13f, 0x16ff, 0xc13f, 0x21, 0 + .dw 0x1740, 0xc13f, 0x177f, 0xc13f, 0x21, 0 + .dw 0x17c0, 0xc13f, 0x17ff, 0xc13f, 0x21, 0 + .dw 0x1840, 0xc13f, 0x187f, 0xc13f, 0x21, 0 + .dw 0x18c0, 0xc13f, 0x18ff, 0xc13f, 0x21, 0 + .dw 0x1940, 0xc13f, 0x197f, 0xc13f, 0x21, 0 + .dw 0x19c0, 0xc13f, 0x1fff, 0xc13f, 0x21, 0 + .dw 0x2040, 0xc13f, 0x207f, 0xc13f, 0x21, 0 + .dw 0x20c0, 0xc13f, 0x20ff, 0xc13f, 0x21, 0 + .dw 0x2140, 0xc13f, 0x217f, 0xc13f, 0x21, 0 + .dw 0x21c0, 0xc13f, 0x21ff, 0xc13f, 0x21, 0 + .dw 0x2240, 0xc13f, 0x227f, 0xc13f, 0x21, 0 + .dw 0x22c0, 0xc13f, 0x22ff, 0xc13f, 0x21, 0 + .dw 0x2340, 0xc13f, 0x237f, 0xc13f, 0x21, 0 + .dw 0x23c0, 0xc13f, 0x23ff, 0xc13f, 0x21, 0 + .dw 0x2440, 0xc13f, 0x247f, 0xc13f, 0x21, 0 + .dw 0x24c0, 0xc13f, 0x24ff, 0xc13f, 0x21, 0 + .dw 0x2540, 0xc13f, 0x257f, 0xc13f, 0x21, 0 + .dw 0x25c0, 0xc13f, 0x25ff, 0xc13f, 0x21, 0 + .dw 0x2640, 0xc13f, 0x267f, 0xc13f, 0x21, 0 + .dw 0x26c0, 0xc13f, 0x26ff, 0xc13f, 0x21, 0 + .dw 0x2740, 0xc13f, 0x277f, 0xc13f, 0x21, 0 + .dw 0x27c0, 0xc13f, 0x27ff, 0xc13f, 0x21, 0 + .dw 0x2840, 0xc13f, 0x287f, 0xc13f, 0x21, 0 + .dw 0x28c0, 0xc13f, 0x28ff, 0xc13f, 0x21, 0 + .dw 0x2940, 0xc13f, 0x297f, 0xc13f, 0x21, 0 + .dw 0x29c0, 0xc13f, 0x29ff, 0xc13f, 0x21, 0 + .dw 0x2a40, 0xc13f, 0x2a7f, 0xc13f, 0x21, 0 + .dw 0x2ac0, 0xc13f, 0x2aff, 0xc13f, 0x21, 0 + .dw 0x2b40, 0xc13f, 0x2b7f, 0xc13f, 0x21, 0 + .dw 0x2bc0, 0xc13f, 0x2bff, 0xc13f, 0x21, 0 + .dw 0x2c40, 0xc13f, 0x2c7f, 0xc13f, 0x21, 0 + .dw 0x2cc0, 0xc13f, 0x2cff, 0xc13f, 0x21, 0 + .dw 0x2d40, 0xc13f, 0x2d7f, 0xc13f, 0x21, 0 + .dw 0x2dc0, 0xc13f, 0x2dff, 0xc13f, 0x21, 0 + .dw 0x2e40, 0xc13f, 0x2e7f, 0xc13f, 0x21, 0 + .dw 0x2ec0, 0xc13f, 0x2eff, 0xc13f, 0x21, 0 + .dw 0x2f40, 0xc13f, 0x2f7f, 0xc13f, 0x21, 0 + .dw 0x2fc0, 0xc13f, 0x2fff, 0xc13f, 0x21, 0 + .dw 0x3040, 0xc13f, 0x307f, 0xc13f, 0x21, 0 + .dw 0x30c0, 0xc13f, 0x30ff, 0xc13f, 0x21, 0 + .dw 0x3140, 0xc13f, 0x317f, 0xc13f, 0x21, 0 + .dw 0x31c0, 0xc13f, 0x31ff, 0xc13f, 0x21, 0 + .dw 0x3240, 0xc13f, 0x327f, 0xc13f, 0x21, 0 + .dw 0x32c0, 0xc13f, 0x32ff, 0xc13f, 0x21, 0 + .dw 0x3340, 0xc13f, 0x337f, 0xc13f, 0x21, 0 + .dw 0x33c0, 0xc13f, 0x33ff, 0xc13f, 0x21, 0 + .dw 0x3440, 0xc13f, 0x347f, 0xc13f, 0x21, 0 + .dw 0x34c0, 0xc13f, 0x34ff, 0xc13f, 0x21, 0 + .dw 0x3540, 0xc13f, 0x357f, 0xc13f, 0x21, 0 + .dw 0x35c0, 0xc13f, 0x35ff, 0xc13f, 0x21, 0 + .dw 0x3640, 0xc13f, 0x367f, 0xc13f, 0x21, 0 + .dw 0x36c0, 0xc13f, 0x36ff, 0xc13f, 0x21, 0 + .dw 0x3740, 0xc13f, 0x377f, 0xc13f, 0x21, 0 + .dw 0x37c0, 0xc13f, 0x37ff, 0xc13f, 0x21, 0 + .dw 0x3840, 0xc13f, 0x387f, 0xc13f, 0x21, 0 + .dw 0x38c0, 0xc13f, 0x38ff, 0xc13f, 0x21, 0 + .dw 0x3940, 0xc13f, 0x397f, 0xc13f, 0x21, 0 + .dw 0x39c0, 0xc13f, 0x1fff, 0xc160, 0x21, 0 + .dw 0x3a00, 0xc160, 0x5fff, 0xc160, 0x21, 0 + .dw 0x7a00, 0xc160, 0x9fff, 0xc160, 0x21, 0 + .dw 0xba00, 0xc160, 0xdfff, 0xc160, 0x21, 0 + .dw 0xfa00, 0xc160, 0x1fff, 0xc161, 0x21, 0 + .dw 0x3a00, 0xc161, 0x5fff, 0xc161, 0x21, 0 + .dw 0x7a00, 0xc161, 0x9fff, 0xc161, 0x21, 0 + .dw 0xba00, 0xc161, 0xdfff, 0xc161, 0x21, 0 + .dw 0xfa00, 0xc161, 0x1fff, 0xc162, 0x21, 0 + .dw 0x3a00, 0xc162, 0x5fff, 0xc162, 0x21, 0 + .dw 0x7a00, 0xc162, 0x9fff, 0xc162, 0x21, 0 + .dw 0xba00, 0xc162, 0xdfff, 0xc162, 0x21, 0 + .dw 0xfa00, 0xc162, 0x1fff, 0xc163, 0x21, 0 + .dw 0x3a00, 0xc163, 0xffff, 0xc163, 0x21, 0 + .dw 0x1a00, 0xc164, 0x1fff, 0xc164, 0x21, 0 + .dw 0x3a00, 0xc164, 0x3fff, 0xc164, 0x21, 0 + .dw 0x5a00, 0xc164, 0x5fff, 0xc164, 0x21, 0 + .dw 0x7a00, 0xc164, 0x7fff, 0xc164, 0x21, 0 + .dw 0x9a00, 0xc164, 0x9fff, 0xc164, 0x21, 0 + .dw 0xba00, 0xc164, 0xbfff, 0xc164, 0x21, 0 + .dw 0xda00, 0xc164, 0xdfff, 0xc164, 0x21, 0 + .dw 0xfa00, 0xc164, 0xffff, 0xc164, 0x21, 0 + .dw 0x1a00, 0xc165, 0x1fff, 0xc165, 0x21, 0 + .dw 0x3a00, 0xc165, 0x3fff, 0xc165, 0x21, 0 + .dw 0x5a00, 0xc165, 0x5fff, 0xc165, 0x21, 0 + .dw 0x7a00, 0xc165, 0x7fff, 0xc165, 0x21, 0 + .dw 0x9a00, 0xc165, 0x9fff, 0xc165, 0x21, 0 + .dw 0xba00, 0xc165, 0xbfff, 0xc165, 0x21, 0 + .dw 0xda00, 0xc165, 0xdfff, 0xc165, 0x21, 0 + .dw 0xfa00, 0xc165, 0xffff, 0xc165, 0x21, 0 + .dw 0x1a00, 0xc166, 0x1fff, 0xc166, 0x21, 0 + .dw 0x3a00, 0xc166, 0x3fff, 0xc166, 0x21, 0 + .dw 0x5a00, 0xc166, 0x5fff, 0xc166, 0x21, 0 + .dw 0x7a00, 0xc166, 0x7fff, 0xc166, 0x21, 0 + .dw 0x9a00, 0xc166, 0x9fff, 0xc166, 0x21, 0 + .dw 0xba00, 0xc166, 0xbfff, 0xc166, 0x21, 0 + .dw 0xda00, 0xc166, 0xdfff, 0xc166, 0x21, 0 + .dw 0xfa00, 0xc166, 0xffff, 0xc166, 0x21, 0 + .dw 0x1a00, 0xc167, 0x1fff, 0xc167, 0x21, 0 + .dw 0x3a00, 0xc167, 0x1fff, 0xc170, 0x21, 0 + .dw 0x3a00, 0xc170, 0x5fff, 0xc170, 0x21, 0 + .dw 0x7a00, 0xc170, 0x9fff, 0xc170, 0x21, 0 + .dw 0xba00, 0xc170, 0xdfff, 0xc170, 0x21, 0 + .dw 0xfa00, 0xc170, 0x1fff, 0xc171, 0x21, 0 + .dw 0x3a00, 0xc171, 0x5fff, 0xc171, 0x21, 0 + .dw 0x7a00, 0xc171, 0x9fff, 0xc171, 0x21, 0 + .dw 0xba00, 0xc171, 0xdfff, 0xc171, 0x21, 0 + .dw 0xfa00, 0xc171, 0x1fff, 0xc172, 0x21, 0 + .dw 0x3a00, 0xc172, 0x5fff, 0xc172, 0x21, 0 + .dw 0x7a00, 0xc172, 0x9fff, 0xc172, 0x21, 0 + .dw 0xba00, 0xc172, 0xdfff, 0xc172, 0x21, 0 + .dw 0xfa00, 0xc172, 0xffff, 0xc173, 0x21, 0 + .dw 0x1a00, 0xc174, 0x1fff, 0xc174, 0x21, 0 + .dw 0x3a00, 0xc174, 0x3fff, 0xc174, 0x21, 0 + .dw 0x5a00, 0xc174, 0x5fff, 0xc174, 0x21, 0 + .dw 0x7a00, 0xc174, 0x7fff, 0xc174, 0x21, 0 + .dw 0x9a00, 0xc174, 0x9fff, 0xc174, 0x21, 0 + .dw 0xba00, 0xc174, 0xbfff, 0xc174, 0x21, 0 + .dw 0xda00, 0xc174, 0xdfff, 0xc174, 0x21, 0 + .dw 0xfa00, 0xc174, 0xffff, 0xc174, 0x21, 0 + .dw 0x1a00, 0xc175, 0x1fff, 0xc175, 0x21, 0 + .dw 0x3a00, 0xc175, 0x3fff, 0xc175, 0x21, 0 + .dw 0x5a00, 0xc175, 0x5fff, 0xc175, 0x21, 0 + .dw 0x7a00, 0xc175, 0x7fff, 0xc175, 0x21, 0 + .dw 0x9a00, 0xc175, 0x9fff, 0xc175, 0x21, 0 + .dw 0xba00, 0xc175, 0xbfff, 0xc175, 0x21, 0 + .dw 0xda00, 0xc175, 0xdfff, 0xc175, 0x21, 0 + .dw 0xfa00, 0xc175, 0xffff, 0xc175, 0x21, 0 + .dw 0x1a00, 0xc176, 0x1fff, 0xc176, 0x21, 0 + .dw 0x3a00, 0xc176, 0x3fff, 0xc176, 0x21, 0 + .dw 0x5a00, 0xc176, 0x5fff, 0xc176, 0x21, 0 + .dw 0x7a00, 0xc176, 0x7fff, 0xc176, 0x21, 0 + .dw 0x9a00, 0xc176, 0x9fff, 0xc176, 0x21, 0 + .dw 0xba00, 0xc176, 0xbfff, 0xc176, 0x21, 0 + .dw 0xda00, 0xc176, 0xdfff, 0xc176, 0x21, 0 + .dw 0xfa00, 0xc176, 0xffff, 0xc176, 0x21, 0 + .dw 0x1a00, 0xc177, 0x1fff, 0xc177, 0x21, 0 + .dw 0x3a00, 0xc177, 0x1fff, 0xc180, 0x21, 0 + .dw 0x3a00, 0xc180, 0x5fff, 0xc180, 0x21, 0 + .dw 0x7a00, 0xc180, 0x9fff, 0xc180, 0x21, 0 + .dw 0xba00, 0xc180, 0xdfff, 0xc180, 0x21, 0 + .dw 0xfa00, 0xc180, 0x1fff, 0xc181, 0x21, 0 + .dw 0x3a00, 0xc181, 0x5fff, 0xc181, 0x21, 0 + .dw 0x7a00, 0xc181, 0x9fff, 0xc181, 0x21, 0 + .dw 0xba00, 0xc181, 0xdfff, 0xc181, 0x21, 0 + .dw 0xfa00, 0xc181, 0x1fff, 0xc182, 0x21, 0 + .dw 0x3a00, 0xc182, 0x5fff, 0xc182, 0x21, 0 + .dw 0x7a00, 0xc182, 0x9fff, 0xc182, 0x21, 0 + .dw 0xba00, 0xc182, 0xdfff, 0xc182, 0x21, 0 + .dw 0xfa00, 0xc182, 0x1fff, 0xc183, 0x21, 0 + .dw 0x3a00, 0xc183, 0xffff, 0xc183, 0x21, 0 + .dw 0x1a00, 0xc184, 0x1fff, 0xc184, 0x21, 0 + .dw 0x3a00, 0xc184, 0x3fff, 0xc184, 0x21, 0 + .dw 0x5a00, 0xc184, 0x5fff, 0xc184, 0x21, 0 + .dw 0x7a00, 0xc184, 0x7fff, 0xc184, 0x21, 0 + .dw 0x9a00, 0xc184, 0x9fff, 0xc184, 0x21, 0 + .dw 0xba00, 0xc184, 0xbfff, 0xc184, 0x21, 0 + .dw 0xda00, 0xc184, 0xdfff, 0xc184, 0x21, 0 + .dw 0xfa00, 0xc184, 0xffff, 0xc184, 0x21, 0 + .dw 0x1a00, 0xc185, 0x1fff, 0xc185, 0x21, 0 + .dw 0x3a00, 0xc185, 0x3fff, 0xc185, 0x21, 0 + .dw 0x5a00, 0xc185, 0x5fff, 0xc185, 0x21, 0 + .dw 0x7a00, 0xc185, 0x7fff, 0xc185, 0x21, 0 + .dw 0x9a00, 0xc185, 0x9fff, 0xc185, 0x21, 0 + .dw 0xba00, 0xc185, 0xbfff, 0xc185, 0x21, 0 + .dw 0xda00, 0xc185, 0xdfff, 0xc185, 0x21, 0 + .dw 0xfa00, 0xc185, 0xffff, 0xc185, 0x21, 0 + .dw 0x1a00, 0xc186, 0x1fff, 0xc186, 0x21, 0 + .dw 0x3a00, 0xc186, 0x3fff, 0xc186, 0x21, 0 + .dw 0x5a00, 0xc186, 0x5fff, 0xc186, 0x21, 0 + .dw 0x7a00, 0xc186, 0x7fff, 0xc186, 0x21, 0 + .dw 0x9a00, 0xc186, 0x9fff, 0xc186, 0x21, 0 + .dw 0xba00, 0xc186, 0xbfff, 0xc186, 0x21, 0 + .dw 0xda00, 0xc186, 0xdfff, 0xc186, 0x21, 0 + .dw 0xfa00, 0xc186, 0xffff, 0xc186, 0x21, 0 + .dw 0x1a00, 0xc187, 0x1fff, 0xc187, 0x21, 0 + .dw 0x3a00, 0xc187, 0x1fff, 0xc188, 0x21, 0 + .dw 0x2040, 0xc188, 0x207f, 0xc188, 0x21, 0 + .dw 0x20c0, 0xc188, 0x20ff, 0xc188, 0x21, 0 + .dw 0x2140, 0xc188, 0x217f, 0xc188, 0x21, 0 + .dw 0x21c0, 0xc188, 0x21ff, 0xc188, 0x21, 0 + .dw 0x2240, 0xc188, 0x227f, 0xc188, 0x21, 0 + .dw 0x22c0, 0xc188, 0x22ff, 0xc188, 0x21, 0 + .dw 0x2340, 0xc188, 0x237f, 0xc188, 0x21, 0 + .dw 0x23c0, 0xc188, 0x23ff, 0xc188, 0x21, 0 + .dw 0x2440, 0xc188, 0x247f, 0xc188, 0x21, 0 + .dw 0x24c0, 0xc188, 0x24ff, 0xc188, 0x21, 0 + .dw 0x2540, 0xc188, 0x257f, 0xc188, 0x21, 0 + .dw 0x25c0, 0xc188, 0x25ff, 0xc188, 0x21, 0 + .dw 0x2640, 0xc188, 0x267f, 0xc188, 0x21, 0 + .dw 0x26c0, 0xc188, 0x26ff, 0xc188, 0x21, 0 + .dw 0x2740, 0xc188, 0x277f, 0xc188, 0x21, 0 + .dw 0x27c0, 0xc188, 0x27ff, 0xc188, 0x21, 0 + .dw 0x2840, 0xc188, 0x287f, 0xc188, 0x21, 0 + .dw 0x28c0, 0xc188, 0x28ff, 0xc188, 0x21, 0 + .dw 0x2940, 0xc188, 0x297f, 0xc188, 0x21, 0 + .dw 0x29c0, 0xc188, 0x29ff, 0xc188, 0x21, 0 + .dw 0x2a40, 0xc188, 0x2a7f, 0xc188, 0x21, 0 + .dw 0x2ac0, 0xc188, 0x2aff, 0xc188, 0x21, 0 + .dw 0x2b40, 0xc188, 0x2b7f, 0xc188, 0x21, 0 + .dw 0x2bc0, 0xc188, 0x2bff, 0xc188, 0x21, 0 + .dw 0x2c40, 0xc188, 0x2c7f, 0xc188, 0x21, 0 + .dw 0x2cc0, 0xc188, 0x2cff, 0xc188, 0x21, 0 + .dw 0x2d40, 0xc188, 0x2d7f, 0xc188, 0x21, 0 + .dw 0x2dc0, 0xc188, 0x2dff, 0xc188, 0x21, 0 + .dw 0x2e40, 0xc188, 0x2e7f, 0xc188, 0x21, 0 + .dw 0x2ec0, 0xc188, 0x2eff, 0xc188, 0x21, 0 + .dw 0x2f40, 0xc188, 0x2f7f, 0xc188, 0x21, 0 + .dw 0x2fc0, 0xc188, 0x2fff, 0xc188, 0x21, 0 + .dw 0x3040, 0xc188, 0x307f, 0xc188, 0x21, 0 + .dw 0x30c0, 0xc188, 0x30ff, 0xc188, 0x21, 0 + .dw 0x3140, 0xc188, 0x317f, 0xc188, 0x21, 0 + .dw 0x31c0, 0xc188, 0x31ff, 0xc188, 0x21, 0 + .dw 0x3240, 0xc188, 0x327f, 0xc188, 0x21, 0 + .dw 0x32c0, 0xc188, 0x32ff, 0xc188, 0x21, 0 + .dw 0x3340, 0xc188, 0x337f, 0xc188, 0x21, 0 + .dw 0x33c0, 0xc188, 0x33ff, 0xc188, 0x21, 0 + .dw 0x3440, 0xc188, 0x347f, 0xc188, 0x21, 0 + .dw 0x34c0, 0xc188, 0x34ff, 0xc188, 0x21, 0 + .dw 0x3540, 0xc188, 0x357f, 0xc188, 0x21, 0 + .dw 0x35c0, 0xc188, 0x35ff, 0xc188, 0x21, 0 + .dw 0x3640, 0xc188, 0x367f, 0xc188, 0x21, 0 + .dw 0x36c0, 0xc188, 0x36ff, 0xc188, 0x21, 0 + .dw 0x3740, 0xc188, 0x377f, 0xc188, 0x21, 0 + .dw 0x37c0, 0xc188, 0x37ff, 0xc188, 0x21, 0 + .dw 0x3840, 0xc188, 0x387f, 0xc188, 0x21, 0 + .dw 0x38c0, 0xc188, 0x38ff, 0xc188, 0x21, 0 + .dw 0x3940, 0xc188, 0x397f, 0xc188, 0x21, 0 + .dw 0x39c0, 0xc188, 0x5fff, 0xc188, 0x21, 0 + .dw 0x6040, 0xc188, 0x607f, 0xc188, 0x21, 0 + .dw 0x60c0, 0xc188, 0x60ff, 0xc188, 0x21, 0 + .dw 0x6140, 0xc188, 0x617f, 0xc188, 0x21, 0 + .dw 0x61c0, 0xc188, 0x61ff, 0xc188, 0x21, 0 + .dw 0x6240, 0xc188, 0x627f, 0xc188, 0x21, 0 + .dw 0x62c0, 0xc188, 0x62ff, 0xc188, 0x21, 0 + .dw 0x6340, 0xc188, 0x637f, 0xc188, 0x21, 0 + .dw 0x63c0, 0xc188, 0x63ff, 0xc188, 0x21, 0 + .dw 0x6440, 0xc188, 0x647f, 0xc188, 0x21, 0 + .dw 0x64c0, 0xc188, 0x64ff, 0xc188, 0x21, 0 + .dw 0x6540, 0xc188, 0x657f, 0xc188, 0x21, 0 + .dw 0x65c0, 0xc188, 0x65ff, 0xc188, 0x21, 0 + .dw 0x6640, 0xc188, 0x667f, 0xc188, 0x21, 0 + .dw 0x66c0, 0xc188, 0x66ff, 0xc188, 0x21, 0 + .dw 0x6740, 0xc188, 0x677f, 0xc188, 0x21, 0 + .dw 0x67c0, 0xc188, 0x67ff, 0xc188, 0x21, 0 + .dw 0x6840, 0xc188, 0x687f, 0xc188, 0x21, 0 + .dw 0x68c0, 0xc188, 0x68ff, 0xc188, 0x21, 0 + .dw 0x6940, 0xc188, 0x697f, 0xc188, 0x21, 0 + .dw 0x69c0, 0xc188, 0x69ff, 0xc188, 0x21, 0 + .dw 0x6a40, 0xc188, 0x6a7f, 0xc188, 0x21, 0 + .dw 0x6ac0, 0xc188, 0x6aff, 0xc188, 0x21, 0 + .dw 0x6b40, 0xc188, 0x6b7f, 0xc188, 0x21, 0 + .dw 0x6bc0, 0xc188, 0x6bff, 0xc188, 0x21, 0 + .dw 0x6c40, 0xc188, 0x6c7f, 0xc188, 0x21, 0 + .dw 0x6cc0, 0xc188, 0x6cff, 0xc188, 0x21, 0 + .dw 0x6d40, 0xc188, 0x6d7f, 0xc188, 0x21, 0 + .dw 0x6dc0, 0xc188, 0x6dff, 0xc188, 0x21, 0 + .dw 0x6e40, 0xc188, 0x6e7f, 0xc188, 0x21, 0 + .dw 0x6ec0, 0xc188, 0x6eff, 0xc188, 0x21, 0 + .dw 0x6f40, 0xc188, 0x6f7f, 0xc188, 0x21, 0 + .dw 0x6fc0, 0xc188, 0x6fff, 0xc188, 0x21, 0 + .dw 0x7040, 0xc188, 0x707f, 0xc188, 0x21, 0 + .dw 0x70c0, 0xc188, 0x70ff, 0xc188, 0x21, 0 + .dw 0x7140, 0xc188, 0x717f, 0xc188, 0x21, 0 + .dw 0x71c0, 0xc188, 0x71ff, 0xc188, 0x21, 0 + .dw 0x7240, 0xc188, 0x727f, 0xc188, 0x21, 0 + .dw 0x72c0, 0xc188, 0x72ff, 0xc188, 0x21, 0 + .dw 0x7340, 0xc188, 0x737f, 0xc188, 0x21, 0 + .dw 0x73c0, 0xc188, 0x73ff, 0xc188, 0x21, 0 + .dw 0x7440, 0xc188, 0x747f, 0xc188, 0x21, 0 + .dw 0x74c0, 0xc188, 0x74ff, 0xc188, 0x21, 0 + .dw 0x7540, 0xc188, 0x757f, 0xc188, 0x21, 0 + .dw 0x75c0, 0xc188, 0x75ff, 0xc188, 0x21, 0 + .dw 0x7640, 0xc188, 0x767f, 0xc188, 0x21, 0 + .dw 0x76c0, 0xc188, 0x76ff, 0xc188, 0x21, 0 + .dw 0x7740, 0xc188, 0x777f, 0xc188, 0x21, 0 + .dw 0x77c0, 0xc188, 0x77ff, 0xc188, 0x21, 0 + .dw 0x7840, 0xc188, 0x787f, 0xc188, 0x21, 0 + .dw 0x78c0, 0xc188, 0x78ff, 0xc188, 0x21, 0 + .dw 0x7940, 0xc188, 0x797f, 0xc188, 0x21, 0 + .dw 0x79c0, 0xc188, 0x9fff, 0xc188, 0x21, 0 + .dw 0xa040, 0xc188, 0xa07f, 0xc188, 0x21, 0 + .dw 0xa0c0, 0xc188, 0xa0ff, 0xc188, 0x21, 0 + .dw 0xa140, 0xc188, 0xa17f, 0xc188, 0x21, 0 + .dw 0xa1c0, 0xc188, 0xa1ff, 0xc188, 0x21, 0 + .dw 0xa240, 0xc188, 0xa27f, 0xc188, 0x21, 0 + .dw 0xa2c0, 0xc188, 0xa2ff, 0xc188, 0x21, 0 + .dw 0xa340, 0xc188, 0xa37f, 0xc188, 0x21, 0 + .dw 0xa3c0, 0xc188, 0xa3ff, 0xc188, 0x21, 0 + .dw 0xa440, 0xc188, 0xa47f, 0xc188, 0x21, 0 + .dw 0xa4c0, 0xc188, 0xa4ff, 0xc188, 0x21, 0 + .dw 0xa540, 0xc188, 0xa57f, 0xc188, 0x21, 0 + .dw 0xa5c0, 0xc188, 0xa5ff, 0xc188, 0x21, 0 + .dw 0xa640, 0xc188, 0xa67f, 0xc188, 0x21, 0 + .dw 0xa6c0, 0xc188, 0xa6ff, 0xc188, 0x21, 0 + .dw 0xa740, 0xc188, 0xa77f, 0xc188, 0x21, 0 + .dw 0xa7c0, 0xc188, 0xa7ff, 0xc188, 0x21, 0 + .dw 0xa840, 0xc188, 0xa87f, 0xc188, 0x21, 0 + .dw 0xa8c0, 0xc188, 0xa8ff, 0xc188, 0x21, 0 + .dw 0xa940, 0xc188, 0xa97f, 0xc188, 0x21, 0 + .dw 0xa9c0, 0xc188, 0xa9ff, 0xc188, 0x21, 0 + .dw 0xaa40, 0xc188, 0xaa7f, 0xc188, 0x21, 0 + .dw 0xaac0, 0xc188, 0xaaff, 0xc188, 0x21, 0 + .dw 0xab40, 0xc188, 0xab7f, 0xc188, 0x21, 0 + .dw 0xabc0, 0xc188, 0xabff, 0xc188, 0x21, 0 + .dw 0xac40, 0xc188, 0xac7f, 0xc188, 0x21, 0 + .dw 0xacc0, 0xc188, 0xacff, 0xc188, 0x21, 0 + .dw 0xad40, 0xc188, 0xad7f, 0xc188, 0x21, 0 + .dw 0xadc0, 0xc188, 0xadff, 0xc188, 0x21, 0 + .dw 0xae40, 0xc188, 0xae7f, 0xc188, 0x21, 0 + .dw 0xaec0, 0xc188, 0xaeff, 0xc188, 0x21, 0 + .dw 0xaf40, 0xc188, 0xaf7f, 0xc188, 0x21, 0 + .dw 0xafc0, 0xc188, 0xafff, 0xc188, 0x21, 0 + .dw 0xb040, 0xc188, 0xb07f, 0xc188, 0x21, 0 + .dw 0xb0c0, 0xc188, 0xb0ff, 0xc188, 0x21, 0 + .dw 0xb140, 0xc188, 0xb17f, 0xc188, 0x21, 0 + .dw 0xb1c0, 0xc188, 0xb1ff, 0xc188, 0x21, 0 + .dw 0xb240, 0xc188, 0xb27f, 0xc188, 0x21, 0 + .dw 0xb2c0, 0xc188, 0xb2ff, 0xc188, 0x21, 0 + .dw 0xb340, 0xc188, 0xb37f, 0xc188, 0x21, 0 + .dw 0xb3c0, 0xc188, 0xb3ff, 0xc188, 0x21, 0 + .dw 0xb440, 0xc188, 0xb47f, 0xc188, 0x21, 0 + .dw 0xb4c0, 0xc188, 0xb4ff, 0xc188, 0x21, 0 + .dw 0xb540, 0xc188, 0xb57f, 0xc188, 0x21, 0 + .dw 0xb5c0, 0xc188, 0xb5ff, 0xc188, 0x21, 0 + .dw 0xb640, 0xc188, 0xb67f, 0xc188, 0x21, 0 + .dw 0xb6c0, 0xc188, 0xb6ff, 0xc188, 0x21, 0 + .dw 0xb740, 0xc188, 0xb77f, 0xc188, 0x21, 0 + .dw 0xb7c0, 0xc188, 0xb7ff, 0xc188, 0x21, 0 + .dw 0xb840, 0xc188, 0xb87f, 0xc188, 0x21, 0 + .dw 0xb8c0, 0xc188, 0xb8ff, 0xc188, 0x21, 0 + .dw 0xb940, 0xc188, 0xb97f, 0xc188, 0x21, 0 + .dw 0xb9c0, 0xc188, 0xdfff, 0xc188, 0x21, 0 + .dw 0xe040, 0xc188, 0xe07f, 0xc188, 0x21, 0 + .dw 0xe0c0, 0xc188, 0xe0ff, 0xc188, 0x21, 0 + .dw 0xe140, 0xc188, 0xe17f, 0xc188, 0x21, 0 + .dw 0xe1c0, 0xc188, 0xe1ff, 0xc188, 0x21, 0 + .dw 0xe240, 0xc188, 0xe27f, 0xc188, 0x21, 0 + .dw 0xe2c0, 0xc188, 0xe2ff, 0xc188, 0x21, 0 + .dw 0xe340, 0xc188, 0xe37f, 0xc188, 0x21, 0 + .dw 0xe3c0, 0xc188, 0xe3ff, 0xc188, 0x21, 0 + .dw 0xe440, 0xc188, 0xe47f, 0xc188, 0x21, 0 + .dw 0xe4c0, 0xc188, 0xe4ff, 0xc188, 0x21, 0 + .dw 0xe540, 0xc188, 0xe57f, 0xc188, 0x21, 0 + .dw 0xe5c0, 0xc188, 0xe5ff, 0xc188, 0x21, 0 + .dw 0xe640, 0xc188, 0xe67f, 0xc188, 0x21, 0 + .dw 0xe6c0, 0xc188, 0xe6ff, 0xc188, 0x21, 0 + .dw 0xe740, 0xc188, 0xe77f, 0xc188, 0x21, 0 + .dw 0xe7c0, 0xc188, 0xe7ff, 0xc188, 0x21, 0 + .dw 0xe840, 0xc188, 0xe87f, 0xc188, 0x21, 0 + .dw 0xe8c0, 0xc188, 0xe8ff, 0xc188, 0x21, 0 + .dw 0xe940, 0xc188, 0xe97f, 0xc188, 0x21, 0 + .dw 0xe9c0, 0xc188, 0xe9ff, 0xc188, 0x21, 0 + .dw 0xea40, 0xc188, 0xea7f, 0xc188, 0x21, 0 + .dw 0xeac0, 0xc188, 0xeaff, 0xc188, 0x21, 0 + .dw 0xeb40, 0xc188, 0xeb7f, 0xc188, 0x21, 0 + .dw 0xebc0, 0xc188, 0xebff, 0xc188, 0x21, 0 + .dw 0xec40, 0xc188, 0xec7f, 0xc188, 0x21, 0 + .dw 0xecc0, 0xc188, 0xecff, 0xc188, 0x21, 0 + .dw 0xed40, 0xc188, 0xed7f, 0xc188, 0x21, 0 + .dw 0xedc0, 0xc188, 0xedff, 0xc188, 0x21, 0 + .dw 0xee40, 0xc188, 0xee7f, 0xc188, 0x21, 0 + .dw 0xeec0, 0xc188, 0xeeff, 0xc188, 0x21, 0 + .dw 0xef40, 0xc188, 0xef7f, 0xc188, 0x21, 0 + .dw 0xefc0, 0xc188, 0xefff, 0xc188, 0x21, 0 + .dw 0xf040, 0xc188, 0xf07f, 0xc188, 0x21, 0 + .dw 0xf0c0, 0xc188, 0xf0ff, 0xc188, 0x21, 0 + .dw 0xf140, 0xc188, 0xf17f, 0xc188, 0x21, 0 + .dw 0xf1c0, 0xc188, 0xf1ff, 0xc188, 0x21, 0 + .dw 0xf240, 0xc188, 0xf27f, 0xc188, 0x21, 0 + .dw 0xf2c0, 0xc188, 0xf2ff, 0xc188, 0x21, 0 + .dw 0xf340, 0xc188, 0xf37f, 0xc188, 0x21, 0 + .dw 0xf3c0, 0xc188, 0xf3ff, 0xc188, 0x21, 0 + .dw 0xf440, 0xc188, 0xf47f, 0xc188, 0x21, 0 + .dw 0xf4c0, 0xc188, 0xf4ff, 0xc188, 0x21, 0 + .dw 0xf540, 0xc188, 0xf57f, 0xc188, 0x21, 0 + .dw 0xf5c0, 0xc188, 0xf5ff, 0xc188, 0x21, 0 + .dw 0xf640, 0xc188, 0xf67f, 0xc188, 0x21, 0 + .dw 0xf6c0, 0xc188, 0xf6ff, 0xc188, 0x21, 0 + .dw 0xf740, 0xc188, 0xf77f, 0xc188, 0x21, 0 + .dw 0xf7c0, 0xc188, 0xf7ff, 0xc188, 0x21, 0 + .dw 0xf840, 0xc188, 0xf87f, 0xc188, 0x21, 0 + .dw 0xf8c0, 0xc188, 0xf8ff, 0xc188, 0x21, 0 + .dw 0xf940, 0xc188, 0xf97f, 0xc188, 0x21, 0 + .dw 0xf9c0, 0xc188, 0x1fff, 0xc189, 0x21, 0 + .dw 0x2040, 0xc189, 0x207f, 0xc189, 0x21, 0 + .dw 0x20c0, 0xc189, 0x20ff, 0xc189, 0x21, 0 + .dw 0x2140, 0xc189, 0x217f, 0xc189, 0x21, 0 + .dw 0x21c0, 0xc189, 0x21ff, 0xc189, 0x21, 0 + .dw 0x2240, 0xc189, 0x227f, 0xc189, 0x21, 0 + .dw 0x22c0, 0xc189, 0x22ff, 0xc189, 0x21, 0 + .dw 0x2340, 0xc189, 0x237f, 0xc189, 0x21, 0 + .dw 0x23c0, 0xc189, 0x23ff, 0xc189, 0x21, 0 + .dw 0x2440, 0xc189, 0x247f, 0xc189, 0x21, 0 + .dw 0x24c0, 0xc189, 0x24ff, 0xc189, 0x21, 0 + .dw 0x2540, 0xc189, 0x257f, 0xc189, 0x21, 0 + .dw 0x25c0, 0xc189, 0x25ff, 0xc189, 0x21, 0 + .dw 0x2640, 0xc189, 0x267f, 0xc189, 0x21, 0 + .dw 0x26c0, 0xc189, 0x26ff, 0xc189, 0x21, 0 + .dw 0x2740, 0xc189, 0x277f, 0xc189, 0x21, 0 + .dw 0x27c0, 0xc189, 0x27ff, 0xc189, 0x21, 0 + .dw 0x2840, 0xc189, 0x287f, 0xc189, 0x21, 0 + .dw 0x28c0, 0xc189, 0x28ff, 0xc189, 0x21, 0 + .dw 0x2940, 0xc189, 0x297f, 0xc189, 0x21, 0 + .dw 0x29c0, 0xc189, 0x29ff, 0xc189, 0x21, 0 + .dw 0x2a40, 0xc189, 0x2a7f, 0xc189, 0x21, 0 + .dw 0x2ac0, 0xc189, 0x2aff, 0xc189, 0x21, 0 + .dw 0x2b40, 0xc189, 0x2b7f, 0xc189, 0x21, 0 + .dw 0x2bc0, 0xc189, 0x2bff, 0xc189, 0x21, 0 + .dw 0x2c40, 0xc189, 0x2c7f, 0xc189, 0x21, 0 + .dw 0x2cc0, 0xc189, 0x2cff, 0xc189, 0x21, 0 + .dw 0x2d40, 0xc189, 0x2d7f, 0xc189, 0x21, 0 + .dw 0x2dc0, 0xc189, 0x2dff, 0xc189, 0x21, 0 + .dw 0x2e40, 0xc189, 0x2e7f, 0xc189, 0x21, 0 + .dw 0x2ec0, 0xc189, 0x2eff, 0xc189, 0x21, 0 + .dw 0x2f40, 0xc189, 0x2f7f, 0xc189, 0x21, 0 + .dw 0x2fc0, 0xc189, 0x2fff, 0xc189, 0x21, 0 + .dw 0x3040, 0xc189, 0x307f, 0xc189, 0x21, 0 + .dw 0x30c0, 0xc189, 0x30ff, 0xc189, 0x21, 0 + .dw 0x3140, 0xc189, 0x317f, 0xc189, 0x21, 0 + .dw 0x31c0, 0xc189, 0x31ff, 0xc189, 0x21, 0 + .dw 0x3240, 0xc189, 0x327f, 0xc189, 0x21, 0 + .dw 0x32c0, 0xc189, 0x32ff, 0xc189, 0x21, 0 + .dw 0x3340, 0xc189, 0x337f, 0xc189, 0x21, 0 + .dw 0x33c0, 0xc189, 0x33ff, 0xc189, 0x21, 0 + .dw 0x3440, 0xc189, 0x347f, 0xc189, 0x21, 0 + .dw 0x34c0, 0xc189, 0x34ff, 0xc189, 0x21, 0 + .dw 0x3540, 0xc189, 0x357f, 0xc189, 0x21, 0 + .dw 0x35c0, 0xc189, 0x35ff, 0xc189, 0x21, 0 + .dw 0x3640, 0xc189, 0x367f, 0xc189, 0x21, 0 + .dw 0x36c0, 0xc189, 0x36ff, 0xc189, 0x21, 0 + .dw 0x3740, 0xc189, 0x377f, 0xc189, 0x21, 0 + .dw 0x37c0, 0xc189, 0x37ff, 0xc189, 0x21, 0 + .dw 0x3840, 0xc189, 0x387f, 0xc189, 0x21, 0 + .dw 0x38c0, 0xc189, 0x38ff, 0xc189, 0x21, 0 + .dw 0x3940, 0xc189, 0x397f, 0xc189, 0x21, 0 + .dw 0x39c0, 0xc189, 0x5fff, 0xc189, 0x21, 0 + .dw 0x6040, 0xc189, 0x607f, 0xc189, 0x21, 0 + .dw 0x60c0, 0xc189, 0x60ff, 0xc189, 0x21, 0 + .dw 0x6140, 0xc189, 0x617f, 0xc189, 0x21, 0 + .dw 0x61c0, 0xc189, 0x61ff, 0xc189, 0x21, 0 + .dw 0x6240, 0xc189, 0x627f, 0xc189, 0x21, 0 + .dw 0x62c0, 0xc189, 0x62ff, 0xc189, 0x21, 0 + .dw 0x6340, 0xc189, 0x637f, 0xc189, 0x21, 0 + .dw 0x63c0, 0xc189, 0x63ff, 0xc189, 0x21, 0 + .dw 0x6440, 0xc189, 0x647f, 0xc189, 0x21, 0 + .dw 0x64c0, 0xc189, 0x64ff, 0xc189, 0x21, 0 + .dw 0x6540, 0xc189, 0x657f, 0xc189, 0x21, 0 + .dw 0x65c0, 0xc189, 0x65ff, 0xc189, 0x21, 0 + .dw 0x6640, 0xc189, 0x667f, 0xc189, 0x21, 0 + .dw 0x66c0, 0xc189, 0x66ff, 0xc189, 0x21, 0 + .dw 0x6740, 0xc189, 0x677f, 0xc189, 0x21, 0 + .dw 0x67c0, 0xc189, 0x67ff, 0xc189, 0x21, 0 + .dw 0x6840, 0xc189, 0x687f, 0xc189, 0x21, 0 + .dw 0x68c0, 0xc189, 0x68ff, 0xc189, 0x21, 0 + .dw 0x6940, 0xc189, 0x697f, 0xc189, 0x21, 0 + .dw 0x69c0, 0xc189, 0x69ff, 0xc189, 0x21, 0 + .dw 0x6a40, 0xc189, 0x6a7f, 0xc189, 0x21, 0 + .dw 0x6ac0, 0xc189, 0x6aff, 0xc189, 0x21, 0 + .dw 0x6b40, 0xc189, 0x6b7f, 0xc189, 0x21, 0 + .dw 0x6bc0, 0xc189, 0x6bff, 0xc189, 0x21, 0 + .dw 0x6c40, 0xc189, 0x6c7f, 0xc189, 0x21, 0 + .dw 0x6cc0, 0xc189, 0x6cff, 0xc189, 0x21, 0 + .dw 0x6d40, 0xc189, 0x6d7f, 0xc189, 0x21, 0 + .dw 0x6dc0, 0xc189, 0x6dff, 0xc189, 0x21, 0 + .dw 0x6e40, 0xc189, 0x6e7f, 0xc189, 0x21, 0 + .dw 0x6ec0, 0xc189, 0x6eff, 0xc189, 0x21, 0 + .dw 0x6f40, 0xc189, 0x6f7f, 0xc189, 0x21, 0 + .dw 0x6fc0, 0xc189, 0x6fff, 0xc189, 0x21, 0 + .dw 0x7040, 0xc189, 0x707f, 0xc189, 0x21, 0 + .dw 0x70c0, 0xc189, 0x70ff, 0xc189, 0x21, 0 + .dw 0x7140, 0xc189, 0x717f, 0xc189, 0x21, 0 + .dw 0x71c0, 0xc189, 0x71ff, 0xc189, 0x21, 0 + .dw 0x7240, 0xc189, 0x727f, 0xc189, 0x21, 0 + .dw 0x72c0, 0xc189, 0x72ff, 0xc189, 0x21, 0 + .dw 0x7340, 0xc189, 0x737f, 0xc189, 0x21, 0 + .dw 0x73c0, 0xc189, 0x73ff, 0xc189, 0x21, 0 + .dw 0x7440, 0xc189, 0x747f, 0xc189, 0x21, 0 + .dw 0x74c0, 0xc189, 0x74ff, 0xc189, 0x21, 0 + .dw 0x7540, 0xc189, 0x757f, 0xc189, 0x21, 0 + .dw 0x75c0, 0xc189, 0x75ff, 0xc189, 0x21, 0 + .dw 0x7640, 0xc189, 0x767f, 0xc189, 0x21, 0 + .dw 0x76c0, 0xc189, 0x76ff, 0xc189, 0x21, 0 + .dw 0x7740, 0xc189, 0x777f, 0xc189, 0x21, 0 + .dw 0x77c0, 0xc189, 0x77ff, 0xc189, 0x21, 0 + .dw 0x7840, 0xc189, 0x787f, 0xc189, 0x21, 0 + .dw 0x78c0, 0xc189, 0x78ff, 0xc189, 0x21, 0 + .dw 0x7940, 0xc189, 0x797f, 0xc189, 0x21, 0 + .dw 0x79c0, 0xc189, 0x9fff, 0xc189, 0x21, 0 + .dw 0xa040, 0xc189, 0xa07f, 0xc189, 0x21, 0 + .dw 0xa0c0, 0xc189, 0xa0ff, 0xc189, 0x21, 0 + .dw 0xa140, 0xc189, 0xa17f, 0xc189, 0x21, 0 + .dw 0xa1c0, 0xc189, 0xa1ff, 0xc189, 0x21, 0 + .dw 0xa240, 0xc189, 0xa27f, 0xc189, 0x21, 0 + .dw 0xa2c0, 0xc189, 0xa2ff, 0xc189, 0x21, 0 + .dw 0xa340, 0xc189, 0xa37f, 0xc189, 0x21, 0 + .dw 0xa3c0, 0xc189, 0xa3ff, 0xc189, 0x21, 0 + .dw 0xa440, 0xc189, 0xa47f, 0xc189, 0x21, 0 + .dw 0xa4c0, 0xc189, 0xa4ff, 0xc189, 0x21, 0 + .dw 0xa540, 0xc189, 0xa57f, 0xc189, 0x21, 0 + .dw 0xa5c0, 0xc189, 0xa5ff, 0xc189, 0x21, 0 + .dw 0xa640, 0xc189, 0xa67f, 0xc189, 0x21, 0 + .dw 0xa6c0, 0xc189, 0xa6ff, 0xc189, 0x21, 0 + .dw 0xa740, 0xc189, 0xa77f, 0xc189, 0x21, 0 + .dw 0xa7c0, 0xc189, 0xa7ff, 0xc189, 0x21, 0 + .dw 0xa840, 0xc189, 0xa87f, 0xc189, 0x21, 0 + .dw 0xa8c0, 0xc189, 0xa8ff, 0xc189, 0x21, 0 + .dw 0xa940, 0xc189, 0xa97f, 0xc189, 0x21, 0 + .dw 0xa9c0, 0xc189, 0xa9ff, 0xc189, 0x21, 0 + .dw 0xaa40, 0xc189, 0xaa7f, 0xc189, 0x21, 0 + .dw 0xaac0, 0xc189, 0xaaff, 0xc189, 0x21, 0 + .dw 0xab40, 0xc189, 0xab7f, 0xc189, 0x21, 0 + .dw 0xabc0, 0xc189, 0xabff, 0xc189, 0x21, 0 + .dw 0xac40, 0xc189, 0xac7f, 0xc189, 0x21, 0 + .dw 0xacc0, 0xc189, 0xacff, 0xc189, 0x21, 0 + .dw 0xad40, 0xc189, 0xad7f, 0xc189, 0x21, 0 + .dw 0xadc0, 0xc189, 0xadff, 0xc189, 0x21, 0 + .dw 0xae40, 0xc189, 0xae7f, 0xc189, 0x21, 0 + .dw 0xaec0, 0xc189, 0xaeff, 0xc189, 0x21, 0 + .dw 0xaf40, 0xc189, 0xaf7f, 0xc189, 0x21, 0 + .dw 0xafc0, 0xc189, 0xafff, 0xc189, 0x21, 0 + .dw 0xb040, 0xc189, 0xb07f, 0xc189, 0x21, 0 + .dw 0xb0c0, 0xc189, 0xb0ff, 0xc189, 0x21, 0 + .dw 0xb140, 0xc189, 0xb17f, 0xc189, 0x21, 0 + .dw 0xb1c0, 0xc189, 0xb1ff, 0xc189, 0x21, 0 + .dw 0xb240, 0xc189, 0xb27f, 0xc189, 0x21, 0 + .dw 0xb2c0, 0xc189, 0xb2ff, 0xc189, 0x21, 0 + .dw 0xb340, 0xc189, 0xb37f, 0xc189, 0x21, 0 + .dw 0xb3c0, 0xc189, 0xb3ff, 0xc189, 0x21, 0 + .dw 0xb440, 0xc189, 0xb47f, 0xc189, 0x21, 0 + .dw 0xb4c0, 0xc189, 0xb4ff, 0xc189, 0x21, 0 + .dw 0xb540, 0xc189, 0xb57f, 0xc189, 0x21, 0 + .dw 0xb5c0, 0xc189, 0xb5ff, 0xc189, 0x21, 0 + .dw 0xb640, 0xc189, 0xb67f, 0xc189, 0x21, 0 + .dw 0xb6c0, 0xc189, 0xb6ff, 0xc189, 0x21, 0 + .dw 0xb740, 0xc189, 0xb77f, 0xc189, 0x21, 0 + .dw 0xb7c0, 0xc189, 0xb7ff, 0xc189, 0x21, 0 + .dw 0xb840, 0xc189, 0xb87f, 0xc189, 0x21, 0 + .dw 0xb8c0, 0xc189, 0xb8ff, 0xc189, 0x21, 0 + .dw 0xb940, 0xc189, 0xb97f, 0xc189, 0x21, 0 + .dw 0xb9c0, 0xc189, 0xdfff, 0xc189, 0x21, 0 + .dw 0xe040, 0xc189, 0xe07f, 0xc189, 0x21, 0 + .dw 0xe0c0, 0xc189, 0xe0ff, 0xc189, 0x21, 0 + .dw 0xe140, 0xc189, 0xe17f, 0xc189, 0x21, 0 + .dw 0xe1c0, 0xc189, 0xe1ff, 0xc189, 0x21, 0 + .dw 0xe240, 0xc189, 0xe27f, 0xc189, 0x21, 0 + .dw 0xe2c0, 0xc189, 0xe2ff, 0xc189, 0x21, 0 + .dw 0xe340, 0xc189, 0xe37f, 0xc189, 0x21, 0 + .dw 0xe3c0, 0xc189, 0xe3ff, 0xc189, 0x21, 0 + .dw 0xe440, 0xc189, 0xe47f, 0xc189, 0x21, 0 + .dw 0xe4c0, 0xc189, 0xe4ff, 0xc189, 0x21, 0 + .dw 0xe540, 0xc189, 0xe57f, 0xc189, 0x21, 0 + .dw 0xe5c0, 0xc189, 0xe5ff, 0xc189, 0x21, 0 + .dw 0xe640, 0xc189, 0xe67f, 0xc189, 0x21, 0 + .dw 0xe6c0, 0xc189, 0xe6ff, 0xc189, 0x21, 0 + .dw 0xe740, 0xc189, 0xe77f, 0xc189, 0x21, 0 + .dw 0xe7c0, 0xc189, 0xe7ff, 0xc189, 0x21, 0 + .dw 0xe840, 0xc189, 0xe87f, 0xc189, 0x21, 0 + .dw 0xe8c0, 0xc189, 0xe8ff, 0xc189, 0x21, 0 + .dw 0xe940, 0xc189, 0xe97f, 0xc189, 0x21, 0 + .dw 0xe9c0, 0xc189, 0xe9ff, 0xc189, 0x21, 0 + .dw 0xea40, 0xc189, 0xea7f, 0xc189, 0x21, 0 + .dw 0xeac0, 0xc189, 0xeaff, 0xc189, 0x21, 0 + .dw 0xeb40, 0xc189, 0xeb7f, 0xc189, 0x21, 0 + .dw 0xebc0, 0xc189, 0xebff, 0xc189, 0x21, 0 + .dw 0xec40, 0xc189, 0xec7f, 0xc189, 0x21, 0 + .dw 0xecc0, 0xc189, 0xecff, 0xc189, 0x21, 0 + .dw 0xed40, 0xc189, 0xed7f, 0xc189, 0x21, 0 + .dw 0xedc0, 0xc189, 0xedff, 0xc189, 0x21, 0 + .dw 0xee40, 0xc189, 0xee7f, 0xc189, 0x21, 0 + .dw 0xeec0, 0xc189, 0xeeff, 0xc189, 0x21, 0 + .dw 0xef40, 0xc189, 0xef7f, 0xc189, 0x21, 0 + .dw 0xefc0, 0xc189, 0xefff, 0xc189, 0x21, 0 + .dw 0xf040, 0xc189, 0xf07f, 0xc189, 0x21, 0 + .dw 0xf0c0, 0xc189, 0xf0ff, 0xc189, 0x21, 0 + .dw 0xf140, 0xc189, 0xf17f, 0xc189, 0x21, 0 + .dw 0xf1c0, 0xc189, 0xf1ff, 0xc189, 0x21, 0 + .dw 0xf240, 0xc189, 0xf27f, 0xc189, 0x21, 0 + .dw 0xf2c0, 0xc189, 0xf2ff, 0xc189, 0x21, 0 + .dw 0xf340, 0xc189, 0xf37f, 0xc189, 0x21, 0 + .dw 0xf3c0, 0xc189, 0xf3ff, 0xc189, 0x21, 0 + .dw 0xf440, 0xc189, 0xf47f, 0xc189, 0x21, 0 + .dw 0xf4c0, 0xc189, 0xf4ff, 0xc189, 0x21, 0 + .dw 0xf540, 0xc189, 0xf57f, 0xc189, 0x21, 0 + .dw 0xf5c0, 0xc189, 0xf5ff, 0xc189, 0x21, 0 + .dw 0xf640, 0xc189, 0xf67f, 0xc189, 0x21, 0 + .dw 0xf6c0, 0xc189, 0xf6ff, 0xc189, 0x21, 0 + .dw 0xf740, 0xc189, 0xf77f, 0xc189, 0x21, 0 + .dw 0xf7c0, 0xc189, 0xf7ff, 0xc189, 0x21, 0 + .dw 0xf840, 0xc189, 0xf87f, 0xc189, 0x21, 0 + .dw 0xf8c0, 0xc189, 0xf8ff, 0xc189, 0x21, 0 + .dw 0xf940, 0xc189, 0xf97f, 0xc189, 0x21, 0 + .dw 0xf9c0, 0xc189, 0x1fff, 0xc18a, 0x21, 0 + .dw 0x2040, 0xc18a, 0x207f, 0xc18a, 0x21, 0 + .dw 0x20c0, 0xc18a, 0x20ff, 0xc18a, 0x21, 0 + .dw 0x2140, 0xc18a, 0x217f, 0xc18a, 0x21, 0 + .dw 0x21c0, 0xc18a, 0x21ff, 0xc18a, 0x21, 0 + .dw 0x2240, 0xc18a, 0x227f, 0xc18a, 0x21, 0 + .dw 0x22c0, 0xc18a, 0x22ff, 0xc18a, 0x21, 0 + .dw 0x2340, 0xc18a, 0x237f, 0xc18a, 0x21, 0 + .dw 0x23c0, 0xc18a, 0x23ff, 0xc18a, 0x21, 0 + .dw 0x2440, 0xc18a, 0x247f, 0xc18a, 0x21, 0 + .dw 0x24c0, 0xc18a, 0x24ff, 0xc18a, 0x21, 0 + .dw 0x2540, 0xc18a, 0x257f, 0xc18a, 0x21, 0 + .dw 0x25c0, 0xc18a, 0x25ff, 0xc18a, 0x21, 0 + .dw 0x2640, 0xc18a, 0x267f, 0xc18a, 0x21, 0 + .dw 0x26c0, 0xc18a, 0x26ff, 0xc18a, 0x21, 0 + .dw 0x2740, 0xc18a, 0x277f, 0xc18a, 0x21, 0 + .dw 0x27c0, 0xc18a, 0x27ff, 0xc18a, 0x21, 0 + .dw 0x2840, 0xc18a, 0x287f, 0xc18a, 0x21, 0 + .dw 0x28c0, 0xc18a, 0x28ff, 0xc18a, 0x21, 0 + .dw 0x2940, 0xc18a, 0x297f, 0xc18a, 0x21, 0 + .dw 0x29c0, 0xc18a, 0x29ff, 0xc18a, 0x21, 0 + .dw 0x2a40, 0xc18a, 0x2a7f, 0xc18a, 0x21, 0 + .dw 0x2ac0, 0xc18a, 0x2aff, 0xc18a, 0x21, 0 + .dw 0x2b40, 0xc18a, 0x2b7f, 0xc18a, 0x21, 0 + .dw 0x2bc0, 0xc18a, 0x2bff, 0xc18a, 0x21, 0 + .dw 0x2c40, 0xc18a, 0x2c7f, 0xc18a, 0x21, 0 + .dw 0x2cc0, 0xc18a, 0x2cff, 0xc18a, 0x21, 0 + .dw 0x2d40, 0xc18a, 0x2d7f, 0xc18a, 0x21, 0 + .dw 0x2dc0, 0xc18a, 0x2dff, 0xc18a, 0x21, 0 + .dw 0x2e40, 0xc18a, 0x2e7f, 0xc18a, 0x21, 0 + .dw 0x2ec0, 0xc18a, 0x2eff, 0xc18a, 0x21, 0 + .dw 0x2f40, 0xc18a, 0x2f7f, 0xc18a, 0x21, 0 + .dw 0x2fc0, 0xc18a, 0x2fff, 0xc18a, 0x21, 0 + .dw 0x3040, 0xc18a, 0x307f, 0xc18a, 0x21, 0 + .dw 0x30c0, 0xc18a, 0x30ff, 0xc18a, 0x21, 0 + .dw 0x3140, 0xc18a, 0x317f, 0xc18a, 0x21, 0 + .dw 0x31c0, 0xc18a, 0x31ff, 0xc18a, 0x21, 0 + .dw 0x3240, 0xc18a, 0x327f, 0xc18a, 0x21, 0 + .dw 0x32c0, 0xc18a, 0x32ff, 0xc18a, 0x21, 0 + .dw 0x3340, 0xc18a, 0x337f, 0xc18a, 0x21, 0 + .dw 0x33c0, 0xc18a, 0x33ff, 0xc18a, 0x21, 0 + .dw 0x3440, 0xc18a, 0x347f, 0xc18a, 0x21, 0 + .dw 0x34c0, 0xc18a, 0x34ff, 0xc18a, 0x21, 0 + .dw 0x3540, 0xc18a, 0x357f, 0xc18a, 0x21, 0 + .dw 0x35c0, 0xc18a, 0x35ff, 0xc18a, 0x21, 0 + .dw 0x3640, 0xc18a, 0x367f, 0xc18a, 0x21, 0 + .dw 0x36c0, 0xc18a, 0x36ff, 0xc18a, 0x21, 0 + .dw 0x3740, 0xc18a, 0x377f, 0xc18a, 0x21, 0 + .dw 0x37c0, 0xc18a, 0x37ff, 0xc18a, 0x21, 0 + .dw 0x3840, 0xc18a, 0x387f, 0xc18a, 0x21, 0 + .dw 0x38c0, 0xc18a, 0x38ff, 0xc18a, 0x21, 0 + .dw 0x3940, 0xc18a, 0x397f, 0xc18a, 0x21, 0 + .dw 0x39c0, 0xc18a, 0x5fff, 0xc18a, 0x21, 0 + .dw 0x6040, 0xc18a, 0x607f, 0xc18a, 0x21, 0 + .dw 0x60c0, 0xc18a, 0x60ff, 0xc18a, 0x21, 0 + .dw 0x6140, 0xc18a, 0x617f, 0xc18a, 0x21, 0 + .dw 0x61c0, 0xc18a, 0x61ff, 0xc18a, 0x21, 0 + .dw 0x6240, 0xc18a, 0x627f, 0xc18a, 0x21, 0 + .dw 0x62c0, 0xc18a, 0x62ff, 0xc18a, 0x21, 0 + .dw 0x6340, 0xc18a, 0x637f, 0xc18a, 0x21, 0 + .dw 0x63c0, 0xc18a, 0x63ff, 0xc18a, 0x21, 0 + .dw 0x6440, 0xc18a, 0x647f, 0xc18a, 0x21, 0 + .dw 0x64c0, 0xc18a, 0x64ff, 0xc18a, 0x21, 0 + .dw 0x6540, 0xc18a, 0x657f, 0xc18a, 0x21, 0 + .dw 0x65c0, 0xc18a, 0x65ff, 0xc18a, 0x21, 0 + .dw 0x6640, 0xc18a, 0x667f, 0xc18a, 0x21, 0 + .dw 0x66c0, 0xc18a, 0x66ff, 0xc18a, 0x21, 0 + .dw 0x6740, 0xc18a, 0x677f, 0xc18a, 0x21, 0 + .dw 0x67c0, 0xc18a, 0x67ff, 0xc18a, 0x21, 0 + .dw 0x6840, 0xc18a, 0x687f, 0xc18a, 0x21, 0 + .dw 0x68c0, 0xc18a, 0x68ff, 0xc18a, 0x21, 0 + .dw 0x6940, 0xc18a, 0x697f, 0xc18a, 0x21, 0 + .dw 0x69c0, 0xc18a, 0x69ff, 0xc18a, 0x21, 0 + .dw 0x6a40, 0xc18a, 0x6a7f, 0xc18a, 0x21, 0 + .dw 0x6ac0, 0xc18a, 0x6aff, 0xc18a, 0x21, 0 + .dw 0x6b40, 0xc18a, 0x6b7f, 0xc18a, 0x21, 0 + .dw 0x6bc0, 0xc18a, 0x6bff, 0xc18a, 0x21, 0 + .dw 0x6c40, 0xc18a, 0x6c7f, 0xc18a, 0x21, 0 + .dw 0x6cc0, 0xc18a, 0x6cff, 0xc18a, 0x21, 0 + .dw 0x6d40, 0xc18a, 0x6d7f, 0xc18a, 0x21, 0 + .dw 0x6dc0, 0xc18a, 0x6dff, 0xc18a, 0x21, 0 + .dw 0x6e40, 0xc18a, 0x6e7f, 0xc18a, 0x21, 0 + .dw 0x6ec0, 0xc18a, 0x6eff, 0xc18a, 0x21, 0 + .dw 0x6f40, 0xc18a, 0x6f7f, 0xc18a, 0x21, 0 + .dw 0x6fc0, 0xc18a, 0x6fff, 0xc18a, 0x21, 0 + .dw 0x7040, 0xc18a, 0x707f, 0xc18a, 0x21, 0 + .dw 0x70c0, 0xc18a, 0x70ff, 0xc18a, 0x21, 0 + .dw 0x7140, 0xc18a, 0x717f, 0xc18a, 0x21, 0 + .dw 0x71c0, 0xc18a, 0x71ff, 0xc18a, 0x21, 0 + .dw 0x7240, 0xc18a, 0x727f, 0xc18a, 0x21, 0 + .dw 0x72c0, 0xc18a, 0x72ff, 0xc18a, 0x21, 0 + .dw 0x7340, 0xc18a, 0x737f, 0xc18a, 0x21, 0 + .dw 0x73c0, 0xc18a, 0x73ff, 0xc18a, 0x21, 0 + .dw 0x7440, 0xc18a, 0x747f, 0xc18a, 0x21, 0 + .dw 0x74c0, 0xc18a, 0x74ff, 0xc18a, 0x21, 0 + .dw 0x7540, 0xc18a, 0x757f, 0xc18a, 0x21, 0 + .dw 0x75c0, 0xc18a, 0x75ff, 0xc18a, 0x21, 0 + .dw 0x7640, 0xc18a, 0x767f, 0xc18a, 0x21, 0 + .dw 0x76c0, 0xc18a, 0x76ff, 0xc18a, 0x21, 0 + .dw 0x7740, 0xc18a, 0x777f, 0xc18a, 0x21, 0 + .dw 0x77c0, 0xc18a, 0x77ff, 0xc18a, 0x21, 0 + .dw 0x7840, 0xc18a, 0x787f, 0xc18a, 0x21, 0 + .dw 0x78c0, 0xc18a, 0x78ff, 0xc18a, 0x21, 0 + .dw 0x7940, 0xc18a, 0x797f, 0xc18a, 0x21, 0 + .dw 0x79c0, 0xc18a, 0x9fff, 0xc18a, 0x21, 0 + .dw 0xa040, 0xc18a, 0xa07f, 0xc18a, 0x21, 0 + .dw 0xa0c0, 0xc18a, 0xa0ff, 0xc18a, 0x21, 0 + .dw 0xa140, 0xc18a, 0xa17f, 0xc18a, 0x21, 0 + .dw 0xa1c0, 0xc18a, 0xa1ff, 0xc18a, 0x21, 0 + .dw 0xa240, 0xc18a, 0xa27f, 0xc18a, 0x21, 0 + .dw 0xa2c0, 0xc18a, 0xa2ff, 0xc18a, 0x21, 0 + .dw 0xa340, 0xc18a, 0xa37f, 0xc18a, 0x21, 0 + .dw 0xa3c0, 0xc18a, 0xa3ff, 0xc18a, 0x21, 0 + .dw 0xa440, 0xc18a, 0xa47f, 0xc18a, 0x21, 0 + .dw 0xa4c0, 0xc18a, 0xa4ff, 0xc18a, 0x21, 0 + .dw 0xa540, 0xc18a, 0xa57f, 0xc18a, 0x21, 0 + .dw 0xa5c0, 0xc18a, 0xa5ff, 0xc18a, 0x21, 0 + .dw 0xa640, 0xc18a, 0xa67f, 0xc18a, 0x21, 0 + .dw 0xa6c0, 0xc18a, 0xa6ff, 0xc18a, 0x21, 0 + .dw 0xa740, 0xc18a, 0xa77f, 0xc18a, 0x21, 0 + .dw 0xa7c0, 0xc18a, 0xa7ff, 0xc18a, 0x21, 0 + .dw 0xa840, 0xc18a, 0xa87f, 0xc18a, 0x21, 0 + .dw 0xa8c0, 0xc18a, 0xa8ff, 0xc18a, 0x21, 0 + .dw 0xa940, 0xc18a, 0xa97f, 0xc18a, 0x21, 0 + .dw 0xa9c0, 0xc18a, 0xa9ff, 0xc18a, 0x21, 0 + .dw 0xaa40, 0xc18a, 0xaa7f, 0xc18a, 0x21, 0 + .dw 0xaac0, 0xc18a, 0xaaff, 0xc18a, 0x21, 0 + .dw 0xab40, 0xc18a, 0xab7f, 0xc18a, 0x21, 0 + .dw 0xabc0, 0xc18a, 0xabff, 0xc18a, 0x21, 0 + .dw 0xac40, 0xc18a, 0xac7f, 0xc18a, 0x21, 0 + .dw 0xacc0, 0xc18a, 0xacff, 0xc18a, 0x21, 0 + .dw 0xad40, 0xc18a, 0xad7f, 0xc18a, 0x21, 0 + .dw 0xadc0, 0xc18a, 0xadff, 0xc18a, 0x21, 0 + .dw 0xae40, 0xc18a, 0xae7f, 0xc18a, 0x21, 0 + .dw 0xaec0, 0xc18a, 0xaeff, 0xc18a, 0x21, 0 + .dw 0xaf40, 0xc18a, 0xaf7f, 0xc18a, 0x21, 0 + .dw 0xafc0, 0xc18a, 0xafff, 0xc18a, 0x21, 0 + .dw 0xb040, 0xc18a, 0xb07f, 0xc18a, 0x21, 0 + .dw 0xb0c0, 0xc18a, 0xb0ff, 0xc18a, 0x21, 0 + .dw 0xb140, 0xc18a, 0xb17f, 0xc18a, 0x21, 0 + .dw 0xb1c0, 0xc18a, 0xb1ff, 0xc18a, 0x21, 0 + .dw 0xb240, 0xc18a, 0xb27f, 0xc18a, 0x21, 0 + .dw 0xb2c0, 0xc18a, 0xb2ff, 0xc18a, 0x21, 0 + .dw 0xb340, 0xc18a, 0xb37f, 0xc18a, 0x21, 0 + .dw 0xb3c0, 0xc18a, 0xb3ff, 0xc18a, 0x21, 0 + .dw 0xb440, 0xc18a, 0xb47f, 0xc18a, 0x21, 0 + .dw 0xb4c0, 0xc18a, 0xb4ff, 0xc18a, 0x21, 0 + .dw 0xb540, 0xc18a, 0xb57f, 0xc18a, 0x21, 0 + .dw 0xb5c0, 0xc18a, 0xb5ff, 0xc18a, 0x21, 0 + .dw 0xb640, 0xc18a, 0xb67f, 0xc18a, 0x21, 0 + .dw 0xb6c0, 0xc18a, 0xb6ff, 0xc18a, 0x21, 0 + .dw 0xb740, 0xc18a, 0xb77f, 0xc18a, 0x21, 0 + .dw 0xb7c0, 0xc18a, 0xb7ff, 0xc18a, 0x21, 0 + .dw 0xb840, 0xc18a, 0xb87f, 0xc18a, 0x21, 0 + .dw 0xb8c0, 0xc18a, 0xb8ff, 0xc18a, 0x21, 0 + .dw 0xb940, 0xc18a, 0xb97f, 0xc18a, 0x21, 0 + .dw 0xb9c0, 0xc18a, 0xdfff, 0xc18a, 0x21, 0 + .dw 0xe040, 0xc18a, 0xe07f, 0xc18a, 0x21, 0 + .dw 0xe0c0, 0xc18a, 0xe0ff, 0xc18a, 0x21, 0 + .dw 0xe140, 0xc18a, 0xe17f, 0xc18a, 0x21, 0 + .dw 0xe1c0, 0xc18a, 0xe1ff, 0xc18a, 0x21, 0 + .dw 0xe240, 0xc18a, 0xe27f, 0xc18a, 0x21, 0 + .dw 0xe2c0, 0xc18a, 0xe2ff, 0xc18a, 0x21, 0 + .dw 0xe340, 0xc18a, 0xe37f, 0xc18a, 0x21, 0 + .dw 0xe3c0, 0xc18a, 0xe3ff, 0xc18a, 0x21, 0 + .dw 0xe440, 0xc18a, 0xe47f, 0xc18a, 0x21, 0 + .dw 0xe4c0, 0xc18a, 0xe4ff, 0xc18a, 0x21, 0 + .dw 0xe540, 0xc18a, 0xe57f, 0xc18a, 0x21, 0 + .dw 0xe5c0, 0xc18a, 0xe5ff, 0xc18a, 0x21, 0 + .dw 0xe640, 0xc18a, 0xe67f, 0xc18a, 0x21, 0 + .dw 0xe6c0, 0xc18a, 0xe6ff, 0xc18a, 0x21, 0 + .dw 0xe740, 0xc18a, 0xe77f, 0xc18a, 0x21, 0 + .dw 0xe7c0, 0xc18a, 0xe7ff, 0xc18a, 0x21, 0 + .dw 0xe840, 0xc18a, 0xe87f, 0xc18a, 0x21, 0 + .dw 0xe8c0, 0xc18a, 0xe8ff, 0xc18a, 0x21, 0 + .dw 0xe940, 0xc18a, 0xe97f, 0xc18a, 0x21, 0 + .dw 0xe9c0, 0xc18a, 0xe9ff, 0xc18a, 0x21, 0 + .dw 0xea40, 0xc18a, 0xea7f, 0xc18a, 0x21, 0 + .dw 0xeac0, 0xc18a, 0xeaff, 0xc18a, 0x21, 0 + .dw 0xeb40, 0xc18a, 0xeb7f, 0xc18a, 0x21, 0 + .dw 0xebc0, 0xc18a, 0xebff, 0xc18a, 0x21, 0 + .dw 0xec40, 0xc18a, 0xec7f, 0xc18a, 0x21, 0 + .dw 0xecc0, 0xc18a, 0xecff, 0xc18a, 0x21, 0 + .dw 0xed40, 0xc18a, 0xed7f, 0xc18a, 0x21, 0 + .dw 0xedc0, 0xc18a, 0xedff, 0xc18a, 0x21, 0 + .dw 0xee40, 0xc18a, 0xee7f, 0xc18a, 0x21, 0 + .dw 0xeec0, 0xc18a, 0xeeff, 0xc18a, 0x21, 0 + .dw 0xef40, 0xc18a, 0xef7f, 0xc18a, 0x21, 0 + .dw 0xefc0, 0xc18a, 0xefff, 0xc18a, 0x21, 0 + .dw 0xf040, 0xc18a, 0xf07f, 0xc18a, 0x21, 0 + .dw 0xf0c0, 0xc18a, 0xf0ff, 0xc18a, 0x21, 0 + .dw 0xf140, 0xc18a, 0xf17f, 0xc18a, 0x21, 0 + .dw 0xf1c0, 0xc18a, 0xf1ff, 0xc18a, 0x21, 0 + .dw 0xf240, 0xc18a, 0xf27f, 0xc18a, 0x21, 0 + .dw 0xf2c0, 0xc18a, 0xf2ff, 0xc18a, 0x21, 0 + .dw 0xf340, 0xc18a, 0xf37f, 0xc18a, 0x21, 0 + .dw 0xf3c0, 0xc18a, 0xf3ff, 0xc18a, 0x21, 0 + .dw 0xf440, 0xc18a, 0xf47f, 0xc18a, 0x21, 0 + .dw 0xf4c0, 0xc18a, 0xf4ff, 0xc18a, 0x21, 0 + .dw 0xf540, 0xc18a, 0xf57f, 0xc18a, 0x21, 0 + .dw 0xf5c0, 0xc18a, 0xf5ff, 0xc18a, 0x21, 0 + .dw 0xf640, 0xc18a, 0xf67f, 0xc18a, 0x21, 0 + .dw 0xf6c0, 0xc18a, 0xf6ff, 0xc18a, 0x21, 0 + .dw 0xf740, 0xc18a, 0xf77f, 0xc18a, 0x21, 0 + .dw 0xf7c0, 0xc18a, 0xf7ff, 0xc18a, 0x21, 0 + .dw 0xf840, 0xc18a, 0xf87f, 0xc18a, 0x21, 0 + .dw 0xf8c0, 0xc18a, 0xf8ff, 0xc18a, 0x21, 0 + .dw 0xf940, 0xc18a, 0xf97f, 0xc18a, 0x21, 0 + .dw 0xf9c0, 0xc18a, 0x1fff, 0xc18b, 0x21, 0 + .dw 0x2040, 0xc18b, 0x207f, 0xc18b, 0x21, 0 + .dw 0x20c0, 0xc18b, 0x20ff, 0xc18b, 0x21, 0 + .dw 0x2140, 0xc18b, 0x217f, 0xc18b, 0x21, 0 + .dw 0x21c0, 0xc18b, 0x21ff, 0xc18b, 0x21, 0 + .dw 0x2240, 0xc18b, 0x227f, 0xc18b, 0x21, 0 + .dw 0x22c0, 0xc18b, 0x22ff, 0xc18b, 0x21, 0 + .dw 0x2340, 0xc18b, 0x237f, 0xc18b, 0x21, 0 + .dw 0x23c0, 0xc18b, 0x23ff, 0xc18b, 0x21, 0 + .dw 0x2440, 0xc18b, 0x247f, 0xc18b, 0x21, 0 + .dw 0x24c0, 0xc18b, 0x24ff, 0xc18b, 0x21, 0 + .dw 0x2540, 0xc18b, 0x257f, 0xc18b, 0x21, 0 + .dw 0x25c0, 0xc18b, 0x25ff, 0xc18b, 0x21, 0 + .dw 0x2640, 0xc18b, 0x267f, 0xc18b, 0x21, 0 + .dw 0x26c0, 0xc18b, 0x26ff, 0xc18b, 0x21, 0 + .dw 0x2740, 0xc18b, 0x277f, 0xc18b, 0x21, 0 + .dw 0x27c0, 0xc18b, 0x27ff, 0xc18b, 0x21, 0 + .dw 0x2840, 0xc18b, 0x287f, 0xc18b, 0x21, 0 + .dw 0x28c0, 0xc18b, 0x28ff, 0xc18b, 0x21, 0 + .dw 0x2940, 0xc18b, 0x297f, 0xc18b, 0x21, 0 + .dw 0x29c0, 0xc18b, 0x29ff, 0xc18b, 0x21, 0 + .dw 0x2a40, 0xc18b, 0x2a7f, 0xc18b, 0x21, 0 + .dw 0x2ac0, 0xc18b, 0x2aff, 0xc18b, 0x21, 0 + .dw 0x2b40, 0xc18b, 0x2b7f, 0xc18b, 0x21, 0 + .dw 0x2bc0, 0xc18b, 0x2bff, 0xc18b, 0x21, 0 + .dw 0x2c40, 0xc18b, 0x2c7f, 0xc18b, 0x21, 0 + .dw 0x2cc0, 0xc18b, 0x2cff, 0xc18b, 0x21, 0 + .dw 0x2d40, 0xc18b, 0x2d7f, 0xc18b, 0x21, 0 + .dw 0x2dc0, 0xc18b, 0x2dff, 0xc18b, 0x21, 0 + .dw 0x2e40, 0xc18b, 0x2e7f, 0xc18b, 0x21, 0 + .dw 0x2ec0, 0xc18b, 0x2eff, 0xc18b, 0x21, 0 + .dw 0x2f40, 0xc18b, 0x2f7f, 0xc18b, 0x21, 0 + .dw 0x2fc0, 0xc18b, 0x2fff, 0xc18b, 0x21, 0 + .dw 0x3040, 0xc18b, 0x307f, 0xc18b, 0x21, 0 + .dw 0x30c0, 0xc18b, 0x30ff, 0xc18b, 0x21, 0 + .dw 0x3140, 0xc18b, 0x317f, 0xc18b, 0x21, 0 + .dw 0x31c0, 0xc18b, 0x31ff, 0xc18b, 0x21, 0 + .dw 0x3240, 0xc18b, 0x327f, 0xc18b, 0x21, 0 + .dw 0x32c0, 0xc18b, 0x32ff, 0xc18b, 0x21, 0 + .dw 0x3340, 0xc18b, 0x337f, 0xc18b, 0x21, 0 + .dw 0x33c0, 0xc18b, 0x33ff, 0xc18b, 0x21, 0 + .dw 0x3440, 0xc18b, 0x347f, 0xc18b, 0x21, 0 + .dw 0x34c0, 0xc18b, 0x34ff, 0xc18b, 0x21, 0 + .dw 0x3540, 0xc18b, 0x357f, 0xc18b, 0x21, 0 + .dw 0x35c0, 0xc18b, 0x35ff, 0xc18b, 0x21, 0 + .dw 0x3640, 0xc18b, 0x367f, 0xc18b, 0x21, 0 + .dw 0x36c0, 0xc18b, 0x36ff, 0xc18b, 0x21, 0 + .dw 0x3740, 0xc18b, 0x377f, 0xc18b, 0x21, 0 + .dw 0x37c0, 0xc18b, 0x37ff, 0xc18b, 0x21, 0 + .dw 0x3840, 0xc18b, 0x387f, 0xc18b, 0x21, 0 + .dw 0x38c0, 0xc18b, 0x38ff, 0xc18b, 0x21, 0 + .dw 0x3940, 0xc18b, 0x397f, 0xc18b, 0x21, 0 + .dw 0x39c0, 0xc18b, 0xffff, 0xc18b, 0x21, 0 + .dw 0x0040, 0xc18c, 0x007f, 0xc18c, 0x21, 0 + .dw 0x00c0, 0xc18c, 0x00ff, 0xc18c, 0x21, 0 + .dw 0x0140, 0xc18c, 0x017f, 0xc18c, 0x21, 0 + .dw 0x01c0, 0xc18c, 0x01ff, 0xc18c, 0x21, 0 + .dw 0x0240, 0xc18c, 0x027f, 0xc18c, 0x21, 0 + .dw 0x02c0, 0xc18c, 0x02ff, 0xc18c, 0x21, 0 + .dw 0x0340, 0xc18c, 0x037f, 0xc18c, 0x21, 0 + .dw 0x03c0, 0xc18c, 0x03ff, 0xc18c, 0x21, 0 + .dw 0x0440, 0xc18c, 0x047f, 0xc18c, 0x21, 0 + .dw 0x04c0, 0xc18c, 0x04ff, 0xc18c, 0x21, 0 + .dw 0x0540, 0xc18c, 0x057f, 0xc18c, 0x21, 0 + .dw 0x05c0, 0xc18c, 0x05ff, 0xc18c, 0x21, 0 + .dw 0x0640, 0xc18c, 0x067f, 0xc18c, 0x21, 0 + .dw 0x06c0, 0xc18c, 0x06ff, 0xc18c, 0x21, 0 + .dw 0x0740, 0xc18c, 0x077f, 0xc18c, 0x21, 0 + .dw 0x07c0, 0xc18c, 0x07ff, 0xc18c, 0x21, 0 + .dw 0x0840, 0xc18c, 0x087f, 0xc18c, 0x21, 0 + .dw 0x08c0, 0xc18c, 0x08ff, 0xc18c, 0x21, 0 + .dw 0x0940, 0xc18c, 0x097f, 0xc18c, 0x21, 0 + .dw 0x09c0, 0xc18c, 0x09ff, 0xc18c, 0x21, 0 + .dw 0x0a40, 0xc18c, 0x0a7f, 0xc18c, 0x21, 0 + .dw 0x0ac0, 0xc18c, 0x0aff, 0xc18c, 0x21, 0 + .dw 0x0b40, 0xc18c, 0x0b7f, 0xc18c, 0x21, 0 + .dw 0x0bc0, 0xc18c, 0x0bff, 0xc18c, 0x21, 0 + .dw 0x0c40, 0xc18c, 0x0c7f, 0xc18c, 0x21, 0 + .dw 0x0cc0, 0xc18c, 0x0cff, 0xc18c, 0x21, 0 + .dw 0x0d40, 0xc18c, 0x0d7f, 0xc18c, 0x21, 0 + .dw 0x0dc0, 0xc18c, 0x0dff, 0xc18c, 0x21, 0 + .dw 0x0e40, 0xc18c, 0x0e7f, 0xc18c, 0x21, 0 + .dw 0x0ec0, 0xc18c, 0x0eff, 0xc18c, 0x21, 0 + .dw 0x0f40, 0xc18c, 0x0f7f, 0xc18c, 0x21, 0 + .dw 0x0fc0, 0xc18c, 0x0fff, 0xc18c, 0x21, 0 + .dw 0x1040, 0xc18c, 0x107f, 0xc18c, 0x21, 0 + .dw 0x10c0, 0xc18c, 0x10ff, 0xc18c, 0x21, 0 + .dw 0x1140, 0xc18c, 0x117f, 0xc18c, 0x21, 0 + .dw 0x11c0, 0xc18c, 0x11ff, 0xc18c, 0x21, 0 + .dw 0x1240, 0xc18c, 0x127f, 0xc18c, 0x21, 0 + .dw 0x12c0, 0xc18c, 0x12ff, 0xc18c, 0x21, 0 + .dw 0x1340, 0xc18c, 0x137f, 0xc18c, 0x21, 0 + .dw 0x13c0, 0xc18c, 0x13ff, 0xc18c, 0x21, 0 + .dw 0x1440, 0xc18c, 0x147f, 0xc18c, 0x21, 0 + .dw 0x14c0, 0xc18c, 0x14ff, 0xc18c, 0x21, 0 + .dw 0x1540, 0xc18c, 0x157f, 0xc18c, 0x21, 0 + .dw 0x15c0, 0xc18c, 0x15ff, 0xc18c, 0x21, 0 + .dw 0x1640, 0xc18c, 0x167f, 0xc18c, 0x21, 0 + .dw 0x16c0, 0xc18c, 0x16ff, 0xc18c, 0x21, 0 + .dw 0x1740, 0xc18c, 0x177f, 0xc18c, 0x21, 0 + .dw 0x17c0, 0xc18c, 0x17ff, 0xc18c, 0x21, 0 + .dw 0x1840, 0xc18c, 0x187f, 0xc18c, 0x21, 0 + .dw 0x18c0, 0xc18c, 0x18ff, 0xc18c, 0x21, 0 + .dw 0x1940, 0xc18c, 0x197f, 0xc18c, 0x21, 0 + .dw 0x19c0, 0xc18c, 0x1fff, 0xc18c, 0x21, 0 + .dw 0x2040, 0xc18c, 0x207f, 0xc18c, 0x21, 0 + .dw 0x20c0, 0xc18c, 0x20ff, 0xc18c, 0x21, 0 + .dw 0x2140, 0xc18c, 0x217f, 0xc18c, 0x21, 0 + .dw 0x21c0, 0xc18c, 0x21ff, 0xc18c, 0x21, 0 + .dw 0x2240, 0xc18c, 0x227f, 0xc18c, 0x21, 0 + .dw 0x22c0, 0xc18c, 0x22ff, 0xc18c, 0x21, 0 + .dw 0x2340, 0xc18c, 0x237f, 0xc18c, 0x21, 0 + .dw 0x23c0, 0xc18c, 0x23ff, 0xc18c, 0x21, 0 + .dw 0x2440, 0xc18c, 0x247f, 0xc18c, 0x21, 0 + .dw 0x24c0, 0xc18c, 0x24ff, 0xc18c, 0x21, 0 + .dw 0x2540, 0xc18c, 0x257f, 0xc18c, 0x21, 0 + .dw 0x25c0, 0xc18c, 0x25ff, 0xc18c, 0x21, 0 + .dw 0x2640, 0xc18c, 0x267f, 0xc18c, 0x21, 0 + .dw 0x26c0, 0xc18c, 0x26ff, 0xc18c, 0x21, 0 + .dw 0x2740, 0xc18c, 0x277f, 0xc18c, 0x21, 0 + .dw 0x27c0, 0xc18c, 0x27ff, 0xc18c, 0x21, 0 + .dw 0x2840, 0xc18c, 0x287f, 0xc18c, 0x21, 0 + .dw 0x28c0, 0xc18c, 0x28ff, 0xc18c, 0x21, 0 + .dw 0x2940, 0xc18c, 0x297f, 0xc18c, 0x21, 0 + .dw 0x29c0, 0xc18c, 0x29ff, 0xc18c, 0x21, 0 + .dw 0x2a40, 0xc18c, 0x2a7f, 0xc18c, 0x21, 0 + .dw 0x2ac0, 0xc18c, 0x2aff, 0xc18c, 0x21, 0 + .dw 0x2b40, 0xc18c, 0x2b7f, 0xc18c, 0x21, 0 + .dw 0x2bc0, 0xc18c, 0x2bff, 0xc18c, 0x21, 0 + .dw 0x2c40, 0xc18c, 0x2c7f, 0xc18c, 0x21, 0 + .dw 0x2cc0, 0xc18c, 0x2cff, 0xc18c, 0x21, 0 + .dw 0x2d40, 0xc18c, 0x2d7f, 0xc18c, 0x21, 0 + .dw 0x2dc0, 0xc18c, 0x2dff, 0xc18c, 0x21, 0 + .dw 0x2e40, 0xc18c, 0x2e7f, 0xc18c, 0x21, 0 + .dw 0x2ec0, 0xc18c, 0x2eff, 0xc18c, 0x21, 0 + .dw 0x2f40, 0xc18c, 0x2f7f, 0xc18c, 0x21, 0 + .dw 0x2fc0, 0xc18c, 0x2fff, 0xc18c, 0x21, 0 + .dw 0x3040, 0xc18c, 0x307f, 0xc18c, 0x21, 0 + .dw 0x30c0, 0xc18c, 0x30ff, 0xc18c, 0x21, 0 + .dw 0x3140, 0xc18c, 0x317f, 0xc18c, 0x21, 0 + .dw 0x31c0, 0xc18c, 0x31ff, 0xc18c, 0x21, 0 + .dw 0x3240, 0xc18c, 0x327f, 0xc18c, 0x21, 0 + .dw 0x32c0, 0xc18c, 0x32ff, 0xc18c, 0x21, 0 + .dw 0x3340, 0xc18c, 0x337f, 0xc18c, 0x21, 0 + .dw 0x33c0, 0xc18c, 0x33ff, 0xc18c, 0x21, 0 + .dw 0x3440, 0xc18c, 0x347f, 0xc18c, 0x21, 0 + .dw 0x34c0, 0xc18c, 0x34ff, 0xc18c, 0x21, 0 + .dw 0x3540, 0xc18c, 0x357f, 0xc18c, 0x21, 0 + .dw 0x35c0, 0xc18c, 0x35ff, 0xc18c, 0x21, 0 + .dw 0x3640, 0xc18c, 0x367f, 0xc18c, 0x21, 0 + .dw 0x36c0, 0xc18c, 0x36ff, 0xc18c, 0x21, 0 + .dw 0x3740, 0xc18c, 0x377f, 0xc18c, 0x21, 0 + .dw 0x37c0, 0xc18c, 0x37ff, 0xc18c, 0x21, 0 + .dw 0x3840, 0xc18c, 0x387f, 0xc18c, 0x21, 0 + .dw 0x38c0, 0xc18c, 0x38ff, 0xc18c, 0x21, 0 + .dw 0x3940, 0xc18c, 0x397f, 0xc18c, 0x21, 0 + .dw 0x39c0, 0xc18c, 0x3fff, 0xc18c, 0x21, 0 + .dw 0x4040, 0xc18c, 0x407f, 0xc18c, 0x21, 0 + .dw 0x40c0, 0xc18c, 0x40ff, 0xc18c, 0x21, 0 + .dw 0x4140, 0xc18c, 0x417f, 0xc18c, 0x21, 0 + .dw 0x41c0, 0xc18c, 0x41ff, 0xc18c, 0x21, 0 + .dw 0x4240, 0xc18c, 0x427f, 0xc18c, 0x21, 0 + .dw 0x42c0, 0xc18c, 0x42ff, 0xc18c, 0x21, 0 + .dw 0x4340, 0xc18c, 0x437f, 0xc18c, 0x21, 0 + .dw 0x43c0, 0xc18c, 0x43ff, 0xc18c, 0x21, 0 + .dw 0x4440, 0xc18c, 0x447f, 0xc18c, 0x21, 0 + .dw 0x44c0, 0xc18c, 0x44ff, 0xc18c, 0x21, 0 + .dw 0x4540, 0xc18c, 0x457f, 0xc18c, 0x21, 0 + .dw 0x45c0, 0xc18c, 0x45ff, 0xc18c, 0x21, 0 + .dw 0x4640, 0xc18c, 0x467f, 0xc18c, 0x21, 0 + .dw 0x46c0, 0xc18c, 0x46ff, 0xc18c, 0x21, 0 + .dw 0x4740, 0xc18c, 0x477f, 0xc18c, 0x21, 0 + .dw 0x47c0, 0xc18c, 0x47ff, 0xc18c, 0x21, 0 + .dw 0x4840, 0xc18c, 0x487f, 0xc18c, 0x21, 0 + .dw 0x48c0, 0xc18c, 0x48ff, 0xc18c, 0x21, 0 + .dw 0x4940, 0xc18c, 0x497f, 0xc18c, 0x21, 0 + .dw 0x49c0, 0xc18c, 0x49ff, 0xc18c, 0x21, 0 + .dw 0x4a40, 0xc18c, 0x4a7f, 0xc18c, 0x21, 0 + .dw 0x4ac0, 0xc18c, 0x4aff, 0xc18c, 0x21, 0 + .dw 0x4b40, 0xc18c, 0x4b7f, 0xc18c, 0x21, 0 + .dw 0x4bc0, 0xc18c, 0x4bff, 0xc18c, 0x21, 0 + .dw 0x4c40, 0xc18c, 0x4c7f, 0xc18c, 0x21, 0 + .dw 0x4cc0, 0xc18c, 0x4cff, 0xc18c, 0x21, 0 + .dw 0x4d40, 0xc18c, 0x4d7f, 0xc18c, 0x21, 0 + .dw 0x4dc0, 0xc18c, 0x4dff, 0xc18c, 0x21, 0 + .dw 0x4e40, 0xc18c, 0x4e7f, 0xc18c, 0x21, 0 + .dw 0x4ec0, 0xc18c, 0x4eff, 0xc18c, 0x21, 0 + .dw 0x4f40, 0xc18c, 0x4f7f, 0xc18c, 0x21, 0 + .dw 0x4fc0, 0xc18c, 0x4fff, 0xc18c, 0x21, 0 + .dw 0x5040, 0xc18c, 0x507f, 0xc18c, 0x21, 0 + .dw 0x50c0, 0xc18c, 0x50ff, 0xc18c, 0x21, 0 + .dw 0x5140, 0xc18c, 0x517f, 0xc18c, 0x21, 0 + .dw 0x51c0, 0xc18c, 0x51ff, 0xc18c, 0x21, 0 + .dw 0x5240, 0xc18c, 0x527f, 0xc18c, 0x21, 0 + .dw 0x52c0, 0xc18c, 0x52ff, 0xc18c, 0x21, 0 + .dw 0x5340, 0xc18c, 0x537f, 0xc18c, 0x21, 0 + .dw 0x53c0, 0xc18c, 0x53ff, 0xc18c, 0x21, 0 + .dw 0x5440, 0xc18c, 0x547f, 0xc18c, 0x21, 0 + .dw 0x54c0, 0xc18c, 0x54ff, 0xc18c, 0x21, 0 + .dw 0x5540, 0xc18c, 0x557f, 0xc18c, 0x21, 0 + .dw 0x55c0, 0xc18c, 0x55ff, 0xc18c, 0x21, 0 + .dw 0x5640, 0xc18c, 0x567f, 0xc18c, 0x21, 0 + .dw 0x56c0, 0xc18c, 0x56ff, 0xc18c, 0x21, 0 + .dw 0x5740, 0xc18c, 0x577f, 0xc18c, 0x21, 0 + .dw 0x57c0, 0xc18c, 0x57ff, 0xc18c, 0x21, 0 + .dw 0x5840, 0xc18c, 0x587f, 0xc18c, 0x21, 0 + .dw 0x58c0, 0xc18c, 0x58ff, 0xc18c, 0x21, 0 + .dw 0x5940, 0xc18c, 0x597f, 0xc18c, 0x21, 0 + .dw 0x59c0, 0xc18c, 0x5fff, 0xc18c, 0x21, 0 + .dw 0x6040, 0xc18c, 0x607f, 0xc18c, 0x21, 0 + .dw 0x60c0, 0xc18c, 0x60ff, 0xc18c, 0x21, 0 + .dw 0x6140, 0xc18c, 0x617f, 0xc18c, 0x21, 0 + .dw 0x61c0, 0xc18c, 0x61ff, 0xc18c, 0x21, 0 + .dw 0x6240, 0xc18c, 0x627f, 0xc18c, 0x21, 0 + .dw 0x62c0, 0xc18c, 0x62ff, 0xc18c, 0x21, 0 + .dw 0x6340, 0xc18c, 0x637f, 0xc18c, 0x21, 0 + .dw 0x63c0, 0xc18c, 0x63ff, 0xc18c, 0x21, 0 + .dw 0x6440, 0xc18c, 0x647f, 0xc18c, 0x21, 0 + .dw 0x64c0, 0xc18c, 0x64ff, 0xc18c, 0x21, 0 + .dw 0x6540, 0xc18c, 0x657f, 0xc18c, 0x21, 0 + .dw 0x65c0, 0xc18c, 0x65ff, 0xc18c, 0x21, 0 + .dw 0x6640, 0xc18c, 0x667f, 0xc18c, 0x21, 0 + .dw 0x66c0, 0xc18c, 0x66ff, 0xc18c, 0x21, 0 + .dw 0x6740, 0xc18c, 0x677f, 0xc18c, 0x21, 0 + .dw 0x67c0, 0xc18c, 0x67ff, 0xc18c, 0x21, 0 + .dw 0x6840, 0xc18c, 0x687f, 0xc18c, 0x21, 0 + .dw 0x68c0, 0xc18c, 0x68ff, 0xc18c, 0x21, 0 + .dw 0x6940, 0xc18c, 0x697f, 0xc18c, 0x21, 0 + .dw 0x69c0, 0xc18c, 0x69ff, 0xc18c, 0x21, 0 + .dw 0x6a40, 0xc18c, 0x6a7f, 0xc18c, 0x21, 0 + .dw 0x6ac0, 0xc18c, 0x6aff, 0xc18c, 0x21, 0 + .dw 0x6b40, 0xc18c, 0x6b7f, 0xc18c, 0x21, 0 + .dw 0x6bc0, 0xc18c, 0x6bff, 0xc18c, 0x21, 0 + .dw 0x6c40, 0xc18c, 0x6c7f, 0xc18c, 0x21, 0 + .dw 0x6cc0, 0xc18c, 0x6cff, 0xc18c, 0x21, 0 + .dw 0x6d40, 0xc18c, 0x6d7f, 0xc18c, 0x21, 0 + .dw 0x6dc0, 0xc18c, 0x6dff, 0xc18c, 0x21, 0 + .dw 0x6e40, 0xc18c, 0x6e7f, 0xc18c, 0x21, 0 + .dw 0x6ec0, 0xc18c, 0x6eff, 0xc18c, 0x21, 0 + .dw 0x6f40, 0xc18c, 0x6f7f, 0xc18c, 0x21, 0 + .dw 0x6fc0, 0xc18c, 0x6fff, 0xc18c, 0x21, 0 + .dw 0x7040, 0xc18c, 0x707f, 0xc18c, 0x21, 0 + .dw 0x70c0, 0xc18c, 0x70ff, 0xc18c, 0x21, 0 + .dw 0x7140, 0xc18c, 0x717f, 0xc18c, 0x21, 0 + .dw 0x71c0, 0xc18c, 0x71ff, 0xc18c, 0x21, 0 + .dw 0x7240, 0xc18c, 0x727f, 0xc18c, 0x21, 0 + .dw 0x72c0, 0xc18c, 0x72ff, 0xc18c, 0x21, 0 + .dw 0x7340, 0xc18c, 0x737f, 0xc18c, 0x21, 0 + .dw 0x73c0, 0xc18c, 0x73ff, 0xc18c, 0x21, 0 + .dw 0x7440, 0xc18c, 0x747f, 0xc18c, 0x21, 0 + .dw 0x74c0, 0xc18c, 0x74ff, 0xc18c, 0x21, 0 + .dw 0x7540, 0xc18c, 0x757f, 0xc18c, 0x21, 0 + .dw 0x75c0, 0xc18c, 0x75ff, 0xc18c, 0x21, 0 + .dw 0x7640, 0xc18c, 0x767f, 0xc18c, 0x21, 0 + .dw 0x76c0, 0xc18c, 0x76ff, 0xc18c, 0x21, 0 + .dw 0x7740, 0xc18c, 0x777f, 0xc18c, 0x21, 0 + .dw 0x77c0, 0xc18c, 0x77ff, 0xc18c, 0x21, 0 + .dw 0x7840, 0xc18c, 0x787f, 0xc18c, 0x21, 0 + .dw 0x78c0, 0xc18c, 0x78ff, 0xc18c, 0x21, 0 + .dw 0x7940, 0xc18c, 0x797f, 0xc18c, 0x21, 0 + .dw 0x79c0, 0xc18c, 0x7fff, 0xc18c, 0x21, 0 + .dw 0x8040, 0xc18c, 0x807f, 0xc18c, 0x21, 0 + .dw 0x80c0, 0xc18c, 0x80ff, 0xc18c, 0x21, 0 + .dw 0x8140, 0xc18c, 0x817f, 0xc18c, 0x21, 0 + .dw 0x81c0, 0xc18c, 0x81ff, 0xc18c, 0x21, 0 + .dw 0x8240, 0xc18c, 0x827f, 0xc18c, 0x21, 0 + .dw 0x82c0, 0xc18c, 0x82ff, 0xc18c, 0x21, 0 + .dw 0x8340, 0xc18c, 0x837f, 0xc18c, 0x21, 0 + .dw 0x83c0, 0xc18c, 0x83ff, 0xc18c, 0x21, 0 + .dw 0x8440, 0xc18c, 0x847f, 0xc18c, 0x21, 0 + .dw 0x84c0, 0xc18c, 0x84ff, 0xc18c, 0x21, 0 + .dw 0x8540, 0xc18c, 0x857f, 0xc18c, 0x21, 0 + .dw 0x85c0, 0xc18c, 0x85ff, 0xc18c, 0x21, 0 + .dw 0x8640, 0xc18c, 0x867f, 0xc18c, 0x21, 0 + .dw 0x86c0, 0xc18c, 0x86ff, 0xc18c, 0x21, 0 + .dw 0x8740, 0xc18c, 0x877f, 0xc18c, 0x21, 0 + .dw 0x87c0, 0xc18c, 0x87ff, 0xc18c, 0x21, 0 + .dw 0x8840, 0xc18c, 0x887f, 0xc18c, 0x21, 0 + .dw 0x88c0, 0xc18c, 0x88ff, 0xc18c, 0x21, 0 + .dw 0x8940, 0xc18c, 0x897f, 0xc18c, 0x21, 0 + .dw 0x89c0, 0xc18c, 0x89ff, 0xc18c, 0x21, 0 + .dw 0x8a40, 0xc18c, 0x8a7f, 0xc18c, 0x21, 0 + .dw 0x8ac0, 0xc18c, 0x8aff, 0xc18c, 0x21, 0 + .dw 0x8b40, 0xc18c, 0x8b7f, 0xc18c, 0x21, 0 + .dw 0x8bc0, 0xc18c, 0x8bff, 0xc18c, 0x21, 0 + .dw 0x8c40, 0xc18c, 0x8c7f, 0xc18c, 0x21, 0 + .dw 0x8cc0, 0xc18c, 0x8cff, 0xc18c, 0x21, 0 + .dw 0x8d40, 0xc18c, 0x8d7f, 0xc18c, 0x21, 0 + .dw 0x8dc0, 0xc18c, 0x8dff, 0xc18c, 0x21, 0 + .dw 0x8e40, 0xc18c, 0x8e7f, 0xc18c, 0x21, 0 + .dw 0x8ec0, 0xc18c, 0x8eff, 0xc18c, 0x21, 0 + .dw 0x8f40, 0xc18c, 0x8f7f, 0xc18c, 0x21, 0 + .dw 0x8fc0, 0xc18c, 0x8fff, 0xc18c, 0x21, 0 + .dw 0x9040, 0xc18c, 0x907f, 0xc18c, 0x21, 0 + .dw 0x90c0, 0xc18c, 0x90ff, 0xc18c, 0x21, 0 + .dw 0x9140, 0xc18c, 0x917f, 0xc18c, 0x21, 0 + .dw 0x91c0, 0xc18c, 0x91ff, 0xc18c, 0x21, 0 + .dw 0x9240, 0xc18c, 0x927f, 0xc18c, 0x21, 0 + .dw 0x92c0, 0xc18c, 0x92ff, 0xc18c, 0x21, 0 + .dw 0x9340, 0xc18c, 0x937f, 0xc18c, 0x21, 0 + .dw 0x93c0, 0xc18c, 0x93ff, 0xc18c, 0x21, 0 + .dw 0x9440, 0xc18c, 0x947f, 0xc18c, 0x21, 0 + .dw 0x94c0, 0xc18c, 0x94ff, 0xc18c, 0x21, 0 + .dw 0x9540, 0xc18c, 0x957f, 0xc18c, 0x21, 0 + .dw 0x95c0, 0xc18c, 0x95ff, 0xc18c, 0x21, 0 + .dw 0x9640, 0xc18c, 0x967f, 0xc18c, 0x21, 0 + .dw 0x96c0, 0xc18c, 0x96ff, 0xc18c, 0x21, 0 + .dw 0x9740, 0xc18c, 0x977f, 0xc18c, 0x21, 0 + .dw 0x97c0, 0xc18c, 0x97ff, 0xc18c, 0x21, 0 + .dw 0x9840, 0xc18c, 0x987f, 0xc18c, 0x21, 0 + .dw 0x98c0, 0xc18c, 0x98ff, 0xc18c, 0x21, 0 + .dw 0x9940, 0xc18c, 0x997f, 0xc18c, 0x21, 0 + .dw 0x99c0, 0xc18c, 0x9fff, 0xc18c, 0x21, 0 + .dw 0xa040, 0xc18c, 0xa07f, 0xc18c, 0x21, 0 + .dw 0xa0c0, 0xc18c, 0xa0ff, 0xc18c, 0x21, 0 + .dw 0xa140, 0xc18c, 0xa17f, 0xc18c, 0x21, 0 + .dw 0xa1c0, 0xc18c, 0xa1ff, 0xc18c, 0x21, 0 + .dw 0xa240, 0xc18c, 0xa27f, 0xc18c, 0x21, 0 + .dw 0xa2c0, 0xc18c, 0xa2ff, 0xc18c, 0x21, 0 + .dw 0xa340, 0xc18c, 0xa37f, 0xc18c, 0x21, 0 + .dw 0xa3c0, 0xc18c, 0xa3ff, 0xc18c, 0x21, 0 + .dw 0xa440, 0xc18c, 0xa47f, 0xc18c, 0x21, 0 + .dw 0xa4c0, 0xc18c, 0xa4ff, 0xc18c, 0x21, 0 + .dw 0xa540, 0xc18c, 0xa57f, 0xc18c, 0x21, 0 + .dw 0xa5c0, 0xc18c, 0xa5ff, 0xc18c, 0x21, 0 + .dw 0xa640, 0xc18c, 0xa67f, 0xc18c, 0x21, 0 + .dw 0xa6c0, 0xc18c, 0xa6ff, 0xc18c, 0x21, 0 + .dw 0xa740, 0xc18c, 0xa77f, 0xc18c, 0x21, 0 + .dw 0xa7c0, 0xc18c, 0xa7ff, 0xc18c, 0x21, 0 + .dw 0xa840, 0xc18c, 0xa87f, 0xc18c, 0x21, 0 + .dw 0xa8c0, 0xc18c, 0xa8ff, 0xc18c, 0x21, 0 + .dw 0xa940, 0xc18c, 0xa97f, 0xc18c, 0x21, 0 + .dw 0xa9c0, 0xc18c, 0xa9ff, 0xc18c, 0x21, 0 + .dw 0xaa40, 0xc18c, 0xaa7f, 0xc18c, 0x21, 0 + .dw 0xaac0, 0xc18c, 0xaaff, 0xc18c, 0x21, 0 + .dw 0xab40, 0xc18c, 0xab7f, 0xc18c, 0x21, 0 + .dw 0xabc0, 0xc18c, 0xabff, 0xc18c, 0x21, 0 + .dw 0xac40, 0xc18c, 0xac7f, 0xc18c, 0x21, 0 + .dw 0xacc0, 0xc18c, 0xacff, 0xc18c, 0x21, 0 + .dw 0xad40, 0xc18c, 0xad7f, 0xc18c, 0x21, 0 + .dw 0xadc0, 0xc18c, 0xadff, 0xc18c, 0x21, 0 + .dw 0xae40, 0xc18c, 0xae7f, 0xc18c, 0x21, 0 + .dw 0xaec0, 0xc18c, 0xaeff, 0xc18c, 0x21, 0 + .dw 0xaf40, 0xc18c, 0xaf7f, 0xc18c, 0x21, 0 + .dw 0xafc0, 0xc18c, 0xafff, 0xc18c, 0x21, 0 + .dw 0xb040, 0xc18c, 0xb07f, 0xc18c, 0x21, 0 + .dw 0xb0c0, 0xc18c, 0xb0ff, 0xc18c, 0x21, 0 + .dw 0xb140, 0xc18c, 0xb17f, 0xc18c, 0x21, 0 + .dw 0xb1c0, 0xc18c, 0xb1ff, 0xc18c, 0x21, 0 + .dw 0xb240, 0xc18c, 0xb27f, 0xc18c, 0x21, 0 + .dw 0xb2c0, 0xc18c, 0xb2ff, 0xc18c, 0x21, 0 + .dw 0xb340, 0xc18c, 0xb37f, 0xc18c, 0x21, 0 + .dw 0xb3c0, 0xc18c, 0xb3ff, 0xc18c, 0x21, 0 + .dw 0xb440, 0xc18c, 0xb47f, 0xc18c, 0x21, 0 + .dw 0xb4c0, 0xc18c, 0xb4ff, 0xc18c, 0x21, 0 + .dw 0xb540, 0xc18c, 0xb57f, 0xc18c, 0x21, 0 + .dw 0xb5c0, 0xc18c, 0xb5ff, 0xc18c, 0x21, 0 + .dw 0xb640, 0xc18c, 0xb67f, 0xc18c, 0x21, 0 + .dw 0xb6c0, 0xc18c, 0xb6ff, 0xc18c, 0x21, 0 + .dw 0xb740, 0xc18c, 0xb77f, 0xc18c, 0x21, 0 + .dw 0xb7c0, 0xc18c, 0xb7ff, 0xc18c, 0x21, 0 + .dw 0xb840, 0xc18c, 0xb87f, 0xc18c, 0x21, 0 + .dw 0xb8c0, 0xc18c, 0xb8ff, 0xc18c, 0x21, 0 + .dw 0xb940, 0xc18c, 0xb97f, 0xc18c, 0x21, 0 + .dw 0xb9c0, 0xc18c, 0xbfff, 0xc18c, 0x21, 0 + .dw 0xc040, 0xc18c, 0xc07f, 0xc18c, 0x21, 0 + .dw 0xc0c0, 0xc18c, 0xc0ff, 0xc18c, 0x21, 0 + .dw 0xc140, 0xc18c, 0xc17f, 0xc18c, 0x21, 0 + .dw 0xc1c0, 0xc18c, 0xc1ff, 0xc18c, 0x21, 0 + .dw 0xc240, 0xc18c, 0xc27f, 0xc18c, 0x21, 0 + .dw 0xc2c0, 0xc18c, 0xc2ff, 0xc18c, 0x21, 0 + .dw 0xc340, 0xc18c, 0xc37f, 0xc18c, 0x21, 0 + .dw 0xc3c0, 0xc18c, 0xc3ff, 0xc18c, 0x21, 0 + .dw 0xc440, 0xc18c, 0xc47f, 0xc18c, 0x21, 0 + .dw 0xc4c0, 0xc18c, 0xc4ff, 0xc18c, 0x21, 0 + .dw 0xc540, 0xc18c, 0xc57f, 0xc18c, 0x21, 0 + .dw 0xc5c0, 0xc18c, 0xc5ff, 0xc18c, 0x21, 0 + .dw 0xc640, 0xc18c, 0xc67f, 0xc18c, 0x21, 0 + .dw 0xc6c0, 0xc18c, 0xc6ff, 0xc18c, 0x21, 0 + .dw 0xc740, 0xc18c, 0xc77f, 0xc18c, 0x21, 0 + .dw 0xc7c0, 0xc18c, 0xc7ff, 0xc18c, 0x21, 0 + .dw 0xc840, 0xc18c, 0xc87f, 0xc18c, 0x21, 0 + .dw 0xc8c0, 0xc18c, 0xc8ff, 0xc18c, 0x21, 0 + .dw 0xc940, 0xc18c, 0xc97f, 0xc18c, 0x21, 0 + .dw 0xc9c0, 0xc18c, 0xc9ff, 0xc18c, 0x21, 0 + .dw 0xca40, 0xc18c, 0xca7f, 0xc18c, 0x21, 0 + .dw 0xcac0, 0xc18c, 0xcaff, 0xc18c, 0x21, 0 + .dw 0xcb40, 0xc18c, 0xcb7f, 0xc18c, 0x21, 0 + .dw 0xcbc0, 0xc18c, 0xcbff, 0xc18c, 0x21, 0 + .dw 0xcc40, 0xc18c, 0xcc7f, 0xc18c, 0x21, 0 + .dw 0xccc0, 0xc18c, 0xccff, 0xc18c, 0x21, 0 + .dw 0xcd40, 0xc18c, 0xcd7f, 0xc18c, 0x21, 0 + .dw 0xcdc0, 0xc18c, 0xcdff, 0xc18c, 0x21, 0 + .dw 0xce40, 0xc18c, 0xce7f, 0xc18c, 0x21, 0 + .dw 0xcec0, 0xc18c, 0xceff, 0xc18c, 0x21, 0 + .dw 0xcf40, 0xc18c, 0xcf7f, 0xc18c, 0x21, 0 + .dw 0xcfc0, 0xc18c, 0xcfff, 0xc18c, 0x21, 0 + .dw 0xd040, 0xc18c, 0xd07f, 0xc18c, 0x21, 0 + .dw 0xd0c0, 0xc18c, 0xd0ff, 0xc18c, 0x21, 0 + .dw 0xd140, 0xc18c, 0xd17f, 0xc18c, 0x21, 0 + .dw 0xd1c0, 0xc18c, 0xd1ff, 0xc18c, 0x21, 0 + .dw 0xd240, 0xc18c, 0xd27f, 0xc18c, 0x21, 0 + .dw 0xd2c0, 0xc18c, 0xd2ff, 0xc18c, 0x21, 0 + .dw 0xd340, 0xc18c, 0xd37f, 0xc18c, 0x21, 0 + .dw 0xd3c0, 0xc18c, 0xd3ff, 0xc18c, 0x21, 0 + .dw 0xd440, 0xc18c, 0xd47f, 0xc18c, 0x21, 0 + .dw 0xd4c0, 0xc18c, 0xd4ff, 0xc18c, 0x21, 0 + .dw 0xd540, 0xc18c, 0xd57f, 0xc18c, 0x21, 0 + .dw 0xd5c0, 0xc18c, 0xd5ff, 0xc18c, 0x21, 0 + .dw 0xd640, 0xc18c, 0xd67f, 0xc18c, 0x21, 0 + .dw 0xd6c0, 0xc18c, 0xd6ff, 0xc18c, 0x21, 0 + .dw 0xd740, 0xc18c, 0xd77f, 0xc18c, 0x21, 0 + .dw 0xd7c0, 0xc18c, 0xd7ff, 0xc18c, 0x21, 0 + .dw 0xd840, 0xc18c, 0xd87f, 0xc18c, 0x21, 0 + .dw 0xd8c0, 0xc18c, 0xd8ff, 0xc18c, 0x21, 0 + .dw 0xd940, 0xc18c, 0xd97f, 0xc18c, 0x21, 0 + .dw 0xd9c0, 0xc18c, 0xdfff, 0xc18c, 0x21, 0 + .dw 0xe040, 0xc18c, 0xe07f, 0xc18c, 0x21, 0 + .dw 0xe0c0, 0xc18c, 0xe0ff, 0xc18c, 0x21, 0 + .dw 0xe140, 0xc18c, 0xe17f, 0xc18c, 0x21, 0 + .dw 0xe1c0, 0xc18c, 0xe1ff, 0xc18c, 0x21, 0 + .dw 0xe240, 0xc18c, 0xe27f, 0xc18c, 0x21, 0 + .dw 0xe2c0, 0xc18c, 0xe2ff, 0xc18c, 0x21, 0 + .dw 0xe340, 0xc18c, 0xe37f, 0xc18c, 0x21, 0 + .dw 0xe3c0, 0xc18c, 0xe3ff, 0xc18c, 0x21, 0 + .dw 0xe440, 0xc18c, 0xe47f, 0xc18c, 0x21, 0 + .dw 0xe4c0, 0xc18c, 0xe4ff, 0xc18c, 0x21, 0 + .dw 0xe540, 0xc18c, 0xe57f, 0xc18c, 0x21, 0 + .dw 0xe5c0, 0xc18c, 0xe5ff, 0xc18c, 0x21, 0 + .dw 0xe640, 0xc18c, 0xe67f, 0xc18c, 0x21, 0 + .dw 0xe6c0, 0xc18c, 0xe6ff, 0xc18c, 0x21, 0 + .dw 0xe740, 0xc18c, 0xe77f, 0xc18c, 0x21, 0 + .dw 0xe7c0, 0xc18c, 0xe7ff, 0xc18c, 0x21, 0 + .dw 0xe840, 0xc18c, 0xe87f, 0xc18c, 0x21, 0 + .dw 0xe8c0, 0xc18c, 0xe8ff, 0xc18c, 0x21, 0 + .dw 0xe940, 0xc18c, 0xe97f, 0xc18c, 0x21, 0 + .dw 0xe9c0, 0xc18c, 0xe9ff, 0xc18c, 0x21, 0 + .dw 0xea40, 0xc18c, 0xea7f, 0xc18c, 0x21, 0 + .dw 0xeac0, 0xc18c, 0xeaff, 0xc18c, 0x21, 0 + .dw 0xeb40, 0xc18c, 0xeb7f, 0xc18c, 0x21, 0 + .dw 0xebc0, 0xc18c, 0xebff, 0xc18c, 0x21, 0 + .dw 0xec40, 0xc18c, 0xec7f, 0xc18c, 0x21, 0 + .dw 0xecc0, 0xc18c, 0xecff, 0xc18c, 0x21, 0 + .dw 0xed40, 0xc18c, 0xed7f, 0xc18c, 0x21, 0 + .dw 0xedc0, 0xc18c, 0xedff, 0xc18c, 0x21, 0 + .dw 0xee40, 0xc18c, 0xee7f, 0xc18c, 0x21, 0 + .dw 0xeec0, 0xc18c, 0xeeff, 0xc18c, 0x21, 0 + .dw 0xef40, 0xc18c, 0xef7f, 0xc18c, 0x21, 0 + .dw 0xefc0, 0xc18c, 0xefff, 0xc18c, 0x21, 0 + .dw 0xf040, 0xc18c, 0xf07f, 0xc18c, 0x21, 0 + .dw 0xf0c0, 0xc18c, 0xf0ff, 0xc18c, 0x21, 0 + .dw 0xf140, 0xc18c, 0xf17f, 0xc18c, 0x21, 0 + .dw 0xf1c0, 0xc18c, 0xf1ff, 0xc18c, 0x21, 0 + .dw 0xf240, 0xc18c, 0xf27f, 0xc18c, 0x21, 0 + .dw 0xf2c0, 0xc18c, 0xf2ff, 0xc18c, 0x21, 0 + .dw 0xf340, 0xc18c, 0xf37f, 0xc18c, 0x21, 0 + .dw 0xf3c0, 0xc18c, 0xf3ff, 0xc18c, 0x21, 0 + .dw 0xf440, 0xc18c, 0xf47f, 0xc18c, 0x21, 0 + .dw 0xf4c0, 0xc18c, 0xf4ff, 0xc18c, 0x21, 0 + .dw 0xf540, 0xc18c, 0xf57f, 0xc18c, 0x21, 0 + .dw 0xf5c0, 0xc18c, 0xf5ff, 0xc18c, 0x21, 0 + .dw 0xf640, 0xc18c, 0xf67f, 0xc18c, 0x21, 0 + .dw 0xf6c0, 0xc18c, 0xf6ff, 0xc18c, 0x21, 0 + .dw 0xf740, 0xc18c, 0xf77f, 0xc18c, 0x21, 0 + .dw 0xf7c0, 0xc18c, 0xf7ff, 0xc18c, 0x21, 0 + .dw 0xf840, 0xc18c, 0xf87f, 0xc18c, 0x21, 0 + .dw 0xf8c0, 0xc18c, 0xf8ff, 0xc18c, 0x21, 0 + .dw 0xf940, 0xc18c, 0xf97f, 0xc18c, 0x21, 0 + .dw 0xf9c0, 0xc18c, 0xffff, 0xc18c, 0x21, 0 + .dw 0x0040, 0xc18d, 0x007f, 0xc18d, 0x21, 0 + .dw 0x00c0, 0xc18d, 0x00ff, 0xc18d, 0x21, 0 + .dw 0x0140, 0xc18d, 0x017f, 0xc18d, 0x21, 0 + .dw 0x01c0, 0xc18d, 0x01ff, 0xc18d, 0x21, 0 + .dw 0x0240, 0xc18d, 0x027f, 0xc18d, 0x21, 0 + .dw 0x02c0, 0xc18d, 0x02ff, 0xc18d, 0x21, 0 + .dw 0x0340, 0xc18d, 0x037f, 0xc18d, 0x21, 0 + .dw 0x03c0, 0xc18d, 0x03ff, 0xc18d, 0x21, 0 + .dw 0x0440, 0xc18d, 0x047f, 0xc18d, 0x21, 0 + .dw 0x04c0, 0xc18d, 0x04ff, 0xc18d, 0x21, 0 + .dw 0x0540, 0xc18d, 0x057f, 0xc18d, 0x21, 0 + .dw 0x05c0, 0xc18d, 0x05ff, 0xc18d, 0x21, 0 + .dw 0x0640, 0xc18d, 0x067f, 0xc18d, 0x21, 0 + .dw 0x06c0, 0xc18d, 0x06ff, 0xc18d, 0x21, 0 + .dw 0x0740, 0xc18d, 0x077f, 0xc18d, 0x21, 0 + .dw 0x07c0, 0xc18d, 0x07ff, 0xc18d, 0x21, 0 + .dw 0x0840, 0xc18d, 0x087f, 0xc18d, 0x21, 0 + .dw 0x08c0, 0xc18d, 0x08ff, 0xc18d, 0x21, 0 + .dw 0x0940, 0xc18d, 0x097f, 0xc18d, 0x21, 0 + .dw 0x09c0, 0xc18d, 0x09ff, 0xc18d, 0x21, 0 + .dw 0x0a40, 0xc18d, 0x0a7f, 0xc18d, 0x21, 0 + .dw 0x0ac0, 0xc18d, 0x0aff, 0xc18d, 0x21, 0 + .dw 0x0b40, 0xc18d, 0x0b7f, 0xc18d, 0x21, 0 + .dw 0x0bc0, 0xc18d, 0x0bff, 0xc18d, 0x21, 0 + .dw 0x0c40, 0xc18d, 0x0c7f, 0xc18d, 0x21, 0 + .dw 0x0cc0, 0xc18d, 0x0cff, 0xc18d, 0x21, 0 + .dw 0x0d40, 0xc18d, 0x0d7f, 0xc18d, 0x21, 0 + .dw 0x0dc0, 0xc18d, 0x0dff, 0xc18d, 0x21, 0 + .dw 0x0e40, 0xc18d, 0x0e7f, 0xc18d, 0x21, 0 + .dw 0x0ec0, 0xc18d, 0x0eff, 0xc18d, 0x21, 0 + .dw 0x0f40, 0xc18d, 0x0f7f, 0xc18d, 0x21, 0 + .dw 0x0fc0, 0xc18d, 0x0fff, 0xc18d, 0x21, 0 + .dw 0x1040, 0xc18d, 0x107f, 0xc18d, 0x21, 0 + .dw 0x10c0, 0xc18d, 0x10ff, 0xc18d, 0x21, 0 + .dw 0x1140, 0xc18d, 0x117f, 0xc18d, 0x21, 0 + .dw 0x11c0, 0xc18d, 0x11ff, 0xc18d, 0x21, 0 + .dw 0x1240, 0xc18d, 0x127f, 0xc18d, 0x21, 0 + .dw 0x12c0, 0xc18d, 0x12ff, 0xc18d, 0x21, 0 + .dw 0x1340, 0xc18d, 0x137f, 0xc18d, 0x21, 0 + .dw 0x13c0, 0xc18d, 0x13ff, 0xc18d, 0x21, 0 + .dw 0x1440, 0xc18d, 0x147f, 0xc18d, 0x21, 0 + .dw 0x14c0, 0xc18d, 0x14ff, 0xc18d, 0x21, 0 + .dw 0x1540, 0xc18d, 0x157f, 0xc18d, 0x21, 0 + .dw 0x15c0, 0xc18d, 0x15ff, 0xc18d, 0x21, 0 + .dw 0x1640, 0xc18d, 0x167f, 0xc18d, 0x21, 0 + .dw 0x16c0, 0xc18d, 0x16ff, 0xc18d, 0x21, 0 + .dw 0x1740, 0xc18d, 0x177f, 0xc18d, 0x21, 0 + .dw 0x17c0, 0xc18d, 0x17ff, 0xc18d, 0x21, 0 + .dw 0x1840, 0xc18d, 0x187f, 0xc18d, 0x21, 0 + .dw 0x18c0, 0xc18d, 0x18ff, 0xc18d, 0x21, 0 + .dw 0x1940, 0xc18d, 0x197f, 0xc18d, 0x21, 0 + .dw 0x19c0, 0xc18d, 0x1fff, 0xc18d, 0x21, 0 + .dw 0x2040, 0xc18d, 0x207f, 0xc18d, 0x21, 0 + .dw 0x20c0, 0xc18d, 0x20ff, 0xc18d, 0x21, 0 + .dw 0x2140, 0xc18d, 0x217f, 0xc18d, 0x21, 0 + .dw 0x21c0, 0xc18d, 0x21ff, 0xc18d, 0x21, 0 + .dw 0x2240, 0xc18d, 0x227f, 0xc18d, 0x21, 0 + .dw 0x22c0, 0xc18d, 0x22ff, 0xc18d, 0x21, 0 + .dw 0x2340, 0xc18d, 0x237f, 0xc18d, 0x21, 0 + .dw 0x23c0, 0xc18d, 0x23ff, 0xc18d, 0x21, 0 + .dw 0x2440, 0xc18d, 0x247f, 0xc18d, 0x21, 0 + .dw 0x24c0, 0xc18d, 0x24ff, 0xc18d, 0x21, 0 + .dw 0x2540, 0xc18d, 0x257f, 0xc18d, 0x21, 0 + .dw 0x25c0, 0xc18d, 0x25ff, 0xc18d, 0x21, 0 + .dw 0x2640, 0xc18d, 0x267f, 0xc18d, 0x21, 0 + .dw 0x26c0, 0xc18d, 0x26ff, 0xc18d, 0x21, 0 + .dw 0x2740, 0xc18d, 0x277f, 0xc18d, 0x21, 0 + .dw 0x27c0, 0xc18d, 0x27ff, 0xc18d, 0x21, 0 + .dw 0x2840, 0xc18d, 0x287f, 0xc18d, 0x21, 0 + .dw 0x28c0, 0xc18d, 0x28ff, 0xc18d, 0x21, 0 + .dw 0x2940, 0xc18d, 0x297f, 0xc18d, 0x21, 0 + .dw 0x29c0, 0xc18d, 0x29ff, 0xc18d, 0x21, 0 + .dw 0x2a40, 0xc18d, 0x2a7f, 0xc18d, 0x21, 0 + .dw 0x2ac0, 0xc18d, 0x2aff, 0xc18d, 0x21, 0 + .dw 0x2b40, 0xc18d, 0x2b7f, 0xc18d, 0x21, 0 + .dw 0x2bc0, 0xc18d, 0x2bff, 0xc18d, 0x21, 0 + .dw 0x2c40, 0xc18d, 0x2c7f, 0xc18d, 0x21, 0 + .dw 0x2cc0, 0xc18d, 0x2cff, 0xc18d, 0x21, 0 + .dw 0x2d40, 0xc18d, 0x2d7f, 0xc18d, 0x21, 0 + .dw 0x2dc0, 0xc18d, 0x2dff, 0xc18d, 0x21, 0 + .dw 0x2e40, 0xc18d, 0x2e7f, 0xc18d, 0x21, 0 + .dw 0x2ec0, 0xc18d, 0x2eff, 0xc18d, 0x21, 0 + .dw 0x2f40, 0xc18d, 0x2f7f, 0xc18d, 0x21, 0 + .dw 0x2fc0, 0xc18d, 0x2fff, 0xc18d, 0x21, 0 + .dw 0x3040, 0xc18d, 0x307f, 0xc18d, 0x21, 0 + .dw 0x30c0, 0xc18d, 0x30ff, 0xc18d, 0x21, 0 + .dw 0x3140, 0xc18d, 0x317f, 0xc18d, 0x21, 0 + .dw 0x31c0, 0xc18d, 0x31ff, 0xc18d, 0x21, 0 + .dw 0x3240, 0xc18d, 0x327f, 0xc18d, 0x21, 0 + .dw 0x32c0, 0xc18d, 0x32ff, 0xc18d, 0x21, 0 + .dw 0x3340, 0xc18d, 0x337f, 0xc18d, 0x21, 0 + .dw 0x33c0, 0xc18d, 0x33ff, 0xc18d, 0x21, 0 + .dw 0x3440, 0xc18d, 0x347f, 0xc18d, 0x21, 0 + .dw 0x34c0, 0xc18d, 0x34ff, 0xc18d, 0x21, 0 + .dw 0x3540, 0xc18d, 0x357f, 0xc18d, 0x21, 0 + .dw 0x35c0, 0xc18d, 0x35ff, 0xc18d, 0x21, 0 + .dw 0x3640, 0xc18d, 0x367f, 0xc18d, 0x21, 0 + .dw 0x36c0, 0xc18d, 0x36ff, 0xc18d, 0x21, 0 + .dw 0x3740, 0xc18d, 0x377f, 0xc18d, 0x21, 0 + .dw 0x37c0, 0xc18d, 0x37ff, 0xc18d, 0x21, 0 + .dw 0x3840, 0xc18d, 0x387f, 0xc18d, 0x21, 0 + .dw 0x38c0, 0xc18d, 0x38ff, 0xc18d, 0x21, 0 + .dw 0x3940, 0xc18d, 0x397f, 0xc18d, 0x21, 0 + .dw 0x39c0, 0xc18d, 0x3fff, 0xc18d, 0x21, 0 + .dw 0x4040, 0xc18d, 0x407f, 0xc18d, 0x21, 0 + .dw 0x40c0, 0xc18d, 0x40ff, 0xc18d, 0x21, 0 + .dw 0x4140, 0xc18d, 0x417f, 0xc18d, 0x21, 0 + .dw 0x41c0, 0xc18d, 0x41ff, 0xc18d, 0x21, 0 + .dw 0x4240, 0xc18d, 0x427f, 0xc18d, 0x21, 0 + .dw 0x42c0, 0xc18d, 0x42ff, 0xc18d, 0x21, 0 + .dw 0x4340, 0xc18d, 0x437f, 0xc18d, 0x21, 0 + .dw 0x43c0, 0xc18d, 0x43ff, 0xc18d, 0x21, 0 + .dw 0x4440, 0xc18d, 0x447f, 0xc18d, 0x21, 0 + .dw 0x44c0, 0xc18d, 0x44ff, 0xc18d, 0x21, 0 + .dw 0x4540, 0xc18d, 0x457f, 0xc18d, 0x21, 0 + .dw 0x45c0, 0xc18d, 0x45ff, 0xc18d, 0x21, 0 + .dw 0x4640, 0xc18d, 0x467f, 0xc18d, 0x21, 0 + .dw 0x46c0, 0xc18d, 0x46ff, 0xc18d, 0x21, 0 + .dw 0x4740, 0xc18d, 0x477f, 0xc18d, 0x21, 0 + .dw 0x47c0, 0xc18d, 0x47ff, 0xc18d, 0x21, 0 + .dw 0x4840, 0xc18d, 0x487f, 0xc18d, 0x21, 0 + .dw 0x48c0, 0xc18d, 0x48ff, 0xc18d, 0x21, 0 + .dw 0x4940, 0xc18d, 0x497f, 0xc18d, 0x21, 0 + .dw 0x49c0, 0xc18d, 0x49ff, 0xc18d, 0x21, 0 + .dw 0x4a40, 0xc18d, 0x4a7f, 0xc18d, 0x21, 0 + .dw 0x4ac0, 0xc18d, 0x4aff, 0xc18d, 0x21, 0 + .dw 0x4b40, 0xc18d, 0x4b7f, 0xc18d, 0x21, 0 + .dw 0x4bc0, 0xc18d, 0x4bff, 0xc18d, 0x21, 0 + .dw 0x4c40, 0xc18d, 0x4c7f, 0xc18d, 0x21, 0 + .dw 0x4cc0, 0xc18d, 0x4cff, 0xc18d, 0x21, 0 + .dw 0x4d40, 0xc18d, 0x4d7f, 0xc18d, 0x21, 0 + .dw 0x4dc0, 0xc18d, 0x4dff, 0xc18d, 0x21, 0 + .dw 0x4e40, 0xc18d, 0x4e7f, 0xc18d, 0x21, 0 + .dw 0x4ec0, 0xc18d, 0x4eff, 0xc18d, 0x21, 0 + .dw 0x4f40, 0xc18d, 0x4f7f, 0xc18d, 0x21, 0 + .dw 0x4fc0, 0xc18d, 0x4fff, 0xc18d, 0x21, 0 + .dw 0x5040, 0xc18d, 0x507f, 0xc18d, 0x21, 0 + .dw 0x50c0, 0xc18d, 0x50ff, 0xc18d, 0x21, 0 + .dw 0x5140, 0xc18d, 0x517f, 0xc18d, 0x21, 0 + .dw 0x51c0, 0xc18d, 0x51ff, 0xc18d, 0x21, 0 + .dw 0x5240, 0xc18d, 0x527f, 0xc18d, 0x21, 0 + .dw 0x52c0, 0xc18d, 0x52ff, 0xc18d, 0x21, 0 + .dw 0x5340, 0xc18d, 0x537f, 0xc18d, 0x21, 0 + .dw 0x53c0, 0xc18d, 0x53ff, 0xc18d, 0x21, 0 + .dw 0x5440, 0xc18d, 0x547f, 0xc18d, 0x21, 0 + .dw 0x54c0, 0xc18d, 0x54ff, 0xc18d, 0x21, 0 + .dw 0x5540, 0xc18d, 0x557f, 0xc18d, 0x21, 0 + .dw 0x55c0, 0xc18d, 0x55ff, 0xc18d, 0x21, 0 + .dw 0x5640, 0xc18d, 0x567f, 0xc18d, 0x21, 0 + .dw 0x56c0, 0xc18d, 0x56ff, 0xc18d, 0x21, 0 + .dw 0x5740, 0xc18d, 0x577f, 0xc18d, 0x21, 0 + .dw 0x57c0, 0xc18d, 0x57ff, 0xc18d, 0x21, 0 + .dw 0x5840, 0xc18d, 0x587f, 0xc18d, 0x21, 0 + .dw 0x58c0, 0xc18d, 0x58ff, 0xc18d, 0x21, 0 + .dw 0x5940, 0xc18d, 0x597f, 0xc18d, 0x21, 0 + .dw 0x59c0, 0xc18d, 0x5fff, 0xc18d, 0x21, 0 + .dw 0x6040, 0xc18d, 0x607f, 0xc18d, 0x21, 0 + .dw 0x60c0, 0xc18d, 0x60ff, 0xc18d, 0x21, 0 + .dw 0x6140, 0xc18d, 0x617f, 0xc18d, 0x21, 0 + .dw 0x61c0, 0xc18d, 0x61ff, 0xc18d, 0x21, 0 + .dw 0x6240, 0xc18d, 0x627f, 0xc18d, 0x21, 0 + .dw 0x62c0, 0xc18d, 0x62ff, 0xc18d, 0x21, 0 + .dw 0x6340, 0xc18d, 0x637f, 0xc18d, 0x21, 0 + .dw 0x63c0, 0xc18d, 0x63ff, 0xc18d, 0x21, 0 + .dw 0x6440, 0xc18d, 0x647f, 0xc18d, 0x21, 0 + .dw 0x64c0, 0xc18d, 0x64ff, 0xc18d, 0x21, 0 + .dw 0x6540, 0xc18d, 0x657f, 0xc18d, 0x21, 0 + .dw 0x65c0, 0xc18d, 0x65ff, 0xc18d, 0x21, 0 + .dw 0x6640, 0xc18d, 0x667f, 0xc18d, 0x21, 0 + .dw 0x66c0, 0xc18d, 0x66ff, 0xc18d, 0x21, 0 + .dw 0x6740, 0xc18d, 0x677f, 0xc18d, 0x21, 0 + .dw 0x67c0, 0xc18d, 0x67ff, 0xc18d, 0x21, 0 + .dw 0x6840, 0xc18d, 0x687f, 0xc18d, 0x21, 0 + .dw 0x68c0, 0xc18d, 0x68ff, 0xc18d, 0x21, 0 + .dw 0x6940, 0xc18d, 0x697f, 0xc18d, 0x21, 0 + .dw 0x69c0, 0xc18d, 0x69ff, 0xc18d, 0x21, 0 + .dw 0x6a40, 0xc18d, 0x6a7f, 0xc18d, 0x21, 0 + .dw 0x6ac0, 0xc18d, 0x6aff, 0xc18d, 0x21, 0 + .dw 0x6b40, 0xc18d, 0x6b7f, 0xc18d, 0x21, 0 + .dw 0x6bc0, 0xc18d, 0x6bff, 0xc18d, 0x21, 0 + .dw 0x6c40, 0xc18d, 0x6c7f, 0xc18d, 0x21, 0 + .dw 0x6cc0, 0xc18d, 0x6cff, 0xc18d, 0x21, 0 + .dw 0x6d40, 0xc18d, 0x6d7f, 0xc18d, 0x21, 0 + .dw 0x6dc0, 0xc18d, 0x6dff, 0xc18d, 0x21, 0 + .dw 0x6e40, 0xc18d, 0x6e7f, 0xc18d, 0x21, 0 + .dw 0x6ec0, 0xc18d, 0x6eff, 0xc18d, 0x21, 0 + .dw 0x6f40, 0xc18d, 0x6f7f, 0xc18d, 0x21, 0 + .dw 0x6fc0, 0xc18d, 0x6fff, 0xc18d, 0x21, 0 + .dw 0x7040, 0xc18d, 0x707f, 0xc18d, 0x21, 0 + .dw 0x70c0, 0xc18d, 0x70ff, 0xc18d, 0x21, 0 + .dw 0x7140, 0xc18d, 0x717f, 0xc18d, 0x21, 0 + .dw 0x71c0, 0xc18d, 0x71ff, 0xc18d, 0x21, 0 + .dw 0x7240, 0xc18d, 0x727f, 0xc18d, 0x21, 0 + .dw 0x72c0, 0xc18d, 0x72ff, 0xc18d, 0x21, 0 + .dw 0x7340, 0xc18d, 0x737f, 0xc18d, 0x21, 0 + .dw 0x73c0, 0xc18d, 0x73ff, 0xc18d, 0x21, 0 + .dw 0x7440, 0xc18d, 0x747f, 0xc18d, 0x21, 0 + .dw 0x74c0, 0xc18d, 0x74ff, 0xc18d, 0x21, 0 + .dw 0x7540, 0xc18d, 0x757f, 0xc18d, 0x21, 0 + .dw 0x75c0, 0xc18d, 0x75ff, 0xc18d, 0x21, 0 + .dw 0x7640, 0xc18d, 0x767f, 0xc18d, 0x21, 0 + .dw 0x76c0, 0xc18d, 0x76ff, 0xc18d, 0x21, 0 + .dw 0x7740, 0xc18d, 0x777f, 0xc18d, 0x21, 0 + .dw 0x77c0, 0xc18d, 0x77ff, 0xc18d, 0x21, 0 + .dw 0x7840, 0xc18d, 0x787f, 0xc18d, 0x21, 0 + .dw 0x78c0, 0xc18d, 0x78ff, 0xc18d, 0x21, 0 + .dw 0x7940, 0xc18d, 0x797f, 0xc18d, 0x21, 0 + .dw 0x79c0, 0xc18d, 0x7fff, 0xc18d, 0x21, 0 + .dw 0x8040, 0xc18d, 0x807f, 0xc18d, 0x21, 0 + .dw 0x80c0, 0xc18d, 0x80ff, 0xc18d, 0x21, 0 + .dw 0x8140, 0xc18d, 0x817f, 0xc18d, 0x21, 0 + .dw 0x81c0, 0xc18d, 0x81ff, 0xc18d, 0x21, 0 + .dw 0x8240, 0xc18d, 0x827f, 0xc18d, 0x21, 0 + .dw 0x82c0, 0xc18d, 0x82ff, 0xc18d, 0x21, 0 + .dw 0x8340, 0xc18d, 0x837f, 0xc18d, 0x21, 0 + .dw 0x83c0, 0xc18d, 0x83ff, 0xc18d, 0x21, 0 + .dw 0x8440, 0xc18d, 0x847f, 0xc18d, 0x21, 0 + .dw 0x84c0, 0xc18d, 0x84ff, 0xc18d, 0x21, 0 + .dw 0x8540, 0xc18d, 0x857f, 0xc18d, 0x21, 0 + .dw 0x85c0, 0xc18d, 0x85ff, 0xc18d, 0x21, 0 + .dw 0x8640, 0xc18d, 0x867f, 0xc18d, 0x21, 0 + .dw 0x86c0, 0xc18d, 0x86ff, 0xc18d, 0x21, 0 + .dw 0x8740, 0xc18d, 0x877f, 0xc18d, 0x21, 0 + .dw 0x87c0, 0xc18d, 0x87ff, 0xc18d, 0x21, 0 + .dw 0x8840, 0xc18d, 0x887f, 0xc18d, 0x21, 0 + .dw 0x88c0, 0xc18d, 0x88ff, 0xc18d, 0x21, 0 + .dw 0x8940, 0xc18d, 0x897f, 0xc18d, 0x21, 0 + .dw 0x89c0, 0xc18d, 0x89ff, 0xc18d, 0x21, 0 + .dw 0x8a40, 0xc18d, 0x8a7f, 0xc18d, 0x21, 0 + .dw 0x8ac0, 0xc18d, 0x8aff, 0xc18d, 0x21, 0 + .dw 0x8b40, 0xc18d, 0x8b7f, 0xc18d, 0x21, 0 + .dw 0x8bc0, 0xc18d, 0x8bff, 0xc18d, 0x21, 0 + .dw 0x8c40, 0xc18d, 0x8c7f, 0xc18d, 0x21, 0 + .dw 0x8cc0, 0xc18d, 0x8cff, 0xc18d, 0x21, 0 + .dw 0x8d40, 0xc18d, 0x8d7f, 0xc18d, 0x21, 0 + .dw 0x8dc0, 0xc18d, 0x8dff, 0xc18d, 0x21, 0 + .dw 0x8e40, 0xc18d, 0x8e7f, 0xc18d, 0x21, 0 + .dw 0x8ec0, 0xc18d, 0x8eff, 0xc18d, 0x21, 0 + .dw 0x8f40, 0xc18d, 0x8f7f, 0xc18d, 0x21, 0 + .dw 0x8fc0, 0xc18d, 0x8fff, 0xc18d, 0x21, 0 + .dw 0x9040, 0xc18d, 0x907f, 0xc18d, 0x21, 0 + .dw 0x90c0, 0xc18d, 0x90ff, 0xc18d, 0x21, 0 + .dw 0x9140, 0xc18d, 0x917f, 0xc18d, 0x21, 0 + .dw 0x91c0, 0xc18d, 0x91ff, 0xc18d, 0x21, 0 + .dw 0x9240, 0xc18d, 0x927f, 0xc18d, 0x21, 0 + .dw 0x92c0, 0xc18d, 0x92ff, 0xc18d, 0x21, 0 + .dw 0x9340, 0xc18d, 0x937f, 0xc18d, 0x21, 0 + .dw 0x93c0, 0xc18d, 0x93ff, 0xc18d, 0x21, 0 + .dw 0x9440, 0xc18d, 0x947f, 0xc18d, 0x21, 0 + .dw 0x94c0, 0xc18d, 0x94ff, 0xc18d, 0x21, 0 + .dw 0x9540, 0xc18d, 0x957f, 0xc18d, 0x21, 0 + .dw 0x95c0, 0xc18d, 0x95ff, 0xc18d, 0x21, 0 + .dw 0x9640, 0xc18d, 0x967f, 0xc18d, 0x21, 0 + .dw 0x96c0, 0xc18d, 0x96ff, 0xc18d, 0x21, 0 + .dw 0x9740, 0xc18d, 0x977f, 0xc18d, 0x21, 0 + .dw 0x97c0, 0xc18d, 0x97ff, 0xc18d, 0x21, 0 + .dw 0x9840, 0xc18d, 0x987f, 0xc18d, 0x21, 0 + .dw 0x98c0, 0xc18d, 0x98ff, 0xc18d, 0x21, 0 + .dw 0x9940, 0xc18d, 0x997f, 0xc18d, 0x21, 0 + .dw 0x99c0, 0xc18d, 0x9fff, 0xc18d, 0x21, 0 + .dw 0xa040, 0xc18d, 0xa07f, 0xc18d, 0x21, 0 + .dw 0xa0c0, 0xc18d, 0xa0ff, 0xc18d, 0x21, 0 + .dw 0xa140, 0xc18d, 0xa17f, 0xc18d, 0x21, 0 + .dw 0xa1c0, 0xc18d, 0xa1ff, 0xc18d, 0x21, 0 + .dw 0xa240, 0xc18d, 0xa27f, 0xc18d, 0x21, 0 + .dw 0xa2c0, 0xc18d, 0xa2ff, 0xc18d, 0x21, 0 + .dw 0xa340, 0xc18d, 0xa37f, 0xc18d, 0x21, 0 + .dw 0xa3c0, 0xc18d, 0xa3ff, 0xc18d, 0x21, 0 + .dw 0xa440, 0xc18d, 0xa47f, 0xc18d, 0x21, 0 + .dw 0xa4c0, 0xc18d, 0xa4ff, 0xc18d, 0x21, 0 + .dw 0xa540, 0xc18d, 0xa57f, 0xc18d, 0x21, 0 + .dw 0xa5c0, 0xc18d, 0xa5ff, 0xc18d, 0x21, 0 + .dw 0xa640, 0xc18d, 0xa67f, 0xc18d, 0x21, 0 + .dw 0xa6c0, 0xc18d, 0xa6ff, 0xc18d, 0x21, 0 + .dw 0xa740, 0xc18d, 0xa77f, 0xc18d, 0x21, 0 + .dw 0xa7c0, 0xc18d, 0xa7ff, 0xc18d, 0x21, 0 + .dw 0xa840, 0xc18d, 0xa87f, 0xc18d, 0x21, 0 + .dw 0xa8c0, 0xc18d, 0xa8ff, 0xc18d, 0x21, 0 + .dw 0xa940, 0xc18d, 0xa97f, 0xc18d, 0x21, 0 + .dw 0xa9c0, 0xc18d, 0xa9ff, 0xc18d, 0x21, 0 + .dw 0xaa40, 0xc18d, 0xaa7f, 0xc18d, 0x21, 0 + .dw 0xaac0, 0xc18d, 0xaaff, 0xc18d, 0x21, 0 + .dw 0xab40, 0xc18d, 0xab7f, 0xc18d, 0x21, 0 + .dw 0xabc0, 0xc18d, 0xabff, 0xc18d, 0x21, 0 + .dw 0xac40, 0xc18d, 0xac7f, 0xc18d, 0x21, 0 + .dw 0xacc0, 0xc18d, 0xacff, 0xc18d, 0x21, 0 + .dw 0xad40, 0xc18d, 0xad7f, 0xc18d, 0x21, 0 + .dw 0xadc0, 0xc18d, 0xadff, 0xc18d, 0x21, 0 + .dw 0xae40, 0xc18d, 0xae7f, 0xc18d, 0x21, 0 + .dw 0xaec0, 0xc18d, 0xaeff, 0xc18d, 0x21, 0 + .dw 0xaf40, 0xc18d, 0xaf7f, 0xc18d, 0x21, 0 + .dw 0xafc0, 0xc18d, 0xafff, 0xc18d, 0x21, 0 + .dw 0xb040, 0xc18d, 0xb07f, 0xc18d, 0x21, 0 + .dw 0xb0c0, 0xc18d, 0xb0ff, 0xc18d, 0x21, 0 + .dw 0xb140, 0xc18d, 0xb17f, 0xc18d, 0x21, 0 + .dw 0xb1c0, 0xc18d, 0xb1ff, 0xc18d, 0x21, 0 + .dw 0xb240, 0xc18d, 0xb27f, 0xc18d, 0x21, 0 + .dw 0xb2c0, 0xc18d, 0xb2ff, 0xc18d, 0x21, 0 + .dw 0xb340, 0xc18d, 0xb37f, 0xc18d, 0x21, 0 + .dw 0xb3c0, 0xc18d, 0xb3ff, 0xc18d, 0x21, 0 + .dw 0xb440, 0xc18d, 0xb47f, 0xc18d, 0x21, 0 + .dw 0xb4c0, 0xc18d, 0xb4ff, 0xc18d, 0x21, 0 + .dw 0xb540, 0xc18d, 0xb57f, 0xc18d, 0x21, 0 + .dw 0xb5c0, 0xc18d, 0xb5ff, 0xc18d, 0x21, 0 + .dw 0xb640, 0xc18d, 0xb67f, 0xc18d, 0x21, 0 + .dw 0xb6c0, 0xc18d, 0xb6ff, 0xc18d, 0x21, 0 + .dw 0xb740, 0xc18d, 0xb77f, 0xc18d, 0x21, 0 + .dw 0xb7c0, 0xc18d, 0xb7ff, 0xc18d, 0x21, 0 + .dw 0xb840, 0xc18d, 0xb87f, 0xc18d, 0x21, 0 + .dw 0xb8c0, 0xc18d, 0xb8ff, 0xc18d, 0x21, 0 + .dw 0xb940, 0xc18d, 0xb97f, 0xc18d, 0x21, 0 + .dw 0xb9c0, 0xc18d, 0xbfff, 0xc18d, 0x21, 0 + .dw 0xc040, 0xc18d, 0xc07f, 0xc18d, 0x21, 0 + .dw 0xc0c0, 0xc18d, 0xc0ff, 0xc18d, 0x21, 0 + .dw 0xc140, 0xc18d, 0xc17f, 0xc18d, 0x21, 0 + .dw 0xc1c0, 0xc18d, 0xc1ff, 0xc18d, 0x21, 0 + .dw 0xc240, 0xc18d, 0xc27f, 0xc18d, 0x21, 0 + .dw 0xc2c0, 0xc18d, 0xc2ff, 0xc18d, 0x21, 0 + .dw 0xc340, 0xc18d, 0xc37f, 0xc18d, 0x21, 0 + .dw 0xc3c0, 0xc18d, 0xc3ff, 0xc18d, 0x21, 0 + .dw 0xc440, 0xc18d, 0xc47f, 0xc18d, 0x21, 0 + .dw 0xc4c0, 0xc18d, 0xc4ff, 0xc18d, 0x21, 0 + .dw 0xc540, 0xc18d, 0xc57f, 0xc18d, 0x21, 0 + .dw 0xc5c0, 0xc18d, 0xc5ff, 0xc18d, 0x21, 0 + .dw 0xc640, 0xc18d, 0xc67f, 0xc18d, 0x21, 0 + .dw 0xc6c0, 0xc18d, 0xc6ff, 0xc18d, 0x21, 0 + .dw 0xc740, 0xc18d, 0xc77f, 0xc18d, 0x21, 0 + .dw 0xc7c0, 0xc18d, 0xc7ff, 0xc18d, 0x21, 0 + .dw 0xc840, 0xc18d, 0xc87f, 0xc18d, 0x21, 0 + .dw 0xc8c0, 0xc18d, 0xc8ff, 0xc18d, 0x21, 0 + .dw 0xc940, 0xc18d, 0xc97f, 0xc18d, 0x21, 0 + .dw 0xc9c0, 0xc18d, 0xc9ff, 0xc18d, 0x21, 0 + .dw 0xca40, 0xc18d, 0xca7f, 0xc18d, 0x21, 0 + .dw 0xcac0, 0xc18d, 0xcaff, 0xc18d, 0x21, 0 + .dw 0xcb40, 0xc18d, 0xcb7f, 0xc18d, 0x21, 0 + .dw 0xcbc0, 0xc18d, 0xcbff, 0xc18d, 0x21, 0 + .dw 0xcc40, 0xc18d, 0xcc7f, 0xc18d, 0x21, 0 + .dw 0xccc0, 0xc18d, 0xccff, 0xc18d, 0x21, 0 + .dw 0xcd40, 0xc18d, 0xcd7f, 0xc18d, 0x21, 0 + .dw 0xcdc0, 0xc18d, 0xcdff, 0xc18d, 0x21, 0 + .dw 0xce40, 0xc18d, 0xce7f, 0xc18d, 0x21, 0 + .dw 0xcec0, 0xc18d, 0xceff, 0xc18d, 0x21, 0 + .dw 0xcf40, 0xc18d, 0xcf7f, 0xc18d, 0x21, 0 + .dw 0xcfc0, 0xc18d, 0xcfff, 0xc18d, 0x21, 0 + .dw 0xd040, 0xc18d, 0xd07f, 0xc18d, 0x21, 0 + .dw 0xd0c0, 0xc18d, 0xd0ff, 0xc18d, 0x21, 0 + .dw 0xd140, 0xc18d, 0xd17f, 0xc18d, 0x21, 0 + .dw 0xd1c0, 0xc18d, 0xd1ff, 0xc18d, 0x21, 0 + .dw 0xd240, 0xc18d, 0xd27f, 0xc18d, 0x21, 0 + .dw 0xd2c0, 0xc18d, 0xd2ff, 0xc18d, 0x21, 0 + .dw 0xd340, 0xc18d, 0xd37f, 0xc18d, 0x21, 0 + .dw 0xd3c0, 0xc18d, 0xd3ff, 0xc18d, 0x21, 0 + .dw 0xd440, 0xc18d, 0xd47f, 0xc18d, 0x21, 0 + .dw 0xd4c0, 0xc18d, 0xd4ff, 0xc18d, 0x21, 0 + .dw 0xd540, 0xc18d, 0xd57f, 0xc18d, 0x21, 0 + .dw 0xd5c0, 0xc18d, 0xd5ff, 0xc18d, 0x21, 0 + .dw 0xd640, 0xc18d, 0xd67f, 0xc18d, 0x21, 0 + .dw 0xd6c0, 0xc18d, 0xd6ff, 0xc18d, 0x21, 0 + .dw 0xd740, 0xc18d, 0xd77f, 0xc18d, 0x21, 0 + .dw 0xd7c0, 0xc18d, 0xd7ff, 0xc18d, 0x21, 0 + .dw 0xd840, 0xc18d, 0xd87f, 0xc18d, 0x21, 0 + .dw 0xd8c0, 0xc18d, 0xd8ff, 0xc18d, 0x21, 0 + .dw 0xd940, 0xc18d, 0xd97f, 0xc18d, 0x21, 0 + .dw 0xd9c0, 0xc18d, 0xdfff, 0xc18d, 0x21, 0 + .dw 0xe040, 0xc18d, 0xe07f, 0xc18d, 0x21, 0 + .dw 0xe0c0, 0xc18d, 0xe0ff, 0xc18d, 0x21, 0 + .dw 0xe140, 0xc18d, 0xe17f, 0xc18d, 0x21, 0 + .dw 0xe1c0, 0xc18d, 0xe1ff, 0xc18d, 0x21, 0 + .dw 0xe240, 0xc18d, 0xe27f, 0xc18d, 0x21, 0 + .dw 0xe2c0, 0xc18d, 0xe2ff, 0xc18d, 0x21, 0 + .dw 0xe340, 0xc18d, 0xe37f, 0xc18d, 0x21, 0 + .dw 0xe3c0, 0xc18d, 0xe3ff, 0xc18d, 0x21, 0 + .dw 0xe440, 0xc18d, 0xe47f, 0xc18d, 0x21, 0 + .dw 0xe4c0, 0xc18d, 0xe4ff, 0xc18d, 0x21, 0 + .dw 0xe540, 0xc18d, 0xe57f, 0xc18d, 0x21, 0 + .dw 0xe5c0, 0xc18d, 0xe5ff, 0xc18d, 0x21, 0 + .dw 0xe640, 0xc18d, 0xe67f, 0xc18d, 0x21, 0 + .dw 0xe6c0, 0xc18d, 0xe6ff, 0xc18d, 0x21, 0 + .dw 0xe740, 0xc18d, 0xe77f, 0xc18d, 0x21, 0 + .dw 0xe7c0, 0xc18d, 0xe7ff, 0xc18d, 0x21, 0 + .dw 0xe840, 0xc18d, 0xe87f, 0xc18d, 0x21, 0 + .dw 0xe8c0, 0xc18d, 0xe8ff, 0xc18d, 0x21, 0 + .dw 0xe940, 0xc18d, 0xe97f, 0xc18d, 0x21, 0 + .dw 0xe9c0, 0xc18d, 0xe9ff, 0xc18d, 0x21, 0 + .dw 0xea40, 0xc18d, 0xea7f, 0xc18d, 0x21, 0 + .dw 0xeac0, 0xc18d, 0xeaff, 0xc18d, 0x21, 0 + .dw 0xeb40, 0xc18d, 0xeb7f, 0xc18d, 0x21, 0 + .dw 0xebc0, 0xc18d, 0xebff, 0xc18d, 0x21, 0 + .dw 0xec40, 0xc18d, 0xec7f, 0xc18d, 0x21, 0 + .dw 0xecc0, 0xc18d, 0xecff, 0xc18d, 0x21, 0 + .dw 0xed40, 0xc18d, 0xed7f, 0xc18d, 0x21, 0 + .dw 0xedc0, 0xc18d, 0xedff, 0xc18d, 0x21, 0 + .dw 0xee40, 0xc18d, 0xee7f, 0xc18d, 0x21, 0 + .dw 0xeec0, 0xc18d, 0xeeff, 0xc18d, 0x21, 0 + .dw 0xef40, 0xc18d, 0xef7f, 0xc18d, 0x21, 0 + .dw 0xefc0, 0xc18d, 0xefff, 0xc18d, 0x21, 0 + .dw 0xf040, 0xc18d, 0xf07f, 0xc18d, 0x21, 0 + .dw 0xf0c0, 0xc18d, 0xf0ff, 0xc18d, 0x21, 0 + .dw 0xf140, 0xc18d, 0xf17f, 0xc18d, 0x21, 0 + .dw 0xf1c0, 0xc18d, 0xf1ff, 0xc18d, 0x21, 0 + .dw 0xf240, 0xc18d, 0xf27f, 0xc18d, 0x21, 0 + .dw 0xf2c0, 0xc18d, 0xf2ff, 0xc18d, 0x21, 0 + .dw 0xf340, 0xc18d, 0xf37f, 0xc18d, 0x21, 0 + .dw 0xf3c0, 0xc18d, 0xf3ff, 0xc18d, 0x21, 0 + .dw 0xf440, 0xc18d, 0xf47f, 0xc18d, 0x21, 0 + .dw 0xf4c0, 0xc18d, 0xf4ff, 0xc18d, 0x21, 0 + .dw 0xf540, 0xc18d, 0xf57f, 0xc18d, 0x21, 0 + .dw 0xf5c0, 0xc18d, 0xf5ff, 0xc18d, 0x21, 0 + .dw 0xf640, 0xc18d, 0xf67f, 0xc18d, 0x21, 0 + .dw 0xf6c0, 0xc18d, 0xf6ff, 0xc18d, 0x21, 0 + .dw 0xf740, 0xc18d, 0xf77f, 0xc18d, 0x21, 0 + .dw 0xf7c0, 0xc18d, 0xf7ff, 0xc18d, 0x21, 0 + .dw 0xf840, 0xc18d, 0xf87f, 0xc18d, 0x21, 0 + .dw 0xf8c0, 0xc18d, 0xf8ff, 0xc18d, 0x21, 0 + .dw 0xf940, 0xc18d, 0xf97f, 0xc18d, 0x21, 0 + .dw 0xf9c0, 0xc18d, 0xffff, 0xc18d, 0x21, 0 + .dw 0x0040, 0xc18e, 0x007f, 0xc18e, 0x21, 0 + .dw 0x00c0, 0xc18e, 0x00ff, 0xc18e, 0x21, 0 + .dw 0x0140, 0xc18e, 0x017f, 0xc18e, 0x21, 0 + .dw 0x01c0, 0xc18e, 0x01ff, 0xc18e, 0x21, 0 + .dw 0x0240, 0xc18e, 0x027f, 0xc18e, 0x21, 0 + .dw 0x02c0, 0xc18e, 0x02ff, 0xc18e, 0x21, 0 + .dw 0x0340, 0xc18e, 0x037f, 0xc18e, 0x21, 0 + .dw 0x03c0, 0xc18e, 0x03ff, 0xc18e, 0x21, 0 + .dw 0x0440, 0xc18e, 0x047f, 0xc18e, 0x21, 0 + .dw 0x04c0, 0xc18e, 0x04ff, 0xc18e, 0x21, 0 + .dw 0x0540, 0xc18e, 0x057f, 0xc18e, 0x21, 0 + .dw 0x05c0, 0xc18e, 0x05ff, 0xc18e, 0x21, 0 + .dw 0x0640, 0xc18e, 0x067f, 0xc18e, 0x21, 0 + .dw 0x06c0, 0xc18e, 0x06ff, 0xc18e, 0x21, 0 + .dw 0x0740, 0xc18e, 0x077f, 0xc18e, 0x21, 0 + .dw 0x07c0, 0xc18e, 0x07ff, 0xc18e, 0x21, 0 + .dw 0x0840, 0xc18e, 0x087f, 0xc18e, 0x21, 0 + .dw 0x08c0, 0xc18e, 0x08ff, 0xc18e, 0x21, 0 + .dw 0x0940, 0xc18e, 0x097f, 0xc18e, 0x21, 0 + .dw 0x09c0, 0xc18e, 0x09ff, 0xc18e, 0x21, 0 + .dw 0x0a40, 0xc18e, 0x0a7f, 0xc18e, 0x21, 0 + .dw 0x0ac0, 0xc18e, 0x0aff, 0xc18e, 0x21, 0 + .dw 0x0b40, 0xc18e, 0x0b7f, 0xc18e, 0x21, 0 + .dw 0x0bc0, 0xc18e, 0x0bff, 0xc18e, 0x21, 0 + .dw 0x0c40, 0xc18e, 0x0c7f, 0xc18e, 0x21, 0 + .dw 0x0cc0, 0xc18e, 0x0cff, 0xc18e, 0x21, 0 + .dw 0x0d40, 0xc18e, 0x0d7f, 0xc18e, 0x21, 0 + .dw 0x0dc0, 0xc18e, 0x0dff, 0xc18e, 0x21, 0 + .dw 0x0e40, 0xc18e, 0x0e7f, 0xc18e, 0x21, 0 + .dw 0x0ec0, 0xc18e, 0x0eff, 0xc18e, 0x21, 0 + .dw 0x0f40, 0xc18e, 0x0f7f, 0xc18e, 0x21, 0 + .dw 0x0fc0, 0xc18e, 0x0fff, 0xc18e, 0x21, 0 + .dw 0x1040, 0xc18e, 0x107f, 0xc18e, 0x21, 0 + .dw 0x10c0, 0xc18e, 0x10ff, 0xc18e, 0x21, 0 + .dw 0x1140, 0xc18e, 0x117f, 0xc18e, 0x21, 0 + .dw 0x11c0, 0xc18e, 0x11ff, 0xc18e, 0x21, 0 + .dw 0x1240, 0xc18e, 0x127f, 0xc18e, 0x21, 0 + .dw 0x12c0, 0xc18e, 0x12ff, 0xc18e, 0x21, 0 + .dw 0x1340, 0xc18e, 0x137f, 0xc18e, 0x21, 0 + .dw 0x13c0, 0xc18e, 0x13ff, 0xc18e, 0x21, 0 + .dw 0x1440, 0xc18e, 0x147f, 0xc18e, 0x21, 0 + .dw 0x14c0, 0xc18e, 0x14ff, 0xc18e, 0x21, 0 + .dw 0x1540, 0xc18e, 0x157f, 0xc18e, 0x21, 0 + .dw 0x15c0, 0xc18e, 0x15ff, 0xc18e, 0x21, 0 + .dw 0x1640, 0xc18e, 0x167f, 0xc18e, 0x21, 0 + .dw 0x16c0, 0xc18e, 0x16ff, 0xc18e, 0x21, 0 + .dw 0x1740, 0xc18e, 0x177f, 0xc18e, 0x21, 0 + .dw 0x17c0, 0xc18e, 0x17ff, 0xc18e, 0x21, 0 + .dw 0x1840, 0xc18e, 0x187f, 0xc18e, 0x21, 0 + .dw 0x18c0, 0xc18e, 0x18ff, 0xc18e, 0x21, 0 + .dw 0x1940, 0xc18e, 0x197f, 0xc18e, 0x21, 0 + .dw 0x19c0, 0xc18e, 0x1fff, 0xc18e, 0x21, 0 + .dw 0x2040, 0xc18e, 0x207f, 0xc18e, 0x21, 0 + .dw 0x20c0, 0xc18e, 0x20ff, 0xc18e, 0x21, 0 + .dw 0x2140, 0xc18e, 0x217f, 0xc18e, 0x21, 0 + .dw 0x21c0, 0xc18e, 0x21ff, 0xc18e, 0x21, 0 + .dw 0x2240, 0xc18e, 0x227f, 0xc18e, 0x21, 0 + .dw 0x22c0, 0xc18e, 0x22ff, 0xc18e, 0x21, 0 + .dw 0x2340, 0xc18e, 0x237f, 0xc18e, 0x21, 0 + .dw 0x23c0, 0xc18e, 0x23ff, 0xc18e, 0x21, 0 + .dw 0x2440, 0xc18e, 0x247f, 0xc18e, 0x21, 0 + .dw 0x24c0, 0xc18e, 0x24ff, 0xc18e, 0x21, 0 + .dw 0x2540, 0xc18e, 0x257f, 0xc18e, 0x21, 0 + .dw 0x25c0, 0xc18e, 0x25ff, 0xc18e, 0x21, 0 + .dw 0x2640, 0xc18e, 0x267f, 0xc18e, 0x21, 0 + .dw 0x26c0, 0xc18e, 0x26ff, 0xc18e, 0x21, 0 + .dw 0x2740, 0xc18e, 0x277f, 0xc18e, 0x21, 0 + .dw 0x27c0, 0xc18e, 0x27ff, 0xc18e, 0x21, 0 + .dw 0x2840, 0xc18e, 0x287f, 0xc18e, 0x21, 0 + .dw 0x28c0, 0xc18e, 0x28ff, 0xc18e, 0x21, 0 + .dw 0x2940, 0xc18e, 0x297f, 0xc18e, 0x21, 0 + .dw 0x29c0, 0xc18e, 0x29ff, 0xc18e, 0x21, 0 + .dw 0x2a40, 0xc18e, 0x2a7f, 0xc18e, 0x21, 0 + .dw 0x2ac0, 0xc18e, 0x2aff, 0xc18e, 0x21, 0 + .dw 0x2b40, 0xc18e, 0x2b7f, 0xc18e, 0x21, 0 + .dw 0x2bc0, 0xc18e, 0x2bff, 0xc18e, 0x21, 0 + .dw 0x2c40, 0xc18e, 0x2c7f, 0xc18e, 0x21, 0 + .dw 0x2cc0, 0xc18e, 0x2cff, 0xc18e, 0x21, 0 + .dw 0x2d40, 0xc18e, 0x2d7f, 0xc18e, 0x21, 0 + .dw 0x2dc0, 0xc18e, 0x2dff, 0xc18e, 0x21, 0 + .dw 0x2e40, 0xc18e, 0x2e7f, 0xc18e, 0x21, 0 + .dw 0x2ec0, 0xc18e, 0x2eff, 0xc18e, 0x21, 0 + .dw 0x2f40, 0xc18e, 0x2f7f, 0xc18e, 0x21, 0 + .dw 0x2fc0, 0xc18e, 0x2fff, 0xc18e, 0x21, 0 + .dw 0x3040, 0xc18e, 0x307f, 0xc18e, 0x21, 0 + .dw 0x30c0, 0xc18e, 0x30ff, 0xc18e, 0x21, 0 + .dw 0x3140, 0xc18e, 0x317f, 0xc18e, 0x21, 0 + .dw 0x31c0, 0xc18e, 0x31ff, 0xc18e, 0x21, 0 + .dw 0x3240, 0xc18e, 0x327f, 0xc18e, 0x21, 0 + .dw 0x32c0, 0xc18e, 0x32ff, 0xc18e, 0x21, 0 + .dw 0x3340, 0xc18e, 0x337f, 0xc18e, 0x21, 0 + .dw 0x33c0, 0xc18e, 0x33ff, 0xc18e, 0x21, 0 + .dw 0x3440, 0xc18e, 0x347f, 0xc18e, 0x21, 0 + .dw 0x34c0, 0xc18e, 0x34ff, 0xc18e, 0x21, 0 + .dw 0x3540, 0xc18e, 0x357f, 0xc18e, 0x21, 0 + .dw 0x35c0, 0xc18e, 0x35ff, 0xc18e, 0x21, 0 + .dw 0x3640, 0xc18e, 0x367f, 0xc18e, 0x21, 0 + .dw 0x36c0, 0xc18e, 0x36ff, 0xc18e, 0x21, 0 + .dw 0x3740, 0xc18e, 0x377f, 0xc18e, 0x21, 0 + .dw 0x37c0, 0xc18e, 0x37ff, 0xc18e, 0x21, 0 + .dw 0x3840, 0xc18e, 0x387f, 0xc18e, 0x21, 0 + .dw 0x38c0, 0xc18e, 0x38ff, 0xc18e, 0x21, 0 + .dw 0x3940, 0xc18e, 0x397f, 0xc18e, 0x21, 0 + .dw 0x39c0, 0xc18e, 0x3fff, 0xc18e, 0x21, 0 + .dw 0x4040, 0xc18e, 0x407f, 0xc18e, 0x21, 0 + .dw 0x40c0, 0xc18e, 0x40ff, 0xc18e, 0x21, 0 + .dw 0x4140, 0xc18e, 0x417f, 0xc18e, 0x21, 0 + .dw 0x41c0, 0xc18e, 0x41ff, 0xc18e, 0x21, 0 + .dw 0x4240, 0xc18e, 0x427f, 0xc18e, 0x21, 0 + .dw 0x42c0, 0xc18e, 0x42ff, 0xc18e, 0x21, 0 + .dw 0x4340, 0xc18e, 0x437f, 0xc18e, 0x21, 0 + .dw 0x43c0, 0xc18e, 0x43ff, 0xc18e, 0x21, 0 + .dw 0x4440, 0xc18e, 0x447f, 0xc18e, 0x21, 0 + .dw 0x44c0, 0xc18e, 0x44ff, 0xc18e, 0x21, 0 + .dw 0x4540, 0xc18e, 0x457f, 0xc18e, 0x21, 0 + .dw 0x45c0, 0xc18e, 0x45ff, 0xc18e, 0x21, 0 + .dw 0x4640, 0xc18e, 0x467f, 0xc18e, 0x21, 0 + .dw 0x46c0, 0xc18e, 0x46ff, 0xc18e, 0x21, 0 + .dw 0x4740, 0xc18e, 0x477f, 0xc18e, 0x21, 0 + .dw 0x47c0, 0xc18e, 0x47ff, 0xc18e, 0x21, 0 + .dw 0x4840, 0xc18e, 0x487f, 0xc18e, 0x21, 0 + .dw 0x48c0, 0xc18e, 0x48ff, 0xc18e, 0x21, 0 + .dw 0x4940, 0xc18e, 0x497f, 0xc18e, 0x21, 0 + .dw 0x49c0, 0xc18e, 0x49ff, 0xc18e, 0x21, 0 + .dw 0x4a40, 0xc18e, 0x4a7f, 0xc18e, 0x21, 0 + .dw 0x4ac0, 0xc18e, 0x4aff, 0xc18e, 0x21, 0 + .dw 0x4b40, 0xc18e, 0x4b7f, 0xc18e, 0x21, 0 + .dw 0x4bc0, 0xc18e, 0x4bff, 0xc18e, 0x21, 0 + .dw 0x4c40, 0xc18e, 0x4c7f, 0xc18e, 0x21, 0 + .dw 0x4cc0, 0xc18e, 0x4cff, 0xc18e, 0x21, 0 + .dw 0x4d40, 0xc18e, 0x4d7f, 0xc18e, 0x21, 0 + .dw 0x4dc0, 0xc18e, 0x4dff, 0xc18e, 0x21, 0 + .dw 0x4e40, 0xc18e, 0x4e7f, 0xc18e, 0x21, 0 + .dw 0x4ec0, 0xc18e, 0x4eff, 0xc18e, 0x21, 0 + .dw 0x4f40, 0xc18e, 0x4f7f, 0xc18e, 0x21, 0 + .dw 0x4fc0, 0xc18e, 0x4fff, 0xc18e, 0x21, 0 + .dw 0x5040, 0xc18e, 0x507f, 0xc18e, 0x21, 0 + .dw 0x50c0, 0xc18e, 0x50ff, 0xc18e, 0x21, 0 + .dw 0x5140, 0xc18e, 0x517f, 0xc18e, 0x21, 0 + .dw 0x51c0, 0xc18e, 0x51ff, 0xc18e, 0x21, 0 + .dw 0x5240, 0xc18e, 0x527f, 0xc18e, 0x21, 0 + .dw 0x52c0, 0xc18e, 0x52ff, 0xc18e, 0x21, 0 + .dw 0x5340, 0xc18e, 0x537f, 0xc18e, 0x21, 0 + .dw 0x53c0, 0xc18e, 0x53ff, 0xc18e, 0x21, 0 + .dw 0x5440, 0xc18e, 0x547f, 0xc18e, 0x21, 0 + .dw 0x54c0, 0xc18e, 0x54ff, 0xc18e, 0x21, 0 + .dw 0x5540, 0xc18e, 0x557f, 0xc18e, 0x21, 0 + .dw 0x55c0, 0xc18e, 0x55ff, 0xc18e, 0x21, 0 + .dw 0x5640, 0xc18e, 0x567f, 0xc18e, 0x21, 0 + .dw 0x56c0, 0xc18e, 0x56ff, 0xc18e, 0x21, 0 + .dw 0x5740, 0xc18e, 0x577f, 0xc18e, 0x21, 0 + .dw 0x57c0, 0xc18e, 0x57ff, 0xc18e, 0x21, 0 + .dw 0x5840, 0xc18e, 0x587f, 0xc18e, 0x21, 0 + .dw 0x58c0, 0xc18e, 0x58ff, 0xc18e, 0x21, 0 + .dw 0x5940, 0xc18e, 0x597f, 0xc18e, 0x21, 0 + .dw 0x59c0, 0xc18e, 0x5fff, 0xc18e, 0x21, 0 + .dw 0x6040, 0xc18e, 0x607f, 0xc18e, 0x21, 0 + .dw 0x60c0, 0xc18e, 0x60ff, 0xc18e, 0x21, 0 + .dw 0x6140, 0xc18e, 0x617f, 0xc18e, 0x21, 0 + .dw 0x61c0, 0xc18e, 0x61ff, 0xc18e, 0x21, 0 + .dw 0x6240, 0xc18e, 0x627f, 0xc18e, 0x21, 0 + .dw 0x62c0, 0xc18e, 0x62ff, 0xc18e, 0x21, 0 + .dw 0x6340, 0xc18e, 0x637f, 0xc18e, 0x21, 0 + .dw 0x63c0, 0xc18e, 0x63ff, 0xc18e, 0x21, 0 + .dw 0x6440, 0xc18e, 0x647f, 0xc18e, 0x21, 0 + .dw 0x64c0, 0xc18e, 0x64ff, 0xc18e, 0x21, 0 + .dw 0x6540, 0xc18e, 0x657f, 0xc18e, 0x21, 0 + .dw 0x65c0, 0xc18e, 0x65ff, 0xc18e, 0x21, 0 + .dw 0x6640, 0xc18e, 0x667f, 0xc18e, 0x21, 0 + .dw 0x66c0, 0xc18e, 0x66ff, 0xc18e, 0x21, 0 + .dw 0x6740, 0xc18e, 0x677f, 0xc18e, 0x21, 0 + .dw 0x67c0, 0xc18e, 0x67ff, 0xc18e, 0x21, 0 + .dw 0x6840, 0xc18e, 0x687f, 0xc18e, 0x21, 0 + .dw 0x68c0, 0xc18e, 0x68ff, 0xc18e, 0x21, 0 + .dw 0x6940, 0xc18e, 0x697f, 0xc18e, 0x21, 0 + .dw 0x69c0, 0xc18e, 0x69ff, 0xc18e, 0x21, 0 + .dw 0x6a40, 0xc18e, 0x6a7f, 0xc18e, 0x21, 0 + .dw 0x6ac0, 0xc18e, 0x6aff, 0xc18e, 0x21, 0 + .dw 0x6b40, 0xc18e, 0x6b7f, 0xc18e, 0x21, 0 + .dw 0x6bc0, 0xc18e, 0x6bff, 0xc18e, 0x21, 0 + .dw 0x6c40, 0xc18e, 0x6c7f, 0xc18e, 0x21, 0 + .dw 0x6cc0, 0xc18e, 0x6cff, 0xc18e, 0x21, 0 + .dw 0x6d40, 0xc18e, 0x6d7f, 0xc18e, 0x21, 0 + .dw 0x6dc0, 0xc18e, 0x6dff, 0xc18e, 0x21, 0 + .dw 0x6e40, 0xc18e, 0x6e7f, 0xc18e, 0x21, 0 + .dw 0x6ec0, 0xc18e, 0x6eff, 0xc18e, 0x21, 0 + .dw 0x6f40, 0xc18e, 0x6f7f, 0xc18e, 0x21, 0 + .dw 0x6fc0, 0xc18e, 0x6fff, 0xc18e, 0x21, 0 + .dw 0x7040, 0xc18e, 0x707f, 0xc18e, 0x21, 0 + .dw 0x70c0, 0xc18e, 0x70ff, 0xc18e, 0x21, 0 + .dw 0x7140, 0xc18e, 0x717f, 0xc18e, 0x21, 0 + .dw 0x71c0, 0xc18e, 0x71ff, 0xc18e, 0x21, 0 + .dw 0x7240, 0xc18e, 0x727f, 0xc18e, 0x21, 0 + .dw 0x72c0, 0xc18e, 0x72ff, 0xc18e, 0x21, 0 + .dw 0x7340, 0xc18e, 0x737f, 0xc18e, 0x21, 0 + .dw 0x73c0, 0xc18e, 0x73ff, 0xc18e, 0x21, 0 + .dw 0x7440, 0xc18e, 0x747f, 0xc18e, 0x21, 0 + .dw 0x74c0, 0xc18e, 0x74ff, 0xc18e, 0x21, 0 + .dw 0x7540, 0xc18e, 0x757f, 0xc18e, 0x21, 0 + .dw 0x75c0, 0xc18e, 0x75ff, 0xc18e, 0x21, 0 + .dw 0x7640, 0xc18e, 0x767f, 0xc18e, 0x21, 0 + .dw 0x76c0, 0xc18e, 0x76ff, 0xc18e, 0x21, 0 + .dw 0x7740, 0xc18e, 0x777f, 0xc18e, 0x21, 0 + .dw 0x77c0, 0xc18e, 0x77ff, 0xc18e, 0x21, 0 + .dw 0x7840, 0xc18e, 0x787f, 0xc18e, 0x21, 0 + .dw 0x78c0, 0xc18e, 0x78ff, 0xc18e, 0x21, 0 + .dw 0x7940, 0xc18e, 0x797f, 0xc18e, 0x21, 0 + .dw 0x79c0, 0xc18e, 0x7fff, 0xc18e, 0x21, 0 + .dw 0x8040, 0xc18e, 0x807f, 0xc18e, 0x21, 0 + .dw 0x80c0, 0xc18e, 0x80ff, 0xc18e, 0x21, 0 + .dw 0x8140, 0xc18e, 0x817f, 0xc18e, 0x21, 0 + .dw 0x81c0, 0xc18e, 0x81ff, 0xc18e, 0x21, 0 + .dw 0x8240, 0xc18e, 0x827f, 0xc18e, 0x21, 0 + .dw 0x82c0, 0xc18e, 0x82ff, 0xc18e, 0x21, 0 + .dw 0x8340, 0xc18e, 0x837f, 0xc18e, 0x21, 0 + .dw 0x83c0, 0xc18e, 0x83ff, 0xc18e, 0x21, 0 + .dw 0x8440, 0xc18e, 0x847f, 0xc18e, 0x21, 0 + .dw 0x84c0, 0xc18e, 0x84ff, 0xc18e, 0x21, 0 + .dw 0x8540, 0xc18e, 0x857f, 0xc18e, 0x21, 0 + .dw 0x85c0, 0xc18e, 0x85ff, 0xc18e, 0x21, 0 + .dw 0x8640, 0xc18e, 0x867f, 0xc18e, 0x21, 0 + .dw 0x86c0, 0xc18e, 0x86ff, 0xc18e, 0x21, 0 + .dw 0x8740, 0xc18e, 0x877f, 0xc18e, 0x21, 0 + .dw 0x87c0, 0xc18e, 0x87ff, 0xc18e, 0x21, 0 + .dw 0x8840, 0xc18e, 0x887f, 0xc18e, 0x21, 0 + .dw 0x88c0, 0xc18e, 0x88ff, 0xc18e, 0x21, 0 + .dw 0x8940, 0xc18e, 0x897f, 0xc18e, 0x21, 0 + .dw 0x89c0, 0xc18e, 0x89ff, 0xc18e, 0x21, 0 + .dw 0x8a40, 0xc18e, 0x8a7f, 0xc18e, 0x21, 0 + .dw 0x8ac0, 0xc18e, 0x8aff, 0xc18e, 0x21, 0 + .dw 0x8b40, 0xc18e, 0x8b7f, 0xc18e, 0x21, 0 + .dw 0x8bc0, 0xc18e, 0x8bff, 0xc18e, 0x21, 0 + .dw 0x8c40, 0xc18e, 0x8c7f, 0xc18e, 0x21, 0 + .dw 0x8cc0, 0xc18e, 0x8cff, 0xc18e, 0x21, 0 + .dw 0x8d40, 0xc18e, 0x8d7f, 0xc18e, 0x21, 0 + .dw 0x8dc0, 0xc18e, 0x8dff, 0xc18e, 0x21, 0 + .dw 0x8e40, 0xc18e, 0x8e7f, 0xc18e, 0x21, 0 + .dw 0x8ec0, 0xc18e, 0x8eff, 0xc18e, 0x21, 0 + .dw 0x8f40, 0xc18e, 0x8f7f, 0xc18e, 0x21, 0 + .dw 0x8fc0, 0xc18e, 0x8fff, 0xc18e, 0x21, 0 + .dw 0x9040, 0xc18e, 0x907f, 0xc18e, 0x21, 0 + .dw 0x90c0, 0xc18e, 0x90ff, 0xc18e, 0x21, 0 + .dw 0x9140, 0xc18e, 0x917f, 0xc18e, 0x21, 0 + .dw 0x91c0, 0xc18e, 0x91ff, 0xc18e, 0x21, 0 + .dw 0x9240, 0xc18e, 0x927f, 0xc18e, 0x21, 0 + .dw 0x92c0, 0xc18e, 0x92ff, 0xc18e, 0x21, 0 + .dw 0x9340, 0xc18e, 0x937f, 0xc18e, 0x21, 0 + .dw 0x93c0, 0xc18e, 0x93ff, 0xc18e, 0x21, 0 + .dw 0x9440, 0xc18e, 0x947f, 0xc18e, 0x21, 0 + .dw 0x94c0, 0xc18e, 0x94ff, 0xc18e, 0x21, 0 + .dw 0x9540, 0xc18e, 0x957f, 0xc18e, 0x21, 0 + .dw 0x95c0, 0xc18e, 0x95ff, 0xc18e, 0x21, 0 + .dw 0x9640, 0xc18e, 0x967f, 0xc18e, 0x21, 0 + .dw 0x96c0, 0xc18e, 0x96ff, 0xc18e, 0x21, 0 + .dw 0x9740, 0xc18e, 0x977f, 0xc18e, 0x21, 0 + .dw 0x97c0, 0xc18e, 0x97ff, 0xc18e, 0x21, 0 + .dw 0x9840, 0xc18e, 0x987f, 0xc18e, 0x21, 0 + .dw 0x98c0, 0xc18e, 0x98ff, 0xc18e, 0x21, 0 + .dw 0x9940, 0xc18e, 0x997f, 0xc18e, 0x21, 0 + .dw 0x99c0, 0xc18e, 0x9fff, 0xc18e, 0x21, 0 + .dw 0xa040, 0xc18e, 0xa07f, 0xc18e, 0x21, 0 + .dw 0xa0c0, 0xc18e, 0xa0ff, 0xc18e, 0x21, 0 + .dw 0xa140, 0xc18e, 0xa17f, 0xc18e, 0x21, 0 + .dw 0xa1c0, 0xc18e, 0xa1ff, 0xc18e, 0x21, 0 + .dw 0xa240, 0xc18e, 0xa27f, 0xc18e, 0x21, 0 + .dw 0xa2c0, 0xc18e, 0xa2ff, 0xc18e, 0x21, 0 + .dw 0xa340, 0xc18e, 0xa37f, 0xc18e, 0x21, 0 + .dw 0xa3c0, 0xc18e, 0xa3ff, 0xc18e, 0x21, 0 + .dw 0xa440, 0xc18e, 0xa47f, 0xc18e, 0x21, 0 + .dw 0xa4c0, 0xc18e, 0xa4ff, 0xc18e, 0x21, 0 + .dw 0xa540, 0xc18e, 0xa57f, 0xc18e, 0x21, 0 + .dw 0xa5c0, 0xc18e, 0xa5ff, 0xc18e, 0x21, 0 + .dw 0xa640, 0xc18e, 0xa67f, 0xc18e, 0x21, 0 + .dw 0xa6c0, 0xc18e, 0xa6ff, 0xc18e, 0x21, 0 + .dw 0xa740, 0xc18e, 0xa77f, 0xc18e, 0x21, 0 + .dw 0xa7c0, 0xc18e, 0xa7ff, 0xc18e, 0x21, 0 + .dw 0xa840, 0xc18e, 0xa87f, 0xc18e, 0x21, 0 + .dw 0xa8c0, 0xc18e, 0xa8ff, 0xc18e, 0x21, 0 + .dw 0xa940, 0xc18e, 0xa97f, 0xc18e, 0x21, 0 + .dw 0xa9c0, 0xc18e, 0xa9ff, 0xc18e, 0x21, 0 + .dw 0xaa40, 0xc18e, 0xaa7f, 0xc18e, 0x21, 0 + .dw 0xaac0, 0xc18e, 0xaaff, 0xc18e, 0x21, 0 + .dw 0xab40, 0xc18e, 0xab7f, 0xc18e, 0x21, 0 + .dw 0xabc0, 0xc18e, 0xabff, 0xc18e, 0x21, 0 + .dw 0xac40, 0xc18e, 0xac7f, 0xc18e, 0x21, 0 + .dw 0xacc0, 0xc18e, 0xacff, 0xc18e, 0x21, 0 + .dw 0xad40, 0xc18e, 0xad7f, 0xc18e, 0x21, 0 + .dw 0xadc0, 0xc18e, 0xadff, 0xc18e, 0x21, 0 + .dw 0xae40, 0xc18e, 0xae7f, 0xc18e, 0x21, 0 + .dw 0xaec0, 0xc18e, 0xaeff, 0xc18e, 0x21, 0 + .dw 0xaf40, 0xc18e, 0xaf7f, 0xc18e, 0x21, 0 + .dw 0xafc0, 0xc18e, 0xafff, 0xc18e, 0x21, 0 + .dw 0xb040, 0xc18e, 0xb07f, 0xc18e, 0x21, 0 + .dw 0xb0c0, 0xc18e, 0xb0ff, 0xc18e, 0x21, 0 + .dw 0xb140, 0xc18e, 0xb17f, 0xc18e, 0x21, 0 + .dw 0xb1c0, 0xc18e, 0xb1ff, 0xc18e, 0x21, 0 + .dw 0xb240, 0xc18e, 0xb27f, 0xc18e, 0x21, 0 + .dw 0xb2c0, 0xc18e, 0xb2ff, 0xc18e, 0x21, 0 + .dw 0xb340, 0xc18e, 0xb37f, 0xc18e, 0x21, 0 + .dw 0xb3c0, 0xc18e, 0xb3ff, 0xc18e, 0x21, 0 + .dw 0xb440, 0xc18e, 0xb47f, 0xc18e, 0x21, 0 + .dw 0xb4c0, 0xc18e, 0xb4ff, 0xc18e, 0x21, 0 + .dw 0xb540, 0xc18e, 0xb57f, 0xc18e, 0x21, 0 + .dw 0xb5c0, 0xc18e, 0xb5ff, 0xc18e, 0x21, 0 + .dw 0xb640, 0xc18e, 0xb67f, 0xc18e, 0x21, 0 + .dw 0xb6c0, 0xc18e, 0xb6ff, 0xc18e, 0x21, 0 + .dw 0xb740, 0xc18e, 0xb77f, 0xc18e, 0x21, 0 + .dw 0xb7c0, 0xc18e, 0xb7ff, 0xc18e, 0x21, 0 + .dw 0xb840, 0xc18e, 0xb87f, 0xc18e, 0x21, 0 + .dw 0xb8c0, 0xc18e, 0xb8ff, 0xc18e, 0x21, 0 + .dw 0xb940, 0xc18e, 0xb97f, 0xc18e, 0x21, 0 + .dw 0xb9c0, 0xc18e, 0xbfff, 0xc18e, 0x21, 0 + .dw 0xc040, 0xc18e, 0xc07f, 0xc18e, 0x21, 0 + .dw 0xc0c0, 0xc18e, 0xc0ff, 0xc18e, 0x21, 0 + .dw 0xc140, 0xc18e, 0xc17f, 0xc18e, 0x21, 0 + .dw 0xc1c0, 0xc18e, 0xc1ff, 0xc18e, 0x21, 0 + .dw 0xc240, 0xc18e, 0xc27f, 0xc18e, 0x21, 0 + .dw 0xc2c0, 0xc18e, 0xc2ff, 0xc18e, 0x21, 0 + .dw 0xc340, 0xc18e, 0xc37f, 0xc18e, 0x21, 0 + .dw 0xc3c0, 0xc18e, 0xc3ff, 0xc18e, 0x21, 0 + .dw 0xc440, 0xc18e, 0xc47f, 0xc18e, 0x21, 0 + .dw 0xc4c0, 0xc18e, 0xc4ff, 0xc18e, 0x21, 0 + .dw 0xc540, 0xc18e, 0xc57f, 0xc18e, 0x21, 0 + .dw 0xc5c0, 0xc18e, 0xc5ff, 0xc18e, 0x21, 0 + .dw 0xc640, 0xc18e, 0xc67f, 0xc18e, 0x21, 0 + .dw 0xc6c0, 0xc18e, 0xc6ff, 0xc18e, 0x21, 0 + .dw 0xc740, 0xc18e, 0xc77f, 0xc18e, 0x21, 0 + .dw 0xc7c0, 0xc18e, 0xc7ff, 0xc18e, 0x21, 0 + .dw 0xc840, 0xc18e, 0xc87f, 0xc18e, 0x21, 0 + .dw 0xc8c0, 0xc18e, 0xc8ff, 0xc18e, 0x21, 0 + .dw 0xc940, 0xc18e, 0xc97f, 0xc18e, 0x21, 0 + .dw 0xc9c0, 0xc18e, 0xc9ff, 0xc18e, 0x21, 0 + .dw 0xca40, 0xc18e, 0xca7f, 0xc18e, 0x21, 0 + .dw 0xcac0, 0xc18e, 0xcaff, 0xc18e, 0x21, 0 + .dw 0xcb40, 0xc18e, 0xcb7f, 0xc18e, 0x21, 0 + .dw 0xcbc0, 0xc18e, 0xcbff, 0xc18e, 0x21, 0 + .dw 0xcc40, 0xc18e, 0xcc7f, 0xc18e, 0x21, 0 + .dw 0xccc0, 0xc18e, 0xccff, 0xc18e, 0x21, 0 + .dw 0xcd40, 0xc18e, 0xcd7f, 0xc18e, 0x21, 0 + .dw 0xcdc0, 0xc18e, 0xcdff, 0xc18e, 0x21, 0 + .dw 0xce40, 0xc18e, 0xce7f, 0xc18e, 0x21, 0 + .dw 0xcec0, 0xc18e, 0xceff, 0xc18e, 0x21, 0 + .dw 0xcf40, 0xc18e, 0xcf7f, 0xc18e, 0x21, 0 + .dw 0xcfc0, 0xc18e, 0xcfff, 0xc18e, 0x21, 0 + .dw 0xd040, 0xc18e, 0xd07f, 0xc18e, 0x21, 0 + .dw 0xd0c0, 0xc18e, 0xd0ff, 0xc18e, 0x21, 0 + .dw 0xd140, 0xc18e, 0xd17f, 0xc18e, 0x21, 0 + .dw 0xd1c0, 0xc18e, 0xd1ff, 0xc18e, 0x21, 0 + .dw 0xd240, 0xc18e, 0xd27f, 0xc18e, 0x21, 0 + .dw 0xd2c0, 0xc18e, 0xd2ff, 0xc18e, 0x21, 0 + .dw 0xd340, 0xc18e, 0xd37f, 0xc18e, 0x21, 0 + .dw 0xd3c0, 0xc18e, 0xd3ff, 0xc18e, 0x21, 0 + .dw 0xd440, 0xc18e, 0xd47f, 0xc18e, 0x21, 0 + .dw 0xd4c0, 0xc18e, 0xd4ff, 0xc18e, 0x21, 0 + .dw 0xd540, 0xc18e, 0xd57f, 0xc18e, 0x21, 0 + .dw 0xd5c0, 0xc18e, 0xd5ff, 0xc18e, 0x21, 0 + .dw 0xd640, 0xc18e, 0xd67f, 0xc18e, 0x21, 0 + .dw 0xd6c0, 0xc18e, 0xd6ff, 0xc18e, 0x21, 0 + .dw 0xd740, 0xc18e, 0xd77f, 0xc18e, 0x21, 0 + .dw 0xd7c0, 0xc18e, 0xd7ff, 0xc18e, 0x21, 0 + .dw 0xd840, 0xc18e, 0xd87f, 0xc18e, 0x21, 0 + .dw 0xd8c0, 0xc18e, 0xd8ff, 0xc18e, 0x21, 0 + .dw 0xd940, 0xc18e, 0xd97f, 0xc18e, 0x21, 0 + .dw 0xd9c0, 0xc18e, 0xdfff, 0xc18e, 0x21, 0 + .dw 0xe040, 0xc18e, 0xe07f, 0xc18e, 0x21, 0 + .dw 0xe0c0, 0xc18e, 0xe0ff, 0xc18e, 0x21, 0 + .dw 0xe140, 0xc18e, 0xe17f, 0xc18e, 0x21, 0 + .dw 0xe1c0, 0xc18e, 0xe1ff, 0xc18e, 0x21, 0 + .dw 0xe240, 0xc18e, 0xe27f, 0xc18e, 0x21, 0 + .dw 0xe2c0, 0xc18e, 0xe2ff, 0xc18e, 0x21, 0 + .dw 0xe340, 0xc18e, 0xe37f, 0xc18e, 0x21, 0 + .dw 0xe3c0, 0xc18e, 0xe3ff, 0xc18e, 0x21, 0 + .dw 0xe440, 0xc18e, 0xe47f, 0xc18e, 0x21, 0 + .dw 0xe4c0, 0xc18e, 0xe4ff, 0xc18e, 0x21, 0 + .dw 0xe540, 0xc18e, 0xe57f, 0xc18e, 0x21, 0 + .dw 0xe5c0, 0xc18e, 0xe5ff, 0xc18e, 0x21, 0 + .dw 0xe640, 0xc18e, 0xe67f, 0xc18e, 0x21, 0 + .dw 0xe6c0, 0xc18e, 0xe6ff, 0xc18e, 0x21, 0 + .dw 0xe740, 0xc18e, 0xe77f, 0xc18e, 0x21, 0 + .dw 0xe7c0, 0xc18e, 0xe7ff, 0xc18e, 0x21, 0 + .dw 0xe840, 0xc18e, 0xe87f, 0xc18e, 0x21, 0 + .dw 0xe8c0, 0xc18e, 0xe8ff, 0xc18e, 0x21, 0 + .dw 0xe940, 0xc18e, 0xe97f, 0xc18e, 0x21, 0 + .dw 0xe9c0, 0xc18e, 0xe9ff, 0xc18e, 0x21, 0 + .dw 0xea40, 0xc18e, 0xea7f, 0xc18e, 0x21, 0 + .dw 0xeac0, 0xc18e, 0xeaff, 0xc18e, 0x21, 0 + .dw 0xeb40, 0xc18e, 0xeb7f, 0xc18e, 0x21, 0 + .dw 0xebc0, 0xc18e, 0xebff, 0xc18e, 0x21, 0 + .dw 0xec40, 0xc18e, 0xec7f, 0xc18e, 0x21, 0 + .dw 0xecc0, 0xc18e, 0xecff, 0xc18e, 0x21, 0 + .dw 0xed40, 0xc18e, 0xed7f, 0xc18e, 0x21, 0 + .dw 0xedc0, 0xc18e, 0xedff, 0xc18e, 0x21, 0 + .dw 0xee40, 0xc18e, 0xee7f, 0xc18e, 0x21, 0 + .dw 0xeec0, 0xc18e, 0xeeff, 0xc18e, 0x21, 0 + .dw 0xef40, 0xc18e, 0xef7f, 0xc18e, 0x21, 0 + .dw 0xefc0, 0xc18e, 0xefff, 0xc18e, 0x21, 0 + .dw 0xf040, 0xc18e, 0xf07f, 0xc18e, 0x21, 0 + .dw 0xf0c0, 0xc18e, 0xf0ff, 0xc18e, 0x21, 0 + .dw 0xf140, 0xc18e, 0xf17f, 0xc18e, 0x21, 0 + .dw 0xf1c0, 0xc18e, 0xf1ff, 0xc18e, 0x21, 0 + .dw 0xf240, 0xc18e, 0xf27f, 0xc18e, 0x21, 0 + .dw 0xf2c0, 0xc18e, 0xf2ff, 0xc18e, 0x21, 0 + .dw 0xf340, 0xc18e, 0xf37f, 0xc18e, 0x21, 0 + .dw 0xf3c0, 0xc18e, 0xf3ff, 0xc18e, 0x21, 0 + .dw 0xf440, 0xc18e, 0xf47f, 0xc18e, 0x21, 0 + .dw 0xf4c0, 0xc18e, 0xf4ff, 0xc18e, 0x21, 0 + .dw 0xf540, 0xc18e, 0xf57f, 0xc18e, 0x21, 0 + .dw 0xf5c0, 0xc18e, 0xf5ff, 0xc18e, 0x21, 0 + .dw 0xf640, 0xc18e, 0xf67f, 0xc18e, 0x21, 0 + .dw 0xf6c0, 0xc18e, 0xf6ff, 0xc18e, 0x21, 0 + .dw 0xf740, 0xc18e, 0xf77f, 0xc18e, 0x21, 0 + .dw 0xf7c0, 0xc18e, 0xf7ff, 0xc18e, 0x21, 0 + .dw 0xf840, 0xc18e, 0xf87f, 0xc18e, 0x21, 0 + .dw 0xf8c0, 0xc18e, 0xf8ff, 0xc18e, 0x21, 0 + .dw 0xf940, 0xc18e, 0xf97f, 0xc18e, 0x21, 0 + .dw 0xf9c0, 0xc18e, 0xffff, 0xc18e, 0x21, 0 + .dw 0x0040, 0xc18f, 0x007f, 0xc18f, 0x21, 0 + .dw 0x00c0, 0xc18f, 0x00ff, 0xc18f, 0x21, 0 + .dw 0x0140, 0xc18f, 0x017f, 0xc18f, 0x21, 0 + .dw 0x01c0, 0xc18f, 0x01ff, 0xc18f, 0x21, 0 + .dw 0x0240, 0xc18f, 0x027f, 0xc18f, 0x21, 0 + .dw 0x02c0, 0xc18f, 0x02ff, 0xc18f, 0x21, 0 + .dw 0x0340, 0xc18f, 0x037f, 0xc18f, 0x21, 0 + .dw 0x03c0, 0xc18f, 0x03ff, 0xc18f, 0x21, 0 + .dw 0x0440, 0xc18f, 0x047f, 0xc18f, 0x21, 0 + .dw 0x04c0, 0xc18f, 0x04ff, 0xc18f, 0x21, 0 + .dw 0x0540, 0xc18f, 0x057f, 0xc18f, 0x21, 0 + .dw 0x05c0, 0xc18f, 0x05ff, 0xc18f, 0x21, 0 + .dw 0x0640, 0xc18f, 0x067f, 0xc18f, 0x21, 0 + .dw 0x06c0, 0xc18f, 0x06ff, 0xc18f, 0x21, 0 + .dw 0x0740, 0xc18f, 0x077f, 0xc18f, 0x21, 0 + .dw 0x07c0, 0xc18f, 0x07ff, 0xc18f, 0x21, 0 + .dw 0x0840, 0xc18f, 0x087f, 0xc18f, 0x21, 0 + .dw 0x08c0, 0xc18f, 0x08ff, 0xc18f, 0x21, 0 + .dw 0x0940, 0xc18f, 0x097f, 0xc18f, 0x21, 0 + .dw 0x09c0, 0xc18f, 0x09ff, 0xc18f, 0x21, 0 + .dw 0x0a40, 0xc18f, 0x0a7f, 0xc18f, 0x21, 0 + .dw 0x0ac0, 0xc18f, 0x0aff, 0xc18f, 0x21, 0 + .dw 0x0b40, 0xc18f, 0x0b7f, 0xc18f, 0x21, 0 + .dw 0x0bc0, 0xc18f, 0x0bff, 0xc18f, 0x21, 0 + .dw 0x0c40, 0xc18f, 0x0c7f, 0xc18f, 0x21, 0 + .dw 0x0cc0, 0xc18f, 0x0cff, 0xc18f, 0x21, 0 + .dw 0x0d40, 0xc18f, 0x0d7f, 0xc18f, 0x21, 0 + .dw 0x0dc0, 0xc18f, 0x0dff, 0xc18f, 0x21, 0 + .dw 0x0e40, 0xc18f, 0x0e7f, 0xc18f, 0x21, 0 + .dw 0x0ec0, 0xc18f, 0x0eff, 0xc18f, 0x21, 0 + .dw 0x0f40, 0xc18f, 0x0f7f, 0xc18f, 0x21, 0 + .dw 0x0fc0, 0xc18f, 0x0fff, 0xc18f, 0x21, 0 + .dw 0x1040, 0xc18f, 0x107f, 0xc18f, 0x21, 0 + .dw 0x10c0, 0xc18f, 0x10ff, 0xc18f, 0x21, 0 + .dw 0x1140, 0xc18f, 0x117f, 0xc18f, 0x21, 0 + .dw 0x11c0, 0xc18f, 0x11ff, 0xc18f, 0x21, 0 + .dw 0x1240, 0xc18f, 0x127f, 0xc18f, 0x21, 0 + .dw 0x12c0, 0xc18f, 0x12ff, 0xc18f, 0x21, 0 + .dw 0x1340, 0xc18f, 0x137f, 0xc18f, 0x21, 0 + .dw 0x13c0, 0xc18f, 0x13ff, 0xc18f, 0x21, 0 + .dw 0x1440, 0xc18f, 0x147f, 0xc18f, 0x21, 0 + .dw 0x14c0, 0xc18f, 0x14ff, 0xc18f, 0x21, 0 + .dw 0x1540, 0xc18f, 0x157f, 0xc18f, 0x21, 0 + .dw 0x15c0, 0xc18f, 0x15ff, 0xc18f, 0x21, 0 + .dw 0x1640, 0xc18f, 0x167f, 0xc18f, 0x21, 0 + .dw 0x16c0, 0xc18f, 0x16ff, 0xc18f, 0x21, 0 + .dw 0x1740, 0xc18f, 0x177f, 0xc18f, 0x21, 0 + .dw 0x17c0, 0xc18f, 0x17ff, 0xc18f, 0x21, 0 + .dw 0x1840, 0xc18f, 0x187f, 0xc18f, 0x21, 0 + .dw 0x18c0, 0xc18f, 0x18ff, 0xc18f, 0x21, 0 + .dw 0x1940, 0xc18f, 0x197f, 0xc18f, 0x21, 0 + .dw 0x19c0, 0xc18f, 0x1fff, 0xc18f, 0x21, 0 + .dw 0x2040, 0xc18f, 0x207f, 0xc18f, 0x21, 0 + .dw 0x20c0, 0xc18f, 0x20ff, 0xc18f, 0x21, 0 + .dw 0x2140, 0xc18f, 0x217f, 0xc18f, 0x21, 0 + .dw 0x21c0, 0xc18f, 0x21ff, 0xc18f, 0x21, 0 + .dw 0x2240, 0xc18f, 0x227f, 0xc18f, 0x21, 0 + .dw 0x22c0, 0xc18f, 0x22ff, 0xc18f, 0x21, 0 + .dw 0x2340, 0xc18f, 0x237f, 0xc18f, 0x21, 0 + .dw 0x23c0, 0xc18f, 0x23ff, 0xc18f, 0x21, 0 + .dw 0x2440, 0xc18f, 0x247f, 0xc18f, 0x21, 0 + .dw 0x24c0, 0xc18f, 0x24ff, 0xc18f, 0x21, 0 + .dw 0x2540, 0xc18f, 0x257f, 0xc18f, 0x21, 0 + .dw 0x25c0, 0xc18f, 0x25ff, 0xc18f, 0x21, 0 + .dw 0x2640, 0xc18f, 0x267f, 0xc18f, 0x21, 0 + .dw 0x26c0, 0xc18f, 0x26ff, 0xc18f, 0x21, 0 + .dw 0x2740, 0xc18f, 0x277f, 0xc18f, 0x21, 0 + .dw 0x27c0, 0xc18f, 0x27ff, 0xc18f, 0x21, 0 + .dw 0x2840, 0xc18f, 0x287f, 0xc18f, 0x21, 0 + .dw 0x28c0, 0xc18f, 0x28ff, 0xc18f, 0x21, 0 + .dw 0x2940, 0xc18f, 0x297f, 0xc18f, 0x21, 0 + .dw 0x29c0, 0xc18f, 0x29ff, 0xc18f, 0x21, 0 + .dw 0x2a40, 0xc18f, 0x2a7f, 0xc18f, 0x21, 0 + .dw 0x2ac0, 0xc18f, 0x2aff, 0xc18f, 0x21, 0 + .dw 0x2b40, 0xc18f, 0x2b7f, 0xc18f, 0x21, 0 + .dw 0x2bc0, 0xc18f, 0x2bff, 0xc18f, 0x21, 0 + .dw 0x2c40, 0xc18f, 0x2c7f, 0xc18f, 0x21, 0 + .dw 0x2cc0, 0xc18f, 0x2cff, 0xc18f, 0x21, 0 + .dw 0x2d40, 0xc18f, 0x2d7f, 0xc18f, 0x21, 0 + .dw 0x2dc0, 0xc18f, 0x2dff, 0xc18f, 0x21, 0 + .dw 0x2e40, 0xc18f, 0x2e7f, 0xc18f, 0x21, 0 + .dw 0x2ec0, 0xc18f, 0x2eff, 0xc18f, 0x21, 0 + .dw 0x2f40, 0xc18f, 0x2f7f, 0xc18f, 0x21, 0 + .dw 0x2fc0, 0xc18f, 0x2fff, 0xc18f, 0x21, 0 + .dw 0x3040, 0xc18f, 0x307f, 0xc18f, 0x21, 0 + .dw 0x30c0, 0xc18f, 0x30ff, 0xc18f, 0x21, 0 + .dw 0x3140, 0xc18f, 0x317f, 0xc18f, 0x21, 0 + .dw 0x31c0, 0xc18f, 0x31ff, 0xc18f, 0x21, 0 + .dw 0x3240, 0xc18f, 0x327f, 0xc18f, 0x21, 0 + .dw 0x32c0, 0xc18f, 0x32ff, 0xc18f, 0x21, 0 + .dw 0x3340, 0xc18f, 0x337f, 0xc18f, 0x21, 0 + .dw 0x33c0, 0xc18f, 0x33ff, 0xc18f, 0x21, 0 + .dw 0x3440, 0xc18f, 0x347f, 0xc18f, 0x21, 0 + .dw 0x34c0, 0xc18f, 0x34ff, 0xc18f, 0x21, 0 + .dw 0x3540, 0xc18f, 0x357f, 0xc18f, 0x21, 0 + .dw 0x35c0, 0xc18f, 0x35ff, 0xc18f, 0x21, 0 + .dw 0x3640, 0xc18f, 0x367f, 0xc18f, 0x21, 0 + .dw 0x36c0, 0xc18f, 0x36ff, 0xc18f, 0x21, 0 + .dw 0x3740, 0xc18f, 0x377f, 0xc18f, 0x21, 0 + .dw 0x37c0, 0xc18f, 0x37ff, 0xc18f, 0x21, 0 + .dw 0x3840, 0xc18f, 0x387f, 0xc18f, 0x21, 0 + .dw 0x38c0, 0xc18f, 0x38ff, 0xc18f, 0x21, 0 + .dw 0x3940, 0xc18f, 0x397f, 0xc18f, 0x21, 0 + .dw 0x39c0, 0xc18f, 0x1fff, 0xc190, 0x21, 0 + .dw 0x3a00, 0xc190, 0x5fff, 0xc190, 0x21, 0 + .dw 0x7a00, 0xc190, 0x9fff, 0xc190, 0x21, 0 + .dw 0xba00, 0xc190, 0xdfff, 0xc190, 0x21, 0 + .dw 0xfa00, 0xc190, 0x1fff, 0xc191, 0x21, 0 + .dw 0x3a00, 0xc191, 0x5fff, 0xc191, 0x21, 0 + .dw 0x7a00, 0xc191, 0x9fff, 0xc191, 0x21, 0 + .dw 0xba00, 0xc191, 0xdfff, 0xc191, 0x21, 0 + .dw 0xfa00, 0xc191, 0x1fff, 0xc192, 0x21, 0 + .dw 0x3a00, 0xc192, 0x5fff, 0xc192, 0x21, 0 + .dw 0x7a00, 0xc192, 0x9fff, 0xc192, 0x21, 0 + .dw 0xba00, 0xc192, 0xdfff, 0xc192, 0x21, 0 + .dw 0xfa00, 0xc192, 0xffff, 0xc193, 0x21, 0 + .dw 0x1a00, 0xc194, 0x1fff, 0xc194, 0x21, 0 + .dw 0x3a00, 0xc194, 0x3fff, 0xc194, 0x21, 0 + .dw 0x5a00, 0xc194, 0x5fff, 0xc194, 0x21, 0 + .dw 0x7a00, 0xc194, 0x7fff, 0xc194, 0x21, 0 + .dw 0x9a00, 0xc194, 0x9fff, 0xc194, 0x21, 0 + .dw 0xba00, 0xc194, 0xbfff, 0xc194, 0x21, 0 + .dw 0xda00, 0xc194, 0xdfff, 0xc194, 0x21, 0 + .dw 0xfa00, 0xc194, 0xffff, 0xc194, 0x21, 0 + .dw 0x1a00, 0xc195, 0x1fff, 0xc195, 0x21, 0 + .dw 0x3a00, 0xc195, 0x3fff, 0xc195, 0x21, 0 + .dw 0x5a00, 0xc195, 0x5fff, 0xc195, 0x21, 0 + .dw 0x7a00, 0xc195, 0x7fff, 0xc195, 0x21, 0 + .dw 0x9a00, 0xc195, 0x9fff, 0xc195, 0x21, 0 + .dw 0xba00, 0xc195, 0xbfff, 0xc195, 0x21, 0 + .dw 0xda00, 0xc195, 0xdfff, 0xc195, 0x21, 0 + .dw 0xfa00, 0xc195, 0xffff, 0xc195, 0x21, 0 + .dw 0x1a00, 0xc196, 0x1fff, 0xc196, 0x21, 0 + .dw 0x3a00, 0xc196, 0x3fff, 0xc196, 0x21, 0 + .dw 0x5a00, 0xc196, 0x5fff, 0xc196, 0x21, 0 + .dw 0x7a00, 0xc196, 0x7fff, 0xc196, 0x21, 0 + .dw 0x9a00, 0xc196, 0x9fff, 0xc196, 0x21, 0 + .dw 0xba00, 0xc196, 0xbfff, 0xc196, 0x21, 0 + .dw 0xda00, 0xc196, 0xdfff, 0xc196, 0x21, 0 + .dw 0xfa00, 0xc196, 0xffff, 0xc196, 0x21, 0 + .dw 0x1a00, 0xc197, 0x1fff, 0xc197, 0x21, 0 + .dw 0x3a00, 0xc197, 0x1fff, 0xc198, 0x21, 0 + .dw 0x2040, 0xc198, 0x207f, 0xc198, 0x21, 0 + .dw 0x20c0, 0xc198, 0x20ff, 0xc198, 0x21, 0 + .dw 0x2140, 0xc198, 0x217f, 0xc198, 0x21, 0 + .dw 0x21c0, 0xc198, 0x21ff, 0xc198, 0x21, 0 + .dw 0x2240, 0xc198, 0x227f, 0xc198, 0x21, 0 + .dw 0x22c0, 0xc198, 0x22ff, 0xc198, 0x21, 0 + .dw 0x2340, 0xc198, 0x237f, 0xc198, 0x21, 0 + .dw 0x23c0, 0xc198, 0x23ff, 0xc198, 0x21, 0 + .dw 0x2440, 0xc198, 0x247f, 0xc198, 0x21, 0 + .dw 0x24c0, 0xc198, 0x24ff, 0xc198, 0x21, 0 + .dw 0x2540, 0xc198, 0x257f, 0xc198, 0x21, 0 + .dw 0x25c0, 0xc198, 0x25ff, 0xc198, 0x21, 0 + .dw 0x2640, 0xc198, 0x267f, 0xc198, 0x21, 0 + .dw 0x26c0, 0xc198, 0x26ff, 0xc198, 0x21, 0 + .dw 0x2740, 0xc198, 0x277f, 0xc198, 0x21, 0 + .dw 0x27c0, 0xc198, 0x27ff, 0xc198, 0x21, 0 + .dw 0x2840, 0xc198, 0x287f, 0xc198, 0x21, 0 + .dw 0x28c0, 0xc198, 0x28ff, 0xc198, 0x21, 0 + .dw 0x2940, 0xc198, 0x297f, 0xc198, 0x21, 0 + .dw 0x29c0, 0xc198, 0x29ff, 0xc198, 0x21, 0 + .dw 0x2a40, 0xc198, 0x2a7f, 0xc198, 0x21, 0 + .dw 0x2ac0, 0xc198, 0x2aff, 0xc198, 0x21, 0 + .dw 0x2b40, 0xc198, 0x2b7f, 0xc198, 0x21, 0 + .dw 0x2bc0, 0xc198, 0x2bff, 0xc198, 0x21, 0 + .dw 0x2c40, 0xc198, 0x2c7f, 0xc198, 0x21, 0 + .dw 0x2cc0, 0xc198, 0x2cff, 0xc198, 0x21, 0 + .dw 0x2d40, 0xc198, 0x2d7f, 0xc198, 0x21, 0 + .dw 0x2dc0, 0xc198, 0x2dff, 0xc198, 0x21, 0 + .dw 0x2e40, 0xc198, 0x2e7f, 0xc198, 0x21, 0 + .dw 0x2ec0, 0xc198, 0x2eff, 0xc198, 0x21, 0 + .dw 0x2f40, 0xc198, 0x2f7f, 0xc198, 0x21, 0 + .dw 0x2fc0, 0xc198, 0x2fff, 0xc198, 0x21, 0 + .dw 0x3040, 0xc198, 0x307f, 0xc198, 0x21, 0 + .dw 0x30c0, 0xc198, 0x30ff, 0xc198, 0x21, 0 + .dw 0x3140, 0xc198, 0x317f, 0xc198, 0x21, 0 + .dw 0x31c0, 0xc198, 0x31ff, 0xc198, 0x21, 0 + .dw 0x3240, 0xc198, 0x327f, 0xc198, 0x21, 0 + .dw 0x32c0, 0xc198, 0x32ff, 0xc198, 0x21, 0 + .dw 0x3340, 0xc198, 0x337f, 0xc198, 0x21, 0 + .dw 0x33c0, 0xc198, 0x33ff, 0xc198, 0x21, 0 + .dw 0x3440, 0xc198, 0x347f, 0xc198, 0x21, 0 + .dw 0x34c0, 0xc198, 0x34ff, 0xc198, 0x21, 0 + .dw 0x3540, 0xc198, 0x357f, 0xc198, 0x21, 0 + .dw 0x35c0, 0xc198, 0x35ff, 0xc198, 0x21, 0 + .dw 0x3640, 0xc198, 0x367f, 0xc198, 0x21, 0 + .dw 0x36c0, 0xc198, 0x36ff, 0xc198, 0x21, 0 + .dw 0x3740, 0xc198, 0x377f, 0xc198, 0x21, 0 + .dw 0x37c0, 0xc198, 0x37ff, 0xc198, 0x21, 0 + .dw 0x3840, 0xc198, 0x387f, 0xc198, 0x21, 0 + .dw 0x38c0, 0xc198, 0x38ff, 0xc198, 0x21, 0 + .dw 0x3940, 0xc198, 0x397f, 0xc198, 0x21, 0 + .dw 0x39c0, 0xc198, 0x5fff, 0xc198, 0x21, 0 + .dw 0x6040, 0xc198, 0x607f, 0xc198, 0x21, 0 + .dw 0x60c0, 0xc198, 0x60ff, 0xc198, 0x21, 0 + .dw 0x6140, 0xc198, 0x617f, 0xc198, 0x21, 0 + .dw 0x61c0, 0xc198, 0x61ff, 0xc198, 0x21, 0 + .dw 0x6240, 0xc198, 0x627f, 0xc198, 0x21, 0 + .dw 0x62c0, 0xc198, 0x62ff, 0xc198, 0x21, 0 + .dw 0x6340, 0xc198, 0x637f, 0xc198, 0x21, 0 + .dw 0x63c0, 0xc198, 0x63ff, 0xc198, 0x21, 0 + .dw 0x6440, 0xc198, 0x647f, 0xc198, 0x21, 0 + .dw 0x64c0, 0xc198, 0x64ff, 0xc198, 0x21, 0 + .dw 0x6540, 0xc198, 0x657f, 0xc198, 0x21, 0 + .dw 0x65c0, 0xc198, 0x65ff, 0xc198, 0x21, 0 + .dw 0x6640, 0xc198, 0x667f, 0xc198, 0x21, 0 + .dw 0x66c0, 0xc198, 0x66ff, 0xc198, 0x21, 0 + .dw 0x6740, 0xc198, 0x677f, 0xc198, 0x21, 0 + .dw 0x67c0, 0xc198, 0x67ff, 0xc198, 0x21, 0 + .dw 0x6840, 0xc198, 0x687f, 0xc198, 0x21, 0 + .dw 0x68c0, 0xc198, 0x68ff, 0xc198, 0x21, 0 + .dw 0x6940, 0xc198, 0x697f, 0xc198, 0x21, 0 + .dw 0x69c0, 0xc198, 0x69ff, 0xc198, 0x21, 0 + .dw 0x6a40, 0xc198, 0x6a7f, 0xc198, 0x21, 0 + .dw 0x6ac0, 0xc198, 0x6aff, 0xc198, 0x21, 0 + .dw 0x6b40, 0xc198, 0x6b7f, 0xc198, 0x21, 0 + .dw 0x6bc0, 0xc198, 0x6bff, 0xc198, 0x21, 0 + .dw 0x6c40, 0xc198, 0x6c7f, 0xc198, 0x21, 0 + .dw 0x6cc0, 0xc198, 0x6cff, 0xc198, 0x21, 0 + .dw 0x6d40, 0xc198, 0x6d7f, 0xc198, 0x21, 0 + .dw 0x6dc0, 0xc198, 0x6dff, 0xc198, 0x21, 0 + .dw 0x6e40, 0xc198, 0x6e7f, 0xc198, 0x21, 0 + .dw 0x6ec0, 0xc198, 0x6eff, 0xc198, 0x21, 0 + .dw 0x6f40, 0xc198, 0x6f7f, 0xc198, 0x21, 0 + .dw 0x6fc0, 0xc198, 0x6fff, 0xc198, 0x21, 0 + .dw 0x7040, 0xc198, 0x707f, 0xc198, 0x21, 0 + .dw 0x70c0, 0xc198, 0x70ff, 0xc198, 0x21, 0 + .dw 0x7140, 0xc198, 0x717f, 0xc198, 0x21, 0 + .dw 0x71c0, 0xc198, 0x71ff, 0xc198, 0x21, 0 + .dw 0x7240, 0xc198, 0x727f, 0xc198, 0x21, 0 + .dw 0x72c0, 0xc198, 0x72ff, 0xc198, 0x21, 0 + .dw 0x7340, 0xc198, 0x737f, 0xc198, 0x21, 0 + .dw 0x73c0, 0xc198, 0x73ff, 0xc198, 0x21, 0 + .dw 0x7440, 0xc198, 0x747f, 0xc198, 0x21, 0 + .dw 0x74c0, 0xc198, 0x74ff, 0xc198, 0x21, 0 + .dw 0x7540, 0xc198, 0x757f, 0xc198, 0x21, 0 + .dw 0x75c0, 0xc198, 0x75ff, 0xc198, 0x21, 0 + .dw 0x7640, 0xc198, 0x767f, 0xc198, 0x21, 0 + .dw 0x76c0, 0xc198, 0x76ff, 0xc198, 0x21, 0 + .dw 0x7740, 0xc198, 0x777f, 0xc198, 0x21, 0 + .dw 0x77c0, 0xc198, 0x77ff, 0xc198, 0x21, 0 + .dw 0x7840, 0xc198, 0x787f, 0xc198, 0x21, 0 + .dw 0x78c0, 0xc198, 0x78ff, 0xc198, 0x21, 0 + .dw 0x7940, 0xc198, 0x797f, 0xc198, 0x21, 0 + .dw 0x79c0, 0xc198, 0x9fff, 0xc198, 0x21, 0 + .dw 0xa040, 0xc198, 0xa07f, 0xc198, 0x21, 0 + .dw 0xa0c0, 0xc198, 0xa0ff, 0xc198, 0x21, 0 + .dw 0xa140, 0xc198, 0xa17f, 0xc198, 0x21, 0 + .dw 0xa1c0, 0xc198, 0xa1ff, 0xc198, 0x21, 0 + .dw 0xa240, 0xc198, 0xa27f, 0xc198, 0x21, 0 + .dw 0xa2c0, 0xc198, 0xa2ff, 0xc198, 0x21, 0 + .dw 0xa340, 0xc198, 0xa37f, 0xc198, 0x21, 0 + .dw 0xa3c0, 0xc198, 0xa3ff, 0xc198, 0x21, 0 + .dw 0xa440, 0xc198, 0xa47f, 0xc198, 0x21, 0 + .dw 0xa4c0, 0xc198, 0xa4ff, 0xc198, 0x21, 0 + .dw 0xa540, 0xc198, 0xa57f, 0xc198, 0x21, 0 + .dw 0xa5c0, 0xc198, 0xa5ff, 0xc198, 0x21, 0 + .dw 0xa640, 0xc198, 0xa67f, 0xc198, 0x21, 0 + .dw 0xa6c0, 0xc198, 0xa6ff, 0xc198, 0x21, 0 + .dw 0xa740, 0xc198, 0xa77f, 0xc198, 0x21, 0 + .dw 0xa7c0, 0xc198, 0xa7ff, 0xc198, 0x21, 0 + .dw 0xa840, 0xc198, 0xa87f, 0xc198, 0x21, 0 + .dw 0xa8c0, 0xc198, 0xa8ff, 0xc198, 0x21, 0 + .dw 0xa940, 0xc198, 0xa97f, 0xc198, 0x21, 0 + .dw 0xa9c0, 0xc198, 0xa9ff, 0xc198, 0x21, 0 + .dw 0xaa40, 0xc198, 0xaa7f, 0xc198, 0x21, 0 + .dw 0xaac0, 0xc198, 0xaaff, 0xc198, 0x21, 0 + .dw 0xab40, 0xc198, 0xab7f, 0xc198, 0x21, 0 + .dw 0xabc0, 0xc198, 0xabff, 0xc198, 0x21, 0 + .dw 0xac40, 0xc198, 0xac7f, 0xc198, 0x21, 0 + .dw 0xacc0, 0xc198, 0xacff, 0xc198, 0x21, 0 + .dw 0xad40, 0xc198, 0xad7f, 0xc198, 0x21, 0 + .dw 0xadc0, 0xc198, 0xadff, 0xc198, 0x21, 0 + .dw 0xae40, 0xc198, 0xae7f, 0xc198, 0x21, 0 + .dw 0xaec0, 0xc198, 0xaeff, 0xc198, 0x21, 0 + .dw 0xaf40, 0xc198, 0xaf7f, 0xc198, 0x21, 0 + .dw 0xafc0, 0xc198, 0xafff, 0xc198, 0x21, 0 + .dw 0xb040, 0xc198, 0xb07f, 0xc198, 0x21, 0 + .dw 0xb0c0, 0xc198, 0xb0ff, 0xc198, 0x21, 0 + .dw 0xb140, 0xc198, 0xb17f, 0xc198, 0x21, 0 + .dw 0xb1c0, 0xc198, 0xb1ff, 0xc198, 0x21, 0 + .dw 0xb240, 0xc198, 0xb27f, 0xc198, 0x21, 0 + .dw 0xb2c0, 0xc198, 0xb2ff, 0xc198, 0x21, 0 + .dw 0xb340, 0xc198, 0xb37f, 0xc198, 0x21, 0 + .dw 0xb3c0, 0xc198, 0xb3ff, 0xc198, 0x21, 0 + .dw 0xb440, 0xc198, 0xb47f, 0xc198, 0x21, 0 + .dw 0xb4c0, 0xc198, 0xb4ff, 0xc198, 0x21, 0 + .dw 0xb540, 0xc198, 0xb57f, 0xc198, 0x21, 0 + .dw 0xb5c0, 0xc198, 0xb5ff, 0xc198, 0x21, 0 + .dw 0xb640, 0xc198, 0xb67f, 0xc198, 0x21, 0 + .dw 0xb6c0, 0xc198, 0xb6ff, 0xc198, 0x21, 0 + .dw 0xb740, 0xc198, 0xb77f, 0xc198, 0x21, 0 + .dw 0xb7c0, 0xc198, 0xb7ff, 0xc198, 0x21, 0 + .dw 0xb840, 0xc198, 0xb87f, 0xc198, 0x21, 0 + .dw 0xb8c0, 0xc198, 0xb8ff, 0xc198, 0x21, 0 + .dw 0xb940, 0xc198, 0xb97f, 0xc198, 0x21, 0 + .dw 0xb9c0, 0xc198, 0xdfff, 0xc198, 0x21, 0 + .dw 0xe040, 0xc198, 0xe07f, 0xc198, 0x21, 0 + .dw 0xe0c0, 0xc198, 0xe0ff, 0xc198, 0x21, 0 + .dw 0xe140, 0xc198, 0xe17f, 0xc198, 0x21, 0 + .dw 0xe1c0, 0xc198, 0xe1ff, 0xc198, 0x21, 0 + .dw 0xe240, 0xc198, 0xe27f, 0xc198, 0x21, 0 + .dw 0xe2c0, 0xc198, 0xe2ff, 0xc198, 0x21, 0 + .dw 0xe340, 0xc198, 0xe37f, 0xc198, 0x21, 0 + .dw 0xe3c0, 0xc198, 0xe3ff, 0xc198, 0x21, 0 + .dw 0xe440, 0xc198, 0xe47f, 0xc198, 0x21, 0 + .dw 0xe4c0, 0xc198, 0xe4ff, 0xc198, 0x21, 0 + .dw 0xe540, 0xc198, 0xe57f, 0xc198, 0x21, 0 + .dw 0xe5c0, 0xc198, 0xe5ff, 0xc198, 0x21, 0 + .dw 0xe640, 0xc198, 0xe67f, 0xc198, 0x21, 0 + .dw 0xe6c0, 0xc198, 0xe6ff, 0xc198, 0x21, 0 + .dw 0xe740, 0xc198, 0xe77f, 0xc198, 0x21, 0 + .dw 0xe7c0, 0xc198, 0xe7ff, 0xc198, 0x21, 0 + .dw 0xe840, 0xc198, 0xe87f, 0xc198, 0x21, 0 + .dw 0xe8c0, 0xc198, 0xe8ff, 0xc198, 0x21, 0 + .dw 0xe940, 0xc198, 0xe97f, 0xc198, 0x21, 0 + .dw 0xe9c0, 0xc198, 0xe9ff, 0xc198, 0x21, 0 + .dw 0xea40, 0xc198, 0xea7f, 0xc198, 0x21, 0 + .dw 0xeac0, 0xc198, 0xeaff, 0xc198, 0x21, 0 + .dw 0xeb40, 0xc198, 0xeb7f, 0xc198, 0x21, 0 + .dw 0xebc0, 0xc198, 0xebff, 0xc198, 0x21, 0 + .dw 0xec40, 0xc198, 0xec7f, 0xc198, 0x21, 0 + .dw 0xecc0, 0xc198, 0xecff, 0xc198, 0x21, 0 + .dw 0xed40, 0xc198, 0xed7f, 0xc198, 0x21, 0 + .dw 0xedc0, 0xc198, 0xedff, 0xc198, 0x21, 0 + .dw 0xee40, 0xc198, 0xee7f, 0xc198, 0x21, 0 + .dw 0xeec0, 0xc198, 0xeeff, 0xc198, 0x21, 0 + .dw 0xef40, 0xc198, 0xef7f, 0xc198, 0x21, 0 + .dw 0xefc0, 0xc198, 0xefff, 0xc198, 0x21, 0 + .dw 0xf040, 0xc198, 0xf07f, 0xc198, 0x21, 0 + .dw 0xf0c0, 0xc198, 0xf0ff, 0xc198, 0x21, 0 + .dw 0xf140, 0xc198, 0xf17f, 0xc198, 0x21, 0 + .dw 0xf1c0, 0xc198, 0xf1ff, 0xc198, 0x21, 0 + .dw 0xf240, 0xc198, 0xf27f, 0xc198, 0x21, 0 + .dw 0xf2c0, 0xc198, 0xf2ff, 0xc198, 0x21, 0 + .dw 0xf340, 0xc198, 0xf37f, 0xc198, 0x21, 0 + .dw 0xf3c0, 0xc198, 0xf3ff, 0xc198, 0x21, 0 + .dw 0xf440, 0xc198, 0xf47f, 0xc198, 0x21, 0 + .dw 0xf4c0, 0xc198, 0xf4ff, 0xc198, 0x21, 0 + .dw 0xf540, 0xc198, 0xf57f, 0xc198, 0x21, 0 + .dw 0xf5c0, 0xc198, 0xf5ff, 0xc198, 0x21, 0 + .dw 0xf640, 0xc198, 0xf67f, 0xc198, 0x21, 0 + .dw 0xf6c0, 0xc198, 0xf6ff, 0xc198, 0x21, 0 + .dw 0xf740, 0xc198, 0xf77f, 0xc198, 0x21, 0 + .dw 0xf7c0, 0xc198, 0xf7ff, 0xc198, 0x21, 0 + .dw 0xf840, 0xc198, 0xf87f, 0xc198, 0x21, 0 + .dw 0xf8c0, 0xc198, 0xf8ff, 0xc198, 0x21, 0 + .dw 0xf940, 0xc198, 0xf97f, 0xc198, 0x21, 0 + .dw 0xf9c0, 0xc198, 0x1fff, 0xc199, 0x21, 0 + .dw 0x2040, 0xc199, 0x207f, 0xc199, 0x21, 0 + .dw 0x20c0, 0xc199, 0x20ff, 0xc199, 0x21, 0 + .dw 0x2140, 0xc199, 0x217f, 0xc199, 0x21, 0 + .dw 0x21c0, 0xc199, 0x21ff, 0xc199, 0x21, 0 + .dw 0x2240, 0xc199, 0x227f, 0xc199, 0x21, 0 + .dw 0x22c0, 0xc199, 0x22ff, 0xc199, 0x21, 0 + .dw 0x2340, 0xc199, 0x237f, 0xc199, 0x21, 0 + .dw 0x23c0, 0xc199, 0x23ff, 0xc199, 0x21, 0 + .dw 0x2440, 0xc199, 0x247f, 0xc199, 0x21, 0 + .dw 0x24c0, 0xc199, 0x24ff, 0xc199, 0x21, 0 + .dw 0x2540, 0xc199, 0x257f, 0xc199, 0x21, 0 + .dw 0x25c0, 0xc199, 0x25ff, 0xc199, 0x21, 0 + .dw 0x2640, 0xc199, 0x267f, 0xc199, 0x21, 0 + .dw 0x26c0, 0xc199, 0x26ff, 0xc199, 0x21, 0 + .dw 0x2740, 0xc199, 0x277f, 0xc199, 0x21, 0 + .dw 0x27c0, 0xc199, 0x27ff, 0xc199, 0x21, 0 + .dw 0x2840, 0xc199, 0x287f, 0xc199, 0x21, 0 + .dw 0x28c0, 0xc199, 0x28ff, 0xc199, 0x21, 0 + .dw 0x2940, 0xc199, 0x297f, 0xc199, 0x21, 0 + .dw 0x29c0, 0xc199, 0x29ff, 0xc199, 0x21, 0 + .dw 0x2a40, 0xc199, 0x2a7f, 0xc199, 0x21, 0 + .dw 0x2ac0, 0xc199, 0x2aff, 0xc199, 0x21, 0 + .dw 0x2b40, 0xc199, 0x2b7f, 0xc199, 0x21, 0 + .dw 0x2bc0, 0xc199, 0x2bff, 0xc199, 0x21, 0 + .dw 0x2c40, 0xc199, 0x2c7f, 0xc199, 0x21, 0 + .dw 0x2cc0, 0xc199, 0x2cff, 0xc199, 0x21, 0 + .dw 0x2d40, 0xc199, 0x2d7f, 0xc199, 0x21, 0 + .dw 0x2dc0, 0xc199, 0x2dff, 0xc199, 0x21, 0 + .dw 0x2e40, 0xc199, 0x2e7f, 0xc199, 0x21, 0 + .dw 0x2ec0, 0xc199, 0x2eff, 0xc199, 0x21, 0 + .dw 0x2f40, 0xc199, 0x2f7f, 0xc199, 0x21, 0 + .dw 0x2fc0, 0xc199, 0x2fff, 0xc199, 0x21, 0 + .dw 0x3040, 0xc199, 0x307f, 0xc199, 0x21, 0 + .dw 0x30c0, 0xc199, 0x30ff, 0xc199, 0x21, 0 + .dw 0x3140, 0xc199, 0x317f, 0xc199, 0x21, 0 + .dw 0x31c0, 0xc199, 0x31ff, 0xc199, 0x21, 0 + .dw 0x3240, 0xc199, 0x327f, 0xc199, 0x21, 0 + .dw 0x32c0, 0xc199, 0x32ff, 0xc199, 0x21, 0 + .dw 0x3340, 0xc199, 0x337f, 0xc199, 0x21, 0 + .dw 0x33c0, 0xc199, 0x33ff, 0xc199, 0x21, 0 + .dw 0x3440, 0xc199, 0x347f, 0xc199, 0x21, 0 + .dw 0x34c0, 0xc199, 0x34ff, 0xc199, 0x21, 0 + .dw 0x3540, 0xc199, 0x357f, 0xc199, 0x21, 0 + .dw 0x35c0, 0xc199, 0x35ff, 0xc199, 0x21, 0 + .dw 0x3640, 0xc199, 0x367f, 0xc199, 0x21, 0 + .dw 0x36c0, 0xc199, 0x36ff, 0xc199, 0x21, 0 + .dw 0x3740, 0xc199, 0x377f, 0xc199, 0x21, 0 + .dw 0x37c0, 0xc199, 0x37ff, 0xc199, 0x21, 0 + .dw 0x3840, 0xc199, 0x387f, 0xc199, 0x21, 0 + .dw 0x38c0, 0xc199, 0x38ff, 0xc199, 0x21, 0 + .dw 0x3940, 0xc199, 0x397f, 0xc199, 0x21, 0 + .dw 0x39c0, 0xc199, 0x5fff, 0xc199, 0x21, 0 + .dw 0x6040, 0xc199, 0x607f, 0xc199, 0x21, 0 + .dw 0x60c0, 0xc199, 0x60ff, 0xc199, 0x21, 0 + .dw 0x6140, 0xc199, 0x617f, 0xc199, 0x21, 0 + .dw 0x61c0, 0xc199, 0x61ff, 0xc199, 0x21, 0 + .dw 0x6240, 0xc199, 0x627f, 0xc199, 0x21, 0 + .dw 0x62c0, 0xc199, 0x62ff, 0xc199, 0x21, 0 + .dw 0x6340, 0xc199, 0x637f, 0xc199, 0x21, 0 + .dw 0x63c0, 0xc199, 0x63ff, 0xc199, 0x21, 0 + .dw 0x6440, 0xc199, 0x647f, 0xc199, 0x21, 0 + .dw 0x64c0, 0xc199, 0x64ff, 0xc199, 0x21, 0 + .dw 0x6540, 0xc199, 0x657f, 0xc199, 0x21, 0 + .dw 0x65c0, 0xc199, 0x65ff, 0xc199, 0x21, 0 + .dw 0x6640, 0xc199, 0x667f, 0xc199, 0x21, 0 + .dw 0x66c0, 0xc199, 0x66ff, 0xc199, 0x21, 0 + .dw 0x6740, 0xc199, 0x677f, 0xc199, 0x21, 0 + .dw 0x67c0, 0xc199, 0x67ff, 0xc199, 0x21, 0 + .dw 0x6840, 0xc199, 0x687f, 0xc199, 0x21, 0 + .dw 0x68c0, 0xc199, 0x68ff, 0xc199, 0x21, 0 + .dw 0x6940, 0xc199, 0x697f, 0xc199, 0x21, 0 + .dw 0x69c0, 0xc199, 0x69ff, 0xc199, 0x21, 0 + .dw 0x6a40, 0xc199, 0x6a7f, 0xc199, 0x21, 0 + .dw 0x6ac0, 0xc199, 0x6aff, 0xc199, 0x21, 0 + .dw 0x6b40, 0xc199, 0x6b7f, 0xc199, 0x21, 0 + .dw 0x6bc0, 0xc199, 0x6bff, 0xc199, 0x21, 0 + .dw 0x6c40, 0xc199, 0x6c7f, 0xc199, 0x21, 0 + .dw 0x6cc0, 0xc199, 0x6cff, 0xc199, 0x21, 0 + .dw 0x6d40, 0xc199, 0x6d7f, 0xc199, 0x21, 0 + .dw 0x6dc0, 0xc199, 0x6dff, 0xc199, 0x21, 0 + .dw 0x6e40, 0xc199, 0x6e7f, 0xc199, 0x21, 0 + .dw 0x6ec0, 0xc199, 0x6eff, 0xc199, 0x21, 0 + .dw 0x6f40, 0xc199, 0x6f7f, 0xc199, 0x21, 0 + .dw 0x6fc0, 0xc199, 0x6fff, 0xc199, 0x21, 0 + .dw 0x7040, 0xc199, 0x707f, 0xc199, 0x21, 0 + .dw 0x70c0, 0xc199, 0x70ff, 0xc199, 0x21, 0 + .dw 0x7140, 0xc199, 0x717f, 0xc199, 0x21, 0 + .dw 0x71c0, 0xc199, 0x71ff, 0xc199, 0x21, 0 + .dw 0x7240, 0xc199, 0x727f, 0xc199, 0x21, 0 + .dw 0x72c0, 0xc199, 0x72ff, 0xc199, 0x21, 0 + .dw 0x7340, 0xc199, 0x737f, 0xc199, 0x21, 0 + .dw 0x73c0, 0xc199, 0x73ff, 0xc199, 0x21, 0 + .dw 0x7440, 0xc199, 0x747f, 0xc199, 0x21, 0 + .dw 0x74c0, 0xc199, 0x74ff, 0xc199, 0x21, 0 + .dw 0x7540, 0xc199, 0x757f, 0xc199, 0x21, 0 + .dw 0x75c0, 0xc199, 0x75ff, 0xc199, 0x21, 0 + .dw 0x7640, 0xc199, 0x767f, 0xc199, 0x21, 0 + .dw 0x76c0, 0xc199, 0x76ff, 0xc199, 0x21, 0 + .dw 0x7740, 0xc199, 0x777f, 0xc199, 0x21, 0 + .dw 0x77c0, 0xc199, 0x77ff, 0xc199, 0x21, 0 + .dw 0x7840, 0xc199, 0x787f, 0xc199, 0x21, 0 + .dw 0x78c0, 0xc199, 0x78ff, 0xc199, 0x21, 0 + .dw 0x7940, 0xc199, 0x797f, 0xc199, 0x21, 0 + .dw 0x79c0, 0xc199, 0x9fff, 0xc199, 0x21, 0 + .dw 0xa040, 0xc199, 0xa07f, 0xc199, 0x21, 0 + .dw 0xa0c0, 0xc199, 0xa0ff, 0xc199, 0x21, 0 + .dw 0xa140, 0xc199, 0xa17f, 0xc199, 0x21, 0 + .dw 0xa1c0, 0xc199, 0xa1ff, 0xc199, 0x21, 0 + .dw 0xa240, 0xc199, 0xa27f, 0xc199, 0x21, 0 + .dw 0xa2c0, 0xc199, 0xa2ff, 0xc199, 0x21, 0 + .dw 0xa340, 0xc199, 0xa37f, 0xc199, 0x21, 0 + .dw 0xa3c0, 0xc199, 0xa3ff, 0xc199, 0x21, 0 + .dw 0xa440, 0xc199, 0xa47f, 0xc199, 0x21, 0 + .dw 0xa4c0, 0xc199, 0xa4ff, 0xc199, 0x21, 0 + .dw 0xa540, 0xc199, 0xa57f, 0xc199, 0x21, 0 + .dw 0xa5c0, 0xc199, 0xa5ff, 0xc199, 0x21, 0 + .dw 0xa640, 0xc199, 0xa67f, 0xc199, 0x21, 0 + .dw 0xa6c0, 0xc199, 0xa6ff, 0xc199, 0x21, 0 + .dw 0xa740, 0xc199, 0xa77f, 0xc199, 0x21, 0 + .dw 0xa7c0, 0xc199, 0xa7ff, 0xc199, 0x21, 0 + .dw 0xa840, 0xc199, 0xa87f, 0xc199, 0x21, 0 + .dw 0xa8c0, 0xc199, 0xa8ff, 0xc199, 0x21, 0 + .dw 0xa940, 0xc199, 0xa97f, 0xc199, 0x21, 0 + .dw 0xa9c0, 0xc199, 0xa9ff, 0xc199, 0x21, 0 + .dw 0xaa40, 0xc199, 0xaa7f, 0xc199, 0x21, 0 + .dw 0xaac0, 0xc199, 0xaaff, 0xc199, 0x21, 0 + .dw 0xab40, 0xc199, 0xab7f, 0xc199, 0x21, 0 + .dw 0xabc0, 0xc199, 0xabff, 0xc199, 0x21, 0 + .dw 0xac40, 0xc199, 0xac7f, 0xc199, 0x21, 0 + .dw 0xacc0, 0xc199, 0xacff, 0xc199, 0x21, 0 + .dw 0xad40, 0xc199, 0xad7f, 0xc199, 0x21, 0 + .dw 0xadc0, 0xc199, 0xadff, 0xc199, 0x21, 0 + .dw 0xae40, 0xc199, 0xae7f, 0xc199, 0x21, 0 + .dw 0xaec0, 0xc199, 0xaeff, 0xc199, 0x21, 0 + .dw 0xaf40, 0xc199, 0xaf7f, 0xc199, 0x21, 0 + .dw 0xafc0, 0xc199, 0xafff, 0xc199, 0x21, 0 + .dw 0xb040, 0xc199, 0xb07f, 0xc199, 0x21, 0 + .dw 0xb0c0, 0xc199, 0xb0ff, 0xc199, 0x21, 0 + .dw 0xb140, 0xc199, 0xb17f, 0xc199, 0x21, 0 + .dw 0xb1c0, 0xc199, 0xb1ff, 0xc199, 0x21, 0 + .dw 0xb240, 0xc199, 0xb27f, 0xc199, 0x21, 0 + .dw 0xb2c0, 0xc199, 0xb2ff, 0xc199, 0x21, 0 + .dw 0xb340, 0xc199, 0xb37f, 0xc199, 0x21, 0 + .dw 0xb3c0, 0xc199, 0xb3ff, 0xc199, 0x21, 0 + .dw 0xb440, 0xc199, 0xb47f, 0xc199, 0x21, 0 + .dw 0xb4c0, 0xc199, 0xb4ff, 0xc199, 0x21, 0 + .dw 0xb540, 0xc199, 0xb57f, 0xc199, 0x21, 0 + .dw 0xb5c0, 0xc199, 0xb5ff, 0xc199, 0x21, 0 + .dw 0xb640, 0xc199, 0xb67f, 0xc199, 0x21, 0 + .dw 0xb6c0, 0xc199, 0xb6ff, 0xc199, 0x21, 0 + .dw 0xb740, 0xc199, 0xb77f, 0xc199, 0x21, 0 + .dw 0xb7c0, 0xc199, 0xb7ff, 0xc199, 0x21, 0 + .dw 0xb840, 0xc199, 0xb87f, 0xc199, 0x21, 0 + .dw 0xb8c0, 0xc199, 0xb8ff, 0xc199, 0x21, 0 + .dw 0xb940, 0xc199, 0xb97f, 0xc199, 0x21, 0 + .dw 0xb9c0, 0xc199, 0xdfff, 0xc199, 0x21, 0 + .dw 0xe040, 0xc199, 0xe07f, 0xc199, 0x21, 0 + .dw 0xe0c0, 0xc199, 0xe0ff, 0xc199, 0x21, 0 + .dw 0xe140, 0xc199, 0xe17f, 0xc199, 0x21, 0 + .dw 0xe1c0, 0xc199, 0xe1ff, 0xc199, 0x21, 0 + .dw 0xe240, 0xc199, 0xe27f, 0xc199, 0x21, 0 + .dw 0xe2c0, 0xc199, 0xe2ff, 0xc199, 0x21, 0 + .dw 0xe340, 0xc199, 0xe37f, 0xc199, 0x21, 0 + .dw 0xe3c0, 0xc199, 0xe3ff, 0xc199, 0x21, 0 + .dw 0xe440, 0xc199, 0xe47f, 0xc199, 0x21, 0 + .dw 0xe4c0, 0xc199, 0xe4ff, 0xc199, 0x21, 0 + .dw 0xe540, 0xc199, 0xe57f, 0xc199, 0x21, 0 + .dw 0xe5c0, 0xc199, 0xe5ff, 0xc199, 0x21, 0 + .dw 0xe640, 0xc199, 0xe67f, 0xc199, 0x21, 0 + .dw 0xe6c0, 0xc199, 0xe6ff, 0xc199, 0x21, 0 + .dw 0xe740, 0xc199, 0xe77f, 0xc199, 0x21, 0 + .dw 0xe7c0, 0xc199, 0xe7ff, 0xc199, 0x21, 0 + .dw 0xe840, 0xc199, 0xe87f, 0xc199, 0x21, 0 + .dw 0xe8c0, 0xc199, 0xe8ff, 0xc199, 0x21, 0 + .dw 0xe940, 0xc199, 0xe97f, 0xc199, 0x21, 0 + .dw 0xe9c0, 0xc199, 0xe9ff, 0xc199, 0x21, 0 + .dw 0xea40, 0xc199, 0xea7f, 0xc199, 0x21, 0 + .dw 0xeac0, 0xc199, 0xeaff, 0xc199, 0x21, 0 + .dw 0xeb40, 0xc199, 0xeb7f, 0xc199, 0x21, 0 + .dw 0xebc0, 0xc199, 0xebff, 0xc199, 0x21, 0 + .dw 0xec40, 0xc199, 0xec7f, 0xc199, 0x21, 0 + .dw 0xecc0, 0xc199, 0xecff, 0xc199, 0x21, 0 + .dw 0xed40, 0xc199, 0xed7f, 0xc199, 0x21, 0 + .dw 0xedc0, 0xc199, 0xedff, 0xc199, 0x21, 0 + .dw 0xee40, 0xc199, 0xee7f, 0xc199, 0x21, 0 + .dw 0xeec0, 0xc199, 0xeeff, 0xc199, 0x21, 0 + .dw 0xef40, 0xc199, 0xef7f, 0xc199, 0x21, 0 + .dw 0xefc0, 0xc199, 0xefff, 0xc199, 0x21, 0 + .dw 0xf040, 0xc199, 0xf07f, 0xc199, 0x21, 0 + .dw 0xf0c0, 0xc199, 0xf0ff, 0xc199, 0x21, 0 + .dw 0xf140, 0xc199, 0xf17f, 0xc199, 0x21, 0 + .dw 0xf1c0, 0xc199, 0xf1ff, 0xc199, 0x21, 0 + .dw 0xf240, 0xc199, 0xf27f, 0xc199, 0x21, 0 + .dw 0xf2c0, 0xc199, 0xf2ff, 0xc199, 0x21, 0 + .dw 0xf340, 0xc199, 0xf37f, 0xc199, 0x21, 0 + .dw 0xf3c0, 0xc199, 0xf3ff, 0xc199, 0x21, 0 + .dw 0xf440, 0xc199, 0xf47f, 0xc199, 0x21, 0 + .dw 0xf4c0, 0xc199, 0xf4ff, 0xc199, 0x21, 0 + .dw 0xf540, 0xc199, 0xf57f, 0xc199, 0x21, 0 + .dw 0xf5c0, 0xc199, 0xf5ff, 0xc199, 0x21, 0 + .dw 0xf640, 0xc199, 0xf67f, 0xc199, 0x21, 0 + .dw 0xf6c0, 0xc199, 0xf6ff, 0xc199, 0x21, 0 + .dw 0xf740, 0xc199, 0xf77f, 0xc199, 0x21, 0 + .dw 0xf7c0, 0xc199, 0xf7ff, 0xc199, 0x21, 0 + .dw 0xf840, 0xc199, 0xf87f, 0xc199, 0x21, 0 + .dw 0xf8c0, 0xc199, 0xf8ff, 0xc199, 0x21, 0 + .dw 0xf940, 0xc199, 0xf97f, 0xc199, 0x21, 0 + .dw 0xf9c0, 0xc199, 0x1fff, 0xc19a, 0x21, 0 + .dw 0x2040, 0xc19a, 0x207f, 0xc19a, 0x21, 0 + .dw 0x20c0, 0xc19a, 0x20ff, 0xc19a, 0x21, 0 + .dw 0x2140, 0xc19a, 0x217f, 0xc19a, 0x21, 0 + .dw 0x21c0, 0xc19a, 0x21ff, 0xc19a, 0x21, 0 + .dw 0x2240, 0xc19a, 0x227f, 0xc19a, 0x21, 0 + .dw 0x22c0, 0xc19a, 0x22ff, 0xc19a, 0x21, 0 + .dw 0x2340, 0xc19a, 0x237f, 0xc19a, 0x21, 0 + .dw 0x23c0, 0xc19a, 0x23ff, 0xc19a, 0x21, 0 + .dw 0x2440, 0xc19a, 0x247f, 0xc19a, 0x21, 0 + .dw 0x24c0, 0xc19a, 0x24ff, 0xc19a, 0x21, 0 + .dw 0x2540, 0xc19a, 0x257f, 0xc19a, 0x21, 0 + .dw 0x25c0, 0xc19a, 0x25ff, 0xc19a, 0x21, 0 + .dw 0x2640, 0xc19a, 0x267f, 0xc19a, 0x21, 0 + .dw 0x26c0, 0xc19a, 0x26ff, 0xc19a, 0x21, 0 + .dw 0x2740, 0xc19a, 0x277f, 0xc19a, 0x21, 0 + .dw 0x27c0, 0xc19a, 0x27ff, 0xc19a, 0x21, 0 + .dw 0x2840, 0xc19a, 0x287f, 0xc19a, 0x21, 0 + .dw 0x28c0, 0xc19a, 0x28ff, 0xc19a, 0x21, 0 + .dw 0x2940, 0xc19a, 0x297f, 0xc19a, 0x21, 0 + .dw 0x29c0, 0xc19a, 0x29ff, 0xc19a, 0x21, 0 + .dw 0x2a40, 0xc19a, 0x2a7f, 0xc19a, 0x21, 0 + .dw 0x2ac0, 0xc19a, 0x2aff, 0xc19a, 0x21, 0 + .dw 0x2b40, 0xc19a, 0x2b7f, 0xc19a, 0x21, 0 + .dw 0x2bc0, 0xc19a, 0x2bff, 0xc19a, 0x21, 0 + .dw 0x2c40, 0xc19a, 0x2c7f, 0xc19a, 0x21, 0 + .dw 0x2cc0, 0xc19a, 0x2cff, 0xc19a, 0x21, 0 + .dw 0x2d40, 0xc19a, 0x2d7f, 0xc19a, 0x21, 0 + .dw 0x2dc0, 0xc19a, 0x2dff, 0xc19a, 0x21, 0 + .dw 0x2e40, 0xc19a, 0x2e7f, 0xc19a, 0x21, 0 + .dw 0x2ec0, 0xc19a, 0x2eff, 0xc19a, 0x21, 0 + .dw 0x2f40, 0xc19a, 0x2f7f, 0xc19a, 0x21, 0 + .dw 0x2fc0, 0xc19a, 0x2fff, 0xc19a, 0x21, 0 + .dw 0x3040, 0xc19a, 0x307f, 0xc19a, 0x21, 0 + .dw 0x30c0, 0xc19a, 0x30ff, 0xc19a, 0x21, 0 + .dw 0x3140, 0xc19a, 0x317f, 0xc19a, 0x21, 0 + .dw 0x31c0, 0xc19a, 0x31ff, 0xc19a, 0x21, 0 + .dw 0x3240, 0xc19a, 0x327f, 0xc19a, 0x21, 0 + .dw 0x32c0, 0xc19a, 0x32ff, 0xc19a, 0x21, 0 + .dw 0x3340, 0xc19a, 0x337f, 0xc19a, 0x21, 0 + .dw 0x33c0, 0xc19a, 0x33ff, 0xc19a, 0x21, 0 + .dw 0x3440, 0xc19a, 0x347f, 0xc19a, 0x21, 0 + .dw 0x34c0, 0xc19a, 0x34ff, 0xc19a, 0x21, 0 + .dw 0x3540, 0xc19a, 0x357f, 0xc19a, 0x21, 0 + .dw 0x35c0, 0xc19a, 0x35ff, 0xc19a, 0x21, 0 + .dw 0x3640, 0xc19a, 0x367f, 0xc19a, 0x21, 0 + .dw 0x36c0, 0xc19a, 0x36ff, 0xc19a, 0x21, 0 + .dw 0x3740, 0xc19a, 0x377f, 0xc19a, 0x21, 0 + .dw 0x37c0, 0xc19a, 0x37ff, 0xc19a, 0x21, 0 + .dw 0x3840, 0xc19a, 0x387f, 0xc19a, 0x21, 0 + .dw 0x38c0, 0xc19a, 0x38ff, 0xc19a, 0x21, 0 + .dw 0x3940, 0xc19a, 0x397f, 0xc19a, 0x21, 0 + .dw 0x39c0, 0xc19a, 0x5fff, 0xc19a, 0x21, 0 + .dw 0x6040, 0xc19a, 0x607f, 0xc19a, 0x21, 0 + .dw 0x60c0, 0xc19a, 0x60ff, 0xc19a, 0x21, 0 + .dw 0x6140, 0xc19a, 0x617f, 0xc19a, 0x21, 0 + .dw 0x61c0, 0xc19a, 0x61ff, 0xc19a, 0x21, 0 + .dw 0x6240, 0xc19a, 0x627f, 0xc19a, 0x21, 0 + .dw 0x62c0, 0xc19a, 0x62ff, 0xc19a, 0x21, 0 + .dw 0x6340, 0xc19a, 0x637f, 0xc19a, 0x21, 0 + .dw 0x63c0, 0xc19a, 0x63ff, 0xc19a, 0x21, 0 + .dw 0x6440, 0xc19a, 0x647f, 0xc19a, 0x21, 0 + .dw 0x64c0, 0xc19a, 0x64ff, 0xc19a, 0x21, 0 + .dw 0x6540, 0xc19a, 0x657f, 0xc19a, 0x21, 0 + .dw 0x65c0, 0xc19a, 0x65ff, 0xc19a, 0x21, 0 + .dw 0x6640, 0xc19a, 0x667f, 0xc19a, 0x21, 0 + .dw 0x66c0, 0xc19a, 0x66ff, 0xc19a, 0x21, 0 + .dw 0x6740, 0xc19a, 0x677f, 0xc19a, 0x21, 0 + .dw 0x67c0, 0xc19a, 0x67ff, 0xc19a, 0x21, 0 + .dw 0x6840, 0xc19a, 0x687f, 0xc19a, 0x21, 0 + .dw 0x68c0, 0xc19a, 0x68ff, 0xc19a, 0x21, 0 + .dw 0x6940, 0xc19a, 0x697f, 0xc19a, 0x21, 0 + .dw 0x69c0, 0xc19a, 0x69ff, 0xc19a, 0x21, 0 + .dw 0x6a40, 0xc19a, 0x6a7f, 0xc19a, 0x21, 0 + .dw 0x6ac0, 0xc19a, 0x6aff, 0xc19a, 0x21, 0 + .dw 0x6b40, 0xc19a, 0x6b7f, 0xc19a, 0x21, 0 + .dw 0x6bc0, 0xc19a, 0x6bff, 0xc19a, 0x21, 0 + .dw 0x6c40, 0xc19a, 0x6c7f, 0xc19a, 0x21, 0 + .dw 0x6cc0, 0xc19a, 0x6cff, 0xc19a, 0x21, 0 + .dw 0x6d40, 0xc19a, 0x6d7f, 0xc19a, 0x21, 0 + .dw 0x6dc0, 0xc19a, 0x6dff, 0xc19a, 0x21, 0 + .dw 0x6e40, 0xc19a, 0x6e7f, 0xc19a, 0x21, 0 + .dw 0x6ec0, 0xc19a, 0x6eff, 0xc19a, 0x21, 0 + .dw 0x6f40, 0xc19a, 0x6f7f, 0xc19a, 0x21, 0 + .dw 0x6fc0, 0xc19a, 0x6fff, 0xc19a, 0x21, 0 + .dw 0x7040, 0xc19a, 0x707f, 0xc19a, 0x21, 0 + .dw 0x70c0, 0xc19a, 0x70ff, 0xc19a, 0x21, 0 + .dw 0x7140, 0xc19a, 0x717f, 0xc19a, 0x21, 0 + .dw 0x71c0, 0xc19a, 0x71ff, 0xc19a, 0x21, 0 + .dw 0x7240, 0xc19a, 0x727f, 0xc19a, 0x21, 0 + .dw 0x72c0, 0xc19a, 0x72ff, 0xc19a, 0x21, 0 + .dw 0x7340, 0xc19a, 0x737f, 0xc19a, 0x21, 0 + .dw 0x73c0, 0xc19a, 0x73ff, 0xc19a, 0x21, 0 + .dw 0x7440, 0xc19a, 0x747f, 0xc19a, 0x21, 0 + .dw 0x74c0, 0xc19a, 0x74ff, 0xc19a, 0x21, 0 + .dw 0x7540, 0xc19a, 0x757f, 0xc19a, 0x21, 0 + .dw 0x75c0, 0xc19a, 0x75ff, 0xc19a, 0x21, 0 + .dw 0x7640, 0xc19a, 0x767f, 0xc19a, 0x21, 0 + .dw 0x76c0, 0xc19a, 0x76ff, 0xc19a, 0x21, 0 + .dw 0x7740, 0xc19a, 0x777f, 0xc19a, 0x21, 0 + .dw 0x77c0, 0xc19a, 0x77ff, 0xc19a, 0x21, 0 + .dw 0x7840, 0xc19a, 0x787f, 0xc19a, 0x21, 0 + .dw 0x78c0, 0xc19a, 0x78ff, 0xc19a, 0x21, 0 + .dw 0x7940, 0xc19a, 0x797f, 0xc19a, 0x21, 0 + .dw 0x79c0, 0xc19a, 0x9fff, 0xc19a, 0x21, 0 + .dw 0xa040, 0xc19a, 0xa07f, 0xc19a, 0x21, 0 + .dw 0xa0c0, 0xc19a, 0xa0ff, 0xc19a, 0x21, 0 + .dw 0xa140, 0xc19a, 0xa17f, 0xc19a, 0x21, 0 + .dw 0xa1c0, 0xc19a, 0xa1ff, 0xc19a, 0x21, 0 + .dw 0xa240, 0xc19a, 0xa27f, 0xc19a, 0x21, 0 + .dw 0xa2c0, 0xc19a, 0xa2ff, 0xc19a, 0x21, 0 + .dw 0xa340, 0xc19a, 0xa37f, 0xc19a, 0x21, 0 + .dw 0xa3c0, 0xc19a, 0xa3ff, 0xc19a, 0x21, 0 + .dw 0xa440, 0xc19a, 0xa47f, 0xc19a, 0x21, 0 + .dw 0xa4c0, 0xc19a, 0xa4ff, 0xc19a, 0x21, 0 + .dw 0xa540, 0xc19a, 0xa57f, 0xc19a, 0x21, 0 + .dw 0xa5c0, 0xc19a, 0xa5ff, 0xc19a, 0x21, 0 + .dw 0xa640, 0xc19a, 0xa67f, 0xc19a, 0x21, 0 + .dw 0xa6c0, 0xc19a, 0xa6ff, 0xc19a, 0x21, 0 + .dw 0xa740, 0xc19a, 0xa77f, 0xc19a, 0x21, 0 + .dw 0xa7c0, 0xc19a, 0xa7ff, 0xc19a, 0x21, 0 + .dw 0xa840, 0xc19a, 0xa87f, 0xc19a, 0x21, 0 + .dw 0xa8c0, 0xc19a, 0xa8ff, 0xc19a, 0x21, 0 + .dw 0xa940, 0xc19a, 0xa97f, 0xc19a, 0x21, 0 + .dw 0xa9c0, 0xc19a, 0xa9ff, 0xc19a, 0x21, 0 + .dw 0xaa40, 0xc19a, 0xaa7f, 0xc19a, 0x21, 0 + .dw 0xaac0, 0xc19a, 0xaaff, 0xc19a, 0x21, 0 + .dw 0xab40, 0xc19a, 0xab7f, 0xc19a, 0x21, 0 + .dw 0xabc0, 0xc19a, 0xabff, 0xc19a, 0x21, 0 + .dw 0xac40, 0xc19a, 0xac7f, 0xc19a, 0x21, 0 + .dw 0xacc0, 0xc19a, 0xacff, 0xc19a, 0x21, 0 + .dw 0xad40, 0xc19a, 0xad7f, 0xc19a, 0x21, 0 + .dw 0xadc0, 0xc19a, 0xadff, 0xc19a, 0x21, 0 + .dw 0xae40, 0xc19a, 0xae7f, 0xc19a, 0x21, 0 + .dw 0xaec0, 0xc19a, 0xaeff, 0xc19a, 0x21, 0 + .dw 0xaf40, 0xc19a, 0xaf7f, 0xc19a, 0x21, 0 + .dw 0xafc0, 0xc19a, 0xafff, 0xc19a, 0x21, 0 + .dw 0xb040, 0xc19a, 0xb07f, 0xc19a, 0x21, 0 + .dw 0xb0c0, 0xc19a, 0xb0ff, 0xc19a, 0x21, 0 + .dw 0xb140, 0xc19a, 0xb17f, 0xc19a, 0x21, 0 + .dw 0xb1c0, 0xc19a, 0xb1ff, 0xc19a, 0x21, 0 + .dw 0xb240, 0xc19a, 0xb27f, 0xc19a, 0x21, 0 + .dw 0xb2c0, 0xc19a, 0xb2ff, 0xc19a, 0x21, 0 + .dw 0xb340, 0xc19a, 0xb37f, 0xc19a, 0x21, 0 + .dw 0xb3c0, 0xc19a, 0xb3ff, 0xc19a, 0x21, 0 + .dw 0xb440, 0xc19a, 0xb47f, 0xc19a, 0x21, 0 + .dw 0xb4c0, 0xc19a, 0xb4ff, 0xc19a, 0x21, 0 + .dw 0xb540, 0xc19a, 0xb57f, 0xc19a, 0x21, 0 + .dw 0xb5c0, 0xc19a, 0xb5ff, 0xc19a, 0x21, 0 + .dw 0xb640, 0xc19a, 0xb67f, 0xc19a, 0x21, 0 + .dw 0xb6c0, 0xc19a, 0xb6ff, 0xc19a, 0x21, 0 + .dw 0xb740, 0xc19a, 0xb77f, 0xc19a, 0x21, 0 + .dw 0xb7c0, 0xc19a, 0xb7ff, 0xc19a, 0x21, 0 + .dw 0xb840, 0xc19a, 0xb87f, 0xc19a, 0x21, 0 + .dw 0xb8c0, 0xc19a, 0xb8ff, 0xc19a, 0x21, 0 + .dw 0xb940, 0xc19a, 0xb97f, 0xc19a, 0x21, 0 + .dw 0xb9c0, 0xc19a, 0xdfff, 0xc19a, 0x21, 0 + .dw 0xe040, 0xc19a, 0xe07f, 0xc19a, 0x21, 0 + .dw 0xe0c0, 0xc19a, 0xe0ff, 0xc19a, 0x21, 0 + .dw 0xe140, 0xc19a, 0xe17f, 0xc19a, 0x21, 0 + .dw 0xe1c0, 0xc19a, 0xe1ff, 0xc19a, 0x21, 0 + .dw 0xe240, 0xc19a, 0xe27f, 0xc19a, 0x21, 0 + .dw 0xe2c0, 0xc19a, 0xe2ff, 0xc19a, 0x21, 0 + .dw 0xe340, 0xc19a, 0xe37f, 0xc19a, 0x21, 0 + .dw 0xe3c0, 0xc19a, 0xe3ff, 0xc19a, 0x21, 0 + .dw 0xe440, 0xc19a, 0xe47f, 0xc19a, 0x21, 0 + .dw 0xe4c0, 0xc19a, 0xe4ff, 0xc19a, 0x21, 0 + .dw 0xe540, 0xc19a, 0xe57f, 0xc19a, 0x21, 0 + .dw 0xe5c0, 0xc19a, 0xe5ff, 0xc19a, 0x21, 0 + .dw 0xe640, 0xc19a, 0xe67f, 0xc19a, 0x21, 0 + .dw 0xe6c0, 0xc19a, 0xe6ff, 0xc19a, 0x21, 0 + .dw 0xe740, 0xc19a, 0xe77f, 0xc19a, 0x21, 0 + .dw 0xe7c0, 0xc19a, 0xe7ff, 0xc19a, 0x21, 0 + .dw 0xe840, 0xc19a, 0xe87f, 0xc19a, 0x21, 0 + .dw 0xe8c0, 0xc19a, 0xe8ff, 0xc19a, 0x21, 0 + .dw 0xe940, 0xc19a, 0xe97f, 0xc19a, 0x21, 0 + .dw 0xe9c0, 0xc19a, 0xe9ff, 0xc19a, 0x21, 0 + .dw 0xea40, 0xc19a, 0xea7f, 0xc19a, 0x21, 0 + .dw 0xeac0, 0xc19a, 0xeaff, 0xc19a, 0x21, 0 + .dw 0xeb40, 0xc19a, 0xeb7f, 0xc19a, 0x21, 0 + .dw 0xebc0, 0xc19a, 0xebff, 0xc19a, 0x21, 0 + .dw 0xec40, 0xc19a, 0xec7f, 0xc19a, 0x21, 0 + .dw 0xecc0, 0xc19a, 0xecff, 0xc19a, 0x21, 0 + .dw 0xed40, 0xc19a, 0xed7f, 0xc19a, 0x21, 0 + .dw 0xedc0, 0xc19a, 0xedff, 0xc19a, 0x21, 0 + .dw 0xee40, 0xc19a, 0xee7f, 0xc19a, 0x21, 0 + .dw 0xeec0, 0xc19a, 0xeeff, 0xc19a, 0x21, 0 + .dw 0xef40, 0xc19a, 0xef7f, 0xc19a, 0x21, 0 + .dw 0xefc0, 0xc19a, 0xefff, 0xc19a, 0x21, 0 + .dw 0xf040, 0xc19a, 0xf07f, 0xc19a, 0x21, 0 + .dw 0xf0c0, 0xc19a, 0xf0ff, 0xc19a, 0x21, 0 + .dw 0xf140, 0xc19a, 0xf17f, 0xc19a, 0x21, 0 + .dw 0xf1c0, 0xc19a, 0xf1ff, 0xc19a, 0x21, 0 + .dw 0xf240, 0xc19a, 0xf27f, 0xc19a, 0x21, 0 + .dw 0xf2c0, 0xc19a, 0xf2ff, 0xc19a, 0x21, 0 + .dw 0xf340, 0xc19a, 0xf37f, 0xc19a, 0x21, 0 + .dw 0xf3c0, 0xc19a, 0xf3ff, 0xc19a, 0x21, 0 + .dw 0xf440, 0xc19a, 0xf47f, 0xc19a, 0x21, 0 + .dw 0xf4c0, 0xc19a, 0xf4ff, 0xc19a, 0x21, 0 + .dw 0xf540, 0xc19a, 0xf57f, 0xc19a, 0x21, 0 + .dw 0xf5c0, 0xc19a, 0xf5ff, 0xc19a, 0x21, 0 + .dw 0xf640, 0xc19a, 0xf67f, 0xc19a, 0x21, 0 + .dw 0xf6c0, 0xc19a, 0xf6ff, 0xc19a, 0x21, 0 + .dw 0xf740, 0xc19a, 0xf77f, 0xc19a, 0x21, 0 + .dw 0xf7c0, 0xc19a, 0xf7ff, 0xc19a, 0x21, 0 + .dw 0xf840, 0xc19a, 0xf87f, 0xc19a, 0x21, 0 + .dw 0xf8c0, 0xc19a, 0xf8ff, 0xc19a, 0x21, 0 + .dw 0xf940, 0xc19a, 0xf97f, 0xc19a, 0x21, 0 + .dw 0xf9c0, 0xc19a, 0xffff, 0xc19b, 0x21, 0 + .dw 0x0040, 0xc19c, 0x007f, 0xc19c, 0x21, 0 + .dw 0x00c0, 0xc19c, 0x00ff, 0xc19c, 0x21, 0 + .dw 0x0140, 0xc19c, 0x017f, 0xc19c, 0x21, 0 + .dw 0x01c0, 0xc19c, 0x01ff, 0xc19c, 0x21, 0 + .dw 0x0240, 0xc19c, 0x027f, 0xc19c, 0x21, 0 + .dw 0x02c0, 0xc19c, 0x02ff, 0xc19c, 0x21, 0 + .dw 0x0340, 0xc19c, 0x037f, 0xc19c, 0x21, 0 + .dw 0x03c0, 0xc19c, 0x03ff, 0xc19c, 0x21, 0 + .dw 0x0440, 0xc19c, 0x047f, 0xc19c, 0x21, 0 + .dw 0x04c0, 0xc19c, 0x04ff, 0xc19c, 0x21, 0 + .dw 0x0540, 0xc19c, 0x057f, 0xc19c, 0x21, 0 + .dw 0x05c0, 0xc19c, 0x05ff, 0xc19c, 0x21, 0 + .dw 0x0640, 0xc19c, 0x067f, 0xc19c, 0x21, 0 + .dw 0x06c0, 0xc19c, 0x06ff, 0xc19c, 0x21, 0 + .dw 0x0740, 0xc19c, 0x077f, 0xc19c, 0x21, 0 + .dw 0x07c0, 0xc19c, 0x07ff, 0xc19c, 0x21, 0 + .dw 0x0840, 0xc19c, 0x087f, 0xc19c, 0x21, 0 + .dw 0x08c0, 0xc19c, 0x08ff, 0xc19c, 0x21, 0 + .dw 0x0940, 0xc19c, 0x097f, 0xc19c, 0x21, 0 + .dw 0x09c0, 0xc19c, 0x09ff, 0xc19c, 0x21, 0 + .dw 0x0a40, 0xc19c, 0x0a7f, 0xc19c, 0x21, 0 + .dw 0x0ac0, 0xc19c, 0x0aff, 0xc19c, 0x21, 0 + .dw 0x0b40, 0xc19c, 0x0b7f, 0xc19c, 0x21, 0 + .dw 0x0bc0, 0xc19c, 0x0bff, 0xc19c, 0x21, 0 + .dw 0x0c40, 0xc19c, 0x0c7f, 0xc19c, 0x21, 0 + .dw 0x0cc0, 0xc19c, 0x0cff, 0xc19c, 0x21, 0 + .dw 0x0d40, 0xc19c, 0x0d7f, 0xc19c, 0x21, 0 + .dw 0x0dc0, 0xc19c, 0x0dff, 0xc19c, 0x21, 0 + .dw 0x0e40, 0xc19c, 0x0e7f, 0xc19c, 0x21, 0 + .dw 0x0ec0, 0xc19c, 0x0eff, 0xc19c, 0x21, 0 + .dw 0x0f40, 0xc19c, 0x0f7f, 0xc19c, 0x21, 0 + .dw 0x0fc0, 0xc19c, 0x0fff, 0xc19c, 0x21, 0 + .dw 0x1040, 0xc19c, 0x107f, 0xc19c, 0x21, 0 + .dw 0x10c0, 0xc19c, 0x10ff, 0xc19c, 0x21, 0 + .dw 0x1140, 0xc19c, 0x117f, 0xc19c, 0x21, 0 + .dw 0x11c0, 0xc19c, 0x11ff, 0xc19c, 0x21, 0 + .dw 0x1240, 0xc19c, 0x127f, 0xc19c, 0x21, 0 + .dw 0x12c0, 0xc19c, 0x12ff, 0xc19c, 0x21, 0 + .dw 0x1340, 0xc19c, 0x137f, 0xc19c, 0x21, 0 + .dw 0x13c0, 0xc19c, 0x13ff, 0xc19c, 0x21, 0 + .dw 0x1440, 0xc19c, 0x147f, 0xc19c, 0x21, 0 + .dw 0x14c0, 0xc19c, 0x14ff, 0xc19c, 0x21, 0 + .dw 0x1540, 0xc19c, 0x157f, 0xc19c, 0x21, 0 + .dw 0x15c0, 0xc19c, 0x15ff, 0xc19c, 0x21, 0 + .dw 0x1640, 0xc19c, 0x167f, 0xc19c, 0x21, 0 + .dw 0x16c0, 0xc19c, 0x16ff, 0xc19c, 0x21, 0 + .dw 0x1740, 0xc19c, 0x177f, 0xc19c, 0x21, 0 + .dw 0x17c0, 0xc19c, 0x17ff, 0xc19c, 0x21, 0 + .dw 0x1840, 0xc19c, 0x187f, 0xc19c, 0x21, 0 + .dw 0x18c0, 0xc19c, 0x18ff, 0xc19c, 0x21, 0 + .dw 0x1940, 0xc19c, 0x197f, 0xc19c, 0x21, 0 + .dw 0x19c0, 0xc19c, 0x1fff, 0xc19c, 0x21, 0 + .dw 0x2040, 0xc19c, 0x207f, 0xc19c, 0x21, 0 + .dw 0x20c0, 0xc19c, 0x20ff, 0xc19c, 0x21, 0 + .dw 0x2140, 0xc19c, 0x217f, 0xc19c, 0x21, 0 + .dw 0x21c0, 0xc19c, 0x21ff, 0xc19c, 0x21, 0 + .dw 0x2240, 0xc19c, 0x227f, 0xc19c, 0x21, 0 + .dw 0x22c0, 0xc19c, 0x22ff, 0xc19c, 0x21, 0 + .dw 0x2340, 0xc19c, 0x237f, 0xc19c, 0x21, 0 + .dw 0x23c0, 0xc19c, 0x23ff, 0xc19c, 0x21, 0 + .dw 0x2440, 0xc19c, 0x247f, 0xc19c, 0x21, 0 + .dw 0x24c0, 0xc19c, 0x24ff, 0xc19c, 0x21, 0 + .dw 0x2540, 0xc19c, 0x257f, 0xc19c, 0x21, 0 + .dw 0x25c0, 0xc19c, 0x25ff, 0xc19c, 0x21, 0 + .dw 0x2640, 0xc19c, 0x267f, 0xc19c, 0x21, 0 + .dw 0x26c0, 0xc19c, 0x26ff, 0xc19c, 0x21, 0 + .dw 0x2740, 0xc19c, 0x277f, 0xc19c, 0x21, 0 + .dw 0x27c0, 0xc19c, 0x27ff, 0xc19c, 0x21, 0 + .dw 0x2840, 0xc19c, 0x287f, 0xc19c, 0x21, 0 + .dw 0x28c0, 0xc19c, 0x28ff, 0xc19c, 0x21, 0 + .dw 0x2940, 0xc19c, 0x297f, 0xc19c, 0x21, 0 + .dw 0x29c0, 0xc19c, 0x29ff, 0xc19c, 0x21, 0 + .dw 0x2a40, 0xc19c, 0x2a7f, 0xc19c, 0x21, 0 + .dw 0x2ac0, 0xc19c, 0x2aff, 0xc19c, 0x21, 0 + .dw 0x2b40, 0xc19c, 0x2b7f, 0xc19c, 0x21, 0 + .dw 0x2bc0, 0xc19c, 0x2bff, 0xc19c, 0x21, 0 + .dw 0x2c40, 0xc19c, 0x2c7f, 0xc19c, 0x21, 0 + .dw 0x2cc0, 0xc19c, 0x2cff, 0xc19c, 0x21, 0 + .dw 0x2d40, 0xc19c, 0x2d7f, 0xc19c, 0x21, 0 + .dw 0x2dc0, 0xc19c, 0x2dff, 0xc19c, 0x21, 0 + .dw 0x2e40, 0xc19c, 0x2e7f, 0xc19c, 0x21, 0 + .dw 0x2ec0, 0xc19c, 0x2eff, 0xc19c, 0x21, 0 + .dw 0x2f40, 0xc19c, 0x2f7f, 0xc19c, 0x21, 0 + .dw 0x2fc0, 0xc19c, 0x2fff, 0xc19c, 0x21, 0 + .dw 0x3040, 0xc19c, 0x307f, 0xc19c, 0x21, 0 + .dw 0x30c0, 0xc19c, 0x30ff, 0xc19c, 0x21, 0 + .dw 0x3140, 0xc19c, 0x317f, 0xc19c, 0x21, 0 + .dw 0x31c0, 0xc19c, 0x31ff, 0xc19c, 0x21, 0 + .dw 0x3240, 0xc19c, 0x327f, 0xc19c, 0x21, 0 + .dw 0x32c0, 0xc19c, 0x32ff, 0xc19c, 0x21, 0 + .dw 0x3340, 0xc19c, 0x337f, 0xc19c, 0x21, 0 + .dw 0x33c0, 0xc19c, 0x33ff, 0xc19c, 0x21, 0 + .dw 0x3440, 0xc19c, 0x347f, 0xc19c, 0x21, 0 + .dw 0x34c0, 0xc19c, 0x34ff, 0xc19c, 0x21, 0 + .dw 0x3540, 0xc19c, 0x357f, 0xc19c, 0x21, 0 + .dw 0x35c0, 0xc19c, 0x35ff, 0xc19c, 0x21, 0 + .dw 0x3640, 0xc19c, 0x367f, 0xc19c, 0x21, 0 + .dw 0x36c0, 0xc19c, 0x36ff, 0xc19c, 0x21, 0 + .dw 0x3740, 0xc19c, 0x377f, 0xc19c, 0x21, 0 + .dw 0x37c0, 0xc19c, 0x37ff, 0xc19c, 0x21, 0 + .dw 0x3840, 0xc19c, 0x387f, 0xc19c, 0x21, 0 + .dw 0x38c0, 0xc19c, 0x38ff, 0xc19c, 0x21, 0 + .dw 0x3940, 0xc19c, 0x397f, 0xc19c, 0x21, 0 + .dw 0x39c0, 0xc19c, 0x3fff, 0xc19c, 0x21, 0 + .dw 0x4040, 0xc19c, 0x407f, 0xc19c, 0x21, 0 + .dw 0x40c0, 0xc19c, 0x40ff, 0xc19c, 0x21, 0 + .dw 0x4140, 0xc19c, 0x417f, 0xc19c, 0x21, 0 + .dw 0x41c0, 0xc19c, 0x41ff, 0xc19c, 0x21, 0 + .dw 0x4240, 0xc19c, 0x427f, 0xc19c, 0x21, 0 + .dw 0x42c0, 0xc19c, 0x42ff, 0xc19c, 0x21, 0 + .dw 0x4340, 0xc19c, 0x437f, 0xc19c, 0x21, 0 + .dw 0x43c0, 0xc19c, 0x43ff, 0xc19c, 0x21, 0 + .dw 0x4440, 0xc19c, 0x447f, 0xc19c, 0x21, 0 + .dw 0x44c0, 0xc19c, 0x44ff, 0xc19c, 0x21, 0 + .dw 0x4540, 0xc19c, 0x457f, 0xc19c, 0x21, 0 + .dw 0x45c0, 0xc19c, 0x45ff, 0xc19c, 0x21, 0 + .dw 0x4640, 0xc19c, 0x467f, 0xc19c, 0x21, 0 + .dw 0x46c0, 0xc19c, 0x46ff, 0xc19c, 0x21, 0 + .dw 0x4740, 0xc19c, 0x477f, 0xc19c, 0x21, 0 + .dw 0x47c0, 0xc19c, 0x47ff, 0xc19c, 0x21, 0 + .dw 0x4840, 0xc19c, 0x487f, 0xc19c, 0x21, 0 + .dw 0x48c0, 0xc19c, 0x48ff, 0xc19c, 0x21, 0 + .dw 0x4940, 0xc19c, 0x497f, 0xc19c, 0x21, 0 + .dw 0x49c0, 0xc19c, 0x49ff, 0xc19c, 0x21, 0 + .dw 0x4a40, 0xc19c, 0x4a7f, 0xc19c, 0x21, 0 + .dw 0x4ac0, 0xc19c, 0x4aff, 0xc19c, 0x21, 0 + .dw 0x4b40, 0xc19c, 0x4b7f, 0xc19c, 0x21, 0 + .dw 0x4bc0, 0xc19c, 0x4bff, 0xc19c, 0x21, 0 + .dw 0x4c40, 0xc19c, 0x4c7f, 0xc19c, 0x21, 0 + .dw 0x4cc0, 0xc19c, 0x4cff, 0xc19c, 0x21, 0 + .dw 0x4d40, 0xc19c, 0x4d7f, 0xc19c, 0x21, 0 + .dw 0x4dc0, 0xc19c, 0x4dff, 0xc19c, 0x21, 0 + .dw 0x4e40, 0xc19c, 0x4e7f, 0xc19c, 0x21, 0 + .dw 0x4ec0, 0xc19c, 0x4eff, 0xc19c, 0x21, 0 + .dw 0x4f40, 0xc19c, 0x4f7f, 0xc19c, 0x21, 0 + .dw 0x4fc0, 0xc19c, 0x4fff, 0xc19c, 0x21, 0 + .dw 0x5040, 0xc19c, 0x507f, 0xc19c, 0x21, 0 + .dw 0x50c0, 0xc19c, 0x50ff, 0xc19c, 0x21, 0 + .dw 0x5140, 0xc19c, 0x517f, 0xc19c, 0x21, 0 + .dw 0x51c0, 0xc19c, 0x51ff, 0xc19c, 0x21, 0 + .dw 0x5240, 0xc19c, 0x527f, 0xc19c, 0x21, 0 + .dw 0x52c0, 0xc19c, 0x52ff, 0xc19c, 0x21, 0 + .dw 0x5340, 0xc19c, 0x537f, 0xc19c, 0x21, 0 + .dw 0x53c0, 0xc19c, 0x53ff, 0xc19c, 0x21, 0 + .dw 0x5440, 0xc19c, 0x547f, 0xc19c, 0x21, 0 + .dw 0x54c0, 0xc19c, 0x54ff, 0xc19c, 0x21, 0 + .dw 0x5540, 0xc19c, 0x557f, 0xc19c, 0x21, 0 + .dw 0x55c0, 0xc19c, 0x55ff, 0xc19c, 0x21, 0 + .dw 0x5640, 0xc19c, 0x567f, 0xc19c, 0x21, 0 + .dw 0x56c0, 0xc19c, 0x56ff, 0xc19c, 0x21, 0 + .dw 0x5740, 0xc19c, 0x577f, 0xc19c, 0x21, 0 + .dw 0x57c0, 0xc19c, 0x57ff, 0xc19c, 0x21, 0 + .dw 0x5840, 0xc19c, 0x587f, 0xc19c, 0x21, 0 + .dw 0x58c0, 0xc19c, 0x58ff, 0xc19c, 0x21, 0 + .dw 0x5940, 0xc19c, 0x597f, 0xc19c, 0x21, 0 + .dw 0x59c0, 0xc19c, 0x5fff, 0xc19c, 0x21, 0 + .dw 0x6040, 0xc19c, 0x607f, 0xc19c, 0x21, 0 + .dw 0x60c0, 0xc19c, 0x60ff, 0xc19c, 0x21, 0 + .dw 0x6140, 0xc19c, 0x617f, 0xc19c, 0x21, 0 + .dw 0x61c0, 0xc19c, 0x61ff, 0xc19c, 0x21, 0 + .dw 0x6240, 0xc19c, 0x627f, 0xc19c, 0x21, 0 + .dw 0x62c0, 0xc19c, 0x62ff, 0xc19c, 0x21, 0 + .dw 0x6340, 0xc19c, 0x637f, 0xc19c, 0x21, 0 + .dw 0x63c0, 0xc19c, 0x63ff, 0xc19c, 0x21, 0 + .dw 0x6440, 0xc19c, 0x647f, 0xc19c, 0x21, 0 + .dw 0x64c0, 0xc19c, 0x64ff, 0xc19c, 0x21, 0 + .dw 0x6540, 0xc19c, 0x657f, 0xc19c, 0x21, 0 + .dw 0x65c0, 0xc19c, 0x65ff, 0xc19c, 0x21, 0 + .dw 0x6640, 0xc19c, 0x667f, 0xc19c, 0x21, 0 + .dw 0x66c0, 0xc19c, 0x66ff, 0xc19c, 0x21, 0 + .dw 0x6740, 0xc19c, 0x677f, 0xc19c, 0x21, 0 + .dw 0x67c0, 0xc19c, 0x67ff, 0xc19c, 0x21, 0 + .dw 0x6840, 0xc19c, 0x687f, 0xc19c, 0x21, 0 + .dw 0x68c0, 0xc19c, 0x68ff, 0xc19c, 0x21, 0 + .dw 0x6940, 0xc19c, 0x697f, 0xc19c, 0x21, 0 + .dw 0x69c0, 0xc19c, 0x69ff, 0xc19c, 0x21, 0 + .dw 0x6a40, 0xc19c, 0x6a7f, 0xc19c, 0x21, 0 + .dw 0x6ac0, 0xc19c, 0x6aff, 0xc19c, 0x21, 0 + .dw 0x6b40, 0xc19c, 0x6b7f, 0xc19c, 0x21, 0 + .dw 0x6bc0, 0xc19c, 0x6bff, 0xc19c, 0x21, 0 + .dw 0x6c40, 0xc19c, 0x6c7f, 0xc19c, 0x21, 0 + .dw 0x6cc0, 0xc19c, 0x6cff, 0xc19c, 0x21, 0 + .dw 0x6d40, 0xc19c, 0x6d7f, 0xc19c, 0x21, 0 + .dw 0x6dc0, 0xc19c, 0x6dff, 0xc19c, 0x21, 0 + .dw 0x6e40, 0xc19c, 0x6e7f, 0xc19c, 0x21, 0 + .dw 0x6ec0, 0xc19c, 0x6eff, 0xc19c, 0x21, 0 + .dw 0x6f40, 0xc19c, 0x6f7f, 0xc19c, 0x21, 0 + .dw 0x6fc0, 0xc19c, 0x6fff, 0xc19c, 0x21, 0 + .dw 0x7040, 0xc19c, 0x707f, 0xc19c, 0x21, 0 + .dw 0x70c0, 0xc19c, 0x70ff, 0xc19c, 0x21, 0 + .dw 0x7140, 0xc19c, 0x717f, 0xc19c, 0x21, 0 + .dw 0x71c0, 0xc19c, 0x71ff, 0xc19c, 0x21, 0 + .dw 0x7240, 0xc19c, 0x727f, 0xc19c, 0x21, 0 + .dw 0x72c0, 0xc19c, 0x72ff, 0xc19c, 0x21, 0 + .dw 0x7340, 0xc19c, 0x737f, 0xc19c, 0x21, 0 + .dw 0x73c0, 0xc19c, 0x73ff, 0xc19c, 0x21, 0 + .dw 0x7440, 0xc19c, 0x747f, 0xc19c, 0x21, 0 + .dw 0x74c0, 0xc19c, 0x74ff, 0xc19c, 0x21, 0 + .dw 0x7540, 0xc19c, 0x757f, 0xc19c, 0x21, 0 + .dw 0x75c0, 0xc19c, 0x75ff, 0xc19c, 0x21, 0 + .dw 0x7640, 0xc19c, 0x767f, 0xc19c, 0x21, 0 + .dw 0x76c0, 0xc19c, 0x76ff, 0xc19c, 0x21, 0 + .dw 0x7740, 0xc19c, 0x777f, 0xc19c, 0x21, 0 + .dw 0x77c0, 0xc19c, 0x77ff, 0xc19c, 0x21, 0 + .dw 0x7840, 0xc19c, 0x787f, 0xc19c, 0x21, 0 + .dw 0x78c0, 0xc19c, 0x78ff, 0xc19c, 0x21, 0 + .dw 0x7940, 0xc19c, 0x797f, 0xc19c, 0x21, 0 + .dw 0x79c0, 0xc19c, 0x7fff, 0xc19c, 0x21, 0 + .dw 0x8040, 0xc19c, 0x807f, 0xc19c, 0x21, 0 + .dw 0x80c0, 0xc19c, 0x80ff, 0xc19c, 0x21, 0 + .dw 0x8140, 0xc19c, 0x817f, 0xc19c, 0x21, 0 + .dw 0x81c0, 0xc19c, 0x81ff, 0xc19c, 0x21, 0 + .dw 0x8240, 0xc19c, 0x827f, 0xc19c, 0x21, 0 + .dw 0x82c0, 0xc19c, 0x82ff, 0xc19c, 0x21, 0 + .dw 0x8340, 0xc19c, 0x837f, 0xc19c, 0x21, 0 + .dw 0x83c0, 0xc19c, 0x83ff, 0xc19c, 0x21, 0 + .dw 0x8440, 0xc19c, 0x847f, 0xc19c, 0x21, 0 + .dw 0x84c0, 0xc19c, 0x84ff, 0xc19c, 0x21, 0 + .dw 0x8540, 0xc19c, 0x857f, 0xc19c, 0x21, 0 + .dw 0x85c0, 0xc19c, 0x85ff, 0xc19c, 0x21, 0 + .dw 0x8640, 0xc19c, 0x867f, 0xc19c, 0x21, 0 + .dw 0x86c0, 0xc19c, 0x86ff, 0xc19c, 0x21, 0 + .dw 0x8740, 0xc19c, 0x877f, 0xc19c, 0x21, 0 + .dw 0x87c0, 0xc19c, 0x87ff, 0xc19c, 0x21, 0 + .dw 0x8840, 0xc19c, 0x887f, 0xc19c, 0x21, 0 + .dw 0x88c0, 0xc19c, 0x88ff, 0xc19c, 0x21, 0 + .dw 0x8940, 0xc19c, 0x897f, 0xc19c, 0x21, 0 + .dw 0x89c0, 0xc19c, 0x89ff, 0xc19c, 0x21, 0 + .dw 0x8a40, 0xc19c, 0x8a7f, 0xc19c, 0x21, 0 + .dw 0x8ac0, 0xc19c, 0x8aff, 0xc19c, 0x21, 0 + .dw 0x8b40, 0xc19c, 0x8b7f, 0xc19c, 0x21, 0 + .dw 0x8bc0, 0xc19c, 0x8bff, 0xc19c, 0x21, 0 + .dw 0x8c40, 0xc19c, 0x8c7f, 0xc19c, 0x21, 0 + .dw 0x8cc0, 0xc19c, 0x8cff, 0xc19c, 0x21, 0 + .dw 0x8d40, 0xc19c, 0x8d7f, 0xc19c, 0x21, 0 + .dw 0x8dc0, 0xc19c, 0x8dff, 0xc19c, 0x21, 0 + .dw 0x8e40, 0xc19c, 0x8e7f, 0xc19c, 0x21, 0 + .dw 0x8ec0, 0xc19c, 0x8eff, 0xc19c, 0x21, 0 + .dw 0x8f40, 0xc19c, 0x8f7f, 0xc19c, 0x21, 0 + .dw 0x8fc0, 0xc19c, 0x8fff, 0xc19c, 0x21, 0 + .dw 0x9040, 0xc19c, 0x907f, 0xc19c, 0x21, 0 + .dw 0x90c0, 0xc19c, 0x90ff, 0xc19c, 0x21, 0 + .dw 0x9140, 0xc19c, 0x917f, 0xc19c, 0x21, 0 + .dw 0x91c0, 0xc19c, 0x91ff, 0xc19c, 0x21, 0 + .dw 0x9240, 0xc19c, 0x927f, 0xc19c, 0x21, 0 + .dw 0x92c0, 0xc19c, 0x92ff, 0xc19c, 0x21, 0 + .dw 0x9340, 0xc19c, 0x937f, 0xc19c, 0x21, 0 + .dw 0x93c0, 0xc19c, 0x93ff, 0xc19c, 0x21, 0 + .dw 0x9440, 0xc19c, 0x947f, 0xc19c, 0x21, 0 + .dw 0x94c0, 0xc19c, 0x94ff, 0xc19c, 0x21, 0 + .dw 0x9540, 0xc19c, 0x957f, 0xc19c, 0x21, 0 + .dw 0x95c0, 0xc19c, 0x95ff, 0xc19c, 0x21, 0 + .dw 0x9640, 0xc19c, 0x967f, 0xc19c, 0x21, 0 + .dw 0x96c0, 0xc19c, 0x96ff, 0xc19c, 0x21, 0 + .dw 0x9740, 0xc19c, 0x977f, 0xc19c, 0x21, 0 + .dw 0x97c0, 0xc19c, 0x97ff, 0xc19c, 0x21, 0 + .dw 0x9840, 0xc19c, 0x987f, 0xc19c, 0x21, 0 + .dw 0x98c0, 0xc19c, 0x98ff, 0xc19c, 0x21, 0 + .dw 0x9940, 0xc19c, 0x997f, 0xc19c, 0x21, 0 + .dw 0x99c0, 0xc19c, 0x9fff, 0xc19c, 0x21, 0 + .dw 0xa040, 0xc19c, 0xa07f, 0xc19c, 0x21, 0 + .dw 0xa0c0, 0xc19c, 0xa0ff, 0xc19c, 0x21, 0 + .dw 0xa140, 0xc19c, 0xa17f, 0xc19c, 0x21, 0 + .dw 0xa1c0, 0xc19c, 0xa1ff, 0xc19c, 0x21, 0 + .dw 0xa240, 0xc19c, 0xa27f, 0xc19c, 0x21, 0 + .dw 0xa2c0, 0xc19c, 0xa2ff, 0xc19c, 0x21, 0 + .dw 0xa340, 0xc19c, 0xa37f, 0xc19c, 0x21, 0 + .dw 0xa3c0, 0xc19c, 0xa3ff, 0xc19c, 0x21, 0 + .dw 0xa440, 0xc19c, 0xa47f, 0xc19c, 0x21, 0 + .dw 0xa4c0, 0xc19c, 0xa4ff, 0xc19c, 0x21, 0 + .dw 0xa540, 0xc19c, 0xa57f, 0xc19c, 0x21, 0 + .dw 0xa5c0, 0xc19c, 0xa5ff, 0xc19c, 0x21, 0 + .dw 0xa640, 0xc19c, 0xa67f, 0xc19c, 0x21, 0 + .dw 0xa6c0, 0xc19c, 0xa6ff, 0xc19c, 0x21, 0 + .dw 0xa740, 0xc19c, 0xa77f, 0xc19c, 0x21, 0 + .dw 0xa7c0, 0xc19c, 0xa7ff, 0xc19c, 0x21, 0 + .dw 0xa840, 0xc19c, 0xa87f, 0xc19c, 0x21, 0 + .dw 0xa8c0, 0xc19c, 0xa8ff, 0xc19c, 0x21, 0 + .dw 0xa940, 0xc19c, 0xa97f, 0xc19c, 0x21, 0 + .dw 0xa9c0, 0xc19c, 0xa9ff, 0xc19c, 0x21, 0 + .dw 0xaa40, 0xc19c, 0xaa7f, 0xc19c, 0x21, 0 + .dw 0xaac0, 0xc19c, 0xaaff, 0xc19c, 0x21, 0 + .dw 0xab40, 0xc19c, 0xab7f, 0xc19c, 0x21, 0 + .dw 0xabc0, 0xc19c, 0xabff, 0xc19c, 0x21, 0 + .dw 0xac40, 0xc19c, 0xac7f, 0xc19c, 0x21, 0 + .dw 0xacc0, 0xc19c, 0xacff, 0xc19c, 0x21, 0 + .dw 0xad40, 0xc19c, 0xad7f, 0xc19c, 0x21, 0 + .dw 0xadc0, 0xc19c, 0xadff, 0xc19c, 0x21, 0 + .dw 0xae40, 0xc19c, 0xae7f, 0xc19c, 0x21, 0 + .dw 0xaec0, 0xc19c, 0xaeff, 0xc19c, 0x21, 0 + .dw 0xaf40, 0xc19c, 0xaf7f, 0xc19c, 0x21, 0 + .dw 0xafc0, 0xc19c, 0xafff, 0xc19c, 0x21, 0 + .dw 0xb040, 0xc19c, 0xb07f, 0xc19c, 0x21, 0 + .dw 0xb0c0, 0xc19c, 0xb0ff, 0xc19c, 0x21, 0 + .dw 0xb140, 0xc19c, 0xb17f, 0xc19c, 0x21, 0 + .dw 0xb1c0, 0xc19c, 0xb1ff, 0xc19c, 0x21, 0 + .dw 0xb240, 0xc19c, 0xb27f, 0xc19c, 0x21, 0 + .dw 0xb2c0, 0xc19c, 0xb2ff, 0xc19c, 0x21, 0 + .dw 0xb340, 0xc19c, 0xb37f, 0xc19c, 0x21, 0 + .dw 0xb3c0, 0xc19c, 0xb3ff, 0xc19c, 0x21, 0 + .dw 0xb440, 0xc19c, 0xb47f, 0xc19c, 0x21, 0 + .dw 0xb4c0, 0xc19c, 0xb4ff, 0xc19c, 0x21, 0 + .dw 0xb540, 0xc19c, 0xb57f, 0xc19c, 0x21, 0 + .dw 0xb5c0, 0xc19c, 0xb5ff, 0xc19c, 0x21, 0 + .dw 0xb640, 0xc19c, 0xb67f, 0xc19c, 0x21, 0 + .dw 0xb6c0, 0xc19c, 0xb6ff, 0xc19c, 0x21, 0 + .dw 0xb740, 0xc19c, 0xb77f, 0xc19c, 0x21, 0 + .dw 0xb7c0, 0xc19c, 0xb7ff, 0xc19c, 0x21, 0 + .dw 0xb840, 0xc19c, 0xb87f, 0xc19c, 0x21, 0 + .dw 0xb8c0, 0xc19c, 0xb8ff, 0xc19c, 0x21, 0 + .dw 0xb940, 0xc19c, 0xb97f, 0xc19c, 0x21, 0 + .dw 0xb9c0, 0xc19c, 0xbfff, 0xc19c, 0x21, 0 + .dw 0xc040, 0xc19c, 0xc07f, 0xc19c, 0x21, 0 + .dw 0xc0c0, 0xc19c, 0xc0ff, 0xc19c, 0x21, 0 + .dw 0xc140, 0xc19c, 0xc17f, 0xc19c, 0x21, 0 + .dw 0xc1c0, 0xc19c, 0xc1ff, 0xc19c, 0x21, 0 + .dw 0xc240, 0xc19c, 0xc27f, 0xc19c, 0x21, 0 + .dw 0xc2c0, 0xc19c, 0xc2ff, 0xc19c, 0x21, 0 + .dw 0xc340, 0xc19c, 0xc37f, 0xc19c, 0x21, 0 + .dw 0xc3c0, 0xc19c, 0xc3ff, 0xc19c, 0x21, 0 + .dw 0xc440, 0xc19c, 0xc47f, 0xc19c, 0x21, 0 + .dw 0xc4c0, 0xc19c, 0xc4ff, 0xc19c, 0x21, 0 + .dw 0xc540, 0xc19c, 0xc57f, 0xc19c, 0x21, 0 + .dw 0xc5c0, 0xc19c, 0xc5ff, 0xc19c, 0x21, 0 + .dw 0xc640, 0xc19c, 0xc67f, 0xc19c, 0x21, 0 + .dw 0xc6c0, 0xc19c, 0xc6ff, 0xc19c, 0x21, 0 + .dw 0xc740, 0xc19c, 0xc77f, 0xc19c, 0x21, 0 + .dw 0xc7c0, 0xc19c, 0xc7ff, 0xc19c, 0x21, 0 + .dw 0xc840, 0xc19c, 0xc87f, 0xc19c, 0x21, 0 + .dw 0xc8c0, 0xc19c, 0xc8ff, 0xc19c, 0x21, 0 + .dw 0xc940, 0xc19c, 0xc97f, 0xc19c, 0x21, 0 + .dw 0xc9c0, 0xc19c, 0xc9ff, 0xc19c, 0x21, 0 + .dw 0xca40, 0xc19c, 0xca7f, 0xc19c, 0x21, 0 + .dw 0xcac0, 0xc19c, 0xcaff, 0xc19c, 0x21, 0 + .dw 0xcb40, 0xc19c, 0xcb7f, 0xc19c, 0x21, 0 + .dw 0xcbc0, 0xc19c, 0xcbff, 0xc19c, 0x21, 0 + .dw 0xcc40, 0xc19c, 0xcc7f, 0xc19c, 0x21, 0 + .dw 0xccc0, 0xc19c, 0xccff, 0xc19c, 0x21, 0 + .dw 0xcd40, 0xc19c, 0xcd7f, 0xc19c, 0x21, 0 + .dw 0xcdc0, 0xc19c, 0xcdff, 0xc19c, 0x21, 0 + .dw 0xce40, 0xc19c, 0xce7f, 0xc19c, 0x21, 0 + .dw 0xcec0, 0xc19c, 0xceff, 0xc19c, 0x21, 0 + .dw 0xcf40, 0xc19c, 0xcf7f, 0xc19c, 0x21, 0 + .dw 0xcfc0, 0xc19c, 0xcfff, 0xc19c, 0x21, 0 + .dw 0xd040, 0xc19c, 0xd07f, 0xc19c, 0x21, 0 + .dw 0xd0c0, 0xc19c, 0xd0ff, 0xc19c, 0x21, 0 + .dw 0xd140, 0xc19c, 0xd17f, 0xc19c, 0x21, 0 + .dw 0xd1c0, 0xc19c, 0xd1ff, 0xc19c, 0x21, 0 + .dw 0xd240, 0xc19c, 0xd27f, 0xc19c, 0x21, 0 + .dw 0xd2c0, 0xc19c, 0xd2ff, 0xc19c, 0x21, 0 + .dw 0xd340, 0xc19c, 0xd37f, 0xc19c, 0x21, 0 + .dw 0xd3c0, 0xc19c, 0xd3ff, 0xc19c, 0x21, 0 + .dw 0xd440, 0xc19c, 0xd47f, 0xc19c, 0x21, 0 + .dw 0xd4c0, 0xc19c, 0xd4ff, 0xc19c, 0x21, 0 + .dw 0xd540, 0xc19c, 0xd57f, 0xc19c, 0x21, 0 + .dw 0xd5c0, 0xc19c, 0xd5ff, 0xc19c, 0x21, 0 + .dw 0xd640, 0xc19c, 0xd67f, 0xc19c, 0x21, 0 + .dw 0xd6c0, 0xc19c, 0xd6ff, 0xc19c, 0x21, 0 + .dw 0xd740, 0xc19c, 0xd77f, 0xc19c, 0x21, 0 + .dw 0xd7c0, 0xc19c, 0xd7ff, 0xc19c, 0x21, 0 + .dw 0xd840, 0xc19c, 0xd87f, 0xc19c, 0x21, 0 + .dw 0xd8c0, 0xc19c, 0xd8ff, 0xc19c, 0x21, 0 + .dw 0xd940, 0xc19c, 0xd97f, 0xc19c, 0x21, 0 + .dw 0xd9c0, 0xc19c, 0xdfff, 0xc19c, 0x21, 0 + .dw 0xe040, 0xc19c, 0xe07f, 0xc19c, 0x21, 0 + .dw 0xe0c0, 0xc19c, 0xe0ff, 0xc19c, 0x21, 0 + .dw 0xe140, 0xc19c, 0xe17f, 0xc19c, 0x21, 0 + .dw 0xe1c0, 0xc19c, 0xe1ff, 0xc19c, 0x21, 0 + .dw 0xe240, 0xc19c, 0xe27f, 0xc19c, 0x21, 0 + .dw 0xe2c0, 0xc19c, 0xe2ff, 0xc19c, 0x21, 0 + .dw 0xe340, 0xc19c, 0xe37f, 0xc19c, 0x21, 0 + .dw 0xe3c0, 0xc19c, 0xe3ff, 0xc19c, 0x21, 0 + .dw 0xe440, 0xc19c, 0xe47f, 0xc19c, 0x21, 0 + .dw 0xe4c0, 0xc19c, 0xe4ff, 0xc19c, 0x21, 0 + .dw 0xe540, 0xc19c, 0xe57f, 0xc19c, 0x21, 0 + .dw 0xe5c0, 0xc19c, 0xe5ff, 0xc19c, 0x21, 0 + .dw 0xe640, 0xc19c, 0xe67f, 0xc19c, 0x21, 0 + .dw 0xe6c0, 0xc19c, 0xe6ff, 0xc19c, 0x21, 0 + .dw 0xe740, 0xc19c, 0xe77f, 0xc19c, 0x21, 0 + .dw 0xe7c0, 0xc19c, 0xe7ff, 0xc19c, 0x21, 0 + .dw 0xe840, 0xc19c, 0xe87f, 0xc19c, 0x21, 0 + .dw 0xe8c0, 0xc19c, 0xe8ff, 0xc19c, 0x21, 0 + .dw 0xe940, 0xc19c, 0xe97f, 0xc19c, 0x21, 0 + .dw 0xe9c0, 0xc19c, 0xe9ff, 0xc19c, 0x21, 0 + .dw 0xea40, 0xc19c, 0xea7f, 0xc19c, 0x21, 0 + .dw 0xeac0, 0xc19c, 0xeaff, 0xc19c, 0x21, 0 + .dw 0xeb40, 0xc19c, 0xeb7f, 0xc19c, 0x21, 0 + .dw 0xebc0, 0xc19c, 0xebff, 0xc19c, 0x21, 0 + .dw 0xec40, 0xc19c, 0xec7f, 0xc19c, 0x21, 0 + .dw 0xecc0, 0xc19c, 0xecff, 0xc19c, 0x21, 0 + .dw 0xed40, 0xc19c, 0xed7f, 0xc19c, 0x21, 0 + .dw 0xedc0, 0xc19c, 0xedff, 0xc19c, 0x21, 0 + .dw 0xee40, 0xc19c, 0xee7f, 0xc19c, 0x21, 0 + .dw 0xeec0, 0xc19c, 0xeeff, 0xc19c, 0x21, 0 + .dw 0xef40, 0xc19c, 0xef7f, 0xc19c, 0x21, 0 + .dw 0xefc0, 0xc19c, 0xefff, 0xc19c, 0x21, 0 + .dw 0xf040, 0xc19c, 0xf07f, 0xc19c, 0x21, 0 + .dw 0xf0c0, 0xc19c, 0xf0ff, 0xc19c, 0x21, 0 + .dw 0xf140, 0xc19c, 0xf17f, 0xc19c, 0x21, 0 + .dw 0xf1c0, 0xc19c, 0xf1ff, 0xc19c, 0x21, 0 + .dw 0xf240, 0xc19c, 0xf27f, 0xc19c, 0x21, 0 + .dw 0xf2c0, 0xc19c, 0xf2ff, 0xc19c, 0x21, 0 + .dw 0xf340, 0xc19c, 0xf37f, 0xc19c, 0x21, 0 + .dw 0xf3c0, 0xc19c, 0xf3ff, 0xc19c, 0x21, 0 + .dw 0xf440, 0xc19c, 0xf47f, 0xc19c, 0x21, 0 + .dw 0xf4c0, 0xc19c, 0xf4ff, 0xc19c, 0x21, 0 + .dw 0xf540, 0xc19c, 0xf57f, 0xc19c, 0x21, 0 + .dw 0xf5c0, 0xc19c, 0xf5ff, 0xc19c, 0x21, 0 + .dw 0xf640, 0xc19c, 0xf67f, 0xc19c, 0x21, 0 + .dw 0xf6c0, 0xc19c, 0xf6ff, 0xc19c, 0x21, 0 + .dw 0xf740, 0xc19c, 0xf77f, 0xc19c, 0x21, 0 + .dw 0xf7c0, 0xc19c, 0xf7ff, 0xc19c, 0x21, 0 + .dw 0xf840, 0xc19c, 0xf87f, 0xc19c, 0x21, 0 + .dw 0xf8c0, 0xc19c, 0xf8ff, 0xc19c, 0x21, 0 + .dw 0xf940, 0xc19c, 0xf97f, 0xc19c, 0x21, 0 + .dw 0xf9c0, 0xc19c, 0xffff, 0xc19c, 0x21, 0 + .dw 0x0040, 0xc19d, 0x007f, 0xc19d, 0x21, 0 + .dw 0x00c0, 0xc19d, 0x00ff, 0xc19d, 0x21, 0 + .dw 0x0140, 0xc19d, 0x017f, 0xc19d, 0x21, 0 + .dw 0x01c0, 0xc19d, 0x01ff, 0xc19d, 0x21, 0 + .dw 0x0240, 0xc19d, 0x027f, 0xc19d, 0x21, 0 + .dw 0x02c0, 0xc19d, 0x02ff, 0xc19d, 0x21, 0 + .dw 0x0340, 0xc19d, 0x037f, 0xc19d, 0x21, 0 + .dw 0x03c0, 0xc19d, 0x03ff, 0xc19d, 0x21, 0 + .dw 0x0440, 0xc19d, 0x047f, 0xc19d, 0x21, 0 + .dw 0x04c0, 0xc19d, 0x04ff, 0xc19d, 0x21, 0 + .dw 0x0540, 0xc19d, 0x057f, 0xc19d, 0x21, 0 + .dw 0x05c0, 0xc19d, 0x05ff, 0xc19d, 0x21, 0 + .dw 0x0640, 0xc19d, 0x067f, 0xc19d, 0x21, 0 + .dw 0x06c0, 0xc19d, 0x06ff, 0xc19d, 0x21, 0 + .dw 0x0740, 0xc19d, 0x077f, 0xc19d, 0x21, 0 + .dw 0x07c0, 0xc19d, 0x07ff, 0xc19d, 0x21, 0 + .dw 0x0840, 0xc19d, 0x087f, 0xc19d, 0x21, 0 + .dw 0x08c0, 0xc19d, 0x08ff, 0xc19d, 0x21, 0 + .dw 0x0940, 0xc19d, 0x097f, 0xc19d, 0x21, 0 + .dw 0x09c0, 0xc19d, 0x09ff, 0xc19d, 0x21, 0 + .dw 0x0a40, 0xc19d, 0x0a7f, 0xc19d, 0x21, 0 + .dw 0x0ac0, 0xc19d, 0x0aff, 0xc19d, 0x21, 0 + .dw 0x0b40, 0xc19d, 0x0b7f, 0xc19d, 0x21, 0 + .dw 0x0bc0, 0xc19d, 0x0bff, 0xc19d, 0x21, 0 + .dw 0x0c40, 0xc19d, 0x0c7f, 0xc19d, 0x21, 0 + .dw 0x0cc0, 0xc19d, 0x0cff, 0xc19d, 0x21, 0 + .dw 0x0d40, 0xc19d, 0x0d7f, 0xc19d, 0x21, 0 + .dw 0x0dc0, 0xc19d, 0x0dff, 0xc19d, 0x21, 0 + .dw 0x0e40, 0xc19d, 0x0e7f, 0xc19d, 0x21, 0 + .dw 0x0ec0, 0xc19d, 0x0eff, 0xc19d, 0x21, 0 + .dw 0x0f40, 0xc19d, 0x0f7f, 0xc19d, 0x21, 0 + .dw 0x0fc0, 0xc19d, 0x0fff, 0xc19d, 0x21, 0 + .dw 0x1040, 0xc19d, 0x107f, 0xc19d, 0x21, 0 + .dw 0x10c0, 0xc19d, 0x10ff, 0xc19d, 0x21, 0 + .dw 0x1140, 0xc19d, 0x117f, 0xc19d, 0x21, 0 + .dw 0x11c0, 0xc19d, 0x11ff, 0xc19d, 0x21, 0 + .dw 0x1240, 0xc19d, 0x127f, 0xc19d, 0x21, 0 + .dw 0x12c0, 0xc19d, 0x12ff, 0xc19d, 0x21, 0 + .dw 0x1340, 0xc19d, 0x137f, 0xc19d, 0x21, 0 + .dw 0x13c0, 0xc19d, 0x13ff, 0xc19d, 0x21, 0 + .dw 0x1440, 0xc19d, 0x147f, 0xc19d, 0x21, 0 + .dw 0x14c0, 0xc19d, 0x14ff, 0xc19d, 0x21, 0 + .dw 0x1540, 0xc19d, 0x157f, 0xc19d, 0x21, 0 + .dw 0x15c0, 0xc19d, 0x15ff, 0xc19d, 0x21, 0 + .dw 0x1640, 0xc19d, 0x167f, 0xc19d, 0x21, 0 + .dw 0x16c0, 0xc19d, 0x16ff, 0xc19d, 0x21, 0 + .dw 0x1740, 0xc19d, 0x177f, 0xc19d, 0x21, 0 + .dw 0x17c0, 0xc19d, 0x17ff, 0xc19d, 0x21, 0 + .dw 0x1840, 0xc19d, 0x187f, 0xc19d, 0x21, 0 + .dw 0x18c0, 0xc19d, 0x18ff, 0xc19d, 0x21, 0 + .dw 0x1940, 0xc19d, 0x197f, 0xc19d, 0x21, 0 + .dw 0x19c0, 0xc19d, 0x1fff, 0xc19d, 0x21, 0 + .dw 0x2040, 0xc19d, 0x207f, 0xc19d, 0x21, 0 + .dw 0x20c0, 0xc19d, 0x20ff, 0xc19d, 0x21, 0 + .dw 0x2140, 0xc19d, 0x217f, 0xc19d, 0x21, 0 + .dw 0x21c0, 0xc19d, 0x21ff, 0xc19d, 0x21, 0 + .dw 0x2240, 0xc19d, 0x227f, 0xc19d, 0x21, 0 + .dw 0x22c0, 0xc19d, 0x22ff, 0xc19d, 0x21, 0 + .dw 0x2340, 0xc19d, 0x237f, 0xc19d, 0x21, 0 + .dw 0x23c0, 0xc19d, 0x23ff, 0xc19d, 0x21, 0 + .dw 0x2440, 0xc19d, 0x247f, 0xc19d, 0x21, 0 + .dw 0x24c0, 0xc19d, 0x24ff, 0xc19d, 0x21, 0 + .dw 0x2540, 0xc19d, 0x257f, 0xc19d, 0x21, 0 + .dw 0x25c0, 0xc19d, 0x25ff, 0xc19d, 0x21, 0 + .dw 0x2640, 0xc19d, 0x267f, 0xc19d, 0x21, 0 + .dw 0x26c0, 0xc19d, 0x26ff, 0xc19d, 0x21, 0 + .dw 0x2740, 0xc19d, 0x277f, 0xc19d, 0x21, 0 + .dw 0x27c0, 0xc19d, 0x27ff, 0xc19d, 0x21, 0 + .dw 0x2840, 0xc19d, 0x287f, 0xc19d, 0x21, 0 + .dw 0x28c0, 0xc19d, 0x28ff, 0xc19d, 0x21, 0 + .dw 0x2940, 0xc19d, 0x297f, 0xc19d, 0x21, 0 + .dw 0x29c0, 0xc19d, 0x29ff, 0xc19d, 0x21, 0 + .dw 0x2a40, 0xc19d, 0x2a7f, 0xc19d, 0x21, 0 + .dw 0x2ac0, 0xc19d, 0x2aff, 0xc19d, 0x21, 0 + .dw 0x2b40, 0xc19d, 0x2b7f, 0xc19d, 0x21, 0 + .dw 0x2bc0, 0xc19d, 0x2bff, 0xc19d, 0x21, 0 + .dw 0x2c40, 0xc19d, 0x2c7f, 0xc19d, 0x21, 0 + .dw 0x2cc0, 0xc19d, 0x2cff, 0xc19d, 0x21, 0 + .dw 0x2d40, 0xc19d, 0x2d7f, 0xc19d, 0x21, 0 + .dw 0x2dc0, 0xc19d, 0x2dff, 0xc19d, 0x21, 0 + .dw 0x2e40, 0xc19d, 0x2e7f, 0xc19d, 0x21, 0 + .dw 0x2ec0, 0xc19d, 0x2eff, 0xc19d, 0x21, 0 + .dw 0x2f40, 0xc19d, 0x2f7f, 0xc19d, 0x21, 0 + .dw 0x2fc0, 0xc19d, 0x2fff, 0xc19d, 0x21, 0 + .dw 0x3040, 0xc19d, 0x307f, 0xc19d, 0x21, 0 + .dw 0x30c0, 0xc19d, 0x30ff, 0xc19d, 0x21, 0 + .dw 0x3140, 0xc19d, 0x317f, 0xc19d, 0x21, 0 + .dw 0x31c0, 0xc19d, 0x31ff, 0xc19d, 0x21, 0 + .dw 0x3240, 0xc19d, 0x327f, 0xc19d, 0x21, 0 + .dw 0x32c0, 0xc19d, 0x32ff, 0xc19d, 0x21, 0 + .dw 0x3340, 0xc19d, 0x337f, 0xc19d, 0x21, 0 + .dw 0x33c0, 0xc19d, 0x33ff, 0xc19d, 0x21, 0 + .dw 0x3440, 0xc19d, 0x347f, 0xc19d, 0x21, 0 + .dw 0x34c0, 0xc19d, 0x34ff, 0xc19d, 0x21, 0 + .dw 0x3540, 0xc19d, 0x357f, 0xc19d, 0x21, 0 + .dw 0x35c0, 0xc19d, 0x35ff, 0xc19d, 0x21, 0 + .dw 0x3640, 0xc19d, 0x367f, 0xc19d, 0x21, 0 + .dw 0x36c0, 0xc19d, 0x36ff, 0xc19d, 0x21, 0 + .dw 0x3740, 0xc19d, 0x377f, 0xc19d, 0x21, 0 + .dw 0x37c0, 0xc19d, 0x37ff, 0xc19d, 0x21, 0 + .dw 0x3840, 0xc19d, 0x387f, 0xc19d, 0x21, 0 + .dw 0x38c0, 0xc19d, 0x38ff, 0xc19d, 0x21, 0 + .dw 0x3940, 0xc19d, 0x397f, 0xc19d, 0x21, 0 + .dw 0x39c0, 0xc19d, 0x3fff, 0xc19d, 0x21, 0 + .dw 0x4040, 0xc19d, 0x407f, 0xc19d, 0x21, 0 + .dw 0x40c0, 0xc19d, 0x40ff, 0xc19d, 0x21, 0 + .dw 0x4140, 0xc19d, 0x417f, 0xc19d, 0x21, 0 + .dw 0x41c0, 0xc19d, 0x41ff, 0xc19d, 0x21, 0 + .dw 0x4240, 0xc19d, 0x427f, 0xc19d, 0x21, 0 + .dw 0x42c0, 0xc19d, 0x42ff, 0xc19d, 0x21, 0 + .dw 0x4340, 0xc19d, 0x437f, 0xc19d, 0x21, 0 + .dw 0x43c0, 0xc19d, 0x43ff, 0xc19d, 0x21, 0 + .dw 0x4440, 0xc19d, 0x447f, 0xc19d, 0x21, 0 + .dw 0x44c0, 0xc19d, 0x44ff, 0xc19d, 0x21, 0 + .dw 0x4540, 0xc19d, 0x457f, 0xc19d, 0x21, 0 + .dw 0x45c0, 0xc19d, 0x45ff, 0xc19d, 0x21, 0 + .dw 0x4640, 0xc19d, 0x467f, 0xc19d, 0x21, 0 + .dw 0x46c0, 0xc19d, 0x46ff, 0xc19d, 0x21, 0 + .dw 0x4740, 0xc19d, 0x477f, 0xc19d, 0x21, 0 + .dw 0x47c0, 0xc19d, 0x47ff, 0xc19d, 0x21, 0 + .dw 0x4840, 0xc19d, 0x487f, 0xc19d, 0x21, 0 + .dw 0x48c0, 0xc19d, 0x48ff, 0xc19d, 0x21, 0 + .dw 0x4940, 0xc19d, 0x497f, 0xc19d, 0x21, 0 + .dw 0x49c0, 0xc19d, 0x49ff, 0xc19d, 0x21, 0 + .dw 0x4a40, 0xc19d, 0x4a7f, 0xc19d, 0x21, 0 + .dw 0x4ac0, 0xc19d, 0x4aff, 0xc19d, 0x21, 0 + .dw 0x4b40, 0xc19d, 0x4b7f, 0xc19d, 0x21, 0 + .dw 0x4bc0, 0xc19d, 0x4bff, 0xc19d, 0x21, 0 + .dw 0x4c40, 0xc19d, 0x4c7f, 0xc19d, 0x21, 0 + .dw 0x4cc0, 0xc19d, 0x4cff, 0xc19d, 0x21, 0 + .dw 0x4d40, 0xc19d, 0x4d7f, 0xc19d, 0x21, 0 + .dw 0x4dc0, 0xc19d, 0x4dff, 0xc19d, 0x21, 0 + .dw 0x4e40, 0xc19d, 0x4e7f, 0xc19d, 0x21, 0 + .dw 0x4ec0, 0xc19d, 0x4eff, 0xc19d, 0x21, 0 + .dw 0x4f40, 0xc19d, 0x4f7f, 0xc19d, 0x21, 0 + .dw 0x4fc0, 0xc19d, 0x4fff, 0xc19d, 0x21, 0 + .dw 0x5040, 0xc19d, 0x507f, 0xc19d, 0x21, 0 + .dw 0x50c0, 0xc19d, 0x50ff, 0xc19d, 0x21, 0 + .dw 0x5140, 0xc19d, 0x517f, 0xc19d, 0x21, 0 + .dw 0x51c0, 0xc19d, 0x51ff, 0xc19d, 0x21, 0 + .dw 0x5240, 0xc19d, 0x527f, 0xc19d, 0x21, 0 + .dw 0x52c0, 0xc19d, 0x52ff, 0xc19d, 0x21, 0 + .dw 0x5340, 0xc19d, 0x537f, 0xc19d, 0x21, 0 + .dw 0x53c0, 0xc19d, 0x53ff, 0xc19d, 0x21, 0 + .dw 0x5440, 0xc19d, 0x547f, 0xc19d, 0x21, 0 + .dw 0x54c0, 0xc19d, 0x54ff, 0xc19d, 0x21, 0 + .dw 0x5540, 0xc19d, 0x557f, 0xc19d, 0x21, 0 + .dw 0x55c0, 0xc19d, 0x55ff, 0xc19d, 0x21, 0 + .dw 0x5640, 0xc19d, 0x567f, 0xc19d, 0x21, 0 + .dw 0x56c0, 0xc19d, 0x56ff, 0xc19d, 0x21, 0 + .dw 0x5740, 0xc19d, 0x577f, 0xc19d, 0x21, 0 + .dw 0x57c0, 0xc19d, 0x57ff, 0xc19d, 0x21, 0 + .dw 0x5840, 0xc19d, 0x587f, 0xc19d, 0x21, 0 + .dw 0x58c0, 0xc19d, 0x58ff, 0xc19d, 0x21, 0 + .dw 0x5940, 0xc19d, 0x597f, 0xc19d, 0x21, 0 + .dw 0x59c0, 0xc19d, 0x5fff, 0xc19d, 0x21, 0 + .dw 0x6040, 0xc19d, 0x607f, 0xc19d, 0x21, 0 + .dw 0x60c0, 0xc19d, 0x60ff, 0xc19d, 0x21, 0 + .dw 0x6140, 0xc19d, 0x617f, 0xc19d, 0x21, 0 + .dw 0x61c0, 0xc19d, 0x61ff, 0xc19d, 0x21, 0 + .dw 0x6240, 0xc19d, 0x627f, 0xc19d, 0x21, 0 + .dw 0x62c0, 0xc19d, 0x62ff, 0xc19d, 0x21, 0 + .dw 0x6340, 0xc19d, 0x637f, 0xc19d, 0x21, 0 + .dw 0x63c0, 0xc19d, 0x63ff, 0xc19d, 0x21, 0 + .dw 0x6440, 0xc19d, 0x647f, 0xc19d, 0x21, 0 + .dw 0x64c0, 0xc19d, 0x64ff, 0xc19d, 0x21, 0 + .dw 0x6540, 0xc19d, 0x657f, 0xc19d, 0x21, 0 + .dw 0x65c0, 0xc19d, 0x65ff, 0xc19d, 0x21, 0 + .dw 0x6640, 0xc19d, 0x667f, 0xc19d, 0x21, 0 + .dw 0x66c0, 0xc19d, 0x66ff, 0xc19d, 0x21, 0 + .dw 0x6740, 0xc19d, 0x677f, 0xc19d, 0x21, 0 + .dw 0x67c0, 0xc19d, 0x67ff, 0xc19d, 0x21, 0 + .dw 0x6840, 0xc19d, 0x687f, 0xc19d, 0x21, 0 + .dw 0x68c0, 0xc19d, 0x68ff, 0xc19d, 0x21, 0 + .dw 0x6940, 0xc19d, 0x697f, 0xc19d, 0x21, 0 + .dw 0x69c0, 0xc19d, 0x69ff, 0xc19d, 0x21, 0 + .dw 0x6a40, 0xc19d, 0x6a7f, 0xc19d, 0x21, 0 + .dw 0x6ac0, 0xc19d, 0x6aff, 0xc19d, 0x21, 0 + .dw 0x6b40, 0xc19d, 0x6b7f, 0xc19d, 0x21, 0 + .dw 0x6bc0, 0xc19d, 0x6bff, 0xc19d, 0x21, 0 + .dw 0x6c40, 0xc19d, 0x6c7f, 0xc19d, 0x21, 0 + .dw 0x6cc0, 0xc19d, 0x6cff, 0xc19d, 0x21, 0 + .dw 0x6d40, 0xc19d, 0x6d7f, 0xc19d, 0x21, 0 + .dw 0x6dc0, 0xc19d, 0x6dff, 0xc19d, 0x21, 0 + .dw 0x6e40, 0xc19d, 0x6e7f, 0xc19d, 0x21, 0 + .dw 0x6ec0, 0xc19d, 0x6eff, 0xc19d, 0x21, 0 + .dw 0x6f40, 0xc19d, 0x6f7f, 0xc19d, 0x21, 0 + .dw 0x6fc0, 0xc19d, 0x6fff, 0xc19d, 0x21, 0 + .dw 0x7040, 0xc19d, 0x707f, 0xc19d, 0x21, 0 + .dw 0x70c0, 0xc19d, 0x70ff, 0xc19d, 0x21, 0 + .dw 0x7140, 0xc19d, 0x717f, 0xc19d, 0x21, 0 + .dw 0x71c0, 0xc19d, 0x71ff, 0xc19d, 0x21, 0 + .dw 0x7240, 0xc19d, 0x727f, 0xc19d, 0x21, 0 + .dw 0x72c0, 0xc19d, 0x72ff, 0xc19d, 0x21, 0 + .dw 0x7340, 0xc19d, 0x737f, 0xc19d, 0x21, 0 + .dw 0x73c0, 0xc19d, 0x73ff, 0xc19d, 0x21, 0 + .dw 0x7440, 0xc19d, 0x747f, 0xc19d, 0x21, 0 + .dw 0x74c0, 0xc19d, 0x74ff, 0xc19d, 0x21, 0 + .dw 0x7540, 0xc19d, 0x757f, 0xc19d, 0x21, 0 + .dw 0x75c0, 0xc19d, 0x75ff, 0xc19d, 0x21, 0 + .dw 0x7640, 0xc19d, 0x767f, 0xc19d, 0x21, 0 + .dw 0x76c0, 0xc19d, 0x76ff, 0xc19d, 0x21, 0 + .dw 0x7740, 0xc19d, 0x777f, 0xc19d, 0x21, 0 + .dw 0x77c0, 0xc19d, 0x77ff, 0xc19d, 0x21, 0 + .dw 0x7840, 0xc19d, 0x787f, 0xc19d, 0x21, 0 + .dw 0x78c0, 0xc19d, 0x78ff, 0xc19d, 0x21, 0 + .dw 0x7940, 0xc19d, 0x797f, 0xc19d, 0x21, 0 + .dw 0x79c0, 0xc19d, 0x7fff, 0xc19d, 0x21, 0 + .dw 0x8040, 0xc19d, 0x807f, 0xc19d, 0x21, 0 + .dw 0x80c0, 0xc19d, 0x80ff, 0xc19d, 0x21, 0 + .dw 0x8140, 0xc19d, 0x817f, 0xc19d, 0x21, 0 + .dw 0x81c0, 0xc19d, 0x81ff, 0xc19d, 0x21, 0 + .dw 0x8240, 0xc19d, 0x827f, 0xc19d, 0x21, 0 + .dw 0x82c0, 0xc19d, 0x82ff, 0xc19d, 0x21, 0 + .dw 0x8340, 0xc19d, 0x837f, 0xc19d, 0x21, 0 + .dw 0x83c0, 0xc19d, 0x83ff, 0xc19d, 0x21, 0 + .dw 0x8440, 0xc19d, 0x847f, 0xc19d, 0x21, 0 + .dw 0x84c0, 0xc19d, 0x84ff, 0xc19d, 0x21, 0 + .dw 0x8540, 0xc19d, 0x857f, 0xc19d, 0x21, 0 + .dw 0x85c0, 0xc19d, 0x85ff, 0xc19d, 0x21, 0 + .dw 0x8640, 0xc19d, 0x867f, 0xc19d, 0x21, 0 + .dw 0x86c0, 0xc19d, 0x86ff, 0xc19d, 0x21, 0 + .dw 0x8740, 0xc19d, 0x877f, 0xc19d, 0x21, 0 + .dw 0x87c0, 0xc19d, 0x87ff, 0xc19d, 0x21, 0 + .dw 0x8840, 0xc19d, 0x887f, 0xc19d, 0x21, 0 + .dw 0x88c0, 0xc19d, 0x88ff, 0xc19d, 0x21, 0 + .dw 0x8940, 0xc19d, 0x897f, 0xc19d, 0x21, 0 + .dw 0x89c0, 0xc19d, 0x89ff, 0xc19d, 0x21, 0 + .dw 0x8a40, 0xc19d, 0x8a7f, 0xc19d, 0x21, 0 + .dw 0x8ac0, 0xc19d, 0x8aff, 0xc19d, 0x21, 0 + .dw 0x8b40, 0xc19d, 0x8b7f, 0xc19d, 0x21, 0 + .dw 0x8bc0, 0xc19d, 0x8bff, 0xc19d, 0x21, 0 + .dw 0x8c40, 0xc19d, 0x8c7f, 0xc19d, 0x21, 0 + .dw 0x8cc0, 0xc19d, 0x8cff, 0xc19d, 0x21, 0 + .dw 0x8d40, 0xc19d, 0x8d7f, 0xc19d, 0x21, 0 + .dw 0x8dc0, 0xc19d, 0x8dff, 0xc19d, 0x21, 0 + .dw 0x8e40, 0xc19d, 0x8e7f, 0xc19d, 0x21, 0 + .dw 0x8ec0, 0xc19d, 0x8eff, 0xc19d, 0x21, 0 + .dw 0x8f40, 0xc19d, 0x8f7f, 0xc19d, 0x21, 0 + .dw 0x8fc0, 0xc19d, 0x8fff, 0xc19d, 0x21, 0 + .dw 0x9040, 0xc19d, 0x907f, 0xc19d, 0x21, 0 + .dw 0x90c0, 0xc19d, 0x90ff, 0xc19d, 0x21, 0 + .dw 0x9140, 0xc19d, 0x917f, 0xc19d, 0x21, 0 + .dw 0x91c0, 0xc19d, 0x91ff, 0xc19d, 0x21, 0 + .dw 0x9240, 0xc19d, 0x927f, 0xc19d, 0x21, 0 + .dw 0x92c0, 0xc19d, 0x92ff, 0xc19d, 0x21, 0 + .dw 0x9340, 0xc19d, 0x937f, 0xc19d, 0x21, 0 + .dw 0x93c0, 0xc19d, 0x93ff, 0xc19d, 0x21, 0 + .dw 0x9440, 0xc19d, 0x947f, 0xc19d, 0x21, 0 + .dw 0x94c0, 0xc19d, 0x94ff, 0xc19d, 0x21, 0 + .dw 0x9540, 0xc19d, 0x957f, 0xc19d, 0x21, 0 + .dw 0x95c0, 0xc19d, 0x95ff, 0xc19d, 0x21, 0 + .dw 0x9640, 0xc19d, 0x967f, 0xc19d, 0x21, 0 + .dw 0x96c0, 0xc19d, 0x96ff, 0xc19d, 0x21, 0 + .dw 0x9740, 0xc19d, 0x977f, 0xc19d, 0x21, 0 + .dw 0x97c0, 0xc19d, 0x97ff, 0xc19d, 0x21, 0 + .dw 0x9840, 0xc19d, 0x987f, 0xc19d, 0x21, 0 + .dw 0x98c0, 0xc19d, 0x98ff, 0xc19d, 0x21, 0 + .dw 0x9940, 0xc19d, 0x997f, 0xc19d, 0x21, 0 + .dw 0x99c0, 0xc19d, 0x9fff, 0xc19d, 0x21, 0 + .dw 0xa040, 0xc19d, 0xa07f, 0xc19d, 0x21, 0 + .dw 0xa0c0, 0xc19d, 0xa0ff, 0xc19d, 0x21, 0 + .dw 0xa140, 0xc19d, 0xa17f, 0xc19d, 0x21, 0 + .dw 0xa1c0, 0xc19d, 0xa1ff, 0xc19d, 0x21, 0 + .dw 0xa240, 0xc19d, 0xa27f, 0xc19d, 0x21, 0 + .dw 0xa2c0, 0xc19d, 0xa2ff, 0xc19d, 0x21, 0 + .dw 0xa340, 0xc19d, 0xa37f, 0xc19d, 0x21, 0 + .dw 0xa3c0, 0xc19d, 0xa3ff, 0xc19d, 0x21, 0 + .dw 0xa440, 0xc19d, 0xa47f, 0xc19d, 0x21, 0 + .dw 0xa4c0, 0xc19d, 0xa4ff, 0xc19d, 0x21, 0 + .dw 0xa540, 0xc19d, 0xa57f, 0xc19d, 0x21, 0 + .dw 0xa5c0, 0xc19d, 0xa5ff, 0xc19d, 0x21, 0 + .dw 0xa640, 0xc19d, 0xa67f, 0xc19d, 0x21, 0 + .dw 0xa6c0, 0xc19d, 0xa6ff, 0xc19d, 0x21, 0 + .dw 0xa740, 0xc19d, 0xa77f, 0xc19d, 0x21, 0 + .dw 0xa7c0, 0xc19d, 0xa7ff, 0xc19d, 0x21, 0 + .dw 0xa840, 0xc19d, 0xa87f, 0xc19d, 0x21, 0 + .dw 0xa8c0, 0xc19d, 0xa8ff, 0xc19d, 0x21, 0 + .dw 0xa940, 0xc19d, 0xa97f, 0xc19d, 0x21, 0 + .dw 0xa9c0, 0xc19d, 0xa9ff, 0xc19d, 0x21, 0 + .dw 0xaa40, 0xc19d, 0xaa7f, 0xc19d, 0x21, 0 + .dw 0xaac0, 0xc19d, 0xaaff, 0xc19d, 0x21, 0 + .dw 0xab40, 0xc19d, 0xab7f, 0xc19d, 0x21, 0 + .dw 0xabc0, 0xc19d, 0xabff, 0xc19d, 0x21, 0 + .dw 0xac40, 0xc19d, 0xac7f, 0xc19d, 0x21, 0 + .dw 0xacc0, 0xc19d, 0xacff, 0xc19d, 0x21, 0 + .dw 0xad40, 0xc19d, 0xad7f, 0xc19d, 0x21, 0 + .dw 0xadc0, 0xc19d, 0xadff, 0xc19d, 0x21, 0 + .dw 0xae40, 0xc19d, 0xae7f, 0xc19d, 0x21, 0 + .dw 0xaec0, 0xc19d, 0xaeff, 0xc19d, 0x21, 0 + .dw 0xaf40, 0xc19d, 0xaf7f, 0xc19d, 0x21, 0 + .dw 0xafc0, 0xc19d, 0xafff, 0xc19d, 0x21, 0 + .dw 0xb040, 0xc19d, 0xb07f, 0xc19d, 0x21, 0 + .dw 0xb0c0, 0xc19d, 0xb0ff, 0xc19d, 0x21, 0 + .dw 0xb140, 0xc19d, 0xb17f, 0xc19d, 0x21, 0 + .dw 0xb1c0, 0xc19d, 0xb1ff, 0xc19d, 0x21, 0 + .dw 0xb240, 0xc19d, 0xb27f, 0xc19d, 0x21, 0 + .dw 0xb2c0, 0xc19d, 0xb2ff, 0xc19d, 0x21, 0 + .dw 0xb340, 0xc19d, 0xb37f, 0xc19d, 0x21, 0 + .dw 0xb3c0, 0xc19d, 0xb3ff, 0xc19d, 0x21, 0 + .dw 0xb440, 0xc19d, 0xb47f, 0xc19d, 0x21, 0 + .dw 0xb4c0, 0xc19d, 0xb4ff, 0xc19d, 0x21, 0 + .dw 0xb540, 0xc19d, 0xb57f, 0xc19d, 0x21, 0 + .dw 0xb5c0, 0xc19d, 0xb5ff, 0xc19d, 0x21, 0 + .dw 0xb640, 0xc19d, 0xb67f, 0xc19d, 0x21, 0 + .dw 0xb6c0, 0xc19d, 0xb6ff, 0xc19d, 0x21, 0 + .dw 0xb740, 0xc19d, 0xb77f, 0xc19d, 0x21, 0 + .dw 0xb7c0, 0xc19d, 0xb7ff, 0xc19d, 0x21, 0 + .dw 0xb840, 0xc19d, 0xb87f, 0xc19d, 0x21, 0 + .dw 0xb8c0, 0xc19d, 0xb8ff, 0xc19d, 0x21, 0 + .dw 0xb940, 0xc19d, 0xb97f, 0xc19d, 0x21, 0 + .dw 0xb9c0, 0xc19d, 0xbfff, 0xc19d, 0x21, 0 + .dw 0xc040, 0xc19d, 0xc07f, 0xc19d, 0x21, 0 + .dw 0xc0c0, 0xc19d, 0xc0ff, 0xc19d, 0x21, 0 + .dw 0xc140, 0xc19d, 0xc17f, 0xc19d, 0x21, 0 + .dw 0xc1c0, 0xc19d, 0xc1ff, 0xc19d, 0x21, 0 + .dw 0xc240, 0xc19d, 0xc27f, 0xc19d, 0x21, 0 + .dw 0xc2c0, 0xc19d, 0xc2ff, 0xc19d, 0x21, 0 + .dw 0xc340, 0xc19d, 0xc37f, 0xc19d, 0x21, 0 + .dw 0xc3c0, 0xc19d, 0xc3ff, 0xc19d, 0x21, 0 + .dw 0xc440, 0xc19d, 0xc47f, 0xc19d, 0x21, 0 + .dw 0xc4c0, 0xc19d, 0xc4ff, 0xc19d, 0x21, 0 + .dw 0xc540, 0xc19d, 0xc57f, 0xc19d, 0x21, 0 + .dw 0xc5c0, 0xc19d, 0xc5ff, 0xc19d, 0x21, 0 + .dw 0xc640, 0xc19d, 0xc67f, 0xc19d, 0x21, 0 + .dw 0xc6c0, 0xc19d, 0xc6ff, 0xc19d, 0x21, 0 + .dw 0xc740, 0xc19d, 0xc77f, 0xc19d, 0x21, 0 + .dw 0xc7c0, 0xc19d, 0xc7ff, 0xc19d, 0x21, 0 + .dw 0xc840, 0xc19d, 0xc87f, 0xc19d, 0x21, 0 + .dw 0xc8c0, 0xc19d, 0xc8ff, 0xc19d, 0x21, 0 + .dw 0xc940, 0xc19d, 0xc97f, 0xc19d, 0x21, 0 + .dw 0xc9c0, 0xc19d, 0xc9ff, 0xc19d, 0x21, 0 + .dw 0xca40, 0xc19d, 0xca7f, 0xc19d, 0x21, 0 + .dw 0xcac0, 0xc19d, 0xcaff, 0xc19d, 0x21, 0 + .dw 0xcb40, 0xc19d, 0xcb7f, 0xc19d, 0x21, 0 + .dw 0xcbc0, 0xc19d, 0xcbff, 0xc19d, 0x21, 0 + .dw 0xcc40, 0xc19d, 0xcc7f, 0xc19d, 0x21, 0 + .dw 0xccc0, 0xc19d, 0xccff, 0xc19d, 0x21, 0 + .dw 0xcd40, 0xc19d, 0xcd7f, 0xc19d, 0x21, 0 + .dw 0xcdc0, 0xc19d, 0xcdff, 0xc19d, 0x21, 0 + .dw 0xce40, 0xc19d, 0xce7f, 0xc19d, 0x21, 0 + .dw 0xcec0, 0xc19d, 0xceff, 0xc19d, 0x21, 0 + .dw 0xcf40, 0xc19d, 0xcf7f, 0xc19d, 0x21, 0 + .dw 0xcfc0, 0xc19d, 0xcfff, 0xc19d, 0x21, 0 + .dw 0xd040, 0xc19d, 0xd07f, 0xc19d, 0x21, 0 + .dw 0xd0c0, 0xc19d, 0xd0ff, 0xc19d, 0x21, 0 + .dw 0xd140, 0xc19d, 0xd17f, 0xc19d, 0x21, 0 + .dw 0xd1c0, 0xc19d, 0xd1ff, 0xc19d, 0x21, 0 + .dw 0xd240, 0xc19d, 0xd27f, 0xc19d, 0x21, 0 + .dw 0xd2c0, 0xc19d, 0xd2ff, 0xc19d, 0x21, 0 + .dw 0xd340, 0xc19d, 0xd37f, 0xc19d, 0x21, 0 + .dw 0xd3c0, 0xc19d, 0xd3ff, 0xc19d, 0x21, 0 + .dw 0xd440, 0xc19d, 0xd47f, 0xc19d, 0x21, 0 + .dw 0xd4c0, 0xc19d, 0xd4ff, 0xc19d, 0x21, 0 + .dw 0xd540, 0xc19d, 0xd57f, 0xc19d, 0x21, 0 + .dw 0xd5c0, 0xc19d, 0xd5ff, 0xc19d, 0x21, 0 + .dw 0xd640, 0xc19d, 0xd67f, 0xc19d, 0x21, 0 + .dw 0xd6c0, 0xc19d, 0xd6ff, 0xc19d, 0x21, 0 + .dw 0xd740, 0xc19d, 0xd77f, 0xc19d, 0x21, 0 + .dw 0xd7c0, 0xc19d, 0xd7ff, 0xc19d, 0x21, 0 + .dw 0xd840, 0xc19d, 0xd87f, 0xc19d, 0x21, 0 + .dw 0xd8c0, 0xc19d, 0xd8ff, 0xc19d, 0x21, 0 + .dw 0xd940, 0xc19d, 0xd97f, 0xc19d, 0x21, 0 + .dw 0xd9c0, 0xc19d, 0xdfff, 0xc19d, 0x21, 0 + .dw 0xe040, 0xc19d, 0xe07f, 0xc19d, 0x21, 0 + .dw 0xe0c0, 0xc19d, 0xe0ff, 0xc19d, 0x21, 0 + .dw 0xe140, 0xc19d, 0xe17f, 0xc19d, 0x21, 0 + .dw 0xe1c0, 0xc19d, 0xe1ff, 0xc19d, 0x21, 0 + .dw 0xe240, 0xc19d, 0xe27f, 0xc19d, 0x21, 0 + .dw 0xe2c0, 0xc19d, 0xe2ff, 0xc19d, 0x21, 0 + .dw 0xe340, 0xc19d, 0xe37f, 0xc19d, 0x21, 0 + .dw 0xe3c0, 0xc19d, 0xe3ff, 0xc19d, 0x21, 0 + .dw 0xe440, 0xc19d, 0xe47f, 0xc19d, 0x21, 0 + .dw 0xe4c0, 0xc19d, 0xe4ff, 0xc19d, 0x21, 0 + .dw 0xe540, 0xc19d, 0xe57f, 0xc19d, 0x21, 0 + .dw 0xe5c0, 0xc19d, 0xe5ff, 0xc19d, 0x21, 0 + .dw 0xe640, 0xc19d, 0xe67f, 0xc19d, 0x21, 0 + .dw 0xe6c0, 0xc19d, 0xe6ff, 0xc19d, 0x21, 0 + .dw 0xe740, 0xc19d, 0xe77f, 0xc19d, 0x21, 0 + .dw 0xe7c0, 0xc19d, 0xe7ff, 0xc19d, 0x21, 0 + .dw 0xe840, 0xc19d, 0xe87f, 0xc19d, 0x21, 0 + .dw 0xe8c0, 0xc19d, 0xe8ff, 0xc19d, 0x21, 0 + .dw 0xe940, 0xc19d, 0xe97f, 0xc19d, 0x21, 0 + .dw 0xe9c0, 0xc19d, 0xe9ff, 0xc19d, 0x21, 0 + .dw 0xea40, 0xc19d, 0xea7f, 0xc19d, 0x21, 0 + .dw 0xeac0, 0xc19d, 0xeaff, 0xc19d, 0x21, 0 + .dw 0xeb40, 0xc19d, 0xeb7f, 0xc19d, 0x21, 0 + .dw 0xebc0, 0xc19d, 0xebff, 0xc19d, 0x21, 0 + .dw 0xec40, 0xc19d, 0xec7f, 0xc19d, 0x21, 0 + .dw 0xecc0, 0xc19d, 0xecff, 0xc19d, 0x21, 0 + .dw 0xed40, 0xc19d, 0xed7f, 0xc19d, 0x21, 0 + .dw 0xedc0, 0xc19d, 0xedff, 0xc19d, 0x21, 0 + .dw 0xee40, 0xc19d, 0xee7f, 0xc19d, 0x21, 0 + .dw 0xeec0, 0xc19d, 0xeeff, 0xc19d, 0x21, 0 + .dw 0xef40, 0xc19d, 0xef7f, 0xc19d, 0x21, 0 + .dw 0xefc0, 0xc19d, 0xefff, 0xc19d, 0x21, 0 + .dw 0xf040, 0xc19d, 0xf07f, 0xc19d, 0x21, 0 + .dw 0xf0c0, 0xc19d, 0xf0ff, 0xc19d, 0x21, 0 + .dw 0xf140, 0xc19d, 0xf17f, 0xc19d, 0x21, 0 + .dw 0xf1c0, 0xc19d, 0xf1ff, 0xc19d, 0x21, 0 + .dw 0xf240, 0xc19d, 0xf27f, 0xc19d, 0x21, 0 + .dw 0xf2c0, 0xc19d, 0xf2ff, 0xc19d, 0x21, 0 + .dw 0xf340, 0xc19d, 0xf37f, 0xc19d, 0x21, 0 + .dw 0xf3c0, 0xc19d, 0xf3ff, 0xc19d, 0x21, 0 + .dw 0xf440, 0xc19d, 0xf47f, 0xc19d, 0x21, 0 + .dw 0xf4c0, 0xc19d, 0xf4ff, 0xc19d, 0x21, 0 + .dw 0xf540, 0xc19d, 0xf57f, 0xc19d, 0x21, 0 + .dw 0xf5c0, 0xc19d, 0xf5ff, 0xc19d, 0x21, 0 + .dw 0xf640, 0xc19d, 0xf67f, 0xc19d, 0x21, 0 + .dw 0xf6c0, 0xc19d, 0xf6ff, 0xc19d, 0x21, 0 + .dw 0xf740, 0xc19d, 0xf77f, 0xc19d, 0x21, 0 + .dw 0xf7c0, 0xc19d, 0xf7ff, 0xc19d, 0x21, 0 + .dw 0xf840, 0xc19d, 0xf87f, 0xc19d, 0x21, 0 + .dw 0xf8c0, 0xc19d, 0xf8ff, 0xc19d, 0x21, 0 + .dw 0xf940, 0xc19d, 0xf97f, 0xc19d, 0x21, 0 + .dw 0xf9c0, 0xc19d, 0xffff, 0xc19d, 0x21, 0 + .dw 0x0040, 0xc19e, 0x007f, 0xc19e, 0x21, 0 + .dw 0x00c0, 0xc19e, 0x00ff, 0xc19e, 0x21, 0 + .dw 0x0140, 0xc19e, 0x017f, 0xc19e, 0x21, 0 + .dw 0x01c0, 0xc19e, 0x01ff, 0xc19e, 0x21, 0 + .dw 0x0240, 0xc19e, 0x027f, 0xc19e, 0x21, 0 + .dw 0x02c0, 0xc19e, 0x02ff, 0xc19e, 0x21, 0 + .dw 0x0340, 0xc19e, 0x037f, 0xc19e, 0x21, 0 + .dw 0x03c0, 0xc19e, 0x03ff, 0xc19e, 0x21, 0 + .dw 0x0440, 0xc19e, 0x047f, 0xc19e, 0x21, 0 + .dw 0x04c0, 0xc19e, 0x04ff, 0xc19e, 0x21, 0 + .dw 0x0540, 0xc19e, 0x057f, 0xc19e, 0x21, 0 + .dw 0x05c0, 0xc19e, 0x05ff, 0xc19e, 0x21, 0 + .dw 0x0640, 0xc19e, 0x067f, 0xc19e, 0x21, 0 + .dw 0x06c0, 0xc19e, 0x06ff, 0xc19e, 0x21, 0 + .dw 0x0740, 0xc19e, 0x077f, 0xc19e, 0x21, 0 + .dw 0x07c0, 0xc19e, 0x07ff, 0xc19e, 0x21, 0 + .dw 0x0840, 0xc19e, 0x087f, 0xc19e, 0x21, 0 + .dw 0x08c0, 0xc19e, 0x08ff, 0xc19e, 0x21, 0 + .dw 0x0940, 0xc19e, 0x097f, 0xc19e, 0x21, 0 + .dw 0x09c0, 0xc19e, 0x09ff, 0xc19e, 0x21, 0 + .dw 0x0a40, 0xc19e, 0x0a7f, 0xc19e, 0x21, 0 + .dw 0x0ac0, 0xc19e, 0x0aff, 0xc19e, 0x21, 0 + .dw 0x0b40, 0xc19e, 0x0b7f, 0xc19e, 0x21, 0 + .dw 0x0bc0, 0xc19e, 0x0bff, 0xc19e, 0x21, 0 + .dw 0x0c40, 0xc19e, 0x0c7f, 0xc19e, 0x21, 0 + .dw 0x0cc0, 0xc19e, 0x0cff, 0xc19e, 0x21, 0 + .dw 0x0d40, 0xc19e, 0x0d7f, 0xc19e, 0x21, 0 + .dw 0x0dc0, 0xc19e, 0x0dff, 0xc19e, 0x21, 0 + .dw 0x0e40, 0xc19e, 0x0e7f, 0xc19e, 0x21, 0 + .dw 0x0ec0, 0xc19e, 0x0eff, 0xc19e, 0x21, 0 + .dw 0x0f40, 0xc19e, 0x0f7f, 0xc19e, 0x21, 0 + .dw 0x0fc0, 0xc19e, 0x0fff, 0xc19e, 0x21, 0 + .dw 0x1040, 0xc19e, 0x107f, 0xc19e, 0x21, 0 + .dw 0x10c0, 0xc19e, 0x10ff, 0xc19e, 0x21, 0 + .dw 0x1140, 0xc19e, 0x117f, 0xc19e, 0x21, 0 + .dw 0x11c0, 0xc19e, 0x11ff, 0xc19e, 0x21, 0 + .dw 0x1240, 0xc19e, 0x127f, 0xc19e, 0x21, 0 + .dw 0x12c0, 0xc19e, 0x12ff, 0xc19e, 0x21, 0 + .dw 0x1340, 0xc19e, 0x137f, 0xc19e, 0x21, 0 + .dw 0x13c0, 0xc19e, 0x13ff, 0xc19e, 0x21, 0 + .dw 0x1440, 0xc19e, 0x147f, 0xc19e, 0x21, 0 + .dw 0x14c0, 0xc19e, 0x14ff, 0xc19e, 0x21, 0 + .dw 0x1540, 0xc19e, 0x157f, 0xc19e, 0x21, 0 + .dw 0x15c0, 0xc19e, 0x15ff, 0xc19e, 0x21, 0 + .dw 0x1640, 0xc19e, 0x167f, 0xc19e, 0x21, 0 + .dw 0x16c0, 0xc19e, 0x16ff, 0xc19e, 0x21, 0 + .dw 0x1740, 0xc19e, 0x177f, 0xc19e, 0x21, 0 + .dw 0x17c0, 0xc19e, 0x17ff, 0xc19e, 0x21, 0 + .dw 0x1840, 0xc19e, 0x187f, 0xc19e, 0x21, 0 + .dw 0x18c0, 0xc19e, 0x18ff, 0xc19e, 0x21, 0 + .dw 0x1940, 0xc19e, 0x197f, 0xc19e, 0x21, 0 + .dw 0x19c0, 0xc19e, 0x1fff, 0xc19e, 0x21, 0 + .dw 0x2040, 0xc19e, 0x207f, 0xc19e, 0x21, 0 + .dw 0x20c0, 0xc19e, 0x20ff, 0xc19e, 0x21, 0 + .dw 0x2140, 0xc19e, 0x217f, 0xc19e, 0x21, 0 + .dw 0x21c0, 0xc19e, 0x21ff, 0xc19e, 0x21, 0 + .dw 0x2240, 0xc19e, 0x227f, 0xc19e, 0x21, 0 + .dw 0x22c0, 0xc19e, 0x22ff, 0xc19e, 0x21, 0 + .dw 0x2340, 0xc19e, 0x237f, 0xc19e, 0x21, 0 + .dw 0x23c0, 0xc19e, 0x23ff, 0xc19e, 0x21, 0 + .dw 0x2440, 0xc19e, 0x247f, 0xc19e, 0x21, 0 + .dw 0x24c0, 0xc19e, 0x24ff, 0xc19e, 0x21, 0 + .dw 0x2540, 0xc19e, 0x257f, 0xc19e, 0x21, 0 + .dw 0x25c0, 0xc19e, 0x25ff, 0xc19e, 0x21, 0 + .dw 0x2640, 0xc19e, 0x267f, 0xc19e, 0x21, 0 + .dw 0x26c0, 0xc19e, 0x26ff, 0xc19e, 0x21, 0 + .dw 0x2740, 0xc19e, 0x277f, 0xc19e, 0x21, 0 + .dw 0x27c0, 0xc19e, 0x27ff, 0xc19e, 0x21, 0 + .dw 0x2840, 0xc19e, 0x287f, 0xc19e, 0x21, 0 + .dw 0x28c0, 0xc19e, 0x28ff, 0xc19e, 0x21, 0 + .dw 0x2940, 0xc19e, 0x297f, 0xc19e, 0x21, 0 + .dw 0x29c0, 0xc19e, 0x29ff, 0xc19e, 0x21, 0 + .dw 0x2a40, 0xc19e, 0x2a7f, 0xc19e, 0x21, 0 + .dw 0x2ac0, 0xc19e, 0x2aff, 0xc19e, 0x21, 0 + .dw 0x2b40, 0xc19e, 0x2b7f, 0xc19e, 0x21, 0 + .dw 0x2bc0, 0xc19e, 0x2bff, 0xc19e, 0x21, 0 + .dw 0x2c40, 0xc19e, 0x2c7f, 0xc19e, 0x21, 0 + .dw 0x2cc0, 0xc19e, 0x2cff, 0xc19e, 0x21, 0 + .dw 0x2d40, 0xc19e, 0x2d7f, 0xc19e, 0x21, 0 + .dw 0x2dc0, 0xc19e, 0x2dff, 0xc19e, 0x21, 0 + .dw 0x2e40, 0xc19e, 0x2e7f, 0xc19e, 0x21, 0 + .dw 0x2ec0, 0xc19e, 0x2eff, 0xc19e, 0x21, 0 + .dw 0x2f40, 0xc19e, 0x2f7f, 0xc19e, 0x21, 0 + .dw 0x2fc0, 0xc19e, 0x2fff, 0xc19e, 0x21, 0 + .dw 0x3040, 0xc19e, 0x307f, 0xc19e, 0x21, 0 + .dw 0x30c0, 0xc19e, 0x30ff, 0xc19e, 0x21, 0 + .dw 0x3140, 0xc19e, 0x317f, 0xc19e, 0x21, 0 + .dw 0x31c0, 0xc19e, 0x31ff, 0xc19e, 0x21, 0 + .dw 0x3240, 0xc19e, 0x327f, 0xc19e, 0x21, 0 + .dw 0x32c0, 0xc19e, 0x32ff, 0xc19e, 0x21, 0 + .dw 0x3340, 0xc19e, 0x337f, 0xc19e, 0x21, 0 + .dw 0x33c0, 0xc19e, 0x33ff, 0xc19e, 0x21, 0 + .dw 0x3440, 0xc19e, 0x347f, 0xc19e, 0x21, 0 + .dw 0x34c0, 0xc19e, 0x34ff, 0xc19e, 0x21, 0 + .dw 0x3540, 0xc19e, 0x357f, 0xc19e, 0x21, 0 + .dw 0x35c0, 0xc19e, 0x35ff, 0xc19e, 0x21, 0 + .dw 0x3640, 0xc19e, 0x367f, 0xc19e, 0x21, 0 + .dw 0x36c0, 0xc19e, 0x36ff, 0xc19e, 0x21, 0 + .dw 0x3740, 0xc19e, 0x377f, 0xc19e, 0x21, 0 + .dw 0x37c0, 0xc19e, 0x37ff, 0xc19e, 0x21, 0 + .dw 0x3840, 0xc19e, 0x387f, 0xc19e, 0x21, 0 + .dw 0x38c0, 0xc19e, 0x38ff, 0xc19e, 0x21, 0 + .dw 0x3940, 0xc19e, 0x397f, 0xc19e, 0x21, 0 + .dw 0x39c0, 0xc19e, 0x3fff, 0xc19e, 0x21, 0 + .dw 0x4040, 0xc19e, 0x407f, 0xc19e, 0x21, 0 + .dw 0x40c0, 0xc19e, 0x40ff, 0xc19e, 0x21, 0 + .dw 0x4140, 0xc19e, 0x417f, 0xc19e, 0x21, 0 + .dw 0x41c0, 0xc19e, 0x41ff, 0xc19e, 0x21, 0 + .dw 0x4240, 0xc19e, 0x427f, 0xc19e, 0x21, 0 + .dw 0x42c0, 0xc19e, 0x42ff, 0xc19e, 0x21, 0 + .dw 0x4340, 0xc19e, 0x437f, 0xc19e, 0x21, 0 + .dw 0x43c0, 0xc19e, 0x43ff, 0xc19e, 0x21, 0 + .dw 0x4440, 0xc19e, 0x447f, 0xc19e, 0x21, 0 + .dw 0x44c0, 0xc19e, 0x44ff, 0xc19e, 0x21, 0 + .dw 0x4540, 0xc19e, 0x457f, 0xc19e, 0x21, 0 + .dw 0x45c0, 0xc19e, 0x45ff, 0xc19e, 0x21, 0 + .dw 0x4640, 0xc19e, 0x467f, 0xc19e, 0x21, 0 + .dw 0x46c0, 0xc19e, 0x46ff, 0xc19e, 0x21, 0 + .dw 0x4740, 0xc19e, 0x477f, 0xc19e, 0x21, 0 + .dw 0x47c0, 0xc19e, 0x47ff, 0xc19e, 0x21, 0 + .dw 0x4840, 0xc19e, 0x487f, 0xc19e, 0x21, 0 + .dw 0x48c0, 0xc19e, 0x48ff, 0xc19e, 0x21, 0 + .dw 0x4940, 0xc19e, 0x497f, 0xc19e, 0x21, 0 + .dw 0x49c0, 0xc19e, 0x49ff, 0xc19e, 0x21, 0 + .dw 0x4a40, 0xc19e, 0x4a7f, 0xc19e, 0x21, 0 + .dw 0x4ac0, 0xc19e, 0x4aff, 0xc19e, 0x21, 0 + .dw 0x4b40, 0xc19e, 0x4b7f, 0xc19e, 0x21, 0 + .dw 0x4bc0, 0xc19e, 0x4bff, 0xc19e, 0x21, 0 + .dw 0x4c40, 0xc19e, 0x4c7f, 0xc19e, 0x21, 0 + .dw 0x4cc0, 0xc19e, 0x4cff, 0xc19e, 0x21, 0 + .dw 0x4d40, 0xc19e, 0x4d7f, 0xc19e, 0x21, 0 + .dw 0x4dc0, 0xc19e, 0x4dff, 0xc19e, 0x21, 0 + .dw 0x4e40, 0xc19e, 0x4e7f, 0xc19e, 0x21, 0 + .dw 0x4ec0, 0xc19e, 0x4eff, 0xc19e, 0x21, 0 + .dw 0x4f40, 0xc19e, 0x4f7f, 0xc19e, 0x21, 0 + .dw 0x4fc0, 0xc19e, 0x4fff, 0xc19e, 0x21, 0 + .dw 0x5040, 0xc19e, 0x507f, 0xc19e, 0x21, 0 + .dw 0x50c0, 0xc19e, 0x50ff, 0xc19e, 0x21, 0 + .dw 0x5140, 0xc19e, 0x517f, 0xc19e, 0x21, 0 + .dw 0x51c0, 0xc19e, 0x51ff, 0xc19e, 0x21, 0 + .dw 0x5240, 0xc19e, 0x527f, 0xc19e, 0x21, 0 + .dw 0x52c0, 0xc19e, 0x52ff, 0xc19e, 0x21, 0 + .dw 0x5340, 0xc19e, 0x537f, 0xc19e, 0x21, 0 + .dw 0x53c0, 0xc19e, 0x53ff, 0xc19e, 0x21, 0 + .dw 0x5440, 0xc19e, 0x547f, 0xc19e, 0x21, 0 + .dw 0x54c0, 0xc19e, 0x54ff, 0xc19e, 0x21, 0 + .dw 0x5540, 0xc19e, 0x557f, 0xc19e, 0x21, 0 + .dw 0x55c0, 0xc19e, 0x55ff, 0xc19e, 0x21, 0 + .dw 0x5640, 0xc19e, 0x567f, 0xc19e, 0x21, 0 + .dw 0x56c0, 0xc19e, 0x56ff, 0xc19e, 0x21, 0 + .dw 0x5740, 0xc19e, 0x577f, 0xc19e, 0x21, 0 + .dw 0x57c0, 0xc19e, 0x57ff, 0xc19e, 0x21, 0 + .dw 0x5840, 0xc19e, 0x587f, 0xc19e, 0x21, 0 + .dw 0x58c0, 0xc19e, 0x58ff, 0xc19e, 0x21, 0 + .dw 0x5940, 0xc19e, 0x597f, 0xc19e, 0x21, 0 + .dw 0x59c0, 0xc19e, 0x5fff, 0xc19e, 0x21, 0 + .dw 0x6040, 0xc19e, 0x607f, 0xc19e, 0x21, 0 + .dw 0x60c0, 0xc19e, 0x60ff, 0xc19e, 0x21, 0 + .dw 0x6140, 0xc19e, 0x617f, 0xc19e, 0x21, 0 + .dw 0x61c0, 0xc19e, 0x61ff, 0xc19e, 0x21, 0 + .dw 0x6240, 0xc19e, 0x627f, 0xc19e, 0x21, 0 + .dw 0x62c0, 0xc19e, 0x62ff, 0xc19e, 0x21, 0 + .dw 0x6340, 0xc19e, 0x637f, 0xc19e, 0x21, 0 + .dw 0x63c0, 0xc19e, 0x63ff, 0xc19e, 0x21, 0 + .dw 0x6440, 0xc19e, 0x647f, 0xc19e, 0x21, 0 + .dw 0x64c0, 0xc19e, 0x64ff, 0xc19e, 0x21, 0 + .dw 0x6540, 0xc19e, 0x657f, 0xc19e, 0x21, 0 + .dw 0x65c0, 0xc19e, 0x65ff, 0xc19e, 0x21, 0 + .dw 0x6640, 0xc19e, 0x667f, 0xc19e, 0x21, 0 + .dw 0x66c0, 0xc19e, 0x66ff, 0xc19e, 0x21, 0 + .dw 0x6740, 0xc19e, 0x677f, 0xc19e, 0x21, 0 + .dw 0x67c0, 0xc19e, 0x67ff, 0xc19e, 0x21, 0 + .dw 0x6840, 0xc19e, 0x687f, 0xc19e, 0x21, 0 + .dw 0x68c0, 0xc19e, 0x68ff, 0xc19e, 0x21, 0 + .dw 0x6940, 0xc19e, 0x697f, 0xc19e, 0x21, 0 + .dw 0x69c0, 0xc19e, 0x69ff, 0xc19e, 0x21, 0 + .dw 0x6a40, 0xc19e, 0x6a7f, 0xc19e, 0x21, 0 + .dw 0x6ac0, 0xc19e, 0x6aff, 0xc19e, 0x21, 0 + .dw 0x6b40, 0xc19e, 0x6b7f, 0xc19e, 0x21, 0 + .dw 0x6bc0, 0xc19e, 0x6bff, 0xc19e, 0x21, 0 + .dw 0x6c40, 0xc19e, 0x6c7f, 0xc19e, 0x21, 0 + .dw 0x6cc0, 0xc19e, 0x6cff, 0xc19e, 0x21, 0 + .dw 0x6d40, 0xc19e, 0x6d7f, 0xc19e, 0x21, 0 + .dw 0x6dc0, 0xc19e, 0x6dff, 0xc19e, 0x21, 0 + .dw 0x6e40, 0xc19e, 0x6e7f, 0xc19e, 0x21, 0 + .dw 0x6ec0, 0xc19e, 0x6eff, 0xc19e, 0x21, 0 + .dw 0x6f40, 0xc19e, 0x6f7f, 0xc19e, 0x21, 0 + .dw 0x6fc0, 0xc19e, 0x6fff, 0xc19e, 0x21, 0 + .dw 0x7040, 0xc19e, 0x707f, 0xc19e, 0x21, 0 + .dw 0x70c0, 0xc19e, 0x70ff, 0xc19e, 0x21, 0 + .dw 0x7140, 0xc19e, 0x717f, 0xc19e, 0x21, 0 + .dw 0x71c0, 0xc19e, 0x71ff, 0xc19e, 0x21, 0 + .dw 0x7240, 0xc19e, 0x727f, 0xc19e, 0x21, 0 + .dw 0x72c0, 0xc19e, 0x72ff, 0xc19e, 0x21, 0 + .dw 0x7340, 0xc19e, 0x737f, 0xc19e, 0x21, 0 + .dw 0x73c0, 0xc19e, 0x73ff, 0xc19e, 0x21, 0 + .dw 0x7440, 0xc19e, 0x747f, 0xc19e, 0x21, 0 + .dw 0x74c0, 0xc19e, 0x74ff, 0xc19e, 0x21, 0 + .dw 0x7540, 0xc19e, 0x757f, 0xc19e, 0x21, 0 + .dw 0x75c0, 0xc19e, 0x75ff, 0xc19e, 0x21, 0 + .dw 0x7640, 0xc19e, 0x767f, 0xc19e, 0x21, 0 + .dw 0x76c0, 0xc19e, 0x76ff, 0xc19e, 0x21, 0 + .dw 0x7740, 0xc19e, 0x777f, 0xc19e, 0x21, 0 + .dw 0x77c0, 0xc19e, 0x77ff, 0xc19e, 0x21, 0 + .dw 0x7840, 0xc19e, 0x787f, 0xc19e, 0x21, 0 + .dw 0x78c0, 0xc19e, 0x78ff, 0xc19e, 0x21, 0 + .dw 0x7940, 0xc19e, 0x797f, 0xc19e, 0x21, 0 + .dw 0x79c0, 0xc19e, 0x7fff, 0xc19e, 0x21, 0 + .dw 0x8040, 0xc19e, 0x807f, 0xc19e, 0x21, 0 + .dw 0x80c0, 0xc19e, 0x80ff, 0xc19e, 0x21, 0 + .dw 0x8140, 0xc19e, 0x817f, 0xc19e, 0x21, 0 + .dw 0x81c0, 0xc19e, 0x81ff, 0xc19e, 0x21, 0 + .dw 0x8240, 0xc19e, 0x827f, 0xc19e, 0x21, 0 + .dw 0x82c0, 0xc19e, 0x82ff, 0xc19e, 0x21, 0 + .dw 0x8340, 0xc19e, 0x837f, 0xc19e, 0x21, 0 + .dw 0x83c0, 0xc19e, 0x83ff, 0xc19e, 0x21, 0 + .dw 0x8440, 0xc19e, 0x847f, 0xc19e, 0x21, 0 + .dw 0x84c0, 0xc19e, 0x84ff, 0xc19e, 0x21, 0 + .dw 0x8540, 0xc19e, 0x857f, 0xc19e, 0x21, 0 + .dw 0x85c0, 0xc19e, 0x85ff, 0xc19e, 0x21, 0 + .dw 0x8640, 0xc19e, 0x867f, 0xc19e, 0x21, 0 + .dw 0x86c0, 0xc19e, 0x86ff, 0xc19e, 0x21, 0 + .dw 0x8740, 0xc19e, 0x877f, 0xc19e, 0x21, 0 + .dw 0x87c0, 0xc19e, 0x87ff, 0xc19e, 0x21, 0 + .dw 0x8840, 0xc19e, 0x887f, 0xc19e, 0x21, 0 + .dw 0x88c0, 0xc19e, 0x88ff, 0xc19e, 0x21, 0 + .dw 0x8940, 0xc19e, 0x897f, 0xc19e, 0x21, 0 + .dw 0x89c0, 0xc19e, 0x89ff, 0xc19e, 0x21, 0 + .dw 0x8a40, 0xc19e, 0x8a7f, 0xc19e, 0x21, 0 + .dw 0x8ac0, 0xc19e, 0x8aff, 0xc19e, 0x21, 0 + .dw 0x8b40, 0xc19e, 0x8b7f, 0xc19e, 0x21, 0 + .dw 0x8bc0, 0xc19e, 0x8bff, 0xc19e, 0x21, 0 + .dw 0x8c40, 0xc19e, 0x8c7f, 0xc19e, 0x21, 0 + .dw 0x8cc0, 0xc19e, 0x8cff, 0xc19e, 0x21, 0 + .dw 0x8d40, 0xc19e, 0x8d7f, 0xc19e, 0x21, 0 + .dw 0x8dc0, 0xc19e, 0x8dff, 0xc19e, 0x21, 0 + .dw 0x8e40, 0xc19e, 0x8e7f, 0xc19e, 0x21, 0 + .dw 0x8ec0, 0xc19e, 0x8eff, 0xc19e, 0x21, 0 + .dw 0x8f40, 0xc19e, 0x8f7f, 0xc19e, 0x21, 0 + .dw 0x8fc0, 0xc19e, 0x8fff, 0xc19e, 0x21, 0 + .dw 0x9040, 0xc19e, 0x907f, 0xc19e, 0x21, 0 + .dw 0x90c0, 0xc19e, 0x90ff, 0xc19e, 0x21, 0 + .dw 0x9140, 0xc19e, 0x917f, 0xc19e, 0x21, 0 + .dw 0x91c0, 0xc19e, 0x91ff, 0xc19e, 0x21, 0 + .dw 0x9240, 0xc19e, 0x927f, 0xc19e, 0x21, 0 + .dw 0x92c0, 0xc19e, 0x92ff, 0xc19e, 0x21, 0 + .dw 0x9340, 0xc19e, 0x937f, 0xc19e, 0x21, 0 + .dw 0x93c0, 0xc19e, 0x93ff, 0xc19e, 0x21, 0 + .dw 0x9440, 0xc19e, 0x947f, 0xc19e, 0x21, 0 + .dw 0x94c0, 0xc19e, 0x94ff, 0xc19e, 0x21, 0 + .dw 0x9540, 0xc19e, 0x957f, 0xc19e, 0x21, 0 + .dw 0x95c0, 0xc19e, 0x95ff, 0xc19e, 0x21, 0 + .dw 0x9640, 0xc19e, 0x967f, 0xc19e, 0x21, 0 + .dw 0x96c0, 0xc19e, 0x96ff, 0xc19e, 0x21, 0 + .dw 0x9740, 0xc19e, 0x977f, 0xc19e, 0x21, 0 + .dw 0x97c0, 0xc19e, 0x97ff, 0xc19e, 0x21, 0 + .dw 0x9840, 0xc19e, 0x987f, 0xc19e, 0x21, 0 + .dw 0x98c0, 0xc19e, 0x98ff, 0xc19e, 0x21, 0 + .dw 0x9940, 0xc19e, 0x997f, 0xc19e, 0x21, 0 + .dw 0x99c0, 0xc19e, 0x9fff, 0xc19e, 0x21, 0 + .dw 0xa040, 0xc19e, 0xa07f, 0xc19e, 0x21, 0 + .dw 0xa0c0, 0xc19e, 0xa0ff, 0xc19e, 0x21, 0 + .dw 0xa140, 0xc19e, 0xa17f, 0xc19e, 0x21, 0 + .dw 0xa1c0, 0xc19e, 0xa1ff, 0xc19e, 0x21, 0 + .dw 0xa240, 0xc19e, 0xa27f, 0xc19e, 0x21, 0 + .dw 0xa2c0, 0xc19e, 0xa2ff, 0xc19e, 0x21, 0 + .dw 0xa340, 0xc19e, 0xa37f, 0xc19e, 0x21, 0 + .dw 0xa3c0, 0xc19e, 0xa3ff, 0xc19e, 0x21, 0 + .dw 0xa440, 0xc19e, 0xa47f, 0xc19e, 0x21, 0 + .dw 0xa4c0, 0xc19e, 0xa4ff, 0xc19e, 0x21, 0 + .dw 0xa540, 0xc19e, 0xa57f, 0xc19e, 0x21, 0 + .dw 0xa5c0, 0xc19e, 0xa5ff, 0xc19e, 0x21, 0 + .dw 0xa640, 0xc19e, 0xa67f, 0xc19e, 0x21, 0 + .dw 0xa6c0, 0xc19e, 0xa6ff, 0xc19e, 0x21, 0 + .dw 0xa740, 0xc19e, 0xa77f, 0xc19e, 0x21, 0 + .dw 0xa7c0, 0xc19e, 0xa7ff, 0xc19e, 0x21, 0 + .dw 0xa840, 0xc19e, 0xa87f, 0xc19e, 0x21, 0 + .dw 0xa8c0, 0xc19e, 0xa8ff, 0xc19e, 0x21, 0 + .dw 0xa940, 0xc19e, 0xa97f, 0xc19e, 0x21, 0 + .dw 0xa9c0, 0xc19e, 0xa9ff, 0xc19e, 0x21, 0 + .dw 0xaa40, 0xc19e, 0xaa7f, 0xc19e, 0x21, 0 + .dw 0xaac0, 0xc19e, 0xaaff, 0xc19e, 0x21, 0 + .dw 0xab40, 0xc19e, 0xab7f, 0xc19e, 0x21, 0 + .dw 0xabc0, 0xc19e, 0xabff, 0xc19e, 0x21, 0 + .dw 0xac40, 0xc19e, 0xac7f, 0xc19e, 0x21, 0 + .dw 0xacc0, 0xc19e, 0xacff, 0xc19e, 0x21, 0 + .dw 0xad40, 0xc19e, 0xad7f, 0xc19e, 0x21, 0 + .dw 0xadc0, 0xc19e, 0xadff, 0xc19e, 0x21, 0 + .dw 0xae40, 0xc19e, 0xae7f, 0xc19e, 0x21, 0 + .dw 0xaec0, 0xc19e, 0xaeff, 0xc19e, 0x21, 0 + .dw 0xaf40, 0xc19e, 0xaf7f, 0xc19e, 0x21, 0 + .dw 0xafc0, 0xc19e, 0xafff, 0xc19e, 0x21, 0 + .dw 0xb040, 0xc19e, 0xb07f, 0xc19e, 0x21, 0 + .dw 0xb0c0, 0xc19e, 0xb0ff, 0xc19e, 0x21, 0 + .dw 0xb140, 0xc19e, 0xb17f, 0xc19e, 0x21, 0 + .dw 0xb1c0, 0xc19e, 0xb1ff, 0xc19e, 0x21, 0 + .dw 0xb240, 0xc19e, 0xb27f, 0xc19e, 0x21, 0 + .dw 0xb2c0, 0xc19e, 0xb2ff, 0xc19e, 0x21, 0 + .dw 0xb340, 0xc19e, 0xb37f, 0xc19e, 0x21, 0 + .dw 0xb3c0, 0xc19e, 0xb3ff, 0xc19e, 0x21, 0 + .dw 0xb440, 0xc19e, 0xb47f, 0xc19e, 0x21, 0 + .dw 0xb4c0, 0xc19e, 0xb4ff, 0xc19e, 0x21, 0 + .dw 0xb540, 0xc19e, 0xb57f, 0xc19e, 0x21, 0 + .dw 0xb5c0, 0xc19e, 0xb5ff, 0xc19e, 0x21, 0 + .dw 0xb640, 0xc19e, 0xb67f, 0xc19e, 0x21, 0 + .dw 0xb6c0, 0xc19e, 0xb6ff, 0xc19e, 0x21, 0 + .dw 0xb740, 0xc19e, 0xb77f, 0xc19e, 0x21, 0 + .dw 0xb7c0, 0xc19e, 0xb7ff, 0xc19e, 0x21, 0 + .dw 0xb840, 0xc19e, 0xb87f, 0xc19e, 0x21, 0 + .dw 0xb8c0, 0xc19e, 0xb8ff, 0xc19e, 0x21, 0 + .dw 0xb940, 0xc19e, 0xb97f, 0xc19e, 0x21, 0 + .dw 0xb9c0, 0xc19e, 0xbfff, 0xc19e, 0x21, 0 + .dw 0xc040, 0xc19e, 0xc07f, 0xc19e, 0x21, 0 + .dw 0xc0c0, 0xc19e, 0xc0ff, 0xc19e, 0x21, 0 + .dw 0xc140, 0xc19e, 0xc17f, 0xc19e, 0x21, 0 + .dw 0xc1c0, 0xc19e, 0xc1ff, 0xc19e, 0x21, 0 + .dw 0xc240, 0xc19e, 0xc27f, 0xc19e, 0x21, 0 + .dw 0xc2c0, 0xc19e, 0xc2ff, 0xc19e, 0x21, 0 + .dw 0xc340, 0xc19e, 0xc37f, 0xc19e, 0x21, 0 + .dw 0xc3c0, 0xc19e, 0xc3ff, 0xc19e, 0x21, 0 + .dw 0xc440, 0xc19e, 0xc47f, 0xc19e, 0x21, 0 + .dw 0xc4c0, 0xc19e, 0xc4ff, 0xc19e, 0x21, 0 + .dw 0xc540, 0xc19e, 0xc57f, 0xc19e, 0x21, 0 + .dw 0xc5c0, 0xc19e, 0xc5ff, 0xc19e, 0x21, 0 + .dw 0xc640, 0xc19e, 0xc67f, 0xc19e, 0x21, 0 + .dw 0xc6c0, 0xc19e, 0xc6ff, 0xc19e, 0x21, 0 + .dw 0xc740, 0xc19e, 0xc77f, 0xc19e, 0x21, 0 + .dw 0xc7c0, 0xc19e, 0xc7ff, 0xc19e, 0x21, 0 + .dw 0xc840, 0xc19e, 0xc87f, 0xc19e, 0x21, 0 + .dw 0xc8c0, 0xc19e, 0xc8ff, 0xc19e, 0x21, 0 + .dw 0xc940, 0xc19e, 0xc97f, 0xc19e, 0x21, 0 + .dw 0xc9c0, 0xc19e, 0xc9ff, 0xc19e, 0x21, 0 + .dw 0xca40, 0xc19e, 0xca7f, 0xc19e, 0x21, 0 + .dw 0xcac0, 0xc19e, 0xcaff, 0xc19e, 0x21, 0 + .dw 0xcb40, 0xc19e, 0xcb7f, 0xc19e, 0x21, 0 + .dw 0xcbc0, 0xc19e, 0xcbff, 0xc19e, 0x21, 0 + .dw 0xcc40, 0xc19e, 0xcc7f, 0xc19e, 0x21, 0 + .dw 0xccc0, 0xc19e, 0xccff, 0xc19e, 0x21, 0 + .dw 0xcd40, 0xc19e, 0xcd7f, 0xc19e, 0x21, 0 + .dw 0xcdc0, 0xc19e, 0xcdff, 0xc19e, 0x21, 0 + .dw 0xce40, 0xc19e, 0xce7f, 0xc19e, 0x21, 0 + .dw 0xcec0, 0xc19e, 0xceff, 0xc19e, 0x21, 0 + .dw 0xcf40, 0xc19e, 0xcf7f, 0xc19e, 0x21, 0 + .dw 0xcfc0, 0xc19e, 0xcfff, 0xc19e, 0x21, 0 + .dw 0xd040, 0xc19e, 0xd07f, 0xc19e, 0x21, 0 + .dw 0xd0c0, 0xc19e, 0xd0ff, 0xc19e, 0x21, 0 + .dw 0xd140, 0xc19e, 0xd17f, 0xc19e, 0x21, 0 + .dw 0xd1c0, 0xc19e, 0xd1ff, 0xc19e, 0x21, 0 + .dw 0xd240, 0xc19e, 0xd27f, 0xc19e, 0x21, 0 + .dw 0xd2c0, 0xc19e, 0xd2ff, 0xc19e, 0x21, 0 + .dw 0xd340, 0xc19e, 0xd37f, 0xc19e, 0x21, 0 + .dw 0xd3c0, 0xc19e, 0xd3ff, 0xc19e, 0x21, 0 + .dw 0xd440, 0xc19e, 0xd47f, 0xc19e, 0x21, 0 + .dw 0xd4c0, 0xc19e, 0xd4ff, 0xc19e, 0x21, 0 + .dw 0xd540, 0xc19e, 0xd57f, 0xc19e, 0x21, 0 + .dw 0xd5c0, 0xc19e, 0xd5ff, 0xc19e, 0x21, 0 + .dw 0xd640, 0xc19e, 0xd67f, 0xc19e, 0x21, 0 + .dw 0xd6c0, 0xc19e, 0xd6ff, 0xc19e, 0x21, 0 + .dw 0xd740, 0xc19e, 0xd77f, 0xc19e, 0x21, 0 + .dw 0xd7c0, 0xc19e, 0xd7ff, 0xc19e, 0x21, 0 + .dw 0xd840, 0xc19e, 0xd87f, 0xc19e, 0x21, 0 + .dw 0xd8c0, 0xc19e, 0xd8ff, 0xc19e, 0x21, 0 + .dw 0xd940, 0xc19e, 0xd97f, 0xc19e, 0x21, 0 + .dw 0xd9c0, 0xc19e, 0xdfff, 0xc19e, 0x21, 0 + .dw 0xe040, 0xc19e, 0xe07f, 0xc19e, 0x21, 0 + .dw 0xe0c0, 0xc19e, 0xe0ff, 0xc19e, 0x21, 0 + .dw 0xe140, 0xc19e, 0xe17f, 0xc19e, 0x21, 0 + .dw 0xe1c0, 0xc19e, 0xe1ff, 0xc19e, 0x21, 0 + .dw 0xe240, 0xc19e, 0xe27f, 0xc19e, 0x21, 0 + .dw 0xe2c0, 0xc19e, 0xe2ff, 0xc19e, 0x21, 0 + .dw 0xe340, 0xc19e, 0xe37f, 0xc19e, 0x21, 0 + .dw 0xe3c0, 0xc19e, 0xe3ff, 0xc19e, 0x21, 0 + .dw 0xe440, 0xc19e, 0xe47f, 0xc19e, 0x21, 0 + .dw 0xe4c0, 0xc19e, 0xe4ff, 0xc19e, 0x21, 0 + .dw 0xe540, 0xc19e, 0xe57f, 0xc19e, 0x21, 0 + .dw 0xe5c0, 0xc19e, 0xe5ff, 0xc19e, 0x21, 0 + .dw 0xe640, 0xc19e, 0xe67f, 0xc19e, 0x21, 0 + .dw 0xe6c0, 0xc19e, 0xe6ff, 0xc19e, 0x21, 0 + .dw 0xe740, 0xc19e, 0xe77f, 0xc19e, 0x21, 0 + .dw 0xe7c0, 0xc19e, 0xe7ff, 0xc19e, 0x21, 0 + .dw 0xe840, 0xc19e, 0xe87f, 0xc19e, 0x21, 0 + .dw 0xe8c0, 0xc19e, 0xe8ff, 0xc19e, 0x21, 0 + .dw 0xe940, 0xc19e, 0xe97f, 0xc19e, 0x21, 0 + .dw 0xe9c0, 0xc19e, 0xe9ff, 0xc19e, 0x21, 0 + .dw 0xea40, 0xc19e, 0xea7f, 0xc19e, 0x21, 0 + .dw 0xeac0, 0xc19e, 0xeaff, 0xc19e, 0x21, 0 + .dw 0xeb40, 0xc19e, 0xeb7f, 0xc19e, 0x21, 0 + .dw 0xebc0, 0xc19e, 0xebff, 0xc19e, 0x21, 0 + .dw 0xec40, 0xc19e, 0xec7f, 0xc19e, 0x21, 0 + .dw 0xecc0, 0xc19e, 0xecff, 0xc19e, 0x21, 0 + .dw 0xed40, 0xc19e, 0xed7f, 0xc19e, 0x21, 0 + .dw 0xedc0, 0xc19e, 0xedff, 0xc19e, 0x21, 0 + .dw 0xee40, 0xc19e, 0xee7f, 0xc19e, 0x21, 0 + .dw 0xeec0, 0xc19e, 0xeeff, 0xc19e, 0x21, 0 + .dw 0xef40, 0xc19e, 0xef7f, 0xc19e, 0x21, 0 + .dw 0xefc0, 0xc19e, 0xefff, 0xc19e, 0x21, 0 + .dw 0xf040, 0xc19e, 0xf07f, 0xc19e, 0x21, 0 + .dw 0xf0c0, 0xc19e, 0xf0ff, 0xc19e, 0x21, 0 + .dw 0xf140, 0xc19e, 0xf17f, 0xc19e, 0x21, 0 + .dw 0xf1c0, 0xc19e, 0xf1ff, 0xc19e, 0x21, 0 + .dw 0xf240, 0xc19e, 0xf27f, 0xc19e, 0x21, 0 + .dw 0xf2c0, 0xc19e, 0xf2ff, 0xc19e, 0x21, 0 + .dw 0xf340, 0xc19e, 0xf37f, 0xc19e, 0x21, 0 + .dw 0xf3c0, 0xc19e, 0xf3ff, 0xc19e, 0x21, 0 + .dw 0xf440, 0xc19e, 0xf47f, 0xc19e, 0x21, 0 + .dw 0xf4c0, 0xc19e, 0xf4ff, 0xc19e, 0x21, 0 + .dw 0xf540, 0xc19e, 0xf57f, 0xc19e, 0x21, 0 + .dw 0xf5c0, 0xc19e, 0xf5ff, 0xc19e, 0x21, 0 + .dw 0xf640, 0xc19e, 0xf67f, 0xc19e, 0x21, 0 + .dw 0xf6c0, 0xc19e, 0xf6ff, 0xc19e, 0x21, 0 + .dw 0xf740, 0xc19e, 0xf77f, 0xc19e, 0x21, 0 + .dw 0xf7c0, 0xc19e, 0xf7ff, 0xc19e, 0x21, 0 + .dw 0xf840, 0xc19e, 0xf87f, 0xc19e, 0x21, 0 + .dw 0xf8c0, 0xc19e, 0xf8ff, 0xc19e, 0x21, 0 + .dw 0xf940, 0xc19e, 0xf97f, 0xc19e, 0x21, 0 + .dw 0xf9c0, 0xc19e, 0xffff, 0xc19e, 0x21, 0 + .dw 0x0040, 0xc19f, 0x007f, 0xc19f, 0x21, 0 + .dw 0x00c0, 0xc19f, 0x00ff, 0xc19f, 0x21, 0 + .dw 0x0140, 0xc19f, 0x017f, 0xc19f, 0x21, 0 + .dw 0x01c0, 0xc19f, 0x01ff, 0xc19f, 0x21, 0 + .dw 0x0240, 0xc19f, 0x027f, 0xc19f, 0x21, 0 + .dw 0x02c0, 0xc19f, 0x02ff, 0xc19f, 0x21, 0 + .dw 0x0340, 0xc19f, 0x037f, 0xc19f, 0x21, 0 + .dw 0x03c0, 0xc19f, 0x03ff, 0xc19f, 0x21, 0 + .dw 0x0440, 0xc19f, 0x047f, 0xc19f, 0x21, 0 + .dw 0x04c0, 0xc19f, 0x04ff, 0xc19f, 0x21, 0 + .dw 0x0540, 0xc19f, 0x057f, 0xc19f, 0x21, 0 + .dw 0x05c0, 0xc19f, 0x05ff, 0xc19f, 0x21, 0 + .dw 0x0640, 0xc19f, 0x067f, 0xc19f, 0x21, 0 + .dw 0x06c0, 0xc19f, 0x06ff, 0xc19f, 0x21, 0 + .dw 0x0740, 0xc19f, 0x077f, 0xc19f, 0x21, 0 + .dw 0x07c0, 0xc19f, 0x07ff, 0xc19f, 0x21, 0 + .dw 0x0840, 0xc19f, 0x087f, 0xc19f, 0x21, 0 + .dw 0x08c0, 0xc19f, 0x08ff, 0xc19f, 0x21, 0 + .dw 0x0940, 0xc19f, 0x097f, 0xc19f, 0x21, 0 + .dw 0x09c0, 0xc19f, 0x09ff, 0xc19f, 0x21, 0 + .dw 0x0a40, 0xc19f, 0x0a7f, 0xc19f, 0x21, 0 + .dw 0x0ac0, 0xc19f, 0x0aff, 0xc19f, 0x21, 0 + .dw 0x0b40, 0xc19f, 0x0b7f, 0xc19f, 0x21, 0 + .dw 0x0bc0, 0xc19f, 0x0bff, 0xc19f, 0x21, 0 + .dw 0x0c40, 0xc19f, 0x0c7f, 0xc19f, 0x21, 0 + .dw 0x0cc0, 0xc19f, 0x0cff, 0xc19f, 0x21, 0 + .dw 0x0d40, 0xc19f, 0x0d7f, 0xc19f, 0x21, 0 + .dw 0x0dc0, 0xc19f, 0x0dff, 0xc19f, 0x21, 0 + .dw 0x0e40, 0xc19f, 0x0e7f, 0xc19f, 0x21, 0 + .dw 0x0ec0, 0xc19f, 0x0eff, 0xc19f, 0x21, 0 + .dw 0x0f40, 0xc19f, 0x0f7f, 0xc19f, 0x21, 0 + .dw 0x0fc0, 0xc19f, 0x0fff, 0xc19f, 0x21, 0 + .dw 0x1040, 0xc19f, 0x107f, 0xc19f, 0x21, 0 + .dw 0x10c0, 0xc19f, 0x10ff, 0xc19f, 0x21, 0 + .dw 0x1140, 0xc19f, 0x117f, 0xc19f, 0x21, 0 + .dw 0x11c0, 0xc19f, 0x11ff, 0xc19f, 0x21, 0 + .dw 0x1240, 0xc19f, 0x127f, 0xc19f, 0x21, 0 + .dw 0x12c0, 0xc19f, 0x12ff, 0xc19f, 0x21, 0 + .dw 0x1340, 0xc19f, 0x137f, 0xc19f, 0x21, 0 + .dw 0x13c0, 0xc19f, 0x13ff, 0xc19f, 0x21, 0 + .dw 0x1440, 0xc19f, 0x147f, 0xc19f, 0x21, 0 + .dw 0x14c0, 0xc19f, 0x14ff, 0xc19f, 0x21, 0 + .dw 0x1540, 0xc19f, 0x157f, 0xc19f, 0x21, 0 + .dw 0x15c0, 0xc19f, 0x15ff, 0xc19f, 0x21, 0 + .dw 0x1640, 0xc19f, 0x167f, 0xc19f, 0x21, 0 + .dw 0x16c0, 0xc19f, 0x16ff, 0xc19f, 0x21, 0 + .dw 0x1740, 0xc19f, 0x177f, 0xc19f, 0x21, 0 + .dw 0x17c0, 0xc19f, 0x17ff, 0xc19f, 0x21, 0 + .dw 0x1840, 0xc19f, 0x187f, 0xc19f, 0x21, 0 + .dw 0x18c0, 0xc19f, 0x18ff, 0xc19f, 0x21, 0 + .dw 0x1940, 0xc19f, 0x197f, 0xc19f, 0x21, 0 + .dw 0x19c0, 0xc19f, 0x1fff, 0xc19f, 0x21, 0 + .dw 0x2040, 0xc19f, 0x207f, 0xc19f, 0x21, 0 + .dw 0x20c0, 0xc19f, 0x20ff, 0xc19f, 0x21, 0 + .dw 0x2140, 0xc19f, 0x217f, 0xc19f, 0x21, 0 + .dw 0x21c0, 0xc19f, 0x21ff, 0xc19f, 0x21, 0 + .dw 0x2240, 0xc19f, 0x227f, 0xc19f, 0x21, 0 + .dw 0x22c0, 0xc19f, 0x22ff, 0xc19f, 0x21, 0 + .dw 0x2340, 0xc19f, 0x237f, 0xc19f, 0x21, 0 + .dw 0x23c0, 0xc19f, 0x23ff, 0xc19f, 0x21, 0 + .dw 0x2440, 0xc19f, 0x247f, 0xc19f, 0x21, 0 + .dw 0x24c0, 0xc19f, 0x24ff, 0xc19f, 0x21, 0 + .dw 0x2540, 0xc19f, 0x257f, 0xc19f, 0x21, 0 + .dw 0x25c0, 0xc19f, 0x25ff, 0xc19f, 0x21, 0 + .dw 0x2640, 0xc19f, 0x267f, 0xc19f, 0x21, 0 + .dw 0x26c0, 0xc19f, 0x26ff, 0xc19f, 0x21, 0 + .dw 0x2740, 0xc19f, 0x277f, 0xc19f, 0x21, 0 + .dw 0x27c0, 0xc19f, 0x27ff, 0xc19f, 0x21, 0 + .dw 0x2840, 0xc19f, 0x287f, 0xc19f, 0x21, 0 + .dw 0x28c0, 0xc19f, 0x28ff, 0xc19f, 0x21, 0 + .dw 0x2940, 0xc19f, 0x297f, 0xc19f, 0x21, 0 + .dw 0x29c0, 0xc19f, 0x29ff, 0xc19f, 0x21, 0 + .dw 0x2a40, 0xc19f, 0x2a7f, 0xc19f, 0x21, 0 + .dw 0x2ac0, 0xc19f, 0x2aff, 0xc19f, 0x21, 0 + .dw 0x2b40, 0xc19f, 0x2b7f, 0xc19f, 0x21, 0 + .dw 0x2bc0, 0xc19f, 0x2bff, 0xc19f, 0x21, 0 + .dw 0x2c40, 0xc19f, 0x2c7f, 0xc19f, 0x21, 0 + .dw 0x2cc0, 0xc19f, 0x2cff, 0xc19f, 0x21, 0 + .dw 0x2d40, 0xc19f, 0x2d7f, 0xc19f, 0x21, 0 + .dw 0x2dc0, 0xc19f, 0x2dff, 0xc19f, 0x21, 0 + .dw 0x2e40, 0xc19f, 0x2e7f, 0xc19f, 0x21, 0 + .dw 0x2ec0, 0xc19f, 0x2eff, 0xc19f, 0x21, 0 + .dw 0x2f40, 0xc19f, 0x2f7f, 0xc19f, 0x21, 0 + .dw 0x2fc0, 0xc19f, 0x2fff, 0xc19f, 0x21, 0 + .dw 0x3040, 0xc19f, 0x307f, 0xc19f, 0x21, 0 + .dw 0x30c0, 0xc19f, 0x30ff, 0xc19f, 0x21, 0 + .dw 0x3140, 0xc19f, 0x317f, 0xc19f, 0x21, 0 + .dw 0x31c0, 0xc19f, 0x31ff, 0xc19f, 0x21, 0 + .dw 0x3240, 0xc19f, 0x327f, 0xc19f, 0x21, 0 + .dw 0x32c0, 0xc19f, 0x32ff, 0xc19f, 0x21, 0 + .dw 0x3340, 0xc19f, 0x337f, 0xc19f, 0x21, 0 + .dw 0x33c0, 0xc19f, 0x33ff, 0xc19f, 0x21, 0 + .dw 0x3440, 0xc19f, 0x347f, 0xc19f, 0x21, 0 + .dw 0x34c0, 0xc19f, 0x34ff, 0xc19f, 0x21, 0 + .dw 0x3540, 0xc19f, 0x357f, 0xc19f, 0x21, 0 + .dw 0x35c0, 0xc19f, 0x35ff, 0xc19f, 0x21, 0 + .dw 0x3640, 0xc19f, 0x367f, 0xc19f, 0x21, 0 + .dw 0x36c0, 0xc19f, 0x36ff, 0xc19f, 0x21, 0 + .dw 0x3740, 0xc19f, 0x377f, 0xc19f, 0x21, 0 + .dw 0x37c0, 0xc19f, 0x37ff, 0xc19f, 0x21, 0 + .dw 0x3840, 0xc19f, 0x387f, 0xc19f, 0x21, 0 + .dw 0x38c0, 0xc19f, 0x38ff, 0xc19f, 0x21, 0 + .dw 0x3940, 0xc19f, 0x397f, 0xc19f, 0x21, 0 + .dw 0x39c0, 0xc19f, 0x1fff, 0xc200, 0x21, 0 + .dw 0x2800, 0xc200, 0xffff, 0xc203, 0x21, 0 + .dw 0x0200, 0xc204, 0x1fff, 0xc204, 0x21, 0 + .dw 0x2800, 0xc204, 0x3fff, 0xc204, 0x21, 0 + .dw 0x4200, 0xc204, 0x5fff, 0xc204, 0x21, 0 + .dw 0x6800, 0xc204, 0x7fff, 0xc204, 0x21, 0 + .dw 0x8200, 0xc204, 0x9fff, 0xc204, 0x21, 0 + .dw 0xa800, 0xc204, 0xbfff, 0xc204, 0x21, 0 + .dw 0xc200, 0xc204, 0xdfff, 0xc204, 0x21, 0 + .dw 0xe800, 0xc204, 0x1fff, 0xc208, 0x21, 0 + .dw 0x2040, 0xc208, 0x207f, 0xc208, 0x21, 0 + .dw 0x20c0, 0xc208, 0x20ff, 0xc208, 0x21, 0 + .dw 0x2140, 0xc208, 0x217f, 0xc208, 0x21, 0 + .dw 0x21c0, 0xc208, 0x21ff, 0xc208, 0x21, 0 + .dw 0x2240, 0xc208, 0x227f, 0xc208, 0x21, 0 + .dw 0x22c0, 0xc208, 0x22ff, 0xc208, 0x21, 0 + .dw 0x2340, 0xc208, 0x237f, 0xc208, 0x21, 0 + .dw 0x23c0, 0xc208, 0x23ff, 0xc208, 0x21, 0 + .dw 0x2440, 0xc208, 0x247f, 0xc208, 0x21, 0 + .dw 0x24c0, 0xc208, 0x24ff, 0xc208, 0x21, 0 + .dw 0x2540, 0xc208, 0x257f, 0xc208, 0x21, 0 + .dw 0x25c0, 0xc208, 0x25ff, 0xc208, 0x21, 0 + .dw 0x2640, 0xc208, 0x267f, 0xc208, 0x21, 0 + .dw 0x26c0, 0xc208, 0x26ff, 0xc208, 0x21, 0 + .dw 0x2740, 0xc208, 0x277f, 0xc208, 0x21, 0 + .dw 0x27c0, 0xc208, 0xffff, 0xc20b, 0x21, 0 + .dw 0x0040, 0xc20c, 0x007f, 0xc20c, 0x21, 0 + .dw 0x00c0, 0xc20c, 0x00ff, 0xc20c, 0x21, 0 + .dw 0x0140, 0xc20c, 0x017f, 0xc20c, 0x21, 0 + .dw 0x01c0, 0xc20c, 0x1fff, 0xc20c, 0x21, 0 + .dw 0x2040, 0xc20c, 0x207f, 0xc20c, 0x21, 0 + .dw 0x20c0, 0xc20c, 0x20ff, 0xc20c, 0x21, 0 + .dw 0x2140, 0xc20c, 0x217f, 0xc20c, 0x21, 0 + .dw 0x21c0, 0xc20c, 0x21ff, 0xc20c, 0x21, 0 + .dw 0x2240, 0xc20c, 0x227f, 0xc20c, 0x21, 0 + .dw 0x22c0, 0xc20c, 0x22ff, 0xc20c, 0x21, 0 + .dw 0x2340, 0xc20c, 0x237f, 0xc20c, 0x21, 0 + .dw 0x23c0, 0xc20c, 0x23ff, 0xc20c, 0x21, 0 + .dw 0x2440, 0xc20c, 0x247f, 0xc20c, 0x21, 0 + .dw 0x24c0, 0xc20c, 0x24ff, 0xc20c, 0x21, 0 + .dw 0x2540, 0xc20c, 0x257f, 0xc20c, 0x21, 0 + .dw 0x25c0, 0xc20c, 0x25ff, 0xc20c, 0x21, 0 + .dw 0x2640, 0xc20c, 0x267f, 0xc20c, 0x21, 0 + .dw 0x26c0, 0xc20c, 0x26ff, 0xc20c, 0x21, 0 + .dw 0x2740, 0xc20c, 0x277f, 0xc20c, 0x21, 0 + .dw 0x27c0, 0xc20c, 0x3fff, 0xc20c, 0x21, 0 + .dw 0x4040, 0xc20c, 0x407f, 0xc20c, 0x21, 0 + .dw 0x40c0, 0xc20c, 0x40ff, 0xc20c, 0x21, 0 + .dw 0x4140, 0xc20c, 0x417f, 0xc20c, 0x21, 0 + .dw 0x41c0, 0xc20c, 0x5fff, 0xc20c, 0x21, 0 + .dw 0x6040, 0xc20c, 0x607f, 0xc20c, 0x21, 0 + .dw 0x60c0, 0xc20c, 0x60ff, 0xc20c, 0x21, 0 + .dw 0x6140, 0xc20c, 0x617f, 0xc20c, 0x21, 0 + .dw 0x61c0, 0xc20c, 0x61ff, 0xc20c, 0x21, 0 + .dw 0x6240, 0xc20c, 0x627f, 0xc20c, 0x21, 0 + .dw 0x62c0, 0xc20c, 0x62ff, 0xc20c, 0x21, 0 + .dw 0x6340, 0xc20c, 0x637f, 0xc20c, 0x21, 0 + .dw 0x63c0, 0xc20c, 0x63ff, 0xc20c, 0x21, 0 + .dw 0x6440, 0xc20c, 0x647f, 0xc20c, 0x21, 0 + .dw 0x64c0, 0xc20c, 0x64ff, 0xc20c, 0x21, 0 + .dw 0x6540, 0xc20c, 0x657f, 0xc20c, 0x21, 0 + .dw 0x65c0, 0xc20c, 0x65ff, 0xc20c, 0x21, 0 + .dw 0x6640, 0xc20c, 0x667f, 0xc20c, 0x21, 0 + .dw 0x66c0, 0xc20c, 0x66ff, 0xc20c, 0x21, 0 + .dw 0x6740, 0xc20c, 0x677f, 0xc20c, 0x21, 0 + .dw 0x67c0, 0xc20c, 0x7fff, 0xc20c, 0x21, 0 + .dw 0x8040, 0xc20c, 0x807f, 0xc20c, 0x21, 0 + .dw 0x80c0, 0xc20c, 0x80ff, 0xc20c, 0x21, 0 + .dw 0x8140, 0xc20c, 0x817f, 0xc20c, 0x21, 0 + .dw 0x81c0, 0xc20c, 0x9fff, 0xc20c, 0x21, 0 + .dw 0xa040, 0xc20c, 0xa07f, 0xc20c, 0x21, 0 + .dw 0xa0c0, 0xc20c, 0xa0ff, 0xc20c, 0x21, 0 + .dw 0xa140, 0xc20c, 0xa17f, 0xc20c, 0x21, 0 + .dw 0xa1c0, 0xc20c, 0xa1ff, 0xc20c, 0x21, 0 + .dw 0xa240, 0xc20c, 0xa27f, 0xc20c, 0x21, 0 + .dw 0xa2c0, 0xc20c, 0xa2ff, 0xc20c, 0x21, 0 + .dw 0xa340, 0xc20c, 0xa37f, 0xc20c, 0x21, 0 + .dw 0xa3c0, 0xc20c, 0xa3ff, 0xc20c, 0x21, 0 + .dw 0xa440, 0xc20c, 0xa47f, 0xc20c, 0x21, 0 + .dw 0xa4c0, 0xc20c, 0xa4ff, 0xc20c, 0x21, 0 + .dw 0xa540, 0xc20c, 0xa57f, 0xc20c, 0x21, 0 + .dw 0xa5c0, 0xc20c, 0xa5ff, 0xc20c, 0x21, 0 + .dw 0xa640, 0xc20c, 0xa67f, 0xc20c, 0x21, 0 + .dw 0xa6c0, 0xc20c, 0xa6ff, 0xc20c, 0x21, 0 + .dw 0xa740, 0xc20c, 0xa77f, 0xc20c, 0x21, 0 + .dw 0xa7c0, 0xc20c, 0xbfff, 0xc20c, 0x21, 0 + .dw 0xc040, 0xc20c, 0xc07f, 0xc20c, 0x21, 0 + .dw 0xc0c0, 0xc20c, 0xc0ff, 0xc20c, 0x21, 0 + .dw 0xc140, 0xc20c, 0xc17f, 0xc20c, 0x21, 0 + .dw 0xc1c0, 0xc20c, 0xdfff, 0xc20c, 0x21, 0 + .dw 0xe040, 0xc20c, 0xe07f, 0xc20c, 0x21, 0 + .dw 0xe0c0, 0xc20c, 0xe0ff, 0xc20c, 0x21, 0 + .dw 0xe140, 0xc20c, 0xe17f, 0xc20c, 0x21, 0 + .dw 0xe1c0, 0xc20c, 0xe1ff, 0xc20c, 0x21, 0 + .dw 0xe240, 0xc20c, 0xe27f, 0xc20c, 0x21, 0 + .dw 0xe2c0, 0xc20c, 0xe2ff, 0xc20c, 0x21, 0 + .dw 0xe340, 0xc20c, 0xe37f, 0xc20c, 0x21, 0 + .dw 0xe3c0, 0xc20c, 0xe3ff, 0xc20c, 0x21, 0 + .dw 0xe440, 0xc20c, 0xe47f, 0xc20c, 0x21, 0 + .dw 0xe4c0, 0xc20c, 0xe4ff, 0xc20c, 0x21, 0 + .dw 0xe540, 0xc20c, 0xe57f, 0xc20c, 0x21, 0 + .dw 0xe5c0, 0xc20c, 0xe5ff, 0xc20c, 0x21, 0 + .dw 0xe640, 0xc20c, 0xe67f, 0xc20c, 0x21, 0 + .dw 0xe6c0, 0xc20c, 0xe6ff, 0xc20c, 0x21, 0 + .dw 0xe740, 0xc20c, 0xe77f, 0xc20c, 0x21, 0 + .dw 0xe7c0, 0xc20c, 0xffff, 0xc213, 0x21, 0 + .dw 0x0200, 0xc214, 0x1fff, 0xc214, 0x21, 0 + .dw 0x2800, 0xc214, 0x3fff, 0xc214, 0x21, 0 + .dw 0x4200, 0xc214, 0x5fff, 0xc214, 0x21, 0 + .dw 0x6800, 0xc214, 0x7fff, 0xc214, 0x21, 0 + .dw 0x8200, 0xc214, 0x9fff, 0xc214, 0x21, 0 + .dw 0xa800, 0xc214, 0xbfff, 0xc214, 0x21, 0 + .dw 0xc200, 0xc214, 0xdfff, 0xc214, 0x21, 0 + .dw 0xe800, 0xc214, 0xffff, 0xc21b, 0x21, 0 + .dw 0x0040, 0xc21c, 0x007f, 0xc21c, 0x21, 0 + .dw 0x00c0, 0xc21c, 0x00ff, 0xc21c, 0x21, 0 + .dw 0x0140, 0xc21c, 0x017f, 0xc21c, 0x21, 0 + .dw 0x01c0, 0xc21c, 0x1fff, 0xc21c, 0x21, 0 + .dw 0x2040, 0xc21c, 0x207f, 0xc21c, 0x21, 0 + .dw 0x20c0, 0xc21c, 0x20ff, 0xc21c, 0x21, 0 + .dw 0x2140, 0xc21c, 0x217f, 0xc21c, 0x21, 0 + .dw 0x21c0, 0xc21c, 0x21ff, 0xc21c, 0x21, 0 + .dw 0x2240, 0xc21c, 0x227f, 0xc21c, 0x21, 0 + .dw 0x22c0, 0xc21c, 0x22ff, 0xc21c, 0x21, 0 + .dw 0x2340, 0xc21c, 0x237f, 0xc21c, 0x21, 0 + .dw 0x23c0, 0xc21c, 0x23ff, 0xc21c, 0x21, 0 + .dw 0x2440, 0xc21c, 0x247f, 0xc21c, 0x21, 0 + .dw 0x24c0, 0xc21c, 0x24ff, 0xc21c, 0x21, 0 + .dw 0x2540, 0xc21c, 0x257f, 0xc21c, 0x21, 0 + .dw 0x25c0, 0xc21c, 0x25ff, 0xc21c, 0x21, 0 + .dw 0x2640, 0xc21c, 0x267f, 0xc21c, 0x21, 0 + .dw 0x26c0, 0xc21c, 0x26ff, 0xc21c, 0x21, 0 + .dw 0x2740, 0xc21c, 0x277f, 0xc21c, 0x21, 0 + .dw 0x27c0, 0xc21c, 0x3fff, 0xc21c, 0x21, 0 + .dw 0x4040, 0xc21c, 0x407f, 0xc21c, 0x21, 0 + .dw 0x40c0, 0xc21c, 0x40ff, 0xc21c, 0x21, 0 + .dw 0x4140, 0xc21c, 0x417f, 0xc21c, 0x21, 0 + .dw 0x41c0, 0xc21c, 0x5fff, 0xc21c, 0x21, 0 + .dw 0x6040, 0xc21c, 0x607f, 0xc21c, 0x21, 0 + .dw 0x60c0, 0xc21c, 0x60ff, 0xc21c, 0x21, 0 + .dw 0x6140, 0xc21c, 0x617f, 0xc21c, 0x21, 0 + .dw 0x61c0, 0xc21c, 0x61ff, 0xc21c, 0x21, 0 + .dw 0x6240, 0xc21c, 0x627f, 0xc21c, 0x21, 0 + .dw 0x62c0, 0xc21c, 0x62ff, 0xc21c, 0x21, 0 + .dw 0x6340, 0xc21c, 0x637f, 0xc21c, 0x21, 0 + .dw 0x63c0, 0xc21c, 0x63ff, 0xc21c, 0x21, 0 + .dw 0x6440, 0xc21c, 0x647f, 0xc21c, 0x21, 0 + .dw 0x64c0, 0xc21c, 0x64ff, 0xc21c, 0x21, 0 + .dw 0x6540, 0xc21c, 0x657f, 0xc21c, 0x21, 0 + .dw 0x65c0, 0xc21c, 0x65ff, 0xc21c, 0x21, 0 + .dw 0x6640, 0xc21c, 0x667f, 0xc21c, 0x21, 0 + .dw 0x66c0, 0xc21c, 0x66ff, 0xc21c, 0x21, 0 + .dw 0x6740, 0xc21c, 0x677f, 0xc21c, 0x21, 0 + .dw 0x67c0, 0xc21c, 0x7fff, 0xc21c, 0x21, 0 + .dw 0x8040, 0xc21c, 0x807f, 0xc21c, 0x21, 0 + .dw 0x80c0, 0xc21c, 0x80ff, 0xc21c, 0x21, 0 + .dw 0x8140, 0xc21c, 0x817f, 0xc21c, 0x21, 0 + .dw 0x81c0, 0xc21c, 0x9fff, 0xc21c, 0x21, 0 + .dw 0xa040, 0xc21c, 0xa07f, 0xc21c, 0x21, 0 + .dw 0xa0c0, 0xc21c, 0xa0ff, 0xc21c, 0x21, 0 + .dw 0xa140, 0xc21c, 0xa17f, 0xc21c, 0x21, 0 + .dw 0xa1c0, 0xc21c, 0xa1ff, 0xc21c, 0x21, 0 + .dw 0xa240, 0xc21c, 0xa27f, 0xc21c, 0x21, 0 + .dw 0xa2c0, 0xc21c, 0xa2ff, 0xc21c, 0x21, 0 + .dw 0xa340, 0xc21c, 0xa37f, 0xc21c, 0x21, 0 + .dw 0xa3c0, 0xc21c, 0xa3ff, 0xc21c, 0x21, 0 + .dw 0xa440, 0xc21c, 0xa47f, 0xc21c, 0x21, 0 + .dw 0xa4c0, 0xc21c, 0xa4ff, 0xc21c, 0x21, 0 + .dw 0xa540, 0xc21c, 0xa57f, 0xc21c, 0x21, 0 + .dw 0xa5c0, 0xc21c, 0xa5ff, 0xc21c, 0x21, 0 + .dw 0xa640, 0xc21c, 0xa67f, 0xc21c, 0x21, 0 + .dw 0xa6c0, 0xc21c, 0xa6ff, 0xc21c, 0x21, 0 + .dw 0xa740, 0xc21c, 0xa77f, 0xc21c, 0x21, 0 + .dw 0xa7c0, 0xc21c, 0xbfff, 0xc21c, 0x21, 0 + .dw 0xc040, 0xc21c, 0xc07f, 0xc21c, 0x21, 0 + .dw 0xc0c0, 0xc21c, 0xc0ff, 0xc21c, 0x21, 0 + .dw 0xc140, 0xc21c, 0xc17f, 0xc21c, 0x21, 0 + .dw 0xc1c0, 0xc21c, 0xdfff, 0xc21c, 0x21, 0 + .dw 0xe040, 0xc21c, 0xe07f, 0xc21c, 0x21, 0 + .dw 0xe0c0, 0xc21c, 0xe0ff, 0xc21c, 0x21, 0 + .dw 0xe140, 0xc21c, 0xe17f, 0xc21c, 0x21, 0 + .dw 0xe1c0, 0xc21c, 0xe1ff, 0xc21c, 0x21, 0 + .dw 0xe240, 0xc21c, 0xe27f, 0xc21c, 0x21, 0 + .dw 0xe2c0, 0xc21c, 0xe2ff, 0xc21c, 0x21, 0 + .dw 0xe340, 0xc21c, 0xe37f, 0xc21c, 0x21, 0 + .dw 0xe3c0, 0xc21c, 0xe3ff, 0xc21c, 0x21, 0 + .dw 0xe440, 0xc21c, 0xe47f, 0xc21c, 0x21, 0 + .dw 0xe4c0, 0xc21c, 0xe4ff, 0xc21c, 0x21, 0 + .dw 0xe540, 0xc21c, 0xe57f, 0xc21c, 0x21, 0 + .dw 0xe5c0, 0xc21c, 0xe5ff, 0xc21c, 0x21, 0 + .dw 0xe640, 0xc21c, 0xe67f, 0xc21c, 0x21, 0 + .dw 0xe6c0, 0xc21c, 0xe6ff, 0xc21c, 0x21, 0 + .dw 0xe740, 0xc21c, 0xe77f, 0xc21c, 0x21, 0 + .dw 0xe7c0, 0xc21c, 0x1fff, 0xc220, 0x21, 0 + .dw 0x2800, 0xc220, 0xffff, 0xc223, 0x21, 0 + .dw 0x0200, 0xc224, 0x1fff, 0xc224, 0x21, 0 + .dw 0x2800, 0xc224, 0x3fff, 0xc224, 0x21, 0 + .dw 0x4200, 0xc224, 0x5fff, 0xc224, 0x21, 0 + .dw 0x6800, 0xc224, 0x7fff, 0xc224, 0x21, 0 + .dw 0x8200, 0xc224, 0x9fff, 0xc224, 0x21, 0 + .dw 0xa800, 0xc224, 0xbfff, 0xc224, 0x21, 0 + .dw 0xc200, 0xc224, 0xdfff, 0xc224, 0x21, 0 + .dw 0xe800, 0xc224, 0x1fff, 0xc228, 0x21, 0 + .dw 0x2040, 0xc228, 0x207f, 0xc228, 0x21, 0 + .dw 0x20c0, 0xc228, 0x20ff, 0xc228, 0x21, 0 + .dw 0x2140, 0xc228, 0x217f, 0xc228, 0x21, 0 + .dw 0x21c0, 0xc228, 0x21ff, 0xc228, 0x21, 0 + .dw 0x2240, 0xc228, 0x227f, 0xc228, 0x21, 0 + .dw 0x22c0, 0xc228, 0x22ff, 0xc228, 0x21, 0 + .dw 0x2340, 0xc228, 0x237f, 0xc228, 0x21, 0 + .dw 0x23c0, 0xc228, 0x23ff, 0xc228, 0x21, 0 + .dw 0x2440, 0xc228, 0x247f, 0xc228, 0x21, 0 + .dw 0x24c0, 0xc228, 0x24ff, 0xc228, 0x21, 0 + .dw 0x2540, 0xc228, 0x257f, 0xc228, 0x21, 0 + .dw 0x25c0, 0xc228, 0x25ff, 0xc228, 0x21, 0 + .dw 0x2640, 0xc228, 0x267f, 0xc228, 0x21, 0 + .dw 0x26c0, 0xc228, 0x26ff, 0xc228, 0x21, 0 + .dw 0x2740, 0xc228, 0x277f, 0xc228, 0x21, 0 + .dw 0x27c0, 0xc228, 0xffff, 0xc22b, 0x21, 0 + .dw 0x0040, 0xc22c, 0x007f, 0xc22c, 0x21, 0 + .dw 0x00c0, 0xc22c, 0x00ff, 0xc22c, 0x21, 0 + .dw 0x0140, 0xc22c, 0x017f, 0xc22c, 0x21, 0 + .dw 0x01c0, 0xc22c, 0x1fff, 0xc22c, 0x21, 0 + .dw 0x2040, 0xc22c, 0x207f, 0xc22c, 0x21, 0 + .dw 0x20c0, 0xc22c, 0x20ff, 0xc22c, 0x21, 0 + .dw 0x2140, 0xc22c, 0x217f, 0xc22c, 0x21, 0 + .dw 0x21c0, 0xc22c, 0x21ff, 0xc22c, 0x21, 0 + .dw 0x2240, 0xc22c, 0x227f, 0xc22c, 0x21, 0 + .dw 0x22c0, 0xc22c, 0x22ff, 0xc22c, 0x21, 0 + .dw 0x2340, 0xc22c, 0x237f, 0xc22c, 0x21, 0 + .dw 0x23c0, 0xc22c, 0x23ff, 0xc22c, 0x21, 0 + .dw 0x2440, 0xc22c, 0x247f, 0xc22c, 0x21, 0 + .dw 0x24c0, 0xc22c, 0x24ff, 0xc22c, 0x21, 0 + .dw 0x2540, 0xc22c, 0x257f, 0xc22c, 0x21, 0 + .dw 0x25c0, 0xc22c, 0x25ff, 0xc22c, 0x21, 0 + .dw 0x2640, 0xc22c, 0x267f, 0xc22c, 0x21, 0 + .dw 0x26c0, 0xc22c, 0x26ff, 0xc22c, 0x21, 0 + .dw 0x2740, 0xc22c, 0x277f, 0xc22c, 0x21, 0 + .dw 0x27c0, 0xc22c, 0x3fff, 0xc22c, 0x21, 0 + .dw 0x4040, 0xc22c, 0x407f, 0xc22c, 0x21, 0 + .dw 0x40c0, 0xc22c, 0x40ff, 0xc22c, 0x21, 0 + .dw 0x4140, 0xc22c, 0x417f, 0xc22c, 0x21, 0 + .dw 0x41c0, 0xc22c, 0x5fff, 0xc22c, 0x21, 0 + .dw 0x6040, 0xc22c, 0x607f, 0xc22c, 0x21, 0 + .dw 0x60c0, 0xc22c, 0x60ff, 0xc22c, 0x21, 0 + .dw 0x6140, 0xc22c, 0x617f, 0xc22c, 0x21, 0 + .dw 0x61c0, 0xc22c, 0x61ff, 0xc22c, 0x21, 0 + .dw 0x6240, 0xc22c, 0x627f, 0xc22c, 0x21, 0 + .dw 0x62c0, 0xc22c, 0x62ff, 0xc22c, 0x21, 0 + .dw 0x6340, 0xc22c, 0x637f, 0xc22c, 0x21, 0 + .dw 0x63c0, 0xc22c, 0x63ff, 0xc22c, 0x21, 0 + .dw 0x6440, 0xc22c, 0x647f, 0xc22c, 0x21, 0 + .dw 0x64c0, 0xc22c, 0x64ff, 0xc22c, 0x21, 0 + .dw 0x6540, 0xc22c, 0x657f, 0xc22c, 0x21, 0 + .dw 0x65c0, 0xc22c, 0x65ff, 0xc22c, 0x21, 0 + .dw 0x6640, 0xc22c, 0x667f, 0xc22c, 0x21, 0 + .dw 0x66c0, 0xc22c, 0x66ff, 0xc22c, 0x21, 0 + .dw 0x6740, 0xc22c, 0x677f, 0xc22c, 0x21, 0 + .dw 0x67c0, 0xc22c, 0x7fff, 0xc22c, 0x21, 0 + .dw 0x8040, 0xc22c, 0x807f, 0xc22c, 0x21, 0 + .dw 0x80c0, 0xc22c, 0x80ff, 0xc22c, 0x21, 0 + .dw 0x8140, 0xc22c, 0x817f, 0xc22c, 0x21, 0 + .dw 0x81c0, 0xc22c, 0x9fff, 0xc22c, 0x21, 0 + .dw 0xa040, 0xc22c, 0xa07f, 0xc22c, 0x21, 0 + .dw 0xa0c0, 0xc22c, 0xa0ff, 0xc22c, 0x21, 0 + .dw 0xa140, 0xc22c, 0xa17f, 0xc22c, 0x21, 0 + .dw 0xa1c0, 0xc22c, 0xa1ff, 0xc22c, 0x21, 0 + .dw 0xa240, 0xc22c, 0xa27f, 0xc22c, 0x21, 0 + .dw 0xa2c0, 0xc22c, 0xa2ff, 0xc22c, 0x21, 0 + .dw 0xa340, 0xc22c, 0xa37f, 0xc22c, 0x21, 0 + .dw 0xa3c0, 0xc22c, 0xa3ff, 0xc22c, 0x21, 0 + .dw 0xa440, 0xc22c, 0xa47f, 0xc22c, 0x21, 0 + .dw 0xa4c0, 0xc22c, 0xa4ff, 0xc22c, 0x21, 0 + .dw 0xa540, 0xc22c, 0xa57f, 0xc22c, 0x21, 0 + .dw 0xa5c0, 0xc22c, 0xa5ff, 0xc22c, 0x21, 0 + .dw 0xa640, 0xc22c, 0xa67f, 0xc22c, 0x21, 0 + .dw 0xa6c0, 0xc22c, 0xa6ff, 0xc22c, 0x21, 0 + .dw 0xa740, 0xc22c, 0xa77f, 0xc22c, 0x21, 0 + .dw 0xa7c0, 0xc22c, 0xbfff, 0xc22c, 0x21, 0 + .dw 0xc040, 0xc22c, 0xc07f, 0xc22c, 0x21, 0 + .dw 0xc0c0, 0xc22c, 0xc0ff, 0xc22c, 0x21, 0 + .dw 0xc140, 0xc22c, 0xc17f, 0xc22c, 0x21, 0 + .dw 0xc1c0, 0xc22c, 0xdfff, 0xc22c, 0x21, 0 + .dw 0xe040, 0xc22c, 0xe07f, 0xc22c, 0x21, 0 + .dw 0xe0c0, 0xc22c, 0xe0ff, 0xc22c, 0x21, 0 + .dw 0xe140, 0xc22c, 0xe17f, 0xc22c, 0x21, 0 + .dw 0xe1c0, 0xc22c, 0xe1ff, 0xc22c, 0x21, 0 + .dw 0xe240, 0xc22c, 0xe27f, 0xc22c, 0x21, 0 + .dw 0xe2c0, 0xc22c, 0xe2ff, 0xc22c, 0x21, 0 + .dw 0xe340, 0xc22c, 0xe37f, 0xc22c, 0x21, 0 + .dw 0xe3c0, 0xc22c, 0xe3ff, 0xc22c, 0x21, 0 + .dw 0xe440, 0xc22c, 0xe47f, 0xc22c, 0x21, 0 + .dw 0xe4c0, 0xc22c, 0xe4ff, 0xc22c, 0x21, 0 + .dw 0xe540, 0xc22c, 0xe57f, 0xc22c, 0x21, 0 + .dw 0xe5c0, 0xc22c, 0xe5ff, 0xc22c, 0x21, 0 + .dw 0xe640, 0xc22c, 0xe67f, 0xc22c, 0x21, 0 + .dw 0xe6c0, 0xc22c, 0xe6ff, 0xc22c, 0x21, 0 + .dw 0xe740, 0xc22c, 0xe77f, 0xc22c, 0x21, 0 + .dw 0xe7c0, 0xc22c, 0xffff, 0xc233, 0x21, 0 + .dw 0x0200, 0xc234, 0x1fff, 0xc234, 0x21, 0 + .dw 0x2800, 0xc234, 0x3fff, 0xc234, 0x21, 0 + .dw 0x4200, 0xc234, 0x5fff, 0xc234, 0x21, 0 + .dw 0x6800, 0xc234, 0x7fff, 0xc234, 0x21, 0 + .dw 0x8200, 0xc234, 0x9fff, 0xc234, 0x21, 0 + .dw 0xa800, 0xc234, 0xbfff, 0xc234, 0x21, 0 + .dw 0xc200, 0xc234, 0xdfff, 0xc234, 0x21, 0 + .dw 0xe800, 0xc234, 0xffff, 0xc23b, 0x21, 0 + .dw 0x0040, 0xc23c, 0x007f, 0xc23c, 0x21, 0 + .dw 0x00c0, 0xc23c, 0x00ff, 0xc23c, 0x21, 0 + .dw 0x0140, 0xc23c, 0x017f, 0xc23c, 0x21, 0 + .dw 0x01c0, 0xc23c, 0x1fff, 0xc23c, 0x21, 0 + .dw 0x2040, 0xc23c, 0x207f, 0xc23c, 0x21, 0 + .dw 0x20c0, 0xc23c, 0x20ff, 0xc23c, 0x21, 0 + .dw 0x2140, 0xc23c, 0x217f, 0xc23c, 0x21, 0 + .dw 0x21c0, 0xc23c, 0x21ff, 0xc23c, 0x21, 0 + .dw 0x2240, 0xc23c, 0x227f, 0xc23c, 0x21, 0 + .dw 0x22c0, 0xc23c, 0x22ff, 0xc23c, 0x21, 0 + .dw 0x2340, 0xc23c, 0x237f, 0xc23c, 0x21, 0 + .dw 0x23c0, 0xc23c, 0x23ff, 0xc23c, 0x21, 0 + .dw 0x2440, 0xc23c, 0x247f, 0xc23c, 0x21, 0 + .dw 0x24c0, 0xc23c, 0x24ff, 0xc23c, 0x21, 0 + .dw 0x2540, 0xc23c, 0x257f, 0xc23c, 0x21, 0 + .dw 0x25c0, 0xc23c, 0x25ff, 0xc23c, 0x21, 0 + .dw 0x2640, 0xc23c, 0x267f, 0xc23c, 0x21, 0 + .dw 0x26c0, 0xc23c, 0x26ff, 0xc23c, 0x21, 0 + .dw 0x2740, 0xc23c, 0x277f, 0xc23c, 0x21, 0 + .dw 0x27c0, 0xc23c, 0x3fff, 0xc23c, 0x21, 0 + .dw 0x4040, 0xc23c, 0x407f, 0xc23c, 0x21, 0 + .dw 0x40c0, 0xc23c, 0x40ff, 0xc23c, 0x21, 0 + .dw 0x4140, 0xc23c, 0x417f, 0xc23c, 0x21, 0 + .dw 0x41c0, 0xc23c, 0x5fff, 0xc23c, 0x21, 0 + .dw 0x6040, 0xc23c, 0x607f, 0xc23c, 0x21, 0 + .dw 0x60c0, 0xc23c, 0x60ff, 0xc23c, 0x21, 0 + .dw 0x6140, 0xc23c, 0x617f, 0xc23c, 0x21, 0 + .dw 0x61c0, 0xc23c, 0x61ff, 0xc23c, 0x21, 0 + .dw 0x6240, 0xc23c, 0x627f, 0xc23c, 0x21, 0 + .dw 0x62c0, 0xc23c, 0x62ff, 0xc23c, 0x21, 0 + .dw 0x6340, 0xc23c, 0x637f, 0xc23c, 0x21, 0 + .dw 0x63c0, 0xc23c, 0x63ff, 0xc23c, 0x21, 0 + .dw 0x6440, 0xc23c, 0x647f, 0xc23c, 0x21, 0 + .dw 0x64c0, 0xc23c, 0x64ff, 0xc23c, 0x21, 0 + .dw 0x6540, 0xc23c, 0x657f, 0xc23c, 0x21, 0 + .dw 0x65c0, 0xc23c, 0x65ff, 0xc23c, 0x21, 0 + .dw 0x6640, 0xc23c, 0x667f, 0xc23c, 0x21, 0 + .dw 0x66c0, 0xc23c, 0x66ff, 0xc23c, 0x21, 0 + .dw 0x6740, 0xc23c, 0x677f, 0xc23c, 0x21, 0 + .dw 0x67c0, 0xc23c, 0x7fff, 0xc23c, 0x21, 0 + .dw 0x8040, 0xc23c, 0x807f, 0xc23c, 0x21, 0 + .dw 0x80c0, 0xc23c, 0x80ff, 0xc23c, 0x21, 0 + .dw 0x8140, 0xc23c, 0x817f, 0xc23c, 0x21, 0 + .dw 0x81c0, 0xc23c, 0x9fff, 0xc23c, 0x21, 0 + .dw 0xa040, 0xc23c, 0xa07f, 0xc23c, 0x21, 0 + .dw 0xa0c0, 0xc23c, 0xa0ff, 0xc23c, 0x21, 0 + .dw 0xa140, 0xc23c, 0xa17f, 0xc23c, 0x21, 0 + .dw 0xa1c0, 0xc23c, 0xa1ff, 0xc23c, 0x21, 0 + .dw 0xa240, 0xc23c, 0xa27f, 0xc23c, 0x21, 0 + .dw 0xa2c0, 0xc23c, 0xa2ff, 0xc23c, 0x21, 0 + .dw 0xa340, 0xc23c, 0xa37f, 0xc23c, 0x21, 0 + .dw 0xa3c0, 0xc23c, 0xa3ff, 0xc23c, 0x21, 0 + .dw 0xa440, 0xc23c, 0xa47f, 0xc23c, 0x21, 0 + .dw 0xa4c0, 0xc23c, 0xa4ff, 0xc23c, 0x21, 0 + .dw 0xa540, 0xc23c, 0xa57f, 0xc23c, 0x21, 0 + .dw 0xa5c0, 0xc23c, 0xa5ff, 0xc23c, 0x21, 0 + .dw 0xa640, 0xc23c, 0xa67f, 0xc23c, 0x21, 0 + .dw 0xa6c0, 0xc23c, 0xa6ff, 0xc23c, 0x21, 0 + .dw 0xa740, 0xc23c, 0xa77f, 0xc23c, 0x21, 0 + .dw 0xa7c0, 0xc23c, 0xbfff, 0xc23c, 0x21, 0 + .dw 0xc040, 0xc23c, 0xc07f, 0xc23c, 0x21, 0 + .dw 0xc0c0, 0xc23c, 0xc0ff, 0xc23c, 0x21, 0 + .dw 0xc140, 0xc23c, 0xc17f, 0xc23c, 0x21, 0 + .dw 0xc1c0, 0xc23c, 0xdfff, 0xc23c, 0x21, 0 + .dw 0xe040, 0xc23c, 0xe07f, 0xc23c, 0x21, 0 + .dw 0xe0c0, 0xc23c, 0xe0ff, 0xc23c, 0x21, 0 + .dw 0xe140, 0xc23c, 0xe17f, 0xc23c, 0x21, 0 + .dw 0xe1c0, 0xc23c, 0xe1ff, 0xc23c, 0x21, 0 + .dw 0xe240, 0xc23c, 0xe27f, 0xc23c, 0x21, 0 + .dw 0xe2c0, 0xc23c, 0xe2ff, 0xc23c, 0x21, 0 + .dw 0xe340, 0xc23c, 0xe37f, 0xc23c, 0x21, 0 + .dw 0xe3c0, 0xc23c, 0xe3ff, 0xc23c, 0x21, 0 + .dw 0xe440, 0xc23c, 0xe47f, 0xc23c, 0x21, 0 + .dw 0xe4c0, 0xc23c, 0xe4ff, 0xc23c, 0x21, 0 + .dw 0xe540, 0xc23c, 0xe57f, 0xc23c, 0x21, 0 + .dw 0xe5c0, 0xc23c, 0xe5ff, 0xc23c, 0x21, 0 + .dw 0xe640, 0xc23c, 0xe67f, 0xc23c, 0x21, 0 + .dw 0xe6c0, 0xc23c, 0xe6ff, 0xc23c, 0x21, 0 + .dw 0xe740, 0xc23c, 0xe77f, 0xc23c, 0x21, 0 + .dw 0xe7c0, 0xc23c, 0x1fff, 0xc240, 0x21, 0 + .dw 0x2800, 0xc240, 0xffff, 0xc243, 0x21, 0 + .dw 0x0200, 0xc244, 0x1fff, 0xc244, 0x21, 0 + .dw 0x2800, 0xc244, 0x3fff, 0xc244, 0x21, 0 + .dw 0x4200, 0xc244, 0x5fff, 0xc244, 0x21, 0 + .dw 0x6800, 0xc244, 0x7fff, 0xc244, 0x21, 0 + .dw 0x8200, 0xc244, 0x9fff, 0xc244, 0x21, 0 + .dw 0xa800, 0xc244, 0xbfff, 0xc244, 0x21, 0 + .dw 0xc200, 0xc244, 0xdfff, 0xc244, 0x21, 0 + .dw 0xe800, 0xc244, 0xffff, 0xc253, 0x21, 0 + .dw 0x0200, 0xc254, 0x1fff, 0xc254, 0x21, 0 + .dw 0x2800, 0xc254, 0x3fff, 0xc254, 0x21, 0 + .dw 0x4200, 0xc254, 0x5fff, 0xc254, 0x21, 0 + .dw 0x6800, 0xc254, 0x7fff, 0xc254, 0x21, 0 + .dw 0x8200, 0xc254, 0x9fff, 0xc254, 0x21, 0 + .dw 0xa800, 0xc254, 0xbfff, 0xc254, 0x21, 0 + .dw 0xc200, 0xc254, 0xdfff, 0xc254, 0x21, 0 + .dw 0xe800, 0xc254, 0x1fff, 0xc280, 0x21, 0 + .dw 0x2800, 0xc280, 0xffff, 0xc283, 0x21, 0 + .dw 0x0200, 0xc284, 0x1fff, 0xc284, 0x21, 0 + .dw 0x2800, 0xc284, 0x3fff, 0xc284, 0x21, 0 + .dw 0x4200, 0xc284, 0x5fff, 0xc284, 0x21, 0 + .dw 0x6800, 0xc284, 0x7fff, 0xc284, 0x21, 0 + .dw 0x8200, 0xc284, 0x9fff, 0xc284, 0x21, 0 + .dw 0xa800, 0xc284, 0xbfff, 0xc284, 0x21, 0 + .dw 0xc200, 0xc284, 0xdfff, 0xc284, 0x21, 0 + .dw 0xe800, 0xc284, 0x1fff, 0xc288, 0x21, 0 + .dw 0x2040, 0xc288, 0x207f, 0xc288, 0x21, 0 + .dw 0x20c0, 0xc288, 0x20ff, 0xc288, 0x21, 0 + .dw 0x2140, 0xc288, 0x217f, 0xc288, 0x21, 0 + .dw 0x21c0, 0xc288, 0x21ff, 0xc288, 0x21, 0 + .dw 0x2240, 0xc288, 0x227f, 0xc288, 0x21, 0 + .dw 0x22c0, 0xc288, 0x22ff, 0xc288, 0x21, 0 + .dw 0x2340, 0xc288, 0x237f, 0xc288, 0x21, 0 + .dw 0x23c0, 0xc288, 0x23ff, 0xc288, 0x21, 0 + .dw 0x2440, 0xc288, 0x247f, 0xc288, 0x21, 0 + .dw 0x24c0, 0xc288, 0x24ff, 0xc288, 0x21, 0 + .dw 0x2540, 0xc288, 0x257f, 0xc288, 0x21, 0 + .dw 0x25c0, 0xc288, 0x25ff, 0xc288, 0x21, 0 + .dw 0x2640, 0xc288, 0x267f, 0xc288, 0x21, 0 + .dw 0x26c0, 0xc288, 0x26ff, 0xc288, 0x21, 0 + .dw 0x2740, 0xc288, 0x277f, 0xc288, 0x21, 0 + .dw 0x27c0, 0xc288, 0xffff, 0xc28b, 0x21, 0 + .dw 0x0040, 0xc28c, 0x007f, 0xc28c, 0x21, 0 + .dw 0x00c0, 0xc28c, 0x00ff, 0xc28c, 0x21, 0 + .dw 0x0140, 0xc28c, 0x017f, 0xc28c, 0x21, 0 + .dw 0x01c0, 0xc28c, 0x1fff, 0xc28c, 0x21, 0 + .dw 0x2040, 0xc28c, 0x207f, 0xc28c, 0x21, 0 + .dw 0x20c0, 0xc28c, 0x20ff, 0xc28c, 0x21, 0 + .dw 0x2140, 0xc28c, 0x217f, 0xc28c, 0x21, 0 + .dw 0x21c0, 0xc28c, 0x21ff, 0xc28c, 0x21, 0 + .dw 0x2240, 0xc28c, 0x227f, 0xc28c, 0x21, 0 + .dw 0x22c0, 0xc28c, 0x22ff, 0xc28c, 0x21, 0 + .dw 0x2340, 0xc28c, 0x237f, 0xc28c, 0x21, 0 + .dw 0x23c0, 0xc28c, 0x23ff, 0xc28c, 0x21, 0 + .dw 0x2440, 0xc28c, 0x247f, 0xc28c, 0x21, 0 + .dw 0x24c0, 0xc28c, 0x24ff, 0xc28c, 0x21, 0 + .dw 0x2540, 0xc28c, 0x257f, 0xc28c, 0x21, 0 + .dw 0x25c0, 0xc28c, 0x25ff, 0xc28c, 0x21, 0 + .dw 0x2640, 0xc28c, 0x267f, 0xc28c, 0x21, 0 + .dw 0x26c0, 0xc28c, 0x26ff, 0xc28c, 0x21, 0 + .dw 0x2740, 0xc28c, 0x277f, 0xc28c, 0x21, 0 + .dw 0x27c0, 0xc28c, 0x3fff, 0xc28c, 0x21, 0 + .dw 0x4040, 0xc28c, 0x407f, 0xc28c, 0x21, 0 + .dw 0x40c0, 0xc28c, 0x40ff, 0xc28c, 0x21, 0 + .dw 0x4140, 0xc28c, 0x417f, 0xc28c, 0x21, 0 + .dw 0x41c0, 0xc28c, 0x5fff, 0xc28c, 0x21, 0 + .dw 0x6040, 0xc28c, 0x607f, 0xc28c, 0x21, 0 + .dw 0x60c0, 0xc28c, 0x60ff, 0xc28c, 0x21, 0 + .dw 0x6140, 0xc28c, 0x617f, 0xc28c, 0x21, 0 + .dw 0x61c0, 0xc28c, 0x61ff, 0xc28c, 0x21, 0 + .dw 0x6240, 0xc28c, 0x627f, 0xc28c, 0x21, 0 + .dw 0x62c0, 0xc28c, 0x62ff, 0xc28c, 0x21, 0 + .dw 0x6340, 0xc28c, 0x637f, 0xc28c, 0x21, 0 + .dw 0x63c0, 0xc28c, 0x63ff, 0xc28c, 0x21, 0 + .dw 0x6440, 0xc28c, 0x647f, 0xc28c, 0x21, 0 + .dw 0x64c0, 0xc28c, 0x64ff, 0xc28c, 0x21, 0 + .dw 0x6540, 0xc28c, 0x657f, 0xc28c, 0x21, 0 + .dw 0x65c0, 0xc28c, 0x65ff, 0xc28c, 0x21, 0 + .dw 0x6640, 0xc28c, 0x667f, 0xc28c, 0x21, 0 + .dw 0x66c0, 0xc28c, 0x66ff, 0xc28c, 0x21, 0 + .dw 0x6740, 0xc28c, 0x677f, 0xc28c, 0x21, 0 + .dw 0x67c0, 0xc28c, 0x7fff, 0xc28c, 0x21, 0 + .dw 0x8040, 0xc28c, 0x807f, 0xc28c, 0x21, 0 + .dw 0x80c0, 0xc28c, 0x80ff, 0xc28c, 0x21, 0 + .dw 0x8140, 0xc28c, 0x817f, 0xc28c, 0x21, 0 + .dw 0x81c0, 0xc28c, 0x9fff, 0xc28c, 0x21, 0 + .dw 0xa040, 0xc28c, 0xa07f, 0xc28c, 0x21, 0 + .dw 0xa0c0, 0xc28c, 0xa0ff, 0xc28c, 0x21, 0 + .dw 0xa140, 0xc28c, 0xa17f, 0xc28c, 0x21, 0 + .dw 0xa1c0, 0xc28c, 0xa1ff, 0xc28c, 0x21, 0 + .dw 0xa240, 0xc28c, 0xa27f, 0xc28c, 0x21, 0 + .dw 0xa2c0, 0xc28c, 0xa2ff, 0xc28c, 0x21, 0 + .dw 0xa340, 0xc28c, 0xa37f, 0xc28c, 0x21, 0 + .dw 0xa3c0, 0xc28c, 0xa3ff, 0xc28c, 0x21, 0 + .dw 0xa440, 0xc28c, 0xa47f, 0xc28c, 0x21, 0 + .dw 0xa4c0, 0xc28c, 0xa4ff, 0xc28c, 0x21, 0 + .dw 0xa540, 0xc28c, 0xa57f, 0xc28c, 0x21, 0 + .dw 0xa5c0, 0xc28c, 0xa5ff, 0xc28c, 0x21, 0 + .dw 0xa640, 0xc28c, 0xa67f, 0xc28c, 0x21, 0 + .dw 0xa6c0, 0xc28c, 0xa6ff, 0xc28c, 0x21, 0 + .dw 0xa740, 0xc28c, 0xa77f, 0xc28c, 0x21, 0 + .dw 0xa7c0, 0xc28c, 0xbfff, 0xc28c, 0x21, 0 + .dw 0xc040, 0xc28c, 0xc07f, 0xc28c, 0x21, 0 + .dw 0xc0c0, 0xc28c, 0xc0ff, 0xc28c, 0x21, 0 + .dw 0xc140, 0xc28c, 0xc17f, 0xc28c, 0x21, 0 + .dw 0xc1c0, 0xc28c, 0xdfff, 0xc28c, 0x21, 0 + .dw 0xe040, 0xc28c, 0xe07f, 0xc28c, 0x21, 0 + .dw 0xe0c0, 0xc28c, 0xe0ff, 0xc28c, 0x21, 0 + .dw 0xe140, 0xc28c, 0xe17f, 0xc28c, 0x21, 0 + .dw 0xe1c0, 0xc28c, 0xe1ff, 0xc28c, 0x21, 0 + .dw 0xe240, 0xc28c, 0xe27f, 0xc28c, 0x21, 0 + .dw 0xe2c0, 0xc28c, 0xe2ff, 0xc28c, 0x21, 0 + .dw 0xe340, 0xc28c, 0xe37f, 0xc28c, 0x21, 0 + .dw 0xe3c0, 0xc28c, 0xe3ff, 0xc28c, 0x21, 0 + .dw 0xe440, 0xc28c, 0xe47f, 0xc28c, 0x21, 0 + .dw 0xe4c0, 0xc28c, 0xe4ff, 0xc28c, 0x21, 0 + .dw 0xe540, 0xc28c, 0xe57f, 0xc28c, 0x21, 0 + .dw 0xe5c0, 0xc28c, 0xe5ff, 0xc28c, 0x21, 0 + .dw 0xe640, 0xc28c, 0xe67f, 0xc28c, 0x21, 0 + .dw 0xe6c0, 0xc28c, 0xe6ff, 0xc28c, 0x21, 0 + .dw 0xe740, 0xc28c, 0xe77f, 0xc28c, 0x21, 0 + .dw 0xe7c0, 0xc28c, 0xffff, 0xc293, 0x21, 0 + .dw 0x0200, 0xc294, 0x1fff, 0xc294, 0x21, 0 + .dw 0x2800, 0xc294, 0x3fff, 0xc294, 0x21, 0 + .dw 0x4200, 0xc294, 0x5fff, 0xc294, 0x21, 0 + .dw 0x6800, 0xc294, 0x7fff, 0xc294, 0x21, 0 + .dw 0x8200, 0xc294, 0x9fff, 0xc294, 0x21, 0 + .dw 0xa800, 0xc294, 0xbfff, 0xc294, 0x21, 0 + .dw 0xc200, 0xc294, 0xdfff, 0xc294, 0x21, 0 + .dw 0xe800, 0xc294, 0xffff, 0xc29b, 0x21, 0 + .dw 0x0040, 0xc29c, 0x007f, 0xc29c, 0x21, 0 + .dw 0x00c0, 0xc29c, 0x00ff, 0xc29c, 0x21, 0 + .dw 0x0140, 0xc29c, 0x017f, 0xc29c, 0x21, 0 + .dw 0x01c0, 0xc29c, 0x1fff, 0xc29c, 0x21, 0 + .dw 0x2040, 0xc29c, 0x207f, 0xc29c, 0x21, 0 + .dw 0x20c0, 0xc29c, 0x20ff, 0xc29c, 0x21, 0 + .dw 0x2140, 0xc29c, 0x217f, 0xc29c, 0x21, 0 + .dw 0x21c0, 0xc29c, 0x21ff, 0xc29c, 0x21, 0 + .dw 0x2240, 0xc29c, 0x227f, 0xc29c, 0x21, 0 + .dw 0x22c0, 0xc29c, 0x22ff, 0xc29c, 0x21, 0 + .dw 0x2340, 0xc29c, 0x237f, 0xc29c, 0x21, 0 + .dw 0x23c0, 0xc29c, 0x23ff, 0xc29c, 0x21, 0 + .dw 0x2440, 0xc29c, 0x247f, 0xc29c, 0x21, 0 + .dw 0x24c0, 0xc29c, 0x24ff, 0xc29c, 0x21, 0 + .dw 0x2540, 0xc29c, 0x257f, 0xc29c, 0x21, 0 + .dw 0x25c0, 0xc29c, 0x25ff, 0xc29c, 0x21, 0 + .dw 0x2640, 0xc29c, 0x267f, 0xc29c, 0x21, 0 + .dw 0x26c0, 0xc29c, 0x26ff, 0xc29c, 0x21, 0 + .dw 0x2740, 0xc29c, 0x277f, 0xc29c, 0x21, 0 + .dw 0x27c0, 0xc29c, 0x3fff, 0xc29c, 0x21, 0 + .dw 0x4040, 0xc29c, 0x407f, 0xc29c, 0x21, 0 + .dw 0x40c0, 0xc29c, 0x40ff, 0xc29c, 0x21, 0 + .dw 0x4140, 0xc29c, 0x417f, 0xc29c, 0x21, 0 + .dw 0x41c0, 0xc29c, 0x5fff, 0xc29c, 0x21, 0 + .dw 0x6040, 0xc29c, 0x607f, 0xc29c, 0x21, 0 + .dw 0x60c0, 0xc29c, 0x60ff, 0xc29c, 0x21, 0 + .dw 0x6140, 0xc29c, 0x617f, 0xc29c, 0x21, 0 + .dw 0x61c0, 0xc29c, 0x61ff, 0xc29c, 0x21, 0 + .dw 0x6240, 0xc29c, 0x627f, 0xc29c, 0x21, 0 + .dw 0x62c0, 0xc29c, 0x62ff, 0xc29c, 0x21, 0 + .dw 0x6340, 0xc29c, 0x637f, 0xc29c, 0x21, 0 + .dw 0x63c0, 0xc29c, 0x63ff, 0xc29c, 0x21, 0 + .dw 0x6440, 0xc29c, 0x647f, 0xc29c, 0x21, 0 + .dw 0x64c0, 0xc29c, 0x64ff, 0xc29c, 0x21, 0 + .dw 0x6540, 0xc29c, 0x657f, 0xc29c, 0x21, 0 + .dw 0x65c0, 0xc29c, 0x65ff, 0xc29c, 0x21, 0 + .dw 0x6640, 0xc29c, 0x667f, 0xc29c, 0x21, 0 + .dw 0x66c0, 0xc29c, 0x66ff, 0xc29c, 0x21, 0 + .dw 0x6740, 0xc29c, 0x677f, 0xc29c, 0x21, 0 + .dw 0x67c0, 0xc29c, 0x7fff, 0xc29c, 0x21, 0 + .dw 0x8040, 0xc29c, 0x807f, 0xc29c, 0x21, 0 + .dw 0x80c0, 0xc29c, 0x80ff, 0xc29c, 0x21, 0 + .dw 0x8140, 0xc29c, 0x817f, 0xc29c, 0x21, 0 + .dw 0x81c0, 0xc29c, 0x9fff, 0xc29c, 0x21, 0 + .dw 0xa040, 0xc29c, 0xa07f, 0xc29c, 0x21, 0 + .dw 0xa0c0, 0xc29c, 0xa0ff, 0xc29c, 0x21, 0 + .dw 0xa140, 0xc29c, 0xa17f, 0xc29c, 0x21, 0 + .dw 0xa1c0, 0xc29c, 0xa1ff, 0xc29c, 0x21, 0 + .dw 0xa240, 0xc29c, 0xa27f, 0xc29c, 0x21, 0 + .dw 0xa2c0, 0xc29c, 0xa2ff, 0xc29c, 0x21, 0 + .dw 0xa340, 0xc29c, 0xa37f, 0xc29c, 0x21, 0 + .dw 0xa3c0, 0xc29c, 0xa3ff, 0xc29c, 0x21, 0 + .dw 0xa440, 0xc29c, 0xa47f, 0xc29c, 0x21, 0 + .dw 0xa4c0, 0xc29c, 0xa4ff, 0xc29c, 0x21, 0 + .dw 0xa540, 0xc29c, 0xa57f, 0xc29c, 0x21, 0 + .dw 0xa5c0, 0xc29c, 0xa5ff, 0xc29c, 0x21, 0 + .dw 0xa640, 0xc29c, 0xa67f, 0xc29c, 0x21, 0 + .dw 0xa6c0, 0xc29c, 0xa6ff, 0xc29c, 0x21, 0 + .dw 0xa740, 0xc29c, 0xa77f, 0xc29c, 0x21, 0 + .dw 0xa7c0, 0xc29c, 0xbfff, 0xc29c, 0x21, 0 + .dw 0xc040, 0xc29c, 0xc07f, 0xc29c, 0x21, 0 + .dw 0xc0c0, 0xc29c, 0xc0ff, 0xc29c, 0x21, 0 + .dw 0xc140, 0xc29c, 0xc17f, 0xc29c, 0x21, 0 + .dw 0xc1c0, 0xc29c, 0xdfff, 0xc29c, 0x21, 0 + .dw 0xe040, 0xc29c, 0xe07f, 0xc29c, 0x21, 0 + .dw 0xe0c0, 0xc29c, 0xe0ff, 0xc29c, 0x21, 0 + .dw 0xe140, 0xc29c, 0xe17f, 0xc29c, 0x21, 0 + .dw 0xe1c0, 0xc29c, 0xe1ff, 0xc29c, 0x21, 0 + .dw 0xe240, 0xc29c, 0xe27f, 0xc29c, 0x21, 0 + .dw 0xe2c0, 0xc29c, 0xe2ff, 0xc29c, 0x21, 0 + .dw 0xe340, 0xc29c, 0xe37f, 0xc29c, 0x21, 0 + .dw 0xe3c0, 0xc29c, 0xe3ff, 0xc29c, 0x21, 0 + .dw 0xe440, 0xc29c, 0xe47f, 0xc29c, 0x21, 0 + .dw 0xe4c0, 0xc29c, 0xe4ff, 0xc29c, 0x21, 0 + .dw 0xe540, 0xc29c, 0xe57f, 0xc29c, 0x21, 0 + .dw 0xe5c0, 0xc29c, 0xe5ff, 0xc29c, 0x21, 0 + .dw 0xe640, 0xc29c, 0xe67f, 0xc29c, 0x21, 0 + .dw 0xe6c0, 0xc29c, 0xe6ff, 0xc29c, 0x21, 0 + .dw 0xe740, 0xc29c, 0xe77f, 0xc29c, 0x21, 0 + .dw 0xe7c0, 0xc29c, 0x1fff, 0xc2c0, 0x21, 0 + .dw 0x2800, 0xc2c0, 0xffff, 0xc2c3, 0x21, 0 + .dw 0x0200, 0xc2c4, 0x1fff, 0xc2c4, 0x21, 0 + .dw 0x2800, 0xc2c4, 0x3fff, 0xc2c4, 0x21, 0 + .dw 0x4200, 0xc2c4, 0x5fff, 0xc2c4, 0x21, 0 + .dw 0x6800, 0xc2c4, 0x7fff, 0xc2c4, 0x21, 0 + .dw 0x8200, 0xc2c4, 0x9fff, 0xc2c4, 0x21, 0 + .dw 0xa800, 0xc2c4, 0xbfff, 0xc2c4, 0x21, 0 + .dw 0xc200, 0xc2c4, 0xdfff, 0xc2c4, 0x21, 0 + .dw 0xe800, 0xc2c4, 0xffff, 0xc2d3, 0x21, 0 + .dw 0x0200, 0xc2d4, 0x1fff, 0xc2d4, 0x21, 0 + .dw 0x2800, 0xc2d4, 0x3fff, 0xc2d4, 0x21, 0 + .dw 0x4200, 0xc2d4, 0x5fff, 0xc2d4, 0x21, 0 + .dw 0x6800, 0xc2d4, 0x7fff, 0xc2d4, 0x21, 0 + .dw 0x8200, 0xc2d4, 0x9fff, 0xc2d4, 0x21, 0 + .dw 0xa800, 0xc2d4, 0xbfff, 0xc2d4, 0x21, 0 + .dw 0xc200, 0xc2d4, 0xdfff, 0xc2d4, 0x21, 0 + .dw 0xe800, 0xc2d4, 0x1fff, 0xc300, 0x21, 0 + .dw 0x2800, 0xc300, 0xffff, 0xc303, 0x21, 0 + .dw 0x0200, 0xc304, 0x1fff, 0xc304, 0x21, 0 + .dw 0x2800, 0xc304, 0x3fff, 0xc304, 0x21, 0 + .dw 0x4200, 0xc304, 0x5fff, 0xc304, 0x21, 0 + .dw 0x6800, 0xc304, 0x7fff, 0xc304, 0x21, 0 + .dw 0x8200, 0xc304, 0x9fff, 0xc304, 0x21, 0 + .dw 0xa800, 0xc304, 0xbfff, 0xc304, 0x21, 0 + .dw 0xc200, 0xc304, 0xdfff, 0xc304, 0x21, 0 + .dw 0xe800, 0xc304, 0x1fff, 0xc308, 0x21, 0 + .dw 0x2040, 0xc308, 0x207f, 0xc308, 0x21, 0 + .dw 0x20c0, 0xc308, 0x20ff, 0xc308, 0x21, 0 + .dw 0x2140, 0xc308, 0x217f, 0xc308, 0x21, 0 + .dw 0x21c0, 0xc308, 0x21ff, 0xc308, 0x21, 0 + .dw 0x2240, 0xc308, 0x227f, 0xc308, 0x21, 0 + .dw 0x22c0, 0xc308, 0x22ff, 0xc308, 0x21, 0 + .dw 0x2340, 0xc308, 0x237f, 0xc308, 0x21, 0 + .dw 0x23c0, 0xc308, 0x23ff, 0xc308, 0x21, 0 + .dw 0x2440, 0xc308, 0x247f, 0xc308, 0x21, 0 + .dw 0x24c0, 0xc308, 0x24ff, 0xc308, 0x21, 0 + .dw 0x2540, 0xc308, 0x257f, 0xc308, 0x21, 0 + .dw 0x25c0, 0xc308, 0x25ff, 0xc308, 0x21, 0 + .dw 0x2640, 0xc308, 0x267f, 0xc308, 0x21, 0 + .dw 0x26c0, 0xc308, 0x26ff, 0xc308, 0x21, 0 + .dw 0x2740, 0xc308, 0x277f, 0xc308, 0x21, 0 + .dw 0x27c0, 0xc308, 0xffff, 0xc30b, 0x21, 0 + .dw 0x0040, 0xc30c, 0x007f, 0xc30c, 0x21, 0 + .dw 0x00c0, 0xc30c, 0x00ff, 0xc30c, 0x21, 0 + .dw 0x0140, 0xc30c, 0x017f, 0xc30c, 0x21, 0 + .dw 0x01c0, 0xc30c, 0x1fff, 0xc30c, 0x21, 0 + .dw 0x2040, 0xc30c, 0x207f, 0xc30c, 0x21, 0 + .dw 0x20c0, 0xc30c, 0x20ff, 0xc30c, 0x21, 0 + .dw 0x2140, 0xc30c, 0x217f, 0xc30c, 0x21, 0 + .dw 0x21c0, 0xc30c, 0x21ff, 0xc30c, 0x21, 0 + .dw 0x2240, 0xc30c, 0x227f, 0xc30c, 0x21, 0 + .dw 0x22c0, 0xc30c, 0x22ff, 0xc30c, 0x21, 0 + .dw 0x2340, 0xc30c, 0x237f, 0xc30c, 0x21, 0 + .dw 0x23c0, 0xc30c, 0x23ff, 0xc30c, 0x21, 0 + .dw 0x2440, 0xc30c, 0x247f, 0xc30c, 0x21, 0 + .dw 0x24c0, 0xc30c, 0x24ff, 0xc30c, 0x21, 0 + .dw 0x2540, 0xc30c, 0x257f, 0xc30c, 0x21, 0 + .dw 0x25c0, 0xc30c, 0x25ff, 0xc30c, 0x21, 0 + .dw 0x2640, 0xc30c, 0x267f, 0xc30c, 0x21, 0 + .dw 0x26c0, 0xc30c, 0x26ff, 0xc30c, 0x21, 0 + .dw 0x2740, 0xc30c, 0x277f, 0xc30c, 0x21, 0 + .dw 0x27c0, 0xc30c, 0x3fff, 0xc30c, 0x21, 0 + .dw 0x4040, 0xc30c, 0x407f, 0xc30c, 0x21, 0 + .dw 0x40c0, 0xc30c, 0x40ff, 0xc30c, 0x21, 0 + .dw 0x4140, 0xc30c, 0x417f, 0xc30c, 0x21, 0 + .dw 0x41c0, 0xc30c, 0x5fff, 0xc30c, 0x21, 0 + .dw 0x6040, 0xc30c, 0x607f, 0xc30c, 0x21, 0 + .dw 0x60c0, 0xc30c, 0x60ff, 0xc30c, 0x21, 0 + .dw 0x6140, 0xc30c, 0x617f, 0xc30c, 0x21, 0 + .dw 0x61c0, 0xc30c, 0x61ff, 0xc30c, 0x21, 0 + .dw 0x6240, 0xc30c, 0x627f, 0xc30c, 0x21, 0 + .dw 0x62c0, 0xc30c, 0x62ff, 0xc30c, 0x21, 0 + .dw 0x6340, 0xc30c, 0x637f, 0xc30c, 0x21, 0 + .dw 0x63c0, 0xc30c, 0x63ff, 0xc30c, 0x21, 0 + .dw 0x6440, 0xc30c, 0x647f, 0xc30c, 0x21, 0 + .dw 0x64c0, 0xc30c, 0x64ff, 0xc30c, 0x21, 0 + .dw 0x6540, 0xc30c, 0x657f, 0xc30c, 0x21, 0 + .dw 0x65c0, 0xc30c, 0x65ff, 0xc30c, 0x21, 0 + .dw 0x6640, 0xc30c, 0x667f, 0xc30c, 0x21, 0 + .dw 0x66c0, 0xc30c, 0x66ff, 0xc30c, 0x21, 0 + .dw 0x6740, 0xc30c, 0x677f, 0xc30c, 0x21, 0 + .dw 0x67c0, 0xc30c, 0x7fff, 0xc30c, 0x21, 0 + .dw 0x8040, 0xc30c, 0x807f, 0xc30c, 0x21, 0 + .dw 0x80c0, 0xc30c, 0x80ff, 0xc30c, 0x21, 0 + .dw 0x8140, 0xc30c, 0x817f, 0xc30c, 0x21, 0 + .dw 0x81c0, 0xc30c, 0x9fff, 0xc30c, 0x21, 0 + .dw 0xa040, 0xc30c, 0xa07f, 0xc30c, 0x21, 0 + .dw 0xa0c0, 0xc30c, 0xa0ff, 0xc30c, 0x21, 0 + .dw 0xa140, 0xc30c, 0xa17f, 0xc30c, 0x21, 0 + .dw 0xa1c0, 0xc30c, 0xa1ff, 0xc30c, 0x21, 0 + .dw 0xa240, 0xc30c, 0xa27f, 0xc30c, 0x21, 0 + .dw 0xa2c0, 0xc30c, 0xa2ff, 0xc30c, 0x21, 0 + .dw 0xa340, 0xc30c, 0xa37f, 0xc30c, 0x21, 0 + .dw 0xa3c0, 0xc30c, 0xa3ff, 0xc30c, 0x21, 0 + .dw 0xa440, 0xc30c, 0xa47f, 0xc30c, 0x21, 0 + .dw 0xa4c0, 0xc30c, 0xa4ff, 0xc30c, 0x21, 0 + .dw 0xa540, 0xc30c, 0xa57f, 0xc30c, 0x21, 0 + .dw 0xa5c0, 0xc30c, 0xa5ff, 0xc30c, 0x21, 0 + .dw 0xa640, 0xc30c, 0xa67f, 0xc30c, 0x21, 0 + .dw 0xa6c0, 0xc30c, 0xa6ff, 0xc30c, 0x21, 0 + .dw 0xa740, 0xc30c, 0xa77f, 0xc30c, 0x21, 0 + .dw 0xa7c0, 0xc30c, 0xbfff, 0xc30c, 0x21, 0 + .dw 0xc040, 0xc30c, 0xc07f, 0xc30c, 0x21, 0 + .dw 0xc0c0, 0xc30c, 0xc0ff, 0xc30c, 0x21, 0 + .dw 0xc140, 0xc30c, 0xc17f, 0xc30c, 0x21, 0 + .dw 0xc1c0, 0xc30c, 0xdfff, 0xc30c, 0x21, 0 + .dw 0xe040, 0xc30c, 0xe07f, 0xc30c, 0x21, 0 + .dw 0xe0c0, 0xc30c, 0xe0ff, 0xc30c, 0x21, 0 + .dw 0xe140, 0xc30c, 0xe17f, 0xc30c, 0x21, 0 + .dw 0xe1c0, 0xc30c, 0xe1ff, 0xc30c, 0x21, 0 + .dw 0xe240, 0xc30c, 0xe27f, 0xc30c, 0x21, 0 + .dw 0xe2c0, 0xc30c, 0xe2ff, 0xc30c, 0x21, 0 + .dw 0xe340, 0xc30c, 0xe37f, 0xc30c, 0x21, 0 + .dw 0xe3c0, 0xc30c, 0xe3ff, 0xc30c, 0x21, 0 + .dw 0xe440, 0xc30c, 0xe47f, 0xc30c, 0x21, 0 + .dw 0xe4c0, 0xc30c, 0xe4ff, 0xc30c, 0x21, 0 + .dw 0xe540, 0xc30c, 0xe57f, 0xc30c, 0x21, 0 + .dw 0xe5c0, 0xc30c, 0xe5ff, 0xc30c, 0x21, 0 + .dw 0xe640, 0xc30c, 0xe67f, 0xc30c, 0x21, 0 + .dw 0xe6c0, 0xc30c, 0xe6ff, 0xc30c, 0x21, 0 + .dw 0xe740, 0xc30c, 0xe77f, 0xc30c, 0x21, 0 + .dw 0xe7c0, 0xc30c, 0xffff, 0xc313, 0x21, 0 + .dw 0x0200, 0xc314, 0x1fff, 0xc314, 0x21, 0 + .dw 0x2800, 0xc314, 0x3fff, 0xc314, 0x21, 0 + .dw 0x4200, 0xc314, 0x5fff, 0xc314, 0x21, 0 + .dw 0x6800, 0xc314, 0x7fff, 0xc314, 0x21, 0 + .dw 0x8200, 0xc314, 0x9fff, 0xc314, 0x21, 0 + .dw 0xa800, 0xc314, 0xbfff, 0xc314, 0x21, 0 + .dw 0xc200, 0xc314, 0xdfff, 0xc314, 0x21, 0 + .dw 0xe800, 0xc314, 0xffff, 0xc31b, 0x21, 0 + .dw 0x0040, 0xc31c, 0x007f, 0xc31c, 0x21, 0 + .dw 0x00c0, 0xc31c, 0x00ff, 0xc31c, 0x21, 0 + .dw 0x0140, 0xc31c, 0x017f, 0xc31c, 0x21, 0 + .dw 0x01c0, 0xc31c, 0x1fff, 0xc31c, 0x21, 0 + .dw 0x2040, 0xc31c, 0x207f, 0xc31c, 0x21, 0 + .dw 0x20c0, 0xc31c, 0x20ff, 0xc31c, 0x21, 0 + .dw 0x2140, 0xc31c, 0x217f, 0xc31c, 0x21, 0 + .dw 0x21c0, 0xc31c, 0x21ff, 0xc31c, 0x21, 0 + .dw 0x2240, 0xc31c, 0x227f, 0xc31c, 0x21, 0 + .dw 0x22c0, 0xc31c, 0x22ff, 0xc31c, 0x21, 0 + .dw 0x2340, 0xc31c, 0x237f, 0xc31c, 0x21, 0 + .dw 0x23c0, 0xc31c, 0x23ff, 0xc31c, 0x21, 0 + .dw 0x2440, 0xc31c, 0x247f, 0xc31c, 0x21, 0 + .dw 0x24c0, 0xc31c, 0x24ff, 0xc31c, 0x21, 0 + .dw 0x2540, 0xc31c, 0x257f, 0xc31c, 0x21, 0 + .dw 0x25c0, 0xc31c, 0x25ff, 0xc31c, 0x21, 0 + .dw 0x2640, 0xc31c, 0x267f, 0xc31c, 0x21, 0 + .dw 0x26c0, 0xc31c, 0x26ff, 0xc31c, 0x21, 0 + .dw 0x2740, 0xc31c, 0x277f, 0xc31c, 0x21, 0 + .dw 0x27c0, 0xc31c, 0x3fff, 0xc31c, 0x21, 0 + .dw 0x4040, 0xc31c, 0x407f, 0xc31c, 0x21, 0 + .dw 0x40c0, 0xc31c, 0x40ff, 0xc31c, 0x21, 0 + .dw 0x4140, 0xc31c, 0x417f, 0xc31c, 0x21, 0 + .dw 0x41c0, 0xc31c, 0x5fff, 0xc31c, 0x21, 0 + .dw 0x6040, 0xc31c, 0x607f, 0xc31c, 0x21, 0 + .dw 0x60c0, 0xc31c, 0x60ff, 0xc31c, 0x21, 0 + .dw 0x6140, 0xc31c, 0x617f, 0xc31c, 0x21, 0 + .dw 0x61c0, 0xc31c, 0x61ff, 0xc31c, 0x21, 0 + .dw 0x6240, 0xc31c, 0x627f, 0xc31c, 0x21, 0 + .dw 0x62c0, 0xc31c, 0x62ff, 0xc31c, 0x21, 0 + .dw 0x6340, 0xc31c, 0x637f, 0xc31c, 0x21, 0 + .dw 0x63c0, 0xc31c, 0x63ff, 0xc31c, 0x21, 0 + .dw 0x6440, 0xc31c, 0x647f, 0xc31c, 0x21, 0 + .dw 0x64c0, 0xc31c, 0x64ff, 0xc31c, 0x21, 0 + .dw 0x6540, 0xc31c, 0x657f, 0xc31c, 0x21, 0 + .dw 0x65c0, 0xc31c, 0x65ff, 0xc31c, 0x21, 0 + .dw 0x6640, 0xc31c, 0x667f, 0xc31c, 0x21, 0 + .dw 0x66c0, 0xc31c, 0x66ff, 0xc31c, 0x21, 0 + .dw 0x6740, 0xc31c, 0x677f, 0xc31c, 0x21, 0 + .dw 0x67c0, 0xc31c, 0x7fff, 0xc31c, 0x21, 0 + .dw 0x8040, 0xc31c, 0x807f, 0xc31c, 0x21, 0 + .dw 0x80c0, 0xc31c, 0x80ff, 0xc31c, 0x21, 0 + .dw 0x8140, 0xc31c, 0x817f, 0xc31c, 0x21, 0 + .dw 0x81c0, 0xc31c, 0x9fff, 0xc31c, 0x21, 0 + .dw 0xa040, 0xc31c, 0xa07f, 0xc31c, 0x21, 0 + .dw 0xa0c0, 0xc31c, 0xa0ff, 0xc31c, 0x21, 0 + .dw 0xa140, 0xc31c, 0xa17f, 0xc31c, 0x21, 0 + .dw 0xa1c0, 0xc31c, 0xa1ff, 0xc31c, 0x21, 0 + .dw 0xa240, 0xc31c, 0xa27f, 0xc31c, 0x21, 0 + .dw 0xa2c0, 0xc31c, 0xa2ff, 0xc31c, 0x21, 0 + .dw 0xa340, 0xc31c, 0xa37f, 0xc31c, 0x21, 0 + .dw 0xa3c0, 0xc31c, 0xa3ff, 0xc31c, 0x21, 0 + .dw 0xa440, 0xc31c, 0xa47f, 0xc31c, 0x21, 0 + .dw 0xa4c0, 0xc31c, 0xa4ff, 0xc31c, 0x21, 0 + .dw 0xa540, 0xc31c, 0xa57f, 0xc31c, 0x21, 0 + .dw 0xa5c0, 0xc31c, 0xa5ff, 0xc31c, 0x21, 0 + .dw 0xa640, 0xc31c, 0xa67f, 0xc31c, 0x21, 0 + .dw 0xa6c0, 0xc31c, 0xa6ff, 0xc31c, 0x21, 0 + .dw 0xa740, 0xc31c, 0xa77f, 0xc31c, 0x21, 0 + .dw 0xa7c0, 0xc31c, 0xbfff, 0xc31c, 0x21, 0 + .dw 0xc040, 0xc31c, 0xc07f, 0xc31c, 0x21, 0 + .dw 0xc0c0, 0xc31c, 0xc0ff, 0xc31c, 0x21, 0 + .dw 0xc140, 0xc31c, 0xc17f, 0xc31c, 0x21, 0 + .dw 0xc1c0, 0xc31c, 0xdfff, 0xc31c, 0x21, 0 + .dw 0xe040, 0xc31c, 0xe07f, 0xc31c, 0x21, 0 + .dw 0xe0c0, 0xc31c, 0xe0ff, 0xc31c, 0x21, 0 + .dw 0xe140, 0xc31c, 0xe17f, 0xc31c, 0x21, 0 + .dw 0xe1c0, 0xc31c, 0xe1ff, 0xc31c, 0x21, 0 + .dw 0xe240, 0xc31c, 0xe27f, 0xc31c, 0x21, 0 + .dw 0xe2c0, 0xc31c, 0xe2ff, 0xc31c, 0x21, 0 + .dw 0xe340, 0xc31c, 0xe37f, 0xc31c, 0x21, 0 + .dw 0xe3c0, 0xc31c, 0xe3ff, 0xc31c, 0x21, 0 + .dw 0xe440, 0xc31c, 0xe47f, 0xc31c, 0x21, 0 + .dw 0xe4c0, 0xc31c, 0xe4ff, 0xc31c, 0x21, 0 + .dw 0xe540, 0xc31c, 0xe57f, 0xc31c, 0x21, 0 + .dw 0xe5c0, 0xc31c, 0xe5ff, 0xc31c, 0x21, 0 + .dw 0xe640, 0xc31c, 0xe67f, 0xc31c, 0x21, 0 + .dw 0xe6c0, 0xc31c, 0xe6ff, 0xc31c, 0x21, 0 + .dw 0xe740, 0xc31c, 0xe77f, 0xc31c, 0x21, 0 + .dw 0xe7c0, 0xc31c, 0x1fff, 0xc320, 0x21, 0 + .dw 0x2800, 0xc320, 0xffff, 0xc323, 0x21, 0 + .dw 0x0200, 0xc324, 0x1fff, 0xc324, 0x21, 0 + .dw 0x2800, 0xc324, 0x3fff, 0xc324, 0x21, 0 + .dw 0x4200, 0xc324, 0x5fff, 0xc324, 0x21, 0 + .dw 0x6800, 0xc324, 0x7fff, 0xc324, 0x21, 0 + .dw 0x8200, 0xc324, 0x9fff, 0xc324, 0x21, 0 + .dw 0xa800, 0xc324, 0xbfff, 0xc324, 0x21, 0 + .dw 0xc200, 0xc324, 0xdfff, 0xc324, 0x21, 0 + .dw 0xe800, 0xc324, 0x1fff, 0xc328, 0x21, 0 + .dw 0x2040, 0xc328, 0x207f, 0xc328, 0x21, 0 + .dw 0x20c0, 0xc328, 0x20ff, 0xc328, 0x21, 0 + .dw 0x2140, 0xc328, 0x217f, 0xc328, 0x21, 0 + .dw 0x21c0, 0xc328, 0x21ff, 0xc328, 0x21, 0 + .dw 0x2240, 0xc328, 0x227f, 0xc328, 0x21, 0 + .dw 0x22c0, 0xc328, 0x22ff, 0xc328, 0x21, 0 + .dw 0x2340, 0xc328, 0x237f, 0xc328, 0x21, 0 + .dw 0x23c0, 0xc328, 0x23ff, 0xc328, 0x21, 0 + .dw 0x2440, 0xc328, 0x247f, 0xc328, 0x21, 0 + .dw 0x24c0, 0xc328, 0x24ff, 0xc328, 0x21, 0 + .dw 0x2540, 0xc328, 0x257f, 0xc328, 0x21, 0 + .dw 0x25c0, 0xc328, 0x25ff, 0xc328, 0x21, 0 + .dw 0x2640, 0xc328, 0x267f, 0xc328, 0x21, 0 + .dw 0x26c0, 0xc328, 0x26ff, 0xc328, 0x21, 0 + .dw 0x2740, 0xc328, 0x277f, 0xc328, 0x21, 0 + .dw 0x27c0, 0xc328, 0xffff, 0xc32b, 0x21, 0 + .dw 0x0040, 0xc32c, 0x007f, 0xc32c, 0x21, 0 + .dw 0x00c0, 0xc32c, 0x00ff, 0xc32c, 0x21, 0 + .dw 0x0140, 0xc32c, 0x017f, 0xc32c, 0x21, 0 + .dw 0x01c0, 0xc32c, 0x1fff, 0xc32c, 0x21, 0 + .dw 0x2040, 0xc32c, 0x207f, 0xc32c, 0x21, 0 + .dw 0x20c0, 0xc32c, 0x20ff, 0xc32c, 0x21, 0 + .dw 0x2140, 0xc32c, 0x217f, 0xc32c, 0x21, 0 + .dw 0x21c0, 0xc32c, 0x21ff, 0xc32c, 0x21, 0 + .dw 0x2240, 0xc32c, 0x227f, 0xc32c, 0x21, 0 + .dw 0x22c0, 0xc32c, 0x22ff, 0xc32c, 0x21, 0 + .dw 0x2340, 0xc32c, 0x237f, 0xc32c, 0x21, 0 + .dw 0x23c0, 0xc32c, 0x23ff, 0xc32c, 0x21, 0 + .dw 0x2440, 0xc32c, 0x247f, 0xc32c, 0x21, 0 + .dw 0x24c0, 0xc32c, 0x24ff, 0xc32c, 0x21, 0 + .dw 0x2540, 0xc32c, 0x257f, 0xc32c, 0x21, 0 + .dw 0x25c0, 0xc32c, 0x25ff, 0xc32c, 0x21, 0 + .dw 0x2640, 0xc32c, 0x267f, 0xc32c, 0x21, 0 + .dw 0x26c0, 0xc32c, 0x26ff, 0xc32c, 0x21, 0 + .dw 0x2740, 0xc32c, 0x277f, 0xc32c, 0x21, 0 + .dw 0x27c0, 0xc32c, 0x3fff, 0xc32c, 0x21, 0 + .dw 0x4040, 0xc32c, 0x407f, 0xc32c, 0x21, 0 + .dw 0x40c0, 0xc32c, 0x40ff, 0xc32c, 0x21, 0 + .dw 0x4140, 0xc32c, 0x417f, 0xc32c, 0x21, 0 + .dw 0x41c0, 0xc32c, 0x5fff, 0xc32c, 0x21, 0 + .dw 0x6040, 0xc32c, 0x607f, 0xc32c, 0x21, 0 + .dw 0x60c0, 0xc32c, 0x60ff, 0xc32c, 0x21, 0 + .dw 0x6140, 0xc32c, 0x617f, 0xc32c, 0x21, 0 + .dw 0x61c0, 0xc32c, 0x61ff, 0xc32c, 0x21, 0 + .dw 0x6240, 0xc32c, 0x627f, 0xc32c, 0x21, 0 + .dw 0x62c0, 0xc32c, 0x62ff, 0xc32c, 0x21, 0 + .dw 0x6340, 0xc32c, 0x637f, 0xc32c, 0x21, 0 + .dw 0x63c0, 0xc32c, 0x63ff, 0xc32c, 0x21, 0 + .dw 0x6440, 0xc32c, 0x647f, 0xc32c, 0x21, 0 + .dw 0x64c0, 0xc32c, 0x64ff, 0xc32c, 0x21, 0 + .dw 0x6540, 0xc32c, 0x657f, 0xc32c, 0x21, 0 + .dw 0x65c0, 0xc32c, 0x65ff, 0xc32c, 0x21, 0 + .dw 0x6640, 0xc32c, 0x667f, 0xc32c, 0x21, 0 + .dw 0x66c0, 0xc32c, 0x66ff, 0xc32c, 0x21, 0 + .dw 0x6740, 0xc32c, 0x677f, 0xc32c, 0x21, 0 + .dw 0x67c0, 0xc32c, 0x7fff, 0xc32c, 0x21, 0 + .dw 0x8040, 0xc32c, 0x807f, 0xc32c, 0x21, 0 + .dw 0x80c0, 0xc32c, 0x80ff, 0xc32c, 0x21, 0 + .dw 0x8140, 0xc32c, 0x817f, 0xc32c, 0x21, 0 + .dw 0x81c0, 0xc32c, 0x9fff, 0xc32c, 0x21, 0 + .dw 0xa040, 0xc32c, 0xa07f, 0xc32c, 0x21, 0 + .dw 0xa0c0, 0xc32c, 0xa0ff, 0xc32c, 0x21, 0 + .dw 0xa140, 0xc32c, 0xa17f, 0xc32c, 0x21, 0 + .dw 0xa1c0, 0xc32c, 0xa1ff, 0xc32c, 0x21, 0 + .dw 0xa240, 0xc32c, 0xa27f, 0xc32c, 0x21, 0 + .dw 0xa2c0, 0xc32c, 0xa2ff, 0xc32c, 0x21, 0 + .dw 0xa340, 0xc32c, 0xa37f, 0xc32c, 0x21, 0 + .dw 0xa3c0, 0xc32c, 0xa3ff, 0xc32c, 0x21, 0 + .dw 0xa440, 0xc32c, 0xa47f, 0xc32c, 0x21, 0 + .dw 0xa4c0, 0xc32c, 0xa4ff, 0xc32c, 0x21, 0 + .dw 0xa540, 0xc32c, 0xa57f, 0xc32c, 0x21, 0 + .dw 0xa5c0, 0xc32c, 0xa5ff, 0xc32c, 0x21, 0 + .dw 0xa640, 0xc32c, 0xa67f, 0xc32c, 0x21, 0 + .dw 0xa6c0, 0xc32c, 0xa6ff, 0xc32c, 0x21, 0 + .dw 0xa740, 0xc32c, 0xa77f, 0xc32c, 0x21, 0 + .dw 0xa7c0, 0xc32c, 0xbfff, 0xc32c, 0x21, 0 + .dw 0xc040, 0xc32c, 0xc07f, 0xc32c, 0x21, 0 + .dw 0xc0c0, 0xc32c, 0xc0ff, 0xc32c, 0x21, 0 + .dw 0xc140, 0xc32c, 0xc17f, 0xc32c, 0x21, 0 + .dw 0xc1c0, 0xc32c, 0xdfff, 0xc32c, 0x21, 0 + .dw 0xe040, 0xc32c, 0xe07f, 0xc32c, 0x21, 0 + .dw 0xe0c0, 0xc32c, 0xe0ff, 0xc32c, 0x21, 0 + .dw 0xe140, 0xc32c, 0xe17f, 0xc32c, 0x21, 0 + .dw 0xe1c0, 0xc32c, 0xe1ff, 0xc32c, 0x21, 0 + .dw 0xe240, 0xc32c, 0xe27f, 0xc32c, 0x21, 0 + .dw 0xe2c0, 0xc32c, 0xe2ff, 0xc32c, 0x21, 0 + .dw 0xe340, 0xc32c, 0xe37f, 0xc32c, 0x21, 0 + .dw 0xe3c0, 0xc32c, 0xe3ff, 0xc32c, 0x21, 0 + .dw 0xe440, 0xc32c, 0xe47f, 0xc32c, 0x21, 0 + .dw 0xe4c0, 0xc32c, 0xe4ff, 0xc32c, 0x21, 0 + .dw 0xe540, 0xc32c, 0xe57f, 0xc32c, 0x21, 0 + .dw 0xe5c0, 0xc32c, 0xe5ff, 0xc32c, 0x21, 0 + .dw 0xe640, 0xc32c, 0xe67f, 0xc32c, 0x21, 0 + .dw 0xe6c0, 0xc32c, 0xe6ff, 0xc32c, 0x21, 0 + .dw 0xe740, 0xc32c, 0xe77f, 0xc32c, 0x21, 0 + .dw 0xe7c0, 0xc32c, 0xffff, 0xc333, 0x21, 0 + .dw 0x0200, 0xc334, 0x1fff, 0xc334, 0x21, 0 + .dw 0x2800, 0xc334, 0x3fff, 0xc334, 0x21, 0 + .dw 0x4200, 0xc334, 0x5fff, 0xc334, 0x21, 0 + .dw 0x6800, 0xc334, 0x7fff, 0xc334, 0x21, 0 + .dw 0x8200, 0xc334, 0x9fff, 0xc334, 0x21, 0 + .dw 0xa800, 0xc334, 0xbfff, 0xc334, 0x21, 0 + .dw 0xc200, 0xc334, 0xdfff, 0xc334, 0x21, 0 + .dw 0xe800, 0xc334, 0xffff, 0xc33b, 0x21, 0 + .dw 0x0040, 0xc33c, 0x007f, 0xc33c, 0x21, 0 + .dw 0x00c0, 0xc33c, 0x00ff, 0xc33c, 0x21, 0 + .dw 0x0140, 0xc33c, 0x017f, 0xc33c, 0x21, 0 + .dw 0x01c0, 0xc33c, 0x1fff, 0xc33c, 0x21, 0 + .dw 0x2040, 0xc33c, 0x207f, 0xc33c, 0x21, 0 + .dw 0x20c0, 0xc33c, 0x20ff, 0xc33c, 0x21, 0 + .dw 0x2140, 0xc33c, 0x217f, 0xc33c, 0x21, 0 + .dw 0x21c0, 0xc33c, 0x21ff, 0xc33c, 0x21, 0 + .dw 0x2240, 0xc33c, 0x227f, 0xc33c, 0x21, 0 + .dw 0x22c0, 0xc33c, 0x22ff, 0xc33c, 0x21, 0 + .dw 0x2340, 0xc33c, 0x237f, 0xc33c, 0x21, 0 + .dw 0x23c0, 0xc33c, 0x23ff, 0xc33c, 0x21, 0 + .dw 0x2440, 0xc33c, 0x247f, 0xc33c, 0x21, 0 + .dw 0x24c0, 0xc33c, 0x24ff, 0xc33c, 0x21, 0 + .dw 0x2540, 0xc33c, 0x257f, 0xc33c, 0x21, 0 + .dw 0x25c0, 0xc33c, 0x25ff, 0xc33c, 0x21, 0 + .dw 0x2640, 0xc33c, 0x267f, 0xc33c, 0x21, 0 + .dw 0x26c0, 0xc33c, 0x26ff, 0xc33c, 0x21, 0 + .dw 0x2740, 0xc33c, 0x277f, 0xc33c, 0x21, 0 + .dw 0x27c0, 0xc33c, 0x3fff, 0xc33c, 0x21, 0 + .dw 0x4040, 0xc33c, 0x407f, 0xc33c, 0x21, 0 + .dw 0x40c0, 0xc33c, 0x40ff, 0xc33c, 0x21, 0 + .dw 0x4140, 0xc33c, 0x417f, 0xc33c, 0x21, 0 + .dw 0x41c0, 0xc33c, 0x5fff, 0xc33c, 0x21, 0 + .dw 0x6040, 0xc33c, 0x607f, 0xc33c, 0x21, 0 + .dw 0x60c0, 0xc33c, 0x60ff, 0xc33c, 0x21, 0 + .dw 0x6140, 0xc33c, 0x617f, 0xc33c, 0x21, 0 + .dw 0x61c0, 0xc33c, 0x61ff, 0xc33c, 0x21, 0 + .dw 0x6240, 0xc33c, 0x627f, 0xc33c, 0x21, 0 + .dw 0x62c0, 0xc33c, 0x62ff, 0xc33c, 0x21, 0 + .dw 0x6340, 0xc33c, 0x637f, 0xc33c, 0x21, 0 + .dw 0x63c0, 0xc33c, 0x63ff, 0xc33c, 0x21, 0 + .dw 0x6440, 0xc33c, 0x647f, 0xc33c, 0x21, 0 + .dw 0x64c0, 0xc33c, 0x64ff, 0xc33c, 0x21, 0 + .dw 0x6540, 0xc33c, 0x657f, 0xc33c, 0x21, 0 + .dw 0x65c0, 0xc33c, 0x65ff, 0xc33c, 0x21, 0 + .dw 0x6640, 0xc33c, 0x667f, 0xc33c, 0x21, 0 + .dw 0x66c0, 0xc33c, 0x66ff, 0xc33c, 0x21, 0 + .dw 0x6740, 0xc33c, 0x677f, 0xc33c, 0x21, 0 + .dw 0x67c0, 0xc33c, 0x7fff, 0xc33c, 0x21, 0 + .dw 0x8040, 0xc33c, 0x807f, 0xc33c, 0x21, 0 + .dw 0x80c0, 0xc33c, 0x80ff, 0xc33c, 0x21, 0 + .dw 0x8140, 0xc33c, 0x817f, 0xc33c, 0x21, 0 + .dw 0x81c0, 0xc33c, 0x9fff, 0xc33c, 0x21, 0 + .dw 0xa040, 0xc33c, 0xa07f, 0xc33c, 0x21, 0 + .dw 0xa0c0, 0xc33c, 0xa0ff, 0xc33c, 0x21, 0 + .dw 0xa140, 0xc33c, 0xa17f, 0xc33c, 0x21, 0 + .dw 0xa1c0, 0xc33c, 0xa1ff, 0xc33c, 0x21, 0 + .dw 0xa240, 0xc33c, 0xa27f, 0xc33c, 0x21, 0 + .dw 0xa2c0, 0xc33c, 0xa2ff, 0xc33c, 0x21, 0 + .dw 0xa340, 0xc33c, 0xa37f, 0xc33c, 0x21, 0 + .dw 0xa3c0, 0xc33c, 0xa3ff, 0xc33c, 0x21, 0 + .dw 0xa440, 0xc33c, 0xa47f, 0xc33c, 0x21, 0 + .dw 0xa4c0, 0xc33c, 0xa4ff, 0xc33c, 0x21, 0 + .dw 0xa540, 0xc33c, 0xa57f, 0xc33c, 0x21, 0 + .dw 0xa5c0, 0xc33c, 0xa5ff, 0xc33c, 0x21, 0 + .dw 0xa640, 0xc33c, 0xa67f, 0xc33c, 0x21, 0 + .dw 0xa6c0, 0xc33c, 0xa6ff, 0xc33c, 0x21, 0 + .dw 0xa740, 0xc33c, 0xa77f, 0xc33c, 0x21, 0 + .dw 0xa7c0, 0xc33c, 0xbfff, 0xc33c, 0x21, 0 + .dw 0xc040, 0xc33c, 0xc07f, 0xc33c, 0x21, 0 + .dw 0xc0c0, 0xc33c, 0xc0ff, 0xc33c, 0x21, 0 + .dw 0xc140, 0xc33c, 0xc17f, 0xc33c, 0x21, 0 + .dw 0xc1c0, 0xc33c, 0xdfff, 0xc33c, 0x21, 0 + .dw 0xe040, 0xc33c, 0xe07f, 0xc33c, 0x21, 0 + .dw 0xe0c0, 0xc33c, 0xe0ff, 0xc33c, 0x21, 0 + .dw 0xe140, 0xc33c, 0xe17f, 0xc33c, 0x21, 0 + .dw 0xe1c0, 0xc33c, 0xe1ff, 0xc33c, 0x21, 0 + .dw 0xe240, 0xc33c, 0xe27f, 0xc33c, 0x21, 0 + .dw 0xe2c0, 0xc33c, 0xe2ff, 0xc33c, 0x21, 0 + .dw 0xe340, 0xc33c, 0xe37f, 0xc33c, 0x21, 0 + .dw 0xe3c0, 0xc33c, 0xe3ff, 0xc33c, 0x21, 0 + .dw 0xe440, 0xc33c, 0xe47f, 0xc33c, 0x21, 0 + .dw 0xe4c0, 0xc33c, 0xe4ff, 0xc33c, 0x21, 0 + .dw 0xe540, 0xc33c, 0xe57f, 0xc33c, 0x21, 0 + .dw 0xe5c0, 0xc33c, 0xe5ff, 0xc33c, 0x21, 0 + .dw 0xe640, 0xc33c, 0xe67f, 0xc33c, 0x21, 0 + .dw 0xe6c0, 0xc33c, 0xe6ff, 0xc33c, 0x21, 0 + .dw 0xe740, 0xc33c, 0xe77f, 0xc33c, 0x21, 0 + .dw 0xe7c0, 0xc33c, 0x1fff, 0xc360, 0x21, 0 + .dw 0x2800, 0xc360, 0xffff, 0xc363, 0x21, 0 + .dw 0x0200, 0xc364, 0x1fff, 0xc364, 0x21, 0 + .dw 0x2800, 0xc364, 0x3fff, 0xc364, 0x21, 0 + .dw 0x4200, 0xc364, 0x5fff, 0xc364, 0x21, 0 + .dw 0x6800, 0xc364, 0x7fff, 0xc364, 0x21, 0 + .dw 0x8200, 0xc364, 0x9fff, 0xc364, 0x21, 0 + .dw 0xa800, 0xc364, 0xbfff, 0xc364, 0x21, 0 + .dw 0xc200, 0xc364, 0xdfff, 0xc364, 0x21, 0 + .dw 0xe800, 0xc364, 0xffff, 0xc373, 0x21, 0 + .dw 0x0200, 0xc374, 0x1fff, 0xc374, 0x21, 0 + .dw 0x2800, 0xc374, 0x3fff, 0xc374, 0x21, 0 + .dw 0x4200, 0xc374, 0x5fff, 0xc374, 0x21, 0 + .dw 0x6800, 0xc374, 0x7fff, 0xc374, 0x21, 0 + .dw 0x8200, 0xc374, 0x9fff, 0xc374, 0x21, 0 + .dw 0xa800, 0xc374, 0xbfff, 0xc374, 0x21, 0 + .dw 0xc200, 0xc374, 0xdfff, 0xc374, 0x21, 0 + .dw 0xe800, 0xc374, 0x1fff, 0xc380, 0x21, 0 + .dw 0x2800, 0xc380, 0xffff, 0xc383, 0x21, 0 + .dw 0x0200, 0xc384, 0x1fff, 0xc384, 0x21, 0 + .dw 0x2800, 0xc384, 0x3fff, 0xc384, 0x21, 0 + .dw 0x4200, 0xc384, 0x5fff, 0xc384, 0x21, 0 + .dw 0x6800, 0xc384, 0x7fff, 0xc384, 0x21, 0 + .dw 0x8200, 0xc384, 0x9fff, 0xc384, 0x21, 0 + .dw 0xa800, 0xc384, 0xbfff, 0xc384, 0x21, 0 + .dw 0xc200, 0xc384, 0xdfff, 0xc384, 0x21, 0 + .dw 0xe800, 0xc384, 0x1fff, 0xc388, 0x21, 0 + .dw 0x2040, 0xc388, 0x207f, 0xc388, 0x21, 0 + .dw 0x20c0, 0xc388, 0x20ff, 0xc388, 0x21, 0 + .dw 0x2140, 0xc388, 0x217f, 0xc388, 0x21, 0 + .dw 0x21c0, 0xc388, 0x21ff, 0xc388, 0x21, 0 + .dw 0x2240, 0xc388, 0x227f, 0xc388, 0x21, 0 + .dw 0x22c0, 0xc388, 0x22ff, 0xc388, 0x21, 0 + .dw 0x2340, 0xc388, 0x237f, 0xc388, 0x21, 0 + .dw 0x23c0, 0xc388, 0x23ff, 0xc388, 0x21, 0 + .dw 0x2440, 0xc388, 0x247f, 0xc388, 0x21, 0 + .dw 0x24c0, 0xc388, 0x24ff, 0xc388, 0x21, 0 + .dw 0x2540, 0xc388, 0x257f, 0xc388, 0x21, 0 + .dw 0x25c0, 0xc388, 0x25ff, 0xc388, 0x21, 0 + .dw 0x2640, 0xc388, 0x267f, 0xc388, 0x21, 0 + .dw 0x26c0, 0xc388, 0x26ff, 0xc388, 0x21, 0 + .dw 0x2740, 0xc388, 0x277f, 0xc388, 0x21, 0 + .dw 0x27c0, 0xc388, 0xffff, 0xc38b, 0x21, 0 + .dw 0x0040, 0xc38c, 0x007f, 0xc38c, 0x21, 0 + .dw 0x00c0, 0xc38c, 0x00ff, 0xc38c, 0x21, 0 + .dw 0x0140, 0xc38c, 0x017f, 0xc38c, 0x21, 0 + .dw 0x01c0, 0xc38c, 0x1fff, 0xc38c, 0x21, 0 + .dw 0x2040, 0xc38c, 0x207f, 0xc38c, 0x21, 0 + .dw 0x20c0, 0xc38c, 0x20ff, 0xc38c, 0x21, 0 + .dw 0x2140, 0xc38c, 0x217f, 0xc38c, 0x21, 0 + .dw 0x21c0, 0xc38c, 0x21ff, 0xc38c, 0x21, 0 + .dw 0x2240, 0xc38c, 0x227f, 0xc38c, 0x21, 0 + .dw 0x22c0, 0xc38c, 0x22ff, 0xc38c, 0x21, 0 + .dw 0x2340, 0xc38c, 0x237f, 0xc38c, 0x21, 0 + .dw 0x23c0, 0xc38c, 0x23ff, 0xc38c, 0x21, 0 + .dw 0x2440, 0xc38c, 0x247f, 0xc38c, 0x21, 0 + .dw 0x24c0, 0xc38c, 0x24ff, 0xc38c, 0x21, 0 + .dw 0x2540, 0xc38c, 0x257f, 0xc38c, 0x21, 0 + .dw 0x25c0, 0xc38c, 0x25ff, 0xc38c, 0x21, 0 + .dw 0x2640, 0xc38c, 0x267f, 0xc38c, 0x21, 0 + .dw 0x26c0, 0xc38c, 0x26ff, 0xc38c, 0x21, 0 + .dw 0x2740, 0xc38c, 0x277f, 0xc38c, 0x21, 0 + .dw 0x27c0, 0xc38c, 0x3fff, 0xc38c, 0x21, 0 + .dw 0x4040, 0xc38c, 0x407f, 0xc38c, 0x21, 0 + .dw 0x40c0, 0xc38c, 0x40ff, 0xc38c, 0x21, 0 + .dw 0x4140, 0xc38c, 0x417f, 0xc38c, 0x21, 0 + .dw 0x41c0, 0xc38c, 0x5fff, 0xc38c, 0x21, 0 + .dw 0x6040, 0xc38c, 0x607f, 0xc38c, 0x21, 0 + .dw 0x60c0, 0xc38c, 0x60ff, 0xc38c, 0x21, 0 + .dw 0x6140, 0xc38c, 0x617f, 0xc38c, 0x21, 0 + .dw 0x61c0, 0xc38c, 0x61ff, 0xc38c, 0x21, 0 + .dw 0x6240, 0xc38c, 0x627f, 0xc38c, 0x21, 0 + .dw 0x62c0, 0xc38c, 0x62ff, 0xc38c, 0x21, 0 + .dw 0x6340, 0xc38c, 0x637f, 0xc38c, 0x21, 0 + .dw 0x63c0, 0xc38c, 0x63ff, 0xc38c, 0x21, 0 + .dw 0x6440, 0xc38c, 0x647f, 0xc38c, 0x21, 0 + .dw 0x64c0, 0xc38c, 0x64ff, 0xc38c, 0x21, 0 + .dw 0x6540, 0xc38c, 0x657f, 0xc38c, 0x21, 0 + .dw 0x65c0, 0xc38c, 0x65ff, 0xc38c, 0x21, 0 + .dw 0x6640, 0xc38c, 0x667f, 0xc38c, 0x21, 0 + .dw 0x66c0, 0xc38c, 0x66ff, 0xc38c, 0x21, 0 + .dw 0x6740, 0xc38c, 0x677f, 0xc38c, 0x21, 0 + .dw 0x67c0, 0xc38c, 0x7fff, 0xc38c, 0x21, 0 + .dw 0x8040, 0xc38c, 0x807f, 0xc38c, 0x21, 0 + .dw 0x80c0, 0xc38c, 0x80ff, 0xc38c, 0x21, 0 + .dw 0x8140, 0xc38c, 0x817f, 0xc38c, 0x21, 0 + .dw 0x81c0, 0xc38c, 0x9fff, 0xc38c, 0x21, 0 + .dw 0xa040, 0xc38c, 0xa07f, 0xc38c, 0x21, 0 + .dw 0xa0c0, 0xc38c, 0xa0ff, 0xc38c, 0x21, 0 + .dw 0xa140, 0xc38c, 0xa17f, 0xc38c, 0x21, 0 + .dw 0xa1c0, 0xc38c, 0xa1ff, 0xc38c, 0x21, 0 + .dw 0xa240, 0xc38c, 0xa27f, 0xc38c, 0x21, 0 + .dw 0xa2c0, 0xc38c, 0xa2ff, 0xc38c, 0x21, 0 + .dw 0xa340, 0xc38c, 0xa37f, 0xc38c, 0x21, 0 + .dw 0xa3c0, 0xc38c, 0xa3ff, 0xc38c, 0x21, 0 + .dw 0xa440, 0xc38c, 0xa47f, 0xc38c, 0x21, 0 + .dw 0xa4c0, 0xc38c, 0xa4ff, 0xc38c, 0x21, 0 + .dw 0xa540, 0xc38c, 0xa57f, 0xc38c, 0x21, 0 + .dw 0xa5c0, 0xc38c, 0xa5ff, 0xc38c, 0x21, 0 + .dw 0xa640, 0xc38c, 0xa67f, 0xc38c, 0x21, 0 + .dw 0xa6c0, 0xc38c, 0xa6ff, 0xc38c, 0x21, 0 + .dw 0xa740, 0xc38c, 0xa77f, 0xc38c, 0x21, 0 + .dw 0xa7c0, 0xc38c, 0xbfff, 0xc38c, 0x21, 0 + .dw 0xc040, 0xc38c, 0xc07f, 0xc38c, 0x21, 0 + .dw 0xc0c0, 0xc38c, 0xc0ff, 0xc38c, 0x21, 0 + .dw 0xc140, 0xc38c, 0xc17f, 0xc38c, 0x21, 0 + .dw 0xc1c0, 0xc38c, 0xdfff, 0xc38c, 0x21, 0 + .dw 0xe040, 0xc38c, 0xe07f, 0xc38c, 0x21, 0 + .dw 0xe0c0, 0xc38c, 0xe0ff, 0xc38c, 0x21, 0 + .dw 0xe140, 0xc38c, 0xe17f, 0xc38c, 0x21, 0 + .dw 0xe1c0, 0xc38c, 0xe1ff, 0xc38c, 0x21, 0 + .dw 0xe240, 0xc38c, 0xe27f, 0xc38c, 0x21, 0 + .dw 0xe2c0, 0xc38c, 0xe2ff, 0xc38c, 0x21, 0 + .dw 0xe340, 0xc38c, 0xe37f, 0xc38c, 0x21, 0 + .dw 0xe3c0, 0xc38c, 0xe3ff, 0xc38c, 0x21, 0 + .dw 0xe440, 0xc38c, 0xe47f, 0xc38c, 0x21, 0 + .dw 0xe4c0, 0xc38c, 0xe4ff, 0xc38c, 0x21, 0 + .dw 0xe540, 0xc38c, 0xe57f, 0xc38c, 0x21, 0 + .dw 0xe5c0, 0xc38c, 0xe5ff, 0xc38c, 0x21, 0 + .dw 0xe640, 0xc38c, 0xe67f, 0xc38c, 0x21, 0 + .dw 0xe6c0, 0xc38c, 0xe6ff, 0xc38c, 0x21, 0 + .dw 0xe740, 0xc38c, 0xe77f, 0xc38c, 0x21, 0 + .dw 0xe7c0, 0xc38c, 0xffff, 0xc393, 0x21, 0 + .dw 0x0200, 0xc394, 0x1fff, 0xc394, 0x21, 0 + .dw 0x2800, 0xc394, 0x3fff, 0xc394, 0x21, 0 + .dw 0x4200, 0xc394, 0x5fff, 0xc394, 0x21, 0 + .dw 0x6800, 0xc394, 0x7fff, 0xc394, 0x21, 0 + .dw 0x8200, 0xc394, 0x9fff, 0xc394, 0x21, 0 + .dw 0xa800, 0xc394, 0xbfff, 0xc394, 0x21, 0 + .dw 0xc200, 0xc394, 0xdfff, 0xc394, 0x21, 0 + .dw 0xe800, 0xc394, 0xffff, 0xc39b, 0x21, 0 + .dw 0x0040, 0xc39c, 0x007f, 0xc39c, 0x21, 0 + .dw 0x00c0, 0xc39c, 0x00ff, 0xc39c, 0x21, 0 + .dw 0x0140, 0xc39c, 0x017f, 0xc39c, 0x21, 0 + .dw 0x01c0, 0xc39c, 0x1fff, 0xc39c, 0x21, 0 + .dw 0x2040, 0xc39c, 0x207f, 0xc39c, 0x21, 0 + .dw 0x20c0, 0xc39c, 0x20ff, 0xc39c, 0x21, 0 + .dw 0x2140, 0xc39c, 0x217f, 0xc39c, 0x21, 0 + .dw 0x21c0, 0xc39c, 0x21ff, 0xc39c, 0x21, 0 + .dw 0x2240, 0xc39c, 0x227f, 0xc39c, 0x21, 0 + .dw 0x22c0, 0xc39c, 0x22ff, 0xc39c, 0x21, 0 + .dw 0x2340, 0xc39c, 0x237f, 0xc39c, 0x21, 0 + .dw 0x23c0, 0xc39c, 0x23ff, 0xc39c, 0x21, 0 + .dw 0x2440, 0xc39c, 0x247f, 0xc39c, 0x21, 0 + .dw 0x24c0, 0xc39c, 0x24ff, 0xc39c, 0x21, 0 + .dw 0x2540, 0xc39c, 0x257f, 0xc39c, 0x21, 0 + .dw 0x25c0, 0xc39c, 0x25ff, 0xc39c, 0x21, 0 + .dw 0x2640, 0xc39c, 0x267f, 0xc39c, 0x21, 0 + .dw 0x26c0, 0xc39c, 0x26ff, 0xc39c, 0x21, 0 + .dw 0x2740, 0xc39c, 0x277f, 0xc39c, 0x21, 0 + .dw 0x27c0, 0xc39c, 0x3fff, 0xc39c, 0x21, 0 + .dw 0x4040, 0xc39c, 0x407f, 0xc39c, 0x21, 0 + .dw 0x40c0, 0xc39c, 0x40ff, 0xc39c, 0x21, 0 + .dw 0x4140, 0xc39c, 0x417f, 0xc39c, 0x21, 0 + .dw 0x41c0, 0xc39c, 0x5fff, 0xc39c, 0x21, 0 + .dw 0x6040, 0xc39c, 0x607f, 0xc39c, 0x21, 0 + .dw 0x60c0, 0xc39c, 0x60ff, 0xc39c, 0x21, 0 + .dw 0x6140, 0xc39c, 0x617f, 0xc39c, 0x21, 0 + .dw 0x61c0, 0xc39c, 0x61ff, 0xc39c, 0x21, 0 + .dw 0x6240, 0xc39c, 0x627f, 0xc39c, 0x21, 0 + .dw 0x62c0, 0xc39c, 0x62ff, 0xc39c, 0x21, 0 + .dw 0x6340, 0xc39c, 0x637f, 0xc39c, 0x21, 0 + .dw 0x63c0, 0xc39c, 0x63ff, 0xc39c, 0x21, 0 + .dw 0x6440, 0xc39c, 0x647f, 0xc39c, 0x21, 0 + .dw 0x64c0, 0xc39c, 0x64ff, 0xc39c, 0x21, 0 + .dw 0x6540, 0xc39c, 0x657f, 0xc39c, 0x21, 0 + .dw 0x65c0, 0xc39c, 0x65ff, 0xc39c, 0x21, 0 + .dw 0x6640, 0xc39c, 0x667f, 0xc39c, 0x21, 0 + .dw 0x66c0, 0xc39c, 0x66ff, 0xc39c, 0x21, 0 + .dw 0x6740, 0xc39c, 0x677f, 0xc39c, 0x21, 0 + .dw 0x67c0, 0xc39c, 0x7fff, 0xc39c, 0x21, 0 + .dw 0x8040, 0xc39c, 0x807f, 0xc39c, 0x21, 0 + .dw 0x80c0, 0xc39c, 0x80ff, 0xc39c, 0x21, 0 + .dw 0x8140, 0xc39c, 0x817f, 0xc39c, 0x21, 0 + .dw 0x81c0, 0xc39c, 0x9fff, 0xc39c, 0x21, 0 + .dw 0xa040, 0xc39c, 0xa07f, 0xc39c, 0x21, 0 + .dw 0xa0c0, 0xc39c, 0xa0ff, 0xc39c, 0x21, 0 + .dw 0xa140, 0xc39c, 0xa17f, 0xc39c, 0x21, 0 + .dw 0xa1c0, 0xc39c, 0xa1ff, 0xc39c, 0x21, 0 + .dw 0xa240, 0xc39c, 0xa27f, 0xc39c, 0x21, 0 + .dw 0xa2c0, 0xc39c, 0xa2ff, 0xc39c, 0x21, 0 + .dw 0xa340, 0xc39c, 0xa37f, 0xc39c, 0x21, 0 + .dw 0xa3c0, 0xc39c, 0xa3ff, 0xc39c, 0x21, 0 + .dw 0xa440, 0xc39c, 0xa47f, 0xc39c, 0x21, 0 + .dw 0xa4c0, 0xc39c, 0xa4ff, 0xc39c, 0x21, 0 + .dw 0xa540, 0xc39c, 0xa57f, 0xc39c, 0x21, 0 + .dw 0xa5c0, 0xc39c, 0xa5ff, 0xc39c, 0x21, 0 + .dw 0xa640, 0xc39c, 0xa67f, 0xc39c, 0x21, 0 + .dw 0xa6c0, 0xc39c, 0xa6ff, 0xc39c, 0x21, 0 + .dw 0xa740, 0xc39c, 0xa77f, 0xc39c, 0x21, 0 + .dw 0xa7c0, 0xc39c, 0xbfff, 0xc39c, 0x21, 0 + .dw 0xc040, 0xc39c, 0xc07f, 0xc39c, 0x21, 0 + .dw 0xc0c0, 0xc39c, 0xc0ff, 0xc39c, 0x21, 0 + .dw 0xc140, 0xc39c, 0xc17f, 0xc39c, 0x21, 0 + .dw 0xc1c0, 0xc39c, 0xdfff, 0xc39c, 0x21, 0 + .dw 0xe040, 0xc39c, 0xe07f, 0xc39c, 0x21, 0 + .dw 0xe0c0, 0xc39c, 0xe0ff, 0xc39c, 0x21, 0 + .dw 0xe140, 0xc39c, 0xe17f, 0xc39c, 0x21, 0 + .dw 0xe1c0, 0xc39c, 0xe1ff, 0xc39c, 0x21, 0 + .dw 0xe240, 0xc39c, 0xe27f, 0xc39c, 0x21, 0 + .dw 0xe2c0, 0xc39c, 0xe2ff, 0xc39c, 0x21, 0 + .dw 0xe340, 0xc39c, 0xe37f, 0xc39c, 0x21, 0 + .dw 0xe3c0, 0xc39c, 0xe3ff, 0xc39c, 0x21, 0 + .dw 0xe440, 0xc39c, 0xe47f, 0xc39c, 0x21, 0 + .dw 0xe4c0, 0xc39c, 0xe4ff, 0xc39c, 0x21, 0 + .dw 0xe540, 0xc39c, 0xe57f, 0xc39c, 0x21, 0 + .dw 0xe5c0, 0xc39c, 0xe5ff, 0xc39c, 0x21, 0 + .dw 0xe640, 0xc39c, 0xe67f, 0xc39c, 0x21, 0 + .dw 0xe6c0, 0xc39c, 0xe6ff, 0xc39c, 0x21, 0 + .dw 0xe740, 0xc39c, 0xe77f, 0xc39c, 0x21, 0 + .dw 0xe7c0, 0xc39c, 0xffff, 0xc3ff, 0x21, 0 + .dw 0x0000, 0xc401, 0x003f, 0xc401, 0x22, 0 + .dw 0x0240, 0xc401, 0x027f, 0xc401, 0x22, 0 + .dw 0x0480, 0xc401, 0x04bf, 0xc401, 0x22, 0 + .dw 0x06c0, 0xc401, 0x06ff, 0xc401, 0x22, 0 + .dw 0x0900, 0xc401, 0x093f, 0xc401, 0x22, 0 + .dw 0x0b40, 0xc401, 0x0b7f, 0xc401, 0x22, 0 + .dw 0x0d80, 0xc401, 0x0dbf, 0xc401, 0x22, 0 + .dw 0x0fc0, 0xc401, 0x103f, 0xc401, 0x22, 0 + .dw 0x1240, 0xc401, 0x127f, 0xc401, 0x22, 0 + .dw 0x1480, 0xc401, 0x14bf, 0xc401, 0x22, 0 + .dw 0x16c0, 0xc401, 0x16ff, 0xc401, 0x22, 0 + .dw 0x1900, 0xc401, 0x193f, 0xc401, 0x22, 0 + .dw 0x1b40, 0xc401, 0x1b7f, 0xc401, 0x22, 0 + .dw 0x1d80, 0xc401, 0x1dbf, 0xc401, 0x22, 0 + .dw 0x1fc0, 0xc401, 0x203f, 0xc401, 0x22, 0 + .dw 0x2240, 0xc401, 0x227f, 0xc401, 0x22, 0 + .dw 0x2480, 0xc401, 0x24bf, 0xc401, 0x22, 0 + .dw 0x26c0, 0xc401, 0x26ff, 0xc401, 0x22, 0 + .dw 0x2900, 0xc401, 0x293f, 0xc401, 0x22, 0 + .dw 0x2b40, 0xc401, 0x2b7f, 0xc401, 0x22, 0 + .dw 0x2d80, 0xc401, 0x2dbf, 0xc401, 0x22, 0 + .dw 0x2fc0, 0xc401, 0x303f, 0xc401, 0x22, 0 + .dw 0x3240, 0xc401, 0x327f, 0xc401, 0x22, 0 + .dw 0x3480, 0xc401, 0x34bf, 0xc401, 0x22, 0 + .dw 0x36c0, 0xc401, 0x36ff, 0xc401, 0x22, 0 + .dw 0x3900, 0xc401, 0x393f, 0xc401, 0x22, 0 + .dw 0x3b40, 0xc401, 0x3b7f, 0xc401, 0x22, 0 + .dw 0x3d80, 0xc401, 0x3dbf, 0xc401, 0x22, 0 + .dw 0x3fc0, 0xc401, 0x3fff, 0xc401, 0x22, 0 + .dw 0x4000, 0xc401, 0x7fff, 0xc401, 0x21, 0 + .dw 0x8000, 0xc401, 0x803f, 0xc401, 0x22, 0 + .dw 0x8240, 0xc401, 0x827f, 0xc401, 0x22, 0 + .dw 0x8480, 0xc401, 0x84bf, 0xc401, 0x22, 0 + .dw 0x86c0, 0xc401, 0x86ff, 0xc401, 0x22, 0 + .dw 0x8900, 0xc401, 0x893f, 0xc401, 0x22, 0 + .dw 0x8b40, 0xc401, 0x8b7f, 0xc401, 0x22, 0 + .dw 0x8d80, 0xc401, 0x8dbf, 0xc401, 0x22, 0 + .dw 0x8fc0, 0xc401, 0x903f, 0xc401, 0x22, 0 + .dw 0x9240, 0xc401, 0x927f, 0xc401, 0x22, 0 + .dw 0x9480, 0xc401, 0x94bf, 0xc401, 0x22, 0 + .dw 0x96c0, 0xc401, 0x96ff, 0xc401, 0x22, 0 + .dw 0x9900, 0xc401, 0x993f, 0xc401, 0x22, 0 + .dw 0x9b40, 0xc401, 0x9b7f, 0xc401, 0x22, 0 + .dw 0x9d80, 0xc401, 0x9dbf, 0xc401, 0x22, 0 + .dw 0x9fc0, 0xc401, 0xa03f, 0xc401, 0x22, 0 + .dw 0xa240, 0xc401, 0xa27f, 0xc401, 0x22, 0 + .dw 0xa480, 0xc401, 0xa4bf, 0xc401, 0x22, 0 + .dw 0xa6c0, 0xc401, 0xa6ff, 0xc401, 0x22, 0 + .dw 0xa900, 0xc401, 0xa93f, 0xc401, 0x22, 0 + .dw 0xab40, 0xc401, 0xab7f, 0xc401, 0x22, 0 + .dw 0xad80, 0xc401, 0xadbf, 0xc401, 0x22, 0 + .dw 0xafc0, 0xc401, 0xb03f, 0xc401, 0x22, 0 + .dw 0xb240, 0xc401, 0xb27f, 0xc401, 0x22, 0 + .dw 0xb480, 0xc401, 0xb4bf, 0xc401, 0x22, 0 + .dw 0xb6c0, 0xc401, 0xb6ff, 0xc401, 0x22, 0 + .dw 0xb900, 0xc401, 0xb93f, 0xc401, 0x22, 0 + .dw 0xbb40, 0xc401, 0xbb7f, 0xc401, 0x22, 0 + .dw 0xbd80, 0xc401, 0xbdbf, 0xc401, 0x22, 0 + .dw 0xbfc0, 0xc401, 0xc03f, 0xc401, 0x22, 0 + .dw 0xc240, 0xc401, 0xc27f, 0xc401, 0x22, 0 + .dw 0xc480, 0xc401, 0xc4bf, 0xc401, 0x22, 0 + .dw 0xc6c0, 0xc401, 0xc6ff, 0xc401, 0x22, 0 + .dw 0xc900, 0xc401, 0xc93f, 0xc401, 0x22, 0 + .dw 0xcb40, 0xc401, 0xcb7f, 0xc401, 0x22, 0 + .dw 0xcd80, 0xc401, 0xcdbf, 0xc401, 0x22, 0 + .dw 0xcfc0, 0xc401, 0xd03f, 0xc401, 0x22, 0 + .dw 0xd240, 0xc401, 0xd27f, 0xc401, 0x22, 0 + .dw 0xd480, 0xc401, 0xd4bf, 0xc401, 0x22, 0 + .dw 0xd6c0, 0xc401, 0xd6ff, 0xc401, 0x22, 0 + .dw 0xd900, 0xc401, 0xd93f, 0xc401, 0x22, 0 + .dw 0xdb40, 0xc401, 0xdb7f, 0xc401, 0x22, 0 + .dw 0xdd80, 0xc401, 0xddbf, 0xc401, 0x22, 0 + .dw 0xdfc0, 0xc401, 0xe03f, 0xc401, 0x22, 0 + .dw 0xe240, 0xc401, 0xe27f, 0xc401, 0x22, 0 + .dw 0xe480, 0xc401, 0xe4bf, 0xc401, 0x22, 0 + .dw 0xe6c0, 0xc401, 0xe6ff, 0xc401, 0x22, 0 + .dw 0xe900, 0xc401, 0xe93f, 0xc401, 0x22, 0 + .dw 0xeb40, 0xc401, 0xeb7f, 0xc401, 0x22, 0 + .dw 0xed80, 0xc401, 0xedbf, 0xc401, 0x22, 0 + .dw 0xefc0, 0xc401, 0xf03f, 0xc401, 0x22, 0 + .dw 0xf240, 0xc401, 0xf27f, 0xc401, 0x22, 0 + .dw 0xf480, 0xc401, 0xf4bf, 0xc401, 0x22, 0 + .dw 0xf6c0, 0xc401, 0xf6ff, 0xc401, 0x22, 0 + .dw 0xf900, 0xc401, 0xf93f, 0xc401, 0x22, 0 + .dw 0xfb40, 0xc401, 0xfb7f, 0xc401, 0x22, 0 + .dw 0xfd80, 0xc401, 0xfdbf, 0xc401, 0x22, 0 + .dw 0xffc0, 0xc401, 0xffff, 0xc401, 0x22, 0 + .dw 0x1000, 0xc402, 0x1fff, 0xc402, 0x21, 0 + .dw 0x3000, 0xc402, 0x3fff, 0xc402, 0x21, 0 + .dw 0x5000, 0xc402, 0x5fff, 0xc402, 0x21, 0 + .dw 0x7000, 0xc402, 0x7fff, 0xc402, 0x21, 0 + .dw 0x9000, 0xc402, 0x9fff, 0xc402, 0x21, 0 + .dw 0xb000, 0xc402, 0xbfff, 0xc402, 0x21, 0 + .dw 0xd000, 0xc402, 0xdfff, 0xc402, 0x21, 0 + .dw 0xf000, 0xc402, 0xffff, 0xc402, 0x21, 0 + .dw 0x1000, 0xc403, 0x1fff, 0xc403, 0x21, 0 + .dw 0x3000, 0xc403, 0x3fff, 0xc403, 0x21, 0 + .dw 0x5000, 0xc403, 0x5fff, 0xc403, 0x21, 0 + .dw 0x7000, 0xc403, 0x7fff, 0xc403, 0x21, 0 + .dw 0x9000, 0xc403, 0x9fff, 0xc403, 0x21, 0 + .dw 0xb000, 0xc403, 0xbfff, 0xc403, 0x21, 0 + .dw 0xd000, 0xc403, 0xdfff, 0xc403, 0x21, 0 + .dw 0xf000, 0xc403, 0xffff, 0xc403, 0x21, 0 + .dw 0x1000, 0xc404, 0x1fff, 0xc404, 0x21, 0 + .dw 0x3000, 0xc404, 0x3fff, 0xc404, 0x21, 0 + .dw 0x5000, 0xc404, 0x5fff, 0xc404, 0x21, 0 + .dw 0x7000, 0xc404, 0x7fff, 0xc404, 0x21, 0 + .dw 0x8000, 0xc404, 0x803f, 0xc404, 0x22, 0 + .dw 0x8240, 0xc404, 0x827f, 0xc404, 0x22, 0 + .dw 0x8480, 0xc404, 0x84bf, 0xc404, 0x22, 0 + .dw 0x86c0, 0xc404, 0x86ff, 0xc404, 0x22, 0 + .dw 0x8900, 0xc404, 0x893f, 0xc404, 0x22, 0 + .dw 0x8b40, 0xc404, 0x8b7f, 0xc404, 0x22, 0 + .dw 0x8d80, 0xc404, 0x8dbf, 0xc404, 0x22, 0 + .dw 0x8fc0, 0xc404, 0x8fff, 0xc404, 0x22, 0 + .dw 0x9000, 0xc404, 0x9fff, 0xc404, 0x21, 0 + .dw 0xa000, 0xc404, 0xa03f, 0xc404, 0x22, 0 + .dw 0xa240, 0xc404, 0xa27f, 0xc404, 0x22, 0 + .dw 0xa480, 0xc404, 0xa4bf, 0xc404, 0x22, 0 + .dw 0xa6c0, 0xc404, 0xa6ff, 0xc404, 0x22, 0 + .dw 0xa900, 0xc404, 0xa93f, 0xc404, 0x22, 0 + .dw 0xab40, 0xc404, 0xab7f, 0xc404, 0x22, 0 + .dw 0xad80, 0xc404, 0xadbf, 0xc404, 0x22, 0 + .dw 0xafc0, 0xc404, 0xafff, 0xc404, 0x22, 0 + .dw 0xb000, 0xc404, 0xffff, 0xc404, 0x21, 0 + .dw 0x1000, 0xc405, 0x3fff, 0xc405, 0x21, 0 + .dw 0x5000, 0xc405, 0x8fff, 0xc405, 0x21, 0 + .dw 0xa000, 0xc405, 0xcfff, 0xc405, 0x21, 0 + .dw 0xe000, 0xc405, 0xffff, 0xc405, 0x21, 0 + .dw 0x1000, 0xc406, 0x3fff, 0xc406, 0x21, 0 + .dw 0x5000, 0xc406, 0x7fff, 0xc406, 0x21, 0 + .dw 0x9000, 0xc406, 0xffff, 0xc406, 0x21, 0 + .dw 0x1000, 0xc407, 0x3fff, 0xc407, 0x21, 0 + .dw 0x5000, 0xc407, 0x7fff, 0xc407, 0x21, 0 + .dw 0x9000, 0xc407, 0xbfff, 0xc407, 0x21, 0 + .dw 0xd000, 0xc407, 0xdfff, 0xc407, 0x21, 0 + .dw 0xf000, 0xc407, 0xffff, 0xc407, 0x21, 0 + .dw 0x1000, 0xc408, 0x1fff, 0xc408, 0x21, 0 + .dw 0x3000, 0xc408, 0x3fff, 0xc408, 0x21, 0 + .dw 0x5000, 0xc408, 0x5fff, 0xc408, 0x21, 0 + .dw 0x7000, 0xc408, 0x7fff, 0xc408, 0x21, 0 + .dw 0x9000, 0xc408, 0x9fff, 0xc408, 0x21, 0 + .dw 0xb000, 0xc408, 0xbfff, 0xc408, 0x21, 0 + .dw 0xd000, 0xc408, 0xdfff, 0xc408, 0x21, 0 + .dw 0xf000, 0xc408, 0xffff, 0xc408, 0x21, 0 + .dw 0x1000, 0xc409, 0x1fff, 0xc409, 0x21, 0 + .dw 0x3000, 0xc409, 0x3fff, 0xc409, 0x21, 0 + .dw 0x5000, 0xc409, 0x7fff, 0xc409, 0x21, 0 + .dw 0x9000, 0xc409, 0x9fff, 0xc409, 0x21, 0 + .dw 0xb000, 0xc409, 0xbfff, 0xc409, 0x21, 0 + .dw 0xd000, 0xc409, 0xffff, 0xc409, 0x21, 0 + .dw 0x1000, 0xc40a, 0x3fff, 0xc40a, 0x21, 0 + .dw 0x5000, 0xc40a, 0xffff, 0xc40a, 0x21, 0 + .dw 0x1000, 0xc40b, 0x3fff, 0xc40b, 0x21, 0 + .dw 0x5000, 0xc40b, 0x7fff, 0xc40b, 0x21, 0 + .dw 0x9000, 0xc40b, 0x9fff, 0xc40b, 0x21, 0 + .dw 0xb000, 0xc40b, 0xbfff, 0xc40b, 0x21, 0 + .dw 0xd000, 0xc40b, 0xdfff, 0xc40b, 0x21, 0 + .dw 0xf000, 0xc40b, 0xffff, 0xc40b, 0x21, 0 + .dw 0x1000, 0xc40c, 0x3fff, 0xc40c, 0x21, 0 + .dw 0x4000, 0xc40c, 0x403f, 0xc40c, 0x22, 0 + .dw 0x4240, 0xc40c, 0x427f, 0xc40c, 0x22, 0 + .dw 0x4480, 0xc40c, 0x44bf, 0xc40c, 0x22, 0 + .dw 0x46c0, 0xc40c, 0x46ff, 0xc40c, 0x22, 0 + .dw 0x4900, 0xc40c, 0x493f, 0xc40c, 0x22, 0 + .dw 0x4b40, 0xc40c, 0x4b7f, 0xc40c, 0x22, 0 + .dw 0x4d80, 0xc40c, 0x4dbf, 0xc40c, 0x22, 0 + .dw 0x4fc0, 0xc40c, 0x4fff, 0xc40c, 0x22, 0 + .dw 0x5000, 0xc40c, 0xbfff, 0xc40c, 0x21, 0 + .dw 0xd000, 0xc40c, 0xffff, 0xc40c, 0x21, 0 + .dw 0x0000, 0xc40d, 0x003f, 0xc40d, 0x22, 0 + .dw 0x0240, 0xc40d, 0x027f, 0xc40d, 0x22, 0 + .dw 0x0480, 0xc40d, 0x04bf, 0xc40d, 0x22, 0 + .dw 0x06c0, 0xc40d, 0x06ff, 0xc40d, 0x22, 0 + .dw 0x0900, 0xc40d, 0x093f, 0xc40d, 0x22, 0 + .dw 0x0b40, 0xc40d, 0x0b7f, 0xc40d, 0x22, 0 + .dw 0x0d80, 0xc40d, 0x0dbf, 0xc40d, 0x22, 0 + .dw 0x0fc0, 0xc40d, 0x0fff, 0xc40d, 0x22, 0 + .dw 0x1000, 0xc40d, 0x3fff, 0xc40d, 0x21, 0 + .dw 0x4000, 0xc40d, 0x403f, 0xc40d, 0x22, 0 + .dw 0x4240, 0xc40d, 0x427f, 0xc40d, 0x22, 0 + .dw 0x4480, 0xc40d, 0x44bf, 0xc40d, 0x22, 0 + .dw 0x46c0, 0xc40d, 0x46ff, 0xc40d, 0x22, 0 + .dw 0x4900, 0xc40d, 0x493f, 0xc40d, 0x22, 0 + .dw 0x4b40, 0xc40d, 0x4b7f, 0xc40d, 0x22, 0 + .dw 0x4d80, 0xc40d, 0x4dbf, 0xc40d, 0x22, 0 + .dw 0x4fc0, 0xc40d, 0x4fff, 0xc40d, 0x22, 0 + .dw 0x5000, 0xc40d, 0x7fff, 0xc40d, 0x21, 0 + .dw 0x8000, 0xc40d, 0x803f, 0xc40d, 0x22, 0 + .dw 0x8240, 0xc40d, 0x827f, 0xc40d, 0x22, 0 + .dw 0x8480, 0xc40d, 0x84bf, 0xc40d, 0x22, 0 + .dw 0x86c0, 0xc40d, 0x86ff, 0xc40d, 0x22, 0 + .dw 0x8900, 0xc40d, 0x893f, 0xc40d, 0x22, 0 + .dw 0x8b40, 0xc40d, 0x8b7f, 0xc40d, 0x22, 0 + .dw 0x8d80, 0xc40d, 0x8dbf, 0xc40d, 0x22, 0 + .dw 0x8fc0, 0xc40d, 0x8fff, 0xc40d, 0x22, 0 + .dw 0x9000, 0xc40d, 0xbfff, 0xc40d, 0x21, 0 + .dw 0xc000, 0xc40d, 0xc03f, 0xc40d, 0x22, 0 + .dw 0xc240, 0xc40d, 0xc27f, 0xc40d, 0x22, 0 + .dw 0xc480, 0xc40d, 0xc4bf, 0xc40d, 0x22, 0 + .dw 0xc6c0, 0xc40d, 0xc6ff, 0xc40d, 0x22, 0 + .dw 0xc900, 0xc40d, 0xc93f, 0xc40d, 0x22, 0 + .dw 0xcb40, 0xc40d, 0xcb7f, 0xc40d, 0x22, 0 + .dw 0xcd80, 0xc40d, 0xcdbf, 0xc40d, 0x22, 0 + .dw 0xcfc0, 0xc40d, 0xcfff, 0xc40d, 0x22, 0 + .dw 0xd000, 0xc40d, 0xffff, 0xc40d, 0x21, 0 + .dw 0x1000, 0xc40e, 0x3fff, 0xc40e, 0x21, 0 + .dw 0x5000, 0xc40e, 0xbfff, 0xc40e, 0x21, 0 + .dw 0xd000, 0xc40e, 0xbfff, 0xc40f, 0x21, 0 + .dw 0xd000, 0xc40f, 0xffff, 0xc40f, 0x21, 0 + .dw 0x1000, 0xc410, 0x3fff, 0xc410, 0x21, 0 + .dw 0x5000, 0xc410, 0xbfff, 0xc410, 0x21, 0 + .dw 0xd000, 0xc410, 0xffff, 0xc410, 0x21, 0 + .dw 0x0000, 0xc411, 0x003f, 0xc411, 0x22, 0 + .dw 0x0240, 0xc411, 0x027f, 0xc411, 0x22, 0 + .dw 0x0480, 0xc411, 0x04bf, 0xc411, 0x22, 0 + .dw 0x06c0, 0xc411, 0x06ff, 0xc411, 0x22, 0 + .dw 0x0900, 0xc411, 0x093f, 0xc411, 0x22, 0 + .dw 0x0b40, 0xc411, 0x0b7f, 0xc411, 0x22, 0 + .dw 0x0d80, 0xc411, 0x0dbf, 0xc411, 0x22, 0 + .dw 0x0fc0, 0xc411, 0x0fff, 0xc411, 0x22, 0 + .dw 0x1000, 0xc411, 0x1fff, 0xc411, 0x21, 0 + .dw 0x2000, 0xc411, 0x203f, 0xc411, 0x22, 0 + .dw 0x2240, 0xc411, 0x227f, 0xc411, 0x22, 0 + .dw 0x2480, 0xc411, 0x24bf, 0xc411, 0x22, 0 + .dw 0x26c0, 0xc411, 0x26ff, 0xc411, 0x22, 0 + .dw 0x2900, 0xc411, 0x293f, 0xc411, 0x22, 0 + .dw 0x2b40, 0xc411, 0x2b7f, 0xc411, 0x22, 0 + .dw 0x2d80, 0xc411, 0x2dbf, 0xc411, 0x22, 0 + .dw 0x2fc0, 0xc411, 0x2fff, 0xc411, 0x22, 0 + .dw 0x3000, 0xc411, 0x3fff, 0xc411, 0x21, 0 + .dw 0x4000, 0xc411, 0x403f, 0xc411, 0x22, 0 + .dw 0x4240, 0xc411, 0x427f, 0xc411, 0x22, 0 + .dw 0x4480, 0xc411, 0x44bf, 0xc411, 0x22, 0 + .dw 0x46c0, 0xc411, 0x46ff, 0xc411, 0x22, 0 + .dw 0x4900, 0xc411, 0x493f, 0xc411, 0x22, 0 + .dw 0x4b40, 0xc411, 0x4b7f, 0xc411, 0x22, 0 + .dw 0x4d80, 0xc411, 0x4dbf, 0xc411, 0x22, 0 + .dw 0x4fc0, 0xc411, 0x4fff, 0xc411, 0x22, 0 + .dw 0x5000, 0xc411, 0x5fff, 0xc411, 0x21, 0 + .dw 0x6000, 0xc411, 0x603f, 0xc411, 0x22, 0 + .dw 0x6240, 0xc411, 0x627f, 0xc411, 0x22, 0 + .dw 0x6480, 0xc411, 0x64bf, 0xc411, 0x22, 0 + .dw 0x66c0, 0xc411, 0x66ff, 0xc411, 0x22, 0 + .dw 0x6900, 0xc411, 0x693f, 0xc411, 0x22, 0 + .dw 0x6b40, 0xc411, 0x6b7f, 0xc411, 0x22, 0 + .dw 0x6d80, 0xc411, 0x6dbf, 0xc411, 0x22, 0 + .dw 0x6fc0, 0xc411, 0x6fff, 0xc411, 0x22, 0 + .dw 0x7000, 0xc411, 0xffff, 0xc411, 0x21, 0 + .dw 0x0001, 0xc412, 0x0001, 0xc412, 0x21, 0 + .dw 0x0003, 0xc412, 0x000f, 0xc412, 0x21, 0 + .dw 0x0011, 0xc412, 0x0011, 0xc412, 0x21, 0 + .dw 0x0013, 0xc412, 0x003f, 0xc412, 0x21, 0 + .dw 0x0041, 0xc412, 0x0041, 0xc412, 0x21, 0 + .dw 0x0043, 0xc412, 0x004f, 0xc412, 0x21, 0 + .dw 0x0051, 0xc412, 0x0051, 0xc412, 0x21, 0 + .dw 0x0053, 0xc412, 0x007f, 0xc412, 0x21, 0 + .dw 0x0081, 0xc412, 0x0081, 0xc412, 0x21, 0 + .dw 0x0083, 0xc412, 0x008f, 0xc412, 0x21, 0 + .dw 0x0091, 0xc412, 0x0091, 0xc412, 0x21, 0 + .dw 0x0093, 0xc412, 0x00bf, 0xc412, 0x21, 0 + .dw 0x00c1, 0xc412, 0x00c1, 0xc412, 0x21, 0 + .dw 0x00c3, 0xc412, 0x00cf, 0xc412, 0x21, 0 + .dw 0x00d1, 0xc412, 0x00d1, 0xc412, 0x21, 0 + .dw 0x00d3, 0xc412, 0x00ff, 0xc412, 0x21, 0 + .dw 0x0101, 0xc412, 0x0101, 0xc412, 0x21, 0 + .dw 0x0103, 0xc412, 0x010f, 0xc412, 0x21, 0 + .dw 0x0111, 0xc412, 0x0111, 0xc412, 0x21, 0 + .dw 0x0113, 0xc412, 0x013f, 0xc412, 0x21, 0 + .dw 0x0141, 0xc412, 0x0141, 0xc412, 0x21, 0 + .dw 0x0143, 0xc412, 0x014f, 0xc412, 0x21, 0 + .dw 0x0151, 0xc412, 0x0151, 0xc412, 0x21, 0 + .dw 0x0153, 0xc412, 0x017f, 0xc412, 0x21, 0 + .dw 0x0181, 0xc412, 0x0181, 0xc412, 0x21, 0 + .dw 0x0183, 0xc412, 0x018f, 0xc412, 0x21, 0 + .dw 0x0191, 0xc412, 0x0191, 0xc412, 0x21, 0 + .dw 0x0193, 0xc412, 0x01bf, 0xc412, 0x21, 0 + .dw 0x01c1, 0xc412, 0x01c1, 0xc412, 0x21, 0 + .dw 0x01c3, 0xc412, 0x01cf, 0xc412, 0x21, 0 + .dw 0x01d1, 0xc412, 0x01d1, 0xc412, 0x21, 0 + .dw 0x01d3, 0xc412, 0x01ff, 0xc412, 0x21, 0 + .dw 0x0201, 0xc412, 0x0201, 0xc412, 0x21, 0 + .dw 0x0203, 0xc412, 0x020f, 0xc412, 0x21, 0 + .dw 0x0211, 0xc412, 0x0211, 0xc412, 0x21, 0 + .dw 0x0213, 0xc412, 0x023f, 0xc412, 0x21, 0 + .dw 0x0241, 0xc412, 0x0241, 0xc412, 0x21, 0 + .dw 0x0243, 0xc412, 0x024f, 0xc412, 0x21, 0 + .dw 0x0251, 0xc412, 0x0251, 0xc412, 0x21, 0 + .dw 0x0253, 0xc412, 0x027f, 0xc412, 0x21, 0 + .dw 0x0281, 0xc412, 0x0281, 0xc412, 0x21, 0 + .dw 0x0283, 0xc412, 0x028f, 0xc412, 0x21, 0 + .dw 0x0291, 0xc412, 0x0291, 0xc412, 0x21, 0 + .dw 0x0293, 0xc412, 0x02bf, 0xc412, 0x21, 0 + .dw 0x02c1, 0xc412, 0x02c1, 0xc412, 0x21, 0 + .dw 0x02c3, 0xc412, 0x02cf, 0xc412, 0x21, 0 + .dw 0x02d1, 0xc412, 0x02d1, 0xc412, 0x21, 0 + .dw 0x02d3, 0xc412, 0x02ff, 0xc412, 0x21, 0 + .dw 0x0301, 0xc412, 0x0301, 0xc412, 0x21, 0 + .dw 0x0303, 0xc412, 0x030f, 0xc412, 0x21, 0 + .dw 0x0311, 0xc412, 0x0311, 0xc412, 0x21, 0 + .dw 0x0313, 0xc412, 0x033f, 0xc412, 0x21, 0 + .dw 0x0341, 0xc412, 0x0341, 0xc412, 0x21, 0 + .dw 0x0343, 0xc412, 0x034f, 0xc412, 0x21, 0 + .dw 0x0351, 0xc412, 0x0351, 0xc412, 0x21, 0 + .dw 0x0353, 0xc412, 0x037f, 0xc412, 0x21, 0 + .dw 0x0381, 0xc412, 0x0381, 0xc412, 0x21, 0 + .dw 0x0383, 0xc412, 0x038f, 0xc412, 0x21, 0 + .dw 0x0391, 0xc412, 0x0391, 0xc412, 0x21, 0 + .dw 0x0393, 0xc412, 0x03bf, 0xc412, 0x21, 0 + .dw 0x03c1, 0xc412, 0x03c1, 0xc412, 0x21, 0 + .dw 0x03c3, 0xc412, 0x03cf, 0xc412, 0x21, 0 + .dw 0x03d1, 0xc412, 0x03d1, 0xc412, 0x21, 0 + .dw 0x03d3, 0xc412, 0x03ff, 0xc412, 0x21, 0 + .dw 0x0401, 0xc412, 0x0401, 0xc412, 0x21, 0 + .dw 0x0403, 0xc412, 0x040f, 0xc412, 0x21, 0 + .dw 0x0411, 0xc412, 0x0411, 0xc412, 0x21, 0 + .dw 0x0413, 0xc412, 0x043f, 0xc412, 0x21, 0 + .dw 0x0441, 0xc412, 0x0441, 0xc412, 0x21, 0 + .dw 0x0443, 0xc412, 0x044f, 0xc412, 0x21, 0 + .dw 0x0451, 0xc412, 0x0451, 0xc412, 0x21, 0 + .dw 0x0453, 0xc412, 0x047f, 0xc412, 0x21, 0 + .dw 0x0481, 0xc412, 0x0481, 0xc412, 0x21, 0 + .dw 0x0483, 0xc412, 0x048f, 0xc412, 0x21, 0 + .dw 0x0491, 0xc412, 0x0491, 0xc412, 0x21, 0 + .dw 0x0493, 0xc412, 0x04bf, 0xc412, 0x21, 0 + .dw 0x04c1, 0xc412, 0x04c1, 0xc412, 0x21, 0 + .dw 0x04c3, 0xc412, 0x04cf, 0xc412, 0x21, 0 + .dw 0x04d1, 0xc412, 0x04d1, 0xc412, 0x21, 0 + .dw 0x04d3, 0xc412, 0x04ff, 0xc412, 0x21, 0 + .dw 0x0501, 0xc412, 0x0501, 0xc412, 0x21, 0 + .dw 0x0503, 0xc412, 0x050f, 0xc412, 0x21, 0 + .dw 0x0511, 0xc412, 0x0511, 0xc412, 0x21, 0 + .dw 0x0513, 0xc412, 0x053f, 0xc412, 0x21, 0 + .dw 0x0541, 0xc412, 0x0541, 0xc412, 0x21, 0 + .dw 0x0543, 0xc412, 0x054f, 0xc412, 0x21, 0 + .dw 0x0551, 0xc412, 0x0551, 0xc412, 0x21, 0 + .dw 0x0553, 0xc412, 0x057f, 0xc412, 0x21, 0 + .dw 0x0581, 0xc412, 0x0581, 0xc412, 0x21, 0 + .dw 0x0583, 0xc412, 0x058f, 0xc412, 0x21, 0 + .dw 0x0591, 0xc412, 0x0591, 0xc412, 0x21, 0 + .dw 0x0593, 0xc412, 0x05bf, 0xc412, 0x21, 0 + .dw 0x05c1, 0xc412, 0x05c1, 0xc412, 0x21, 0 + .dw 0x05c3, 0xc412, 0x05cf, 0xc412, 0x21, 0 + .dw 0x05d1, 0xc412, 0x05d1, 0xc412, 0x21, 0 + .dw 0x05d3, 0xc412, 0x05ff, 0xc412, 0x21, 0 + .dw 0x0601, 0xc412, 0x0601, 0xc412, 0x21, 0 + .dw 0x0603, 0xc412, 0x060f, 0xc412, 0x21, 0 + .dw 0x0611, 0xc412, 0x0611, 0xc412, 0x21, 0 + .dw 0x0613, 0xc412, 0x063f, 0xc412, 0x21, 0 + .dw 0x0641, 0xc412, 0x0641, 0xc412, 0x21, 0 + .dw 0x0643, 0xc412, 0x064f, 0xc412, 0x21, 0 + .dw 0x0651, 0xc412, 0x0651, 0xc412, 0x21, 0 + .dw 0x0653, 0xc412, 0x067f, 0xc412, 0x21, 0 + .dw 0x0681, 0xc412, 0x0681, 0xc412, 0x21, 0 + .dw 0x0683, 0xc412, 0x068f, 0xc412, 0x21, 0 + .dw 0x0691, 0xc412, 0x0691, 0xc412, 0x21, 0 + .dw 0x0693, 0xc412, 0x06bf, 0xc412, 0x21, 0 + .dw 0x06c1, 0xc412, 0x06c1, 0xc412, 0x21, 0 + .dw 0x06c3, 0xc412, 0x06cf, 0xc412, 0x21, 0 + .dw 0x06d1, 0xc412, 0x06d1, 0xc412, 0x21, 0 + .dw 0x06d3, 0xc412, 0x06ff, 0xc412, 0x21, 0 + .dw 0x0701, 0xc412, 0x0701, 0xc412, 0x21, 0 + .dw 0x0703, 0xc412, 0x070f, 0xc412, 0x21, 0 + .dw 0x0711, 0xc412, 0x0711, 0xc412, 0x21, 0 + .dw 0x0713, 0xc412, 0x073f, 0xc412, 0x21, 0 + .dw 0x0741, 0xc412, 0x0741, 0xc412, 0x21, 0 + .dw 0x0743, 0xc412, 0x074f, 0xc412, 0x21, 0 + .dw 0x0751, 0xc412, 0x0751, 0xc412, 0x21, 0 + .dw 0x0753, 0xc412, 0x077f, 0xc412, 0x21, 0 + .dw 0x0781, 0xc412, 0x0781, 0xc412, 0x21, 0 + .dw 0x0783, 0xc412, 0x078f, 0xc412, 0x21, 0 + .dw 0x0791, 0xc412, 0x0791, 0xc412, 0x21, 0 + .dw 0x0793, 0xc412, 0x07bf, 0xc412, 0x21, 0 + .dw 0x07c1, 0xc412, 0x07c1, 0xc412, 0x21, 0 + .dw 0x07c3, 0xc412, 0x07cf, 0xc412, 0x21, 0 + .dw 0x07d1, 0xc412, 0x07d1, 0xc412, 0x21, 0 + .dw 0x07d3, 0xc412, 0x07ff, 0xc412, 0x21, 0 + .dw 0x0801, 0xc412, 0x0801, 0xc412, 0x21, 0 + .dw 0x0803, 0xc412, 0x080f, 0xc412, 0x21, 0 + .dw 0x0811, 0xc412, 0x0811, 0xc412, 0x21, 0 + .dw 0x0813, 0xc412, 0x083f, 0xc412, 0x21, 0 + .dw 0x0841, 0xc412, 0x0841, 0xc412, 0x21, 0 + .dw 0x0843, 0xc412, 0x084f, 0xc412, 0x21, 0 + .dw 0x0851, 0xc412, 0x0851, 0xc412, 0x21, 0 + .dw 0x0853, 0xc412, 0x087f, 0xc412, 0x21, 0 + .dw 0x0881, 0xc412, 0x0881, 0xc412, 0x21, 0 + .dw 0x0883, 0xc412, 0x088f, 0xc412, 0x21, 0 + .dw 0x0891, 0xc412, 0x0891, 0xc412, 0x21, 0 + .dw 0x0893, 0xc412, 0x08bf, 0xc412, 0x21, 0 + .dw 0x08c1, 0xc412, 0x08c1, 0xc412, 0x21, 0 + .dw 0x08c3, 0xc412, 0x08cf, 0xc412, 0x21, 0 + .dw 0x08d1, 0xc412, 0x08d1, 0xc412, 0x21, 0 + .dw 0x08d3, 0xc412, 0x08ff, 0xc412, 0x21, 0 + .dw 0x0901, 0xc412, 0x0901, 0xc412, 0x21, 0 + .dw 0x0903, 0xc412, 0x090f, 0xc412, 0x21, 0 + .dw 0x0911, 0xc412, 0x0911, 0xc412, 0x21, 0 + .dw 0x0913, 0xc412, 0x093f, 0xc412, 0x21, 0 + .dw 0x0941, 0xc412, 0x0941, 0xc412, 0x21, 0 + .dw 0x0943, 0xc412, 0x094f, 0xc412, 0x21, 0 + .dw 0x0951, 0xc412, 0x0951, 0xc412, 0x21, 0 + .dw 0x0953, 0xc412, 0x097f, 0xc412, 0x21, 0 + .dw 0x0981, 0xc412, 0x0981, 0xc412, 0x21, 0 + .dw 0x0983, 0xc412, 0x098f, 0xc412, 0x21, 0 + .dw 0x0991, 0xc412, 0x0991, 0xc412, 0x21, 0 + .dw 0x0993, 0xc412, 0x09bf, 0xc412, 0x21, 0 + .dw 0x09c1, 0xc412, 0x09c1, 0xc412, 0x21, 0 + .dw 0x09c3, 0xc412, 0x09cf, 0xc412, 0x21, 0 + .dw 0x09d1, 0xc412, 0x09d1, 0xc412, 0x21, 0 + .dw 0x09d3, 0xc412, 0x09ff, 0xc412, 0x21, 0 + .dw 0x0a01, 0xc412, 0x0a01, 0xc412, 0x21, 0 + .dw 0x0a03, 0xc412, 0x0a0f, 0xc412, 0x21, 0 + .dw 0x0a11, 0xc412, 0x0a11, 0xc412, 0x21, 0 + .dw 0x0a13, 0xc412, 0x0a3f, 0xc412, 0x21, 0 + .dw 0x0a41, 0xc412, 0x0a41, 0xc412, 0x21, 0 + .dw 0x0a43, 0xc412, 0x0a4f, 0xc412, 0x21, 0 + .dw 0x0a51, 0xc412, 0x0a51, 0xc412, 0x21, 0 + .dw 0x0a53, 0xc412, 0x0a7f, 0xc412, 0x21, 0 + .dw 0x0a81, 0xc412, 0x0a81, 0xc412, 0x21, 0 + .dw 0x0a83, 0xc412, 0x0a8f, 0xc412, 0x21, 0 + .dw 0x0a91, 0xc412, 0x0a91, 0xc412, 0x21, 0 + .dw 0x0a93, 0xc412, 0x0abf, 0xc412, 0x21, 0 + .dw 0x0ac1, 0xc412, 0x0ac1, 0xc412, 0x21, 0 + .dw 0x0ac3, 0xc412, 0x0acf, 0xc412, 0x21, 0 + .dw 0x0ad1, 0xc412, 0x0ad1, 0xc412, 0x21, 0 + .dw 0x0ad3, 0xc412, 0x0aff, 0xc412, 0x21, 0 + .dw 0x0b01, 0xc412, 0x0b01, 0xc412, 0x21, 0 + .dw 0x0b03, 0xc412, 0x0b0f, 0xc412, 0x21, 0 + .dw 0x0b11, 0xc412, 0x0b11, 0xc412, 0x21, 0 + .dw 0x0b13, 0xc412, 0x0b3f, 0xc412, 0x21, 0 + .dw 0x0b41, 0xc412, 0x0b41, 0xc412, 0x21, 0 + .dw 0x0b43, 0xc412, 0x0b4f, 0xc412, 0x21, 0 + .dw 0x0b51, 0xc412, 0x0b51, 0xc412, 0x21, 0 + .dw 0x0b53, 0xc412, 0x0b7f, 0xc412, 0x21, 0 + .dw 0x0b81, 0xc412, 0x0b81, 0xc412, 0x21, 0 + .dw 0x0b83, 0xc412, 0x0b8f, 0xc412, 0x21, 0 + .dw 0x0b91, 0xc412, 0x0b91, 0xc412, 0x21, 0 + .dw 0x0b93, 0xc412, 0x0bbf, 0xc412, 0x21, 0 + .dw 0x0bc1, 0xc412, 0x0bc1, 0xc412, 0x21, 0 + .dw 0x0bc3, 0xc412, 0x0bcf, 0xc412, 0x21, 0 + .dw 0x0bd1, 0xc412, 0x0bd1, 0xc412, 0x21, 0 + .dw 0x0bd3, 0xc412, 0x0bff, 0xc412, 0x21, 0 + .dw 0x0c01, 0xc412, 0x0c01, 0xc412, 0x21, 0 + .dw 0x0c03, 0xc412, 0x0c0f, 0xc412, 0x21, 0 + .dw 0x0c11, 0xc412, 0x0c11, 0xc412, 0x21, 0 + .dw 0x0c13, 0xc412, 0x0c3f, 0xc412, 0x21, 0 + .dw 0x0c41, 0xc412, 0x0c41, 0xc412, 0x21, 0 + .dw 0x0c43, 0xc412, 0x0c4f, 0xc412, 0x21, 0 + .dw 0x0c51, 0xc412, 0x0c51, 0xc412, 0x21, 0 + .dw 0x0c53, 0xc412, 0x0c7f, 0xc412, 0x21, 0 + .dw 0x0c81, 0xc412, 0x0c81, 0xc412, 0x21, 0 + .dw 0x0c83, 0xc412, 0x0c8f, 0xc412, 0x21, 0 + .dw 0x0c91, 0xc412, 0x0c91, 0xc412, 0x21, 0 + .dw 0x0c93, 0xc412, 0x0cbf, 0xc412, 0x21, 0 + .dw 0x0cc1, 0xc412, 0x0cc1, 0xc412, 0x21, 0 + .dw 0x0cc3, 0xc412, 0x0ccf, 0xc412, 0x21, 0 + .dw 0x0cd1, 0xc412, 0x0cd1, 0xc412, 0x21, 0 + .dw 0x0cd3, 0xc412, 0x0cff, 0xc412, 0x21, 0 + .dw 0x0d01, 0xc412, 0x0d01, 0xc412, 0x21, 0 + .dw 0x0d03, 0xc412, 0x0d0f, 0xc412, 0x21, 0 + .dw 0x0d11, 0xc412, 0x0d11, 0xc412, 0x21, 0 + .dw 0x0d13, 0xc412, 0x0d3f, 0xc412, 0x21, 0 + .dw 0x0d41, 0xc412, 0x0d41, 0xc412, 0x21, 0 + .dw 0x0d43, 0xc412, 0x0d4f, 0xc412, 0x21, 0 + .dw 0x0d51, 0xc412, 0x0d51, 0xc412, 0x21, 0 + .dw 0x0d53, 0xc412, 0x0d7f, 0xc412, 0x21, 0 + .dw 0x0d81, 0xc412, 0x0d81, 0xc412, 0x21, 0 + .dw 0x0d83, 0xc412, 0x0d8f, 0xc412, 0x21, 0 + .dw 0x0d91, 0xc412, 0x0d91, 0xc412, 0x21, 0 + .dw 0x0d93, 0xc412, 0x0dbf, 0xc412, 0x21, 0 + .dw 0x0dc1, 0xc412, 0x0dc1, 0xc412, 0x21, 0 + .dw 0x0dc3, 0xc412, 0x0dcf, 0xc412, 0x21, 0 + .dw 0x0dd1, 0xc412, 0x0dd1, 0xc412, 0x21, 0 + .dw 0x0dd3, 0xc412, 0x0dff, 0xc412, 0x21, 0 + .dw 0x0e01, 0xc412, 0x0e01, 0xc412, 0x21, 0 + .dw 0x0e03, 0xc412, 0x0e0f, 0xc412, 0x21, 0 + .dw 0x0e11, 0xc412, 0x0e11, 0xc412, 0x21, 0 + .dw 0x0e13, 0xc412, 0x0e3f, 0xc412, 0x21, 0 + .dw 0x0e41, 0xc412, 0x0e41, 0xc412, 0x21, 0 + .dw 0x0e43, 0xc412, 0x0e4f, 0xc412, 0x21, 0 + .dw 0x0e51, 0xc412, 0x0e51, 0xc412, 0x21, 0 + .dw 0x0e53, 0xc412, 0x0e7f, 0xc412, 0x21, 0 + .dw 0x0e81, 0xc412, 0x0e81, 0xc412, 0x21, 0 + .dw 0x0e83, 0xc412, 0x0e8f, 0xc412, 0x21, 0 + .dw 0x0e91, 0xc412, 0x0e91, 0xc412, 0x21, 0 + .dw 0x0e93, 0xc412, 0x0ebf, 0xc412, 0x21, 0 + .dw 0x0ec1, 0xc412, 0x0ec1, 0xc412, 0x21, 0 + .dw 0x0ec3, 0xc412, 0x0ecf, 0xc412, 0x21, 0 + .dw 0x0ed1, 0xc412, 0x0ed1, 0xc412, 0x21, 0 + .dw 0x0ed3, 0xc412, 0x0eff, 0xc412, 0x21, 0 + .dw 0x0f01, 0xc412, 0x0f01, 0xc412, 0x21, 0 + .dw 0x0f03, 0xc412, 0x0f0f, 0xc412, 0x21, 0 + .dw 0x0f11, 0xc412, 0x0f11, 0xc412, 0x21, 0 + .dw 0x0f13, 0xc412, 0x0f3f, 0xc412, 0x21, 0 + .dw 0x0f41, 0xc412, 0x0f41, 0xc412, 0x21, 0 + .dw 0x0f43, 0xc412, 0x0f4f, 0xc412, 0x21, 0 + .dw 0x0f51, 0xc412, 0x0f51, 0xc412, 0x21, 0 + .dw 0x0f53, 0xc412, 0x0f7f, 0xc412, 0x21, 0 + .dw 0x0f81, 0xc412, 0x0f81, 0xc412, 0x21, 0 + .dw 0x0f83, 0xc412, 0x0f8f, 0xc412, 0x21, 0 + .dw 0x0f91, 0xc412, 0x0f91, 0xc412, 0x21, 0 + .dw 0x0f93, 0xc412, 0x0fbf, 0xc412, 0x21, 0 + .dw 0x0fc1, 0xc412, 0x0fc1, 0xc412, 0x21, 0 + .dw 0x0fc3, 0xc412, 0x0fcf, 0xc412, 0x21, 0 + .dw 0x0fd1, 0xc412, 0x0fd1, 0xc412, 0x21, 0 + .dw 0x0fd3, 0xc412, 0x1fff, 0xc412, 0x21, 0 + .dw 0x2001, 0xc412, 0x2001, 0xc412, 0x21, 0 + .dw 0x2003, 0xc412, 0x200f, 0xc412, 0x21, 0 + .dw 0x2011, 0xc412, 0x2011, 0xc412, 0x21, 0 + .dw 0x2013, 0xc412, 0x203f, 0xc412, 0x21, 0 + .dw 0x2041, 0xc412, 0x2041, 0xc412, 0x21, 0 + .dw 0x2043, 0xc412, 0x204f, 0xc412, 0x21, 0 + .dw 0x2051, 0xc412, 0x2051, 0xc412, 0x21, 0 + .dw 0x2053, 0xc412, 0x207f, 0xc412, 0x21, 0 + .dw 0x2081, 0xc412, 0x2081, 0xc412, 0x21, 0 + .dw 0x2083, 0xc412, 0x208f, 0xc412, 0x21, 0 + .dw 0x2091, 0xc412, 0x2091, 0xc412, 0x21, 0 + .dw 0x2093, 0xc412, 0x20bf, 0xc412, 0x21, 0 + .dw 0x20c1, 0xc412, 0x20c1, 0xc412, 0x21, 0 + .dw 0x20c3, 0xc412, 0x20cf, 0xc412, 0x21, 0 + .dw 0x20d1, 0xc412, 0x20d1, 0xc412, 0x21, 0 + .dw 0x20d3, 0xc412, 0x20ff, 0xc412, 0x21, 0 + .dw 0x2101, 0xc412, 0x2101, 0xc412, 0x21, 0 + .dw 0x2103, 0xc412, 0x210f, 0xc412, 0x21, 0 + .dw 0x2111, 0xc412, 0x2111, 0xc412, 0x21, 0 + .dw 0x2113, 0xc412, 0x213f, 0xc412, 0x21, 0 + .dw 0x2141, 0xc412, 0x2141, 0xc412, 0x21, 0 + .dw 0x2143, 0xc412, 0x214f, 0xc412, 0x21, 0 + .dw 0x2151, 0xc412, 0x2151, 0xc412, 0x21, 0 + .dw 0x2153, 0xc412, 0x217f, 0xc412, 0x21, 0 + .dw 0x2181, 0xc412, 0x2181, 0xc412, 0x21, 0 + .dw 0x2183, 0xc412, 0x218f, 0xc412, 0x21, 0 + .dw 0x2191, 0xc412, 0x2191, 0xc412, 0x21, 0 + .dw 0x2193, 0xc412, 0x21bf, 0xc412, 0x21, 0 + .dw 0x21c1, 0xc412, 0x21c1, 0xc412, 0x21, 0 + .dw 0x21c3, 0xc412, 0x21cf, 0xc412, 0x21, 0 + .dw 0x21d1, 0xc412, 0x21d1, 0xc412, 0x21, 0 + .dw 0x21d3, 0xc412, 0x21ff, 0xc412, 0x21, 0 + .dw 0x2201, 0xc412, 0x2201, 0xc412, 0x21, 0 + .dw 0x2203, 0xc412, 0x220f, 0xc412, 0x21, 0 + .dw 0x2211, 0xc412, 0x2211, 0xc412, 0x21, 0 + .dw 0x2213, 0xc412, 0x223f, 0xc412, 0x21, 0 + .dw 0x2241, 0xc412, 0x2241, 0xc412, 0x21, 0 + .dw 0x2243, 0xc412, 0x224f, 0xc412, 0x21, 0 + .dw 0x2251, 0xc412, 0x2251, 0xc412, 0x21, 0 + .dw 0x2253, 0xc412, 0x227f, 0xc412, 0x21, 0 + .dw 0x2281, 0xc412, 0x2281, 0xc412, 0x21, 0 + .dw 0x2283, 0xc412, 0x228f, 0xc412, 0x21, 0 + .dw 0x2291, 0xc412, 0x2291, 0xc412, 0x21, 0 + .dw 0x2293, 0xc412, 0x22bf, 0xc412, 0x21, 0 + .dw 0x22c1, 0xc412, 0x22c1, 0xc412, 0x21, 0 + .dw 0x22c3, 0xc412, 0x22cf, 0xc412, 0x21, 0 + .dw 0x22d1, 0xc412, 0x22d1, 0xc412, 0x21, 0 + .dw 0x22d3, 0xc412, 0x22ff, 0xc412, 0x21, 0 + .dw 0x2301, 0xc412, 0x2301, 0xc412, 0x21, 0 + .dw 0x2303, 0xc412, 0x230f, 0xc412, 0x21, 0 + .dw 0x2311, 0xc412, 0x2311, 0xc412, 0x21, 0 + .dw 0x2313, 0xc412, 0x233f, 0xc412, 0x21, 0 + .dw 0x2341, 0xc412, 0x2341, 0xc412, 0x21, 0 + .dw 0x2343, 0xc412, 0x234f, 0xc412, 0x21, 0 + .dw 0x2351, 0xc412, 0x2351, 0xc412, 0x21, 0 + .dw 0x2353, 0xc412, 0x237f, 0xc412, 0x21, 0 + .dw 0x2381, 0xc412, 0x2381, 0xc412, 0x21, 0 + .dw 0x2383, 0xc412, 0x238f, 0xc412, 0x21, 0 + .dw 0x2391, 0xc412, 0x2391, 0xc412, 0x21, 0 + .dw 0x2393, 0xc412, 0x23bf, 0xc412, 0x21, 0 + .dw 0x23c1, 0xc412, 0x23c1, 0xc412, 0x21, 0 + .dw 0x23c3, 0xc412, 0x23cf, 0xc412, 0x21, 0 + .dw 0x23d1, 0xc412, 0x23d1, 0xc412, 0x21, 0 + .dw 0x23d3, 0xc412, 0x23ff, 0xc412, 0x21, 0 + .dw 0x2401, 0xc412, 0x2401, 0xc412, 0x21, 0 + .dw 0x2403, 0xc412, 0x240f, 0xc412, 0x21, 0 + .dw 0x2411, 0xc412, 0x2411, 0xc412, 0x21, 0 + .dw 0x2413, 0xc412, 0x243f, 0xc412, 0x21, 0 + .dw 0x2441, 0xc412, 0x2441, 0xc412, 0x21, 0 + .dw 0x2443, 0xc412, 0x244f, 0xc412, 0x21, 0 + .dw 0x2451, 0xc412, 0x2451, 0xc412, 0x21, 0 + .dw 0x2453, 0xc412, 0x247f, 0xc412, 0x21, 0 + .dw 0x2481, 0xc412, 0x2481, 0xc412, 0x21, 0 + .dw 0x2483, 0xc412, 0x248f, 0xc412, 0x21, 0 + .dw 0x2491, 0xc412, 0x2491, 0xc412, 0x21, 0 + .dw 0x2493, 0xc412, 0x24bf, 0xc412, 0x21, 0 + .dw 0x24c1, 0xc412, 0x24c1, 0xc412, 0x21, 0 + .dw 0x24c3, 0xc412, 0x24cf, 0xc412, 0x21, 0 + .dw 0x24d1, 0xc412, 0x24d1, 0xc412, 0x21, 0 + .dw 0x24d3, 0xc412, 0x24ff, 0xc412, 0x21, 0 + .dw 0x2501, 0xc412, 0x2501, 0xc412, 0x21, 0 + .dw 0x2503, 0xc412, 0x250f, 0xc412, 0x21, 0 + .dw 0x2511, 0xc412, 0x2511, 0xc412, 0x21, 0 + .dw 0x2513, 0xc412, 0x253f, 0xc412, 0x21, 0 + .dw 0x2541, 0xc412, 0x2541, 0xc412, 0x21, 0 + .dw 0x2543, 0xc412, 0x254f, 0xc412, 0x21, 0 + .dw 0x2551, 0xc412, 0x2551, 0xc412, 0x21, 0 + .dw 0x2553, 0xc412, 0x257f, 0xc412, 0x21, 0 + .dw 0x2581, 0xc412, 0x2581, 0xc412, 0x21, 0 + .dw 0x2583, 0xc412, 0x258f, 0xc412, 0x21, 0 + .dw 0x2591, 0xc412, 0x2591, 0xc412, 0x21, 0 + .dw 0x2593, 0xc412, 0x25bf, 0xc412, 0x21, 0 + .dw 0x25c1, 0xc412, 0x25c1, 0xc412, 0x21, 0 + .dw 0x25c3, 0xc412, 0x25cf, 0xc412, 0x21, 0 + .dw 0x25d1, 0xc412, 0x25d1, 0xc412, 0x21, 0 + .dw 0x25d3, 0xc412, 0x25ff, 0xc412, 0x21, 0 + .dw 0x2601, 0xc412, 0x2601, 0xc412, 0x21, 0 + .dw 0x2603, 0xc412, 0x260f, 0xc412, 0x21, 0 + .dw 0x2611, 0xc412, 0x2611, 0xc412, 0x21, 0 + .dw 0x2613, 0xc412, 0x263f, 0xc412, 0x21, 0 + .dw 0x2641, 0xc412, 0x2641, 0xc412, 0x21, 0 + .dw 0x2643, 0xc412, 0x264f, 0xc412, 0x21, 0 + .dw 0x2651, 0xc412, 0x2651, 0xc412, 0x21, 0 + .dw 0x2653, 0xc412, 0x267f, 0xc412, 0x21, 0 + .dw 0x2681, 0xc412, 0x2681, 0xc412, 0x21, 0 + .dw 0x2683, 0xc412, 0x268f, 0xc412, 0x21, 0 + .dw 0x2691, 0xc412, 0x2691, 0xc412, 0x21, 0 + .dw 0x2693, 0xc412, 0x26bf, 0xc412, 0x21, 0 + .dw 0x26c1, 0xc412, 0x26c1, 0xc412, 0x21, 0 + .dw 0x26c3, 0xc412, 0x26cf, 0xc412, 0x21, 0 + .dw 0x26d1, 0xc412, 0x26d1, 0xc412, 0x21, 0 + .dw 0x26d3, 0xc412, 0x26ff, 0xc412, 0x21, 0 + .dw 0x2701, 0xc412, 0x2701, 0xc412, 0x21, 0 + .dw 0x2703, 0xc412, 0x270f, 0xc412, 0x21, 0 + .dw 0x2711, 0xc412, 0x2711, 0xc412, 0x21, 0 + .dw 0x2713, 0xc412, 0x273f, 0xc412, 0x21, 0 + .dw 0x2741, 0xc412, 0x2741, 0xc412, 0x21, 0 + .dw 0x2743, 0xc412, 0x274f, 0xc412, 0x21, 0 + .dw 0x2751, 0xc412, 0x2751, 0xc412, 0x21, 0 + .dw 0x2753, 0xc412, 0x277f, 0xc412, 0x21, 0 + .dw 0x2781, 0xc412, 0x2781, 0xc412, 0x21, 0 + .dw 0x2783, 0xc412, 0x278f, 0xc412, 0x21, 0 + .dw 0x2791, 0xc412, 0x2791, 0xc412, 0x21, 0 + .dw 0x2793, 0xc412, 0x27bf, 0xc412, 0x21, 0 + .dw 0x27c1, 0xc412, 0x27c1, 0xc412, 0x21, 0 + .dw 0x27c3, 0xc412, 0x27cf, 0xc412, 0x21, 0 + .dw 0x27d1, 0xc412, 0x27d1, 0xc412, 0x21, 0 + .dw 0x27d3, 0xc412, 0x27ff, 0xc412, 0x21, 0 + .dw 0x2801, 0xc412, 0x2801, 0xc412, 0x21, 0 + .dw 0x2803, 0xc412, 0x280f, 0xc412, 0x21, 0 + .dw 0x2811, 0xc412, 0x2811, 0xc412, 0x21, 0 + .dw 0x2813, 0xc412, 0x283f, 0xc412, 0x21, 0 + .dw 0x2841, 0xc412, 0x2841, 0xc412, 0x21, 0 + .dw 0x2843, 0xc412, 0x284f, 0xc412, 0x21, 0 + .dw 0x2851, 0xc412, 0x2851, 0xc412, 0x21, 0 + .dw 0x2853, 0xc412, 0x287f, 0xc412, 0x21, 0 + .dw 0x2881, 0xc412, 0x2881, 0xc412, 0x21, 0 + .dw 0x2883, 0xc412, 0x288f, 0xc412, 0x21, 0 + .dw 0x2891, 0xc412, 0x2891, 0xc412, 0x21, 0 + .dw 0x2893, 0xc412, 0x28bf, 0xc412, 0x21, 0 + .dw 0x28c1, 0xc412, 0x28c1, 0xc412, 0x21, 0 + .dw 0x28c3, 0xc412, 0x28cf, 0xc412, 0x21, 0 + .dw 0x28d1, 0xc412, 0x28d1, 0xc412, 0x21, 0 + .dw 0x28d3, 0xc412, 0x28ff, 0xc412, 0x21, 0 + .dw 0x2901, 0xc412, 0x2901, 0xc412, 0x21, 0 + .dw 0x2903, 0xc412, 0x290f, 0xc412, 0x21, 0 + .dw 0x2911, 0xc412, 0x2911, 0xc412, 0x21, 0 + .dw 0x2913, 0xc412, 0x293f, 0xc412, 0x21, 0 + .dw 0x2941, 0xc412, 0x2941, 0xc412, 0x21, 0 + .dw 0x2943, 0xc412, 0x294f, 0xc412, 0x21, 0 + .dw 0x2951, 0xc412, 0x2951, 0xc412, 0x21, 0 + .dw 0x2953, 0xc412, 0x297f, 0xc412, 0x21, 0 + .dw 0x2981, 0xc412, 0x2981, 0xc412, 0x21, 0 + .dw 0x2983, 0xc412, 0x298f, 0xc412, 0x21, 0 + .dw 0x2991, 0xc412, 0x2991, 0xc412, 0x21, 0 + .dw 0x2993, 0xc412, 0x29bf, 0xc412, 0x21, 0 + .dw 0x29c1, 0xc412, 0x29c1, 0xc412, 0x21, 0 + .dw 0x29c3, 0xc412, 0x29cf, 0xc412, 0x21, 0 + .dw 0x29d1, 0xc412, 0x29d1, 0xc412, 0x21, 0 + .dw 0x29d3, 0xc412, 0x29ff, 0xc412, 0x21, 0 + .dw 0x2a01, 0xc412, 0x2a01, 0xc412, 0x21, 0 + .dw 0x2a03, 0xc412, 0x2a0f, 0xc412, 0x21, 0 + .dw 0x2a11, 0xc412, 0x2a11, 0xc412, 0x21, 0 + .dw 0x2a13, 0xc412, 0x2a3f, 0xc412, 0x21, 0 + .dw 0x2a41, 0xc412, 0x2a41, 0xc412, 0x21, 0 + .dw 0x2a43, 0xc412, 0x2a4f, 0xc412, 0x21, 0 + .dw 0x2a51, 0xc412, 0x2a51, 0xc412, 0x21, 0 + .dw 0x2a53, 0xc412, 0x2a7f, 0xc412, 0x21, 0 + .dw 0x2a81, 0xc412, 0x2a81, 0xc412, 0x21, 0 + .dw 0x2a83, 0xc412, 0x2a8f, 0xc412, 0x21, 0 + .dw 0x2a91, 0xc412, 0x2a91, 0xc412, 0x21, 0 + .dw 0x2a93, 0xc412, 0x2abf, 0xc412, 0x21, 0 + .dw 0x2ac1, 0xc412, 0x2ac1, 0xc412, 0x21, 0 + .dw 0x2ac3, 0xc412, 0x2acf, 0xc412, 0x21, 0 + .dw 0x2ad1, 0xc412, 0x2ad1, 0xc412, 0x21, 0 + .dw 0x2ad3, 0xc412, 0x2aff, 0xc412, 0x21, 0 + .dw 0x2b01, 0xc412, 0x2b01, 0xc412, 0x21, 0 + .dw 0x2b03, 0xc412, 0x2b0f, 0xc412, 0x21, 0 + .dw 0x2b11, 0xc412, 0x2b11, 0xc412, 0x21, 0 + .dw 0x2b13, 0xc412, 0x2b3f, 0xc412, 0x21, 0 + .dw 0x2b41, 0xc412, 0x2b41, 0xc412, 0x21, 0 + .dw 0x2b43, 0xc412, 0x2b4f, 0xc412, 0x21, 0 + .dw 0x2b51, 0xc412, 0x2b51, 0xc412, 0x21, 0 + .dw 0x2b53, 0xc412, 0x2b7f, 0xc412, 0x21, 0 + .dw 0x2b81, 0xc412, 0x2b81, 0xc412, 0x21, 0 + .dw 0x2b83, 0xc412, 0x2b8f, 0xc412, 0x21, 0 + .dw 0x2b91, 0xc412, 0x2b91, 0xc412, 0x21, 0 + .dw 0x2b93, 0xc412, 0x2bbf, 0xc412, 0x21, 0 + .dw 0x2bc1, 0xc412, 0x2bc1, 0xc412, 0x21, 0 + .dw 0x2bc3, 0xc412, 0x2bcf, 0xc412, 0x21, 0 + .dw 0x2bd1, 0xc412, 0x2bd1, 0xc412, 0x21, 0 + .dw 0x2bd3, 0xc412, 0x2bff, 0xc412, 0x21, 0 + .dw 0x2c01, 0xc412, 0x2c01, 0xc412, 0x21, 0 + .dw 0x2c03, 0xc412, 0x2c0f, 0xc412, 0x21, 0 + .dw 0x2c11, 0xc412, 0x2c11, 0xc412, 0x21, 0 + .dw 0x2c13, 0xc412, 0x2c3f, 0xc412, 0x21, 0 + .dw 0x2c41, 0xc412, 0x2c41, 0xc412, 0x21, 0 + .dw 0x2c43, 0xc412, 0x2c4f, 0xc412, 0x21, 0 + .dw 0x2c51, 0xc412, 0x2c51, 0xc412, 0x21, 0 + .dw 0x2c53, 0xc412, 0x2c7f, 0xc412, 0x21, 0 + .dw 0x2c81, 0xc412, 0x2c81, 0xc412, 0x21, 0 + .dw 0x2c83, 0xc412, 0x2c8f, 0xc412, 0x21, 0 + .dw 0x2c91, 0xc412, 0x2c91, 0xc412, 0x21, 0 + .dw 0x2c93, 0xc412, 0x2cbf, 0xc412, 0x21, 0 + .dw 0x2cc1, 0xc412, 0x2cc1, 0xc412, 0x21, 0 + .dw 0x2cc3, 0xc412, 0x2ccf, 0xc412, 0x21, 0 + .dw 0x2cd1, 0xc412, 0x2cd1, 0xc412, 0x21, 0 + .dw 0x2cd3, 0xc412, 0x2cff, 0xc412, 0x21, 0 + .dw 0x2d01, 0xc412, 0x2d01, 0xc412, 0x21, 0 + .dw 0x2d03, 0xc412, 0x2d0f, 0xc412, 0x21, 0 + .dw 0x2d11, 0xc412, 0x2d11, 0xc412, 0x21, 0 + .dw 0x2d13, 0xc412, 0x2d3f, 0xc412, 0x21, 0 + .dw 0x2d41, 0xc412, 0x2d41, 0xc412, 0x21, 0 + .dw 0x2d43, 0xc412, 0x2d4f, 0xc412, 0x21, 0 + .dw 0x2d51, 0xc412, 0x2d51, 0xc412, 0x21, 0 + .dw 0x2d53, 0xc412, 0x2d7f, 0xc412, 0x21, 0 + .dw 0x2d81, 0xc412, 0x2d81, 0xc412, 0x21, 0 + .dw 0x2d83, 0xc412, 0x2d8f, 0xc412, 0x21, 0 + .dw 0x2d91, 0xc412, 0x2d91, 0xc412, 0x21, 0 + .dw 0x2d93, 0xc412, 0x2dbf, 0xc412, 0x21, 0 + .dw 0x2dc1, 0xc412, 0x2dc1, 0xc412, 0x21, 0 + .dw 0x2dc3, 0xc412, 0x2dcf, 0xc412, 0x21, 0 + .dw 0x2dd1, 0xc412, 0x2dd1, 0xc412, 0x21, 0 + .dw 0x2dd3, 0xc412, 0x2dff, 0xc412, 0x21, 0 + .dw 0x2e01, 0xc412, 0x2e01, 0xc412, 0x21, 0 + .dw 0x2e03, 0xc412, 0x2e0f, 0xc412, 0x21, 0 + .dw 0x2e11, 0xc412, 0x2e11, 0xc412, 0x21, 0 + .dw 0x2e13, 0xc412, 0x2e3f, 0xc412, 0x21, 0 + .dw 0x2e41, 0xc412, 0x2e41, 0xc412, 0x21, 0 + .dw 0x2e43, 0xc412, 0x2e4f, 0xc412, 0x21, 0 + .dw 0x2e51, 0xc412, 0x2e51, 0xc412, 0x21, 0 + .dw 0x2e53, 0xc412, 0x2e7f, 0xc412, 0x21, 0 + .dw 0x2e81, 0xc412, 0x2e81, 0xc412, 0x21, 0 + .dw 0x2e83, 0xc412, 0x2e8f, 0xc412, 0x21, 0 + .dw 0x2e91, 0xc412, 0x2e91, 0xc412, 0x21, 0 + .dw 0x2e93, 0xc412, 0x2ebf, 0xc412, 0x21, 0 + .dw 0x2ec1, 0xc412, 0x2ec1, 0xc412, 0x21, 0 + .dw 0x2ec3, 0xc412, 0x2ecf, 0xc412, 0x21, 0 + .dw 0x2ed1, 0xc412, 0x2ed1, 0xc412, 0x21, 0 + .dw 0x2ed3, 0xc412, 0x2eff, 0xc412, 0x21, 0 + .dw 0x2f01, 0xc412, 0x2f01, 0xc412, 0x21, 0 + .dw 0x2f03, 0xc412, 0x2f0f, 0xc412, 0x21, 0 + .dw 0x2f11, 0xc412, 0x2f11, 0xc412, 0x21, 0 + .dw 0x2f13, 0xc412, 0x2f3f, 0xc412, 0x21, 0 + .dw 0x2f41, 0xc412, 0x2f41, 0xc412, 0x21, 0 + .dw 0x2f43, 0xc412, 0x2f4f, 0xc412, 0x21, 0 + .dw 0x2f51, 0xc412, 0x2f51, 0xc412, 0x21, 0 + .dw 0x2f53, 0xc412, 0x2f7f, 0xc412, 0x21, 0 + .dw 0x2f81, 0xc412, 0x2f81, 0xc412, 0x21, 0 + .dw 0x2f83, 0xc412, 0x2f8f, 0xc412, 0x21, 0 + .dw 0x2f91, 0xc412, 0x2f91, 0xc412, 0x21, 0 + .dw 0x2f93, 0xc412, 0x2fbf, 0xc412, 0x21, 0 + .dw 0x2fc1, 0xc412, 0x2fc1, 0xc412, 0x21, 0 + .dw 0x2fc3, 0xc412, 0x2fcf, 0xc412, 0x21, 0 + .dw 0x2fd1, 0xc412, 0x2fd1, 0xc412, 0x21, 0 + .dw 0x2fd3, 0xc412, 0xbfff, 0xc412, 0x21, 0 + .dw 0xd000, 0xc412, 0xffff, 0xc413, 0x21, 0 + .dw 0x0001, 0xc414, 0x0001, 0xc414, 0x21, 0 + .dw 0x0003, 0xc414, 0x000f, 0xc414, 0x21, 0 + .dw 0x0011, 0xc414, 0x0011, 0xc414, 0x21, 0 + .dw 0x0013, 0xc414, 0x003f, 0xc414, 0x21, 0 + .dw 0x0041, 0xc414, 0x0041, 0xc414, 0x21, 0 + .dw 0x0043, 0xc414, 0x004f, 0xc414, 0x21, 0 + .dw 0x0051, 0xc414, 0x0051, 0xc414, 0x21, 0 + .dw 0x0053, 0xc414, 0x007f, 0xc414, 0x21, 0 + .dw 0x0081, 0xc414, 0x0081, 0xc414, 0x21, 0 + .dw 0x0083, 0xc414, 0x008f, 0xc414, 0x21, 0 + .dw 0x0091, 0xc414, 0x0091, 0xc414, 0x21, 0 + .dw 0x0093, 0xc414, 0x00bf, 0xc414, 0x21, 0 + .dw 0x00c1, 0xc414, 0x00c1, 0xc414, 0x21, 0 + .dw 0x00c3, 0xc414, 0x00cf, 0xc414, 0x21, 0 + .dw 0x00d1, 0xc414, 0x00d1, 0xc414, 0x21, 0 + .dw 0x00d3, 0xc414, 0x00ff, 0xc414, 0x21, 0 + .dw 0x0101, 0xc414, 0x0101, 0xc414, 0x21, 0 + .dw 0x0103, 0xc414, 0x010f, 0xc414, 0x21, 0 + .dw 0x0111, 0xc414, 0x0111, 0xc414, 0x21, 0 + .dw 0x0113, 0xc414, 0x013f, 0xc414, 0x21, 0 + .dw 0x0141, 0xc414, 0x0141, 0xc414, 0x21, 0 + .dw 0x0143, 0xc414, 0x014f, 0xc414, 0x21, 0 + .dw 0x0151, 0xc414, 0x0151, 0xc414, 0x21, 0 + .dw 0x0153, 0xc414, 0x017f, 0xc414, 0x21, 0 + .dw 0x0181, 0xc414, 0x0181, 0xc414, 0x21, 0 + .dw 0x0183, 0xc414, 0x018f, 0xc414, 0x21, 0 + .dw 0x0191, 0xc414, 0x0191, 0xc414, 0x21, 0 + .dw 0x0193, 0xc414, 0x01bf, 0xc414, 0x21, 0 + .dw 0x01c1, 0xc414, 0x01c1, 0xc414, 0x21, 0 + .dw 0x01c3, 0xc414, 0x01cf, 0xc414, 0x21, 0 + .dw 0x01d1, 0xc414, 0x01d1, 0xc414, 0x21, 0 + .dw 0x01d3, 0xc414, 0x01ff, 0xc414, 0x21, 0 + .dw 0x0201, 0xc414, 0x0201, 0xc414, 0x21, 0 + .dw 0x0203, 0xc414, 0x020f, 0xc414, 0x21, 0 + .dw 0x0211, 0xc414, 0x0211, 0xc414, 0x21, 0 + .dw 0x0213, 0xc414, 0x023f, 0xc414, 0x21, 0 + .dw 0x0241, 0xc414, 0x0241, 0xc414, 0x21, 0 + .dw 0x0243, 0xc414, 0x024f, 0xc414, 0x21, 0 + .dw 0x0251, 0xc414, 0x0251, 0xc414, 0x21, 0 + .dw 0x0253, 0xc414, 0x027f, 0xc414, 0x21, 0 + .dw 0x0281, 0xc414, 0x0281, 0xc414, 0x21, 0 + .dw 0x0283, 0xc414, 0x028f, 0xc414, 0x21, 0 + .dw 0x0291, 0xc414, 0x0291, 0xc414, 0x21, 0 + .dw 0x0293, 0xc414, 0x02bf, 0xc414, 0x21, 0 + .dw 0x02c1, 0xc414, 0x02c1, 0xc414, 0x21, 0 + .dw 0x02c3, 0xc414, 0x02cf, 0xc414, 0x21, 0 + .dw 0x02d1, 0xc414, 0x02d1, 0xc414, 0x21, 0 + .dw 0x02d3, 0xc414, 0x02ff, 0xc414, 0x21, 0 + .dw 0x0301, 0xc414, 0x0301, 0xc414, 0x21, 0 + .dw 0x0303, 0xc414, 0x030f, 0xc414, 0x21, 0 + .dw 0x0311, 0xc414, 0x0311, 0xc414, 0x21, 0 + .dw 0x0313, 0xc414, 0x033f, 0xc414, 0x21, 0 + .dw 0x0341, 0xc414, 0x0341, 0xc414, 0x21, 0 + .dw 0x0343, 0xc414, 0x034f, 0xc414, 0x21, 0 + .dw 0x0351, 0xc414, 0x0351, 0xc414, 0x21, 0 + .dw 0x0353, 0xc414, 0x037f, 0xc414, 0x21, 0 + .dw 0x0381, 0xc414, 0x0381, 0xc414, 0x21, 0 + .dw 0x0383, 0xc414, 0x038f, 0xc414, 0x21, 0 + .dw 0x0391, 0xc414, 0x0391, 0xc414, 0x21, 0 + .dw 0x0393, 0xc414, 0x03bf, 0xc414, 0x21, 0 + .dw 0x03c1, 0xc414, 0x03c1, 0xc414, 0x21, 0 + .dw 0x03c3, 0xc414, 0x03cf, 0xc414, 0x21, 0 + .dw 0x03d1, 0xc414, 0x03d1, 0xc414, 0x21, 0 + .dw 0x03d3, 0xc414, 0x03ff, 0xc414, 0x21, 0 + .dw 0x0401, 0xc414, 0x0401, 0xc414, 0x21, 0 + .dw 0x0403, 0xc414, 0x040f, 0xc414, 0x21, 0 + .dw 0x0411, 0xc414, 0x0411, 0xc414, 0x21, 0 + .dw 0x0413, 0xc414, 0x043f, 0xc414, 0x21, 0 + .dw 0x0441, 0xc414, 0x0441, 0xc414, 0x21, 0 + .dw 0x0443, 0xc414, 0x044f, 0xc414, 0x21, 0 + .dw 0x0451, 0xc414, 0x0451, 0xc414, 0x21, 0 + .dw 0x0453, 0xc414, 0x047f, 0xc414, 0x21, 0 + .dw 0x0481, 0xc414, 0x0481, 0xc414, 0x21, 0 + .dw 0x0483, 0xc414, 0x048f, 0xc414, 0x21, 0 + .dw 0x0491, 0xc414, 0x0491, 0xc414, 0x21, 0 + .dw 0x0493, 0xc414, 0x04bf, 0xc414, 0x21, 0 + .dw 0x04c1, 0xc414, 0x04c1, 0xc414, 0x21, 0 + .dw 0x04c3, 0xc414, 0x04cf, 0xc414, 0x21, 0 + .dw 0x04d1, 0xc414, 0x04d1, 0xc414, 0x21, 0 + .dw 0x04d3, 0xc414, 0x04ff, 0xc414, 0x21, 0 + .dw 0x0501, 0xc414, 0x0501, 0xc414, 0x21, 0 + .dw 0x0503, 0xc414, 0x050f, 0xc414, 0x21, 0 + .dw 0x0511, 0xc414, 0x0511, 0xc414, 0x21, 0 + .dw 0x0513, 0xc414, 0x053f, 0xc414, 0x21, 0 + .dw 0x0541, 0xc414, 0x0541, 0xc414, 0x21, 0 + .dw 0x0543, 0xc414, 0x054f, 0xc414, 0x21, 0 + .dw 0x0551, 0xc414, 0x0551, 0xc414, 0x21, 0 + .dw 0x0553, 0xc414, 0x057f, 0xc414, 0x21, 0 + .dw 0x0581, 0xc414, 0x0581, 0xc414, 0x21, 0 + .dw 0x0583, 0xc414, 0x058f, 0xc414, 0x21, 0 + .dw 0x0591, 0xc414, 0x0591, 0xc414, 0x21, 0 + .dw 0x0593, 0xc414, 0x05bf, 0xc414, 0x21, 0 + .dw 0x05c1, 0xc414, 0x05c1, 0xc414, 0x21, 0 + .dw 0x05c3, 0xc414, 0x05cf, 0xc414, 0x21, 0 + .dw 0x05d1, 0xc414, 0x05d1, 0xc414, 0x21, 0 + .dw 0x05d3, 0xc414, 0x05ff, 0xc414, 0x21, 0 + .dw 0x0601, 0xc414, 0x0601, 0xc414, 0x21, 0 + .dw 0x0603, 0xc414, 0x060f, 0xc414, 0x21, 0 + .dw 0x0611, 0xc414, 0x0611, 0xc414, 0x21, 0 + .dw 0x0613, 0xc414, 0x063f, 0xc414, 0x21, 0 + .dw 0x0641, 0xc414, 0x0641, 0xc414, 0x21, 0 + .dw 0x0643, 0xc414, 0x064f, 0xc414, 0x21, 0 + .dw 0x0651, 0xc414, 0x0651, 0xc414, 0x21, 0 + .dw 0x0653, 0xc414, 0x067f, 0xc414, 0x21, 0 + .dw 0x0681, 0xc414, 0x0681, 0xc414, 0x21, 0 + .dw 0x0683, 0xc414, 0x068f, 0xc414, 0x21, 0 + .dw 0x0691, 0xc414, 0x0691, 0xc414, 0x21, 0 + .dw 0x0693, 0xc414, 0x06bf, 0xc414, 0x21, 0 + .dw 0x06c1, 0xc414, 0x06c1, 0xc414, 0x21, 0 + .dw 0x06c3, 0xc414, 0x06cf, 0xc414, 0x21, 0 + .dw 0x06d1, 0xc414, 0x06d1, 0xc414, 0x21, 0 + .dw 0x06d3, 0xc414, 0x06ff, 0xc414, 0x21, 0 + .dw 0x0701, 0xc414, 0x0701, 0xc414, 0x21, 0 + .dw 0x0703, 0xc414, 0x070f, 0xc414, 0x21, 0 + .dw 0x0711, 0xc414, 0x0711, 0xc414, 0x21, 0 + .dw 0x0713, 0xc414, 0x073f, 0xc414, 0x21, 0 + .dw 0x0741, 0xc414, 0x0741, 0xc414, 0x21, 0 + .dw 0x0743, 0xc414, 0x074f, 0xc414, 0x21, 0 + .dw 0x0751, 0xc414, 0x0751, 0xc414, 0x21, 0 + .dw 0x0753, 0xc414, 0x077f, 0xc414, 0x21, 0 + .dw 0x0781, 0xc414, 0x0781, 0xc414, 0x21, 0 + .dw 0x0783, 0xc414, 0x078f, 0xc414, 0x21, 0 + .dw 0x0791, 0xc414, 0x0791, 0xc414, 0x21, 0 + .dw 0x0793, 0xc414, 0x07bf, 0xc414, 0x21, 0 + .dw 0x07c1, 0xc414, 0x07c1, 0xc414, 0x21, 0 + .dw 0x07c3, 0xc414, 0x07cf, 0xc414, 0x21, 0 + .dw 0x07d1, 0xc414, 0x07d1, 0xc414, 0x21, 0 + .dw 0x07d3, 0xc414, 0x07ff, 0xc414, 0x21, 0 + .dw 0x0801, 0xc414, 0x0801, 0xc414, 0x21, 0 + .dw 0x0803, 0xc414, 0x080f, 0xc414, 0x21, 0 + .dw 0x0811, 0xc414, 0x0811, 0xc414, 0x21, 0 + .dw 0x0813, 0xc414, 0x083f, 0xc414, 0x21, 0 + .dw 0x0841, 0xc414, 0x0841, 0xc414, 0x21, 0 + .dw 0x0843, 0xc414, 0x084f, 0xc414, 0x21, 0 + .dw 0x0851, 0xc414, 0x0851, 0xc414, 0x21, 0 + .dw 0x0853, 0xc414, 0x087f, 0xc414, 0x21, 0 + .dw 0x0881, 0xc414, 0x0881, 0xc414, 0x21, 0 + .dw 0x0883, 0xc414, 0x088f, 0xc414, 0x21, 0 + .dw 0x0891, 0xc414, 0x0891, 0xc414, 0x21, 0 + .dw 0x0893, 0xc414, 0x08bf, 0xc414, 0x21, 0 + .dw 0x08c1, 0xc414, 0x08c1, 0xc414, 0x21, 0 + .dw 0x08c3, 0xc414, 0x08cf, 0xc414, 0x21, 0 + .dw 0x08d1, 0xc414, 0x08d1, 0xc414, 0x21, 0 + .dw 0x08d3, 0xc414, 0x08ff, 0xc414, 0x21, 0 + .dw 0x0901, 0xc414, 0x0901, 0xc414, 0x21, 0 + .dw 0x0903, 0xc414, 0x090f, 0xc414, 0x21, 0 + .dw 0x0911, 0xc414, 0x0911, 0xc414, 0x21, 0 + .dw 0x0913, 0xc414, 0x093f, 0xc414, 0x21, 0 + .dw 0x0941, 0xc414, 0x0941, 0xc414, 0x21, 0 + .dw 0x0943, 0xc414, 0x094f, 0xc414, 0x21, 0 + .dw 0x0951, 0xc414, 0x0951, 0xc414, 0x21, 0 + .dw 0x0953, 0xc414, 0x097f, 0xc414, 0x21, 0 + .dw 0x0981, 0xc414, 0x0981, 0xc414, 0x21, 0 + .dw 0x0983, 0xc414, 0x098f, 0xc414, 0x21, 0 + .dw 0x0991, 0xc414, 0x0991, 0xc414, 0x21, 0 + .dw 0x0993, 0xc414, 0x09bf, 0xc414, 0x21, 0 + .dw 0x09c1, 0xc414, 0x09c1, 0xc414, 0x21, 0 + .dw 0x09c3, 0xc414, 0x09cf, 0xc414, 0x21, 0 + .dw 0x09d1, 0xc414, 0x09d1, 0xc414, 0x21, 0 + .dw 0x09d3, 0xc414, 0x09ff, 0xc414, 0x21, 0 + .dw 0x0a01, 0xc414, 0x0a01, 0xc414, 0x21, 0 + .dw 0x0a03, 0xc414, 0x0a0f, 0xc414, 0x21, 0 + .dw 0x0a11, 0xc414, 0x0a11, 0xc414, 0x21, 0 + .dw 0x0a13, 0xc414, 0x0a3f, 0xc414, 0x21, 0 + .dw 0x0a41, 0xc414, 0x0a41, 0xc414, 0x21, 0 + .dw 0x0a43, 0xc414, 0x0a4f, 0xc414, 0x21, 0 + .dw 0x0a51, 0xc414, 0x0a51, 0xc414, 0x21, 0 + .dw 0x0a53, 0xc414, 0x0a7f, 0xc414, 0x21, 0 + .dw 0x0a81, 0xc414, 0x0a81, 0xc414, 0x21, 0 + .dw 0x0a83, 0xc414, 0x0a8f, 0xc414, 0x21, 0 + .dw 0x0a91, 0xc414, 0x0a91, 0xc414, 0x21, 0 + .dw 0x0a93, 0xc414, 0x0abf, 0xc414, 0x21, 0 + .dw 0x0ac1, 0xc414, 0x0ac1, 0xc414, 0x21, 0 + .dw 0x0ac3, 0xc414, 0x0acf, 0xc414, 0x21, 0 + .dw 0x0ad1, 0xc414, 0x0ad1, 0xc414, 0x21, 0 + .dw 0x0ad3, 0xc414, 0x0aff, 0xc414, 0x21, 0 + .dw 0x0b01, 0xc414, 0x0b01, 0xc414, 0x21, 0 + .dw 0x0b03, 0xc414, 0x0b0f, 0xc414, 0x21, 0 + .dw 0x0b11, 0xc414, 0x0b11, 0xc414, 0x21, 0 + .dw 0x0b13, 0xc414, 0x0b3f, 0xc414, 0x21, 0 + .dw 0x0b41, 0xc414, 0x0b41, 0xc414, 0x21, 0 + .dw 0x0b43, 0xc414, 0x0b4f, 0xc414, 0x21, 0 + .dw 0x0b51, 0xc414, 0x0b51, 0xc414, 0x21, 0 + .dw 0x0b53, 0xc414, 0x0b7f, 0xc414, 0x21, 0 + .dw 0x0b81, 0xc414, 0x0b81, 0xc414, 0x21, 0 + .dw 0x0b83, 0xc414, 0x0b8f, 0xc414, 0x21, 0 + .dw 0x0b91, 0xc414, 0x0b91, 0xc414, 0x21, 0 + .dw 0x0b93, 0xc414, 0x0bbf, 0xc414, 0x21, 0 + .dw 0x0bc1, 0xc414, 0x0bc1, 0xc414, 0x21, 0 + .dw 0x0bc3, 0xc414, 0x0bcf, 0xc414, 0x21, 0 + .dw 0x0bd1, 0xc414, 0x0bd1, 0xc414, 0x21, 0 + .dw 0x0bd3, 0xc414, 0x0bff, 0xc414, 0x21, 0 + .dw 0x0c01, 0xc414, 0x0c01, 0xc414, 0x21, 0 + .dw 0x0c03, 0xc414, 0x0c0f, 0xc414, 0x21, 0 + .dw 0x0c11, 0xc414, 0x0c11, 0xc414, 0x21, 0 + .dw 0x0c13, 0xc414, 0x0c3f, 0xc414, 0x21, 0 + .dw 0x0c41, 0xc414, 0x0c41, 0xc414, 0x21, 0 + .dw 0x0c43, 0xc414, 0x0c4f, 0xc414, 0x21, 0 + .dw 0x0c51, 0xc414, 0x0c51, 0xc414, 0x21, 0 + .dw 0x0c53, 0xc414, 0x0c7f, 0xc414, 0x21, 0 + .dw 0x0c81, 0xc414, 0x0c81, 0xc414, 0x21, 0 + .dw 0x0c83, 0xc414, 0x0c8f, 0xc414, 0x21, 0 + .dw 0x0c91, 0xc414, 0x0c91, 0xc414, 0x21, 0 + .dw 0x0c93, 0xc414, 0x0cbf, 0xc414, 0x21, 0 + .dw 0x0cc1, 0xc414, 0x0cc1, 0xc414, 0x21, 0 + .dw 0x0cc3, 0xc414, 0x0ccf, 0xc414, 0x21, 0 + .dw 0x0cd1, 0xc414, 0x0cd1, 0xc414, 0x21, 0 + .dw 0x0cd3, 0xc414, 0x0cff, 0xc414, 0x21, 0 + .dw 0x0d01, 0xc414, 0x0d01, 0xc414, 0x21, 0 + .dw 0x0d03, 0xc414, 0x0d0f, 0xc414, 0x21, 0 + .dw 0x0d11, 0xc414, 0x0d11, 0xc414, 0x21, 0 + .dw 0x0d13, 0xc414, 0x0d3f, 0xc414, 0x21, 0 + .dw 0x0d41, 0xc414, 0x0d41, 0xc414, 0x21, 0 + .dw 0x0d43, 0xc414, 0x0d4f, 0xc414, 0x21, 0 + .dw 0x0d51, 0xc414, 0x0d51, 0xc414, 0x21, 0 + .dw 0x0d53, 0xc414, 0x0d7f, 0xc414, 0x21, 0 + .dw 0x0d81, 0xc414, 0x0d81, 0xc414, 0x21, 0 + .dw 0x0d83, 0xc414, 0x0d8f, 0xc414, 0x21, 0 + .dw 0x0d91, 0xc414, 0x0d91, 0xc414, 0x21, 0 + .dw 0x0d93, 0xc414, 0x0dbf, 0xc414, 0x21, 0 + .dw 0x0dc1, 0xc414, 0x0dc1, 0xc414, 0x21, 0 + .dw 0x0dc3, 0xc414, 0x0dcf, 0xc414, 0x21, 0 + .dw 0x0dd1, 0xc414, 0x0dd1, 0xc414, 0x21, 0 + .dw 0x0dd3, 0xc414, 0x0dff, 0xc414, 0x21, 0 + .dw 0x0e01, 0xc414, 0x0e01, 0xc414, 0x21, 0 + .dw 0x0e03, 0xc414, 0x0e0f, 0xc414, 0x21, 0 + .dw 0x0e11, 0xc414, 0x0e11, 0xc414, 0x21, 0 + .dw 0x0e13, 0xc414, 0x0e3f, 0xc414, 0x21, 0 + .dw 0x0e41, 0xc414, 0x0e41, 0xc414, 0x21, 0 + .dw 0x0e43, 0xc414, 0x0e4f, 0xc414, 0x21, 0 + .dw 0x0e51, 0xc414, 0x0e51, 0xc414, 0x21, 0 + .dw 0x0e53, 0xc414, 0x0e7f, 0xc414, 0x21, 0 + .dw 0x0e81, 0xc414, 0x0e81, 0xc414, 0x21, 0 + .dw 0x0e83, 0xc414, 0x0e8f, 0xc414, 0x21, 0 + .dw 0x0e91, 0xc414, 0x0e91, 0xc414, 0x21, 0 + .dw 0x0e93, 0xc414, 0x0ebf, 0xc414, 0x21, 0 + .dw 0x0ec1, 0xc414, 0x0ec1, 0xc414, 0x21, 0 + .dw 0x0ec3, 0xc414, 0x0ecf, 0xc414, 0x21, 0 + .dw 0x0ed1, 0xc414, 0x0ed1, 0xc414, 0x21, 0 + .dw 0x0ed3, 0xc414, 0x0eff, 0xc414, 0x21, 0 + .dw 0x0f01, 0xc414, 0x0f01, 0xc414, 0x21, 0 + .dw 0x0f03, 0xc414, 0x0f0f, 0xc414, 0x21, 0 + .dw 0x0f11, 0xc414, 0x0f11, 0xc414, 0x21, 0 + .dw 0x0f13, 0xc414, 0x0f3f, 0xc414, 0x21, 0 + .dw 0x0f41, 0xc414, 0x0f41, 0xc414, 0x21, 0 + .dw 0x0f43, 0xc414, 0x0f4f, 0xc414, 0x21, 0 + .dw 0x0f51, 0xc414, 0x0f51, 0xc414, 0x21, 0 + .dw 0x0f53, 0xc414, 0x0f7f, 0xc414, 0x21, 0 + .dw 0x0f81, 0xc414, 0x0f81, 0xc414, 0x21, 0 + .dw 0x0f83, 0xc414, 0x0f8f, 0xc414, 0x21, 0 + .dw 0x0f91, 0xc414, 0x0f91, 0xc414, 0x21, 0 + .dw 0x0f93, 0xc414, 0x0fbf, 0xc414, 0x21, 0 + .dw 0x0fc1, 0xc414, 0x0fc1, 0xc414, 0x21, 0 + .dw 0x0fc3, 0xc414, 0x0fcf, 0xc414, 0x21, 0 + .dw 0x0fd1, 0xc414, 0x0fd1, 0xc414, 0x21, 0 + .dw 0x0fd3, 0xc414, 0x1fff, 0xc414, 0x21, 0 + .dw 0x2001, 0xc414, 0x2001, 0xc414, 0x21, 0 + .dw 0x2003, 0xc414, 0x200f, 0xc414, 0x21, 0 + .dw 0x2011, 0xc414, 0x2011, 0xc414, 0x21, 0 + .dw 0x2013, 0xc414, 0x203f, 0xc414, 0x21, 0 + .dw 0x2041, 0xc414, 0x2041, 0xc414, 0x21, 0 + .dw 0x2043, 0xc414, 0x204f, 0xc414, 0x21, 0 + .dw 0x2051, 0xc414, 0x2051, 0xc414, 0x21, 0 + .dw 0x2053, 0xc414, 0x207f, 0xc414, 0x21, 0 + .dw 0x2081, 0xc414, 0x2081, 0xc414, 0x21, 0 + .dw 0x2083, 0xc414, 0x208f, 0xc414, 0x21, 0 + .dw 0x2091, 0xc414, 0x2091, 0xc414, 0x21, 0 + .dw 0x2093, 0xc414, 0x20bf, 0xc414, 0x21, 0 + .dw 0x20c1, 0xc414, 0x20c1, 0xc414, 0x21, 0 + .dw 0x20c3, 0xc414, 0x20cf, 0xc414, 0x21, 0 + .dw 0x20d1, 0xc414, 0x20d1, 0xc414, 0x21, 0 + .dw 0x20d3, 0xc414, 0x20ff, 0xc414, 0x21, 0 + .dw 0x2101, 0xc414, 0x2101, 0xc414, 0x21, 0 + .dw 0x2103, 0xc414, 0x210f, 0xc414, 0x21, 0 + .dw 0x2111, 0xc414, 0x2111, 0xc414, 0x21, 0 + .dw 0x2113, 0xc414, 0x213f, 0xc414, 0x21, 0 + .dw 0x2141, 0xc414, 0x2141, 0xc414, 0x21, 0 + .dw 0x2143, 0xc414, 0x214f, 0xc414, 0x21, 0 + .dw 0x2151, 0xc414, 0x2151, 0xc414, 0x21, 0 + .dw 0x2153, 0xc414, 0x217f, 0xc414, 0x21, 0 + .dw 0x2181, 0xc414, 0x2181, 0xc414, 0x21, 0 + .dw 0x2183, 0xc414, 0x218f, 0xc414, 0x21, 0 + .dw 0x2191, 0xc414, 0x2191, 0xc414, 0x21, 0 + .dw 0x2193, 0xc414, 0x21bf, 0xc414, 0x21, 0 + .dw 0x21c1, 0xc414, 0x21c1, 0xc414, 0x21, 0 + .dw 0x21c3, 0xc414, 0x21cf, 0xc414, 0x21, 0 + .dw 0x21d1, 0xc414, 0x21d1, 0xc414, 0x21, 0 + .dw 0x21d3, 0xc414, 0x21ff, 0xc414, 0x21, 0 + .dw 0x2201, 0xc414, 0x2201, 0xc414, 0x21, 0 + .dw 0x2203, 0xc414, 0x220f, 0xc414, 0x21, 0 + .dw 0x2211, 0xc414, 0x2211, 0xc414, 0x21, 0 + .dw 0x2213, 0xc414, 0x223f, 0xc414, 0x21, 0 + .dw 0x2241, 0xc414, 0x2241, 0xc414, 0x21, 0 + .dw 0x2243, 0xc414, 0x224f, 0xc414, 0x21, 0 + .dw 0x2251, 0xc414, 0x2251, 0xc414, 0x21, 0 + .dw 0x2253, 0xc414, 0x227f, 0xc414, 0x21, 0 + .dw 0x2281, 0xc414, 0x2281, 0xc414, 0x21, 0 + .dw 0x2283, 0xc414, 0x228f, 0xc414, 0x21, 0 + .dw 0x2291, 0xc414, 0x2291, 0xc414, 0x21, 0 + .dw 0x2293, 0xc414, 0x22bf, 0xc414, 0x21, 0 + .dw 0x22c1, 0xc414, 0x22c1, 0xc414, 0x21, 0 + .dw 0x22c3, 0xc414, 0x22cf, 0xc414, 0x21, 0 + .dw 0x22d1, 0xc414, 0x22d1, 0xc414, 0x21, 0 + .dw 0x22d3, 0xc414, 0x22ff, 0xc414, 0x21, 0 + .dw 0x2301, 0xc414, 0x2301, 0xc414, 0x21, 0 + .dw 0x2303, 0xc414, 0x230f, 0xc414, 0x21, 0 + .dw 0x2311, 0xc414, 0x2311, 0xc414, 0x21, 0 + .dw 0x2313, 0xc414, 0x233f, 0xc414, 0x21, 0 + .dw 0x2341, 0xc414, 0x2341, 0xc414, 0x21, 0 + .dw 0x2343, 0xc414, 0x234f, 0xc414, 0x21, 0 + .dw 0x2351, 0xc414, 0x2351, 0xc414, 0x21, 0 + .dw 0x2353, 0xc414, 0x237f, 0xc414, 0x21, 0 + .dw 0x2381, 0xc414, 0x2381, 0xc414, 0x21, 0 + .dw 0x2383, 0xc414, 0x238f, 0xc414, 0x21, 0 + .dw 0x2391, 0xc414, 0x2391, 0xc414, 0x21, 0 + .dw 0x2393, 0xc414, 0x23bf, 0xc414, 0x21, 0 + .dw 0x23c1, 0xc414, 0x23c1, 0xc414, 0x21, 0 + .dw 0x23c3, 0xc414, 0x23cf, 0xc414, 0x21, 0 + .dw 0x23d1, 0xc414, 0x23d1, 0xc414, 0x21, 0 + .dw 0x23d3, 0xc414, 0x23ff, 0xc414, 0x21, 0 + .dw 0x2401, 0xc414, 0x2401, 0xc414, 0x21, 0 + .dw 0x2403, 0xc414, 0x240f, 0xc414, 0x21, 0 + .dw 0x2411, 0xc414, 0x2411, 0xc414, 0x21, 0 + .dw 0x2413, 0xc414, 0x243f, 0xc414, 0x21, 0 + .dw 0x2441, 0xc414, 0x2441, 0xc414, 0x21, 0 + .dw 0x2443, 0xc414, 0x244f, 0xc414, 0x21, 0 + .dw 0x2451, 0xc414, 0x2451, 0xc414, 0x21, 0 + .dw 0x2453, 0xc414, 0x247f, 0xc414, 0x21, 0 + .dw 0x2481, 0xc414, 0x2481, 0xc414, 0x21, 0 + .dw 0x2483, 0xc414, 0x248f, 0xc414, 0x21, 0 + .dw 0x2491, 0xc414, 0x2491, 0xc414, 0x21, 0 + .dw 0x2493, 0xc414, 0x24bf, 0xc414, 0x21, 0 + .dw 0x24c1, 0xc414, 0x24c1, 0xc414, 0x21, 0 + .dw 0x24c3, 0xc414, 0x24cf, 0xc414, 0x21, 0 + .dw 0x24d1, 0xc414, 0x24d1, 0xc414, 0x21, 0 + .dw 0x24d3, 0xc414, 0x24ff, 0xc414, 0x21, 0 + .dw 0x2501, 0xc414, 0x2501, 0xc414, 0x21, 0 + .dw 0x2503, 0xc414, 0x250f, 0xc414, 0x21, 0 + .dw 0x2511, 0xc414, 0x2511, 0xc414, 0x21, 0 + .dw 0x2513, 0xc414, 0x253f, 0xc414, 0x21, 0 + .dw 0x2541, 0xc414, 0x2541, 0xc414, 0x21, 0 + .dw 0x2543, 0xc414, 0x254f, 0xc414, 0x21, 0 + .dw 0x2551, 0xc414, 0x2551, 0xc414, 0x21, 0 + .dw 0x2553, 0xc414, 0x257f, 0xc414, 0x21, 0 + .dw 0x2581, 0xc414, 0x2581, 0xc414, 0x21, 0 + .dw 0x2583, 0xc414, 0x258f, 0xc414, 0x21, 0 + .dw 0x2591, 0xc414, 0x2591, 0xc414, 0x21, 0 + .dw 0x2593, 0xc414, 0x25bf, 0xc414, 0x21, 0 + .dw 0x25c1, 0xc414, 0x25c1, 0xc414, 0x21, 0 + .dw 0x25c3, 0xc414, 0x25cf, 0xc414, 0x21, 0 + .dw 0x25d1, 0xc414, 0x25d1, 0xc414, 0x21, 0 + .dw 0x25d3, 0xc414, 0x25ff, 0xc414, 0x21, 0 + .dw 0x2601, 0xc414, 0x2601, 0xc414, 0x21, 0 + .dw 0x2603, 0xc414, 0x260f, 0xc414, 0x21, 0 + .dw 0x2611, 0xc414, 0x2611, 0xc414, 0x21, 0 + .dw 0x2613, 0xc414, 0x263f, 0xc414, 0x21, 0 + .dw 0x2641, 0xc414, 0x2641, 0xc414, 0x21, 0 + .dw 0x2643, 0xc414, 0x264f, 0xc414, 0x21, 0 + .dw 0x2651, 0xc414, 0x2651, 0xc414, 0x21, 0 + .dw 0x2653, 0xc414, 0x267f, 0xc414, 0x21, 0 + .dw 0x2681, 0xc414, 0x2681, 0xc414, 0x21, 0 + .dw 0x2683, 0xc414, 0x268f, 0xc414, 0x21, 0 + .dw 0x2691, 0xc414, 0x2691, 0xc414, 0x21, 0 + .dw 0x2693, 0xc414, 0x26bf, 0xc414, 0x21, 0 + .dw 0x26c1, 0xc414, 0x26c1, 0xc414, 0x21, 0 + .dw 0x26c3, 0xc414, 0x26cf, 0xc414, 0x21, 0 + .dw 0x26d1, 0xc414, 0x26d1, 0xc414, 0x21, 0 + .dw 0x26d3, 0xc414, 0x26ff, 0xc414, 0x21, 0 + .dw 0x2701, 0xc414, 0x2701, 0xc414, 0x21, 0 + .dw 0x2703, 0xc414, 0x270f, 0xc414, 0x21, 0 + .dw 0x2711, 0xc414, 0x2711, 0xc414, 0x21, 0 + .dw 0x2713, 0xc414, 0x273f, 0xc414, 0x21, 0 + .dw 0x2741, 0xc414, 0x2741, 0xc414, 0x21, 0 + .dw 0x2743, 0xc414, 0x274f, 0xc414, 0x21, 0 + .dw 0x2751, 0xc414, 0x2751, 0xc414, 0x21, 0 + .dw 0x2753, 0xc414, 0x277f, 0xc414, 0x21, 0 + .dw 0x2781, 0xc414, 0x2781, 0xc414, 0x21, 0 + .dw 0x2783, 0xc414, 0x278f, 0xc414, 0x21, 0 + .dw 0x2791, 0xc414, 0x2791, 0xc414, 0x21, 0 + .dw 0x2793, 0xc414, 0x27bf, 0xc414, 0x21, 0 + .dw 0x27c1, 0xc414, 0x27c1, 0xc414, 0x21, 0 + .dw 0x27c3, 0xc414, 0x27cf, 0xc414, 0x21, 0 + .dw 0x27d1, 0xc414, 0x27d1, 0xc414, 0x21, 0 + .dw 0x27d3, 0xc414, 0x27ff, 0xc414, 0x21, 0 + .dw 0x2801, 0xc414, 0x2801, 0xc414, 0x21, 0 + .dw 0x2803, 0xc414, 0x280f, 0xc414, 0x21, 0 + .dw 0x2811, 0xc414, 0x2811, 0xc414, 0x21, 0 + .dw 0x2813, 0xc414, 0x283f, 0xc414, 0x21, 0 + .dw 0x2841, 0xc414, 0x2841, 0xc414, 0x21, 0 + .dw 0x2843, 0xc414, 0x284f, 0xc414, 0x21, 0 + .dw 0x2851, 0xc414, 0x2851, 0xc414, 0x21, 0 + .dw 0x2853, 0xc414, 0x287f, 0xc414, 0x21, 0 + .dw 0x2881, 0xc414, 0x2881, 0xc414, 0x21, 0 + .dw 0x2883, 0xc414, 0x288f, 0xc414, 0x21, 0 + .dw 0x2891, 0xc414, 0x2891, 0xc414, 0x21, 0 + .dw 0x2893, 0xc414, 0x28bf, 0xc414, 0x21, 0 + .dw 0x28c1, 0xc414, 0x28c1, 0xc414, 0x21, 0 + .dw 0x28c3, 0xc414, 0x28cf, 0xc414, 0x21, 0 + .dw 0x28d1, 0xc414, 0x28d1, 0xc414, 0x21, 0 + .dw 0x28d3, 0xc414, 0x28ff, 0xc414, 0x21, 0 + .dw 0x2901, 0xc414, 0x2901, 0xc414, 0x21, 0 + .dw 0x2903, 0xc414, 0x290f, 0xc414, 0x21, 0 + .dw 0x2911, 0xc414, 0x2911, 0xc414, 0x21, 0 + .dw 0x2913, 0xc414, 0x293f, 0xc414, 0x21, 0 + .dw 0x2941, 0xc414, 0x2941, 0xc414, 0x21, 0 + .dw 0x2943, 0xc414, 0x294f, 0xc414, 0x21, 0 + .dw 0x2951, 0xc414, 0x2951, 0xc414, 0x21, 0 + .dw 0x2953, 0xc414, 0x297f, 0xc414, 0x21, 0 + .dw 0x2981, 0xc414, 0x2981, 0xc414, 0x21, 0 + .dw 0x2983, 0xc414, 0x298f, 0xc414, 0x21, 0 + .dw 0x2991, 0xc414, 0x2991, 0xc414, 0x21, 0 + .dw 0x2993, 0xc414, 0x29bf, 0xc414, 0x21, 0 + .dw 0x29c1, 0xc414, 0x29c1, 0xc414, 0x21, 0 + .dw 0x29c3, 0xc414, 0x29cf, 0xc414, 0x21, 0 + .dw 0x29d1, 0xc414, 0x29d1, 0xc414, 0x21, 0 + .dw 0x29d3, 0xc414, 0x29ff, 0xc414, 0x21, 0 + .dw 0x2a01, 0xc414, 0x2a01, 0xc414, 0x21, 0 + .dw 0x2a03, 0xc414, 0x2a0f, 0xc414, 0x21, 0 + .dw 0x2a11, 0xc414, 0x2a11, 0xc414, 0x21, 0 + .dw 0x2a13, 0xc414, 0x2a3f, 0xc414, 0x21, 0 + .dw 0x2a41, 0xc414, 0x2a41, 0xc414, 0x21, 0 + .dw 0x2a43, 0xc414, 0x2a4f, 0xc414, 0x21, 0 + .dw 0x2a51, 0xc414, 0x2a51, 0xc414, 0x21, 0 + .dw 0x2a53, 0xc414, 0x2a7f, 0xc414, 0x21, 0 + .dw 0x2a81, 0xc414, 0x2a81, 0xc414, 0x21, 0 + .dw 0x2a83, 0xc414, 0x2a8f, 0xc414, 0x21, 0 + .dw 0x2a91, 0xc414, 0x2a91, 0xc414, 0x21, 0 + .dw 0x2a93, 0xc414, 0x2abf, 0xc414, 0x21, 0 + .dw 0x2ac1, 0xc414, 0x2ac1, 0xc414, 0x21, 0 + .dw 0x2ac3, 0xc414, 0x2acf, 0xc414, 0x21, 0 + .dw 0x2ad1, 0xc414, 0x2ad1, 0xc414, 0x21, 0 + .dw 0x2ad3, 0xc414, 0x2aff, 0xc414, 0x21, 0 + .dw 0x2b01, 0xc414, 0x2b01, 0xc414, 0x21, 0 + .dw 0x2b03, 0xc414, 0x2b0f, 0xc414, 0x21, 0 + .dw 0x2b11, 0xc414, 0x2b11, 0xc414, 0x21, 0 + .dw 0x2b13, 0xc414, 0x2b3f, 0xc414, 0x21, 0 + .dw 0x2b41, 0xc414, 0x2b41, 0xc414, 0x21, 0 + .dw 0x2b43, 0xc414, 0x2b4f, 0xc414, 0x21, 0 + .dw 0x2b51, 0xc414, 0x2b51, 0xc414, 0x21, 0 + .dw 0x2b53, 0xc414, 0x2b7f, 0xc414, 0x21, 0 + .dw 0x2b81, 0xc414, 0x2b81, 0xc414, 0x21, 0 + .dw 0x2b83, 0xc414, 0x2b8f, 0xc414, 0x21, 0 + .dw 0x2b91, 0xc414, 0x2b91, 0xc414, 0x21, 0 + .dw 0x2b93, 0xc414, 0x2bbf, 0xc414, 0x21, 0 + .dw 0x2bc1, 0xc414, 0x2bc1, 0xc414, 0x21, 0 + .dw 0x2bc3, 0xc414, 0x2bcf, 0xc414, 0x21, 0 + .dw 0x2bd1, 0xc414, 0x2bd1, 0xc414, 0x21, 0 + .dw 0x2bd3, 0xc414, 0x2bff, 0xc414, 0x21, 0 + .dw 0x2c01, 0xc414, 0x2c01, 0xc414, 0x21, 0 + .dw 0x2c03, 0xc414, 0x2c0f, 0xc414, 0x21, 0 + .dw 0x2c11, 0xc414, 0x2c11, 0xc414, 0x21, 0 + .dw 0x2c13, 0xc414, 0x2c3f, 0xc414, 0x21, 0 + .dw 0x2c41, 0xc414, 0x2c41, 0xc414, 0x21, 0 + .dw 0x2c43, 0xc414, 0x2c4f, 0xc414, 0x21, 0 + .dw 0x2c51, 0xc414, 0x2c51, 0xc414, 0x21, 0 + .dw 0x2c53, 0xc414, 0x2c7f, 0xc414, 0x21, 0 + .dw 0x2c81, 0xc414, 0x2c81, 0xc414, 0x21, 0 + .dw 0x2c83, 0xc414, 0x2c8f, 0xc414, 0x21, 0 + .dw 0x2c91, 0xc414, 0x2c91, 0xc414, 0x21, 0 + .dw 0x2c93, 0xc414, 0x2cbf, 0xc414, 0x21, 0 + .dw 0x2cc1, 0xc414, 0x2cc1, 0xc414, 0x21, 0 + .dw 0x2cc3, 0xc414, 0x2ccf, 0xc414, 0x21, 0 + .dw 0x2cd1, 0xc414, 0x2cd1, 0xc414, 0x21, 0 + .dw 0x2cd3, 0xc414, 0x2cff, 0xc414, 0x21, 0 + .dw 0x2d01, 0xc414, 0x2d01, 0xc414, 0x21, 0 + .dw 0x2d03, 0xc414, 0x2d0f, 0xc414, 0x21, 0 + .dw 0x2d11, 0xc414, 0x2d11, 0xc414, 0x21, 0 + .dw 0x2d13, 0xc414, 0x2d3f, 0xc414, 0x21, 0 + .dw 0x2d41, 0xc414, 0x2d41, 0xc414, 0x21, 0 + .dw 0x2d43, 0xc414, 0x2d4f, 0xc414, 0x21, 0 + .dw 0x2d51, 0xc414, 0x2d51, 0xc414, 0x21, 0 + .dw 0x2d53, 0xc414, 0x2d7f, 0xc414, 0x21, 0 + .dw 0x2d81, 0xc414, 0x2d81, 0xc414, 0x21, 0 + .dw 0x2d83, 0xc414, 0x2d8f, 0xc414, 0x21, 0 + .dw 0x2d91, 0xc414, 0x2d91, 0xc414, 0x21, 0 + .dw 0x2d93, 0xc414, 0x2dbf, 0xc414, 0x21, 0 + .dw 0x2dc1, 0xc414, 0x2dc1, 0xc414, 0x21, 0 + .dw 0x2dc3, 0xc414, 0x2dcf, 0xc414, 0x21, 0 + .dw 0x2dd1, 0xc414, 0x2dd1, 0xc414, 0x21, 0 + .dw 0x2dd3, 0xc414, 0x2dff, 0xc414, 0x21, 0 + .dw 0x2e01, 0xc414, 0x2e01, 0xc414, 0x21, 0 + .dw 0x2e03, 0xc414, 0x2e0f, 0xc414, 0x21, 0 + .dw 0x2e11, 0xc414, 0x2e11, 0xc414, 0x21, 0 + .dw 0x2e13, 0xc414, 0x2e3f, 0xc414, 0x21, 0 + .dw 0x2e41, 0xc414, 0x2e41, 0xc414, 0x21, 0 + .dw 0x2e43, 0xc414, 0x2e4f, 0xc414, 0x21, 0 + .dw 0x2e51, 0xc414, 0x2e51, 0xc414, 0x21, 0 + .dw 0x2e53, 0xc414, 0x2e7f, 0xc414, 0x21, 0 + .dw 0x2e81, 0xc414, 0x2e81, 0xc414, 0x21, 0 + .dw 0x2e83, 0xc414, 0x2e8f, 0xc414, 0x21, 0 + .dw 0x2e91, 0xc414, 0x2e91, 0xc414, 0x21, 0 + .dw 0x2e93, 0xc414, 0x2ebf, 0xc414, 0x21, 0 + .dw 0x2ec1, 0xc414, 0x2ec1, 0xc414, 0x21, 0 + .dw 0x2ec3, 0xc414, 0x2ecf, 0xc414, 0x21, 0 + .dw 0x2ed1, 0xc414, 0x2ed1, 0xc414, 0x21, 0 + .dw 0x2ed3, 0xc414, 0x2eff, 0xc414, 0x21, 0 + .dw 0x2f01, 0xc414, 0x2f01, 0xc414, 0x21, 0 + .dw 0x2f03, 0xc414, 0x2f0f, 0xc414, 0x21, 0 + .dw 0x2f11, 0xc414, 0x2f11, 0xc414, 0x21, 0 + .dw 0x2f13, 0xc414, 0x2f3f, 0xc414, 0x21, 0 + .dw 0x2f41, 0xc414, 0x2f41, 0xc414, 0x21, 0 + .dw 0x2f43, 0xc414, 0x2f4f, 0xc414, 0x21, 0 + .dw 0x2f51, 0xc414, 0x2f51, 0xc414, 0x21, 0 + .dw 0x2f53, 0xc414, 0x2f7f, 0xc414, 0x21, 0 + .dw 0x2f81, 0xc414, 0x2f81, 0xc414, 0x21, 0 + .dw 0x2f83, 0xc414, 0x2f8f, 0xc414, 0x21, 0 + .dw 0x2f91, 0xc414, 0x2f91, 0xc414, 0x21, 0 + .dw 0x2f93, 0xc414, 0x2fbf, 0xc414, 0x21, 0 + .dw 0x2fc1, 0xc414, 0x2fc1, 0xc414, 0x21, 0 + .dw 0x2fc3, 0xc414, 0x2fcf, 0xc414, 0x21, 0 + .dw 0x2fd1, 0xc414, 0x2fd1, 0xc414, 0x21, 0 + .dw 0x2fd3, 0xc414, 0x3fff, 0xc414, 0x21, 0 + .dw 0x4001, 0xc414, 0x4001, 0xc414, 0x21, 0 + .dw 0x4003, 0xc414, 0x400f, 0xc414, 0x21, 0 + .dw 0x4011, 0xc414, 0x4011, 0xc414, 0x21, 0 + .dw 0x4013, 0xc414, 0x403f, 0xc414, 0x21, 0 + .dw 0x4041, 0xc414, 0x4041, 0xc414, 0x21, 0 + .dw 0x4043, 0xc414, 0x404f, 0xc414, 0x21, 0 + .dw 0x4051, 0xc414, 0x4051, 0xc414, 0x21, 0 + .dw 0x4053, 0xc414, 0x407f, 0xc414, 0x21, 0 + .dw 0x4081, 0xc414, 0x4081, 0xc414, 0x21, 0 + .dw 0x4083, 0xc414, 0x408f, 0xc414, 0x21, 0 + .dw 0x4091, 0xc414, 0x4091, 0xc414, 0x21, 0 + .dw 0x4093, 0xc414, 0x40bf, 0xc414, 0x21, 0 + .dw 0x40c1, 0xc414, 0x40c1, 0xc414, 0x21, 0 + .dw 0x40c3, 0xc414, 0x40cf, 0xc414, 0x21, 0 + .dw 0x40d1, 0xc414, 0x40d1, 0xc414, 0x21, 0 + .dw 0x40d3, 0xc414, 0x40ff, 0xc414, 0x21, 0 + .dw 0x4101, 0xc414, 0x4101, 0xc414, 0x21, 0 + .dw 0x4103, 0xc414, 0x410f, 0xc414, 0x21, 0 + .dw 0x4111, 0xc414, 0x4111, 0xc414, 0x21, 0 + .dw 0x4113, 0xc414, 0x413f, 0xc414, 0x21, 0 + .dw 0x4141, 0xc414, 0x4141, 0xc414, 0x21, 0 + .dw 0x4143, 0xc414, 0x414f, 0xc414, 0x21, 0 + .dw 0x4151, 0xc414, 0x4151, 0xc414, 0x21, 0 + .dw 0x4153, 0xc414, 0x417f, 0xc414, 0x21, 0 + .dw 0x4181, 0xc414, 0x4181, 0xc414, 0x21, 0 + .dw 0x4183, 0xc414, 0x418f, 0xc414, 0x21, 0 + .dw 0x4191, 0xc414, 0x4191, 0xc414, 0x21, 0 + .dw 0x4193, 0xc414, 0x41bf, 0xc414, 0x21, 0 + .dw 0x41c1, 0xc414, 0x41c1, 0xc414, 0x21, 0 + .dw 0x41c3, 0xc414, 0x41cf, 0xc414, 0x21, 0 + .dw 0x41d1, 0xc414, 0x41d1, 0xc414, 0x21, 0 + .dw 0x41d3, 0xc414, 0x41ff, 0xc414, 0x21, 0 + .dw 0x4201, 0xc414, 0x4201, 0xc414, 0x21, 0 + .dw 0x4203, 0xc414, 0x420f, 0xc414, 0x21, 0 + .dw 0x4211, 0xc414, 0x4211, 0xc414, 0x21, 0 + .dw 0x4213, 0xc414, 0x423f, 0xc414, 0x21, 0 + .dw 0x4241, 0xc414, 0x4241, 0xc414, 0x21, 0 + .dw 0x4243, 0xc414, 0x424f, 0xc414, 0x21, 0 + .dw 0x4251, 0xc414, 0x4251, 0xc414, 0x21, 0 + .dw 0x4253, 0xc414, 0x427f, 0xc414, 0x21, 0 + .dw 0x4281, 0xc414, 0x4281, 0xc414, 0x21, 0 + .dw 0x4283, 0xc414, 0x428f, 0xc414, 0x21, 0 + .dw 0x4291, 0xc414, 0x4291, 0xc414, 0x21, 0 + .dw 0x4293, 0xc414, 0x42bf, 0xc414, 0x21, 0 + .dw 0x42c1, 0xc414, 0x42c1, 0xc414, 0x21, 0 + .dw 0x42c3, 0xc414, 0x42cf, 0xc414, 0x21, 0 + .dw 0x42d1, 0xc414, 0x42d1, 0xc414, 0x21, 0 + .dw 0x42d3, 0xc414, 0x42ff, 0xc414, 0x21, 0 + .dw 0x4301, 0xc414, 0x4301, 0xc414, 0x21, 0 + .dw 0x4303, 0xc414, 0x430f, 0xc414, 0x21, 0 + .dw 0x4311, 0xc414, 0x4311, 0xc414, 0x21, 0 + .dw 0x4313, 0xc414, 0x433f, 0xc414, 0x21, 0 + .dw 0x4341, 0xc414, 0x4341, 0xc414, 0x21, 0 + .dw 0x4343, 0xc414, 0x434f, 0xc414, 0x21, 0 + .dw 0x4351, 0xc414, 0x4351, 0xc414, 0x21, 0 + .dw 0x4353, 0xc414, 0x437f, 0xc414, 0x21, 0 + .dw 0x4381, 0xc414, 0x4381, 0xc414, 0x21, 0 + .dw 0x4383, 0xc414, 0x438f, 0xc414, 0x21, 0 + .dw 0x4391, 0xc414, 0x4391, 0xc414, 0x21, 0 + .dw 0x4393, 0xc414, 0x43bf, 0xc414, 0x21, 0 + .dw 0x43c1, 0xc414, 0x43c1, 0xc414, 0x21, 0 + .dw 0x43c3, 0xc414, 0x43cf, 0xc414, 0x21, 0 + .dw 0x43d1, 0xc414, 0x43d1, 0xc414, 0x21, 0 + .dw 0x43d3, 0xc414, 0x43ff, 0xc414, 0x21, 0 + .dw 0x4401, 0xc414, 0x4401, 0xc414, 0x21, 0 + .dw 0x4403, 0xc414, 0x440f, 0xc414, 0x21, 0 + .dw 0x4411, 0xc414, 0x4411, 0xc414, 0x21, 0 + .dw 0x4413, 0xc414, 0x443f, 0xc414, 0x21, 0 + .dw 0x4441, 0xc414, 0x4441, 0xc414, 0x21, 0 + .dw 0x4443, 0xc414, 0x444f, 0xc414, 0x21, 0 + .dw 0x4451, 0xc414, 0x4451, 0xc414, 0x21, 0 + .dw 0x4453, 0xc414, 0x447f, 0xc414, 0x21, 0 + .dw 0x4481, 0xc414, 0x4481, 0xc414, 0x21, 0 + .dw 0x4483, 0xc414, 0x448f, 0xc414, 0x21, 0 + .dw 0x4491, 0xc414, 0x4491, 0xc414, 0x21, 0 + .dw 0x4493, 0xc414, 0x44bf, 0xc414, 0x21, 0 + .dw 0x44c1, 0xc414, 0x44c1, 0xc414, 0x21, 0 + .dw 0x44c3, 0xc414, 0x44cf, 0xc414, 0x21, 0 + .dw 0x44d1, 0xc414, 0x44d1, 0xc414, 0x21, 0 + .dw 0x44d3, 0xc414, 0x44ff, 0xc414, 0x21, 0 + .dw 0x4501, 0xc414, 0x4501, 0xc414, 0x21, 0 + .dw 0x4503, 0xc414, 0x450f, 0xc414, 0x21, 0 + .dw 0x4511, 0xc414, 0x4511, 0xc414, 0x21, 0 + .dw 0x4513, 0xc414, 0x453f, 0xc414, 0x21, 0 + .dw 0x4541, 0xc414, 0x4541, 0xc414, 0x21, 0 + .dw 0x4543, 0xc414, 0x454f, 0xc414, 0x21, 0 + .dw 0x4551, 0xc414, 0x4551, 0xc414, 0x21, 0 + .dw 0x4553, 0xc414, 0x457f, 0xc414, 0x21, 0 + .dw 0x4581, 0xc414, 0x4581, 0xc414, 0x21, 0 + .dw 0x4583, 0xc414, 0x458f, 0xc414, 0x21, 0 + .dw 0x4591, 0xc414, 0x4591, 0xc414, 0x21, 0 + .dw 0x4593, 0xc414, 0x45bf, 0xc414, 0x21, 0 + .dw 0x45c1, 0xc414, 0x45c1, 0xc414, 0x21, 0 + .dw 0x45c3, 0xc414, 0x45cf, 0xc414, 0x21, 0 + .dw 0x45d1, 0xc414, 0x45d1, 0xc414, 0x21, 0 + .dw 0x45d3, 0xc414, 0x45ff, 0xc414, 0x21, 0 + .dw 0x4601, 0xc414, 0x4601, 0xc414, 0x21, 0 + .dw 0x4603, 0xc414, 0x460f, 0xc414, 0x21, 0 + .dw 0x4611, 0xc414, 0x4611, 0xc414, 0x21, 0 + .dw 0x4613, 0xc414, 0x463f, 0xc414, 0x21, 0 + .dw 0x4641, 0xc414, 0x4641, 0xc414, 0x21, 0 + .dw 0x4643, 0xc414, 0x464f, 0xc414, 0x21, 0 + .dw 0x4651, 0xc414, 0x4651, 0xc414, 0x21, 0 + .dw 0x4653, 0xc414, 0x467f, 0xc414, 0x21, 0 + .dw 0x4681, 0xc414, 0x4681, 0xc414, 0x21, 0 + .dw 0x4683, 0xc414, 0x468f, 0xc414, 0x21, 0 + .dw 0x4691, 0xc414, 0x4691, 0xc414, 0x21, 0 + .dw 0x4693, 0xc414, 0x46bf, 0xc414, 0x21, 0 + .dw 0x46c1, 0xc414, 0x46c1, 0xc414, 0x21, 0 + .dw 0x46c3, 0xc414, 0x46cf, 0xc414, 0x21, 0 + .dw 0x46d1, 0xc414, 0x46d1, 0xc414, 0x21, 0 + .dw 0x46d3, 0xc414, 0x46ff, 0xc414, 0x21, 0 + .dw 0x4701, 0xc414, 0x4701, 0xc414, 0x21, 0 + .dw 0x4703, 0xc414, 0x470f, 0xc414, 0x21, 0 + .dw 0x4711, 0xc414, 0x4711, 0xc414, 0x21, 0 + .dw 0x4713, 0xc414, 0x473f, 0xc414, 0x21, 0 + .dw 0x4741, 0xc414, 0x4741, 0xc414, 0x21, 0 + .dw 0x4743, 0xc414, 0x474f, 0xc414, 0x21, 0 + .dw 0x4751, 0xc414, 0x4751, 0xc414, 0x21, 0 + .dw 0x4753, 0xc414, 0x477f, 0xc414, 0x21, 0 + .dw 0x4781, 0xc414, 0x4781, 0xc414, 0x21, 0 + .dw 0x4783, 0xc414, 0x478f, 0xc414, 0x21, 0 + .dw 0x4791, 0xc414, 0x4791, 0xc414, 0x21, 0 + .dw 0x4793, 0xc414, 0x47bf, 0xc414, 0x21, 0 + .dw 0x47c1, 0xc414, 0x47c1, 0xc414, 0x21, 0 + .dw 0x47c3, 0xc414, 0x47cf, 0xc414, 0x21, 0 + .dw 0x47d1, 0xc414, 0x47d1, 0xc414, 0x21, 0 + .dw 0x47d3, 0xc414, 0x47ff, 0xc414, 0x21, 0 + .dw 0x4801, 0xc414, 0x4801, 0xc414, 0x21, 0 + .dw 0x4803, 0xc414, 0x480f, 0xc414, 0x21, 0 + .dw 0x4811, 0xc414, 0x4811, 0xc414, 0x21, 0 + .dw 0x4813, 0xc414, 0x483f, 0xc414, 0x21, 0 + .dw 0x4841, 0xc414, 0x4841, 0xc414, 0x21, 0 + .dw 0x4843, 0xc414, 0x484f, 0xc414, 0x21, 0 + .dw 0x4851, 0xc414, 0x4851, 0xc414, 0x21, 0 + .dw 0x4853, 0xc414, 0x487f, 0xc414, 0x21, 0 + .dw 0x4881, 0xc414, 0x4881, 0xc414, 0x21, 0 + .dw 0x4883, 0xc414, 0x488f, 0xc414, 0x21, 0 + .dw 0x4891, 0xc414, 0x4891, 0xc414, 0x21, 0 + .dw 0x4893, 0xc414, 0x48bf, 0xc414, 0x21, 0 + .dw 0x48c1, 0xc414, 0x48c1, 0xc414, 0x21, 0 + .dw 0x48c3, 0xc414, 0x48cf, 0xc414, 0x21, 0 + .dw 0x48d1, 0xc414, 0x48d1, 0xc414, 0x21, 0 + .dw 0x48d3, 0xc414, 0x48ff, 0xc414, 0x21, 0 + .dw 0x4901, 0xc414, 0x4901, 0xc414, 0x21, 0 + .dw 0x4903, 0xc414, 0x490f, 0xc414, 0x21, 0 + .dw 0x4911, 0xc414, 0x4911, 0xc414, 0x21, 0 + .dw 0x4913, 0xc414, 0x493f, 0xc414, 0x21, 0 + .dw 0x4941, 0xc414, 0x4941, 0xc414, 0x21, 0 + .dw 0x4943, 0xc414, 0x494f, 0xc414, 0x21, 0 + .dw 0x4951, 0xc414, 0x4951, 0xc414, 0x21, 0 + .dw 0x4953, 0xc414, 0x497f, 0xc414, 0x21, 0 + .dw 0x4981, 0xc414, 0x4981, 0xc414, 0x21, 0 + .dw 0x4983, 0xc414, 0x498f, 0xc414, 0x21, 0 + .dw 0x4991, 0xc414, 0x4991, 0xc414, 0x21, 0 + .dw 0x4993, 0xc414, 0x49bf, 0xc414, 0x21, 0 + .dw 0x49c1, 0xc414, 0x49c1, 0xc414, 0x21, 0 + .dw 0x49c3, 0xc414, 0x49cf, 0xc414, 0x21, 0 + .dw 0x49d1, 0xc414, 0x49d1, 0xc414, 0x21, 0 + .dw 0x49d3, 0xc414, 0x49ff, 0xc414, 0x21, 0 + .dw 0x4a01, 0xc414, 0x4a01, 0xc414, 0x21, 0 + .dw 0x4a03, 0xc414, 0x4a0f, 0xc414, 0x21, 0 + .dw 0x4a11, 0xc414, 0x4a11, 0xc414, 0x21, 0 + .dw 0x4a13, 0xc414, 0x4a3f, 0xc414, 0x21, 0 + .dw 0x4a41, 0xc414, 0x4a41, 0xc414, 0x21, 0 + .dw 0x4a43, 0xc414, 0x4a4f, 0xc414, 0x21, 0 + .dw 0x4a51, 0xc414, 0x4a51, 0xc414, 0x21, 0 + .dw 0x4a53, 0xc414, 0x4a7f, 0xc414, 0x21, 0 + .dw 0x4a81, 0xc414, 0x4a81, 0xc414, 0x21, 0 + .dw 0x4a83, 0xc414, 0x4a8f, 0xc414, 0x21, 0 + .dw 0x4a91, 0xc414, 0x4a91, 0xc414, 0x21, 0 + .dw 0x4a93, 0xc414, 0x4abf, 0xc414, 0x21, 0 + .dw 0x4ac1, 0xc414, 0x4ac1, 0xc414, 0x21, 0 + .dw 0x4ac3, 0xc414, 0x4acf, 0xc414, 0x21, 0 + .dw 0x4ad1, 0xc414, 0x4ad1, 0xc414, 0x21, 0 + .dw 0x4ad3, 0xc414, 0x4aff, 0xc414, 0x21, 0 + .dw 0x4b01, 0xc414, 0x4b01, 0xc414, 0x21, 0 + .dw 0x4b03, 0xc414, 0x4b0f, 0xc414, 0x21, 0 + .dw 0x4b11, 0xc414, 0x4b11, 0xc414, 0x21, 0 + .dw 0x4b13, 0xc414, 0x4b3f, 0xc414, 0x21, 0 + .dw 0x4b41, 0xc414, 0x4b41, 0xc414, 0x21, 0 + .dw 0x4b43, 0xc414, 0x4b4f, 0xc414, 0x21, 0 + .dw 0x4b51, 0xc414, 0x4b51, 0xc414, 0x21, 0 + .dw 0x4b53, 0xc414, 0x4b7f, 0xc414, 0x21, 0 + .dw 0x4b81, 0xc414, 0x4b81, 0xc414, 0x21, 0 + .dw 0x4b83, 0xc414, 0x4b8f, 0xc414, 0x21, 0 + .dw 0x4b91, 0xc414, 0x4b91, 0xc414, 0x21, 0 + .dw 0x4b93, 0xc414, 0x4bbf, 0xc414, 0x21, 0 + .dw 0x4bc1, 0xc414, 0x4bc1, 0xc414, 0x21, 0 + .dw 0x4bc3, 0xc414, 0x4bcf, 0xc414, 0x21, 0 + .dw 0x4bd1, 0xc414, 0x4bd1, 0xc414, 0x21, 0 + .dw 0x4bd3, 0xc414, 0x4bff, 0xc414, 0x21, 0 + .dw 0x4c01, 0xc414, 0x4c01, 0xc414, 0x21, 0 + .dw 0x4c03, 0xc414, 0x4c0f, 0xc414, 0x21, 0 + .dw 0x4c11, 0xc414, 0x4c11, 0xc414, 0x21, 0 + .dw 0x4c13, 0xc414, 0x4c3f, 0xc414, 0x21, 0 + .dw 0x4c41, 0xc414, 0x4c41, 0xc414, 0x21, 0 + .dw 0x4c43, 0xc414, 0x4c4f, 0xc414, 0x21, 0 + .dw 0x4c51, 0xc414, 0x4c51, 0xc414, 0x21, 0 + .dw 0x4c53, 0xc414, 0x4c7f, 0xc414, 0x21, 0 + .dw 0x4c81, 0xc414, 0x4c81, 0xc414, 0x21, 0 + .dw 0x4c83, 0xc414, 0x4c8f, 0xc414, 0x21, 0 + .dw 0x4c91, 0xc414, 0x4c91, 0xc414, 0x21, 0 + .dw 0x4c93, 0xc414, 0x4cbf, 0xc414, 0x21, 0 + .dw 0x4cc1, 0xc414, 0x4cc1, 0xc414, 0x21, 0 + .dw 0x4cc3, 0xc414, 0x4ccf, 0xc414, 0x21, 0 + .dw 0x4cd1, 0xc414, 0x4cd1, 0xc414, 0x21, 0 + .dw 0x4cd3, 0xc414, 0x4cff, 0xc414, 0x21, 0 + .dw 0x4d01, 0xc414, 0x4d01, 0xc414, 0x21, 0 + .dw 0x4d03, 0xc414, 0x4d0f, 0xc414, 0x21, 0 + .dw 0x4d11, 0xc414, 0x4d11, 0xc414, 0x21, 0 + .dw 0x4d13, 0xc414, 0x4d3f, 0xc414, 0x21, 0 + .dw 0x4d41, 0xc414, 0x4d41, 0xc414, 0x21, 0 + .dw 0x4d43, 0xc414, 0x4d4f, 0xc414, 0x21, 0 + .dw 0x4d51, 0xc414, 0x4d51, 0xc414, 0x21, 0 + .dw 0x4d53, 0xc414, 0x4d7f, 0xc414, 0x21, 0 + .dw 0x4d81, 0xc414, 0x4d81, 0xc414, 0x21, 0 + .dw 0x4d83, 0xc414, 0x4d8f, 0xc414, 0x21, 0 + .dw 0x4d91, 0xc414, 0x4d91, 0xc414, 0x21, 0 + .dw 0x4d93, 0xc414, 0x4dbf, 0xc414, 0x21, 0 + .dw 0x4dc1, 0xc414, 0x4dc1, 0xc414, 0x21, 0 + .dw 0x4dc3, 0xc414, 0x4dcf, 0xc414, 0x21, 0 + .dw 0x4dd1, 0xc414, 0x4dd1, 0xc414, 0x21, 0 + .dw 0x4dd3, 0xc414, 0x4dff, 0xc414, 0x21, 0 + .dw 0x4e01, 0xc414, 0x4e01, 0xc414, 0x21, 0 + .dw 0x4e03, 0xc414, 0x4e0f, 0xc414, 0x21, 0 + .dw 0x4e11, 0xc414, 0x4e11, 0xc414, 0x21, 0 + .dw 0x4e13, 0xc414, 0x4e3f, 0xc414, 0x21, 0 + .dw 0x4e41, 0xc414, 0x4e41, 0xc414, 0x21, 0 + .dw 0x4e43, 0xc414, 0x4e4f, 0xc414, 0x21, 0 + .dw 0x4e51, 0xc414, 0x4e51, 0xc414, 0x21, 0 + .dw 0x4e53, 0xc414, 0x4e7f, 0xc414, 0x21, 0 + .dw 0x4e81, 0xc414, 0x4e81, 0xc414, 0x21, 0 + .dw 0x4e83, 0xc414, 0x4e8f, 0xc414, 0x21, 0 + .dw 0x4e91, 0xc414, 0x4e91, 0xc414, 0x21, 0 + .dw 0x4e93, 0xc414, 0x4ebf, 0xc414, 0x21, 0 + .dw 0x4ec1, 0xc414, 0x4ec1, 0xc414, 0x21, 0 + .dw 0x4ec3, 0xc414, 0x4ecf, 0xc414, 0x21, 0 + .dw 0x4ed1, 0xc414, 0x4ed1, 0xc414, 0x21, 0 + .dw 0x4ed3, 0xc414, 0x4eff, 0xc414, 0x21, 0 + .dw 0x4f01, 0xc414, 0x4f01, 0xc414, 0x21, 0 + .dw 0x4f03, 0xc414, 0x4f0f, 0xc414, 0x21, 0 + .dw 0x4f11, 0xc414, 0x4f11, 0xc414, 0x21, 0 + .dw 0x4f13, 0xc414, 0x4f3f, 0xc414, 0x21, 0 + .dw 0x4f41, 0xc414, 0x4f41, 0xc414, 0x21, 0 + .dw 0x4f43, 0xc414, 0x4f4f, 0xc414, 0x21, 0 + .dw 0x4f51, 0xc414, 0x4f51, 0xc414, 0x21, 0 + .dw 0x4f53, 0xc414, 0x4f7f, 0xc414, 0x21, 0 + .dw 0x4f81, 0xc414, 0x4f81, 0xc414, 0x21, 0 + .dw 0x4f83, 0xc414, 0x4f8f, 0xc414, 0x21, 0 + .dw 0x4f91, 0xc414, 0x4f91, 0xc414, 0x21, 0 + .dw 0x4f93, 0xc414, 0x4fbf, 0xc414, 0x21, 0 + .dw 0x4fc1, 0xc414, 0x4fc1, 0xc414, 0x21, 0 + .dw 0x4fc3, 0xc414, 0x4fcf, 0xc414, 0x21, 0 + .dw 0x4fd1, 0xc414, 0x4fd1, 0xc414, 0x21, 0 + .dw 0x4fd3, 0xc414, 0x5fff, 0xc414, 0x21, 0 + .dw 0x6001, 0xc414, 0x6001, 0xc414, 0x21, 0 + .dw 0x6003, 0xc414, 0x600f, 0xc414, 0x21, 0 + .dw 0x6011, 0xc414, 0x6011, 0xc414, 0x21, 0 + .dw 0x6013, 0xc414, 0x603f, 0xc414, 0x21, 0 + .dw 0x6041, 0xc414, 0x6041, 0xc414, 0x21, 0 + .dw 0x6043, 0xc414, 0x604f, 0xc414, 0x21, 0 + .dw 0x6051, 0xc414, 0x6051, 0xc414, 0x21, 0 + .dw 0x6053, 0xc414, 0x607f, 0xc414, 0x21, 0 + .dw 0x6081, 0xc414, 0x6081, 0xc414, 0x21, 0 + .dw 0x6083, 0xc414, 0x608f, 0xc414, 0x21, 0 + .dw 0x6091, 0xc414, 0x6091, 0xc414, 0x21, 0 + .dw 0x6093, 0xc414, 0x60bf, 0xc414, 0x21, 0 + .dw 0x60c1, 0xc414, 0x60c1, 0xc414, 0x21, 0 + .dw 0x60c3, 0xc414, 0x60cf, 0xc414, 0x21, 0 + .dw 0x60d1, 0xc414, 0x60d1, 0xc414, 0x21, 0 + .dw 0x60d3, 0xc414, 0x60ff, 0xc414, 0x21, 0 + .dw 0x6101, 0xc414, 0x6101, 0xc414, 0x21, 0 + .dw 0x6103, 0xc414, 0x610f, 0xc414, 0x21, 0 + .dw 0x6111, 0xc414, 0x6111, 0xc414, 0x21, 0 + .dw 0x6113, 0xc414, 0x613f, 0xc414, 0x21, 0 + .dw 0x6141, 0xc414, 0x6141, 0xc414, 0x21, 0 + .dw 0x6143, 0xc414, 0x614f, 0xc414, 0x21, 0 + .dw 0x6151, 0xc414, 0x6151, 0xc414, 0x21, 0 + .dw 0x6153, 0xc414, 0x617f, 0xc414, 0x21, 0 + .dw 0x6181, 0xc414, 0x6181, 0xc414, 0x21, 0 + .dw 0x6183, 0xc414, 0x618f, 0xc414, 0x21, 0 + .dw 0x6191, 0xc414, 0x6191, 0xc414, 0x21, 0 + .dw 0x6193, 0xc414, 0x61bf, 0xc414, 0x21, 0 + .dw 0x61c1, 0xc414, 0x61c1, 0xc414, 0x21, 0 + .dw 0x61c3, 0xc414, 0x61cf, 0xc414, 0x21, 0 + .dw 0x61d1, 0xc414, 0x61d1, 0xc414, 0x21, 0 + .dw 0x61d3, 0xc414, 0x61ff, 0xc414, 0x21, 0 + .dw 0x6201, 0xc414, 0x6201, 0xc414, 0x21, 0 + .dw 0x6203, 0xc414, 0x620f, 0xc414, 0x21, 0 + .dw 0x6211, 0xc414, 0x6211, 0xc414, 0x21, 0 + .dw 0x6213, 0xc414, 0x623f, 0xc414, 0x21, 0 + .dw 0x6241, 0xc414, 0x6241, 0xc414, 0x21, 0 + .dw 0x6243, 0xc414, 0x624f, 0xc414, 0x21, 0 + .dw 0x6251, 0xc414, 0x6251, 0xc414, 0x21, 0 + .dw 0x6253, 0xc414, 0x627f, 0xc414, 0x21, 0 + .dw 0x6281, 0xc414, 0x6281, 0xc414, 0x21, 0 + .dw 0x6283, 0xc414, 0x628f, 0xc414, 0x21, 0 + .dw 0x6291, 0xc414, 0x6291, 0xc414, 0x21, 0 + .dw 0x6293, 0xc414, 0x62bf, 0xc414, 0x21, 0 + .dw 0x62c1, 0xc414, 0x62c1, 0xc414, 0x21, 0 + .dw 0x62c3, 0xc414, 0x62cf, 0xc414, 0x21, 0 + .dw 0x62d1, 0xc414, 0x62d1, 0xc414, 0x21, 0 + .dw 0x62d3, 0xc414, 0x62ff, 0xc414, 0x21, 0 + .dw 0x6301, 0xc414, 0x6301, 0xc414, 0x21, 0 + .dw 0x6303, 0xc414, 0x630f, 0xc414, 0x21, 0 + .dw 0x6311, 0xc414, 0x6311, 0xc414, 0x21, 0 + .dw 0x6313, 0xc414, 0x633f, 0xc414, 0x21, 0 + .dw 0x6341, 0xc414, 0x6341, 0xc414, 0x21, 0 + .dw 0x6343, 0xc414, 0x634f, 0xc414, 0x21, 0 + .dw 0x6351, 0xc414, 0x6351, 0xc414, 0x21, 0 + .dw 0x6353, 0xc414, 0x637f, 0xc414, 0x21, 0 + .dw 0x6381, 0xc414, 0x6381, 0xc414, 0x21, 0 + .dw 0x6383, 0xc414, 0x638f, 0xc414, 0x21, 0 + .dw 0x6391, 0xc414, 0x6391, 0xc414, 0x21, 0 + .dw 0x6393, 0xc414, 0x63bf, 0xc414, 0x21, 0 + .dw 0x63c1, 0xc414, 0x63c1, 0xc414, 0x21, 0 + .dw 0x63c3, 0xc414, 0x63cf, 0xc414, 0x21, 0 + .dw 0x63d1, 0xc414, 0x63d1, 0xc414, 0x21, 0 + .dw 0x63d3, 0xc414, 0x63ff, 0xc414, 0x21, 0 + .dw 0x6401, 0xc414, 0x6401, 0xc414, 0x21, 0 + .dw 0x6403, 0xc414, 0x640f, 0xc414, 0x21, 0 + .dw 0x6411, 0xc414, 0x6411, 0xc414, 0x21, 0 + .dw 0x6413, 0xc414, 0x643f, 0xc414, 0x21, 0 + .dw 0x6441, 0xc414, 0x6441, 0xc414, 0x21, 0 + .dw 0x6443, 0xc414, 0x644f, 0xc414, 0x21, 0 + .dw 0x6451, 0xc414, 0x6451, 0xc414, 0x21, 0 + .dw 0x6453, 0xc414, 0x647f, 0xc414, 0x21, 0 + .dw 0x6481, 0xc414, 0x6481, 0xc414, 0x21, 0 + .dw 0x6483, 0xc414, 0x648f, 0xc414, 0x21, 0 + .dw 0x6491, 0xc414, 0x6491, 0xc414, 0x21, 0 + .dw 0x6493, 0xc414, 0x64bf, 0xc414, 0x21, 0 + .dw 0x64c1, 0xc414, 0x64c1, 0xc414, 0x21, 0 + .dw 0x64c3, 0xc414, 0x64cf, 0xc414, 0x21, 0 + .dw 0x64d1, 0xc414, 0x64d1, 0xc414, 0x21, 0 + .dw 0x64d3, 0xc414, 0x64ff, 0xc414, 0x21, 0 + .dw 0x6501, 0xc414, 0x6501, 0xc414, 0x21, 0 + .dw 0x6503, 0xc414, 0x650f, 0xc414, 0x21, 0 + .dw 0x6511, 0xc414, 0x6511, 0xc414, 0x21, 0 + .dw 0x6513, 0xc414, 0x653f, 0xc414, 0x21, 0 + .dw 0x6541, 0xc414, 0x6541, 0xc414, 0x21, 0 + .dw 0x6543, 0xc414, 0x654f, 0xc414, 0x21, 0 + .dw 0x6551, 0xc414, 0x6551, 0xc414, 0x21, 0 + .dw 0x6553, 0xc414, 0x657f, 0xc414, 0x21, 0 + .dw 0x6581, 0xc414, 0x6581, 0xc414, 0x21, 0 + .dw 0x6583, 0xc414, 0x658f, 0xc414, 0x21, 0 + .dw 0x6591, 0xc414, 0x6591, 0xc414, 0x21, 0 + .dw 0x6593, 0xc414, 0x65bf, 0xc414, 0x21, 0 + .dw 0x65c1, 0xc414, 0x65c1, 0xc414, 0x21, 0 + .dw 0x65c3, 0xc414, 0x65cf, 0xc414, 0x21, 0 + .dw 0x65d1, 0xc414, 0x65d1, 0xc414, 0x21, 0 + .dw 0x65d3, 0xc414, 0x65ff, 0xc414, 0x21, 0 + .dw 0x6601, 0xc414, 0x6601, 0xc414, 0x21, 0 + .dw 0x6603, 0xc414, 0x660f, 0xc414, 0x21, 0 + .dw 0x6611, 0xc414, 0x6611, 0xc414, 0x21, 0 + .dw 0x6613, 0xc414, 0x663f, 0xc414, 0x21, 0 + .dw 0x6641, 0xc414, 0x6641, 0xc414, 0x21, 0 + .dw 0x6643, 0xc414, 0x664f, 0xc414, 0x21, 0 + .dw 0x6651, 0xc414, 0x6651, 0xc414, 0x21, 0 + .dw 0x6653, 0xc414, 0x667f, 0xc414, 0x21, 0 + .dw 0x6681, 0xc414, 0x6681, 0xc414, 0x21, 0 + .dw 0x6683, 0xc414, 0x668f, 0xc414, 0x21, 0 + .dw 0x6691, 0xc414, 0x6691, 0xc414, 0x21, 0 + .dw 0x6693, 0xc414, 0x66bf, 0xc414, 0x21, 0 + .dw 0x66c1, 0xc414, 0x66c1, 0xc414, 0x21, 0 + .dw 0x66c3, 0xc414, 0x66cf, 0xc414, 0x21, 0 + .dw 0x66d1, 0xc414, 0x66d1, 0xc414, 0x21, 0 + .dw 0x66d3, 0xc414, 0x66ff, 0xc414, 0x21, 0 + .dw 0x6701, 0xc414, 0x6701, 0xc414, 0x21, 0 + .dw 0x6703, 0xc414, 0x670f, 0xc414, 0x21, 0 + .dw 0x6711, 0xc414, 0x6711, 0xc414, 0x21, 0 + .dw 0x6713, 0xc414, 0x673f, 0xc414, 0x21, 0 + .dw 0x6741, 0xc414, 0x6741, 0xc414, 0x21, 0 + .dw 0x6743, 0xc414, 0x674f, 0xc414, 0x21, 0 + .dw 0x6751, 0xc414, 0x6751, 0xc414, 0x21, 0 + .dw 0x6753, 0xc414, 0x677f, 0xc414, 0x21, 0 + .dw 0x6781, 0xc414, 0x6781, 0xc414, 0x21, 0 + .dw 0x6783, 0xc414, 0x678f, 0xc414, 0x21, 0 + .dw 0x6791, 0xc414, 0x6791, 0xc414, 0x21, 0 + .dw 0x6793, 0xc414, 0x67bf, 0xc414, 0x21, 0 + .dw 0x67c1, 0xc414, 0x67c1, 0xc414, 0x21, 0 + .dw 0x67c3, 0xc414, 0x67cf, 0xc414, 0x21, 0 + .dw 0x67d1, 0xc414, 0x67d1, 0xc414, 0x21, 0 + .dw 0x67d3, 0xc414, 0x67ff, 0xc414, 0x21, 0 + .dw 0x6801, 0xc414, 0x6801, 0xc414, 0x21, 0 + .dw 0x6803, 0xc414, 0x680f, 0xc414, 0x21, 0 + .dw 0x6811, 0xc414, 0x6811, 0xc414, 0x21, 0 + .dw 0x6813, 0xc414, 0x683f, 0xc414, 0x21, 0 + .dw 0x6841, 0xc414, 0x6841, 0xc414, 0x21, 0 + .dw 0x6843, 0xc414, 0x684f, 0xc414, 0x21, 0 + .dw 0x6851, 0xc414, 0x6851, 0xc414, 0x21, 0 + .dw 0x6853, 0xc414, 0x687f, 0xc414, 0x21, 0 + .dw 0x6881, 0xc414, 0x6881, 0xc414, 0x21, 0 + .dw 0x6883, 0xc414, 0x688f, 0xc414, 0x21, 0 + .dw 0x6891, 0xc414, 0x6891, 0xc414, 0x21, 0 + .dw 0x6893, 0xc414, 0x68bf, 0xc414, 0x21, 0 + .dw 0x68c1, 0xc414, 0x68c1, 0xc414, 0x21, 0 + .dw 0x68c3, 0xc414, 0x68cf, 0xc414, 0x21, 0 + .dw 0x68d1, 0xc414, 0x68d1, 0xc414, 0x21, 0 + .dw 0x68d3, 0xc414, 0x68ff, 0xc414, 0x21, 0 + .dw 0x6901, 0xc414, 0x6901, 0xc414, 0x21, 0 + .dw 0x6903, 0xc414, 0x690f, 0xc414, 0x21, 0 + .dw 0x6911, 0xc414, 0x6911, 0xc414, 0x21, 0 + .dw 0x6913, 0xc414, 0x693f, 0xc414, 0x21, 0 + .dw 0x6941, 0xc414, 0x6941, 0xc414, 0x21, 0 + .dw 0x6943, 0xc414, 0x694f, 0xc414, 0x21, 0 + .dw 0x6951, 0xc414, 0x6951, 0xc414, 0x21, 0 + .dw 0x6953, 0xc414, 0x697f, 0xc414, 0x21, 0 + .dw 0x6981, 0xc414, 0x6981, 0xc414, 0x21, 0 + .dw 0x6983, 0xc414, 0x698f, 0xc414, 0x21, 0 + .dw 0x6991, 0xc414, 0x6991, 0xc414, 0x21, 0 + .dw 0x6993, 0xc414, 0x69bf, 0xc414, 0x21, 0 + .dw 0x69c1, 0xc414, 0x69c1, 0xc414, 0x21, 0 + .dw 0x69c3, 0xc414, 0x69cf, 0xc414, 0x21, 0 + .dw 0x69d1, 0xc414, 0x69d1, 0xc414, 0x21, 0 + .dw 0x69d3, 0xc414, 0x69ff, 0xc414, 0x21, 0 + .dw 0x6a01, 0xc414, 0x6a01, 0xc414, 0x21, 0 + .dw 0x6a03, 0xc414, 0x6a0f, 0xc414, 0x21, 0 + .dw 0x6a11, 0xc414, 0x6a11, 0xc414, 0x21, 0 + .dw 0x6a13, 0xc414, 0x6a3f, 0xc414, 0x21, 0 + .dw 0x6a41, 0xc414, 0x6a41, 0xc414, 0x21, 0 + .dw 0x6a43, 0xc414, 0x6a4f, 0xc414, 0x21, 0 + .dw 0x6a51, 0xc414, 0x6a51, 0xc414, 0x21, 0 + .dw 0x6a53, 0xc414, 0x6a7f, 0xc414, 0x21, 0 + .dw 0x6a81, 0xc414, 0x6a81, 0xc414, 0x21, 0 + .dw 0x6a83, 0xc414, 0x6a8f, 0xc414, 0x21, 0 + .dw 0x6a91, 0xc414, 0x6a91, 0xc414, 0x21, 0 + .dw 0x6a93, 0xc414, 0x6abf, 0xc414, 0x21, 0 + .dw 0x6ac1, 0xc414, 0x6ac1, 0xc414, 0x21, 0 + .dw 0x6ac3, 0xc414, 0x6acf, 0xc414, 0x21, 0 + .dw 0x6ad1, 0xc414, 0x6ad1, 0xc414, 0x21, 0 + .dw 0x6ad3, 0xc414, 0x6aff, 0xc414, 0x21, 0 + .dw 0x6b01, 0xc414, 0x6b01, 0xc414, 0x21, 0 + .dw 0x6b03, 0xc414, 0x6b0f, 0xc414, 0x21, 0 + .dw 0x6b11, 0xc414, 0x6b11, 0xc414, 0x21, 0 + .dw 0x6b13, 0xc414, 0x6b3f, 0xc414, 0x21, 0 + .dw 0x6b41, 0xc414, 0x6b41, 0xc414, 0x21, 0 + .dw 0x6b43, 0xc414, 0x6b4f, 0xc414, 0x21, 0 + .dw 0x6b51, 0xc414, 0x6b51, 0xc414, 0x21, 0 + .dw 0x6b53, 0xc414, 0x6b7f, 0xc414, 0x21, 0 + .dw 0x6b81, 0xc414, 0x6b81, 0xc414, 0x21, 0 + .dw 0x6b83, 0xc414, 0x6b8f, 0xc414, 0x21, 0 + .dw 0x6b91, 0xc414, 0x6b91, 0xc414, 0x21, 0 + .dw 0x6b93, 0xc414, 0x6bbf, 0xc414, 0x21, 0 + .dw 0x6bc1, 0xc414, 0x6bc1, 0xc414, 0x21, 0 + .dw 0x6bc3, 0xc414, 0x6bcf, 0xc414, 0x21, 0 + .dw 0x6bd1, 0xc414, 0x6bd1, 0xc414, 0x21, 0 + .dw 0x6bd3, 0xc414, 0x6bff, 0xc414, 0x21, 0 + .dw 0x6c01, 0xc414, 0x6c01, 0xc414, 0x21, 0 + .dw 0x6c03, 0xc414, 0x6c0f, 0xc414, 0x21, 0 + .dw 0x6c11, 0xc414, 0x6c11, 0xc414, 0x21, 0 + .dw 0x6c13, 0xc414, 0x6c3f, 0xc414, 0x21, 0 + .dw 0x6c41, 0xc414, 0x6c41, 0xc414, 0x21, 0 + .dw 0x6c43, 0xc414, 0x6c4f, 0xc414, 0x21, 0 + .dw 0x6c51, 0xc414, 0x6c51, 0xc414, 0x21, 0 + .dw 0x6c53, 0xc414, 0x6c7f, 0xc414, 0x21, 0 + .dw 0x6c81, 0xc414, 0x6c81, 0xc414, 0x21, 0 + .dw 0x6c83, 0xc414, 0x6c8f, 0xc414, 0x21, 0 + .dw 0x6c91, 0xc414, 0x6c91, 0xc414, 0x21, 0 + .dw 0x6c93, 0xc414, 0x6cbf, 0xc414, 0x21, 0 + .dw 0x6cc1, 0xc414, 0x6cc1, 0xc414, 0x21, 0 + .dw 0x6cc3, 0xc414, 0x6ccf, 0xc414, 0x21, 0 + .dw 0x6cd1, 0xc414, 0x6cd1, 0xc414, 0x21, 0 + .dw 0x6cd3, 0xc414, 0x6cff, 0xc414, 0x21, 0 + .dw 0x6d01, 0xc414, 0x6d01, 0xc414, 0x21, 0 + .dw 0x6d03, 0xc414, 0x6d0f, 0xc414, 0x21, 0 + .dw 0x6d11, 0xc414, 0x6d11, 0xc414, 0x21, 0 + .dw 0x6d13, 0xc414, 0x6d3f, 0xc414, 0x21, 0 + .dw 0x6d41, 0xc414, 0x6d41, 0xc414, 0x21, 0 + .dw 0x6d43, 0xc414, 0x6d4f, 0xc414, 0x21, 0 + .dw 0x6d51, 0xc414, 0x6d51, 0xc414, 0x21, 0 + .dw 0x6d53, 0xc414, 0x6d7f, 0xc414, 0x21, 0 + .dw 0x6d81, 0xc414, 0x6d81, 0xc414, 0x21, 0 + .dw 0x6d83, 0xc414, 0x6d8f, 0xc414, 0x21, 0 + .dw 0x6d91, 0xc414, 0x6d91, 0xc414, 0x21, 0 + .dw 0x6d93, 0xc414, 0x6dbf, 0xc414, 0x21, 0 + .dw 0x6dc1, 0xc414, 0x6dc1, 0xc414, 0x21, 0 + .dw 0x6dc3, 0xc414, 0x6dcf, 0xc414, 0x21, 0 + .dw 0x6dd1, 0xc414, 0x6dd1, 0xc414, 0x21, 0 + .dw 0x6dd3, 0xc414, 0x6dff, 0xc414, 0x21, 0 + .dw 0x6e01, 0xc414, 0x6e01, 0xc414, 0x21, 0 + .dw 0x6e03, 0xc414, 0x6e0f, 0xc414, 0x21, 0 + .dw 0x6e11, 0xc414, 0x6e11, 0xc414, 0x21, 0 + .dw 0x6e13, 0xc414, 0x6e3f, 0xc414, 0x21, 0 + .dw 0x6e41, 0xc414, 0x6e41, 0xc414, 0x21, 0 + .dw 0x6e43, 0xc414, 0x6e4f, 0xc414, 0x21, 0 + .dw 0x6e51, 0xc414, 0x6e51, 0xc414, 0x21, 0 + .dw 0x6e53, 0xc414, 0x6e7f, 0xc414, 0x21, 0 + .dw 0x6e81, 0xc414, 0x6e81, 0xc414, 0x21, 0 + .dw 0x6e83, 0xc414, 0x6e8f, 0xc414, 0x21, 0 + .dw 0x6e91, 0xc414, 0x6e91, 0xc414, 0x21, 0 + .dw 0x6e93, 0xc414, 0x6ebf, 0xc414, 0x21, 0 + .dw 0x6ec1, 0xc414, 0x6ec1, 0xc414, 0x21, 0 + .dw 0x6ec3, 0xc414, 0x6ecf, 0xc414, 0x21, 0 + .dw 0x6ed1, 0xc414, 0x6ed1, 0xc414, 0x21, 0 + .dw 0x6ed3, 0xc414, 0x6eff, 0xc414, 0x21, 0 + .dw 0x6f01, 0xc414, 0x6f01, 0xc414, 0x21, 0 + .dw 0x6f03, 0xc414, 0x6f0f, 0xc414, 0x21, 0 + .dw 0x6f11, 0xc414, 0x6f11, 0xc414, 0x21, 0 + .dw 0x6f13, 0xc414, 0x6f3f, 0xc414, 0x21, 0 + .dw 0x6f41, 0xc414, 0x6f41, 0xc414, 0x21, 0 + .dw 0x6f43, 0xc414, 0x6f4f, 0xc414, 0x21, 0 + .dw 0x6f51, 0xc414, 0x6f51, 0xc414, 0x21, 0 + .dw 0x6f53, 0xc414, 0x6f7f, 0xc414, 0x21, 0 + .dw 0x6f81, 0xc414, 0x6f81, 0xc414, 0x21, 0 + .dw 0x6f83, 0xc414, 0x6f8f, 0xc414, 0x21, 0 + .dw 0x6f91, 0xc414, 0x6f91, 0xc414, 0x21, 0 + .dw 0x6f93, 0xc414, 0x6fbf, 0xc414, 0x21, 0 + .dw 0x6fc1, 0xc414, 0x6fc1, 0xc414, 0x21, 0 + .dw 0x6fc3, 0xc414, 0x6fcf, 0xc414, 0x21, 0 + .dw 0x6fd1, 0xc414, 0x6fd1, 0xc414, 0x21, 0 + .dw 0x6fd3, 0xc414, 0xffff, 0xc414, 0x21, 0 + .dw 0x0000, 0xc415, 0x0000, 0xc415, 0x22, 0 + .dw 0x0001, 0xc415, 0x0001, 0xc415, 0x21, 0 + .dw 0x0002, 0xc415, 0x0002, 0xc415, 0x22, 0 + .dw 0x0003, 0xc415, 0x000f, 0xc415, 0x21, 0 + .dw 0x0010, 0xc415, 0x0010, 0xc415, 0x22, 0 + .dw 0x0011, 0xc415, 0x0011, 0xc415, 0x21, 0 + .dw 0x0012, 0xc415, 0x0012, 0xc415, 0x22, 0 + .dw 0x0013, 0xc415, 0x003f, 0xc415, 0x21, 0 + .dw 0x0041, 0xc415, 0x0041, 0xc415, 0x21, 0 + .dw 0x0043, 0xc415, 0x004f, 0xc415, 0x21, 0 + .dw 0x0051, 0xc415, 0x0051, 0xc415, 0x21, 0 + .dw 0x0053, 0xc415, 0x007f, 0xc415, 0x21, 0 + .dw 0x0081, 0xc415, 0x0081, 0xc415, 0x21, 0 + .dw 0x0083, 0xc415, 0x008f, 0xc415, 0x21, 0 + .dw 0x0091, 0xc415, 0x0091, 0xc415, 0x21, 0 + .dw 0x0093, 0xc415, 0x00bf, 0xc415, 0x21, 0 + .dw 0x00c1, 0xc415, 0x00c1, 0xc415, 0x21, 0 + .dw 0x00c3, 0xc415, 0x00cf, 0xc415, 0x21, 0 + .dw 0x00d1, 0xc415, 0x00d1, 0xc415, 0x21, 0 + .dw 0x00d3, 0xc415, 0x00ff, 0xc415, 0x21, 0 + .dw 0x0101, 0xc415, 0x0101, 0xc415, 0x21, 0 + .dw 0x0103, 0xc415, 0x010f, 0xc415, 0x21, 0 + .dw 0x0111, 0xc415, 0x0111, 0xc415, 0x21, 0 + .dw 0x0113, 0xc415, 0x013f, 0xc415, 0x21, 0 + .dw 0x0141, 0xc415, 0x0141, 0xc415, 0x21, 0 + .dw 0x0143, 0xc415, 0x014f, 0xc415, 0x21, 0 + .dw 0x0151, 0xc415, 0x0151, 0xc415, 0x21, 0 + .dw 0x0153, 0xc415, 0x017f, 0xc415, 0x21, 0 + .dw 0x0181, 0xc415, 0x0181, 0xc415, 0x21, 0 + .dw 0x0183, 0xc415, 0x018f, 0xc415, 0x21, 0 + .dw 0x0191, 0xc415, 0x0191, 0xc415, 0x21, 0 + .dw 0x0193, 0xc415, 0x01bf, 0xc415, 0x21, 0 + .dw 0x01c1, 0xc415, 0x01c1, 0xc415, 0x21, 0 + .dw 0x01c3, 0xc415, 0x01cf, 0xc415, 0x21, 0 + .dw 0x01d1, 0xc415, 0x01d1, 0xc415, 0x21, 0 + .dw 0x01d3, 0xc415, 0x01ff, 0xc415, 0x21, 0 + .dw 0x0201, 0xc415, 0x0201, 0xc415, 0x21, 0 + .dw 0x0203, 0xc415, 0x020f, 0xc415, 0x21, 0 + .dw 0x0211, 0xc415, 0x0211, 0xc415, 0x21, 0 + .dw 0x0213, 0xc415, 0x023f, 0xc415, 0x21, 0 + .dw 0x0240, 0xc415, 0x0240, 0xc415, 0x22, 0 + .dw 0x0241, 0xc415, 0x0241, 0xc415, 0x21, 0 + .dw 0x0242, 0xc415, 0x0242, 0xc415, 0x22, 0 + .dw 0x0243, 0xc415, 0x024f, 0xc415, 0x21, 0 + .dw 0x0250, 0xc415, 0x0250, 0xc415, 0x22, 0 + .dw 0x0251, 0xc415, 0x0251, 0xc415, 0x21, 0 + .dw 0x0252, 0xc415, 0x0252, 0xc415, 0x22, 0 + .dw 0x0253, 0xc415, 0x027f, 0xc415, 0x21, 0 + .dw 0x0281, 0xc415, 0x0281, 0xc415, 0x21, 0 + .dw 0x0283, 0xc415, 0x028f, 0xc415, 0x21, 0 + .dw 0x0291, 0xc415, 0x0291, 0xc415, 0x21, 0 + .dw 0x0293, 0xc415, 0x02bf, 0xc415, 0x21, 0 + .dw 0x02c1, 0xc415, 0x02c1, 0xc415, 0x21, 0 + .dw 0x02c3, 0xc415, 0x02cf, 0xc415, 0x21, 0 + .dw 0x02d1, 0xc415, 0x02d1, 0xc415, 0x21, 0 + .dw 0x02d3, 0xc415, 0x02ff, 0xc415, 0x21, 0 + .dw 0x0301, 0xc415, 0x0301, 0xc415, 0x21, 0 + .dw 0x0303, 0xc415, 0x030f, 0xc415, 0x21, 0 + .dw 0x0311, 0xc415, 0x0311, 0xc415, 0x21, 0 + .dw 0x0313, 0xc415, 0x033f, 0xc415, 0x21, 0 + .dw 0x0341, 0xc415, 0x0341, 0xc415, 0x21, 0 + .dw 0x0343, 0xc415, 0x034f, 0xc415, 0x21, 0 + .dw 0x0351, 0xc415, 0x0351, 0xc415, 0x21, 0 + .dw 0x0353, 0xc415, 0x037f, 0xc415, 0x21, 0 + .dw 0x0381, 0xc415, 0x0381, 0xc415, 0x21, 0 + .dw 0x0383, 0xc415, 0x038f, 0xc415, 0x21, 0 + .dw 0x0391, 0xc415, 0x0391, 0xc415, 0x21, 0 + .dw 0x0393, 0xc415, 0x03bf, 0xc415, 0x21, 0 + .dw 0x03c1, 0xc415, 0x03c1, 0xc415, 0x21, 0 + .dw 0x03c3, 0xc415, 0x03cf, 0xc415, 0x21, 0 + .dw 0x03d1, 0xc415, 0x03d1, 0xc415, 0x21, 0 + .dw 0x03d3, 0xc415, 0x03ff, 0xc415, 0x21, 0 + .dw 0x0401, 0xc415, 0x0401, 0xc415, 0x21, 0 + .dw 0x0403, 0xc415, 0x040f, 0xc415, 0x21, 0 + .dw 0x0411, 0xc415, 0x0411, 0xc415, 0x21, 0 + .dw 0x0413, 0xc415, 0x043f, 0xc415, 0x21, 0 + .dw 0x0441, 0xc415, 0x0441, 0xc415, 0x21, 0 + .dw 0x0443, 0xc415, 0x044f, 0xc415, 0x21, 0 + .dw 0x0451, 0xc415, 0x0451, 0xc415, 0x21, 0 + .dw 0x0453, 0xc415, 0x047f, 0xc415, 0x21, 0 + .dw 0x0480, 0xc415, 0x0480, 0xc415, 0x22, 0 + .dw 0x0481, 0xc415, 0x0481, 0xc415, 0x21, 0 + .dw 0x0482, 0xc415, 0x0482, 0xc415, 0x22, 0 + .dw 0x0483, 0xc415, 0x048f, 0xc415, 0x21, 0 + .dw 0x0490, 0xc415, 0x0490, 0xc415, 0x22, 0 + .dw 0x0491, 0xc415, 0x0491, 0xc415, 0x21, 0 + .dw 0x0492, 0xc415, 0x0492, 0xc415, 0x22, 0 + .dw 0x0493, 0xc415, 0x04bf, 0xc415, 0x21, 0 + .dw 0x04c1, 0xc415, 0x04c1, 0xc415, 0x21, 0 + .dw 0x04c3, 0xc415, 0x04cf, 0xc415, 0x21, 0 + .dw 0x04d1, 0xc415, 0x04d1, 0xc415, 0x21, 0 + .dw 0x04d3, 0xc415, 0x04ff, 0xc415, 0x21, 0 + .dw 0x0501, 0xc415, 0x0501, 0xc415, 0x21, 0 + .dw 0x0503, 0xc415, 0x050f, 0xc415, 0x21, 0 + .dw 0x0511, 0xc415, 0x0511, 0xc415, 0x21, 0 + .dw 0x0513, 0xc415, 0x053f, 0xc415, 0x21, 0 + .dw 0x0541, 0xc415, 0x0541, 0xc415, 0x21, 0 + .dw 0x0543, 0xc415, 0x054f, 0xc415, 0x21, 0 + .dw 0x0551, 0xc415, 0x0551, 0xc415, 0x21, 0 + .dw 0x0553, 0xc415, 0x057f, 0xc415, 0x21, 0 + .dw 0x0581, 0xc415, 0x0581, 0xc415, 0x21, 0 + .dw 0x0583, 0xc415, 0x058f, 0xc415, 0x21, 0 + .dw 0x0591, 0xc415, 0x0591, 0xc415, 0x21, 0 + .dw 0x0593, 0xc415, 0x05bf, 0xc415, 0x21, 0 + .dw 0x05c1, 0xc415, 0x05c1, 0xc415, 0x21, 0 + .dw 0x05c3, 0xc415, 0x05cf, 0xc415, 0x21, 0 + .dw 0x05d1, 0xc415, 0x05d1, 0xc415, 0x21, 0 + .dw 0x05d3, 0xc415, 0x05ff, 0xc415, 0x21, 0 + .dw 0x0601, 0xc415, 0x0601, 0xc415, 0x21, 0 + .dw 0x0603, 0xc415, 0x060f, 0xc415, 0x21, 0 + .dw 0x0611, 0xc415, 0x0611, 0xc415, 0x21, 0 + .dw 0x0613, 0xc415, 0x063f, 0xc415, 0x21, 0 + .dw 0x0641, 0xc415, 0x0641, 0xc415, 0x21, 0 + .dw 0x0643, 0xc415, 0x064f, 0xc415, 0x21, 0 + .dw 0x0651, 0xc415, 0x0651, 0xc415, 0x21, 0 + .dw 0x0653, 0xc415, 0x067f, 0xc415, 0x21, 0 + .dw 0x0681, 0xc415, 0x0681, 0xc415, 0x21, 0 + .dw 0x0683, 0xc415, 0x068f, 0xc415, 0x21, 0 + .dw 0x0691, 0xc415, 0x0691, 0xc415, 0x21, 0 + .dw 0x0693, 0xc415, 0x06bf, 0xc415, 0x21, 0 + .dw 0x06c0, 0xc415, 0x06c0, 0xc415, 0x22, 0 + .dw 0x06c1, 0xc415, 0x06c1, 0xc415, 0x21, 0 + .dw 0x06c2, 0xc415, 0x06c2, 0xc415, 0x22, 0 + .dw 0x06c3, 0xc415, 0x06cf, 0xc415, 0x21, 0 + .dw 0x06d0, 0xc415, 0x06d0, 0xc415, 0x22, 0 + .dw 0x06d1, 0xc415, 0x06d1, 0xc415, 0x21, 0 + .dw 0x06d2, 0xc415, 0x06d2, 0xc415, 0x22, 0 + .dw 0x06d3, 0xc415, 0x06ff, 0xc415, 0x21, 0 + .dw 0x0701, 0xc415, 0x0701, 0xc415, 0x21, 0 + .dw 0x0703, 0xc415, 0x070f, 0xc415, 0x21, 0 + .dw 0x0711, 0xc415, 0x0711, 0xc415, 0x21, 0 + .dw 0x0713, 0xc415, 0x073f, 0xc415, 0x21, 0 + .dw 0x0741, 0xc415, 0x0741, 0xc415, 0x21, 0 + .dw 0x0743, 0xc415, 0x074f, 0xc415, 0x21, 0 + .dw 0x0751, 0xc415, 0x0751, 0xc415, 0x21, 0 + .dw 0x0753, 0xc415, 0x077f, 0xc415, 0x21, 0 + .dw 0x0781, 0xc415, 0x0781, 0xc415, 0x21, 0 + .dw 0x0783, 0xc415, 0x078f, 0xc415, 0x21, 0 + .dw 0x0791, 0xc415, 0x0791, 0xc415, 0x21, 0 + .dw 0x0793, 0xc415, 0x07bf, 0xc415, 0x21, 0 + .dw 0x07c1, 0xc415, 0x07c1, 0xc415, 0x21, 0 + .dw 0x07c3, 0xc415, 0x07cf, 0xc415, 0x21, 0 + .dw 0x07d1, 0xc415, 0x07d1, 0xc415, 0x21, 0 + .dw 0x07d3, 0xc415, 0x07ff, 0xc415, 0x21, 0 + .dw 0x0801, 0xc415, 0x0801, 0xc415, 0x21, 0 + .dw 0x0803, 0xc415, 0x080f, 0xc415, 0x21, 0 + .dw 0x0811, 0xc415, 0x0811, 0xc415, 0x21, 0 + .dw 0x0813, 0xc415, 0x083f, 0xc415, 0x21, 0 + .dw 0x0841, 0xc415, 0x0841, 0xc415, 0x21, 0 + .dw 0x0843, 0xc415, 0x084f, 0xc415, 0x21, 0 + .dw 0x0851, 0xc415, 0x0851, 0xc415, 0x21, 0 + .dw 0x0853, 0xc415, 0x087f, 0xc415, 0x21, 0 + .dw 0x0881, 0xc415, 0x0881, 0xc415, 0x21, 0 + .dw 0x0883, 0xc415, 0x088f, 0xc415, 0x21, 0 + .dw 0x0891, 0xc415, 0x0891, 0xc415, 0x21, 0 + .dw 0x0893, 0xc415, 0x08bf, 0xc415, 0x21, 0 + .dw 0x08c1, 0xc415, 0x08c1, 0xc415, 0x21, 0 + .dw 0x08c3, 0xc415, 0x08cf, 0xc415, 0x21, 0 + .dw 0x08d1, 0xc415, 0x08d1, 0xc415, 0x21, 0 + .dw 0x08d3, 0xc415, 0x08ff, 0xc415, 0x21, 0 + .dw 0x0900, 0xc415, 0x0900, 0xc415, 0x22, 0 + .dw 0x0901, 0xc415, 0x0901, 0xc415, 0x21, 0 + .dw 0x0902, 0xc415, 0x0902, 0xc415, 0x22, 0 + .dw 0x0903, 0xc415, 0x090f, 0xc415, 0x21, 0 + .dw 0x0910, 0xc415, 0x0910, 0xc415, 0x22, 0 + .dw 0x0911, 0xc415, 0x0911, 0xc415, 0x21, 0 + .dw 0x0912, 0xc415, 0x0912, 0xc415, 0x22, 0 + .dw 0x0913, 0xc415, 0x093f, 0xc415, 0x21, 0 + .dw 0x0941, 0xc415, 0x0941, 0xc415, 0x21, 0 + .dw 0x0943, 0xc415, 0x094f, 0xc415, 0x21, 0 + .dw 0x0951, 0xc415, 0x0951, 0xc415, 0x21, 0 + .dw 0x0953, 0xc415, 0x097f, 0xc415, 0x21, 0 + .dw 0x0981, 0xc415, 0x0981, 0xc415, 0x21, 0 + .dw 0x0983, 0xc415, 0x098f, 0xc415, 0x21, 0 + .dw 0x0991, 0xc415, 0x0991, 0xc415, 0x21, 0 + .dw 0x0993, 0xc415, 0x09bf, 0xc415, 0x21, 0 + .dw 0x09c1, 0xc415, 0x09c1, 0xc415, 0x21, 0 + .dw 0x09c3, 0xc415, 0x09cf, 0xc415, 0x21, 0 + .dw 0x09d1, 0xc415, 0x09d1, 0xc415, 0x21, 0 + .dw 0x09d3, 0xc415, 0x09ff, 0xc415, 0x21, 0 + .dw 0x0a01, 0xc415, 0x0a01, 0xc415, 0x21, 0 + .dw 0x0a03, 0xc415, 0x0a0f, 0xc415, 0x21, 0 + .dw 0x0a11, 0xc415, 0x0a11, 0xc415, 0x21, 0 + .dw 0x0a13, 0xc415, 0x0a3f, 0xc415, 0x21, 0 + .dw 0x0a41, 0xc415, 0x0a41, 0xc415, 0x21, 0 + .dw 0x0a43, 0xc415, 0x0a4f, 0xc415, 0x21, 0 + .dw 0x0a51, 0xc415, 0x0a51, 0xc415, 0x21, 0 + .dw 0x0a53, 0xc415, 0x0a7f, 0xc415, 0x21, 0 + .dw 0x0a81, 0xc415, 0x0a81, 0xc415, 0x21, 0 + .dw 0x0a83, 0xc415, 0x0a8f, 0xc415, 0x21, 0 + .dw 0x0a91, 0xc415, 0x0a91, 0xc415, 0x21, 0 + .dw 0x0a93, 0xc415, 0x0abf, 0xc415, 0x21, 0 + .dw 0x0ac1, 0xc415, 0x0ac1, 0xc415, 0x21, 0 + .dw 0x0ac3, 0xc415, 0x0acf, 0xc415, 0x21, 0 + .dw 0x0ad1, 0xc415, 0x0ad1, 0xc415, 0x21, 0 + .dw 0x0ad3, 0xc415, 0x0aff, 0xc415, 0x21, 0 + .dw 0x0b01, 0xc415, 0x0b01, 0xc415, 0x21, 0 + .dw 0x0b03, 0xc415, 0x0b0f, 0xc415, 0x21, 0 + .dw 0x0b11, 0xc415, 0x0b11, 0xc415, 0x21, 0 + .dw 0x0b13, 0xc415, 0x0b3f, 0xc415, 0x21, 0 + .dw 0x0b40, 0xc415, 0x0b40, 0xc415, 0x22, 0 + .dw 0x0b41, 0xc415, 0x0b41, 0xc415, 0x21, 0 + .dw 0x0b42, 0xc415, 0x0b42, 0xc415, 0x22, 0 + .dw 0x0b43, 0xc415, 0x0b4f, 0xc415, 0x21, 0 + .dw 0x0b50, 0xc415, 0x0b50, 0xc415, 0x22, 0 + .dw 0x0b51, 0xc415, 0x0b51, 0xc415, 0x21, 0 + .dw 0x0b52, 0xc415, 0x0b52, 0xc415, 0x22, 0 + .dw 0x0b53, 0xc415, 0x0b7f, 0xc415, 0x21, 0 + .dw 0x0b81, 0xc415, 0x0b81, 0xc415, 0x21, 0 + .dw 0x0b83, 0xc415, 0x0b8f, 0xc415, 0x21, 0 + .dw 0x0b91, 0xc415, 0x0b91, 0xc415, 0x21, 0 + .dw 0x0b93, 0xc415, 0x0bbf, 0xc415, 0x21, 0 + .dw 0x0bc1, 0xc415, 0x0bc1, 0xc415, 0x21, 0 + .dw 0x0bc3, 0xc415, 0x0bcf, 0xc415, 0x21, 0 + .dw 0x0bd1, 0xc415, 0x0bd1, 0xc415, 0x21, 0 + .dw 0x0bd3, 0xc415, 0x0bff, 0xc415, 0x21, 0 + .dw 0x0c01, 0xc415, 0x0c01, 0xc415, 0x21, 0 + .dw 0x0c03, 0xc415, 0x0c0f, 0xc415, 0x21, 0 + .dw 0x0c11, 0xc415, 0x0c11, 0xc415, 0x21, 0 + .dw 0x0c13, 0xc415, 0x0c3f, 0xc415, 0x21, 0 + .dw 0x0c41, 0xc415, 0x0c41, 0xc415, 0x21, 0 + .dw 0x0c43, 0xc415, 0x0c4f, 0xc415, 0x21, 0 + .dw 0x0c51, 0xc415, 0x0c51, 0xc415, 0x21, 0 + .dw 0x0c53, 0xc415, 0x0c7f, 0xc415, 0x21, 0 + .dw 0x0c81, 0xc415, 0x0c81, 0xc415, 0x21, 0 + .dw 0x0c83, 0xc415, 0x0c8f, 0xc415, 0x21, 0 + .dw 0x0c91, 0xc415, 0x0c91, 0xc415, 0x21, 0 + .dw 0x0c93, 0xc415, 0x0cbf, 0xc415, 0x21, 0 + .dw 0x0cc1, 0xc415, 0x0cc1, 0xc415, 0x21, 0 + .dw 0x0cc3, 0xc415, 0x0ccf, 0xc415, 0x21, 0 + .dw 0x0cd1, 0xc415, 0x0cd1, 0xc415, 0x21, 0 + .dw 0x0cd3, 0xc415, 0x0cff, 0xc415, 0x21, 0 + .dw 0x0d01, 0xc415, 0x0d01, 0xc415, 0x21, 0 + .dw 0x0d03, 0xc415, 0x0d0f, 0xc415, 0x21, 0 + .dw 0x0d11, 0xc415, 0x0d11, 0xc415, 0x21, 0 + .dw 0x0d13, 0xc415, 0x0d3f, 0xc415, 0x21, 0 + .dw 0x0d41, 0xc415, 0x0d41, 0xc415, 0x21, 0 + .dw 0x0d43, 0xc415, 0x0d4f, 0xc415, 0x21, 0 + .dw 0x0d51, 0xc415, 0x0d51, 0xc415, 0x21, 0 + .dw 0x0d53, 0xc415, 0x0d7f, 0xc415, 0x21, 0 + .dw 0x0d80, 0xc415, 0x0d80, 0xc415, 0x22, 0 + .dw 0x0d81, 0xc415, 0x0d81, 0xc415, 0x21, 0 + .dw 0x0d82, 0xc415, 0x0d82, 0xc415, 0x22, 0 + .dw 0x0d83, 0xc415, 0x0d8f, 0xc415, 0x21, 0 + .dw 0x0d90, 0xc415, 0x0d90, 0xc415, 0x22, 0 + .dw 0x0d91, 0xc415, 0x0d91, 0xc415, 0x21, 0 + .dw 0x0d92, 0xc415, 0x0d92, 0xc415, 0x22, 0 + .dw 0x0d93, 0xc415, 0x0dbf, 0xc415, 0x21, 0 + .dw 0x0dc1, 0xc415, 0x0dc1, 0xc415, 0x21, 0 + .dw 0x0dc3, 0xc415, 0x0dcf, 0xc415, 0x21, 0 + .dw 0x0dd1, 0xc415, 0x0dd1, 0xc415, 0x21, 0 + .dw 0x0dd3, 0xc415, 0x0dff, 0xc415, 0x21, 0 + .dw 0x0e01, 0xc415, 0x0e01, 0xc415, 0x21, 0 + .dw 0x0e03, 0xc415, 0x0e0f, 0xc415, 0x21, 0 + .dw 0x0e11, 0xc415, 0x0e11, 0xc415, 0x21, 0 + .dw 0x0e13, 0xc415, 0x0e3f, 0xc415, 0x21, 0 + .dw 0x0e41, 0xc415, 0x0e41, 0xc415, 0x21, 0 + .dw 0x0e43, 0xc415, 0x0e4f, 0xc415, 0x21, 0 + .dw 0x0e51, 0xc415, 0x0e51, 0xc415, 0x21, 0 + .dw 0x0e53, 0xc415, 0x0e7f, 0xc415, 0x21, 0 + .dw 0x0e81, 0xc415, 0x0e81, 0xc415, 0x21, 0 + .dw 0x0e83, 0xc415, 0x0e8f, 0xc415, 0x21, 0 + .dw 0x0e91, 0xc415, 0x0e91, 0xc415, 0x21, 0 + .dw 0x0e93, 0xc415, 0x0ebf, 0xc415, 0x21, 0 + .dw 0x0ec1, 0xc415, 0x0ec1, 0xc415, 0x21, 0 + .dw 0x0ec3, 0xc415, 0x0ecf, 0xc415, 0x21, 0 + .dw 0x0ed1, 0xc415, 0x0ed1, 0xc415, 0x21, 0 + .dw 0x0ed3, 0xc415, 0x0eff, 0xc415, 0x21, 0 + .dw 0x0f01, 0xc415, 0x0f01, 0xc415, 0x21, 0 + .dw 0x0f03, 0xc415, 0x0f0f, 0xc415, 0x21, 0 + .dw 0x0f11, 0xc415, 0x0f11, 0xc415, 0x21, 0 + .dw 0x0f13, 0xc415, 0x0f3f, 0xc415, 0x21, 0 + .dw 0x0f41, 0xc415, 0x0f41, 0xc415, 0x21, 0 + .dw 0x0f43, 0xc415, 0x0f4f, 0xc415, 0x21, 0 + .dw 0x0f51, 0xc415, 0x0f51, 0xc415, 0x21, 0 + .dw 0x0f53, 0xc415, 0x0f7f, 0xc415, 0x21, 0 + .dw 0x0f81, 0xc415, 0x0f81, 0xc415, 0x21, 0 + .dw 0x0f83, 0xc415, 0x0f8f, 0xc415, 0x21, 0 + .dw 0x0f91, 0xc415, 0x0f91, 0xc415, 0x21, 0 + .dw 0x0f93, 0xc415, 0x0fbf, 0xc415, 0x21, 0 + .dw 0x0fc0, 0xc415, 0x0fc0, 0xc415, 0x22, 0 + .dw 0x0fc1, 0xc415, 0x0fc1, 0xc415, 0x21, 0 + .dw 0x0fc2, 0xc415, 0x0fc2, 0xc415, 0x22, 0 + .dw 0x0fc3, 0xc415, 0x0fcf, 0xc415, 0x21, 0 + .dw 0x0fd0, 0xc415, 0x0fd0, 0xc415, 0x22, 0 + .dw 0x0fd1, 0xc415, 0x0fd1, 0xc415, 0x21, 0 + .dw 0x0fd2, 0xc415, 0x0fd2, 0xc415, 0x22, 0 + .dw 0x0fd3, 0xc415, 0x1fff, 0xc415, 0x21, 0 + .dw 0x2000, 0xc415, 0x2000, 0xc415, 0x22, 0 + .dw 0x2001, 0xc415, 0x2001, 0xc415, 0x21, 0 + .dw 0x2002, 0xc415, 0x2002, 0xc415, 0x22, 0 + .dw 0x2003, 0xc415, 0x200f, 0xc415, 0x21, 0 + .dw 0x2010, 0xc415, 0x2010, 0xc415, 0x22, 0 + .dw 0x2011, 0xc415, 0x2011, 0xc415, 0x21, 0 + .dw 0x2012, 0xc415, 0x2012, 0xc415, 0x22, 0 + .dw 0x2013, 0xc415, 0x203f, 0xc415, 0x21, 0 + .dw 0x2041, 0xc415, 0x2041, 0xc415, 0x21, 0 + .dw 0x2043, 0xc415, 0x204f, 0xc415, 0x21, 0 + .dw 0x2051, 0xc415, 0x2051, 0xc415, 0x21, 0 + .dw 0x2053, 0xc415, 0x207f, 0xc415, 0x21, 0 + .dw 0x2081, 0xc415, 0x2081, 0xc415, 0x21, 0 + .dw 0x2083, 0xc415, 0x208f, 0xc415, 0x21, 0 + .dw 0x2091, 0xc415, 0x2091, 0xc415, 0x21, 0 + .dw 0x2093, 0xc415, 0x20bf, 0xc415, 0x21, 0 + .dw 0x20c1, 0xc415, 0x20c1, 0xc415, 0x21, 0 + .dw 0x20c3, 0xc415, 0x20cf, 0xc415, 0x21, 0 + .dw 0x20d1, 0xc415, 0x20d1, 0xc415, 0x21, 0 + .dw 0x20d3, 0xc415, 0x20ff, 0xc415, 0x21, 0 + .dw 0x2101, 0xc415, 0x2101, 0xc415, 0x21, 0 + .dw 0x2103, 0xc415, 0x210f, 0xc415, 0x21, 0 + .dw 0x2111, 0xc415, 0x2111, 0xc415, 0x21, 0 + .dw 0x2113, 0xc415, 0x213f, 0xc415, 0x21, 0 + .dw 0x2141, 0xc415, 0x2141, 0xc415, 0x21, 0 + .dw 0x2143, 0xc415, 0x214f, 0xc415, 0x21, 0 + .dw 0x2151, 0xc415, 0x2151, 0xc415, 0x21, 0 + .dw 0x2153, 0xc415, 0x217f, 0xc415, 0x21, 0 + .dw 0x2181, 0xc415, 0x2181, 0xc415, 0x21, 0 + .dw 0x2183, 0xc415, 0x218f, 0xc415, 0x21, 0 + .dw 0x2191, 0xc415, 0x2191, 0xc415, 0x21, 0 + .dw 0x2193, 0xc415, 0x21bf, 0xc415, 0x21, 0 + .dw 0x21c1, 0xc415, 0x21c1, 0xc415, 0x21, 0 + .dw 0x21c3, 0xc415, 0x21cf, 0xc415, 0x21, 0 + .dw 0x21d1, 0xc415, 0x21d1, 0xc415, 0x21, 0 + .dw 0x21d3, 0xc415, 0x21ff, 0xc415, 0x21, 0 + .dw 0x2201, 0xc415, 0x2201, 0xc415, 0x21, 0 + .dw 0x2203, 0xc415, 0x220f, 0xc415, 0x21, 0 + .dw 0x2211, 0xc415, 0x2211, 0xc415, 0x21, 0 + .dw 0x2213, 0xc415, 0x223f, 0xc415, 0x21, 0 + .dw 0x2240, 0xc415, 0x2240, 0xc415, 0x22, 0 + .dw 0x2241, 0xc415, 0x2241, 0xc415, 0x21, 0 + .dw 0x2242, 0xc415, 0x2242, 0xc415, 0x22, 0 + .dw 0x2243, 0xc415, 0x224f, 0xc415, 0x21, 0 + .dw 0x2250, 0xc415, 0x2250, 0xc415, 0x22, 0 + .dw 0x2251, 0xc415, 0x2251, 0xc415, 0x21, 0 + .dw 0x2252, 0xc415, 0x2252, 0xc415, 0x22, 0 + .dw 0x2253, 0xc415, 0x227f, 0xc415, 0x21, 0 + .dw 0x2281, 0xc415, 0x2281, 0xc415, 0x21, 0 + .dw 0x2283, 0xc415, 0x228f, 0xc415, 0x21, 0 + .dw 0x2291, 0xc415, 0x2291, 0xc415, 0x21, 0 + .dw 0x2293, 0xc415, 0x22bf, 0xc415, 0x21, 0 + .dw 0x22c1, 0xc415, 0x22c1, 0xc415, 0x21, 0 + .dw 0x22c3, 0xc415, 0x22cf, 0xc415, 0x21, 0 + .dw 0x22d1, 0xc415, 0x22d1, 0xc415, 0x21, 0 + .dw 0x22d3, 0xc415, 0x22ff, 0xc415, 0x21, 0 + .dw 0x2301, 0xc415, 0x2301, 0xc415, 0x21, 0 + .dw 0x2303, 0xc415, 0x230f, 0xc415, 0x21, 0 + .dw 0x2311, 0xc415, 0x2311, 0xc415, 0x21, 0 + .dw 0x2313, 0xc415, 0x233f, 0xc415, 0x21, 0 + .dw 0x2341, 0xc415, 0x2341, 0xc415, 0x21, 0 + .dw 0x2343, 0xc415, 0x234f, 0xc415, 0x21, 0 + .dw 0x2351, 0xc415, 0x2351, 0xc415, 0x21, 0 + .dw 0x2353, 0xc415, 0x237f, 0xc415, 0x21, 0 + .dw 0x2381, 0xc415, 0x2381, 0xc415, 0x21, 0 + .dw 0x2383, 0xc415, 0x238f, 0xc415, 0x21, 0 + .dw 0x2391, 0xc415, 0x2391, 0xc415, 0x21, 0 + .dw 0x2393, 0xc415, 0x23bf, 0xc415, 0x21, 0 + .dw 0x23c1, 0xc415, 0x23c1, 0xc415, 0x21, 0 + .dw 0x23c3, 0xc415, 0x23cf, 0xc415, 0x21, 0 + .dw 0x23d1, 0xc415, 0x23d1, 0xc415, 0x21, 0 + .dw 0x23d3, 0xc415, 0x23ff, 0xc415, 0x21, 0 + .dw 0x2401, 0xc415, 0x2401, 0xc415, 0x21, 0 + .dw 0x2403, 0xc415, 0x240f, 0xc415, 0x21, 0 + .dw 0x2411, 0xc415, 0x2411, 0xc415, 0x21, 0 + .dw 0x2413, 0xc415, 0x243f, 0xc415, 0x21, 0 + .dw 0x2441, 0xc415, 0x2441, 0xc415, 0x21, 0 + .dw 0x2443, 0xc415, 0x244f, 0xc415, 0x21, 0 + .dw 0x2451, 0xc415, 0x2451, 0xc415, 0x21, 0 + .dw 0x2453, 0xc415, 0x247f, 0xc415, 0x21, 0 + .dw 0x2480, 0xc415, 0x2480, 0xc415, 0x22, 0 + .dw 0x2481, 0xc415, 0x2481, 0xc415, 0x21, 0 + .dw 0x2482, 0xc415, 0x2482, 0xc415, 0x22, 0 + .dw 0x2483, 0xc415, 0x248f, 0xc415, 0x21, 0 + .dw 0x2490, 0xc415, 0x2490, 0xc415, 0x22, 0 + .dw 0x2491, 0xc415, 0x2491, 0xc415, 0x21, 0 + .dw 0x2492, 0xc415, 0x2492, 0xc415, 0x22, 0 + .dw 0x2493, 0xc415, 0x24bf, 0xc415, 0x21, 0 + .dw 0x24c1, 0xc415, 0x24c1, 0xc415, 0x21, 0 + .dw 0x24c3, 0xc415, 0x24cf, 0xc415, 0x21, 0 + .dw 0x24d1, 0xc415, 0x24d1, 0xc415, 0x21, 0 + .dw 0x24d3, 0xc415, 0x24ff, 0xc415, 0x21, 0 + .dw 0x2501, 0xc415, 0x2501, 0xc415, 0x21, 0 + .dw 0x2503, 0xc415, 0x250f, 0xc415, 0x21, 0 + .dw 0x2511, 0xc415, 0x2511, 0xc415, 0x21, 0 + .dw 0x2513, 0xc415, 0x253f, 0xc415, 0x21, 0 + .dw 0x2541, 0xc415, 0x2541, 0xc415, 0x21, 0 + .dw 0x2543, 0xc415, 0x254f, 0xc415, 0x21, 0 + .dw 0x2551, 0xc415, 0x2551, 0xc415, 0x21, 0 + .dw 0x2553, 0xc415, 0x257f, 0xc415, 0x21, 0 + .dw 0x2581, 0xc415, 0x2581, 0xc415, 0x21, 0 + .dw 0x2583, 0xc415, 0x258f, 0xc415, 0x21, 0 + .dw 0x2591, 0xc415, 0x2591, 0xc415, 0x21, 0 + .dw 0x2593, 0xc415, 0x25bf, 0xc415, 0x21, 0 + .dw 0x25c1, 0xc415, 0x25c1, 0xc415, 0x21, 0 + .dw 0x25c3, 0xc415, 0x25cf, 0xc415, 0x21, 0 + .dw 0x25d1, 0xc415, 0x25d1, 0xc415, 0x21, 0 + .dw 0x25d3, 0xc415, 0x25ff, 0xc415, 0x21, 0 + .dw 0x2601, 0xc415, 0x2601, 0xc415, 0x21, 0 + .dw 0x2603, 0xc415, 0x260f, 0xc415, 0x21, 0 + .dw 0x2611, 0xc415, 0x2611, 0xc415, 0x21, 0 + .dw 0x2613, 0xc415, 0x263f, 0xc415, 0x21, 0 + .dw 0x2641, 0xc415, 0x2641, 0xc415, 0x21, 0 + .dw 0x2643, 0xc415, 0x264f, 0xc415, 0x21, 0 + .dw 0x2651, 0xc415, 0x2651, 0xc415, 0x21, 0 + .dw 0x2653, 0xc415, 0x267f, 0xc415, 0x21, 0 + .dw 0x2681, 0xc415, 0x2681, 0xc415, 0x21, 0 + .dw 0x2683, 0xc415, 0x268f, 0xc415, 0x21, 0 + .dw 0x2691, 0xc415, 0x2691, 0xc415, 0x21, 0 + .dw 0x2693, 0xc415, 0x26bf, 0xc415, 0x21, 0 + .dw 0x26c0, 0xc415, 0x26c0, 0xc415, 0x22, 0 + .dw 0x26c1, 0xc415, 0x26c1, 0xc415, 0x21, 0 + .dw 0x26c2, 0xc415, 0x26c2, 0xc415, 0x22, 0 + .dw 0x26c3, 0xc415, 0x26cf, 0xc415, 0x21, 0 + .dw 0x26d0, 0xc415, 0x26d0, 0xc415, 0x22, 0 + .dw 0x26d1, 0xc415, 0x26d1, 0xc415, 0x21, 0 + .dw 0x26d2, 0xc415, 0x26d2, 0xc415, 0x22, 0 + .dw 0x26d3, 0xc415, 0x26ff, 0xc415, 0x21, 0 + .dw 0x2701, 0xc415, 0x2701, 0xc415, 0x21, 0 + .dw 0x2703, 0xc415, 0x270f, 0xc415, 0x21, 0 + .dw 0x2711, 0xc415, 0x2711, 0xc415, 0x21, 0 + .dw 0x2713, 0xc415, 0x273f, 0xc415, 0x21, 0 + .dw 0x2741, 0xc415, 0x2741, 0xc415, 0x21, 0 + .dw 0x2743, 0xc415, 0x274f, 0xc415, 0x21, 0 + .dw 0x2751, 0xc415, 0x2751, 0xc415, 0x21, 0 + .dw 0x2753, 0xc415, 0x277f, 0xc415, 0x21, 0 + .dw 0x2781, 0xc415, 0x2781, 0xc415, 0x21, 0 + .dw 0x2783, 0xc415, 0x278f, 0xc415, 0x21, 0 + .dw 0x2791, 0xc415, 0x2791, 0xc415, 0x21, 0 + .dw 0x2793, 0xc415, 0x27bf, 0xc415, 0x21, 0 + .dw 0x27c1, 0xc415, 0x27c1, 0xc415, 0x21, 0 + .dw 0x27c3, 0xc415, 0x27cf, 0xc415, 0x21, 0 + .dw 0x27d1, 0xc415, 0x27d1, 0xc415, 0x21, 0 + .dw 0x27d3, 0xc415, 0x27ff, 0xc415, 0x21, 0 + .dw 0x2801, 0xc415, 0x2801, 0xc415, 0x21, 0 + .dw 0x2803, 0xc415, 0x280f, 0xc415, 0x21, 0 + .dw 0x2811, 0xc415, 0x2811, 0xc415, 0x21, 0 + .dw 0x2813, 0xc415, 0x283f, 0xc415, 0x21, 0 + .dw 0x2841, 0xc415, 0x2841, 0xc415, 0x21, 0 + .dw 0x2843, 0xc415, 0x284f, 0xc415, 0x21, 0 + .dw 0x2851, 0xc415, 0x2851, 0xc415, 0x21, 0 + .dw 0x2853, 0xc415, 0x287f, 0xc415, 0x21, 0 + .dw 0x2881, 0xc415, 0x2881, 0xc415, 0x21, 0 + .dw 0x2883, 0xc415, 0x288f, 0xc415, 0x21, 0 + .dw 0x2891, 0xc415, 0x2891, 0xc415, 0x21, 0 + .dw 0x2893, 0xc415, 0x28bf, 0xc415, 0x21, 0 + .dw 0x28c1, 0xc415, 0x28c1, 0xc415, 0x21, 0 + .dw 0x28c3, 0xc415, 0x28cf, 0xc415, 0x21, 0 + .dw 0x28d1, 0xc415, 0x28d1, 0xc415, 0x21, 0 + .dw 0x28d3, 0xc415, 0x28ff, 0xc415, 0x21, 0 + .dw 0x2900, 0xc415, 0x2900, 0xc415, 0x22, 0 + .dw 0x2901, 0xc415, 0x2901, 0xc415, 0x21, 0 + .dw 0x2902, 0xc415, 0x2902, 0xc415, 0x22, 0 + .dw 0x2903, 0xc415, 0x290f, 0xc415, 0x21, 0 + .dw 0x2910, 0xc415, 0x2910, 0xc415, 0x22, 0 + .dw 0x2911, 0xc415, 0x2911, 0xc415, 0x21, 0 + .dw 0x2912, 0xc415, 0x2912, 0xc415, 0x22, 0 + .dw 0x2913, 0xc415, 0x293f, 0xc415, 0x21, 0 + .dw 0x2941, 0xc415, 0x2941, 0xc415, 0x21, 0 + .dw 0x2943, 0xc415, 0x294f, 0xc415, 0x21, 0 + .dw 0x2951, 0xc415, 0x2951, 0xc415, 0x21, 0 + .dw 0x2953, 0xc415, 0x297f, 0xc415, 0x21, 0 + .dw 0x2981, 0xc415, 0x2981, 0xc415, 0x21, 0 + .dw 0x2983, 0xc415, 0x298f, 0xc415, 0x21, 0 + .dw 0x2991, 0xc415, 0x2991, 0xc415, 0x21, 0 + .dw 0x2993, 0xc415, 0x29bf, 0xc415, 0x21, 0 + .dw 0x29c1, 0xc415, 0x29c1, 0xc415, 0x21, 0 + .dw 0x29c3, 0xc415, 0x29cf, 0xc415, 0x21, 0 + .dw 0x29d1, 0xc415, 0x29d1, 0xc415, 0x21, 0 + .dw 0x29d3, 0xc415, 0x29ff, 0xc415, 0x21, 0 + .dw 0x2a01, 0xc415, 0x2a01, 0xc415, 0x21, 0 + .dw 0x2a03, 0xc415, 0x2a0f, 0xc415, 0x21, 0 + .dw 0x2a11, 0xc415, 0x2a11, 0xc415, 0x21, 0 + .dw 0x2a13, 0xc415, 0x2a3f, 0xc415, 0x21, 0 + .dw 0x2a41, 0xc415, 0x2a41, 0xc415, 0x21, 0 + .dw 0x2a43, 0xc415, 0x2a4f, 0xc415, 0x21, 0 + .dw 0x2a51, 0xc415, 0x2a51, 0xc415, 0x21, 0 + .dw 0x2a53, 0xc415, 0x2a7f, 0xc415, 0x21, 0 + .dw 0x2a81, 0xc415, 0x2a81, 0xc415, 0x21, 0 + .dw 0x2a83, 0xc415, 0x2a8f, 0xc415, 0x21, 0 + .dw 0x2a91, 0xc415, 0x2a91, 0xc415, 0x21, 0 + .dw 0x2a93, 0xc415, 0x2abf, 0xc415, 0x21, 0 + .dw 0x2ac1, 0xc415, 0x2ac1, 0xc415, 0x21, 0 + .dw 0x2ac3, 0xc415, 0x2acf, 0xc415, 0x21, 0 + .dw 0x2ad1, 0xc415, 0x2ad1, 0xc415, 0x21, 0 + .dw 0x2ad3, 0xc415, 0x2aff, 0xc415, 0x21, 0 + .dw 0x2b01, 0xc415, 0x2b01, 0xc415, 0x21, 0 + .dw 0x2b03, 0xc415, 0x2b0f, 0xc415, 0x21, 0 + .dw 0x2b11, 0xc415, 0x2b11, 0xc415, 0x21, 0 + .dw 0x2b13, 0xc415, 0x2b3f, 0xc415, 0x21, 0 + .dw 0x2b40, 0xc415, 0x2b40, 0xc415, 0x22, 0 + .dw 0x2b41, 0xc415, 0x2b41, 0xc415, 0x21, 0 + .dw 0x2b42, 0xc415, 0x2b42, 0xc415, 0x22, 0 + .dw 0x2b43, 0xc415, 0x2b4f, 0xc415, 0x21, 0 + .dw 0x2b50, 0xc415, 0x2b50, 0xc415, 0x22, 0 + .dw 0x2b51, 0xc415, 0x2b51, 0xc415, 0x21, 0 + .dw 0x2b52, 0xc415, 0x2b52, 0xc415, 0x22, 0 + .dw 0x2b53, 0xc415, 0x2b7f, 0xc415, 0x21, 0 + .dw 0x2b81, 0xc415, 0x2b81, 0xc415, 0x21, 0 + .dw 0x2b83, 0xc415, 0x2b8f, 0xc415, 0x21, 0 + .dw 0x2b91, 0xc415, 0x2b91, 0xc415, 0x21, 0 + .dw 0x2b93, 0xc415, 0x2bbf, 0xc415, 0x21, 0 + .dw 0x2bc1, 0xc415, 0x2bc1, 0xc415, 0x21, 0 + .dw 0x2bc3, 0xc415, 0x2bcf, 0xc415, 0x21, 0 + .dw 0x2bd1, 0xc415, 0x2bd1, 0xc415, 0x21, 0 + .dw 0x2bd3, 0xc415, 0x2bff, 0xc415, 0x21, 0 + .dw 0x2c01, 0xc415, 0x2c01, 0xc415, 0x21, 0 + .dw 0x2c03, 0xc415, 0x2c0f, 0xc415, 0x21, 0 + .dw 0x2c11, 0xc415, 0x2c11, 0xc415, 0x21, 0 + .dw 0x2c13, 0xc415, 0x2c3f, 0xc415, 0x21, 0 + .dw 0x2c41, 0xc415, 0x2c41, 0xc415, 0x21, 0 + .dw 0x2c43, 0xc415, 0x2c4f, 0xc415, 0x21, 0 + .dw 0x2c51, 0xc415, 0x2c51, 0xc415, 0x21, 0 + .dw 0x2c53, 0xc415, 0x2c7f, 0xc415, 0x21, 0 + .dw 0x2c81, 0xc415, 0x2c81, 0xc415, 0x21, 0 + .dw 0x2c83, 0xc415, 0x2c8f, 0xc415, 0x21, 0 + .dw 0x2c91, 0xc415, 0x2c91, 0xc415, 0x21, 0 + .dw 0x2c93, 0xc415, 0x2cbf, 0xc415, 0x21, 0 + .dw 0x2cc1, 0xc415, 0x2cc1, 0xc415, 0x21, 0 + .dw 0x2cc3, 0xc415, 0x2ccf, 0xc415, 0x21, 0 + .dw 0x2cd1, 0xc415, 0x2cd1, 0xc415, 0x21, 0 + .dw 0x2cd3, 0xc415, 0x2cff, 0xc415, 0x21, 0 + .dw 0x2d01, 0xc415, 0x2d01, 0xc415, 0x21, 0 + .dw 0x2d03, 0xc415, 0x2d0f, 0xc415, 0x21, 0 + .dw 0x2d11, 0xc415, 0x2d11, 0xc415, 0x21, 0 + .dw 0x2d13, 0xc415, 0x2d3f, 0xc415, 0x21, 0 + .dw 0x2d41, 0xc415, 0x2d41, 0xc415, 0x21, 0 + .dw 0x2d43, 0xc415, 0x2d4f, 0xc415, 0x21, 0 + .dw 0x2d51, 0xc415, 0x2d51, 0xc415, 0x21, 0 + .dw 0x2d53, 0xc415, 0x2d7f, 0xc415, 0x21, 0 + .dw 0x2d80, 0xc415, 0x2d80, 0xc415, 0x22, 0 + .dw 0x2d81, 0xc415, 0x2d81, 0xc415, 0x21, 0 + .dw 0x2d82, 0xc415, 0x2d82, 0xc415, 0x22, 0 + .dw 0x2d83, 0xc415, 0x2d8f, 0xc415, 0x21, 0 + .dw 0x2d90, 0xc415, 0x2d90, 0xc415, 0x22, 0 + .dw 0x2d91, 0xc415, 0x2d91, 0xc415, 0x21, 0 + .dw 0x2d92, 0xc415, 0x2d92, 0xc415, 0x22, 0 + .dw 0x2d93, 0xc415, 0x2dbf, 0xc415, 0x21, 0 + .dw 0x2dc1, 0xc415, 0x2dc1, 0xc415, 0x21, 0 + .dw 0x2dc3, 0xc415, 0x2dcf, 0xc415, 0x21, 0 + .dw 0x2dd1, 0xc415, 0x2dd1, 0xc415, 0x21, 0 + .dw 0x2dd3, 0xc415, 0x2dff, 0xc415, 0x21, 0 + .dw 0x2e01, 0xc415, 0x2e01, 0xc415, 0x21, 0 + .dw 0x2e03, 0xc415, 0x2e0f, 0xc415, 0x21, 0 + .dw 0x2e11, 0xc415, 0x2e11, 0xc415, 0x21, 0 + .dw 0x2e13, 0xc415, 0x2e3f, 0xc415, 0x21, 0 + .dw 0x2e41, 0xc415, 0x2e41, 0xc415, 0x21, 0 + .dw 0x2e43, 0xc415, 0x2e4f, 0xc415, 0x21, 0 + .dw 0x2e51, 0xc415, 0x2e51, 0xc415, 0x21, 0 + .dw 0x2e53, 0xc415, 0x2e7f, 0xc415, 0x21, 0 + .dw 0x2e81, 0xc415, 0x2e81, 0xc415, 0x21, 0 + .dw 0x2e83, 0xc415, 0x2e8f, 0xc415, 0x21, 0 + .dw 0x2e91, 0xc415, 0x2e91, 0xc415, 0x21, 0 + .dw 0x2e93, 0xc415, 0x2ebf, 0xc415, 0x21, 0 + .dw 0x2ec1, 0xc415, 0x2ec1, 0xc415, 0x21, 0 + .dw 0x2ec3, 0xc415, 0x2ecf, 0xc415, 0x21, 0 + .dw 0x2ed1, 0xc415, 0x2ed1, 0xc415, 0x21, 0 + .dw 0x2ed3, 0xc415, 0x2eff, 0xc415, 0x21, 0 + .dw 0x2f01, 0xc415, 0x2f01, 0xc415, 0x21, 0 + .dw 0x2f03, 0xc415, 0x2f0f, 0xc415, 0x21, 0 + .dw 0x2f11, 0xc415, 0x2f11, 0xc415, 0x21, 0 + .dw 0x2f13, 0xc415, 0x2f3f, 0xc415, 0x21, 0 + .dw 0x2f41, 0xc415, 0x2f41, 0xc415, 0x21, 0 + .dw 0x2f43, 0xc415, 0x2f4f, 0xc415, 0x21, 0 + .dw 0x2f51, 0xc415, 0x2f51, 0xc415, 0x21, 0 + .dw 0x2f53, 0xc415, 0x2f7f, 0xc415, 0x21, 0 + .dw 0x2f81, 0xc415, 0x2f81, 0xc415, 0x21, 0 + .dw 0x2f83, 0xc415, 0x2f8f, 0xc415, 0x21, 0 + .dw 0x2f91, 0xc415, 0x2f91, 0xc415, 0x21, 0 + .dw 0x2f93, 0xc415, 0x2fbf, 0xc415, 0x21, 0 + .dw 0x2fc0, 0xc415, 0x2fc0, 0xc415, 0x22, 0 + .dw 0x2fc1, 0xc415, 0x2fc1, 0xc415, 0x21, 0 + .dw 0x2fc2, 0xc415, 0x2fc2, 0xc415, 0x22, 0 + .dw 0x2fc3, 0xc415, 0x2fcf, 0xc415, 0x21, 0 + .dw 0x2fd0, 0xc415, 0x2fd0, 0xc415, 0x22, 0 + .dw 0x2fd1, 0xc415, 0x2fd1, 0xc415, 0x21, 0 + .dw 0x2fd2, 0xc415, 0x2fd2, 0xc415, 0x22, 0 + .dw 0x2fd3, 0xc415, 0x3fff, 0xc415, 0x21, 0 + .dw 0x4000, 0xc415, 0x4000, 0xc415, 0x22, 0 + .dw 0x4001, 0xc415, 0x4001, 0xc415, 0x21, 0 + .dw 0x4002, 0xc415, 0x4002, 0xc415, 0x22, 0 + .dw 0x4003, 0xc415, 0x400f, 0xc415, 0x21, 0 + .dw 0x4010, 0xc415, 0x4010, 0xc415, 0x22, 0 + .dw 0x4011, 0xc415, 0x4011, 0xc415, 0x21, 0 + .dw 0x4012, 0xc415, 0x4012, 0xc415, 0x22, 0 + .dw 0x4013, 0xc415, 0x403f, 0xc415, 0x21, 0 + .dw 0x4041, 0xc415, 0x4041, 0xc415, 0x21, 0 + .dw 0x4043, 0xc415, 0x404f, 0xc415, 0x21, 0 + .dw 0x4051, 0xc415, 0x4051, 0xc415, 0x21, 0 + .dw 0x4053, 0xc415, 0x407f, 0xc415, 0x21, 0 + .dw 0x4081, 0xc415, 0x4081, 0xc415, 0x21, 0 + .dw 0x4083, 0xc415, 0x408f, 0xc415, 0x21, 0 + .dw 0x4091, 0xc415, 0x4091, 0xc415, 0x21, 0 + .dw 0x4093, 0xc415, 0x40bf, 0xc415, 0x21, 0 + .dw 0x40c1, 0xc415, 0x40c1, 0xc415, 0x21, 0 + .dw 0x40c3, 0xc415, 0x40cf, 0xc415, 0x21, 0 + .dw 0x40d1, 0xc415, 0x40d1, 0xc415, 0x21, 0 + .dw 0x40d3, 0xc415, 0x40ff, 0xc415, 0x21, 0 + .dw 0x4101, 0xc415, 0x4101, 0xc415, 0x21, 0 + .dw 0x4103, 0xc415, 0x410f, 0xc415, 0x21, 0 + .dw 0x4111, 0xc415, 0x4111, 0xc415, 0x21, 0 + .dw 0x4113, 0xc415, 0x413f, 0xc415, 0x21, 0 + .dw 0x4141, 0xc415, 0x4141, 0xc415, 0x21, 0 + .dw 0x4143, 0xc415, 0x414f, 0xc415, 0x21, 0 + .dw 0x4151, 0xc415, 0x4151, 0xc415, 0x21, 0 + .dw 0x4153, 0xc415, 0x417f, 0xc415, 0x21, 0 + .dw 0x4181, 0xc415, 0x4181, 0xc415, 0x21, 0 + .dw 0x4183, 0xc415, 0x418f, 0xc415, 0x21, 0 + .dw 0x4191, 0xc415, 0x4191, 0xc415, 0x21, 0 + .dw 0x4193, 0xc415, 0x41bf, 0xc415, 0x21, 0 + .dw 0x41c1, 0xc415, 0x41c1, 0xc415, 0x21, 0 + .dw 0x41c3, 0xc415, 0x41cf, 0xc415, 0x21, 0 + .dw 0x41d1, 0xc415, 0x41d1, 0xc415, 0x21, 0 + .dw 0x41d3, 0xc415, 0x41ff, 0xc415, 0x21, 0 + .dw 0x4201, 0xc415, 0x4201, 0xc415, 0x21, 0 + .dw 0x4203, 0xc415, 0x420f, 0xc415, 0x21, 0 + .dw 0x4211, 0xc415, 0x4211, 0xc415, 0x21, 0 + .dw 0x4213, 0xc415, 0x423f, 0xc415, 0x21, 0 + .dw 0x4240, 0xc415, 0x4240, 0xc415, 0x22, 0 + .dw 0x4241, 0xc415, 0x4241, 0xc415, 0x21, 0 + .dw 0x4242, 0xc415, 0x4242, 0xc415, 0x22, 0 + .dw 0x4243, 0xc415, 0x424f, 0xc415, 0x21, 0 + .dw 0x4250, 0xc415, 0x4250, 0xc415, 0x22, 0 + .dw 0x4251, 0xc415, 0x4251, 0xc415, 0x21, 0 + .dw 0x4252, 0xc415, 0x4252, 0xc415, 0x22, 0 + .dw 0x4253, 0xc415, 0x427f, 0xc415, 0x21, 0 + .dw 0x4281, 0xc415, 0x4281, 0xc415, 0x21, 0 + .dw 0x4283, 0xc415, 0x428f, 0xc415, 0x21, 0 + .dw 0x4291, 0xc415, 0x4291, 0xc415, 0x21, 0 + .dw 0x4293, 0xc415, 0x42bf, 0xc415, 0x21, 0 + .dw 0x42c1, 0xc415, 0x42c1, 0xc415, 0x21, 0 + .dw 0x42c3, 0xc415, 0x42cf, 0xc415, 0x21, 0 + .dw 0x42d1, 0xc415, 0x42d1, 0xc415, 0x21, 0 + .dw 0x42d3, 0xc415, 0x42ff, 0xc415, 0x21, 0 + .dw 0x4301, 0xc415, 0x4301, 0xc415, 0x21, 0 + .dw 0x4303, 0xc415, 0x430f, 0xc415, 0x21, 0 + .dw 0x4311, 0xc415, 0x4311, 0xc415, 0x21, 0 + .dw 0x4313, 0xc415, 0x433f, 0xc415, 0x21, 0 + .dw 0x4341, 0xc415, 0x4341, 0xc415, 0x21, 0 + .dw 0x4343, 0xc415, 0x434f, 0xc415, 0x21, 0 + .dw 0x4351, 0xc415, 0x4351, 0xc415, 0x21, 0 + .dw 0x4353, 0xc415, 0x437f, 0xc415, 0x21, 0 + .dw 0x4381, 0xc415, 0x4381, 0xc415, 0x21, 0 + .dw 0x4383, 0xc415, 0x438f, 0xc415, 0x21, 0 + .dw 0x4391, 0xc415, 0x4391, 0xc415, 0x21, 0 + .dw 0x4393, 0xc415, 0x43bf, 0xc415, 0x21, 0 + .dw 0x43c1, 0xc415, 0x43c1, 0xc415, 0x21, 0 + .dw 0x43c3, 0xc415, 0x43cf, 0xc415, 0x21, 0 + .dw 0x43d1, 0xc415, 0x43d1, 0xc415, 0x21, 0 + .dw 0x43d3, 0xc415, 0x43ff, 0xc415, 0x21, 0 + .dw 0x4401, 0xc415, 0x4401, 0xc415, 0x21, 0 + .dw 0x4403, 0xc415, 0x440f, 0xc415, 0x21, 0 + .dw 0x4411, 0xc415, 0x4411, 0xc415, 0x21, 0 + .dw 0x4413, 0xc415, 0x443f, 0xc415, 0x21, 0 + .dw 0x4441, 0xc415, 0x4441, 0xc415, 0x21, 0 + .dw 0x4443, 0xc415, 0x444f, 0xc415, 0x21, 0 + .dw 0x4451, 0xc415, 0x4451, 0xc415, 0x21, 0 + .dw 0x4453, 0xc415, 0x447f, 0xc415, 0x21, 0 + .dw 0x4480, 0xc415, 0x4480, 0xc415, 0x22, 0 + .dw 0x4481, 0xc415, 0x4481, 0xc415, 0x21, 0 + .dw 0x4482, 0xc415, 0x4482, 0xc415, 0x22, 0 + .dw 0x4483, 0xc415, 0x448f, 0xc415, 0x21, 0 + .dw 0x4490, 0xc415, 0x4490, 0xc415, 0x22, 0 + .dw 0x4491, 0xc415, 0x4491, 0xc415, 0x21, 0 + .dw 0x4492, 0xc415, 0x4492, 0xc415, 0x22, 0 + .dw 0x4493, 0xc415, 0x44bf, 0xc415, 0x21, 0 + .dw 0x44c1, 0xc415, 0x44c1, 0xc415, 0x21, 0 + .dw 0x44c3, 0xc415, 0x44cf, 0xc415, 0x21, 0 + .dw 0x44d1, 0xc415, 0x44d1, 0xc415, 0x21, 0 + .dw 0x44d3, 0xc415, 0x44ff, 0xc415, 0x21, 0 + .dw 0x4501, 0xc415, 0x4501, 0xc415, 0x21, 0 + .dw 0x4503, 0xc415, 0x450f, 0xc415, 0x21, 0 + .dw 0x4511, 0xc415, 0x4511, 0xc415, 0x21, 0 + .dw 0x4513, 0xc415, 0x453f, 0xc415, 0x21, 0 + .dw 0x4541, 0xc415, 0x4541, 0xc415, 0x21, 0 + .dw 0x4543, 0xc415, 0x454f, 0xc415, 0x21, 0 + .dw 0x4551, 0xc415, 0x4551, 0xc415, 0x21, 0 + .dw 0x4553, 0xc415, 0x457f, 0xc415, 0x21, 0 + .dw 0x4581, 0xc415, 0x4581, 0xc415, 0x21, 0 + .dw 0x4583, 0xc415, 0x458f, 0xc415, 0x21, 0 + .dw 0x4591, 0xc415, 0x4591, 0xc415, 0x21, 0 + .dw 0x4593, 0xc415, 0x45bf, 0xc415, 0x21, 0 + .dw 0x45c1, 0xc415, 0x45c1, 0xc415, 0x21, 0 + .dw 0x45c3, 0xc415, 0x45cf, 0xc415, 0x21, 0 + .dw 0x45d1, 0xc415, 0x45d1, 0xc415, 0x21, 0 + .dw 0x45d3, 0xc415, 0x45ff, 0xc415, 0x21, 0 + .dw 0x4601, 0xc415, 0x4601, 0xc415, 0x21, 0 + .dw 0x4603, 0xc415, 0x460f, 0xc415, 0x21, 0 + .dw 0x4611, 0xc415, 0x4611, 0xc415, 0x21, 0 + .dw 0x4613, 0xc415, 0x463f, 0xc415, 0x21, 0 + .dw 0x4641, 0xc415, 0x4641, 0xc415, 0x21, 0 + .dw 0x4643, 0xc415, 0x464f, 0xc415, 0x21, 0 + .dw 0x4651, 0xc415, 0x4651, 0xc415, 0x21, 0 + .dw 0x4653, 0xc415, 0x467f, 0xc415, 0x21, 0 + .dw 0x4681, 0xc415, 0x4681, 0xc415, 0x21, 0 + .dw 0x4683, 0xc415, 0x468f, 0xc415, 0x21, 0 + .dw 0x4691, 0xc415, 0x4691, 0xc415, 0x21, 0 + .dw 0x4693, 0xc415, 0x46bf, 0xc415, 0x21, 0 + .dw 0x46c0, 0xc415, 0x46c0, 0xc415, 0x22, 0 + .dw 0x46c1, 0xc415, 0x46c1, 0xc415, 0x21, 0 + .dw 0x46c2, 0xc415, 0x46c2, 0xc415, 0x22, 0 + .dw 0x46c3, 0xc415, 0x46cf, 0xc415, 0x21, 0 + .dw 0x46d0, 0xc415, 0x46d0, 0xc415, 0x22, 0 + .dw 0x46d1, 0xc415, 0x46d1, 0xc415, 0x21, 0 + .dw 0x46d2, 0xc415, 0x46d2, 0xc415, 0x22, 0 + .dw 0x46d3, 0xc415, 0x46ff, 0xc415, 0x21, 0 + .dw 0x4701, 0xc415, 0x4701, 0xc415, 0x21, 0 + .dw 0x4703, 0xc415, 0x470f, 0xc415, 0x21, 0 + .dw 0x4711, 0xc415, 0x4711, 0xc415, 0x21, 0 + .dw 0x4713, 0xc415, 0x473f, 0xc415, 0x21, 0 + .dw 0x4741, 0xc415, 0x4741, 0xc415, 0x21, 0 + .dw 0x4743, 0xc415, 0x474f, 0xc415, 0x21, 0 + .dw 0x4751, 0xc415, 0x4751, 0xc415, 0x21, 0 + .dw 0x4753, 0xc415, 0x477f, 0xc415, 0x21, 0 + .dw 0x4781, 0xc415, 0x4781, 0xc415, 0x21, 0 + .dw 0x4783, 0xc415, 0x478f, 0xc415, 0x21, 0 + .dw 0x4791, 0xc415, 0x4791, 0xc415, 0x21, 0 + .dw 0x4793, 0xc415, 0x47bf, 0xc415, 0x21, 0 + .dw 0x47c1, 0xc415, 0x47c1, 0xc415, 0x21, 0 + .dw 0x47c3, 0xc415, 0x47cf, 0xc415, 0x21, 0 + .dw 0x47d1, 0xc415, 0x47d1, 0xc415, 0x21, 0 + .dw 0x47d3, 0xc415, 0x47ff, 0xc415, 0x21, 0 + .dw 0x4801, 0xc415, 0x4801, 0xc415, 0x21, 0 + .dw 0x4803, 0xc415, 0x480f, 0xc415, 0x21, 0 + .dw 0x4811, 0xc415, 0x4811, 0xc415, 0x21, 0 + .dw 0x4813, 0xc415, 0x483f, 0xc415, 0x21, 0 + .dw 0x4841, 0xc415, 0x4841, 0xc415, 0x21, 0 + .dw 0x4843, 0xc415, 0x484f, 0xc415, 0x21, 0 + .dw 0x4851, 0xc415, 0x4851, 0xc415, 0x21, 0 + .dw 0x4853, 0xc415, 0x487f, 0xc415, 0x21, 0 + .dw 0x4881, 0xc415, 0x4881, 0xc415, 0x21, 0 + .dw 0x4883, 0xc415, 0x488f, 0xc415, 0x21, 0 + .dw 0x4891, 0xc415, 0x4891, 0xc415, 0x21, 0 + .dw 0x4893, 0xc415, 0x48bf, 0xc415, 0x21, 0 + .dw 0x48c1, 0xc415, 0x48c1, 0xc415, 0x21, 0 + .dw 0x48c3, 0xc415, 0x48cf, 0xc415, 0x21, 0 + .dw 0x48d1, 0xc415, 0x48d1, 0xc415, 0x21, 0 + .dw 0x48d3, 0xc415, 0x48ff, 0xc415, 0x21, 0 + .dw 0x4900, 0xc415, 0x4900, 0xc415, 0x22, 0 + .dw 0x4901, 0xc415, 0x4901, 0xc415, 0x21, 0 + .dw 0x4902, 0xc415, 0x4902, 0xc415, 0x22, 0 + .dw 0x4903, 0xc415, 0x490f, 0xc415, 0x21, 0 + .dw 0x4910, 0xc415, 0x4910, 0xc415, 0x22, 0 + .dw 0x4911, 0xc415, 0x4911, 0xc415, 0x21, 0 + .dw 0x4912, 0xc415, 0x4912, 0xc415, 0x22, 0 + .dw 0x4913, 0xc415, 0x493f, 0xc415, 0x21, 0 + .dw 0x4941, 0xc415, 0x4941, 0xc415, 0x21, 0 + .dw 0x4943, 0xc415, 0x494f, 0xc415, 0x21, 0 + .dw 0x4951, 0xc415, 0x4951, 0xc415, 0x21, 0 + .dw 0x4953, 0xc415, 0x497f, 0xc415, 0x21, 0 + .dw 0x4981, 0xc415, 0x4981, 0xc415, 0x21, 0 + .dw 0x4983, 0xc415, 0x498f, 0xc415, 0x21, 0 + .dw 0x4991, 0xc415, 0x4991, 0xc415, 0x21, 0 + .dw 0x4993, 0xc415, 0x49bf, 0xc415, 0x21, 0 + .dw 0x49c1, 0xc415, 0x49c1, 0xc415, 0x21, 0 + .dw 0x49c3, 0xc415, 0x49cf, 0xc415, 0x21, 0 + .dw 0x49d1, 0xc415, 0x49d1, 0xc415, 0x21, 0 + .dw 0x49d3, 0xc415, 0x49ff, 0xc415, 0x21, 0 + .dw 0x4a01, 0xc415, 0x4a01, 0xc415, 0x21, 0 + .dw 0x4a03, 0xc415, 0x4a0f, 0xc415, 0x21, 0 + .dw 0x4a11, 0xc415, 0x4a11, 0xc415, 0x21, 0 + .dw 0x4a13, 0xc415, 0x4a3f, 0xc415, 0x21, 0 + .dw 0x4a41, 0xc415, 0x4a41, 0xc415, 0x21, 0 + .dw 0x4a43, 0xc415, 0x4a4f, 0xc415, 0x21, 0 + .dw 0x4a51, 0xc415, 0x4a51, 0xc415, 0x21, 0 + .dw 0x4a53, 0xc415, 0x4a7f, 0xc415, 0x21, 0 + .dw 0x4a81, 0xc415, 0x4a81, 0xc415, 0x21, 0 + .dw 0x4a83, 0xc415, 0x4a8f, 0xc415, 0x21, 0 + .dw 0x4a91, 0xc415, 0x4a91, 0xc415, 0x21, 0 + .dw 0x4a93, 0xc415, 0x4abf, 0xc415, 0x21, 0 + .dw 0x4ac1, 0xc415, 0x4ac1, 0xc415, 0x21, 0 + .dw 0x4ac3, 0xc415, 0x4acf, 0xc415, 0x21, 0 + .dw 0x4ad1, 0xc415, 0x4ad1, 0xc415, 0x21, 0 + .dw 0x4ad3, 0xc415, 0x4aff, 0xc415, 0x21, 0 + .dw 0x4b01, 0xc415, 0x4b01, 0xc415, 0x21, 0 + .dw 0x4b03, 0xc415, 0x4b0f, 0xc415, 0x21, 0 + .dw 0x4b11, 0xc415, 0x4b11, 0xc415, 0x21, 0 + .dw 0x4b13, 0xc415, 0x4b3f, 0xc415, 0x21, 0 + .dw 0x4b40, 0xc415, 0x4b40, 0xc415, 0x22, 0 + .dw 0x4b41, 0xc415, 0x4b41, 0xc415, 0x21, 0 + .dw 0x4b42, 0xc415, 0x4b42, 0xc415, 0x22, 0 + .dw 0x4b43, 0xc415, 0x4b4f, 0xc415, 0x21, 0 + .dw 0x4b50, 0xc415, 0x4b50, 0xc415, 0x22, 0 + .dw 0x4b51, 0xc415, 0x4b51, 0xc415, 0x21, 0 + .dw 0x4b52, 0xc415, 0x4b52, 0xc415, 0x22, 0 + .dw 0x4b53, 0xc415, 0x4b7f, 0xc415, 0x21, 0 + .dw 0x4b81, 0xc415, 0x4b81, 0xc415, 0x21, 0 + .dw 0x4b83, 0xc415, 0x4b8f, 0xc415, 0x21, 0 + .dw 0x4b91, 0xc415, 0x4b91, 0xc415, 0x21, 0 + .dw 0x4b93, 0xc415, 0x4bbf, 0xc415, 0x21, 0 + .dw 0x4bc1, 0xc415, 0x4bc1, 0xc415, 0x21, 0 + .dw 0x4bc3, 0xc415, 0x4bcf, 0xc415, 0x21, 0 + .dw 0x4bd1, 0xc415, 0x4bd1, 0xc415, 0x21, 0 + .dw 0x4bd3, 0xc415, 0x4bff, 0xc415, 0x21, 0 + .dw 0x4c01, 0xc415, 0x4c01, 0xc415, 0x21, 0 + .dw 0x4c03, 0xc415, 0x4c0f, 0xc415, 0x21, 0 + .dw 0x4c11, 0xc415, 0x4c11, 0xc415, 0x21, 0 + .dw 0x4c13, 0xc415, 0x4c3f, 0xc415, 0x21, 0 + .dw 0x4c41, 0xc415, 0x4c41, 0xc415, 0x21, 0 + .dw 0x4c43, 0xc415, 0x4c4f, 0xc415, 0x21, 0 + .dw 0x4c51, 0xc415, 0x4c51, 0xc415, 0x21, 0 + .dw 0x4c53, 0xc415, 0x4c7f, 0xc415, 0x21, 0 + .dw 0x4c81, 0xc415, 0x4c81, 0xc415, 0x21, 0 + .dw 0x4c83, 0xc415, 0x4c8f, 0xc415, 0x21, 0 + .dw 0x4c91, 0xc415, 0x4c91, 0xc415, 0x21, 0 + .dw 0x4c93, 0xc415, 0x4cbf, 0xc415, 0x21, 0 + .dw 0x4cc1, 0xc415, 0x4cc1, 0xc415, 0x21, 0 + .dw 0x4cc3, 0xc415, 0x4ccf, 0xc415, 0x21, 0 + .dw 0x4cd1, 0xc415, 0x4cd1, 0xc415, 0x21, 0 + .dw 0x4cd3, 0xc415, 0x4cff, 0xc415, 0x21, 0 + .dw 0x4d01, 0xc415, 0x4d01, 0xc415, 0x21, 0 + .dw 0x4d03, 0xc415, 0x4d0f, 0xc415, 0x21, 0 + .dw 0x4d11, 0xc415, 0x4d11, 0xc415, 0x21, 0 + .dw 0x4d13, 0xc415, 0x4d3f, 0xc415, 0x21, 0 + .dw 0x4d41, 0xc415, 0x4d41, 0xc415, 0x21, 0 + .dw 0x4d43, 0xc415, 0x4d4f, 0xc415, 0x21, 0 + .dw 0x4d51, 0xc415, 0x4d51, 0xc415, 0x21, 0 + .dw 0x4d53, 0xc415, 0x4d7f, 0xc415, 0x21, 0 + .dw 0x4d80, 0xc415, 0x4d80, 0xc415, 0x22, 0 + .dw 0x4d81, 0xc415, 0x4d81, 0xc415, 0x21, 0 + .dw 0x4d82, 0xc415, 0x4d82, 0xc415, 0x22, 0 + .dw 0x4d83, 0xc415, 0x4d8f, 0xc415, 0x21, 0 + .dw 0x4d90, 0xc415, 0x4d90, 0xc415, 0x22, 0 + .dw 0x4d91, 0xc415, 0x4d91, 0xc415, 0x21, 0 + .dw 0x4d92, 0xc415, 0x4d92, 0xc415, 0x22, 0 + .dw 0x4d93, 0xc415, 0x4dbf, 0xc415, 0x21, 0 + .dw 0x4dc1, 0xc415, 0x4dc1, 0xc415, 0x21, 0 + .dw 0x4dc3, 0xc415, 0x4dcf, 0xc415, 0x21, 0 + .dw 0x4dd1, 0xc415, 0x4dd1, 0xc415, 0x21, 0 + .dw 0x4dd3, 0xc415, 0x4dff, 0xc415, 0x21, 0 + .dw 0x4e01, 0xc415, 0x4e01, 0xc415, 0x21, 0 + .dw 0x4e03, 0xc415, 0x4e0f, 0xc415, 0x21, 0 + .dw 0x4e11, 0xc415, 0x4e11, 0xc415, 0x21, 0 + .dw 0x4e13, 0xc415, 0x4e3f, 0xc415, 0x21, 0 + .dw 0x4e41, 0xc415, 0x4e41, 0xc415, 0x21, 0 + .dw 0x4e43, 0xc415, 0x4e4f, 0xc415, 0x21, 0 + .dw 0x4e51, 0xc415, 0x4e51, 0xc415, 0x21, 0 + .dw 0x4e53, 0xc415, 0x4e7f, 0xc415, 0x21, 0 + .dw 0x4e81, 0xc415, 0x4e81, 0xc415, 0x21, 0 + .dw 0x4e83, 0xc415, 0x4e8f, 0xc415, 0x21, 0 + .dw 0x4e91, 0xc415, 0x4e91, 0xc415, 0x21, 0 + .dw 0x4e93, 0xc415, 0x4ebf, 0xc415, 0x21, 0 + .dw 0x4ec1, 0xc415, 0x4ec1, 0xc415, 0x21, 0 + .dw 0x4ec3, 0xc415, 0x4ecf, 0xc415, 0x21, 0 + .dw 0x4ed1, 0xc415, 0x4ed1, 0xc415, 0x21, 0 + .dw 0x4ed3, 0xc415, 0x4eff, 0xc415, 0x21, 0 + .dw 0x4f01, 0xc415, 0x4f01, 0xc415, 0x21, 0 + .dw 0x4f03, 0xc415, 0x4f0f, 0xc415, 0x21, 0 + .dw 0x4f11, 0xc415, 0x4f11, 0xc415, 0x21, 0 + .dw 0x4f13, 0xc415, 0x4f3f, 0xc415, 0x21, 0 + .dw 0x4f41, 0xc415, 0x4f41, 0xc415, 0x21, 0 + .dw 0x4f43, 0xc415, 0x4f4f, 0xc415, 0x21, 0 + .dw 0x4f51, 0xc415, 0x4f51, 0xc415, 0x21, 0 + .dw 0x4f53, 0xc415, 0x4f7f, 0xc415, 0x21, 0 + .dw 0x4f81, 0xc415, 0x4f81, 0xc415, 0x21, 0 + .dw 0x4f83, 0xc415, 0x4f8f, 0xc415, 0x21, 0 + .dw 0x4f91, 0xc415, 0x4f91, 0xc415, 0x21, 0 + .dw 0x4f93, 0xc415, 0x4fbf, 0xc415, 0x21, 0 + .dw 0x4fc0, 0xc415, 0x4fc0, 0xc415, 0x22, 0 + .dw 0x4fc1, 0xc415, 0x4fc1, 0xc415, 0x21, 0 + .dw 0x4fc2, 0xc415, 0x4fc2, 0xc415, 0x22, 0 + .dw 0x4fc3, 0xc415, 0x4fcf, 0xc415, 0x21, 0 + .dw 0x4fd0, 0xc415, 0x4fd0, 0xc415, 0x22, 0 + .dw 0x4fd1, 0xc415, 0x4fd1, 0xc415, 0x21, 0 + .dw 0x4fd2, 0xc415, 0x4fd2, 0xc415, 0x22, 0 + .dw 0x4fd3, 0xc415, 0x5fff, 0xc415, 0x21, 0 + .dw 0x6000, 0xc415, 0x6000, 0xc415, 0x22, 0 + .dw 0x6001, 0xc415, 0x6001, 0xc415, 0x21, 0 + .dw 0x6002, 0xc415, 0x6002, 0xc415, 0x22, 0 + .dw 0x6003, 0xc415, 0x600f, 0xc415, 0x21, 0 + .dw 0x6010, 0xc415, 0x6010, 0xc415, 0x22, 0 + .dw 0x6011, 0xc415, 0x6011, 0xc415, 0x21, 0 + .dw 0x6012, 0xc415, 0x6012, 0xc415, 0x22, 0 + .dw 0x6013, 0xc415, 0x603f, 0xc415, 0x21, 0 + .dw 0x6041, 0xc415, 0x6041, 0xc415, 0x21, 0 + .dw 0x6043, 0xc415, 0x604f, 0xc415, 0x21, 0 + .dw 0x6051, 0xc415, 0x6051, 0xc415, 0x21, 0 + .dw 0x6053, 0xc415, 0x607f, 0xc415, 0x21, 0 + .dw 0x6081, 0xc415, 0x6081, 0xc415, 0x21, 0 + .dw 0x6083, 0xc415, 0x608f, 0xc415, 0x21, 0 + .dw 0x6091, 0xc415, 0x6091, 0xc415, 0x21, 0 + .dw 0x6093, 0xc415, 0x60bf, 0xc415, 0x21, 0 + .dw 0x60c1, 0xc415, 0x60c1, 0xc415, 0x21, 0 + .dw 0x60c3, 0xc415, 0x60cf, 0xc415, 0x21, 0 + .dw 0x60d1, 0xc415, 0x60d1, 0xc415, 0x21, 0 + .dw 0x60d3, 0xc415, 0x60ff, 0xc415, 0x21, 0 + .dw 0x6101, 0xc415, 0x6101, 0xc415, 0x21, 0 + .dw 0x6103, 0xc415, 0x610f, 0xc415, 0x21, 0 + .dw 0x6111, 0xc415, 0x6111, 0xc415, 0x21, 0 + .dw 0x6113, 0xc415, 0x613f, 0xc415, 0x21, 0 + .dw 0x6141, 0xc415, 0x6141, 0xc415, 0x21, 0 + .dw 0x6143, 0xc415, 0x614f, 0xc415, 0x21, 0 + .dw 0x6151, 0xc415, 0x6151, 0xc415, 0x21, 0 + .dw 0x6153, 0xc415, 0x617f, 0xc415, 0x21, 0 + .dw 0x6181, 0xc415, 0x6181, 0xc415, 0x21, 0 + .dw 0x6183, 0xc415, 0x618f, 0xc415, 0x21, 0 + .dw 0x6191, 0xc415, 0x6191, 0xc415, 0x21, 0 + .dw 0x6193, 0xc415, 0x61bf, 0xc415, 0x21, 0 + .dw 0x61c1, 0xc415, 0x61c1, 0xc415, 0x21, 0 + .dw 0x61c3, 0xc415, 0x61cf, 0xc415, 0x21, 0 + .dw 0x61d1, 0xc415, 0x61d1, 0xc415, 0x21, 0 + .dw 0x61d3, 0xc415, 0x61ff, 0xc415, 0x21, 0 + .dw 0x6201, 0xc415, 0x6201, 0xc415, 0x21, 0 + .dw 0x6203, 0xc415, 0x620f, 0xc415, 0x21, 0 + .dw 0x6211, 0xc415, 0x6211, 0xc415, 0x21, 0 + .dw 0x6213, 0xc415, 0x623f, 0xc415, 0x21, 0 + .dw 0x6240, 0xc415, 0x6240, 0xc415, 0x22, 0 + .dw 0x6241, 0xc415, 0x6241, 0xc415, 0x21, 0 + .dw 0x6242, 0xc415, 0x6242, 0xc415, 0x22, 0 + .dw 0x6243, 0xc415, 0x624f, 0xc415, 0x21, 0 + .dw 0x6250, 0xc415, 0x6250, 0xc415, 0x22, 0 + .dw 0x6251, 0xc415, 0x6251, 0xc415, 0x21, 0 + .dw 0x6252, 0xc415, 0x6252, 0xc415, 0x22, 0 + .dw 0x6253, 0xc415, 0x627f, 0xc415, 0x21, 0 + .dw 0x6281, 0xc415, 0x6281, 0xc415, 0x21, 0 + .dw 0x6283, 0xc415, 0x628f, 0xc415, 0x21, 0 + .dw 0x6291, 0xc415, 0x6291, 0xc415, 0x21, 0 + .dw 0x6293, 0xc415, 0x62bf, 0xc415, 0x21, 0 + .dw 0x62c1, 0xc415, 0x62c1, 0xc415, 0x21, 0 + .dw 0x62c3, 0xc415, 0x62cf, 0xc415, 0x21, 0 + .dw 0x62d1, 0xc415, 0x62d1, 0xc415, 0x21, 0 + .dw 0x62d3, 0xc415, 0x62ff, 0xc415, 0x21, 0 + .dw 0x6301, 0xc415, 0x6301, 0xc415, 0x21, 0 + .dw 0x6303, 0xc415, 0x630f, 0xc415, 0x21, 0 + .dw 0x6311, 0xc415, 0x6311, 0xc415, 0x21, 0 + .dw 0x6313, 0xc415, 0x633f, 0xc415, 0x21, 0 + .dw 0x6341, 0xc415, 0x6341, 0xc415, 0x21, 0 + .dw 0x6343, 0xc415, 0x634f, 0xc415, 0x21, 0 + .dw 0x6351, 0xc415, 0x6351, 0xc415, 0x21, 0 + .dw 0x6353, 0xc415, 0x637f, 0xc415, 0x21, 0 + .dw 0x6381, 0xc415, 0x6381, 0xc415, 0x21, 0 + .dw 0x6383, 0xc415, 0x638f, 0xc415, 0x21, 0 + .dw 0x6391, 0xc415, 0x6391, 0xc415, 0x21, 0 + .dw 0x6393, 0xc415, 0x63bf, 0xc415, 0x21, 0 + .dw 0x63c1, 0xc415, 0x63c1, 0xc415, 0x21, 0 + .dw 0x63c3, 0xc415, 0x63cf, 0xc415, 0x21, 0 + .dw 0x63d1, 0xc415, 0x63d1, 0xc415, 0x21, 0 + .dw 0x63d3, 0xc415, 0x63ff, 0xc415, 0x21, 0 + .dw 0x6401, 0xc415, 0x6401, 0xc415, 0x21, 0 + .dw 0x6403, 0xc415, 0x640f, 0xc415, 0x21, 0 + .dw 0x6411, 0xc415, 0x6411, 0xc415, 0x21, 0 + .dw 0x6413, 0xc415, 0x643f, 0xc415, 0x21, 0 + .dw 0x6441, 0xc415, 0x6441, 0xc415, 0x21, 0 + .dw 0x6443, 0xc415, 0x644f, 0xc415, 0x21, 0 + .dw 0x6451, 0xc415, 0x6451, 0xc415, 0x21, 0 + .dw 0x6453, 0xc415, 0x647f, 0xc415, 0x21, 0 + .dw 0x6480, 0xc415, 0x6480, 0xc415, 0x22, 0 + .dw 0x6481, 0xc415, 0x6481, 0xc415, 0x21, 0 + .dw 0x6482, 0xc415, 0x6482, 0xc415, 0x22, 0 + .dw 0x6483, 0xc415, 0x648f, 0xc415, 0x21, 0 + .dw 0x6490, 0xc415, 0x6490, 0xc415, 0x22, 0 + .dw 0x6491, 0xc415, 0x6491, 0xc415, 0x21, 0 + .dw 0x6492, 0xc415, 0x6492, 0xc415, 0x22, 0 + .dw 0x6493, 0xc415, 0x64bf, 0xc415, 0x21, 0 + .dw 0x64c1, 0xc415, 0x64c1, 0xc415, 0x21, 0 + .dw 0x64c3, 0xc415, 0x64cf, 0xc415, 0x21, 0 + .dw 0x64d1, 0xc415, 0x64d1, 0xc415, 0x21, 0 + .dw 0x64d3, 0xc415, 0x64ff, 0xc415, 0x21, 0 + .dw 0x6501, 0xc415, 0x6501, 0xc415, 0x21, 0 + .dw 0x6503, 0xc415, 0x650f, 0xc415, 0x21, 0 + .dw 0x6511, 0xc415, 0x6511, 0xc415, 0x21, 0 + .dw 0x6513, 0xc415, 0x653f, 0xc415, 0x21, 0 + .dw 0x6541, 0xc415, 0x6541, 0xc415, 0x21, 0 + .dw 0x6543, 0xc415, 0x654f, 0xc415, 0x21, 0 + .dw 0x6551, 0xc415, 0x6551, 0xc415, 0x21, 0 + .dw 0x6553, 0xc415, 0x657f, 0xc415, 0x21, 0 + .dw 0x6581, 0xc415, 0x6581, 0xc415, 0x21, 0 + .dw 0x6583, 0xc415, 0x658f, 0xc415, 0x21, 0 + .dw 0x6591, 0xc415, 0x6591, 0xc415, 0x21, 0 + .dw 0x6593, 0xc415, 0x65bf, 0xc415, 0x21, 0 + .dw 0x65c1, 0xc415, 0x65c1, 0xc415, 0x21, 0 + .dw 0x65c3, 0xc415, 0x65cf, 0xc415, 0x21, 0 + .dw 0x65d1, 0xc415, 0x65d1, 0xc415, 0x21, 0 + .dw 0x65d3, 0xc415, 0x65ff, 0xc415, 0x21, 0 + .dw 0x6601, 0xc415, 0x6601, 0xc415, 0x21, 0 + .dw 0x6603, 0xc415, 0x660f, 0xc415, 0x21, 0 + .dw 0x6611, 0xc415, 0x6611, 0xc415, 0x21, 0 + .dw 0x6613, 0xc415, 0x663f, 0xc415, 0x21, 0 + .dw 0x6641, 0xc415, 0x6641, 0xc415, 0x21, 0 + .dw 0x6643, 0xc415, 0x664f, 0xc415, 0x21, 0 + .dw 0x6651, 0xc415, 0x6651, 0xc415, 0x21, 0 + .dw 0x6653, 0xc415, 0x667f, 0xc415, 0x21, 0 + .dw 0x6681, 0xc415, 0x6681, 0xc415, 0x21, 0 + .dw 0x6683, 0xc415, 0x668f, 0xc415, 0x21, 0 + .dw 0x6691, 0xc415, 0x6691, 0xc415, 0x21, 0 + .dw 0x6693, 0xc415, 0x66bf, 0xc415, 0x21, 0 + .dw 0x66c0, 0xc415, 0x66c0, 0xc415, 0x22, 0 + .dw 0x66c1, 0xc415, 0x66c1, 0xc415, 0x21, 0 + .dw 0x66c2, 0xc415, 0x66c2, 0xc415, 0x22, 0 + .dw 0x66c3, 0xc415, 0x66cf, 0xc415, 0x21, 0 + .dw 0x66d0, 0xc415, 0x66d0, 0xc415, 0x22, 0 + .dw 0x66d1, 0xc415, 0x66d1, 0xc415, 0x21, 0 + .dw 0x66d2, 0xc415, 0x66d2, 0xc415, 0x22, 0 + .dw 0x66d3, 0xc415, 0x66ff, 0xc415, 0x21, 0 + .dw 0x6701, 0xc415, 0x6701, 0xc415, 0x21, 0 + .dw 0x6703, 0xc415, 0x670f, 0xc415, 0x21, 0 + .dw 0x6711, 0xc415, 0x6711, 0xc415, 0x21, 0 + .dw 0x6713, 0xc415, 0x673f, 0xc415, 0x21, 0 + .dw 0x6741, 0xc415, 0x6741, 0xc415, 0x21, 0 + .dw 0x6743, 0xc415, 0x674f, 0xc415, 0x21, 0 + .dw 0x6751, 0xc415, 0x6751, 0xc415, 0x21, 0 + .dw 0x6753, 0xc415, 0x677f, 0xc415, 0x21, 0 + .dw 0x6781, 0xc415, 0x6781, 0xc415, 0x21, 0 + .dw 0x6783, 0xc415, 0x678f, 0xc415, 0x21, 0 + .dw 0x6791, 0xc415, 0x6791, 0xc415, 0x21, 0 + .dw 0x6793, 0xc415, 0x67bf, 0xc415, 0x21, 0 + .dw 0x67c1, 0xc415, 0x67c1, 0xc415, 0x21, 0 + .dw 0x67c3, 0xc415, 0x67cf, 0xc415, 0x21, 0 + .dw 0x67d1, 0xc415, 0x67d1, 0xc415, 0x21, 0 + .dw 0x67d3, 0xc415, 0x67ff, 0xc415, 0x21, 0 + .dw 0x6801, 0xc415, 0x6801, 0xc415, 0x21, 0 + .dw 0x6803, 0xc415, 0x680f, 0xc415, 0x21, 0 + .dw 0x6811, 0xc415, 0x6811, 0xc415, 0x21, 0 + .dw 0x6813, 0xc415, 0x683f, 0xc415, 0x21, 0 + .dw 0x6841, 0xc415, 0x6841, 0xc415, 0x21, 0 + .dw 0x6843, 0xc415, 0x684f, 0xc415, 0x21, 0 + .dw 0x6851, 0xc415, 0x6851, 0xc415, 0x21, 0 + .dw 0x6853, 0xc415, 0x687f, 0xc415, 0x21, 0 + .dw 0x6881, 0xc415, 0x6881, 0xc415, 0x21, 0 + .dw 0x6883, 0xc415, 0x688f, 0xc415, 0x21, 0 + .dw 0x6891, 0xc415, 0x6891, 0xc415, 0x21, 0 + .dw 0x6893, 0xc415, 0x68bf, 0xc415, 0x21, 0 + .dw 0x68c1, 0xc415, 0x68c1, 0xc415, 0x21, 0 + .dw 0x68c3, 0xc415, 0x68cf, 0xc415, 0x21, 0 + .dw 0x68d1, 0xc415, 0x68d1, 0xc415, 0x21, 0 + .dw 0x68d3, 0xc415, 0x68ff, 0xc415, 0x21, 0 + .dw 0x6900, 0xc415, 0x6900, 0xc415, 0x22, 0 + .dw 0x6901, 0xc415, 0x6901, 0xc415, 0x21, 0 + .dw 0x6902, 0xc415, 0x6902, 0xc415, 0x22, 0 + .dw 0x6903, 0xc415, 0x690f, 0xc415, 0x21, 0 + .dw 0x6910, 0xc415, 0x6910, 0xc415, 0x22, 0 + .dw 0x6911, 0xc415, 0x6911, 0xc415, 0x21, 0 + .dw 0x6912, 0xc415, 0x6912, 0xc415, 0x22, 0 + .dw 0x6913, 0xc415, 0x693f, 0xc415, 0x21, 0 + .dw 0x6941, 0xc415, 0x6941, 0xc415, 0x21, 0 + .dw 0x6943, 0xc415, 0x694f, 0xc415, 0x21, 0 + .dw 0x6951, 0xc415, 0x6951, 0xc415, 0x21, 0 + .dw 0x6953, 0xc415, 0x697f, 0xc415, 0x21, 0 + .dw 0x6981, 0xc415, 0x6981, 0xc415, 0x21, 0 + .dw 0x6983, 0xc415, 0x698f, 0xc415, 0x21, 0 + .dw 0x6991, 0xc415, 0x6991, 0xc415, 0x21, 0 + .dw 0x6993, 0xc415, 0x69bf, 0xc415, 0x21, 0 + .dw 0x69c1, 0xc415, 0x69c1, 0xc415, 0x21, 0 + .dw 0x69c3, 0xc415, 0x69cf, 0xc415, 0x21, 0 + .dw 0x69d1, 0xc415, 0x69d1, 0xc415, 0x21, 0 + .dw 0x69d3, 0xc415, 0x69ff, 0xc415, 0x21, 0 + .dw 0x6a01, 0xc415, 0x6a01, 0xc415, 0x21, 0 + .dw 0x6a03, 0xc415, 0x6a0f, 0xc415, 0x21, 0 + .dw 0x6a11, 0xc415, 0x6a11, 0xc415, 0x21, 0 + .dw 0x6a13, 0xc415, 0x6a3f, 0xc415, 0x21, 0 + .dw 0x6a41, 0xc415, 0x6a41, 0xc415, 0x21, 0 + .dw 0x6a43, 0xc415, 0x6a4f, 0xc415, 0x21, 0 + .dw 0x6a51, 0xc415, 0x6a51, 0xc415, 0x21, 0 + .dw 0x6a53, 0xc415, 0x6a7f, 0xc415, 0x21, 0 + .dw 0x6a81, 0xc415, 0x6a81, 0xc415, 0x21, 0 + .dw 0x6a83, 0xc415, 0x6a8f, 0xc415, 0x21, 0 + .dw 0x6a91, 0xc415, 0x6a91, 0xc415, 0x21, 0 + .dw 0x6a93, 0xc415, 0x6abf, 0xc415, 0x21, 0 + .dw 0x6ac1, 0xc415, 0x6ac1, 0xc415, 0x21, 0 + .dw 0x6ac3, 0xc415, 0x6acf, 0xc415, 0x21, 0 + .dw 0x6ad1, 0xc415, 0x6ad1, 0xc415, 0x21, 0 + .dw 0x6ad3, 0xc415, 0x6aff, 0xc415, 0x21, 0 + .dw 0x6b01, 0xc415, 0x6b01, 0xc415, 0x21, 0 + .dw 0x6b03, 0xc415, 0x6b0f, 0xc415, 0x21, 0 + .dw 0x6b11, 0xc415, 0x6b11, 0xc415, 0x21, 0 + .dw 0x6b13, 0xc415, 0x6b3f, 0xc415, 0x21, 0 + .dw 0x6b40, 0xc415, 0x6b40, 0xc415, 0x22, 0 + .dw 0x6b41, 0xc415, 0x6b41, 0xc415, 0x21, 0 + .dw 0x6b42, 0xc415, 0x6b42, 0xc415, 0x22, 0 + .dw 0x6b43, 0xc415, 0x6b4f, 0xc415, 0x21, 0 + .dw 0x6b50, 0xc415, 0x6b50, 0xc415, 0x22, 0 + .dw 0x6b51, 0xc415, 0x6b51, 0xc415, 0x21, 0 + .dw 0x6b52, 0xc415, 0x6b52, 0xc415, 0x22, 0 + .dw 0x6b53, 0xc415, 0x6b7f, 0xc415, 0x21, 0 + .dw 0x6b81, 0xc415, 0x6b81, 0xc415, 0x21, 0 + .dw 0x6b83, 0xc415, 0x6b8f, 0xc415, 0x21, 0 + .dw 0x6b91, 0xc415, 0x6b91, 0xc415, 0x21, 0 + .dw 0x6b93, 0xc415, 0x6bbf, 0xc415, 0x21, 0 + .dw 0x6bc1, 0xc415, 0x6bc1, 0xc415, 0x21, 0 + .dw 0x6bc3, 0xc415, 0x6bcf, 0xc415, 0x21, 0 + .dw 0x6bd1, 0xc415, 0x6bd1, 0xc415, 0x21, 0 + .dw 0x6bd3, 0xc415, 0x6bff, 0xc415, 0x21, 0 + .dw 0x6c01, 0xc415, 0x6c01, 0xc415, 0x21, 0 + .dw 0x6c03, 0xc415, 0x6c0f, 0xc415, 0x21, 0 + .dw 0x6c11, 0xc415, 0x6c11, 0xc415, 0x21, 0 + .dw 0x6c13, 0xc415, 0x6c3f, 0xc415, 0x21, 0 + .dw 0x6c41, 0xc415, 0x6c41, 0xc415, 0x21, 0 + .dw 0x6c43, 0xc415, 0x6c4f, 0xc415, 0x21, 0 + .dw 0x6c51, 0xc415, 0x6c51, 0xc415, 0x21, 0 + .dw 0x6c53, 0xc415, 0x6c7f, 0xc415, 0x21, 0 + .dw 0x6c81, 0xc415, 0x6c81, 0xc415, 0x21, 0 + .dw 0x6c83, 0xc415, 0x6c8f, 0xc415, 0x21, 0 + .dw 0x6c91, 0xc415, 0x6c91, 0xc415, 0x21, 0 + .dw 0x6c93, 0xc415, 0x6cbf, 0xc415, 0x21, 0 + .dw 0x6cc1, 0xc415, 0x6cc1, 0xc415, 0x21, 0 + .dw 0x6cc3, 0xc415, 0x6ccf, 0xc415, 0x21, 0 + .dw 0x6cd1, 0xc415, 0x6cd1, 0xc415, 0x21, 0 + .dw 0x6cd3, 0xc415, 0x6cff, 0xc415, 0x21, 0 + .dw 0x6d01, 0xc415, 0x6d01, 0xc415, 0x21, 0 + .dw 0x6d03, 0xc415, 0x6d0f, 0xc415, 0x21, 0 + .dw 0x6d11, 0xc415, 0x6d11, 0xc415, 0x21, 0 + .dw 0x6d13, 0xc415, 0x6d3f, 0xc415, 0x21, 0 + .dw 0x6d41, 0xc415, 0x6d41, 0xc415, 0x21, 0 + .dw 0x6d43, 0xc415, 0x6d4f, 0xc415, 0x21, 0 + .dw 0x6d51, 0xc415, 0x6d51, 0xc415, 0x21, 0 + .dw 0x6d53, 0xc415, 0x6d7f, 0xc415, 0x21, 0 + .dw 0x6d80, 0xc415, 0x6d80, 0xc415, 0x22, 0 + .dw 0x6d81, 0xc415, 0x6d81, 0xc415, 0x21, 0 + .dw 0x6d82, 0xc415, 0x6d82, 0xc415, 0x22, 0 + .dw 0x6d83, 0xc415, 0x6d8f, 0xc415, 0x21, 0 + .dw 0x6d90, 0xc415, 0x6d90, 0xc415, 0x22, 0 + .dw 0x6d91, 0xc415, 0x6d91, 0xc415, 0x21, 0 + .dw 0x6d92, 0xc415, 0x6d92, 0xc415, 0x22, 0 + .dw 0x6d93, 0xc415, 0x6dbf, 0xc415, 0x21, 0 + .dw 0x6dc1, 0xc415, 0x6dc1, 0xc415, 0x21, 0 + .dw 0x6dc3, 0xc415, 0x6dcf, 0xc415, 0x21, 0 + .dw 0x6dd1, 0xc415, 0x6dd1, 0xc415, 0x21, 0 + .dw 0x6dd3, 0xc415, 0x6dff, 0xc415, 0x21, 0 + .dw 0x6e01, 0xc415, 0x6e01, 0xc415, 0x21, 0 + .dw 0x6e03, 0xc415, 0x6e0f, 0xc415, 0x21, 0 + .dw 0x6e11, 0xc415, 0x6e11, 0xc415, 0x21, 0 + .dw 0x6e13, 0xc415, 0x6e3f, 0xc415, 0x21, 0 + .dw 0x6e41, 0xc415, 0x6e41, 0xc415, 0x21, 0 + .dw 0x6e43, 0xc415, 0x6e4f, 0xc415, 0x21, 0 + .dw 0x6e51, 0xc415, 0x6e51, 0xc415, 0x21, 0 + .dw 0x6e53, 0xc415, 0x6e7f, 0xc415, 0x21, 0 + .dw 0x6e81, 0xc415, 0x6e81, 0xc415, 0x21, 0 + .dw 0x6e83, 0xc415, 0x6e8f, 0xc415, 0x21, 0 + .dw 0x6e91, 0xc415, 0x6e91, 0xc415, 0x21, 0 + .dw 0x6e93, 0xc415, 0x6ebf, 0xc415, 0x21, 0 + .dw 0x6ec1, 0xc415, 0x6ec1, 0xc415, 0x21, 0 + .dw 0x6ec3, 0xc415, 0x6ecf, 0xc415, 0x21, 0 + .dw 0x6ed1, 0xc415, 0x6ed1, 0xc415, 0x21, 0 + .dw 0x6ed3, 0xc415, 0x6eff, 0xc415, 0x21, 0 + .dw 0x6f01, 0xc415, 0x6f01, 0xc415, 0x21, 0 + .dw 0x6f03, 0xc415, 0x6f0f, 0xc415, 0x21, 0 + .dw 0x6f11, 0xc415, 0x6f11, 0xc415, 0x21, 0 + .dw 0x6f13, 0xc415, 0x6f3f, 0xc415, 0x21, 0 + .dw 0x6f41, 0xc415, 0x6f41, 0xc415, 0x21, 0 + .dw 0x6f43, 0xc415, 0x6f4f, 0xc415, 0x21, 0 + .dw 0x6f51, 0xc415, 0x6f51, 0xc415, 0x21, 0 + .dw 0x6f53, 0xc415, 0x6f7f, 0xc415, 0x21, 0 + .dw 0x6f81, 0xc415, 0x6f81, 0xc415, 0x21, 0 + .dw 0x6f83, 0xc415, 0x6f8f, 0xc415, 0x21, 0 + .dw 0x6f91, 0xc415, 0x6f91, 0xc415, 0x21, 0 + .dw 0x6f93, 0xc415, 0x6fbf, 0xc415, 0x21, 0 + .dw 0x6fc0, 0xc415, 0x6fc0, 0xc415, 0x22, 0 + .dw 0x6fc1, 0xc415, 0x6fc1, 0xc415, 0x21, 0 + .dw 0x6fc2, 0xc415, 0x6fc2, 0xc415, 0x22, 0 + .dw 0x6fc3, 0xc415, 0x6fcf, 0xc415, 0x21, 0 + .dw 0x6fd0, 0xc415, 0x6fd0, 0xc415, 0x22, 0 + .dw 0x6fd1, 0xc415, 0x6fd1, 0xc415, 0x21, 0 + .dw 0x6fd2, 0xc415, 0x6fd2, 0xc415, 0x22, 0 + .dw 0x6fd3, 0xc415, 0xffff, 0xc415, 0x21, 0 + .dw 0x0001, 0xc416, 0x0001, 0xc416, 0x21, 0 + .dw 0x0003, 0xc416, 0x000f, 0xc416, 0x21, 0 + .dw 0x0011, 0xc416, 0x0011, 0xc416, 0x21, 0 + .dw 0x0013, 0xc416, 0x003f, 0xc416, 0x21, 0 + .dw 0x0041, 0xc416, 0x0041, 0xc416, 0x21, 0 + .dw 0x0043, 0xc416, 0x004f, 0xc416, 0x21, 0 + .dw 0x0051, 0xc416, 0x0051, 0xc416, 0x21, 0 + .dw 0x0053, 0xc416, 0x007f, 0xc416, 0x21, 0 + .dw 0x0081, 0xc416, 0x0081, 0xc416, 0x21, 0 + .dw 0x0083, 0xc416, 0x008f, 0xc416, 0x21, 0 + .dw 0x0091, 0xc416, 0x0091, 0xc416, 0x21, 0 + .dw 0x0093, 0xc416, 0x00bf, 0xc416, 0x21, 0 + .dw 0x00c1, 0xc416, 0x00c1, 0xc416, 0x21, 0 + .dw 0x00c3, 0xc416, 0x00cf, 0xc416, 0x21, 0 + .dw 0x00d1, 0xc416, 0x00d1, 0xc416, 0x21, 0 + .dw 0x00d3, 0xc416, 0x00ff, 0xc416, 0x21, 0 + .dw 0x0101, 0xc416, 0x0101, 0xc416, 0x21, 0 + .dw 0x0103, 0xc416, 0x010f, 0xc416, 0x21, 0 + .dw 0x0111, 0xc416, 0x0111, 0xc416, 0x21, 0 + .dw 0x0113, 0xc416, 0x013f, 0xc416, 0x21, 0 + .dw 0x0141, 0xc416, 0x0141, 0xc416, 0x21, 0 + .dw 0x0143, 0xc416, 0x014f, 0xc416, 0x21, 0 + .dw 0x0151, 0xc416, 0x0151, 0xc416, 0x21, 0 + .dw 0x0153, 0xc416, 0x017f, 0xc416, 0x21, 0 + .dw 0x0181, 0xc416, 0x0181, 0xc416, 0x21, 0 + .dw 0x0183, 0xc416, 0x018f, 0xc416, 0x21, 0 + .dw 0x0191, 0xc416, 0x0191, 0xc416, 0x21, 0 + .dw 0x0193, 0xc416, 0x01bf, 0xc416, 0x21, 0 + .dw 0x01c1, 0xc416, 0x01c1, 0xc416, 0x21, 0 + .dw 0x01c3, 0xc416, 0x01cf, 0xc416, 0x21, 0 + .dw 0x01d1, 0xc416, 0x01d1, 0xc416, 0x21, 0 + .dw 0x01d3, 0xc416, 0x01ff, 0xc416, 0x21, 0 + .dw 0x0201, 0xc416, 0x0201, 0xc416, 0x21, 0 + .dw 0x0203, 0xc416, 0x020f, 0xc416, 0x21, 0 + .dw 0x0211, 0xc416, 0x0211, 0xc416, 0x21, 0 + .dw 0x0213, 0xc416, 0x023f, 0xc416, 0x21, 0 + .dw 0x0241, 0xc416, 0x0241, 0xc416, 0x21, 0 + .dw 0x0243, 0xc416, 0x024f, 0xc416, 0x21, 0 + .dw 0x0251, 0xc416, 0x0251, 0xc416, 0x21, 0 + .dw 0x0253, 0xc416, 0x027f, 0xc416, 0x21, 0 + .dw 0x0281, 0xc416, 0x0281, 0xc416, 0x21, 0 + .dw 0x0283, 0xc416, 0x028f, 0xc416, 0x21, 0 + .dw 0x0291, 0xc416, 0x0291, 0xc416, 0x21, 0 + .dw 0x0293, 0xc416, 0x02bf, 0xc416, 0x21, 0 + .dw 0x02c1, 0xc416, 0x02c1, 0xc416, 0x21, 0 + .dw 0x02c3, 0xc416, 0x02cf, 0xc416, 0x21, 0 + .dw 0x02d1, 0xc416, 0x02d1, 0xc416, 0x21, 0 + .dw 0x02d3, 0xc416, 0x02ff, 0xc416, 0x21, 0 + .dw 0x0301, 0xc416, 0x0301, 0xc416, 0x21, 0 + .dw 0x0303, 0xc416, 0x030f, 0xc416, 0x21, 0 + .dw 0x0311, 0xc416, 0x0311, 0xc416, 0x21, 0 + .dw 0x0313, 0xc416, 0x033f, 0xc416, 0x21, 0 + .dw 0x0341, 0xc416, 0x0341, 0xc416, 0x21, 0 + .dw 0x0343, 0xc416, 0x034f, 0xc416, 0x21, 0 + .dw 0x0351, 0xc416, 0x0351, 0xc416, 0x21, 0 + .dw 0x0353, 0xc416, 0x037f, 0xc416, 0x21, 0 + .dw 0x0381, 0xc416, 0x0381, 0xc416, 0x21, 0 + .dw 0x0383, 0xc416, 0x038f, 0xc416, 0x21, 0 + .dw 0x0391, 0xc416, 0x0391, 0xc416, 0x21, 0 + .dw 0x0393, 0xc416, 0x03bf, 0xc416, 0x21, 0 + .dw 0x03c1, 0xc416, 0x03c1, 0xc416, 0x21, 0 + .dw 0x03c3, 0xc416, 0x03cf, 0xc416, 0x21, 0 + .dw 0x03d1, 0xc416, 0x03d1, 0xc416, 0x21, 0 + .dw 0x03d3, 0xc416, 0x03ff, 0xc416, 0x21, 0 + .dw 0x0401, 0xc416, 0x0401, 0xc416, 0x21, 0 + .dw 0x0403, 0xc416, 0x040f, 0xc416, 0x21, 0 + .dw 0x0411, 0xc416, 0x0411, 0xc416, 0x21, 0 + .dw 0x0413, 0xc416, 0x043f, 0xc416, 0x21, 0 + .dw 0x0441, 0xc416, 0x0441, 0xc416, 0x21, 0 + .dw 0x0443, 0xc416, 0x044f, 0xc416, 0x21, 0 + .dw 0x0451, 0xc416, 0x0451, 0xc416, 0x21, 0 + .dw 0x0453, 0xc416, 0x047f, 0xc416, 0x21, 0 + .dw 0x0481, 0xc416, 0x0481, 0xc416, 0x21, 0 + .dw 0x0483, 0xc416, 0x048f, 0xc416, 0x21, 0 + .dw 0x0491, 0xc416, 0x0491, 0xc416, 0x21, 0 + .dw 0x0493, 0xc416, 0x04bf, 0xc416, 0x21, 0 + .dw 0x04c1, 0xc416, 0x04c1, 0xc416, 0x21, 0 + .dw 0x04c3, 0xc416, 0x04cf, 0xc416, 0x21, 0 + .dw 0x04d1, 0xc416, 0x04d1, 0xc416, 0x21, 0 + .dw 0x04d3, 0xc416, 0x04ff, 0xc416, 0x21, 0 + .dw 0x0501, 0xc416, 0x0501, 0xc416, 0x21, 0 + .dw 0x0503, 0xc416, 0x050f, 0xc416, 0x21, 0 + .dw 0x0511, 0xc416, 0x0511, 0xc416, 0x21, 0 + .dw 0x0513, 0xc416, 0x053f, 0xc416, 0x21, 0 + .dw 0x0541, 0xc416, 0x0541, 0xc416, 0x21, 0 + .dw 0x0543, 0xc416, 0x054f, 0xc416, 0x21, 0 + .dw 0x0551, 0xc416, 0x0551, 0xc416, 0x21, 0 + .dw 0x0553, 0xc416, 0x057f, 0xc416, 0x21, 0 + .dw 0x0581, 0xc416, 0x0581, 0xc416, 0x21, 0 + .dw 0x0583, 0xc416, 0x058f, 0xc416, 0x21, 0 + .dw 0x0591, 0xc416, 0x0591, 0xc416, 0x21, 0 + .dw 0x0593, 0xc416, 0x05bf, 0xc416, 0x21, 0 + .dw 0x05c1, 0xc416, 0x05c1, 0xc416, 0x21, 0 + .dw 0x05c3, 0xc416, 0x05cf, 0xc416, 0x21, 0 + .dw 0x05d1, 0xc416, 0x05d1, 0xc416, 0x21, 0 + .dw 0x05d3, 0xc416, 0x05ff, 0xc416, 0x21, 0 + .dw 0x0601, 0xc416, 0x0601, 0xc416, 0x21, 0 + .dw 0x0603, 0xc416, 0x060f, 0xc416, 0x21, 0 + .dw 0x0611, 0xc416, 0x0611, 0xc416, 0x21, 0 + .dw 0x0613, 0xc416, 0x063f, 0xc416, 0x21, 0 + .dw 0x0641, 0xc416, 0x0641, 0xc416, 0x21, 0 + .dw 0x0643, 0xc416, 0x064f, 0xc416, 0x21, 0 + .dw 0x0651, 0xc416, 0x0651, 0xc416, 0x21, 0 + .dw 0x0653, 0xc416, 0x067f, 0xc416, 0x21, 0 + .dw 0x0681, 0xc416, 0x0681, 0xc416, 0x21, 0 + .dw 0x0683, 0xc416, 0x068f, 0xc416, 0x21, 0 + .dw 0x0691, 0xc416, 0x0691, 0xc416, 0x21, 0 + .dw 0x0693, 0xc416, 0x06bf, 0xc416, 0x21, 0 + .dw 0x06c1, 0xc416, 0x06c1, 0xc416, 0x21, 0 + .dw 0x06c3, 0xc416, 0x06cf, 0xc416, 0x21, 0 + .dw 0x06d1, 0xc416, 0x06d1, 0xc416, 0x21, 0 + .dw 0x06d3, 0xc416, 0x06ff, 0xc416, 0x21, 0 + .dw 0x0701, 0xc416, 0x0701, 0xc416, 0x21, 0 + .dw 0x0703, 0xc416, 0x070f, 0xc416, 0x21, 0 + .dw 0x0711, 0xc416, 0x0711, 0xc416, 0x21, 0 + .dw 0x0713, 0xc416, 0x073f, 0xc416, 0x21, 0 + .dw 0x0741, 0xc416, 0x0741, 0xc416, 0x21, 0 + .dw 0x0743, 0xc416, 0x074f, 0xc416, 0x21, 0 + .dw 0x0751, 0xc416, 0x0751, 0xc416, 0x21, 0 + .dw 0x0753, 0xc416, 0x077f, 0xc416, 0x21, 0 + .dw 0x0781, 0xc416, 0x0781, 0xc416, 0x21, 0 + .dw 0x0783, 0xc416, 0x078f, 0xc416, 0x21, 0 + .dw 0x0791, 0xc416, 0x0791, 0xc416, 0x21, 0 + .dw 0x0793, 0xc416, 0x07bf, 0xc416, 0x21, 0 + .dw 0x07c1, 0xc416, 0x07c1, 0xc416, 0x21, 0 + .dw 0x07c3, 0xc416, 0x07cf, 0xc416, 0x21, 0 + .dw 0x07d1, 0xc416, 0x07d1, 0xc416, 0x21, 0 + .dw 0x07d3, 0xc416, 0x07ff, 0xc416, 0x21, 0 + .dw 0x0801, 0xc416, 0x0801, 0xc416, 0x21, 0 + .dw 0x0803, 0xc416, 0x080f, 0xc416, 0x21, 0 + .dw 0x0811, 0xc416, 0x0811, 0xc416, 0x21, 0 + .dw 0x0813, 0xc416, 0x083f, 0xc416, 0x21, 0 + .dw 0x0841, 0xc416, 0x0841, 0xc416, 0x21, 0 + .dw 0x0843, 0xc416, 0x084f, 0xc416, 0x21, 0 + .dw 0x0851, 0xc416, 0x0851, 0xc416, 0x21, 0 + .dw 0x0853, 0xc416, 0x087f, 0xc416, 0x21, 0 + .dw 0x0881, 0xc416, 0x0881, 0xc416, 0x21, 0 + .dw 0x0883, 0xc416, 0x088f, 0xc416, 0x21, 0 + .dw 0x0891, 0xc416, 0x0891, 0xc416, 0x21, 0 + .dw 0x0893, 0xc416, 0x08bf, 0xc416, 0x21, 0 + .dw 0x08c1, 0xc416, 0x08c1, 0xc416, 0x21, 0 + .dw 0x08c3, 0xc416, 0x08cf, 0xc416, 0x21, 0 + .dw 0x08d1, 0xc416, 0x08d1, 0xc416, 0x21, 0 + .dw 0x08d3, 0xc416, 0x08ff, 0xc416, 0x21, 0 + .dw 0x0901, 0xc416, 0x0901, 0xc416, 0x21, 0 + .dw 0x0903, 0xc416, 0x090f, 0xc416, 0x21, 0 + .dw 0x0911, 0xc416, 0x0911, 0xc416, 0x21, 0 + .dw 0x0913, 0xc416, 0x093f, 0xc416, 0x21, 0 + .dw 0x0941, 0xc416, 0x0941, 0xc416, 0x21, 0 + .dw 0x0943, 0xc416, 0x094f, 0xc416, 0x21, 0 + .dw 0x0951, 0xc416, 0x0951, 0xc416, 0x21, 0 + .dw 0x0953, 0xc416, 0x097f, 0xc416, 0x21, 0 + .dw 0x0981, 0xc416, 0x0981, 0xc416, 0x21, 0 + .dw 0x0983, 0xc416, 0x098f, 0xc416, 0x21, 0 + .dw 0x0991, 0xc416, 0x0991, 0xc416, 0x21, 0 + .dw 0x0993, 0xc416, 0x09bf, 0xc416, 0x21, 0 + .dw 0x09c1, 0xc416, 0x09c1, 0xc416, 0x21, 0 + .dw 0x09c3, 0xc416, 0x09cf, 0xc416, 0x21, 0 + .dw 0x09d1, 0xc416, 0x09d1, 0xc416, 0x21, 0 + .dw 0x09d3, 0xc416, 0x09ff, 0xc416, 0x21, 0 + .dw 0x0a01, 0xc416, 0x0a01, 0xc416, 0x21, 0 + .dw 0x0a03, 0xc416, 0x0a0f, 0xc416, 0x21, 0 + .dw 0x0a11, 0xc416, 0x0a11, 0xc416, 0x21, 0 + .dw 0x0a13, 0xc416, 0x0a3f, 0xc416, 0x21, 0 + .dw 0x0a41, 0xc416, 0x0a41, 0xc416, 0x21, 0 + .dw 0x0a43, 0xc416, 0x0a4f, 0xc416, 0x21, 0 + .dw 0x0a51, 0xc416, 0x0a51, 0xc416, 0x21, 0 + .dw 0x0a53, 0xc416, 0x0a7f, 0xc416, 0x21, 0 + .dw 0x0a81, 0xc416, 0x0a81, 0xc416, 0x21, 0 + .dw 0x0a83, 0xc416, 0x0a8f, 0xc416, 0x21, 0 + .dw 0x0a91, 0xc416, 0x0a91, 0xc416, 0x21, 0 + .dw 0x0a93, 0xc416, 0x0abf, 0xc416, 0x21, 0 + .dw 0x0ac1, 0xc416, 0x0ac1, 0xc416, 0x21, 0 + .dw 0x0ac3, 0xc416, 0x0acf, 0xc416, 0x21, 0 + .dw 0x0ad1, 0xc416, 0x0ad1, 0xc416, 0x21, 0 + .dw 0x0ad3, 0xc416, 0x0aff, 0xc416, 0x21, 0 + .dw 0x0b01, 0xc416, 0x0b01, 0xc416, 0x21, 0 + .dw 0x0b03, 0xc416, 0x0b0f, 0xc416, 0x21, 0 + .dw 0x0b11, 0xc416, 0x0b11, 0xc416, 0x21, 0 + .dw 0x0b13, 0xc416, 0x0b3f, 0xc416, 0x21, 0 + .dw 0x0b41, 0xc416, 0x0b41, 0xc416, 0x21, 0 + .dw 0x0b43, 0xc416, 0x0b4f, 0xc416, 0x21, 0 + .dw 0x0b51, 0xc416, 0x0b51, 0xc416, 0x21, 0 + .dw 0x0b53, 0xc416, 0x0b7f, 0xc416, 0x21, 0 + .dw 0x0b81, 0xc416, 0x0b81, 0xc416, 0x21, 0 + .dw 0x0b83, 0xc416, 0x0b8f, 0xc416, 0x21, 0 + .dw 0x0b91, 0xc416, 0x0b91, 0xc416, 0x21, 0 + .dw 0x0b93, 0xc416, 0x0bbf, 0xc416, 0x21, 0 + .dw 0x0bc1, 0xc416, 0x0bc1, 0xc416, 0x21, 0 + .dw 0x0bc3, 0xc416, 0x0bcf, 0xc416, 0x21, 0 + .dw 0x0bd1, 0xc416, 0x0bd1, 0xc416, 0x21, 0 + .dw 0x0bd3, 0xc416, 0x0bff, 0xc416, 0x21, 0 + .dw 0x0c01, 0xc416, 0x0c01, 0xc416, 0x21, 0 + .dw 0x0c03, 0xc416, 0x0c0f, 0xc416, 0x21, 0 + .dw 0x0c11, 0xc416, 0x0c11, 0xc416, 0x21, 0 + .dw 0x0c13, 0xc416, 0x0c3f, 0xc416, 0x21, 0 + .dw 0x0c41, 0xc416, 0x0c41, 0xc416, 0x21, 0 + .dw 0x0c43, 0xc416, 0x0c4f, 0xc416, 0x21, 0 + .dw 0x0c51, 0xc416, 0x0c51, 0xc416, 0x21, 0 + .dw 0x0c53, 0xc416, 0x0c7f, 0xc416, 0x21, 0 + .dw 0x0c81, 0xc416, 0x0c81, 0xc416, 0x21, 0 + .dw 0x0c83, 0xc416, 0x0c8f, 0xc416, 0x21, 0 + .dw 0x0c91, 0xc416, 0x0c91, 0xc416, 0x21, 0 + .dw 0x0c93, 0xc416, 0x0cbf, 0xc416, 0x21, 0 + .dw 0x0cc1, 0xc416, 0x0cc1, 0xc416, 0x21, 0 + .dw 0x0cc3, 0xc416, 0x0ccf, 0xc416, 0x21, 0 + .dw 0x0cd1, 0xc416, 0x0cd1, 0xc416, 0x21, 0 + .dw 0x0cd3, 0xc416, 0x0cff, 0xc416, 0x21, 0 + .dw 0x0d01, 0xc416, 0x0d01, 0xc416, 0x21, 0 + .dw 0x0d03, 0xc416, 0x0d0f, 0xc416, 0x21, 0 + .dw 0x0d11, 0xc416, 0x0d11, 0xc416, 0x21, 0 + .dw 0x0d13, 0xc416, 0x0d3f, 0xc416, 0x21, 0 + .dw 0x0d41, 0xc416, 0x0d41, 0xc416, 0x21, 0 + .dw 0x0d43, 0xc416, 0x0d4f, 0xc416, 0x21, 0 + .dw 0x0d51, 0xc416, 0x0d51, 0xc416, 0x21, 0 + .dw 0x0d53, 0xc416, 0x0d7f, 0xc416, 0x21, 0 + .dw 0x0d81, 0xc416, 0x0d81, 0xc416, 0x21, 0 + .dw 0x0d83, 0xc416, 0x0d8f, 0xc416, 0x21, 0 + .dw 0x0d91, 0xc416, 0x0d91, 0xc416, 0x21, 0 + .dw 0x0d93, 0xc416, 0x0dbf, 0xc416, 0x21, 0 + .dw 0x0dc1, 0xc416, 0x0dc1, 0xc416, 0x21, 0 + .dw 0x0dc3, 0xc416, 0x0dcf, 0xc416, 0x21, 0 + .dw 0x0dd1, 0xc416, 0x0dd1, 0xc416, 0x21, 0 + .dw 0x0dd3, 0xc416, 0x0dff, 0xc416, 0x21, 0 + .dw 0x0e01, 0xc416, 0x0e01, 0xc416, 0x21, 0 + .dw 0x0e03, 0xc416, 0x0e0f, 0xc416, 0x21, 0 + .dw 0x0e11, 0xc416, 0x0e11, 0xc416, 0x21, 0 + .dw 0x0e13, 0xc416, 0x0e3f, 0xc416, 0x21, 0 + .dw 0x0e41, 0xc416, 0x0e41, 0xc416, 0x21, 0 + .dw 0x0e43, 0xc416, 0x0e4f, 0xc416, 0x21, 0 + .dw 0x0e51, 0xc416, 0x0e51, 0xc416, 0x21, 0 + .dw 0x0e53, 0xc416, 0x0e7f, 0xc416, 0x21, 0 + .dw 0x0e81, 0xc416, 0x0e81, 0xc416, 0x21, 0 + .dw 0x0e83, 0xc416, 0x0e8f, 0xc416, 0x21, 0 + .dw 0x0e91, 0xc416, 0x0e91, 0xc416, 0x21, 0 + .dw 0x0e93, 0xc416, 0x0ebf, 0xc416, 0x21, 0 + .dw 0x0ec1, 0xc416, 0x0ec1, 0xc416, 0x21, 0 + .dw 0x0ec3, 0xc416, 0x0ecf, 0xc416, 0x21, 0 + .dw 0x0ed1, 0xc416, 0x0ed1, 0xc416, 0x21, 0 + .dw 0x0ed3, 0xc416, 0x0eff, 0xc416, 0x21, 0 + .dw 0x0f01, 0xc416, 0x0f01, 0xc416, 0x21, 0 + .dw 0x0f03, 0xc416, 0x0f0f, 0xc416, 0x21, 0 + .dw 0x0f11, 0xc416, 0x0f11, 0xc416, 0x21, 0 + .dw 0x0f13, 0xc416, 0x0f3f, 0xc416, 0x21, 0 + .dw 0x0f41, 0xc416, 0x0f41, 0xc416, 0x21, 0 + .dw 0x0f43, 0xc416, 0x0f4f, 0xc416, 0x21, 0 + .dw 0x0f51, 0xc416, 0x0f51, 0xc416, 0x21, 0 + .dw 0x0f53, 0xc416, 0x0f7f, 0xc416, 0x21, 0 + .dw 0x0f81, 0xc416, 0x0f81, 0xc416, 0x21, 0 + .dw 0x0f83, 0xc416, 0x0f8f, 0xc416, 0x21, 0 + .dw 0x0f91, 0xc416, 0x0f91, 0xc416, 0x21, 0 + .dw 0x0f93, 0xc416, 0x0fbf, 0xc416, 0x21, 0 + .dw 0x0fc1, 0xc416, 0x0fc1, 0xc416, 0x21, 0 + .dw 0x0fc3, 0xc416, 0x0fcf, 0xc416, 0x21, 0 + .dw 0x0fd1, 0xc416, 0x0fd1, 0xc416, 0x21, 0 + .dw 0x0fd3, 0xc416, 0x1fff, 0xc416, 0x21, 0 + .dw 0x2001, 0xc416, 0x2001, 0xc416, 0x21, 0 + .dw 0x2003, 0xc416, 0x200f, 0xc416, 0x21, 0 + .dw 0x2011, 0xc416, 0x2011, 0xc416, 0x21, 0 + .dw 0x2013, 0xc416, 0x203f, 0xc416, 0x21, 0 + .dw 0x2041, 0xc416, 0x2041, 0xc416, 0x21, 0 + .dw 0x2043, 0xc416, 0x204f, 0xc416, 0x21, 0 + .dw 0x2051, 0xc416, 0x2051, 0xc416, 0x21, 0 + .dw 0x2053, 0xc416, 0x207f, 0xc416, 0x21, 0 + .dw 0x2081, 0xc416, 0x2081, 0xc416, 0x21, 0 + .dw 0x2083, 0xc416, 0x208f, 0xc416, 0x21, 0 + .dw 0x2091, 0xc416, 0x2091, 0xc416, 0x21, 0 + .dw 0x2093, 0xc416, 0x20bf, 0xc416, 0x21, 0 + .dw 0x20c1, 0xc416, 0x20c1, 0xc416, 0x21, 0 + .dw 0x20c3, 0xc416, 0x20cf, 0xc416, 0x21, 0 + .dw 0x20d1, 0xc416, 0x20d1, 0xc416, 0x21, 0 + .dw 0x20d3, 0xc416, 0x20ff, 0xc416, 0x21, 0 + .dw 0x2101, 0xc416, 0x2101, 0xc416, 0x21, 0 + .dw 0x2103, 0xc416, 0x210f, 0xc416, 0x21, 0 + .dw 0x2111, 0xc416, 0x2111, 0xc416, 0x21, 0 + .dw 0x2113, 0xc416, 0x213f, 0xc416, 0x21, 0 + .dw 0x2141, 0xc416, 0x2141, 0xc416, 0x21, 0 + .dw 0x2143, 0xc416, 0x214f, 0xc416, 0x21, 0 + .dw 0x2151, 0xc416, 0x2151, 0xc416, 0x21, 0 + .dw 0x2153, 0xc416, 0x217f, 0xc416, 0x21, 0 + .dw 0x2181, 0xc416, 0x2181, 0xc416, 0x21, 0 + .dw 0x2183, 0xc416, 0x218f, 0xc416, 0x21, 0 + .dw 0x2191, 0xc416, 0x2191, 0xc416, 0x21, 0 + .dw 0x2193, 0xc416, 0x21bf, 0xc416, 0x21, 0 + .dw 0x21c1, 0xc416, 0x21c1, 0xc416, 0x21, 0 + .dw 0x21c3, 0xc416, 0x21cf, 0xc416, 0x21, 0 + .dw 0x21d1, 0xc416, 0x21d1, 0xc416, 0x21, 0 + .dw 0x21d3, 0xc416, 0x21ff, 0xc416, 0x21, 0 + .dw 0x2201, 0xc416, 0x2201, 0xc416, 0x21, 0 + .dw 0x2203, 0xc416, 0x220f, 0xc416, 0x21, 0 + .dw 0x2211, 0xc416, 0x2211, 0xc416, 0x21, 0 + .dw 0x2213, 0xc416, 0x223f, 0xc416, 0x21, 0 + .dw 0x2241, 0xc416, 0x2241, 0xc416, 0x21, 0 + .dw 0x2243, 0xc416, 0x224f, 0xc416, 0x21, 0 + .dw 0x2251, 0xc416, 0x2251, 0xc416, 0x21, 0 + .dw 0x2253, 0xc416, 0x227f, 0xc416, 0x21, 0 + .dw 0x2281, 0xc416, 0x2281, 0xc416, 0x21, 0 + .dw 0x2283, 0xc416, 0x228f, 0xc416, 0x21, 0 + .dw 0x2291, 0xc416, 0x2291, 0xc416, 0x21, 0 + .dw 0x2293, 0xc416, 0x22bf, 0xc416, 0x21, 0 + .dw 0x22c1, 0xc416, 0x22c1, 0xc416, 0x21, 0 + .dw 0x22c3, 0xc416, 0x22cf, 0xc416, 0x21, 0 + .dw 0x22d1, 0xc416, 0x22d1, 0xc416, 0x21, 0 + .dw 0x22d3, 0xc416, 0x22ff, 0xc416, 0x21, 0 + .dw 0x2301, 0xc416, 0x2301, 0xc416, 0x21, 0 + .dw 0x2303, 0xc416, 0x230f, 0xc416, 0x21, 0 + .dw 0x2311, 0xc416, 0x2311, 0xc416, 0x21, 0 + .dw 0x2313, 0xc416, 0x233f, 0xc416, 0x21, 0 + .dw 0x2341, 0xc416, 0x2341, 0xc416, 0x21, 0 + .dw 0x2343, 0xc416, 0x234f, 0xc416, 0x21, 0 + .dw 0x2351, 0xc416, 0x2351, 0xc416, 0x21, 0 + .dw 0x2353, 0xc416, 0x237f, 0xc416, 0x21, 0 + .dw 0x2381, 0xc416, 0x2381, 0xc416, 0x21, 0 + .dw 0x2383, 0xc416, 0x238f, 0xc416, 0x21, 0 + .dw 0x2391, 0xc416, 0x2391, 0xc416, 0x21, 0 + .dw 0x2393, 0xc416, 0x23bf, 0xc416, 0x21, 0 + .dw 0x23c1, 0xc416, 0x23c1, 0xc416, 0x21, 0 + .dw 0x23c3, 0xc416, 0x23cf, 0xc416, 0x21, 0 + .dw 0x23d1, 0xc416, 0x23d1, 0xc416, 0x21, 0 + .dw 0x23d3, 0xc416, 0x23ff, 0xc416, 0x21, 0 + .dw 0x2401, 0xc416, 0x2401, 0xc416, 0x21, 0 + .dw 0x2403, 0xc416, 0x240f, 0xc416, 0x21, 0 + .dw 0x2411, 0xc416, 0x2411, 0xc416, 0x21, 0 + .dw 0x2413, 0xc416, 0x243f, 0xc416, 0x21, 0 + .dw 0x2441, 0xc416, 0x2441, 0xc416, 0x21, 0 + .dw 0x2443, 0xc416, 0x244f, 0xc416, 0x21, 0 + .dw 0x2451, 0xc416, 0x2451, 0xc416, 0x21, 0 + .dw 0x2453, 0xc416, 0x247f, 0xc416, 0x21, 0 + .dw 0x2481, 0xc416, 0x2481, 0xc416, 0x21, 0 + .dw 0x2483, 0xc416, 0x248f, 0xc416, 0x21, 0 + .dw 0x2491, 0xc416, 0x2491, 0xc416, 0x21, 0 + .dw 0x2493, 0xc416, 0x24bf, 0xc416, 0x21, 0 + .dw 0x24c1, 0xc416, 0x24c1, 0xc416, 0x21, 0 + .dw 0x24c3, 0xc416, 0x24cf, 0xc416, 0x21, 0 + .dw 0x24d1, 0xc416, 0x24d1, 0xc416, 0x21, 0 + .dw 0x24d3, 0xc416, 0x24ff, 0xc416, 0x21, 0 + .dw 0x2501, 0xc416, 0x2501, 0xc416, 0x21, 0 + .dw 0x2503, 0xc416, 0x250f, 0xc416, 0x21, 0 + .dw 0x2511, 0xc416, 0x2511, 0xc416, 0x21, 0 + .dw 0x2513, 0xc416, 0x253f, 0xc416, 0x21, 0 + .dw 0x2541, 0xc416, 0x2541, 0xc416, 0x21, 0 + .dw 0x2543, 0xc416, 0x254f, 0xc416, 0x21, 0 + .dw 0x2551, 0xc416, 0x2551, 0xc416, 0x21, 0 + .dw 0x2553, 0xc416, 0x257f, 0xc416, 0x21, 0 + .dw 0x2581, 0xc416, 0x2581, 0xc416, 0x21, 0 + .dw 0x2583, 0xc416, 0x258f, 0xc416, 0x21, 0 + .dw 0x2591, 0xc416, 0x2591, 0xc416, 0x21, 0 + .dw 0x2593, 0xc416, 0x25bf, 0xc416, 0x21, 0 + .dw 0x25c1, 0xc416, 0x25c1, 0xc416, 0x21, 0 + .dw 0x25c3, 0xc416, 0x25cf, 0xc416, 0x21, 0 + .dw 0x25d1, 0xc416, 0x25d1, 0xc416, 0x21, 0 + .dw 0x25d3, 0xc416, 0x25ff, 0xc416, 0x21, 0 + .dw 0x2601, 0xc416, 0x2601, 0xc416, 0x21, 0 + .dw 0x2603, 0xc416, 0x260f, 0xc416, 0x21, 0 + .dw 0x2611, 0xc416, 0x2611, 0xc416, 0x21, 0 + .dw 0x2613, 0xc416, 0x263f, 0xc416, 0x21, 0 + .dw 0x2641, 0xc416, 0x2641, 0xc416, 0x21, 0 + .dw 0x2643, 0xc416, 0x264f, 0xc416, 0x21, 0 + .dw 0x2651, 0xc416, 0x2651, 0xc416, 0x21, 0 + .dw 0x2653, 0xc416, 0x267f, 0xc416, 0x21, 0 + .dw 0x2681, 0xc416, 0x2681, 0xc416, 0x21, 0 + .dw 0x2683, 0xc416, 0x268f, 0xc416, 0x21, 0 + .dw 0x2691, 0xc416, 0x2691, 0xc416, 0x21, 0 + .dw 0x2693, 0xc416, 0x26bf, 0xc416, 0x21, 0 + .dw 0x26c1, 0xc416, 0x26c1, 0xc416, 0x21, 0 + .dw 0x26c3, 0xc416, 0x26cf, 0xc416, 0x21, 0 + .dw 0x26d1, 0xc416, 0x26d1, 0xc416, 0x21, 0 + .dw 0x26d3, 0xc416, 0x26ff, 0xc416, 0x21, 0 + .dw 0x2701, 0xc416, 0x2701, 0xc416, 0x21, 0 + .dw 0x2703, 0xc416, 0x270f, 0xc416, 0x21, 0 + .dw 0x2711, 0xc416, 0x2711, 0xc416, 0x21, 0 + .dw 0x2713, 0xc416, 0x273f, 0xc416, 0x21, 0 + .dw 0x2741, 0xc416, 0x2741, 0xc416, 0x21, 0 + .dw 0x2743, 0xc416, 0x274f, 0xc416, 0x21, 0 + .dw 0x2751, 0xc416, 0x2751, 0xc416, 0x21, 0 + .dw 0x2753, 0xc416, 0x277f, 0xc416, 0x21, 0 + .dw 0x2781, 0xc416, 0x2781, 0xc416, 0x21, 0 + .dw 0x2783, 0xc416, 0x278f, 0xc416, 0x21, 0 + .dw 0x2791, 0xc416, 0x2791, 0xc416, 0x21, 0 + .dw 0x2793, 0xc416, 0x27bf, 0xc416, 0x21, 0 + .dw 0x27c1, 0xc416, 0x27c1, 0xc416, 0x21, 0 + .dw 0x27c3, 0xc416, 0x27cf, 0xc416, 0x21, 0 + .dw 0x27d1, 0xc416, 0x27d1, 0xc416, 0x21, 0 + .dw 0x27d3, 0xc416, 0x27ff, 0xc416, 0x21, 0 + .dw 0x2801, 0xc416, 0x2801, 0xc416, 0x21, 0 + .dw 0x2803, 0xc416, 0x280f, 0xc416, 0x21, 0 + .dw 0x2811, 0xc416, 0x2811, 0xc416, 0x21, 0 + .dw 0x2813, 0xc416, 0x283f, 0xc416, 0x21, 0 + .dw 0x2841, 0xc416, 0x2841, 0xc416, 0x21, 0 + .dw 0x2843, 0xc416, 0x284f, 0xc416, 0x21, 0 + .dw 0x2851, 0xc416, 0x2851, 0xc416, 0x21, 0 + .dw 0x2853, 0xc416, 0x287f, 0xc416, 0x21, 0 + .dw 0x2881, 0xc416, 0x2881, 0xc416, 0x21, 0 + .dw 0x2883, 0xc416, 0x288f, 0xc416, 0x21, 0 + .dw 0x2891, 0xc416, 0x2891, 0xc416, 0x21, 0 + .dw 0x2893, 0xc416, 0x28bf, 0xc416, 0x21, 0 + .dw 0x28c1, 0xc416, 0x28c1, 0xc416, 0x21, 0 + .dw 0x28c3, 0xc416, 0x28cf, 0xc416, 0x21, 0 + .dw 0x28d1, 0xc416, 0x28d1, 0xc416, 0x21, 0 + .dw 0x28d3, 0xc416, 0x28ff, 0xc416, 0x21, 0 + .dw 0x2901, 0xc416, 0x2901, 0xc416, 0x21, 0 + .dw 0x2903, 0xc416, 0x290f, 0xc416, 0x21, 0 + .dw 0x2911, 0xc416, 0x2911, 0xc416, 0x21, 0 + .dw 0x2913, 0xc416, 0x293f, 0xc416, 0x21, 0 + .dw 0x2941, 0xc416, 0x2941, 0xc416, 0x21, 0 + .dw 0x2943, 0xc416, 0x294f, 0xc416, 0x21, 0 + .dw 0x2951, 0xc416, 0x2951, 0xc416, 0x21, 0 + .dw 0x2953, 0xc416, 0x297f, 0xc416, 0x21, 0 + .dw 0x2981, 0xc416, 0x2981, 0xc416, 0x21, 0 + .dw 0x2983, 0xc416, 0x298f, 0xc416, 0x21, 0 + .dw 0x2991, 0xc416, 0x2991, 0xc416, 0x21, 0 + .dw 0x2993, 0xc416, 0x29bf, 0xc416, 0x21, 0 + .dw 0x29c1, 0xc416, 0x29c1, 0xc416, 0x21, 0 + .dw 0x29c3, 0xc416, 0x29cf, 0xc416, 0x21, 0 + .dw 0x29d1, 0xc416, 0x29d1, 0xc416, 0x21, 0 + .dw 0x29d3, 0xc416, 0x29ff, 0xc416, 0x21, 0 + .dw 0x2a01, 0xc416, 0x2a01, 0xc416, 0x21, 0 + .dw 0x2a03, 0xc416, 0x2a0f, 0xc416, 0x21, 0 + .dw 0x2a11, 0xc416, 0x2a11, 0xc416, 0x21, 0 + .dw 0x2a13, 0xc416, 0x2a3f, 0xc416, 0x21, 0 + .dw 0x2a41, 0xc416, 0x2a41, 0xc416, 0x21, 0 + .dw 0x2a43, 0xc416, 0x2a4f, 0xc416, 0x21, 0 + .dw 0x2a51, 0xc416, 0x2a51, 0xc416, 0x21, 0 + .dw 0x2a53, 0xc416, 0x2a7f, 0xc416, 0x21, 0 + .dw 0x2a81, 0xc416, 0x2a81, 0xc416, 0x21, 0 + .dw 0x2a83, 0xc416, 0x2a8f, 0xc416, 0x21, 0 + .dw 0x2a91, 0xc416, 0x2a91, 0xc416, 0x21, 0 + .dw 0x2a93, 0xc416, 0x2abf, 0xc416, 0x21, 0 + .dw 0x2ac1, 0xc416, 0x2ac1, 0xc416, 0x21, 0 + .dw 0x2ac3, 0xc416, 0x2acf, 0xc416, 0x21, 0 + .dw 0x2ad1, 0xc416, 0x2ad1, 0xc416, 0x21, 0 + .dw 0x2ad3, 0xc416, 0x2aff, 0xc416, 0x21, 0 + .dw 0x2b01, 0xc416, 0x2b01, 0xc416, 0x21, 0 + .dw 0x2b03, 0xc416, 0x2b0f, 0xc416, 0x21, 0 + .dw 0x2b11, 0xc416, 0x2b11, 0xc416, 0x21, 0 + .dw 0x2b13, 0xc416, 0x2b3f, 0xc416, 0x21, 0 + .dw 0x2b41, 0xc416, 0x2b41, 0xc416, 0x21, 0 + .dw 0x2b43, 0xc416, 0x2b4f, 0xc416, 0x21, 0 + .dw 0x2b51, 0xc416, 0x2b51, 0xc416, 0x21, 0 + .dw 0x2b53, 0xc416, 0x2b7f, 0xc416, 0x21, 0 + .dw 0x2b81, 0xc416, 0x2b81, 0xc416, 0x21, 0 + .dw 0x2b83, 0xc416, 0x2b8f, 0xc416, 0x21, 0 + .dw 0x2b91, 0xc416, 0x2b91, 0xc416, 0x21, 0 + .dw 0x2b93, 0xc416, 0x2bbf, 0xc416, 0x21, 0 + .dw 0x2bc1, 0xc416, 0x2bc1, 0xc416, 0x21, 0 + .dw 0x2bc3, 0xc416, 0x2bcf, 0xc416, 0x21, 0 + .dw 0x2bd1, 0xc416, 0x2bd1, 0xc416, 0x21, 0 + .dw 0x2bd3, 0xc416, 0x2bff, 0xc416, 0x21, 0 + .dw 0x2c01, 0xc416, 0x2c01, 0xc416, 0x21, 0 + .dw 0x2c03, 0xc416, 0x2c0f, 0xc416, 0x21, 0 + .dw 0x2c11, 0xc416, 0x2c11, 0xc416, 0x21, 0 + .dw 0x2c13, 0xc416, 0x2c3f, 0xc416, 0x21, 0 + .dw 0x2c41, 0xc416, 0x2c41, 0xc416, 0x21, 0 + .dw 0x2c43, 0xc416, 0x2c4f, 0xc416, 0x21, 0 + .dw 0x2c51, 0xc416, 0x2c51, 0xc416, 0x21, 0 + .dw 0x2c53, 0xc416, 0x2c7f, 0xc416, 0x21, 0 + .dw 0x2c81, 0xc416, 0x2c81, 0xc416, 0x21, 0 + .dw 0x2c83, 0xc416, 0x2c8f, 0xc416, 0x21, 0 + .dw 0x2c91, 0xc416, 0x2c91, 0xc416, 0x21, 0 + .dw 0x2c93, 0xc416, 0x2cbf, 0xc416, 0x21, 0 + .dw 0x2cc1, 0xc416, 0x2cc1, 0xc416, 0x21, 0 + .dw 0x2cc3, 0xc416, 0x2ccf, 0xc416, 0x21, 0 + .dw 0x2cd1, 0xc416, 0x2cd1, 0xc416, 0x21, 0 + .dw 0x2cd3, 0xc416, 0x2cff, 0xc416, 0x21, 0 + .dw 0x2d01, 0xc416, 0x2d01, 0xc416, 0x21, 0 + .dw 0x2d03, 0xc416, 0x2d0f, 0xc416, 0x21, 0 + .dw 0x2d11, 0xc416, 0x2d11, 0xc416, 0x21, 0 + .dw 0x2d13, 0xc416, 0x2d3f, 0xc416, 0x21, 0 + .dw 0x2d41, 0xc416, 0x2d41, 0xc416, 0x21, 0 + .dw 0x2d43, 0xc416, 0x2d4f, 0xc416, 0x21, 0 + .dw 0x2d51, 0xc416, 0x2d51, 0xc416, 0x21, 0 + .dw 0x2d53, 0xc416, 0x2d7f, 0xc416, 0x21, 0 + .dw 0x2d81, 0xc416, 0x2d81, 0xc416, 0x21, 0 + .dw 0x2d83, 0xc416, 0x2d8f, 0xc416, 0x21, 0 + .dw 0x2d91, 0xc416, 0x2d91, 0xc416, 0x21, 0 + .dw 0x2d93, 0xc416, 0x2dbf, 0xc416, 0x21, 0 + .dw 0x2dc1, 0xc416, 0x2dc1, 0xc416, 0x21, 0 + .dw 0x2dc3, 0xc416, 0x2dcf, 0xc416, 0x21, 0 + .dw 0x2dd1, 0xc416, 0x2dd1, 0xc416, 0x21, 0 + .dw 0x2dd3, 0xc416, 0x2dff, 0xc416, 0x21, 0 + .dw 0x2e01, 0xc416, 0x2e01, 0xc416, 0x21, 0 + .dw 0x2e03, 0xc416, 0x2e0f, 0xc416, 0x21, 0 + .dw 0x2e11, 0xc416, 0x2e11, 0xc416, 0x21, 0 + .dw 0x2e13, 0xc416, 0x2e3f, 0xc416, 0x21, 0 + .dw 0x2e41, 0xc416, 0x2e41, 0xc416, 0x21, 0 + .dw 0x2e43, 0xc416, 0x2e4f, 0xc416, 0x21, 0 + .dw 0x2e51, 0xc416, 0x2e51, 0xc416, 0x21, 0 + .dw 0x2e53, 0xc416, 0x2e7f, 0xc416, 0x21, 0 + .dw 0x2e81, 0xc416, 0x2e81, 0xc416, 0x21, 0 + .dw 0x2e83, 0xc416, 0x2e8f, 0xc416, 0x21, 0 + .dw 0x2e91, 0xc416, 0x2e91, 0xc416, 0x21, 0 + .dw 0x2e93, 0xc416, 0x2ebf, 0xc416, 0x21, 0 + .dw 0x2ec1, 0xc416, 0x2ec1, 0xc416, 0x21, 0 + .dw 0x2ec3, 0xc416, 0x2ecf, 0xc416, 0x21, 0 + .dw 0x2ed1, 0xc416, 0x2ed1, 0xc416, 0x21, 0 + .dw 0x2ed3, 0xc416, 0x2eff, 0xc416, 0x21, 0 + .dw 0x2f01, 0xc416, 0x2f01, 0xc416, 0x21, 0 + .dw 0x2f03, 0xc416, 0x2f0f, 0xc416, 0x21, 0 + .dw 0x2f11, 0xc416, 0x2f11, 0xc416, 0x21, 0 + .dw 0x2f13, 0xc416, 0x2f3f, 0xc416, 0x21, 0 + .dw 0x2f41, 0xc416, 0x2f41, 0xc416, 0x21, 0 + .dw 0x2f43, 0xc416, 0x2f4f, 0xc416, 0x21, 0 + .dw 0x2f51, 0xc416, 0x2f51, 0xc416, 0x21, 0 + .dw 0x2f53, 0xc416, 0x2f7f, 0xc416, 0x21, 0 + .dw 0x2f81, 0xc416, 0x2f81, 0xc416, 0x21, 0 + .dw 0x2f83, 0xc416, 0x2f8f, 0xc416, 0x21, 0 + .dw 0x2f91, 0xc416, 0x2f91, 0xc416, 0x21, 0 + .dw 0x2f93, 0xc416, 0x2fbf, 0xc416, 0x21, 0 + .dw 0x2fc1, 0xc416, 0x2fc1, 0xc416, 0x21, 0 + .dw 0x2fc3, 0xc416, 0x2fcf, 0xc416, 0x21, 0 + .dw 0x2fd1, 0xc416, 0x2fd1, 0xc416, 0x21, 0 + .dw 0x2fd3, 0xc416, 0x3fff, 0xc416, 0x21, 0 + .dw 0x4001, 0xc416, 0x4001, 0xc416, 0x21, 0 + .dw 0x4003, 0xc416, 0x400f, 0xc416, 0x21, 0 + .dw 0x4011, 0xc416, 0x4011, 0xc416, 0x21, 0 + .dw 0x4013, 0xc416, 0x403f, 0xc416, 0x21, 0 + .dw 0x4041, 0xc416, 0x4041, 0xc416, 0x21, 0 + .dw 0x4043, 0xc416, 0x404f, 0xc416, 0x21, 0 + .dw 0x4051, 0xc416, 0x4051, 0xc416, 0x21, 0 + .dw 0x4053, 0xc416, 0x407f, 0xc416, 0x21, 0 + .dw 0x4081, 0xc416, 0x4081, 0xc416, 0x21, 0 + .dw 0x4083, 0xc416, 0x408f, 0xc416, 0x21, 0 + .dw 0x4091, 0xc416, 0x4091, 0xc416, 0x21, 0 + .dw 0x4093, 0xc416, 0x40bf, 0xc416, 0x21, 0 + .dw 0x40c1, 0xc416, 0x40c1, 0xc416, 0x21, 0 + .dw 0x40c3, 0xc416, 0x40cf, 0xc416, 0x21, 0 + .dw 0x40d1, 0xc416, 0x40d1, 0xc416, 0x21, 0 + .dw 0x40d3, 0xc416, 0x40ff, 0xc416, 0x21, 0 + .dw 0x4101, 0xc416, 0x4101, 0xc416, 0x21, 0 + .dw 0x4103, 0xc416, 0x410f, 0xc416, 0x21, 0 + .dw 0x4111, 0xc416, 0x4111, 0xc416, 0x21, 0 + .dw 0x4113, 0xc416, 0x413f, 0xc416, 0x21, 0 + .dw 0x4141, 0xc416, 0x4141, 0xc416, 0x21, 0 + .dw 0x4143, 0xc416, 0x414f, 0xc416, 0x21, 0 + .dw 0x4151, 0xc416, 0x4151, 0xc416, 0x21, 0 + .dw 0x4153, 0xc416, 0x417f, 0xc416, 0x21, 0 + .dw 0x4181, 0xc416, 0x4181, 0xc416, 0x21, 0 + .dw 0x4183, 0xc416, 0x418f, 0xc416, 0x21, 0 + .dw 0x4191, 0xc416, 0x4191, 0xc416, 0x21, 0 + .dw 0x4193, 0xc416, 0x41bf, 0xc416, 0x21, 0 + .dw 0x41c1, 0xc416, 0x41c1, 0xc416, 0x21, 0 + .dw 0x41c3, 0xc416, 0x41cf, 0xc416, 0x21, 0 + .dw 0x41d1, 0xc416, 0x41d1, 0xc416, 0x21, 0 + .dw 0x41d3, 0xc416, 0x41ff, 0xc416, 0x21, 0 + .dw 0x4201, 0xc416, 0x4201, 0xc416, 0x21, 0 + .dw 0x4203, 0xc416, 0x420f, 0xc416, 0x21, 0 + .dw 0x4211, 0xc416, 0x4211, 0xc416, 0x21, 0 + .dw 0x4213, 0xc416, 0x423f, 0xc416, 0x21, 0 + .dw 0x4241, 0xc416, 0x4241, 0xc416, 0x21, 0 + .dw 0x4243, 0xc416, 0x424f, 0xc416, 0x21, 0 + .dw 0x4251, 0xc416, 0x4251, 0xc416, 0x21, 0 + .dw 0x4253, 0xc416, 0x427f, 0xc416, 0x21, 0 + .dw 0x4281, 0xc416, 0x4281, 0xc416, 0x21, 0 + .dw 0x4283, 0xc416, 0x428f, 0xc416, 0x21, 0 + .dw 0x4291, 0xc416, 0x4291, 0xc416, 0x21, 0 + .dw 0x4293, 0xc416, 0x42bf, 0xc416, 0x21, 0 + .dw 0x42c1, 0xc416, 0x42c1, 0xc416, 0x21, 0 + .dw 0x42c3, 0xc416, 0x42cf, 0xc416, 0x21, 0 + .dw 0x42d1, 0xc416, 0x42d1, 0xc416, 0x21, 0 + .dw 0x42d3, 0xc416, 0x42ff, 0xc416, 0x21, 0 + .dw 0x4301, 0xc416, 0x4301, 0xc416, 0x21, 0 + .dw 0x4303, 0xc416, 0x430f, 0xc416, 0x21, 0 + .dw 0x4311, 0xc416, 0x4311, 0xc416, 0x21, 0 + .dw 0x4313, 0xc416, 0x433f, 0xc416, 0x21, 0 + .dw 0x4341, 0xc416, 0x4341, 0xc416, 0x21, 0 + .dw 0x4343, 0xc416, 0x434f, 0xc416, 0x21, 0 + .dw 0x4351, 0xc416, 0x4351, 0xc416, 0x21, 0 + .dw 0x4353, 0xc416, 0x437f, 0xc416, 0x21, 0 + .dw 0x4381, 0xc416, 0x4381, 0xc416, 0x21, 0 + .dw 0x4383, 0xc416, 0x438f, 0xc416, 0x21, 0 + .dw 0x4391, 0xc416, 0x4391, 0xc416, 0x21, 0 + .dw 0x4393, 0xc416, 0x43bf, 0xc416, 0x21, 0 + .dw 0x43c1, 0xc416, 0x43c1, 0xc416, 0x21, 0 + .dw 0x43c3, 0xc416, 0x43cf, 0xc416, 0x21, 0 + .dw 0x43d1, 0xc416, 0x43d1, 0xc416, 0x21, 0 + .dw 0x43d3, 0xc416, 0x43ff, 0xc416, 0x21, 0 + .dw 0x4401, 0xc416, 0x4401, 0xc416, 0x21, 0 + .dw 0x4403, 0xc416, 0x440f, 0xc416, 0x21, 0 + .dw 0x4411, 0xc416, 0x4411, 0xc416, 0x21, 0 + .dw 0x4413, 0xc416, 0x443f, 0xc416, 0x21, 0 + .dw 0x4441, 0xc416, 0x4441, 0xc416, 0x21, 0 + .dw 0x4443, 0xc416, 0x444f, 0xc416, 0x21, 0 + .dw 0x4451, 0xc416, 0x4451, 0xc416, 0x21, 0 + .dw 0x4453, 0xc416, 0x447f, 0xc416, 0x21, 0 + .dw 0x4481, 0xc416, 0x4481, 0xc416, 0x21, 0 + .dw 0x4483, 0xc416, 0x448f, 0xc416, 0x21, 0 + .dw 0x4491, 0xc416, 0x4491, 0xc416, 0x21, 0 + .dw 0x4493, 0xc416, 0x44bf, 0xc416, 0x21, 0 + .dw 0x44c1, 0xc416, 0x44c1, 0xc416, 0x21, 0 + .dw 0x44c3, 0xc416, 0x44cf, 0xc416, 0x21, 0 + .dw 0x44d1, 0xc416, 0x44d1, 0xc416, 0x21, 0 + .dw 0x44d3, 0xc416, 0x44ff, 0xc416, 0x21, 0 + .dw 0x4501, 0xc416, 0x4501, 0xc416, 0x21, 0 + .dw 0x4503, 0xc416, 0x450f, 0xc416, 0x21, 0 + .dw 0x4511, 0xc416, 0x4511, 0xc416, 0x21, 0 + .dw 0x4513, 0xc416, 0x453f, 0xc416, 0x21, 0 + .dw 0x4541, 0xc416, 0x4541, 0xc416, 0x21, 0 + .dw 0x4543, 0xc416, 0x454f, 0xc416, 0x21, 0 + .dw 0x4551, 0xc416, 0x4551, 0xc416, 0x21, 0 + .dw 0x4553, 0xc416, 0x457f, 0xc416, 0x21, 0 + .dw 0x4581, 0xc416, 0x4581, 0xc416, 0x21, 0 + .dw 0x4583, 0xc416, 0x458f, 0xc416, 0x21, 0 + .dw 0x4591, 0xc416, 0x4591, 0xc416, 0x21, 0 + .dw 0x4593, 0xc416, 0x45bf, 0xc416, 0x21, 0 + .dw 0x45c1, 0xc416, 0x45c1, 0xc416, 0x21, 0 + .dw 0x45c3, 0xc416, 0x45cf, 0xc416, 0x21, 0 + .dw 0x45d1, 0xc416, 0x45d1, 0xc416, 0x21, 0 + .dw 0x45d3, 0xc416, 0x45ff, 0xc416, 0x21, 0 + .dw 0x4601, 0xc416, 0x4601, 0xc416, 0x21, 0 + .dw 0x4603, 0xc416, 0x460f, 0xc416, 0x21, 0 + .dw 0x4611, 0xc416, 0x4611, 0xc416, 0x21, 0 + .dw 0x4613, 0xc416, 0x463f, 0xc416, 0x21, 0 + .dw 0x4641, 0xc416, 0x4641, 0xc416, 0x21, 0 + .dw 0x4643, 0xc416, 0x464f, 0xc416, 0x21, 0 + .dw 0x4651, 0xc416, 0x4651, 0xc416, 0x21, 0 + .dw 0x4653, 0xc416, 0x467f, 0xc416, 0x21, 0 + .dw 0x4681, 0xc416, 0x4681, 0xc416, 0x21, 0 + .dw 0x4683, 0xc416, 0x468f, 0xc416, 0x21, 0 + .dw 0x4691, 0xc416, 0x4691, 0xc416, 0x21, 0 + .dw 0x4693, 0xc416, 0x46bf, 0xc416, 0x21, 0 + .dw 0x46c1, 0xc416, 0x46c1, 0xc416, 0x21, 0 + .dw 0x46c3, 0xc416, 0x46cf, 0xc416, 0x21, 0 + .dw 0x46d1, 0xc416, 0x46d1, 0xc416, 0x21, 0 + .dw 0x46d3, 0xc416, 0x46ff, 0xc416, 0x21, 0 + .dw 0x4701, 0xc416, 0x4701, 0xc416, 0x21, 0 + .dw 0x4703, 0xc416, 0x470f, 0xc416, 0x21, 0 + .dw 0x4711, 0xc416, 0x4711, 0xc416, 0x21, 0 + .dw 0x4713, 0xc416, 0x473f, 0xc416, 0x21, 0 + .dw 0x4741, 0xc416, 0x4741, 0xc416, 0x21, 0 + .dw 0x4743, 0xc416, 0x474f, 0xc416, 0x21, 0 + .dw 0x4751, 0xc416, 0x4751, 0xc416, 0x21, 0 + .dw 0x4753, 0xc416, 0x477f, 0xc416, 0x21, 0 + .dw 0x4781, 0xc416, 0x4781, 0xc416, 0x21, 0 + .dw 0x4783, 0xc416, 0x478f, 0xc416, 0x21, 0 + .dw 0x4791, 0xc416, 0x4791, 0xc416, 0x21, 0 + .dw 0x4793, 0xc416, 0x47bf, 0xc416, 0x21, 0 + .dw 0x47c1, 0xc416, 0x47c1, 0xc416, 0x21, 0 + .dw 0x47c3, 0xc416, 0x47cf, 0xc416, 0x21, 0 + .dw 0x47d1, 0xc416, 0x47d1, 0xc416, 0x21, 0 + .dw 0x47d3, 0xc416, 0x47ff, 0xc416, 0x21, 0 + .dw 0x4801, 0xc416, 0x4801, 0xc416, 0x21, 0 + .dw 0x4803, 0xc416, 0x480f, 0xc416, 0x21, 0 + .dw 0x4811, 0xc416, 0x4811, 0xc416, 0x21, 0 + .dw 0x4813, 0xc416, 0x483f, 0xc416, 0x21, 0 + .dw 0x4841, 0xc416, 0x4841, 0xc416, 0x21, 0 + .dw 0x4843, 0xc416, 0x484f, 0xc416, 0x21, 0 + .dw 0x4851, 0xc416, 0x4851, 0xc416, 0x21, 0 + .dw 0x4853, 0xc416, 0x487f, 0xc416, 0x21, 0 + .dw 0x4881, 0xc416, 0x4881, 0xc416, 0x21, 0 + .dw 0x4883, 0xc416, 0x488f, 0xc416, 0x21, 0 + .dw 0x4891, 0xc416, 0x4891, 0xc416, 0x21, 0 + .dw 0x4893, 0xc416, 0x48bf, 0xc416, 0x21, 0 + .dw 0x48c1, 0xc416, 0x48c1, 0xc416, 0x21, 0 + .dw 0x48c3, 0xc416, 0x48cf, 0xc416, 0x21, 0 + .dw 0x48d1, 0xc416, 0x48d1, 0xc416, 0x21, 0 + .dw 0x48d3, 0xc416, 0x48ff, 0xc416, 0x21, 0 + .dw 0x4901, 0xc416, 0x4901, 0xc416, 0x21, 0 + .dw 0x4903, 0xc416, 0x490f, 0xc416, 0x21, 0 + .dw 0x4911, 0xc416, 0x4911, 0xc416, 0x21, 0 + .dw 0x4913, 0xc416, 0x493f, 0xc416, 0x21, 0 + .dw 0x4941, 0xc416, 0x4941, 0xc416, 0x21, 0 + .dw 0x4943, 0xc416, 0x494f, 0xc416, 0x21, 0 + .dw 0x4951, 0xc416, 0x4951, 0xc416, 0x21, 0 + .dw 0x4953, 0xc416, 0x497f, 0xc416, 0x21, 0 + .dw 0x4981, 0xc416, 0x4981, 0xc416, 0x21, 0 + .dw 0x4983, 0xc416, 0x498f, 0xc416, 0x21, 0 + .dw 0x4991, 0xc416, 0x4991, 0xc416, 0x21, 0 + .dw 0x4993, 0xc416, 0x49bf, 0xc416, 0x21, 0 + .dw 0x49c1, 0xc416, 0x49c1, 0xc416, 0x21, 0 + .dw 0x49c3, 0xc416, 0x49cf, 0xc416, 0x21, 0 + .dw 0x49d1, 0xc416, 0x49d1, 0xc416, 0x21, 0 + .dw 0x49d3, 0xc416, 0x49ff, 0xc416, 0x21, 0 + .dw 0x4a01, 0xc416, 0x4a01, 0xc416, 0x21, 0 + .dw 0x4a03, 0xc416, 0x4a0f, 0xc416, 0x21, 0 + .dw 0x4a11, 0xc416, 0x4a11, 0xc416, 0x21, 0 + .dw 0x4a13, 0xc416, 0x4a3f, 0xc416, 0x21, 0 + .dw 0x4a41, 0xc416, 0x4a41, 0xc416, 0x21, 0 + .dw 0x4a43, 0xc416, 0x4a4f, 0xc416, 0x21, 0 + .dw 0x4a51, 0xc416, 0x4a51, 0xc416, 0x21, 0 + .dw 0x4a53, 0xc416, 0x4a7f, 0xc416, 0x21, 0 + .dw 0x4a81, 0xc416, 0x4a81, 0xc416, 0x21, 0 + .dw 0x4a83, 0xc416, 0x4a8f, 0xc416, 0x21, 0 + .dw 0x4a91, 0xc416, 0x4a91, 0xc416, 0x21, 0 + .dw 0x4a93, 0xc416, 0x4abf, 0xc416, 0x21, 0 + .dw 0x4ac1, 0xc416, 0x4ac1, 0xc416, 0x21, 0 + .dw 0x4ac3, 0xc416, 0x4acf, 0xc416, 0x21, 0 + .dw 0x4ad1, 0xc416, 0x4ad1, 0xc416, 0x21, 0 + .dw 0x4ad3, 0xc416, 0x4aff, 0xc416, 0x21, 0 + .dw 0x4b01, 0xc416, 0x4b01, 0xc416, 0x21, 0 + .dw 0x4b03, 0xc416, 0x4b0f, 0xc416, 0x21, 0 + .dw 0x4b11, 0xc416, 0x4b11, 0xc416, 0x21, 0 + .dw 0x4b13, 0xc416, 0x4b3f, 0xc416, 0x21, 0 + .dw 0x4b41, 0xc416, 0x4b41, 0xc416, 0x21, 0 + .dw 0x4b43, 0xc416, 0x4b4f, 0xc416, 0x21, 0 + .dw 0x4b51, 0xc416, 0x4b51, 0xc416, 0x21, 0 + .dw 0x4b53, 0xc416, 0x4b7f, 0xc416, 0x21, 0 + .dw 0x4b81, 0xc416, 0x4b81, 0xc416, 0x21, 0 + .dw 0x4b83, 0xc416, 0x4b8f, 0xc416, 0x21, 0 + .dw 0x4b91, 0xc416, 0x4b91, 0xc416, 0x21, 0 + .dw 0x4b93, 0xc416, 0x4bbf, 0xc416, 0x21, 0 + .dw 0x4bc1, 0xc416, 0x4bc1, 0xc416, 0x21, 0 + .dw 0x4bc3, 0xc416, 0x4bcf, 0xc416, 0x21, 0 + .dw 0x4bd1, 0xc416, 0x4bd1, 0xc416, 0x21, 0 + .dw 0x4bd3, 0xc416, 0x4bff, 0xc416, 0x21, 0 + .dw 0x4c01, 0xc416, 0x4c01, 0xc416, 0x21, 0 + .dw 0x4c03, 0xc416, 0x4c0f, 0xc416, 0x21, 0 + .dw 0x4c11, 0xc416, 0x4c11, 0xc416, 0x21, 0 + .dw 0x4c13, 0xc416, 0x4c3f, 0xc416, 0x21, 0 + .dw 0x4c41, 0xc416, 0x4c41, 0xc416, 0x21, 0 + .dw 0x4c43, 0xc416, 0x4c4f, 0xc416, 0x21, 0 + .dw 0x4c51, 0xc416, 0x4c51, 0xc416, 0x21, 0 + .dw 0x4c53, 0xc416, 0x4c7f, 0xc416, 0x21, 0 + .dw 0x4c81, 0xc416, 0x4c81, 0xc416, 0x21, 0 + .dw 0x4c83, 0xc416, 0x4c8f, 0xc416, 0x21, 0 + .dw 0x4c91, 0xc416, 0x4c91, 0xc416, 0x21, 0 + .dw 0x4c93, 0xc416, 0x4cbf, 0xc416, 0x21, 0 + .dw 0x4cc1, 0xc416, 0x4cc1, 0xc416, 0x21, 0 + .dw 0x4cc3, 0xc416, 0x4ccf, 0xc416, 0x21, 0 + .dw 0x4cd1, 0xc416, 0x4cd1, 0xc416, 0x21, 0 + .dw 0x4cd3, 0xc416, 0x4cff, 0xc416, 0x21, 0 + .dw 0x4d01, 0xc416, 0x4d01, 0xc416, 0x21, 0 + .dw 0x4d03, 0xc416, 0x4d0f, 0xc416, 0x21, 0 + .dw 0x4d11, 0xc416, 0x4d11, 0xc416, 0x21, 0 + .dw 0x4d13, 0xc416, 0x4d3f, 0xc416, 0x21, 0 + .dw 0x4d41, 0xc416, 0x4d41, 0xc416, 0x21, 0 + .dw 0x4d43, 0xc416, 0x4d4f, 0xc416, 0x21, 0 + .dw 0x4d51, 0xc416, 0x4d51, 0xc416, 0x21, 0 + .dw 0x4d53, 0xc416, 0x4d7f, 0xc416, 0x21, 0 + .dw 0x4d81, 0xc416, 0x4d81, 0xc416, 0x21, 0 + .dw 0x4d83, 0xc416, 0x4d8f, 0xc416, 0x21, 0 + .dw 0x4d91, 0xc416, 0x4d91, 0xc416, 0x21, 0 + .dw 0x4d93, 0xc416, 0x4dbf, 0xc416, 0x21, 0 + .dw 0x4dc1, 0xc416, 0x4dc1, 0xc416, 0x21, 0 + .dw 0x4dc3, 0xc416, 0x4dcf, 0xc416, 0x21, 0 + .dw 0x4dd1, 0xc416, 0x4dd1, 0xc416, 0x21, 0 + .dw 0x4dd3, 0xc416, 0x4dff, 0xc416, 0x21, 0 + .dw 0x4e01, 0xc416, 0x4e01, 0xc416, 0x21, 0 + .dw 0x4e03, 0xc416, 0x4e0f, 0xc416, 0x21, 0 + .dw 0x4e11, 0xc416, 0x4e11, 0xc416, 0x21, 0 + .dw 0x4e13, 0xc416, 0x4e3f, 0xc416, 0x21, 0 + .dw 0x4e41, 0xc416, 0x4e41, 0xc416, 0x21, 0 + .dw 0x4e43, 0xc416, 0x4e4f, 0xc416, 0x21, 0 + .dw 0x4e51, 0xc416, 0x4e51, 0xc416, 0x21, 0 + .dw 0x4e53, 0xc416, 0x4e7f, 0xc416, 0x21, 0 + .dw 0x4e81, 0xc416, 0x4e81, 0xc416, 0x21, 0 + .dw 0x4e83, 0xc416, 0x4e8f, 0xc416, 0x21, 0 + .dw 0x4e91, 0xc416, 0x4e91, 0xc416, 0x21, 0 + .dw 0x4e93, 0xc416, 0x4ebf, 0xc416, 0x21, 0 + .dw 0x4ec1, 0xc416, 0x4ec1, 0xc416, 0x21, 0 + .dw 0x4ec3, 0xc416, 0x4ecf, 0xc416, 0x21, 0 + .dw 0x4ed1, 0xc416, 0x4ed1, 0xc416, 0x21, 0 + .dw 0x4ed3, 0xc416, 0x4eff, 0xc416, 0x21, 0 + .dw 0x4f01, 0xc416, 0x4f01, 0xc416, 0x21, 0 + .dw 0x4f03, 0xc416, 0x4f0f, 0xc416, 0x21, 0 + .dw 0x4f11, 0xc416, 0x4f11, 0xc416, 0x21, 0 + .dw 0x4f13, 0xc416, 0x4f3f, 0xc416, 0x21, 0 + .dw 0x4f41, 0xc416, 0x4f41, 0xc416, 0x21, 0 + .dw 0x4f43, 0xc416, 0x4f4f, 0xc416, 0x21, 0 + .dw 0x4f51, 0xc416, 0x4f51, 0xc416, 0x21, 0 + .dw 0x4f53, 0xc416, 0x4f7f, 0xc416, 0x21, 0 + .dw 0x4f81, 0xc416, 0x4f81, 0xc416, 0x21, 0 + .dw 0x4f83, 0xc416, 0x4f8f, 0xc416, 0x21, 0 + .dw 0x4f91, 0xc416, 0x4f91, 0xc416, 0x21, 0 + .dw 0x4f93, 0xc416, 0x4fbf, 0xc416, 0x21, 0 + .dw 0x4fc1, 0xc416, 0x4fc1, 0xc416, 0x21, 0 + .dw 0x4fc3, 0xc416, 0x4fcf, 0xc416, 0x21, 0 + .dw 0x4fd1, 0xc416, 0x4fd1, 0xc416, 0x21, 0 + .dw 0x4fd3, 0xc416, 0x5fff, 0xc416, 0x21, 0 + .dw 0x6001, 0xc416, 0x6001, 0xc416, 0x21, 0 + .dw 0x6003, 0xc416, 0x600f, 0xc416, 0x21, 0 + .dw 0x6011, 0xc416, 0x6011, 0xc416, 0x21, 0 + .dw 0x6013, 0xc416, 0x603f, 0xc416, 0x21, 0 + .dw 0x6041, 0xc416, 0x6041, 0xc416, 0x21, 0 + .dw 0x6043, 0xc416, 0x604f, 0xc416, 0x21, 0 + .dw 0x6051, 0xc416, 0x6051, 0xc416, 0x21, 0 + .dw 0x6053, 0xc416, 0x607f, 0xc416, 0x21, 0 + .dw 0x6081, 0xc416, 0x6081, 0xc416, 0x21, 0 + .dw 0x6083, 0xc416, 0x608f, 0xc416, 0x21, 0 + .dw 0x6091, 0xc416, 0x6091, 0xc416, 0x21, 0 + .dw 0x6093, 0xc416, 0x60bf, 0xc416, 0x21, 0 + .dw 0x60c1, 0xc416, 0x60c1, 0xc416, 0x21, 0 + .dw 0x60c3, 0xc416, 0x60cf, 0xc416, 0x21, 0 + .dw 0x60d1, 0xc416, 0x60d1, 0xc416, 0x21, 0 + .dw 0x60d3, 0xc416, 0x60ff, 0xc416, 0x21, 0 + .dw 0x6101, 0xc416, 0x6101, 0xc416, 0x21, 0 + .dw 0x6103, 0xc416, 0x610f, 0xc416, 0x21, 0 + .dw 0x6111, 0xc416, 0x6111, 0xc416, 0x21, 0 + .dw 0x6113, 0xc416, 0x613f, 0xc416, 0x21, 0 + .dw 0x6141, 0xc416, 0x6141, 0xc416, 0x21, 0 + .dw 0x6143, 0xc416, 0x614f, 0xc416, 0x21, 0 + .dw 0x6151, 0xc416, 0x6151, 0xc416, 0x21, 0 + .dw 0x6153, 0xc416, 0x617f, 0xc416, 0x21, 0 + .dw 0x6181, 0xc416, 0x6181, 0xc416, 0x21, 0 + .dw 0x6183, 0xc416, 0x618f, 0xc416, 0x21, 0 + .dw 0x6191, 0xc416, 0x6191, 0xc416, 0x21, 0 + .dw 0x6193, 0xc416, 0x61bf, 0xc416, 0x21, 0 + .dw 0x61c1, 0xc416, 0x61c1, 0xc416, 0x21, 0 + .dw 0x61c3, 0xc416, 0x61cf, 0xc416, 0x21, 0 + .dw 0x61d1, 0xc416, 0x61d1, 0xc416, 0x21, 0 + .dw 0x61d3, 0xc416, 0x61ff, 0xc416, 0x21, 0 + .dw 0x6201, 0xc416, 0x6201, 0xc416, 0x21, 0 + .dw 0x6203, 0xc416, 0x620f, 0xc416, 0x21, 0 + .dw 0x6211, 0xc416, 0x6211, 0xc416, 0x21, 0 + .dw 0x6213, 0xc416, 0x623f, 0xc416, 0x21, 0 + .dw 0x6241, 0xc416, 0x6241, 0xc416, 0x21, 0 + .dw 0x6243, 0xc416, 0x624f, 0xc416, 0x21, 0 + .dw 0x6251, 0xc416, 0x6251, 0xc416, 0x21, 0 + .dw 0x6253, 0xc416, 0x627f, 0xc416, 0x21, 0 + .dw 0x6281, 0xc416, 0x6281, 0xc416, 0x21, 0 + .dw 0x6283, 0xc416, 0x628f, 0xc416, 0x21, 0 + .dw 0x6291, 0xc416, 0x6291, 0xc416, 0x21, 0 + .dw 0x6293, 0xc416, 0x62bf, 0xc416, 0x21, 0 + .dw 0x62c1, 0xc416, 0x62c1, 0xc416, 0x21, 0 + .dw 0x62c3, 0xc416, 0x62cf, 0xc416, 0x21, 0 + .dw 0x62d1, 0xc416, 0x62d1, 0xc416, 0x21, 0 + .dw 0x62d3, 0xc416, 0x62ff, 0xc416, 0x21, 0 + .dw 0x6301, 0xc416, 0x6301, 0xc416, 0x21, 0 + .dw 0x6303, 0xc416, 0x630f, 0xc416, 0x21, 0 + .dw 0x6311, 0xc416, 0x6311, 0xc416, 0x21, 0 + .dw 0x6313, 0xc416, 0x633f, 0xc416, 0x21, 0 + .dw 0x6341, 0xc416, 0x6341, 0xc416, 0x21, 0 + .dw 0x6343, 0xc416, 0x634f, 0xc416, 0x21, 0 + .dw 0x6351, 0xc416, 0x6351, 0xc416, 0x21, 0 + .dw 0x6353, 0xc416, 0x637f, 0xc416, 0x21, 0 + .dw 0x6381, 0xc416, 0x6381, 0xc416, 0x21, 0 + .dw 0x6383, 0xc416, 0x638f, 0xc416, 0x21, 0 + .dw 0x6391, 0xc416, 0x6391, 0xc416, 0x21, 0 + .dw 0x6393, 0xc416, 0x63bf, 0xc416, 0x21, 0 + .dw 0x63c1, 0xc416, 0x63c1, 0xc416, 0x21, 0 + .dw 0x63c3, 0xc416, 0x63cf, 0xc416, 0x21, 0 + .dw 0x63d1, 0xc416, 0x63d1, 0xc416, 0x21, 0 + .dw 0x63d3, 0xc416, 0x63ff, 0xc416, 0x21, 0 + .dw 0x6401, 0xc416, 0x6401, 0xc416, 0x21, 0 + .dw 0x6403, 0xc416, 0x640f, 0xc416, 0x21, 0 + .dw 0x6411, 0xc416, 0x6411, 0xc416, 0x21, 0 + .dw 0x6413, 0xc416, 0x643f, 0xc416, 0x21, 0 + .dw 0x6441, 0xc416, 0x6441, 0xc416, 0x21, 0 + .dw 0x6443, 0xc416, 0x644f, 0xc416, 0x21, 0 + .dw 0x6451, 0xc416, 0x6451, 0xc416, 0x21, 0 + .dw 0x6453, 0xc416, 0x647f, 0xc416, 0x21, 0 + .dw 0x6481, 0xc416, 0x6481, 0xc416, 0x21, 0 + .dw 0x6483, 0xc416, 0x648f, 0xc416, 0x21, 0 + .dw 0x6491, 0xc416, 0x6491, 0xc416, 0x21, 0 + .dw 0x6493, 0xc416, 0x64bf, 0xc416, 0x21, 0 + .dw 0x64c1, 0xc416, 0x64c1, 0xc416, 0x21, 0 + .dw 0x64c3, 0xc416, 0x64cf, 0xc416, 0x21, 0 + .dw 0x64d1, 0xc416, 0x64d1, 0xc416, 0x21, 0 + .dw 0x64d3, 0xc416, 0x64ff, 0xc416, 0x21, 0 + .dw 0x6501, 0xc416, 0x6501, 0xc416, 0x21, 0 + .dw 0x6503, 0xc416, 0x650f, 0xc416, 0x21, 0 + .dw 0x6511, 0xc416, 0x6511, 0xc416, 0x21, 0 + .dw 0x6513, 0xc416, 0x653f, 0xc416, 0x21, 0 + .dw 0x6541, 0xc416, 0x6541, 0xc416, 0x21, 0 + .dw 0x6543, 0xc416, 0x654f, 0xc416, 0x21, 0 + .dw 0x6551, 0xc416, 0x6551, 0xc416, 0x21, 0 + .dw 0x6553, 0xc416, 0x657f, 0xc416, 0x21, 0 + .dw 0x6581, 0xc416, 0x6581, 0xc416, 0x21, 0 + .dw 0x6583, 0xc416, 0x658f, 0xc416, 0x21, 0 + .dw 0x6591, 0xc416, 0x6591, 0xc416, 0x21, 0 + .dw 0x6593, 0xc416, 0x65bf, 0xc416, 0x21, 0 + .dw 0x65c1, 0xc416, 0x65c1, 0xc416, 0x21, 0 + .dw 0x65c3, 0xc416, 0x65cf, 0xc416, 0x21, 0 + .dw 0x65d1, 0xc416, 0x65d1, 0xc416, 0x21, 0 + .dw 0x65d3, 0xc416, 0x65ff, 0xc416, 0x21, 0 + .dw 0x6601, 0xc416, 0x6601, 0xc416, 0x21, 0 + .dw 0x6603, 0xc416, 0x660f, 0xc416, 0x21, 0 + .dw 0x6611, 0xc416, 0x6611, 0xc416, 0x21, 0 + .dw 0x6613, 0xc416, 0x663f, 0xc416, 0x21, 0 + .dw 0x6641, 0xc416, 0x6641, 0xc416, 0x21, 0 + .dw 0x6643, 0xc416, 0x664f, 0xc416, 0x21, 0 + .dw 0x6651, 0xc416, 0x6651, 0xc416, 0x21, 0 + .dw 0x6653, 0xc416, 0x667f, 0xc416, 0x21, 0 + .dw 0x6681, 0xc416, 0x6681, 0xc416, 0x21, 0 + .dw 0x6683, 0xc416, 0x668f, 0xc416, 0x21, 0 + .dw 0x6691, 0xc416, 0x6691, 0xc416, 0x21, 0 + .dw 0x6693, 0xc416, 0x66bf, 0xc416, 0x21, 0 + .dw 0x66c1, 0xc416, 0x66c1, 0xc416, 0x21, 0 + .dw 0x66c3, 0xc416, 0x66cf, 0xc416, 0x21, 0 + .dw 0x66d1, 0xc416, 0x66d1, 0xc416, 0x21, 0 + .dw 0x66d3, 0xc416, 0x66ff, 0xc416, 0x21, 0 + .dw 0x6701, 0xc416, 0x6701, 0xc416, 0x21, 0 + .dw 0x6703, 0xc416, 0x670f, 0xc416, 0x21, 0 + .dw 0x6711, 0xc416, 0x6711, 0xc416, 0x21, 0 + .dw 0x6713, 0xc416, 0x673f, 0xc416, 0x21, 0 + .dw 0x6741, 0xc416, 0x6741, 0xc416, 0x21, 0 + .dw 0x6743, 0xc416, 0x674f, 0xc416, 0x21, 0 + .dw 0x6751, 0xc416, 0x6751, 0xc416, 0x21, 0 + .dw 0x6753, 0xc416, 0x677f, 0xc416, 0x21, 0 + .dw 0x6781, 0xc416, 0x6781, 0xc416, 0x21, 0 + .dw 0x6783, 0xc416, 0x678f, 0xc416, 0x21, 0 + .dw 0x6791, 0xc416, 0x6791, 0xc416, 0x21, 0 + .dw 0x6793, 0xc416, 0x67bf, 0xc416, 0x21, 0 + .dw 0x67c1, 0xc416, 0x67c1, 0xc416, 0x21, 0 + .dw 0x67c3, 0xc416, 0x67cf, 0xc416, 0x21, 0 + .dw 0x67d1, 0xc416, 0x67d1, 0xc416, 0x21, 0 + .dw 0x67d3, 0xc416, 0x67ff, 0xc416, 0x21, 0 + .dw 0x6801, 0xc416, 0x6801, 0xc416, 0x21, 0 + .dw 0x6803, 0xc416, 0x680f, 0xc416, 0x21, 0 + .dw 0x6811, 0xc416, 0x6811, 0xc416, 0x21, 0 + .dw 0x6813, 0xc416, 0x683f, 0xc416, 0x21, 0 + .dw 0x6841, 0xc416, 0x6841, 0xc416, 0x21, 0 + .dw 0x6843, 0xc416, 0x684f, 0xc416, 0x21, 0 + .dw 0x6851, 0xc416, 0x6851, 0xc416, 0x21, 0 + .dw 0x6853, 0xc416, 0x687f, 0xc416, 0x21, 0 + .dw 0x6881, 0xc416, 0x6881, 0xc416, 0x21, 0 + .dw 0x6883, 0xc416, 0x688f, 0xc416, 0x21, 0 + .dw 0x6891, 0xc416, 0x6891, 0xc416, 0x21, 0 + .dw 0x6893, 0xc416, 0x68bf, 0xc416, 0x21, 0 + .dw 0x68c1, 0xc416, 0x68c1, 0xc416, 0x21, 0 + .dw 0x68c3, 0xc416, 0x68cf, 0xc416, 0x21, 0 + .dw 0x68d1, 0xc416, 0x68d1, 0xc416, 0x21, 0 + .dw 0x68d3, 0xc416, 0x68ff, 0xc416, 0x21, 0 + .dw 0x6901, 0xc416, 0x6901, 0xc416, 0x21, 0 + .dw 0x6903, 0xc416, 0x690f, 0xc416, 0x21, 0 + .dw 0x6911, 0xc416, 0x6911, 0xc416, 0x21, 0 + .dw 0x6913, 0xc416, 0x693f, 0xc416, 0x21, 0 + .dw 0x6941, 0xc416, 0x6941, 0xc416, 0x21, 0 + .dw 0x6943, 0xc416, 0x694f, 0xc416, 0x21, 0 + .dw 0x6951, 0xc416, 0x6951, 0xc416, 0x21, 0 + .dw 0x6953, 0xc416, 0x697f, 0xc416, 0x21, 0 + .dw 0x6981, 0xc416, 0x6981, 0xc416, 0x21, 0 + .dw 0x6983, 0xc416, 0x698f, 0xc416, 0x21, 0 + .dw 0x6991, 0xc416, 0x6991, 0xc416, 0x21, 0 + .dw 0x6993, 0xc416, 0x69bf, 0xc416, 0x21, 0 + .dw 0x69c1, 0xc416, 0x69c1, 0xc416, 0x21, 0 + .dw 0x69c3, 0xc416, 0x69cf, 0xc416, 0x21, 0 + .dw 0x69d1, 0xc416, 0x69d1, 0xc416, 0x21, 0 + .dw 0x69d3, 0xc416, 0x69ff, 0xc416, 0x21, 0 + .dw 0x6a01, 0xc416, 0x6a01, 0xc416, 0x21, 0 + .dw 0x6a03, 0xc416, 0x6a0f, 0xc416, 0x21, 0 + .dw 0x6a11, 0xc416, 0x6a11, 0xc416, 0x21, 0 + .dw 0x6a13, 0xc416, 0x6a3f, 0xc416, 0x21, 0 + .dw 0x6a41, 0xc416, 0x6a41, 0xc416, 0x21, 0 + .dw 0x6a43, 0xc416, 0x6a4f, 0xc416, 0x21, 0 + .dw 0x6a51, 0xc416, 0x6a51, 0xc416, 0x21, 0 + .dw 0x6a53, 0xc416, 0x6a7f, 0xc416, 0x21, 0 + .dw 0x6a81, 0xc416, 0x6a81, 0xc416, 0x21, 0 + .dw 0x6a83, 0xc416, 0x6a8f, 0xc416, 0x21, 0 + .dw 0x6a91, 0xc416, 0x6a91, 0xc416, 0x21, 0 + .dw 0x6a93, 0xc416, 0x6abf, 0xc416, 0x21, 0 + .dw 0x6ac1, 0xc416, 0x6ac1, 0xc416, 0x21, 0 + .dw 0x6ac3, 0xc416, 0x6acf, 0xc416, 0x21, 0 + .dw 0x6ad1, 0xc416, 0x6ad1, 0xc416, 0x21, 0 + .dw 0x6ad3, 0xc416, 0x6aff, 0xc416, 0x21, 0 + .dw 0x6b01, 0xc416, 0x6b01, 0xc416, 0x21, 0 + .dw 0x6b03, 0xc416, 0x6b0f, 0xc416, 0x21, 0 + .dw 0x6b11, 0xc416, 0x6b11, 0xc416, 0x21, 0 + .dw 0x6b13, 0xc416, 0x6b3f, 0xc416, 0x21, 0 + .dw 0x6b41, 0xc416, 0x6b41, 0xc416, 0x21, 0 + .dw 0x6b43, 0xc416, 0x6b4f, 0xc416, 0x21, 0 + .dw 0x6b51, 0xc416, 0x6b51, 0xc416, 0x21, 0 + .dw 0x6b53, 0xc416, 0x6b7f, 0xc416, 0x21, 0 + .dw 0x6b81, 0xc416, 0x6b81, 0xc416, 0x21, 0 + .dw 0x6b83, 0xc416, 0x6b8f, 0xc416, 0x21, 0 + .dw 0x6b91, 0xc416, 0x6b91, 0xc416, 0x21, 0 + .dw 0x6b93, 0xc416, 0x6bbf, 0xc416, 0x21, 0 + .dw 0x6bc1, 0xc416, 0x6bc1, 0xc416, 0x21, 0 + .dw 0x6bc3, 0xc416, 0x6bcf, 0xc416, 0x21, 0 + .dw 0x6bd1, 0xc416, 0x6bd1, 0xc416, 0x21, 0 + .dw 0x6bd3, 0xc416, 0x6bff, 0xc416, 0x21, 0 + .dw 0x6c01, 0xc416, 0x6c01, 0xc416, 0x21, 0 + .dw 0x6c03, 0xc416, 0x6c0f, 0xc416, 0x21, 0 + .dw 0x6c11, 0xc416, 0x6c11, 0xc416, 0x21, 0 + .dw 0x6c13, 0xc416, 0x6c3f, 0xc416, 0x21, 0 + .dw 0x6c41, 0xc416, 0x6c41, 0xc416, 0x21, 0 + .dw 0x6c43, 0xc416, 0x6c4f, 0xc416, 0x21, 0 + .dw 0x6c51, 0xc416, 0x6c51, 0xc416, 0x21, 0 + .dw 0x6c53, 0xc416, 0x6c7f, 0xc416, 0x21, 0 + .dw 0x6c81, 0xc416, 0x6c81, 0xc416, 0x21, 0 + .dw 0x6c83, 0xc416, 0x6c8f, 0xc416, 0x21, 0 + .dw 0x6c91, 0xc416, 0x6c91, 0xc416, 0x21, 0 + .dw 0x6c93, 0xc416, 0x6cbf, 0xc416, 0x21, 0 + .dw 0x6cc1, 0xc416, 0x6cc1, 0xc416, 0x21, 0 + .dw 0x6cc3, 0xc416, 0x6ccf, 0xc416, 0x21, 0 + .dw 0x6cd1, 0xc416, 0x6cd1, 0xc416, 0x21, 0 + .dw 0x6cd3, 0xc416, 0x6cff, 0xc416, 0x21, 0 + .dw 0x6d01, 0xc416, 0x6d01, 0xc416, 0x21, 0 + .dw 0x6d03, 0xc416, 0x6d0f, 0xc416, 0x21, 0 + .dw 0x6d11, 0xc416, 0x6d11, 0xc416, 0x21, 0 + .dw 0x6d13, 0xc416, 0x6d3f, 0xc416, 0x21, 0 + .dw 0x6d41, 0xc416, 0x6d41, 0xc416, 0x21, 0 + .dw 0x6d43, 0xc416, 0x6d4f, 0xc416, 0x21, 0 + .dw 0x6d51, 0xc416, 0x6d51, 0xc416, 0x21, 0 + .dw 0x6d53, 0xc416, 0x6d7f, 0xc416, 0x21, 0 + .dw 0x6d81, 0xc416, 0x6d81, 0xc416, 0x21, 0 + .dw 0x6d83, 0xc416, 0x6d8f, 0xc416, 0x21, 0 + .dw 0x6d91, 0xc416, 0x6d91, 0xc416, 0x21, 0 + .dw 0x6d93, 0xc416, 0x6dbf, 0xc416, 0x21, 0 + .dw 0x6dc1, 0xc416, 0x6dc1, 0xc416, 0x21, 0 + .dw 0x6dc3, 0xc416, 0x6dcf, 0xc416, 0x21, 0 + .dw 0x6dd1, 0xc416, 0x6dd1, 0xc416, 0x21, 0 + .dw 0x6dd3, 0xc416, 0x6dff, 0xc416, 0x21, 0 + .dw 0x6e01, 0xc416, 0x6e01, 0xc416, 0x21, 0 + .dw 0x6e03, 0xc416, 0x6e0f, 0xc416, 0x21, 0 + .dw 0x6e11, 0xc416, 0x6e11, 0xc416, 0x21, 0 + .dw 0x6e13, 0xc416, 0x6e3f, 0xc416, 0x21, 0 + .dw 0x6e41, 0xc416, 0x6e41, 0xc416, 0x21, 0 + .dw 0x6e43, 0xc416, 0x6e4f, 0xc416, 0x21, 0 + .dw 0x6e51, 0xc416, 0x6e51, 0xc416, 0x21, 0 + .dw 0x6e53, 0xc416, 0x6e7f, 0xc416, 0x21, 0 + .dw 0x6e81, 0xc416, 0x6e81, 0xc416, 0x21, 0 + .dw 0x6e83, 0xc416, 0x6e8f, 0xc416, 0x21, 0 + .dw 0x6e91, 0xc416, 0x6e91, 0xc416, 0x21, 0 + .dw 0x6e93, 0xc416, 0x6ebf, 0xc416, 0x21, 0 + .dw 0x6ec1, 0xc416, 0x6ec1, 0xc416, 0x21, 0 + .dw 0x6ec3, 0xc416, 0x6ecf, 0xc416, 0x21, 0 + .dw 0x6ed1, 0xc416, 0x6ed1, 0xc416, 0x21, 0 + .dw 0x6ed3, 0xc416, 0x6eff, 0xc416, 0x21, 0 + .dw 0x6f01, 0xc416, 0x6f01, 0xc416, 0x21, 0 + .dw 0x6f03, 0xc416, 0x6f0f, 0xc416, 0x21, 0 + .dw 0x6f11, 0xc416, 0x6f11, 0xc416, 0x21, 0 + .dw 0x6f13, 0xc416, 0x6f3f, 0xc416, 0x21, 0 + .dw 0x6f41, 0xc416, 0x6f41, 0xc416, 0x21, 0 + .dw 0x6f43, 0xc416, 0x6f4f, 0xc416, 0x21, 0 + .dw 0x6f51, 0xc416, 0x6f51, 0xc416, 0x21, 0 + .dw 0x6f53, 0xc416, 0x6f7f, 0xc416, 0x21, 0 + .dw 0x6f81, 0xc416, 0x6f81, 0xc416, 0x21, 0 + .dw 0x6f83, 0xc416, 0x6f8f, 0xc416, 0x21, 0 + .dw 0x6f91, 0xc416, 0x6f91, 0xc416, 0x21, 0 + .dw 0x6f93, 0xc416, 0x6fbf, 0xc416, 0x21, 0 + .dw 0x6fc1, 0xc416, 0x6fc1, 0xc416, 0x21, 0 + .dw 0x6fc3, 0xc416, 0x6fcf, 0xc416, 0x21, 0 + .dw 0x6fd1, 0xc416, 0x6fd1, 0xc416, 0x21, 0 + .dw 0x6fd3, 0xc416, 0xffff, 0xc416, 0x21, 0 + .dw 0x0001, 0xc417, 0x0001, 0xc417, 0x21, 0 + .dw 0x0003, 0xc417, 0x000f, 0xc417, 0x21, 0 + .dw 0x0011, 0xc417, 0x0011, 0xc417, 0x21, 0 + .dw 0x0013, 0xc417, 0x003f, 0xc417, 0x21, 0 + .dw 0x0041, 0xc417, 0x0041, 0xc417, 0x21, 0 + .dw 0x0043, 0xc417, 0x004f, 0xc417, 0x21, 0 + .dw 0x0051, 0xc417, 0x0051, 0xc417, 0x21, 0 + .dw 0x0053, 0xc417, 0x007f, 0xc417, 0x21, 0 + .dw 0x0081, 0xc417, 0x0081, 0xc417, 0x21, 0 + .dw 0x0083, 0xc417, 0x008f, 0xc417, 0x21, 0 + .dw 0x0091, 0xc417, 0x0091, 0xc417, 0x21, 0 + .dw 0x0093, 0xc417, 0x00bf, 0xc417, 0x21, 0 + .dw 0x00c1, 0xc417, 0x00c1, 0xc417, 0x21, 0 + .dw 0x00c3, 0xc417, 0x00cf, 0xc417, 0x21, 0 + .dw 0x00d1, 0xc417, 0x00d1, 0xc417, 0x21, 0 + .dw 0x00d3, 0xc417, 0x00ff, 0xc417, 0x21, 0 + .dw 0x0101, 0xc417, 0x0101, 0xc417, 0x21, 0 + .dw 0x0103, 0xc417, 0x010f, 0xc417, 0x21, 0 + .dw 0x0111, 0xc417, 0x0111, 0xc417, 0x21, 0 + .dw 0x0113, 0xc417, 0x013f, 0xc417, 0x21, 0 + .dw 0x0141, 0xc417, 0x0141, 0xc417, 0x21, 0 + .dw 0x0143, 0xc417, 0x014f, 0xc417, 0x21, 0 + .dw 0x0151, 0xc417, 0x0151, 0xc417, 0x21, 0 + .dw 0x0153, 0xc417, 0x017f, 0xc417, 0x21, 0 + .dw 0x0181, 0xc417, 0x0181, 0xc417, 0x21, 0 + .dw 0x0183, 0xc417, 0x018f, 0xc417, 0x21, 0 + .dw 0x0191, 0xc417, 0x0191, 0xc417, 0x21, 0 + .dw 0x0193, 0xc417, 0x01bf, 0xc417, 0x21, 0 + .dw 0x01c1, 0xc417, 0x01c1, 0xc417, 0x21, 0 + .dw 0x01c3, 0xc417, 0x01cf, 0xc417, 0x21, 0 + .dw 0x01d1, 0xc417, 0x01d1, 0xc417, 0x21, 0 + .dw 0x01d3, 0xc417, 0x01ff, 0xc417, 0x21, 0 + .dw 0x0201, 0xc417, 0x0201, 0xc417, 0x21, 0 + .dw 0x0203, 0xc417, 0x020f, 0xc417, 0x21, 0 + .dw 0x0211, 0xc417, 0x0211, 0xc417, 0x21, 0 + .dw 0x0213, 0xc417, 0x023f, 0xc417, 0x21, 0 + .dw 0x0241, 0xc417, 0x0241, 0xc417, 0x21, 0 + .dw 0x0243, 0xc417, 0x024f, 0xc417, 0x21, 0 + .dw 0x0251, 0xc417, 0x0251, 0xc417, 0x21, 0 + .dw 0x0253, 0xc417, 0x027f, 0xc417, 0x21, 0 + .dw 0x0281, 0xc417, 0x0281, 0xc417, 0x21, 0 + .dw 0x0283, 0xc417, 0x028f, 0xc417, 0x21, 0 + .dw 0x0291, 0xc417, 0x0291, 0xc417, 0x21, 0 + .dw 0x0293, 0xc417, 0x02bf, 0xc417, 0x21, 0 + .dw 0x02c1, 0xc417, 0x02c1, 0xc417, 0x21, 0 + .dw 0x02c3, 0xc417, 0x02cf, 0xc417, 0x21, 0 + .dw 0x02d1, 0xc417, 0x02d1, 0xc417, 0x21, 0 + .dw 0x02d3, 0xc417, 0x02ff, 0xc417, 0x21, 0 + .dw 0x0301, 0xc417, 0x0301, 0xc417, 0x21, 0 + .dw 0x0303, 0xc417, 0x030f, 0xc417, 0x21, 0 + .dw 0x0311, 0xc417, 0x0311, 0xc417, 0x21, 0 + .dw 0x0313, 0xc417, 0x033f, 0xc417, 0x21, 0 + .dw 0x0341, 0xc417, 0x0341, 0xc417, 0x21, 0 + .dw 0x0343, 0xc417, 0x034f, 0xc417, 0x21, 0 + .dw 0x0351, 0xc417, 0x0351, 0xc417, 0x21, 0 + .dw 0x0353, 0xc417, 0x037f, 0xc417, 0x21, 0 + .dw 0x0381, 0xc417, 0x0381, 0xc417, 0x21, 0 + .dw 0x0383, 0xc417, 0x038f, 0xc417, 0x21, 0 + .dw 0x0391, 0xc417, 0x0391, 0xc417, 0x21, 0 + .dw 0x0393, 0xc417, 0x03bf, 0xc417, 0x21, 0 + .dw 0x03c1, 0xc417, 0x03c1, 0xc417, 0x21, 0 + .dw 0x03c3, 0xc417, 0x03cf, 0xc417, 0x21, 0 + .dw 0x03d1, 0xc417, 0x03d1, 0xc417, 0x21, 0 + .dw 0x03d3, 0xc417, 0x03ff, 0xc417, 0x21, 0 + .dw 0x0401, 0xc417, 0x0401, 0xc417, 0x21, 0 + .dw 0x0403, 0xc417, 0x040f, 0xc417, 0x21, 0 + .dw 0x0411, 0xc417, 0x0411, 0xc417, 0x21, 0 + .dw 0x0413, 0xc417, 0x043f, 0xc417, 0x21, 0 + .dw 0x0441, 0xc417, 0x0441, 0xc417, 0x21, 0 + .dw 0x0443, 0xc417, 0x044f, 0xc417, 0x21, 0 + .dw 0x0451, 0xc417, 0x0451, 0xc417, 0x21, 0 + .dw 0x0453, 0xc417, 0x047f, 0xc417, 0x21, 0 + .dw 0x0481, 0xc417, 0x0481, 0xc417, 0x21, 0 + .dw 0x0483, 0xc417, 0x048f, 0xc417, 0x21, 0 + .dw 0x0491, 0xc417, 0x0491, 0xc417, 0x21, 0 + .dw 0x0493, 0xc417, 0x04bf, 0xc417, 0x21, 0 + .dw 0x04c1, 0xc417, 0x04c1, 0xc417, 0x21, 0 + .dw 0x04c3, 0xc417, 0x04cf, 0xc417, 0x21, 0 + .dw 0x04d1, 0xc417, 0x04d1, 0xc417, 0x21, 0 + .dw 0x04d3, 0xc417, 0x04ff, 0xc417, 0x21, 0 + .dw 0x0501, 0xc417, 0x0501, 0xc417, 0x21, 0 + .dw 0x0503, 0xc417, 0x050f, 0xc417, 0x21, 0 + .dw 0x0511, 0xc417, 0x0511, 0xc417, 0x21, 0 + .dw 0x0513, 0xc417, 0x053f, 0xc417, 0x21, 0 + .dw 0x0541, 0xc417, 0x0541, 0xc417, 0x21, 0 + .dw 0x0543, 0xc417, 0x054f, 0xc417, 0x21, 0 + .dw 0x0551, 0xc417, 0x0551, 0xc417, 0x21, 0 + .dw 0x0553, 0xc417, 0x057f, 0xc417, 0x21, 0 + .dw 0x0581, 0xc417, 0x0581, 0xc417, 0x21, 0 + .dw 0x0583, 0xc417, 0x058f, 0xc417, 0x21, 0 + .dw 0x0591, 0xc417, 0x0591, 0xc417, 0x21, 0 + .dw 0x0593, 0xc417, 0x05bf, 0xc417, 0x21, 0 + .dw 0x05c1, 0xc417, 0x05c1, 0xc417, 0x21, 0 + .dw 0x05c3, 0xc417, 0x05cf, 0xc417, 0x21, 0 + .dw 0x05d1, 0xc417, 0x05d1, 0xc417, 0x21, 0 + .dw 0x05d3, 0xc417, 0x05ff, 0xc417, 0x21, 0 + .dw 0x0601, 0xc417, 0x0601, 0xc417, 0x21, 0 + .dw 0x0603, 0xc417, 0x060f, 0xc417, 0x21, 0 + .dw 0x0611, 0xc417, 0x0611, 0xc417, 0x21, 0 + .dw 0x0613, 0xc417, 0x063f, 0xc417, 0x21, 0 + .dw 0x0641, 0xc417, 0x0641, 0xc417, 0x21, 0 + .dw 0x0643, 0xc417, 0x064f, 0xc417, 0x21, 0 + .dw 0x0651, 0xc417, 0x0651, 0xc417, 0x21, 0 + .dw 0x0653, 0xc417, 0x067f, 0xc417, 0x21, 0 + .dw 0x0681, 0xc417, 0x0681, 0xc417, 0x21, 0 + .dw 0x0683, 0xc417, 0x068f, 0xc417, 0x21, 0 + .dw 0x0691, 0xc417, 0x0691, 0xc417, 0x21, 0 + .dw 0x0693, 0xc417, 0x06bf, 0xc417, 0x21, 0 + .dw 0x06c1, 0xc417, 0x06c1, 0xc417, 0x21, 0 + .dw 0x06c3, 0xc417, 0x06cf, 0xc417, 0x21, 0 + .dw 0x06d1, 0xc417, 0x06d1, 0xc417, 0x21, 0 + .dw 0x06d3, 0xc417, 0x06ff, 0xc417, 0x21, 0 + .dw 0x0701, 0xc417, 0x0701, 0xc417, 0x21, 0 + .dw 0x0703, 0xc417, 0x070f, 0xc417, 0x21, 0 + .dw 0x0711, 0xc417, 0x0711, 0xc417, 0x21, 0 + .dw 0x0713, 0xc417, 0x073f, 0xc417, 0x21, 0 + .dw 0x0741, 0xc417, 0x0741, 0xc417, 0x21, 0 + .dw 0x0743, 0xc417, 0x074f, 0xc417, 0x21, 0 + .dw 0x0751, 0xc417, 0x0751, 0xc417, 0x21, 0 + .dw 0x0753, 0xc417, 0x077f, 0xc417, 0x21, 0 + .dw 0x0781, 0xc417, 0x0781, 0xc417, 0x21, 0 + .dw 0x0783, 0xc417, 0x078f, 0xc417, 0x21, 0 + .dw 0x0791, 0xc417, 0x0791, 0xc417, 0x21, 0 + .dw 0x0793, 0xc417, 0x07bf, 0xc417, 0x21, 0 + .dw 0x07c1, 0xc417, 0x07c1, 0xc417, 0x21, 0 + .dw 0x07c3, 0xc417, 0x07cf, 0xc417, 0x21, 0 + .dw 0x07d1, 0xc417, 0x07d1, 0xc417, 0x21, 0 + .dw 0x07d3, 0xc417, 0x07ff, 0xc417, 0x21, 0 + .dw 0x0801, 0xc417, 0x0801, 0xc417, 0x21, 0 + .dw 0x0803, 0xc417, 0x080f, 0xc417, 0x21, 0 + .dw 0x0811, 0xc417, 0x0811, 0xc417, 0x21, 0 + .dw 0x0813, 0xc417, 0x083f, 0xc417, 0x21, 0 + .dw 0x0841, 0xc417, 0x0841, 0xc417, 0x21, 0 + .dw 0x0843, 0xc417, 0x084f, 0xc417, 0x21, 0 + .dw 0x0851, 0xc417, 0x0851, 0xc417, 0x21, 0 + .dw 0x0853, 0xc417, 0x087f, 0xc417, 0x21, 0 + .dw 0x0881, 0xc417, 0x0881, 0xc417, 0x21, 0 + .dw 0x0883, 0xc417, 0x088f, 0xc417, 0x21, 0 + .dw 0x0891, 0xc417, 0x0891, 0xc417, 0x21, 0 + .dw 0x0893, 0xc417, 0x08bf, 0xc417, 0x21, 0 + .dw 0x08c1, 0xc417, 0x08c1, 0xc417, 0x21, 0 + .dw 0x08c3, 0xc417, 0x08cf, 0xc417, 0x21, 0 + .dw 0x08d1, 0xc417, 0x08d1, 0xc417, 0x21, 0 + .dw 0x08d3, 0xc417, 0x08ff, 0xc417, 0x21, 0 + .dw 0x0901, 0xc417, 0x0901, 0xc417, 0x21, 0 + .dw 0x0903, 0xc417, 0x090f, 0xc417, 0x21, 0 + .dw 0x0911, 0xc417, 0x0911, 0xc417, 0x21, 0 + .dw 0x0913, 0xc417, 0x093f, 0xc417, 0x21, 0 + .dw 0x0941, 0xc417, 0x0941, 0xc417, 0x21, 0 + .dw 0x0943, 0xc417, 0x094f, 0xc417, 0x21, 0 + .dw 0x0951, 0xc417, 0x0951, 0xc417, 0x21, 0 + .dw 0x0953, 0xc417, 0x097f, 0xc417, 0x21, 0 + .dw 0x0981, 0xc417, 0x0981, 0xc417, 0x21, 0 + .dw 0x0983, 0xc417, 0x098f, 0xc417, 0x21, 0 + .dw 0x0991, 0xc417, 0x0991, 0xc417, 0x21, 0 + .dw 0x0993, 0xc417, 0x09bf, 0xc417, 0x21, 0 + .dw 0x09c1, 0xc417, 0x09c1, 0xc417, 0x21, 0 + .dw 0x09c3, 0xc417, 0x09cf, 0xc417, 0x21, 0 + .dw 0x09d1, 0xc417, 0x09d1, 0xc417, 0x21, 0 + .dw 0x09d3, 0xc417, 0x09ff, 0xc417, 0x21, 0 + .dw 0x0a01, 0xc417, 0x0a01, 0xc417, 0x21, 0 + .dw 0x0a03, 0xc417, 0x0a0f, 0xc417, 0x21, 0 + .dw 0x0a11, 0xc417, 0x0a11, 0xc417, 0x21, 0 + .dw 0x0a13, 0xc417, 0x0a3f, 0xc417, 0x21, 0 + .dw 0x0a41, 0xc417, 0x0a41, 0xc417, 0x21, 0 + .dw 0x0a43, 0xc417, 0x0a4f, 0xc417, 0x21, 0 + .dw 0x0a51, 0xc417, 0x0a51, 0xc417, 0x21, 0 + .dw 0x0a53, 0xc417, 0x0a7f, 0xc417, 0x21, 0 + .dw 0x0a81, 0xc417, 0x0a81, 0xc417, 0x21, 0 + .dw 0x0a83, 0xc417, 0x0a8f, 0xc417, 0x21, 0 + .dw 0x0a91, 0xc417, 0x0a91, 0xc417, 0x21, 0 + .dw 0x0a93, 0xc417, 0x0abf, 0xc417, 0x21, 0 + .dw 0x0ac1, 0xc417, 0x0ac1, 0xc417, 0x21, 0 + .dw 0x0ac3, 0xc417, 0x0acf, 0xc417, 0x21, 0 + .dw 0x0ad1, 0xc417, 0x0ad1, 0xc417, 0x21, 0 + .dw 0x0ad3, 0xc417, 0x0aff, 0xc417, 0x21, 0 + .dw 0x0b01, 0xc417, 0x0b01, 0xc417, 0x21, 0 + .dw 0x0b03, 0xc417, 0x0b0f, 0xc417, 0x21, 0 + .dw 0x0b11, 0xc417, 0x0b11, 0xc417, 0x21, 0 + .dw 0x0b13, 0xc417, 0x0b3f, 0xc417, 0x21, 0 + .dw 0x0b41, 0xc417, 0x0b41, 0xc417, 0x21, 0 + .dw 0x0b43, 0xc417, 0x0b4f, 0xc417, 0x21, 0 + .dw 0x0b51, 0xc417, 0x0b51, 0xc417, 0x21, 0 + .dw 0x0b53, 0xc417, 0x0b7f, 0xc417, 0x21, 0 + .dw 0x0b81, 0xc417, 0x0b81, 0xc417, 0x21, 0 + .dw 0x0b83, 0xc417, 0x0b8f, 0xc417, 0x21, 0 + .dw 0x0b91, 0xc417, 0x0b91, 0xc417, 0x21, 0 + .dw 0x0b93, 0xc417, 0x0bbf, 0xc417, 0x21, 0 + .dw 0x0bc1, 0xc417, 0x0bc1, 0xc417, 0x21, 0 + .dw 0x0bc3, 0xc417, 0x0bcf, 0xc417, 0x21, 0 + .dw 0x0bd1, 0xc417, 0x0bd1, 0xc417, 0x21, 0 + .dw 0x0bd3, 0xc417, 0x0bff, 0xc417, 0x21, 0 + .dw 0x0c01, 0xc417, 0x0c01, 0xc417, 0x21, 0 + .dw 0x0c03, 0xc417, 0x0c0f, 0xc417, 0x21, 0 + .dw 0x0c11, 0xc417, 0x0c11, 0xc417, 0x21, 0 + .dw 0x0c13, 0xc417, 0x0c3f, 0xc417, 0x21, 0 + .dw 0x0c41, 0xc417, 0x0c41, 0xc417, 0x21, 0 + .dw 0x0c43, 0xc417, 0x0c4f, 0xc417, 0x21, 0 + .dw 0x0c51, 0xc417, 0x0c51, 0xc417, 0x21, 0 + .dw 0x0c53, 0xc417, 0x0c7f, 0xc417, 0x21, 0 + .dw 0x0c81, 0xc417, 0x0c81, 0xc417, 0x21, 0 + .dw 0x0c83, 0xc417, 0x0c8f, 0xc417, 0x21, 0 + .dw 0x0c91, 0xc417, 0x0c91, 0xc417, 0x21, 0 + .dw 0x0c93, 0xc417, 0x0cbf, 0xc417, 0x21, 0 + .dw 0x0cc1, 0xc417, 0x0cc1, 0xc417, 0x21, 0 + .dw 0x0cc3, 0xc417, 0x0ccf, 0xc417, 0x21, 0 + .dw 0x0cd1, 0xc417, 0x0cd1, 0xc417, 0x21, 0 + .dw 0x0cd3, 0xc417, 0x0cff, 0xc417, 0x21, 0 + .dw 0x0d01, 0xc417, 0x0d01, 0xc417, 0x21, 0 + .dw 0x0d03, 0xc417, 0x0d0f, 0xc417, 0x21, 0 + .dw 0x0d11, 0xc417, 0x0d11, 0xc417, 0x21, 0 + .dw 0x0d13, 0xc417, 0x0d3f, 0xc417, 0x21, 0 + .dw 0x0d41, 0xc417, 0x0d41, 0xc417, 0x21, 0 + .dw 0x0d43, 0xc417, 0x0d4f, 0xc417, 0x21, 0 + .dw 0x0d51, 0xc417, 0x0d51, 0xc417, 0x21, 0 + .dw 0x0d53, 0xc417, 0x0d7f, 0xc417, 0x21, 0 + .dw 0x0d81, 0xc417, 0x0d81, 0xc417, 0x21, 0 + .dw 0x0d83, 0xc417, 0x0d8f, 0xc417, 0x21, 0 + .dw 0x0d91, 0xc417, 0x0d91, 0xc417, 0x21, 0 + .dw 0x0d93, 0xc417, 0x0dbf, 0xc417, 0x21, 0 + .dw 0x0dc1, 0xc417, 0x0dc1, 0xc417, 0x21, 0 + .dw 0x0dc3, 0xc417, 0x0dcf, 0xc417, 0x21, 0 + .dw 0x0dd1, 0xc417, 0x0dd1, 0xc417, 0x21, 0 + .dw 0x0dd3, 0xc417, 0x0dff, 0xc417, 0x21, 0 + .dw 0x0e01, 0xc417, 0x0e01, 0xc417, 0x21, 0 + .dw 0x0e03, 0xc417, 0x0e0f, 0xc417, 0x21, 0 + .dw 0x0e11, 0xc417, 0x0e11, 0xc417, 0x21, 0 + .dw 0x0e13, 0xc417, 0x0e3f, 0xc417, 0x21, 0 + .dw 0x0e41, 0xc417, 0x0e41, 0xc417, 0x21, 0 + .dw 0x0e43, 0xc417, 0x0e4f, 0xc417, 0x21, 0 + .dw 0x0e51, 0xc417, 0x0e51, 0xc417, 0x21, 0 + .dw 0x0e53, 0xc417, 0x0e7f, 0xc417, 0x21, 0 + .dw 0x0e81, 0xc417, 0x0e81, 0xc417, 0x21, 0 + .dw 0x0e83, 0xc417, 0x0e8f, 0xc417, 0x21, 0 + .dw 0x0e91, 0xc417, 0x0e91, 0xc417, 0x21, 0 + .dw 0x0e93, 0xc417, 0x0ebf, 0xc417, 0x21, 0 + .dw 0x0ec1, 0xc417, 0x0ec1, 0xc417, 0x21, 0 + .dw 0x0ec3, 0xc417, 0x0ecf, 0xc417, 0x21, 0 + .dw 0x0ed1, 0xc417, 0x0ed1, 0xc417, 0x21, 0 + .dw 0x0ed3, 0xc417, 0x0eff, 0xc417, 0x21, 0 + .dw 0x0f01, 0xc417, 0x0f01, 0xc417, 0x21, 0 + .dw 0x0f03, 0xc417, 0x0f0f, 0xc417, 0x21, 0 + .dw 0x0f11, 0xc417, 0x0f11, 0xc417, 0x21, 0 + .dw 0x0f13, 0xc417, 0x0f3f, 0xc417, 0x21, 0 + .dw 0x0f41, 0xc417, 0x0f41, 0xc417, 0x21, 0 + .dw 0x0f43, 0xc417, 0x0f4f, 0xc417, 0x21, 0 + .dw 0x0f51, 0xc417, 0x0f51, 0xc417, 0x21, 0 + .dw 0x0f53, 0xc417, 0x0f7f, 0xc417, 0x21, 0 + .dw 0x0f81, 0xc417, 0x0f81, 0xc417, 0x21, 0 + .dw 0x0f83, 0xc417, 0x0f8f, 0xc417, 0x21, 0 + .dw 0x0f91, 0xc417, 0x0f91, 0xc417, 0x21, 0 + .dw 0x0f93, 0xc417, 0x0fbf, 0xc417, 0x21, 0 + .dw 0x0fc1, 0xc417, 0x0fc1, 0xc417, 0x21, 0 + .dw 0x0fc3, 0xc417, 0x0fcf, 0xc417, 0x21, 0 + .dw 0x0fd1, 0xc417, 0x0fd1, 0xc417, 0x21, 0 + .dw 0x0fd3, 0xc417, 0x1fff, 0xc417, 0x21, 0 + .dw 0x2001, 0xc417, 0x2001, 0xc417, 0x21, 0 + .dw 0x2003, 0xc417, 0x200f, 0xc417, 0x21, 0 + .dw 0x2011, 0xc417, 0x2011, 0xc417, 0x21, 0 + .dw 0x2013, 0xc417, 0x203f, 0xc417, 0x21, 0 + .dw 0x2041, 0xc417, 0x2041, 0xc417, 0x21, 0 + .dw 0x2043, 0xc417, 0x204f, 0xc417, 0x21, 0 + .dw 0x2051, 0xc417, 0x2051, 0xc417, 0x21, 0 + .dw 0x2053, 0xc417, 0x207f, 0xc417, 0x21, 0 + .dw 0x2081, 0xc417, 0x2081, 0xc417, 0x21, 0 + .dw 0x2083, 0xc417, 0x208f, 0xc417, 0x21, 0 + .dw 0x2091, 0xc417, 0x2091, 0xc417, 0x21, 0 + .dw 0x2093, 0xc417, 0x20bf, 0xc417, 0x21, 0 + .dw 0x20c1, 0xc417, 0x20c1, 0xc417, 0x21, 0 + .dw 0x20c3, 0xc417, 0x20cf, 0xc417, 0x21, 0 + .dw 0x20d1, 0xc417, 0x20d1, 0xc417, 0x21, 0 + .dw 0x20d3, 0xc417, 0x20ff, 0xc417, 0x21, 0 + .dw 0x2101, 0xc417, 0x2101, 0xc417, 0x21, 0 + .dw 0x2103, 0xc417, 0x210f, 0xc417, 0x21, 0 + .dw 0x2111, 0xc417, 0x2111, 0xc417, 0x21, 0 + .dw 0x2113, 0xc417, 0x213f, 0xc417, 0x21, 0 + .dw 0x2141, 0xc417, 0x2141, 0xc417, 0x21, 0 + .dw 0x2143, 0xc417, 0x214f, 0xc417, 0x21, 0 + .dw 0x2151, 0xc417, 0x2151, 0xc417, 0x21, 0 + .dw 0x2153, 0xc417, 0x217f, 0xc417, 0x21, 0 + .dw 0x2181, 0xc417, 0x2181, 0xc417, 0x21, 0 + .dw 0x2183, 0xc417, 0x218f, 0xc417, 0x21, 0 + .dw 0x2191, 0xc417, 0x2191, 0xc417, 0x21, 0 + .dw 0x2193, 0xc417, 0x21bf, 0xc417, 0x21, 0 + .dw 0x21c1, 0xc417, 0x21c1, 0xc417, 0x21, 0 + .dw 0x21c3, 0xc417, 0x21cf, 0xc417, 0x21, 0 + .dw 0x21d1, 0xc417, 0x21d1, 0xc417, 0x21, 0 + .dw 0x21d3, 0xc417, 0x21ff, 0xc417, 0x21, 0 + .dw 0x2201, 0xc417, 0x2201, 0xc417, 0x21, 0 + .dw 0x2203, 0xc417, 0x220f, 0xc417, 0x21, 0 + .dw 0x2211, 0xc417, 0x2211, 0xc417, 0x21, 0 + .dw 0x2213, 0xc417, 0x223f, 0xc417, 0x21, 0 + .dw 0x2241, 0xc417, 0x2241, 0xc417, 0x21, 0 + .dw 0x2243, 0xc417, 0x224f, 0xc417, 0x21, 0 + .dw 0x2251, 0xc417, 0x2251, 0xc417, 0x21, 0 + .dw 0x2253, 0xc417, 0x227f, 0xc417, 0x21, 0 + .dw 0x2281, 0xc417, 0x2281, 0xc417, 0x21, 0 + .dw 0x2283, 0xc417, 0x228f, 0xc417, 0x21, 0 + .dw 0x2291, 0xc417, 0x2291, 0xc417, 0x21, 0 + .dw 0x2293, 0xc417, 0x22bf, 0xc417, 0x21, 0 + .dw 0x22c1, 0xc417, 0x22c1, 0xc417, 0x21, 0 + .dw 0x22c3, 0xc417, 0x22cf, 0xc417, 0x21, 0 + .dw 0x22d1, 0xc417, 0x22d1, 0xc417, 0x21, 0 + .dw 0x22d3, 0xc417, 0x22ff, 0xc417, 0x21, 0 + .dw 0x2301, 0xc417, 0x2301, 0xc417, 0x21, 0 + .dw 0x2303, 0xc417, 0x230f, 0xc417, 0x21, 0 + .dw 0x2311, 0xc417, 0x2311, 0xc417, 0x21, 0 + .dw 0x2313, 0xc417, 0x233f, 0xc417, 0x21, 0 + .dw 0x2341, 0xc417, 0x2341, 0xc417, 0x21, 0 + .dw 0x2343, 0xc417, 0x234f, 0xc417, 0x21, 0 + .dw 0x2351, 0xc417, 0x2351, 0xc417, 0x21, 0 + .dw 0x2353, 0xc417, 0x237f, 0xc417, 0x21, 0 + .dw 0x2381, 0xc417, 0x2381, 0xc417, 0x21, 0 + .dw 0x2383, 0xc417, 0x238f, 0xc417, 0x21, 0 + .dw 0x2391, 0xc417, 0x2391, 0xc417, 0x21, 0 + .dw 0x2393, 0xc417, 0x23bf, 0xc417, 0x21, 0 + .dw 0x23c1, 0xc417, 0x23c1, 0xc417, 0x21, 0 + .dw 0x23c3, 0xc417, 0x23cf, 0xc417, 0x21, 0 + .dw 0x23d1, 0xc417, 0x23d1, 0xc417, 0x21, 0 + .dw 0x23d3, 0xc417, 0x23ff, 0xc417, 0x21, 0 + .dw 0x2401, 0xc417, 0x2401, 0xc417, 0x21, 0 + .dw 0x2403, 0xc417, 0x240f, 0xc417, 0x21, 0 + .dw 0x2411, 0xc417, 0x2411, 0xc417, 0x21, 0 + .dw 0x2413, 0xc417, 0x243f, 0xc417, 0x21, 0 + .dw 0x2441, 0xc417, 0x2441, 0xc417, 0x21, 0 + .dw 0x2443, 0xc417, 0x244f, 0xc417, 0x21, 0 + .dw 0x2451, 0xc417, 0x2451, 0xc417, 0x21, 0 + .dw 0x2453, 0xc417, 0x247f, 0xc417, 0x21, 0 + .dw 0x2481, 0xc417, 0x2481, 0xc417, 0x21, 0 + .dw 0x2483, 0xc417, 0x248f, 0xc417, 0x21, 0 + .dw 0x2491, 0xc417, 0x2491, 0xc417, 0x21, 0 + .dw 0x2493, 0xc417, 0x24bf, 0xc417, 0x21, 0 + .dw 0x24c1, 0xc417, 0x24c1, 0xc417, 0x21, 0 + .dw 0x24c3, 0xc417, 0x24cf, 0xc417, 0x21, 0 + .dw 0x24d1, 0xc417, 0x24d1, 0xc417, 0x21, 0 + .dw 0x24d3, 0xc417, 0x24ff, 0xc417, 0x21, 0 + .dw 0x2501, 0xc417, 0x2501, 0xc417, 0x21, 0 + .dw 0x2503, 0xc417, 0x250f, 0xc417, 0x21, 0 + .dw 0x2511, 0xc417, 0x2511, 0xc417, 0x21, 0 + .dw 0x2513, 0xc417, 0x253f, 0xc417, 0x21, 0 + .dw 0x2541, 0xc417, 0x2541, 0xc417, 0x21, 0 + .dw 0x2543, 0xc417, 0x254f, 0xc417, 0x21, 0 + .dw 0x2551, 0xc417, 0x2551, 0xc417, 0x21, 0 + .dw 0x2553, 0xc417, 0x257f, 0xc417, 0x21, 0 + .dw 0x2581, 0xc417, 0x2581, 0xc417, 0x21, 0 + .dw 0x2583, 0xc417, 0x258f, 0xc417, 0x21, 0 + .dw 0x2591, 0xc417, 0x2591, 0xc417, 0x21, 0 + .dw 0x2593, 0xc417, 0x25bf, 0xc417, 0x21, 0 + .dw 0x25c1, 0xc417, 0x25c1, 0xc417, 0x21, 0 + .dw 0x25c3, 0xc417, 0x25cf, 0xc417, 0x21, 0 + .dw 0x25d1, 0xc417, 0x25d1, 0xc417, 0x21, 0 + .dw 0x25d3, 0xc417, 0x25ff, 0xc417, 0x21, 0 + .dw 0x2601, 0xc417, 0x2601, 0xc417, 0x21, 0 + .dw 0x2603, 0xc417, 0x260f, 0xc417, 0x21, 0 + .dw 0x2611, 0xc417, 0x2611, 0xc417, 0x21, 0 + .dw 0x2613, 0xc417, 0x263f, 0xc417, 0x21, 0 + .dw 0x2641, 0xc417, 0x2641, 0xc417, 0x21, 0 + .dw 0x2643, 0xc417, 0x264f, 0xc417, 0x21, 0 + .dw 0x2651, 0xc417, 0x2651, 0xc417, 0x21, 0 + .dw 0x2653, 0xc417, 0x267f, 0xc417, 0x21, 0 + .dw 0x2681, 0xc417, 0x2681, 0xc417, 0x21, 0 + .dw 0x2683, 0xc417, 0x268f, 0xc417, 0x21, 0 + .dw 0x2691, 0xc417, 0x2691, 0xc417, 0x21, 0 + .dw 0x2693, 0xc417, 0x26bf, 0xc417, 0x21, 0 + .dw 0x26c1, 0xc417, 0x26c1, 0xc417, 0x21, 0 + .dw 0x26c3, 0xc417, 0x26cf, 0xc417, 0x21, 0 + .dw 0x26d1, 0xc417, 0x26d1, 0xc417, 0x21, 0 + .dw 0x26d3, 0xc417, 0x26ff, 0xc417, 0x21, 0 + .dw 0x2701, 0xc417, 0x2701, 0xc417, 0x21, 0 + .dw 0x2703, 0xc417, 0x270f, 0xc417, 0x21, 0 + .dw 0x2711, 0xc417, 0x2711, 0xc417, 0x21, 0 + .dw 0x2713, 0xc417, 0x273f, 0xc417, 0x21, 0 + .dw 0x2741, 0xc417, 0x2741, 0xc417, 0x21, 0 + .dw 0x2743, 0xc417, 0x274f, 0xc417, 0x21, 0 + .dw 0x2751, 0xc417, 0x2751, 0xc417, 0x21, 0 + .dw 0x2753, 0xc417, 0x277f, 0xc417, 0x21, 0 + .dw 0x2781, 0xc417, 0x2781, 0xc417, 0x21, 0 + .dw 0x2783, 0xc417, 0x278f, 0xc417, 0x21, 0 + .dw 0x2791, 0xc417, 0x2791, 0xc417, 0x21, 0 + .dw 0x2793, 0xc417, 0x27bf, 0xc417, 0x21, 0 + .dw 0x27c1, 0xc417, 0x27c1, 0xc417, 0x21, 0 + .dw 0x27c3, 0xc417, 0x27cf, 0xc417, 0x21, 0 + .dw 0x27d1, 0xc417, 0x27d1, 0xc417, 0x21, 0 + .dw 0x27d3, 0xc417, 0x27ff, 0xc417, 0x21, 0 + .dw 0x2801, 0xc417, 0x2801, 0xc417, 0x21, 0 + .dw 0x2803, 0xc417, 0x280f, 0xc417, 0x21, 0 + .dw 0x2811, 0xc417, 0x2811, 0xc417, 0x21, 0 + .dw 0x2813, 0xc417, 0x283f, 0xc417, 0x21, 0 + .dw 0x2841, 0xc417, 0x2841, 0xc417, 0x21, 0 + .dw 0x2843, 0xc417, 0x284f, 0xc417, 0x21, 0 + .dw 0x2851, 0xc417, 0x2851, 0xc417, 0x21, 0 + .dw 0x2853, 0xc417, 0x287f, 0xc417, 0x21, 0 + .dw 0x2881, 0xc417, 0x2881, 0xc417, 0x21, 0 + .dw 0x2883, 0xc417, 0x288f, 0xc417, 0x21, 0 + .dw 0x2891, 0xc417, 0x2891, 0xc417, 0x21, 0 + .dw 0x2893, 0xc417, 0x28bf, 0xc417, 0x21, 0 + .dw 0x28c1, 0xc417, 0x28c1, 0xc417, 0x21, 0 + .dw 0x28c3, 0xc417, 0x28cf, 0xc417, 0x21, 0 + .dw 0x28d1, 0xc417, 0x28d1, 0xc417, 0x21, 0 + .dw 0x28d3, 0xc417, 0x28ff, 0xc417, 0x21, 0 + .dw 0x2901, 0xc417, 0x2901, 0xc417, 0x21, 0 + .dw 0x2903, 0xc417, 0x290f, 0xc417, 0x21, 0 + .dw 0x2911, 0xc417, 0x2911, 0xc417, 0x21, 0 + .dw 0x2913, 0xc417, 0x293f, 0xc417, 0x21, 0 + .dw 0x2941, 0xc417, 0x2941, 0xc417, 0x21, 0 + .dw 0x2943, 0xc417, 0x294f, 0xc417, 0x21, 0 + .dw 0x2951, 0xc417, 0x2951, 0xc417, 0x21, 0 + .dw 0x2953, 0xc417, 0x297f, 0xc417, 0x21, 0 + .dw 0x2981, 0xc417, 0x2981, 0xc417, 0x21, 0 + .dw 0x2983, 0xc417, 0x298f, 0xc417, 0x21, 0 + .dw 0x2991, 0xc417, 0x2991, 0xc417, 0x21, 0 + .dw 0x2993, 0xc417, 0x29bf, 0xc417, 0x21, 0 + .dw 0x29c1, 0xc417, 0x29c1, 0xc417, 0x21, 0 + .dw 0x29c3, 0xc417, 0x29cf, 0xc417, 0x21, 0 + .dw 0x29d1, 0xc417, 0x29d1, 0xc417, 0x21, 0 + .dw 0x29d3, 0xc417, 0x29ff, 0xc417, 0x21, 0 + .dw 0x2a01, 0xc417, 0x2a01, 0xc417, 0x21, 0 + .dw 0x2a03, 0xc417, 0x2a0f, 0xc417, 0x21, 0 + .dw 0x2a11, 0xc417, 0x2a11, 0xc417, 0x21, 0 + .dw 0x2a13, 0xc417, 0x2a3f, 0xc417, 0x21, 0 + .dw 0x2a41, 0xc417, 0x2a41, 0xc417, 0x21, 0 + .dw 0x2a43, 0xc417, 0x2a4f, 0xc417, 0x21, 0 + .dw 0x2a51, 0xc417, 0x2a51, 0xc417, 0x21, 0 + .dw 0x2a53, 0xc417, 0x2a7f, 0xc417, 0x21, 0 + .dw 0x2a81, 0xc417, 0x2a81, 0xc417, 0x21, 0 + .dw 0x2a83, 0xc417, 0x2a8f, 0xc417, 0x21, 0 + .dw 0x2a91, 0xc417, 0x2a91, 0xc417, 0x21, 0 + .dw 0x2a93, 0xc417, 0x2abf, 0xc417, 0x21, 0 + .dw 0x2ac1, 0xc417, 0x2ac1, 0xc417, 0x21, 0 + .dw 0x2ac3, 0xc417, 0x2acf, 0xc417, 0x21, 0 + .dw 0x2ad1, 0xc417, 0x2ad1, 0xc417, 0x21, 0 + .dw 0x2ad3, 0xc417, 0x2aff, 0xc417, 0x21, 0 + .dw 0x2b01, 0xc417, 0x2b01, 0xc417, 0x21, 0 + .dw 0x2b03, 0xc417, 0x2b0f, 0xc417, 0x21, 0 + .dw 0x2b11, 0xc417, 0x2b11, 0xc417, 0x21, 0 + .dw 0x2b13, 0xc417, 0x2b3f, 0xc417, 0x21, 0 + .dw 0x2b41, 0xc417, 0x2b41, 0xc417, 0x21, 0 + .dw 0x2b43, 0xc417, 0x2b4f, 0xc417, 0x21, 0 + .dw 0x2b51, 0xc417, 0x2b51, 0xc417, 0x21, 0 + .dw 0x2b53, 0xc417, 0x2b7f, 0xc417, 0x21, 0 + .dw 0x2b81, 0xc417, 0x2b81, 0xc417, 0x21, 0 + .dw 0x2b83, 0xc417, 0x2b8f, 0xc417, 0x21, 0 + .dw 0x2b91, 0xc417, 0x2b91, 0xc417, 0x21, 0 + .dw 0x2b93, 0xc417, 0x2bbf, 0xc417, 0x21, 0 + .dw 0x2bc1, 0xc417, 0x2bc1, 0xc417, 0x21, 0 + .dw 0x2bc3, 0xc417, 0x2bcf, 0xc417, 0x21, 0 + .dw 0x2bd1, 0xc417, 0x2bd1, 0xc417, 0x21, 0 + .dw 0x2bd3, 0xc417, 0x2bff, 0xc417, 0x21, 0 + .dw 0x2c01, 0xc417, 0x2c01, 0xc417, 0x21, 0 + .dw 0x2c03, 0xc417, 0x2c0f, 0xc417, 0x21, 0 + .dw 0x2c11, 0xc417, 0x2c11, 0xc417, 0x21, 0 + .dw 0x2c13, 0xc417, 0x2c3f, 0xc417, 0x21, 0 + .dw 0x2c41, 0xc417, 0x2c41, 0xc417, 0x21, 0 + .dw 0x2c43, 0xc417, 0x2c4f, 0xc417, 0x21, 0 + .dw 0x2c51, 0xc417, 0x2c51, 0xc417, 0x21, 0 + .dw 0x2c53, 0xc417, 0x2c7f, 0xc417, 0x21, 0 + .dw 0x2c81, 0xc417, 0x2c81, 0xc417, 0x21, 0 + .dw 0x2c83, 0xc417, 0x2c8f, 0xc417, 0x21, 0 + .dw 0x2c91, 0xc417, 0x2c91, 0xc417, 0x21, 0 + .dw 0x2c93, 0xc417, 0x2cbf, 0xc417, 0x21, 0 + .dw 0x2cc1, 0xc417, 0x2cc1, 0xc417, 0x21, 0 + .dw 0x2cc3, 0xc417, 0x2ccf, 0xc417, 0x21, 0 + .dw 0x2cd1, 0xc417, 0x2cd1, 0xc417, 0x21, 0 + .dw 0x2cd3, 0xc417, 0x2cff, 0xc417, 0x21, 0 + .dw 0x2d01, 0xc417, 0x2d01, 0xc417, 0x21, 0 + .dw 0x2d03, 0xc417, 0x2d0f, 0xc417, 0x21, 0 + .dw 0x2d11, 0xc417, 0x2d11, 0xc417, 0x21, 0 + .dw 0x2d13, 0xc417, 0x2d3f, 0xc417, 0x21, 0 + .dw 0x2d41, 0xc417, 0x2d41, 0xc417, 0x21, 0 + .dw 0x2d43, 0xc417, 0x2d4f, 0xc417, 0x21, 0 + .dw 0x2d51, 0xc417, 0x2d51, 0xc417, 0x21, 0 + .dw 0x2d53, 0xc417, 0x2d7f, 0xc417, 0x21, 0 + .dw 0x2d81, 0xc417, 0x2d81, 0xc417, 0x21, 0 + .dw 0x2d83, 0xc417, 0x2d8f, 0xc417, 0x21, 0 + .dw 0x2d91, 0xc417, 0x2d91, 0xc417, 0x21, 0 + .dw 0x2d93, 0xc417, 0x2dbf, 0xc417, 0x21, 0 + .dw 0x2dc1, 0xc417, 0x2dc1, 0xc417, 0x21, 0 + .dw 0x2dc3, 0xc417, 0x2dcf, 0xc417, 0x21, 0 + .dw 0x2dd1, 0xc417, 0x2dd1, 0xc417, 0x21, 0 + .dw 0x2dd3, 0xc417, 0x2dff, 0xc417, 0x21, 0 + .dw 0x2e01, 0xc417, 0x2e01, 0xc417, 0x21, 0 + .dw 0x2e03, 0xc417, 0x2e0f, 0xc417, 0x21, 0 + .dw 0x2e11, 0xc417, 0x2e11, 0xc417, 0x21, 0 + .dw 0x2e13, 0xc417, 0x2e3f, 0xc417, 0x21, 0 + .dw 0x2e41, 0xc417, 0x2e41, 0xc417, 0x21, 0 + .dw 0x2e43, 0xc417, 0x2e4f, 0xc417, 0x21, 0 + .dw 0x2e51, 0xc417, 0x2e51, 0xc417, 0x21, 0 + .dw 0x2e53, 0xc417, 0x2e7f, 0xc417, 0x21, 0 + .dw 0x2e81, 0xc417, 0x2e81, 0xc417, 0x21, 0 + .dw 0x2e83, 0xc417, 0x2e8f, 0xc417, 0x21, 0 + .dw 0x2e91, 0xc417, 0x2e91, 0xc417, 0x21, 0 + .dw 0x2e93, 0xc417, 0x2ebf, 0xc417, 0x21, 0 + .dw 0x2ec1, 0xc417, 0x2ec1, 0xc417, 0x21, 0 + .dw 0x2ec3, 0xc417, 0x2ecf, 0xc417, 0x21, 0 + .dw 0x2ed1, 0xc417, 0x2ed1, 0xc417, 0x21, 0 + .dw 0x2ed3, 0xc417, 0x2eff, 0xc417, 0x21, 0 + .dw 0x2f01, 0xc417, 0x2f01, 0xc417, 0x21, 0 + .dw 0x2f03, 0xc417, 0x2f0f, 0xc417, 0x21, 0 + .dw 0x2f11, 0xc417, 0x2f11, 0xc417, 0x21, 0 + .dw 0x2f13, 0xc417, 0x2f3f, 0xc417, 0x21, 0 + .dw 0x2f41, 0xc417, 0x2f41, 0xc417, 0x21, 0 + .dw 0x2f43, 0xc417, 0x2f4f, 0xc417, 0x21, 0 + .dw 0x2f51, 0xc417, 0x2f51, 0xc417, 0x21, 0 + .dw 0x2f53, 0xc417, 0x2f7f, 0xc417, 0x21, 0 + .dw 0x2f81, 0xc417, 0x2f81, 0xc417, 0x21, 0 + .dw 0x2f83, 0xc417, 0x2f8f, 0xc417, 0x21, 0 + .dw 0x2f91, 0xc417, 0x2f91, 0xc417, 0x21, 0 + .dw 0x2f93, 0xc417, 0x2fbf, 0xc417, 0x21, 0 + .dw 0x2fc1, 0xc417, 0x2fc1, 0xc417, 0x21, 0 + .dw 0x2fc3, 0xc417, 0x2fcf, 0xc417, 0x21, 0 + .dw 0x2fd1, 0xc417, 0x2fd1, 0xc417, 0x21, 0 + .dw 0x2fd3, 0xc417, 0xffff, 0xc417, 0x21, 0 + .dw 0x1000, 0xc418, 0x3fff, 0xc418, 0x21, 0 + .dw 0x4000, 0xc418, 0x4000, 0xc418, 0x22, 0 + .dw 0x4001, 0xc418, 0x4001, 0xc418, 0x21, 0 + .dw 0x4002, 0xc418, 0x4002, 0xc418, 0x22, 0 + .dw 0x4003, 0xc418, 0x400f, 0xc418, 0x21, 0 + .dw 0x4010, 0xc418, 0x4010, 0xc418, 0x22, 0 + .dw 0x4011, 0xc418, 0x4011, 0xc418, 0x21, 0 + .dw 0x4012, 0xc418, 0x4012, 0xc418, 0x22, 0 + .dw 0x4013, 0xc418, 0x403f, 0xc418, 0x21, 0 + .dw 0x4041, 0xc418, 0x4041, 0xc418, 0x21, 0 + .dw 0x4043, 0xc418, 0x404f, 0xc418, 0x21, 0 + .dw 0x4051, 0xc418, 0x4051, 0xc418, 0x21, 0 + .dw 0x4053, 0xc418, 0x407f, 0xc418, 0x21, 0 + .dw 0x4081, 0xc418, 0x4081, 0xc418, 0x21, 0 + .dw 0x4083, 0xc418, 0x408f, 0xc418, 0x21, 0 + .dw 0x4091, 0xc418, 0x4091, 0xc418, 0x21, 0 + .dw 0x4093, 0xc418, 0x40bf, 0xc418, 0x21, 0 + .dw 0x40c1, 0xc418, 0x40c1, 0xc418, 0x21, 0 + .dw 0x40c3, 0xc418, 0x40cf, 0xc418, 0x21, 0 + .dw 0x40d1, 0xc418, 0x40d1, 0xc418, 0x21, 0 + .dw 0x40d3, 0xc418, 0x40ff, 0xc418, 0x21, 0 + .dw 0x4101, 0xc418, 0x4101, 0xc418, 0x21, 0 + .dw 0x4103, 0xc418, 0x410f, 0xc418, 0x21, 0 + .dw 0x4111, 0xc418, 0x4111, 0xc418, 0x21, 0 + .dw 0x4113, 0xc418, 0x413f, 0xc418, 0x21, 0 + .dw 0x4141, 0xc418, 0x4141, 0xc418, 0x21, 0 + .dw 0x4143, 0xc418, 0x414f, 0xc418, 0x21, 0 + .dw 0x4151, 0xc418, 0x4151, 0xc418, 0x21, 0 + .dw 0x4153, 0xc418, 0x417f, 0xc418, 0x21, 0 + .dw 0x4181, 0xc418, 0x4181, 0xc418, 0x21, 0 + .dw 0x4183, 0xc418, 0x418f, 0xc418, 0x21, 0 + .dw 0x4191, 0xc418, 0x4191, 0xc418, 0x21, 0 + .dw 0x4193, 0xc418, 0x41bf, 0xc418, 0x21, 0 + .dw 0x41c1, 0xc418, 0x41c1, 0xc418, 0x21, 0 + .dw 0x41c3, 0xc418, 0x41cf, 0xc418, 0x21, 0 + .dw 0x41d1, 0xc418, 0x41d1, 0xc418, 0x21, 0 + .dw 0x41d3, 0xc418, 0x41ff, 0xc418, 0x21, 0 + .dw 0x4201, 0xc418, 0x4201, 0xc418, 0x21, 0 + .dw 0x4203, 0xc418, 0x420f, 0xc418, 0x21, 0 + .dw 0x4211, 0xc418, 0x4211, 0xc418, 0x21, 0 + .dw 0x4213, 0xc418, 0x423f, 0xc418, 0x21, 0 + .dw 0x4240, 0xc418, 0x4240, 0xc418, 0x22, 0 + .dw 0x4241, 0xc418, 0x4241, 0xc418, 0x21, 0 + .dw 0x4242, 0xc418, 0x4242, 0xc418, 0x22, 0 + .dw 0x4243, 0xc418, 0x424f, 0xc418, 0x21, 0 + .dw 0x4250, 0xc418, 0x4250, 0xc418, 0x22, 0 + .dw 0x4251, 0xc418, 0x4251, 0xc418, 0x21, 0 + .dw 0x4252, 0xc418, 0x4252, 0xc418, 0x22, 0 + .dw 0x4253, 0xc418, 0x427f, 0xc418, 0x21, 0 + .dw 0x4281, 0xc418, 0x4281, 0xc418, 0x21, 0 + .dw 0x4283, 0xc418, 0x428f, 0xc418, 0x21, 0 + .dw 0x4291, 0xc418, 0x4291, 0xc418, 0x21, 0 + .dw 0x4293, 0xc418, 0x42bf, 0xc418, 0x21, 0 + .dw 0x42c1, 0xc418, 0x42c1, 0xc418, 0x21, 0 + .dw 0x42c3, 0xc418, 0x42cf, 0xc418, 0x21, 0 + .dw 0x42d1, 0xc418, 0x42d1, 0xc418, 0x21, 0 + .dw 0x42d3, 0xc418, 0x42ff, 0xc418, 0x21, 0 + .dw 0x4301, 0xc418, 0x4301, 0xc418, 0x21, 0 + .dw 0x4303, 0xc418, 0x430f, 0xc418, 0x21, 0 + .dw 0x4311, 0xc418, 0x4311, 0xc418, 0x21, 0 + .dw 0x4313, 0xc418, 0x433f, 0xc418, 0x21, 0 + .dw 0x4341, 0xc418, 0x4341, 0xc418, 0x21, 0 + .dw 0x4343, 0xc418, 0x434f, 0xc418, 0x21, 0 + .dw 0x4351, 0xc418, 0x4351, 0xc418, 0x21, 0 + .dw 0x4353, 0xc418, 0x437f, 0xc418, 0x21, 0 + .dw 0x4381, 0xc418, 0x4381, 0xc418, 0x21, 0 + .dw 0x4383, 0xc418, 0x438f, 0xc418, 0x21, 0 + .dw 0x4391, 0xc418, 0x4391, 0xc418, 0x21, 0 + .dw 0x4393, 0xc418, 0x43bf, 0xc418, 0x21, 0 + .dw 0x43c1, 0xc418, 0x43c1, 0xc418, 0x21, 0 + .dw 0x43c3, 0xc418, 0x43cf, 0xc418, 0x21, 0 + .dw 0x43d1, 0xc418, 0x43d1, 0xc418, 0x21, 0 + .dw 0x43d3, 0xc418, 0x43ff, 0xc418, 0x21, 0 + .dw 0x4401, 0xc418, 0x4401, 0xc418, 0x21, 0 + .dw 0x4403, 0xc418, 0x440f, 0xc418, 0x21, 0 + .dw 0x4411, 0xc418, 0x4411, 0xc418, 0x21, 0 + .dw 0x4413, 0xc418, 0x443f, 0xc418, 0x21, 0 + .dw 0x4441, 0xc418, 0x4441, 0xc418, 0x21, 0 + .dw 0x4443, 0xc418, 0x444f, 0xc418, 0x21, 0 + .dw 0x4451, 0xc418, 0x4451, 0xc418, 0x21, 0 + .dw 0x4453, 0xc418, 0x447f, 0xc418, 0x21, 0 + .dw 0x4480, 0xc418, 0x4480, 0xc418, 0x22, 0 + .dw 0x4481, 0xc418, 0x4481, 0xc418, 0x21, 0 + .dw 0x4482, 0xc418, 0x4482, 0xc418, 0x22, 0 + .dw 0x4483, 0xc418, 0x448f, 0xc418, 0x21, 0 + .dw 0x4490, 0xc418, 0x4490, 0xc418, 0x22, 0 + .dw 0x4491, 0xc418, 0x4491, 0xc418, 0x21, 0 + .dw 0x4492, 0xc418, 0x4492, 0xc418, 0x22, 0 + .dw 0x4493, 0xc418, 0x44bf, 0xc418, 0x21, 0 + .dw 0x44c1, 0xc418, 0x44c1, 0xc418, 0x21, 0 + .dw 0x44c3, 0xc418, 0x44cf, 0xc418, 0x21, 0 + .dw 0x44d1, 0xc418, 0x44d1, 0xc418, 0x21, 0 + .dw 0x44d3, 0xc418, 0x44ff, 0xc418, 0x21, 0 + .dw 0x4501, 0xc418, 0x4501, 0xc418, 0x21, 0 + .dw 0x4503, 0xc418, 0x450f, 0xc418, 0x21, 0 + .dw 0x4511, 0xc418, 0x4511, 0xc418, 0x21, 0 + .dw 0x4513, 0xc418, 0x453f, 0xc418, 0x21, 0 + .dw 0x4541, 0xc418, 0x4541, 0xc418, 0x21, 0 + .dw 0x4543, 0xc418, 0x454f, 0xc418, 0x21, 0 + .dw 0x4551, 0xc418, 0x4551, 0xc418, 0x21, 0 + .dw 0x4553, 0xc418, 0x457f, 0xc418, 0x21, 0 + .dw 0x4581, 0xc418, 0x4581, 0xc418, 0x21, 0 + .dw 0x4583, 0xc418, 0x458f, 0xc418, 0x21, 0 + .dw 0x4591, 0xc418, 0x4591, 0xc418, 0x21, 0 + .dw 0x4593, 0xc418, 0x45bf, 0xc418, 0x21, 0 + .dw 0x45c1, 0xc418, 0x45c1, 0xc418, 0x21, 0 + .dw 0x45c3, 0xc418, 0x45cf, 0xc418, 0x21, 0 + .dw 0x45d1, 0xc418, 0x45d1, 0xc418, 0x21, 0 + .dw 0x45d3, 0xc418, 0x45ff, 0xc418, 0x21, 0 + .dw 0x4601, 0xc418, 0x4601, 0xc418, 0x21, 0 + .dw 0x4603, 0xc418, 0x460f, 0xc418, 0x21, 0 + .dw 0x4611, 0xc418, 0x4611, 0xc418, 0x21, 0 + .dw 0x4613, 0xc418, 0x463f, 0xc418, 0x21, 0 + .dw 0x4641, 0xc418, 0x4641, 0xc418, 0x21, 0 + .dw 0x4643, 0xc418, 0x464f, 0xc418, 0x21, 0 + .dw 0x4651, 0xc418, 0x4651, 0xc418, 0x21, 0 + .dw 0x4653, 0xc418, 0x467f, 0xc418, 0x21, 0 + .dw 0x4681, 0xc418, 0x4681, 0xc418, 0x21, 0 + .dw 0x4683, 0xc418, 0x468f, 0xc418, 0x21, 0 + .dw 0x4691, 0xc418, 0x4691, 0xc418, 0x21, 0 + .dw 0x4693, 0xc418, 0x46bf, 0xc418, 0x21, 0 + .dw 0x46c0, 0xc418, 0x46c0, 0xc418, 0x22, 0 + .dw 0x46c1, 0xc418, 0x46c1, 0xc418, 0x21, 0 + .dw 0x46c2, 0xc418, 0x46c2, 0xc418, 0x22, 0 + .dw 0x46c3, 0xc418, 0x46cf, 0xc418, 0x21, 0 + .dw 0x46d0, 0xc418, 0x46d0, 0xc418, 0x22, 0 + .dw 0x46d1, 0xc418, 0x46d1, 0xc418, 0x21, 0 + .dw 0x46d2, 0xc418, 0x46d2, 0xc418, 0x22, 0 + .dw 0x46d3, 0xc418, 0x46ff, 0xc418, 0x21, 0 + .dw 0x4701, 0xc418, 0x4701, 0xc418, 0x21, 0 + .dw 0x4703, 0xc418, 0x470f, 0xc418, 0x21, 0 + .dw 0x4711, 0xc418, 0x4711, 0xc418, 0x21, 0 + .dw 0x4713, 0xc418, 0x473f, 0xc418, 0x21, 0 + .dw 0x4741, 0xc418, 0x4741, 0xc418, 0x21, 0 + .dw 0x4743, 0xc418, 0x474f, 0xc418, 0x21, 0 + .dw 0x4751, 0xc418, 0x4751, 0xc418, 0x21, 0 + .dw 0x4753, 0xc418, 0x477f, 0xc418, 0x21, 0 + .dw 0x4781, 0xc418, 0x4781, 0xc418, 0x21, 0 + .dw 0x4783, 0xc418, 0x478f, 0xc418, 0x21, 0 + .dw 0x4791, 0xc418, 0x4791, 0xc418, 0x21, 0 + .dw 0x4793, 0xc418, 0x47bf, 0xc418, 0x21, 0 + .dw 0x47c1, 0xc418, 0x47c1, 0xc418, 0x21, 0 + .dw 0x47c3, 0xc418, 0x47cf, 0xc418, 0x21, 0 + .dw 0x47d1, 0xc418, 0x47d1, 0xc418, 0x21, 0 + .dw 0x47d3, 0xc418, 0x47ff, 0xc418, 0x21, 0 + .dw 0x4801, 0xc418, 0x4801, 0xc418, 0x21, 0 + .dw 0x4803, 0xc418, 0x480f, 0xc418, 0x21, 0 + .dw 0x4811, 0xc418, 0x4811, 0xc418, 0x21, 0 + .dw 0x4813, 0xc418, 0x483f, 0xc418, 0x21, 0 + .dw 0x4841, 0xc418, 0x4841, 0xc418, 0x21, 0 + .dw 0x4843, 0xc418, 0x484f, 0xc418, 0x21, 0 + .dw 0x4851, 0xc418, 0x4851, 0xc418, 0x21, 0 + .dw 0x4853, 0xc418, 0x487f, 0xc418, 0x21, 0 + .dw 0x4881, 0xc418, 0x4881, 0xc418, 0x21, 0 + .dw 0x4883, 0xc418, 0x488f, 0xc418, 0x21, 0 + .dw 0x4891, 0xc418, 0x4891, 0xc418, 0x21, 0 + .dw 0x4893, 0xc418, 0x48bf, 0xc418, 0x21, 0 + .dw 0x48c1, 0xc418, 0x48c1, 0xc418, 0x21, 0 + .dw 0x48c3, 0xc418, 0x48cf, 0xc418, 0x21, 0 + .dw 0x48d1, 0xc418, 0x48d1, 0xc418, 0x21, 0 + .dw 0x48d3, 0xc418, 0x48ff, 0xc418, 0x21, 0 + .dw 0x4900, 0xc418, 0x4900, 0xc418, 0x22, 0 + .dw 0x4901, 0xc418, 0x4901, 0xc418, 0x21, 0 + .dw 0x4902, 0xc418, 0x4902, 0xc418, 0x22, 0 + .dw 0x4903, 0xc418, 0x490f, 0xc418, 0x21, 0 + .dw 0x4910, 0xc418, 0x4910, 0xc418, 0x22, 0 + .dw 0x4911, 0xc418, 0x4911, 0xc418, 0x21, 0 + .dw 0x4912, 0xc418, 0x4912, 0xc418, 0x22, 0 + .dw 0x4913, 0xc418, 0x493f, 0xc418, 0x21, 0 + .dw 0x4941, 0xc418, 0x4941, 0xc418, 0x21, 0 + .dw 0x4943, 0xc418, 0x494f, 0xc418, 0x21, 0 + .dw 0x4951, 0xc418, 0x4951, 0xc418, 0x21, 0 + .dw 0x4953, 0xc418, 0x497f, 0xc418, 0x21, 0 + .dw 0x4981, 0xc418, 0x4981, 0xc418, 0x21, 0 + .dw 0x4983, 0xc418, 0x498f, 0xc418, 0x21, 0 + .dw 0x4991, 0xc418, 0x4991, 0xc418, 0x21, 0 + .dw 0x4993, 0xc418, 0x49bf, 0xc418, 0x21, 0 + .dw 0x49c1, 0xc418, 0x49c1, 0xc418, 0x21, 0 + .dw 0x49c3, 0xc418, 0x49cf, 0xc418, 0x21, 0 + .dw 0x49d1, 0xc418, 0x49d1, 0xc418, 0x21, 0 + .dw 0x49d3, 0xc418, 0x49ff, 0xc418, 0x21, 0 + .dw 0x4a01, 0xc418, 0x4a01, 0xc418, 0x21, 0 + .dw 0x4a03, 0xc418, 0x4a0f, 0xc418, 0x21, 0 + .dw 0x4a11, 0xc418, 0x4a11, 0xc418, 0x21, 0 + .dw 0x4a13, 0xc418, 0x4a3f, 0xc418, 0x21, 0 + .dw 0x4a41, 0xc418, 0x4a41, 0xc418, 0x21, 0 + .dw 0x4a43, 0xc418, 0x4a4f, 0xc418, 0x21, 0 + .dw 0x4a51, 0xc418, 0x4a51, 0xc418, 0x21, 0 + .dw 0x4a53, 0xc418, 0x4a7f, 0xc418, 0x21, 0 + .dw 0x4a81, 0xc418, 0x4a81, 0xc418, 0x21, 0 + .dw 0x4a83, 0xc418, 0x4a8f, 0xc418, 0x21, 0 + .dw 0x4a91, 0xc418, 0x4a91, 0xc418, 0x21, 0 + .dw 0x4a93, 0xc418, 0x4abf, 0xc418, 0x21, 0 + .dw 0x4ac1, 0xc418, 0x4ac1, 0xc418, 0x21, 0 + .dw 0x4ac3, 0xc418, 0x4acf, 0xc418, 0x21, 0 + .dw 0x4ad1, 0xc418, 0x4ad1, 0xc418, 0x21, 0 + .dw 0x4ad3, 0xc418, 0x4aff, 0xc418, 0x21, 0 + .dw 0x4b01, 0xc418, 0x4b01, 0xc418, 0x21, 0 + .dw 0x4b03, 0xc418, 0x4b0f, 0xc418, 0x21, 0 + .dw 0x4b11, 0xc418, 0x4b11, 0xc418, 0x21, 0 + .dw 0x4b13, 0xc418, 0x4b3f, 0xc418, 0x21, 0 + .dw 0x4b40, 0xc418, 0x4b40, 0xc418, 0x22, 0 + .dw 0x4b41, 0xc418, 0x4b41, 0xc418, 0x21, 0 + .dw 0x4b42, 0xc418, 0x4b42, 0xc418, 0x22, 0 + .dw 0x4b43, 0xc418, 0x4b4f, 0xc418, 0x21, 0 + .dw 0x4b50, 0xc418, 0x4b50, 0xc418, 0x22, 0 + .dw 0x4b51, 0xc418, 0x4b51, 0xc418, 0x21, 0 + .dw 0x4b52, 0xc418, 0x4b52, 0xc418, 0x22, 0 + .dw 0x4b53, 0xc418, 0x4b7f, 0xc418, 0x21, 0 + .dw 0x4b81, 0xc418, 0x4b81, 0xc418, 0x21, 0 + .dw 0x4b83, 0xc418, 0x4b8f, 0xc418, 0x21, 0 + .dw 0x4b91, 0xc418, 0x4b91, 0xc418, 0x21, 0 + .dw 0x4b93, 0xc418, 0x4bbf, 0xc418, 0x21, 0 + .dw 0x4bc1, 0xc418, 0x4bc1, 0xc418, 0x21, 0 + .dw 0x4bc3, 0xc418, 0x4bcf, 0xc418, 0x21, 0 + .dw 0x4bd1, 0xc418, 0x4bd1, 0xc418, 0x21, 0 + .dw 0x4bd3, 0xc418, 0x4bff, 0xc418, 0x21, 0 + .dw 0x4c01, 0xc418, 0x4c01, 0xc418, 0x21, 0 + .dw 0x4c03, 0xc418, 0x4c0f, 0xc418, 0x21, 0 + .dw 0x4c11, 0xc418, 0x4c11, 0xc418, 0x21, 0 + .dw 0x4c13, 0xc418, 0x4c3f, 0xc418, 0x21, 0 + .dw 0x4c41, 0xc418, 0x4c41, 0xc418, 0x21, 0 + .dw 0x4c43, 0xc418, 0x4c4f, 0xc418, 0x21, 0 + .dw 0x4c51, 0xc418, 0x4c51, 0xc418, 0x21, 0 + .dw 0x4c53, 0xc418, 0x4c7f, 0xc418, 0x21, 0 + .dw 0x4c81, 0xc418, 0x4c81, 0xc418, 0x21, 0 + .dw 0x4c83, 0xc418, 0x4c8f, 0xc418, 0x21, 0 + .dw 0x4c91, 0xc418, 0x4c91, 0xc418, 0x21, 0 + .dw 0x4c93, 0xc418, 0x4cbf, 0xc418, 0x21, 0 + .dw 0x4cc1, 0xc418, 0x4cc1, 0xc418, 0x21, 0 + .dw 0x4cc3, 0xc418, 0x4ccf, 0xc418, 0x21, 0 + .dw 0x4cd1, 0xc418, 0x4cd1, 0xc418, 0x21, 0 + .dw 0x4cd3, 0xc418, 0x4cff, 0xc418, 0x21, 0 + .dw 0x4d01, 0xc418, 0x4d01, 0xc418, 0x21, 0 + .dw 0x4d03, 0xc418, 0x4d0f, 0xc418, 0x21, 0 + .dw 0x4d11, 0xc418, 0x4d11, 0xc418, 0x21, 0 + .dw 0x4d13, 0xc418, 0x4d3f, 0xc418, 0x21, 0 + .dw 0x4d41, 0xc418, 0x4d41, 0xc418, 0x21, 0 + .dw 0x4d43, 0xc418, 0x4d4f, 0xc418, 0x21, 0 + .dw 0x4d51, 0xc418, 0x4d51, 0xc418, 0x21, 0 + .dw 0x4d53, 0xc418, 0x4d7f, 0xc418, 0x21, 0 + .dw 0x4d80, 0xc418, 0x4d80, 0xc418, 0x22, 0 + .dw 0x4d81, 0xc418, 0x4d81, 0xc418, 0x21, 0 + .dw 0x4d82, 0xc418, 0x4d82, 0xc418, 0x22, 0 + .dw 0x4d83, 0xc418, 0x4d8f, 0xc418, 0x21, 0 + .dw 0x4d90, 0xc418, 0x4d90, 0xc418, 0x22, 0 + .dw 0x4d91, 0xc418, 0x4d91, 0xc418, 0x21, 0 + .dw 0x4d92, 0xc418, 0x4d92, 0xc418, 0x22, 0 + .dw 0x4d93, 0xc418, 0x4dbf, 0xc418, 0x21, 0 + .dw 0x4dc1, 0xc418, 0x4dc1, 0xc418, 0x21, 0 + .dw 0x4dc3, 0xc418, 0x4dcf, 0xc418, 0x21, 0 + .dw 0x4dd1, 0xc418, 0x4dd1, 0xc418, 0x21, 0 + .dw 0x4dd3, 0xc418, 0x4dff, 0xc418, 0x21, 0 + .dw 0x4e01, 0xc418, 0x4e01, 0xc418, 0x21, 0 + .dw 0x4e03, 0xc418, 0x4e0f, 0xc418, 0x21, 0 + .dw 0x4e11, 0xc418, 0x4e11, 0xc418, 0x21, 0 + .dw 0x4e13, 0xc418, 0x4e3f, 0xc418, 0x21, 0 + .dw 0x4e41, 0xc418, 0x4e41, 0xc418, 0x21, 0 + .dw 0x4e43, 0xc418, 0x4e4f, 0xc418, 0x21, 0 + .dw 0x4e51, 0xc418, 0x4e51, 0xc418, 0x21, 0 + .dw 0x4e53, 0xc418, 0x4e7f, 0xc418, 0x21, 0 + .dw 0x4e81, 0xc418, 0x4e81, 0xc418, 0x21, 0 + .dw 0x4e83, 0xc418, 0x4e8f, 0xc418, 0x21, 0 + .dw 0x4e91, 0xc418, 0x4e91, 0xc418, 0x21, 0 + .dw 0x4e93, 0xc418, 0x4ebf, 0xc418, 0x21, 0 + .dw 0x4ec1, 0xc418, 0x4ec1, 0xc418, 0x21, 0 + .dw 0x4ec3, 0xc418, 0x4ecf, 0xc418, 0x21, 0 + .dw 0x4ed1, 0xc418, 0x4ed1, 0xc418, 0x21, 0 + .dw 0x4ed3, 0xc418, 0x4eff, 0xc418, 0x21, 0 + .dw 0x4f01, 0xc418, 0x4f01, 0xc418, 0x21, 0 + .dw 0x4f03, 0xc418, 0x4f0f, 0xc418, 0x21, 0 + .dw 0x4f11, 0xc418, 0x4f11, 0xc418, 0x21, 0 + .dw 0x4f13, 0xc418, 0x4f3f, 0xc418, 0x21, 0 + .dw 0x4f41, 0xc418, 0x4f41, 0xc418, 0x21, 0 + .dw 0x4f43, 0xc418, 0x4f4f, 0xc418, 0x21, 0 + .dw 0x4f51, 0xc418, 0x4f51, 0xc418, 0x21, 0 + .dw 0x4f53, 0xc418, 0x4f7f, 0xc418, 0x21, 0 + .dw 0x4f81, 0xc418, 0x4f81, 0xc418, 0x21, 0 + .dw 0x4f83, 0xc418, 0x4f8f, 0xc418, 0x21, 0 + .dw 0x4f91, 0xc418, 0x4f91, 0xc418, 0x21, 0 + .dw 0x4f93, 0xc418, 0x4fbf, 0xc418, 0x21, 0 + .dw 0x4fc0, 0xc418, 0x4fc0, 0xc418, 0x22, 0 + .dw 0x4fc1, 0xc418, 0x4fc1, 0xc418, 0x21, 0 + .dw 0x4fc2, 0xc418, 0x4fc2, 0xc418, 0x22, 0 + .dw 0x4fc3, 0xc418, 0x4fcf, 0xc418, 0x21, 0 + .dw 0x4fd0, 0xc418, 0x4fd0, 0xc418, 0x22, 0 + .dw 0x4fd1, 0xc418, 0x4fd1, 0xc418, 0x21, 0 + .dw 0x4fd2, 0xc418, 0x4fd2, 0xc418, 0x22, 0 + .dw 0x4fd3, 0xc418, 0x5fff, 0xc418, 0x21, 0 + .dw 0x6000, 0xc418, 0x6000, 0xc418, 0x22, 0 + .dw 0x6001, 0xc418, 0x6001, 0xc418, 0x21, 0 + .dw 0x6002, 0xc418, 0x6002, 0xc418, 0x22, 0 + .dw 0x6003, 0xc418, 0x600f, 0xc418, 0x21, 0 + .dw 0x6010, 0xc418, 0x6010, 0xc418, 0x22, 0 + .dw 0x6011, 0xc418, 0x6011, 0xc418, 0x21, 0 + .dw 0x6012, 0xc418, 0x6012, 0xc418, 0x22, 0 + .dw 0x6013, 0xc418, 0x603f, 0xc418, 0x21, 0 + .dw 0x6041, 0xc418, 0x6041, 0xc418, 0x21, 0 + .dw 0x6043, 0xc418, 0x604f, 0xc418, 0x21, 0 + .dw 0x6051, 0xc418, 0x6051, 0xc418, 0x21, 0 + .dw 0x6053, 0xc418, 0x607f, 0xc418, 0x21, 0 + .dw 0x6081, 0xc418, 0x6081, 0xc418, 0x21, 0 + .dw 0x6083, 0xc418, 0x608f, 0xc418, 0x21, 0 + .dw 0x6091, 0xc418, 0x6091, 0xc418, 0x21, 0 + .dw 0x6093, 0xc418, 0x60bf, 0xc418, 0x21, 0 + .dw 0x60c1, 0xc418, 0x60c1, 0xc418, 0x21, 0 + .dw 0x60c3, 0xc418, 0x60cf, 0xc418, 0x21, 0 + .dw 0x60d1, 0xc418, 0x60d1, 0xc418, 0x21, 0 + .dw 0x60d3, 0xc418, 0x60ff, 0xc418, 0x21, 0 + .dw 0x6101, 0xc418, 0x6101, 0xc418, 0x21, 0 + .dw 0x6103, 0xc418, 0x610f, 0xc418, 0x21, 0 + .dw 0x6111, 0xc418, 0x6111, 0xc418, 0x21, 0 + .dw 0x6113, 0xc418, 0x613f, 0xc418, 0x21, 0 + .dw 0x6141, 0xc418, 0x6141, 0xc418, 0x21, 0 + .dw 0x6143, 0xc418, 0x614f, 0xc418, 0x21, 0 + .dw 0x6151, 0xc418, 0x6151, 0xc418, 0x21, 0 + .dw 0x6153, 0xc418, 0x617f, 0xc418, 0x21, 0 + .dw 0x6181, 0xc418, 0x6181, 0xc418, 0x21, 0 + .dw 0x6183, 0xc418, 0x618f, 0xc418, 0x21, 0 + .dw 0x6191, 0xc418, 0x6191, 0xc418, 0x21, 0 + .dw 0x6193, 0xc418, 0x61bf, 0xc418, 0x21, 0 + .dw 0x61c1, 0xc418, 0x61c1, 0xc418, 0x21, 0 + .dw 0x61c3, 0xc418, 0x61cf, 0xc418, 0x21, 0 + .dw 0x61d1, 0xc418, 0x61d1, 0xc418, 0x21, 0 + .dw 0x61d3, 0xc418, 0x61ff, 0xc418, 0x21, 0 + .dw 0x6201, 0xc418, 0x6201, 0xc418, 0x21, 0 + .dw 0x6203, 0xc418, 0x620f, 0xc418, 0x21, 0 + .dw 0x6211, 0xc418, 0x6211, 0xc418, 0x21, 0 + .dw 0x6213, 0xc418, 0x623f, 0xc418, 0x21, 0 + .dw 0x6240, 0xc418, 0x6240, 0xc418, 0x22, 0 + .dw 0x6241, 0xc418, 0x6241, 0xc418, 0x21, 0 + .dw 0x6242, 0xc418, 0x6242, 0xc418, 0x22, 0 + .dw 0x6243, 0xc418, 0x624f, 0xc418, 0x21, 0 + .dw 0x6250, 0xc418, 0x6250, 0xc418, 0x22, 0 + .dw 0x6251, 0xc418, 0x6251, 0xc418, 0x21, 0 + .dw 0x6252, 0xc418, 0x6252, 0xc418, 0x22, 0 + .dw 0x6253, 0xc418, 0x627f, 0xc418, 0x21, 0 + .dw 0x6281, 0xc418, 0x6281, 0xc418, 0x21, 0 + .dw 0x6283, 0xc418, 0x628f, 0xc418, 0x21, 0 + .dw 0x6291, 0xc418, 0x6291, 0xc418, 0x21, 0 + .dw 0x6293, 0xc418, 0x62bf, 0xc418, 0x21, 0 + .dw 0x62c1, 0xc418, 0x62c1, 0xc418, 0x21, 0 + .dw 0x62c3, 0xc418, 0x62cf, 0xc418, 0x21, 0 + .dw 0x62d1, 0xc418, 0x62d1, 0xc418, 0x21, 0 + .dw 0x62d3, 0xc418, 0x62ff, 0xc418, 0x21, 0 + .dw 0x6301, 0xc418, 0x6301, 0xc418, 0x21, 0 + .dw 0x6303, 0xc418, 0x630f, 0xc418, 0x21, 0 + .dw 0x6311, 0xc418, 0x6311, 0xc418, 0x21, 0 + .dw 0x6313, 0xc418, 0x633f, 0xc418, 0x21, 0 + .dw 0x6341, 0xc418, 0x6341, 0xc418, 0x21, 0 + .dw 0x6343, 0xc418, 0x634f, 0xc418, 0x21, 0 + .dw 0x6351, 0xc418, 0x6351, 0xc418, 0x21, 0 + .dw 0x6353, 0xc418, 0x637f, 0xc418, 0x21, 0 + .dw 0x6381, 0xc418, 0x6381, 0xc418, 0x21, 0 + .dw 0x6383, 0xc418, 0x638f, 0xc418, 0x21, 0 + .dw 0x6391, 0xc418, 0x6391, 0xc418, 0x21, 0 + .dw 0x6393, 0xc418, 0x63bf, 0xc418, 0x21, 0 + .dw 0x63c1, 0xc418, 0x63c1, 0xc418, 0x21, 0 + .dw 0x63c3, 0xc418, 0x63cf, 0xc418, 0x21, 0 + .dw 0x63d1, 0xc418, 0x63d1, 0xc418, 0x21, 0 + .dw 0x63d3, 0xc418, 0x63ff, 0xc418, 0x21, 0 + .dw 0x6401, 0xc418, 0x6401, 0xc418, 0x21, 0 + .dw 0x6403, 0xc418, 0x640f, 0xc418, 0x21, 0 + .dw 0x6411, 0xc418, 0x6411, 0xc418, 0x21, 0 + .dw 0x6413, 0xc418, 0x643f, 0xc418, 0x21, 0 + .dw 0x6441, 0xc418, 0x6441, 0xc418, 0x21, 0 + .dw 0x6443, 0xc418, 0x644f, 0xc418, 0x21, 0 + .dw 0x6451, 0xc418, 0x6451, 0xc418, 0x21, 0 + .dw 0x6453, 0xc418, 0x647f, 0xc418, 0x21, 0 + .dw 0x6480, 0xc418, 0x6480, 0xc418, 0x22, 0 + .dw 0x6481, 0xc418, 0x6481, 0xc418, 0x21, 0 + .dw 0x6482, 0xc418, 0x6482, 0xc418, 0x22, 0 + .dw 0x6483, 0xc418, 0x648f, 0xc418, 0x21, 0 + .dw 0x6490, 0xc418, 0x6490, 0xc418, 0x22, 0 + .dw 0x6491, 0xc418, 0x6491, 0xc418, 0x21, 0 + .dw 0x6492, 0xc418, 0x6492, 0xc418, 0x22, 0 + .dw 0x6493, 0xc418, 0x64bf, 0xc418, 0x21, 0 + .dw 0x64c1, 0xc418, 0x64c1, 0xc418, 0x21, 0 + .dw 0x64c3, 0xc418, 0x64cf, 0xc418, 0x21, 0 + .dw 0x64d1, 0xc418, 0x64d1, 0xc418, 0x21, 0 + .dw 0x64d3, 0xc418, 0x64ff, 0xc418, 0x21, 0 + .dw 0x6501, 0xc418, 0x6501, 0xc418, 0x21, 0 + .dw 0x6503, 0xc418, 0x650f, 0xc418, 0x21, 0 + .dw 0x6511, 0xc418, 0x6511, 0xc418, 0x21, 0 + .dw 0x6513, 0xc418, 0x653f, 0xc418, 0x21, 0 + .dw 0x6541, 0xc418, 0x6541, 0xc418, 0x21, 0 + .dw 0x6543, 0xc418, 0x654f, 0xc418, 0x21, 0 + .dw 0x6551, 0xc418, 0x6551, 0xc418, 0x21, 0 + .dw 0x6553, 0xc418, 0x657f, 0xc418, 0x21, 0 + .dw 0x6581, 0xc418, 0x6581, 0xc418, 0x21, 0 + .dw 0x6583, 0xc418, 0x658f, 0xc418, 0x21, 0 + .dw 0x6591, 0xc418, 0x6591, 0xc418, 0x21, 0 + .dw 0x6593, 0xc418, 0x65bf, 0xc418, 0x21, 0 + .dw 0x65c1, 0xc418, 0x65c1, 0xc418, 0x21, 0 + .dw 0x65c3, 0xc418, 0x65cf, 0xc418, 0x21, 0 + .dw 0x65d1, 0xc418, 0x65d1, 0xc418, 0x21, 0 + .dw 0x65d3, 0xc418, 0x65ff, 0xc418, 0x21, 0 + .dw 0x6601, 0xc418, 0x6601, 0xc418, 0x21, 0 + .dw 0x6603, 0xc418, 0x660f, 0xc418, 0x21, 0 + .dw 0x6611, 0xc418, 0x6611, 0xc418, 0x21, 0 + .dw 0x6613, 0xc418, 0x663f, 0xc418, 0x21, 0 + .dw 0x6641, 0xc418, 0x6641, 0xc418, 0x21, 0 + .dw 0x6643, 0xc418, 0x664f, 0xc418, 0x21, 0 + .dw 0x6651, 0xc418, 0x6651, 0xc418, 0x21, 0 + .dw 0x6653, 0xc418, 0x667f, 0xc418, 0x21, 0 + .dw 0x6681, 0xc418, 0x6681, 0xc418, 0x21, 0 + .dw 0x6683, 0xc418, 0x668f, 0xc418, 0x21, 0 + .dw 0x6691, 0xc418, 0x6691, 0xc418, 0x21, 0 + .dw 0x6693, 0xc418, 0x66bf, 0xc418, 0x21, 0 + .dw 0x66c0, 0xc418, 0x66c0, 0xc418, 0x22, 0 + .dw 0x66c1, 0xc418, 0x66c1, 0xc418, 0x21, 0 + .dw 0x66c2, 0xc418, 0x66c2, 0xc418, 0x22, 0 + .dw 0x66c3, 0xc418, 0x66cf, 0xc418, 0x21, 0 + .dw 0x66d0, 0xc418, 0x66d0, 0xc418, 0x22, 0 + .dw 0x66d1, 0xc418, 0x66d1, 0xc418, 0x21, 0 + .dw 0x66d2, 0xc418, 0x66d2, 0xc418, 0x22, 0 + .dw 0x66d3, 0xc418, 0x66ff, 0xc418, 0x21, 0 + .dw 0x6701, 0xc418, 0x6701, 0xc418, 0x21, 0 + .dw 0x6703, 0xc418, 0x670f, 0xc418, 0x21, 0 + .dw 0x6711, 0xc418, 0x6711, 0xc418, 0x21, 0 + .dw 0x6713, 0xc418, 0x673f, 0xc418, 0x21, 0 + .dw 0x6741, 0xc418, 0x6741, 0xc418, 0x21, 0 + .dw 0x6743, 0xc418, 0x674f, 0xc418, 0x21, 0 + .dw 0x6751, 0xc418, 0x6751, 0xc418, 0x21, 0 + .dw 0x6753, 0xc418, 0x677f, 0xc418, 0x21, 0 + .dw 0x6781, 0xc418, 0x6781, 0xc418, 0x21, 0 + .dw 0x6783, 0xc418, 0x678f, 0xc418, 0x21, 0 + .dw 0x6791, 0xc418, 0x6791, 0xc418, 0x21, 0 + .dw 0x6793, 0xc418, 0x67bf, 0xc418, 0x21, 0 + .dw 0x67c1, 0xc418, 0x67c1, 0xc418, 0x21, 0 + .dw 0x67c3, 0xc418, 0x67cf, 0xc418, 0x21, 0 + .dw 0x67d1, 0xc418, 0x67d1, 0xc418, 0x21, 0 + .dw 0x67d3, 0xc418, 0x67ff, 0xc418, 0x21, 0 + .dw 0x6801, 0xc418, 0x6801, 0xc418, 0x21, 0 + .dw 0x6803, 0xc418, 0x680f, 0xc418, 0x21, 0 + .dw 0x6811, 0xc418, 0x6811, 0xc418, 0x21, 0 + .dw 0x6813, 0xc418, 0x683f, 0xc418, 0x21, 0 + .dw 0x6841, 0xc418, 0x6841, 0xc418, 0x21, 0 + .dw 0x6843, 0xc418, 0x684f, 0xc418, 0x21, 0 + .dw 0x6851, 0xc418, 0x6851, 0xc418, 0x21, 0 + .dw 0x6853, 0xc418, 0x687f, 0xc418, 0x21, 0 + .dw 0x6881, 0xc418, 0x6881, 0xc418, 0x21, 0 + .dw 0x6883, 0xc418, 0x688f, 0xc418, 0x21, 0 + .dw 0x6891, 0xc418, 0x6891, 0xc418, 0x21, 0 + .dw 0x6893, 0xc418, 0x68bf, 0xc418, 0x21, 0 + .dw 0x68c1, 0xc418, 0x68c1, 0xc418, 0x21, 0 + .dw 0x68c3, 0xc418, 0x68cf, 0xc418, 0x21, 0 + .dw 0x68d1, 0xc418, 0x68d1, 0xc418, 0x21, 0 + .dw 0x68d3, 0xc418, 0x68ff, 0xc418, 0x21, 0 + .dw 0x6900, 0xc418, 0x6900, 0xc418, 0x22, 0 + .dw 0x6901, 0xc418, 0x6901, 0xc418, 0x21, 0 + .dw 0x6902, 0xc418, 0x6902, 0xc418, 0x22, 0 + .dw 0x6903, 0xc418, 0x690f, 0xc418, 0x21, 0 + .dw 0x6910, 0xc418, 0x6910, 0xc418, 0x22, 0 + .dw 0x6911, 0xc418, 0x6911, 0xc418, 0x21, 0 + .dw 0x6912, 0xc418, 0x6912, 0xc418, 0x22, 0 + .dw 0x6913, 0xc418, 0x693f, 0xc418, 0x21, 0 + .dw 0x6941, 0xc418, 0x6941, 0xc418, 0x21, 0 + .dw 0x6943, 0xc418, 0x694f, 0xc418, 0x21, 0 + .dw 0x6951, 0xc418, 0x6951, 0xc418, 0x21, 0 + .dw 0x6953, 0xc418, 0x697f, 0xc418, 0x21, 0 + .dw 0x6981, 0xc418, 0x6981, 0xc418, 0x21, 0 + .dw 0x6983, 0xc418, 0x698f, 0xc418, 0x21, 0 + .dw 0x6991, 0xc418, 0x6991, 0xc418, 0x21, 0 + .dw 0x6993, 0xc418, 0x69bf, 0xc418, 0x21, 0 + .dw 0x69c1, 0xc418, 0x69c1, 0xc418, 0x21, 0 + .dw 0x69c3, 0xc418, 0x69cf, 0xc418, 0x21, 0 + .dw 0x69d1, 0xc418, 0x69d1, 0xc418, 0x21, 0 + .dw 0x69d3, 0xc418, 0x69ff, 0xc418, 0x21, 0 + .dw 0x6a01, 0xc418, 0x6a01, 0xc418, 0x21, 0 + .dw 0x6a03, 0xc418, 0x6a0f, 0xc418, 0x21, 0 + .dw 0x6a11, 0xc418, 0x6a11, 0xc418, 0x21, 0 + .dw 0x6a13, 0xc418, 0x6a3f, 0xc418, 0x21, 0 + .dw 0x6a41, 0xc418, 0x6a41, 0xc418, 0x21, 0 + .dw 0x6a43, 0xc418, 0x6a4f, 0xc418, 0x21, 0 + .dw 0x6a51, 0xc418, 0x6a51, 0xc418, 0x21, 0 + .dw 0x6a53, 0xc418, 0x6a7f, 0xc418, 0x21, 0 + .dw 0x6a81, 0xc418, 0x6a81, 0xc418, 0x21, 0 + .dw 0x6a83, 0xc418, 0x6a8f, 0xc418, 0x21, 0 + .dw 0x6a91, 0xc418, 0x6a91, 0xc418, 0x21, 0 + .dw 0x6a93, 0xc418, 0x6abf, 0xc418, 0x21, 0 + .dw 0x6ac1, 0xc418, 0x6ac1, 0xc418, 0x21, 0 + .dw 0x6ac3, 0xc418, 0x6acf, 0xc418, 0x21, 0 + .dw 0x6ad1, 0xc418, 0x6ad1, 0xc418, 0x21, 0 + .dw 0x6ad3, 0xc418, 0x6aff, 0xc418, 0x21, 0 + .dw 0x6b01, 0xc418, 0x6b01, 0xc418, 0x21, 0 + .dw 0x6b03, 0xc418, 0x6b0f, 0xc418, 0x21, 0 + .dw 0x6b11, 0xc418, 0x6b11, 0xc418, 0x21, 0 + .dw 0x6b13, 0xc418, 0x6b3f, 0xc418, 0x21, 0 + .dw 0x6b40, 0xc418, 0x6b40, 0xc418, 0x22, 0 + .dw 0x6b41, 0xc418, 0x6b41, 0xc418, 0x21, 0 + .dw 0x6b42, 0xc418, 0x6b42, 0xc418, 0x22, 0 + .dw 0x6b43, 0xc418, 0x6b4f, 0xc418, 0x21, 0 + .dw 0x6b50, 0xc418, 0x6b50, 0xc418, 0x22, 0 + .dw 0x6b51, 0xc418, 0x6b51, 0xc418, 0x21, 0 + .dw 0x6b52, 0xc418, 0x6b52, 0xc418, 0x22, 0 + .dw 0x6b53, 0xc418, 0x6b7f, 0xc418, 0x21, 0 + .dw 0x6b81, 0xc418, 0x6b81, 0xc418, 0x21, 0 + .dw 0x6b83, 0xc418, 0x6b8f, 0xc418, 0x21, 0 + .dw 0x6b91, 0xc418, 0x6b91, 0xc418, 0x21, 0 + .dw 0x6b93, 0xc418, 0x6bbf, 0xc418, 0x21, 0 + .dw 0x6bc1, 0xc418, 0x6bc1, 0xc418, 0x21, 0 + .dw 0x6bc3, 0xc418, 0x6bcf, 0xc418, 0x21, 0 + .dw 0x6bd1, 0xc418, 0x6bd1, 0xc418, 0x21, 0 + .dw 0x6bd3, 0xc418, 0x6bff, 0xc418, 0x21, 0 + .dw 0x6c01, 0xc418, 0x6c01, 0xc418, 0x21, 0 + .dw 0x6c03, 0xc418, 0x6c0f, 0xc418, 0x21, 0 + .dw 0x6c11, 0xc418, 0x6c11, 0xc418, 0x21, 0 + .dw 0x6c13, 0xc418, 0x6c3f, 0xc418, 0x21, 0 + .dw 0x6c41, 0xc418, 0x6c41, 0xc418, 0x21, 0 + .dw 0x6c43, 0xc418, 0x6c4f, 0xc418, 0x21, 0 + .dw 0x6c51, 0xc418, 0x6c51, 0xc418, 0x21, 0 + .dw 0x6c53, 0xc418, 0x6c7f, 0xc418, 0x21, 0 + .dw 0x6c81, 0xc418, 0x6c81, 0xc418, 0x21, 0 + .dw 0x6c83, 0xc418, 0x6c8f, 0xc418, 0x21, 0 + .dw 0x6c91, 0xc418, 0x6c91, 0xc418, 0x21, 0 + .dw 0x6c93, 0xc418, 0x6cbf, 0xc418, 0x21, 0 + .dw 0x6cc1, 0xc418, 0x6cc1, 0xc418, 0x21, 0 + .dw 0x6cc3, 0xc418, 0x6ccf, 0xc418, 0x21, 0 + .dw 0x6cd1, 0xc418, 0x6cd1, 0xc418, 0x21, 0 + .dw 0x6cd3, 0xc418, 0x6cff, 0xc418, 0x21, 0 + .dw 0x6d01, 0xc418, 0x6d01, 0xc418, 0x21, 0 + .dw 0x6d03, 0xc418, 0x6d0f, 0xc418, 0x21, 0 + .dw 0x6d11, 0xc418, 0x6d11, 0xc418, 0x21, 0 + .dw 0x6d13, 0xc418, 0x6d3f, 0xc418, 0x21, 0 + .dw 0x6d41, 0xc418, 0x6d41, 0xc418, 0x21, 0 + .dw 0x6d43, 0xc418, 0x6d4f, 0xc418, 0x21, 0 + .dw 0x6d51, 0xc418, 0x6d51, 0xc418, 0x21, 0 + .dw 0x6d53, 0xc418, 0x6d7f, 0xc418, 0x21, 0 + .dw 0x6d80, 0xc418, 0x6d80, 0xc418, 0x22, 0 + .dw 0x6d81, 0xc418, 0x6d81, 0xc418, 0x21, 0 + .dw 0x6d82, 0xc418, 0x6d82, 0xc418, 0x22, 0 + .dw 0x6d83, 0xc418, 0x6d8f, 0xc418, 0x21, 0 + .dw 0x6d90, 0xc418, 0x6d90, 0xc418, 0x22, 0 + .dw 0x6d91, 0xc418, 0x6d91, 0xc418, 0x21, 0 + .dw 0x6d92, 0xc418, 0x6d92, 0xc418, 0x22, 0 + .dw 0x6d93, 0xc418, 0x6dbf, 0xc418, 0x21, 0 + .dw 0x6dc1, 0xc418, 0x6dc1, 0xc418, 0x21, 0 + .dw 0x6dc3, 0xc418, 0x6dcf, 0xc418, 0x21, 0 + .dw 0x6dd1, 0xc418, 0x6dd1, 0xc418, 0x21, 0 + .dw 0x6dd3, 0xc418, 0x6dff, 0xc418, 0x21, 0 + .dw 0x6e01, 0xc418, 0x6e01, 0xc418, 0x21, 0 + .dw 0x6e03, 0xc418, 0x6e0f, 0xc418, 0x21, 0 + .dw 0x6e11, 0xc418, 0x6e11, 0xc418, 0x21, 0 + .dw 0x6e13, 0xc418, 0x6e3f, 0xc418, 0x21, 0 + .dw 0x6e41, 0xc418, 0x6e41, 0xc418, 0x21, 0 + .dw 0x6e43, 0xc418, 0x6e4f, 0xc418, 0x21, 0 + .dw 0x6e51, 0xc418, 0x6e51, 0xc418, 0x21, 0 + .dw 0x6e53, 0xc418, 0x6e7f, 0xc418, 0x21, 0 + .dw 0x6e81, 0xc418, 0x6e81, 0xc418, 0x21, 0 + .dw 0x6e83, 0xc418, 0x6e8f, 0xc418, 0x21, 0 + .dw 0x6e91, 0xc418, 0x6e91, 0xc418, 0x21, 0 + .dw 0x6e93, 0xc418, 0x6ebf, 0xc418, 0x21, 0 + .dw 0x6ec1, 0xc418, 0x6ec1, 0xc418, 0x21, 0 + .dw 0x6ec3, 0xc418, 0x6ecf, 0xc418, 0x21, 0 + .dw 0x6ed1, 0xc418, 0x6ed1, 0xc418, 0x21, 0 + .dw 0x6ed3, 0xc418, 0x6eff, 0xc418, 0x21, 0 + .dw 0x6f01, 0xc418, 0x6f01, 0xc418, 0x21, 0 + .dw 0x6f03, 0xc418, 0x6f0f, 0xc418, 0x21, 0 + .dw 0x6f11, 0xc418, 0x6f11, 0xc418, 0x21, 0 + .dw 0x6f13, 0xc418, 0x6f3f, 0xc418, 0x21, 0 + .dw 0x6f41, 0xc418, 0x6f41, 0xc418, 0x21, 0 + .dw 0x6f43, 0xc418, 0x6f4f, 0xc418, 0x21, 0 + .dw 0x6f51, 0xc418, 0x6f51, 0xc418, 0x21, 0 + .dw 0x6f53, 0xc418, 0x6f7f, 0xc418, 0x21, 0 + .dw 0x6f81, 0xc418, 0x6f81, 0xc418, 0x21, 0 + .dw 0x6f83, 0xc418, 0x6f8f, 0xc418, 0x21, 0 + .dw 0x6f91, 0xc418, 0x6f91, 0xc418, 0x21, 0 + .dw 0x6f93, 0xc418, 0x6fbf, 0xc418, 0x21, 0 + .dw 0x6fc0, 0xc418, 0x6fc0, 0xc418, 0x22, 0 + .dw 0x6fc1, 0xc418, 0x6fc1, 0xc418, 0x21, 0 + .dw 0x6fc2, 0xc418, 0x6fc2, 0xc418, 0x22, 0 + .dw 0x6fc3, 0xc418, 0x6fcf, 0xc418, 0x21, 0 + .dw 0x6fd0, 0xc418, 0x6fd0, 0xc418, 0x22, 0 + .dw 0x6fd1, 0xc418, 0x6fd1, 0xc418, 0x21, 0 + .dw 0x6fd2, 0xc418, 0x6fd2, 0xc418, 0x22, 0 + .dw 0x6fd3, 0xc418, 0xffff, 0xc420, 0x21, 0 + .dw 0x0000, 0xc421, 0x003f, 0xc421, 0x22, 0 + .dw 0x0240, 0xc421, 0x027f, 0xc421, 0x22, 0 + .dw 0x0480, 0xc421, 0x04bf, 0xc421, 0x22, 0 + .dw 0x06c0, 0xc421, 0x06ff, 0xc421, 0x22, 0 + .dw 0x0900, 0xc421, 0x093f, 0xc421, 0x22, 0 + .dw 0x0b40, 0xc421, 0x0b7f, 0xc421, 0x22, 0 + .dw 0x0d80, 0xc421, 0x0dbf, 0xc421, 0x22, 0 + .dw 0x0fc0, 0xc421, 0x103f, 0xc421, 0x22, 0 + .dw 0x1240, 0xc421, 0x127f, 0xc421, 0x22, 0 + .dw 0x1480, 0xc421, 0x14bf, 0xc421, 0x22, 0 + .dw 0x16c0, 0xc421, 0x16ff, 0xc421, 0x22, 0 + .dw 0x1900, 0xc421, 0x193f, 0xc421, 0x22, 0 + .dw 0x1b40, 0xc421, 0x1b7f, 0xc421, 0x22, 0 + .dw 0x1d80, 0xc421, 0x1dbf, 0xc421, 0x22, 0 + .dw 0x1fc0, 0xc421, 0x203f, 0xc421, 0x22, 0 + .dw 0x2240, 0xc421, 0x227f, 0xc421, 0x22, 0 + .dw 0x2480, 0xc421, 0x24bf, 0xc421, 0x22, 0 + .dw 0x26c0, 0xc421, 0x26ff, 0xc421, 0x22, 0 + .dw 0x2900, 0xc421, 0x293f, 0xc421, 0x22, 0 + .dw 0x2b40, 0xc421, 0x2b7f, 0xc421, 0x22, 0 + .dw 0x2d80, 0xc421, 0x2dbf, 0xc421, 0x22, 0 + .dw 0x2fc0, 0xc421, 0x303f, 0xc421, 0x22, 0 + .dw 0x3240, 0xc421, 0x327f, 0xc421, 0x22, 0 + .dw 0x3480, 0xc421, 0x34bf, 0xc421, 0x22, 0 + .dw 0x36c0, 0xc421, 0x36ff, 0xc421, 0x22, 0 + .dw 0x3900, 0xc421, 0x393f, 0xc421, 0x22, 0 + .dw 0x3b40, 0xc421, 0x3b7f, 0xc421, 0x22, 0 + .dw 0x3d80, 0xc421, 0x3dbf, 0xc421, 0x22, 0 + .dw 0x3fc0, 0xc421, 0x3fff, 0xc421, 0x22, 0 + .dw 0x4000, 0xc421, 0x7fff, 0xc421, 0x21, 0 + .dw 0x8000, 0xc421, 0x803f, 0xc421, 0x22, 0 + .dw 0x8240, 0xc421, 0x827f, 0xc421, 0x22, 0 + .dw 0x8480, 0xc421, 0x84bf, 0xc421, 0x22, 0 + .dw 0x86c0, 0xc421, 0x86ff, 0xc421, 0x22, 0 + .dw 0x8900, 0xc421, 0x893f, 0xc421, 0x22, 0 + .dw 0x8b40, 0xc421, 0x8b7f, 0xc421, 0x22, 0 + .dw 0x8d80, 0xc421, 0x8dbf, 0xc421, 0x22, 0 + .dw 0x8fc0, 0xc421, 0x903f, 0xc421, 0x22, 0 + .dw 0x9240, 0xc421, 0x927f, 0xc421, 0x22, 0 + .dw 0x9480, 0xc421, 0x94bf, 0xc421, 0x22, 0 + .dw 0x96c0, 0xc421, 0x96ff, 0xc421, 0x22, 0 + .dw 0x9900, 0xc421, 0x993f, 0xc421, 0x22, 0 + .dw 0x9b40, 0xc421, 0x9b7f, 0xc421, 0x22, 0 + .dw 0x9d80, 0xc421, 0x9dbf, 0xc421, 0x22, 0 + .dw 0x9fc0, 0xc421, 0xa03f, 0xc421, 0x22, 0 + .dw 0xa240, 0xc421, 0xa27f, 0xc421, 0x22, 0 + .dw 0xa480, 0xc421, 0xa4bf, 0xc421, 0x22, 0 + .dw 0xa6c0, 0xc421, 0xa6ff, 0xc421, 0x22, 0 + .dw 0xa900, 0xc421, 0xa93f, 0xc421, 0x22, 0 + .dw 0xab40, 0xc421, 0xab7f, 0xc421, 0x22, 0 + .dw 0xad80, 0xc421, 0xadbf, 0xc421, 0x22, 0 + .dw 0xafc0, 0xc421, 0xb03f, 0xc421, 0x22, 0 + .dw 0xb240, 0xc421, 0xb27f, 0xc421, 0x22, 0 + .dw 0xb480, 0xc421, 0xb4bf, 0xc421, 0x22, 0 + .dw 0xb6c0, 0xc421, 0xb6ff, 0xc421, 0x22, 0 + .dw 0xb900, 0xc421, 0xb93f, 0xc421, 0x22, 0 + .dw 0xbb40, 0xc421, 0xbb7f, 0xc421, 0x22, 0 + .dw 0xbd80, 0xc421, 0xbdbf, 0xc421, 0x22, 0 + .dw 0xbfc0, 0xc421, 0xc03f, 0xc421, 0x22, 0 + .dw 0xc240, 0xc421, 0xc27f, 0xc421, 0x22, 0 + .dw 0xc480, 0xc421, 0xc4bf, 0xc421, 0x22, 0 + .dw 0xc6c0, 0xc421, 0xc6ff, 0xc421, 0x22, 0 + .dw 0xc900, 0xc421, 0xc93f, 0xc421, 0x22, 0 + .dw 0xcb40, 0xc421, 0xcb7f, 0xc421, 0x22, 0 + .dw 0xcd80, 0xc421, 0xcdbf, 0xc421, 0x22, 0 + .dw 0xcfc0, 0xc421, 0xd03f, 0xc421, 0x22, 0 + .dw 0xd240, 0xc421, 0xd27f, 0xc421, 0x22, 0 + .dw 0xd480, 0xc421, 0xd4bf, 0xc421, 0x22, 0 + .dw 0xd6c0, 0xc421, 0xd6ff, 0xc421, 0x22, 0 + .dw 0xd900, 0xc421, 0xd93f, 0xc421, 0x22, 0 + .dw 0xdb40, 0xc421, 0xdb7f, 0xc421, 0x22, 0 + .dw 0xdd80, 0xc421, 0xddbf, 0xc421, 0x22, 0 + .dw 0xdfc0, 0xc421, 0xe03f, 0xc421, 0x22, 0 + .dw 0xe240, 0xc421, 0xe27f, 0xc421, 0x22, 0 + .dw 0xe480, 0xc421, 0xe4bf, 0xc421, 0x22, 0 + .dw 0xe6c0, 0xc421, 0xe6ff, 0xc421, 0x22, 0 + .dw 0xe900, 0xc421, 0xe93f, 0xc421, 0x22, 0 + .dw 0xeb40, 0xc421, 0xeb7f, 0xc421, 0x22, 0 + .dw 0xed80, 0xc421, 0xedbf, 0xc421, 0x22, 0 + .dw 0xefc0, 0xc421, 0xf03f, 0xc421, 0x22, 0 + .dw 0xf240, 0xc421, 0xf27f, 0xc421, 0x22, 0 + .dw 0xf480, 0xc421, 0xf4bf, 0xc421, 0x22, 0 + .dw 0xf6c0, 0xc421, 0xf6ff, 0xc421, 0x22, 0 + .dw 0xf900, 0xc421, 0xf93f, 0xc421, 0x22, 0 + .dw 0xfb40, 0xc421, 0xfb7f, 0xc421, 0x22, 0 + .dw 0xfd80, 0xc421, 0xfdbf, 0xc421, 0x22, 0 + .dw 0xffc0, 0xc421, 0xffff, 0xc421, 0x22, 0 + .dw 0x1000, 0xc422, 0x1fff, 0xc422, 0x21, 0 + .dw 0x3000, 0xc422, 0x3fff, 0xc422, 0x21, 0 + .dw 0x5000, 0xc422, 0x5fff, 0xc422, 0x21, 0 + .dw 0x7000, 0xc422, 0x7fff, 0xc422, 0x21, 0 + .dw 0x9000, 0xc422, 0x9fff, 0xc422, 0x21, 0 + .dw 0xb000, 0xc422, 0xbfff, 0xc422, 0x21, 0 + .dw 0xd000, 0xc422, 0xdfff, 0xc422, 0x21, 0 + .dw 0xf000, 0xc422, 0xffff, 0xc422, 0x21, 0 + .dw 0x1000, 0xc423, 0x1fff, 0xc423, 0x21, 0 + .dw 0x3000, 0xc423, 0x3fff, 0xc423, 0x21, 0 + .dw 0x5000, 0xc423, 0x5fff, 0xc423, 0x21, 0 + .dw 0x7000, 0xc423, 0x7fff, 0xc423, 0x21, 0 + .dw 0x9000, 0xc423, 0x9fff, 0xc423, 0x21, 0 + .dw 0xb000, 0xc423, 0xbfff, 0xc423, 0x21, 0 + .dw 0xd000, 0xc423, 0xdfff, 0xc423, 0x21, 0 + .dw 0xf000, 0xc423, 0xffff, 0xc424, 0x21, 0 + .dw 0x1000, 0xc425, 0x3fff, 0xc425, 0x21, 0 + .dw 0x5000, 0xc425, 0x8fff, 0xc425, 0x21, 0 + .dw 0xa000, 0xc425, 0xcfff, 0xc425, 0x21, 0 + .dw 0xe000, 0xc425, 0xffff, 0xc428, 0x21, 0 + .dw 0x1000, 0xc429, 0x7fff, 0xc429, 0x21, 0 + .dw 0x9000, 0xc429, 0xffff, 0xc42a, 0x21, 0 + .dw 0x1000, 0xc42b, 0x3fff, 0xc42b, 0x21, 0 + .dw 0x5000, 0xc42b, 0xbfff, 0xc42c, 0x21, 0 + .dw 0xd000, 0xc42c, 0xffff, 0xc42d, 0x21, 0 + .dw 0x1000, 0xc42e, 0x3fff, 0xc42e, 0x21, 0 + .dw 0x5000, 0xc42e, 0xffff, 0xc42f, 0x21, 0 + .dw 0x1000, 0xc430, 0x3fff, 0xc430, 0x21, 0 + .dw 0x5000, 0xc430, 0xffff, 0xc435, 0x21, 0 + .dw 0x0001, 0xc436, 0x0001, 0xc436, 0x21, 0 + .dw 0x0003, 0xc436, 0x000f, 0xc436, 0x21, 0 + .dw 0x0011, 0xc436, 0x0011, 0xc436, 0x21, 0 + .dw 0x0013, 0xc436, 0x003f, 0xc436, 0x21, 0 + .dw 0x0041, 0xc436, 0x0041, 0xc436, 0x21, 0 + .dw 0x0043, 0xc436, 0x004f, 0xc436, 0x21, 0 + .dw 0x0051, 0xc436, 0x0051, 0xc436, 0x21, 0 + .dw 0x0053, 0xc436, 0x007f, 0xc436, 0x21, 0 + .dw 0x0081, 0xc436, 0x0081, 0xc436, 0x21, 0 + .dw 0x0083, 0xc436, 0x008f, 0xc436, 0x21, 0 + .dw 0x0091, 0xc436, 0x0091, 0xc436, 0x21, 0 + .dw 0x0093, 0xc436, 0x00bf, 0xc436, 0x21, 0 + .dw 0x00c1, 0xc436, 0x00c1, 0xc436, 0x21, 0 + .dw 0x00c3, 0xc436, 0x00cf, 0xc436, 0x21, 0 + .dw 0x00d1, 0xc436, 0x00d1, 0xc436, 0x21, 0 + .dw 0x00d3, 0xc436, 0x00ff, 0xc436, 0x21, 0 + .dw 0x0101, 0xc436, 0x0101, 0xc436, 0x21, 0 + .dw 0x0103, 0xc436, 0x010f, 0xc436, 0x21, 0 + .dw 0x0111, 0xc436, 0x0111, 0xc436, 0x21, 0 + .dw 0x0113, 0xc436, 0x013f, 0xc436, 0x21, 0 + .dw 0x0141, 0xc436, 0x0141, 0xc436, 0x21, 0 + .dw 0x0143, 0xc436, 0x014f, 0xc436, 0x21, 0 + .dw 0x0151, 0xc436, 0x0151, 0xc436, 0x21, 0 + .dw 0x0153, 0xc436, 0x017f, 0xc436, 0x21, 0 + .dw 0x0181, 0xc436, 0x0181, 0xc436, 0x21, 0 + .dw 0x0183, 0xc436, 0x018f, 0xc436, 0x21, 0 + .dw 0x0191, 0xc436, 0x0191, 0xc436, 0x21, 0 + .dw 0x0193, 0xc436, 0x01bf, 0xc436, 0x21, 0 + .dw 0x01c1, 0xc436, 0x01c1, 0xc436, 0x21, 0 + .dw 0x01c3, 0xc436, 0x01cf, 0xc436, 0x21, 0 + .dw 0x01d1, 0xc436, 0x01d1, 0xc436, 0x21, 0 + .dw 0x01d3, 0xc436, 0x01ff, 0xc436, 0x21, 0 + .dw 0x0201, 0xc436, 0x0201, 0xc436, 0x21, 0 + .dw 0x0203, 0xc436, 0x020f, 0xc436, 0x21, 0 + .dw 0x0211, 0xc436, 0x0211, 0xc436, 0x21, 0 + .dw 0x0213, 0xc436, 0x023f, 0xc436, 0x21, 0 + .dw 0x0241, 0xc436, 0x0241, 0xc436, 0x21, 0 + .dw 0x0243, 0xc436, 0x024f, 0xc436, 0x21, 0 + .dw 0x0251, 0xc436, 0x0251, 0xc436, 0x21, 0 + .dw 0x0253, 0xc436, 0x027f, 0xc436, 0x21, 0 + .dw 0x0281, 0xc436, 0x0281, 0xc436, 0x21, 0 + .dw 0x0283, 0xc436, 0x028f, 0xc436, 0x21, 0 + .dw 0x0291, 0xc436, 0x0291, 0xc436, 0x21, 0 + .dw 0x0293, 0xc436, 0x02bf, 0xc436, 0x21, 0 + .dw 0x02c1, 0xc436, 0x02c1, 0xc436, 0x21, 0 + .dw 0x02c3, 0xc436, 0x02cf, 0xc436, 0x21, 0 + .dw 0x02d1, 0xc436, 0x02d1, 0xc436, 0x21, 0 + .dw 0x02d3, 0xc436, 0x02ff, 0xc436, 0x21, 0 + .dw 0x0301, 0xc436, 0x0301, 0xc436, 0x21, 0 + .dw 0x0303, 0xc436, 0x030f, 0xc436, 0x21, 0 + .dw 0x0311, 0xc436, 0x0311, 0xc436, 0x21, 0 + .dw 0x0313, 0xc436, 0x033f, 0xc436, 0x21, 0 + .dw 0x0341, 0xc436, 0x0341, 0xc436, 0x21, 0 + .dw 0x0343, 0xc436, 0x034f, 0xc436, 0x21, 0 + .dw 0x0351, 0xc436, 0x0351, 0xc436, 0x21, 0 + .dw 0x0353, 0xc436, 0x037f, 0xc436, 0x21, 0 + .dw 0x0381, 0xc436, 0x0381, 0xc436, 0x21, 0 + .dw 0x0383, 0xc436, 0x038f, 0xc436, 0x21, 0 + .dw 0x0391, 0xc436, 0x0391, 0xc436, 0x21, 0 + .dw 0x0393, 0xc436, 0x03bf, 0xc436, 0x21, 0 + .dw 0x03c1, 0xc436, 0x03c1, 0xc436, 0x21, 0 + .dw 0x03c3, 0xc436, 0x03cf, 0xc436, 0x21, 0 + .dw 0x03d1, 0xc436, 0x03d1, 0xc436, 0x21, 0 + .dw 0x03d3, 0xc436, 0x03ff, 0xc436, 0x21, 0 + .dw 0x0401, 0xc436, 0x0401, 0xc436, 0x21, 0 + .dw 0x0403, 0xc436, 0x040f, 0xc436, 0x21, 0 + .dw 0x0411, 0xc436, 0x0411, 0xc436, 0x21, 0 + .dw 0x0413, 0xc436, 0x043f, 0xc436, 0x21, 0 + .dw 0x0441, 0xc436, 0x0441, 0xc436, 0x21, 0 + .dw 0x0443, 0xc436, 0x044f, 0xc436, 0x21, 0 + .dw 0x0451, 0xc436, 0x0451, 0xc436, 0x21, 0 + .dw 0x0453, 0xc436, 0x047f, 0xc436, 0x21, 0 + .dw 0x0481, 0xc436, 0x0481, 0xc436, 0x21, 0 + .dw 0x0483, 0xc436, 0x048f, 0xc436, 0x21, 0 + .dw 0x0491, 0xc436, 0x0491, 0xc436, 0x21, 0 + .dw 0x0493, 0xc436, 0x04bf, 0xc436, 0x21, 0 + .dw 0x04c1, 0xc436, 0x04c1, 0xc436, 0x21, 0 + .dw 0x04c3, 0xc436, 0x04cf, 0xc436, 0x21, 0 + .dw 0x04d1, 0xc436, 0x04d1, 0xc436, 0x21, 0 + .dw 0x04d3, 0xc436, 0x04ff, 0xc436, 0x21, 0 + .dw 0x0501, 0xc436, 0x0501, 0xc436, 0x21, 0 + .dw 0x0503, 0xc436, 0x050f, 0xc436, 0x21, 0 + .dw 0x0511, 0xc436, 0x0511, 0xc436, 0x21, 0 + .dw 0x0513, 0xc436, 0x053f, 0xc436, 0x21, 0 + .dw 0x0541, 0xc436, 0x0541, 0xc436, 0x21, 0 + .dw 0x0543, 0xc436, 0x054f, 0xc436, 0x21, 0 + .dw 0x0551, 0xc436, 0x0551, 0xc436, 0x21, 0 + .dw 0x0553, 0xc436, 0x057f, 0xc436, 0x21, 0 + .dw 0x0581, 0xc436, 0x0581, 0xc436, 0x21, 0 + .dw 0x0583, 0xc436, 0x058f, 0xc436, 0x21, 0 + .dw 0x0591, 0xc436, 0x0591, 0xc436, 0x21, 0 + .dw 0x0593, 0xc436, 0x05bf, 0xc436, 0x21, 0 + .dw 0x05c1, 0xc436, 0x05c1, 0xc436, 0x21, 0 + .dw 0x05c3, 0xc436, 0x05cf, 0xc436, 0x21, 0 + .dw 0x05d1, 0xc436, 0x05d1, 0xc436, 0x21, 0 + .dw 0x05d3, 0xc436, 0x05ff, 0xc436, 0x21, 0 + .dw 0x0601, 0xc436, 0x0601, 0xc436, 0x21, 0 + .dw 0x0603, 0xc436, 0x060f, 0xc436, 0x21, 0 + .dw 0x0611, 0xc436, 0x0611, 0xc436, 0x21, 0 + .dw 0x0613, 0xc436, 0x063f, 0xc436, 0x21, 0 + .dw 0x0641, 0xc436, 0x0641, 0xc436, 0x21, 0 + .dw 0x0643, 0xc436, 0x064f, 0xc436, 0x21, 0 + .dw 0x0651, 0xc436, 0x0651, 0xc436, 0x21, 0 + .dw 0x0653, 0xc436, 0x067f, 0xc436, 0x21, 0 + .dw 0x0681, 0xc436, 0x0681, 0xc436, 0x21, 0 + .dw 0x0683, 0xc436, 0x068f, 0xc436, 0x21, 0 + .dw 0x0691, 0xc436, 0x0691, 0xc436, 0x21, 0 + .dw 0x0693, 0xc436, 0x06bf, 0xc436, 0x21, 0 + .dw 0x06c1, 0xc436, 0x06c1, 0xc436, 0x21, 0 + .dw 0x06c3, 0xc436, 0x06cf, 0xc436, 0x21, 0 + .dw 0x06d1, 0xc436, 0x06d1, 0xc436, 0x21, 0 + .dw 0x06d3, 0xc436, 0x06ff, 0xc436, 0x21, 0 + .dw 0x0701, 0xc436, 0x0701, 0xc436, 0x21, 0 + .dw 0x0703, 0xc436, 0x070f, 0xc436, 0x21, 0 + .dw 0x0711, 0xc436, 0x0711, 0xc436, 0x21, 0 + .dw 0x0713, 0xc436, 0x073f, 0xc436, 0x21, 0 + .dw 0x0741, 0xc436, 0x0741, 0xc436, 0x21, 0 + .dw 0x0743, 0xc436, 0x074f, 0xc436, 0x21, 0 + .dw 0x0751, 0xc436, 0x0751, 0xc436, 0x21, 0 + .dw 0x0753, 0xc436, 0x077f, 0xc436, 0x21, 0 + .dw 0x0781, 0xc436, 0x0781, 0xc436, 0x21, 0 + .dw 0x0783, 0xc436, 0x078f, 0xc436, 0x21, 0 + .dw 0x0791, 0xc436, 0x0791, 0xc436, 0x21, 0 + .dw 0x0793, 0xc436, 0x07bf, 0xc436, 0x21, 0 + .dw 0x07c1, 0xc436, 0x07c1, 0xc436, 0x21, 0 + .dw 0x07c3, 0xc436, 0x07cf, 0xc436, 0x21, 0 + .dw 0x07d1, 0xc436, 0x07d1, 0xc436, 0x21, 0 + .dw 0x07d3, 0xc436, 0x07ff, 0xc436, 0x21, 0 + .dw 0x0801, 0xc436, 0x0801, 0xc436, 0x21, 0 + .dw 0x0803, 0xc436, 0x080f, 0xc436, 0x21, 0 + .dw 0x0811, 0xc436, 0x0811, 0xc436, 0x21, 0 + .dw 0x0813, 0xc436, 0x083f, 0xc436, 0x21, 0 + .dw 0x0841, 0xc436, 0x0841, 0xc436, 0x21, 0 + .dw 0x0843, 0xc436, 0x084f, 0xc436, 0x21, 0 + .dw 0x0851, 0xc436, 0x0851, 0xc436, 0x21, 0 + .dw 0x0853, 0xc436, 0x087f, 0xc436, 0x21, 0 + .dw 0x0881, 0xc436, 0x0881, 0xc436, 0x21, 0 + .dw 0x0883, 0xc436, 0x088f, 0xc436, 0x21, 0 + .dw 0x0891, 0xc436, 0x0891, 0xc436, 0x21, 0 + .dw 0x0893, 0xc436, 0x08bf, 0xc436, 0x21, 0 + .dw 0x08c1, 0xc436, 0x08c1, 0xc436, 0x21, 0 + .dw 0x08c3, 0xc436, 0x08cf, 0xc436, 0x21, 0 + .dw 0x08d1, 0xc436, 0x08d1, 0xc436, 0x21, 0 + .dw 0x08d3, 0xc436, 0x08ff, 0xc436, 0x21, 0 + .dw 0x0901, 0xc436, 0x0901, 0xc436, 0x21, 0 + .dw 0x0903, 0xc436, 0x090f, 0xc436, 0x21, 0 + .dw 0x0911, 0xc436, 0x0911, 0xc436, 0x21, 0 + .dw 0x0913, 0xc436, 0x093f, 0xc436, 0x21, 0 + .dw 0x0941, 0xc436, 0x0941, 0xc436, 0x21, 0 + .dw 0x0943, 0xc436, 0x094f, 0xc436, 0x21, 0 + .dw 0x0951, 0xc436, 0x0951, 0xc436, 0x21, 0 + .dw 0x0953, 0xc436, 0x097f, 0xc436, 0x21, 0 + .dw 0x0981, 0xc436, 0x0981, 0xc436, 0x21, 0 + .dw 0x0983, 0xc436, 0x098f, 0xc436, 0x21, 0 + .dw 0x0991, 0xc436, 0x0991, 0xc436, 0x21, 0 + .dw 0x0993, 0xc436, 0x09bf, 0xc436, 0x21, 0 + .dw 0x09c1, 0xc436, 0x09c1, 0xc436, 0x21, 0 + .dw 0x09c3, 0xc436, 0x09cf, 0xc436, 0x21, 0 + .dw 0x09d1, 0xc436, 0x09d1, 0xc436, 0x21, 0 + .dw 0x09d3, 0xc436, 0x09ff, 0xc436, 0x21, 0 + .dw 0x0a01, 0xc436, 0x0a01, 0xc436, 0x21, 0 + .dw 0x0a03, 0xc436, 0x0a0f, 0xc436, 0x21, 0 + .dw 0x0a11, 0xc436, 0x0a11, 0xc436, 0x21, 0 + .dw 0x0a13, 0xc436, 0x0a3f, 0xc436, 0x21, 0 + .dw 0x0a41, 0xc436, 0x0a41, 0xc436, 0x21, 0 + .dw 0x0a43, 0xc436, 0x0a4f, 0xc436, 0x21, 0 + .dw 0x0a51, 0xc436, 0x0a51, 0xc436, 0x21, 0 + .dw 0x0a53, 0xc436, 0x0a7f, 0xc436, 0x21, 0 + .dw 0x0a81, 0xc436, 0x0a81, 0xc436, 0x21, 0 + .dw 0x0a83, 0xc436, 0x0a8f, 0xc436, 0x21, 0 + .dw 0x0a91, 0xc436, 0x0a91, 0xc436, 0x21, 0 + .dw 0x0a93, 0xc436, 0x0abf, 0xc436, 0x21, 0 + .dw 0x0ac1, 0xc436, 0x0ac1, 0xc436, 0x21, 0 + .dw 0x0ac3, 0xc436, 0x0acf, 0xc436, 0x21, 0 + .dw 0x0ad1, 0xc436, 0x0ad1, 0xc436, 0x21, 0 + .dw 0x0ad3, 0xc436, 0x0aff, 0xc436, 0x21, 0 + .dw 0x0b01, 0xc436, 0x0b01, 0xc436, 0x21, 0 + .dw 0x0b03, 0xc436, 0x0b0f, 0xc436, 0x21, 0 + .dw 0x0b11, 0xc436, 0x0b11, 0xc436, 0x21, 0 + .dw 0x0b13, 0xc436, 0x0b3f, 0xc436, 0x21, 0 + .dw 0x0b41, 0xc436, 0x0b41, 0xc436, 0x21, 0 + .dw 0x0b43, 0xc436, 0x0b4f, 0xc436, 0x21, 0 + .dw 0x0b51, 0xc436, 0x0b51, 0xc436, 0x21, 0 + .dw 0x0b53, 0xc436, 0x0b7f, 0xc436, 0x21, 0 + .dw 0x0b81, 0xc436, 0x0b81, 0xc436, 0x21, 0 + .dw 0x0b83, 0xc436, 0x0b8f, 0xc436, 0x21, 0 + .dw 0x0b91, 0xc436, 0x0b91, 0xc436, 0x21, 0 + .dw 0x0b93, 0xc436, 0x0bbf, 0xc436, 0x21, 0 + .dw 0x0bc1, 0xc436, 0x0bc1, 0xc436, 0x21, 0 + .dw 0x0bc3, 0xc436, 0x0bcf, 0xc436, 0x21, 0 + .dw 0x0bd1, 0xc436, 0x0bd1, 0xc436, 0x21, 0 + .dw 0x0bd3, 0xc436, 0x0bff, 0xc436, 0x21, 0 + .dw 0x0c01, 0xc436, 0x0c01, 0xc436, 0x21, 0 + .dw 0x0c03, 0xc436, 0x0c0f, 0xc436, 0x21, 0 + .dw 0x0c11, 0xc436, 0x0c11, 0xc436, 0x21, 0 + .dw 0x0c13, 0xc436, 0x0c3f, 0xc436, 0x21, 0 + .dw 0x0c41, 0xc436, 0x0c41, 0xc436, 0x21, 0 + .dw 0x0c43, 0xc436, 0x0c4f, 0xc436, 0x21, 0 + .dw 0x0c51, 0xc436, 0x0c51, 0xc436, 0x21, 0 + .dw 0x0c53, 0xc436, 0x0c7f, 0xc436, 0x21, 0 + .dw 0x0c81, 0xc436, 0x0c81, 0xc436, 0x21, 0 + .dw 0x0c83, 0xc436, 0x0c8f, 0xc436, 0x21, 0 + .dw 0x0c91, 0xc436, 0x0c91, 0xc436, 0x21, 0 + .dw 0x0c93, 0xc436, 0x0cbf, 0xc436, 0x21, 0 + .dw 0x0cc1, 0xc436, 0x0cc1, 0xc436, 0x21, 0 + .dw 0x0cc3, 0xc436, 0x0ccf, 0xc436, 0x21, 0 + .dw 0x0cd1, 0xc436, 0x0cd1, 0xc436, 0x21, 0 + .dw 0x0cd3, 0xc436, 0x0cff, 0xc436, 0x21, 0 + .dw 0x0d01, 0xc436, 0x0d01, 0xc436, 0x21, 0 + .dw 0x0d03, 0xc436, 0x0d0f, 0xc436, 0x21, 0 + .dw 0x0d11, 0xc436, 0x0d11, 0xc436, 0x21, 0 + .dw 0x0d13, 0xc436, 0x0d3f, 0xc436, 0x21, 0 + .dw 0x0d41, 0xc436, 0x0d41, 0xc436, 0x21, 0 + .dw 0x0d43, 0xc436, 0x0d4f, 0xc436, 0x21, 0 + .dw 0x0d51, 0xc436, 0x0d51, 0xc436, 0x21, 0 + .dw 0x0d53, 0xc436, 0x0d7f, 0xc436, 0x21, 0 + .dw 0x0d81, 0xc436, 0x0d81, 0xc436, 0x21, 0 + .dw 0x0d83, 0xc436, 0x0d8f, 0xc436, 0x21, 0 + .dw 0x0d91, 0xc436, 0x0d91, 0xc436, 0x21, 0 + .dw 0x0d93, 0xc436, 0x0dbf, 0xc436, 0x21, 0 + .dw 0x0dc1, 0xc436, 0x0dc1, 0xc436, 0x21, 0 + .dw 0x0dc3, 0xc436, 0x0dcf, 0xc436, 0x21, 0 + .dw 0x0dd1, 0xc436, 0x0dd1, 0xc436, 0x21, 0 + .dw 0x0dd3, 0xc436, 0x0dff, 0xc436, 0x21, 0 + .dw 0x0e01, 0xc436, 0x0e01, 0xc436, 0x21, 0 + .dw 0x0e03, 0xc436, 0x0e0f, 0xc436, 0x21, 0 + .dw 0x0e11, 0xc436, 0x0e11, 0xc436, 0x21, 0 + .dw 0x0e13, 0xc436, 0x0e3f, 0xc436, 0x21, 0 + .dw 0x0e41, 0xc436, 0x0e41, 0xc436, 0x21, 0 + .dw 0x0e43, 0xc436, 0x0e4f, 0xc436, 0x21, 0 + .dw 0x0e51, 0xc436, 0x0e51, 0xc436, 0x21, 0 + .dw 0x0e53, 0xc436, 0x0e7f, 0xc436, 0x21, 0 + .dw 0x0e81, 0xc436, 0x0e81, 0xc436, 0x21, 0 + .dw 0x0e83, 0xc436, 0x0e8f, 0xc436, 0x21, 0 + .dw 0x0e91, 0xc436, 0x0e91, 0xc436, 0x21, 0 + .dw 0x0e93, 0xc436, 0x0ebf, 0xc436, 0x21, 0 + .dw 0x0ec1, 0xc436, 0x0ec1, 0xc436, 0x21, 0 + .dw 0x0ec3, 0xc436, 0x0ecf, 0xc436, 0x21, 0 + .dw 0x0ed1, 0xc436, 0x0ed1, 0xc436, 0x21, 0 + .dw 0x0ed3, 0xc436, 0x0eff, 0xc436, 0x21, 0 + .dw 0x0f01, 0xc436, 0x0f01, 0xc436, 0x21, 0 + .dw 0x0f03, 0xc436, 0x0f0f, 0xc436, 0x21, 0 + .dw 0x0f11, 0xc436, 0x0f11, 0xc436, 0x21, 0 + .dw 0x0f13, 0xc436, 0x0f3f, 0xc436, 0x21, 0 + .dw 0x0f41, 0xc436, 0x0f41, 0xc436, 0x21, 0 + .dw 0x0f43, 0xc436, 0x0f4f, 0xc436, 0x21, 0 + .dw 0x0f51, 0xc436, 0x0f51, 0xc436, 0x21, 0 + .dw 0x0f53, 0xc436, 0x0f7f, 0xc436, 0x21, 0 + .dw 0x0f81, 0xc436, 0x0f81, 0xc436, 0x21, 0 + .dw 0x0f83, 0xc436, 0x0f8f, 0xc436, 0x21, 0 + .dw 0x0f91, 0xc436, 0x0f91, 0xc436, 0x21, 0 + .dw 0x0f93, 0xc436, 0x0fbf, 0xc436, 0x21, 0 + .dw 0x0fc1, 0xc436, 0x0fc1, 0xc436, 0x21, 0 + .dw 0x0fc3, 0xc436, 0x0fcf, 0xc436, 0x21, 0 + .dw 0x0fd1, 0xc436, 0x0fd1, 0xc436, 0x21, 0 + .dw 0x0fd3, 0xc436, 0x1fff, 0xc436, 0x21, 0 + .dw 0x2001, 0xc436, 0x2001, 0xc436, 0x21, 0 + .dw 0x2003, 0xc436, 0x200f, 0xc436, 0x21, 0 + .dw 0x2011, 0xc436, 0x2011, 0xc436, 0x21, 0 + .dw 0x2013, 0xc436, 0x203f, 0xc436, 0x21, 0 + .dw 0x2041, 0xc436, 0x2041, 0xc436, 0x21, 0 + .dw 0x2043, 0xc436, 0x204f, 0xc436, 0x21, 0 + .dw 0x2051, 0xc436, 0x2051, 0xc436, 0x21, 0 + .dw 0x2053, 0xc436, 0x207f, 0xc436, 0x21, 0 + .dw 0x2081, 0xc436, 0x2081, 0xc436, 0x21, 0 + .dw 0x2083, 0xc436, 0x208f, 0xc436, 0x21, 0 + .dw 0x2091, 0xc436, 0x2091, 0xc436, 0x21, 0 + .dw 0x2093, 0xc436, 0x20bf, 0xc436, 0x21, 0 + .dw 0x20c1, 0xc436, 0x20c1, 0xc436, 0x21, 0 + .dw 0x20c3, 0xc436, 0x20cf, 0xc436, 0x21, 0 + .dw 0x20d1, 0xc436, 0x20d1, 0xc436, 0x21, 0 + .dw 0x20d3, 0xc436, 0x20ff, 0xc436, 0x21, 0 + .dw 0x2101, 0xc436, 0x2101, 0xc436, 0x21, 0 + .dw 0x2103, 0xc436, 0x210f, 0xc436, 0x21, 0 + .dw 0x2111, 0xc436, 0x2111, 0xc436, 0x21, 0 + .dw 0x2113, 0xc436, 0x213f, 0xc436, 0x21, 0 + .dw 0x2141, 0xc436, 0x2141, 0xc436, 0x21, 0 + .dw 0x2143, 0xc436, 0x214f, 0xc436, 0x21, 0 + .dw 0x2151, 0xc436, 0x2151, 0xc436, 0x21, 0 + .dw 0x2153, 0xc436, 0x217f, 0xc436, 0x21, 0 + .dw 0x2181, 0xc436, 0x2181, 0xc436, 0x21, 0 + .dw 0x2183, 0xc436, 0x218f, 0xc436, 0x21, 0 + .dw 0x2191, 0xc436, 0x2191, 0xc436, 0x21, 0 + .dw 0x2193, 0xc436, 0x21bf, 0xc436, 0x21, 0 + .dw 0x21c1, 0xc436, 0x21c1, 0xc436, 0x21, 0 + .dw 0x21c3, 0xc436, 0x21cf, 0xc436, 0x21, 0 + .dw 0x21d1, 0xc436, 0x21d1, 0xc436, 0x21, 0 + .dw 0x21d3, 0xc436, 0x21ff, 0xc436, 0x21, 0 + .dw 0x2201, 0xc436, 0x2201, 0xc436, 0x21, 0 + .dw 0x2203, 0xc436, 0x220f, 0xc436, 0x21, 0 + .dw 0x2211, 0xc436, 0x2211, 0xc436, 0x21, 0 + .dw 0x2213, 0xc436, 0x223f, 0xc436, 0x21, 0 + .dw 0x2241, 0xc436, 0x2241, 0xc436, 0x21, 0 + .dw 0x2243, 0xc436, 0x224f, 0xc436, 0x21, 0 + .dw 0x2251, 0xc436, 0x2251, 0xc436, 0x21, 0 + .dw 0x2253, 0xc436, 0x227f, 0xc436, 0x21, 0 + .dw 0x2281, 0xc436, 0x2281, 0xc436, 0x21, 0 + .dw 0x2283, 0xc436, 0x228f, 0xc436, 0x21, 0 + .dw 0x2291, 0xc436, 0x2291, 0xc436, 0x21, 0 + .dw 0x2293, 0xc436, 0x22bf, 0xc436, 0x21, 0 + .dw 0x22c1, 0xc436, 0x22c1, 0xc436, 0x21, 0 + .dw 0x22c3, 0xc436, 0x22cf, 0xc436, 0x21, 0 + .dw 0x22d1, 0xc436, 0x22d1, 0xc436, 0x21, 0 + .dw 0x22d3, 0xc436, 0x22ff, 0xc436, 0x21, 0 + .dw 0x2301, 0xc436, 0x2301, 0xc436, 0x21, 0 + .dw 0x2303, 0xc436, 0x230f, 0xc436, 0x21, 0 + .dw 0x2311, 0xc436, 0x2311, 0xc436, 0x21, 0 + .dw 0x2313, 0xc436, 0x233f, 0xc436, 0x21, 0 + .dw 0x2341, 0xc436, 0x2341, 0xc436, 0x21, 0 + .dw 0x2343, 0xc436, 0x234f, 0xc436, 0x21, 0 + .dw 0x2351, 0xc436, 0x2351, 0xc436, 0x21, 0 + .dw 0x2353, 0xc436, 0x237f, 0xc436, 0x21, 0 + .dw 0x2381, 0xc436, 0x2381, 0xc436, 0x21, 0 + .dw 0x2383, 0xc436, 0x238f, 0xc436, 0x21, 0 + .dw 0x2391, 0xc436, 0x2391, 0xc436, 0x21, 0 + .dw 0x2393, 0xc436, 0x23bf, 0xc436, 0x21, 0 + .dw 0x23c1, 0xc436, 0x23c1, 0xc436, 0x21, 0 + .dw 0x23c3, 0xc436, 0x23cf, 0xc436, 0x21, 0 + .dw 0x23d1, 0xc436, 0x23d1, 0xc436, 0x21, 0 + .dw 0x23d3, 0xc436, 0x23ff, 0xc436, 0x21, 0 + .dw 0x2401, 0xc436, 0x2401, 0xc436, 0x21, 0 + .dw 0x2403, 0xc436, 0x240f, 0xc436, 0x21, 0 + .dw 0x2411, 0xc436, 0x2411, 0xc436, 0x21, 0 + .dw 0x2413, 0xc436, 0x243f, 0xc436, 0x21, 0 + .dw 0x2441, 0xc436, 0x2441, 0xc436, 0x21, 0 + .dw 0x2443, 0xc436, 0x244f, 0xc436, 0x21, 0 + .dw 0x2451, 0xc436, 0x2451, 0xc436, 0x21, 0 + .dw 0x2453, 0xc436, 0x247f, 0xc436, 0x21, 0 + .dw 0x2481, 0xc436, 0x2481, 0xc436, 0x21, 0 + .dw 0x2483, 0xc436, 0x248f, 0xc436, 0x21, 0 + .dw 0x2491, 0xc436, 0x2491, 0xc436, 0x21, 0 + .dw 0x2493, 0xc436, 0x24bf, 0xc436, 0x21, 0 + .dw 0x24c1, 0xc436, 0x24c1, 0xc436, 0x21, 0 + .dw 0x24c3, 0xc436, 0x24cf, 0xc436, 0x21, 0 + .dw 0x24d1, 0xc436, 0x24d1, 0xc436, 0x21, 0 + .dw 0x24d3, 0xc436, 0x24ff, 0xc436, 0x21, 0 + .dw 0x2501, 0xc436, 0x2501, 0xc436, 0x21, 0 + .dw 0x2503, 0xc436, 0x250f, 0xc436, 0x21, 0 + .dw 0x2511, 0xc436, 0x2511, 0xc436, 0x21, 0 + .dw 0x2513, 0xc436, 0x253f, 0xc436, 0x21, 0 + .dw 0x2541, 0xc436, 0x2541, 0xc436, 0x21, 0 + .dw 0x2543, 0xc436, 0x254f, 0xc436, 0x21, 0 + .dw 0x2551, 0xc436, 0x2551, 0xc436, 0x21, 0 + .dw 0x2553, 0xc436, 0x257f, 0xc436, 0x21, 0 + .dw 0x2581, 0xc436, 0x2581, 0xc436, 0x21, 0 + .dw 0x2583, 0xc436, 0x258f, 0xc436, 0x21, 0 + .dw 0x2591, 0xc436, 0x2591, 0xc436, 0x21, 0 + .dw 0x2593, 0xc436, 0x25bf, 0xc436, 0x21, 0 + .dw 0x25c1, 0xc436, 0x25c1, 0xc436, 0x21, 0 + .dw 0x25c3, 0xc436, 0x25cf, 0xc436, 0x21, 0 + .dw 0x25d1, 0xc436, 0x25d1, 0xc436, 0x21, 0 + .dw 0x25d3, 0xc436, 0x25ff, 0xc436, 0x21, 0 + .dw 0x2601, 0xc436, 0x2601, 0xc436, 0x21, 0 + .dw 0x2603, 0xc436, 0x260f, 0xc436, 0x21, 0 + .dw 0x2611, 0xc436, 0x2611, 0xc436, 0x21, 0 + .dw 0x2613, 0xc436, 0x263f, 0xc436, 0x21, 0 + .dw 0x2641, 0xc436, 0x2641, 0xc436, 0x21, 0 + .dw 0x2643, 0xc436, 0x264f, 0xc436, 0x21, 0 + .dw 0x2651, 0xc436, 0x2651, 0xc436, 0x21, 0 + .dw 0x2653, 0xc436, 0x267f, 0xc436, 0x21, 0 + .dw 0x2681, 0xc436, 0x2681, 0xc436, 0x21, 0 + .dw 0x2683, 0xc436, 0x268f, 0xc436, 0x21, 0 + .dw 0x2691, 0xc436, 0x2691, 0xc436, 0x21, 0 + .dw 0x2693, 0xc436, 0x26bf, 0xc436, 0x21, 0 + .dw 0x26c1, 0xc436, 0x26c1, 0xc436, 0x21, 0 + .dw 0x26c3, 0xc436, 0x26cf, 0xc436, 0x21, 0 + .dw 0x26d1, 0xc436, 0x26d1, 0xc436, 0x21, 0 + .dw 0x26d3, 0xc436, 0x26ff, 0xc436, 0x21, 0 + .dw 0x2701, 0xc436, 0x2701, 0xc436, 0x21, 0 + .dw 0x2703, 0xc436, 0x270f, 0xc436, 0x21, 0 + .dw 0x2711, 0xc436, 0x2711, 0xc436, 0x21, 0 + .dw 0x2713, 0xc436, 0x273f, 0xc436, 0x21, 0 + .dw 0x2741, 0xc436, 0x2741, 0xc436, 0x21, 0 + .dw 0x2743, 0xc436, 0x274f, 0xc436, 0x21, 0 + .dw 0x2751, 0xc436, 0x2751, 0xc436, 0x21, 0 + .dw 0x2753, 0xc436, 0x277f, 0xc436, 0x21, 0 + .dw 0x2781, 0xc436, 0x2781, 0xc436, 0x21, 0 + .dw 0x2783, 0xc436, 0x278f, 0xc436, 0x21, 0 + .dw 0x2791, 0xc436, 0x2791, 0xc436, 0x21, 0 + .dw 0x2793, 0xc436, 0x27bf, 0xc436, 0x21, 0 + .dw 0x27c1, 0xc436, 0x27c1, 0xc436, 0x21, 0 + .dw 0x27c3, 0xc436, 0x27cf, 0xc436, 0x21, 0 + .dw 0x27d1, 0xc436, 0x27d1, 0xc436, 0x21, 0 + .dw 0x27d3, 0xc436, 0x27ff, 0xc436, 0x21, 0 + .dw 0x2801, 0xc436, 0x2801, 0xc436, 0x21, 0 + .dw 0x2803, 0xc436, 0x280f, 0xc436, 0x21, 0 + .dw 0x2811, 0xc436, 0x2811, 0xc436, 0x21, 0 + .dw 0x2813, 0xc436, 0x283f, 0xc436, 0x21, 0 + .dw 0x2841, 0xc436, 0x2841, 0xc436, 0x21, 0 + .dw 0x2843, 0xc436, 0x284f, 0xc436, 0x21, 0 + .dw 0x2851, 0xc436, 0x2851, 0xc436, 0x21, 0 + .dw 0x2853, 0xc436, 0x287f, 0xc436, 0x21, 0 + .dw 0x2881, 0xc436, 0x2881, 0xc436, 0x21, 0 + .dw 0x2883, 0xc436, 0x288f, 0xc436, 0x21, 0 + .dw 0x2891, 0xc436, 0x2891, 0xc436, 0x21, 0 + .dw 0x2893, 0xc436, 0x28bf, 0xc436, 0x21, 0 + .dw 0x28c1, 0xc436, 0x28c1, 0xc436, 0x21, 0 + .dw 0x28c3, 0xc436, 0x28cf, 0xc436, 0x21, 0 + .dw 0x28d1, 0xc436, 0x28d1, 0xc436, 0x21, 0 + .dw 0x28d3, 0xc436, 0x28ff, 0xc436, 0x21, 0 + .dw 0x2901, 0xc436, 0x2901, 0xc436, 0x21, 0 + .dw 0x2903, 0xc436, 0x290f, 0xc436, 0x21, 0 + .dw 0x2911, 0xc436, 0x2911, 0xc436, 0x21, 0 + .dw 0x2913, 0xc436, 0x293f, 0xc436, 0x21, 0 + .dw 0x2941, 0xc436, 0x2941, 0xc436, 0x21, 0 + .dw 0x2943, 0xc436, 0x294f, 0xc436, 0x21, 0 + .dw 0x2951, 0xc436, 0x2951, 0xc436, 0x21, 0 + .dw 0x2953, 0xc436, 0x297f, 0xc436, 0x21, 0 + .dw 0x2981, 0xc436, 0x2981, 0xc436, 0x21, 0 + .dw 0x2983, 0xc436, 0x298f, 0xc436, 0x21, 0 + .dw 0x2991, 0xc436, 0x2991, 0xc436, 0x21, 0 + .dw 0x2993, 0xc436, 0x29bf, 0xc436, 0x21, 0 + .dw 0x29c1, 0xc436, 0x29c1, 0xc436, 0x21, 0 + .dw 0x29c3, 0xc436, 0x29cf, 0xc436, 0x21, 0 + .dw 0x29d1, 0xc436, 0x29d1, 0xc436, 0x21, 0 + .dw 0x29d3, 0xc436, 0x29ff, 0xc436, 0x21, 0 + .dw 0x2a01, 0xc436, 0x2a01, 0xc436, 0x21, 0 + .dw 0x2a03, 0xc436, 0x2a0f, 0xc436, 0x21, 0 + .dw 0x2a11, 0xc436, 0x2a11, 0xc436, 0x21, 0 + .dw 0x2a13, 0xc436, 0x2a3f, 0xc436, 0x21, 0 + .dw 0x2a41, 0xc436, 0x2a41, 0xc436, 0x21, 0 + .dw 0x2a43, 0xc436, 0x2a4f, 0xc436, 0x21, 0 + .dw 0x2a51, 0xc436, 0x2a51, 0xc436, 0x21, 0 + .dw 0x2a53, 0xc436, 0x2a7f, 0xc436, 0x21, 0 + .dw 0x2a81, 0xc436, 0x2a81, 0xc436, 0x21, 0 + .dw 0x2a83, 0xc436, 0x2a8f, 0xc436, 0x21, 0 + .dw 0x2a91, 0xc436, 0x2a91, 0xc436, 0x21, 0 + .dw 0x2a93, 0xc436, 0x2abf, 0xc436, 0x21, 0 + .dw 0x2ac1, 0xc436, 0x2ac1, 0xc436, 0x21, 0 + .dw 0x2ac3, 0xc436, 0x2acf, 0xc436, 0x21, 0 + .dw 0x2ad1, 0xc436, 0x2ad1, 0xc436, 0x21, 0 + .dw 0x2ad3, 0xc436, 0x2aff, 0xc436, 0x21, 0 + .dw 0x2b01, 0xc436, 0x2b01, 0xc436, 0x21, 0 + .dw 0x2b03, 0xc436, 0x2b0f, 0xc436, 0x21, 0 + .dw 0x2b11, 0xc436, 0x2b11, 0xc436, 0x21, 0 + .dw 0x2b13, 0xc436, 0x2b3f, 0xc436, 0x21, 0 + .dw 0x2b41, 0xc436, 0x2b41, 0xc436, 0x21, 0 + .dw 0x2b43, 0xc436, 0x2b4f, 0xc436, 0x21, 0 + .dw 0x2b51, 0xc436, 0x2b51, 0xc436, 0x21, 0 + .dw 0x2b53, 0xc436, 0x2b7f, 0xc436, 0x21, 0 + .dw 0x2b81, 0xc436, 0x2b81, 0xc436, 0x21, 0 + .dw 0x2b83, 0xc436, 0x2b8f, 0xc436, 0x21, 0 + .dw 0x2b91, 0xc436, 0x2b91, 0xc436, 0x21, 0 + .dw 0x2b93, 0xc436, 0x2bbf, 0xc436, 0x21, 0 + .dw 0x2bc1, 0xc436, 0x2bc1, 0xc436, 0x21, 0 + .dw 0x2bc3, 0xc436, 0x2bcf, 0xc436, 0x21, 0 + .dw 0x2bd1, 0xc436, 0x2bd1, 0xc436, 0x21, 0 + .dw 0x2bd3, 0xc436, 0x2bff, 0xc436, 0x21, 0 + .dw 0x2c01, 0xc436, 0x2c01, 0xc436, 0x21, 0 + .dw 0x2c03, 0xc436, 0x2c0f, 0xc436, 0x21, 0 + .dw 0x2c11, 0xc436, 0x2c11, 0xc436, 0x21, 0 + .dw 0x2c13, 0xc436, 0x2c3f, 0xc436, 0x21, 0 + .dw 0x2c41, 0xc436, 0x2c41, 0xc436, 0x21, 0 + .dw 0x2c43, 0xc436, 0x2c4f, 0xc436, 0x21, 0 + .dw 0x2c51, 0xc436, 0x2c51, 0xc436, 0x21, 0 + .dw 0x2c53, 0xc436, 0x2c7f, 0xc436, 0x21, 0 + .dw 0x2c81, 0xc436, 0x2c81, 0xc436, 0x21, 0 + .dw 0x2c83, 0xc436, 0x2c8f, 0xc436, 0x21, 0 + .dw 0x2c91, 0xc436, 0x2c91, 0xc436, 0x21, 0 + .dw 0x2c93, 0xc436, 0x2cbf, 0xc436, 0x21, 0 + .dw 0x2cc1, 0xc436, 0x2cc1, 0xc436, 0x21, 0 + .dw 0x2cc3, 0xc436, 0x2ccf, 0xc436, 0x21, 0 + .dw 0x2cd1, 0xc436, 0x2cd1, 0xc436, 0x21, 0 + .dw 0x2cd3, 0xc436, 0x2cff, 0xc436, 0x21, 0 + .dw 0x2d01, 0xc436, 0x2d01, 0xc436, 0x21, 0 + .dw 0x2d03, 0xc436, 0x2d0f, 0xc436, 0x21, 0 + .dw 0x2d11, 0xc436, 0x2d11, 0xc436, 0x21, 0 + .dw 0x2d13, 0xc436, 0x2d3f, 0xc436, 0x21, 0 + .dw 0x2d41, 0xc436, 0x2d41, 0xc436, 0x21, 0 + .dw 0x2d43, 0xc436, 0x2d4f, 0xc436, 0x21, 0 + .dw 0x2d51, 0xc436, 0x2d51, 0xc436, 0x21, 0 + .dw 0x2d53, 0xc436, 0x2d7f, 0xc436, 0x21, 0 + .dw 0x2d81, 0xc436, 0x2d81, 0xc436, 0x21, 0 + .dw 0x2d83, 0xc436, 0x2d8f, 0xc436, 0x21, 0 + .dw 0x2d91, 0xc436, 0x2d91, 0xc436, 0x21, 0 + .dw 0x2d93, 0xc436, 0x2dbf, 0xc436, 0x21, 0 + .dw 0x2dc1, 0xc436, 0x2dc1, 0xc436, 0x21, 0 + .dw 0x2dc3, 0xc436, 0x2dcf, 0xc436, 0x21, 0 + .dw 0x2dd1, 0xc436, 0x2dd1, 0xc436, 0x21, 0 + .dw 0x2dd3, 0xc436, 0x2dff, 0xc436, 0x21, 0 + .dw 0x2e01, 0xc436, 0x2e01, 0xc436, 0x21, 0 + .dw 0x2e03, 0xc436, 0x2e0f, 0xc436, 0x21, 0 + .dw 0x2e11, 0xc436, 0x2e11, 0xc436, 0x21, 0 + .dw 0x2e13, 0xc436, 0x2e3f, 0xc436, 0x21, 0 + .dw 0x2e41, 0xc436, 0x2e41, 0xc436, 0x21, 0 + .dw 0x2e43, 0xc436, 0x2e4f, 0xc436, 0x21, 0 + .dw 0x2e51, 0xc436, 0x2e51, 0xc436, 0x21, 0 + .dw 0x2e53, 0xc436, 0x2e7f, 0xc436, 0x21, 0 + .dw 0x2e81, 0xc436, 0x2e81, 0xc436, 0x21, 0 + .dw 0x2e83, 0xc436, 0x2e8f, 0xc436, 0x21, 0 + .dw 0x2e91, 0xc436, 0x2e91, 0xc436, 0x21, 0 + .dw 0x2e93, 0xc436, 0x2ebf, 0xc436, 0x21, 0 + .dw 0x2ec1, 0xc436, 0x2ec1, 0xc436, 0x21, 0 + .dw 0x2ec3, 0xc436, 0x2ecf, 0xc436, 0x21, 0 + .dw 0x2ed1, 0xc436, 0x2ed1, 0xc436, 0x21, 0 + .dw 0x2ed3, 0xc436, 0x2eff, 0xc436, 0x21, 0 + .dw 0x2f01, 0xc436, 0x2f01, 0xc436, 0x21, 0 + .dw 0x2f03, 0xc436, 0x2f0f, 0xc436, 0x21, 0 + .dw 0x2f11, 0xc436, 0x2f11, 0xc436, 0x21, 0 + .dw 0x2f13, 0xc436, 0x2f3f, 0xc436, 0x21, 0 + .dw 0x2f41, 0xc436, 0x2f41, 0xc436, 0x21, 0 + .dw 0x2f43, 0xc436, 0x2f4f, 0xc436, 0x21, 0 + .dw 0x2f51, 0xc436, 0x2f51, 0xc436, 0x21, 0 + .dw 0x2f53, 0xc436, 0x2f7f, 0xc436, 0x21, 0 + .dw 0x2f81, 0xc436, 0x2f81, 0xc436, 0x21, 0 + .dw 0x2f83, 0xc436, 0x2f8f, 0xc436, 0x21, 0 + .dw 0x2f91, 0xc436, 0x2f91, 0xc436, 0x21, 0 + .dw 0x2f93, 0xc436, 0x2fbf, 0xc436, 0x21, 0 + .dw 0x2fc1, 0xc436, 0x2fc1, 0xc436, 0x21, 0 + .dw 0x2fc3, 0xc436, 0x2fcf, 0xc436, 0x21, 0 + .dw 0x2fd1, 0xc436, 0x2fd1, 0xc436, 0x21, 0 + .dw 0x2fd3, 0xc436, 0x3fff, 0xc436, 0x21, 0 + .dw 0x4001, 0xc436, 0x4001, 0xc436, 0x21, 0 + .dw 0x4003, 0xc436, 0x400f, 0xc436, 0x21, 0 + .dw 0x4011, 0xc436, 0x4011, 0xc436, 0x21, 0 + .dw 0x4013, 0xc436, 0x403f, 0xc436, 0x21, 0 + .dw 0x4041, 0xc436, 0x4041, 0xc436, 0x21, 0 + .dw 0x4043, 0xc436, 0x404f, 0xc436, 0x21, 0 + .dw 0x4051, 0xc436, 0x4051, 0xc436, 0x21, 0 + .dw 0x4053, 0xc436, 0x407f, 0xc436, 0x21, 0 + .dw 0x4081, 0xc436, 0x4081, 0xc436, 0x21, 0 + .dw 0x4083, 0xc436, 0x408f, 0xc436, 0x21, 0 + .dw 0x4091, 0xc436, 0x4091, 0xc436, 0x21, 0 + .dw 0x4093, 0xc436, 0x40bf, 0xc436, 0x21, 0 + .dw 0x40c1, 0xc436, 0x40c1, 0xc436, 0x21, 0 + .dw 0x40c3, 0xc436, 0x40cf, 0xc436, 0x21, 0 + .dw 0x40d1, 0xc436, 0x40d1, 0xc436, 0x21, 0 + .dw 0x40d3, 0xc436, 0x40ff, 0xc436, 0x21, 0 + .dw 0x4101, 0xc436, 0x4101, 0xc436, 0x21, 0 + .dw 0x4103, 0xc436, 0x410f, 0xc436, 0x21, 0 + .dw 0x4111, 0xc436, 0x4111, 0xc436, 0x21, 0 + .dw 0x4113, 0xc436, 0x413f, 0xc436, 0x21, 0 + .dw 0x4141, 0xc436, 0x4141, 0xc436, 0x21, 0 + .dw 0x4143, 0xc436, 0x414f, 0xc436, 0x21, 0 + .dw 0x4151, 0xc436, 0x4151, 0xc436, 0x21, 0 + .dw 0x4153, 0xc436, 0x417f, 0xc436, 0x21, 0 + .dw 0x4181, 0xc436, 0x4181, 0xc436, 0x21, 0 + .dw 0x4183, 0xc436, 0x418f, 0xc436, 0x21, 0 + .dw 0x4191, 0xc436, 0x4191, 0xc436, 0x21, 0 + .dw 0x4193, 0xc436, 0x41bf, 0xc436, 0x21, 0 + .dw 0x41c1, 0xc436, 0x41c1, 0xc436, 0x21, 0 + .dw 0x41c3, 0xc436, 0x41cf, 0xc436, 0x21, 0 + .dw 0x41d1, 0xc436, 0x41d1, 0xc436, 0x21, 0 + .dw 0x41d3, 0xc436, 0x41ff, 0xc436, 0x21, 0 + .dw 0x4201, 0xc436, 0x4201, 0xc436, 0x21, 0 + .dw 0x4203, 0xc436, 0x420f, 0xc436, 0x21, 0 + .dw 0x4211, 0xc436, 0x4211, 0xc436, 0x21, 0 + .dw 0x4213, 0xc436, 0x423f, 0xc436, 0x21, 0 + .dw 0x4241, 0xc436, 0x4241, 0xc436, 0x21, 0 + .dw 0x4243, 0xc436, 0x424f, 0xc436, 0x21, 0 + .dw 0x4251, 0xc436, 0x4251, 0xc436, 0x21, 0 + .dw 0x4253, 0xc436, 0x427f, 0xc436, 0x21, 0 + .dw 0x4281, 0xc436, 0x4281, 0xc436, 0x21, 0 + .dw 0x4283, 0xc436, 0x428f, 0xc436, 0x21, 0 + .dw 0x4291, 0xc436, 0x4291, 0xc436, 0x21, 0 + .dw 0x4293, 0xc436, 0x42bf, 0xc436, 0x21, 0 + .dw 0x42c1, 0xc436, 0x42c1, 0xc436, 0x21, 0 + .dw 0x42c3, 0xc436, 0x42cf, 0xc436, 0x21, 0 + .dw 0x42d1, 0xc436, 0x42d1, 0xc436, 0x21, 0 + .dw 0x42d3, 0xc436, 0x42ff, 0xc436, 0x21, 0 + .dw 0x4301, 0xc436, 0x4301, 0xc436, 0x21, 0 + .dw 0x4303, 0xc436, 0x430f, 0xc436, 0x21, 0 + .dw 0x4311, 0xc436, 0x4311, 0xc436, 0x21, 0 + .dw 0x4313, 0xc436, 0x433f, 0xc436, 0x21, 0 + .dw 0x4341, 0xc436, 0x4341, 0xc436, 0x21, 0 + .dw 0x4343, 0xc436, 0x434f, 0xc436, 0x21, 0 + .dw 0x4351, 0xc436, 0x4351, 0xc436, 0x21, 0 + .dw 0x4353, 0xc436, 0x437f, 0xc436, 0x21, 0 + .dw 0x4381, 0xc436, 0x4381, 0xc436, 0x21, 0 + .dw 0x4383, 0xc436, 0x438f, 0xc436, 0x21, 0 + .dw 0x4391, 0xc436, 0x4391, 0xc436, 0x21, 0 + .dw 0x4393, 0xc436, 0x43bf, 0xc436, 0x21, 0 + .dw 0x43c1, 0xc436, 0x43c1, 0xc436, 0x21, 0 + .dw 0x43c3, 0xc436, 0x43cf, 0xc436, 0x21, 0 + .dw 0x43d1, 0xc436, 0x43d1, 0xc436, 0x21, 0 + .dw 0x43d3, 0xc436, 0x43ff, 0xc436, 0x21, 0 + .dw 0x4401, 0xc436, 0x4401, 0xc436, 0x21, 0 + .dw 0x4403, 0xc436, 0x440f, 0xc436, 0x21, 0 + .dw 0x4411, 0xc436, 0x4411, 0xc436, 0x21, 0 + .dw 0x4413, 0xc436, 0x443f, 0xc436, 0x21, 0 + .dw 0x4441, 0xc436, 0x4441, 0xc436, 0x21, 0 + .dw 0x4443, 0xc436, 0x444f, 0xc436, 0x21, 0 + .dw 0x4451, 0xc436, 0x4451, 0xc436, 0x21, 0 + .dw 0x4453, 0xc436, 0x447f, 0xc436, 0x21, 0 + .dw 0x4481, 0xc436, 0x4481, 0xc436, 0x21, 0 + .dw 0x4483, 0xc436, 0x448f, 0xc436, 0x21, 0 + .dw 0x4491, 0xc436, 0x4491, 0xc436, 0x21, 0 + .dw 0x4493, 0xc436, 0x44bf, 0xc436, 0x21, 0 + .dw 0x44c1, 0xc436, 0x44c1, 0xc436, 0x21, 0 + .dw 0x44c3, 0xc436, 0x44cf, 0xc436, 0x21, 0 + .dw 0x44d1, 0xc436, 0x44d1, 0xc436, 0x21, 0 + .dw 0x44d3, 0xc436, 0x44ff, 0xc436, 0x21, 0 + .dw 0x4501, 0xc436, 0x4501, 0xc436, 0x21, 0 + .dw 0x4503, 0xc436, 0x450f, 0xc436, 0x21, 0 + .dw 0x4511, 0xc436, 0x4511, 0xc436, 0x21, 0 + .dw 0x4513, 0xc436, 0x453f, 0xc436, 0x21, 0 + .dw 0x4541, 0xc436, 0x4541, 0xc436, 0x21, 0 + .dw 0x4543, 0xc436, 0x454f, 0xc436, 0x21, 0 + .dw 0x4551, 0xc436, 0x4551, 0xc436, 0x21, 0 + .dw 0x4553, 0xc436, 0x457f, 0xc436, 0x21, 0 + .dw 0x4581, 0xc436, 0x4581, 0xc436, 0x21, 0 + .dw 0x4583, 0xc436, 0x458f, 0xc436, 0x21, 0 + .dw 0x4591, 0xc436, 0x4591, 0xc436, 0x21, 0 + .dw 0x4593, 0xc436, 0x45bf, 0xc436, 0x21, 0 + .dw 0x45c1, 0xc436, 0x45c1, 0xc436, 0x21, 0 + .dw 0x45c3, 0xc436, 0x45cf, 0xc436, 0x21, 0 + .dw 0x45d1, 0xc436, 0x45d1, 0xc436, 0x21, 0 + .dw 0x45d3, 0xc436, 0x45ff, 0xc436, 0x21, 0 + .dw 0x4601, 0xc436, 0x4601, 0xc436, 0x21, 0 + .dw 0x4603, 0xc436, 0x460f, 0xc436, 0x21, 0 + .dw 0x4611, 0xc436, 0x4611, 0xc436, 0x21, 0 + .dw 0x4613, 0xc436, 0x463f, 0xc436, 0x21, 0 + .dw 0x4641, 0xc436, 0x4641, 0xc436, 0x21, 0 + .dw 0x4643, 0xc436, 0x464f, 0xc436, 0x21, 0 + .dw 0x4651, 0xc436, 0x4651, 0xc436, 0x21, 0 + .dw 0x4653, 0xc436, 0x467f, 0xc436, 0x21, 0 + .dw 0x4681, 0xc436, 0x4681, 0xc436, 0x21, 0 + .dw 0x4683, 0xc436, 0x468f, 0xc436, 0x21, 0 + .dw 0x4691, 0xc436, 0x4691, 0xc436, 0x21, 0 + .dw 0x4693, 0xc436, 0x46bf, 0xc436, 0x21, 0 + .dw 0x46c1, 0xc436, 0x46c1, 0xc436, 0x21, 0 + .dw 0x46c3, 0xc436, 0x46cf, 0xc436, 0x21, 0 + .dw 0x46d1, 0xc436, 0x46d1, 0xc436, 0x21, 0 + .dw 0x46d3, 0xc436, 0x46ff, 0xc436, 0x21, 0 + .dw 0x4701, 0xc436, 0x4701, 0xc436, 0x21, 0 + .dw 0x4703, 0xc436, 0x470f, 0xc436, 0x21, 0 + .dw 0x4711, 0xc436, 0x4711, 0xc436, 0x21, 0 + .dw 0x4713, 0xc436, 0x473f, 0xc436, 0x21, 0 + .dw 0x4741, 0xc436, 0x4741, 0xc436, 0x21, 0 + .dw 0x4743, 0xc436, 0x474f, 0xc436, 0x21, 0 + .dw 0x4751, 0xc436, 0x4751, 0xc436, 0x21, 0 + .dw 0x4753, 0xc436, 0x477f, 0xc436, 0x21, 0 + .dw 0x4781, 0xc436, 0x4781, 0xc436, 0x21, 0 + .dw 0x4783, 0xc436, 0x478f, 0xc436, 0x21, 0 + .dw 0x4791, 0xc436, 0x4791, 0xc436, 0x21, 0 + .dw 0x4793, 0xc436, 0x47bf, 0xc436, 0x21, 0 + .dw 0x47c1, 0xc436, 0x47c1, 0xc436, 0x21, 0 + .dw 0x47c3, 0xc436, 0x47cf, 0xc436, 0x21, 0 + .dw 0x47d1, 0xc436, 0x47d1, 0xc436, 0x21, 0 + .dw 0x47d3, 0xc436, 0x47ff, 0xc436, 0x21, 0 + .dw 0x4801, 0xc436, 0x4801, 0xc436, 0x21, 0 + .dw 0x4803, 0xc436, 0x480f, 0xc436, 0x21, 0 + .dw 0x4811, 0xc436, 0x4811, 0xc436, 0x21, 0 + .dw 0x4813, 0xc436, 0x483f, 0xc436, 0x21, 0 + .dw 0x4841, 0xc436, 0x4841, 0xc436, 0x21, 0 + .dw 0x4843, 0xc436, 0x484f, 0xc436, 0x21, 0 + .dw 0x4851, 0xc436, 0x4851, 0xc436, 0x21, 0 + .dw 0x4853, 0xc436, 0x487f, 0xc436, 0x21, 0 + .dw 0x4881, 0xc436, 0x4881, 0xc436, 0x21, 0 + .dw 0x4883, 0xc436, 0x488f, 0xc436, 0x21, 0 + .dw 0x4891, 0xc436, 0x4891, 0xc436, 0x21, 0 + .dw 0x4893, 0xc436, 0x48bf, 0xc436, 0x21, 0 + .dw 0x48c1, 0xc436, 0x48c1, 0xc436, 0x21, 0 + .dw 0x48c3, 0xc436, 0x48cf, 0xc436, 0x21, 0 + .dw 0x48d1, 0xc436, 0x48d1, 0xc436, 0x21, 0 + .dw 0x48d3, 0xc436, 0x48ff, 0xc436, 0x21, 0 + .dw 0x4901, 0xc436, 0x4901, 0xc436, 0x21, 0 + .dw 0x4903, 0xc436, 0x490f, 0xc436, 0x21, 0 + .dw 0x4911, 0xc436, 0x4911, 0xc436, 0x21, 0 + .dw 0x4913, 0xc436, 0x493f, 0xc436, 0x21, 0 + .dw 0x4941, 0xc436, 0x4941, 0xc436, 0x21, 0 + .dw 0x4943, 0xc436, 0x494f, 0xc436, 0x21, 0 + .dw 0x4951, 0xc436, 0x4951, 0xc436, 0x21, 0 + .dw 0x4953, 0xc436, 0x497f, 0xc436, 0x21, 0 + .dw 0x4981, 0xc436, 0x4981, 0xc436, 0x21, 0 + .dw 0x4983, 0xc436, 0x498f, 0xc436, 0x21, 0 + .dw 0x4991, 0xc436, 0x4991, 0xc436, 0x21, 0 + .dw 0x4993, 0xc436, 0x49bf, 0xc436, 0x21, 0 + .dw 0x49c1, 0xc436, 0x49c1, 0xc436, 0x21, 0 + .dw 0x49c3, 0xc436, 0x49cf, 0xc436, 0x21, 0 + .dw 0x49d1, 0xc436, 0x49d1, 0xc436, 0x21, 0 + .dw 0x49d3, 0xc436, 0x49ff, 0xc436, 0x21, 0 + .dw 0x4a01, 0xc436, 0x4a01, 0xc436, 0x21, 0 + .dw 0x4a03, 0xc436, 0x4a0f, 0xc436, 0x21, 0 + .dw 0x4a11, 0xc436, 0x4a11, 0xc436, 0x21, 0 + .dw 0x4a13, 0xc436, 0x4a3f, 0xc436, 0x21, 0 + .dw 0x4a41, 0xc436, 0x4a41, 0xc436, 0x21, 0 + .dw 0x4a43, 0xc436, 0x4a4f, 0xc436, 0x21, 0 + .dw 0x4a51, 0xc436, 0x4a51, 0xc436, 0x21, 0 + .dw 0x4a53, 0xc436, 0x4a7f, 0xc436, 0x21, 0 + .dw 0x4a81, 0xc436, 0x4a81, 0xc436, 0x21, 0 + .dw 0x4a83, 0xc436, 0x4a8f, 0xc436, 0x21, 0 + .dw 0x4a91, 0xc436, 0x4a91, 0xc436, 0x21, 0 + .dw 0x4a93, 0xc436, 0x4abf, 0xc436, 0x21, 0 + .dw 0x4ac1, 0xc436, 0x4ac1, 0xc436, 0x21, 0 + .dw 0x4ac3, 0xc436, 0x4acf, 0xc436, 0x21, 0 + .dw 0x4ad1, 0xc436, 0x4ad1, 0xc436, 0x21, 0 + .dw 0x4ad3, 0xc436, 0x4aff, 0xc436, 0x21, 0 + .dw 0x4b01, 0xc436, 0x4b01, 0xc436, 0x21, 0 + .dw 0x4b03, 0xc436, 0x4b0f, 0xc436, 0x21, 0 + .dw 0x4b11, 0xc436, 0x4b11, 0xc436, 0x21, 0 + .dw 0x4b13, 0xc436, 0x4b3f, 0xc436, 0x21, 0 + .dw 0x4b41, 0xc436, 0x4b41, 0xc436, 0x21, 0 + .dw 0x4b43, 0xc436, 0x4b4f, 0xc436, 0x21, 0 + .dw 0x4b51, 0xc436, 0x4b51, 0xc436, 0x21, 0 + .dw 0x4b53, 0xc436, 0x4b7f, 0xc436, 0x21, 0 + .dw 0x4b81, 0xc436, 0x4b81, 0xc436, 0x21, 0 + .dw 0x4b83, 0xc436, 0x4b8f, 0xc436, 0x21, 0 + .dw 0x4b91, 0xc436, 0x4b91, 0xc436, 0x21, 0 + .dw 0x4b93, 0xc436, 0x4bbf, 0xc436, 0x21, 0 + .dw 0x4bc1, 0xc436, 0x4bc1, 0xc436, 0x21, 0 + .dw 0x4bc3, 0xc436, 0x4bcf, 0xc436, 0x21, 0 + .dw 0x4bd1, 0xc436, 0x4bd1, 0xc436, 0x21, 0 + .dw 0x4bd3, 0xc436, 0x4bff, 0xc436, 0x21, 0 + .dw 0x4c01, 0xc436, 0x4c01, 0xc436, 0x21, 0 + .dw 0x4c03, 0xc436, 0x4c0f, 0xc436, 0x21, 0 + .dw 0x4c11, 0xc436, 0x4c11, 0xc436, 0x21, 0 + .dw 0x4c13, 0xc436, 0x4c3f, 0xc436, 0x21, 0 + .dw 0x4c41, 0xc436, 0x4c41, 0xc436, 0x21, 0 + .dw 0x4c43, 0xc436, 0x4c4f, 0xc436, 0x21, 0 + .dw 0x4c51, 0xc436, 0x4c51, 0xc436, 0x21, 0 + .dw 0x4c53, 0xc436, 0x4c7f, 0xc436, 0x21, 0 + .dw 0x4c81, 0xc436, 0x4c81, 0xc436, 0x21, 0 + .dw 0x4c83, 0xc436, 0x4c8f, 0xc436, 0x21, 0 + .dw 0x4c91, 0xc436, 0x4c91, 0xc436, 0x21, 0 + .dw 0x4c93, 0xc436, 0x4cbf, 0xc436, 0x21, 0 + .dw 0x4cc1, 0xc436, 0x4cc1, 0xc436, 0x21, 0 + .dw 0x4cc3, 0xc436, 0x4ccf, 0xc436, 0x21, 0 + .dw 0x4cd1, 0xc436, 0x4cd1, 0xc436, 0x21, 0 + .dw 0x4cd3, 0xc436, 0x4cff, 0xc436, 0x21, 0 + .dw 0x4d01, 0xc436, 0x4d01, 0xc436, 0x21, 0 + .dw 0x4d03, 0xc436, 0x4d0f, 0xc436, 0x21, 0 + .dw 0x4d11, 0xc436, 0x4d11, 0xc436, 0x21, 0 + .dw 0x4d13, 0xc436, 0x4d3f, 0xc436, 0x21, 0 + .dw 0x4d41, 0xc436, 0x4d41, 0xc436, 0x21, 0 + .dw 0x4d43, 0xc436, 0x4d4f, 0xc436, 0x21, 0 + .dw 0x4d51, 0xc436, 0x4d51, 0xc436, 0x21, 0 + .dw 0x4d53, 0xc436, 0x4d7f, 0xc436, 0x21, 0 + .dw 0x4d81, 0xc436, 0x4d81, 0xc436, 0x21, 0 + .dw 0x4d83, 0xc436, 0x4d8f, 0xc436, 0x21, 0 + .dw 0x4d91, 0xc436, 0x4d91, 0xc436, 0x21, 0 + .dw 0x4d93, 0xc436, 0x4dbf, 0xc436, 0x21, 0 + .dw 0x4dc1, 0xc436, 0x4dc1, 0xc436, 0x21, 0 + .dw 0x4dc3, 0xc436, 0x4dcf, 0xc436, 0x21, 0 + .dw 0x4dd1, 0xc436, 0x4dd1, 0xc436, 0x21, 0 + .dw 0x4dd3, 0xc436, 0x4dff, 0xc436, 0x21, 0 + .dw 0x4e01, 0xc436, 0x4e01, 0xc436, 0x21, 0 + .dw 0x4e03, 0xc436, 0x4e0f, 0xc436, 0x21, 0 + .dw 0x4e11, 0xc436, 0x4e11, 0xc436, 0x21, 0 + .dw 0x4e13, 0xc436, 0x4e3f, 0xc436, 0x21, 0 + .dw 0x4e41, 0xc436, 0x4e41, 0xc436, 0x21, 0 + .dw 0x4e43, 0xc436, 0x4e4f, 0xc436, 0x21, 0 + .dw 0x4e51, 0xc436, 0x4e51, 0xc436, 0x21, 0 + .dw 0x4e53, 0xc436, 0x4e7f, 0xc436, 0x21, 0 + .dw 0x4e81, 0xc436, 0x4e81, 0xc436, 0x21, 0 + .dw 0x4e83, 0xc436, 0x4e8f, 0xc436, 0x21, 0 + .dw 0x4e91, 0xc436, 0x4e91, 0xc436, 0x21, 0 + .dw 0x4e93, 0xc436, 0x4ebf, 0xc436, 0x21, 0 + .dw 0x4ec1, 0xc436, 0x4ec1, 0xc436, 0x21, 0 + .dw 0x4ec3, 0xc436, 0x4ecf, 0xc436, 0x21, 0 + .dw 0x4ed1, 0xc436, 0x4ed1, 0xc436, 0x21, 0 + .dw 0x4ed3, 0xc436, 0x4eff, 0xc436, 0x21, 0 + .dw 0x4f01, 0xc436, 0x4f01, 0xc436, 0x21, 0 + .dw 0x4f03, 0xc436, 0x4f0f, 0xc436, 0x21, 0 + .dw 0x4f11, 0xc436, 0x4f11, 0xc436, 0x21, 0 + .dw 0x4f13, 0xc436, 0x4f3f, 0xc436, 0x21, 0 + .dw 0x4f41, 0xc436, 0x4f41, 0xc436, 0x21, 0 + .dw 0x4f43, 0xc436, 0x4f4f, 0xc436, 0x21, 0 + .dw 0x4f51, 0xc436, 0x4f51, 0xc436, 0x21, 0 + .dw 0x4f53, 0xc436, 0x4f7f, 0xc436, 0x21, 0 + .dw 0x4f81, 0xc436, 0x4f81, 0xc436, 0x21, 0 + .dw 0x4f83, 0xc436, 0x4f8f, 0xc436, 0x21, 0 + .dw 0x4f91, 0xc436, 0x4f91, 0xc436, 0x21, 0 + .dw 0x4f93, 0xc436, 0x4fbf, 0xc436, 0x21, 0 + .dw 0x4fc1, 0xc436, 0x4fc1, 0xc436, 0x21, 0 + .dw 0x4fc3, 0xc436, 0x4fcf, 0xc436, 0x21, 0 + .dw 0x4fd1, 0xc436, 0x4fd1, 0xc436, 0x21, 0 + .dw 0x4fd3, 0xc436, 0x5fff, 0xc436, 0x21, 0 + .dw 0x6001, 0xc436, 0x6001, 0xc436, 0x21, 0 + .dw 0x6003, 0xc436, 0x600f, 0xc436, 0x21, 0 + .dw 0x6011, 0xc436, 0x6011, 0xc436, 0x21, 0 + .dw 0x6013, 0xc436, 0x603f, 0xc436, 0x21, 0 + .dw 0x6041, 0xc436, 0x6041, 0xc436, 0x21, 0 + .dw 0x6043, 0xc436, 0x604f, 0xc436, 0x21, 0 + .dw 0x6051, 0xc436, 0x6051, 0xc436, 0x21, 0 + .dw 0x6053, 0xc436, 0x607f, 0xc436, 0x21, 0 + .dw 0x6081, 0xc436, 0x6081, 0xc436, 0x21, 0 + .dw 0x6083, 0xc436, 0x608f, 0xc436, 0x21, 0 + .dw 0x6091, 0xc436, 0x6091, 0xc436, 0x21, 0 + .dw 0x6093, 0xc436, 0x60bf, 0xc436, 0x21, 0 + .dw 0x60c1, 0xc436, 0x60c1, 0xc436, 0x21, 0 + .dw 0x60c3, 0xc436, 0x60cf, 0xc436, 0x21, 0 + .dw 0x60d1, 0xc436, 0x60d1, 0xc436, 0x21, 0 + .dw 0x60d3, 0xc436, 0x60ff, 0xc436, 0x21, 0 + .dw 0x6101, 0xc436, 0x6101, 0xc436, 0x21, 0 + .dw 0x6103, 0xc436, 0x610f, 0xc436, 0x21, 0 + .dw 0x6111, 0xc436, 0x6111, 0xc436, 0x21, 0 + .dw 0x6113, 0xc436, 0x613f, 0xc436, 0x21, 0 + .dw 0x6141, 0xc436, 0x6141, 0xc436, 0x21, 0 + .dw 0x6143, 0xc436, 0x614f, 0xc436, 0x21, 0 + .dw 0x6151, 0xc436, 0x6151, 0xc436, 0x21, 0 + .dw 0x6153, 0xc436, 0x617f, 0xc436, 0x21, 0 + .dw 0x6181, 0xc436, 0x6181, 0xc436, 0x21, 0 + .dw 0x6183, 0xc436, 0x618f, 0xc436, 0x21, 0 + .dw 0x6191, 0xc436, 0x6191, 0xc436, 0x21, 0 + .dw 0x6193, 0xc436, 0x61bf, 0xc436, 0x21, 0 + .dw 0x61c1, 0xc436, 0x61c1, 0xc436, 0x21, 0 + .dw 0x61c3, 0xc436, 0x61cf, 0xc436, 0x21, 0 + .dw 0x61d1, 0xc436, 0x61d1, 0xc436, 0x21, 0 + .dw 0x61d3, 0xc436, 0x61ff, 0xc436, 0x21, 0 + .dw 0x6201, 0xc436, 0x6201, 0xc436, 0x21, 0 + .dw 0x6203, 0xc436, 0x620f, 0xc436, 0x21, 0 + .dw 0x6211, 0xc436, 0x6211, 0xc436, 0x21, 0 + .dw 0x6213, 0xc436, 0x623f, 0xc436, 0x21, 0 + .dw 0x6241, 0xc436, 0x6241, 0xc436, 0x21, 0 + .dw 0x6243, 0xc436, 0x624f, 0xc436, 0x21, 0 + .dw 0x6251, 0xc436, 0x6251, 0xc436, 0x21, 0 + .dw 0x6253, 0xc436, 0x627f, 0xc436, 0x21, 0 + .dw 0x6281, 0xc436, 0x6281, 0xc436, 0x21, 0 + .dw 0x6283, 0xc436, 0x628f, 0xc436, 0x21, 0 + .dw 0x6291, 0xc436, 0x6291, 0xc436, 0x21, 0 + .dw 0x6293, 0xc436, 0x62bf, 0xc436, 0x21, 0 + .dw 0x62c1, 0xc436, 0x62c1, 0xc436, 0x21, 0 + .dw 0x62c3, 0xc436, 0x62cf, 0xc436, 0x21, 0 + .dw 0x62d1, 0xc436, 0x62d1, 0xc436, 0x21, 0 + .dw 0x62d3, 0xc436, 0x62ff, 0xc436, 0x21, 0 + .dw 0x6301, 0xc436, 0x6301, 0xc436, 0x21, 0 + .dw 0x6303, 0xc436, 0x630f, 0xc436, 0x21, 0 + .dw 0x6311, 0xc436, 0x6311, 0xc436, 0x21, 0 + .dw 0x6313, 0xc436, 0x633f, 0xc436, 0x21, 0 + .dw 0x6341, 0xc436, 0x6341, 0xc436, 0x21, 0 + .dw 0x6343, 0xc436, 0x634f, 0xc436, 0x21, 0 + .dw 0x6351, 0xc436, 0x6351, 0xc436, 0x21, 0 + .dw 0x6353, 0xc436, 0x637f, 0xc436, 0x21, 0 + .dw 0x6381, 0xc436, 0x6381, 0xc436, 0x21, 0 + .dw 0x6383, 0xc436, 0x638f, 0xc436, 0x21, 0 + .dw 0x6391, 0xc436, 0x6391, 0xc436, 0x21, 0 + .dw 0x6393, 0xc436, 0x63bf, 0xc436, 0x21, 0 + .dw 0x63c1, 0xc436, 0x63c1, 0xc436, 0x21, 0 + .dw 0x63c3, 0xc436, 0x63cf, 0xc436, 0x21, 0 + .dw 0x63d1, 0xc436, 0x63d1, 0xc436, 0x21, 0 + .dw 0x63d3, 0xc436, 0x63ff, 0xc436, 0x21, 0 + .dw 0x6401, 0xc436, 0x6401, 0xc436, 0x21, 0 + .dw 0x6403, 0xc436, 0x640f, 0xc436, 0x21, 0 + .dw 0x6411, 0xc436, 0x6411, 0xc436, 0x21, 0 + .dw 0x6413, 0xc436, 0x643f, 0xc436, 0x21, 0 + .dw 0x6441, 0xc436, 0x6441, 0xc436, 0x21, 0 + .dw 0x6443, 0xc436, 0x644f, 0xc436, 0x21, 0 + .dw 0x6451, 0xc436, 0x6451, 0xc436, 0x21, 0 + .dw 0x6453, 0xc436, 0x647f, 0xc436, 0x21, 0 + .dw 0x6481, 0xc436, 0x6481, 0xc436, 0x21, 0 + .dw 0x6483, 0xc436, 0x648f, 0xc436, 0x21, 0 + .dw 0x6491, 0xc436, 0x6491, 0xc436, 0x21, 0 + .dw 0x6493, 0xc436, 0x64bf, 0xc436, 0x21, 0 + .dw 0x64c1, 0xc436, 0x64c1, 0xc436, 0x21, 0 + .dw 0x64c3, 0xc436, 0x64cf, 0xc436, 0x21, 0 + .dw 0x64d1, 0xc436, 0x64d1, 0xc436, 0x21, 0 + .dw 0x64d3, 0xc436, 0x64ff, 0xc436, 0x21, 0 + .dw 0x6501, 0xc436, 0x6501, 0xc436, 0x21, 0 + .dw 0x6503, 0xc436, 0x650f, 0xc436, 0x21, 0 + .dw 0x6511, 0xc436, 0x6511, 0xc436, 0x21, 0 + .dw 0x6513, 0xc436, 0x653f, 0xc436, 0x21, 0 + .dw 0x6541, 0xc436, 0x6541, 0xc436, 0x21, 0 + .dw 0x6543, 0xc436, 0x654f, 0xc436, 0x21, 0 + .dw 0x6551, 0xc436, 0x6551, 0xc436, 0x21, 0 + .dw 0x6553, 0xc436, 0x657f, 0xc436, 0x21, 0 + .dw 0x6581, 0xc436, 0x6581, 0xc436, 0x21, 0 + .dw 0x6583, 0xc436, 0x658f, 0xc436, 0x21, 0 + .dw 0x6591, 0xc436, 0x6591, 0xc436, 0x21, 0 + .dw 0x6593, 0xc436, 0x65bf, 0xc436, 0x21, 0 + .dw 0x65c1, 0xc436, 0x65c1, 0xc436, 0x21, 0 + .dw 0x65c3, 0xc436, 0x65cf, 0xc436, 0x21, 0 + .dw 0x65d1, 0xc436, 0x65d1, 0xc436, 0x21, 0 + .dw 0x65d3, 0xc436, 0x65ff, 0xc436, 0x21, 0 + .dw 0x6601, 0xc436, 0x6601, 0xc436, 0x21, 0 + .dw 0x6603, 0xc436, 0x660f, 0xc436, 0x21, 0 + .dw 0x6611, 0xc436, 0x6611, 0xc436, 0x21, 0 + .dw 0x6613, 0xc436, 0x663f, 0xc436, 0x21, 0 + .dw 0x6641, 0xc436, 0x6641, 0xc436, 0x21, 0 + .dw 0x6643, 0xc436, 0x664f, 0xc436, 0x21, 0 + .dw 0x6651, 0xc436, 0x6651, 0xc436, 0x21, 0 + .dw 0x6653, 0xc436, 0x667f, 0xc436, 0x21, 0 + .dw 0x6681, 0xc436, 0x6681, 0xc436, 0x21, 0 + .dw 0x6683, 0xc436, 0x668f, 0xc436, 0x21, 0 + .dw 0x6691, 0xc436, 0x6691, 0xc436, 0x21, 0 + .dw 0x6693, 0xc436, 0x66bf, 0xc436, 0x21, 0 + .dw 0x66c1, 0xc436, 0x66c1, 0xc436, 0x21, 0 + .dw 0x66c3, 0xc436, 0x66cf, 0xc436, 0x21, 0 + .dw 0x66d1, 0xc436, 0x66d1, 0xc436, 0x21, 0 + .dw 0x66d3, 0xc436, 0x66ff, 0xc436, 0x21, 0 + .dw 0x6701, 0xc436, 0x6701, 0xc436, 0x21, 0 + .dw 0x6703, 0xc436, 0x670f, 0xc436, 0x21, 0 + .dw 0x6711, 0xc436, 0x6711, 0xc436, 0x21, 0 + .dw 0x6713, 0xc436, 0x673f, 0xc436, 0x21, 0 + .dw 0x6741, 0xc436, 0x6741, 0xc436, 0x21, 0 + .dw 0x6743, 0xc436, 0x674f, 0xc436, 0x21, 0 + .dw 0x6751, 0xc436, 0x6751, 0xc436, 0x21, 0 + .dw 0x6753, 0xc436, 0x677f, 0xc436, 0x21, 0 + .dw 0x6781, 0xc436, 0x6781, 0xc436, 0x21, 0 + .dw 0x6783, 0xc436, 0x678f, 0xc436, 0x21, 0 + .dw 0x6791, 0xc436, 0x6791, 0xc436, 0x21, 0 + .dw 0x6793, 0xc436, 0x67bf, 0xc436, 0x21, 0 + .dw 0x67c1, 0xc436, 0x67c1, 0xc436, 0x21, 0 + .dw 0x67c3, 0xc436, 0x67cf, 0xc436, 0x21, 0 + .dw 0x67d1, 0xc436, 0x67d1, 0xc436, 0x21, 0 + .dw 0x67d3, 0xc436, 0x67ff, 0xc436, 0x21, 0 + .dw 0x6801, 0xc436, 0x6801, 0xc436, 0x21, 0 + .dw 0x6803, 0xc436, 0x680f, 0xc436, 0x21, 0 + .dw 0x6811, 0xc436, 0x6811, 0xc436, 0x21, 0 + .dw 0x6813, 0xc436, 0x683f, 0xc436, 0x21, 0 + .dw 0x6841, 0xc436, 0x6841, 0xc436, 0x21, 0 + .dw 0x6843, 0xc436, 0x684f, 0xc436, 0x21, 0 + .dw 0x6851, 0xc436, 0x6851, 0xc436, 0x21, 0 + .dw 0x6853, 0xc436, 0x687f, 0xc436, 0x21, 0 + .dw 0x6881, 0xc436, 0x6881, 0xc436, 0x21, 0 + .dw 0x6883, 0xc436, 0x688f, 0xc436, 0x21, 0 + .dw 0x6891, 0xc436, 0x6891, 0xc436, 0x21, 0 + .dw 0x6893, 0xc436, 0x68bf, 0xc436, 0x21, 0 + .dw 0x68c1, 0xc436, 0x68c1, 0xc436, 0x21, 0 + .dw 0x68c3, 0xc436, 0x68cf, 0xc436, 0x21, 0 + .dw 0x68d1, 0xc436, 0x68d1, 0xc436, 0x21, 0 + .dw 0x68d3, 0xc436, 0x68ff, 0xc436, 0x21, 0 + .dw 0x6901, 0xc436, 0x6901, 0xc436, 0x21, 0 + .dw 0x6903, 0xc436, 0x690f, 0xc436, 0x21, 0 + .dw 0x6911, 0xc436, 0x6911, 0xc436, 0x21, 0 + .dw 0x6913, 0xc436, 0x693f, 0xc436, 0x21, 0 + .dw 0x6941, 0xc436, 0x6941, 0xc436, 0x21, 0 + .dw 0x6943, 0xc436, 0x694f, 0xc436, 0x21, 0 + .dw 0x6951, 0xc436, 0x6951, 0xc436, 0x21, 0 + .dw 0x6953, 0xc436, 0x697f, 0xc436, 0x21, 0 + .dw 0x6981, 0xc436, 0x6981, 0xc436, 0x21, 0 + .dw 0x6983, 0xc436, 0x698f, 0xc436, 0x21, 0 + .dw 0x6991, 0xc436, 0x6991, 0xc436, 0x21, 0 + .dw 0x6993, 0xc436, 0x69bf, 0xc436, 0x21, 0 + .dw 0x69c1, 0xc436, 0x69c1, 0xc436, 0x21, 0 + .dw 0x69c3, 0xc436, 0x69cf, 0xc436, 0x21, 0 + .dw 0x69d1, 0xc436, 0x69d1, 0xc436, 0x21, 0 + .dw 0x69d3, 0xc436, 0x69ff, 0xc436, 0x21, 0 + .dw 0x6a01, 0xc436, 0x6a01, 0xc436, 0x21, 0 + .dw 0x6a03, 0xc436, 0x6a0f, 0xc436, 0x21, 0 + .dw 0x6a11, 0xc436, 0x6a11, 0xc436, 0x21, 0 + .dw 0x6a13, 0xc436, 0x6a3f, 0xc436, 0x21, 0 + .dw 0x6a41, 0xc436, 0x6a41, 0xc436, 0x21, 0 + .dw 0x6a43, 0xc436, 0x6a4f, 0xc436, 0x21, 0 + .dw 0x6a51, 0xc436, 0x6a51, 0xc436, 0x21, 0 + .dw 0x6a53, 0xc436, 0x6a7f, 0xc436, 0x21, 0 + .dw 0x6a81, 0xc436, 0x6a81, 0xc436, 0x21, 0 + .dw 0x6a83, 0xc436, 0x6a8f, 0xc436, 0x21, 0 + .dw 0x6a91, 0xc436, 0x6a91, 0xc436, 0x21, 0 + .dw 0x6a93, 0xc436, 0x6abf, 0xc436, 0x21, 0 + .dw 0x6ac1, 0xc436, 0x6ac1, 0xc436, 0x21, 0 + .dw 0x6ac3, 0xc436, 0x6acf, 0xc436, 0x21, 0 + .dw 0x6ad1, 0xc436, 0x6ad1, 0xc436, 0x21, 0 + .dw 0x6ad3, 0xc436, 0x6aff, 0xc436, 0x21, 0 + .dw 0x6b01, 0xc436, 0x6b01, 0xc436, 0x21, 0 + .dw 0x6b03, 0xc436, 0x6b0f, 0xc436, 0x21, 0 + .dw 0x6b11, 0xc436, 0x6b11, 0xc436, 0x21, 0 + .dw 0x6b13, 0xc436, 0x6b3f, 0xc436, 0x21, 0 + .dw 0x6b41, 0xc436, 0x6b41, 0xc436, 0x21, 0 + .dw 0x6b43, 0xc436, 0x6b4f, 0xc436, 0x21, 0 + .dw 0x6b51, 0xc436, 0x6b51, 0xc436, 0x21, 0 + .dw 0x6b53, 0xc436, 0x6b7f, 0xc436, 0x21, 0 + .dw 0x6b81, 0xc436, 0x6b81, 0xc436, 0x21, 0 + .dw 0x6b83, 0xc436, 0x6b8f, 0xc436, 0x21, 0 + .dw 0x6b91, 0xc436, 0x6b91, 0xc436, 0x21, 0 + .dw 0x6b93, 0xc436, 0x6bbf, 0xc436, 0x21, 0 + .dw 0x6bc1, 0xc436, 0x6bc1, 0xc436, 0x21, 0 + .dw 0x6bc3, 0xc436, 0x6bcf, 0xc436, 0x21, 0 + .dw 0x6bd1, 0xc436, 0x6bd1, 0xc436, 0x21, 0 + .dw 0x6bd3, 0xc436, 0x6bff, 0xc436, 0x21, 0 + .dw 0x6c01, 0xc436, 0x6c01, 0xc436, 0x21, 0 + .dw 0x6c03, 0xc436, 0x6c0f, 0xc436, 0x21, 0 + .dw 0x6c11, 0xc436, 0x6c11, 0xc436, 0x21, 0 + .dw 0x6c13, 0xc436, 0x6c3f, 0xc436, 0x21, 0 + .dw 0x6c41, 0xc436, 0x6c41, 0xc436, 0x21, 0 + .dw 0x6c43, 0xc436, 0x6c4f, 0xc436, 0x21, 0 + .dw 0x6c51, 0xc436, 0x6c51, 0xc436, 0x21, 0 + .dw 0x6c53, 0xc436, 0x6c7f, 0xc436, 0x21, 0 + .dw 0x6c81, 0xc436, 0x6c81, 0xc436, 0x21, 0 + .dw 0x6c83, 0xc436, 0x6c8f, 0xc436, 0x21, 0 + .dw 0x6c91, 0xc436, 0x6c91, 0xc436, 0x21, 0 + .dw 0x6c93, 0xc436, 0x6cbf, 0xc436, 0x21, 0 + .dw 0x6cc1, 0xc436, 0x6cc1, 0xc436, 0x21, 0 + .dw 0x6cc3, 0xc436, 0x6ccf, 0xc436, 0x21, 0 + .dw 0x6cd1, 0xc436, 0x6cd1, 0xc436, 0x21, 0 + .dw 0x6cd3, 0xc436, 0x6cff, 0xc436, 0x21, 0 + .dw 0x6d01, 0xc436, 0x6d01, 0xc436, 0x21, 0 + .dw 0x6d03, 0xc436, 0x6d0f, 0xc436, 0x21, 0 + .dw 0x6d11, 0xc436, 0x6d11, 0xc436, 0x21, 0 + .dw 0x6d13, 0xc436, 0x6d3f, 0xc436, 0x21, 0 + .dw 0x6d41, 0xc436, 0x6d41, 0xc436, 0x21, 0 + .dw 0x6d43, 0xc436, 0x6d4f, 0xc436, 0x21, 0 + .dw 0x6d51, 0xc436, 0x6d51, 0xc436, 0x21, 0 + .dw 0x6d53, 0xc436, 0x6d7f, 0xc436, 0x21, 0 + .dw 0x6d81, 0xc436, 0x6d81, 0xc436, 0x21, 0 + .dw 0x6d83, 0xc436, 0x6d8f, 0xc436, 0x21, 0 + .dw 0x6d91, 0xc436, 0x6d91, 0xc436, 0x21, 0 + .dw 0x6d93, 0xc436, 0x6dbf, 0xc436, 0x21, 0 + .dw 0x6dc1, 0xc436, 0x6dc1, 0xc436, 0x21, 0 + .dw 0x6dc3, 0xc436, 0x6dcf, 0xc436, 0x21, 0 + .dw 0x6dd1, 0xc436, 0x6dd1, 0xc436, 0x21, 0 + .dw 0x6dd3, 0xc436, 0x6dff, 0xc436, 0x21, 0 + .dw 0x6e01, 0xc436, 0x6e01, 0xc436, 0x21, 0 + .dw 0x6e03, 0xc436, 0x6e0f, 0xc436, 0x21, 0 + .dw 0x6e11, 0xc436, 0x6e11, 0xc436, 0x21, 0 + .dw 0x6e13, 0xc436, 0x6e3f, 0xc436, 0x21, 0 + .dw 0x6e41, 0xc436, 0x6e41, 0xc436, 0x21, 0 + .dw 0x6e43, 0xc436, 0x6e4f, 0xc436, 0x21, 0 + .dw 0x6e51, 0xc436, 0x6e51, 0xc436, 0x21, 0 + .dw 0x6e53, 0xc436, 0x6e7f, 0xc436, 0x21, 0 + .dw 0x6e81, 0xc436, 0x6e81, 0xc436, 0x21, 0 + .dw 0x6e83, 0xc436, 0x6e8f, 0xc436, 0x21, 0 + .dw 0x6e91, 0xc436, 0x6e91, 0xc436, 0x21, 0 + .dw 0x6e93, 0xc436, 0x6ebf, 0xc436, 0x21, 0 + .dw 0x6ec1, 0xc436, 0x6ec1, 0xc436, 0x21, 0 + .dw 0x6ec3, 0xc436, 0x6ecf, 0xc436, 0x21, 0 + .dw 0x6ed1, 0xc436, 0x6ed1, 0xc436, 0x21, 0 + .dw 0x6ed3, 0xc436, 0x6eff, 0xc436, 0x21, 0 + .dw 0x6f01, 0xc436, 0x6f01, 0xc436, 0x21, 0 + .dw 0x6f03, 0xc436, 0x6f0f, 0xc436, 0x21, 0 + .dw 0x6f11, 0xc436, 0x6f11, 0xc436, 0x21, 0 + .dw 0x6f13, 0xc436, 0x6f3f, 0xc436, 0x21, 0 + .dw 0x6f41, 0xc436, 0x6f41, 0xc436, 0x21, 0 + .dw 0x6f43, 0xc436, 0x6f4f, 0xc436, 0x21, 0 + .dw 0x6f51, 0xc436, 0x6f51, 0xc436, 0x21, 0 + .dw 0x6f53, 0xc436, 0x6f7f, 0xc436, 0x21, 0 + .dw 0x6f81, 0xc436, 0x6f81, 0xc436, 0x21, 0 + .dw 0x6f83, 0xc436, 0x6f8f, 0xc436, 0x21, 0 + .dw 0x6f91, 0xc436, 0x6f91, 0xc436, 0x21, 0 + .dw 0x6f93, 0xc436, 0x6fbf, 0xc436, 0x21, 0 + .dw 0x6fc1, 0xc436, 0x6fc1, 0xc436, 0x21, 0 + .dw 0x6fc3, 0xc436, 0x6fcf, 0xc436, 0x21, 0 + .dw 0x6fd1, 0xc436, 0x6fd1, 0xc436, 0x21, 0 + .dw 0x6fd3, 0xc436, 0xffff, 0xc436, 0x21, 0 + .dw 0x0001, 0xc437, 0x0001, 0xc437, 0x21, 0 + .dw 0x0003, 0xc437, 0x000f, 0xc437, 0x21, 0 + .dw 0x0011, 0xc437, 0x0011, 0xc437, 0x21, 0 + .dw 0x0013, 0xc437, 0x003f, 0xc437, 0x21, 0 + .dw 0x0041, 0xc437, 0x0041, 0xc437, 0x21, 0 + .dw 0x0043, 0xc437, 0x004f, 0xc437, 0x21, 0 + .dw 0x0051, 0xc437, 0x0051, 0xc437, 0x21, 0 + .dw 0x0053, 0xc437, 0x007f, 0xc437, 0x21, 0 + .dw 0x0081, 0xc437, 0x0081, 0xc437, 0x21, 0 + .dw 0x0083, 0xc437, 0x008f, 0xc437, 0x21, 0 + .dw 0x0091, 0xc437, 0x0091, 0xc437, 0x21, 0 + .dw 0x0093, 0xc437, 0x00bf, 0xc437, 0x21, 0 + .dw 0x00c1, 0xc437, 0x00c1, 0xc437, 0x21, 0 + .dw 0x00c3, 0xc437, 0x00cf, 0xc437, 0x21, 0 + .dw 0x00d1, 0xc437, 0x00d1, 0xc437, 0x21, 0 + .dw 0x00d3, 0xc437, 0x00ff, 0xc437, 0x21, 0 + .dw 0x0101, 0xc437, 0x0101, 0xc437, 0x21, 0 + .dw 0x0103, 0xc437, 0x010f, 0xc437, 0x21, 0 + .dw 0x0111, 0xc437, 0x0111, 0xc437, 0x21, 0 + .dw 0x0113, 0xc437, 0x013f, 0xc437, 0x21, 0 + .dw 0x0141, 0xc437, 0x0141, 0xc437, 0x21, 0 + .dw 0x0143, 0xc437, 0x014f, 0xc437, 0x21, 0 + .dw 0x0151, 0xc437, 0x0151, 0xc437, 0x21, 0 + .dw 0x0153, 0xc437, 0x017f, 0xc437, 0x21, 0 + .dw 0x0181, 0xc437, 0x0181, 0xc437, 0x21, 0 + .dw 0x0183, 0xc437, 0x018f, 0xc437, 0x21, 0 + .dw 0x0191, 0xc437, 0x0191, 0xc437, 0x21, 0 + .dw 0x0193, 0xc437, 0x01bf, 0xc437, 0x21, 0 + .dw 0x01c1, 0xc437, 0x01c1, 0xc437, 0x21, 0 + .dw 0x01c3, 0xc437, 0x01cf, 0xc437, 0x21, 0 + .dw 0x01d1, 0xc437, 0x01d1, 0xc437, 0x21, 0 + .dw 0x01d3, 0xc437, 0x01ff, 0xc437, 0x21, 0 + .dw 0x0201, 0xc437, 0x0201, 0xc437, 0x21, 0 + .dw 0x0203, 0xc437, 0x020f, 0xc437, 0x21, 0 + .dw 0x0211, 0xc437, 0x0211, 0xc437, 0x21, 0 + .dw 0x0213, 0xc437, 0x023f, 0xc437, 0x21, 0 + .dw 0x0241, 0xc437, 0x0241, 0xc437, 0x21, 0 + .dw 0x0243, 0xc437, 0x024f, 0xc437, 0x21, 0 + .dw 0x0251, 0xc437, 0x0251, 0xc437, 0x21, 0 + .dw 0x0253, 0xc437, 0x027f, 0xc437, 0x21, 0 + .dw 0x0281, 0xc437, 0x0281, 0xc437, 0x21, 0 + .dw 0x0283, 0xc437, 0x028f, 0xc437, 0x21, 0 + .dw 0x0291, 0xc437, 0x0291, 0xc437, 0x21, 0 + .dw 0x0293, 0xc437, 0x02bf, 0xc437, 0x21, 0 + .dw 0x02c1, 0xc437, 0x02c1, 0xc437, 0x21, 0 + .dw 0x02c3, 0xc437, 0x02cf, 0xc437, 0x21, 0 + .dw 0x02d1, 0xc437, 0x02d1, 0xc437, 0x21, 0 + .dw 0x02d3, 0xc437, 0x02ff, 0xc437, 0x21, 0 + .dw 0x0301, 0xc437, 0x0301, 0xc437, 0x21, 0 + .dw 0x0303, 0xc437, 0x030f, 0xc437, 0x21, 0 + .dw 0x0311, 0xc437, 0x0311, 0xc437, 0x21, 0 + .dw 0x0313, 0xc437, 0x033f, 0xc437, 0x21, 0 + .dw 0x0341, 0xc437, 0x0341, 0xc437, 0x21, 0 + .dw 0x0343, 0xc437, 0x034f, 0xc437, 0x21, 0 + .dw 0x0351, 0xc437, 0x0351, 0xc437, 0x21, 0 + .dw 0x0353, 0xc437, 0x037f, 0xc437, 0x21, 0 + .dw 0x0381, 0xc437, 0x0381, 0xc437, 0x21, 0 + .dw 0x0383, 0xc437, 0x038f, 0xc437, 0x21, 0 + .dw 0x0391, 0xc437, 0x0391, 0xc437, 0x21, 0 + .dw 0x0393, 0xc437, 0x03bf, 0xc437, 0x21, 0 + .dw 0x03c1, 0xc437, 0x03c1, 0xc437, 0x21, 0 + .dw 0x03c3, 0xc437, 0x03cf, 0xc437, 0x21, 0 + .dw 0x03d1, 0xc437, 0x03d1, 0xc437, 0x21, 0 + .dw 0x03d3, 0xc437, 0x03ff, 0xc437, 0x21, 0 + .dw 0x0401, 0xc437, 0x0401, 0xc437, 0x21, 0 + .dw 0x0403, 0xc437, 0x040f, 0xc437, 0x21, 0 + .dw 0x0411, 0xc437, 0x0411, 0xc437, 0x21, 0 + .dw 0x0413, 0xc437, 0x043f, 0xc437, 0x21, 0 + .dw 0x0441, 0xc437, 0x0441, 0xc437, 0x21, 0 + .dw 0x0443, 0xc437, 0x044f, 0xc437, 0x21, 0 + .dw 0x0451, 0xc437, 0x0451, 0xc437, 0x21, 0 + .dw 0x0453, 0xc437, 0x047f, 0xc437, 0x21, 0 + .dw 0x0481, 0xc437, 0x0481, 0xc437, 0x21, 0 + .dw 0x0483, 0xc437, 0x048f, 0xc437, 0x21, 0 + .dw 0x0491, 0xc437, 0x0491, 0xc437, 0x21, 0 + .dw 0x0493, 0xc437, 0x04bf, 0xc437, 0x21, 0 + .dw 0x04c1, 0xc437, 0x04c1, 0xc437, 0x21, 0 + .dw 0x04c3, 0xc437, 0x04cf, 0xc437, 0x21, 0 + .dw 0x04d1, 0xc437, 0x04d1, 0xc437, 0x21, 0 + .dw 0x04d3, 0xc437, 0x04ff, 0xc437, 0x21, 0 + .dw 0x0501, 0xc437, 0x0501, 0xc437, 0x21, 0 + .dw 0x0503, 0xc437, 0x050f, 0xc437, 0x21, 0 + .dw 0x0511, 0xc437, 0x0511, 0xc437, 0x21, 0 + .dw 0x0513, 0xc437, 0x053f, 0xc437, 0x21, 0 + .dw 0x0541, 0xc437, 0x0541, 0xc437, 0x21, 0 + .dw 0x0543, 0xc437, 0x054f, 0xc437, 0x21, 0 + .dw 0x0551, 0xc437, 0x0551, 0xc437, 0x21, 0 + .dw 0x0553, 0xc437, 0x057f, 0xc437, 0x21, 0 + .dw 0x0581, 0xc437, 0x0581, 0xc437, 0x21, 0 + .dw 0x0583, 0xc437, 0x058f, 0xc437, 0x21, 0 + .dw 0x0591, 0xc437, 0x0591, 0xc437, 0x21, 0 + .dw 0x0593, 0xc437, 0x05bf, 0xc437, 0x21, 0 + .dw 0x05c1, 0xc437, 0x05c1, 0xc437, 0x21, 0 + .dw 0x05c3, 0xc437, 0x05cf, 0xc437, 0x21, 0 + .dw 0x05d1, 0xc437, 0x05d1, 0xc437, 0x21, 0 + .dw 0x05d3, 0xc437, 0x05ff, 0xc437, 0x21, 0 + .dw 0x0601, 0xc437, 0x0601, 0xc437, 0x21, 0 + .dw 0x0603, 0xc437, 0x060f, 0xc437, 0x21, 0 + .dw 0x0611, 0xc437, 0x0611, 0xc437, 0x21, 0 + .dw 0x0613, 0xc437, 0x063f, 0xc437, 0x21, 0 + .dw 0x0641, 0xc437, 0x0641, 0xc437, 0x21, 0 + .dw 0x0643, 0xc437, 0x064f, 0xc437, 0x21, 0 + .dw 0x0651, 0xc437, 0x0651, 0xc437, 0x21, 0 + .dw 0x0653, 0xc437, 0x067f, 0xc437, 0x21, 0 + .dw 0x0681, 0xc437, 0x0681, 0xc437, 0x21, 0 + .dw 0x0683, 0xc437, 0x068f, 0xc437, 0x21, 0 + .dw 0x0691, 0xc437, 0x0691, 0xc437, 0x21, 0 + .dw 0x0693, 0xc437, 0x06bf, 0xc437, 0x21, 0 + .dw 0x06c1, 0xc437, 0x06c1, 0xc437, 0x21, 0 + .dw 0x06c3, 0xc437, 0x06cf, 0xc437, 0x21, 0 + .dw 0x06d1, 0xc437, 0x06d1, 0xc437, 0x21, 0 + .dw 0x06d3, 0xc437, 0x06ff, 0xc437, 0x21, 0 + .dw 0x0701, 0xc437, 0x0701, 0xc437, 0x21, 0 + .dw 0x0703, 0xc437, 0x070f, 0xc437, 0x21, 0 + .dw 0x0711, 0xc437, 0x0711, 0xc437, 0x21, 0 + .dw 0x0713, 0xc437, 0x073f, 0xc437, 0x21, 0 + .dw 0x0741, 0xc437, 0x0741, 0xc437, 0x21, 0 + .dw 0x0743, 0xc437, 0x074f, 0xc437, 0x21, 0 + .dw 0x0751, 0xc437, 0x0751, 0xc437, 0x21, 0 + .dw 0x0753, 0xc437, 0x077f, 0xc437, 0x21, 0 + .dw 0x0781, 0xc437, 0x0781, 0xc437, 0x21, 0 + .dw 0x0783, 0xc437, 0x078f, 0xc437, 0x21, 0 + .dw 0x0791, 0xc437, 0x0791, 0xc437, 0x21, 0 + .dw 0x0793, 0xc437, 0x07bf, 0xc437, 0x21, 0 + .dw 0x07c1, 0xc437, 0x07c1, 0xc437, 0x21, 0 + .dw 0x07c3, 0xc437, 0x07cf, 0xc437, 0x21, 0 + .dw 0x07d1, 0xc437, 0x07d1, 0xc437, 0x21, 0 + .dw 0x07d3, 0xc437, 0x07ff, 0xc437, 0x21, 0 + .dw 0x0801, 0xc437, 0x0801, 0xc437, 0x21, 0 + .dw 0x0803, 0xc437, 0x080f, 0xc437, 0x21, 0 + .dw 0x0811, 0xc437, 0x0811, 0xc437, 0x21, 0 + .dw 0x0813, 0xc437, 0x083f, 0xc437, 0x21, 0 + .dw 0x0841, 0xc437, 0x0841, 0xc437, 0x21, 0 + .dw 0x0843, 0xc437, 0x084f, 0xc437, 0x21, 0 + .dw 0x0851, 0xc437, 0x0851, 0xc437, 0x21, 0 + .dw 0x0853, 0xc437, 0x087f, 0xc437, 0x21, 0 + .dw 0x0881, 0xc437, 0x0881, 0xc437, 0x21, 0 + .dw 0x0883, 0xc437, 0x088f, 0xc437, 0x21, 0 + .dw 0x0891, 0xc437, 0x0891, 0xc437, 0x21, 0 + .dw 0x0893, 0xc437, 0x08bf, 0xc437, 0x21, 0 + .dw 0x08c1, 0xc437, 0x08c1, 0xc437, 0x21, 0 + .dw 0x08c3, 0xc437, 0x08cf, 0xc437, 0x21, 0 + .dw 0x08d1, 0xc437, 0x08d1, 0xc437, 0x21, 0 + .dw 0x08d3, 0xc437, 0x08ff, 0xc437, 0x21, 0 + .dw 0x0901, 0xc437, 0x0901, 0xc437, 0x21, 0 + .dw 0x0903, 0xc437, 0x090f, 0xc437, 0x21, 0 + .dw 0x0911, 0xc437, 0x0911, 0xc437, 0x21, 0 + .dw 0x0913, 0xc437, 0x093f, 0xc437, 0x21, 0 + .dw 0x0941, 0xc437, 0x0941, 0xc437, 0x21, 0 + .dw 0x0943, 0xc437, 0x094f, 0xc437, 0x21, 0 + .dw 0x0951, 0xc437, 0x0951, 0xc437, 0x21, 0 + .dw 0x0953, 0xc437, 0x097f, 0xc437, 0x21, 0 + .dw 0x0981, 0xc437, 0x0981, 0xc437, 0x21, 0 + .dw 0x0983, 0xc437, 0x098f, 0xc437, 0x21, 0 + .dw 0x0991, 0xc437, 0x0991, 0xc437, 0x21, 0 + .dw 0x0993, 0xc437, 0x09bf, 0xc437, 0x21, 0 + .dw 0x09c1, 0xc437, 0x09c1, 0xc437, 0x21, 0 + .dw 0x09c3, 0xc437, 0x09cf, 0xc437, 0x21, 0 + .dw 0x09d1, 0xc437, 0x09d1, 0xc437, 0x21, 0 + .dw 0x09d3, 0xc437, 0x09ff, 0xc437, 0x21, 0 + .dw 0x0a01, 0xc437, 0x0a01, 0xc437, 0x21, 0 + .dw 0x0a03, 0xc437, 0x0a0f, 0xc437, 0x21, 0 + .dw 0x0a11, 0xc437, 0x0a11, 0xc437, 0x21, 0 + .dw 0x0a13, 0xc437, 0x0a3f, 0xc437, 0x21, 0 + .dw 0x0a41, 0xc437, 0x0a41, 0xc437, 0x21, 0 + .dw 0x0a43, 0xc437, 0x0a4f, 0xc437, 0x21, 0 + .dw 0x0a51, 0xc437, 0x0a51, 0xc437, 0x21, 0 + .dw 0x0a53, 0xc437, 0x0a7f, 0xc437, 0x21, 0 + .dw 0x0a81, 0xc437, 0x0a81, 0xc437, 0x21, 0 + .dw 0x0a83, 0xc437, 0x0a8f, 0xc437, 0x21, 0 + .dw 0x0a91, 0xc437, 0x0a91, 0xc437, 0x21, 0 + .dw 0x0a93, 0xc437, 0x0abf, 0xc437, 0x21, 0 + .dw 0x0ac1, 0xc437, 0x0ac1, 0xc437, 0x21, 0 + .dw 0x0ac3, 0xc437, 0x0acf, 0xc437, 0x21, 0 + .dw 0x0ad1, 0xc437, 0x0ad1, 0xc437, 0x21, 0 + .dw 0x0ad3, 0xc437, 0x0aff, 0xc437, 0x21, 0 + .dw 0x0b01, 0xc437, 0x0b01, 0xc437, 0x21, 0 + .dw 0x0b03, 0xc437, 0x0b0f, 0xc437, 0x21, 0 + .dw 0x0b11, 0xc437, 0x0b11, 0xc437, 0x21, 0 + .dw 0x0b13, 0xc437, 0x0b3f, 0xc437, 0x21, 0 + .dw 0x0b41, 0xc437, 0x0b41, 0xc437, 0x21, 0 + .dw 0x0b43, 0xc437, 0x0b4f, 0xc437, 0x21, 0 + .dw 0x0b51, 0xc437, 0x0b51, 0xc437, 0x21, 0 + .dw 0x0b53, 0xc437, 0x0b7f, 0xc437, 0x21, 0 + .dw 0x0b81, 0xc437, 0x0b81, 0xc437, 0x21, 0 + .dw 0x0b83, 0xc437, 0x0b8f, 0xc437, 0x21, 0 + .dw 0x0b91, 0xc437, 0x0b91, 0xc437, 0x21, 0 + .dw 0x0b93, 0xc437, 0x0bbf, 0xc437, 0x21, 0 + .dw 0x0bc1, 0xc437, 0x0bc1, 0xc437, 0x21, 0 + .dw 0x0bc3, 0xc437, 0x0bcf, 0xc437, 0x21, 0 + .dw 0x0bd1, 0xc437, 0x0bd1, 0xc437, 0x21, 0 + .dw 0x0bd3, 0xc437, 0x0bff, 0xc437, 0x21, 0 + .dw 0x0c01, 0xc437, 0x0c01, 0xc437, 0x21, 0 + .dw 0x0c03, 0xc437, 0x0c0f, 0xc437, 0x21, 0 + .dw 0x0c11, 0xc437, 0x0c11, 0xc437, 0x21, 0 + .dw 0x0c13, 0xc437, 0x0c3f, 0xc437, 0x21, 0 + .dw 0x0c41, 0xc437, 0x0c41, 0xc437, 0x21, 0 + .dw 0x0c43, 0xc437, 0x0c4f, 0xc437, 0x21, 0 + .dw 0x0c51, 0xc437, 0x0c51, 0xc437, 0x21, 0 + .dw 0x0c53, 0xc437, 0x0c7f, 0xc437, 0x21, 0 + .dw 0x0c81, 0xc437, 0x0c81, 0xc437, 0x21, 0 + .dw 0x0c83, 0xc437, 0x0c8f, 0xc437, 0x21, 0 + .dw 0x0c91, 0xc437, 0x0c91, 0xc437, 0x21, 0 + .dw 0x0c93, 0xc437, 0x0cbf, 0xc437, 0x21, 0 + .dw 0x0cc1, 0xc437, 0x0cc1, 0xc437, 0x21, 0 + .dw 0x0cc3, 0xc437, 0x0ccf, 0xc437, 0x21, 0 + .dw 0x0cd1, 0xc437, 0x0cd1, 0xc437, 0x21, 0 + .dw 0x0cd3, 0xc437, 0x0cff, 0xc437, 0x21, 0 + .dw 0x0d01, 0xc437, 0x0d01, 0xc437, 0x21, 0 + .dw 0x0d03, 0xc437, 0x0d0f, 0xc437, 0x21, 0 + .dw 0x0d11, 0xc437, 0x0d11, 0xc437, 0x21, 0 + .dw 0x0d13, 0xc437, 0x0d3f, 0xc437, 0x21, 0 + .dw 0x0d41, 0xc437, 0x0d41, 0xc437, 0x21, 0 + .dw 0x0d43, 0xc437, 0x0d4f, 0xc437, 0x21, 0 + .dw 0x0d51, 0xc437, 0x0d51, 0xc437, 0x21, 0 + .dw 0x0d53, 0xc437, 0x0d7f, 0xc437, 0x21, 0 + .dw 0x0d81, 0xc437, 0x0d81, 0xc437, 0x21, 0 + .dw 0x0d83, 0xc437, 0x0d8f, 0xc437, 0x21, 0 + .dw 0x0d91, 0xc437, 0x0d91, 0xc437, 0x21, 0 + .dw 0x0d93, 0xc437, 0x0dbf, 0xc437, 0x21, 0 + .dw 0x0dc1, 0xc437, 0x0dc1, 0xc437, 0x21, 0 + .dw 0x0dc3, 0xc437, 0x0dcf, 0xc437, 0x21, 0 + .dw 0x0dd1, 0xc437, 0x0dd1, 0xc437, 0x21, 0 + .dw 0x0dd3, 0xc437, 0x0dff, 0xc437, 0x21, 0 + .dw 0x0e01, 0xc437, 0x0e01, 0xc437, 0x21, 0 + .dw 0x0e03, 0xc437, 0x0e0f, 0xc437, 0x21, 0 + .dw 0x0e11, 0xc437, 0x0e11, 0xc437, 0x21, 0 + .dw 0x0e13, 0xc437, 0x0e3f, 0xc437, 0x21, 0 + .dw 0x0e41, 0xc437, 0x0e41, 0xc437, 0x21, 0 + .dw 0x0e43, 0xc437, 0x0e4f, 0xc437, 0x21, 0 + .dw 0x0e51, 0xc437, 0x0e51, 0xc437, 0x21, 0 + .dw 0x0e53, 0xc437, 0x0e7f, 0xc437, 0x21, 0 + .dw 0x0e81, 0xc437, 0x0e81, 0xc437, 0x21, 0 + .dw 0x0e83, 0xc437, 0x0e8f, 0xc437, 0x21, 0 + .dw 0x0e91, 0xc437, 0x0e91, 0xc437, 0x21, 0 + .dw 0x0e93, 0xc437, 0x0ebf, 0xc437, 0x21, 0 + .dw 0x0ec1, 0xc437, 0x0ec1, 0xc437, 0x21, 0 + .dw 0x0ec3, 0xc437, 0x0ecf, 0xc437, 0x21, 0 + .dw 0x0ed1, 0xc437, 0x0ed1, 0xc437, 0x21, 0 + .dw 0x0ed3, 0xc437, 0x0eff, 0xc437, 0x21, 0 + .dw 0x0f01, 0xc437, 0x0f01, 0xc437, 0x21, 0 + .dw 0x0f03, 0xc437, 0x0f0f, 0xc437, 0x21, 0 + .dw 0x0f11, 0xc437, 0x0f11, 0xc437, 0x21, 0 + .dw 0x0f13, 0xc437, 0x0f3f, 0xc437, 0x21, 0 + .dw 0x0f41, 0xc437, 0x0f41, 0xc437, 0x21, 0 + .dw 0x0f43, 0xc437, 0x0f4f, 0xc437, 0x21, 0 + .dw 0x0f51, 0xc437, 0x0f51, 0xc437, 0x21, 0 + .dw 0x0f53, 0xc437, 0x0f7f, 0xc437, 0x21, 0 + .dw 0x0f81, 0xc437, 0x0f81, 0xc437, 0x21, 0 + .dw 0x0f83, 0xc437, 0x0f8f, 0xc437, 0x21, 0 + .dw 0x0f91, 0xc437, 0x0f91, 0xc437, 0x21, 0 + .dw 0x0f93, 0xc437, 0x0fbf, 0xc437, 0x21, 0 + .dw 0x0fc1, 0xc437, 0x0fc1, 0xc437, 0x21, 0 + .dw 0x0fc3, 0xc437, 0x0fcf, 0xc437, 0x21, 0 + .dw 0x0fd1, 0xc437, 0x0fd1, 0xc437, 0x21, 0 + .dw 0x0fd3, 0xc437, 0x1fff, 0xc437, 0x21, 0 + .dw 0x2001, 0xc437, 0x2001, 0xc437, 0x21, 0 + .dw 0x2003, 0xc437, 0x200f, 0xc437, 0x21, 0 + .dw 0x2011, 0xc437, 0x2011, 0xc437, 0x21, 0 + .dw 0x2013, 0xc437, 0x203f, 0xc437, 0x21, 0 + .dw 0x2041, 0xc437, 0x2041, 0xc437, 0x21, 0 + .dw 0x2043, 0xc437, 0x204f, 0xc437, 0x21, 0 + .dw 0x2051, 0xc437, 0x2051, 0xc437, 0x21, 0 + .dw 0x2053, 0xc437, 0x207f, 0xc437, 0x21, 0 + .dw 0x2081, 0xc437, 0x2081, 0xc437, 0x21, 0 + .dw 0x2083, 0xc437, 0x208f, 0xc437, 0x21, 0 + .dw 0x2091, 0xc437, 0x2091, 0xc437, 0x21, 0 + .dw 0x2093, 0xc437, 0x20bf, 0xc437, 0x21, 0 + .dw 0x20c1, 0xc437, 0x20c1, 0xc437, 0x21, 0 + .dw 0x20c3, 0xc437, 0x20cf, 0xc437, 0x21, 0 + .dw 0x20d1, 0xc437, 0x20d1, 0xc437, 0x21, 0 + .dw 0x20d3, 0xc437, 0x20ff, 0xc437, 0x21, 0 + .dw 0x2101, 0xc437, 0x2101, 0xc437, 0x21, 0 + .dw 0x2103, 0xc437, 0x210f, 0xc437, 0x21, 0 + .dw 0x2111, 0xc437, 0x2111, 0xc437, 0x21, 0 + .dw 0x2113, 0xc437, 0x213f, 0xc437, 0x21, 0 + .dw 0x2141, 0xc437, 0x2141, 0xc437, 0x21, 0 + .dw 0x2143, 0xc437, 0x214f, 0xc437, 0x21, 0 + .dw 0x2151, 0xc437, 0x2151, 0xc437, 0x21, 0 + .dw 0x2153, 0xc437, 0x217f, 0xc437, 0x21, 0 + .dw 0x2181, 0xc437, 0x2181, 0xc437, 0x21, 0 + .dw 0x2183, 0xc437, 0x218f, 0xc437, 0x21, 0 + .dw 0x2191, 0xc437, 0x2191, 0xc437, 0x21, 0 + .dw 0x2193, 0xc437, 0x21bf, 0xc437, 0x21, 0 + .dw 0x21c1, 0xc437, 0x21c1, 0xc437, 0x21, 0 + .dw 0x21c3, 0xc437, 0x21cf, 0xc437, 0x21, 0 + .dw 0x21d1, 0xc437, 0x21d1, 0xc437, 0x21, 0 + .dw 0x21d3, 0xc437, 0x21ff, 0xc437, 0x21, 0 + .dw 0x2201, 0xc437, 0x2201, 0xc437, 0x21, 0 + .dw 0x2203, 0xc437, 0x220f, 0xc437, 0x21, 0 + .dw 0x2211, 0xc437, 0x2211, 0xc437, 0x21, 0 + .dw 0x2213, 0xc437, 0x223f, 0xc437, 0x21, 0 + .dw 0x2241, 0xc437, 0x2241, 0xc437, 0x21, 0 + .dw 0x2243, 0xc437, 0x224f, 0xc437, 0x21, 0 + .dw 0x2251, 0xc437, 0x2251, 0xc437, 0x21, 0 + .dw 0x2253, 0xc437, 0x227f, 0xc437, 0x21, 0 + .dw 0x2281, 0xc437, 0x2281, 0xc437, 0x21, 0 + .dw 0x2283, 0xc437, 0x228f, 0xc437, 0x21, 0 + .dw 0x2291, 0xc437, 0x2291, 0xc437, 0x21, 0 + .dw 0x2293, 0xc437, 0x22bf, 0xc437, 0x21, 0 + .dw 0x22c1, 0xc437, 0x22c1, 0xc437, 0x21, 0 + .dw 0x22c3, 0xc437, 0x22cf, 0xc437, 0x21, 0 + .dw 0x22d1, 0xc437, 0x22d1, 0xc437, 0x21, 0 + .dw 0x22d3, 0xc437, 0x22ff, 0xc437, 0x21, 0 + .dw 0x2301, 0xc437, 0x2301, 0xc437, 0x21, 0 + .dw 0x2303, 0xc437, 0x230f, 0xc437, 0x21, 0 + .dw 0x2311, 0xc437, 0x2311, 0xc437, 0x21, 0 + .dw 0x2313, 0xc437, 0x233f, 0xc437, 0x21, 0 + .dw 0x2341, 0xc437, 0x2341, 0xc437, 0x21, 0 + .dw 0x2343, 0xc437, 0x234f, 0xc437, 0x21, 0 + .dw 0x2351, 0xc437, 0x2351, 0xc437, 0x21, 0 + .dw 0x2353, 0xc437, 0x237f, 0xc437, 0x21, 0 + .dw 0x2381, 0xc437, 0x2381, 0xc437, 0x21, 0 + .dw 0x2383, 0xc437, 0x238f, 0xc437, 0x21, 0 + .dw 0x2391, 0xc437, 0x2391, 0xc437, 0x21, 0 + .dw 0x2393, 0xc437, 0x23bf, 0xc437, 0x21, 0 + .dw 0x23c1, 0xc437, 0x23c1, 0xc437, 0x21, 0 + .dw 0x23c3, 0xc437, 0x23cf, 0xc437, 0x21, 0 + .dw 0x23d1, 0xc437, 0x23d1, 0xc437, 0x21, 0 + .dw 0x23d3, 0xc437, 0x23ff, 0xc437, 0x21, 0 + .dw 0x2401, 0xc437, 0x2401, 0xc437, 0x21, 0 + .dw 0x2403, 0xc437, 0x240f, 0xc437, 0x21, 0 + .dw 0x2411, 0xc437, 0x2411, 0xc437, 0x21, 0 + .dw 0x2413, 0xc437, 0x243f, 0xc437, 0x21, 0 + .dw 0x2441, 0xc437, 0x2441, 0xc437, 0x21, 0 + .dw 0x2443, 0xc437, 0x244f, 0xc437, 0x21, 0 + .dw 0x2451, 0xc437, 0x2451, 0xc437, 0x21, 0 + .dw 0x2453, 0xc437, 0x247f, 0xc437, 0x21, 0 + .dw 0x2481, 0xc437, 0x2481, 0xc437, 0x21, 0 + .dw 0x2483, 0xc437, 0x248f, 0xc437, 0x21, 0 + .dw 0x2491, 0xc437, 0x2491, 0xc437, 0x21, 0 + .dw 0x2493, 0xc437, 0x24bf, 0xc437, 0x21, 0 + .dw 0x24c1, 0xc437, 0x24c1, 0xc437, 0x21, 0 + .dw 0x24c3, 0xc437, 0x24cf, 0xc437, 0x21, 0 + .dw 0x24d1, 0xc437, 0x24d1, 0xc437, 0x21, 0 + .dw 0x24d3, 0xc437, 0x24ff, 0xc437, 0x21, 0 + .dw 0x2501, 0xc437, 0x2501, 0xc437, 0x21, 0 + .dw 0x2503, 0xc437, 0x250f, 0xc437, 0x21, 0 + .dw 0x2511, 0xc437, 0x2511, 0xc437, 0x21, 0 + .dw 0x2513, 0xc437, 0x253f, 0xc437, 0x21, 0 + .dw 0x2541, 0xc437, 0x2541, 0xc437, 0x21, 0 + .dw 0x2543, 0xc437, 0x254f, 0xc437, 0x21, 0 + .dw 0x2551, 0xc437, 0x2551, 0xc437, 0x21, 0 + .dw 0x2553, 0xc437, 0x257f, 0xc437, 0x21, 0 + .dw 0x2581, 0xc437, 0x2581, 0xc437, 0x21, 0 + .dw 0x2583, 0xc437, 0x258f, 0xc437, 0x21, 0 + .dw 0x2591, 0xc437, 0x2591, 0xc437, 0x21, 0 + .dw 0x2593, 0xc437, 0x25bf, 0xc437, 0x21, 0 + .dw 0x25c1, 0xc437, 0x25c1, 0xc437, 0x21, 0 + .dw 0x25c3, 0xc437, 0x25cf, 0xc437, 0x21, 0 + .dw 0x25d1, 0xc437, 0x25d1, 0xc437, 0x21, 0 + .dw 0x25d3, 0xc437, 0x25ff, 0xc437, 0x21, 0 + .dw 0x2601, 0xc437, 0x2601, 0xc437, 0x21, 0 + .dw 0x2603, 0xc437, 0x260f, 0xc437, 0x21, 0 + .dw 0x2611, 0xc437, 0x2611, 0xc437, 0x21, 0 + .dw 0x2613, 0xc437, 0x263f, 0xc437, 0x21, 0 + .dw 0x2641, 0xc437, 0x2641, 0xc437, 0x21, 0 + .dw 0x2643, 0xc437, 0x264f, 0xc437, 0x21, 0 + .dw 0x2651, 0xc437, 0x2651, 0xc437, 0x21, 0 + .dw 0x2653, 0xc437, 0x267f, 0xc437, 0x21, 0 + .dw 0x2681, 0xc437, 0x2681, 0xc437, 0x21, 0 + .dw 0x2683, 0xc437, 0x268f, 0xc437, 0x21, 0 + .dw 0x2691, 0xc437, 0x2691, 0xc437, 0x21, 0 + .dw 0x2693, 0xc437, 0x26bf, 0xc437, 0x21, 0 + .dw 0x26c1, 0xc437, 0x26c1, 0xc437, 0x21, 0 + .dw 0x26c3, 0xc437, 0x26cf, 0xc437, 0x21, 0 + .dw 0x26d1, 0xc437, 0x26d1, 0xc437, 0x21, 0 + .dw 0x26d3, 0xc437, 0x26ff, 0xc437, 0x21, 0 + .dw 0x2701, 0xc437, 0x2701, 0xc437, 0x21, 0 + .dw 0x2703, 0xc437, 0x270f, 0xc437, 0x21, 0 + .dw 0x2711, 0xc437, 0x2711, 0xc437, 0x21, 0 + .dw 0x2713, 0xc437, 0x273f, 0xc437, 0x21, 0 + .dw 0x2741, 0xc437, 0x2741, 0xc437, 0x21, 0 + .dw 0x2743, 0xc437, 0x274f, 0xc437, 0x21, 0 + .dw 0x2751, 0xc437, 0x2751, 0xc437, 0x21, 0 + .dw 0x2753, 0xc437, 0x277f, 0xc437, 0x21, 0 + .dw 0x2781, 0xc437, 0x2781, 0xc437, 0x21, 0 + .dw 0x2783, 0xc437, 0x278f, 0xc437, 0x21, 0 + .dw 0x2791, 0xc437, 0x2791, 0xc437, 0x21, 0 + .dw 0x2793, 0xc437, 0x27bf, 0xc437, 0x21, 0 + .dw 0x27c1, 0xc437, 0x27c1, 0xc437, 0x21, 0 + .dw 0x27c3, 0xc437, 0x27cf, 0xc437, 0x21, 0 + .dw 0x27d1, 0xc437, 0x27d1, 0xc437, 0x21, 0 + .dw 0x27d3, 0xc437, 0x27ff, 0xc437, 0x21, 0 + .dw 0x2801, 0xc437, 0x2801, 0xc437, 0x21, 0 + .dw 0x2803, 0xc437, 0x280f, 0xc437, 0x21, 0 + .dw 0x2811, 0xc437, 0x2811, 0xc437, 0x21, 0 + .dw 0x2813, 0xc437, 0x283f, 0xc437, 0x21, 0 + .dw 0x2841, 0xc437, 0x2841, 0xc437, 0x21, 0 + .dw 0x2843, 0xc437, 0x284f, 0xc437, 0x21, 0 + .dw 0x2851, 0xc437, 0x2851, 0xc437, 0x21, 0 + .dw 0x2853, 0xc437, 0x287f, 0xc437, 0x21, 0 + .dw 0x2881, 0xc437, 0x2881, 0xc437, 0x21, 0 + .dw 0x2883, 0xc437, 0x288f, 0xc437, 0x21, 0 + .dw 0x2891, 0xc437, 0x2891, 0xc437, 0x21, 0 + .dw 0x2893, 0xc437, 0x28bf, 0xc437, 0x21, 0 + .dw 0x28c1, 0xc437, 0x28c1, 0xc437, 0x21, 0 + .dw 0x28c3, 0xc437, 0x28cf, 0xc437, 0x21, 0 + .dw 0x28d1, 0xc437, 0x28d1, 0xc437, 0x21, 0 + .dw 0x28d3, 0xc437, 0x28ff, 0xc437, 0x21, 0 + .dw 0x2901, 0xc437, 0x2901, 0xc437, 0x21, 0 + .dw 0x2903, 0xc437, 0x290f, 0xc437, 0x21, 0 + .dw 0x2911, 0xc437, 0x2911, 0xc437, 0x21, 0 + .dw 0x2913, 0xc437, 0x293f, 0xc437, 0x21, 0 + .dw 0x2941, 0xc437, 0x2941, 0xc437, 0x21, 0 + .dw 0x2943, 0xc437, 0x294f, 0xc437, 0x21, 0 + .dw 0x2951, 0xc437, 0x2951, 0xc437, 0x21, 0 + .dw 0x2953, 0xc437, 0x297f, 0xc437, 0x21, 0 + .dw 0x2981, 0xc437, 0x2981, 0xc437, 0x21, 0 + .dw 0x2983, 0xc437, 0x298f, 0xc437, 0x21, 0 + .dw 0x2991, 0xc437, 0x2991, 0xc437, 0x21, 0 + .dw 0x2993, 0xc437, 0x29bf, 0xc437, 0x21, 0 + .dw 0x29c1, 0xc437, 0x29c1, 0xc437, 0x21, 0 + .dw 0x29c3, 0xc437, 0x29cf, 0xc437, 0x21, 0 + .dw 0x29d1, 0xc437, 0x29d1, 0xc437, 0x21, 0 + .dw 0x29d3, 0xc437, 0x29ff, 0xc437, 0x21, 0 + .dw 0x2a01, 0xc437, 0x2a01, 0xc437, 0x21, 0 + .dw 0x2a03, 0xc437, 0x2a0f, 0xc437, 0x21, 0 + .dw 0x2a11, 0xc437, 0x2a11, 0xc437, 0x21, 0 + .dw 0x2a13, 0xc437, 0x2a3f, 0xc437, 0x21, 0 + .dw 0x2a41, 0xc437, 0x2a41, 0xc437, 0x21, 0 + .dw 0x2a43, 0xc437, 0x2a4f, 0xc437, 0x21, 0 + .dw 0x2a51, 0xc437, 0x2a51, 0xc437, 0x21, 0 + .dw 0x2a53, 0xc437, 0x2a7f, 0xc437, 0x21, 0 + .dw 0x2a81, 0xc437, 0x2a81, 0xc437, 0x21, 0 + .dw 0x2a83, 0xc437, 0x2a8f, 0xc437, 0x21, 0 + .dw 0x2a91, 0xc437, 0x2a91, 0xc437, 0x21, 0 + .dw 0x2a93, 0xc437, 0x2abf, 0xc437, 0x21, 0 + .dw 0x2ac1, 0xc437, 0x2ac1, 0xc437, 0x21, 0 + .dw 0x2ac3, 0xc437, 0x2acf, 0xc437, 0x21, 0 + .dw 0x2ad1, 0xc437, 0x2ad1, 0xc437, 0x21, 0 + .dw 0x2ad3, 0xc437, 0x2aff, 0xc437, 0x21, 0 + .dw 0x2b01, 0xc437, 0x2b01, 0xc437, 0x21, 0 + .dw 0x2b03, 0xc437, 0x2b0f, 0xc437, 0x21, 0 + .dw 0x2b11, 0xc437, 0x2b11, 0xc437, 0x21, 0 + .dw 0x2b13, 0xc437, 0x2b3f, 0xc437, 0x21, 0 + .dw 0x2b41, 0xc437, 0x2b41, 0xc437, 0x21, 0 + .dw 0x2b43, 0xc437, 0x2b4f, 0xc437, 0x21, 0 + .dw 0x2b51, 0xc437, 0x2b51, 0xc437, 0x21, 0 + .dw 0x2b53, 0xc437, 0x2b7f, 0xc437, 0x21, 0 + .dw 0x2b81, 0xc437, 0x2b81, 0xc437, 0x21, 0 + .dw 0x2b83, 0xc437, 0x2b8f, 0xc437, 0x21, 0 + .dw 0x2b91, 0xc437, 0x2b91, 0xc437, 0x21, 0 + .dw 0x2b93, 0xc437, 0x2bbf, 0xc437, 0x21, 0 + .dw 0x2bc1, 0xc437, 0x2bc1, 0xc437, 0x21, 0 + .dw 0x2bc3, 0xc437, 0x2bcf, 0xc437, 0x21, 0 + .dw 0x2bd1, 0xc437, 0x2bd1, 0xc437, 0x21, 0 + .dw 0x2bd3, 0xc437, 0x2bff, 0xc437, 0x21, 0 + .dw 0x2c01, 0xc437, 0x2c01, 0xc437, 0x21, 0 + .dw 0x2c03, 0xc437, 0x2c0f, 0xc437, 0x21, 0 + .dw 0x2c11, 0xc437, 0x2c11, 0xc437, 0x21, 0 + .dw 0x2c13, 0xc437, 0x2c3f, 0xc437, 0x21, 0 + .dw 0x2c41, 0xc437, 0x2c41, 0xc437, 0x21, 0 + .dw 0x2c43, 0xc437, 0x2c4f, 0xc437, 0x21, 0 + .dw 0x2c51, 0xc437, 0x2c51, 0xc437, 0x21, 0 + .dw 0x2c53, 0xc437, 0x2c7f, 0xc437, 0x21, 0 + .dw 0x2c81, 0xc437, 0x2c81, 0xc437, 0x21, 0 + .dw 0x2c83, 0xc437, 0x2c8f, 0xc437, 0x21, 0 + .dw 0x2c91, 0xc437, 0x2c91, 0xc437, 0x21, 0 + .dw 0x2c93, 0xc437, 0x2cbf, 0xc437, 0x21, 0 + .dw 0x2cc1, 0xc437, 0x2cc1, 0xc437, 0x21, 0 + .dw 0x2cc3, 0xc437, 0x2ccf, 0xc437, 0x21, 0 + .dw 0x2cd1, 0xc437, 0x2cd1, 0xc437, 0x21, 0 + .dw 0x2cd3, 0xc437, 0x2cff, 0xc437, 0x21, 0 + .dw 0x2d01, 0xc437, 0x2d01, 0xc437, 0x21, 0 + .dw 0x2d03, 0xc437, 0x2d0f, 0xc437, 0x21, 0 + .dw 0x2d11, 0xc437, 0x2d11, 0xc437, 0x21, 0 + .dw 0x2d13, 0xc437, 0x2d3f, 0xc437, 0x21, 0 + .dw 0x2d41, 0xc437, 0x2d41, 0xc437, 0x21, 0 + .dw 0x2d43, 0xc437, 0x2d4f, 0xc437, 0x21, 0 + .dw 0x2d51, 0xc437, 0x2d51, 0xc437, 0x21, 0 + .dw 0x2d53, 0xc437, 0x2d7f, 0xc437, 0x21, 0 + .dw 0x2d81, 0xc437, 0x2d81, 0xc437, 0x21, 0 + .dw 0x2d83, 0xc437, 0x2d8f, 0xc437, 0x21, 0 + .dw 0x2d91, 0xc437, 0x2d91, 0xc437, 0x21, 0 + .dw 0x2d93, 0xc437, 0x2dbf, 0xc437, 0x21, 0 + .dw 0x2dc1, 0xc437, 0x2dc1, 0xc437, 0x21, 0 + .dw 0x2dc3, 0xc437, 0x2dcf, 0xc437, 0x21, 0 + .dw 0x2dd1, 0xc437, 0x2dd1, 0xc437, 0x21, 0 + .dw 0x2dd3, 0xc437, 0x2dff, 0xc437, 0x21, 0 + .dw 0x2e01, 0xc437, 0x2e01, 0xc437, 0x21, 0 + .dw 0x2e03, 0xc437, 0x2e0f, 0xc437, 0x21, 0 + .dw 0x2e11, 0xc437, 0x2e11, 0xc437, 0x21, 0 + .dw 0x2e13, 0xc437, 0x2e3f, 0xc437, 0x21, 0 + .dw 0x2e41, 0xc437, 0x2e41, 0xc437, 0x21, 0 + .dw 0x2e43, 0xc437, 0x2e4f, 0xc437, 0x21, 0 + .dw 0x2e51, 0xc437, 0x2e51, 0xc437, 0x21, 0 + .dw 0x2e53, 0xc437, 0x2e7f, 0xc437, 0x21, 0 + .dw 0x2e81, 0xc437, 0x2e81, 0xc437, 0x21, 0 + .dw 0x2e83, 0xc437, 0x2e8f, 0xc437, 0x21, 0 + .dw 0x2e91, 0xc437, 0x2e91, 0xc437, 0x21, 0 + .dw 0x2e93, 0xc437, 0x2ebf, 0xc437, 0x21, 0 + .dw 0x2ec1, 0xc437, 0x2ec1, 0xc437, 0x21, 0 + .dw 0x2ec3, 0xc437, 0x2ecf, 0xc437, 0x21, 0 + .dw 0x2ed1, 0xc437, 0x2ed1, 0xc437, 0x21, 0 + .dw 0x2ed3, 0xc437, 0x2eff, 0xc437, 0x21, 0 + .dw 0x2f01, 0xc437, 0x2f01, 0xc437, 0x21, 0 + .dw 0x2f03, 0xc437, 0x2f0f, 0xc437, 0x21, 0 + .dw 0x2f11, 0xc437, 0x2f11, 0xc437, 0x21, 0 + .dw 0x2f13, 0xc437, 0x2f3f, 0xc437, 0x21, 0 + .dw 0x2f41, 0xc437, 0x2f41, 0xc437, 0x21, 0 + .dw 0x2f43, 0xc437, 0x2f4f, 0xc437, 0x21, 0 + .dw 0x2f51, 0xc437, 0x2f51, 0xc437, 0x21, 0 + .dw 0x2f53, 0xc437, 0x2f7f, 0xc437, 0x21, 0 + .dw 0x2f81, 0xc437, 0x2f81, 0xc437, 0x21, 0 + .dw 0x2f83, 0xc437, 0x2f8f, 0xc437, 0x21, 0 + .dw 0x2f91, 0xc437, 0x2f91, 0xc437, 0x21, 0 + .dw 0x2f93, 0xc437, 0x2fbf, 0xc437, 0x21, 0 + .dw 0x2fc1, 0xc437, 0x2fc1, 0xc437, 0x21, 0 + .dw 0x2fc3, 0xc437, 0x2fcf, 0xc437, 0x21, 0 + .dw 0x2fd1, 0xc437, 0x2fd1, 0xc437, 0x21, 0 + .dw 0x2fd3, 0xc437, 0xffff, 0xc5ff, 0x21, 0 + .dw 0x0040, 0xc600, 0x01ff, 0xc600, 0x21, 0 + .dw 0x0240, 0xc600, 0x03ff, 0xc600, 0x21, 0 + .dw 0x0440, 0xc600, 0x05ff, 0xc600, 0x21, 0 + .dw 0x0640, 0xc600, 0x07ff, 0xc600, 0x21, 0 + .dw 0x0840, 0xc600, 0x09ff, 0xc600, 0x21, 0 + .dw 0x0a40, 0xc600, 0x0bff, 0xc600, 0x21, 0 + .dw 0x0c40, 0xc600, 0x0dff, 0xc600, 0x21, 0 + .dw 0x0e40, 0xc600, 0x0fff, 0xc600, 0x21, 0 + .dw 0x1040, 0xc600, 0x11ff, 0xc600, 0x21, 0 + .dw 0x1240, 0xc600, 0x13ff, 0xc600, 0x21, 0 + .dw 0x1440, 0xc600, 0x15ff, 0xc600, 0x21, 0 + .dw 0x1640, 0xc600, 0x17ff, 0xc600, 0x21, 0 + .dw 0x1840, 0xc600, 0x19ff, 0xc600, 0x21, 0 + .dw 0x1a40, 0xc600, 0x1bff, 0xc600, 0x21, 0 + .dw 0x1c40, 0xc600, 0x1dff, 0xc600, 0x21, 0 + .dw 0x1e40, 0xc600, 0x1fff, 0xc600, 0x21, 0 + .dw 0x2040, 0xc600, 0x21ff, 0xc600, 0x21, 0 + .dw 0x2240, 0xc600, 0x23ff, 0xc600, 0x21, 0 + .dw 0x2440, 0xc600, 0x25ff, 0xc600, 0x21, 0 + .dw 0x2640, 0xc600, 0x27ff, 0xc600, 0x21, 0 + .dw 0x2840, 0xc600, 0x29ff, 0xc600, 0x21, 0 + .dw 0x2a40, 0xc600, 0x2bff, 0xc600, 0x21, 0 + .dw 0x2c40, 0xc600, 0x2dff, 0xc600, 0x21, 0 + .dw 0x2e40, 0xc600, 0x2fff, 0xc600, 0x21, 0 + .dw 0x3040, 0xc600, 0x31ff, 0xc600, 0x21, 0 + .dw 0x3240, 0xc600, 0x33ff, 0xc600, 0x21, 0 + .dw 0x3440, 0xc600, 0x35ff, 0xc600, 0x21, 0 + .dw 0x3640, 0xc600, 0x37ff, 0xc600, 0x21, 0 + .dw 0x3840, 0xc600, 0x39ff, 0xc600, 0x21, 0 + .dw 0x3a40, 0xc600, 0x3bff, 0xc600, 0x21, 0 + .dw 0x3c40, 0xc600, 0x3dff, 0xc600, 0x21, 0 + .dw 0x3e40, 0xc600, 0x3fff, 0xc600, 0x21, 0 + .dw 0x4040, 0xc600, 0x41ff, 0xc600, 0x21, 0 + .dw 0x4240, 0xc600, 0x43ff, 0xc600, 0x21, 0 + .dw 0x4440, 0xc600, 0x45ff, 0xc600, 0x21, 0 + .dw 0x4640, 0xc600, 0x47ff, 0xc600, 0x21, 0 + .dw 0x4840, 0xc600, 0x49ff, 0xc600, 0x21, 0 + .dw 0x4a40, 0xc600, 0x4bff, 0xc600, 0x21, 0 + .dw 0x4c40, 0xc600, 0x4dff, 0xc600, 0x21, 0 + .dw 0x4e40, 0xc600, 0x4fff, 0xc600, 0x21, 0 + .dw 0x5040, 0xc600, 0x51ff, 0xc600, 0x21, 0 + .dw 0x5240, 0xc600, 0x53ff, 0xc600, 0x21, 0 + .dw 0x5440, 0xc600, 0x55ff, 0xc600, 0x21, 0 + .dw 0x5640, 0xc600, 0x57ff, 0xc600, 0x21, 0 + .dw 0x5840, 0xc600, 0x59ff, 0xc600, 0x21, 0 + .dw 0x5a40, 0xc600, 0x5bff, 0xc600, 0x21, 0 + .dw 0x5c40, 0xc600, 0x5dff, 0xc600, 0x21, 0 + .dw 0x5e40, 0xc600, 0x5fff, 0xc600, 0x21, 0 + .dw 0x6040, 0xc600, 0x61ff, 0xc600, 0x21, 0 + .dw 0x6240, 0xc600, 0x63ff, 0xc600, 0x21, 0 + .dw 0x6440, 0xc600, 0x65ff, 0xc600, 0x21, 0 + .dw 0x6640, 0xc600, 0x67ff, 0xc600, 0x21, 0 + .dw 0x6840, 0xc600, 0x69ff, 0xc600, 0x21, 0 + .dw 0x6a40, 0xc600, 0x6bff, 0xc600, 0x21, 0 + .dw 0x6c40, 0xc600, 0x6dff, 0xc600, 0x21, 0 + .dw 0x6e40, 0xc600, 0x6fff, 0xc600, 0x21, 0 + .dw 0x7040, 0xc600, 0x71ff, 0xc600, 0x21, 0 + .dw 0x7240, 0xc600, 0x73ff, 0xc600, 0x21, 0 + .dw 0x7440, 0xc600, 0x75ff, 0xc600, 0x21, 0 + .dw 0x7640, 0xc600, 0x77ff, 0xc600, 0x21, 0 + .dw 0x7840, 0xc600, 0x79ff, 0xc600, 0x21, 0 + .dw 0x7a40, 0xc600, 0x7bff, 0xc600, 0x21, 0 + .dw 0x7c40, 0xc600, 0x7dff, 0xc600, 0x21, 0 + .dw 0x7e40, 0xc600, 0x7fff, 0xc600, 0x21, 0 + .dw 0x8040, 0xc600, 0x81ff, 0xc600, 0x21, 0 + .dw 0x8240, 0xc600, 0x83ff, 0xc600, 0x21, 0 + .dw 0x8440, 0xc600, 0x85ff, 0xc600, 0x21, 0 + .dw 0x8640, 0xc600, 0x87ff, 0xc600, 0x21, 0 + .dw 0x8840, 0xc600, 0x89ff, 0xc600, 0x21, 0 + .dw 0x8a40, 0xc600, 0x8bff, 0xc600, 0x21, 0 + .dw 0x8c40, 0xc600, 0x8dff, 0xc600, 0x21, 0 + .dw 0x8e40, 0xc600, 0x8fff, 0xc600, 0x21, 0 + .dw 0x9040, 0xc600, 0x91ff, 0xc600, 0x21, 0 + .dw 0x9240, 0xc600, 0x93ff, 0xc600, 0x21, 0 + .dw 0x9440, 0xc600, 0x95ff, 0xc600, 0x21, 0 + .dw 0x9640, 0xc600, 0x97ff, 0xc600, 0x21, 0 + .dw 0x9840, 0xc600, 0x99ff, 0xc600, 0x21, 0 + .dw 0x9a40, 0xc600, 0x9bff, 0xc600, 0x21, 0 + .dw 0x9c40, 0xc600, 0x9dff, 0xc600, 0x21, 0 + .dw 0x9e40, 0xc600, 0x9fff, 0xc600, 0x21, 0 + .dw 0xa040, 0xc600, 0xa1ff, 0xc600, 0x21, 0 + .dw 0xa240, 0xc600, 0xa3ff, 0xc600, 0x21, 0 + .dw 0xa440, 0xc600, 0xa5ff, 0xc600, 0x21, 0 + .dw 0xa640, 0xc600, 0xa7ff, 0xc600, 0x21, 0 + .dw 0xa840, 0xc600, 0xa9ff, 0xc600, 0x21, 0 + .dw 0xaa40, 0xc600, 0xabff, 0xc600, 0x21, 0 + .dw 0xac40, 0xc600, 0xadff, 0xc600, 0x21, 0 + .dw 0xae40, 0xc600, 0xafff, 0xc600, 0x21, 0 + .dw 0xb040, 0xc600, 0xb1ff, 0xc600, 0x21, 0 + .dw 0xb240, 0xc600, 0xb3ff, 0xc600, 0x21, 0 + .dw 0xb440, 0xc600, 0xb5ff, 0xc600, 0x21, 0 + .dw 0xb640, 0xc600, 0xb7ff, 0xc600, 0x21, 0 + .dw 0xb840, 0xc600, 0xb9ff, 0xc600, 0x21, 0 + .dw 0xba40, 0xc600, 0xbbff, 0xc600, 0x21, 0 + .dw 0xbc40, 0xc600, 0xbdff, 0xc600, 0x21, 0 + .dw 0xbe40, 0xc600, 0xffff, 0xc600, 0x21, 0 + .dw 0x0040, 0xc601, 0x01ff, 0xc601, 0x21, 0 + .dw 0x0240, 0xc601, 0x03ff, 0xc601, 0x21, 0 + .dw 0x0440, 0xc601, 0x05ff, 0xc601, 0x21, 0 + .dw 0x0640, 0xc601, 0x07ff, 0xc601, 0x21, 0 + .dw 0x0840, 0xc601, 0x09ff, 0xc601, 0x21, 0 + .dw 0x0a40, 0xc601, 0x0bff, 0xc601, 0x21, 0 + .dw 0x0c40, 0xc601, 0x0dff, 0xc601, 0x21, 0 + .dw 0x0e40, 0xc601, 0x3fff, 0xc601, 0x21, 0 + .dw 0x4040, 0xc601, 0x41ff, 0xc601, 0x21, 0 + .dw 0x4240, 0xc601, 0x43ff, 0xc601, 0x21, 0 + .dw 0x4440, 0xc601, 0x45ff, 0xc601, 0x21, 0 + .dw 0x4640, 0xc601, 0x47ff, 0xc601, 0x21, 0 + .dw 0x4840, 0xc601, 0x49ff, 0xc601, 0x21, 0 + .dw 0x4a40, 0xc601, 0x4bff, 0xc601, 0x21, 0 + .dw 0x4c40, 0xc601, 0x4dff, 0xc601, 0x21, 0 + .dw 0x4e40, 0xc601, 0x7fff, 0xc601, 0x21, 0 + .dw 0x8040, 0xc601, 0x81ff, 0xc601, 0x21, 0 + .dw 0x8240, 0xc601, 0x83ff, 0xc601, 0x21, 0 + .dw 0x8440, 0xc601, 0x85ff, 0xc601, 0x21, 0 + .dw 0x8640, 0xc601, 0x87ff, 0xc601, 0x21, 0 + .dw 0x8840, 0xc601, 0x89ff, 0xc601, 0x21, 0 + .dw 0x8a40, 0xc601, 0x8bff, 0xc601, 0x21, 0 + .dw 0x8c40, 0xc601, 0x8dff, 0xc601, 0x21, 0 + .dw 0x8e40, 0xc601, 0xffff, 0xc601, 0x21, 0 + .dw 0x0040, 0xc602, 0x01ff, 0xc602, 0x21, 0 + .dw 0x0240, 0xc602, 0x03ff, 0xc602, 0x21, 0 + .dw 0x0440, 0xc602, 0x05ff, 0xc602, 0x21, 0 + .dw 0x0640, 0xc602, 0x07ff, 0xc602, 0x21, 0 + .dw 0x0840, 0xc602, 0x09ff, 0xc602, 0x21, 0 + .dw 0x0a40, 0xc602, 0x0bff, 0xc602, 0x21, 0 + .dw 0x0c40, 0xc602, 0x0dff, 0xc602, 0x21, 0 + .dw 0x0e40, 0xc602, 0x3fff, 0xc602, 0x21, 0 + .dw 0x4040, 0xc602, 0x41ff, 0xc602, 0x21, 0 + .dw 0x4240, 0xc602, 0x43ff, 0xc602, 0x21, 0 + .dw 0x4440, 0xc602, 0x45ff, 0xc602, 0x21, 0 + .dw 0x4640, 0xc602, 0x47ff, 0xc602, 0x21, 0 + .dw 0x4840, 0xc602, 0x49ff, 0xc602, 0x21, 0 + .dw 0x4a40, 0xc602, 0x4bff, 0xc602, 0x21, 0 + .dw 0x4c40, 0xc602, 0x4dff, 0xc602, 0x21, 0 + .dw 0x4e40, 0xc602, 0x7fff, 0xc602, 0x21, 0 + .dw 0x8040, 0xc602, 0x81ff, 0xc602, 0x21, 0 + .dw 0x8240, 0xc602, 0x83ff, 0xc602, 0x21, 0 + .dw 0x8440, 0xc602, 0x85ff, 0xc602, 0x21, 0 + .dw 0x8640, 0xc602, 0x87ff, 0xc602, 0x21, 0 + .dw 0x8840, 0xc602, 0x89ff, 0xc602, 0x21, 0 + .dw 0x8a40, 0xc602, 0x8bff, 0xc602, 0x21, 0 + .dw 0x8c40, 0xc602, 0x8dff, 0xc602, 0x21, 0 + .dw 0x8e40, 0xc602, 0xbfff, 0xc602, 0x21, 0 + .dw 0xc040, 0xc602, 0xc1ff, 0xc602, 0x21, 0 + .dw 0xc240, 0xc602, 0xc3ff, 0xc602, 0x21, 0 + .dw 0xc440, 0xc602, 0xc5ff, 0xc602, 0x21, 0 + .dw 0xc640, 0xc602, 0xc7ff, 0xc602, 0x21, 0 + .dw 0xc840, 0xc602, 0xc9ff, 0xc602, 0x21, 0 + .dw 0xca40, 0xc602, 0xcbff, 0xc602, 0x21, 0 + .dw 0xcc40, 0xc602, 0xcdff, 0xc602, 0x21, 0 + .dw 0xce40, 0xc602, 0xffff, 0xc602, 0x21, 0 + .dw 0x0040, 0xc603, 0x01ff, 0xc603, 0x21, 0 + .dw 0x0240, 0xc603, 0x03ff, 0xc603, 0x21, 0 + .dw 0x0440, 0xc603, 0x05ff, 0xc603, 0x21, 0 + .dw 0x0640, 0xc603, 0x07ff, 0xc603, 0x21, 0 + .dw 0x0840, 0xc603, 0x09ff, 0xc603, 0x21, 0 + .dw 0x0a40, 0xc603, 0x0bff, 0xc603, 0x21, 0 + .dw 0x0c40, 0xc603, 0x0dff, 0xc603, 0x21, 0 + .dw 0x0e40, 0xc603, 0x0fff, 0xc603, 0x21, 0 + .dw 0x1040, 0xc603, 0x11ff, 0xc603, 0x21, 0 + .dw 0x1240, 0xc603, 0x13ff, 0xc603, 0x21, 0 + .dw 0x1440, 0xc603, 0x15ff, 0xc603, 0x21, 0 + .dw 0x1640, 0xc603, 0x17ff, 0xc603, 0x21, 0 + .dw 0x1840, 0xc603, 0x19ff, 0xc603, 0x21, 0 + .dw 0x1a40, 0xc603, 0x1bff, 0xc603, 0x21, 0 + .dw 0x1c40, 0xc603, 0x1dff, 0xc603, 0x21, 0 + .dw 0x1e40, 0xc603, 0x3fff, 0xc603, 0x21, 0 + .dw 0x4040, 0xc603, 0x41ff, 0xc603, 0x21, 0 + .dw 0x4240, 0xc603, 0x43ff, 0xc603, 0x21, 0 + .dw 0x4440, 0xc603, 0x45ff, 0xc603, 0x21, 0 + .dw 0x4640, 0xc603, 0x47ff, 0xc603, 0x21, 0 + .dw 0x4840, 0xc603, 0x49ff, 0xc603, 0x21, 0 + .dw 0x4a40, 0xc603, 0x4bff, 0xc603, 0x21, 0 + .dw 0x4c40, 0xc603, 0x4dff, 0xc603, 0x21, 0 + .dw 0x4e40, 0xc603, 0x4fff, 0xc603, 0x21, 0 + .dw 0x5040, 0xc603, 0x51ff, 0xc603, 0x21, 0 + .dw 0x5240, 0xc603, 0x53ff, 0xc603, 0x21, 0 + .dw 0x5440, 0xc603, 0x55ff, 0xc603, 0x21, 0 + .dw 0x5640, 0xc603, 0x57ff, 0xc603, 0x21, 0 + .dw 0x5840, 0xc603, 0x59ff, 0xc603, 0x21, 0 + .dw 0x5a40, 0xc603, 0x5bff, 0xc603, 0x21, 0 + .dw 0x5c40, 0xc603, 0x5dff, 0xc603, 0x21, 0 + .dw 0x5e40, 0xc603, 0x7fff, 0xc603, 0x21, 0 + .dw 0x8040, 0xc603, 0x81ff, 0xc603, 0x21, 0 + .dw 0x8240, 0xc603, 0x83ff, 0xc603, 0x21, 0 + .dw 0x8440, 0xc603, 0x85ff, 0xc603, 0x21, 0 + .dw 0x8640, 0xc603, 0x87ff, 0xc603, 0x21, 0 + .dw 0x8840, 0xc603, 0x89ff, 0xc603, 0x21, 0 + .dw 0x8a40, 0xc603, 0x8bff, 0xc603, 0x21, 0 + .dw 0x8c40, 0xc603, 0x8dff, 0xc603, 0x21, 0 + .dw 0x8e40, 0xc603, 0x8fff, 0xc603, 0x21, 0 + .dw 0x9040, 0xc603, 0x91ff, 0xc603, 0x21, 0 + .dw 0x9240, 0xc603, 0x93ff, 0xc603, 0x21, 0 + .dw 0x9440, 0xc603, 0x95ff, 0xc603, 0x21, 0 + .dw 0x9640, 0xc603, 0x97ff, 0xc603, 0x21, 0 + .dw 0x9840, 0xc603, 0x99ff, 0xc603, 0x21, 0 + .dw 0x9a40, 0xc603, 0x9bff, 0xc603, 0x21, 0 + .dw 0x9c40, 0xc603, 0x9dff, 0xc603, 0x21, 0 + .dw 0x9e40, 0xc603, 0xffff, 0xc603, 0x21, 0 + .dw 0x0040, 0xc604, 0x01ff, 0xc604, 0x21, 0 + .dw 0x0240, 0xc604, 0x03ff, 0xc604, 0x21, 0 + .dw 0x0440, 0xc604, 0x05ff, 0xc604, 0x21, 0 + .dw 0x0640, 0xc604, 0x07ff, 0xc604, 0x21, 0 + .dw 0x0840, 0xc604, 0x09ff, 0xc604, 0x21, 0 + .dw 0x0a40, 0xc604, 0x0bff, 0xc604, 0x21, 0 + .dw 0x0c40, 0xc604, 0x0dff, 0xc604, 0x21, 0 + .dw 0x0e40, 0xc604, 0x3fff, 0xc604, 0x21, 0 + .dw 0x4040, 0xc604, 0x41ff, 0xc604, 0x21, 0 + .dw 0x4240, 0xc604, 0x43ff, 0xc604, 0x21, 0 + .dw 0x4440, 0xc604, 0x45ff, 0xc604, 0x21, 0 + .dw 0x4640, 0xc604, 0x47ff, 0xc604, 0x21, 0 + .dw 0x4840, 0xc604, 0x49ff, 0xc604, 0x21, 0 + .dw 0x4a40, 0xc604, 0x4bff, 0xc604, 0x21, 0 + .dw 0x4c40, 0xc604, 0x4dff, 0xc604, 0x21, 0 + .dw 0x4e40, 0xc604, 0x7fff, 0xc604, 0x21, 0 + .dw 0x8040, 0xc604, 0x81ff, 0xc604, 0x21, 0 + .dw 0x8240, 0xc604, 0x83ff, 0xc604, 0x21, 0 + .dw 0x8440, 0xc604, 0x85ff, 0xc604, 0x21, 0 + .dw 0x8640, 0xc604, 0x87ff, 0xc604, 0x21, 0 + .dw 0x8840, 0xc604, 0x89ff, 0xc604, 0x21, 0 + .dw 0x8a40, 0xc604, 0x8bff, 0xc604, 0x21, 0 + .dw 0x8c40, 0xc604, 0x8dff, 0xc604, 0x21, 0 + .dw 0x8e40, 0xc604, 0xbfff, 0xc604, 0x21, 0 + .dw 0xc040, 0xc604, 0xc1ff, 0xc604, 0x21, 0 + .dw 0xc240, 0xc604, 0xc3ff, 0xc604, 0x21, 0 + .dw 0xc440, 0xc604, 0xc5ff, 0xc604, 0x21, 0 + .dw 0xc640, 0xc604, 0xc7ff, 0xc604, 0x21, 0 + .dw 0xc840, 0xc604, 0xc9ff, 0xc604, 0x21, 0 + .dw 0xca40, 0xc604, 0xcbff, 0xc604, 0x21, 0 + .dw 0xcc40, 0xc604, 0xcdff, 0xc604, 0x21, 0 + .dw 0xce40, 0xc604, 0xffff, 0xc604, 0x21, 0 + .dw 0x0040, 0xc605, 0x01ff, 0xc605, 0x21, 0 + .dw 0x0240, 0xc605, 0x03ff, 0xc605, 0x21, 0 + .dw 0x0440, 0xc605, 0x05ff, 0xc605, 0x21, 0 + .dw 0x0640, 0xc605, 0x07ff, 0xc605, 0x21, 0 + .dw 0x0840, 0xc605, 0x09ff, 0xc605, 0x21, 0 + .dw 0x0a40, 0xc605, 0x0bff, 0xc605, 0x21, 0 + .dw 0x0c40, 0xc605, 0x0dff, 0xc605, 0x21, 0 + .dw 0x0e40, 0xc605, 0x3fff, 0xc605, 0x21, 0 + .dw 0x4040, 0xc605, 0x41ff, 0xc605, 0x21, 0 + .dw 0x4240, 0xc605, 0x43ff, 0xc605, 0x21, 0 + .dw 0x4440, 0xc605, 0x45ff, 0xc605, 0x21, 0 + .dw 0x4640, 0xc605, 0x47ff, 0xc605, 0x21, 0 + .dw 0x4840, 0xc605, 0x49ff, 0xc605, 0x21, 0 + .dw 0x4a40, 0xc605, 0x4bff, 0xc605, 0x21, 0 + .dw 0x4c40, 0xc605, 0x4dff, 0xc605, 0x21, 0 + .dw 0x4e40, 0xc605, 0x7fff, 0xc605, 0x21, 0 + .dw 0x8040, 0xc605, 0x81ff, 0xc605, 0x21, 0 + .dw 0x8240, 0xc605, 0x83ff, 0xc605, 0x21, 0 + .dw 0x8440, 0xc605, 0x85ff, 0xc605, 0x21, 0 + .dw 0x8640, 0xc605, 0x87ff, 0xc605, 0x21, 0 + .dw 0x8840, 0xc605, 0x89ff, 0xc605, 0x21, 0 + .dw 0x8a40, 0xc605, 0x8bff, 0xc605, 0x21, 0 + .dw 0x8c40, 0xc605, 0x8dff, 0xc605, 0x21, 0 + .dw 0x8e40, 0xc605, 0xffff, 0xc605, 0x21, 0 + .dw 0x0040, 0xc606, 0x01ff, 0xc606, 0x21, 0 + .dw 0x0240, 0xc606, 0x03ff, 0xc606, 0x21, 0 + .dw 0x0440, 0xc606, 0x05ff, 0xc606, 0x21, 0 + .dw 0x0640, 0xc606, 0x07ff, 0xc606, 0x21, 0 + .dw 0x0840, 0xc606, 0x09ff, 0xc606, 0x21, 0 + .dw 0x0a40, 0xc606, 0x0bff, 0xc606, 0x21, 0 + .dw 0x0c40, 0xc606, 0x0dff, 0xc606, 0x21, 0 + .dw 0x0e40, 0xc606, 0x3fff, 0xc606, 0x21, 0 + .dw 0x4040, 0xc606, 0x41ff, 0xc606, 0x21, 0 + .dw 0x4240, 0xc606, 0x43ff, 0xc606, 0x21, 0 + .dw 0x4440, 0xc606, 0x45ff, 0xc606, 0x21, 0 + .dw 0x4640, 0xc606, 0x47ff, 0xc606, 0x21, 0 + .dw 0x4840, 0xc606, 0x49ff, 0xc606, 0x21, 0 + .dw 0x4a40, 0xc606, 0x4bff, 0xc606, 0x21, 0 + .dw 0x4c40, 0xc606, 0x4dff, 0xc606, 0x21, 0 + .dw 0x4e40, 0xc606, 0xbfff, 0xc606, 0x21, 0 + .dw 0xc040, 0xc606, 0xc1ff, 0xc606, 0x21, 0 + .dw 0xc240, 0xc606, 0xc3ff, 0xc606, 0x21, 0 + .dw 0xc440, 0xc606, 0xc5ff, 0xc606, 0x21, 0 + .dw 0xc640, 0xc606, 0xc7ff, 0xc606, 0x21, 0 + .dw 0xc840, 0xc606, 0xc9ff, 0xc606, 0x21, 0 + .dw 0xca40, 0xc606, 0xcbff, 0xc606, 0x21, 0 + .dw 0xcc40, 0xc606, 0xcdff, 0xc606, 0x21, 0 + .dw 0xce40, 0xc606, 0xffff, 0xc606, 0x21, 0 + .dw 0x0040, 0xc607, 0x01ff, 0xc607, 0x21, 0 + .dw 0x0240, 0xc607, 0x03ff, 0xc607, 0x21, 0 + .dw 0x0440, 0xc607, 0x05ff, 0xc607, 0x21, 0 + .dw 0x0640, 0xc607, 0x07ff, 0xc607, 0x21, 0 + .dw 0x0840, 0xc607, 0x09ff, 0xc607, 0x21, 0 + .dw 0x0a40, 0xc607, 0x0bff, 0xc607, 0x21, 0 + .dw 0x0c40, 0xc607, 0x0dff, 0xc607, 0x21, 0 + .dw 0x0e40, 0xc607, 0x3fff, 0xc607, 0x21, 0 + .dw 0x4040, 0xc607, 0x41ff, 0xc607, 0x21, 0 + .dw 0x4240, 0xc607, 0x43ff, 0xc607, 0x21, 0 + .dw 0x4440, 0xc607, 0x45ff, 0xc607, 0x21, 0 + .dw 0x4640, 0xc607, 0x47ff, 0xc607, 0x21, 0 + .dw 0x4840, 0xc607, 0x49ff, 0xc607, 0x21, 0 + .dw 0x4a40, 0xc607, 0x4bff, 0xc607, 0x21, 0 + .dw 0x4c40, 0xc607, 0x4dff, 0xc607, 0x21, 0 + .dw 0x4e40, 0xc607, 0x7fff, 0xc607, 0x21, 0 + .dw 0x8040, 0xc607, 0x81ff, 0xc607, 0x21, 0 + .dw 0x8240, 0xc607, 0x83ff, 0xc607, 0x21, 0 + .dw 0x8440, 0xc607, 0x85ff, 0xc607, 0x21, 0 + .dw 0x8640, 0xc607, 0x87ff, 0xc607, 0x21, 0 + .dw 0x8840, 0xc607, 0x89ff, 0xc607, 0x21, 0 + .dw 0x8a40, 0xc607, 0x8bff, 0xc607, 0x21, 0 + .dw 0x8c40, 0xc607, 0x8dff, 0xc607, 0x21, 0 + .dw 0x8e40, 0xc607, 0xbfff, 0xc607, 0x21, 0 + .dw 0xc040, 0xc607, 0xc1ff, 0xc607, 0x21, 0 + .dw 0xc240, 0xc607, 0xc3ff, 0xc607, 0x21, 0 + .dw 0xc440, 0xc607, 0xc5ff, 0xc607, 0x21, 0 + .dw 0xc640, 0xc607, 0xc7ff, 0xc607, 0x21, 0 + .dw 0xc840, 0xc607, 0xc9ff, 0xc607, 0x21, 0 + .dw 0xca40, 0xc607, 0xcbff, 0xc607, 0x21, 0 + .dw 0xcc40, 0xc607, 0xcdff, 0xc607, 0x21, 0 + .dw 0xce40, 0xc607, 0xffff, 0xc607, 0x21, 0 + .dw 0x0000, 0xc608, 0x0000, 0xc608, 0x22, 0 + .dw 0x0009, 0xc608, 0x0009, 0xc608, 0x22, 0 + .dw 0x0012, 0xc608, 0x0012, 0xc608, 0x22, 0 + .dw 0x001b, 0xc608, 0x001b, 0xc608, 0x22, 0 + .dw 0x0024, 0xc608, 0x0024, 0xc608, 0x22, 0 + .dw 0x002d, 0xc608, 0x002d, 0xc608, 0x22, 0 + .dw 0x0036, 0xc608, 0x0036, 0xc608, 0x22, 0 + .dw 0x003f, 0xc608, 0x003f, 0xc608, 0x22, 0 + .dw 0x0040, 0xc608, 0x01ff, 0xc608, 0x21, 0 + .dw 0x0200, 0xc608, 0x0200, 0xc608, 0x22, 0 + .dw 0x0209, 0xc608, 0x0209, 0xc608, 0x22, 0 + .dw 0x0212, 0xc608, 0x0212, 0xc608, 0x22, 0 + .dw 0x021b, 0xc608, 0x021b, 0xc608, 0x22, 0 + .dw 0x0224, 0xc608, 0x0224, 0xc608, 0x22, 0 + .dw 0x022d, 0xc608, 0x022d, 0xc608, 0x22, 0 + .dw 0x0236, 0xc608, 0x0236, 0xc608, 0x22, 0 + .dw 0x023f, 0xc608, 0x023f, 0xc608, 0x22, 0 + .dw 0x0240, 0xc608, 0x03ff, 0xc608, 0x21, 0 + .dw 0x0400, 0xc608, 0x0400, 0xc608, 0x22, 0 + .dw 0x0409, 0xc608, 0x0409, 0xc608, 0x22, 0 + .dw 0x0412, 0xc608, 0x0412, 0xc608, 0x22, 0 + .dw 0x041b, 0xc608, 0x041b, 0xc608, 0x22, 0 + .dw 0x0424, 0xc608, 0x0424, 0xc608, 0x22, 0 + .dw 0x042d, 0xc608, 0x042d, 0xc608, 0x22, 0 + .dw 0x0436, 0xc608, 0x0436, 0xc608, 0x22, 0 + .dw 0x043f, 0xc608, 0x043f, 0xc608, 0x22, 0 + .dw 0x0440, 0xc608, 0x05ff, 0xc608, 0x21, 0 + .dw 0x0600, 0xc608, 0x0600, 0xc608, 0x22, 0 + .dw 0x0609, 0xc608, 0x0609, 0xc608, 0x22, 0 + .dw 0x0612, 0xc608, 0x0612, 0xc608, 0x22, 0 + .dw 0x061b, 0xc608, 0x061b, 0xc608, 0x22, 0 + .dw 0x0624, 0xc608, 0x0624, 0xc608, 0x22, 0 + .dw 0x062d, 0xc608, 0x062d, 0xc608, 0x22, 0 + .dw 0x0636, 0xc608, 0x0636, 0xc608, 0x22, 0 + .dw 0x063f, 0xc608, 0x063f, 0xc608, 0x22, 0 + .dw 0x0640, 0xc608, 0x07ff, 0xc608, 0x21, 0 + .dw 0x0800, 0xc608, 0x0800, 0xc608, 0x22, 0 + .dw 0x0809, 0xc608, 0x0809, 0xc608, 0x22, 0 + .dw 0x0812, 0xc608, 0x0812, 0xc608, 0x22, 0 + .dw 0x081b, 0xc608, 0x081b, 0xc608, 0x22, 0 + .dw 0x0824, 0xc608, 0x0824, 0xc608, 0x22, 0 + .dw 0x082d, 0xc608, 0x082d, 0xc608, 0x22, 0 + .dw 0x0836, 0xc608, 0x0836, 0xc608, 0x22, 0 + .dw 0x083f, 0xc608, 0x083f, 0xc608, 0x22, 0 + .dw 0x0840, 0xc608, 0x09ff, 0xc608, 0x21, 0 + .dw 0x0a00, 0xc608, 0x0a00, 0xc608, 0x22, 0 + .dw 0x0a09, 0xc608, 0x0a09, 0xc608, 0x22, 0 + .dw 0x0a12, 0xc608, 0x0a12, 0xc608, 0x22, 0 + .dw 0x0a1b, 0xc608, 0x0a1b, 0xc608, 0x22, 0 + .dw 0x0a24, 0xc608, 0x0a24, 0xc608, 0x22, 0 + .dw 0x0a2d, 0xc608, 0x0a2d, 0xc608, 0x22, 0 + .dw 0x0a36, 0xc608, 0x0a36, 0xc608, 0x22, 0 + .dw 0x0a3f, 0xc608, 0x0a3f, 0xc608, 0x22, 0 + .dw 0x0a40, 0xc608, 0x0bff, 0xc608, 0x21, 0 + .dw 0x0c00, 0xc608, 0x0c00, 0xc608, 0x22, 0 + .dw 0x0c09, 0xc608, 0x0c09, 0xc608, 0x22, 0 + .dw 0x0c12, 0xc608, 0x0c12, 0xc608, 0x22, 0 + .dw 0x0c1b, 0xc608, 0x0c1b, 0xc608, 0x22, 0 + .dw 0x0c24, 0xc608, 0x0c24, 0xc608, 0x22, 0 + .dw 0x0c2d, 0xc608, 0x0c2d, 0xc608, 0x22, 0 + .dw 0x0c36, 0xc608, 0x0c36, 0xc608, 0x22, 0 + .dw 0x0c3f, 0xc608, 0x0c3f, 0xc608, 0x22, 0 + .dw 0x0c40, 0xc608, 0x0dff, 0xc608, 0x21, 0 + .dw 0x0e00, 0xc608, 0x0e00, 0xc608, 0x22, 0 + .dw 0x0e09, 0xc608, 0x0e09, 0xc608, 0x22, 0 + .dw 0x0e12, 0xc608, 0x0e12, 0xc608, 0x22, 0 + .dw 0x0e1b, 0xc608, 0x0e1b, 0xc608, 0x22, 0 + .dw 0x0e24, 0xc608, 0x0e24, 0xc608, 0x22, 0 + .dw 0x0e2d, 0xc608, 0x0e2d, 0xc608, 0x22, 0 + .dw 0x0e36, 0xc608, 0x0e36, 0xc608, 0x22, 0 + .dw 0x0e3f, 0xc608, 0x0e3f, 0xc608, 0x22, 0 + .dw 0x0e40, 0xc608, 0x3fff, 0xc608, 0x21, 0 + .dw 0x4000, 0xc608, 0x4000, 0xc608, 0x22, 0 + .dw 0x4009, 0xc608, 0x4009, 0xc608, 0x22, 0 + .dw 0x4012, 0xc608, 0x4012, 0xc608, 0x22, 0 + .dw 0x401b, 0xc608, 0x401b, 0xc608, 0x22, 0 + .dw 0x4024, 0xc608, 0x4024, 0xc608, 0x22, 0 + .dw 0x402d, 0xc608, 0x402d, 0xc608, 0x22, 0 + .dw 0x4036, 0xc608, 0x4036, 0xc608, 0x22, 0 + .dw 0x403f, 0xc608, 0x403f, 0xc608, 0x22, 0 + .dw 0x4040, 0xc608, 0x41ff, 0xc608, 0x21, 0 + .dw 0x4200, 0xc608, 0x4200, 0xc608, 0x22, 0 + .dw 0x4209, 0xc608, 0x4209, 0xc608, 0x22, 0 + .dw 0x4212, 0xc608, 0x4212, 0xc608, 0x22, 0 + .dw 0x421b, 0xc608, 0x421b, 0xc608, 0x22, 0 + .dw 0x4224, 0xc608, 0x4224, 0xc608, 0x22, 0 + .dw 0x422d, 0xc608, 0x422d, 0xc608, 0x22, 0 + .dw 0x4236, 0xc608, 0x4236, 0xc608, 0x22, 0 + .dw 0x423f, 0xc608, 0x423f, 0xc608, 0x22, 0 + .dw 0x4240, 0xc608, 0x43ff, 0xc608, 0x21, 0 + .dw 0x4400, 0xc608, 0x4400, 0xc608, 0x22, 0 + .dw 0x4409, 0xc608, 0x4409, 0xc608, 0x22, 0 + .dw 0x4412, 0xc608, 0x4412, 0xc608, 0x22, 0 + .dw 0x441b, 0xc608, 0x441b, 0xc608, 0x22, 0 + .dw 0x4424, 0xc608, 0x4424, 0xc608, 0x22, 0 + .dw 0x442d, 0xc608, 0x442d, 0xc608, 0x22, 0 + .dw 0x4436, 0xc608, 0x4436, 0xc608, 0x22, 0 + .dw 0x443f, 0xc608, 0x443f, 0xc608, 0x22, 0 + .dw 0x4440, 0xc608, 0x45ff, 0xc608, 0x21, 0 + .dw 0x4600, 0xc608, 0x4600, 0xc608, 0x22, 0 + .dw 0x4609, 0xc608, 0x4609, 0xc608, 0x22, 0 + .dw 0x4612, 0xc608, 0x4612, 0xc608, 0x22, 0 + .dw 0x461b, 0xc608, 0x461b, 0xc608, 0x22, 0 + .dw 0x4624, 0xc608, 0x4624, 0xc608, 0x22, 0 + .dw 0x462d, 0xc608, 0x462d, 0xc608, 0x22, 0 + .dw 0x4636, 0xc608, 0x4636, 0xc608, 0x22, 0 + .dw 0x463f, 0xc608, 0x463f, 0xc608, 0x22, 0 + .dw 0x4640, 0xc608, 0x47ff, 0xc608, 0x21, 0 + .dw 0x4800, 0xc608, 0x4800, 0xc608, 0x22, 0 + .dw 0x4809, 0xc608, 0x4809, 0xc608, 0x22, 0 + .dw 0x4812, 0xc608, 0x4812, 0xc608, 0x22, 0 + .dw 0x481b, 0xc608, 0x481b, 0xc608, 0x22, 0 + .dw 0x4824, 0xc608, 0x4824, 0xc608, 0x22, 0 + .dw 0x482d, 0xc608, 0x482d, 0xc608, 0x22, 0 + .dw 0x4836, 0xc608, 0x4836, 0xc608, 0x22, 0 + .dw 0x483f, 0xc608, 0x483f, 0xc608, 0x22, 0 + .dw 0x4840, 0xc608, 0x49ff, 0xc608, 0x21, 0 + .dw 0x4a00, 0xc608, 0x4a00, 0xc608, 0x22, 0 + .dw 0x4a09, 0xc608, 0x4a09, 0xc608, 0x22, 0 + .dw 0x4a12, 0xc608, 0x4a12, 0xc608, 0x22, 0 + .dw 0x4a1b, 0xc608, 0x4a1b, 0xc608, 0x22, 0 + .dw 0x4a24, 0xc608, 0x4a24, 0xc608, 0x22, 0 + .dw 0x4a2d, 0xc608, 0x4a2d, 0xc608, 0x22, 0 + .dw 0x4a36, 0xc608, 0x4a36, 0xc608, 0x22, 0 + .dw 0x4a3f, 0xc608, 0x4a3f, 0xc608, 0x22, 0 + .dw 0x4a40, 0xc608, 0x4bff, 0xc608, 0x21, 0 + .dw 0x4c00, 0xc608, 0x4c00, 0xc608, 0x22, 0 + .dw 0x4c09, 0xc608, 0x4c09, 0xc608, 0x22, 0 + .dw 0x4c12, 0xc608, 0x4c12, 0xc608, 0x22, 0 + .dw 0x4c1b, 0xc608, 0x4c1b, 0xc608, 0x22, 0 + .dw 0x4c24, 0xc608, 0x4c24, 0xc608, 0x22, 0 + .dw 0x4c2d, 0xc608, 0x4c2d, 0xc608, 0x22, 0 + .dw 0x4c36, 0xc608, 0x4c36, 0xc608, 0x22, 0 + .dw 0x4c3f, 0xc608, 0x4c3f, 0xc608, 0x22, 0 + .dw 0x4c40, 0xc608, 0x4dff, 0xc608, 0x21, 0 + .dw 0x4e00, 0xc608, 0x4e00, 0xc608, 0x22, 0 + .dw 0x4e09, 0xc608, 0x4e09, 0xc608, 0x22, 0 + .dw 0x4e12, 0xc608, 0x4e12, 0xc608, 0x22, 0 + .dw 0x4e1b, 0xc608, 0x4e1b, 0xc608, 0x22, 0 + .dw 0x4e24, 0xc608, 0x4e24, 0xc608, 0x22, 0 + .dw 0x4e2d, 0xc608, 0x4e2d, 0xc608, 0x22, 0 + .dw 0x4e36, 0xc608, 0x4e36, 0xc608, 0x22, 0 + .dw 0x4e3f, 0xc608, 0x4e3f, 0xc608, 0x22, 0 + .dw 0x4e40, 0xc608, 0xffff, 0xc608, 0x21, 0 + .dw 0x0040, 0xc609, 0x01ff, 0xc609, 0x21, 0 + .dw 0x0240, 0xc609, 0x03ff, 0xc609, 0x21, 0 + .dw 0x0440, 0xc609, 0x05ff, 0xc609, 0x21, 0 + .dw 0x0640, 0xc609, 0x07ff, 0xc609, 0x21, 0 + .dw 0x0840, 0xc609, 0x09ff, 0xc609, 0x21, 0 + .dw 0x0a40, 0xc609, 0x0bff, 0xc609, 0x21, 0 + .dw 0x0c40, 0xc609, 0x0dff, 0xc609, 0x21, 0 + .dw 0x0e40, 0xc609, 0x3fff, 0xc609, 0x21, 0 + .dw 0x4040, 0xc609, 0x41ff, 0xc609, 0x21, 0 + .dw 0x4240, 0xc609, 0x43ff, 0xc609, 0x21, 0 + .dw 0x4440, 0xc609, 0x45ff, 0xc609, 0x21, 0 + .dw 0x4640, 0xc609, 0x47ff, 0xc609, 0x21, 0 + .dw 0x4840, 0xc609, 0x49ff, 0xc609, 0x21, 0 + .dw 0x4a40, 0xc609, 0x4bff, 0xc609, 0x21, 0 + .dw 0x4c40, 0xc609, 0x4dff, 0xc609, 0x21, 0 + .dw 0x4e40, 0xc609, 0x7fff, 0xc609, 0x21, 0 + .dw 0x8040, 0xc609, 0x81ff, 0xc609, 0x21, 0 + .dw 0x8240, 0xc609, 0x83ff, 0xc609, 0x21, 0 + .dw 0x8440, 0xc609, 0x85ff, 0xc609, 0x21, 0 + .dw 0x8640, 0xc609, 0x87ff, 0xc609, 0x21, 0 + .dw 0x8840, 0xc609, 0x89ff, 0xc609, 0x21, 0 + .dw 0x8a40, 0xc609, 0x8bff, 0xc609, 0x21, 0 + .dw 0x8c40, 0xc609, 0x8dff, 0xc609, 0x21, 0 + .dw 0x8e40, 0xc609, 0xbfff, 0xc609, 0x21, 0 + .dw 0xc040, 0xc609, 0xc1ff, 0xc609, 0x21, 0 + .dw 0xc240, 0xc609, 0xc3ff, 0xc609, 0x21, 0 + .dw 0xc440, 0xc609, 0xc5ff, 0xc609, 0x21, 0 + .dw 0xc640, 0xc609, 0xc7ff, 0xc609, 0x21, 0 + .dw 0xc840, 0xc609, 0xc9ff, 0xc609, 0x21, 0 + .dw 0xca40, 0xc609, 0xcbff, 0xc609, 0x21, 0 + .dw 0xcc40, 0xc609, 0xcdff, 0xc609, 0x21, 0 + .dw 0xce40, 0xc609, 0xffff, 0xc609, 0x21, 0 + .dw 0x0040, 0xc60a, 0x01ff, 0xc60a, 0x21, 0 + .dw 0x0240, 0xc60a, 0x03ff, 0xc60a, 0x21, 0 + .dw 0x0440, 0xc60a, 0x05ff, 0xc60a, 0x21, 0 + .dw 0x0640, 0xc60a, 0x07ff, 0xc60a, 0x21, 0 + .dw 0x0840, 0xc60a, 0x09ff, 0xc60a, 0x21, 0 + .dw 0x0a40, 0xc60a, 0x0bff, 0xc60a, 0x21, 0 + .dw 0x0c40, 0xc60a, 0x0dff, 0xc60a, 0x21, 0 + .dw 0x0e40, 0xc60a, 0x3fff, 0xc60a, 0x21, 0 + .dw 0x4040, 0xc60a, 0x41ff, 0xc60a, 0x21, 0 + .dw 0x4240, 0xc60a, 0x43ff, 0xc60a, 0x21, 0 + .dw 0x4440, 0xc60a, 0x45ff, 0xc60a, 0x21, 0 + .dw 0x4640, 0xc60a, 0x47ff, 0xc60a, 0x21, 0 + .dw 0x4840, 0xc60a, 0x49ff, 0xc60a, 0x21, 0 + .dw 0x4a40, 0xc60a, 0x4bff, 0xc60a, 0x21, 0 + .dw 0x4c40, 0xc60a, 0x4dff, 0xc60a, 0x21, 0 + .dw 0x4e40, 0xc60a, 0x7fff, 0xc60a, 0x21, 0 + .dw 0x8040, 0xc60a, 0x81ff, 0xc60a, 0x21, 0 + .dw 0x8240, 0xc60a, 0x83ff, 0xc60a, 0x21, 0 + .dw 0x8440, 0xc60a, 0x85ff, 0xc60a, 0x21, 0 + .dw 0x8640, 0xc60a, 0x87ff, 0xc60a, 0x21, 0 + .dw 0x8840, 0xc60a, 0x89ff, 0xc60a, 0x21, 0 + .dw 0x8a40, 0xc60a, 0x8bff, 0xc60a, 0x21, 0 + .dw 0x8c40, 0xc60a, 0x8dff, 0xc60a, 0x21, 0 + .dw 0x8e40, 0xc60a, 0xbfff, 0xc60a, 0x21, 0 + .dw 0xc040, 0xc60a, 0xc1ff, 0xc60a, 0x21, 0 + .dw 0xc240, 0xc60a, 0xc3ff, 0xc60a, 0x21, 0 + .dw 0xc440, 0xc60a, 0xc5ff, 0xc60a, 0x21, 0 + .dw 0xc640, 0xc60a, 0xc7ff, 0xc60a, 0x21, 0 + .dw 0xc840, 0xc60a, 0xc9ff, 0xc60a, 0x21, 0 + .dw 0xca40, 0xc60a, 0xcbff, 0xc60a, 0x21, 0 + .dw 0xcc40, 0xc60a, 0xcdff, 0xc60a, 0x21, 0 + .dw 0xce40, 0xc60a, 0xffff, 0xc60a, 0x21, 0 + .dw 0x0040, 0xc60b, 0x01ff, 0xc60b, 0x21, 0 + .dw 0x0240, 0xc60b, 0x03ff, 0xc60b, 0x21, 0 + .dw 0x0440, 0xc60b, 0x05ff, 0xc60b, 0x21, 0 + .dw 0x0640, 0xc60b, 0x07ff, 0xc60b, 0x21, 0 + .dw 0x0840, 0xc60b, 0x09ff, 0xc60b, 0x21, 0 + .dw 0x0a40, 0xc60b, 0x0bff, 0xc60b, 0x21, 0 + .dw 0x0c40, 0xc60b, 0x0dff, 0xc60b, 0x21, 0 + .dw 0x0e40, 0xc60b, 0x3fff, 0xc60b, 0x21, 0 + .dw 0x4040, 0xc60b, 0x41ff, 0xc60b, 0x21, 0 + .dw 0x4240, 0xc60b, 0x43ff, 0xc60b, 0x21, 0 + .dw 0x4440, 0xc60b, 0x45ff, 0xc60b, 0x21, 0 + .dw 0x4640, 0xc60b, 0x47ff, 0xc60b, 0x21, 0 + .dw 0x4840, 0xc60b, 0x49ff, 0xc60b, 0x21, 0 + .dw 0x4a40, 0xc60b, 0x4bff, 0xc60b, 0x21, 0 + .dw 0x4c40, 0xc60b, 0x4dff, 0xc60b, 0x21, 0 + .dw 0x4e40, 0xc60b, 0xffff, 0xc60b, 0x21, 0 + .dw 0x0040, 0xc60c, 0x01ff, 0xc60c, 0x21, 0 + .dw 0x0240, 0xc60c, 0x03ff, 0xc60c, 0x21, 0 + .dw 0x0440, 0xc60c, 0x05ff, 0xc60c, 0x21, 0 + .dw 0x0640, 0xc60c, 0x07ff, 0xc60c, 0x21, 0 + .dw 0x0840, 0xc60c, 0x09ff, 0xc60c, 0x21, 0 + .dw 0x0a40, 0xc60c, 0x0bff, 0xc60c, 0x21, 0 + .dw 0x0c40, 0xc60c, 0x0dff, 0xc60c, 0x21, 0 + .dw 0x0e40, 0xc60c, 0x3fff, 0xc60c, 0x21, 0 + .dw 0x4040, 0xc60c, 0x41ff, 0xc60c, 0x21, 0 + .dw 0x4240, 0xc60c, 0x43ff, 0xc60c, 0x21, 0 + .dw 0x4440, 0xc60c, 0x45ff, 0xc60c, 0x21, 0 + .dw 0x4640, 0xc60c, 0x47ff, 0xc60c, 0x21, 0 + .dw 0x4840, 0xc60c, 0x49ff, 0xc60c, 0x21, 0 + .dw 0x4a40, 0xc60c, 0x4bff, 0xc60c, 0x21, 0 + .dw 0x4c40, 0xc60c, 0x4dff, 0xc60c, 0x21, 0 + .dw 0x4e40, 0xc60c, 0xffff, 0xc60c, 0x21, 0 + .dw 0x0040, 0xc60d, 0x01ff, 0xc60d, 0x21, 0 + .dw 0x0240, 0xc60d, 0x03ff, 0xc60d, 0x21, 0 + .dw 0x0440, 0xc60d, 0x05ff, 0xc60d, 0x21, 0 + .dw 0x0640, 0xc60d, 0x07ff, 0xc60d, 0x21, 0 + .dw 0x0840, 0xc60d, 0x09ff, 0xc60d, 0x21, 0 + .dw 0x0a40, 0xc60d, 0x0bff, 0xc60d, 0x21, 0 + .dw 0x0c40, 0xc60d, 0x0dff, 0xc60d, 0x21, 0 + .dw 0x0e40, 0xc60d, 0x3fff, 0xc60d, 0x21, 0 + .dw 0x4040, 0xc60d, 0x41ff, 0xc60d, 0x21, 0 + .dw 0x4240, 0xc60d, 0x43ff, 0xc60d, 0x21, 0 + .dw 0x4440, 0xc60d, 0x45ff, 0xc60d, 0x21, 0 + .dw 0x4640, 0xc60d, 0x47ff, 0xc60d, 0x21, 0 + .dw 0x4840, 0xc60d, 0x49ff, 0xc60d, 0x21, 0 + .dw 0x4a40, 0xc60d, 0x4bff, 0xc60d, 0x21, 0 + .dw 0x4c40, 0xc60d, 0x4dff, 0xc60d, 0x21, 0 + .dw 0x4e40, 0xc60d, 0x7fff, 0xc60d, 0x21, 0 + .dw 0x8040, 0xc60d, 0x81ff, 0xc60d, 0x21, 0 + .dw 0x8240, 0xc60d, 0x83ff, 0xc60d, 0x21, 0 + .dw 0x8440, 0xc60d, 0x85ff, 0xc60d, 0x21, 0 + .dw 0x8640, 0xc60d, 0x87ff, 0xc60d, 0x21, 0 + .dw 0x8840, 0xc60d, 0x89ff, 0xc60d, 0x21, 0 + .dw 0x8a40, 0xc60d, 0x8bff, 0xc60d, 0x21, 0 + .dw 0x8c40, 0xc60d, 0x8dff, 0xc60d, 0x21, 0 + .dw 0x8e40, 0xc60d, 0xffff, 0xc67f, 0x21, 0 + .dw 0xc000, 0xc680, 0xffff, 0xc680, 0x21, 0 + .dw 0x1000, 0xc681, 0x3fff, 0xc681, 0x21, 0 + .dw 0x5000, 0xc681, 0x7fff, 0xc681, 0x21, 0 + .dw 0x9000, 0xc681, 0xffff, 0xc681, 0x21, 0 + .dw 0x1000, 0xc682, 0x3fff, 0xc682, 0x21, 0 + .dw 0x5000, 0xc682, 0x7fff, 0xc682, 0x21, 0 + .dw 0x9000, 0xc682, 0xbfff, 0xc682, 0x21, 0 + .dw 0xd000, 0xc682, 0xffff, 0xc682, 0x21, 0 + .dw 0x2000, 0xc683, 0x3fff, 0xc683, 0x21, 0 + .dw 0x6000, 0xc683, 0x7fff, 0xc683, 0x21, 0 + .dw 0xa000, 0xc683, 0xffff, 0xe07f, 0x21, 0 + .dw 0x0400, 0xe080, 0x0fff, 0xe080, 0x21, 0 + .dw 0x1400, 0xe080, 0x1fff, 0xe080, 0x21, 0 + .dw 0x2400, 0xe080, 0x2fff, 0xe080, 0x21, 0 + .dw 0x3400, 0xe080, 0x3fff, 0xe080, 0x21, 0 + .dw 0x4400, 0xe080, 0x4fff, 0xe080, 0x21, 0 + .dw 0x5400, 0xe080, 0x5fff, 0xe080, 0x21, 0 + .dw 0x6400, 0xe080, 0x6fff, 0xe080, 0x21, 0 + .dw 0x7400, 0xe080, 0xffff, 0xe080, 0x21, 0 + .dw 0x0400, 0xe081, 0x0fff, 0xe081, 0x21, 0 + .dw 0x1400, 0xe081, 0x1fff, 0xe081, 0x21, 0 + .dw 0x2400, 0xe081, 0x2fff, 0xe081, 0x21, 0 + .dw 0x3400, 0xe081, 0x3fff, 0xe081, 0x21, 0 + .dw 0x4400, 0xe081, 0x4fff, 0xe081, 0x21, 0 + .dw 0x5400, 0xe081, 0x5fff, 0xe081, 0x21, 0 + .dw 0x6400, 0xe081, 0x6fff, 0xe081, 0x21, 0 + .dw 0x7400, 0xe081, 0xffff, 0xe081, 0x21, 0 + .dw 0x0400, 0xe082, 0x0fff, 0xe082, 0x21, 0 + .dw 0x1400, 0xe082, 0x1fff, 0xe082, 0x21, 0 + .dw 0x2400, 0xe082, 0x2fff, 0xe082, 0x21, 0 + .dw 0x3400, 0xe082, 0x3fff, 0xe082, 0x21, 0 + .dw 0x4400, 0xe082, 0x4fff, 0xe082, 0x21, 0 + .dw 0x5400, 0xe082, 0x5fff, 0xe082, 0x21, 0 + .dw 0x6400, 0xe082, 0x6fff, 0xe082, 0x21, 0 + .dw 0x7400, 0xe082, 0xffff, 0xe082, 0x21, 0 + .dw 0x0400, 0xe083, 0x0fff, 0xe083, 0x21, 0 + .dw 0x1400, 0xe083, 0x1fff, 0xe083, 0x21, 0 + .dw 0x2400, 0xe083, 0x2fff, 0xe083, 0x21, 0 + .dw 0x3400, 0xe083, 0x3fff, 0xe083, 0x21, 0 + .dw 0x4400, 0xe083, 0x4fff, 0xe083, 0x21, 0 + .dw 0x5400, 0xe083, 0x5fff, 0xe083, 0x21, 0 + .dw 0x6400, 0xe083, 0x6fff, 0xe083, 0x21, 0 + .dw 0x7400, 0xe083, 0xffff, 0xe083, 0x21, 0 + .dw 0x0400, 0xe084, 0x0fff, 0xe084, 0x21, 0 + .dw 0x1400, 0xe084, 0x1fff, 0xe084, 0x21, 0 + .dw 0x2400, 0xe084, 0x2fff, 0xe084, 0x21, 0 + .dw 0x3400, 0xe084, 0x3fff, 0xe084, 0x21, 0 + .dw 0x4400, 0xe084, 0x4fff, 0xe084, 0x21, 0 + .dw 0x5400, 0xe084, 0x5fff, 0xe084, 0x21, 0 + .dw 0x6400, 0xe084, 0x6fff, 0xe084, 0x21, 0 + .dw 0x7400, 0xe084, 0xffff, 0xe084, 0x21, 0 + .dw 0x0400, 0xe085, 0x0fff, 0xe085, 0x21, 0 + .dw 0x1400, 0xe085, 0x1fff, 0xe085, 0x21, 0 + .dw 0x2400, 0xe085, 0x2fff, 0xe085, 0x21, 0 + .dw 0x3400, 0xe085, 0x3fff, 0xe085, 0x21, 0 + .dw 0x4400, 0xe085, 0x4fff, 0xe085, 0x21, 0 + .dw 0x5400, 0xe085, 0x5fff, 0xe085, 0x21, 0 + .dw 0x6400, 0xe085, 0x6fff, 0xe085, 0x21, 0 + .dw 0x7400, 0xe085, 0xffff, 0xe085, 0x21, 0 + .dw 0x0400, 0xe086, 0x0fff, 0xe086, 0x21, 0 + .dw 0x1400, 0xe086, 0x1fff, 0xe086, 0x21, 0 + .dw 0x2400, 0xe086, 0x2fff, 0xe086, 0x21, 0 + .dw 0x3400, 0xe086, 0x3fff, 0xe086, 0x21, 0 + .dw 0x4400, 0xe086, 0x4fff, 0xe086, 0x21, 0 + .dw 0x5400, 0xe086, 0x5fff, 0xe086, 0x21, 0 + .dw 0x6400, 0xe086, 0x6fff, 0xe086, 0x21, 0 + .dw 0x7400, 0xe086, 0xffff, 0xe086, 0x21, 0 + .dw 0x0400, 0xe087, 0x0fff, 0xe087, 0x21, 0 + .dw 0x1400, 0xe087, 0x1fff, 0xe087, 0x21, 0 + .dw 0x2400, 0xe087, 0x2fff, 0xe087, 0x21, 0 + .dw 0x3400, 0xe087, 0x3fff, 0xe087, 0x21, 0 + .dw 0x4400, 0xe087, 0x4fff, 0xe087, 0x21, 0 + .dw 0x5400, 0xe087, 0x5fff, 0xe087, 0x21, 0 + .dw 0x6400, 0xe087, 0x6fff, 0xe087, 0x21, 0 + .dw 0x7400, 0xe087, 0xffff, 0xe087, 0x21, 0 + .dw 0x0400, 0xe088, 0x0fff, 0xe088, 0x21, 0 + .dw 0x1400, 0xe088, 0x1fff, 0xe088, 0x21, 0 + .dw 0x2400, 0xe088, 0x2fff, 0xe088, 0x21, 0 + .dw 0x3400, 0xe088, 0x3fff, 0xe088, 0x21, 0 + .dw 0x4400, 0xe088, 0x4fff, 0xe088, 0x21, 0 + .dw 0x5400, 0xe088, 0x5fff, 0xe088, 0x21, 0 + .dw 0x6400, 0xe088, 0x6fff, 0xe088, 0x21, 0 + .dw 0x7400, 0xe088, 0xffff, 0xe088, 0x21, 0 + .dw 0x0400, 0xe089, 0x0fff, 0xe089, 0x21, 0 + .dw 0x1400, 0xe089, 0x1fff, 0xe089, 0x21, 0 + .dw 0x2400, 0xe089, 0x2fff, 0xe089, 0x21, 0 + .dw 0x3400, 0xe089, 0x3fff, 0xe089, 0x21, 0 + .dw 0x4400, 0xe089, 0x4fff, 0xe089, 0x21, 0 + .dw 0x5400, 0xe089, 0x5fff, 0xe089, 0x21, 0 + .dw 0x6400, 0xe089, 0x6fff, 0xe089, 0x21, 0 + .dw 0x7400, 0xe089, 0xffff, 0xe089, 0x21, 0 + .dw 0x0400, 0xe08a, 0x0fff, 0xe08a, 0x21, 0 + .dw 0x1400, 0xe08a, 0x1fff, 0xe08a, 0x21, 0 + .dw 0x2400, 0xe08a, 0x2fff, 0xe08a, 0x21, 0 + .dw 0x3400, 0xe08a, 0x3fff, 0xe08a, 0x21, 0 + .dw 0x4400, 0xe08a, 0x4fff, 0xe08a, 0x21, 0 + .dw 0x5400, 0xe08a, 0x5fff, 0xe08a, 0x21, 0 + .dw 0x6400, 0xe08a, 0x6fff, 0xe08a, 0x21, 0 + .dw 0x7400, 0xe08a, 0xffff, 0xe08a, 0x21, 0 + .dw 0x0400, 0xe08b, 0x0fff, 0xe08b, 0x21, 0 + .dw 0x1400, 0xe08b, 0x1fff, 0xe08b, 0x21, 0 + .dw 0x2400, 0xe08b, 0x2fff, 0xe08b, 0x21, 0 + .dw 0x3400, 0xe08b, 0x3fff, 0xe08b, 0x21, 0 + .dw 0x4400, 0xe08b, 0x4fff, 0xe08b, 0x21, 0 + .dw 0x5400, 0xe08b, 0x5fff, 0xe08b, 0x21, 0 + .dw 0x6400, 0xe08b, 0x6fff, 0xe08b, 0x21, 0 + .dw 0x7400, 0xe08b, 0xffff, 0xe08b, 0x21, 0 + .dw 0x0400, 0xe08c, 0x0fff, 0xe08c, 0x21, 0 + .dw 0x1400, 0xe08c, 0x1fff, 0xe08c, 0x21, 0 + .dw 0x2400, 0xe08c, 0x2fff, 0xe08c, 0x21, 0 + .dw 0x3400, 0xe08c, 0x3fff, 0xe08c, 0x21, 0 + .dw 0x4400, 0xe08c, 0x4fff, 0xe08c, 0x21, 0 + .dw 0x5400, 0xe08c, 0x5fff, 0xe08c, 0x21, 0 + .dw 0x6400, 0xe08c, 0x6fff, 0xe08c, 0x21, 0 + .dw 0x7400, 0xe08c, 0xffff, 0xe08c, 0x21, 0 + .dw 0x0400, 0xe08d, 0x0fff, 0xe08d, 0x21, 0 + .dw 0x1400, 0xe08d, 0x1fff, 0xe08d, 0x21, 0 + .dw 0x2400, 0xe08d, 0x2fff, 0xe08d, 0x21, 0 + .dw 0x3400, 0xe08d, 0x3fff, 0xe08d, 0x21, 0 + .dw 0x4400, 0xe08d, 0x4fff, 0xe08d, 0x21, 0 + .dw 0x5400, 0xe08d, 0x5fff, 0xe08d, 0x21, 0 + .dw 0x6400, 0xe08d, 0x6fff, 0xe08d, 0x21, 0 + .dw 0x7400, 0xe08d, 0xffff, 0xe08d, 0x21, 0 + .dw 0x0400, 0xe08e, 0x0fff, 0xe08e, 0x21, 0 + .dw 0x1400, 0xe08e, 0x1fff, 0xe08e, 0x21, 0 + .dw 0x2400, 0xe08e, 0x2fff, 0xe08e, 0x21, 0 + .dw 0x3400, 0xe08e, 0x3fff, 0xe08e, 0x21, 0 + .dw 0x4400, 0xe08e, 0x4fff, 0xe08e, 0x21, 0 + .dw 0x5400, 0xe08e, 0x5fff, 0xe08e, 0x21, 0 + .dw 0x6400, 0xe08e, 0x6fff, 0xe08e, 0x21, 0 + .dw 0x7400, 0xe08e, 0xffff, 0xe08e, 0x21, 0 + .dw 0x0400, 0xe08f, 0x0fff, 0xe08f, 0x21, 0 + .dw 0x1400, 0xe08f, 0x1fff, 0xe08f, 0x21, 0 + .dw 0x2400, 0xe08f, 0x2fff, 0xe08f, 0x21, 0 + .dw 0x3400, 0xe08f, 0x3fff, 0xe08f, 0x21, 0 + .dw 0x4400, 0xe08f, 0x4fff, 0xe08f, 0x21, 0 + .dw 0x5400, 0xe08f, 0x5fff, 0xe08f, 0x21, 0 + .dw 0x6400, 0xe08f, 0x6fff, 0xe08f, 0x21, 0 + .dw 0x7400, 0xe08f, 0xffff, 0xe08f, 0x21, 0 + .dw 0x0400, 0xe090, 0x0fff, 0xe090, 0x21, 0 + .dw 0x1400, 0xe090, 0x1fff, 0xe090, 0x21, 0 + .dw 0x2400, 0xe090, 0x2fff, 0xe090, 0x21, 0 + .dw 0x3400, 0xe090, 0x3fff, 0xe090, 0x21, 0 + .dw 0x4400, 0xe090, 0x4fff, 0xe090, 0x21, 0 + .dw 0x5400, 0xe090, 0x5fff, 0xe090, 0x21, 0 + .dw 0x6400, 0xe090, 0x6fff, 0xe090, 0x21, 0 + .dw 0x7400, 0xe090, 0xffff, 0xe090, 0x21, 0 + .dw 0x0400, 0xe091, 0x0fff, 0xe091, 0x21, 0 + .dw 0x1400, 0xe091, 0x1fff, 0xe091, 0x21, 0 + .dw 0x2400, 0xe091, 0x2fff, 0xe091, 0x21, 0 + .dw 0x3400, 0xe091, 0x3fff, 0xe091, 0x21, 0 + .dw 0x4400, 0xe091, 0x4fff, 0xe091, 0x21, 0 + .dw 0x5400, 0xe091, 0x5fff, 0xe091, 0x21, 0 + .dw 0x6400, 0xe091, 0x6fff, 0xe091, 0x21, 0 + .dw 0x7400, 0xe091, 0xffff, 0xe091, 0x21, 0 + .dw 0x0400, 0xe092, 0x0fff, 0xe092, 0x21, 0 + .dw 0x1400, 0xe092, 0x1fff, 0xe092, 0x21, 0 + .dw 0x2400, 0xe092, 0x2fff, 0xe092, 0x21, 0 + .dw 0x3400, 0xe092, 0x3fff, 0xe092, 0x21, 0 + .dw 0x4400, 0xe092, 0x4fff, 0xe092, 0x21, 0 + .dw 0x5400, 0xe092, 0x5fff, 0xe092, 0x21, 0 + .dw 0x6400, 0xe092, 0x6fff, 0xe092, 0x21, 0 + .dw 0x7400, 0xe092, 0xffff, 0xe092, 0x21, 0 + .dw 0x0400, 0xe093, 0x0fff, 0xe093, 0x21, 0 + .dw 0x1400, 0xe093, 0x1fff, 0xe093, 0x21, 0 + .dw 0x2400, 0xe093, 0x2fff, 0xe093, 0x21, 0 + .dw 0x3400, 0xe093, 0x3fff, 0xe093, 0x21, 0 + .dw 0x4400, 0xe093, 0x4fff, 0xe093, 0x21, 0 + .dw 0x5400, 0xe093, 0x5fff, 0xe093, 0x21, 0 + .dw 0x6400, 0xe093, 0x6fff, 0xe093, 0x21, 0 + .dw 0x7400, 0xe093, 0xffff, 0xe093, 0x21, 0 + .dw 0x0400, 0xe094, 0x0fff, 0xe094, 0x21, 0 + .dw 0x1400, 0xe094, 0x1fff, 0xe094, 0x21, 0 + .dw 0x2400, 0xe094, 0x2fff, 0xe094, 0x21, 0 + .dw 0x3400, 0xe094, 0x3fff, 0xe094, 0x21, 0 + .dw 0x4400, 0xe094, 0x4fff, 0xe094, 0x21, 0 + .dw 0x5400, 0xe094, 0x5fff, 0xe094, 0x21, 0 + .dw 0x6400, 0xe094, 0x6fff, 0xe094, 0x21, 0 + .dw 0x7400, 0xe094, 0xffff, 0xe094, 0x21, 0 + .dw 0x0400, 0xe095, 0x0fff, 0xe095, 0x21, 0 + .dw 0x1400, 0xe095, 0x1fff, 0xe095, 0x21, 0 + .dw 0x2400, 0xe095, 0x2fff, 0xe095, 0x21, 0 + .dw 0x3400, 0xe095, 0x3fff, 0xe095, 0x21, 0 + .dw 0x4400, 0xe095, 0x4fff, 0xe095, 0x21, 0 + .dw 0x5400, 0xe095, 0x5fff, 0xe095, 0x21, 0 + .dw 0x6400, 0xe095, 0x6fff, 0xe095, 0x21, 0 + .dw 0x7400, 0xe095, 0xffff, 0xe095, 0x21, 0 + .dw 0x0400, 0xe096, 0x0fff, 0xe096, 0x21, 0 + .dw 0x1400, 0xe096, 0x1fff, 0xe096, 0x21, 0 + .dw 0x2400, 0xe096, 0x2fff, 0xe096, 0x21, 0 + .dw 0x3400, 0xe096, 0x3fff, 0xe096, 0x21, 0 + .dw 0x4400, 0xe096, 0x4fff, 0xe096, 0x21, 0 + .dw 0x5400, 0xe096, 0x5fff, 0xe096, 0x21, 0 + .dw 0x6400, 0xe096, 0x6fff, 0xe096, 0x21, 0 + .dw 0x7400, 0xe096, 0xffff, 0xe096, 0x21, 0 + .dw 0x0400, 0xe097, 0x0fff, 0xe097, 0x21, 0 + .dw 0x1400, 0xe097, 0x1fff, 0xe097, 0x21, 0 + .dw 0x2400, 0xe097, 0x2fff, 0xe097, 0x21, 0 + .dw 0x3400, 0xe097, 0x3fff, 0xe097, 0x21, 0 + .dw 0x4400, 0xe097, 0x4fff, 0xe097, 0x21, 0 + .dw 0x5400, 0xe097, 0x5fff, 0xe097, 0x21, 0 + .dw 0x6400, 0xe097, 0x6fff, 0xe097, 0x21, 0 + .dw 0x7400, 0xe097, 0xffff, 0xe097, 0x21, 0 + .dw 0x0400, 0xe098, 0x0fff, 0xe098, 0x21, 0 + .dw 0x1400, 0xe098, 0x1fff, 0xe098, 0x21, 0 + .dw 0x2400, 0xe098, 0x2fff, 0xe098, 0x21, 0 + .dw 0x3400, 0xe098, 0x3fff, 0xe098, 0x21, 0 + .dw 0x4400, 0xe098, 0x4fff, 0xe098, 0x21, 0 + .dw 0x5400, 0xe098, 0x5fff, 0xe098, 0x21, 0 + .dw 0x6400, 0xe098, 0x6fff, 0xe098, 0x21, 0 + .dw 0x7400, 0xe098, 0xffff, 0xe098, 0x21, 0 + .dw 0x0400, 0xe099, 0x0fff, 0xe099, 0x21, 0 + .dw 0x1400, 0xe099, 0x1fff, 0xe099, 0x21, 0 + .dw 0x2400, 0xe099, 0x2fff, 0xe099, 0x21, 0 + .dw 0x3400, 0xe099, 0x3fff, 0xe099, 0x21, 0 + .dw 0x4400, 0xe099, 0x4fff, 0xe099, 0x21, 0 + .dw 0x5400, 0xe099, 0x5fff, 0xe099, 0x21, 0 + .dw 0x6400, 0xe099, 0x6fff, 0xe099, 0x21, 0 + .dw 0x7400, 0xe099, 0xffff, 0xe099, 0x21, 0 + .dw 0x0400, 0xe09a, 0x0fff, 0xe09a, 0x21, 0 + .dw 0x1400, 0xe09a, 0x1fff, 0xe09a, 0x21, 0 + .dw 0x2400, 0xe09a, 0x2fff, 0xe09a, 0x21, 0 + .dw 0x3400, 0xe09a, 0x3fff, 0xe09a, 0x21, 0 + .dw 0x4400, 0xe09a, 0x4fff, 0xe09a, 0x21, 0 + .dw 0x5400, 0xe09a, 0x5fff, 0xe09a, 0x21, 0 + .dw 0x6400, 0xe09a, 0x6fff, 0xe09a, 0x21, 0 + .dw 0x7400, 0xe09a, 0xffff, 0xe09a, 0x21, 0 + .dw 0x0400, 0xe09b, 0x0fff, 0xe09b, 0x21, 0 + .dw 0x1400, 0xe09b, 0x1fff, 0xe09b, 0x21, 0 + .dw 0x2400, 0xe09b, 0x2fff, 0xe09b, 0x21, 0 + .dw 0x3400, 0xe09b, 0x3fff, 0xe09b, 0x21, 0 + .dw 0x4400, 0xe09b, 0x4fff, 0xe09b, 0x21, 0 + .dw 0x5400, 0xe09b, 0x5fff, 0xe09b, 0x21, 0 + .dw 0x6400, 0xe09b, 0x6fff, 0xe09b, 0x21, 0 + .dw 0x7400, 0xe09b, 0xffff, 0xe09b, 0x21, 0 + .dw 0x0400, 0xe09c, 0x0fff, 0xe09c, 0x21, 0 + .dw 0x1400, 0xe09c, 0x1fff, 0xe09c, 0x21, 0 + .dw 0x2400, 0xe09c, 0x2fff, 0xe09c, 0x21, 0 + .dw 0x3400, 0xe09c, 0x3fff, 0xe09c, 0x21, 0 + .dw 0x4400, 0xe09c, 0x4fff, 0xe09c, 0x21, 0 + .dw 0x5400, 0xe09c, 0x5fff, 0xe09c, 0x21, 0 + .dw 0x6400, 0xe09c, 0x6fff, 0xe09c, 0x21, 0 + .dw 0x7400, 0xe09c, 0xffff, 0xe09c, 0x21, 0 + .dw 0x0400, 0xe09d, 0x0fff, 0xe09d, 0x21, 0 + .dw 0x1400, 0xe09d, 0x1fff, 0xe09d, 0x21, 0 + .dw 0x2400, 0xe09d, 0x2fff, 0xe09d, 0x21, 0 + .dw 0x3400, 0xe09d, 0x3fff, 0xe09d, 0x21, 0 + .dw 0x4400, 0xe09d, 0x4fff, 0xe09d, 0x21, 0 + .dw 0x5400, 0xe09d, 0x5fff, 0xe09d, 0x21, 0 + .dw 0x6400, 0xe09d, 0x6fff, 0xe09d, 0x21, 0 + .dw 0x7400, 0xe09d, 0xffff, 0xe09d, 0x21, 0 + .dw 0x0400, 0xe09e, 0x0fff, 0xe09e, 0x21, 0 + .dw 0x1400, 0xe09e, 0x1fff, 0xe09e, 0x21, 0 + .dw 0x2400, 0xe09e, 0x2fff, 0xe09e, 0x21, 0 + .dw 0x3400, 0xe09e, 0x3fff, 0xe09e, 0x21, 0 + .dw 0x4400, 0xe09e, 0x4fff, 0xe09e, 0x21, 0 + .dw 0x5400, 0xe09e, 0x5fff, 0xe09e, 0x21, 0 + .dw 0x6400, 0xe09e, 0x6fff, 0xe09e, 0x21, 0 + .dw 0x7400, 0xe09e, 0xffff, 0xe09e, 0x21, 0 + .dw 0x0400, 0xe09f, 0x0fff, 0xe09f, 0x21, 0 + .dw 0x1400, 0xe09f, 0x1fff, 0xe09f, 0x21, 0 + .dw 0x2400, 0xe09f, 0x2fff, 0xe09f, 0x21, 0 + .dw 0x3400, 0xe09f, 0x3fff, 0xe09f, 0x21, 0 + .dw 0x4400, 0xe09f, 0x4fff, 0xe09f, 0x21, 0 + .dw 0x5400, 0xe09f, 0x5fff, 0xe09f, 0x21, 0 + .dw 0x6400, 0xe09f, 0x6fff, 0xe09f, 0x21, 0 + .dw 0x7400, 0xe09f, 0xffff, 0xe09f, 0x21, 0 + .dw 0x0400, 0xe0a0, 0x0fff, 0xe0a0, 0x21, 0 + .dw 0x1400, 0xe0a0, 0x1fff, 0xe0a0, 0x21, 0 + .dw 0x2400, 0xe0a0, 0x2fff, 0xe0a0, 0x21, 0 + .dw 0x3400, 0xe0a0, 0x3fff, 0xe0a0, 0x21, 0 + .dw 0x4400, 0xe0a0, 0x4fff, 0xe0a0, 0x21, 0 + .dw 0x5400, 0xe0a0, 0x5fff, 0xe0a0, 0x21, 0 + .dw 0x6400, 0xe0a0, 0x6fff, 0xe0a0, 0x21, 0 + .dw 0x7400, 0xe0a0, 0xffff, 0xe0a0, 0x21, 0 + .dw 0x0400, 0xe0a1, 0x0fff, 0xe0a1, 0x21, 0 + .dw 0x1400, 0xe0a1, 0x1fff, 0xe0a1, 0x21, 0 + .dw 0x2400, 0xe0a1, 0x2fff, 0xe0a1, 0x21, 0 + .dw 0x3400, 0xe0a1, 0x3fff, 0xe0a1, 0x21, 0 + .dw 0x4400, 0xe0a1, 0x4fff, 0xe0a1, 0x21, 0 + .dw 0x5400, 0xe0a1, 0x5fff, 0xe0a1, 0x21, 0 + .dw 0x6400, 0xe0a1, 0x6fff, 0xe0a1, 0x21, 0 + .dw 0x7400, 0xe0a1, 0xffff, 0xe0a1, 0x21, 0 + .dw 0x0400, 0xe0a2, 0x0fff, 0xe0a2, 0x21, 0 + .dw 0x1400, 0xe0a2, 0x1fff, 0xe0a2, 0x21, 0 + .dw 0x2400, 0xe0a2, 0x2fff, 0xe0a2, 0x21, 0 + .dw 0x3400, 0xe0a2, 0x3fff, 0xe0a2, 0x21, 0 + .dw 0x4400, 0xe0a2, 0x4fff, 0xe0a2, 0x21, 0 + .dw 0x5400, 0xe0a2, 0x5fff, 0xe0a2, 0x21, 0 + .dw 0x6400, 0xe0a2, 0x6fff, 0xe0a2, 0x21, 0 + .dw 0x7400, 0xe0a2, 0xffff, 0xe0a2, 0x21, 0 + .dw 0x0400, 0xe0a3, 0x0fff, 0xe0a3, 0x21, 0 + .dw 0x1400, 0xe0a3, 0x1fff, 0xe0a3, 0x21, 0 + .dw 0x2400, 0xe0a3, 0x2fff, 0xe0a3, 0x21, 0 + .dw 0x3400, 0xe0a3, 0x3fff, 0xe0a3, 0x21, 0 + .dw 0x4400, 0xe0a3, 0x4fff, 0xe0a3, 0x21, 0 + .dw 0x5400, 0xe0a3, 0x5fff, 0xe0a3, 0x21, 0 + .dw 0x6400, 0xe0a3, 0x6fff, 0xe0a3, 0x21, 0 + .dw 0x7400, 0xe0a3, 0xffff, 0xe0a3, 0x21, 0 + .dw 0x0400, 0xe0a4, 0x0fff, 0xe0a4, 0x21, 0 + .dw 0x1400, 0xe0a4, 0x1fff, 0xe0a4, 0x21, 0 + .dw 0x2400, 0xe0a4, 0x2fff, 0xe0a4, 0x21, 0 + .dw 0x3400, 0xe0a4, 0x3fff, 0xe0a4, 0x21, 0 + .dw 0x4400, 0xe0a4, 0x4fff, 0xe0a4, 0x21, 0 + .dw 0x5400, 0xe0a4, 0x5fff, 0xe0a4, 0x21, 0 + .dw 0x6400, 0xe0a4, 0x6fff, 0xe0a4, 0x21, 0 + .dw 0x7400, 0xe0a4, 0xffff, 0xe0a4, 0x21, 0 + .dw 0x0400, 0xe0a5, 0x0fff, 0xe0a5, 0x21, 0 + .dw 0x1400, 0xe0a5, 0x1fff, 0xe0a5, 0x21, 0 + .dw 0x2400, 0xe0a5, 0x2fff, 0xe0a5, 0x21, 0 + .dw 0x3400, 0xe0a5, 0x3fff, 0xe0a5, 0x21, 0 + .dw 0x4400, 0xe0a5, 0x4fff, 0xe0a5, 0x21, 0 + .dw 0x5400, 0xe0a5, 0x5fff, 0xe0a5, 0x21, 0 + .dw 0x6400, 0xe0a5, 0x6fff, 0xe0a5, 0x21, 0 + .dw 0x7400, 0xe0a5, 0xffff, 0xe0a5, 0x21, 0 + .dw 0x0400, 0xe0a6, 0x0fff, 0xe0a6, 0x21, 0 + .dw 0x1400, 0xe0a6, 0x1fff, 0xe0a6, 0x21, 0 + .dw 0x2400, 0xe0a6, 0x2fff, 0xe0a6, 0x21, 0 + .dw 0x3400, 0xe0a6, 0x3fff, 0xe0a6, 0x21, 0 + .dw 0x4400, 0xe0a6, 0x4fff, 0xe0a6, 0x21, 0 + .dw 0x5400, 0xe0a6, 0x5fff, 0xe0a6, 0x21, 0 + .dw 0x6400, 0xe0a6, 0x6fff, 0xe0a6, 0x21, 0 + .dw 0x7400, 0xe0a6, 0xffff, 0xe0a6, 0x21, 0 + .dw 0x0400, 0xe0a7, 0x0fff, 0xe0a7, 0x21, 0 + .dw 0x1400, 0xe0a7, 0x1fff, 0xe0a7, 0x21, 0 + .dw 0x2400, 0xe0a7, 0x2fff, 0xe0a7, 0x21, 0 + .dw 0x3400, 0xe0a7, 0x3fff, 0xe0a7, 0x21, 0 + .dw 0x4400, 0xe0a7, 0x4fff, 0xe0a7, 0x21, 0 + .dw 0x5400, 0xe0a7, 0x5fff, 0xe0a7, 0x21, 0 + .dw 0x6400, 0xe0a7, 0x6fff, 0xe0a7, 0x21, 0 + .dw 0x7400, 0xe0a7, 0xffff, 0xe0a7, 0x21, 0 + .dw 0x0400, 0xe0a8, 0x0fff, 0xe0a8, 0x21, 0 + .dw 0x1400, 0xe0a8, 0x1fff, 0xe0a8, 0x21, 0 + .dw 0x2400, 0xe0a8, 0x2fff, 0xe0a8, 0x21, 0 + .dw 0x3400, 0xe0a8, 0x3fff, 0xe0a8, 0x21, 0 + .dw 0x4400, 0xe0a8, 0x4fff, 0xe0a8, 0x21, 0 + .dw 0x5400, 0xe0a8, 0x5fff, 0xe0a8, 0x21, 0 + .dw 0x6400, 0xe0a8, 0x6fff, 0xe0a8, 0x21, 0 + .dw 0x7400, 0xe0a8, 0xffff, 0xe0a8, 0x21, 0 + .dw 0x0400, 0xe0a9, 0x0fff, 0xe0a9, 0x21, 0 + .dw 0x1400, 0xe0a9, 0x1fff, 0xe0a9, 0x21, 0 + .dw 0x2400, 0xe0a9, 0x2fff, 0xe0a9, 0x21, 0 + .dw 0x3400, 0xe0a9, 0x3fff, 0xe0a9, 0x21, 0 + .dw 0x4400, 0xe0a9, 0x4fff, 0xe0a9, 0x21, 0 + .dw 0x5400, 0xe0a9, 0x5fff, 0xe0a9, 0x21, 0 + .dw 0x6400, 0xe0a9, 0x6fff, 0xe0a9, 0x21, 0 + .dw 0x7400, 0xe0a9, 0xffff, 0xe0a9, 0x21, 0 + .dw 0x0400, 0xe0aa, 0x0fff, 0xe0aa, 0x21, 0 + .dw 0x1400, 0xe0aa, 0x1fff, 0xe0aa, 0x21, 0 + .dw 0x2400, 0xe0aa, 0x2fff, 0xe0aa, 0x21, 0 + .dw 0x3400, 0xe0aa, 0x3fff, 0xe0aa, 0x21, 0 + .dw 0x4400, 0xe0aa, 0x4fff, 0xe0aa, 0x21, 0 + .dw 0x5400, 0xe0aa, 0x5fff, 0xe0aa, 0x21, 0 + .dw 0x6400, 0xe0aa, 0x6fff, 0xe0aa, 0x21, 0 + .dw 0x7400, 0xe0aa, 0xffff, 0xe0aa, 0x21, 0 + .dw 0x0400, 0xe0ab, 0x0fff, 0xe0ab, 0x21, 0 + .dw 0x1400, 0xe0ab, 0x1fff, 0xe0ab, 0x21, 0 + .dw 0x2400, 0xe0ab, 0x2fff, 0xe0ab, 0x21, 0 + .dw 0x3400, 0xe0ab, 0x3fff, 0xe0ab, 0x21, 0 + .dw 0x4400, 0xe0ab, 0x4fff, 0xe0ab, 0x21, 0 + .dw 0x5400, 0xe0ab, 0x5fff, 0xe0ab, 0x21, 0 + .dw 0x6400, 0xe0ab, 0x6fff, 0xe0ab, 0x21, 0 + .dw 0x7400, 0xe0ab, 0xffff, 0xe0ab, 0x21, 0 + .dw 0x0400, 0xe0ac, 0x0fff, 0xe0ac, 0x21, 0 + .dw 0x1400, 0xe0ac, 0x1fff, 0xe0ac, 0x21, 0 + .dw 0x2400, 0xe0ac, 0x2fff, 0xe0ac, 0x21, 0 + .dw 0x3400, 0xe0ac, 0x3fff, 0xe0ac, 0x21, 0 + .dw 0x4400, 0xe0ac, 0x4fff, 0xe0ac, 0x21, 0 + .dw 0x5400, 0xe0ac, 0x5fff, 0xe0ac, 0x21, 0 + .dw 0x6400, 0xe0ac, 0x6fff, 0xe0ac, 0x21, 0 + .dw 0x7400, 0xe0ac, 0xffff, 0xe0ac, 0x21, 0 + .dw 0x0400, 0xe0ad, 0x0fff, 0xe0ad, 0x21, 0 + .dw 0x1400, 0xe0ad, 0x1fff, 0xe0ad, 0x21, 0 + .dw 0x2400, 0xe0ad, 0x2fff, 0xe0ad, 0x21, 0 + .dw 0x3400, 0xe0ad, 0x3fff, 0xe0ad, 0x21, 0 + .dw 0x4400, 0xe0ad, 0x4fff, 0xe0ad, 0x21, 0 + .dw 0x5400, 0xe0ad, 0x5fff, 0xe0ad, 0x21, 0 + .dw 0x6400, 0xe0ad, 0x6fff, 0xe0ad, 0x21, 0 + .dw 0x7400, 0xe0ad, 0xffff, 0xe0ad, 0x21, 0 + .dw 0x0400, 0xe0ae, 0x0fff, 0xe0ae, 0x21, 0 + .dw 0x1400, 0xe0ae, 0x1fff, 0xe0ae, 0x21, 0 + .dw 0x2400, 0xe0ae, 0x2fff, 0xe0ae, 0x21, 0 + .dw 0x3400, 0xe0ae, 0x3fff, 0xe0ae, 0x21, 0 + .dw 0x4400, 0xe0ae, 0x4fff, 0xe0ae, 0x21, 0 + .dw 0x5400, 0xe0ae, 0x5fff, 0xe0ae, 0x21, 0 + .dw 0x6400, 0xe0ae, 0x6fff, 0xe0ae, 0x21, 0 + .dw 0x7400, 0xe0ae, 0xffff, 0xe0ae, 0x21, 0 + .dw 0x0400, 0xe0af, 0x0fff, 0xe0af, 0x21, 0 + .dw 0x1400, 0xe0af, 0x1fff, 0xe0af, 0x21, 0 + .dw 0x2400, 0xe0af, 0x2fff, 0xe0af, 0x21, 0 + .dw 0x3400, 0xe0af, 0x3fff, 0xe0af, 0x21, 0 + .dw 0x4400, 0xe0af, 0x4fff, 0xe0af, 0x21, 0 + .dw 0x5400, 0xe0af, 0x5fff, 0xe0af, 0x21, 0 + .dw 0x6400, 0xe0af, 0x6fff, 0xe0af, 0x21, 0 + .dw 0x7400, 0xe0af, 0xffff, 0xe0af, 0x21, 0 + .dw 0x0400, 0xe0b0, 0x0fff, 0xe0b0, 0x21, 0 + .dw 0x1400, 0xe0b0, 0x1fff, 0xe0b0, 0x21, 0 + .dw 0x2400, 0xe0b0, 0x2fff, 0xe0b0, 0x21, 0 + .dw 0x3400, 0xe0b0, 0x3fff, 0xe0b0, 0x21, 0 + .dw 0x4400, 0xe0b0, 0x4fff, 0xe0b0, 0x21, 0 + .dw 0x5400, 0xe0b0, 0x5fff, 0xe0b0, 0x21, 0 + .dw 0x6400, 0xe0b0, 0x6fff, 0xe0b0, 0x21, 0 + .dw 0x7400, 0xe0b0, 0xffff, 0xe0b0, 0x21, 0 + .dw 0x0400, 0xe0b1, 0x0fff, 0xe0b1, 0x21, 0 + .dw 0x1400, 0xe0b1, 0x1fff, 0xe0b1, 0x21, 0 + .dw 0x2400, 0xe0b1, 0x2fff, 0xe0b1, 0x21, 0 + .dw 0x3400, 0xe0b1, 0x3fff, 0xe0b1, 0x21, 0 + .dw 0x4400, 0xe0b1, 0x4fff, 0xe0b1, 0x21, 0 + .dw 0x5400, 0xe0b1, 0x5fff, 0xe0b1, 0x21, 0 + .dw 0x6400, 0xe0b1, 0x6fff, 0xe0b1, 0x21, 0 + .dw 0x7400, 0xe0b1, 0xffff, 0xe0b1, 0x21, 0 + .dw 0x0400, 0xe0b2, 0x0fff, 0xe0b2, 0x21, 0 + .dw 0x1400, 0xe0b2, 0x1fff, 0xe0b2, 0x21, 0 + .dw 0x2400, 0xe0b2, 0x2fff, 0xe0b2, 0x21, 0 + .dw 0x3400, 0xe0b2, 0x3fff, 0xe0b2, 0x21, 0 + .dw 0x4400, 0xe0b2, 0x4fff, 0xe0b2, 0x21, 0 + .dw 0x5400, 0xe0b2, 0x5fff, 0xe0b2, 0x21, 0 + .dw 0x6400, 0xe0b2, 0x6fff, 0xe0b2, 0x21, 0 + .dw 0x7400, 0xe0b2, 0xffff, 0xe0b2, 0x21, 0 + .dw 0x0400, 0xe0b3, 0x0fff, 0xe0b3, 0x21, 0 + .dw 0x1400, 0xe0b3, 0x1fff, 0xe0b3, 0x21, 0 + .dw 0x2400, 0xe0b3, 0x2fff, 0xe0b3, 0x21, 0 + .dw 0x3400, 0xe0b3, 0x3fff, 0xe0b3, 0x21, 0 + .dw 0x4400, 0xe0b3, 0x4fff, 0xe0b3, 0x21, 0 + .dw 0x5400, 0xe0b3, 0x5fff, 0xe0b3, 0x21, 0 + .dw 0x6400, 0xe0b3, 0x6fff, 0xe0b3, 0x21, 0 + .dw 0x7400, 0xe0b3, 0xffff, 0xe0b3, 0x21, 0 + .dw 0x0400, 0xe0b4, 0x0fff, 0xe0b4, 0x21, 0 + .dw 0x1400, 0xe0b4, 0x1fff, 0xe0b4, 0x21, 0 + .dw 0x2400, 0xe0b4, 0x2fff, 0xe0b4, 0x21, 0 + .dw 0x3400, 0xe0b4, 0x3fff, 0xe0b4, 0x21, 0 + .dw 0x4400, 0xe0b4, 0x4fff, 0xe0b4, 0x21, 0 + .dw 0x5400, 0xe0b4, 0x5fff, 0xe0b4, 0x21, 0 + .dw 0x6400, 0xe0b4, 0x6fff, 0xe0b4, 0x21, 0 + .dw 0x7400, 0xe0b4, 0xffff, 0xe0b4, 0x21, 0 + .dw 0x0400, 0xe0b5, 0x0fff, 0xe0b5, 0x21, 0 + .dw 0x1400, 0xe0b5, 0x1fff, 0xe0b5, 0x21, 0 + .dw 0x2400, 0xe0b5, 0x2fff, 0xe0b5, 0x21, 0 + .dw 0x3400, 0xe0b5, 0x3fff, 0xe0b5, 0x21, 0 + .dw 0x4400, 0xe0b5, 0x4fff, 0xe0b5, 0x21, 0 + .dw 0x5400, 0xe0b5, 0x5fff, 0xe0b5, 0x21, 0 + .dw 0x6400, 0xe0b5, 0x6fff, 0xe0b5, 0x21, 0 + .dw 0x7400, 0xe0b5, 0xffff, 0xe0b5, 0x21, 0 + .dw 0x0400, 0xe0b6, 0x0fff, 0xe0b6, 0x21, 0 + .dw 0x1400, 0xe0b6, 0x1fff, 0xe0b6, 0x21, 0 + .dw 0x2400, 0xe0b6, 0x2fff, 0xe0b6, 0x21, 0 + .dw 0x3400, 0xe0b6, 0x3fff, 0xe0b6, 0x21, 0 + .dw 0x4400, 0xe0b6, 0x4fff, 0xe0b6, 0x21, 0 + .dw 0x5400, 0xe0b6, 0x5fff, 0xe0b6, 0x21, 0 + .dw 0x6400, 0xe0b6, 0x6fff, 0xe0b6, 0x21, 0 + .dw 0x7400, 0xe0b6, 0xffff, 0xe0b6, 0x21, 0 + .dw 0x0400, 0xe0b7, 0x0fff, 0xe0b7, 0x21, 0 + .dw 0x1400, 0xe0b7, 0x1fff, 0xe0b7, 0x21, 0 + .dw 0x2400, 0xe0b7, 0x2fff, 0xe0b7, 0x21, 0 + .dw 0x3400, 0xe0b7, 0x3fff, 0xe0b7, 0x21, 0 + .dw 0x4400, 0xe0b7, 0x4fff, 0xe0b7, 0x21, 0 + .dw 0x5400, 0xe0b7, 0x5fff, 0xe0b7, 0x21, 0 + .dw 0x6400, 0xe0b7, 0x6fff, 0xe0b7, 0x21, 0 + .dw 0x7400, 0xe0b7, 0xffff, 0xe0b7, 0x21, 0 + .dw 0x0400, 0xe0b8, 0x0fff, 0xe0b8, 0x21, 0 + .dw 0x1400, 0xe0b8, 0x1fff, 0xe0b8, 0x21, 0 + .dw 0x2400, 0xe0b8, 0x2fff, 0xe0b8, 0x21, 0 + .dw 0x3400, 0xe0b8, 0x3fff, 0xe0b8, 0x21, 0 + .dw 0x4400, 0xe0b8, 0x4fff, 0xe0b8, 0x21, 0 + .dw 0x5400, 0xe0b8, 0x5fff, 0xe0b8, 0x21, 0 + .dw 0x6400, 0xe0b8, 0x6fff, 0xe0b8, 0x21, 0 + .dw 0x7400, 0xe0b8, 0xffff, 0xe0b8, 0x21, 0 + .dw 0x0400, 0xe0b9, 0x0fff, 0xe0b9, 0x21, 0 + .dw 0x1400, 0xe0b9, 0x1fff, 0xe0b9, 0x21, 0 + .dw 0x2400, 0xe0b9, 0x2fff, 0xe0b9, 0x21, 0 + .dw 0x3400, 0xe0b9, 0x3fff, 0xe0b9, 0x21, 0 + .dw 0x4400, 0xe0b9, 0x4fff, 0xe0b9, 0x21, 0 + .dw 0x5400, 0xe0b9, 0x5fff, 0xe0b9, 0x21, 0 + .dw 0x6400, 0xe0b9, 0x6fff, 0xe0b9, 0x21, 0 + .dw 0x7400, 0xe0b9, 0xffff, 0xe0b9, 0x21, 0 + .dw 0x0400, 0xe0ba, 0x0fff, 0xe0ba, 0x21, 0 + .dw 0x1400, 0xe0ba, 0x1fff, 0xe0ba, 0x21, 0 + .dw 0x2400, 0xe0ba, 0x2fff, 0xe0ba, 0x21, 0 + .dw 0x3400, 0xe0ba, 0x3fff, 0xe0ba, 0x21, 0 + .dw 0x4400, 0xe0ba, 0x4fff, 0xe0ba, 0x21, 0 + .dw 0x5400, 0xe0ba, 0x5fff, 0xe0ba, 0x21, 0 + .dw 0x6400, 0xe0ba, 0x6fff, 0xe0ba, 0x21, 0 + .dw 0x7400, 0xe0ba, 0xffff, 0xe0ba, 0x21, 0 + .dw 0x0400, 0xe0bb, 0x0fff, 0xe0bb, 0x21, 0 + .dw 0x1400, 0xe0bb, 0x1fff, 0xe0bb, 0x21, 0 + .dw 0x2400, 0xe0bb, 0x2fff, 0xe0bb, 0x21, 0 + .dw 0x3400, 0xe0bb, 0x3fff, 0xe0bb, 0x21, 0 + .dw 0x4400, 0xe0bb, 0x4fff, 0xe0bb, 0x21, 0 + .dw 0x5400, 0xe0bb, 0x5fff, 0xe0bb, 0x21, 0 + .dw 0x6400, 0xe0bb, 0x6fff, 0xe0bb, 0x21, 0 + .dw 0x7400, 0xe0bb, 0xffff, 0xe0bb, 0x21, 0 + .dw 0x0400, 0xe0bc, 0x0fff, 0xe0bc, 0x21, 0 + .dw 0x1400, 0xe0bc, 0x1fff, 0xe0bc, 0x21, 0 + .dw 0x2400, 0xe0bc, 0x2fff, 0xe0bc, 0x21, 0 + .dw 0x3400, 0xe0bc, 0x3fff, 0xe0bc, 0x21, 0 + .dw 0x4400, 0xe0bc, 0x4fff, 0xe0bc, 0x21, 0 + .dw 0x5400, 0xe0bc, 0x5fff, 0xe0bc, 0x21, 0 + .dw 0x6400, 0xe0bc, 0x6fff, 0xe0bc, 0x21, 0 + .dw 0x7400, 0xe0bc, 0xffff, 0xe0bc, 0x21, 0 + .dw 0x0400, 0xe0bd, 0x0fff, 0xe0bd, 0x21, 0 + .dw 0x1400, 0xe0bd, 0x1fff, 0xe0bd, 0x21, 0 + .dw 0x2400, 0xe0bd, 0x2fff, 0xe0bd, 0x21, 0 + .dw 0x3400, 0xe0bd, 0x3fff, 0xe0bd, 0x21, 0 + .dw 0x4400, 0xe0bd, 0x4fff, 0xe0bd, 0x21, 0 + .dw 0x5400, 0xe0bd, 0x5fff, 0xe0bd, 0x21, 0 + .dw 0x6400, 0xe0bd, 0x6fff, 0xe0bd, 0x21, 0 + .dw 0x7400, 0xe0bd, 0xffff, 0xe0bd, 0x21, 0 + .dw 0x0400, 0xe0be, 0x0fff, 0xe0be, 0x21, 0 + .dw 0x1400, 0xe0be, 0x1fff, 0xe0be, 0x21, 0 + .dw 0x2400, 0xe0be, 0x2fff, 0xe0be, 0x21, 0 + .dw 0x3400, 0xe0be, 0x3fff, 0xe0be, 0x21, 0 + .dw 0x4400, 0xe0be, 0x4fff, 0xe0be, 0x21, 0 + .dw 0x5400, 0xe0be, 0x5fff, 0xe0be, 0x21, 0 + .dw 0x6400, 0xe0be, 0x6fff, 0xe0be, 0x21, 0 + .dw 0x7400, 0xe0be, 0xffff, 0xe0be, 0x21, 0 + .dw 0x0400, 0xe0bf, 0x0fff, 0xe0bf, 0x21, 0 + .dw 0x1400, 0xe0bf, 0x1fff, 0xe0bf, 0x21, 0 + .dw 0x2400, 0xe0bf, 0x2fff, 0xe0bf, 0x21, 0 + .dw 0x3400, 0xe0bf, 0x3fff, 0xe0bf, 0x21, 0 + .dw 0x4400, 0xe0bf, 0x4fff, 0xe0bf, 0x21, 0 + .dw 0x5400, 0xe0bf, 0x5fff, 0xe0bf, 0x21, 0 + .dw 0x6400, 0xe0bf, 0x6fff, 0xe0bf, 0x21, 0 + .dw 0x7400, 0xe0bf, 0xffff, 0xe0df, 0x21, 0 + .dw 0x0400, 0xe0e0, 0x0fff, 0xe0e0, 0x21, 0 + .dw 0x1400, 0xe0e0, 0x1fff, 0xe0e0, 0x21, 0 + .dw 0x2400, 0xe0e0, 0x2fff, 0xe0e0, 0x21, 0 + .dw 0x3400, 0xe0e0, 0x3fff, 0xe0e0, 0x21, 0 + .dw 0x4400, 0xe0e0, 0x4fff, 0xe0e0, 0x21, 0 + .dw 0x5400, 0xe0e0, 0x5fff, 0xe0e0, 0x21, 0 + .dw 0x6400, 0xe0e0, 0x6fff, 0xe0e0, 0x21, 0 + .dw 0x7400, 0xe0e0, 0xffff, 0xe0e0, 0x21, 0 + .dw 0x0400, 0xe0e1, 0x0fff, 0xe0e1, 0x21, 0 + .dw 0x1400, 0xe0e1, 0x1fff, 0xe0e1, 0x21, 0 + .dw 0x2400, 0xe0e1, 0x2fff, 0xe0e1, 0x21, 0 + .dw 0x3400, 0xe0e1, 0x3fff, 0xe0e1, 0x21, 0 + .dw 0x4400, 0xe0e1, 0x4fff, 0xe0e1, 0x21, 0 + .dw 0x5400, 0xe0e1, 0x5fff, 0xe0e1, 0x21, 0 + .dw 0x6400, 0xe0e1, 0x6fff, 0xe0e1, 0x21, 0 + .dw 0x7400, 0xe0e1, 0xffff, 0xe0e1, 0x21, 0 + .dw 0x0400, 0xe0e2, 0x0fff, 0xe0e2, 0x21, 0 + .dw 0x1400, 0xe0e2, 0x1fff, 0xe0e2, 0x21, 0 + .dw 0x2400, 0xe0e2, 0x2fff, 0xe0e2, 0x21, 0 + .dw 0x3400, 0xe0e2, 0x3fff, 0xe0e2, 0x21, 0 + .dw 0x4400, 0xe0e2, 0x4fff, 0xe0e2, 0x21, 0 + .dw 0x5400, 0xe0e2, 0x5fff, 0xe0e2, 0x21, 0 + .dw 0x6400, 0xe0e2, 0x6fff, 0xe0e2, 0x21, 0 + .dw 0x7400, 0xe0e2, 0xffff, 0xe0e2, 0x21, 0 + .dw 0x0400, 0xe0e3, 0x0fff, 0xe0e3, 0x21, 0 + .dw 0x1400, 0xe0e3, 0x1fff, 0xe0e3, 0x21, 0 + .dw 0x2400, 0xe0e3, 0x2fff, 0xe0e3, 0x21, 0 + .dw 0x3400, 0xe0e3, 0x3fff, 0xe0e3, 0x21, 0 + .dw 0x4400, 0xe0e3, 0x4fff, 0xe0e3, 0x21, 0 + .dw 0x5400, 0xe0e3, 0x5fff, 0xe0e3, 0x21, 0 + .dw 0x6400, 0xe0e3, 0x6fff, 0xe0e3, 0x21, 0 + .dw 0x7400, 0xe0e3, 0xffff, 0xe0e3, 0x21, 0 + .dw 0x0400, 0xe0e4, 0x0fff, 0xe0e4, 0x21, 0 + .dw 0x1400, 0xe0e4, 0x1fff, 0xe0e4, 0x21, 0 + .dw 0x2400, 0xe0e4, 0x2fff, 0xe0e4, 0x21, 0 + .dw 0x3400, 0xe0e4, 0x3fff, 0xe0e4, 0x21, 0 + .dw 0x4400, 0xe0e4, 0x4fff, 0xe0e4, 0x21, 0 + .dw 0x5400, 0xe0e4, 0x5fff, 0xe0e4, 0x21, 0 + .dw 0x6400, 0xe0e4, 0x6fff, 0xe0e4, 0x21, 0 + .dw 0x7400, 0xe0e4, 0xffff, 0xe0e4, 0x21, 0 + .dw 0x0400, 0xe0e5, 0x0fff, 0xe0e5, 0x21, 0 + .dw 0x1400, 0xe0e5, 0x1fff, 0xe0e5, 0x21, 0 + .dw 0x2400, 0xe0e5, 0x2fff, 0xe0e5, 0x21, 0 + .dw 0x3400, 0xe0e5, 0x3fff, 0xe0e5, 0x21, 0 + .dw 0x4400, 0xe0e5, 0x4fff, 0xe0e5, 0x21, 0 + .dw 0x5400, 0xe0e5, 0x5fff, 0xe0e5, 0x21, 0 + .dw 0x6400, 0xe0e5, 0x6fff, 0xe0e5, 0x21, 0 + .dw 0x7400, 0xe0e5, 0xffff, 0xe0e5, 0x21, 0 + .dw 0x0400, 0xe0e6, 0x0fff, 0xe0e6, 0x21, 0 + .dw 0x1400, 0xe0e6, 0x1fff, 0xe0e6, 0x21, 0 + .dw 0x2400, 0xe0e6, 0x2fff, 0xe0e6, 0x21, 0 + .dw 0x3400, 0xe0e6, 0x3fff, 0xe0e6, 0x21, 0 + .dw 0x4400, 0xe0e6, 0x4fff, 0xe0e6, 0x21, 0 + .dw 0x5400, 0xe0e6, 0x5fff, 0xe0e6, 0x21, 0 + .dw 0x6400, 0xe0e6, 0x6fff, 0xe0e6, 0x21, 0 + .dw 0x7400, 0xe0e6, 0xffff, 0xe0e6, 0x21, 0 + .dw 0x0400, 0xe0e7, 0x0fff, 0xe0e7, 0x21, 0 + .dw 0x1400, 0xe0e7, 0x1fff, 0xe0e7, 0x21, 0 + .dw 0x2400, 0xe0e7, 0x2fff, 0xe0e7, 0x21, 0 + .dw 0x3400, 0xe0e7, 0x3fff, 0xe0e7, 0x21, 0 + .dw 0x4400, 0xe0e7, 0x4fff, 0xe0e7, 0x21, 0 + .dw 0x5400, 0xe0e7, 0x5fff, 0xe0e7, 0x21, 0 + .dw 0x6400, 0xe0e7, 0x6fff, 0xe0e7, 0x21, 0 + .dw 0x7400, 0xe0e7, 0xffff, 0xe0e7, 0x21, 0 + .dw 0x0400, 0xe0e8, 0x0fff, 0xe0e8, 0x21, 0 + .dw 0x1400, 0xe0e8, 0x1fff, 0xe0e8, 0x21, 0 + .dw 0x2400, 0xe0e8, 0x2fff, 0xe0e8, 0x21, 0 + .dw 0x3400, 0xe0e8, 0x3fff, 0xe0e8, 0x21, 0 + .dw 0x4400, 0xe0e8, 0x4fff, 0xe0e8, 0x21, 0 + .dw 0x5400, 0xe0e8, 0x5fff, 0xe0e8, 0x21, 0 + .dw 0x6400, 0xe0e8, 0x6fff, 0xe0e8, 0x21, 0 + .dw 0x7400, 0xe0e8, 0xffff, 0xe0e8, 0x21, 0 + .dw 0x0400, 0xe0e9, 0x0fff, 0xe0e9, 0x21, 0 + .dw 0x1400, 0xe0e9, 0x1fff, 0xe0e9, 0x21, 0 + .dw 0x2400, 0xe0e9, 0x2fff, 0xe0e9, 0x21, 0 + .dw 0x3400, 0xe0e9, 0x3fff, 0xe0e9, 0x21, 0 + .dw 0x4400, 0xe0e9, 0x4fff, 0xe0e9, 0x21, 0 + .dw 0x5400, 0xe0e9, 0x5fff, 0xe0e9, 0x21, 0 + .dw 0x6400, 0xe0e9, 0x6fff, 0xe0e9, 0x21, 0 + .dw 0x7400, 0xe0e9, 0xffff, 0xe0e9, 0x21, 0 + .dw 0x0400, 0xe0ea, 0x0fff, 0xe0ea, 0x21, 0 + .dw 0x1400, 0xe0ea, 0x1fff, 0xe0ea, 0x21, 0 + .dw 0x2400, 0xe0ea, 0x2fff, 0xe0ea, 0x21, 0 + .dw 0x3400, 0xe0ea, 0x3fff, 0xe0ea, 0x21, 0 + .dw 0x4400, 0xe0ea, 0x4fff, 0xe0ea, 0x21, 0 + .dw 0x5400, 0xe0ea, 0x5fff, 0xe0ea, 0x21, 0 + .dw 0x6400, 0xe0ea, 0x6fff, 0xe0ea, 0x21, 0 + .dw 0x7400, 0xe0ea, 0xffff, 0xe0ea, 0x21, 0 + .dw 0x0400, 0xe0eb, 0x0fff, 0xe0eb, 0x21, 0 + .dw 0x1400, 0xe0eb, 0x1fff, 0xe0eb, 0x21, 0 + .dw 0x2400, 0xe0eb, 0x2fff, 0xe0eb, 0x21, 0 + .dw 0x3400, 0xe0eb, 0x3fff, 0xe0eb, 0x21, 0 + .dw 0x4400, 0xe0eb, 0x4fff, 0xe0eb, 0x21, 0 + .dw 0x5400, 0xe0eb, 0x5fff, 0xe0eb, 0x21, 0 + .dw 0x6400, 0xe0eb, 0x6fff, 0xe0eb, 0x21, 0 + .dw 0x7400, 0xe0eb, 0xffff, 0xe0eb, 0x21, 0 + .dw 0x0400, 0xe0ec, 0x0fff, 0xe0ec, 0x21, 0 + .dw 0x1400, 0xe0ec, 0x1fff, 0xe0ec, 0x21, 0 + .dw 0x2400, 0xe0ec, 0x2fff, 0xe0ec, 0x21, 0 + .dw 0x3400, 0xe0ec, 0x3fff, 0xe0ec, 0x21, 0 + .dw 0x4400, 0xe0ec, 0x4fff, 0xe0ec, 0x21, 0 + .dw 0x5400, 0xe0ec, 0x5fff, 0xe0ec, 0x21, 0 + .dw 0x6400, 0xe0ec, 0x6fff, 0xe0ec, 0x21, 0 + .dw 0x7400, 0xe0ec, 0xffff, 0xe0ec, 0x21, 0 + .dw 0x0400, 0xe0ed, 0x0fff, 0xe0ed, 0x21, 0 + .dw 0x1400, 0xe0ed, 0x1fff, 0xe0ed, 0x21, 0 + .dw 0x2400, 0xe0ed, 0x2fff, 0xe0ed, 0x21, 0 + .dw 0x3400, 0xe0ed, 0x3fff, 0xe0ed, 0x21, 0 + .dw 0x4400, 0xe0ed, 0x4fff, 0xe0ed, 0x21, 0 + .dw 0x5400, 0xe0ed, 0x5fff, 0xe0ed, 0x21, 0 + .dw 0x6400, 0xe0ed, 0x6fff, 0xe0ed, 0x21, 0 + .dw 0x7400, 0xe0ed, 0xffff, 0xe0ed, 0x21, 0 + .dw 0x0400, 0xe0ee, 0x0fff, 0xe0ee, 0x21, 0 + .dw 0x1400, 0xe0ee, 0x1fff, 0xe0ee, 0x21, 0 + .dw 0x2400, 0xe0ee, 0x2fff, 0xe0ee, 0x21, 0 + .dw 0x3400, 0xe0ee, 0x3fff, 0xe0ee, 0x21, 0 + .dw 0x4400, 0xe0ee, 0x4fff, 0xe0ee, 0x21, 0 + .dw 0x5400, 0xe0ee, 0x5fff, 0xe0ee, 0x21, 0 + .dw 0x6400, 0xe0ee, 0x6fff, 0xe0ee, 0x21, 0 + .dw 0x7400, 0xe0ee, 0xffff, 0xe0ee, 0x21, 0 + .dw 0x0400, 0xe0ef, 0x0fff, 0xe0ef, 0x21, 0 + .dw 0x1400, 0xe0ef, 0x1fff, 0xe0ef, 0x21, 0 + .dw 0x2400, 0xe0ef, 0x2fff, 0xe0ef, 0x21, 0 + .dw 0x3400, 0xe0ef, 0x3fff, 0xe0ef, 0x21, 0 + .dw 0x4400, 0xe0ef, 0x4fff, 0xe0ef, 0x21, 0 + .dw 0x5400, 0xe0ef, 0x5fff, 0xe0ef, 0x21, 0 + .dw 0x6400, 0xe0ef, 0x6fff, 0xe0ef, 0x21, 0 + .dw 0x7400, 0xe0ef, 0xffff, 0xe0ef, 0x21, 0 + .dw 0x0400, 0xe0f0, 0x0fff, 0xe0f0, 0x21, 0 + .dw 0x1400, 0xe0f0, 0x1fff, 0xe0f0, 0x21, 0 + .dw 0x2400, 0xe0f0, 0x2fff, 0xe0f0, 0x21, 0 + .dw 0x3400, 0xe0f0, 0x3fff, 0xe0f0, 0x21, 0 + .dw 0x4400, 0xe0f0, 0x4fff, 0xe0f0, 0x21, 0 + .dw 0x5400, 0xe0f0, 0x5fff, 0xe0f0, 0x21, 0 + .dw 0x6400, 0xe0f0, 0x6fff, 0xe0f0, 0x21, 0 + .dw 0x7400, 0xe0f0, 0xffff, 0xe0f0, 0x21, 0 + .dw 0x0400, 0xe0f1, 0x0fff, 0xe0f1, 0x21, 0 + .dw 0x1400, 0xe0f1, 0x1fff, 0xe0f1, 0x21, 0 + .dw 0x2400, 0xe0f1, 0x2fff, 0xe0f1, 0x21, 0 + .dw 0x3400, 0xe0f1, 0x3fff, 0xe0f1, 0x21, 0 + .dw 0x4400, 0xe0f1, 0x4fff, 0xe0f1, 0x21, 0 + .dw 0x5400, 0xe0f1, 0x5fff, 0xe0f1, 0x21, 0 + .dw 0x6400, 0xe0f1, 0x6fff, 0xe0f1, 0x21, 0 + .dw 0x7400, 0xe0f1, 0xffff, 0xe0f1, 0x21, 0 + .dw 0x0400, 0xe0f2, 0x0fff, 0xe0f2, 0x21, 0 + .dw 0x1400, 0xe0f2, 0x1fff, 0xe0f2, 0x21, 0 + .dw 0x2400, 0xe0f2, 0x2fff, 0xe0f2, 0x21, 0 + .dw 0x3400, 0xe0f2, 0x3fff, 0xe0f2, 0x21, 0 + .dw 0x4400, 0xe0f2, 0x4fff, 0xe0f2, 0x21, 0 + .dw 0x5400, 0xe0f2, 0x5fff, 0xe0f2, 0x21, 0 + .dw 0x6400, 0xe0f2, 0x6fff, 0xe0f2, 0x21, 0 + .dw 0x7400, 0xe0f2, 0xffff, 0xe0f2, 0x21, 0 + .dw 0x0400, 0xe0f3, 0x0fff, 0xe0f3, 0x21, 0 + .dw 0x1400, 0xe0f3, 0x1fff, 0xe0f3, 0x21, 0 + .dw 0x2400, 0xe0f3, 0x2fff, 0xe0f3, 0x21, 0 + .dw 0x3400, 0xe0f3, 0x3fff, 0xe0f3, 0x21, 0 + .dw 0x4400, 0xe0f3, 0x4fff, 0xe0f3, 0x21, 0 + .dw 0x5400, 0xe0f3, 0x5fff, 0xe0f3, 0x21, 0 + .dw 0x6400, 0xe0f3, 0x6fff, 0xe0f3, 0x21, 0 + .dw 0x7400, 0xe0f3, 0xffff, 0xe0f3, 0x21, 0 + .dw 0x0400, 0xe0f4, 0x0fff, 0xe0f4, 0x21, 0 + .dw 0x1400, 0xe0f4, 0x1fff, 0xe0f4, 0x21, 0 + .dw 0x2400, 0xe0f4, 0x2fff, 0xe0f4, 0x21, 0 + .dw 0x3400, 0xe0f4, 0x3fff, 0xe0f4, 0x21, 0 + .dw 0x4400, 0xe0f4, 0x4fff, 0xe0f4, 0x21, 0 + .dw 0x5400, 0xe0f4, 0x5fff, 0xe0f4, 0x21, 0 + .dw 0x6400, 0xe0f4, 0x6fff, 0xe0f4, 0x21, 0 + .dw 0x7400, 0xe0f4, 0xffff, 0xe0f4, 0x21, 0 + .dw 0x0400, 0xe0f5, 0x0fff, 0xe0f5, 0x21, 0 + .dw 0x1400, 0xe0f5, 0x1fff, 0xe0f5, 0x21, 0 + .dw 0x2400, 0xe0f5, 0x2fff, 0xe0f5, 0x21, 0 + .dw 0x3400, 0xe0f5, 0x3fff, 0xe0f5, 0x21, 0 + .dw 0x4400, 0xe0f5, 0x4fff, 0xe0f5, 0x21, 0 + .dw 0x5400, 0xe0f5, 0x5fff, 0xe0f5, 0x21, 0 + .dw 0x6400, 0xe0f5, 0x6fff, 0xe0f5, 0x21, 0 + .dw 0x7400, 0xe0f5, 0xffff, 0xe0f5, 0x21, 0 + .dw 0x0400, 0xe0f6, 0x0fff, 0xe0f6, 0x21, 0 + .dw 0x1400, 0xe0f6, 0x1fff, 0xe0f6, 0x21, 0 + .dw 0x2400, 0xe0f6, 0x2fff, 0xe0f6, 0x21, 0 + .dw 0x3400, 0xe0f6, 0x3fff, 0xe0f6, 0x21, 0 + .dw 0x4400, 0xe0f6, 0x4fff, 0xe0f6, 0x21, 0 + .dw 0x5400, 0xe0f6, 0x5fff, 0xe0f6, 0x21, 0 + .dw 0x6400, 0xe0f6, 0x6fff, 0xe0f6, 0x21, 0 + .dw 0x7400, 0xe0f6, 0xffff, 0xe0f6, 0x21, 0 + .dw 0x0400, 0xe0f7, 0x0fff, 0xe0f7, 0x21, 0 + .dw 0x1400, 0xe0f7, 0x1fff, 0xe0f7, 0x21, 0 + .dw 0x2400, 0xe0f7, 0x2fff, 0xe0f7, 0x21, 0 + .dw 0x3400, 0xe0f7, 0x3fff, 0xe0f7, 0x21, 0 + .dw 0x4400, 0xe0f7, 0x4fff, 0xe0f7, 0x21, 0 + .dw 0x5400, 0xe0f7, 0x5fff, 0xe0f7, 0x21, 0 + .dw 0x6400, 0xe0f7, 0x6fff, 0xe0f7, 0x21, 0 + .dw 0x7400, 0xe0f7, 0xffff, 0xe0f7, 0x21, 0 + .dw 0x0400, 0xe0f8, 0x0fff, 0xe0f8, 0x21, 0 + .dw 0x1400, 0xe0f8, 0x1fff, 0xe0f8, 0x21, 0 + .dw 0x2400, 0xe0f8, 0x2fff, 0xe0f8, 0x21, 0 + .dw 0x3400, 0xe0f8, 0x3fff, 0xe0f8, 0x21, 0 + .dw 0x4400, 0xe0f8, 0x4fff, 0xe0f8, 0x21, 0 + .dw 0x5400, 0xe0f8, 0x5fff, 0xe0f8, 0x21, 0 + .dw 0x6400, 0xe0f8, 0x6fff, 0xe0f8, 0x21, 0 + .dw 0x7400, 0xe0f8, 0xffff, 0xe0f8, 0x21, 0 + .dw 0x0400, 0xe0f9, 0x0fff, 0xe0f9, 0x21, 0 + .dw 0x1400, 0xe0f9, 0x1fff, 0xe0f9, 0x21, 0 + .dw 0x2400, 0xe0f9, 0x2fff, 0xe0f9, 0x21, 0 + .dw 0x3400, 0xe0f9, 0x3fff, 0xe0f9, 0x21, 0 + .dw 0x4400, 0xe0f9, 0x4fff, 0xe0f9, 0x21, 0 + .dw 0x5400, 0xe0f9, 0x5fff, 0xe0f9, 0x21, 0 + .dw 0x6400, 0xe0f9, 0x6fff, 0xe0f9, 0x21, 0 + .dw 0x7400, 0xe0f9, 0xffff, 0xe0f9, 0x21, 0 + .dw 0x0400, 0xe0fa, 0x0fff, 0xe0fa, 0x21, 0 + .dw 0x1400, 0xe0fa, 0x1fff, 0xe0fa, 0x21, 0 + .dw 0x2400, 0xe0fa, 0x2fff, 0xe0fa, 0x21, 0 + .dw 0x3400, 0xe0fa, 0x3fff, 0xe0fa, 0x21, 0 + .dw 0x4400, 0xe0fa, 0x4fff, 0xe0fa, 0x21, 0 + .dw 0x5400, 0xe0fa, 0x5fff, 0xe0fa, 0x21, 0 + .dw 0x6400, 0xe0fa, 0x6fff, 0xe0fa, 0x21, 0 + .dw 0x7400, 0xe0fa, 0xffff, 0xe0fa, 0x21, 0 + .dw 0x0400, 0xe0fb, 0x0fff, 0xe0fb, 0x21, 0 + .dw 0x1400, 0xe0fb, 0x1fff, 0xe0fb, 0x21, 0 + .dw 0x2400, 0xe0fb, 0x2fff, 0xe0fb, 0x21, 0 + .dw 0x3400, 0xe0fb, 0x3fff, 0xe0fb, 0x21, 0 + .dw 0x4400, 0xe0fb, 0x4fff, 0xe0fb, 0x21, 0 + .dw 0x5400, 0xe0fb, 0x5fff, 0xe0fb, 0x21, 0 + .dw 0x6400, 0xe0fb, 0x6fff, 0xe0fb, 0x21, 0 + .dw 0x7400, 0xe0fb, 0xffff, 0xe0fb, 0x21, 0 + .dw 0x0400, 0xe0fc, 0x0fff, 0xe0fc, 0x21, 0 + .dw 0x1400, 0xe0fc, 0x1fff, 0xe0fc, 0x21, 0 + .dw 0x2400, 0xe0fc, 0x2fff, 0xe0fc, 0x21, 0 + .dw 0x3400, 0xe0fc, 0x3fff, 0xe0fc, 0x21, 0 + .dw 0x4400, 0xe0fc, 0x4fff, 0xe0fc, 0x21, 0 + .dw 0x5400, 0xe0fc, 0x5fff, 0xe0fc, 0x21, 0 + .dw 0x6400, 0xe0fc, 0x6fff, 0xe0fc, 0x21, 0 + .dw 0x7400, 0xe0fc, 0xffff, 0xe0fc, 0x21, 0 + .dw 0x0400, 0xe0fd, 0x0fff, 0xe0fd, 0x21, 0 + .dw 0x1400, 0xe0fd, 0x1fff, 0xe0fd, 0x21, 0 + .dw 0x2400, 0xe0fd, 0x2fff, 0xe0fd, 0x21, 0 + .dw 0x3400, 0xe0fd, 0x3fff, 0xe0fd, 0x21, 0 + .dw 0x4400, 0xe0fd, 0x4fff, 0xe0fd, 0x21, 0 + .dw 0x5400, 0xe0fd, 0x5fff, 0xe0fd, 0x21, 0 + .dw 0x6400, 0xe0fd, 0x6fff, 0xe0fd, 0x21, 0 + .dw 0x7400, 0xe0fd, 0xffff, 0xe0fd, 0x21, 0 + .dw 0x0400, 0xe0fe, 0x0fff, 0xe0fe, 0x21, 0 + .dw 0x1400, 0xe0fe, 0x1fff, 0xe0fe, 0x21, 0 + .dw 0x2400, 0xe0fe, 0x2fff, 0xe0fe, 0x21, 0 + .dw 0x3400, 0xe0fe, 0x3fff, 0xe0fe, 0x21, 0 + .dw 0x4400, 0xe0fe, 0x4fff, 0xe0fe, 0x21, 0 + .dw 0x5400, 0xe0fe, 0x5fff, 0xe0fe, 0x21, 0 + .dw 0x6400, 0xe0fe, 0x6fff, 0xe0fe, 0x21, 0 + .dw 0x7400, 0xe0fe, 0xffff, 0xe0fe, 0x21, 0 + .dw 0x0400, 0xe0ff, 0x0fff, 0xe0ff, 0x21, 0 + .dw 0x1400, 0xe0ff, 0x1fff, 0xe0ff, 0x21, 0 + .dw 0x2400, 0xe0ff, 0x2fff, 0xe0ff, 0x21, 0 + .dw 0x3400, 0xe0ff, 0x3fff, 0xe0ff, 0x21, 0 + .dw 0x4400, 0xe0ff, 0x4fff, 0xe0ff, 0x21, 0 + .dw 0x5400, 0xe0ff, 0x5fff, 0xe0ff, 0x21, 0 + .dw 0x6400, 0xe0ff, 0x6fff, 0xe0ff, 0x21, 0 + .dw 0x7400, 0xe0ff, 0xffff, 0xe0ff, 0x21, 0 + .dw 0x0000, 0xe160, 0xffff, 0xe17f, 0x21, 0 + .dw 0x0000, 0xe1a0, 0xffff, 0xe1ff, 0x21, 0 + .dw 0x0000, 0xe4c0, 0xffff, 0xe4ff, 0x21, 0 + .dw 0x0000, 0xe5c0, 0xffff, 0xe5ff, 0x21, 0 + .dw 0x0000, 0xe6c0, 0xffff, 0xe6ff, 0x21, 0 + .dw 0x0000, 0xe740, 0xffff, 0xe7ff, 0x21, 0 + .dw 0x0000, 0xf001, 0xffff, 0xffff, 0x21, 0 + .dw 0x0000, 0x0000, 0x0000, 0x0000, 0x00, 0 +_table_end: diff --git a/sim/testsuite/sim/bfin/se_all32bitopcodes.lds b/sim/testsuite/sim/bfin/se_all32bitopcodes.lds new file mode 100644 index 0000000..6f37d65 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_all32bitopcodes.lds @@ -0,0 +1,16 @@ +MEMORY +{ + L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000 + L1_DATA : ORIGIN = 0xFF800000, LENGTH = 0x8000 + SDRAM : ORIGIN = 0x4000, LENGTH = 0x4000000 +} + +OUTPUT_ARCH(bfin) +ENTRY(__start) + +SECTIONS +{ + .text : { *(.text) } >L1_CODE + .text.usr : { *(.text.usr) } >SDRAM + .data : { *(.data) } >SDRAM +} diff --git a/sim/testsuite/sim/bfin/se_brtarget_stall.S b/sim/testsuite/sim/bfin/se_brtarget_stall.S new file mode 100644 index 0000000..066602b --- /dev/null +++ b/sim/testsuite/sim/bfin/se_brtarget_stall.S @@ -0,0 +1,462 @@ +//Original:/proj/frio/dv/testcases/seq/se_brtarget_stall/se_brtarget_stall.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000020 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + +///////////////////////////////////////////////////////////////////////////// +//////////////////////// CPLB Setup ///////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + // Setup CPLB for Data Memory starting at 0x00F0_0000; +WR_MMR(DCPLB_DATA0, 0x0003109d, p0, r0); // Page Size = 4MB + // CPLB_L1_CHLB = 1 + // CPLB_DIRTY = 1 + // CPLB_USER_RD = 1 + // CPLB_USER_WR = 1 + // CPLB_SUPV_WR = 1 + // CPLB_VALID = 1 + // + + // Setup CPLB Address to point to 0x00F0_0000 +WR_MMR_LABEL(DCPLB_ADDR0, data, p0, r0); + + // Enable CPLB's +WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1 + // ENDCPLB = 1 + // DMC = 11 + // Sync it! +CSYNC; + + + // Return to Supervisor Code +RAISE 15; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +NOP; + P0 = 0x0100 (Z); + P0.H = 0x00f0; +JUMP.S lab1; // Branch in EX1 + + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +lab1: + [ -- SP ] = ( R7:3 ); + P0 = 0x0200 (Z); + P0.H = 0x00f0; +RTI; +JUMP.S 8; // Branch in EX1 +NOP; +NOP; +NOP; + [ -- SP ] = ( R7:4 ); + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +data: +.section MEM_0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_0x00F00200,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_bug_ui.S b/sim/testsuite/sim/bfin/se_bug_ui.S new file mode 100644 index 0000000..4922d97 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_bug_ui.S @@ -0,0 +1,296 @@ +//Original:/proj/frio/dv/testcases/seq/se_bug_ui/se_bug_ui.dsp +// Description: 16 bit special cases Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // count of UI's will be in r5, which was initialized to 0 by header + + .dw 0x41FD ; + .dw 0x41FE ; + .dw 0x41FF ; + .dw 0x9040 ; + .dw 0x9049 ; + .dw 0x9052 ; + .dw 0x905B ; + .dw 0x9064 ; + .dw 0x906D ; + .dw 0x9076 ; + .dw 0x907F ; + .dw 0x90C0 ; + .dw 0x90C9 ; + .dw 0x90D2 ; + .dw 0x90DB ; + .dw 0x90E4 ; + .dw 0x90ED ; + .dw 0x90F6 ; + .dw 0x90FF ; + .dw 0x9180 ; + + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +CHECKREG(r5, 20); // count of all 16 bit UI's. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 16 bit illegal opcode handler - skips bad instruction + + // handler MADE LEAN and destructive so test runs more quckly + // se_undefinedinstruction1.dsp tests using a "nice" handler + +// [--sp] = ASTAT; // save what we damage +// [--sp] = (r7 - r6); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + + R6 = 0x22; // Also accept illegal insn combo +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + +dbg_fail; + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + R7 += 2; // skip offending 16 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: +// (r7 - r6) = [sp++]; +// ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_bug_ui2.S b/sim/testsuite/sim/bfin/se_bug_ui2.S new file mode 100644 index 0000000..5e0af4c --- /dev/null +++ b/sim/testsuite/sim/bfin/se_bug_ui2.S @@ -0,0 +1,296 @@ +//Original:/proj/frio/dv/testcases/seq/se_bug_ui2/se_bug_ui2.dsp +// Description: 16 bit special cases Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // count of UI's will be in r5, which was initialized to 0 by header + +// .dw 0x41FD ; +// .dw 0x41FE ; +// .dw 0x41FF ; + .dw 0x9040 ; + .dw 0x9049 ; + .dw 0x9052 ; + .dw 0x905B ; + .dw 0x9064 ; + .dw 0x906D ; + .dw 0x9076 ; + .dw 0x907F ; + .dw 0x90C0 ; + .dw 0x90C9 ; + .dw 0x90D2 ; + .dw 0x90DB ; + .dw 0x90E4 ; + .dw 0x90ED ; + .dw 0x90F6 ; + .dw 0x90FF ; + .dw 0x9180 ; + + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +CHECKREG(r5, 17); // count of all 16 bit UI's. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 16 bit illegal opcode handler - skips bad instruction + + // handler MADE LEAN and destructive so test runs more quckly + // se_undefinedinstruction1.dsp tests using a "nice" handler + +// [--sp] = ASTAT; // save what we damage +// [--sp] = (r7 - r6); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + + R6 = 0x22; // Also accept illegal insn combo +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + +dbg_fail; + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + R7 += 2; // skip offending 16 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: +// (r7 - r6) = [sp++]; +// ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_bug_ui3.S b/sim/testsuite/sim/bfin/se_bug_ui3.S new file mode 100644 index 0000000..3c0ff77 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_bug_ui3.S @@ -0,0 +1,300 @@ +//Original:/proj/frio/dv/testcases/seq/se_bug_ui3/se_bug_ui3.dsp +// Description: 32 bit special cases Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // count of UI's will be in r5, which was initialized to 0 by header + .dw 0xC0E0 ; + .dw 0x2000 ; + .dw 0xC140 ; + .dw 0x2000 ; + .dw 0xC1A0 ; + .dw 0x2000 ; + .dw 0xC1C0 ; + .dw 0x2000 ; + .dw 0xC1E0 ; + .dw 0x2000 ; + + .dw 0xC0E4 ; + .dw 0x0 ; + .dw 0xC144 ; + .dw 0x0 ; + .dw 0xC1A4 ; + .dw 0x0 ; + .dw 0xC1C4 ; + .dw 0x0 ; + .dw 0xC1E4 ; + .dw 0x0 ; + + .dw 0xC0E4 ; + .dw 0x2000 ; + .dw 0xC144 ; + .dw 0x2000 ; + .dw 0xC1A4 ; + .dw 0x2000 ; + .dw 0xC1C4 ; + .dw 0x2000 ; + .dw 0xC1E4 ; + .dw 0x2000 ; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +CHECKREG(r5, 15); // count of all 16 bit UI's. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 32 bit illegal opcode handler - skips bad instruction + + // handler MADE LEAN and destructive so test runs more quckly + // se_undefinedinstruction1.dsp tests using a "nice" handler + +// [--sp] = ASTAT; // save what we damage +// [--sp] = (r7 - r6); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF !CC JUMP OUT; // If EXCAUSE != 0x21 then leave + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + R7 += 4; // skip offending 32 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: +// (r7 - r6) = [sp++]; +// ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_cc2stat_haz.S b/sim/testsuite/sim/bfin/se_cc2stat_haz.S new file mode 100644 index 0000000..7bb1a24 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_cc2stat_haz.S @@ -0,0 +1,632 @@ +//Original:/proj/frio/dv/testcases/seq/se_cc2stat_haz/se_cc2stat_haz.dsp +// Description: +// Verify CC hazards under the following condition: +// +// (1a) cc2stat (that modifies CC) followed by that uses CC +// (1b) same as (1a) but kill cc2stat instruction in WB +// +// (2a) cc2stat (that modifies CC) followed by conditional branch (predicted) +// (2b) same as (2a) but kill cc2stat instruction in WB +// +// (3a) cc2stat (that modifies CC) followed by conditional branch (mispredicted) +// (3b) same as (3a) but kill cc2stat instruction in WB +// +// (4a) cc2stat (that modifies CC) followed by testset +// (4b) same as (4a) but kill cc2stat instruction in WB +// +// (5a) cc2stat (that modifies CC) followed by dag instruction that modifies CC +// (5b) same as (5a) but kill cc2stat instruction in WB +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// ---------------------------------------------------------------- +// Include Files +// ---------------------------------------------------------------- + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +// ---------------------------------------------------------------- +// Defines +// ---------------------------------------------------------------- + +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_1 // +#endif + +// ---------------------------------------------------------------- +// Reset ISR +// - set the processor operating modes +// - initialize registers +// - etc ... +// ---------------------------------------------------------------- + +RST_ISR: + + // Initialize data registers + //INIT_R_REGS(0); + R7 = 0; + R6 = 0; + R5 = 0; + R4 = 0; + R3 = 0; + R2 = 0; + R1 = 0; + R0 = 0; + + // Initialize pointer registers +INIT_P_REGS(0); + + // Initialize address registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the address of the checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Inhibit events during MMR writes +CLI R1; + + // Setup user stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup kernel stack +LD32_LABEL(sp, KSTACK); + + // Setup frame pointer +FP = SP; + + // Setup event vector table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (EVT0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (EVT1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (EVT2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (EVT3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // EVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (EVT5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (EVT6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Set the EVT_OVERRIDE MMR +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + // Disable L1 data cache +WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0); + + // Mask interrupts (*) + R1 = -1; + + // Wait for MMR writes to finish +CSYNC; + + // Re-enable events +STI R1; + + // Reset accumulator registers + A0 = 0; + A1 = 0; + + // Reset loop counters to deterministic values + R0 = 0 (Z); + +LT0 = R0; +LB0 = R0; +LC0 = R0; +LT1 = R0; +LB1 = R0; +LC1 = R0; + + // Reset other internal regs +ASTAT = R0; +SYSCFG = R0; +RETS = R0; + + // Setup the test to run in USER mode +LD32_LABEL(r0, USER_CODE); +RETI = R0; + + // Setup the test to run in SUPERVISOR mode + // Comment the following line for a USER mode test +JUMP.S SUPERVISOR_CODE; +RTI; + +SUPERVISOR_CODE: + // Load IVG15 general handler (Int15) with MAIN_CODE +LD32_LABEL(p1, MAIN_CODE); + +LD32(p0, EVT15); + +CLI R1; + [ P0 ] = P1; +CSYNC; +STI R1; + + // Take Int15 which branch to MAIN_CODE after RTI +RAISE 15; +RTI; + +USER_CODE: + // Setup the stack pointer and the frame pointer +LD32_LABEL(sp, USTACK); +FP = SP; +JUMP.S MAIN_CODE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// ISR Table +// ---------------------------------------------------------------- + + +// ---------------------------------------------------------------- +// EMU ISR +// ---------------------------------------------------------------- + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// NMI ISR +// ---------------------------------------------------------------- + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// EXC ISR +// ---------------------------------------------------------------- + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// HWE ISR +// ---------------------------------------------------------------- + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// TMR ISR +// ---------------------------------------------------------------- + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV7 ISR +// ---------------------------------------------------------------- + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV8 ISR +// ---------------------------------------------------------------- + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV9 ISR +// ---------------------------------------------------------------- + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV10 ISR +// ---------------------------------------------------------------- + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV11 ISR +// ---------------------------------------------------------------- + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV12 ISR +// ---------------------------------------------------------------- + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV13 ISR +// ---------------------------------------------------------------- + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV14 ISR +// ---------------------------------------------------------------- + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV15 ISR +// ---------------------------------------------------------------- + + IGV15_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// Main Code +// ---------------------------------------------------------------- + + +MAIN_CODE: + // Enable interrupts in SUPERVISOR mode + // Comment the following line for a USER mode test + [ -- SP ] = RETI; + + // Start of the program code + R0 = 0; + R1 = 1; + R2 = 2; + + // Verify CC hazards under the following condition: + // + // (1a) cc2stat (that modifies CC) followed by that uses CC + A0 = 0; + A1 = R1; +CC = R0 < R2; +CC = AV0; + A0 = BXORSHIFT( A0 , A1, CC ); + R7 = CC; CHECKREG(R7, 0); + R6 = A0; CHECKREG(R6, 0); + R6 = A0.X; CHECKREG(R6, 0); + R7 = A1; CHECKREG(R7, 1); + R7 = A1.X; CHECKREG(R7, 0); + + // (1b) same as (1a) but kill cc2stat instruction in WB + A0 = R1; + A1 = R1; +CC = R0 < R2; +EXCPT 3; +CC = AV0; + A0 = BXORSHIFT( A0 , A1, CC ); + R7 = CC; CHECKREG(R7, 0); + R6 = A0; CHECKREG(R6, 3); + R6 = A0.X; CHECKREG(R6, 0); + R7 = A1; CHECKREG(R7, 1); + R7 = A1.X; CHECKREG(R7, 0); + + // (2a) cc2stat (that modifies CC) followed by conditional branch (predicted) + R3 = 0; + A0 = 0; + A1 = R1; +CC = R0 < R2; +CC = AV0; +IF !CC JUMP INC_R3_TO_10 (BP); + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; +INC_R3_TO_10: + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + + // (2b) same as (2a) but kill cc2stat instruction in WB + A0 = 0; + A1 = R1; +CC = R0 < R2; +EXCPT 3; +CC = AV0; +IF !CC JUMP INC_R3_TO_20 (BP); + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; +INC_R3_TO_20: + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + R3 += 1; + + // (3a) cc2stat (that modifies CC) followed by conditional branch (mispredicted) + A0 = 0; + A1 = R1; +CC = R0 < R2; +CC = AV0; +IF CC JUMP INC_R3_TO_20 (BP); + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + + // (3b) same as (3a) but kill cc2stat instruction in WB + A0 = 0; + A1 = R1; +CC = R0 < R2; +EXCPT 3; +CC = AV0; +IF CC JUMP INC_R3_TO_20 (BP); + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + R3 += 2; + +CHECKREG(r3, 60); + +dbg_pass; + + // (4a) cc2stat (that modifies CC) followed by testset +LD32(p0, DATA_ADDR_3); //LD32(p0, 0xff000000); +LD32(p1, DATA_ADDR_2); //LD32(p1, 0xffe00000); + [ P0 ] = R0; + + A0 = 0; + A1 = R1; +CC = R0 < R2; +CC = AV0; +QUERY_0: +TESTSET ( P0 ); +IF !CC JUMP QUERY_0; + [ P0 ] = R1; +CHECKMEM32(DATA_ADDR_3, 1); //CHECKMEM32(0xff000000, 1); + [ P0 ] = R0; +CHECKMEM32(DATA_ADDR_3, 0); //CHECKMEM32(0xff000000, 0); + + // (4b) same as (4a) but kill cc2stat instruction in WB + A0 = 0; + A1 = R1; +CC = R0 < R2; +EXCPT 3; +CC = AV0; +QUERY_1: +TESTSET ( P0 ); +IF !CC JUMP QUERY_1; + [ P0 ] = R2; +CHECKMEM32(DATA_ADDR_3, 2); //CHECKMEM32(0xff000000, 2); + [ P0 ] = R0; +CHECKMEM32(DATA_ADDR_3, 0); //CHECKMEM32(0xff000000, 0); + + // (5a) cc2stat (that modifies CC) followed by dag instruction that modifies CC + A0 = 0; + A1 = R1; +CC = R0 < R2; +CC = AV0; +CC = P0 < P1; + + // (5b) same as (5a) but kill cc2stat instruction in WB + A0 = 0; + A1 = R1; +CC = R0 < R2; +EXCPT 3; +CC = AV0; +CC = P0 < P1; + + +END: +dbg_pass; + +// ---------------------------------------------------------------- +// Data Segment +// - define kernel and user stacks +// ---------------------------------------------------------------- + +.data + DATA: + .space (STACKSIZE); + + .space (STACKSIZE); + KSTACK: + + .space (STACKSIZE); + USTACK: diff --git a/sim/testsuite/sim/bfin/se_cc_kill.S b/sim/testsuite/sim/bfin/se_cc_kill.S new file mode 100644 index 0000000..5d0aead --- /dev/null +++ b/sim/testsuite/sim/bfin/se_cc_kill.S @@ -0,0 +1,480 @@ +//Original:/proj/frio/dv/testcases/seq/se_cc_kill/se_cc_kill.dsp +// Description: +// Verify CC kill under the following condition: +// +// (1) CC = AZ killed in WB +// (2) CC = AN killed in WB +// (3) CC = AC killed in WB +// (4) CC = AV0 killed in WB +// (5) CC = AV1 killed in WB +// (6) CC = AQ killed in WB +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// ---------------------------------------------------------------- +// Include Files +// ---------------------------------------------------------------- + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +// ---------------------------------------------------------------- +// Defines +// ---------------------------------------------------------------- + +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_1 // +#endif + + +// ---------------------------------------------------------------- +// Reset ISR +// - set the processor operating modes +// - initialize registers +// - etc ... +// ---------------------------------------------------------------- + +RST_ISR: + + // Initialize data registers + //INIT_R_REGS(0); + R7 = 0; + R6 = 0; + R5 = 0; + R4 = 0; + R3 = 0; + R2 = 0; + R1 = 0; + R0 = 0; + + // Initialize pointer registers +INIT_P_REGS(0); + + // Initialize address registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the address of the checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Inhibit events during MMR writes +CLI R1; + + // Setup user stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup kernel stack +LD32_LABEL(sp, KSTACK); + + // Setup frame pointer +FP = SP; + + // Setup event vector table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (EVT0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (EVT1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (EVT2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (EVT3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // EVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (EVT5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (EVT6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Set the EVT_OVERRIDE MMR +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + // Disable L1 data cache +WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0); + + // Mask interrupts (*) + R1 = -1; + + // Wait for MMR writes to finish +CSYNC; + + // Re-enable events +STI R1; + + // Reset loop counters to deterministic values + R0 = 0 (Z); + +LT0 = R0; +LB0 = R0; +LC0 = R0; +LT1 = R0; +LB1 = R0; +LC1 = R0; + + // Reset other internal regs +ASTAT = R0; +SYSCFG = R0; +RETS = R0; + + // Setup the test to run in USER mode +LD32_LABEL(r0, USER_CODE); +RETI = R0; + + // Setup the test to run in SUPERVISOR mode + // Comment the following line for a USER mode test +JUMP.S SUPERVISOR_CODE; +RTI; + +SUPERVISOR_CODE: + // Load IVG15 general handler (Int15) with MAIN_CODE +LD32_LABEL(p1, MAIN_CODE); + +LD32(p0, EVT15); + +CLI R1; + [ P0 ] = P1; +CSYNC; +STI R1; + + // Take Int15 which branch to MAIN_CODE after RTI +RAISE 15; +RTI; + +USER_CODE: + // Setup the stack pointer and the frame pointer +LD32_LABEL(sp, USTACK); +FP = SP; +JUMP.S MAIN_CODE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// ISR Table +// ---------------------------------------------------------------- + + +// ---------------------------------------------------------------- +// EMU ISR +// ---------------------------------------------------------------- + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// NMI ISR +// ---------------------------------------------------------------- + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// EXC ISR +// ---------------------------------------------------------------- + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// HWE ISR +// ---------------------------------------------------------------- + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// TMR ISR +// ---------------------------------------------------------------- + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV7 ISR +// ---------------------------------------------------------------- + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV8 ISR +// ---------------------------------------------------------------- + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV9 ISR +// ---------------------------------------------------------------- + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV10 ISR +// ---------------------------------------------------------------- + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV11 ISR +// ---------------------------------------------------------------- + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV12 ISR +// ---------------------------------------------------------------- + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV13 ISR +// ---------------------------------------------------------------- + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV14 ISR +// ---------------------------------------------------------------- + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// IGV15 ISR +// ---------------------------------------------------------------- + + IGV15_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +// ---------------------------------------------------------------- +// Main Code +// ---------------------------------------------------------------- + + +MAIN_CODE: + // Enable interrupts in SUPERVISOR mode + // Comment the following line for a USER mode test + [ -- SP ] = RETI; + + // Start of the program code + + // Verify CC kill under the following condition: + + // (1) CC = AZ killed in WB +CC = R2 < R3; +EXCPT 3; +CC = AZ; + + // (2) CC = AN killed in WB +CC = R2 == R3; +EXCPT 3; +CC = AN; + + // (3) CC = AC killed in WB +CC = R2 < R3; +EXCPT 3; +CC = AC0; + + // (4) CC = AV0 killed in WB +CC = R2 == R3; +EXCPT 3; +CC = AV0; + + // (5) CC = AV1 killed in WB +CC = R2 == R3; +EXCPT 3; +CC = AV1; + + // (6) CC = AQ killed in WB +CC = R2 == R3; +EXCPT 3; +CC = AQ; + + +END: +dbg_pass; + +// ---------------------------------------------------------------- +// Data Segment +// - define kernel and user stacks +// ---------------------------------------------------------------- + +.data + DATA: + .space (STACKSIZE); + + .space (STACKSIZE); + KSTACK: + + .space (STACKSIZE); + USTACK: diff --git a/sim/testsuite/sim/bfin/se_cof.S b/sim/testsuite/sim/bfin/se_cof.S new file mode 100644 index 0000000..4802cce --- /dev/null +++ b/sim/testsuite/sim/bfin/se_cof.S @@ -0,0 +1,424 @@ +//Original:/proj/frio/dv/testcases/seq/se_cof/se_cof.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +NOP; + //lz(p0) = 0x0004; + //h(p0) = 0xffe0; +LD32(p0, DMEM_CONTROL); +CSYNC; + R0 = [ P0 ]; // MMR load will Stall +JUMP.S lab1; // Branch in EX1 + + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +lab1: + [ -- SP ] = ( R7:3 ); +IF !CC JUMP 2; // Mispredicted branch; +NOP; +JUMP.S lab2; // Branch in EX1 +NOP; +NOP; +NOP; +NOP; + +lab2: +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_3 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_3 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_event_quad.S b/sim/testsuite/sim/bfin/se_event_quad.S new file mode 100644 index 0000000..0a1611b --- /dev/null +++ b/sim/testsuite/sim/bfin/se_event_quad.S @@ -0,0 +1,436 @@ +//Original:/proj/frio/dv/testcases/seq/se_event_quad/se_event_quad.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + + P0 = 0x5 (Z); + P1 = 0xa (Z); + + P2 = 0x0100 (Z); + P2.H = 0x00f0; + R0 = 0xf0f0 (Z); + R0.H = 0x0f0f; + +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; + +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_excpt_dagprotviol.S b/sim/testsuite/sim/bfin/se_excpt_dagprotviol.S new file mode 100644 index 0000000..48e496b --- /dev/null +++ b/sim/testsuite/sim/bfin/se_excpt_dagprotviol.S @@ -0,0 +1,281 @@ +//Original:/proj/frio/dv/testcases/seq/se_excpt_dagprotviol/se_excpt_dagprotviol.dsp +// Description: EXCPT instruction combined with DAG Misaligned Access +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x100 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +RETI = r0; // prevent Xs later on +RETX = r0; +RETN = r0; +RETE = r0; + + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +FP = SP; +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests +// [--sp] = RETI; // enable interrupts in supervisor mode + + R0 = 0; + R1 = -1; +LD32_LABEL(p1, USTACK); + P1 += 1; // misalign it + +EXCPT 2; // the RAISE should not prevent the EXCPT from being taken + R2 = [ P1 ]; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + +CHECKREG(r5, 2); // check the flag + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 instruction +CC = r7 == r6; +IF CC JUMP EXCPT2; + + R6 = 0x24; // EXCAUSE 0x24 means DAG misalign +CC = r7 == r6; +IF CC JUMP DGPROTVIOL; + +JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop + +EXCPT2: + R5 = 1; // Set a Flag +JUMP.S OUT; + +DGPROTVIOL: + R7 = RETX; // Fix up return address + + R7 += 2; // skip offending 16 bit instruction + +RETX = r7; // and put back in RETX + + R5 <<= 1; // Alter Global Flag + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_excpt_ifprotviol.S b/sim/testsuite/sim/bfin/se_excpt_ifprotviol.S new file mode 100644 index 0000000..50207fc --- /dev/null +++ b/sim/testsuite/sim/bfin/se_excpt_ifprotviol.S @@ -0,0 +1,280 @@ +//Original:/proj/frio/dv/testcases/seq/se_excpt_ifprotviol/se_excpt_ifprotviol.dsp +// Description: EXCPT instruction and IF Prot Viol priority +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x100 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +RETI = r0; // prevent Xs later on +RETX = r0; +RETN = r0; +RETE = r0; + + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +FP = SP; +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests +// [--sp] = RETI; // enable interrupts in supervisor mode + + R0 = 0; + R1 = -1; + + +EXCPT 2; // the RAISE should not prevent the EXCPT from being taken +RAISE 15; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + +CHECKREG(r5, 2); // check the flag + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 instruction +CC = r7 == r6; +IF CC JUMP EXCPT2; + + R6 = 0x2E; // EXCAUSE 0x2E means Illegal Use Supervisor Resource +CC = r7 == r6; +IF CC JUMP IFPROTVIOL; + +JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop + +EXCPT2: + R5 = 1; // Set a Flag +JUMP.S OUT; + +IFPROTVIOL: + R7 = RETX; // Fix up return address + + R7 += 2; // skip offending 16 bit instruction + +RETX = r7; // and put back in RETX + + R5 <<= 1; // Alter Global Flag + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_excpt_ssstep.S b/sim/testsuite/sim/bfin/se_excpt_ssstep.S new file mode 100644 index 0000000..5cb5558 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_excpt_ssstep.S @@ -0,0 +1,290 @@ +//Original:/proj/frio/dv/testcases/seq/se_excpt_ssstep/se_excpt_ssstep.dsp +// Description: EXCPT instruction vs Single Step Exception Priority +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +//include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + + R0 = 1; + +SYSCFG = r0; // Enable Supervisor Single Step + +CHECK_INIT_DEF(p2); //CHECK_INIT(p2, 0x2000); + + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// + +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests +// [--sp] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + R0 = 0; + R0 = 0; + R0 = 0; + R0 = 0; + R0 = 0; +EXCPT 15; // single step shouldn't happen for this. + R0 = 0; + R0 = 0; + R0 = 0; + R0 = 0; + R0 = 0; + +EXCPT 3; // turn off single step via handler + +CHECKREG(r4, 1); // one EXCPT 15 instruction +CHECKREG(r5, 14); // 14 instructions are executed before we disable single step + + + // PUT YOUR TEST HERE! + + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x10; // EXCAUSE 0x10 means Single Step +CC = r7 == r6; +IF CC JUMP SINGLESTEP (BP); // Go to Single Step Handler + + R6 = 15; // EXCAUSE 15 means EXCPT 15 instruction +CC = r7 == r6; +IF CC JUMP EXCPT15 (BP); + +SYSCFG = r0; // otherwise must be an EXCPT, so turn off singlestep + +JUMP.S OUT; + +EXCPT15: + R4 += 1; // R4 counts EXCPT 15s +JUMP.S OUT; + +SINGLESTEP: + R5 += 1; // R5 counts single step events + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_illegalcombination.S b/sim/testsuite/sim/bfin/se_illegalcombination.S new file mode 100644 index 0000000..0fe5f27 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_illegalcombination.S @@ -0,0 +1,622 @@ +//Original:/proj/frio/dv/testcases/seq/se_illegalcombination/se_illegalcombination.dsp +// Description: Multi-issue Illegal Combinations +# mach: bfin +# sim: --environment operating +# xfail: "missing a few checks; hardware doesnt seem to match PRM?" bfin-* + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x100 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + A0 = 0; // reset accumulators + A1 = 0; + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // PUT YOUR TEST HERE! + +// Slot 0 can only be LDST LOAD with search instruction (2 instrs) + + + .dw 0xcc0d //(R0,R1)=SEARCH R2(GT)||[P0]=R3||NOP; + .dw 0x0210 + .dw 0x9303 + .dw 0x0000 +// (r0,r1) = search r2 gt, nop, r3 = [i0]; // nop supposedly ok +( R0 , R1 ) = SEARCH R2 (GT) || R4 = [ P0 ++ P1 ] || NOP; + +// only nop or dspLDST allowed in slot 1 (1 instr) + + // a0 = r0, nop, [p0] = r3; + .dw 0xCC09; // can't assemble + .dw 0x2000; + .dw 0x0000; + .dw 0x9303; + +// Slot 0 illegal opcodes (1 instr) + + // a0 = r0, raise 15, nop; + .dw 0xCC09; // can't assemble + .dw 0x2000; + .dw 0x009F; + .dw 0x0000; + +// multiissue with two stores (8 instrs) + + + .dw 0xcc09 //A0=R0||W[P3]=R5.L||[I0]=R4; + .dw 0x2000 + .dw 0x8b5b + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[I2]=R2||[I0]=R4; + .dw 0x2000 + .dw 0x9f12 + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[P3]=R0||[I0]=R4; + .dw 0x2000 + .dw 0x9318 + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[P3]=P0||[I0]=R4; + .dw 0x2000 + .dw 0x9358 + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[FP+-36]=R0||[I0]=R4; + .dw 0x2000 + .dw 0xbb70 + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[FP+-48]=P0||[I0]=R4; + .dw 0x2000 + .dw 0xbb48 + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[P3+0x20]=R1||[I0]=R4; + .dw 0x2000 + .dw 0xb219 + .dw 0x9f04 + + .dw 0xcc09 //A0=R0||[P3+0x20]=P1||[I0]=R4; + .dw 0x2000 + .dw 0xbe19 + .dw 0x9f04 + +// multiissue two instructions can't modify same ireg (6 instrs) + + + .dw 0xcc09 //A0=R0||I0+=M1(BREV)||R1.L=W[I0++]; + .dw 0x2000 + .dw 0x9ee4 + .dw 0x9c21 + + .dw 0xcc09 //A0=R0||I1-=M3||R0=[I1++M3]; + .dw 0x2000 + .dw 0x9e7d + .dw 0x9de8 + + .dw 0xcc09 //A0=R0||I2+=2||W[I2++]=R0.L; + .dw 0x2000 + .dw 0x9f62 + .dw 0x9e30 + + .dw 0xcc09 //A0=R0||I3-=4||[I3++M1]=R7; + .dw 0x2000 + .dw 0x9f6f + .dw 0x9fbf + + .dw 0xcc09 //A0=R0||R1.L=W[I1++]||W[I1++]=R2.L; + .dw 0x2000 + .dw 0x9c29 + .dw 0x9e2a + + .dw 0xcc09 //A0=R0||[I2++M3]=R7||R6=[I2++M0]; + .dw 0x2000 + .dw 0x9ff7 + .dw 0x9d96 + +// multiissue two instructions can't load same dreg (9 instrs) + + + .dw 0xcc09 //A0=R0||R0.L=W[P0++P2]||R0=[I0++]; + .dw 0x2000 + .dw 0x8210 + .dw 0x9c00 + + .dw 0xcc09 //A0=R0||R1=W[P0++P3](X)||R1.L=W[I2]; + .dw 0x2000 + .dw 0x8e58 + .dw 0x9d31 + + .dw 0xcc09 //A0=R0||R2=W[P0++P3](X)||R2=[I1++M3]; + .dw 0x2000 + .dw 0x8e98 + .dw 0x9dea + + .dw 0xcc09 //A0=R0||R3=[I0++]||R3=[I1++]; + .dw 0x2000 + .dw 0x9c03 + .dw 0x9c0b + + .dw 0xcc09 //A0=R0||R4.L=W[I2]||R4.L=W[I3]; + .dw 0x2000 + .dw 0x9d34 + .dw 0x9d3c + + .dw 0xcc09 //A0=R0||R5=[I1++M3]||R5.L=W[I2++]; + .dw 0x2000 + .dw 0x9ded + .dw 0x9c35 + + .dw 0xcc09 //A0=R0||R6=[P0]||R6=[I0++]; + .dw 0x2000 + .dw 0x9106 + .dw 0x9c06 + + .dw 0xcc09 //A0=R0||R7=[FP+-56]||R7.L=W[I1]; + .dw 0x2000 + .dw 0xb927 + .dw 0x9d2f + + .dw 0xcc09 //A0=R0||R0=W[P1+0x1e](X)||R0=[I0++]; + .dw 0x2000 + .dw 0xabc8 + .dw 0x9c00 + +// dsp32alu instructions with one dest and slot 0 multi with same dest (1 ins) + + + .dw 0xcc00 //R0=R2+|+R3||R0=W[P1+0x1e](X)||NOP; + .dw 0x0013 + .dw 0xabc8 + .dw 0x0000 + // other slot 0 dreg cases already covered + +// dsp32alu one dest and slot 1 multi with same dest (1 ins) + + + .dw 0xcc18 //R1=BYTEPACK(R4,R5)||NOP||R1.L=W[I2]; + .dw 0x0225 + .dw 0x0000 + .dw 0x9d31 + // other slot 1 dreg dest cases already covered + +// dsp32alu dual dests and slot 0 multi with either same dest (2 instrs) + + + .dw 0xcc18 //(R2,R3)=BYTEUNPACKR1:0||R2=W[P0++P3](X)||NOP; + .dw 0x4680 + .dw 0x8e98 + .dw 0x0000 + + .dw 0xcc01 //R2=R2+|+R3,R3=R2-|-R3||R3=[P3]||NOP; + .dw 0x0693 + .dw 0x911b + .dw 0x0000 + +// dsp32alu dual dests and slot 1 multi with either same dest (2 instrs) + + + .dw 0xcc18 //(R4,R5)=BYTEUNPACKR1:0||NOP||R4=[I1++M3]; + .dw 0x4b00 + .dw 0x0000 + .dw 0x9dec + + .dw 0xcc01 //R4=R2+|+R3,R5=R2-|-R3||NOP||R5.L=W[I2++]; + .dw 0x0b13 + .dw 0x0000 + .dw 0x9c35 + +// dsp32shift one dest and slot 0 multi with same dest (1 instruction) + + + .dw 0xce0d //R6=ALIGN8(R4,R5)||R6=[P0]||NOP; + .dw 0x0c2c + .dw 0x9106 + .dw 0x0000 + +// dsp32shift one dest and slot 1 multi with same dest (1 instruction) + + + .dw 0xce00 //R7.L=ASHIFTR0.HBYR7.L||NOP||R7.L=W[I1]; + .dw 0x1e38 + .dw 0x0000 + .dw 0x9d2f + +// dsp32shift two dests and slot 0 multi with either same dest (2 instrs) + + + .dw 0xce08 //BITMUX(R0,R1,A0)(ASR)||R0.L=W[P0++P2]||NOP; + .dw 0x0001 + .dw 0x8210 + .dw 0x0000 + + .dw 0xce08 //BITMUX(R2,R3,A0)(ASL)||R3=[I0++]||NOP; + .dw 0x4013 + .dw 0x9c03 + .dw 0x0000 + +// dsp32shift two dests and slot 1 multi with either same dest (2 instrs) + + + .dw 0xce08 //BITMUX(R4,R5,A0)(ASR)||NOP||R4.H=W[I3]; + .dw 0x0025 + .dw 0x0000 + .dw 0x9d5c + + .dw 0xce08 //BITMUX(R6,R7,A0)(ASL)||NOP||R7.L=W[I1]; + .dw 0x4037 + .dw 0x0000 + .dw 0x9d2f + +// dsp32shiftimm one dest and slot 0 with same dest (1 instr) + + + .dw 0xce80 //R1.L=R0.H<<0x7||R1=W[P0++P3](X)||NOP; + .dw 0x1238 + .dw 0x8e58 + .dw 0x0000 + +// dsp32shiftimm one dest and slot 1 with same dest (1 instr) + + + .dw 0xce81 //R5=R2<<0x9(V)||NOP||R5.L=W[I2++]; + .dw 0x0a4a + .dw 0x0000 + .dw 0x9c35 + +// dsp32mac one dest and slot 0 multi with same dest (1 inst) + + + .dw 0xc805 //A0+=R1.H*R0.L,R6.H=(A1+=R1.L*R0.H)||R6=W[P0++P3](X)||NOP; + .dw 0x4d88 + .dw 0x8f98 + .dw 0x0000 + +// dsp32mult one dest and slot 0 multi with same dest (1 inst) + + + .dw 0xca04 //R7.H=R3.L*R4.H||R7=[FP+-56]||NOP; + .dw 0x41dc + .dw 0xb927 + .dw 0x0000 + +// dsp32 mac one dest and slot 1 multi with same dest (1 inst) + + + .dw 0xc805 //A0+=R1.H*R0.L,R0.H=(A1+=R1.L*R0.H)||NOP||R0=[I0++]; + .dw 0x4c08 + .dw 0x0000 + .dw 0x9c00 + +// dsp32mult one dest and slot 1 multi with same dest (1 inst) + + + .dw 0xca04 //R1.H=R3.L*R4.H||NOP||R1.H=W[I1]; + .dw 0x405c + .dw 0x0000 + .dw 0x9d49 + +// dsp32mac write to register pair and slot 0 same dest - even (1 instr) + + + .dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||R2=W[P0++P3](X)||NOP; + .dw 0x6c88 + .dw 0x8e98 + .dw 0x0000 + +// dsp32mult write to register pair and slot 0 same dest - even (1 instr) + + + .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R4=[P0++P1]||NOP; + .dw 0x6508 + .dw 0x8108 + .dw 0x0000 + +// dsp32mac write to register pair and slot 1 same dest - even (1 instr) + + + .dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||NOP||R2=[I1++M3]; + .dw 0x6c88 + .dw 0x0000 + .dw 0x9dea + +// dsp32mult write to register pair and slot 1 same dest - even (1 instr) + + + .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R4=[I1++M3]; + .dw 0x6508 + .dw 0x0000 + .dw 0x9dec + +// dsp32mac write to register pair and slot 0 same dest - odd (1 instr) + + + .dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||R3=W[P0++P3](X)||NOP; + .dw 0x4c88 + .dw 0x8ed8 + .dw 0x0000 + +// dsp32mult write to register pair and slot 0 same dest - odd (1 instr) + + + .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R5=[P0++P1]||NOP; + .dw 0x6508 + .dw 0x8148 + .dw 0x0000 + +// dsp32mac write to register pair and slot 1 same dest - odd (1 instr) + + + .dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||NOP||R3=[I1++M3]; + .dw 0x4c88 + .dw 0x0000 + .dw 0x9deb + +// dsp32mult write to register pair and slot 1 same dest - odd (1 instr) + + + .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R5=[I1++M3]; + .dw 0x6508 + .dw 0x0000 + .dw 0x9ded + +// CHECKER + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x22; +CHECKREG(r5, 53); // count of all Illegal Combination Exceptions. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 16 bit illegal opcode handler - skips bad instruction + + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x22; // EXCAUSE 0x22 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP ILLEGALCOMBINATION; // If EXCAUSE != 0x22 then leave + +dbg_fail; +JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop + +ILLEGALCOMBINATION: + R7 = RETX; // Fix up return address + + R7 += 8; // skip offending 64 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_kill_wbbr.S b/sim/testsuite/sim/bfin/se_kill_wbbr.S new file mode 100644 index 0000000..80ec7d1 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_kill_wbbr.S @@ -0,0 +1,422 @@ +//Original:/proj/frio/dv/testcases/seq/se_kill_wbbr/se_kill_wbbr.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Load RETS +LD32_LABEL(r0, USER_CODE); +RETS = R0; + + // Return to Supervisor Code +RAISE 2; +RAISE 5; +RAISE 6; +RAISE 7; +RAISE 8; +RAISE 9; +RAISE 10; +RAISE 11; +RAISE 12; +RAISE 13; +RAISE 14; +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; +IF !CC JUMP 2; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; +NOP; +IF !CC JUMP 2; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; +CSYNC; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; +NOP; +CSYNC; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; +SSYNC; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; +NOP; +SSYNC; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; +NOP; +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; +NOP; +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +RTI; +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +EXCPT 0x5; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_2 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_2 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.section MEM_(DATA_ADDR_2 + 0x110) //.data 0x00F00210,"aw" + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_kills2.S b/sim/testsuite/sim/bfin/se_kills2.S new file mode 100644 index 0000000..73f9d28 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_kills2.S @@ -0,0 +1,148 @@ +//Original:/proj/frio/dv/testcases/seq/se_kills2/se_kills2.dsp +// Description: Test se_kill for all supported types of RTL1 instructions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(selfcheck.inc) +include(std.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +SP = 0 (Z); +SP.L = KSTACK; // setup the stack pointer +SP.H = KSTACK; +FP = SP; // and frame pointer + +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +ASTAT = r0; // reset sequencer registers + +// +// The Main Program +// + +START: + + // **** YOUR CODE GOES HERE **** + // CHECK_INIT(p0, 0xFF7FFFFC); // original +CHECK_INIT_DEF(p0); + + R0 = 0; + R1 = 1; + R2 = 2; + R3 = 3; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + P1 = 11; + // Assume CC is reset to 0. +IF !CC JUMP NEXT1; // following instruction should be killed +RAISE 13; + +NEXT1: + IF !CC JUMP NEXT2; +EXCPT 15; + +NEXT2: + IF !CC JUMP NEXT3; + ( R7:0, P5:0 ) = [ SP ++ ]; + +NEXT3: + IF !CC JUMP NEXT4; + [ -- SP ] = ( R7:0, P5:0 ); + +NEXT4: + IF !CC JUMP NEXT5; +EMUEXCPT; + +NEXT5: + IF !CC JUMP NEXT6; +.dd 0xFACEBABE + +NEXT6: + IF !CC JUMP NEXT7; +LINK 12; + +NEXT7: + IF !CC JUMP NEXT8; +UNLINK; + +NEXT8: + IF !CC JUMP NEXT9; +LSETUP (NEXT10, NEXT11) lc0 = p0; + +NEXT9: + IF !CC JUMP NEXT10; + +NEXT10: + IF !CC JUMP NEXT11; + +NEXT11: + IF !CC JUMP NEXT12; + +NEXT12: + IF !CC JUMP NEXT13; + +NEXT13: + IF !CC JUMP NEXT14; + +NEXT14: + IF !CC JUMP NEXT15; + +NEXT15: + IF !CC JUMP NEXT16; + +NEXT16: + +END: +CHECKREG(r0, 0); +CHECKREG(r1, 1); +CHECKREG(r2, 2); +CHECKREG(r3, 3); +CHECKREG(r4, 4); +CHECKREG(r5, 5); +CHECKREG(r6, 6); +CHECKREG(r7, 7); + +dbg_pass; // Call Endtest Macro + +//********************************************************************* +// +// Data Segment +// + +//.data 0xF0000000 +.data +DATA: + .space (0x010); // Some data space + +// Stack Segments + + .space (STACKSIZE); +KSTACK: diff --git a/sim/testsuite/sim/bfin/se_loop_disable.S b/sim/testsuite/sim/bfin/se_loop_disable.S new file mode 100644 index 0000000..3b84d8c --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_disable.S @@ -0,0 +1,408 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_disable/se_loop_disable.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + +LSETUP ( 1f , 1f ) LC0 = P1; +1:R7 += 1; +LSETUP ( 1f , 1f ) LC0 = P1; +1:R6 += 1; +LC0 = P0; +LD32_LABEL(r0, l0t); +LD32_LABEL(r1, l0b); +LT0 = r0; +LB0 = r1; +l0t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l0b:R2 += 2; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_3 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_( DATA_ADDR_3 + 100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.section MEM_( DATA_ADDR_3 + 110) //.data 0x00F00210,"aw" + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_kill.S b/sim/testsuite/sim/bfin/se_loop_kill.S new file mode 100644 index 0000000..6a2b633 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_kill.S @@ -0,0 +1,519 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_kill/se_loop_kill.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + P2 = 0x0200 (Z); + P2.H = 0x00F0; + [ -- SP ] = P0; + [ -- SP ] = P0; +SSYNC; + +LD32_LABEL(r0, l0t); +LD32_LABEL(r1, l0b); +LT0 = r0; +LB0 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 +NOP; +LC0 = P0; +l0t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l0b:R2 += 2; + +LD32_LABEL(r0, l2t); +LD32_LABEL(r1, l2b); +LT0 = r0; +LB0 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 when stalled +LC0 = [ SP ++ ]; +l2t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l2b:R2 += 2; + +LD32_LABEL(r0, l1t); +LD32_LABEL(r1, l1b); +LT1 = r0; +LB1 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 when stalled +LC1 = [ SP ++ ]; +l1t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l1b:R2 += 2; + +LD32_LABEL(r0, l3t); +LD32_LABEL(r1, l3b); +LT1 = r0; +LB1 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 +NOP; +LC1 = P0; +l3t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l3b:R2 += 2; + +EXCPT 0x6; // Will kill Lsetup in EX2 +NOP; +NOP; +LSETUP ( l1e , l1e ) LC0 = P1; +l1e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX2 +NOP; +NOP; +LSETUP ( m1e , m1e ) LC1 = P1; +m1e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 +NOP; +NOP; +NOP; +LSETUP ( l2e , l2e ) LC0 = P1; +l2e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 +NOP; +NOP; +NOP; +LSETUP ( m2e , m2e ) LC1 = P1; +m2e:R7 += 1; + +NOP; +NOP; +NOP; + +EXCPT 0x6; // Will kill Lsetup in EX2 when stalled + R0 = [ P2 ++ ]; +LSETUP ( l3e , l3e ) LC0 = P1; +l3e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX2 when stalled + R0 = [ P2 ++ ]; +LSETUP ( m3e , m3e ) LC1 = P1; +m3e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 when stalled + R0 = [ P2 ++ ]; +NOP; +LSETUP ( l4e , l4e ) LC0 = P1; +l4e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 when stalled + R0 = [ P2 ++ ]; +NOP; +LSETUP ( m4e , m4e ) LC1 = P1; +m4e:R7 += 1; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_0x00F00200,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_kill_01.S b/sim/testsuite/sim/bfin/se_loop_kill_01.S new file mode 100644 index 0000000..55b6273 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_kill_01.S @@ -0,0 +1,521 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_kill_01/se_loop_kill_01.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + P2 = 0x0200 (Z); + P2.H = 0x00F0; + [ -- SP ] = P0; + [ -- SP ] = P0; +SSYNC; + +LD32_LABEL(r0, l0t); +LD32_LABEL(r1, l0b); + [ -- SP ] = R0; + [ -- SP ] = R1; +SSYNC; +LB0 = [sp++]; +EXCPT 0x5; // Will kill mv2lc in EX3 +LC0 = P0; +LT0 = [sp++]; +l0t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l0b:R2 += 2; + +LD32_LABEL(r0, l2t); +LD32_LABEL(r1, l2b); +LT0 = r0; +LB0 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 when stalled +LC0 = [ SP ++ ]; +l2t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l2b:R2 += 2; + +LD32_LABEL(r0, l1t); +LD32_LABEL(r1, l1b); +LT1 = r0; +LB1 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 when stalled +LC1 = [ SP ++ ]; +l1t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l1b:R2 += 2; + +LD32_LABEL(r0, l3t); +LD32_LABEL(r1, l3b); +LT1 = r0; +LB1 = r1; +EXCPT 0x5; // Will kill mv2lc in EX3 +NOP; +LC1 = P0; +l3t:R3 += 3; + R1 += 1; + R4 += 4; + R5 += 5; + R6 += 6; +l3b:R2 += 2; + +EXCPT 0x6; // Will kill Lsetup in EX2 +NOP; +NOP; +LSETUP ( l1e , l1e ) LC0 = P1; +l1e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX2 +NOP; +NOP; +LSETUP ( m1e , m1e ) LC1 = P1; +m1e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 +NOP; +NOP; +NOP; +LSETUP ( l2e , l2e ) LC0 = P1; +l2e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 +NOP; +NOP; +NOP; +LSETUP ( m2e , m2e ) LC1 = P1; +m2e:R7 += 1; + +NOP; +NOP; +NOP; + +EXCPT 0x6; // Will kill Lsetup in EX2 when stalled + R0 = [ P2 ++ ]; +LSETUP ( l3e , l3e ) LC0 = P1; +l3e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX2 when stalled + R0 = [ P2 ++ ]; +LSETUP ( m3e , m3e ) LC1 = P1; +m3e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 when stalled + R0 = [ P2 ++ ]; +NOP; +LSETUP ( l4e , l4e ) LC0 = P1; +l4e:R7 += 1; + +EXCPT 0x6; // Will kill Lsetup in EX1 when stalled + R0 = [ P2 ++ ]; +NOP; +LSETUP ( m4e , m4e ) LC1 = P1; +m4e:R7 += 1; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_0x00F00200,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_kill_dcr.S b/sim/testsuite/sim/bfin/se_loop_kill_dcr.S new file mode 100644 index 0000000..13bf16a --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_kill_dcr.S @@ -0,0 +1,914 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr/se_loop_kill_dcr.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x1 (Z); + P1 = 0x2 (Z); + P2 = 0x3 (Z); + P3 = 0x4 (Z); + P4 = 0x5 (Z); + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (with Kill WB) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in WB +LSETUP ( L0T , L0T ) LC0 = P0; +EXCPT 0x5; +L0T:R0 += 5; + + // Kill Valid Dcr in EX3 +LSETUP ( L1T , L1B ) LC0 = P0; +EXCPT 0x5; +L1T:R0 += 5; +L1B:R1 += 4; + + // Kill Valid Dcr in EX2 +LSETUP ( L2T , L2B ) LC0 = P0; +EXCPT 0x5; +L2T:R0 += 5; + R1 += 4; +L2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( L3T , L3B ) LC0 = P0; +EXCPT 0x5; +L3T:R0 += 5; + R1 += 4; + R2 += 3; +L3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( L4T , L4B ) LC0 = P0; +EXCPT 0x5; +L4T:R0 += 5; + R1 += 4; + R2 += 3; + R3 += 2; +L4B:R4 += 1; + + // Kill Valid Dcr in WB, EX3 +LSETUP ( L5T , L5T ) LC0 = P1; +EXCPT 0x5; +L5T:R1 += 5; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( L6T , L6T ) LC0 = P1; +EXCPT 0x5; +NOP; +L6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( L7T , L7T ) LC0 = P1; +EXCPT 0x5; +NOP; +NOP; +L7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( L8T , L8T ) LC0 = P1; +EXCPT 0x5; +NOP; +NOP; +NOP; +L8T:R4 += 5; + + // Kill Valid Dcr in WB, EX3, EX2 +LSETUP ( L9T , L9T ) LC0 = P2; +EXCPT 0x5; +L9T:R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( LAT , LAT ) LC0 = P2; +EXCPT 0x5; +NOP; +LAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( LBT , LBT ) LC0 = P2; +EXCPT 0x5; +NOP; +NOP; +LBT: + R5 += 5; + + // Kill Valid Dcr in WB, EX3, EX2, EX1 +LSETUP ( LCT , LCT ) LC0 = P3; +EXCPT 0x5; +LCT: + R7 += 7; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( LDT , LDT ) LC0 = P3; +EXCPT 0x5; +NOP; +LDT: + R0 += 7; + + // Kill Valid Dcr in WB, EX3, EX2, EX1, AC +LSETUP ( LET , LET ) LC0 = P4; +EXCPT 0x5; +LET: + R1 += 1; + + // Kill Valid Dcr in WB, EX2 +LSETUP ( LFT , LFB ) LC0 = P1; +LFT: + EXCPT 0x5; +LFB: + R1 += 2; + + // Kill Valid Dcr in WB, EX1 +LSETUP ( LGT , LGB ) LC0 = P1; +LGT: + R2 += 3; +EXCPT 0x5; +LGB: + R1 += 2; + + // Kill Valid Dcr in WB, AC +LSETUP ( LHT , LHB ) LC0 = P1; +LHT: + R2 += 3; + R3 += 4; +EXCPT 0x5; +LHB: + R1 += 2; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( LIT , LIB ) LC0 = P1; +EXCPT 0x5; +LIT: + R2 += 1; +LIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( LJT , LJB ) LC0 = P1; +LJT: + EXCPT 0x5; + R2 += 1; +LJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( LKT , LKB ) LC0 = P1; +EXCPT 0x5; +NOP; +LKT: + R2 += 1; +LKB: + R1 += 2; + + // Kill Valid Dcr in WB, EX2, AC +LSETUP ( LLT , LLB ) LC0 = P2; +LLT: + EXCPT 0x5; +LLB: + R2 += 2; + + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (with Kill WB) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in WB +LSETUP ( M0T , M0T ) LC1 = P0; +EXCPT 0x5; +M0T:R0 += 5; + + // Kill Valid Dcr in EX3 +LSETUP ( M1T , M1B ) LC1 = P0; +EXCPT 0x5; +M1T:R0 += 5; +M1B:R1 += 4; + + // Kill Valid Dcr in EX2 +LSETUP ( M2T , M2B ) LC1 = P0; +EXCPT 0x5; +M2T:R0 += 5; + R1 += 4; +M2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( M3T , M3B ) LC1 = P0; +EXCPT 0x5; +M3T:R0 += 5; + R1 += 4; + R2 += 3; +M3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( M4T , M4B ) LC1 = P0; +EXCPT 0x5; +M4T:R0 += 5; + R1 += 4; + R2 += 3; + R3 += 2; +M4B:R4 += 1; + + // Kill Valid Dcr in WB, EX3 +LSETUP ( M5T , M5T ) LC1 = P1; +EXCPT 0x5; +M5T:R1 += 5; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( M6T , M6T ) LC1 = P1; +EXCPT 0x5; +NOP; +M6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( M7T , M7T ) LC1 = P1; +EXCPT 0x5; +NOP; +NOP; +M7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( M8T , M8T ) LC1 = P1; +EXCPT 0x5; +NOP; +NOP; +NOP; +M8T:R4 += 5; + + // Kill Valid Dcr in WB, EX3, EX2 +LSETUP ( M9T , M9T ) LC1 = P2; +EXCPT 0x5; +M9T:R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( MAT , MAT ) LC1 = P2; +EXCPT 0x5; +NOP; +MAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( MBT , MBT ) LC1 = P2; +EXCPT 0x5; +NOP; +NOP; +MBT: + R5 += 5; + + // Kill Valid Dcr in WB, EX3, EX2, EX1 +LSETUP ( MCT , MCT ) LC1 = P3; +EXCPT 0x5; +MCT: + R7 += 7; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( MDT , MDT ) LC1 = P3; +EXCPT 0x5; +NOP; +MDT: + R0 += 7; + + // Kill Valid Dcr in WB, EX3, EX2, EX1, AC +LSETUP ( MET , MET ) LC1 = P4; +EXCPT 0x5; +MET: + R1 += 1; + + // Kill Valid Dcr in WB, EX2 +LSETUP ( MFT , MFB ) LC1 = P1; +MFT: + EXCPT 0x5; +MFB: + R1 += 2; + + // Kill Valid Dcr in WB, EX1 +LSETUP ( MGT , MGB ) LC1 = P1; +MGT: + R2 += 3; +EXCPT 0x5; +MGB: + R1 += 2; + + // Kill Valid Dcr in WB, AC +LSETUP ( MHT , MHB ) LC1 = P1; +MHT: + R2 += 3; + R3 += 4; +EXCPT 0x5; +MHB: + R1 += 2; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( MIT , MIB ) LC1 = P1; +EXCPT 0x5; +MIT: + R2 += 1; +MIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( MJT , MJB ) LC1 = P1; +MJT: + EXCPT 0x5; + R2 += 1; +MJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( MKT , MKB ) LC1 = P1; +EXCPT 0x5; +NOP; +MKT: + R2 += 1; +MKB: + R1 += 2; + + // Kill Valid Dcr in WB, EX2, AC +LSETUP ( MLT , MLB ) LC1 = P2; +MLT: + EXCPT 0x5; +MLB: + R2 += 2; + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (with Kill EX3) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in EX3 +LSETUP ( N1T , N1T ) LC0 = P0; +CSYNC; +N1T:R0 += 5; + + // Kill Valid Dcr in EX2 +LSETUP ( N2T , N2B ) LC0 = P0; +CSYNC; +N2T:R0 += 5; +N2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( N3T , N3B ) LC0 = P0; +CSYNC; +N3T:R0 += 5; + R2 += 3; +N3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( N4T , N4B ) LC0 = P0; +CSYNC; +N4T:R0 += 5; + R2 += 3; + R3 += 2; +N4B:R4 += 1; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( N6T , N6T ) LC0 = P1; +CSYNC; +N6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( N7T , N7T ) LC0 = P1; +CSYNC; +NOP; +N7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( N8T , N8T ) LC0 = P1; +CSYNC; +NOP; +NOP; +N8T:R4 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( NAT , NAT ) LC0 = P2; +CSYNC; +NAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( NBT , NBT ) LC0 = P2; +CSYNC; +NOP; +NBT: + R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( NDT , NDT ) LC0 = P3; +CSYNC; +NDT: + R0 += 7; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( NIT , NIB ) LC0 = P1; +NIT: + CSYNC; +NIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( NJT , NJB ) LC0 = P1; +NJT: + R2 += 1; +CSYNC; +NJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( NKT , NKB ) LC0 = P1; +CSYNC; +NKT: + R2 += 1; +NKB: + R1 += 2; + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (with Kill EX3) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in EX3 +LSETUP ( O1T , O1T ) LC1 = P0; +CSYNC; +O1T:R0 += 5; + + // Kill Valid Dcr in EX2 +LSETUP ( O2T , O2B ) LC1 = P0; +CSYNC; +O2T:R0 += 5; +O2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( O3T , O3B ) LC1 = P0; +CSYNC; +O3T:R0 += 5; + R2 += 3; +O3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( O4T , O4B ) LC1 = P0; +CSYNC; +O4T:R0 += 5; + R2 += 3; + R3 += 2; +O4B:R4 += 1; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( O6T , O6T ) LC1 = P1; +CSYNC; +O6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( O7T , O7T ) LC1 = P1; +CSYNC; +NOP; +O7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( O8T , O8T ) LC1 = P1; +CSYNC; +NOP; +NOP; +O8T:R4 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( OAT , OAT ) LC1 = P2; +CSYNC; +OAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( OBT , OBT ) LC1 = P2; +CSYNC; +NOP; +OBT: + R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( ODT , ODT ) LC1 = P3; +CSYNC; +ODT: + R0 += 7; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( OIT , OIB ) LC1 = P1; +OIT: + CSYNC; +OIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( OJT , OJB ) LC1 = P1; +OJT: + R2 += 1; +CSYNC; +OJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( OKT , OKB ) LC1 = P1; +CSYNC; +OKT: + R2 += 1; +OKB: + R1 += 2; + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (with Kill AC) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in AC +LSETUP ( P4T , P4T ) LC0 = P0; +JUMP.S 2; +P4T:R0 += 5; + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (with Kill AC) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in AC +LSETUP ( Q4T , Q4T ) LC1 = P0; +JUMP.S 2; +Q4T:R0 += 5; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_kill_dcr_01.S b/sim/testsuite/sim/bfin/se_loop_kill_dcr_01.S new file mode 100644 index 0000000..39a2e8d --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_kill_dcr_01.S @@ -0,0 +1,917 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr_01/se_loop_kill_dcr_01.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x1 (Z); + P1 = 0x2 (Z); + P2 = 0x3 (Z); + P3 = 0x4 (Z); + P4 = 0x5 (Z); + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (with Kill WB) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in WB +LSETUP ( L0T , L0T ) LC0 = P0; +EXCPT 0x5; +L0T:R0 += 5; + + // Kill Valid Dcr in EX3 +LSETUP ( L1T , L1B ) LC0 = P0; +EXCPT 0x5; +L1T:R0 += 5; +L1B:R1 += 4; + + // Kill Valid Dcr in EX2 +LSETUP ( L2T , L2B ) LC0 = P0; +EXCPT 0x5; +L2T:R0 += 5; + R1 += 4; +L2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( L3T , L3B ) LC0 = P0; +EXCPT 0x5; +L3T:R0 += 5; + R1 += 4; + R2 += 3; +L3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( L4T , L4B ) LC0 = P0; +EXCPT 0x5; +L4T:R0 += 5; + R1 += 4; + R2 += 3; + R3 += 2; +L4B:R4 += 1; + + // Kill Valid Dcr in WB, EX3 +LSETUP ( L5T , L5T ) LC0 = P1; +EXCPT 0x5; +L5T:R1 += 5; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( L6T , L6T ) LC0 = P1; +EXCPT 0x5; +NOP; +L6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( L7T , L7T ) LC0 = P1; +EXCPT 0x5; +NOP; +NOP; +L7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( L8T , L8T ) LC0 = P1; +EXCPT 0x5; +NOP; +NOP; +NOP; +L8T:R4 += 5; + + // Kill Valid Dcr in WB, EX3, EX2 +LSETUP ( L9T , L9T ) LC0 = P2; +EXCPT 0x5; +L9T:R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( LAT , LAT ) LC0 = P2; +EXCPT 0x5; +NOP; +LAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( LBT , LBT ) LC0 = P2; +EXCPT 0x5; +NOP; +NOP; +LBT: + R5 += 5; + + // Kill Valid Dcr in WB, EX3, EX2, EX1 +LSETUP ( LCT , LCT ) LC0 = P3; +EXCPT 0x5; +LCT: + R7 += 7; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( LDT , LDT ) LC0 = P3; +EXCPT 0x5; +NOP; +LDT: + R0 += 7; + + // Kill Valid Dcr in WB, EX3, EX2, EX1, AC +LSETUP ( LET , LET ) LC0 = P4; +EXCPT 0x5; +LET: + R1 += 1; + + // Kill Valid Dcr in WB, EX2 +LSETUP ( LFT , LFB ) LC0 = P1; +LFT: + EXCPT 0x5; +LFB: + R1 += 2; + + // Kill Valid Dcr in WB, EX1 +LSETUP ( LGT , LGB ) LC0 = P1; +LGT: + R2 += 3; +EXCPT 0x5; +LGB: + R1 += 2; + + // Kill Valid Dcr in WB, AC +LSETUP ( LHT , LHB ) LC0 = P1; +LHT: + R2 += 3; + R3 += 4; +EXCPT 0x5; +LHB: + R1 += 2; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( LIT , LIB ) LC0 = P1; +EXCPT 0x5; +LIT: + R2 += 1; +LIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( LJT , LJB ) LC0 = P1; +LJT: + EXCPT 0x5; + R2 += 1; +LJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( LKT , LKB ) LC0 = P1; +EXCPT 0x5; +NOP; +LKT: + R2 += 1; +LKB: + R1 += 2; + + // Kill Valid Dcr in WB, EX2, AC +LSETUP ( LLT , LLB ) LC0 = P2; +LLT: + EXCPT 0x5; +LLB: + R2 += 2; + + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (with Kill WB) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in WB +LSETUP ( M0T , M0T ) LC1 = P0; +EXCPT 0x5; +M0T:R0 += 5; + + // Kill Valid Dcr in EX3 +LSETUP ( M1T , M1B ) LC1 = P0; +EXCPT 0x5; +M1T:R0 += 5; +M1B:R1 += 4; + + // Kill Valid Dcr in EX2 +LSETUP ( M2T , M2B ) LC1 = P0; +EXCPT 0x5; +M2T:R0 += 5; + R1 += 4; +M2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( M3T , M3B ) LC1 = P0; +EXCPT 0x5; +M3T:R0 += 5; + R1 += 4; + R2 += 3; +M3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( M4T , M4B ) LC1 = P0; +EXCPT 0x5; +M4T:R0 += 5; + R1 += 4; + R2 += 3; + R3 += 2; +M4B:R4 += 1; + + // Kill Valid Dcr in WB, EX3 +LSETUP ( M5T , M5T ) LC1 = P1; +EXCPT 0x5; +M5T:R1 += 5; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( M6T , M6T ) LC1 = P1; +EXCPT 0x5; +NOP; +M6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( M7T , M7T ) LC1 = P1; +EXCPT 0x5; +NOP; +NOP; +M7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( M8T , M8T ) LC1 = P1; +EXCPT 0x5; +NOP; +NOP; +NOP; +M8T:R4 += 5; + + // Kill Valid Dcr in WB, EX3, EX2 +LSETUP ( M9T , M9T ) LC1 = P2; +EXCPT 0x5; +M9T:R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( MAT , MAT ) LC1 = P2; +EXCPT 0x5; +NOP; +MAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( MBT , MBT ) LC1 = P2; +EXCPT 0x5; +NOP; +NOP; +MBT: + R5 += 5; + + // Kill Valid Dcr in WB, EX3, EX2, EX1 +LSETUP ( MCT , MCT ) LC1 = P3; +EXCPT 0x5; +MCT: + R7 += 7; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( MDT , MDT ) LC1 = P3; +EXCPT 0x5; +NOP; +MDT: + R0 += 7; + + // Kill Valid Dcr in WB, EX3, EX2, EX1, AC +LSETUP ( MET , MET ) LC1 = P4; +EXCPT 0x5; +MET: + R1 += 1; + + // Kill Valid Dcr in WB, EX2 +LSETUP ( MFT , MFB ) LC1 = P1; +MFT: + EXCPT 0x5; +MFB: + R1 += 2; + + // Kill Valid Dcr in WB, EX1 +LSETUP ( MGT , MGB ) LC1 = P1; +MGT: + R2 += 3; +EXCPT 0x5; +MGB: + R1 += 2; + + // Kill Valid Dcr in WB, AC +LSETUP ( MHT , MHB ) LC1 = P1; +MHT: + R2 += 3; + R3 += 4; +EXCPT 0x5; +MHB: + R1 += 2; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( MIT , MIB ) LC1 = P1; +EXCPT 0x5; +MIT: + R2 += 1; +MIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( MJT , MJB ) LC1 = P1; +MJT: + EXCPT 0x5; + R2 += 1; +MJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( MKT , MKB ) LC1 = P1; +EXCPT 0x5; +NOP; +MKT: + R2 += 1; +MKB: + R1 += 2; + + // Kill Valid Dcr in WB, EX2, AC +LSETUP ( MLT , MLB ) LC1 = P2; +MLT: + EXCPT 0x5; +MLB: + R2 += 2; + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (with Kill EX3) +///////////////////////////////////////////////////////////////////////////// + + R0 = 1; +CC = R0; + + // Kill %Valid Dcr in EX3 +LSETUP ( N1T , N1T ) LC0 = P0; +IF CC JUMP 2; +N1T:R0 += 5; + + // Kill Valid Dcr in EX2 +LSETUP ( N2T , N2B ) LC0 = P0; +IF CC JUMP 2; +N2T:R0 += 5; +N2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( N3T , N3B ) LC0 = P0; +IF CC JUMP 2; +N3T:R0 += 5; + R2 += 3; +N3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( N4T , N4B ) LC0 = P0; +IF CC JUMP 2; +N4T:R0 += 5; + R2 += 3; + R3 += 2; +N4B:R4 += 1; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( N6T , N6T ) LC0 = P1; +IF CC JUMP 2; +N6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( N7T , N7T ) LC0 = P1; +IF CC JUMP 2; +NOP; +N7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( N8T , N8T ) LC0 = P1; +IF CC JUMP 2; +NOP; +NOP; +N8T:R4 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( NAT , NAT ) LC0 = P2; +IF CC JUMP 2; +NAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( NBT , NBT ) LC0 = P2; +IF CC JUMP 2; +NOP; +NBT: + R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( NDT , NDT ) LC0 = P3; +IF CC JUMP 2; +NDT: + R0 += 7; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( NIT , NIB ) LC0 = P1; +NIT: + IF CC JUMP 2; +NIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( NJT , NJB ) LC0 = P1; +NJT: + R2 += 1; +IF CC JUMP 2; +NJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( NKT , NKB ) LC0 = P1; +IF CC JUMP 2; +NKT: + R2 += 1; +NKB: + R1 += 2; + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (with Kill EX3) +///////////////////////////////////////////////////////////////////////////// + + // Kill %Valid Dcr in EX3 +LSETUP ( O1T , O1T ) LC1 = P0; +IF CC JUMP 2; +O1T:R0 += 5; + + // Kill Valid Dcr in EX2 +LSETUP ( O2T , O2B ) LC1 = P0; +IF CC JUMP 2; +O2T:R0 += 5; +O2B:R2 += 3; + + // Kill Valid Dcr in EX1 +LSETUP ( O3T , O3B ) LC1 = P0; +IF CC JUMP 2; +O3T:R0 += 5; + R2 += 3; +O3B:R3 += 2; + + // Kill Valid Dcr in AC +LSETUP ( O4T , O4B ) LC1 = P0; +IF CC JUMP 2; +O4T:R0 += 5; + R2 += 3; + R3 += 2; +O4B:R4 += 1; + + // Kill Valid Dcr in EX3, EX2 +LSETUP ( O6T , O6T ) LC1 = P1; +IF CC JUMP 2; +O6T:R2 += 5; + + // Kill Valid Dcr in EX2, EX1 +LSETUP ( O7T , O7T ) LC1 = P1; +IF CC JUMP 2; +NOP; +O7T:R3 += 5; + + // Kill Valid Dcr in EX1, AC +LSETUP ( O8T , O8T ) LC1 = P1; +IF CC JUMP 2; +NOP; +NOP; +O8T:R4 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1 +LSETUP ( OAT , OAT ) LC1 = P2; +IF CC JUMP 2; +OAT: + R6 += 6; + + // Kill Valid Dcr in EX2, EX1, AC +LSETUP ( OBT , OBT ) LC1 = P2; +IF CC JUMP 2; +NOP; +OBT: + R5 += 5; + + // Kill Valid Dcr in EX3, EX2, EX1, AC +LSETUP ( ODT , ODT ) LC1 = P3; +IF CC JUMP 2; +ODT: + R0 += 7; + + // Kill Valid Dcr in EX3, EX1 +LSETUP ( OIT , OIB ) LC1 = P1; +OIT: + IF CC JUMP 2; +OIB: + R1 += 2; + + // Kill Valid Dcr in EX3, AC +LSETUP ( OJT , OJB ) LC1 = P1; +OJT: + R2 += 1; +IF CC JUMP 2; +OJB: + R1 += 2; + + // Kill Valid Dcr in EX2, AC +LSETUP ( OKT , OKB ) LC1 = P1; +IF CC JUMP 2; +OKT: + R2 += 1; +OKB: + R1 += 2; + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (with Kill AC) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in AC +LSETUP ( P4T , P4T ) LC0 = P0; +JUMP.S 2; +P4T:R0 += 5; + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (with Kill AC) +///////////////////////////////////////////////////////////////////////////// + + // Kill Valid Dcr in AC +LSETUP ( Q4T , Q4T ) LC1 = P0; +JUMP.S 2; +Q4T:R0 += 5; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_lr.S b/sim/testsuite/sim/bfin/se_loop_lr.S new file mode 100644 index 0000000..71e0308 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_lr.S @@ -0,0 +1,507 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_lr/se_loop_lr.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + + +LD32_LABEL(r0, l1e); +LSETUP ( l1e , l1e ) LC0 = P1; +l1s:LT0 = R0; +l1e:[ -- SP ] = R7; + + +LD32_LABEL(r0, ls1); +LSETUP ( l2s , l2e ) LC0 = P0; +l2s:LB0 = R0; +ls1:R6 += 2; +l2e:[ -- SP ] = ( R7:5 ); + + +LD32_LABEL(r0, ls2); +LD32_LABEL(r1, ls3); +LSETUP ( l3s , l3e ) LC0 = P0; +l3s:LT0 = R0; +ls2:LB0 = R1; +ls3:R7 += 3; +l3e:[ -- SP ] = ( R7:5 ); + + +LD32_LABEL(r0, ls4); +LD32_LABEL(r1, ls5); +LSETUP ( l4s , l4e ) LC0 = P0; +l4s:LT0 = R0; +LB0 = r1; +ls4:R7 += 3; +ls5:R4 += 4; +l4e:[ -- SP ] = ( R7:4 ); + +LD32_LABEL(r0, ls6); +LD32_LABEL(r1, ls7); +LSETUP ( l5s , l5e ) LC0 = P0; +l5s:LB0 = R1; +LT0 = r0; +ls6:R7 += 3; + R4 += 4; + R5 += 3; +ls7:R6 += 3; +l5e:[ -- SP ] = ( R7:4 ); + +LD32_LABEL(r0, ls8); +LD32_LABEL(r1, ls9); +LSETUP ( l6s , l6e ) LC0 = P0; +l6s:R5 += 1; +LB0 = r1; +LT0 = r0; +ls8:R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +ls9:R7 += 5; +l6e:[ -- SP ] = ( R7:4 ); + + +NOP; +NOP; + +LD32_LABEL(r0, m1e); +LSETUP ( m1e , m1e ) LC1 = P1; +m1s:LT0 = R0; +m1e:[ -- SP ] = R7; + + +LD32_LABEL(r0, ms1); +LSETUP ( m2s , m2e ) LC1 = P0; +m2s:LB0 = R0; +ms1:R6 += 2; +m2e:[ -- SP ] = ( R7:5 ); + + +LD32_LABEL(r0, ms2); +LD32_LABEL(r1, ms3); +LSETUP ( m3s , m3e ) LC1 = P0; +m3s:LT0 = R0; +ms2:LB0 = R1; +ms3:R7 += 3; +m3e:[ -- SP ] = ( R7:5 ); + + +LD32_LABEL(r0, ms4); +LD32_LABEL(r1, ms5); +LSETUP ( m4s , m4e ) LC1 = P0; +m4s:LT0 = R0; +LB0 = r1; +ms4:R7 += 3; +ms5:R4 += 4; +m4e:[ -- SP ] = ( R7:4 ); + +LD32_LABEL(r0, ms6); +LD32_LABEL(r1, ms7); +LSETUP ( m5s , m5e ) LC1 = P0; +m5s:LB0 = R1; +LT0 = r0; +ms6:R7 += 3; + R4 += 4; + R5 += 3; +ms7:R6 += 3; +m5e:[ -- SP ] = ( R7:4 ); + +LD32_LABEL(r0, ms8); +LD32_LABEL(r1, ms9); +LSETUP ( m6s , m6e ) LC1 = P0; +m6s:R5 += 1; +LB0 = r1; +LT0 = r0; +ms8:R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +ms9:R7 += 5; +m6e:[ -- SP ] = ( R7:4 ); + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S b/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S new file mode 100644 index 0000000..a3b2c24 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_mv2lb_stall.S @@ -0,0 +1,612 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lb_stall/se_loop_mv2lb_stall.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + P2 = 0x0100 (Z); + P2.H = 0x00f0; + + // Loop 0 +LD32_LABEL(r0, L0T); +LD32_LABEL(r1, L0B); +LC0 = p1; +LT0 = r0; + R0 = [ P2 ++ ]; +LB0 = r1; +L0T:R3 += 4; + R2 += 3; + R4 += 5; + R5 += 6; + R6 += 7; +L0B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L1T); +LD32_LABEL(r1, L1B); +LT0 = r0; +LC0 = p1; + R0 = [ P2 ++ ]; +NOP; +LB0 = r1; +L1T:R4 += 5; + R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; +L1B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L2T); +LD32_LABEL(r1, L2B); +LT0 = r0; +LC0 = p1; + R0 = [ P2 ++ ]; +NOP; +NOP; +LB0 = r1; +L2T:R5 += 6; + R2 += 3; + R3 += 4; + R4 += 5; + R6 += 7; +L2B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L3T); +LD32_LABEL(r1, L3B); +LT0 = r0; +LC0 = p1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LB0 = r1; +L3T:R2 += 3; + R5 += 6; + R6 += 7; + R3 += 4; + R4 += 5; +L3B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L4T); +LD32_LABEL(r1, L4B); +LT0 = r0; +LC0 = p1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LB0 = r1; +L4T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +L4B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L5T); +LD32_LABEL(r1, L5B); + [ -- SP ] = R1; +SSYNC; +LT0 = r0; +LC0 = p0; + R0 = [ P2 ++ ]; +LB0 = [sp++]; +L5T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +L5B:R7 += 8; + + + // Loop 1 +LD32_LABEL(r0, M0T); +LD32_LABEL(r1, M0B); +LT1 = r0; +LC1 = p1; + R0 = [ P2 ++ ]; +LB1 = r1; +M0T:R3 += 4; + R2 += 3; + R4 += 5; + R5 += 6; + R6 += 7; +M0B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M1T); +LD32_LABEL(r1, M1B); +LT1 = r0; +LC1 = p1; + R0 = [ P2 ++ ]; +NOP; +LB1 = r1; +M1T:R4 += 5; + R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; +M1B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M2T); +LD32_LABEL(r1, M2B); +LT1 = r0; +LC1 = p1; + R0 = [ P2 ++ ]; +NOP; +NOP; +LB1 = r1; +M2T:R5 += 6; + R2 += 3; + R3 += 4; + R4 += 5; + R6 += 7; +M2B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M3T); +LD32_LABEL(r1, M3B); +LT1 = r0; +LC1 = p1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LB1 = r1; +M3T:R2 += 3; + R5 += 6; + R6 += 7; + R3 += 4; + R4 += 5; +M3B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M4T); +LD32_LABEL(r1, M4B); +LT1 = r0; +LC1 = p1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LB1 = r1; +M4T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +M4B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M5T); +LD32_LABEL(r1, M5B); + [ -- SP ] = R1; +SSYNC; +LT1 = r0; +LC1 = p0; + R0 = [ P2 ++ ]; +LB1 = [sp++]; +M5T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +M5B:R7 += 8; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_mv2lc.S b/sim/testsuite/sim/bfin/se_loop_mv2lc.S new file mode 100644 index 0000000..69adeca --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_mv2lc.S @@ -0,0 +1,777 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lc/se_loop_mv2lc.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + + // Loop 0 +LD32_LABEL(r0, L0T); +LD32_LABEL(r1, L0B); +LT0 = r0; +LB0 = r1; + +LC0 = P0; +NOP; +JUMP.S 2; + +JUMP.S 6; +NOP; +LC0 = P0; +LC0 = P1; +L0T:R2 += 3; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; +L0B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, L1T); +LD32_LABEL(r1, L1B); +LT1 = r0; +LB1 = r1; + +LC1 = P0; +NOP; +JUMP.S 2; + +JUMP.S 6; +NOP; +LC1 = P0; +LC1 = P1; +L1T:R2 += 3; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; +L1B:R7 += 8; + + // Loop 0 +LSETUP ( L2T , L2T ) LC0 = P0; +NOP; +NOP; +NOP; +LC0 = P1; +L2T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +L2B:R7 += 6; + +LC0 = P1; +NOP; +NOP; +NOP; +LSETUP ( L3T , L3T ) LC0 = P0; +L3T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +L3B:R7 += 6; + +LSETUP ( L4T , L4B ) LC0 = P0; +NOP; +NOP; +LC0 = P1; +L4T:R2 += 1; +L4B:R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LC0 = P1; +NOP; +NOP; +LSETUP ( L5T , L5B ) LC0 = P0; +L5T:R2 += 1; +L5B:R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LSETUP ( L6T , L6B ) LC0 = P0; +NOP; +LC0 = P1; +L6T:R2 += 1; + R3 += 2; +L6B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LC0 = P1; +NOP; +LSETUP ( L7T , L7B ) LC0 = P0; +L7T:R2 += 1; + R3 += 2; +L7B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LSETUP ( L8T , L8B ) LC0 = P0; +LC0 = P1; +L8T:R2 += 1; + R3 += 2; + R4 += 3; +L8B:R5 += 4; + R6 += 5; + R7 += 6; + +LC0 = P1; +LSETUP ( L9T , L9B ) LC0 = P0; +L9T:R2 += 1; + R3 += 2; + R4 += 3; +L9B:R5 += 4; + R6 += 5; + R7 += 6; + + + // Loop 1 +LSETUP ( M2T , M2T ) LC1 = P0; +NOP; +NOP; +NOP; +LC1 = P1; +M2T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +M2B:R7 += 6; + +LC1 = P1; +NOP; +NOP; +NOP; +LSETUP ( M3T , M3T ) LC1 = P0; +M3T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +M3B:R7 += 6; + +LSETUP ( M4T , M4B ) LC1 = P0; +NOP; +NOP; +LC1 = P1; +M4T:R2 += 1; +M4B:R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LC1 = P1; +NOP; +NOP; +LSETUP ( M5T , M5B ) LC1 = P0; +M5T:R2 += 1; +M5B:R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LSETUP ( M6T , M6B ) LC1 = P0; +NOP; +LC1 = P1; +M6T:R2 += 1; + R3 += 2; +M6B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LC1 = P1; +NOP; +LSETUP ( M7T , M7B ) LC1 = P0; +M7T:R2 += 1; + R3 += 2; +M7B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LSETUP ( M8T , M8B ) LC1 = P0; +LC1 = P1; +M8T:R2 += 1; + R3 += 2; + R4 += 3; +M8B:R5 += 4; + R6 += 5; + R7 += 6; + +LC1 = P1; +LSETUP ( M9T , M9B ) LC1 = P0; +M9T:R2 += 1; + R3 += 2; + R4 += 3; +M9B:R5 += 4; + R6 += 5; + R7 += 6; + + // Loop 0 +LSETUP ( N2T , N2B ) LC0 = P0 >> 1; +NOP; +NOP; +NOP; +LC0 = P1; +N2T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +N2B:R7 += 6; + +LC0 = P1; +NOP; +NOP; +NOP; +LSETUP ( N3T , N3B ) LC0 = P0 >> 1; +N3T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +N3B:R7 += 6; + +LSETUP ( N4T , N4B ) LC0 = P0 >> 1; +NOP; +NOP; +LC0 = P1; +N4T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; +N4B:R6 += 5; + R7 += 6; + +LC0 = P1; +NOP; +NOP; +LSETUP ( N5T , N5B ) LC0 = P0 >> 1; +N5T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; +N5B:R6 += 5; + R7 += 6; + +LSETUP ( N6T , N6B ) LC0 = P0 >> 1; +NOP; +LC0 = P1; +N6T:R2 += 1; + R3 += 2; + R4 += 3; +N6B:R5 += 4; + R6 += 5; + R7 += 6; + +LC0 = P1; +NOP; +LSETUP ( N7T , N7B ) LC0 = P0 >> 1; +N7T:R2 += 1; + R3 += 2; + R4 += 3; +N7B:R5 += 4; + R6 += 5; + R7 += 6; + +LSETUP ( N8T , N8T ) LC0 = P0 >> 1; +LC0 = P1; +N8T:R2 += 1; + R3 += 2; +N8B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LC0 = P1; +LSETUP ( N9T , N9T ) LC0 = P0 >> 1; +N9T:R2 += 1; + R3 += 2; +N9B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + + + // Loop 1 +LSETUP ( O2T , O2B ) LC1 = P0 >> 1; +NOP; +NOP; +NOP; +LC1 = P1; +O2T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +O2B:R7 += 6; + +LC1 = P1; +NOP; +NOP; +NOP; +LSETUP ( O3T , O3B ) LC1 = P0 >> 1; +O3T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; +O3B:R7 += 6; + +LSETUP ( O4T , O4B ) LC1 = P0 >> 1; +NOP; +NOP; +LC1 = P1; +O4T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; +O4B:R6 += 5; + R7 += 6; + +LC1 = P1; +NOP; +NOP; +LSETUP ( O5T , O5B ) LC1 = P0 >> 1; +O5T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; +O5B:R6 += 5; + R7 += 6; + +LSETUP ( O6T , O6B ) LC1 = P0 >> 1; +NOP; +LC1 = P1; +O6T:R2 += 1; + R3 += 2; + R4 += 3; +O6B:R5 += 4; + R6 += 5; + R7 += 6; + +LC1 = P1; +NOP; +LSETUP ( O7T , O7B ) LC1 = P0 >> 1; +O7T:R2 += 1; + R3 += 2; + R4 += 3; +O7B:R5 += 4; + R6 += 5; + R7 += 6; + +LSETUP ( O8T , O8T ) LC1 = P0 >> 1; +LC1 = P1; +O8T:R2 += 1; + R3 += 2; +O8B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + +LC1 = P1; +LSETUP ( O9T , O9T ) LC1 = P0 >> 1; +O9T:R2 += 1; + R3 += 2; +O9B:R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S b/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S new file mode 100644 index 0000000..ecd98bf --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_mv2lc_stall.S @@ -0,0 +1,612 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lc_stall/se_loop_mv2lc_stall.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + P2 = 0x0100 (Z); + P2.H = 0x00f0; + + // 2 pushes of P0 onto the Stack; + [ -- SP ] = P0; + [ -- SP ] = P0; + + // Loop 0 +LD32_LABEL(r0, L0T); +LD32_LABEL(r1, L0B); +LT0 = r0; +LB0 = r1; + R0 = [ P2 ++ ]; +LC0 = p1; +L0T:R3 += 4; + R2 += 3; + R4 += 5; + R5 += 6; + R6 += 7; +L0B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L1T); +LD32_LABEL(r1, L1B); +LT0 = r0; +LB0 = r1; + R0 = [ P2 ++ ]; +NOP; +LC0 = p1; +L1T:R4 += 5; + R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; +L1B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L2T); +LD32_LABEL(r1, L2B); +LT0 = r0; +LB0 = r1; + R0 = [ P2 ++ ]; +NOP; +NOP; +LC0 = p1; +L2T:R5 += 6; + R2 += 3; + R3 += 4; + R4 += 5; + R6 += 7; +L2B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L3T); +LD32_LABEL(r1, L3B); +LT0 = r0; +LB0 = r1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LC0 = p1; +L3T:R2 += 3; + R5 += 6; + R6 += 7; + R3 += 4; + R4 += 5; +L3B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L4T); +LD32_LABEL(r1, L4B); +LT0 = r0; +LB0 = r1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LC0 = p1; +L4T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +L4B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L5T); +LD32_LABEL(r1, L5B); +LT0 = r0; +LB0 = r1; + R0 = [ P2 ++ ]; +LC0 = [sp++]; +L5T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +L5B:R7 += 8; + + + // Loop 1 +LD32_LABEL(r0, M0T); +LD32_LABEL(r1, M0B); +LT1 = r0; +LB1 = r1; + R0 = [ P2 ++ ]; +LC1 = p1; +M0T:R3 += 4; + R2 += 3; + R4 += 5; + R5 += 6; + R6 += 7; +M0B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M1T); +LD32_LABEL(r1, M1B); +LT1 = r0; +LB1 = r1; + R0 = [ P2 ++ ]; +NOP; +LC1 = p1; +M1T:R4 += 5; + R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; +M1B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M2T); +LD32_LABEL(r1, M2B); +LT1 = r0; +LB1 = r1; + R0 = [ P2 ++ ]; +NOP; +NOP; +LC1 = p1; +M2T:R5 += 6; + R2 += 3; + R3 += 4; + R4 += 5; + R6 += 7; +M2B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M3T); +LD32_LABEL(r1, M3B); +LT1 = r0; +LB1 = r1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LC1 = p1; +M3T:R2 += 3; + R5 += 6; + R6 += 7; + R3 += 4; + R4 += 5; +M3B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M4T); +LD32_LABEL(r1, M4B); +LT1 = r0; +LB1 = r1; + R0 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LC1 = p1; +M4T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +M4B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M5T); +LD32_LABEL(r1, M5B); +LT1 = r0; +LB1 = r1; + R0 = [ P2 ++ ]; +LC1 = [sp++]; +M5T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +M5B:R7 += 8; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S b/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S new file mode 100644 index 0000000..36d2d73 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_mv2lt_stall.S @@ -0,0 +1,612 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lt_stall/se_loop_mv2lt_stall.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + P2 = 0x0100 (Z); + P2.H = 0x00f0; + + // Loop 0 +LD32_LABEL(r0, L0T); +LD32_LABEL(r1, L0B); +LC0 = p1; +LB0 = r1; + R5 = [ P2 ++ ]; +LT0 = r0; +L0T:R3 += 4; + R2 += 3; + R4 += 5; + R5 += 6; + R6 += 7; +L0B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L1T); +LD32_LABEL(r1, L1B); +LB0 = r1; +LC0 = p1; + R5 = [ P2 ++ ]; +NOP; +LT0 = r0; +L1T:R4 += 5; + R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; +L1B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L2T); +LD32_LABEL(r1, L2B); +LB0 = r1; +LC0 = p1; + R5 = [ P2 ++ ]; +NOP; +NOP; +LT0 = r0; +L2T:R5 += 6; + R2 += 3; + R3 += 4; + R4 += 5; + R6 += 7; +L2B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L3T); +LD32_LABEL(r1, L3B); +LB0 = r1; +LC0 = p1; + R5 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LT0 = r0; +L3T:R2 += 3; + R5 += 6; + R6 += 7; + R3 += 4; + R4 += 5; +L3B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L4T); +LD32_LABEL(r1, L4B); +LB0 = r1; +LC0 = p1; + R5 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LT0 = r0; +L4T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +L4B:R7 += 8; + + // Loop 0 +LD32_LABEL(r0, L5T); +LD32_LABEL(r1, L5B); + [ -- SP ] = R0; +SSYNC; +LB0 = r1; +LC0 = p0; + R5 = [ P2 ++ ]; +LT0 = [sp++]; +L5T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +L5B:R7 += 8; + + + // Loop 1 +LD32_LABEL(r0, M0T); +LD32_LABEL(r1, M0B); +LB1 = r1; +LC1 = p1; + R5 = [ P2 ++ ]; +LT1 = r0; +M0T:R3 += 4; + R2 += 3; + R4 += 5; + R5 += 6; + R6 += 7; +M0B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M1T); +LD32_LABEL(r1, M1B); +LB1 = r1; +LC1 = p1; + R5 = [ P2 ++ ]; +NOP; +LT1 = r0; +M1T:R4 += 5; + R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; +M1B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M2T); +LD32_LABEL(r1, M2B); +LB1 = r1; +LC1 = p1; + R5 = [ P2 ++ ]; +NOP; +NOP; +LT1 = r0; +M2T:R5 += 6; + R2 += 3; + R3 += 4; + R4 += 5; + R6 += 7; +M2B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M3T); +LD32_LABEL(r1, M3B); +LB1 = r1; +LC1 = p1; + R5 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LT1 = r0; +M3T:R2 += 3; + R5 += 6; + R6 += 7; + R3 += 4; + R4 += 5; +M3B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M4T); +LD32_LABEL(r1, M4B); +LB1 = r1; +LC1 = p1; + R5 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LT1 = r0; +M4T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +M4B:R7 += 8; + + // Loop 1 +LD32_LABEL(r0, M5T); +LD32_LABEL(r1, M5B); + [ -- SP ] = R0; +SSYNC; +LB1 = r1; +LC1 = p0; + R5 = [ P2 ++ ]; +LT1 = [sp++]; +M5T:R2 += 3; + R3 += 4; + R5 += 6; + R6 += 7; + R4 += 5; +M5B:R7 += 8; + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_nest_ppm.S b/sim/testsuite/sim/bfin/se_loop_nest_ppm.S new file mode 100644 index 0000000..81613db --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_nest_ppm.S @@ -0,0 +1,442 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm/se_loop_nest_ppm.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x4 (Z); + +LSETUP ( l0s , l0s ) LC0 = P0; +LSETUP ( l0s , l0s ) LC1 = P1; +l0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( l1s , l1e ) LC0 = P0; +LSETUP ( l1e , l1e ) LC1 = P1; +l1s:R5 += 1; +l1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l2s , l2e ) LC0 = P0; +LSETUP ( l2e , l2e ) LC1 = P1; +l2s:R5 += 1; + R6 += 2; +l2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l3s , l3e ) LC0 = P0; +LSETUP ( l3e , l3e ) LC1 = P1; +l3s:R5 += 1; + R6 += 2; + R7 += 3; +l3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l4s , l4e ) LC0 = P0; +LSETUP ( l4e , l4e ) LC1 = P1; +l4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +l4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l5s , l5e ) LC0 = P0; +LSETUP ( l5e , l5e ) LC1 = P1; +l5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +l5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l6s , l6e ) LC0 = P0; +LSETUP ( l6e , l6e ) LC1 = P1; +l6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +l6e:[ -- SP ] = ( R7:4 ); + +NOP; +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_nest_ppm_1.S b/sim/testsuite/sim/bfin/se_loop_nest_ppm_1.S new file mode 100644 index 0000000..6eab92f --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_nest_ppm_1.S @@ -0,0 +1,442 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_1/se_loop_nest_ppm_1.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x4 (Z); + +LSETUP ( l0s , l0s ) LC0 = P0; +LSETUP ( l0s , l0s ) LC1 = P1; +l0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( l1s , l1e ) LC0 = P0; +LSETUP ( l1s , l1e ) LC1 = P1; +l1s:R5 += 1; +l1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l2s , l2e ) LC0 = P0; +LSETUP ( l2s , l2e ) LC1 = P1; +l2s:R5 += 1; + R6 += 2; +l2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l3s , l3e ) LC0 = P0; +LSETUP ( l3s , l3e ) LC1 = P1; +l3s:R5 += 1; + R6 += 2; + R7 += 3; +l3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l4s , l4e ) LC0 = P0; +LSETUP ( l4s , l4e ) LC1 = P1; +l4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +l4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l5s , l5e ) LC0 = P0; +LSETUP ( l5s , l5e ) LC1 = P1; +l5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +l5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l6s , l6e ) LC1 = P0; +LSETUP ( l6s , l6e ) LC1 = P1; +l6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +l6e:[ -- SP ] = ( R7:4 ); + +NOP; +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_nest_ppm_2.S b/sim/testsuite/sim/bfin/se_loop_nest_ppm_2.S new file mode 100644 index 0000000..bf842ed --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_nest_ppm_2.S @@ -0,0 +1,491 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_2/se_loop_nest_ppm_2.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0x3 (Z); + +// lsetup (l0s, l0s) lc0 = p0; +LSETUP ( l0s , l0s ) LC0 = P1; +l0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( l1s , l1e ) LC0 = P0; +LSETUP ( l1e , l1e ) LC0 = P1; +l1s:R5 += 1; +l1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l2s , l2e ) LC0 = P0; +LSETUP ( l2e , l2e ) LC0 = P1; +l2s:R5 += 1; + R6 += 2; +l2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l3s , l3e ) LC0 = P0; +LSETUP ( l3e , l3e ) LC0 = P1; +l3s:R5 += 1; + R6 += 2; + R7 += 3; +l3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l4s , l4e ) LC0 = P0; +LSETUP ( l4e , l4e ) LC0 = P1; +l4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +l4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l5s , l5e ) LC0 = P0; +LSETUP ( l5e , l5e ) LC0 = P1; +l5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +l5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l6s , l6e ) LC0 = P0; +LSETUP ( l6e , l6e ) LC0 = P1; +l6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +l6e:[ -- SP ] = ( R7:4 ); + +NOP; + +LSETUP ( m0s , m0s ) LC1 = P0; +LSETUP ( m0s , m0s ) LC1 = P1; +m0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( m1s , m1e ) LC1 = P0; +LSETUP ( m1e , m1e ) LC1 = P1; +m1s:R5 += 1; +m1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m2s , m2e ) LC1 = P0; +LSETUP ( m2e , m2e ) LC1 = P1; +m2s:R5 += 1; + R6 += 2; +m2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m3s , m3e ) LC1 = P0; +LSETUP ( m3e , m3e ) LC1 = P1; +m3s:R5 += 1; + R6 += 2; + R7 += 3; +m3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m4s , m4e ) LC1 = P0; +LSETUP ( m4e , m4e ) LC1 = P1; +m4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +m4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( m5s , m5e ) LC1 = P0; +LSETUP ( m5e , m5e ) LC1 = P1; +m5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +m5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( m6s , m6e ) LC1 = P0; +LSETUP ( m6e , m6e ) LC1 = P1; +m6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +m6e:[ -- SP ] = ( R7:4 ); +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_ppm.S b/sim/testsuite/sim/bfin/se_loop_ppm.S new file mode 100644 index 0000000..b551baf --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_ppm.S @@ -0,0 +1,477 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_ppm/se_loop_ppm.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + +LSETUP ( l0s , l0s ) LC0 = P0; +l0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( l1s , l1e ) LC0 = P0; +l1s:R5 += 1; +l1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l2s , l2e ) LC0 = P0; +l2s:R5 += 1; + R6 += 2; +l2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l3s , l3e ) LC0 = P0; +l3s:R5 += 1; + R6 += 2; + R7 += 3; +l3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l4s , l4e ) LC0 = P0; +l4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +l4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l5s , l5e ) LC0 = P0; +l5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +l5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l6s , l6e ) LC1 = P0; +l6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +l6e:[ -- SP ] = ( R7:4 ); + +NOP; + +LSETUP ( m0s , m0s ) LC1 = P0; +m0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( m1s , m1e ) LC1 = P0; +m1s:R5 += 1; +m1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m2s , m2e ) LC1 = P0; +m2s:R5 += 1; + R6 += 2; +m2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m3s , m3e ) LC1 = P0; +m3s:R5 += 1; + R6 += 2; + R7 += 3; +m3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m4s , m4e ) LC1 = P0; +m4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +m4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( m5s , m5e ) LC1 = P0; +m5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +m5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( m6s , m6e ) LC1 = P0; +m6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +m6e:[ -- SP ] = ( R7:4 ); + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_ppm_1.S b/sim/testsuite/sim/bfin/se_loop_ppm_1.S new file mode 100644 index 0000000..db8e2ca --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_ppm_1.S @@ -0,0 +1,519 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_ppm_1/se_loop_ppm_1.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + +LSETUP ( l0s , l0s ) LC0 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( l1s , l1e ) LC0 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l1s:R5 += 1; +l1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l2s , l2e ) LC0 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l2s:R5 += 1; + R6 += 2; +l2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l3s , l3e ) LC0 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l3s:R5 += 1; + R6 += 2; + R7 += 3; +l3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( l4s , l4e ) LC0 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +l4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l5s , l5e ) LC0 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +l5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( l6s , l6e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +l6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +l6e:[ -- SP ] = ( R7:4 ); + +NOP; + +LSETUP ( m0s , m0s ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( m1s , m1e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m1s:R5 += 1; +m1e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m2s , m2e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m2s:R5 += 1; + R6 += 2; +m2e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m3s , m3e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m3s:R5 += 1; + R6 += 2; + R7 += 3; +m3e:[ -- SP ] = ( R7:5 ); + +LSETUP ( m4s , m4e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m4s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; +m4e:[ -- SP ] = ( R7:4 ); + +LSETUP ( m5s , m5e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m5s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; +m5e:[ -- SP ] = ( R7:4 ); + +LSETUP ( m6s , m6e ) LC1 = P0; + R0 += 1; + R4 += 3; + R5 += 5; +m6s:R5 += 1; + R6 += 2; + R7 += 3; + R4 += 4; + R5 += 3; + R7 += 5; +m6e:[ -- SP ] = ( R7:4 ); + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_loop_ppm_int.S b/sim/testsuite/sim/bfin/se_loop_ppm_int.S new file mode 100644 index 0000000..eed16b4 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_loop_ppm_int.S @@ -0,0 +1,429 @@ +//Original:/proj/frio/dv/testcases/seq/se_loop_ppm_int/se_loop_ppm_int.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Sync it! +CSYNC; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; +NOP;NOP;NOP;NOP; + + P0 = 0x5 (Z); + +LSETUP ( l0s , l0s ) LC0 = P0; +CSYNC; +l0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( l3s , l3e ) LC0 = P0; +l3s:[ -- SP ] = ( R7:5 ); + R6 += 2; + R7 += 3; +NOP; + +CSYNC; +NOP; +NOP; +NOP; +l3e:R5 += 1; + +NOP; + +LSETUP ( m0s , m0s ) LC1 = P0; +CSYNC; +m0s:[ -- SP ] = ( R7:5 ); + +LSETUP ( m3s , m3e ) LC1 = P0; +m3s:[ -- SP ] = ( R7:5 ); + R6 += 2; + R7 += 3; +NOP; + +CSYNC; +NOP; +NOP; +NOP; +m3e:R5 += 1; + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_lsetup_kill.S b/sim/testsuite/sim/bfin/se_lsetup_kill.S new file mode 100644 index 0000000..65d3441 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_lsetup_kill.S @@ -0,0 +1,776 @@ +//Original:/proj/frio/dv/testcases/seq/se_lsetup_kill/se_lsetup_kill.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + + P0 = 0x5 (Z); + P1 = 0xa (Z); + +NOP; +NOP; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (Kill Lsetup in WB) +///////////////////////////////////////////////////////////////////////////// + +EXCPT 0x5; +LSETUP ( L0T , L0T ) LC0 = P0; +L0T:R0 += 5; + +EXCPT 0x5; +LSETUP ( L1T , L1B ) LC0 = P0; +L1T:R0 += 5; +L1B:R1 += 4; + +EXCPT 0x5; +LSETUP ( L2T , L2B ) LC0 = P0; +L2T:R0 += 5; + R1 += 4; +L2B:R2 += 3; + +EXCPT 0x5; +LSETUP ( L3T , L3B ) LC0 = P0; +L3T:R0 += 5; + R1 += 4; + R2 += 3; +L3B:R3 += 2; + +EXCPT 0x5; +LSETUP ( L4T , L4B ) LC0 = P0; +L4T:R0 += 5; + R1 += 4; + R2 += 3; + R3 += 2; +L4B:R4 += 1; + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (Kill Lsetup in WB) +///////////////////////////////////////////////////////////////////////////// + +EXCPT 0x5; +LSETUP ( M0T , M0T ) LC1 = P0; +M0T:R0 += 5; + +EXCPT 0x5; +LSETUP ( M1T , M1B ) LC1 = P0; +M1T:R0 += 5; +M1B:R1 += 4; + +EXCPT 0x5; +LSETUP ( M2T , M2B ) LC1 = P0; +M2T:R0 += 5; + R1 += 4; +M2B:R2 += 3; + +EXCPT 0x5; +LSETUP ( M3T , M3B ) LC1 = P0; +M3T:R0 += 5; + R1 += 4; + R2 += 3; +M3B:R3 += 2; + +EXCPT 0x5; +LSETUP ( M4T , M4B ) LC1 = P0; +M4T:R0 += 5; + R1 += 4; + R2 += 3; + R3 += 2; +M4B:R4 += 1; + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (Kill during the last iteration at each pipe stage) +///////////////////////////////////////////////////////////////////////////// + +LSETUP ( N0T , N0B ) LC0 = P1; +NOP; +N0T:R0 = LC0; +CC = R0 == 1; +IF !CC JUMP N0B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; +N0B:R2 += 3; + +LSETUP ( N1T , N1B ) LC0 = P1; +NOP; +N1T:R0 = LC0; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP N1B (BP); +EXCPT 0x5; +N1B:R2 += 3; + +LSETUP ( N2T , N2B ) LC0 = P1; +NOP; +N2T:R0 = LC0; +CC = R0 == 1; +IF !CC JUMP N2B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; +N2B:R2 += 3; + +LSETUP ( N3T , N3B ) LC0 = P1; +NOP; +N3T:R0 = LC0; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP N3B (BP); +EXCPT 0x5; + R3 += 4; +N3B:R2 += 3; + +LSETUP ( N4T , N4B ) LC0 = P1; +NOP; +N4T:R0 = LC0; +CC = R0 == 1; +IF !CC JUMP N4B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; +N4B:R2 += 3; + +LSETUP ( N5T , N5B ) LC0 = P1; +NOP; +N5T:R0 = LC0; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP N5B (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; +N5B:R2 += 3; + +LSETUP ( N6T , N6B ) LC0 = P1; +NOP; +N6T:R0 = LC0; +CC = R0 == 1; +IF !CC JUMP N6B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; +N6B:R2 += 3; + +LSETUP ( N7T , N7B ) LC0 = P1; +NOP; +N7T:R0 = LC0; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP N7B (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; +N7B:R2 += 3; + +LSETUP ( N8T , N8B ) LC0 = P1; +NOP; +N8T:R0 = LC0; +CC = R0 == 1; +IF !CC JUMP N8B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; +N8B:R2 += 3; + +LSETUP ( N9T , N9B ) LC0 = P1; +NOP; +N9T:R0 = LC0; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP N9B (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; +N9B:R2 += 3; + +LSETUP ( NAT , NAB ) LC0 = P1; +NOP; +NAT: + R0 = LC0; +CC = R0 == 1; +IF !CC JUMP NAB (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; +NAB: + R2 += 3; + +LSETUP ( NBT , NBB ) LC0 = P1; +NOP; +NBT: + R0 = LC0; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP NBB (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; +NBB: + R2 += 3; + + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (Kill during the last iteration at each pipe stage) +///////////////////////////////////////////////////////////////////////////// + +LSETUP ( O0T , O0B ) LC1 = P1; +NOP; +O0T:R0 = LC1; +CC = R0 == 1; +IF !CC JUMP O0B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; +O0B:R2 += 3; + +LSETUP ( O1T , O1B ) LC1 = P1; +NOP; +O1T:R0 = LC1; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP O1B (BP); +EXCPT 0x5; +O1B:R2 += 3; + +LSETUP ( O2T , O2B ) LC1 = P1; +NOP; +O2T:R0 = LC1; +CC = R0 == 1; +IF !CC JUMP O2B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; +O2B:R2 += 3; + +LSETUP ( O3T , O3B ) LC1 = P1; +NOP; +O3T:R0 = LC1; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP O3B (BP); +EXCPT 0x5; + R3 += 4; +O3B:R2 += 3; + +LSETUP ( O4T , O4B ) LC1 = P1; +NOP; +O4T:R0 = LC1; +CC = R0 == 1; +IF !CC JUMP O4B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; +O4B:R2 += 3; + +LSETUP ( O5T , O5B ) LC1 = P1; +NOP; +O5T:R0 = LC1; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP O5B (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; +O5B:R2 += 3; + +LSETUP ( O6T , O6B ) LC1 = P1; +NOP; +O6T:R0 = LC1; +CC = R0 == 1; +IF !CC JUMP O6B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; +O6B:R2 += 3; + +LSETUP ( O7T , O7B ) LC1 = P1; +NOP; +O7T:R0 = LC1; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP O7B (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; +O7B:R2 += 3; + +LSETUP ( O8T , O8B ) LC1 = P1; +NOP; +O8T:R0 = LC1; +CC = R0 == 1; +IF !CC JUMP O8B (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; +O8B:R2 += 3; + +LSETUP ( O9T , O9B ) LC1 = P1; +NOP; +O9T:R0 = LC1; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP O9B (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; +O9B:R2 += 3; + +LSETUP ( OAT , OAB ) LC1 = P1; +NOP; +OAT: + R0 = LC1; +CC = R0 == 1; +IF !CC JUMP OAB (BP); + R0 += 1; + R1 += 2; +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; +OAB: + R2 += 3; + +LSETUP ( OBT , OBB ) LC1 = P1; +NOP; +OBT: + R0 = LC1; + R0 += 1; + R1 += 2; +CC = R0 == 1; +IF !CC JUMP OBB (BP); +EXCPT 0x5; + R3 += 4; + R4 += 5; + R5 += 6; + R6 += 7; + R7 += 8; +OBB: + R2 += 3; + +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_misaligned_fetch.S b/sim/testsuite/sim/bfin/se_misaligned_fetch.S new file mode 100644 index 0000000..2249243 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_misaligned_fetch.S @@ -0,0 +1,286 @@ +//Original:/proj/frio/dv/testcases/seq/se_misaligned_fetch/se_misaligned_fetch.dsp +// Description: attempt to fetch code from misaligned address +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT); // Setup Event Vectors and Handlers + +CLI R0; // hold off nonmaskables while writing EVTs + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + R0 = -1; // Change this to mask interrupts (*) + [ P0 ] = R0; // IMASK +CSYNC; // wait for MMR writes +STI R0; // reenable events + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests +// [--sp] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + +LD32_LABEL(p1, TARGET); + + P1 += 1; // cause access to be misaligned + +JUMP ( P1 ); // should cause misaligned + + R1 += 1; + R1 += 1; + R1 += 1; + R1 += 1; + R1 += 1; + R1 += 1; + R1 += 1; + R1 += 1; + +TARGET: +NOP; +NOP; +NOP; + + // PUT YOUR TEST HERE! + + +END: +CHECKREG(r5, 0xFFFFFFFF); // handler sets this if reached + +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x2A; // EXCAUSE 0x2A means I-Fetch Misaligned Access +CC = r7 == r6; +IF CC JUMP IFETCHMISALIGNED; // If EXCAUSE != 0x2A then leave + +dbg_pass; // if the EXCAUSE is wrong the test will infinite loop + +IFETCHMISALIGNED: + R7 = P1; // Fix up return address +BITCLR(r7, 0); // Strip off errant LSB +RETX = r7; // and put back in RETX + + R5 = -1; // set flag to indicate success + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_more_ret_haz.S b/sim/testsuite/sim/bfin/se_more_ret_haz.S new file mode 100644 index 0000000..c25ddca --- /dev/null +++ b/sim/testsuite/sim/bfin/se_more_ret_haz.S @@ -0,0 +1,271 @@ +//Original:/proj/frio/dv/testcases/seq/se_more_ret_haz/se_more_ret_haz.dsp +// Description: Return insts following pop, move. +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT15 +#define EVT15 0xFFE0203C +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +LD32_LABEL(sp, KSTACK); // setup the stack pointer +FP = SP; // and frame pointer + +CLI R1; + +LD32(p0, EVT); // Setup Event Vectors and Handlers + +LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + [ P0 ++ ] = R0; // IVT4 not used + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; +STI R1; + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start + +RAISE 15; // after we RTI, INT 15 should be taken + +NOP; // Workaround for Bug 217 +RTI; + +// +// The Main Program +// + +STARTUSER: +LD32_LABEL(sp, USTACK); // setup the stack pointer +FP = SP; // set frame pointer +JUMP BEGIN; + +//********************************************************************* + +BEGIN: +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // PUT YOUR TEST HERE! + // Can't Raise 0, 3, or 4 + + // Raise 1 requires some intelligence so the test + // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) +RAISE 2; + R2.L = 0xBAD; +CHECKREG(r2, 0); + +AFTER_RTN: +EXCPT 5; + R2.L = 0xBAD; +CHECKREG(r2, 0); + +AFTER_RTX: +RAISE 5; + R2.L = 0xBAD; +CHECKREG(r2, 0); + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +EHANDLE: // Emulation Handler 0 +RTE; + +RHANDLE: // Reset Handler 1 +RTI; + +NHANDLE: // NMI Handler 2 + R1.L = AFTER_RTN; + R1.H = AFTER_RTN; + [ -- SP ] = R1; +RETN = [ SP ++ ]; +RTN; + +XHANDLE: // Exception Handler 3 + R1.L = AFTER_RTX; + R1.H = AFTER_RTX; + [ -- SP ] = R1; +RETX = [ SP ++ ]; +RTX; + +HWHANDLE: // HW Error Handler 5 + R1.L = END; + R1.H = END; + [ -- SP ] = R1; +RETI = [ SP ++ ]; +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + +NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_mv2lp.S b/sim/testsuite/sim/bfin/se_mv2lp.S new file mode 100644 index 0000000..09feafc --- /dev/null +++ b/sim/testsuite/sim/bfin/se_mv2lp.S @@ -0,0 +1,481 @@ +//Original:/proj/frio/dv/testcases/seq/se_mv2lp/se_mv2lp.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_1 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + + P0 = 0x5 (Z); + P1 = 0xa (Z); + + P2 = 0x0100 (Z); + P2.H = 0x00f0; + +LD32_LABEL(r0, L0T); +LD32_LABEL(r1, L0B); +LSETUP ( L0T , L0B ) LC0 = P0; +L0T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + R0 += 2; + R1 += 2; +LT0 = R0; +LB0 = R1; +L0B:R7 += 6; + R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + +LD32_LABEL(r0, L1T); +LD32_LABEL(r1, L1B); +LSETUP ( L1T , L1B ) LC1 = P0; +L1T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + R0 += 2; + R1 += 2; +LT1 = R0; +LB1 = R1; +L1B:R7 += 6; + R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + +LD32_LABEL(r0, L2T); +LD32_LABEL(r1, L2B); +LSETUP ( L2T , L2B ) LC0 = P0; +L2T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + R0 += 2; + R1 += -2; +LT0 = R0; +LB0 = R1; + R7 += 6; + R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; +L2B:R6 += 5; + +LD32_LABEL(r0, L3T); +LD32_LABEL(r1, L3B); +LSETUP ( L3T , L3B ) LC1 = P0; +L3T:R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; + R6 += 5; + R7 += 6; + R0 += 2; + R1 += -2; +LT1 = R0; +LB1 = R1; + R7 += 6; + R2 += 1; + R3 += 2; + R4 += 3; + R5 += 4; +L3B:R6 += 5; + +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_oneins_zoff.S b/sim/testsuite/sim/bfin/se_oneins_zoff.S new file mode 100644 index 0000000..79259fc --- /dev/null +++ b/sim/testsuite/sim/bfin/se_oneins_zoff.S @@ -0,0 +1,487 @@ +//Original:/proj/frio/dv/testcases/seq/se_oneins_zoff/se_oneins_zoff.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Return to Supervisor Code +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + + P0 = 0x5 (Z); + P1 = 0xa (Z); + + P2 = 0x0100 (Z); + P2.H = 0x00f0; + +///////////////////////////////////////////////////////////////////////////// +// Loop 0 (One instruction Zero-offset) +///////////////////////////////////////////////////////////////////////////// + + R0 = [ P2 ++ ]; +LSETUP ( L0T , L0T ) LC0 = P0; +L0T:R0 += 5; + + R1 = [ P2 ++ ]; +NOP; +LSETUP ( L1T , L1T ) LC0 = P0; +L1T:R1 += 5; + + R2 = [ P2 ++ ]; +NOP; +NOP; +LSETUP ( L2T , L2T ) LC0 = P0; +L2T:R2 += 5; + + R3 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LSETUP ( L3T , L3T ) LC0 = P0; +L3T:R3 += 5; + + R4 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LSETUP ( L4T , L4T ) LC0 = P0; +L4T:R4 += 5; + + +///////////////////////////////////////////////////////////////////////////// +// Loop 1 (One instruction Zero-offset) +///////////////////////////////////////////////////////////////////////////// + + R0 = [ P2 ++ ]; +LSETUP ( M0T , M0T ) LC1 = P0; +M0T:R0 += 5; + + R1 = [ P2 ++ ]; +NOP; +LSETUP ( M1T , M1T ) LC1 = P0; +M1T:R1 += 5; + + R2 = [ P2 ++ ]; +NOP; +NOP; +LSETUP ( M2T , M2T ) LC1 = P0; +M2T:R2 += 5; + + R3 = [ P2 ++ ]; +NOP; +NOP; +NOP; +LSETUP ( M3T , M3T ) LC1 = P0; +M3T:R3 += 5; + + R4 = [ P2 ++ ]; +NOP; +NOP; +NOP; +NOP; +LSETUP ( M4T , M4T ) LC1 = P0; +M4T:R4 += 5; + + +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_0x00F00100,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; +.dd 0x05050505; +.dd 0x06060606; +.dd 0x07070707; +.dd 0x08080808; +.dd 0x09090909; +.dd 0x0a0a0a0a; +.dd 0x0b0b0b0b; +.dd 0x0c0c0c0c; +.dd 0x0d0d0d0d; +.dd 0x0e0e0e0e; +.dd 0x0f0f0f0f; + +// Define Kernal Stack +.section MEM_0x00F00210,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_popkill.S b/sim/testsuite/sim/bfin/se_popkill.S new file mode 100644 index 0000000..550db19 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_popkill.S @@ -0,0 +1,566 @@ +//Original:/proj/frio/dv/testcases/seq/se_popkill/se_popkill.dsp +// Description: Kill pops to sysregs in WB +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_RST_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_RST_2 // +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + +///////////////////////////////////////////////////////////////////////////// +//////////////////////// CPLB Setup ///////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + // Setup CPLB for Data Memory starting at 0x00F0_0000; +WR_MMR(DCPLB_DATA0, DATA_ADDR_1, p0, r0); + //WR_MMR(DCPLB_DATA0, 0x00031005, p0, r0); // Page Size = 4MB + // CPLB_L1_CHLB = 1 + // CPLB_USER_RD = 1 + // CPLB_VALID = 1 + // + + // Setup CPLB Address to point to 0x00F0_0000 +WR_MMR(DCPLB_ADDR0, DATA_ADDR_2, p0, r0); + //WR_MMR(DCPLB_ADDR0, 0x00F00000, p0, r0); + + // Enable CPLB's +WR_MMR(DMEM_CONTROL, DATA_ADDR_3, p0, r0); + //WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1 + // ENDCPLB = 1 + // DMC = 11 + // Sync it! +CSYNC; + + + // Return to Supervisor Code +RAISE 15; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + + R3 = SEQSTAT; + R4 = RETX; + R4 += 8; +RETX = R4; +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +NOP; +ASTAT = R7; +RETS = R7; +LC0 = R7; +LB0 = R7; +LT0 = R7; +LC1 = R7; +LB1 = R7; +LT1 = R7; +CYCLES = R7; +CYCLES2 = R7; +SYSCFG = R7; +RETN = R7; +RETX = R7; +RETE = R7; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +EXCPT 1; +ASTAT = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 2; +RETS = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 3; +LC0 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 4; +LT0 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 5; +LB0 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 6; +LC1 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 7; +LB1 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 8; +LT1 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 9; +CYCLES = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 10; +CYCLES2 = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 11; +SYSCFG = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 12; +RETI = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 13; +RETX = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 14; +RETN = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; +EXCPT 15; +RETE = [ SP ++ ]; +NOP; +NOP; +NOP; +NOP; + +NOP; +NOP; +NOP; +NOP; + + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +// Define Kernal Stack +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +.section MEM_DATA_ADDR_2 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; +.dd 0xdeadbeef; + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_regmv_usp_sysreg.S b/sim/testsuite/sim/bfin/se_regmv_usp_sysreg.S new file mode 100644 index 0000000..9d776ac --- /dev/null +++ b/sim/testsuite/sim/bfin/se_regmv_usp_sysreg.S @@ -0,0 +1,171 @@ +//Original:/proj/frio/dv/testcases/seq/se_regmv_usp_sysreg/se_regmv_usp_sysreg.dsp +// Description: RegMV USP to SYSREG +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(selfcheck.inc) +include(std.inc) +include(symtable.inc) + +//********************************************************************* + +BEGIN: + + // KLUDGE: from perl script must place cycles 2 write before cycles + // write, and cycles 2 read AFTER cycles read + + // PUT YOUR TEST HERE! + R0 = 0; +SP = R0; +SYSCFG = R0; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + + R0 = 0x59c4 (Z); + R0.H = 0x95a6; +USP = R0; +ASTAT = USP; + R1 = ASTAT; + + R0 = 0xd4a4 (Z); + R0.H = 0xd16c; +USP = R0; +RETS = USP; + R1 = RETS; +CHECKREG(r1, 3513570468); + + R0 = 0x2bca (Z); + R0.H = 0x6ad8; +USP = R0; +LC0 = USP; + R1 = LC0; +CHECKREG(r1, 1792551882); + + R0 = 0x6d4a (Z); + R0.H = 0xada2; +USP = R0; +LT0 = USP; + R1 = LT0; +CHECKREG(r1, 2913103178); + + R0 = 0x6b18 (Z); + R0.H = 0x931c; +USP = R0; +LB0 = USP; + R1 = LB0; +CHECKREG(r1, 2468113176); + + R0 = 0x62da (Z); + R0.H = 0x16ee; +USP = R0; +LC1 = USP; + R1 = LC1; +CHECKREG(r1, 384721626); + + R0 = 0x7c60 (Z); + R0.H = 0xf7c8; +USP = R0; +LT1 = USP; + R1 = LT1; +CHECKREG(r1, 4157111392); + + R0 = 0x182 (Z); + R0.H = 0x942; +USP = R0; +LB1 = USP; + R1 = LB1; +CHECKREG(r1, 155320706); + + R0 = 0xd5a2 (Z); + R0.H = 0x8782; +USP = R0; +CYCLES2 = USP; + // KLUDGE - moved read after that for cycles + + R0 = 0x297c (Z); + R0.H = 0x9d06; +USP = R0; +CYCLES = USP; + R1 = CYCLES; +CHECKREG(r1, 2634426748); + R1 = CYCLES2; // KLUDGE moved read after that for cycles +CHECKREG(r1, 2273498530); + + R0 = 0x8c66 (Z); + R0.H = 0x3d64; +USP = R0; +SEQSTAT = USP; + R1 = SEQSTAT; + + R0 = 0x3b8c (Z); + R0.H = 0xdcd4; +USP = R0; +SYSCFG = USP; + R1 = SYSCFG; + + R0 = 0xb1ae (Z); + R0.H = 0x6f6; +USP = R0; +RETI = USP; + R1 = RETI; +CHECKREG(r1, 116830638); + + R0 = 0x32b0 (Z); + R0.H = 0x9b7e; +USP = R0; +RETX = USP; + R1 = RETX; +CHECKREG(r1, 2608738992); + + R0 = 0xea72 (Z); + R0.H = 0x11ea; +USP = R0; +RETN = USP; + R1 = RETN; +CHECKREG(r1, 300608114); + + R0 = 0x2c58 (Z); + R0.H = 0xb13a; +USP = R0; +RETE = USP; + R1 = RETE; +CHECKREG(r1, 2973379672); + +// Sanity check +USP = R0; +USP = R1; +USP = R2; +USP = R3; +USP = R4; +USP = R5; +USP = R6; +USP = R7; +USP = P0; +USP = P1; +USP = P2; +USP = P3; +USP = P4; +USP = P5; +USP = SP; +USP = FP; +USP = A0.X; +USP = A0.W; +USP = A1.X; +USP = A1.W; +A0.X = USP; +A0.W = USP; +A1.X = USP; +A1.W = USP; + +END: +dbg_pass; // End the test + +//********************************************************************* diff --git a/sim/testsuite/sim/bfin/se_rets_hazard.s b/sim/testsuite/sim/bfin/se_rets_hazard.s new file mode 100644 index 0000000..7406e87 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_rets_hazard.s @@ -0,0 +1,55 @@ +//Original:/testcases/seq/se_rets_hazard/se_rets_hazard.dsp +# mach: bfin + +.include "testutils.inc" + start + + +BOOT: + FP = SP; // and frame pointer + + INIT_R_REGS 0; // initialize general purpose regs + + + + + ASTAT = r0; // reset sequencer registers + +// The Main Program + + +START: + loadsym r1, SUB1; + RETS = r1; + RTS; + +MID1: + CHECKREG r6, 0; // shouldn't be BAD + R6.L = 0xBAD2; // In case we come back to MID1 + loadsym P1, MID2; + CALL ( P1 ); + RTS; + +MID2: + loadsym R1, END; + RETS = r1; + [ -- SP ] = I0; + LINK 0; + I0 = FP; + UNLINK; + RTS; + +END: + + pass // Call Endtest Macro + +// Subroutines and Functions + +SUB1: // Code goes here + CHECKREG r7, 0; // should be if sub executed + R7.L = 0xBAD; // In case we come back to SUB1 + loadsym R2, MID1; + [ -- SP ] = R2; + RETS = [sp++]; + RTS; + R6.L = 0xBAD; diff --git a/sim/testsuite/sim/bfin/se_rts_rti.S b/sim/testsuite/sim/bfin/se_rts_rti.S new file mode 100644 index 0000000..8767d67 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_rts_rti.S @@ -0,0 +1,442 @@ +//Original:/proj/frio/dv/testcases/seq/se_rts_rti/se_rts_rti.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) +include(symtable.inc) +include(mmrs.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE CODE_ADDR_1 // +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE CODE_ADDR_2 // +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT0); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + + // Load RETS +LD32_LABEL(r0, USER_CODE); +RETS = R0; + + // Return to Supervisor Code +RAISE 2; +RAISE 5; +RAISE 6; +RAISE 7; +RAISE 8; +RAISE 9; +RAISE 10; +RAISE 11; +RAISE 12; +RAISE 13; +RAISE 14; +RAISE 15; +NOP; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +RTI; +NOP; +NOP; +RTS; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +EXCPT 0x5; +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" +.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +// Define Kernal Stack +.data + .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> + KSTACK : + + .space (STACKSIZE); + USTACK : + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_ssstep_dagprotviol.S b/sim/testsuite/sim/bfin/se_ssstep_dagprotviol.S new file mode 100644 index 0000000..bd4daf3 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_ssstep_dagprotviol.S @@ -0,0 +1,297 @@ +//Original:/proj/frio/dv/testcases/seq/se_ssstep_dagprotviol/se_ssstep_dagprotviol.dsp +// Description: prioritize DAG Protection Violation and Supervisor Single Step +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +RETS = r0; // prevent X's breaking LINK instruction + + R0 = 1; +SYSCFG = r0; // enable ssstep + + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests +// [--sp] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // PUT YOUR TEST HERE! + +NOP; + I0 += 2; + I1 += 2; + I2 += 2; + R7 = [ P0 ]; // cause DAG PROTECTION VIOLATION (p0 is an MMR) + I3 += 2; + + +EXCPT 2; // turn off SSSTEP + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + +CHECKREG(r5, 7); // check the flag (# SSSTEP) +CHECKREG(r4, 1); // check the flag (# illegal opcodes) + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 +CC = r7 == r6; +IF CC JUMP EXCPT2; + + R6 = 0x10; // EXCAUSE 0x10 means Single Step +CC = r7 == r6; +IF CC JUMP SSSTEP (BP); + + R6 = 0x23; // EXCAUSE 0x23 means DAG Protection Violation +CC = r7 == r6; +IF CC JUMP DAGPROTVIOL (BP); + +JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop + +EXCPT2: // turn off SSSTEP + R7 = 0; +SYSCFG = r7; +JUMP.S OUT; + +SSSTEP: + R5 += 1; // increment a counter +JUMP.S OUT; + +DAGPROTVIOL: + R7 = RETX; + R7 += 2; +RETX = R7; // skip offending instruction + + R4 += 1; // increment another counter + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.section MEM_DATA_ADDR_1 //.data 0xE0000000,"aw" +DATA: + .space (0x10); + +DATADUMMY: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_ssync.S b/sim/testsuite/sim/bfin/se_ssync.S new file mode 100644 index 0000000..e59f2f5 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_ssync.S @@ -0,0 +1,61 @@ +//Original:/proj/frio/dv/testcases/seq/se_ssync/se_ssync.dsp +// Description: Test SSYNC by writing a bunch of MMRs and verifying read +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif + +LD32(p0, EVT5); +LD32(r0, 0x55555555); +LD32(p1, EVT6); +LD32(r1, 0xAAAAAAAA); +LD32(p2, EVT7); +LD32(r2, 0xBABEFACE); +LD32(p3, EVT8); +LD32(r3, 0xCFCFCFCF); +LD32(p4, EVT9); +LD32(r4, 0xDEADBEEF); +LD32(p5, EVT10); +LD32(r5, 0xBAD1BAD1); + + [ P0 ] = R0; // write the MMRS + [ P1 ] = R1; + [ P2 ] = R2; + [ P3 ] = R3; + [ P4 ] = R4; + [ P5 ] = R5; + +SSYNC; // wait for it + + R7 = [ P5 ]; // read back MMRs + R6 = [ P4 ]; // should be updated + R5 = [ P3 ]; + R4 = [ P2 ]; + R3 = [ P1 ]; + R2 = [ P0 ]; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + +CHECKREG(r2, 0x55555555); +CHECKREG(r3, 0xAAAAAAAA); +CHECKREG(r4, 0xBABEFACE); +CHECKREG(r5, 0xCFCFCFCF); +CHECKREG(r6, 0xDEADBEEF); +CHECKREG(r7, 0xBAD1BAD1); + +dbg_pass; diff --git a/sim/testsuite/sim/bfin/se_stall_if2.S b/sim/testsuite/sim/bfin/se_stall_if2.S new file mode 100644 index 0000000..a6c939f --- /dev/null +++ b/sim/testsuite/sim/bfin/se_stall_if2.S @@ -0,0 +1,458 @@ +//Original:/proj/frio/dv/testcases/seq/se_stall_if2/se_stall_if2.dsp +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Include Files ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +include(std.inc) +include(selfcheck.inc) + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// Defines ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +#ifndef USER_CODE_SPACE +#define USER_CODE_SPACE 0x00000500 +#endif +#ifndef STACKSIZE +#define STACKSIZE 0x00000010 +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif +#ifndef EVT +#define EVT 0xFFE02000 +#endif +#ifndef EVT_OVERRIDE +#define EVT_OVERRIDE 0xFFE02100 +#endif +#ifndef IMASK +#define IMASK 0xFFE02104 +#endif +#ifndef DMEM_CONTROL +#define DMEM_CONTROL 0xFFE00004 +#endif +#ifndef DCPLB_ADDR0 +#define DCPLB_ADDR0 0xFFE00100 +#endif +#ifndef DCPLB_DATA0 +#define DCPLB_DATA0 0xFFE00200 +#endif + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// RESET ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + RST_ISR : + + // Initialize Dregs +INIT_R_REGS(0); + + // Initialize Pregs +INIT_P_REGS(0); + + // Initialize ILBM Registers +INIT_I_REGS(0); +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + + // Initialize the Address of the Checkreg data segment + // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** +CHECK_INIT(p5, 0x00BFFFFC); + + // Setup User Stack +LD32_LABEL(sp, USTACK); +USP = SP; + + // Setup Kernel Stack +LD32_LABEL(sp, KSTACK); + + // Setup Frame Pointer +FP = SP; + + // Setup Event Vector Table +LD32(p0, EVT); + +LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) + [ P0 ++ ] = R0; +LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) + [ P0 ++ ] = R0; +LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) + [ P0 ++ ] = R0; +LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) + [ P0 ++ ] = R0; + [ P0 ++ ] = R0; // IVT4 not used +LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) + [ P0 ++ ] = R0; +LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler + [ P0 ++ ] = R0; +LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler + [ P0 ++ ] = R0; + + // Setup the EVT_OVERRIDE MMR + R0 = 0; +LD32(p0, EVT_OVERRIDE); + [ P0 ] = R0; + + // Setup Interrupt Mask + R0 = -1; +LD32(p0, IMASK); + [ P0 ] = R0; + +///////////////////////////////////////////////////////////////////////////// +//////////////////////// CPLB Setup ///////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + // Setup CPLB for Data Memory starting at 0x00F0_0000; +WR_MMR(DCPLB_DATA0, 0x00031005, p0, r0); // Page Size = 4MB + // CPLB_L1_CHLB = 1 + // CPLB_USER_RD = 1 + // CPLB_VALID = 1 + // + + // Setup CPLB Address to point to 0x00F0_0000 +WR_MMR(DCPLB_ADDR0, 0x00F00000, p0, r0); + + // Enable CPLB's +WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1 + // ENDCPLB = 1 + // DMC = 11 + // Sync it! +CSYNC; + + + // Return to Supervisor Code +RAISE 15; + +LD32_LABEL(r0, USER_CODE); +RETI = R0; +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EMU ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EMU_ISR : + +RTE; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// NMI ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + NMI_ISR : + +RTN; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// EXC ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + EXC_ISR : + +RTX; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// HWE ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + HWE_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// TMR ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + TMR_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV7 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV7_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV8 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV8_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV9 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV9_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV10 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV10_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV11 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV11_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV12 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV12_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV13 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV13_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV14 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV14_ISR : + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// IGV15 ISR ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + IGV15_ISR : + +NOP; + P0 = 0x0100 (Z); + P0.H = 0x00f0; + R0 = [ P0 ++ ]; +JUMP.S lab1; // Branch in EX1 + + +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; +NOP; + +lab1: + P0 = 0x0200 (Z); + P0.H = 0x00f0; +RTI; + R1 = [ P0 ++ ]; +JUMP.S 8; // Branch in EX1 +NOP; +NOP; +NOP; + +RTI; + +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF +.dw 0xFFFF + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// USER CODE ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + + + USER_CODE : + +NOP; +NOP; +NOP; +NOP; +dbg_pass; // Call Endtest Macro + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// DATA MEMRORY ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// + +// Define Kernal Stack +.section MEM_0xE0000000,"aw" + .space (STACKSIZE); + KSTACK : + + .space (STACKSIZE); + USTACK : + +.section MEM_0x00F00100,"aw" +.dd 0xdeadbeef; +.section MEM_0x00F00200,"aw" +.dd 0x01010101; +.dd 0x02020202; +.dd 0x03030303; +.dd 0x04040404; + +///////////////////////////////////////////////////////////////////////////// +///////////////////////// END OF TEST ///////////////////////////// +///////////////////////////////////////////////////////////////////////////// diff --git a/sim/testsuite/sim/bfin/se_undefinedinstruction1.S b/sim/testsuite/sim/bfin/se_undefinedinstruction1.S new file mode 100644 index 0000000..5337a74 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_undefinedinstruction1.S @@ -0,0 +1,1102 @@ +//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction1/se_undefinedinstruction1.dsp +// Description: 16 bit "holes" Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + A0 = 0; // reset accumulators + A1 = 0; + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // count of UI's will be in r5, which was initialized to 0 by header + + + .dw 0x1 ; + .dw 0x2 ; + .dw 0x3 ; + .dw 0x4 ; + .dw 0x5 ; + .dw 0x6 ; + .dw 0x7 ; + .dw 0x8 ; + .dw 0x9 ; + .dw 0xA ; + .dw 0xB ; + .dw 0xC ; + .dw 0xD ; + .dw 0xE ; + .dw 0xF ; + .dw 0x15 ; + .dw 0x16 ; + .dw 0x17 ; + .dw 0x18 ; + .dw 0x19 ; + .dw 0x1A ; + .dw 0x1B ; + .dw 0x1C ; + .dw 0x1D ; + .dw 0x1E ; + .dw 0x1F ; + .dw 0x21 ; + .dw 0x22 ; + .dw 0x26 ; + .dw 0x27 ; // XXX: hardware doesnt trigger illegal exception ? + .dw 0x28 ; + .dw 0x29 ; + .dw 0x2A ; + .dw 0x2B ; + .dw 0x2C ; + .dw 0x2D ; + .dw 0x2E ; + .dw 0x2F ; + .dw 0x38 ; + .dw 0x39 ; + .dw 0x3A ; + .dw 0x3B ; + .dw 0x3C ; + .dw 0x3D ; + .dw 0x3E ; + .dw 0x3F ; + .dw 0x48 ; + .dw 0x49 ; + .dw 0x4A ; + .dw 0x4B ; + .dw 0x4C ; + .dw 0x4D ; + .dw 0x4E ; + .dw 0x4F ; + .dw 0x58 ; + .dw 0x59 ; + .dw 0x5A ; + .dw 0x5B ; + .dw 0x5C ; + .dw 0x5D ; + .dw 0x5E ; + .dw 0x5F ; + .dw 0x68 ; + .dw 0x69 ; + .dw 0x6A ; + .dw 0x6B ; + .dw 0x6C ; + .dw 0x6D ; + .dw 0x6E ; + .dw 0x6F ; + .dw 0x78 ; + .dw 0x79 ; + .dw 0x7A ; + .dw 0x7B ; + .dw 0x7C ; + .dw 0x7D ; + .dw 0x7E ; + .dw 0x7F ; + .dw 0x88 ; + .dw 0x89 ; + .dw 0x8A ; + .dw 0x8B ; + .dw 0x8C ; + .dw 0x8D ; + .dw 0x8E ; + .dw 0x8F ; + .dw 0xB8 ; + .dw 0xB9 ; + .dw 0xBA ; + .dw 0xBB ; + .dw 0xBC ; + .dw 0xBD ; + .dw 0xBE ; + .dw 0xBF ; + .dw 0xC0 ; + .dw 0xC1 ; + .dw 0xC2 ; + .dw 0xC3 ; + .dw 0xC4 ; + .dw 0xC5 ; + .dw 0xC6 ; + .dw 0xC7 ; + .dw 0xC8 ; + .dw 0xC9 ; + .dw 0xCA ; + .dw 0xCB ; + .dw 0xCC ; + .dw 0xCD ; + .dw 0xCE ; + .dw 0xCF ; + .dw 0xD0 ; + .dw 0xD1 ; + .dw 0xD2 ; + .dw 0xD3 ; + .dw 0xD4 ; + .dw 0xD5 ; + .dw 0xD6 ; + .dw 0xD7 ; + .dw 0xD8 ; + .dw 0xD9 ; + .dw 0xDA ; + .dw 0xDB ; + .dw 0xDC ; + .dw 0xDD ; + .dw 0xDE ; + .dw 0xDF ; + .dw 0xE0 ; + .dw 0xE1 ; + .dw 0xE2 ; + .dw 0xE3 ; + .dw 0xE4 ; + .dw 0xE5 ; + .dw 0xE6 ; + .dw 0xE7 ; + .dw 0xE8 ; + .dw 0xE9 ; + .dw 0xEA ; + .dw 0xEB ; + .dw 0xEC ; + .dw 0xED ; + .dw 0xEE ; + .dw 0xEF ; + .dw 0xF0 ; + .dw 0xF1 ; + .dw 0xF2 ; + .dw 0xF3 ; + .dw 0xF4 ; + .dw 0xF5 ; + .dw 0xF6 ; + .dw 0xF7 ; + .dw 0xF8 ; + .dw 0xF9 ; + .dw 0xFA ; + .dw 0xFB ; + .dw 0xFC ; + .dw 0xFD ; + .dw 0xFE ; + .dw 0xFF ; + .dw 0x220 ; + .dw 0x221 ; + .dw 0x222 ; + .dw 0x223 ; + .dw 0x224 ; + .dw 0x225 ; + .dw 0x226 ; + .dw 0x227 ; + .dw 0x228 ; + .dw 0x229 ; + .dw 0x22A ; + .dw 0x22B ; + .dw 0x22C ; + .dw 0x22D ; + .dw 0x22E ; + .dw 0x22F ; + .dw 0x230 ; + .dw 0x231 ; + .dw 0x232 ; + .dw 0x233 ; + .dw 0x234 ; + .dw 0x235 ; + .dw 0x236 ; + .dw 0x237 ; + .dw 0x238 ; + .dw 0x239 ; + .dw 0x23A ; + .dw 0x23B ; + .dw 0x23C ; + .dw 0x23D ; + .dw 0x23E ; + .dw 0x23F ; + .dw 0x280 ; + .dw 0x281 ; + .dw 0x282 ; + .dw 0x283 ; + .dw 0x284 ; + .dw 0x285 ; + .dw 0x286 ; + .dw 0x287 ; + .dw 0x288 ; + .dw 0x289 ; + .dw 0x28A ; + .dw 0x28B ; + .dw 0x28C ; + .dw 0x28D ; + .dw 0x28E ; + .dw 0x28F ; + .dw 0x290 ; + .dw 0x291 ; + .dw 0x292 ; + .dw 0x293 ; + .dw 0x294 ; + .dw 0x295 ; + .dw 0x296 ; + .dw 0x297 ; + .dw 0x298 ; + .dw 0x299 ; + .dw 0x29A ; + .dw 0x29B ; + .dw 0x29C ; + .dw 0x29D ; + .dw 0x29E ; + .dw 0x29F ; + .dw 0x2A0 ; + .dw 0x2A1 ; + .dw 0x2A2 ; + .dw 0x2A3 ; + .dw 0x2A4 ; + .dw 0x2A5 ; + .dw 0x2A6 ; + .dw 0x2A7 ; + .dw 0x2A8 ; + .dw 0x2A9 ; + .dw 0x2AA ; + .dw 0x2AB ; + .dw 0x2AC ; + .dw 0x2AD ; + .dw 0x2AE ; + .dw 0x2AF ; + .dw 0x2B0 ; + .dw 0x2B1 ; + .dw 0x2B2 ; + .dw 0x2B3 ; + .dw 0x2B4 ; + .dw 0x2B5 ; + .dw 0x2B6 ; + .dw 0x2B7 ; + .dw 0x2B8 ; + .dw 0x2B9 ; + .dw 0x2BA ; + .dw 0x2BB ; + .dw 0x2BC ; + .dw 0x2BD ; + .dw 0x2BE ; + .dw 0x2BF ; + .dw 0x2C0 ; + .dw 0x2C1 ; + .dw 0x2C2 ; + .dw 0x2C3 ; + .dw 0x2C4 ; + .dw 0x2C5 ; + .dw 0x2C6 ; + .dw 0x2C7 ; + .dw 0x2C8 ; + .dw 0x2C9 ; + .dw 0x2CA ; + .dw 0x2CB ; + .dw 0x2CC ; + .dw 0x2CD ; + .dw 0x2CE ; + .dw 0x2CF ; + .dw 0x2D0 ; + .dw 0x2D1 ; + .dw 0x2D2 ; + .dw 0x2D3 ; + .dw 0x2D4 ; + .dw 0x2D5 ; + .dw 0x2D6 ; + .dw 0x2D7 ; + .dw 0x2D8 ; + .dw 0x2D9 ; + .dw 0x2DA ; + .dw 0x2DB ; + .dw 0x2DC ; + .dw 0x2DD ; + .dw 0x2DE ; + .dw 0x2DF ; + .dw 0x2E0 ; + .dw 0x2E1 ; + .dw 0x2E2 ; + .dw 0x2E3 ; + .dw 0x2E4 ; + .dw 0x2E5 ; + .dw 0x2E6 ; + .dw 0x2E7 ; + .dw 0x2E8 ; + .dw 0x2E9 ; + .dw 0x2EA ; + .dw 0x2EB ; + .dw 0x2EC ; + .dw 0x2ED ; + .dw 0x2EE ; + .dw 0x2EF ; + .dw 0x2F0 ; + .dw 0x2F1 ; + .dw 0x2F2 ; + .dw 0x2F3 ; + .dw 0x2F4 ; + .dw 0x2F5 ; + .dw 0x2F6 ; + .dw 0x2F7 ; + .dw 0x2F8 ; + .dw 0x2F9 ; + .dw 0x2FA ; + .dw 0x2FB ; + .dw 0x2FC ; + .dw 0x2FD ; + .dw 0x2FE ; + .dw 0x2FF ; + .dw 0x4600 ; + .dw 0x4601 ; + .dw 0x4602 ; + .dw 0x4603 ; + .dw 0x4604 ; + .dw 0x4605 ; + .dw 0x4606 ; + .dw 0x4607 ; + .dw 0x4608 ; + .dw 0x4609 ; + .dw 0x460A ; + .dw 0x460B ; + .dw 0x460C ; + .dw 0x460D ; + .dw 0x460E ; + .dw 0x460F ; + .dw 0x4610 ; + .dw 0x4611 ; + .dw 0x4612 ; + .dw 0x4613 ; + .dw 0x4614 ; + .dw 0x4615 ; + .dw 0x4616 ; + .dw 0x4617 ; + .dw 0x4618 ; + .dw 0x4619 ; + .dw 0x461A ; + .dw 0x461B ; + .dw 0x461C ; + .dw 0x461D ; + .dw 0x461E ; + .dw 0x461F ; + .dw 0x4620 ; + .dw 0x4621 ; + .dw 0x4622 ; + .dw 0x4623 ; + .dw 0x4624 ; + .dw 0x4625 ; + .dw 0x4626 ; + .dw 0x4627 ; + .dw 0x4628 ; + .dw 0x4629 ; + .dw 0x462A ; + .dw 0x462B ; + .dw 0x462C ; + .dw 0x462D ; + .dw 0x462E ; + .dw 0x462F ; + .dw 0x4630 ; + .dw 0x4631 ; + .dw 0x4632 ; + .dw 0x4633 ; + .dw 0x4634 ; + .dw 0x4635 ; + .dw 0x4636 ; + .dw 0x4637 ; + .dw 0x4638 ; + .dw 0x4639 ; + .dw 0x463A ; + .dw 0x463B ; + .dw 0x463C ; + .dw 0x463D ; + .dw 0x463E ; + .dw 0x463F ; + .dw 0x4640 ; + .dw 0x4641 ; + .dw 0x4642 ; + .dw 0x4643 ; + .dw 0x4644 ; + .dw 0x4645 ; + .dw 0x4646 ; + .dw 0x4647 ; + .dw 0x4648 ; + .dw 0x4649 ; + .dw 0x464A ; + .dw 0x464B ; + .dw 0x464C ; + .dw 0x464D ; + .dw 0x464E ; + .dw 0x464F ; + .dw 0x4650 ; + .dw 0x4651 ; + .dw 0x4652 ; + .dw 0x4653 ; + .dw 0x4654 ; + .dw 0x4655 ; + .dw 0x4656 ; + .dw 0x4657 ; + .dw 0x4658 ; + .dw 0x4659 ; + .dw 0x465A ; + .dw 0x465B ; + .dw 0x465C ; + .dw 0x465D ; + .dw 0x465E ; + .dw 0x465F ; + .dw 0x4660 ; + .dw 0x4661 ; + .dw 0x4662 ; + .dw 0x4663 ; + .dw 0x4664 ; + .dw 0x4665 ; + .dw 0x4666 ; + .dw 0x4667 ; + .dw 0x4668 ; + .dw 0x4669 ; + .dw 0x466A ; + .dw 0x466B ; + .dw 0x466C ; + .dw 0x466D ; + .dw 0x466E ; + .dw 0x466F ; + .dw 0x4670 ; + .dw 0x4671 ; + .dw 0x4672 ; + .dw 0x4673 ; + .dw 0x4674 ; + .dw 0x4675 ; + .dw 0x4676 ; + .dw 0x4677 ; + .dw 0x4678 ; + .dw 0x4679 ; + .dw 0x467A ; + .dw 0x467B ; + .dw 0x467C ; + .dw 0x467D ; + .dw 0x467E ; + .dw 0x467F ; + .dw 0x4680 ; + .dw 0x4681 ; + .dw 0x4682 ; + .dw 0x4683 ; + .dw 0x4684 ; + .dw 0x4685 ; + .dw 0x4686 ; + .dw 0x4687 ; + .dw 0x4688 ; + .dw 0x4689 ; + .dw 0x468A ; + .dw 0x468B ; + .dw 0x468C ; + .dw 0x468D ; + .dw 0x468E ; + .dw 0x468F ; + .dw 0x4690 ; + .dw 0x4691 ; + .dw 0x4692 ; + .dw 0x4693 ; + .dw 0x4694 ; + .dw 0x4695 ; + .dw 0x4696 ; + .dw 0x4697 ; + .dw 0x4698 ; + .dw 0x4699 ; + .dw 0x469A ; + .dw 0x469B ; + .dw 0x469C ; + .dw 0x469D ; + .dw 0x469E ; + .dw 0x469F ; + .dw 0x46A0 ; + .dw 0x46A1 ; + .dw 0x46A2 ; + .dw 0x46A3 ; + .dw 0x46A4 ; + .dw 0x46A5 ; + .dw 0x46A6 ; + .dw 0x46A7 ; + .dw 0x46A8 ; + .dw 0x46A9 ; + .dw 0x46AA ; + .dw 0x46AB ; + .dw 0x46AC ; + .dw 0x46AD ; + .dw 0x46AE ; + .dw 0x46AF ; + .dw 0x46B0 ; + .dw 0x46B1 ; + .dw 0x46B2 ; + .dw 0x46B3 ; + .dw 0x46B4 ; + .dw 0x46B5 ; + .dw 0x46B6 ; + .dw 0x46B7 ; + .dw 0x46B8 ; + .dw 0x46B9 ; + .dw 0x46BA ; + .dw 0x46BB ; + .dw 0x46BC ; + .dw 0x46BD ; + .dw 0x46BE ; + .dw 0x46BF ; + .dw 0x46C0 ; + .dw 0x46C1 ; + .dw 0x46C2 ; + .dw 0x46C3 ; + .dw 0x46C4 ; + .dw 0x46C5 ; + .dw 0x46C6 ; + .dw 0x46C7 ; + .dw 0x46C8 ; + .dw 0x46C9 ; + .dw 0x46CA ; + .dw 0x46CB ; + .dw 0x46CC ; + .dw 0x46CD ; + .dw 0x46CE ; + .dw 0x46CF ; + .dw 0x46D0 ; + .dw 0x46D1 ; + .dw 0x46D2 ; + .dw 0x46D3 ; + .dw 0x46D4 ; + .dw 0x46D5 ; + .dw 0x46D6 ; + .dw 0x46D7 ; + .dw 0x46D8 ; + .dw 0x46D9 ; + .dw 0x46DA ; + .dw 0x46DB ; + .dw 0x46DC ; + .dw 0x46DD ; + .dw 0x46DE ; + .dw 0x46DF ; + .dw 0x46E0 ; + .dw 0x46E1 ; + .dw 0x46E2 ; + .dw 0x46E3 ; + .dw 0x46E4 ; + .dw 0x46E5 ; + .dw 0x46E6 ; + .dw 0x46E7 ; + .dw 0x46E8 ; + .dw 0x46E9 ; + .dw 0x46EA ; + .dw 0x46EB ; + .dw 0x46EC ; + .dw 0x46ED ; + .dw 0x46EE ; + .dw 0x46EF ; + .dw 0x46F0 ; + .dw 0x46F1 ; + .dw 0x46F2 ; + .dw 0x46F3 ; + .dw 0x46F4 ; + .dw 0x46F5 ; + .dw 0x46F6 ; + .dw 0x46F7 ; + .dw 0x46F8 ; + .dw 0x46F9 ; + .dw 0x46FA ; + .dw 0x46FB ; + .dw 0x46FC ; + .dw 0x46FD ; + .dw 0x46FE ; + .dw 0x46FF ; + .dw 0x4700 ; + .dw 0x4701 ; + .dw 0x4702 ; + .dw 0x4703 ; + .dw 0x4704 ; + .dw 0x4705 ; + .dw 0x4706 ; + .dw 0x4707 ; + .dw 0x4708 ; + .dw 0x4709 ; + .dw 0x470A ; + .dw 0x470B ; + .dw 0x470C ; + .dw 0x470D ; + .dw 0x470E ; + .dw 0x470F ; + .dw 0x4710 ; + .dw 0x4711 ; + .dw 0x4712 ; + .dw 0x4713 ; + .dw 0x4714 ; + .dw 0x4715 ; + .dw 0x4716 ; + .dw 0x4717 ; + .dw 0x4718 ; + .dw 0x4719 ; + .dw 0x471A ; + .dw 0x471B ; + .dw 0x471C ; + .dw 0x471D ; + .dw 0x471E ; + .dw 0x471F ; + .dw 0x4720 ; + .dw 0x4721 ; + .dw 0x4722 ; + .dw 0x4723 ; + .dw 0x4724 ; + .dw 0x4725 ; + .dw 0x4726 ; + .dw 0x4727 ; + .dw 0x4728 ; + .dw 0x4729 ; + .dw 0x472A ; + .dw 0x472B ; + .dw 0x472C ; + .dw 0x472D ; + .dw 0x472E ; + .dw 0x472F ; + .dw 0x4730 ; + .dw 0x4731 ; + .dw 0x4732 ; + .dw 0x4733 ; + .dw 0x4734 ; + .dw 0x4735 ; + .dw 0x4736 ; + .dw 0x4737 ; + .dw 0x4738 ; + .dw 0x4739 ; + .dw 0x473A ; + .dw 0x473B ; + .dw 0x473C ; + .dw 0x473D ; + .dw 0x473E ; + .dw 0x473F ; + .dw 0x4740 ; + .dw 0x4741 ; + .dw 0x4742 ; + .dw 0x4743 ; + .dw 0x4744 ; + .dw 0x4745 ; + .dw 0x4746 ; + .dw 0x4747 ; + .dw 0x4748 ; + .dw 0x4749 ; + .dw 0x474A ; + .dw 0x474B ; + .dw 0x474C ; + .dw 0x474D ; + .dw 0x474E ; + .dw 0x474F ; + .dw 0x4750 ; + .dw 0x4751 ; + .dw 0x4752 ; + .dw 0x4753 ; + .dw 0x4754 ; + .dw 0x4755 ; + .dw 0x4756 ; + .dw 0x4757 ; + .dw 0x4758 ; + .dw 0x4759 ; + .dw 0x475A ; + .dw 0x475B ; + .dw 0x475C ; + .dw 0x475D ; + .dw 0x475E ; + .dw 0x475F ; + .dw 0x4760 ; + .dw 0x4761 ; + .dw 0x4762 ; + .dw 0x4763 ; + .dw 0x4764 ; + .dw 0x4765 ; + .dw 0x4766 ; + .dw 0x4767 ; + .dw 0x4768 ; + .dw 0x4769 ; + .dw 0x476A ; + .dw 0x476B ; + .dw 0x476C ; + .dw 0x476D ; + .dw 0x476E ; + .dw 0x476F ; + .dw 0x4770 ; + .dw 0x4771 ; + .dw 0x4772 ; + .dw 0x4773 ; + .dw 0x4774 ; + .dw 0x4775 ; + .dw 0x4776 ; + .dw 0x4777 ; + .dw 0x4778 ; + .dw 0x4779 ; + .dw 0x477A ; + .dw 0x477B ; + .dw 0x477C ; + .dw 0x477D ; + .dw 0x477E ; + .dw 0x477F ; + .dw 0x4780 ; + .dw 0x4781 ; + .dw 0x4782 ; + .dw 0x4783 ; + .dw 0x4784 ; + .dw 0x4785 ; + .dw 0x4786 ; + .dw 0x4787 ; + .dw 0x4788 ; + .dw 0x4789 ; + .dw 0x478A ; + .dw 0x478B ; + .dw 0x478C ; + .dw 0x478D ; + .dw 0x478E ; + .dw 0x478F ; + .dw 0x4790 ; + .dw 0x4791 ; + .dw 0x4792 ; + .dw 0x4793 ; + .dw 0x4794 ; + .dw 0x4795 ; + .dw 0x4796 ; + .dw 0x4797 ; + .dw 0x4798 ; + .dw 0x4799 ; + .dw 0x479A ; + .dw 0x479B ; + .dw 0x479C ; + .dw 0x479D ; + .dw 0x479E ; + .dw 0x479F ; + .dw 0x47A0 ; + .dw 0x47A1 ; + .dw 0x47A2 ; + .dw 0x47A3 ; + .dw 0x47A4 ; + .dw 0x47A5 ; + .dw 0x47A6 ; + .dw 0x47A7 ; + .dw 0x47A8 ; + .dw 0x47A9 ; + .dw 0x47AA ; + .dw 0x47AB ; + .dw 0x47AC ; + .dw 0x47AD ; + .dw 0x47AE ; + .dw 0x47AF ; + .dw 0x47B0 ; + .dw 0x47B1 ; + .dw 0x47B2 ; + .dw 0x47B3 ; + .dw 0x47B4 ; + .dw 0x47B5 ; + .dw 0x47B6 ; + .dw 0x47B7 ; + .dw 0x47B8 ; + .dw 0x47B9 ; + .dw 0x47BA ; + .dw 0x47BB ; + .dw 0x47BC ; + .dw 0x47BD ; + .dw 0x47BE ; + .dw 0x47BF ; + .dw 0x47C0 ; + .dw 0x47C1 ; + .dw 0x47C2 ; + .dw 0x47C3 ; + .dw 0x47C4 ; + .dw 0x47C5 ; + .dw 0x47C6 ; + .dw 0x47C7 ; + .dw 0x47C8 ; + .dw 0x47C9 ; + .dw 0x47CA ; + .dw 0x47CB ; + .dw 0x47CC ; + .dw 0x47CD ; + .dw 0x47CE ; + .dw 0x47CF ; + .dw 0x47D0 ; + .dw 0x47D1 ; + .dw 0x47D2 ; + .dw 0x47D3 ; + .dw 0x47D4 ; + .dw 0x47D5 ; + .dw 0x47D6 ; + .dw 0x47D7 ; + .dw 0x47D8 ; + .dw 0x47D9 ; + .dw 0x47DA ; + .dw 0x47DB ; + .dw 0x47DC ; + .dw 0x47DD ; + .dw 0x47DE ; + .dw 0x47DF ; + .dw 0x47E0 ; + .dw 0x47E1 ; + .dw 0x47E2 ; + .dw 0x47E3 ; + .dw 0x47E4 ; + .dw 0x47E5 ; + .dw 0x47E6 ; + .dw 0x47E7 ; + .dw 0x47E8 ; + .dw 0x47E9 ; + .dw 0x47EA ; + .dw 0x47EB ; + .dw 0x47EC ; + .dw 0x47ED ; + .dw 0x47EE ; + .dw 0x47EF ; + .dw 0x47F0 ; + .dw 0x47F1 ; + .dw 0x47F2 ; + .dw 0x47F3 ; + .dw 0x47F4 ; + .dw 0x47F5 ; + .dw 0x47F6 ; + .dw 0x47F7 ; + .dw 0x47F8 ; + .dw 0x47F9 ; + .dw 0x47FA ; + .dw 0x47FB ; + .dw 0x47FC ; + .dw 0x47FD ; + .dw 0x47FE ; + .dw 0x47FF ; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +CHECKREG(r5, 830); // count of all 16 bit UI's. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 16 bit illegal opcode handler - skips bad instruction + + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + +JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + R7 += 2; // skip offending 16 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_undefinedinstruction2.S b/sim/testsuite/sim/bfin/se_undefinedinstruction2.S new file mode 100644 index 0000000..d21e375 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_undefinedinstruction2.S @@ -0,0 +1,3147 @@ +//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction2/se_undefinedinstruction2.dsp +// Description: 16 bit special cases Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + A0 = 0; // reset accumulators + A1 = 0; + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); +r4 = p1; + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // count of UI's will be in r5, which was initialized to 0 by header + +// 16 bit special cases COUNT = 830 + .dw 0x10E ; + .dw 0x124 ; +.ifndef BFIN_HW + // XXX: hardware doesnt trigger illegal exception ? + .dw 0x125 ; +.endif + .dw 0x164 ; +.ifndef BFIN_HW + // XXX: hardware doesnt trigger illegal exception ? + .dw 0x165 ; +.endif + .dw 0x128 ; + .dw 0x129 ; + .dw 0x12A ; + .dw 0x12B ; + .dw 0x12C ; + .dw 0x12D ; + .dw 0x12E ; + .dw 0x12F ; + .dw 0x168 ; + .dw 0x169 ; + .dw 0x16A ; + .dw 0x16B ; + .dw 0x16C ; + .dw 0x16D ; + .dw 0x16E ; + .dw 0x16F ; +#if 0 + // EMUDAT = [SP++]; is valid + .dw 0x13F ; + // [SP++] = EMUDAT; is valid + .dw 0x17F ; +#endif + .dw 0x486 ; + .dw 0x487 ; + .dw 0x210 ; + .dw 0x211 ; + .dw 0x212 ; + .dw 0x213 ; + .dw 0x214 ; + .dw 0x215 ; + .dw 0x216 ; + .dw 0x217 ; + .dw 0x305 ; +#if 0 + // Not documented, but hardware takes them + // CC = + .dw 0x307 ; + .dw 0x308 ; + .dw 0x309 ; + .dw 0x30A ; + .dw 0x30B ; + .dw 0x30C ; + .dw 0x30D ; + .dw 0x30E ; + .dw 0x30F ; + .dw 0x310 ; + .dw 0x311 ; + .dw 0x312 ; + .dw 0x313 ; + .dw 0x314 ; + .dw 0x315 ; + .dw 0x316 ; + .dw 0x317 ; + .dw 0x318 ; + .dw 0x319 ; + .dw 0x31A ; + .dw 0x31B ; + .dw 0x31C ; + .dw 0x31D ; + .dw 0x31E ; + .dw 0x31F ; +#endif + .dw 0x325 ; +#if 0 + // Not documented, but hardware takes them + // CC |= + .dw 0x327 ; + .dw 0x328 ; + .dw 0x329 ; + .dw 0x32A ; + .dw 0x32B ; + .dw 0x32C ; + .dw 0x32D ; + .dw 0x32E ; + .dw 0x32F ; + .dw 0x330 ; + .dw 0x331 ; + .dw 0x332 ; + .dw 0x333 ; + .dw 0x334 ; + .dw 0x335 ; + .dw 0x336 ; + .dw 0x337 ; + .dw 0x338 ; + .dw 0x339 ; + .dw 0x33A ; + .dw 0x33B ; + .dw 0x33C ; + .dw 0x33D ; + .dw 0x33E ; + .dw 0x33F ; +#endif + .dw 0x345 ; +#if 0 + // Not documented, but hardware takes them + // CC &= + .dw 0x347 ; + .dw 0x348 ; + .dw 0x349 ; + .dw 0x34A ; + .dw 0x34B ; + .dw 0x34C ; + .dw 0x34D ; + .dw 0x34E ; + .dw 0x34F ; + .dw 0x350 ; + .dw 0x351 ; + .dw 0x352 ; + .dw 0x353 ; + .dw 0x354 ; + .dw 0x355 ; + .dw 0x356 ; + .dw 0x357 ; + .dw 0x358 ; + .dw 0x359 ; + .dw 0x35A ; + .dw 0x35B ; + .dw 0x35C ; + .dw 0x35D ; + .dw 0x35E ; + .dw 0x35F ; +#endif + .dw 0x365 ; +#if 0 + // Not documented, but hardware takes them + // CC ^= + .dw 0x367 ; + .dw 0x368 ; + .dw 0x369 ; + .dw 0x36A ; + .dw 0x36B ; + .dw 0x36C ; + .dw 0x36D ; + .dw 0x36E ; + .dw 0x36F ; + .dw 0x370 ; + .dw 0x371 ; + .dw 0x372 ; + .dw 0x373 ; + .dw 0x374 ; + .dw 0x375 ; + .dw 0x376 ; + .dw 0x377 ; + .dw 0x378 ; + .dw 0x379 ; + .dw 0x37A ; + .dw 0x37B ; + .dw 0x37C ; + .dw 0x37D ; + .dw 0x37E ; + .dw 0x37F ; +#endif + .dw 0x385 ; +#if 0 + // Not documented, but hardware takes them + // = CC + .dw 0x387 ; + .dw 0x388 ; + .dw 0x389 ; + .dw 0x38A ; + .dw 0x38B ; + .dw 0x38C ; + .dw 0x38D ; + .dw 0x38E ; + .dw 0x38F ; + .dw 0x390 ; + .dw 0x391 ; + .dw 0x392 ; + .dw 0x393 ; + .dw 0x394 ; + .dw 0x395 ; + .dw 0x396 ; + .dw 0x397 ; + .dw 0x398 ; + .dw 0x399 ; + .dw 0x39A ; + .dw 0x39B ; + .dw 0x39C ; + .dw 0x39D ; + .dw 0x39E ; + .dw 0x39F ; +#endif + .dw 0x3A5 ; +#if 0 + // Not documented, but hardware takes them + // |= CC + .dw 0x3A7 ; + .dw 0x3A8 ; + .dw 0x3A9 ; + .dw 0x3AA ; + .dw 0x3AB ; + .dw 0x3AC ; + .dw 0x3AD ; + .dw 0x3AE ; + .dw 0x3AF ; + .dw 0x3B0 ; + .dw 0x3B1 ; + .dw 0x3B2 ; + .dw 0x3B3 ; + .dw 0x3B4 ; + .dw 0x3B5 ; + .dw 0x3B6 ; + .dw 0x3B7 ; + .dw 0x3B8 ; + .dw 0x3B9 ; + .dw 0x3BA ; + .dw 0x3BB ; + .dw 0x3BC ; + .dw 0x3BD ; + .dw 0x3BE ; + .dw 0x3BF ; +#endif + .dw 0x3C5 ; +#if 0 + // Not documented, but hardware takes them + // &= CC + .dw 0x3C7 ; + .dw 0x3C8 ; + .dw 0x3C9 ; + .dw 0x3CA ; + .dw 0x3CB ; + .dw 0x3CC ; + .dw 0x3CD ; + .dw 0x3CE ; + .dw 0x3CF ; + .dw 0x3D0 ; + .dw 0x3D1 ; + .dw 0x3D2 ; + .dw 0x3D3 ; + .dw 0x3D4 ; + .dw 0x3D5 ; + .dw 0x3D6 ; + .dw 0x3D7 ; + .dw 0x3D8 ; + .dw 0x3D9 ; + .dw 0x3DA ; + .dw 0x3DB ; + .dw 0x3DC ; + .dw 0x3DD ; + .dw 0x3DE ; + .dw 0x3DF ; +#endif + .dw 0x3E5 ; +#if 0 + // Not documented, but hardware takes them + // ^= CC + .dw 0x3E7 ; + .dw 0x3E8 ; + .dw 0x3E9 ; + .dw 0x3EA ; + .dw 0x3EB ; + .dw 0x3EC ; + .dw 0x3ED ; + .dw 0x3EE ; + .dw 0x3EF ; + .dw 0x3F0 ; + .dw 0x3F1 ; + .dw 0x3F2 ; + .dw 0x3F3 ; + .dw 0x3F4 ; + .dw 0x3F5 ; + .dw 0x3F6 ; + .dw 0x3F7 ; + .dw 0x3F8 ; + .dw 0x3F9 ; + .dw 0x3FA ; + .dw 0x3FB ; + .dw 0x3FC ; + .dw 0x3FD ; + .dw 0x3FE ; + .dw 0x3FF ; +#endif + .dw 0x3A00 ; + .dw 0x3A01 ; + .dw 0x3A02 ; + .dw 0x3A03 ; + .dw 0x3A04 ; + .dw 0x3A05 ; + .dw 0x3A06 ; + .dw 0x3A07 ; + .dw 0x3A08 ; + .dw 0x3A09 ; + .dw 0x3A0A ; + .dw 0x3A0B ; + .dw 0x3A0C ; + .dw 0x3A0D ; + .dw 0x3A0E ; + .dw 0x3A0F ; + .dw 0x3A10 ; + .dw 0x3A11 ; + .dw 0x3A12 ; + .dw 0x3A13 ; + .dw 0x3A14 ; + .dw 0x3A15 ; + .dw 0x3A16 ; + .dw 0x3A17 ; + .dw 0x3A18 ; + .dw 0x3A19 ; + .dw 0x3A1A ; + .dw 0x3A1B ; + .dw 0x3A1C ; + .dw 0x3A1D ; + .dw 0x3A1E ; + .dw 0x3A1F ; + .dw 0x3A20 ; + .dw 0x3A21 ; + .dw 0x3A22 ; + .dw 0x3A23 ; + .dw 0x3A24 ; + .dw 0x3A25 ; + .dw 0x3A26 ; + .dw 0x3A27 ; + .dw 0x3A28 ; + .dw 0x3A29 ; + .dw 0x3A2A ; + .dw 0x3A2B ; + .dw 0x3A2C ; + .dw 0x3A2D ; + .dw 0x3A2E ; + .dw 0x3A2F ; + .dw 0x3A30 ; + .dw 0x3A31 ; + .dw 0x3A32 ; + .dw 0x3A33 ; + .dw 0x3A34 ; + .dw 0x3A35 ; + .dw 0x3A36 ; + .dw 0x3A37 ; + .dw 0x3A38 ; + .dw 0x3A39 ; + .dw 0x3A3A ; + .dw 0x3A3B ; + .dw 0x3A3C ; + .dw 0x3A3D ; + .dw 0x3A3E ; + .dw 0x3A3F ; + .dw 0x3A40 ; + .dw 0x3A41 ; + .dw 0x3A42 ; + .dw 0x3A43 ; + .dw 0x3A44 ; + .dw 0x3A45 ; + .dw 0x3A46 ; + .dw 0x3A47 ; + .dw 0x3A48 ; + .dw 0x3A49 ; + .dw 0x3A4A ; + .dw 0x3A4B ; + .dw 0x3A4C ; + .dw 0x3A4D ; + .dw 0x3A4E ; + .dw 0x3A4F ; + .dw 0x3A50 ; + .dw 0x3A51 ; + .dw 0x3A52 ; + .dw 0x3A53 ; + .dw 0x3A54 ; + .dw 0x3A55 ; + .dw 0x3A56 ; + .dw 0x3A57 ; + .dw 0x3A58 ; + .dw 0x3A59 ; + .dw 0x3A5A ; + .dw 0x3A5B ; + .dw 0x3A5C ; + .dw 0x3A5D ; + .dw 0x3A5E ; + .dw 0x3A5F ; + .dw 0x3A60 ; + .dw 0x3A61 ; + .dw 0x3A62 ; + .dw 0x3A63 ; + .dw 0x3A64 ; + .dw 0x3A65 ; + .dw 0x3A66 ; + .dw 0x3A67 ; + .dw 0x3A68 ; + .dw 0x3A69 ; + .dw 0x3A6A ; + .dw 0x3A6B ; + .dw 0x3A6C ; + .dw 0x3A6D ; + .dw 0x3A6E ; + .dw 0x3A6F ; + .dw 0x3A70 ; + .dw 0x3A71 ; + .dw 0x3A72 ; + .dw 0x3A73 ; + .dw 0x3A74 ; + .dw 0x3A75 ; + .dw 0x3A76 ; + .dw 0x3A77 ; + .dw 0x3A78 ; + .dw 0x3A79 ; + .dw 0x3A7A ; + .dw 0x3A7B ; + .dw 0x3A7C ; + .dw 0x3A7D ; + .dw 0x3A7E ; + .dw 0x3A7F ; + .dw 0x3A80 ; + .dw 0x3A81 ; + .dw 0x3A82 ; + .dw 0x3A83 ; + .dw 0x3A84 ; + .dw 0x3A85 ; + .dw 0x3A86 ; + .dw 0x3A87 ; + .dw 0x3A88 ; + .dw 0x3A89 ; + .dw 0x3A8A ; + .dw 0x3A8B ; + .dw 0x3A8C ; + .dw 0x3A8D ; + .dw 0x3A8E ; + .dw 0x3A8F ; + .dw 0x3A90 ; + .dw 0x3A91 ; + .dw 0x3A92 ; + .dw 0x3A93 ; + .dw 0x3A94 ; + .dw 0x3A95 ; + .dw 0x3A96 ; + .dw 0x3A97 ; + .dw 0x3A98 ; + .dw 0x3A99 ; + .dw 0x3A9A ; + .dw 0x3A9B ; + .dw 0x3A9C ; + .dw 0x3A9D ; + .dw 0x3A9E ; + .dw 0x3A9F ; + .dw 0x3AA0 ; + .dw 0x3AA1 ; + .dw 0x3AA2 ; + .dw 0x3AA3 ; + .dw 0x3AA4 ; + .dw 0x3AA5 ; + .dw 0x3AA6 ; + .dw 0x3AA7 ; + .dw 0x3AA8 ; + .dw 0x3AA9 ; + .dw 0x3AAA ; + .dw 0x3AAB ; + .dw 0x3AAC ; + .dw 0x3AAD ; + .dw 0x3AAE ; + .dw 0x3AAF ; + .dw 0x3AB0 ; + .dw 0x3AB1 ; + .dw 0x3AB2 ; + .dw 0x3AB3 ; + .dw 0x3AB4 ; + .dw 0x3AB5 ; + .dw 0x3AB6 ; + .dw 0x3AB7 ; + .dw 0x3AB8 ; + .dw 0x3AB9 ; + .dw 0x3ABA ; + .dw 0x3ABB ; + .dw 0x3ABC ; + .dw 0x3ABD ; + .dw 0x3ABE ; + .dw 0x3ABF ; + .dw 0x3AC0 ; + .dw 0x3AC1 ; + .dw 0x3AC2 ; + .dw 0x3AC3 ; + .dw 0x3AC4 ; + .dw 0x3AC5 ; + .dw 0x3AC6 ; + .dw 0x3AC7 ; + .dw 0x3AC8 ; + .dw 0x3AC9 ; + .dw 0x3ACA ; + .dw 0x3ACB ; + .dw 0x3ACC ; + .dw 0x3ACD ; + .dw 0x3ACE ; + .dw 0x3ACF ; + .dw 0x3AD0 ; + .dw 0x3AD1 ; + .dw 0x3AD2 ; + .dw 0x3AD3 ; + .dw 0x3AD4 ; + .dw 0x3AD5 ; + .dw 0x3AD6 ; + .dw 0x3AD7 ; + .dw 0x3AD8 ; + .dw 0x3AD9 ; + .dw 0x3ADA ; + .dw 0x3ADB ; + .dw 0x3ADC ; + .dw 0x3ADD ; + .dw 0x3ADE ; + .dw 0x3ADF ; + .dw 0x3AE0 ; + .dw 0x3AE1 ; + .dw 0x3AE2 ; + .dw 0x3AE3 ; + .dw 0x3AE4 ; + .dw 0x3AE5 ; + .dw 0x3AE6 ; + .dw 0x3AE7 ; + .dw 0x3AE8 ; + .dw 0x3AE9 ; + .dw 0x3AEA ; + .dw 0x3AEB ; + .dw 0x3AEC ; + .dw 0x3AED ; + .dw 0x3AEE ; + .dw 0x3AEF ; + .dw 0x3AF0 ; + .dw 0x3AF1 ; + .dw 0x3AF2 ; + .dw 0x3AF3 ; + .dw 0x3AF4 ; + .dw 0x3AF5 ; + .dw 0x3AF6 ; + .dw 0x3AF7 ; + .dw 0x3AF8 ; + .dw 0x3AF9 ; + .dw 0x3AFA ; + .dw 0x3AFB ; + .dw 0x3AFC ; + .dw 0x3AFD ; + .dw 0x3AFE ; + .dw 0x3AFF ; + .dw 0x3B00 ; + .dw 0x3B01 ; + .dw 0x3B02 ; + .dw 0x3B03 ; + .dw 0x3B04 ; + .dw 0x3B05 ; + .dw 0x3B06 ; + .dw 0x3B07 ; + .dw 0x3B08 ; + .dw 0x3B09 ; + .dw 0x3B0A ; + .dw 0x3B0B ; + .dw 0x3B0C ; + .dw 0x3B0D ; + .dw 0x3B0E ; + .dw 0x3B0F ; + .dw 0x3B10 ; + .dw 0x3B11 ; + .dw 0x3B12 ; + .dw 0x3B13 ; + .dw 0x3B14 ; + .dw 0x3B15 ; + .dw 0x3B16 ; + .dw 0x3B17 ; + .dw 0x3B18 ; + .dw 0x3B19 ; + .dw 0x3B1A ; + .dw 0x3B1B ; + .dw 0x3B1C ; + .dw 0x3B1D ; + .dw 0x3B1E ; + .dw 0x3B1F ; + .dw 0x3B20 ; + .dw 0x3B21 ; + .dw 0x3B22 ; + .dw 0x3B23 ; + .dw 0x3B24 ; + .dw 0x3B25 ; + .dw 0x3B26 ; + .dw 0x3B27 ; + .dw 0x3B28 ; + .dw 0x3B29 ; + .dw 0x3B2A ; + .dw 0x3B2B ; + .dw 0x3B2C ; + .dw 0x3B2D ; + .dw 0x3B2E ; + .dw 0x3B2F ; + .dw 0x3B30 ; + .dw 0x3B31 ; + .dw 0x3B32 ; + .dw 0x3B33 ; + .dw 0x3B34 ; + .dw 0x3B35 ; + .dw 0x3B36 ; + .dw 0x3B37 ; + .dw 0x3B38 ; + .dw 0x3B39 ; + .dw 0x3B3A ; + .dw 0x3B3B ; + .dw 0x3B3C ; + .dw 0x3B3D ; + .dw 0x3B3E ; + .dw 0x3B3F ; + .dw 0x3B40 ; + .dw 0x3B41 ; + .dw 0x3B42 ; + .dw 0x3B43 ; + .dw 0x3B44 ; + .dw 0x3B45 ; + .dw 0x3B46 ; + .dw 0x3B47 ; + .dw 0x3B48 ; + .dw 0x3B49 ; + .dw 0x3B4A ; + .dw 0x3B4B ; + .dw 0x3B4C ; + .dw 0x3B4D ; + .dw 0x3B4E ; + .dw 0x3B4F ; + .dw 0x3B50 ; + .dw 0x3B51 ; + .dw 0x3B52 ; + .dw 0x3B53 ; + .dw 0x3B54 ; + .dw 0x3B55 ; + .dw 0x3B56 ; + .dw 0x3B57 ; + .dw 0x3B58 ; + .dw 0x3B59 ; + .dw 0x3B5A ; + .dw 0x3B5B ; + .dw 0x3B5C ; + .dw 0x3B5D ; + .dw 0x3B5E ; + .dw 0x3B5F ; + .dw 0x3B60 ; + .dw 0x3B61 ; + .dw 0x3B62 ; + .dw 0x3B63 ; + .dw 0x3B64 ; + .dw 0x3B65 ; + .dw 0x3B66 ; + .dw 0x3B67 ; + .dw 0x3B68 ; + .dw 0x3B69 ; + .dw 0x3B6A ; + .dw 0x3B6B ; + .dw 0x3B6C ; + .dw 0x3B6D ; + .dw 0x3B6E ; + .dw 0x3B6F ; + .dw 0x3B70 ; + .dw 0x3B71 ; + .dw 0x3B72 ; + .dw 0x3B73 ; + .dw 0x3B74 ; + .dw 0x3B75 ; + .dw 0x3B76 ; + .dw 0x3B77 ; + .dw 0x3B78 ; + .dw 0x3B79 ; + .dw 0x3B7A ; + .dw 0x3B7B ; + .dw 0x3B7C ; + .dw 0x3B7D ; + .dw 0x3B7E ; + .dw 0x3B7F ; + .dw 0x3B80 ; + .dw 0x3B81 ; + .dw 0x3B82 ; + .dw 0x3B83 ; + .dw 0x3B84 ; + .dw 0x3B85 ; + .dw 0x3B86 ; + .dw 0x3B87 ; + .dw 0x3B88 ; + .dw 0x3B89 ; + .dw 0x3B8A ; + .dw 0x3B8B ; + .dw 0x3B8C ; + .dw 0x3B8D ; + .dw 0x3B8E ; + .dw 0x3B8F ; + .dw 0x3B90 ; + .dw 0x3B91 ; + .dw 0x3B92 ; + .dw 0x3B93 ; + .dw 0x3B94 ; + .dw 0x3B95 ; + .dw 0x3B96 ; + .dw 0x3B97 ; + .dw 0x3B98 ; + .dw 0x3B99 ; + .dw 0x3B9A ; + .dw 0x3B9B ; + .dw 0x3B9C ; + .dw 0x3B9D ; + .dw 0x3B9E ; + .dw 0x3B9F ; + .dw 0x3BA0 ; + .dw 0x3BA1 ; + .dw 0x3BA2 ; + .dw 0x3BA3 ; + .dw 0x3BA4 ; + .dw 0x3BA5 ; + .dw 0x3BA6 ; + .dw 0x3BA7 ; + .dw 0x3BA8 ; + .dw 0x3BA9 ; + .dw 0x3BAA ; + .dw 0x3BAB ; + .dw 0x3BAC ; + .dw 0x3BAD ; + .dw 0x3BAE ; + .dw 0x3BAF ; + .dw 0x3BB0 ; + .dw 0x3BB1 ; + .dw 0x3BB2 ; + .dw 0x3BB3 ; + .dw 0x3BB4 ; + .dw 0x3BB5 ; + .dw 0x3BB6 ; + .dw 0x3BB7 ; + .dw 0x3BB8 ; + .dw 0x3BB9 ; + .dw 0x3BBA ; + .dw 0x3BBB ; + .dw 0x3BBC ; + .dw 0x3BBD ; + .dw 0x3BBE ; + .dw 0x3BBF ; + .dw 0x3BC0 ; + .dw 0x3BC1 ; + .dw 0x3BC2 ; + .dw 0x3BC3 ; + .dw 0x3BC4 ; + .dw 0x3BC5 ; + .dw 0x3BC6 ; + .dw 0x3BC7 ; + .dw 0x3BC8 ; + .dw 0x3BC9 ; + .dw 0x3BCA ; + .dw 0x3BCB ; + .dw 0x3BCC ; + .dw 0x3BCD ; + .dw 0x3BCE ; + .dw 0x3BCF ; + .dw 0x3BD0 ; + .dw 0x3BD1 ; + .dw 0x3BD2 ; + .dw 0x3BD3 ; + .dw 0x3BD4 ; + .dw 0x3BD5 ; + .dw 0x3BD6 ; + .dw 0x3BD7 ; + .dw 0x3BD8 ; + .dw 0x3BD9 ; + .dw 0x3BDA ; + .dw 0x3BDB ; + .dw 0x3BDC ; + .dw 0x3BDD ; + .dw 0x3BDE ; + .dw 0x3BDF ; + .dw 0x3BE0 ; + .dw 0x3BE1 ; + .dw 0x3BE2 ; + .dw 0x3BE3 ; + .dw 0x3BE4 ; + .dw 0x3BE5 ; + .dw 0x3BE6 ; + .dw 0x3BE7 ; + .dw 0x3BE8 ; + .dw 0x3BE9 ; + .dw 0x3BEA ; + .dw 0x3BEB ; + .dw 0x3BEC ; + .dw 0x3BED ; + .dw 0x3BEE ; + .dw 0x3BEF ; + .dw 0x3BF0 ; + .dw 0x3BF1 ; + .dw 0x3BF2 ; + .dw 0x3BF3 ; + .dw 0x3BF4 ; + .dw 0x3BF5 ; + .dw 0x3BF6 ; + .dw 0x3BF7 ; + .dw 0x3BF8 ; + .dw 0x3BF9 ; + .dw 0x3BFA ; + .dw 0x3BFB ; + .dw 0x3BFC ; + .dw 0x3BFD ; + .dw 0x3BFE ; + .dw 0x3BFF ; + .dw 0x3140 ; + .dw 0x3141 ; + .dw 0x3142 ; + .dw 0x3143 ; + .dw 0x3144 ; + .dw 0x3145 ; + .dw 0x3146 ; + .dw 0x3147 ; + .dw 0x3148 ; + .dw 0x3149 ; + .dw 0x314A ; + .dw 0x314B ; + .dw 0x314C ; + .dw 0x314D ; + .dw 0x314E ; + .dw 0x314F ; + .dw 0x3150 ; + .dw 0x3151 ; + .dw 0x3152 ; + .dw 0x3153 ; + .dw 0x3154 ; + .dw 0x3155 ; + .dw 0x3156 ; + .dw 0x3157 ; + .dw 0x3158 ; + .dw 0x3159 ; + .dw 0x315A ; + .dw 0x315B ; + .dw 0x315C ; + .dw 0x315D ; + .dw 0x315E ; + .dw 0x315F ; + .dw 0x3160 ; + .dw 0x3161 ; + .dw 0x3162 ; + .dw 0x3163 ; + .dw 0x3164 ; + .dw 0x3165 ; + .dw 0x3166 ; + .dw 0x3167 ; + .dw 0x3168 ; + .dw 0x3169 ; + .dw 0x316A ; + .dw 0x316B ; + .dw 0x316C ; + .dw 0x316D ; + .dw 0x316E ; + .dw 0x316F ; + .dw 0x3170 ; + .dw 0x3171 ; + .dw 0x3172 ; + .dw 0x3173 ; + .dw 0x3174 ; + .dw 0x3175 ; + .dw 0x3176 ; + .dw 0x3177 ; + .dw 0x3178 ; + .dw 0x3179 ; + .dw 0x317A ; + .dw 0x317B ; + .dw 0x317C ; + .dw 0x317D ; + .dw 0x317E ; + .dw 0x317F ; + .dw 0x3340 ; + .dw 0x3341 ; + .dw 0x3342 ; + .dw 0x3343 ; + .dw 0x3344 ; + .dw 0x3345 ; + .dw 0x3346 ; + .dw 0x3347 ; + .dw 0x3348 ; + .dw 0x3349 ; + .dw 0x334A ; + .dw 0x334B ; + .dw 0x334C ; + .dw 0x334D ; + .dw 0x334E ; + .dw 0x334F ; + .dw 0x3350 ; + .dw 0x3351 ; + .dw 0x3352 ; + .dw 0x3353 ; + .dw 0x3354 ; + .dw 0x3355 ; + .dw 0x3356 ; + .dw 0x3357 ; + .dw 0x3358 ; + .dw 0x3359 ; + .dw 0x335A ; + .dw 0x335B ; + .dw 0x335C ; + .dw 0x335D ; + .dw 0x335E ; + .dw 0x335F ; + .dw 0x3360 ; + .dw 0x3361 ; + .dw 0x3362 ; + .dw 0x3363 ; + .dw 0x3364 ; + .dw 0x3365 ; + .dw 0x3366 ; + .dw 0x3367 ; + .dw 0x3368 ; + .dw 0x3369 ; + .dw 0x336A ; + .dw 0x336B ; + .dw 0x336C ; + .dw 0x336D ; + .dw 0x336E ; + .dw 0x336F ; + .dw 0x3370 ; + .dw 0x3371 ; + .dw 0x3372 ; + .dw 0x3373 ; + .dw 0x3374 ; + .dw 0x3375 ; + .dw 0x3376 ; + .dw 0x3377 ; + .dw 0x3378 ; + .dw 0x3379 ; + .dw 0x337A ; + .dw 0x337B ; + .dw 0x337C ; + .dw 0x337D ; + .dw 0x337E ; + .dw 0x337F ; + .dw 0x3540 ; + .dw 0x3541 ; + .dw 0x3542 ; + .dw 0x3543 ; + .dw 0x3544 ; + .dw 0x3545 ; + .dw 0x3546 ; + .dw 0x3547 ; + .dw 0x3548 ; + .dw 0x3549 ; + .dw 0x354A ; + .dw 0x354B ; + .dw 0x354C ; + .dw 0x354D ; + .dw 0x354E ; + .dw 0x354F ; + .dw 0x3550 ; + .dw 0x3551 ; + .dw 0x3552 ; + .dw 0x3553 ; + .dw 0x3554 ; + .dw 0x3555 ; + .dw 0x3556 ; + .dw 0x3557 ; + .dw 0x3558 ; + .dw 0x3559 ; + .dw 0x355A ; + .dw 0x355B ; + .dw 0x355C ; + .dw 0x355D ; + .dw 0x355E ; + .dw 0x355F ; + .dw 0x3560 ; + .dw 0x3561 ; + .dw 0x3562 ; + .dw 0x3563 ; + .dw 0x3564 ; + .dw 0x3565 ; + .dw 0x3566 ; + .dw 0x3567 ; + .dw 0x3568 ; + .dw 0x3569 ; + .dw 0x356A ; + .dw 0x356B ; + .dw 0x356C ; + .dw 0x356D ; + .dw 0x356E ; + .dw 0x356F ; + .dw 0x3570 ; + .dw 0x3571 ; + .dw 0x3572 ; + .dw 0x3573 ; + .dw 0x3574 ; + .dw 0x3575 ; + .dw 0x3576 ; + .dw 0x3577 ; + .dw 0x3578 ; + .dw 0x3579 ; + .dw 0x357A ; + .dw 0x357B ; + .dw 0x357C ; + .dw 0x357D ; + .dw 0x357E ; + .dw 0x357F ; + .dw 0x3740 ; + .dw 0x3741 ; + .dw 0x3742 ; + .dw 0x3743 ; + .dw 0x3744 ; + .dw 0x3745 ; + .dw 0x3746 ; + .dw 0x3747 ; + .dw 0x3748 ; + .dw 0x3749 ; + .dw 0x374A ; + .dw 0x374B ; + .dw 0x374C ; + .dw 0x374D ; + .dw 0x374E ; + .dw 0x374F ; + .dw 0x3750 ; + .dw 0x3751 ; + .dw 0x3752 ; + .dw 0x3753 ; + .dw 0x3754 ; + .dw 0x3755 ; + .dw 0x3756 ; + .dw 0x3757 ; + .dw 0x3758 ; + .dw 0x3759 ; + .dw 0x375A ; + .dw 0x375B ; + .dw 0x375C ; + .dw 0x375D ; + .dw 0x375E ; + .dw 0x375F ; + .dw 0x3760 ; + .dw 0x3761 ; + .dw 0x3762 ; + .dw 0x3763 ; + .dw 0x3764 ; + .dw 0x3765 ; + .dw 0x3766 ; + .dw 0x3767 ; + .dw 0x3768 ; + .dw 0x3769 ; + .dw 0x376A ; + .dw 0x376B ; + .dw 0x376C ; + .dw 0x376D ; + .dw 0x376E ; + .dw 0x376F ; + .dw 0x3770 ; + .dw 0x3771 ; + .dw 0x3772 ; + .dw 0x3773 ; + .dw 0x3774 ; + .dw 0x3775 ; + .dw 0x3776 ; + .dw 0x3777 ; + .dw 0x3778 ; + .dw 0x3779 ; + .dw 0x377A ; + .dw 0x377B ; + .dw 0x377C ; + .dw 0x377D ; + .dw 0x377E ; + .dw 0x377F ; + .dw 0x3940 ; + .dw 0x3941 ; + .dw 0x3942 ; + .dw 0x3943 ; + .dw 0x3944 ; + .dw 0x3945 ; + .dw 0x3946 ; + .dw 0x3947 ; + .dw 0x3948 ; + .dw 0x3949 ; + .dw 0x394A ; + .dw 0x394B ; + .dw 0x394C ; + .dw 0x394D ; + .dw 0x394E ; + .dw 0x394F ; + .dw 0x3950 ; + .dw 0x3951 ; + .dw 0x3952 ; + .dw 0x3953 ; + .dw 0x3954 ; + .dw 0x3955 ; + .dw 0x3956 ; + .dw 0x3957 ; + .dw 0x3958 ; + .dw 0x3959 ; + .dw 0x395A ; + .dw 0x395B ; + .dw 0x395C ; + .dw 0x395D ; + .dw 0x395E ; + .dw 0x395F ; + .dw 0x3960 ; + .dw 0x3961 ; + .dw 0x3962 ; + .dw 0x3963 ; + .dw 0x3964 ; + .dw 0x3965 ; + .dw 0x3966 ; + .dw 0x3967 ; + .dw 0x3968 ; + .dw 0x3969 ; + .dw 0x396A ; + .dw 0x396B ; + .dw 0x396C ; + .dw 0x396D ; + .dw 0x396E ; + .dw 0x396F ; + .dw 0x3970 ; + .dw 0x3971 ; + .dw 0x3972 ; + .dw 0x3973 ; + .dw 0x3974 ; + .dw 0x3975 ; + .dw 0x3976 ; + .dw 0x3977 ; + .dw 0x3978 ; + .dw 0x3979 ; + .dw 0x397A ; + .dw 0x397B ; + .dw 0x397C ; + .dw 0x397D ; + .dw 0x397E ; + .dw 0x397F ; + .dw 0x3D40 ; + .dw 0x3D41 ; + .dw 0x3D42 ; + .dw 0x3D43 ; + .dw 0x3D44 ; + .dw 0x3D45 ; + .dw 0x3D46 ; + .dw 0x3D47 ; + .dw 0x3D48 ; + .dw 0x3D49 ; + .dw 0x3D4A ; + .dw 0x3D4B ; + .dw 0x3D4C ; + .dw 0x3D4D ; + .dw 0x3D4E ; + .dw 0x3D4F ; + .dw 0x3D50 ; + .dw 0x3D51 ; + .dw 0x3D52 ; + .dw 0x3D53 ; + .dw 0x3D54 ; + .dw 0x3D55 ; + .dw 0x3D56 ; + .dw 0x3D57 ; + .dw 0x3D58 ; + .dw 0x3D59 ; + .dw 0x3D5A ; + .dw 0x3D5B ; + .dw 0x3D5C ; + .dw 0x3D5D ; + .dw 0x3D5E ; + .dw 0x3D5F ; + .dw 0x3D60 ; + .dw 0x3D61 ; + .dw 0x3D62 ; + .dw 0x3D63 ; + .dw 0x3D64 ; + .dw 0x3D65 ; + .dw 0x3D66 ; + .dw 0x3D67 ; + .dw 0x3D68 ; + .dw 0x3D69 ; + .dw 0x3D6A ; + .dw 0x3D6B ; + .dw 0x3D6C ; + .dw 0x3D6D ; + .dw 0x3D6E ; + .dw 0x3D6F ; + .dw 0x3D70 ; + .dw 0x3D71 ; + .dw 0x3D72 ; + .dw 0x3D73 ; + .dw 0x3D74 ; + .dw 0x3D75 ; + .dw 0x3D76 ; + .dw 0x3D77 ; + .dw 0x3D78 ; + .dw 0x3D79 ; + .dw 0x3D7A ; + .dw 0x3D7B ; + .dw 0x3D7C ; + .dw 0x3D7D ; + .dw 0x3D7E ; + .dw 0x3D7F ; + .dw 0x3F40 ; + .dw 0x3F41 ; + .dw 0x3F42 ; + .dw 0x3F43 ; + .dw 0x3F44 ; + .dw 0x3F45 ; + .dw 0x3F46 ; + .dw 0x3F47 ; + .dw 0x3F48 ; + .dw 0x3F49 ; + .dw 0x3F4A ; + .dw 0x3F4B ; + .dw 0x3F4C ; + .dw 0x3F4D ; + .dw 0x3F4E ; + .dw 0x3F4F ; + .dw 0x3F50 ; + .dw 0x3F51 ; + .dw 0x3F52 ; + .dw 0x3F53 ; + .dw 0x3F54 ; + .dw 0x3F55 ; + .dw 0x3F56 ; + .dw 0x3F57 ; + .dw 0x3F58 ; + .dw 0x3F59 ; + .dw 0x3F5A ; + .dw 0x3F5B ; + .dw 0x3F5C ; + .dw 0x3F5D ; + .dw 0x3F5E ; + .dw 0x3F5F ; + .dw 0x3F60 ; + .dw 0x3F61 ; + .dw 0x3F62 ; + .dw 0x3F63 ; + .dw 0x3F64 ; + .dw 0x3F65 ; + .dw 0x3F66 ; + .dw 0x3F67 ; + .dw 0x3F68 ; + .dw 0x3F69 ; + .dw 0x3F6A ; + .dw 0x3F6B ; + .dw 0x3F6C ; + .dw 0x3F6D ; + .dw 0x3F6E ; + .dw 0x3F6F ; + .dw 0x3F70 ; + .dw 0x3F71 ; + .dw 0x3F72 ; + .dw 0x3F73 ; + .dw 0x3F74 ; + .dw 0x3F75 ; + .dw 0x3F76 ; + .dw 0x3F77 ; + .dw 0x3F78 ; + .dw 0x3F79 ; + .dw 0x3F7A ; + .dw 0x3F7B ; + .dw 0x3F7C ; + .dw 0x3F7D ; + .dw 0x3F7E ; + .dw 0x3F7F ; + .dw 0x3104 ; + .dw 0x3105 ; + .dw 0x310C ; + .dw 0x310D ; + .dw 0x3114 ; + .dw 0x3115 ; + .dw 0x311C ; + .dw 0x311D ; + .dw 0x3124 ; + .dw 0x3125 ; + .dw 0x312C ; + .dw 0x312D ; + .dw 0x3134 ; + .dw 0x3135 ; + .dw 0x313C ; + .dw 0x313D ; + .dw 0x3304 ; + .dw 0x3305 ; + .dw 0x330C ; + .dw 0x330D ; + .dw 0x3314 ; + .dw 0x3315 ; + .dw 0x331C ; + .dw 0x331D ; + .dw 0x3324 ; + .dw 0x3325 ; + .dw 0x332C ; + .dw 0x332D ; + .dw 0x3334 ; + .dw 0x3335 ; + .dw 0x333C ; + .dw 0x333D ; + .dw 0x3504 ; + .dw 0x3505 ; + .dw 0x350C ; + .dw 0x350D ; + .dw 0x3514 ; + .dw 0x3515 ; + .dw 0x351C ; + .dw 0x351D ; + .dw 0x3524 ; + .dw 0x3525 ; + .dw 0x352C ; + .dw 0x352D ; + .dw 0x3534 ; + .dw 0x3535 ; + .dw 0x353C ; + .dw 0x353D ; + .dw 0x3704 ; + .dw 0x3705 ; + .dw 0x370C ; + .dw 0x370D ; + .dw 0x3714 ; + .dw 0x3715 ; + .dw 0x371C ; + .dw 0x371D ; + .dw 0x3724 ; + .dw 0x3725 ; + .dw 0x372C ; + .dw 0x372D ; + .dw 0x3734 ; + .dw 0x3735 ; + .dw 0x373C ; + .dw 0x373D ; + .dw 0x3904 ; + .dw 0x3905 ; + .dw 0x390C ; + .dw 0x390D ; + .dw 0x3914 ; + .dw 0x3915 ; + .dw 0x391C ; + .dw 0x391D ; + .dw 0x3924 ; + .dw 0x3925 ; + .dw 0x392C ; + .dw 0x392D ; + .dw 0x3934 ; + .dw 0x3935 ; + .dw 0x393C ; + .dw 0x393D ; + .dw 0x3D04 ; + .dw 0x3D05 ; + .dw 0x3D0C ; + .dw 0x3D0D ; + .dw 0x3D14 ; + .dw 0x3D15 ; + .dw 0x3D1C ; + .dw 0x3D1D ; + .dw 0x3D24 ; + .dw 0x3D25 ; + .dw 0x3D2C ; + .dw 0x3D2D ; + .dw 0x3D34 ; + .dw 0x3D35 ; + .dw 0x3D3C ; + .dw 0x3D3D ; + .dw 0x3F04 ; + .dw 0x3F05 ; + .dw 0x3F0C ; + .dw 0x3F0D ; + .dw 0x3F14 ; + .dw 0x3F15 ; + .dw 0x3F1C ; + .dw 0x3F1D ; + .dw 0x3F24 ; + .dw 0x3F25 ; + .dw 0x3F2C ; + .dw 0x3F2D ; + .dw 0x3F34 ; + .dw 0x3F35 ; + .dw 0x3F3C ; + .dw 0x3F3D ; + .dw 0x3820 ; + .dw 0x3821 ; + .dw 0x3822 ; + .dw 0x3823 ; + .dw 0x3824 ; + .dw 0x3825 ; + .dw 0x3826 ; + .dw 0x3827 ; + .dw 0x3828 ; + .dw 0x3829 ; + .dw 0x382A ; + .dw 0x382B ; + .dw 0x382C ; + .dw 0x382D ; + .dw 0x382E ; + .dw 0x382F ; + .dw 0x3860 ; + .dw 0x3861 ; + .dw 0x3862 ; + .dw 0x3863 ; + .dw 0x3864 ; + .dw 0x3865 ; + .dw 0x3866 ; + .dw 0x3867 ; + .dw 0x3868 ; + .dw 0x3869 ; + .dw 0x386A ; + .dw 0x386B ; + .dw 0x386C ; + .dw 0x386D ; + .dw 0x386E ; + .dw 0x386F ; + .dw 0x38A0 ; + .dw 0x38A1 ; + .dw 0x38A2 ; + .dw 0x38A3 ; + .dw 0x38A4 ; + .dw 0x38A5 ; + .dw 0x38A6 ; + .dw 0x38A7 ; + .dw 0x38A8 ; + .dw 0x38A9 ; + .dw 0x38AA ; + .dw 0x38AB ; + .dw 0x38AC ; + .dw 0x38AD ; + .dw 0x38AE ; + .dw 0x38AF ; + .dw 0x38E0 ; + .dw 0x38E1 ; + .dw 0x38E2 ; + .dw 0x38E3 ; + .dw 0x38E4 ; + .dw 0x38E5 ; + .dw 0x38E6 ; + .dw 0x38E7 ; + .dw 0x38E8 ; + .dw 0x38E9 ; + .dw 0x38EA ; + .dw 0x38EB ; + .dw 0x38EC ; + .dw 0x38ED ; + .dw 0x38EE ; + .dw 0x38EF ; + .dw 0x3920 ; + .dw 0x3921 ; + .dw 0x3922 ; + .dw 0x3923 ; + .dw 0x3924 ; + .dw 0x3925 ; + .dw 0x3926 ; + .dw 0x3927 ; + .dw 0x3928 ; + .dw 0x3929 ; + .dw 0x392A ; + .dw 0x392B ; + .dw 0x392C ; + .dw 0x392D ; + .dw 0x392E ; + .dw 0x392F ; + .dw 0x39A0 ; + .dw 0x39A1 ; + .dw 0x39A2 ; + .dw 0x39A3 ; + .dw 0x39A4 ; + .dw 0x39A5 ; + .dw 0x39A6 ; + .dw 0x39A7 ; + .dw 0x39A8 ; + .dw 0x39A9 ; + .dw 0x39AA ; + .dw 0x39AB ; + .dw 0x39AC ; + .dw 0x39AD ; + .dw 0x39AE ; + .dw 0x39AF ; + .dw 0x39E0 ; + .dw 0x39E1 ; + .dw 0x39E2 ; + .dw 0x39E3 ; + .dw 0x39E4 ; + .dw 0x39E5 ; + .dw 0x39E6 ; + .dw 0x39E7 ; + .dw 0x39E8 ; + .dw 0x39E9 ; + .dw 0x39EA ; + .dw 0x39EB ; + .dw 0x39EC ; + .dw 0x39ED ; + .dw 0x39EE ; + .dw 0x39EF ; +#if 0 + // EMUDAT = Dreg; is valid + .dw 0x3E38 ; + .dw 0x3E39 ; + .dw 0x3E3A ; + .dw 0x3E3B ; + .dw 0x3E3C ; + .dw 0x3E3D ; + .dw 0x3E3E ; + .dw 0x3E3F ; + // EMUDAT = Preg; is valid + .dw 0x3E78 ; + .dw 0x3E79 ; + .dw 0x3E7A ; + .dw 0x3E7B ; + .dw 0x3E7C ; + .dw 0x3E7D ; + .dw 0x3E7E ; + .dw 0x3E7F ; + // EMUDAT = Ireg; is valid + .dw 0x3EB8 ; + .dw 0x3EB9 ; + .dw 0x3EBA ; + .dw 0x3EBB ; + // EMUDAT = Mreg; is valid + .dw 0x3EBC ; + .dw 0x3EBD ; + .dw 0x3EBE ; + .dw 0x3EBF ; + // EMUDAT = Breg; is valid + .dw 0x3EF8 ; + .dw 0x3EF9 ; + .dw 0x3EFA ; + .dw 0x3EFB ; + // EMUDAT = Lreg; is valid + .dw 0x3EFC ; + .dw 0x3EFD ; + .dw 0x3EFE ; + .dw 0x3EFF ; + // EMUDAT = Areg; is valid + .dw 0x3F38 ; + .dw 0x3F39 ; + .dw 0x3F3A ; + .dw 0x3F3B ; +#endif + .dw 0x3F3C ; + .dw 0x3F3D ; +#if 0 + // EMUDAT = ASTAT; is valid + .dw 0x3F3E ; + // EMUDAT = RETS; is valid + .dw 0x3F3F ; + // EMUDAT = loopregs; is valid + .dw 0x3FB8 ; + .dw 0x3FB9 ; + .dw 0x3FBA ; + .dw 0x3FBB ; + .dw 0x3FBC ; + .dw 0x3FBD ; + // EMUDAT = cycles; is valid + .dw 0x3FBE ; + .dw 0x3FBF ; + // EMUDAT = USP; is valid + .dw 0x3FF8 ; + // EMUDAT = SEQSTAT; is valid + .dw 0x3FF9 ; + // EMUDAT = SYSCFG; is valid + .dw 0x3FFA ; + // EMDUAT = RET[IXNE]; is valid + .dw 0x3FFB ; + .dw 0x3FFC ; + .dw 0x3FFD ; + .dw 0x3FFE ; + // EMUDAT = EMUDAT; is valid + .dw 0x3FFF ; + // Dreg = EMUDAT; is valid + .dw 0x31C7 ; + .dw 0x31CF ; + .dw 0x31D7 ; + .dw 0x31DF ; +#if 0 + // R4 = EMUDAT; breaks the test + .dw 0x31E7 ; + // R5 = EMUDAT; breaks the test + .dw 0x31EF ; +#endif + .dw 0x31F7 ; + .dw 0x31FF ; + // Preg = EMUDAT; is valid + .dw 0x33C7 ; + .dw 0x33CF ; + .dw 0x33D7 ; + .dw 0x33DF ; + .dw 0x33E7 ; + .dw 0x33EF ; + .dw 0x33F7 ; + .dw 0x33FF ; + // Ireg = EMUDAT; is valid + .dw 0x35C7 ; + .dw 0x35CF ; + .dw 0x35D7 ; + .dw 0x35DF ; + // Mreg = EMUDAT; is valid + .dw 0x35E7 ; + .dw 0x35EF ; + .dw 0x35F7 ; + .dw 0x35FF ; + // EMUDAT = Breg; is valid + .dw 0x37C7 ; + .dw 0x37CF ; + .dw 0x37D7 ; + .dw 0x37DF ; + // EMUDAT = Lreg; is valid + .dw 0x37E7 ; + .dw 0x37EF ; + .dw 0x37F7 ; + .dw 0x37FF ; +#endif + .dw 0x39C7 ; + .dw 0x39CF ; + .dw 0x39D7 ; + .dw 0x39DF ; + .dw 0x39E7 ; + .dw 0x39EF ; +#if 0 + // ASTAT = EMUDAT; is valid + .dw 0x39F7 ; + // RETS = EMUDAT; is valid + .dw 0x39FF ; + // loopregs = EMUDAT; is valid + .dw 0x3DC7 ; + .dw 0x3DCF ; + .dw 0x3DD7 ; + .dw 0x3DDF ; + .dw 0x3DE7 ; + .dw 0x3DEF ; + // cycles = EMUDAT; is valid + .dw 0x3DF7 ; + .dw 0x3DFF ; + // USP = EMUDAT; is valid + .dw 0x3FC7 ; + // SEQSTAT = EMUDAT; is valid + .dw 0x3FCF ; + // SYSCFG = EMUDAT; is valid + .dw 0x3FD7 ; + // RET[IXNE] = EMUDAT; is valid + .dw 0x3FDF ; + .dw 0x3FE7 ; + .dw 0x3FEF ; + .dw 0x3FF7 ; + // EMUDAT = EMUDAT; is valid + .dw 0x3FFF ; +#endif + .dw 0x3D80 ; + .dw 0x3D81 ; + .dw 0x3D82 ; + .dw 0x3D83 ; + .dw 0x3D84 ; + .dw 0x3D85 ; + .dw 0x3D86 ; + .dw 0x3D87 ; + .dw 0x3D88 ; + .dw 0x3D89 ; + .dw 0x3D8A ; + .dw 0x3D8B ; + .dw 0x3D8C ; + .dw 0x3D8D ; + .dw 0x3D8E ; + .dw 0x3D8F ; + .dw 0x3D90 ; + .dw 0x3D91 ; + .dw 0x3D92 ; + .dw 0x3D93 ; + .dw 0x3D94 ; + .dw 0x3D95 ; + .dw 0x3D96 ; + .dw 0x3D97 ; + .dw 0x3D98 ; + .dw 0x3D99 ; + .dw 0x3D9A ; + .dw 0x3D9B ; + .dw 0x3D9C ; + .dw 0x3D9D ; + .dw 0x3D9E ; + .dw 0x3D9F ; + .dw 0x3DA0 ; + .dw 0x3DA1 ; + .dw 0x3DA2 ; + .dw 0x3DA3 ; + .dw 0x3DA4 ; + .dw 0x3DA5 ; + .dw 0x3DA6 ; + .dw 0x3DA7 ; + .dw 0x3DA8 ; + .dw 0x3DA9 ; + .dw 0x3DAA ; + .dw 0x3DAB ; + .dw 0x3DAC ; + .dw 0x3DAD ; + .dw 0x3DAE ; + .dw 0x3DAF ; + .dw 0x3DB0 ; + .dw 0x3DB1 ; + .dw 0x3DB2 ; + .dw 0x3DB3 ; + .dw 0x3DB4 ; + .dw 0x3DB5 ; + .dw 0x3DB6 ; + .dw 0x3DB7 ; + .dw 0x3DB8 ; + .dw 0x3DB9 ; + .dw 0x3DBA ; + .dw 0x3DBB ; + .dw 0x3DBC ; + .dw 0x3DBD ; + .dw 0x3DBE ; + .dw 0x3DBF ; + .dw 0x3DC1 ; + .dw 0x3DC2 ; + .dw 0x3DC3 ; + .dw 0x3DC4 ; + .dw 0x3DC5 ; + .dw 0x3DC6 ; +#if 0 + // loopregs = EMUDAT; is valid + .dw 0x3DC7 ; +#endif + .dw 0x3DC9 ; + .dw 0x3DCA ; + .dw 0x3DCB ; + .dw 0x3DCC ; + .dw 0x3DCD ; + .dw 0x3DCE ; +#if 0 + // loopregs = EMUDAT; is valid + .dw 0x3DCF ; +#endif + .dw 0x3DD1 ; + .dw 0x3DD2 ; + .dw 0x3DD3 ; + .dw 0x3DD4 ; + .dw 0x3DD5 ; + .dw 0x3DD6 ; +#if 0 + // loopregs = EMUDAT; is valid + .dw 0x3DD7 ; +#endif + .dw 0x3DD9 ; + .dw 0x3DDA ; + .dw 0x3DDB ; + .dw 0x3DDC ; + .dw 0x3DDD ; + .dw 0x3DDE ; +#if 0 + // loopregs = EMUDAT; is valid + .dw 0x3DDF ; +#endif + .dw 0x3DE1 ; + .dw 0x3DE2 ; + .dw 0x3DE3 ; + .dw 0x3DE4 ; + .dw 0x3DE5 ; + .dw 0x3DE6 ; +#if 0 + // loopregs = EMUDAT; is valid + .dw 0x3DE7 ; +#endif + .dw 0x3DE9 ; + .dw 0x3DEA ; + .dw 0x3DEB ; + .dw 0x3DEC ; + .dw 0x3DED ; + .dw 0x3DEE ; +#if 0 + // loopregs = EMUDAT; is valid + .dw 0x3DEF ; +#endif + .dw 0x3DF1 ; + .dw 0x3DF2 ; + .dw 0x3DF3 ; + .dw 0x3DF4 ; + .dw 0x3DF5 ; + .dw 0x3DF6 ; +#if 0 + // cycles = EMUDAT; is valid + .dw 0x3DF7 ; +#endif + .dw 0x3DF9 ; + .dw 0x3DFA ; + .dw 0x3DFB ; + .dw 0x3DFC ; + .dw 0x3DFD ; + .dw 0x3DFE ; +#if 0 + // cycles = EMUDAT; is valid + .dw 0x3DFF ; +#endif + .dw 0x3F88 ; + .dw 0x3F89 ; + .dw 0x3F8A ; + .dw 0x3F8B ; + .dw 0x3F8C ; + .dw 0x3F8D ; + .dw 0x3F8E ; + .dw 0x3F8F ; + .dw 0x3F90 ; + .dw 0x3F91 ; + .dw 0x3F92 ; + .dw 0x3F93 ; + .dw 0x3F94 ; + .dw 0x3F95 ; + .dw 0x3F96 ; + .dw 0x3F97 ; + .dw 0x3F98 ; + .dw 0x3F99 ; + .dw 0x3F9A ; + .dw 0x3F9B ; + .dw 0x3F9C ; + .dw 0x3F9D ; + .dw 0x3F9E ; + .dw 0x3F9F ; + .dw 0x3FA0 ; + .dw 0x3FA1 ; + .dw 0x3FA2 ; + .dw 0x3FA3 ; + .dw 0x3FA4 ; + .dw 0x3FA5 ; + .dw 0x3FA6 ; + .dw 0x3FA7 ; + .dw 0x3FA8 ; + .dw 0x3FA9 ; + .dw 0x3FAA ; + .dw 0x3FAB ; + .dw 0x3FAC ; + .dw 0x3FAD ; + .dw 0x3FAE ; + .dw 0x3FAF ; + .dw 0x3FB0 ; + .dw 0x3FB1 ; + .dw 0x3FB2 ; + .dw 0x3FB3 ; + .dw 0x3FB4 ; + .dw 0x3FB5 ; + .dw 0x3FB6 ; + .dw 0x3FB7 ; +#if 0 + // EMUDAT = loopregs; is valid + .dw 0x3FB8 ; + .dw 0x3FB9 ; + .dw 0x3FBA ; + .dw 0x3FBB ; + .dw 0x3FBC ; + .dw 0x3FBD ; + // EMUDAT = cycles; is valid + .dw 0x3FBE ; + .dw 0x3FBF ; +#endif + .dw 0x3FC9 ; + .dw 0x3FCA ; + .dw 0x3FCB ; + .dw 0x3FCC ; + .dw 0x3FCD ; + .dw 0x3FCE ; +#if 0 + // SEQSTAT = EMUDAT; is valid + .dw 0x3FCF ; +#endif + .dw 0x3FD1 ; + .dw 0x3FD2 ; + .dw 0x3FD3 ; + .dw 0x3FD4 ; + .dw 0x3FD5 ; + .dw 0x3FD6 ; +#if 0 + // SYSCFG = EMUDAT; is valid + .dw 0x3FD7 ; +#endif + .dw 0x3FD9 ; + .dw 0x3FDA ; + .dw 0x3FDB ; + .dw 0x3FDC ; + .dw 0x3FDD ; + .dw 0x3FDE ; +#if 0 + // RET[IXNE] = EMUDAT; is valid + .dw 0x3FDF ; +#endif + .dw 0x3FE1 ; + .dw 0x3FE2 ; + .dw 0x3FE3 ; + .dw 0x3FE4 ; + .dw 0x3FE5 ; + .dw 0x3FE6 ; +#if 0 + // RET[IXNE] = EMUDAT; is valid + .dw 0x3FE7 ; +#endif + .dw 0x3FE9 ; + .dw 0x3FEA ; + .dw 0x3FEB ; + .dw 0x3FEC ; + .dw 0x3FED ; + .dw 0x3FEE ; +#if 0 + // RET[IXNE] = EMUDAT; is valid + .dw 0x3FEF ; +#endif + .dw 0x3FF1 ; + .dw 0x3FF2 ; + .dw 0x3FF3 ; + .dw 0x3FF4 ; + .dw 0x3FF5 ; + .dw 0x3FF6 ; +#if 0 + // RET[IXNE] = EMUDAT; is valid + .dw 0x3FF7 ; + // EMUDAT = SEQSTAT; is valid + .dw 0x3FF9 ; + // EMUDAT = SYSCFG; is valid + .dw 0x3FFA ; + // EMDUAT = RET[IXNE]; is valid + .dw 0x3FFB ; + .dw 0x3FFC ; + .dw 0x3FFD ; + .dw 0x3FFE ; + // EMUDAT = EMUDAT; is valid + .dw 0x3FFF ; +#endif + .dw 0x39B0 ; + .dw 0x39B1 ; + .dw 0x39B2 ; + .dw 0x39B3 ; + .dw 0x39B4 ; + .dw 0x39B5 ; + .dw 0x39B6 ; + .dw 0x39B7 ; + .dw 0x39B8 ; + .dw 0x39B9 ; + .dw 0x39BA ; + .dw 0x39BB ; + .dw 0x39BC ; + .dw 0x39BD ; + .dw 0x39BE ; + .dw 0x39BF ; + .dw 0x39F1 ; + .dw 0x39F2 ; + .dw 0x39F3 ; + .dw 0x39F4 ; + .dw 0x39F5 ; + .dw 0x39F6 ; +#if 0 + // ASTAT = EMUDAT; is valid + .dw 0x39F7 ; +#endif + .dw 0x39F9 ; + .dw 0x39FA ; + .dw 0x39FB ; + .dw 0x39FC ; + .dw 0x39FD ; + .dw 0x39FE ; +#if 0 + // RETS = EMUDAT; is valid + .dw 0x39FF ; +#endif + .dw 0x3D06 ; + .dw 0x3D07 ; + .dw 0x3D0E ; + .dw 0x3D0F ; + .dw 0x3D16 ; + .dw 0x3D17 ; + .dw 0x3D1E ; + .dw 0x3D1F ; + .dw 0x3D26 ; + .dw 0x3D27 ; + .dw 0x3D2E ; + .dw 0x3D2F ; + .dw 0x3D36 ; + .dw 0x3D37 ; + .dw 0x3D3E ; + .dw 0x3D3F ; + .dw 0x3F0E ; + .dw 0x3F0F ; + .dw 0x3F16 ; + .dw 0x3F17 ; + .dw 0x3F1E ; + .dw 0x3F1F ; + .dw 0x3F26 ; + .dw 0x3F27 ; + .dw 0x3F2E ; + .dw 0x3F2F ; + .dw 0x3F36 ; + .dw 0x3F37 ; +#if 0 + // EMUDAT = ASTAT; is valid + .dw 0x3F3E ; + // EMUDAT = RETS; is valid + .dw 0x3F3F ; +#endif + .dw 0x3936 ; + .dw 0x3937 ; + .dw 0x393E ; + .dw 0x393F ; + .dw 0x3C80 ; + .dw 0x3C81 ; + .dw 0x3C82 ; + .dw 0x3C83 ; + .dw 0x3C84 ; + .dw 0x3C85 ; + .dw 0x3C86 ; + .dw 0x3C87 ; + .dw 0x3C88 ; + .dw 0x3C89 ; + .dw 0x3C8A ; + .dw 0x3C8B ; + .dw 0x3C8C ; + .dw 0x3C8D ; + .dw 0x3C8E ; + .dw 0x3C8F ; + .dw 0x3C90 ; + .dw 0x3C91 ; + .dw 0x3C92 ; + .dw 0x3C93 ; + .dw 0x3C94 ; + .dw 0x3C95 ; + .dw 0x3C96 ; + .dw 0x3C97 ; + .dw 0x3C98 ; + .dw 0x3C99 ; + .dw 0x3C9A ; + .dw 0x3C9B ; + .dw 0x3C9C ; + .dw 0x3C9D ; + .dw 0x3C9E ; + .dw 0x3C9F ; + .dw 0x3CA0 ; + .dw 0x3CA1 ; + .dw 0x3CA2 ; + .dw 0x3CA3 ; + .dw 0x3CA4 ; + .dw 0x3CA5 ; + .dw 0x3CA6 ; + .dw 0x3CA7 ; + .dw 0x3CA8 ; + .dw 0x3CA9 ; + .dw 0x3CAA ; + .dw 0x3CAB ; + .dw 0x3CAC ; + .dw 0x3CAD ; + .dw 0x3CAE ; + .dw 0x3CAF ; + .dw 0x3CB0 ; + .dw 0x3CB1 ; + .dw 0x3CB2 ; + .dw 0x3CB3 ; + .dw 0x3CB4 ; + .dw 0x3CB5 ; + .dw 0x3CB6 ; + .dw 0x3CB7 ; + .dw 0x3CB8 ; + .dw 0x3CB9 ; + .dw 0x3CBA ; + .dw 0x3CBB ; + .dw 0x3CBC ; + .dw 0x3CBD ; + .dw 0x3CBE ; + .dw 0x3CBF ; + .dw 0x3CC0 ; + .dw 0x3CC1 ; + .dw 0x3CC2 ; + .dw 0x3CC3 ; + .dw 0x3CC4 ; + .dw 0x3CC5 ; + .dw 0x3CC6 ; + .dw 0x3CC7 ; + .dw 0x3CC8 ; + .dw 0x3CC9 ; + .dw 0x3CCA ; + .dw 0x3CCB ; + .dw 0x3CCC ; + .dw 0x3CCD ; + .dw 0x3CCE ; + .dw 0x3CCF ; + .dw 0x3CD0 ; + .dw 0x3CD1 ; + .dw 0x3CD2 ; + .dw 0x3CD3 ; + .dw 0x3CD4 ; + .dw 0x3CD5 ; + .dw 0x3CD6 ; + .dw 0x3CD7 ; + .dw 0x3CD8 ; + .dw 0x3CD9 ; + .dw 0x3CDA ; + .dw 0x3CDB ; + .dw 0x3CDC ; + .dw 0x3CDD ; + .dw 0x3CDE ; + .dw 0x3CDF ; + .dw 0x3CE0 ; + .dw 0x3CE1 ; + .dw 0x3CE2 ; + .dw 0x3CE3 ; + .dw 0x3CE4 ; + .dw 0x3CE5 ; + .dw 0x3CE6 ; + .dw 0x3CE7 ; + .dw 0x3CE8 ; + .dw 0x3CE9 ; + .dw 0x3CEA ; + .dw 0x3CEB ; + .dw 0x3CEC ; + .dw 0x3CED ; + .dw 0x3CEE ; + .dw 0x3CEF ; + .dw 0x3CF0 ; + .dw 0x3CF1 ; + .dw 0x3CF2 ; + .dw 0x3CF3 ; + .dw 0x3CF4 ; + .dw 0x3CF5 ; + .dw 0x3CF6 ; + .dw 0x3CF7 ; + .dw 0x3CF8 ; + .dw 0x3CF9 ; + .dw 0x3CFA ; + .dw 0x3CFB ; + .dw 0x3CFC ; + .dw 0x3CFD ; + .dw 0x3CFE ; + .dw 0x3CFF ; + .dw 0x3E88 ; + .dw 0x3E89 ; + .dw 0x3E8A ; + .dw 0x3E8B ; + .dw 0x3E8C ; + .dw 0x3E8D ; + .dw 0x3E8E ; + .dw 0x3E8F ; + .dw 0x3E90 ; + .dw 0x3E91 ; + .dw 0x3E92 ; + .dw 0x3E93 ; + .dw 0x3E94 ; + .dw 0x3E95 ; + .dw 0x3E96 ; + .dw 0x3E97 ; + .dw 0x3E98 ; + .dw 0x3E99 ; + .dw 0x3E9A ; + .dw 0x3E9B ; + .dw 0x3E9C ; + .dw 0x3E9D ; + .dw 0x3E9E ; + .dw 0x3E9F ; + .dw 0x3EA0 ; + .dw 0x3EA1 ; + .dw 0x3EA2 ; + .dw 0x3EA3 ; + .dw 0x3EA4 ; + .dw 0x3EA5 ; + .dw 0x3EA6 ; + .dw 0x3EA7 ; + .dw 0x3EA8 ; + .dw 0x3EA9 ; + .dw 0x3EAA ; + .dw 0x3EAB ; + .dw 0x3EAC ; + .dw 0x3EAD ; + .dw 0x3EAE ; + .dw 0x3EAF ; + .dw 0x3EB0 ; + .dw 0x3EB1 ; + .dw 0x3EB2 ; + .dw 0x3EB3 ; + .dw 0x3EB4 ; + .dw 0x3EB5 ; + .dw 0x3EB6 ; + .dw 0x3EB7 ; +#if 0 + // EMUDAT = Ireg; is valid + .dw 0x3EB8 ; + .dw 0x3EB9 ; + .dw 0x3EBA ; + .dw 0x3EBB ; + // EMUDAT = Mreg; is valid + .dw 0x3EBC ; + .dw 0x3EBD ; + .dw 0x3EBE ; + .dw 0x3EBF ; +#endif + .dw 0x3EC8 ; + .dw 0x3EC9 ; + .dw 0x3ECA ; + .dw 0x3ECB ; + .dw 0x3ECC ; + .dw 0x3ECD ; + .dw 0x3ECE ; + .dw 0x3ECF ; + .dw 0x3ED0 ; + .dw 0x3ED1 ; + .dw 0x3ED2 ; + .dw 0x3ED3 ; + .dw 0x3ED4 ; + .dw 0x3ED5 ; + .dw 0x3ED6 ; + .dw 0x3ED7 ; + .dw 0x3ED8 ; + .dw 0x3ED9 ; + .dw 0x3EDA ; + .dw 0x3EDB ; + .dw 0x3EDC ; + .dw 0x3EDD ; + .dw 0x3EDE ; + .dw 0x3EDF ; + .dw 0x3EE0 ; + .dw 0x3EE1 ; + .dw 0x3EE2 ; + .dw 0x3EE3 ; + .dw 0x3EE4 ; + .dw 0x3EE5 ; + .dw 0x3EE6 ; + .dw 0x3EE7 ; + .dw 0x3EE8 ; + .dw 0x3EE9 ; + .dw 0x3EEA ; + .dw 0x3EEB ; + .dw 0x3EEC ; + .dw 0x3EED ; + .dw 0x3EEE ; + .dw 0x3EEF ; + .dw 0x3EF0 ; + .dw 0x3EF1 ; + .dw 0x3EF2 ; + .dw 0x3EF3 ; + .dw 0x3EF4 ; + .dw 0x3EF5 ; + .dw 0x3EF6 ; + .dw 0x3EF7 ; +#if 0 + // EMUDAT = Breg; is valid + .dw 0x3EF8 ; + .dw 0x3EF9 ; + .dw 0x3EFA ; + .dw 0x3EFB ; + // EMUDAT = Lreg; is valid + .dw 0x3EFC ; + .dw 0x3EFD ; + .dw 0x3EFE ; + .dw 0x3EFF ; +#endif + .dw 0x38B0 ; + .dw 0x38B1 ; + .dw 0x38B2 ; + .dw 0x38B3 ; + .dw 0x38B4 ; + .dw 0x38B5 ; + .dw 0x38B6 ; + .dw 0x38B7 ; + .dw 0x38B8 ; + .dw 0x38B9 ; + .dw 0x38BA ; + .dw 0x38BB ; + .dw 0x38BC ; + .dw 0x38BD ; + .dw 0x38BE ; + .dw 0x38BF ; + .dw 0x38F0 ; + .dw 0x38F1 ; + .dw 0x38F2 ; + .dw 0x38F3 ; + .dw 0x38F4 ; + .dw 0x38F5 ; + .dw 0x38F6 ; + .dw 0x38F7 ; + .dw 0x38F8 ; + .dw 0x38F9 ; + .dw 0x38FA ; + .dw 0x38FB ; + .dw 0x38FC ; + .dw 0x38FD ; + .dw 0x38FE ; + .dw 0x38FF ; +#if 0 + // Preg = sysreg; is valid + .dw 0x3380 ; + .dw 0x3381 ; + .dw 0x3382 ; + .dw 0x3383 ; + .dw 0x3384 ; + .dw 0x3385 ; + .dw 0x3386 ; + .dw 0x3387 ; + .dw 0x3388 ; + .dw 0x3389 ; + .dw 0x338A ; + .dw 0x338B ; + .dw 0x338C ; + .dw 0x338D ; + .dw 0x338E ; + .dw 0x338F ; + .dw 0x3390 ; + .dw 0x3391 ; + .dw 0x3392 ; + .dw 0x3393 ; + .dw 0x3394 ; + .dw 0x3395 ; + .dw 0x3396 ; + .dw 0x3397 ; + .dw 0x3398 ; + .dw 0x3399 ; + .dw 0x339A ; + .dw 0x339B ; + .dw 0x339C ; + .dw 0x339D ; + .dw 0x339E ; + .dw 0x339F ; + .dw 0x33A0 ; + .dw 0x33A1 ; + .dw 0x33A2 ; + .dw 0x33A3 ; + .dw 0x33A4 ; + .dw 0x33A5 ; + .dw 0x33A6 ; + .dw 0x33A7 ; + .dw 0x33A8 ; + .dw 0x33A9 ; + .dw 0x33AA ; + .dw 0x33AB ; + .dw 0x33AC ; + .dw 0x33AD ; + .dw 0x33AE ; + .dw 0x33AF ; + .dw 0x33B0 ; + .dw 0x33B1 ; + .dw 0x33B2 ; + .dw 0x33B3 ; + .dw 0x33B4 ; + .dw 0x33B5 ; + .dw 0x33B6 ; + .dw 0x33B7 ; + .dw 0x33B8 ; + .dw 0x33B9 ; + .dw 0x33BA ; + .dw 0x33BB ; + .dw 0x33BC ; + .dw 0x33BD ; + .dw 0x33BE ; + .dw 0x33BF ; + .dw 0x33C1 ; + .dw 0x33C2 ; + .dw 0x33C3 ; + .dw 0x33C4 ; + .dw 0x33C5 ; + .dw 0x33C6 ; + .dw 0x33C7 ; + .dw 0x33C9 ; + .dw 0x33CA ; + .dw 0x33CB ; + .dw 0x33CC ; + .dw 0x33CD ; + .dw 0x33CE ; + .dw 0x33CF ; + .dw 0x33D1 ; + .dw 0x33D2 ; + .dw 0x33D3 ; + .dw 0x33D4 ; + .dw 0x33D5 ; + .dw 0x33D6 ; + .dw 0x33D7 ; + .dw 0x33D9 ; + .dw 0x33DA ; + .dw 0x33DB ; + .dw 0x33DC ; + .dw 0x33DD ; + .dw 0x33DE ; + .dw 0x33DF ; + .dw 0x33E1 ; + .dw 0x33E2 ; + .dw 0x33E3 ; + .dw 0x33E4 ; + .dw 0x33E5 ; + .dw 0x33E6 ; + .dw 0x33E7 ; + .dw 0x33E9 ; + .dw 0x33EA ; + .dw 0x33EB ; + .dw 0x33EC ; + .dw 0x33ED ; + .dw 0x33EE ; + .dw 0x33EF ; + .dw 0x33F1 ; + .dw 0x33F2 ; + .dw 0x33F3 ; + .dw 0x33F4 ; + .dw 0x33F5 ; + .dw 0x33F6 ; + .dw 0x33F7 ; + .dw 0x33F9 ; + .dw 0x33FA ; + .dw 0x33FB ; + .dw 0x33FC ; + .dw 0x33FD ; + .dw 0x33FE ; + .dw 0x33FF ; + .dw 0x3306 ; + .dw 0x3307 ; + .dw 0x330E ; + .dw 0x330F ; + .dw 0x3316 ; + .dw 0x3317 ; + .dw 0x331E ; + .dw 0x331F ; + .dw 0x3326 ; + .dw 0x3327 ; + .dw 0x332E ; + .dw 0x332F ; + .dw 0x3336 ; + .dw 0x3337 ; + .dw 0x333E ; + .dw 0x333F ; +#endif + .dw 0x3580 ; + .dw 0x3581 ; + .dw 0x3582 ; + .dw 0x3583 ; + .dw 0x3584 ; + .dw 0x3585 ; + .dw 0x3586 ; + .dw 0x3587 ; + .dw 0x3588 ; + .dw 0x3589 ; + .dw 0x358A ; + .dw 0x358B ; + .dw 0x358C ; + .dw 0x358D ; + .dw 0x358E ; + .dw 0x358F ; + .dw 0x3590 ; + .dw 0x3591 ; + .dw 0x3592 ; + .dw 0x3593 ; + .dw 0x3594 ; + .dw 0x3595 ; + .dw 0x3596 ; + .dw 0x3597 ; + .dw 0x3598 ; + .dw 0x3599 ; + .dw 0x359A ; + .dw 0x359B ; + .dw 0x359C ; + .dw 0x359D ; + .dw 0x359E ; + .dw 0x359F ; + .dw 0x35A0 ; + .dw 0x35A1 ; + .dw 0x35A2 ; + .dw 0x35A3 ; + .dw 0x35A4 ; + .dw 0x35A5 ; + .dw 0x35A6 ; + .dw 0x35A7 ; + .dw 0x35A8 ; + .dw 0x35A9 ; + .dw 0x35AA ; + .dw 0x35AB ; + .dw 0x35AC ; + .dw 0x35AD ; + .dw 0x35AE ; + .dw 0x35AF ; + .dw 0x35B0 ; + .dw 0x35B1 ; + .dw 0x35B2 ; + .dw 0x35B3 ; + .dw 0x35B4 ; + .dw 0x35B5 ; + .dw 0x35B6 ; + .dw 0x35B7 ; + .dw 0x35B8 ; + .dw 0x35B9 ; + .dw 0x35BA ; + .dw 0x35BB ; + .dw 0x35BC ; + .dw 0x35BD ; + .dw 0x35BE ; + .dw 0x35BF ; + .dw 0x35C1 ; + .dw 0x35C2 ; + .dw 0x35C3 ; + .dw 0x35C4 ; + .dw 0x35C5 ; + .dw 0x35C6 ; +#if 0 + // Ireg = EMUDAT; is valid + .dw 0x35C7 ; +#endif + .dw 0x35C9 ; + .dw 0x35CA ; + .dw 0x35CB ; + .dw 0x35CC ; + .dw 0x35CD ; + .dw 0x35CE ; +#if 0 + // Ireg = EMUDAT; is valid + .dw 0x35CF ; +#endif + .dw 0x35D1 ; + .dw 0x35D2 ; + .dw 0x35D3 ; + .dw 0x35D4 ; + .dw 0x35D5 ; + .dw 0x35D6 ; +#if 0 + // Ireg = EMUDAT; is valid + .dw 0x35D7 ; +#endif + .dw 0x35D9 ; + .dw 0x35DA ; + .dw 0x35DB ; + .dw 0x35DC ; + .dw 0x35DD ; + .dw 0x35DE ; +#if 0 + // Ireg = EMUDAT; is valid + .dw 0x35DF ; +#endif + .dw 0x35E1 ; + .dw 0x35E2 ; + .dw 0x35E3 ; + .dw 0x35E4 ; + .dw 0x35E5 ; + .dw 0x35E6 ; +#if 0 + // Mreg = EMUDAT; is valid + .dw 0x35E7 ; +#endif + .dw 0x35E9 ; + .dw 0x35EA ; + .dw 0x35EB ; + .dw 0x35EC ; + .dw 0x35ED ; + .dw 0x35EE ; +#if 0 + // Mreg = EMUDAT; is valid + .dw 0x35EF ; +#endif + .dw 0x35F1 ; + .dw 0x35F2 ; + .dw 0x35F3 ; + .dw 0x35F4 ; + .dw 0x35F5 ; + .dw 0x35F6 ; +#if 0 + // Mreg = EMUDAT; is valid + .dw 0x35F7 ; +#endif + .dw 0x35F9 ; + .dw 0x35FA ; + .dw 0x35FB ; + .dw 0x35FC ; + .dw 0x35FD ; + .dw 0x35FE ; +#if 0 + // Mreg = EMUDAT; is valid + .dw 0x35FF ; +#endif + .dw 0x3780 ; + .dw 0x3781 ; + .dw 0x3782 ; + .dw 0x3783 ; + .dw 0x3784 ; + .dw 0x3785 ; + .dw 0x3786 ; + .dw 0x3787 ; + .dw 0x3788 ; + .dw 0x3789 ; + .dw 0x378A ; + .dw 0x378B ; + .dw 0x378C ; + .dw 0x378D ; + .dw 0x378E ; + .dw 0x378F ; + .dw 0x3790 ; + .dw 0x3791 ; + .dw 0x3792 ; + .dw 0x3793 ; + .dw 0x3794 ; + .dw 0x3795 ; + .dw 0x3796 ; + .dw 0x3797 ; + .dw 0x3798 ; + .dw 0x3799 ; + .dw 0x379A ; + .dw 0x379B ; + .dw 0x379C ; + .dw 0x379D ; + .dw 0x379E ; + .dw 0x379F ; + .dw 0x37A0 ; + .dw 0x37A1 ; + .dw 0x37A2 ; + .dw 0x37A3 ; + .dw 0x37A4 ; + .dw 0x37A5 ; + .dw 0x37A6 ; + .dw 0x37A7 ; + .dw 0x37A8 ; + .dw 0x37A9 ; + .dw 0x37AA ; + .dw 0x37AB ; + .dw 0x37AC ; + .dw 0x37AD ; + .dw 0x37AE ; + .dw 0x37AF ; + .dw 0x37B0 ; + .dw 0x37B1 ; + .dw 0x37B2 ; + .dw 0x37B3 ; + .dw 0x37B4 ; + .dw 0x37B5 ; + .dw 0x37B6 ; + .dw 0x37B7 ; + .dw 0x37B8 ; + .dw 0x37B9 ; + .dw 0x37BA ; + .dw 0x37BB ; + .dw 0x37BC ; + .dw 0x37BD ; + .dw 0x37BE ; + .dw 0x37BF ; + .dw 0x37C1 ; + .dw 0x37C2 ; + .dw 0x37C3 ; + .dw 0x37C4 ; + .dw 0x37C5 ; + .dw 0x37C6 ; +#if 0 + // EMUDAT = Breg; is valid + .dw 0x37C7 ; +#endif + .dw 0x37C9 ; + .dw 0x37CA ; + .dw 0x37CB ; + .dw 0x37CC ; + .dw 0x37CD ; + .dw 0x37CE ; +#if 0 + // EMUDAT = Breg; is valid + .dw 0x37CF ; +#endif + .dw 0x37D1 ; + .dw 0x37D2 ; + .dw 0x37D3 ; + .dw 0x37D4 ; + .dw 0x37D5 ; + .dw 0x37D6 ; +#if 0 + // EMUDAT = Breg; is valid + .dw 0x37D7 ; +#endif + .dw 0x37D9 ; + .dw 0x37DA ; + .dw 0x37DB ; + .dw 0x37DC ; + .dw 0x37DD ; + .dw 0x37DE ; +#if 0 + // EMUDAT = Breg; is valid + .dw 0x37DF ; +#endif + .dw 0x37E1 ; + .dw 0x37E2 ; + .dw 0x37E3 ; + .dw 0x37E4 ; + .dw 0x37E5 ; + .dw 0x37E6 ; +#if 0 + // EMUDAT = Lreg; is valid + .dw 0x37E7 ; +#endif + .dw 0x37E9 ; + .dw 0x37EA ; + .dw 0x37EB ; + .dw 0x37EC ; + .dw 0x37ED ; + .dw 0x37EE ; +#if 0 + // EMUDAT = Lreg; is valid + .dw 0x37EF ; +#endif + .dw 0x37F1 ; + .dw 0x37F2 ; + .dw 0x37F3 ; + .dw 0x37F4 ; + .dw 0x37F5 ; + .dw 0x37F6 ; +#if 0 + // EMUDAT = Lreg; is valid + .dw 0x37F7 ; +#endif + .dw 0x37F9 ; + .dw 0x37FA ; + .dw 0x37FB ; + .dw 0x37FC ; + .dw 0x37FD ; + .dw 0x37FE ; +#if 0 + // EMUDAT = Lreg; is valid + .dw 0x37FF ; +#endif + .dw 0x3506 ; + .dw 0x3507 ; + .dw 0x350E ; + .dw 0x350F ; + .dw 0x3516 ; + .dw 0x3517 ; + .dw 0x351E ; + .dw 0x351F ; + .dw 0x3526 ; + .dw 0x3527 ; + .dw 0x352E ; + .dw 0x352F ; + .dw 0x3536 ; + .dw 0x3537 ; + .dw 0x353E ; + .dw 0x353F ; + .dw 0x3706 ; + .dw 0x3707 ; + .dw 0x370E ; + .dw 0x370F ; + .dw 0x3716 ; + .dw 0x3717 ; + .dw 0x371E ; + .dw 0x371F ; + .dw 0x3726 ; + .dw 0x3727 ; + .dw 0x372E ; + .dw 0x372F ; + .dw 0x3736 ; + .dw 0x3737 ; + .dw 0x373E ; + .dw 0x373F ; + .dw 0x4180 ; + .dw 0x4181 ; + .dw 0x4182 ; + .dw 0x4183 ; + .dw 0x4184 ; + .dw 0x4185 ; + .dw 0x4186 ; + .dw 0x4187 ; + .dw 0x4188 ; + .dw 0x4189 ; + .dw 0x418A ; + .dw 0x418B ; + .dw 0x418C ; + .dw 0x418D ; + .dw 0x418E ; + .dw 0x418F ; + .dw 0x4190 ; + .dw 0x4191 ; + .dw 0x4192 ; + .dw 0x4193 ; + .dw 0x4194 ; + .dw 0x4195 ; + .dw 0x4196 ; + .dw 0x4197 ; + .dw 0x4198 ; + .dw 0x4199 ; + .dw 0x419A ; + .dw 0x419B ; + .dw 0x419C ; + .dw 0x419D ; + .dw 0x419E ; + .dw 0x419F ; + .dw 0x41A0 ; + .dw 0x41A1 ; + .dw 0x41A2 ; + .dw 0x41A3 ; + .dw 0x41A4 ; + .dw 0x41A5 ; + .dw 0x41A6 ; + .dw 0x41A7 ; + .dw 0x41A8 ; + .dw 0x41A9 ; + .dw 0x41AA ; + .dw 0x41AB ; + .dw 0x41AC ; + .dw 0x41AD ; + .dw 0x41AE ; + .dw 0x41AF ; + .dw 0x41B0 ; + .dw 0x41B1 ; + .dw 0x41B2 ; + .dw 0x41B3 ; + .dw 0x41B4 ; + .dw 0x41B5 ; + .dw 0x41B6 ; + .dw 0x41B7 ; + .dw 0x41B8 ; + .dw 0x41B9 ; + .dw 0x41BA ; + .dw 0x41BB ; + .dw 0x41BC ; + .dw 0x41BD ; + .dw 0x41BE ; + .dw 0x41BF ; + .dw 0x41C0 ; + .dw 0x41C1 ; + .dw 0x41C2 ; + .dw 0x41C3 ; + .dw 0x41C4 ; + .dw 0x41C5 ; + .dw 0x41C6 ; + .dw 0x41C7 ; + .dw 0x41C8 ; + .dw 0x41C9 ; + .dw 0x41CA ; + .dw 0x41CB ; + .dw 0x41CC ; + .dw 0x41CD ; + .dw 0x41CE ; + .dw 0x41CF ; + .dw 0x41D0 ; + .dw 0x41D1 ; + .dw 0x41D2 ; + .dw 0x41D3 ; + .dw 0x41D4 ; + .dw 0x41D5 ; + .dw 0x41D6 ; + .dw 0x41D7 ; + .dw 0x41D8 ; + .dw 0x41D9 ; + .dw 0x41DA ; + .dw 0x41DB ; + .dw 0x41DC ; + .dw 0x41DD ; + .dw 0x41DE ; + .dw 0x41DF ; + .dw 0x41E0 ; + .dw 0x41E1 ; + .dw 0x41E2 ; + .dw 0x41E3 ; + .dw 0x41E4 ; + .dw 0x41E5 ; + .dw 0x41E6 ; + .dw 0x41E7 ; + .dw 0x41E8 ; + .dw 0x41E9 ; + .dw 0x41EA ; + .dw 0x41EB ; + .dw 0x41EC ; + .dw 0x41ED ; + .dw 0x41EE ; + .dw 0x41EF ; + .dw 0x41F0 ; + .dw 0x41F1 ; + .dw 0x41F2 ; + .dw 0x41F3 ; + .dw 0x41F4 ; + .dw 0x41F5 ; + .dw 0x41F6 ; + .dw 0x41F7 ; + .dw 0x41F8 ; + .dw 0x41F9 ; + .dw 0x41FA ; + .dw 0x41FB ; + .dw 0x41FC ; + .dw 0x41FD ; + .dw 0x41FE ; + .dw 0x41FF ; +.ifndef BFIN_HW + // XXX: These cause double fault on hardware when run in IVG15 !? + .dw 0x9040 ; + .dw 0x9049 ; + .dw 0x9052 ; + .dw 0x905B ; + .dw 0x9064 ; + .dw 0x906D ; + .dw 0x9076 ; + .dw 0x907F ; + .dw 0x90C0 ; + .dw 0x90C9 ; + .dw 0x90D2 ; + .dw 0x90DB ; + .dw 0x90E4 ; + .dw 0x90ED ; + .dw 0x90F6 ; + .dw 0x90FF ; +.endif + .dw 0x9180 ; +// Starting 32bit s section COUNT = 3481 + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +.ifndef BFIN_HW +CHECKREG(r5, 2651 - 507); // count of all 16 bit UI's. +.else +CHECKREG(r5, 2651 - 524); // count of all 16 bit UI's. +.endif + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 16 bit illegal opcode handler - skips bad instruction + + // handler MADE LEAN and destructive so test runs more quckly + // se_undefinedinstruction1.dsp tests using a "nice" handler + +// [--sp] = ASTAT; // save what we damage +// [--sp] = (r7 - r6); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + + R6 = 0x22; // Also accept illegal insn combo +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + +dbg_fail; + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + r4 += 2; + CC = r4 == r7; + if !CC jump fail; + + R7 += 2; // skip offending 16 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: +// (r7 - r6) = [sp++]; +// ASTAT = [sp++]; + +RTX; +fail: +dbg_fail; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_undefinedinstruction3.S b/sim/testsuite/sim/bfin/se_undefinedinstruction3.S new file mode 100644 index 0000000..0acfb88 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_undefinedinstruction3.S @@ -0,0 +1,6022 @@ +//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction3/se_undefinedinstruction3.dsp +// Description: 32 bit special cases Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating +# xfail: "missing checks in A0/A1 macfunc" bfin-* + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + A0 = 0; // reset accumulators + A1 = 0; + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** + + // count of UI's will be in r5, which was initialized to 0 by header + + .dw 0xE802 ; + .dw 0xB3FD ; + .dw 0xE803 ; + .dw 0xD461 ; + .dw 0xE804 ; + .dw 0x36A1 ; + .dw 0xE805 ; + .dw 0x7FED ; + .dw 0xE806 ; + .dw 0xFEB3 ; + .dw 0xE807 ; + .dw 0x8785 ; + .dw 0xE808 ; + .dw 0x2F21 ; + .dw 0xE809 ; + .dw 0x2889 ; + .dw 0xE80A ; + .dw 0x96B7 ; + .dw 0xE80B ; + .dw 0x8357 ; + .dw 0xE80C ; + .dw 0x5D07 ; + .dw 0xE80D ; + .dw 0x13D5 ; + .dw 0xE80E ; + .dw 0x1C11 ; + .dw 0xE80F ; + .dw 0x19D3 ; + .dw 0xE810 ; + .dw 0xBF4B ; + .dw 0xE811 ; + .dw 0xEF89 ; + .dw 0xE812 ; + .dw 0x2BD ; + .dw 0xE813 ; + .dw 0x6FC5 ; + .dw 0xE814 ; + .dw 0x89F1 ; + .dw 0xE815 ; + .dw 0x1D13 ; + .dw 0xE816 ; + .dw 0xA03F ; + .dw 0xE817 ; + .dw 0x9681 ; + .dw 0xE818 ; + .dw 0x2961 ; + .dw 0xE819 ; + .dw 0xEE23 ; + .dw 0xE81A ; + .dw 0x7ABB ; + .dw 0xE81B ; + .dw 0x8927 ; + .dw 0xE81C ; + .dw 0x2343 ; + .dw 0xE81D ; + .dw 0x308F ; + .dw 0xE81E ; + .dw 0x718F ; + .dw 0xE81F ; + .dw 0xC549 ; + .dw 0xE820 ; + .dw 0x2CD3 ; + .dw 0xE821 ; + .dw 0x81D9 ; + .dw 0xE822 ; + .dw 0xD76B ; + .dw 0xE823 ; + .dw 0xB735 ; + .dw 0xE824 ; + .dw 0x4EBB ; + .dw 0xE825 ; + .dw 0x6223 ; + .dw 0xE826 ; + .dw 0x15EB ; + .dw 0xE827 ; + .dw 0xB19F ; + .dw 0xE828 ; + .dw 0x6E6B ; + .dw 0xE829 ; + .dw 0x7EA3 ; + .dw 0xE82A ; + .dw 0xF2A7 ; + .dw 0xE82B ; + .dw 0xA8E1 ; + .dw 0xE82C ; + .dw 0x14ED ; + .dw 0xE82D ; + .dw 0x2BA5 ; + .dw 0xE82E ; + .dw 0xDD5 ; + .dw 0xE82F ; + .dw 0x69AD ; + .dw 0xE830 ; + .dw 0xCB47 ; + .dw 0xE831 ; + .dw 0x85F7 ; + .dw 0xE832 ; + .dw 0xB25D ; + .dw 0xE833 ; + .dw 0x8351 ; + .dw 0xE834 ; + .dw 0xE445 ; + .dw 0xE835 ; + .dw 0x33E5 ; + .dw 0xE836 ; + .dw 0x8F6B ; + .dw 0xE837 ; + .dw 0x9D5B ; + .dw 0xE838 ; + .dw 0xBE1 ; + .dw 0xE839 ; + .dw 0x3DB9 ; + .dw 0xE83A ; + .dw 0x7391 ; + .dw 0xE83B ; + .dw 0x70E5 ; + .dw 0xE83C ; + .dw 0x7409 ; + .dw 0xE83D ; + .dw 0xF5A9 ; + .dw 0xE83E ; + .dw 0xA15B ; + .dw 0xE83F ; + .dw 0x1D3F ; + .dw 0xE840 ; + .dw 0xF709 ; + .dw 0xE841 ; + .dw 0x6751 ; + .dw 0xE842 ; + .dw 0xD565 ; + .dw 0xE843 ; + .dw 0x1035 ; + .dw 0xE844 ; + .dw 0x755 ; + .dw 0xE845 ; + .dw 0x46AD ; + .dw 0xE846 ; + .dw 0x95F3 ; + .dw 0xE847 ; + .dw 0x39B3 ; + .dw 0xE848 ; + .dw 0xC4EB ; + .dw 0xE849 ; + .dw 0xD693 ; + .dw 0xE84A ; + .dw 0xE40F ; + .dw 0xE84B ; + .dw 0xC30F ; + .dw 0xE84C ; + .dw 0x101F ; + .dw 0xE84D ; + .dw 0xBEA7 ; + .dw 0xE84E ; + .dw 0xE617 ; + .dw 0xE84F ; + .dw 0x1BD ; + .dw 0xE850 ; + .dw 0xF203 ; + .dw 0xE851 ; + .dw 0x48D5 ; + .dw 0xE852 ; + .dw 0xA3DD ; + .dw 0xE853 ; + .dw 0xDD7F ; + .dw 0xE854 ; + .dw 0x3233 ; + .dw 0xE855 ; + .dw 0xFE45 ; + .dw 0xE856 ; + .dw 0x6C3D ; + .dw 0xE857 ; + .dw 0x6225 ; + .dw 0xE858 ; + .dw 0x722F ; + .dw 0xE859 ; + .dw 0x1BDD ; + .dw 0xE85A ; + .dw 0xFC35 ; + .dw 0xE85B ; + .dw 0xB4C1 ; + .dw 0xE85C ; + .dw 0xA635 ; + .dw 0xE85D ; + .dw 0xD62D ; + .dw 0xE85E ; + .dw 0xFF7D ; + .dw 0xE85F ; + .dw 0x2463 ; + .dw 0xE860 ; + .dw 0x439B ; + .dw 0xE861 ; + .dw 0xE4EF ; + .dw 0xE862 ; + .dw 0x299 ; + .dw 0xE863 ; + .dw 0x8E4F ; + .dw 0xE864 ; + .dw 0xFCA1 ; + .dw 0xE865 ; + .dw 0x4DFD ; + .dw 0xE866 ; + .dw 0x6E7D ; + .dw 0xE867 ; + .dw 0xCDAF ; + .dw 0xE868 ; + .dw 0x61D1 ; + .dw 0xE869 ; + .dw 0xE7C7 ; + .dw 0xE86A ; + .dw 0xA59D ; + .dw 0xE86B ; + .dw 0x6ED7 ; + .dw 0xE86C ; + .dw 0x40CF ; + .dw 0xE86D ; + .dw 0x8B4B ; + .dw 0xE86E ; + .dw 0xDA83 ; + .dw 0xE86F ; + .dw 0x5DF1 ; + .dw 0xE870 ; + .dw 0x18B5 ; + .dw 0xE871 ; + .dw 0x6D91 ; + .dw 0xE872 ; + .dw 0xB7EF ; + .dw 0xE873 ; + .dw 0xC941 ; + .dw 0xE874 ; + .dw 0x7BE9 ; + .dw 0xE875 ; + .dw 0x98A3 ; + .dw 0xE876 ; + .dw 0x7269 ; + .dw 0xE877 ; + .dw 0xEECF ; + .dw 0xE878 ; + .dw 0xB77B ; + .dw 0xE879 ; + .dw 0xFBFD ; + .dw 0xE87A ; + .dw 0x5B59 ; + .dw 0xE87B ; + .dw 0xDAD ; + .dw 0xE87C ; + .dw 0x97F5 ; + .dw 0xE87D ; + .dw 0xC8B ; + .dw 0xE87E ; + .dw 0x8DA1 ; + .dw 0xE87F ; + .dw 0x32A5 ; + .dw 0xE880 ; + .dw 0xA3B7 ; + .dw 0xE881 ; + .dw 0x6C27 ; + .dw 0xE882 ; + .dw 0xCBB7 ; + .dw 0xE883 ; + .dw 0x1873 ; + .dw 0xE884 ; + .dw 0xA2CF ; + .dw 0xE885 ; + .dw 0x9083 ; + .dw 0xE886 ; + .dw 0x2737 ; + .dw 0xE887 ; + .dw 0xD383 ; + .dw 0xE888 ; + .dw 0xCC51 ; + .dw 0xE889 ; + .dw 0xE1AD ; + .dw 0xE88A ; + .dw 0x8A01 ; + .dw 0xE88B ; + .dw 0x8123 ; + .dw 0xE88C ; + .dw 0x712D ; + .dw 0xE88D ; + .dw 0x47FF ; + .dw 0xE88E ; + .dw 0xB8CD ; + .dw 0xE88F ; + .dw 0xB23B ; + .dw 0xE890 ; + .dw 0x7C89 ; + .dw 0xE891 ; + .dw 0xA19F ; + .dw 0xE892 ; + .dw 0xE745 ; + .dw 0xE893 ; + .dw 0xC985 ; + .dw 0xE894 ; + .dw 0xA199 ; + .dw 0xE895 ; + .dw 0x176F ; + .dw 0xE896 ; + .dw 0x759D ; + .dw 0xE897 ; + .dw 0x54B ; + .dw 0xE898 ; + .dw 0x8EF7 ; + .dw 0xE899 ; + .dw 0xC987 ; + .dw 0xE89A ; + .dw 0xEFAB ; + .dw 0xE89B ; + .dw 0x6C97 ; + .dw 0xE89C ; + .dw 0xFF7B ; + .dw 0xE89D ; + .dw 0xCB35 ; + .dw 0xE89E ; + .dw 0xE57B ; + .dw 0xE89F ; + .dw 0x57F1 ; + .dw 0xE8A0 ; + .dw 0x8F ; + .dw 0xE8A1 ; + .dw 0xE667 ; + .dw 0xE8A2 ; + .dw 0xB56F ; + .dw 0xE8A3 ; + .dw 0xCD93 ; + .dw 0xE8A4 ; + .dw 0x460F ; + .dw 0xE8A5 ; + .dw 0x1EAF ; + .dw 0xE8A6 ; + .dw 0xDFD1 ; + .dw 0xE8A7 ; + .dw 0x6921 ; + .dw 0xE8A8 ; + .dw 0xE397 ; + .dw 0xE8A9 ; + .dw 0x6BB9 ; + .dw 0xE8AA ; + .dw 0xFBEB ; + .dw 0xE8AB ; + .dw 0x6E7 ; + .dw 0xE8AC ; + .dw 0x4367 ; + .dw 0xE8AD ; + .dw 0xA337 ; + .dw 0xE8AE ; + .dw 0xE6A3 ; + .dw 0xE8AF ; + .dw 0xEA89 ; + .dw 0xE8B0 ; + .dw 0xB2B1 ; + .dw 0xE8B1 ; + .dw 0xA6D ; + .dw 0xE8B2 ; + .dw 0x428D ; + .dw 0xE8B3 ; + .dw 0x993D ; + .dw 0xE8B4 ; + .dw 0x5B73 ; + .dw 0xE8B5 ; + .dw 0x8717 ; + .dw 0xE8B6 ; + .dw 0xE189 ; + .dw 0xE8B7 ; + .dw 0x1F87 ; + .dw 0xE8B8 ; + .dw 0x3D3 ; + .dw 0xE8B9 ; + .dw 0xE7ED ; + .dw 0xE8BA ; + .dw 0x2FDB ; + .dw 0xE8BB ; + .dw 0xFA71 ; + .dw 0xE8BC ; + .dw 0x6AF7 ; + .dw 0xE8BD ; + .dw 0x3C97 ; + .dw 0xE8BE ; + .dw 0x38B9 ; + .dw 0xE8BF ; + .dw 0x5C3B ; + .dw 0xE8C0 ; + .dw 0x9B53 ; + .dw 0xE8C1 ; + .dw 0xB51F ; + .dw 0xE8C2 ; + .dw 0x5C73 ; + .dw 0xE8C3 ; + .dw 0x49D ; + .dw 0xE8C4 ; + .dw 0xA8F ; + .dw 0xE8C5 ; + .dw 0xF3 ; + .dw 0xE8C6 ; + .dw 0x4FFB ; + .dw 0xE8C7 ; + .dw 0x6479 ; + .dw 0xE8C8 ; + .dw 0xDED5 ; + .dw 0xE8C9 ; + .dw 0xA557 ; + .dw 0xE8CA ; + .dw 0x7E0D ; + .dw 0xE8CB ; + .dw 0x4513 ; + .dw 0xE8CC ; + .dw 0x31AF ; + .dw 0xE8CD ; + .dw 0x4361 ; + .dw 0xE8CE ; + .dw 0x61B5 ; + .dw 0xE8CF ; + .dw 0xAACB ; + .dw 0xE8D0 ; + .dw 0xA85B ; + .dw 0xE8D1 ; + .dw 0x4569 ; + .dw 0xE8D2 ; + .dw 0xF277 ; + .dw 0xE8D3 ; + .dw 0x2B57 ; + .dw 0xE8D4 ; + .dw 0x39A5 ; + .dw 0xE8D5 ; + .dw 0xEC0F ; + .dw 0xE8D6 ; + .dw 0xB9DF ; + .dw 0xE8D7 ; + .dw 0x6F75 ; + .dw 0xE8D8 ; + .dw 0x793F ; + .dw 0xE8D9 ; + .dw 0x32A1 ; + .dw 0xE8DA ; + .dw 0xAA99 ; + .dw 0xE8DB ; + .dw 0x1829 ; + .dw 0xE8DC ; + .dw 0x4097 ; + .dw 0xE8DD ; + .dw 0x8323 ; + .dw 0xE8DE ; + .dw 0x510B ; + .dw 0xE8DF ; + .dw 0xBF73 ; + .dw 0xE8E0 ; + .dw 0xD31 ; + .dw 0xE8E1 ; + .dw 0xB1BD ; + .dw 0xE8E2 ; + .dw 0x756F ; + .dw 0xE8E3 ; + .dw 0x4C83 ; + .dw 0xE8E4 ; + .dw 0xEC7F ; + .dw 0xE8E5 ; + .dw 0x37BB ; + .dw 0xE8E6 ; + .dw 0xC767 ; + .dw 0xE8E7 ; + .dw 0x5379 ; + .dw 0xE8E8 ; + .dw 0x4D39 ; + .dw 0xE8E9 ; + .dw 0x25F9 ; + .dw 0xE8EA ; + .dw 0xAB13 ; + .dw 0xE8EB ; + .dw 0xB895 ; + .dw 0xE8EC ; + .dw 0x8E35 ; + .dw 0xE8ED ; + .dw 0xC6EB ; + .dw 0xE8EE ; + .dw 0xBFB3 ; + .dw 0xE8EF ; + .dw 0x4EF3 ; + .dw 0xE8F0 ; + .dw 0xA2B9 ; + .dw 0xE8F1 ; + .dw 0x6807 ; + .dw 0xE8F2 ; + .dw 0x37B3 ; + .dw 0xE8F3 ; + .dw 0xAAC3 ; + .dw 0xE8F4 ; + .dw 0xA461 ; + .dw 0xE8F5 ; + .dw 0x42C3 ; + .dw 0xE8F6 ; + .dw 0x9A4B ; + .dw 0xE8F7 ; + .dw 0xDF03 ; + .dw 0xE8F8 ; + .dw 0xAA6B ; + .dw 0xE8F9 ; + .dw 0xFD0F ; + .dw 0xE8FA ; + .dw 0x695 ; + .dw 0xE8FB ; + .dw 0x5EB1 ; + .dw 0xE8FC ; + .dw 0xBE8D ; + .dw 0xE8FD ; + .dw 0xB949 ; + .dw 0xE8FE ; + .dw 0x9023 ; + .dw 0xE8FF ; + .dw 0xB987 ; + .dw 0xE900 ; + .dw 0x475B ; + .dw 0xE901 ; + .dw 0x2DB5 ; + .dw 0xE902 ; + .dw 0xCD17 ; + .dw 0xE903 ; + .dw 0x6C33 ; + .dw 0xE904 ; + .dw 0xC013 ; + .dw 0xE905 ; + .dw 0xBB77 ; + .dw 0xE906 ; + .dw 0x2DC3 ; + .dw 0xE907 ; + .dw 0x7C11 ; + .dw 0xE908 ; + .dw 0x15F7 ; + .dw 0xE909 ; + .dw 0xFD0F ; + .dw 0xE90A ; + .dw 0x35B1 ; + .dw 0xE90B ; + .dw 0x165D ; + .dw 0xE90C ; + .dw 0x8327 ; + .dw 0xE90D ; + .dw 0xC449 ; + .dw 0xE90E ; + .dw 0x2E4F ; + .dw 0xE90F ; + .dw 0xEAEF ; + .dw 0xE910 ; + .dw 0x3EFB ; + .dw 0xE911 ; + .dw 0xFFB3 ; + .dw 0xE912 ; + .dw 0x6AF3 ; + .dw 0xE913 ; + .dw 0x7A73 ; + .dw 0xE914 ; + .dw 0xDBD7 ; + .dw 0xE915 ; + .dw 0x7FA7 ; + .dw 0xE916 ; + .dw 0xB681 ; + .dw 0xE917 ; + .dw 0x1023 ; + .dw 0xE918 ; + .dw 0xAA85 ; + .dw 0xE919 ; + .dw 0x12A9 ; + .dw 0xE91A ; + .dw 0x27F ; + .dw 0xE91B ; + .dw 0x9EF7 ; + .dw 0xE91C ; + .dw 0xFB09 ; + .dw 0xE91D ; + .dw 0xF179 ; + .dw 0xE91E ; + .dw 0xEFAD ; + .dw 0xE91F ; + .dw 0x3A67 ; + .dw 0xE920 ; + .dw 0x9301 ; + .dw 0xE921 ; + .dw 0xF273 ; + .dw 0xE922 ; + .dw 0x4819 ; + .dw 0xE923 ; + .dw 0x629F ; + .dw 0xE924 ; + .dw 0x3177 ; + .dw 0xE925 ; + .dw 0x7C9B ; + .dw 0xE926 ; + .dw 0x2BD ; + .dw 0xE927 ; + .dw 0xDC33 ; + .dw 0xE928 ; + .dw 0x783B ; + .dw 0xE929 ; + .dw 0xB20B ; + .dw 0xE92A ; + .dw 0xE895 ; + .dw 0xE92B ; + .dw 0x4B5D ; + .dw 0xE92C ; + .dw 0x12B7 ; + .dw 0xE92D ; + .dw 0xC9E7 ; + .dw 0xE92E ; + .dw 0x7335 ; + .dw 0xE92F ; + .dw 0x4AB1 ; + .dw 0xE930 ; + .dw 0x7251 ; + .dw 0xE931 ; + .dw 0x11E1 ; + .dw 0xE932 ; + .dw 0xFCE3 ; + .dw 0xE933 ; + .dw 0x3557 ; + .dw 0xE934 ; + .dw 0xF837 ; + .dw 0xE935 ; + .dw 0x8F27 ; + .dw 0xE936 ; + .dw 0xDA2F ; + .dw 0xE937 ; + .dw 0x5CC3 ; + .dw 0xE938 ; + .dw 0xE4BD ; + .dw 0xE939 ; + .dw 0xB6DF ; + .dw 0xE93A ; + .dw 0x7509 ; + .dw 0xE93B ; + .dw 0xE1EB ; + .dw 0xE93C ; + .dw 0xE439 ; + .dw 0xE93D ; + .dw 0x3621 ; + .dw 0xE93E ; + .dw 0x15D ; + .dw 0xE93F ; + .dw 0xEA05 ; + .dw 0xE940 ; + .dw 0x9151 ; + .dw 0xE941 ; + .dw 0x4169 ; + .dw 0xE942 ; + .dw 0xE325 ; + .dw 0xE943 ; + .dw 0x66B5 ; + .dw 0xE944 ; + .dw 0xC4DD ; + .dw 0xE945 ; + .dw 0x6395 ; + .dw 0xE946 ; + .dw 0x5E09 ; + .dw 0xE947 ; + .dw 0x29CD ; + .dw 0xE948 ; + .dw 0xB35 ; + .dw 0xE949 ; + .dw 0x4459 ; + .dw 0xE94A ; + .dw 0xA671 ; + .dw 0xE94B ; + .dw 0x7C83 ; + .dw 0xE94C ; + .dw 0x1715 ; + .dw 0xE94D ; + .dw 0x5E37 ; + .dw 0xE94E ; + .dw 0xEC19 ; + .dw 0xE94F ; + .dw 0xF227 ; + .dw 0xE950 ; + .dw 0x89E9 ; + .dw 0xE951 ; + .dw 0x1BFD ; + .dw 0xE952 ; + .dw 0x7637 ; + .dw 0xE953 ; + .dw 0xAE5B ; + .dw 0xE954 ; + .dw 0xE9AF ; + .dw 0xE955 ; + .dw 0x55B5 ; + .dw 0xE956 ; + .dw 0x6905 ; + .dw 0xE957 ; + .dw 0xD6D3 ; + .dw 0xE958 ; + .dw 0x1C47 ; + .dw 0xE959 ; + .dw 0xA523 ; + .dw 0xE95A ; + .dw 0x4CE1 ; + .dw 0xE95B ; + .dw 0x687F ; + .dw 0xE95C ; + .dw 0x404F ; + .dw 0xE95D ; + .dw 0x89B5 ; + .dw 0xE95E ; + .dw 0xEEE1 ; + .dw 0xE95F ; + .dw 0x2851 ; + .dw 0xE960 ; + .dw 0x3B7D ; + .dw 0xE961 ; + .dw 0xD409 ; + .dw 0xE962 ; + .dw 0xB2ED ; + .dw 0xE963 ; + .dw 0xE767 ; + .dw 0xE964 ; + .dw 0xD673 ; + .dw 0xE965 ; + .dw 0x50D5 ; + .dw 0xE966 ; + .dw 0xEF57 ; + .dw 0xE967 ; + .dw 0xD2D1 ; + .dw 0xE968 ; + .dw 0xBE17 ; + .dw 0xE969 ; + .dw 0x2B6B ; + .dw 0xE96A ; + .dw 0x69F1 ; + .dw 0xE96B ; + .dw 0x6C1 ; + .dw 0xE96C ; + .dw 0x426F ; + .dw 0xE96D ; + .dw 0xFFA9 ; + .dw 0xE96E ; + .dw 0x8EA9 ; + .dw 0xE96F ; + .dw 0x1D41 ; + .dw 0xE970 ; + .dw 0x2AF5 ; + .dw 0xE971 ; + .dw 0x1379 ; + .dw 0xE972 ; + .dw 0x779D ; + .dw 0xE973 ; + .dw 0xF075 ; + .dw 0xE974 ; + .dw 0x7871 ; + .dw 0xE975 ; + .dw 0xAFC1 ; + .dw 0xE976 ; + .dw 0x5EB3 ; + .dw 0xE977 ; + .dw 0x4845 ; + .dw 0xE978 ; + .dw 0x6C4F ; + .dw 0xE979 ; + .dw 0x10E1 ; + .dw 0xE97A ; + .dw 0x90B7 ; + .dw 0xE97B ; + .dw 0xABA3 ; + .dw 0xE97C ; + .dw 0xAD7B ; + .dw 0xE97D ; + .dw 0xE6A3 ; + .dw 0xE97E ; + .dw 0x79E9 ; + .dw 0xE97F ; + .dw 0xD37 ; + .dw 0xE980 ; + .dw 0xE2B5 ; + .dw 0xE981 ; + .dw 0xDBBF ; + .dw 0xE982 ; + .dw 0xE41D ; + .dw 0xE983 ; + .dw 0x8BA3 ; + .dw 0xE984 ; + .dw 0x9A6B ; + .dw 0xE985 ; + .dw 0x1CCB ; + .dw 0xE986 ; + .dw 0xFE53 ; + .dw 0xE987 ; + .dw 0xFD2D ; + .dw 0xE988 ; + .dw 0xD811 ; + .dw 0xE989 ; + .dw 0x56B1 ; + .dw 0xE98A ; + .dw 0x45C9 ; + .dw 0xE98B ; + .dw 0x7F05 ; + .dw 0xE98C ; + .dw 0x1EF7 ; + .dw 0xE98D ; + .dw 0x24AF ; + .dw 0xE98E ; + .dw 0xE895 ; + .dw 0xE98F ; + .dw 0xBFF1 ; + .dw 0xE990 ; + .dw 0x52A5 ; + .dw 0xE991 ; + .dw 0x65C7 ; + .dw 0xE992 ; + .dw 0xB9C5 ; + .dw 0xE993 ; + .dw 0x3E8F ; + .dw 0xE994 ; + .dw 0x44AB ; + .dw 0xE995 ; + .dw 0x71BD ; + .dw 0xE996 ; + .dw 0x4EEB ; + .dw 0xE997 ; + .dw 0x3307 ; + .dw 0xE998 ; + .dw 0x4807 ; + .dw 0xE999 ; + .dw 0xA58B ; + .dw 0xE99A ; + .dw 0x5F3B ; + .dw 0xE99B ; + .dw 0x5C45 ; + .dw 0xE99C ; + .dw 0xA1EB ; + .dw 0xE99D ; + .dw 0x3F5B ; + .dw 0xE99E ; + .dw 0xFC25 ; + .dw 0xE99F ; + .dw 0x68AD ; + .dw 0xE9A0 ; + .dw 0x3029 ; + .dw 0xE9A1 ; + .dw 0x1FD ; + .dw 0xE9A2 ; + .dw 0xBB69 ; + .dw 0xE9A3 ; + .dw 0x3259 ; + .dw 0xE9A4 ; + .dw 0x1CF5 ; + .dw 0xE9A5 ; + .dw 0x97E5 ; + .dw 0xE9A6 ; + .dw 0x6AB1 ; + .dw 0xE9A7 ; + .dw 0x86D3 ; + .dw 0xE9A8 ; + .dw 0xF853 ; + .dw 0xE9A9 ; + .dw 0x2D9B ; + .dw 0xE9AA ; + .dw 0x64A5 ; + .dw 0xE9AB ; + .dw 0xB23F ; + .dw 0xE9AC ; + .dw 0xEDD ; + .dw 0xE9AD ; + .dw 0x3BB5 ; + .dw 0xE9AE ; + .dw 0x1F8F ; + .dw 0xE9AF ; + .dw 0x8627 ; + .dw 0xE9B0 ; + .dw 0x5627 ; + .dw 0xE9B1 ; + .dw 0xF853 ; + .dw 0xE9B2 ; + .dw 0xD5F ; + .dw 0xE9B3 ; + .dw 0x139F ; + .dw 0xE9B4 ; + .dw 0xC691 ; + .dw 0xE9B5 ; + .dw 0x6815 ; + .dw 0xE9B6 ; + .dw 0x655B ; + .dw 0xE9B7 ; + .dw 0xD10B ; + .dw 0xE9B8 ; + .dw 0x7A9D ; + .dw 0xE9B9 ; + .dw 0x868F ; + .dw 0xE9BA ; + .dw 0xEF1F ; + .dw 0xE9BB ; + .dw 0x6355 ; + .dw 0xE9BC ; + .dw 0x6BD3 ; + .dw 0xE9BD ; + .dw 0x7E4B ; + .dw 0xE9BE ; + .dw 0x6747 ; + .dw 0xE9BF ; + .dw 0xC29D ; + .dw 0xE9C0 ; + .dw 0x2507 ; + .dw 0xE9C1 ; + .dw 0x6833 ; + .dw 0xE9C2 ; + .dw 0x957F ; + .dw 0xE9C3 ; + .dw 0xF27B ; + .dw 0xE9C4 ; + .dw 0x4241 ; + .dw 0xE9C5 ; + .dw 0x8A97 ; + .dw 0xE9C6 ; + .dw 0xAC1D ; + .dw 0xE9C7 ; + .dw 0x5B1 ; + .dw 0xE9C8 ; + .dw 0x160B ; + .dw 0xE9C9 ; + .dw 0x8F99 ; + .dw 0xE9CA ; + .dw 0x939 ; + .dw 0xE9CB ; + .dw 0xA561 ; + .dw 0xE9CC ; + .dw 0x4C51 ; + .dw 0xE9CD ; + .dw 0xAB2D ; + .dw 0xE9CE ; + .dw 0xF143 ; + .dw 0xE9CF ; + .dw 0xD3CF ; + .dw 0xE9D0 ; + .dw 0xE2AD ; + .dw 0xE9D1 ; + .dw 0x288F ; + .dw 0xE9D2 ; + .dw 0x5B1D ; + .dw 0xE9D3 ; + .dw 0x228F ; + .dw 0xE9D4 ; + .dw 0x4E4D ; + .dw 0xE9D5 ; + .dw 0x573B ; + .dw 0xE9D6 ; + .dw 0x65B1 ; + .dw 0xE9D7 ; + .dw 0x143F ; + .dw 0xE9D8 ; + .dw 0x2743 ; + .dw 0xE9D9 ; + .dw 0x4F61 ; + .dw 0xE9DA ; + .dw 0x8F0F ; + .dw 0xE9DB ; + .dw 0xE1C5 ; + .dw 0xE9DC ; + .dw 0x315D ; + .dw 0xE9DD ; + .dw 0x85E7 ; + .dw 0xE9DE ; + .dw 0x44FB ; + .dw 0xE9DF ; + .dw 0x5AFB ; + .dw 0xE9E0 ; + .dw 0x1A81 ; + .dw 0xE9E1 ; + .dw 0xA7D3 ; + .dw 0xE9E2 ; + .dw 0xE70F ; + .dw 0xE9E3 ; + .dw 0x1AF7 ; + .dw 0xE9E4 ; + .dw 0xC67D ; + .dw 0xE9E5 ; + .dw 0xB54D ; + .dw 0xE9E6 ; + .dw 0xD24B ; + .dw 0xE9E7 ; + .dw 0xC7B7 ; + .dw 0xE9E8 ; + .dw 0x806B ; + .dw 0xE9E9 ; + .dw 0xD419 ; + .dw 0xE9EA ; + .dw 0x8E35 ; + .dw 0xE9EB ; + .dw 0x955B ; + .dw 0xE9EC ; + .dw 0xE981 ; + .dw 0xE9ED ; + .dw 0xD187 ; + .dw 0xE9EE ; + .dw 0xB365 ; + .dw 0xE9EF ; + .dw 0xC4DF ; + .dw 0xE9F0 ; + .dw 0xFD67 ; + .dw 0xE9F1 ; + .dw 0xCBEB ; + .dw 0xE9F2 ; + .dw 0xA3AD ; + .dw 0xE9F3 ; + .dw 0x5653 ; + .dw 0xE9F4 ; + .dw 0x415 ; + .dw 0xE9F5 ; + .dw 0xFB9F ; + .dw 0xE9F6 ; + .dw 0xABA3 ; + .dw 0xE9F7 ; + .dw 0xA695 ; + .dw 0xE9F8 ; + .dw 0xC929 ; + .dw 0xE9F9 ; + .dw 0x136F ; + .dw 0xE9FA ; + .dw 0xA5BF ; + .dw 0xE9FB ; + .dw 0x3083 ; + .dw 0xE9FC ; + .dw 0xF0BF ; + .dw 0xE9FD ; + .dw 0x309B ; + .dw 0xE9FE ; + .dw 0xB6F5 ; + .dw 0xE9FF ; + .dw 0x29B7 ; + .dw 0xEA00 ; + .dw 0xC1C5 ; + .dw 0xEA01 ; + .dw 0xD249 ; + .dw 0xEA02 ; + .dw 0x3CCB ; + .dw 0xEA03 ; + .dw 0x32BF ; + .dw 0xEA04 ; + .dw 0x3DDB ; + .dw 0xEA05 ; + .dw 0xD07B ; + .dw 0xEA06 ; + .dw 0x84EB ; + .dw 0xEA07 ; + .dw 0xD2D7 ; + .dw 0xEA08 ; + .dw 0xDEA3 ; + .dw 0xEA09 ; + .dw 0xCA8F ; + .dw 0xEA0A ; + .dw 0x6645 ; + .dw 0xEA0B ; + .dw 0xF71B ; + .dw 0xEA0C ; + .dw 0xD09F ; + .dw 0xEA0D ; + .dw 0x533 ; + .dw 0xEA0E ; + .dw 0x53A3 ; + .dw 0xEA0F ; + .dw 0x2D41 ; + .dw 0xEA10 ; + .dw 0x383 ; + .dw 0xEA11 ; + .dw 0x2FD7 ; + .dw 0xEA12 ; + .dw 0xFFBF ; + .dw 0xEA13 ; + .dw 0xD1DB ; + .dw 0xEA14 ; + .dw 0xE815 ; + .dw 0xEA15 ; + .dw 0x9B1 ; + .dw 0xEA16 ; + .dw 0x2ADB ; + .dw 0xEA17 ; + .dw 0xE9FB ; + .dw 0xEA18 ; + .dw 0x337F ; + .dw 0xEA19 ; + .dw 0x5E29 ; + .dw 0xEA1A ; + .dw 0xB1DD ; + .dw 0xEA1B ; + .dw 0xE07F ; + .dw 0xEA1C ; + .dw 0x8025 ; + .dw 0xEA1D ; + .dw 0x50DB ; + .dw 0xEA1E ; + .dw 0x76E3 ; + .dw 0xEA1F ; + .dw 0xDEBF ; + .dw 0xEA20 ; + .dw 0x2407 ; + .dw 0xEA21 ; + .dw 0x7107 ; + .dw 0xEA22 ; + .dw 0x3B5F ; + .dw 0xEA23 ; + .dw 0xF8C1 ; + .dw 0xEA24 ; + .dw 0x148B ; + .dw 0xEA25 ; + .dw 0x8C8D ; + .dw 0xEA26 ; + .dw 0x3A9 ; + .dw 0xEA27 ; + .dw 0xE4FF ; + .dw 0xEA28 ; + .dw 0x2FE3 ; + .dw 0xEA29 ; + .dw 0xBA69 ; + .dw 0xEA2A ; + .dw 0x1C1D ; + .dw 0xEA2B ; + .dw 0x7791 ; + .dw 0xEA2C ; + .dw 0xC3D9 ; + .dw 0xEA2D ; + .dw 0x94A1 ; + .dw 0xEA2E ; + .dw 0x57AD ; + .dw 0xEA2F ; + .dw 0x98EB ; + .dw 0xEA30 ; + .dw 0xAA33 ; + .dw 0xEA31 ; + .dw 0x19C3 ; + .dw 0xEA32 ; + .dw 0xA003 ; + .dw 0xEA33 ; + .dw 0xF015 ; + .dw 0xEA34 ; + .dw 0xD27F ; + .dw 0xEA35 ; + .dw 0x2DE1 ; + .dw 0xEA36 ; + .dw 0x6F0B ; + .dw 0xEA37 ; + .dw 0xF863 ; + .dw 0xEA38 ; + .dw 0x9173 ; + .dw 0xEA39 ; + .dw 0x32FD ; + .dw 0xEA3A ; + .dw 0x4A19 ; + .dw 0xEA3B ; + .dw 0xBAAB ; + .dw 0xEA3C ; + .dw 0x8DC1 ; + .dw 0xEA3D ; + .dw 0xB113 ; + .dw 0xEA3E ; + .dw 0xD677 ; + .dw 0xEA3F ; + .dw 0xE203 ; + .dw 0xEA40 ; + .dw 0xA271 ; + .dw 0xEA41 ; + .dw 0x857B ; + .dw 0xEA42 ; + .dw 0x9F7F ; + .dw 0xEA43 ; + .dw 0x63EF ; + .dw 0xEA44 ; + .dw 0x8EBB ; + .dw 0xEA45 ; + .dw 0x91F7 ; + .dw 0xEA46 ; + .dw 0x2639 ; + .dw 0xEA47 ; + .dw 0x7421 ; + .dw 0xEA48 ; + .dw 0xCB59 ; + .dw 0xEA49 ; + .dw 0x6317 ; + .dw 0xEA4A ; + .dw 0x5269 ; + .dw 0xEA4B ; + .dw 0xFBAF ; + .dw 0xEA4C ; + .dw 0x5D63 ; + .dw 0xEA4D ; + .dw 0xC63F ; + .dw 0xEA4E ; + .dw 0xDD33 ; + .dw 0xEA4F ; + .dw 0x4BC7 ; + .dw 0xEA50 ; + .dw 0xFEA7 ; + .dw 0xEA51 ; + .dw 0xC71F ; + .dw 0xEA52 ; + .dw 0xCD29 ; + .dw 0xEA53 ; + .dw 0x43F1 ; + .dw 0xEA54 ; + .dw 0x7383 ; + .dw 0xEA55 ; + .dw 0xC9D ; + .dw 0xEA56 ; + .dw 0x9BE5 ; + .dw 0xEA57 ; + .dw 0xA3BB ; + .dw 0xEA58 ; + .dw 0x6637 ; + .dw 0xEA59 ; + .dw 0xD5F ; + .dw 0xEA5A ; + .dw 0x1D23 ; + .dw 0xEA5B ; + .dw 0xBFF7 ; + .dw 0xEA5C ; + .dw 0x9FC3 ; + .dw 0xEA5D ; + .dw 0x13B5 ; + .dw 0xEA5E ; + .dw 0xBF5D ; + .dw 0xEA5F ; + .dw 0x5375 ; + .dw 0xEA60 ; + .dw 0xF639 ; + .dw 0xEA61 ; + .dw 0x8919 ; + .dw 0xEA62 ; + .dw 0x3DD9 ; + .dw 0xEA63 ; + .dw 0xA337 ; + .dw 0xEA64 ; + .dw 0xC89D ; + .dw 0xEA65 ; + .dw 0x8125 ; + .dw 0xEA66 ; + .dw 0x5C47 ; + .dw 0xEA67 ; + .dw 0xAE2B ; + .dw 0xEA68 ; + .dw 0x6035 ; + .dw 0xEA69 ; + .dw 0xFC07 ; + .dw 0xEA6A ; + .dw 0xC3DD ; + .dw 0xEA6B ; + .dw 0xA063 ; + .dw 0xEA6C ; + .dw 0xF69 ; + .dw 0xEA6D ; + .dw 0xD881 ; + .dw 0xEA6E ; + .dw 0x99E7 ; + .dw 0xEA6F ; + .dw 0x41C9 ; + .dw 0xEA70 ; + .dw 0x660F ; + .dw 0xEA71 ; + .dw 0xED5B ; + .dw 0xEA72 ; + .dw 0xE7E3 ; + .dw 0xEA73 ; + .dw 0x9861 ; + .dw 0xEA74 ; + .dw 0x534F ; + .dw 0xEA75 ; + .dw 0x4259 ; + .dw 0xEA76 ; + .dw 0x6D17 ; + .dw 0xEA77 ; + .dw 0x75F3 ; + .dw 0xEA78 ; + .dw 0x8CFB ; + .dw 0xEA79 ; + .dw 0xE0BD ; + .dw 0xEA7A ; + .dw 0xF1AD ; + .dw 0xEA7B ; + .dw 0x2951 ; + .dw 0xEA7C ; + .dw 0x1459 ; + .dw 0xEA7D ; + .dw 0x3331 ; + .dw 0xEA7E ; + .dw 0xB349 ; + .dw 0xEA7F ; + .dw 0xB03 ; + .dw 0xEA80 ; + .dw 0x308B ; + .dw 0xEA81 ; + .dw 0x6D4F ; + .dw 0xEA82 ; + .dw 0x31D ; + .dw 0xEA83 ; + .dw 0x1D8B ; + .dw 0xEA84 ; + .dw 0xB661 ; + .dw 0xEA85 ; + .dw 0xF289 ; + .dw 0xEA86 ; + .dw 0xAD87 ; + .dw 0xEA87 ; + .dw 0x790F ; + .dw 0xEA88 ; + .dw 0xF5AB ; + .dw 0xEA89 ; + .dw 0x34AD ; + .dw 0xEA8A ; + .dw 0x4327 ; + .dw 0xEA8B ; + .dw 0xBA9D ; + .dw 0xEA8C ; + .dw 0x241B ; + .dw 0xEA8D ; + .dw 0x1D5 ; + .dw 0xEA8E ; + .dw 0xDB77 ; + .dw 0xEA8F ; + .dw 0x2EE1 ; + .dw 0xEA90 ; + .dw 0x9D99 ; + .dw 0xEA91 ; + .dw 0xB9E5 ; + .dw 0xEA92 ; + .dw 0x68DD ; + .dw 0xEA93 ; + .dw 0xF053 ; + .dw 0xEA94 ; + .dw 0xD215 ; + .dw 0xEA95 ; + .dw 0x6383 ; + .dw 0xEA96 ; + .dw 0x3651 ; + .dw 0xEA97 ; + .dw 0xB0FD ; + .dw 0xEA98 ; + .dw 0x38ED ; + .dw 0xEA99 ; + .dw 0x1885 ; + .dw 0xEA9A ; + .dw 0xA665 ; + .dw 0xEA9B ; + .dw 0x67A9 ; + .dw 0xEA9C ; + .dw 0x21B5 ; + .dw 0xEA9D ; + .dw 0xC1F9 ; + .dw 0xEA9E ; + .dw 0xCBE7 ; + .dw 0xEA9F ; + .dw 0x989F ; + .dw 0xEAA0 ; + .dw 0xBA99 ; + .dw 0xEAA1 ; + .dw 0x9B8D ; + .dw 0xEAA2 ; + .dw 0xF3FB ; + .dw 0xEAA3 ; + .dw 0x71D9 ; + .dw 0xEAA4 ; + .dw 0x2435 ; + .dw 0xEAA5 ; + .dw 0x7693 ; + .dw 0xEAA6 ; + .dw 0xB9A7 ; + .dw 0xEAA7 ; + .dw 0x72BB ; + .dw 0xEAA8 ; + .dw 0xEAE7 ; + .dw 0xEAA9 ; + .dw 0x3475 ; + .dw 0xEAAA ; + .dw 0xBAF9 ; + .dw 0xEAAB ; + .dw 0xD74F ; + .dw 0xEAAC ; + .dw 0xBDAB ; + .dw 0xEAAD ; + .dw 0x70A9 ; + .dw 0xEAAE ; + .dw 0x8793 ; + .dw 0xEAAF ; + .dw 0x7EFD ; + .dw 0xEAB0 ; + .dw 0xBA75 ; + .dw 0xEAB1 ; + .dw 0xD231 ; + .dw 0xEAB2 ; + .dw 0xE0CB ; + .dw 0xEAB3 ; + .dw 0x86B9 ; + .dw 0xEAB4 ; + .dw 0x2805 ; + .dw 0xEAB5 ; + .dw 0xFC89 ; + .dw 0xEAB6 ; + .dw 0xE343 ; + .dw 0xEAB7 ; + .dw 0x4EC7 ; + .dw 0xEAB8 ; + .dw 0xF53F ; + .dw 0xEAB9 ; + .dw 0x982B ; + .dw 0xEABA ; + .dw 0x31FB ; + .dw 0xEABB ; + .dw 0x23F1 ; + .dw 0xEABC ; + .dw 0xD607 ; + .dw 0xEABD ; + .dw 0x6A79 ; + .dw 0xEABE ; + .dw 0xBAEB ; + .dw 0xEABF ; + .dw 0x4437 ; + .dw 0xEAC0 ; + .dw 0x5593 ; + .dw 0xEAC1 ; + .dw 0xF541 ; + .dw 0xEAC2 ; + .dw 0x2D23 ; + .dw 0xEAC3 ; + .dw 0x7711 ; + .dw 0xEAC4 ; + .dw 0xB64B ; + .dw 0xEAC5 ; + .dw 0x95B3 ; + .dw 0xEAC6 ; + .dw 0xB859 ; + .dw 0xEAC7 ; + .dw 0xF11F ; + .dw 0xEAC8 ; + .dw 0xF71B ; + .dw 0xEAC9 ; + .dw 0x9AD1 ; + .dw 0xEACA ; + .dw 0x2DFF ; + .dw 0xEACB ; + .dw 0xBB69 ; + .dw 0xEACC ; + .dw 0xD649 ; + .dw 0xEACD ; + .dw 0x4B71 ; + .dw 0xEACE ; + .dw 0x1BEB ; + .dw 0xEACF ; + .dw 0x560D ; + .dw 0xEAD0 ; + .dw 0x29D7 ; + .dw 0xEAD1 ; + .dw 0x53AD ; + .dw 0xEAD2 ; + .dw 0xF85B ; + .dw 0xEAD3 ; + .dw 0xCE81 ; + .dw 0xEAD4 ; + .dw 0x654F ; + .dw 0xEAD5 ; + .dw 0x91DF ; + .dw 0xEAD6 ; + .dw 0xF79D ; + .dw 0xEAD7 ; + .dw 0x143 ; + .dw 0xEAD8 ; + .dw 0xA521 ; + .dw 0xEAD9 ; + .dw 0xBB1B ; + .dw 0xEADA ; + .dw 0xA31F ; + .dw 0xEADB ; + .dw 0x3F17 ; + .dw 0xEADC ; + .dw 0x177D ; + .dw 0xEADD ; + .dw 0xCF23 ; + .dw 0xEADE ; + .dw 0xCA05 ; + .dw 0xEADF ; + .dw 0xDBD ; + .dw 0xEAE0 ; + .dw 0x1AA7 ; + .dw 0xEAE1 ; + .dw 0xD3DF ; + .dw 0xEAE2 ; + .dw 0xE347 ; + .dw 0xEAE3 ; + .dw 0x3C25 ; + .dw 0xEAE4 ; + .dw 0xE8D3 ; + .dw 0xEAE5 ; + .dw 0xD059 ; + .dw 0xEAE6 ; + .dw 0x7949 ; + .dw 0xEAE7 ; + .dw 0x22D ; + .dw 0xEAE8 ; + .dw 0x2975 ; + .dw 0xEAE9 ; + .dw 0x7F33 ; + .dw 0xEAEA ; + .dw 0xB6ED ; + .dw 0xEAEB ; + .dw 0x63D9 ; + .dw 0xEAEC ; + .dw 0x4025 ; + .dw 0xEAED ; + .dw 0xB09B ; + .dw 0xEAEE ; + .dw 0xAE2F ; + .dw 0xEAEF ; + .dw 0x9003 ; + .dw 0xEAF0 ; + .dw 0xB0EB ; + .dw 0xEAF1 ; + .dw 0xD3C7 ; + .dw 0xEAF2 ; + .dw 0x703D ; + .dw 0xEAF3 ; + .dw 0x729B ; + .dw 0xEAF4 ; + .dw 0x7221 ; + .dw 0xEAF5 ; + .dw 0x9FF1 ; + .dw 0xEAF6 ; + .dw 0x8F11 ; + .dw 0xEAF7 ; + .dw 0x325F ; + .dw 0xEAF8 ; + .dw 0x83C1 ; + .dw 0xEAF9 ; + .dw 0x54C7 ; + .dw 0xEAFA ; + .dw 0x2081 ; + .dw 0xEAFB ; + .dw 0xD20D ; + .dw 0xEAFC ; + .dw 0xA449 ; + .dw 0xEAFD ; + .dw 0x8A67 ; + .dw 0xEAFE ; + .dw 0xDAE1 ; + .dw 0xEAFF ; + .dw 0xAD1F ; + .dw 0xEB00 ; + .dw 0x7B07 ; + .dw 0xEB01 ; + .dw 0x8D3 ; + .dw 0xEB02 ; + .dw 0x6315 ; + .dw 0xEB03 ; + .dw 0x803 ; + .dw 0xEB04 ; + .dw 0xFFB ; + .dw 0xEB05 ; + .dw 0x9EF5 ; + .dw 0xEB06 ; + .dw 0x642B ; + .dw 0xEB07 ; + .dw 0x6BD5 ; + .dw 0xEB08 ; + .dw 0xE929 ; + .dw 0xEB09 ; + .dw 0x7107 ; + .dw 0xEB0A ; + .dw 0x8871 ; + .dw 0xEB0B ; + .dw 0x58F ; + .dw 0xEB0C ; + .dw 0xA56D ; + .dw 0xEB0D ; + .dw 0xB695 ; + .dw 0xEB0E ; + .dw 0xEC0F ; + .dw 0xEB0F ; + .dw 0xC0CD ; + .dw 0xEB10 ; + .dw 0x6CE3 ; + .dw 0xEB11 ; + .dw 0x5FF3 ; + .dw 0xEB12 ; + .dw 0x2123 ; + .dw 0xEB13 ; + .dw 0x55F9 ; + .dw 0xEB14 ; + .dw 0xEAB ; + .dw 0xEB15 ; + .dw 0x9B33 ; + .dw 0xEB16 ; + .dw 0x5D4D ; + .dw 0xEB17 ; + .dw 0x40D ; + .dw 0xEB18 ; + .dw 0x2451 ; + .dw 0xEB19 ; + .dw 0xB09F ; + .dw 0xEB1A ; + .dw 0xE8D1 ; + .dw 0xEB1B ; + .dw 0x2DC1 ; + .dw 0xEB1C ; + .dw 0x129B ; + .dw 0xEB1D ; + .dw 0x2EB5 ; + .dw 0xEB1E ; + .dw 0x6731 ; + .dw 0xEB1F ; + .dw 0x924D ; + .dw 0xEB20 ; + .dw 0x3FE3 ; + .dw 0xEB21 ; + .dw 0xDD91 ; + .dw 0xEB22 ; + .dw 0x113D ; + .dw 0xEB23 ; + .dw 0x599D ; + .dw 0xEB24 ; + .dw 0x57F7 ; + .dw 0xEB25 ; + .dw 0x71F7 ; + .dw 0xEB26 ; + .dw 0x78AD ; + .dw 0xEB27 ; + .dw 0xAC03 ; + .dw 0xEB28 ; + .dw 0xF563 ; + .dw 0xEB29 ; + .dw 0x77BF ; + .dw 0xEB2A ; + .dw 0xED3B ; + .dw 0xEB2B ; + .dw 0xD7D ; + .dw 0xEB2C ; + .dw 0x8855 ; + .dw 0xEB2D ; + .dw 0x6BD1 ; + .dw 0xEB2E ; + .dw 0x1B3D ; + .dw 0xEB2F ; + .dw 0x345D ; + .dw 0xEB30 ; + .dw 0xD2EF ; + .dw 0xEB31 ; + .dw 0x7D9D ; + .dw 0xEB32 ; + .dw 0xFBB9 ; + .dw 0xEB33 ; + .dw 0x938B ; + .dw 0xEB34 ; + .dw 0xD321 ; + .dw 0xEB35 ; + .dw 0xF011 ; + .dw 0xEB36 ; + .dw 0xAE01 ; + .dw 0xEB37 ; + .dw 0x503B ; + .dw 0xEB38 ; + .dw 0x7201 ; + .dw 0xEB39 ; + .dw 0x9215 ; + .dw 0xEB3A ; + .dw 0x52C1 ; + .dw 0xEB3B ; + .dw 0xDB23 ; + .dw 0xEB3C ; + .dw 0xD0A1 ; + .dw 0xEB3D ; + .dw 0x467B ; + .dw 0xEB3E ; + .dw 0x80A7 ; + .dw 0xEB3F ; + .dw 0xE539 ; + .dw 0xEB40 ; + .dw 0x8A6B ; + .dw 0xEB41 ; + .dw 0x1385 ; + .dw 0xEB42 ; + .dw 0x6A6F ; + .dw 0xEB43 ; + .dw 0xE7E1 ; + .dw 0xEB44 ; + .dw 0xC4F1 ; + .dw 0xEB45 ; + .dw 0xB1CF ; + .dw 0xEB46 ; + .dw 0x4E7F ; + .dw 0xEB47 ; + .dw 0xF8AD ; + .dw 0xEB48 ; + .dw 0x6553 ; + .dw 0xEB49 ; + .dw 0x12CB ; + .dw 0xEB4A ; + .dw 0x47FB ; + .dw 0xEB4B ; + .dw 0x2091 ; + .dw 0xEB4C ; + .dw 0x4307 ; + .dw 0xEB4D ; + .dw 0xD6C1 ; + .dw 0xEB4E ; + .dw 0x1967 ; + .dw 0xEB4F ; + .dw 0xEEA1 ; + .dw 0xEB50 ; + .dw 0xB03D ; + .dw 0xEB51 ; + .dw 0x2A37 ; + .dw 0xEB52 ; + .dw 0x8B3 ; + .dw 0xEB53 ; + .dw 0x7E3D ; + .dw 0xEB54 ; + .dw 0x2FAF ; + .dw 0xEB55 ; + .dw 0x2FD ; + .dw 0xEB56 ; + .dw 0x64DD ; + .dw 0xEB57 ; + .dw 0xA8D9 ; + .dw 0xEB58 ; + .dw 0xAFFF ; + .dw 0xEB59 ; + .dw 0x3495 ; + .dw 0xEB5A ; + .dw 0xCCFF ; + .dw 0xEB5B ; + .dw 0x9B25 ; + .dw 0xEB5C ; + .dw 0x248D ; + .dw 0xEB5D ; + .dw 0x542D ; + .dw 0xEB5E ; + .dw 0xD0F1 ; + .dw 0xEB5F ; + .dw 0x85D1 ; + .dw 0xEB60 ; + .dw 0xD3CD ; + .dw 0xEB61 ; + .dw 0xE423 ; + .dw 0xEB62 ; + .dw 0x35D ; + .dw 0xEB63 ; + .dw 0xA1BF ; + .dw 0xEB64 ; + .dw 0x331F ; + .dw 0xEB65 ; + .dw 0xBEED ; + .dw 0xEB66 ; + .dw 0x1551 ; + .dw 0xEB67 ; + .dw 0x3FBD ; + .dw 0xEB68 ; + .dw 0xA82B ; + .dw 0xEB69 ; + .dw 0x399B ; + .dw 0xEB6A ; + .dw 0x1361 ; + .dw 0xEB6B ; + .dw 0x1BBD ; + .dw 0xEB6C ; + .dw 0x7B9 ; + .dw 0xEB6D ; + .dw 0xF5D1 ; + .dw 0xEB6E ; + .dw 0x5C3D ; + .dw 0xEB6F ; + .dw 0xAB89 ; + .dw 0xEB70 ; + .dw 0x29FF ; + .dw 0xEB71 ; + .dw 0xDB33 ; + .dw 0xEB72 ; + .dw 0x68BF ; + .dw 0xEB73 ; + .dw 0xA105 ; + .dw 0xEB74 ; + .dw 0x6C87 ; + .dw 0xEB75 ; + .dw 0x3069 ; + .dw 0xEB76 ; + .dw 0xFD91 ; + .dw 0xEB77 ; + .dw 0x57D9 ; + .dw 0xEB78 ; + .dw 0x797D ; + .dw 0xEB79 ; + .dw 0x4B91 ; + .dw 0xEB7A ; + .dw 0xDE3B ; + .dw 0xEB7B ; + .dw 0x66B7 ; + .dw 0xEB7C ; + .dw 0x2C8F ; + .dw 0xEB7D ; + .dw 0xD239 ; + .dw 0xEB7E ; + .dw 0x99BF ; + .dw 0xEB7F ; + .dw 0xC07 ; + .dw 0xEB80 ; + .dw 0xED3B ; + .dw 0xEB81 ; + .dw 0xD7 ; + .dw 0xEB82 ; + .dw 0x88B3 ; + .dw 0xEB83 ; + .dw 0xAE29 ; + .dw 0xEB84 ; + .dw 0x56AD ; + .dw 0xEB85 ; + .dw 0xF1BF ; + .dw 0xEB86 ; + .dw 0x94D3 ; + .dw 0xEB87 ; + .dw 0x2727 ; + .dw 0xEB88 ; + .dw 0x851B ; + .dw 0xEB89 ; + .dw 0x5B9F ; + .dw 0xEB8A ; + .dw 0xE21F ; + .dw 0xEB8B ; + .dw 0x13EF ; + .dw 0xEB8C ; + .dw 0xE097 ; + .dw 0xEB8D ; + .dw 0xBF73 ; + .dw 0xEB8E ; + .dw 0xF16F ; + .dw 0xEB8F ; + .dw 0xDF07 ; + .dw 0xEB90 ; + .dw 0xBD65 ; + .dw 0xEB91 ; + .dw 0x7DFD ; + .dw 0xEB92 ; + .dw 0x548D ; + .dw 0xEB93 ; + .dw 0xBECD ; + .dw 0xEB94 ; + .dw 0xA9D7 ; + .dw 0xEB95 ; + .dw 0xCCC1 ; + .dw 0xEB96 ; + .dw 0x8BCD ; + .dw 0xEB97 ; + .dw 0x5F29 ; + .dw 0xEB98 ; + .dw 0xC1AB ; + .dw 0xEB99 ; + .dw 0x279 ; + .dw 0xEB9A ; + .dw 0x2525 ; + .dw 0xEB9B ; + .dw 0x6EC5 ; + .dw 0xEB9C ; + .dw 0xDED5 ; + .dw 0xEB9D ; + .dw 0x330D ; + .dw 0xEB9E ; + .dw 0xB4C3 ; + .dw 0xEB9F ; + .dw 0xC7C9 ; + .dw 0xEBA0 ; + .dw 0xFFE3 ; + .dw 0xEBA1 ; + .dw 0x9313 ; + .dw 0xEBA2 ; + .dw 0xBF25 ; + .dw 0xEBA3 ; + .dw 0x6C0F ; + .dw 0xEBA4 ; + .dw 0xBBCD ; + .dw 0xEBA5 ; + .dw 0x9AB9 ; + .dw 0xEBA6 ; + .dw 0x2CB7 ; + .dw 0xEBA7 ; + .dw 0xCDB ; + .dw 0xEBA8 ; + .dw 0x1B53 ; + .dw 0xEBA9 ; + .dw 0x6047 ; + .dw 0xEBAA ; + .dw 0x5EE3 ; + .dw 0xEBAB ; + .dw 0x5619 ; + .dw 0xEBAC ; + .dw 0xAFD3 ; + .dw 0xEBAD ; + .dw 0x2217 ; + .dw 0xEBAE ; + .dw 0x7EAF ; + .dw 0xEBAF ; + .dw 0xB50B ; + .dw 0xEBB0 ; + .dw 0x3F9D ; + .dw 0xEBB1 ; + .dw 0x7807 ; + .dw 0xEBB2 ; + .dw 0x1CCF ; + .dw 0xEBB3 ; + .dw 0xD28B ; + .dw 0xEBB4 ; + .dw 0xDFD3 ; + .dw 0xEBB5 ; + .dw 0x2477 ; + .dw 0xEBB6 ; + .dw 0xBB43 ; + .dw 0xEBB7 ; + .dw 0x78BB ; + .dw 0xEBB8 ; + .dw 0xD3B9 ; + .dw 0xEBB9 ; + .dw 0xFCBD ; + .dw 0xEBBA ; + .dw 0x586F ; + .dw 0xEBBB ; + .dw 0x1C45 ; + .dw 0xEBBC ; + .dw 0x993 ; + .dw 0xEBBD ; + .dw 0xE11D ; + .dw 0xEBBE ; + .dw 0x93A9 ; + .dw 0xEBBF ; + .dw 0xC109 ; + .dw 0xEBC0 ; + .dw 0x8CF7 ; + .dw 0xEBC1 ; + .dw 0x3C47 ; + .dw 0xEBC2 ; + .dw 0x8361 ; + .dw 0xEBC3 ; + .dw 0x725F ; + .dw 0xEBC4 ; + .dw 0xC6AF ; + .dw 0xEBC5 ; + .dw 0x249 ; + .dw 0xEBC6 ; + .dw 0xD4AB ; + .dw 0xEBC7 ; + .dw 0x6C7 ; + .dw 0xEBC8 ; + .dw 0xE201 ; + .dw 0xEBC9 ; + .dw 0xA703 ; + .dw 0xEBCA ; + .dw 0x4C5D ; + .dw 0xEBCB ; + .dw 0x6729 ; + .dw 0xEBCC ; + .dw 0x2F9B ; + .dw 0xEBCD ; + .dw 0x42D ; + .dw 0xEBCE ; + .dw 0x41A9 ; + .dw 0xEBCF ; + .dw 0x1183 ; + .dw 0xEBD0 ; + .dw 0xDDD9 ; + .dw 0xEBD1 ; + .dw 0xA6C1 ; + .dw 0xEBD2 ; + .dw 0x2A31 ; + .dw 0xEBD3 ; + .dw 0xF29 ; + .dw 0xEBD4 ; + .dw 0xDEA7 ; + .dw 0xEBD5 ; + .dw 0x7BFB ; + .dw 0xEBD6 ; + .dw 0xCFA1 ; + .dw 0xEBD7 ; + .dw 0x167D ; + .dw 0xEBD8 ; + .dw 0x52D5 ; + .dw 0xEBD9 ; + .dw 0x55CB ; + .dw 0xEBDA ; + .dw 0x46C5 ; + .dw 0xEBDB ; + .dw 0x1021 ; + .dw 0xEBDC ; + .dw 0x52F3 ; + .dw 0xEBDD ; + .dw 0x3ED7 ; + .dw 0xEBDE ; + .dw 0x4025 ; + .dw 0xEBDF ; + .dw 0xB7B5 ; + .dw 0xEBE0 ; + .dw 0x6DA7 ; + .dw 0xEBE1 ; + .dw 0x15E3 ; + .dw 0xEBE2 ; + .dw 0xCA17 ; + .dw 0xEBE3 ; + .dw 0x9009 ; + .dw 0xEBE4 ; + .dw 0xB381 ; + .dw 0xEBE5 ; + .dw 0x68DD ; + .dw 0xEBE6 ; + .dw 0x1C5F ; + .dw 0xEBE7 ; + .dw 0xE2DB ; + .dw 0xEBE8 ; + .dw 0xA857 ; + .dw 0xEBE9 ; + .dw 0x743 ; + .dw 0xEBEA ; + .dw 0x853D ; + .dw 0xEBEB ; + .dw 0x40F ; + .dw 0xEBEC ; + .dw 0xF221 ; + .dw 0xEBED ; + .dw 0x4425 ; + .dw 0xEBEE ; + .dw 0x1011 ; + .dw 0xEBEF ; + .dw 0x905F ; + .dw 0xEBF0 ; + .dw 0x1D49 ; + .dw 0xEBF1 ; + .dw 0x5F9B ; + .dw 0xEBF2 ; + .dw 0xFD67 ; + .dw 0xEBF3 ; + .dw 0xDF9B ; + .dw 0xEBF4 ; + .dw 0x4E83 ; + .dw 0xEBF5 ; + .dw 0xFBD ; + .dw 0xEBF6 ; + .dw 0xA497 ; + .dw 0xEBF7 ; + .dw 0x6261 ; + .dw 0xEBF8 ; + .dw 0x3A31 ; + .dw 0xEBF9 ; + .dw 0xA117 ; + .dw 0xEBFA ; + .dw 0xD6DB ; + .dw 0xEBFB ; + .dw 0x234D ; + .dw 0xEBFC ; + .dw 0x392B ; + .dw 0xEBFD ; + .dw 0xA6A9 ; + .dw 0xEBFE ; + .dw 0x5BE5 ; + .dw 0xEBFF ; + .dw 0x23BD ; + .dw 0xEC00 ; + .dw 0xD323 ; + .dw 0xEC01 ; + .dw 0xB157 ; + .dw 0xEC02 ; + .dw 0x9FF7 ; + .dw 0xEC03 ; + .dw 0xCBFF ; + .dw 0xEC04 ; + .dw 0x9675 ; + .dw 0xEC05 ; + .dw 0x6E9 ; + .dw 0xEC06 ; + .dw 0x2B83 ; + .dw 0xEC07 ; + .dw 0x2709 ; + .dw 0xEC08 ; + .dw 0x9585 ; + .dw 0xEC09 ; + .dw 0xD077 ; + .dw 0xEC0A ; + .dw 0xFC33 ; + .dw 0xEC0B ; + .dw 0x21BD ; + .dw 0xEC0C ; + .dw 0x6195 ; + .dw 0xEC0D ; + .dw 0xB86F ; + .dw 0xEC0E ; + .dw 0x5795 ; + .dw 0xEC0F ; + .dw 0x8591 ; + .dw 0xEC10 ; + .dw 0xDB1B ; + .dw 0xEC11 ; + .dw 0x7005 ; + .dw 0xEC12 ; + .dw 0x2F1F ; + .dw 0xEC13 ; + .dw 0xE6D1 ; + .dw 0xEC14 ; + .dw 0xAF9B ; + .dw 0xEC15 ; + .dw 0x142D ; + .dw 0xEC16 ; + .dw 0xADD5 ; + .dw 0xEC17 ; + .dw 0x3E55 ; + .dw 0xEC18 ; + .dw 0xDCFB ; + .dw 0xEC19 ; + .dw 0xEA0F ; + .dw 0xEC1A ; + .dw 0x75F ; + .dw 0xEC1B ; + .dw 0x66B9 ; + .dw 0xEC1C ; + .dw 0x1267 ; + .dw 0xEC1D ; + .dw 0x6B05 ; + .dw 0xEC1E ; + .dw 0x2099 ; + .dw 0xEC1F ; + .dw 0x3513 ; + .dw 0xEC20 ; + .dw 0x4699 ; + .dw 0xEC21 ; + .dw 0x1813 ; + .dw 0xEC22 ; + .dw 0x29B3 ; + .dw 0xEC23 ; + .dw 0x652F ; + .dw 0xEC24 ; + .dw 0x5BB9 ; + .dw 0xEC25 ; + .dw 0xCD9 ; + .dw 0xEC26 ; + .dw 0xC1C7 ; + .dw 0xEC27 ; + .dw 0x1141 ; + .dw 0xEC28 ; + .dw 0x28BB ; + .dw 0xEC29 ; + .dw 0xCA0D ; + .dw 0xEC2A ; + .dw 0xBBF1 ; + .dw 0xEC2B ; + .dw 0xED21 ; + .dw 0xEC2C ; + .dw 0xC027 ; + .dw 0xEC2D ; + .dw 0x2F7B ; + .dw 0xEC2E ; + .dw 0x1DE5 ; + .dw 0xEC2F ; + .dw 0xFD07 ; + .dw 0xEC30 ; + .dw 0x4C81 ; + .dw 0xEC31 ; + .dw 0x1D6F ; + .dw 0xEC32 ; + .dw 0x7009 ; + .dw 0xEC33 ; + .dw 0xFFB9 ; + .dw 0xEC34 ; + .dw 0x5A19 ; + .dw 0xEC35 ; + .dw 0xB5BB ; + .dw 0xEC36 ; + .dw 0xF70D ; + .dw 0xEC37 ; + .dw 0x4449 ; + .dw 0xEC38 ; + .dw 0xE667 ; + .dw 0xEC39 ; + .dw 0xB423 ; + .dw 0xEC3A ; + .dw 0xEF01 ; + .dw 0xEC3B ; + .dw 0x2353 ; + .dw 0xEC3C ; + .dw 0xCD9 ; + .dw 0xEC3D ; + .dw 0xD65D ; + .dw 0xEC3E ; + .dw 0x5FF1 ; + .dw 0xEC3F ; + .dw 0xD3A7 ; + .dw 0xEC40 ; + .dw 0xA93B ; + .dw 0xEC41 ; + .dw 0xCB87 ; + .dw 0xEC42 ; + .dw 0xA3F7 ; + .dw 0xEC43 ; + .dw 0xD28B ; + .dw 0xEC44 ; + .dw 0xC781 ; + .dw 0xEC45 ; + .dw 0xA31F ; + .dw 0xEC46 ; + .dw 0x36DD ; + .dw 0xEC47 ; + .dw 0x976F ; + .dw 0xEC48 ; + .dw 0x3927 ; + .dw 0xEC49 ; + .dw 0x3379 ; + .dw 0xEC4A ; + .dw 0xE725 ; + .dw 0xEC4B ; + .dw 0xCB2D ; + .dw 0xEC4C ; + .dw 0x2805 ; + .dw 0xEC4D ; + .dw 0x6FB9 ; + .dw 0xEC4E ; + .dw 0xB1 ; + .dw 0xEC4F ; + .dw 0xBAB1 ; + .dw 0xEC50 ; + .dw 0xFEAB ; + .dw 0xEC51 ; + .dw 0x2549 ; + .dw 0xEC52 ; + .dw 0x88D5 ; + .dw 0xEC53 ; + .dw 0x3D43 ; + .dw 0xEC54 ; + .dw 0x7E33 ; + .dw 0xEC55 ; + .dw 0x18D5 ; + .dw 0xEC56 ; + .dw 0x23EB ; + .dw 0xEC57 ; + .dw 0xC62F ; + .dw 0xEC58 ; + .dw 0x59A1 ; + .dw 0xEC59 ; + .dw 0xFAC1 ; + .dw 0xEC5A ; + .dw 0xBC71 ; + .dw 0xEC5B ; + .dw 0xDA0D ; + .dw 0xEC5C ; + .dw 0x2EB1 ; + .dw 0xEC5D ; + .dw 0x2B1D ; + .dw 0xEC5E ; + .dw 0x839D ; + .dw 0xEC5F ; + .dw 0x9F67 ; + .dw 0xEC60 ; + .dw 0x3437 ; + .dw 0xEC61 ; + .dw 0xC523 ; + .dw 0xEC62 ; + .dw 0x6377 ; + .dw 0xEC63 ; + .dw 0xC301 ; + .dw 0xEC64 ; + .dw 0x75F9 ; + .dw 0xEC65 ; + .dw 0xEA2B ; + .dw 0xEC66 ; + .dw 0x7A71 ; + .dw 0xEC67 ; + .dw 0x6789 ; + .dw 0xEC68 ; + .dw 0xF5F9 ; + .dw 0xEC69 ; + .dw 0xC429 ; + .dw 0xEC6A ; + .dw 0xB87F ; + .dw 0xEC6B ; + .dw 0x58CF ; + .dw 0xEC6C ; + .dw 0x8B61 ; + .dw 0xEC6D ; + .dw 0x3799 ; + .dw 0xEC6E ; + .dw 0x35AB ; + .dw 0xEC6F ; + .dw 0x3A81 ; + .dw 0xEC70 ; + .dw 0xD6C7 ; + .dw 0xEC71 ; + .dw 0xBD03 ; + .dw 0xEC72 ; + .dw 0x5A35 ; + .dw 0xEC73 ; + .dw 0xEA61 ; + .dw 0xEC74 ; + .dw 0x2415 ; + .dw 0xEC75 ; + .dw 0x59EF ; + .dw 0xEC76 ; + .dw 0x7023 ; + .dw 0xEC77 ; + .dw 0xCDF7 ; + .dw 0xEC78 ; + .dw 0x91D9 ; + .dw 0xEC79 ; + .dw 0x315D ; + .dw 0xEC7A ; + .dw 0xB661 ; + .dw 0xEC7B ; + .dw 0x43D3 ; + .dw 0xEC7C ; + .dw 0x561D ; + .dw 0xEC7D ; + .dw 0xA3B7 ; + .dw 0xEC7E ; + .dw 0x8D4F ; + .dw 0xEC7F ; + .dw 0xF043 ; + .dw 0xEC80 ; + .dw 0x78C1 ; + .dw 0xEC81 ; + .dw 0x7657 ; + .dw 0xEC82 ; + .dw 0xD4E1 ; + .dw 0xEC83 ; + .dw 0x1D81 ; + .dw 0xEC84 ; + .dw 0xDB51 ; + .dw 0xEC85 ; + .dw 0xFA6F ; + .dw 0xEC86 ; + .dw 0x1437 ; + .dw 0xEC87 ; + .dw 0xE779 ; + .dw 0xEC88 ; + .dw 0xE665 ; + .dw 0xEC89 ; + .dw 0xAB8B ; + .dw 0xEC8A ; + .dw 0x82AF ; + .dw 0xEC8B ; + .dw 0x6AF9 ; + .dw 0xEC8C ; + .dw 0xB46B ; + .dw 0xEC8D ; + .dw 0x3D89 ; + .dw 0xEC8E ; + .dw 0x8A81 ; + .dw 0xEC8F ; + .dw 0xB067 ; + .dw 0xEC90 ; + .dw 0x1207 ; + .dw 0xEC91 ; + .dw 0x920D ; + .dw 0xEC92 ; + .dw 0xDCD5 ; + .dw 0xEC93 ; + .dw 0x8A01 ; + .dw 0xEC94 ; + .dw 0x2BF3 ; + .dw 0xEC95 ; + .dw 0x8D77 ; + .dw 0xEC96 ; + .dw 0xAF63 ; + .dw 0xEC97 ; + .dw 0x1D8F ; + .dw 0xEC98 ; + .dw 0x4243 ; + .dw 0xEC99 ; + .dw 0x4363 ; + .dw 0xEC9A ; + .dw 0x3B7F ; + .dw 0xEC9B ; + .dw 0x519B ; + .dw 0xEC9C ; + .dw 0x394F ; + .dw 0xEC9D ; + .dw 0x729B ; + .dw 0xEC9E ; + .dw 0x16B5 ; + .dw 0xEC9F ; + .dw 0xD62B ; + .dw 0xECA0 ; + .dw 0x6005 ; + .dw 0xECA1 ; + .dw 0xC893 ; + .dw 0xECA2 ; + .dw 0x7CE7 ; + .dw 0xECA3 ; + .dw 0xFD ; + .dw 0xECA4 ; + .dw 0x43BD ; + .dw 0xECA5 ; + .dw 0xE457 ; + .dw 0xECA6 ; + .dw 0x23DD ; + .dw 0xECA7 ; + .dw 0x3533 ; + .dw 0xECA8 ; + .dw 0xE997 ; + .dw 0xECA9 ; + .dw 0x9113 ; + .dw 0xECAA ; + .dw 0xB065 ; + .dw 0xECAB ; + .dw 0xE99 ; + .dw 0xECAC ; + .dw 0x4551 ; + .dw 0xECAD ; + .dw 0x2FFD ; + .dw 0xECAE ; + .dw 0x64E1 ; + .dw 0xECAF ; + .dw 0x851 ; + .dw 0xECB0 ; + .dw 0x459B ; + .dw 0xECB1 ; + .dw 0xC9D5 ; + .dw 0xECB2 ; + .dw 0x2169 ; + .dw 0xECB3 ; + .dw 0xD715 ; + .dw 0xECB4 ; + .dw 0x4DF7 ; + .dw 0xECB5 ; + .dw 0xBFDB ; + .dw 0xECB6 ; + .dw 0x4D5B ; + .dw 0xECB7 ; + .dw 0x2EE7 ; + .dw 0xECB8 ; + .dw 0x760B ; + .dw 0xECB9 ; + .dw 0x9447 ; + .dw 0xECBA ; + .dw 0xC279 ; + .dw 0xECBB ; + .dw 0x2C4F ; + .dw 0xECBC ; + .dw 0x6675 ; + .dw 0xECBD ; + .dw 0xC23B ; + .dw 0xECBE ; + .dw 0x517F ; + .dw 0xECBF ; + .dw 0x1913 ; + .dw 0xECC0 ; + .dw 0x2B33 ; + .dw 0xECC1 ; + .dw 0x1D45 ; + .dw 0xECC2 ; + .dw 0xF835 ; + .dw 0xECC3 ; + .dw 0xC463 ; + .dw 0xECC4 ; + .dw 0xD369 ; + .dw 0xECC5 ; + .dw 0xB055 ; + .dw 0xECC6 ; + .dw 0x6115 ; + .dw 0xECC7 ; + .dw 0x26A7 ; + .dw 0xECC8 ; + .dw 0x36C1 ; + .dw 0xECC9 ; + .dw 0x942D ; + .dw 0xECCA ; + .dw 0xC453 ; + .dw 0xECCB ; + .dw 0x889F ; + .dw 0xECCC ; + .dw 0xB845 ; + .dw 0xECCD ; + .dw 0xB561 ; + .dw 0xECCE ; + .dw 0xC281 ; + .dw 0xECCF ; + .dw 0xE62F ; + .dw 0xECD0 ; + .dw 0x5EB3 ; + .dw 0xECD1 ; + .dw 0x1CF ; + .dw 0xECD2 ; + .dw 0x509F ; + .dw 0xECD3 ; + .dw 0xC48B ; + .dw 0xECD4 ; + .dw 0x1A57 ; + .dw 0xECD5 ; + .dw 0xF58F ; + .dw 0xECD6 ; + .dw 0x4DBD ; + .dw 0xECD7 ; + .dw 0x33F1 ; + .dw 0xECD8 ; + .dw 0x9061 ; + .dw 0xECD9 ; + .dw 0xFF75 ; + .dw 0xECDA ; + .dw 0xDA05 ; + .dw 0xECDB ; + .dw 0x34E5 ; + .dw 0xECDC ; + .dw 0x43C3 ; + .dw 0xECDD ; + .dw 0xB503 ; + .dw 0xECDE ; + .dw 0x75D ; + .dw 0xECDF ; + .dw 0x38E5 ; + .dw 0xECE0 ; + .dw 0x737F ; + .dw 0xECE1 ; + .dw 0x4DE1 ; + .dw 0xECE2 ; + .dw 0xFB7F ; + .dw 0xECE3 ; + .dw 0xF6A5 ; + .dw 0xECE4 ; + .dw 0x8687 ; + .dw 0xECE5 ; + .dw 0x5ED9 ; + .dw 0xECE6 ; + .dw 0x1B8B ; + .dw 0xECE7 ; + .dw 0x49C3 ; + .dw 0xECE8 ; + .dw 0x5D11 ; + .dw 0xECE9 ; + .dw 0x4C4B ; + .dw 0xECEA ; + .dw 0x5925 ; + .dw 0xECEB ; + .dw 0x55FD ; + .dw 0xECEC ; + .dw 0x5F77 ; + .dw 0xECED ; + .dw 0x6C29 ; + .dw 0xECEE ; + .dw 0x390B ; + .dw 0xECEF ; + .dw 0xA5F3 ; + .dw 0xECF0 ; + .dw 0xA27D ; + .dw 0xECF1 ; + .dw 0x4F69 ; + .dw 0xECF2 ; + .dw 0xAB29 ; + .dw 0xECF3 ; + .dw 0x7D53 ; + .dw 0xECF4 ; + .dw 0xF93F ; + .dw 0xECF5 ; + .dw 0x2B01 ; + .dw 0xECF6 ; + .dw 0x4C35 ; + .dw 0xECF7 ; + .dw 0x169B ; + .dw 0xECF8 ; + .dw 0x4C79 ; + .dw 0xECF9 ; + .dw 0xD85F ; + .dw 0xECFA ; + .dw 0x28CD ; + .dw 0xECFB ; + .dw 0x447 ; + .dw 0xECFC ; + .dw 0xF65 ; + .dw 0xECFD ; + .dw 0x6565 ; + .dw 0xECFE ; + .dw 0x99FF ; + .dw 0xECFF ; + .dw 0x6D95 ; + .dw 0xED00 ; + .dw 0x2A15 ; + .dw 0xED01 ; + .dw 0xABD3 ; + .dw 0xED02 ; + .dw 0x5373 ; + .dw 0xED03 ; + .dw 0x5EB1 ; + .dw 0xED04 ; + .dw 0x3145 ; + .dw 0xED05 ; + .dw 0xE853 ; + .dw 0xED06 ; + .dw 0x3AF3 ; + .dw 0xED07 ; + .dw 0xE477 ; + .dw 0xED08 ; + .dw 0x43BB ; + .dw 0xED09 ; + .dw 0xC8DF ; + .dw 0xED0A ; + .dw 0x218F ; + .dw 0xED0B ; + .dw 0x2BA1 ; + .dw 0xED0C ; + .dw 0x6515 ; + .dw 0xED0D ; + .dw 0xEAC1 ; + .dw 0xED0E ; + .dw 0xF631 ; + .dw 0xED0F ; + .dw 0x5B8B ; + .dw 0xED10 ; + .dw 0xAE2B ; + .dw 0xED11 ; + .dw 0x4011 ; + .dw 0xED12 ; + .dw 0x89B3 ; + .dw 0xED13 ; + .dw 0x645F ; + .dw 0xED14 ; + .dw 0x2AE1 ; + .dw 0xED15 ; + .dw 0x549F ; + .dw 0xED16 ; + .dw 0x7C77 ; + .dw 0xED17 ; + .dw 0x78D5 ; + .dw 0xED18 ; + .dw 0xBD7F ; + .dw 0xED19 ; + .dw 0xEA75 ; + .dw 0xED1A ; + .dw 0x6D83 ; + .dw 0xED1B ; + .dw 0x6B69 ; + .dw 0xED1C ; + .dw 0xDF8D ; + .dw 0xED1D ; + .dw 0xE5CF ; + .dw 0xED1E ; + .dw 0x317 ; + .dw 0xED1F ; + .dw 0xA713 ; + .dw 0xED20 ; + .dw 0x9825 ; + .dw 0xED21 ; + .dw 0x8F ; + .dw 0xED22 ; + .dw 0xE4C1 ; + .dw 0xED23 ; + .dw 0xFB79 ; + .dw 0xED24 ; + .dw 0x7FD5 ; + .dw 0xED25 ; + .dw 0x3D33 ; + .dw 0xED26 ; + .dw 0x3EFB ; + .dw 0xED27 ; + .dw 0xF4B5 ; + .dw 0xED28 ; + .dw 0x29EB ; + .dw 0xED29 ; + .dw 0x9155 ; + .dw 0xED2A ; + .dw 0xE83F ; + .dw 0xED2B ; + .dw 0xF67D ; + .dw 0xED2C ; + .dw 0xCB51 ; + .dw 0xED2D ; + .dw 0xBF9D ; + .dw 0xED2E ; + .dw 0xBFA5 ; + .dw 0xED2F ; + .dw 0xD2E9 ; + .dw 0xED30 ; + .dw 0x76EB ; + .dw 0xED31 ; + .dw 0xD939 ; + .dw 0xED32 ; + .dw 0x5CF1 ; + .dw 0xED33 ; + .dw 0x149F ; + .dw 0xED34 ; + .dw 0xC76B ; + .dw 0xED35 ; + .dw 0x5EDB ; + .dw 0xED36 ; + .dw 0xAA31 ; + .dw 0xED37 ; + .dw 0xB491 ; + .dw 0xED38 ; + .dw 0x4EA3 ; + .dw 0xED39 ; + .dw 0x7929 ; + .dw 0xED3A ; + .dw 0x7ED9 ; + .dw 0xED3B ; + .dw 0x733B ; + .dw 0xED3C ; + .dw 0xA269 ; + .dw 0xED3D ; + .dw 0x40B5 ; + .dw 0xED3E ; + .dw 0xD453 ; + .dw 0xED3F ; + .dw 0x8D4D ; + .dw 0xED40 ; + .dw 0x5EE3 ; + .dw 0xED41 ; + .dw 0x8D81 ; + .dw 0xED42 ; + .dw 0xAC19 ; + .dw 0xED43 ; + .dw 0x3EB ; + .dw 0xED44 ; + .dw 0xF667 ; + .dw 0xED45 ; + .dw 0x45E9 ; + .dw 0xED46 ; + .dw 0x3F53 ; + .dw 0xED47 ; + .dw 0x306B ; + .dw 0xED48 ; + .dw 0xA6D1 ; + .dw 0xED49 ; + .dw 0xA51F ; + .dw 0xED4A ; + .dw 0x8FE7 ; + .dw 0xED4B ; + .dw 0xDB7F ; + .dw 0xED4C ; + .dw 0x6C5B ; + .dw 0xED4D ; + .dw 0x7129 ; + .dw 0xED4E ; + .dw 0xF315 ; + .dw 0xED4F ; + .dw 0x8FFB ; + .dw 0xED50 ; + .dw 0x49F1 ; + .dw 0xED51 ; + .dw 0x9853 ; + .dw 0xED52 ; + .dw 0xAD8F ; + .dw 0xED53 ; + .dw 0x60FF ; + .dw 0xED54 ; + .dw 0xBF0F ; + .dw 0xED55 ; + .dw 0x2E27 ; + .dw 0xED56 ; + .dw 0x3913 ; + .dw 0xED57 ; + .dw 0xDBBF ; + .dw 0xED58 ; + .dw 0xC319 ; + .dw 0xED59 ; + .dw 0x3FE7 ; + .dw 0xED5A ; + .dw 0x4B7D ; + .dw 0xED5B ; + .dw 0x5CAB ; + .dw 0xED5C ; + .dw 0x1E2B ; + .dw 0xED5D ; + .dw 0x7885 ; + .dw 0xED5E ; + .dw 0x3761 ; + .dw 0xED5F ; + .dw 0x8033 ; + .dw 0xED60 ; + .dw 0x777B ; + .dw 0xED61 ; + .dw 0xC1B ; + .dw 0xED62 ; + .dw 0xBE2B ; + .dw 0xED63 ; + .dw 0xE6F9 ; + .dw 0xED64 ; + .dw 0xF12B ; + .dw 0xED65 ; + .dw 0xE2E3 ; + .dw 0xED66 ; + .dw 0xEBAB ; + .dw 0xED67 ; + .dw 0x58B ; + .dw 0xED68 ; + .dw 0xA99F ; + .dw 0xED69 ; + .dw 0x7BAD ; + .dw 0xED6A ; + .dw 0x1333 ; + .dw 0xED6B ; + .dw 0x3799 ; + .dw 0xED6C ; + .dw 0xFA61 ; + .dw 0xED6D ; + .dw 0x7DD7 ; + .dw 0xED6E ; + .dw 0x8631 ; + .dw 0xED6F ; + .dw 0xCEB1 ; + .dw 0xED70 ; + .dw 0xCC69 ; + .dw 0xED71 ; + .dw 0x72CB ; + .dw 0xED72 ; + .dw 0x1C41 ; + .dw 0xED73 ; + .dw 0x5475 ; + .dw 0xED74 ; + .dw 0xD9FD ; + .dw 0xED75 ; + .dw 0x9EEF ; + .dw 0xED76 ; + .dw 0x24CF ; + .dw 0xED77 ; + .dw 0xB84D ; + .dw 0xED78 ; + .dw 0x360D ; + .dw 0xED79 ; + .dw 0x7221 ; + .dw 0xED7A ; + .dw 0xDA1F ; + .dw 0xED7B ; + .dw 0xA0A9 ; + .dw 0xED7C ; + .dw 0xF103 ; + .dw 0xED7D ; + .dw 0x87AF ; + .dw 0xED7E ; + .dw 0xEDF7 ; + .dw 0xED7F ; + .dw 0x97B7 ; + .dw 0xED80 ; + .dw 0x331F ; + .dw 0xED81 ; + .dw 0xADCF ; + .dw 0xED82 ; + .dw 0x47A9 ; + .dw 0xED83 ; + .dw 0x4B91 ; + .dw 0xED84 ; + .dw 0xA44F ; + .dw 0xED85 ; + .dw 0xEC95 ; + .dw 0xED86 ; + .dw 0x8BB3 ; + .dw 0xED87 ; + .dw 0x9A03 ; + .dw 0xED88 ; + .dw 0x7985 ; + .dw 0xED89 ; + .dw 0x46F ; + .dw 0xED8A ; + .dw 0x84D7 ; + .dw 0xED8B ; + .dw 0x9FB9 ; + .dw 0xED8C ; + .dw 0xFF95 ; + .dw 0xED8D ; + .dw 0x5C17 ; + .dw 0xED8E ; + .dw 0x6A9 ; + .dw 0xED8F ; + .dw 0x82FD ; + .dw 0xED90 ; + .dw 0xFB83 ; + .dw 0xED91 ; + .dw 0xD613 ; + .dw 0xED92 ; + .dw 0x61B7 ; + .dw 0xED93 ; + .dw 0x31EB ; + .dw 0xED94 ; + .dw 0xB865 ; + .dw 0xED95 ; + .dw 0x85A5 ; + .dw 0xED96 ; + .dw 0x111 ; + .dw 0xED97 ; + .dw 0xCC2B ; + .dw 0xED98 ; + .dw 0x1AB1 ; + .dw 0xED99 ; + .dw 0xBB47 ; + .dw 0xED9A ; + .dw 0x496F ; + .dw 0xED9B ; + .dw 0xF027 ; + .dw 0xED9C ; + .dw 0x911F ; + .dw 0xED9D ; + .dw 0x60A1 ; + .dw 0xED9E ; + .dw 0x51BF ; + .dw 0xED9F ; + .dw 0xA3C7 ; + .dw 0xEDA0 ; + .dw 0x3AFD ; + .dw 0xEDA1 ; + .dw 0x1C09 ; + .dw 0xEDA2 ; + .dw 0x8D41 ; + .dw 0xEDA3 ; + .dw 0x10A3 ; + .dw 0xEDA4 ; + .dw 0x1C05 ; + .dw 0xEDA5 ; + .dw 0x336D ; + .dw 0xEDA6 ; + .dw 0xFF1D ; + .dw 0xEDA7 ; + .dw 0xCBC3 ; + .dw 0xEDA8 ; + .dw 0xB5B3 ; + .dw 0xEDA9 ; + .dw 0xA6D5 ; + .dw 0xEDAA ; + .dw 0xF7F ; + .dw 0xEDAB ; + .dw 0xE0D1 ; + .dw 0xEDAC ; + .dw 0xDE27 ; + .dw 0xEDAD ; + .dw 0x7A5B ; + .dw 0xEDAE ; + .dw 0x9A2D ; + .dw 0xEDAF ; + .dw 0x58CF ; + .dw 0xEDB0 ; + .dw 0x2C73 ; + .dw 0xEDB1 ; + .dw 0xA79B ; + .dw 0xEDB2 ; + .dw 0x4E9D ; + .dw 0xEDB3 ; + .dw 0x7457 ; + .dw 0xEDB4 ; + .dw 0xD275 ; + .dw 0xEDB5 ; + .dw 0xAEB9 ; + .dw 0xEDB6 ; + .dw 0xF98D ; + .dw 0xEDB7 ; + .dw 0x514B ; + .dw 0xEDB8 ; + .dw 0x3C33 ; + .dw 0xEDB9 ; + .dw 0x3EC9 ; + .dw 0xEDBA ; + .dw 0xD01D ; + .dw 0xEDBB ; + .dw 0x3413 ; + .dw 0xEDBC ; + .dw 0x4CB1 ; + .dw 0xEDBD ; + .dw 0xEDCF ; + .dw 0xEDBE ; + .dw 0x546B ; + .dw 0xEDBF ; + .dw 0x2C53 ; + .dw 0xEDC0 ; + .dw 0x9047 ; + .dw 0xEDC1 ; + .dw 0x783B ; + .dw 0xEDC2 ; + .dw 0xEBA3 ; + .dw 0xEDC3 ; + .dw 0x4D21 ; + .dw 0xEDC4 ; + .dw 0x3C7B ; + .dw 0xEDC5 ; + .dw 0x7FD9 ; + .dw 0xEDC6 ; + .dw 0xBD97 ; + .dw 0xEDC7 ; + .dw 0x30BD ; + .dw 0xEDC8 ; + .dw 0x5557 ; + .dw 0xEDC9 ; + .dw 0x424F ; + .dw 0xEDCA ; + .dw 0xF5DF ; + .dw 0xEDCB ; + .dw 0xFFCF ; + .dw 0xEDCC ; + .dw 0xD047 ; + .dw 0xEDCD ; + .dw 0x3F0F ; + .dw 0xEDCE ; + .dw 0xFE6F ; + .dw 0xEDCF ; + .dw 0xB415 ; + .dw 0xEDD0 ; + .dw 0xC65 ; + .dw 0xEDD1 ; + .dw 0x44D5 ; + .dw 0xEDD2 ; + .dw 0xCBA5 ; + .dw 0xEDD3 ; + .dw 0xCEA3 ; + .dw 0xEDD4 ; + .dw 0x785F ; + .dw 0xEDD5 ; + .dw 0xDE9B ; + .dw 0xEDD6 ; + .dw 0xD1F1 ; + .dw 0xEDD7 ; + .dw 0x399B ; + .dw 0xEDD8 ; + .dw 0xBDC5 ; + .dw 0xEDD9 ; + .dw 0x9815 ; + .dw 0xEDDA ; + .dw 0xBCDB ; + .dw 0xEDDB ; + .dw 0x8D5F ; + .dw 0xEDDC ; + .dw 0x49E9 ; + .dw 0xEDDD ; + .dw 0x11A7 ; + .dw 0xEDDE ; + .dw 0x7FAD ; + .dw 0xEDDF ; + .dw 0x714F ; + .dw 0xEDE0 ; + .dw 0x8C2D ; + .dw 0xEDE1 ; + .dw 0x5BD5 ; + .dw 0xEDE2 ; + .dw 0xD77F ; + .dw 0xEDE3 ; + .dw 0x4FF9 ; + .dw 0xEDE4 ; + .dw 0xC1E3 ; + .dw 0xEDE5 ; + .dw 0x924D ; + .dw 0xEDE6 ; + .dw 0xD6D1 ; + .dw 0xEDE7 ; + .dw 0x16E1 ; + .dw 0xEDE8 ; + .dw 0xA7A3 ; + .dw 0xEDE9 ; + .dw 0x2E4D ; + .dw 0xEDEA ; + .dw 0x92A7 ; + .dw 0xEDEB ; + .dw 0x39A3 ; + .dw 0xEDEC ; + .dw 0xE823 ; + .dw 0xEDED ; + .dw 0x8A5 ; + .dw 0xEDEE ; + .dw 0x891D ; + .dw 0xEDEF ; + .dw 0xB0BF ; + .dw 0xEDF0 ; + .dw 0xA089 ; + .dw 0xEDF1 ; + .dw 0x832D ; + .dw 0xEDF2 ; + .dw 0xD981 ; + .dw 0xEDF3 ; + .dw 0x2BC3 ; + .dw 0xEDF4 ; + .dw 0xD251 ; + .dw 0xEDF5 ; + .dw 0xD1BB ; + .dw 0xEDF6 ; + .dw 0xE5ED ; + .dw 0xEDF7 ; + .dw 0x2F0D ; + .dw 0xEDF8 ; + .dw 0x1A97 ; + .dw 0xEDF9 ; + .dw 0xDA9F ; + .dw 0xEDFA ; + .dw 0x7657 ; + .dw 0xEDFB ; + .dw 0x54F9 ; + .dw 0xEDFC ; + .dw 0x86F7 ; + .dw 0xEDFD ; + .dw 0xA697 ; + .dw 0xEDFE ; + .dw 0xF533 ; + .dw 0xEDFF ; + .dw 0x6AA5 ; + .dw 0xEE00 ; + .dw 0xDFDF ; + .dw 0xEE01 ; + .dw 0xD847 ; + .dw 0xEE02 ; + .dw 0xDD85 ; + .dw 0xEE03 ; + .dw 0xA01D ; + .dw 0xEE04 ; + .dw 0x406D ; + .dw 0xEE05 ; + .dw 0x2335 ; + .dw 0xEE06 ; + .dw 0xF27B ; + .dw 0xEE07 ; + .dw 0x841D ; + .dw 0xEE08 ; + .dw 0x53C7 ; + .dw 0xEE09 ; + .dw 0x3A3D ; + .dw 0xEE0A ; + .dw 0x5883 ; + .dw 0xEE0B ; + .dw 0x33F ; + .dw 0xEE0C ; + .dw 0xFED ; + .dw 0xEE0D ; + .dw 0x2D8D ; + .dw 0xEE0E ; + .dw 0x27E7 ; + .dw 0xEE0F ; + .dw 0x22BF ; + .dw 0xEE10 ; + .dw 0x4613 ; + .dw 0xEE11 ; + .dw 0xB015 ; + .dw 0xEE12 ; + .dw 0x90DF ; + .dw 0xEE13 ; + .dw 0xAEA7 ; + .dw 0xEE14 ; + .dw 0xE07F ; + .dw 0xEE15 ; + .dw 0x3C89 ; + .dw 0xEE16 ; + .dw 0x2931 ; + .dw 0xEE17 ; + .dw 0x938F ; + .dw 0xEE18 ; + .dw 0x25D9 ; + .dw 0xEE19 ; + .dw 0x91D5 ; + .dw 0xEE1A ; + .dw 0x7B41 ; + .dw 0xEE1B ; + .dw 0x1BD3 ; + .dw 0xEE1C ; + .dw 0xDA09 ; + .dw 0xEE1D ; + .dw 0x7F11 ; + .dw 0xEE1E ; + .dw 0x6EAD ; + .dw 0xEE1F ; + .dw 0xC849 ; + .dw 0xEE20 ; + .dw 0x948B ; + .dw 0xEE21 ; + .dw 0x7701 ; + .dw 0xEE22 ; + .dw 0xA265 ; + .dw 0xEE23 ; + .dw 0xFC7B ; + .dw 0xEE24 ; + .dw 0x2449 ; + .dw 0xEE25 ; + .dw 0xE305 ; + .dw 0xEE26 ; + .dw 0x5045 ; + .dw 0xEE27 ; + .dw 0x3661 ; + .dw 0xEE28 ; + .dw 0x58F3 ; + .dw 0xEE29 ; + .dw 0xAD93 ; + .dw 0xEE2A ; + .dw 0xD225 ; + .dw 0xEE2B ; + .dw 0x991 ; + .dw 0xEE2C ; + .dw 0x9D3 ; + .dw 0xEE2D ; + .dw 0xFC35 ; + .dw 0xEE2E ; + .dw 0x607D ; + .dw 0xEE2F ; + .dw 0x9603 ; + .dw 0xEE30 ; + .dw 0xB22F ; + .dw 0xEE31 ; + .dw 0x90FD ; + .dw 0xEE32 ; + .dw 0x226F ; + .dw 0xEE33 ; + .dw 0xB23D ; + .dw 0xEE34 ; + .dw 0x7B15 ; + .dw 0xEE35 ; + .dw 0xCB75 ; + .dw 0xEE36 ; + .dw 0x276D ; + .dw 0xEE37 ; + .dw 0x8111 ; + .dw 0xEE38 ; + .dw 0xAB9 ; + .dw 0xEE39 ; + .dw 0xC127 ; + .dw 0xEE3A ; + .dw 0x6249 ; + .dw 0xEE3B ; + .dw 0xAADB ; + .dw 0xEE3C ; + .dw 0xF151 ; + .dw 0xEE3D ; + .dw 0x6587 ; + .dw 0xEE3E ; + .dw 0x3DCB ; + .dw 0xEE3F ; + .dw 0xF229 ; + .dw 0xEE40 ; + .dw 0xB63 ; + .dw 0xEE41 ; + .dw 0x3973 ; + .dw 0xEE42 ; + .dw 0xE2D1 ; + .dw 0xEE43 ; + .dw 0x5C05 ; + .dw 0xEE44 ; + .dw 0xB1A5 ; + .dw 0xEE45 ; + .dw 0x7A29 ; + .dw 0xEE46 ; + .dw 0xC7E1 ; + .dw 0xEE47 ; + .dw 0xA39F ; + .dw 0xEE48 ; + .dw 0xE55 ; + .dw 0xEE49 ; + .dw 0x47BD ; + .dw 0xEE4A ; + .dw 0xA23F ; + .dw 0xEE4B ; + .dw 0x318B ; + .dw 0xEE4C ; + .dw 0x7007 ; + .dw 0xEE4D ; + .dw 0xBB11 ; + .dw 0xEE4E ; + .dw 0x508F ; + .dw 0xEE4F ; + .dw 0x4E7B ; + .dw 0xEE50 ; + .dw 0xF20F ; + .dw 0xEE51 ; + .dw 0x6353 ; + .dw 0xEE52 ; + .dw 0xD6E1 ; + .dw 0xEE53 ; + .dw 0xC975 ; + .dw 0xEE54 ; + .dw 0x5243 ; + .dw 0xEE55 ; + .dw 0x22EF ; + .dw 0xEE56 ; + .dw 0x453 ; + .dw 0xEE57 ; + .dw 0xC985 ; + .dw 0xEE58 ; + .dw 0x4C69 ; + .dw 0xEE59 ; + .dw 0xE403 ; + .dw 0xEE5A ; + .dw 0xDA1F ; + .dw 0xEE5B ; + .dw 0x301 ; + .dw 0xEE5C ; + .dw 0x52FF ; + .dw 0xEE5D ; + .dw 0x1C65 ; + .dw 0xEE5E ; + .dw 0x4C3F ; + .dw 0xEE5F ; + .dw 0x837 ; + .dw 0xEE60 ; + .dw 0xFD97 ; + .dw 0xEE61 ; + .dw 0x990D ; + .dw 0xEE62 ; + .dw 0x7377 ; + .dw 0xEE63 ; + .dw 0xEDA9 ; + .dw 0xEE64 ; + .dw 0x4B3 ; + .dw 0xEE65 ; + .dw 0x8913 ; + .dw 0xEE66 ; + .dw 0xC8FB ; + .dw 0xEE67 ; + .dw 0xF9C5 ; + .dw 0xEE68 ; + .dw 0x231D ; + .dw 0xEE69 ; + .dw 0x4029 ; + .dw 0xEE6A ; + .dw 0x837F ; + .dw 0xEE6B ; + .dw 0x981B ; + .dw 0xEE6C ; + .dw 0xB4B9 ; + .dw 0xEE6D ; + .dw 0xA88F ; + .dw 0xEE6E ; + .dw 0xADCF ; + .dw 0xEE6F ; + .dw 0x4819 ; + .dw 0xEE70 ; + .dw 0x6AE1 ; + .dw 0xEE71 ; + .dw 0xDC8B ; + .dw 0xEE72 ; + .dw 0xEE7 ; + .dw 0xEE73 ; + .dw 0xBF41 ; + .dw 0xEE74 ; + .dw 0xEE3D ; + .dw 0xEE75 ; + .dw 0xDF65 ; + .dw 0xEE76 ; + .dw 0x7B91 ; + .dw 0xEE77 ; + .dw 0xF6DB ; + .dw 0xEE78 ; + .dw 0xC619 ; + .dw 0xEE79 ; + .dw 0xEDDD ; + .dw 0xEE7A ; + .dw 0xA975 ; + .dw 0xEE7B ; + .dw 0x5D37 ; + .dw 0xEE7C ; + .dw 0x5D41 ; + .dw 0xEE7D ; + .dw 0x5E1D ; + .dw 0xEE7E ; + .dw 0x1BB5 ; + .dw 0xEE7F ; + .dw 0xE261 ; + .dw 0xEE80 ; + .dw 0x7C55 ; + .dw 0xEE81 ; + .dw 0x873F ; + .dw 0xEE82 ; + .dw 0x4107 ; + .dw 0xEE83 ; + .dw 0x1859 ; + .dw 0xEE84 ; + .dw 0x11A3 ; + .dw 0xEE85 ; + .dw 0xA833 ; + .dw 0xEE86 ; + .dw 0x5B47 ; + .dw 0xEE87 ; + .dw 0x1EC5 ; + .dw 0xEE88 ; + .dw 0x9E7F ; + .dw 0xEE89 ; + .dw 0x464B ; + .dw 0xEE8A ; + .dw 0x4895 ; + .dw 0xEE8B ; + .dw 0x9233 ; + .dw 0xEE8C ; + .dw 0x2219 ; + .dw 0xEE8D ; + .dw 0xFB1F ; + .dw 0xEE8E ; + .dw 0xC5E9 ; + .dw 0xEE8F ; + .dw 0x36CD ; + .dw 0xEE90 ; + .dw 0xD9D7 ; + .dw 0xEE91 ; + .dw 0x2A13 ; + .dw 0xEE92 ; + .dw 0x432F ; + .dw 0xEE93 ; + .dw 0x968F ; + .dw 0xEE94 ; + .dw 0xAF2F ; + .dw 0xEE95 ; + .dw 0x954B ; + .dw 0xEE96 ; + .dw 0xE0D7 ; + .dw 0xEE97 ; + .dw 0x4B01 ; + .dw 0xEE98 ; + .dw 0xAAF7 ; + .dw 0xEE99 ; + .dw 0x4A21 ; + .dw 0xEE9A ; + .dw 0xAEF9 ; + .dw 0xEE9B ; + .dw 0x2A6B ; + .dw 0xEE9C ; + .dw 0x4649 ; + .dw 0xEE9D ; + .dw 0xDD1F ; + .dw 0xEE9E ; + .dw 0xC5E1 ; + .dw 0xEE9F ; + .dw 0x1099 ; + .dw 0xEEA0 ; + .dw 0xF0CF ; + .dw 0xEEA1 ; + .dw 0x6D77 ; + .dw 0xEEA2 ; + .dw 0x5031 ; + .dw 0xEEA3 ; + .dw 0x7B03 ; + .dw 0xEEA4 ; + .dw 0xA4A3 ; + .dw 0xEEA5 ; + .dw 0x67FB ; + .dw 0xEEA6 ; + .dw 0x1E73 ; + .dw 0xEEA7 ; + .dw 0xB08D ; + .dw 0xEEA8 ; + .dw 0xDFA7 ; + .dw 0xEEA9 ; + .dw 0x818F ; + .dw 0xEEAA ; + .dw 0xDC33 ; + .dw 0xEEAB ; + .dw 0xACC1 ; + .dw 0xEEAC ; + .dw 0xDA55 ; + .dw 0xEEAD ; + .dw 0xE12F ; + .dw 0xEEAE ; + .dw 0x7E91 ; + .dw 0xEEAF ; + .dw 0x8685 ; + .dw 0xEEB0 ; + .dw 0x5421 ; + .dw 0xEEB1 ; + .dw 0xF15B ; + .dw 0xEEB2 ; + .dw 0x467 ; + .dw 0xEEB3 ; + .dw 0x8A51 ; + .dw 0xEEB4 ; + .dw 0xCD49 ; + .dw 0xEEB5 ; + .dw 0xD10F ; + .dw 0xEEB6 ; + .dw 0x1FD5 ; + .dw 0xEEB7 ; + .dw 0xBFE7 ; + .dw 0xEEB8 ; + .dw 0x8635 ; + .dw 0xEEB9 ; + .dw 0xDC43 ; + .dw 0xEEBA ; + .dw 0xE159 ; + .dw 0xEEBB ; + .dw 0x138F ; + .dw 0xEEBC ; + .dw 0x1C45 ; + .dw 0xEEBD ; + .dw 0x43DB ; + .dw 0xEEBE ; + .dw 0xFC71 ; + .dw 0xEEBF ; + .dw 0xDACD ; + .dw 0xEEC0 ; + .dw 0x1C35 ; + .dw 0xEEC1 ; + .dw 0x2D29 ; + .dw 0xEEC2 ; + .dw 0xBDA7 ; + .dw 0xEEC3 ; + .dw 0xEC97 ; + .dw 0xEEC4 ; + .dw 0x61E7 ; + .dw 0xEEC5 ; + .dw 0x50D7 ; + .dw 0xEEC6 ; + .dw 0x4A31 ; + .dw 0xEEC7 ; + .dw 0x50D ; + .dw 0xEEC8 ; + .dw 0x9DC7 ; + .dw 0xEEC9 ; + .dw 0x9169 ; + .dw 0xEECA ; + .dw 0x4105 ; + .dw 0xEECB ; + .dw 0xACB5 ; + .dw 0xEECC ; + .dw 0xD79F ; + .dw 0xEECD ; + .dw 0x8133 ; + .dw 0xEECE ; + .dw 0x5575 ; + .dw 0xEECF ; + .dw 0x5B31 ; + .dw 0xEED0 ; + .dw 0x46EF ; + .dw 0xEED1 ; + .dw 0x4FD1 ; + .dw 0xEED2 ; + .dw 0xFB45 ; + .dw 0xEED3 ; + .dw 0xD75 ; + .dw 0xEED4 ; + .dw 0x58BF ; + .dw 0xEED5 ; + .dw 0x171F ; + .dw 0xEED6 ; + .dw 0xBC3B ; + .dw 0xEED7 ; + .dw 0x77F ; + .dw 0xEED8 ; + .dw 0x3B03 ; + .dw 0xEED9 ; + .dw 0xFFAF ; + .dw 0xEEDA ; + .dw 0x4F4B ; + .dw 0xEEDB ; + .dw 0xF991 ; + .dw 0xEEDC ; + .dw 0xC569 ; + .dw 0xEEDD ; + .dw 0x34C1 ; + .dw 0xEEDE ; + .dw 0x915 ; + .dw 0xEEDF ; + .dw 0x40EF ; + .dw 0xEEE0 ; + .dw 0x17B5 ; + .dw 0xEEE1 ; + .dw 0x1FC3 ; + .dw 0xEEE2 ; + .dw 0xBE17 ; + .dw 0xEEE3 ; + .dw 0x7C07 ; + .dw 0xEEE4 ; + .dw 0xC599 ; + .dw 0xEEE5 ; + .dw 0xE339 ; + .dw 0xEEE6 ; + .dw 0xAE2D ; + .dw 0xEEE7 ; + .dw 0x2A37 ; + .dw 0xEEE8 ; + .dw 0xE80D ; + .dw 0xEEE9 ; + .dw 0x8D45 ; + .dw 0xEEEA ; + .dw 0x91BF ; + .dw 0xEEEB ; + .dw 0x8F01 ; + .dw 0xEEEC ; + .dw 0xEC27 ; + .dw 0xEEED ; + .dw 0xF997 ; + .dw 0xEEEE ; + .dw 0x6047 ; + .dw 0xEEEF ; + .dw 0x90C3 ; + .dw 0xEEF0 ; + .dw 0x776F ; + .dw 0xEEF1 ; + .dw 0xDAE9 ; + .dw 0xEEF2 ; + .dw 0xE873 ; + .dw 0xEEF3 ; + .dw 0xCAEB ; + .dw 0xEEF4 ; + .dw 0x39BD ; + .dw 0xEEF5 ; + .dw 0xE3EF ; + .dw 0xEEF6 ; + .dw 0xD1BB ; + .dw 0xEEF7 ; + .dw 0x8BB7 ; + .dw 0xEEF8 ; + .dw 0x48F ; + .dw 0xEEF9 ; + .dw 0x87D7 ; + .dw 0xEEFA ; + .dw 0x1F79 ; + .dw 0xEEFB ; + .dw 0xF563 ; + .dw 0xEEFC ; + .dw 0xFFE1 ; + .dw 0xEEFD ; + .dw 0x4A41 ; + .dw 0xEEFE ; + .dw 0xCD7F ; + .dw 0xEEFF ; + .dw 0xFAED ; + .dw 0xEF00 ; + .dw 0x5481 ; + .dw 0xEF01 ; + .dw 0x16B3 ; + .dw 0xEF02 ; + .dw 0x9E2F ; + .dw 0xEF03 ; + .dw 0x7041 ; + .dw 0xEF04 ; + .dw 0x23EF ; + .dw 0xEF05 ; + .dw 0x9791 ; + .dw 0xEF06 ; + .dw 0xB21B ; + .dw 0xEF07 ; + .dw 0xE5F9 ; + .dw 0xEF08 ; + .dw 0x25AD ; + .dw 0xEF09 ; + .dw 0x495 ; + .dw 0xEF0A ; + .dw 0x10F ; + .dw 0xEF0B ; + .dw 0x8895 ; + .dw 0xEF0C ; + .dw 0xC21B ; + .dw 0xEF0D ; + .dw 0x60CF ; + .dw 0xEF0E ; + .dw 0x4CB3 ; + .dw 0xEF0F ; + .dw 0xBB29 ; + .dw 0xEF10 ; + .dw 0x2D3 ; + .dw 0xEF11 ; + .dw 0xA00F ; + .dw 0xEF12 ; + .dw 0xA4A3 ; + .dw 0xEF13 ; + .dw 0xA5A5 ; + .dw 0xEF14 ; + .dw 0x3075 ; + .dw 0xEF15 ; + .dw 0xABEB ; + .dw 0xEF16 ; + .dw 0x1403 ; + .dw 0xEF17 ; + .dw 0x6E7F ; + .dw 0xEF18 ; + .dw 0x760B ; + .dw 0xEF19 ; + .dw 0xC02B ; + .dw 0xEF1A ; + .dw 0x9095 ; + .dw 0xEF1B ; + .dw 0x57F3 ; + .dw 0xEF1C ; + .dw 0x61DD ; + .dw 0xEF1D ; + .dw 0x16CB ; + .dw 0xEF1E ; + .dw 0xC35B ; + .dw 0xEF1F ; + .dw 0x78B7 ; + .dw 0xEF20 ; + .dw 0x9BC9 ; + .dw 0xEF21 ; + .dw 0x5B6D ; + .dw 0xEF22 ; + .dw 0xC2A3 ; + .dw 0xEF23 ; + .dw 0x4837 ; + .dw 0xEF24 ; + .dw 0xA915 ; + .dw 0xEF25 ; + .dw 0xDE4D ; + .dw 0xEF26 ; + .dw 0x55A9 ; + .dw 0xEF27 ; + .dw 0xB645 ; + .dw 0xEF28 ; + .dw 0x15D3 ; + .dw 0xEF29 ; + .dw 0xFEC9 ; + .dw 0xEF2A ; + .dw 0xD9A5 ; + .dw 0xEF2B ; + .dw 0x65D ; + .dw 0xEF2C ; + .dw 0xDBAD ; + .dw 0xEF2D ; + .dw 0xC547 ; + .dw 0xEF2E ; + .dw 0x606D ; + .dw 0xEF2F ; + .dw 0x2655 ; + .dw 0xEF30 ; + .dw 0x5E49 ; + .dw 0xEF31 ; + .dw 0x24B7 ; + .dw 0xEF32 ; + .dw 0x2087 ; + .dw 0xEF33 ; + .dw 0xB893 ; + .dw 0xEF34 ; + .dw 0xD515 ; + .dw 0xEF35 ; + .dw 0xDB85 ; + .dw 0xEF36 ; + .dw 0xCEC3 ; + .dw 0xEF37 ; + .dw 0x89C9 ; + .dw 0xEF38 ; + .dw 0x7AA7 ; + .dw 0xEF39 ; + .dw 0x6C1D ; + .dw 0xEF3A ; + .dw 0xF951 ; + .dw 0xEF3B ; + .dw 0xAA33 ; + .dw 0xEF3C ; + .dw 0x5991 ; + .dw 0xEF3D ; + .dw 0x24CF ; + .dw 0xEF3E ; + .dw 0xFC5D ; + .dw 0xEF3F ; + .dw 0xE23F ; + .dw 0xEF40 ; + .dw 0xEBB ; + .dw 0xEF41 ; + .dw 0xAF5D ; + .dw 0xEF42 ; + .dw 0xA823 ; + .dw 0xEF43 ; + .dw 0xBAD7 ; + .dw 0xEF44 ; + .dw 0x593D ; + .dw 0xEF45 ; + .dw 0x1FE1 ; + .dw 0xEF46 ; + .dw 0x3087 ; + .dw 0xEF47 ; + .dw 0xD109 ; + .dw 0xEF48 ; + .dw 0xCFAF ; + .dw 0xEF49 ; + .dw 0xFB51 ; + .dw 0xEF4A ; + .dw 0x7E31 ; + .dw 0xEF4B ; + .dw 0xAD4F ; + .dw 0xEF4C ; + .dw 0x930D ; + .dw 0xEF4D ; + .dw 0x2D71 ; + .dw 0xEF4E ; + .dw 0x7923 ; + .dw 0xEF4F ; + .dw 0xD635 ; + .dw 0xEF50 ; + .dw 0x5703 ; + .dw 0xEF51 ; + .dw 0x664D ; + .dw 0xEF52 ; + .dw 0x64CD ; + .dw 0xEF53 ; + .dw 0x56A1 ; + .dw 0xEF54 ; + .dw 0x97CF ; + .dw 0xEF55 ; + .dw 0xD72F ; + .dw 0xEF56 ; + .dw 0xE5AB ; + .dw 0xEF57 ; + .dw 0x6F85 ; + .dw 0xEF58 ; + .dw 0x5591 ; + .dw 0xEF59 ; + .dw 0xC719 ; + .dw 0xEF5A ; + .dw 0xC85B ; + .dw 0xEF5B ; + .dw 0xAD11 ; + .dw 0xEF5C ; + .dw 0x2D29 ; + .dw 0xEF5D ; + .dw 0xF6BD ; + .dw 0xEF5E ; + .dw 0x2233 ; + .dw 0xEF5F ; + .dw 0x1773 ; + .dw 0xEF60 ; + .dw 0x2689 ; + .dw 0xEF61 ; + .dw 0x4BF5 ; + .dw 0xEF62 ; + .dw 0xE35B ; + .dw 0xEF63 ; + .dw 0xB711 ; + .dw 0xEF64 ; + .dw 0x1095 ; + .dw 0xEF65 ; + .dw 0xBCBB ; + .dw 0xEF66 ; + .dw 0x7265 ; + .dw 0xEF67 ; + .dw 0x2437 ; + .dw 0xEF68 ; + .dw 0xC273 ; + .dw 0xEF69 ; + .dw 0xF19F ; + .dw 0xEF6A ; + .dw 0x6963 ; + .dw 0xEF6B ; + .dw 0x5A55 ; + .dw 0xEF6C ; + .dw 0x1A6B ; + .dw 0xEF6D ; + .dw 0x97BF ; + .dw 0xEF6E ; + .dw 0xC85 ; + .dw 0xEF6F ; + .dw 0x86BB ; + .dw 0xEF70 ; + .dw 0x1231 ; + .dw 0xEF71 ; + .dw 0xDA43 ; + .dw 0xEF72 ; + .dw 0x9225 ; + .dw 0xEF73 ; + .dw 0xAC5 ; + .dw 0xEF74 ; + .dw 0xC0D3 ; + .dw 0xEF75 ; + .dw 0xFB55 ; + .dw 0xEF76 ; + .dw 0xD46B ; + .dw 0xEF77 ; + .dw 0x69A1 ; + .dw 0xEF78 ; + .dw 0xA1FD ; + .dw 0xEF79 ; + .dw 0x8491 ; + .dw 0xEF7A ; + .dw 0x8463 ; + .dw 0xEF7B ; + .dw 0x597D ; + .dw 0xEF7C ; + .dw 0xFAD7 ; + .dw 0xEF7D ; + .dw 0x705 ; + .dw 0xEF7E ; + .dw 0x768D ; + .dw 0xEF7F ; + .dw 0xB045 ; + .dw 0xEF80 ; + .dw 0xB463 ; + .dw 0xEF81 ; + .dw 0xE2A7 ; + .dw 0xEF82 ; + .dw 0x20FF ; + .dw 0xEF83 ; + .dw 0x63D7 ; + .dw 0xEF84 ; + .dw 0x834F ; + .dw 0xEF85 ; + .dw 0xD4B ; + .dw 0xEF86 ; + .dw 0xE2F3 ; + .dw 0xEF87 ; + .dw 0x55BD ; + .dw 0xEF88 ; + .dw 0xB54F ; + .dw 0xEF89 ; + .dw 0x511F ; + .dw 0xEF8A ; + .dw 0x2DED ; + .dw 0xEF8B ; + .dw 0x2265 ; + .dw 0xEF8C ; + .dw 0x7BF5 ; + .dw 0xEF8D ; + .dw 0xFA9D ; + .dw 0xEF8E ; + .dw 0x2843 ; + .dw 0xEF8F ; + .dw 0xABD5 ; + .dw 0xEF90 ; + .dw 0xD03 ; + .dw 0xEF91 ; + .dw 0x6E0B ; + .dw 0xEF92 ; + .dw 0xE13F ; + .dw 0xEF93 ; + .dw 0x97E9 ; + .dw 0xEF94 ; + .dw 0x7051 ; + .dw 0xEF95 ; + .dw 0x9C69 ; + .dw 0xEF96 ; + .dw 0xAEB5 ; + .dw 0xEF97 ; + .dw 0x7A0D ; + .dw 0xEF98 ; + .dw 0x5315 ; + .dw 0xEF99 ; + .dw 0xCFF5 ; + .dw 0xEF9A ; + .dw 0xCC19 ; + .dw 0xEF9B ; + .dw 0xE069 ; + .dw 0xEF9C ; + .dw 0xB8C9 ; + .dw 0xEF9D ; + .dw 0xC815 ; + .dw 0xEF9E ; + .dw 0xD31B ; + .dw 0xEF9F ; + .dw 0xFCA3 ; + .dw 0xEFA0 ; + .dw 0xE179 ; + .dw 0xEFA1 ; + .dw 0x9CDF ; + .dw 0xEFA2 ; + .dw 0x25BB ; + .dw 0xEFA3 ; + .dw 0x2019 ; + .dw 0xEFA4 ; + .dw 0x3D9B ; + .dw 0xEFA5 ; + .dw 0x61FF ; + .dw 0xEFA6 ; + .dw 0xE1E3 ; + .dw 0xEFA7 ; + .dw 0xC38D ; + .dw 0xEFA8 ; + .dw 0xC773 ; + .dw 0xEFA9 ; + .dw 0x141 ; + .dw 0xEFAA ; + .dw 0x767D ; + .dw 0xEFAB ; + .dw 0x5269 ; + .dw 0xEFAC ; + .dw 0x99DB ; + .dw 0xEFAD ; + .dw 0x447D ; + .dw 0xEFAE ; + .dw 0x720D ; + .dw 0xEFAF ; + .dw 0x7173 ; + .dw 0xEFB0 ; + .dw 0x1CA7 ; + .dw 0xEFB1 ; + .dw 0x8711 ; + .dw 0xEFB2 ; + .dw 0xA2CB ; + .dw 0xEFB3 ; + .dw 0xF903 ; + .dw 0xEFB4 ; + .dw 0x9E77 ; + .dw 0xEFB5 ; + .dw 0x6DB ; + .dw 0xEFB6 ; + .dw 0x2035 ; + .dw 0xEFB7 ; + .dw 0x5ABB ; + .dw 0xEFB8 ; + .dw 0xB40F ; + .dw 0xEFB9 ; + .dw 0x4CB5 ; + .dw 0xEFBA ; + .dw 0x562D ; + .dw 0xEFBB ; + .dw 0xAAC3 ; + .dw 0xEFBC ; + .dw 0x3531 ; + .dw 0xEFBD ; + .dw 0xA461 ; + .dw 0xEFBE ; + .dw 0xA98F ; + .dw 0xEFBF ; + .dw 0x47F ; + .dw 0xEFC0 ; + .dw 0x2EF9 ; + .dw 0xEFC1 ; + .dw 0x1C0F ; + .dw 0xEFC2 ; + .dw 0xCE43 ; + .dw 0xEFC3 ; + .dw 0x82C5 ; + .dw 0xEFC4 ; + .dw 0xA3A9 ; + .dw 0xEFC5 ; + .dw 0x34B ; + .dw 0xEFC6 ; + .dw 0x66E3 ; + .dw 0xEFC7 ; + .dw 0x8395 ; + .dw 0xEFC8 ; + .dw 0x700D ; + .dw 0xEFC9 ; + .dw 0x6179 ; + .dw 0xEFCA ; + .dw 0x5C3 ; + .dw 0xEFCB ; + .dw 0x6F55 ; + .dw 0xEFCC ; + .dw 0x2E51 ; + .dw 0xEFCD ; + .dw 0x5BCF ; + .dw 0xEFCE ; + .dw 0x2795 ; + .dw 0xEFCF ; + .dw 0xBB87 ; + .dw 0xEFD0 ; + .dw 0x6E4F ; + .dw 0xEFD1 ; + .dw 0x2C7 ; + .dw 0xEFD2 ; + .dw 0x3F7B ; + .dw 0xEFD3 ; + .dw 0x60FD ; + .dw 0xEFD4 ; + .dw 0x1B77 ; + .dw 0xEFD5 ; + .dw 0x7F1B ; + .dw 0xEFD6 ; + .dw 0x6C9F ; + .dw 0xEFD7 ; + .dw 0x7D99 ; + .dw 0xEFD8 ; + .dw 0x6817 ; + .dw 0xEFD9 ; + .dw 0x163F ; + .dw 0xEFDA ; + .dw 0xF151 ; + .dw 0xEFDB ; + .dw 0x597D ; + .dw 0xEFDC ; + .dw 0x163F ; + .dw 0xEFDD ; + .dw 0xFE55 ; + .dw 0xEFDE ; + .dw 0x395 ; + .dw 0xEFDF ; + .dw 0x87C7 ; + .dw 0xEFE0 ; + .dw 0x7615 ; + .dw 0xEFE1 ; + .dw 0x79A7 ; + .dw 0xEFE2 ; + .dw 0xF45 ; + .dw 0xEFE3 ; + .dw 0x5ACB ; + .dw 0xEFE4 ; + .dw 0xF1A7 ; + .dw 0xEFE5 ; + .dw 0x319B ; + .dw 0xEFE6 ; + .dw 0x1A3 ; + .dw 0xEFE7 ; + .dw 0x63C5 ; + .dw 0xEFE8 ; + .dw 0x7E4F ; + .dw 0xEFE9 ; + .dw 0x4935 ; + .dw 0xEFEA ; + .dw 0xB66F ; + .dw 0xEFEB ; + .dw 0x3617 ; + .dw 0xEFEC ; + .dw 0xCB83 ; + .dw 0xEFED ; + .dw 0x1F03 ; + .dw 0xEFEE ; + .dw 0x1E89 ; + .dw 0xEFEF ; + .dw 0x25FF ; + .dw 0xEFF0 ; + .dw 0x872B ; + .dw 0xEFF1 ; + .dw 0x369D ; + .dw 0xEFF2 ; + .dw 0x37FB ; + .dw 0xEFF3 ; + .dw 0x3ACB ; + .dw 0xEFF4 ; + .dw 0x8F81 ; + .dw 0xEFF5 ; + .dw 0x4199 ; + .dw 0xEFF6 ; + .dw 0x6FA1 ; + .dw 0xEFF7 ; + .dw 0xC99 ; + .dw 0xEFF8 ; + .dw 0x6A5F ; + .dw 0xEFF9 ; + .dw 0xC007 ; + .dw 0xEFFA ; + .dw 0x8433 ; + .dw 0xEFFB ; + .dw 0xC585 ; + .dw 0xEFFC ; + .dw 0xDA23 ; + .dw 0xEFFD ; + .dw 0x3065 ; + .dw 0xEFFE ; + .dw 0x82E1 ; + .dw 0xEFFF ; + .dw 0xFE6D ; + .dw 0xC700 ; + .dw 0xE7FB ; + .dw 0xC701 ; + .dw 0x4717 ; + .dw 0xC702 ; + .dw 0xF573 ; + .dw 0xC703 ; + .dw 0xAF1D ; + .dw 0xC704 ; + .dw 0x3BC7 ; + .dw 0xC705 ; + .dw 0x2563 ; + .dw 0xC706 ; + .dw 0xD9D3 ; + .dw 0xC707 ; + .dw 0xEA0F ; + .dw 0xC708 ; + .dw 0x1969 ; + .dw 0xC709 ; + .dw 0x7E5 ; + .dw 0xC70A ; + .dw 0x7B31 ; + .dw 0xC70B ; + .dw 0x9BA1 ; + .dw 0xC70C ; + .dw 0xDBA3 ; + .dw 0xC70D ; + .dw 0x6489 ; + .dw 0xC70E ; + .dw 0xC499 ; + .dw 0xC70F ; + .dw 0x4CD ; + .dw 0xC710 ; + .dw 0x446B ; + .dw 0xC711 ; + .dw 0xF003 ; + .dw 0xC712 ; + .dw 0x24FF ; + .dw 0xC713 ; + .dw 0x295D ; + .dw 0xC714 ; + .dw 0x7AC3 ; + .dw 0xC715 ; + .dw 0x82C5 ; + .dw 0xC716 ; + .dw 0x9CED ; + .dw 0xC717 ; + .dw 0xE9A9 ; + .dw 0xC718 ; + .dw 0xE15 ; + .dw 0xC719 ; + .dw 0x557B ; + .dw 0xC71A ; + .dw 0xD83 ; + .dw 0xC71B ; + .dw 0xFFCD ; + .dw 0xC71C ; + .dw 0xD70B ; + .dw 0xC71D ; + .dw 0x8CFD ; + .dw 0xC71E ; + .dw 0x6121 ; + .dw 0xC71F ; + .dw 0x985F ; + .dw 0xC720 ; + .dw 0xDDD ; + .dw 0xC721 ; + .dw 0x8DCF ; + .dw 0xC722 ; + .dw 0xA579 ; + .dw 0xC723 ; + .dw 0xBEA9 ; + .dw 0xC724 ; + .dw 0x6E39 ; + .dw 0xC725 ; + .dw 0xF0F ; + .dw 0xC726 ; + .dw 0xAF23 ; + .dw 0xC727 ; + .dw 0x5461 ; + .dw 0xC728 ; + .dw 0xC08B ; + .dw 0xC729 ; + .dw 0x64F9 ; + .dw 0xC72A ; + .dw 0x5EBB ; + .dw 0xC72B ; + .dw 0xCCE3 ; + .dw 0xC72C ; + .dw 0xA0E1 ; + .dw 0xC72D ; + .dw 0xFAD1 ; + .dw 0xC72E ; + .dw 0x1F75 ; + .dw 0xC72F ; + .dw 0x63DF ; + .dw 0xC730 ; + .dw 0xDB3D ; + .dw 0xC731 ; + .dw 0x7469 ; + .dw 0xC732 ; + .dw 0xB735 ; + .dw 0xC733 ; + .dw 0x7A1 ; + .dw 0xC734 ; + .dw 0x356F ; + .dw 0xC735 ; + .dw 0x6F0F ; + .dw 0xC736 ; + .dw 0x2F ; + .dw 0xC737 ; + .dw 0xAEB9 ; + .dw 0xC738 ; + .dw 0xFE6D ; + .dw 0xC739 ; + .dw 0x5A0B ; + .dw 0xC73A ; + .dw 0xA3F1 ; + .dw 0xC73B ; + .dw 0x5143 ; + .dw 0xC73C ; + .dw 0x3B29 ; + .dw 0xC73D ; + .dw 0x5E91 ; + .dw 0xC73E ; + .dw 0x7007 ; + .dw 0xC73F ; + .dw 0x3D8D ; + .dw 0xC740 ; + .dw 0xC8EB ; + .dw 0xC741 ; + .dw 0xCF3F ; + .dw 0xC742 ; + .dw 0x5C0B ; + .dw 0xC743 ; + .dw 0x61 ; + .dw 0xC744 ; + .dw 0x4D2B ; + .dw 0xC745 ; + .dw 0x1713 ; + .dw 0xC746 ; + .dw 0xD945 ; + .dw 0xC747 ; + .dw 0x98AD ; + .dw 0xC748 ; + .dw 0x4AE3 ; + .dw 0xC749 ; + .dw 0x9FDF ; + .dw 0xC74A ; + .dw 0x83BB ; + .dw 0xC74B ; + .dw 0x2EC9 ; + .dw 0xC74C ; + .dw 0x356B ; + .dw 0xC74D ; + .dw 0xA84B ; + .dw 0xC74E ; + .dw 0xCCCD ; + .dw 0xC74F ; + .dw 0x727 ; + .dw 0xC750 ; + .dw 0xD8D1 ; + .dw 0xC751 ; + .dw 0x813F ; + .dw 0xC752 ; + .dw 0xB74F ; + .dw 0xC753 ; + .dw 0xE887 ; + .dw 0xC754 ; + .dw 0xEFB3 ; + .dw 0xC755 ; + .dw 0x2AE7 ; + .dw 0xC756 ; + .dw 0x3D1B ; + .dw 0xC757 ; + .dw 0xADBB ; + .dw 0xC758 ; + .dw 0x3E93 ; + .dw 0xC759 ; + .dw 0xC925 ; + .dw 0xC75A ; + .dw 0x762D ; + .dw 0xC75B ; + .dw 0x3AD7 ; + .dw 0xC75C ; + .dw 0xCAB ; + .dw 0xC75D ; + .dw 0xE78D ; + .dw 0xC75E ; + .dw 0x193F ; + .dw 0xC75F ; + .dw 0x8DE9 ; + .dw 0xC760 ; + .dw 0x5255 ; + .dw 0xC761 ; + .dw 0x4D7 ; + .dw 0xC762 ; + .dw 0x6DD7 ; + .dw 0xC763 ; + .dw 0x2333 ; + .dw 0xC764 ; + .dw 0x74CF ; + .dw 0xC765 ; + .dw 0x5DDB ; + .dw 0xC766 ; + .dw 0x47E5 ; + .dw 0xC767 ; + .dw 0x64E1 ; + .dw 0xC768 ; + .dw 0xE7A1 ; + .dw 0xC769 ; + .dw 0x700B ; + .dw 0xC76A ; + .dw 0x24E1 ; + .dw 0xC76B ; + .dw 0x5E49 ; + .dw 0xC76C ; + .dw 0x8B73 ; + .dw 0xC76D ; + .dw 0x2B65 ; + .dw 0xC76E ; + .dw 0x253 ; + .dw 0xC76F ; + .dw 0x6A93 ; + .dw 0xC770 ; + .dw 0x225B ; + .dw 0xC771 ; + .dw 0x4BF5 ; + .dw 0xC772 ; + .dw 0x5F9 ; + .dw 0xC773 ; + .dw 0x1701 ; + .dw 0xC774 ; + .dw 0xB1C3 ; + .dw 0xC775 ; + .dw 0xD2BD ; + .dw 0xC776 ; + .dw 0x8F5D ; + .dw 0xC777 ; + .dw 0xF09F ; + .dw 0xC778 ; + .dw 0x29B7 ; + .dw 0xC779 ; + .dw 0x163D ; + .dw 0xC77A ; + .dw 0xCAE9 ; + .dw 0xC77B ; + .dw 0x757B ; + .dw 0xC77C ; + .dw 0x29C5 ; + .dw 0xC77D ; + .dw 0x6263 ; + .dw 0xC77E ; + .dw 0x5E7D ; + .dw 0xC77F ; + .dw 0xE161 ; + .dw 0xC780 ; + .dw 0x3B49 ; + .dw 0xC781 ; + .dw 0xA005 ; + .dw 0xC782 ; + .dw 0x478D ; + .dw 0xC783 ; + .dw 0xE0F ; + .dw 0xC784 ; + .dw 0x5955 ; + .dw 0xC785 ; + .dw 0xFBD9 ; + .dw 0xC786 ; + .dw 0x82B7 ; + .dw 0xC787 ; + .dw 0x1EEF ; + .dw 0xC788 ; + .dw 0x1DF9 ; + .dw 0xC789 ; + .dw 0x4E9 ; + .dw 0xC78A ; + .dw 0x94DD ; + .dw 0xC78B ; + .dw 0x304D ; + .dw 0xC78C ; + .dw 0x6D27 ; + .dw 0xC78D ; + .dw 0x3A93 ; + .dw 0xC78E ; + .dw 0x8DB3 ; + .dw 0xC78F ; + .dw 0xC213 ; + .dw 0xC790 ; + .dw 0xF507 ; + .dw 0xC791 ; + .dw 0x81F9 ; + .dw 0xC792 ; + .dw 0x9BE7 ; + .dw 0xC793 ; + .dw 0x15FD ; + .dw 0xC794 ; + .dw 0x5BCB ; + .dw 0xC795 ; + .dw 0x7AFF ; + .dw 0xC796 ; + .dw 0xCAA9 ; + .dw 0xC797 ; + .dw 0x3951 ; + .dw 0xC798 ; + .dw 0x730D ; + .dw 0xC799 ; + .dw 0x2CBF ; + .dw 0xC79A ; + .dw 0xD3 ; + .dw 0xC79B ; + .dw 0xF21D ; + .dw 0xC79C ; + .dw 0x48A3 ; + .dw 0xC79D ; + .dw 0x183 ; + .dw 0xC79E ; + .dw 0xD96D ; + .dw 0xC79F ; + .dw 0x47E7 ; + .dw 0xC7A0 ; + .dw 0x6CF9 ; + .dw 0xC7A1 ; + .dw 0x8A3D ; + .dw 0xC7A2 ; + .dw 0x6DDD ; + .dw 0xC7A3 ; + .dw 0xDFE7 ; + .dw 0xC7A4 ; + .dw 0x46EB ; + .dw 0xC7A5 ; + .dw 0x17D ; + .dw 0xC7A6 ; + .dw 0xA96B ; + .dw 0xC7A7 ; + .dw 0xE4C5 ; + .dw 0xC7A8 ; + .dw 0xCD17 ; + .dw 0xC7A9 ; + .dw 0x5ED ; + .dw 0xC7AA ; + .dw 0x3E5F ; + .dw 0xC7AB ; + .dw 0xB1C9 ; + .dw 0xC7AC ; + .dw 0x7CBB ; + .dw 0xC7AD ; + .dw 0x8443 ; + .dw 0xC7AE ; + .dw 0xD4A1 ; + .dw 0xC7AF ; + .dw 0xF999 ; + .dw 0xC7B0 ; + .dw 0xE607 ; + .dw 0xC7B1 ; + .dw 0x48BF ; + .dw 0xC7B2 ; + .dw 0x89C7 ; + .dw 0xC7B3 ; + .dw 0xA06D ; + .dw 0xC7B4 ; + .dw 0xA5FD ; + .dw 0xC7B5 ; + .dw 0x3021 ; + .dw 0xC7B6 ; + .dw 0x5AAF ; + .dw 0xC7B7 ; + .dw 0x1C7 ; + .dw 0xC7B8 ; + .dw 0x25C1 ; + .dw 0xC7B9 ; + .dw 0x701F ; + .dw 0xC7BA ; + .dw 0x8E99 ; + .dw 0xC7BB ; + .dw 0xD9AF ; + .dw 0xC7BC ; + .dw 0xF775 ; + .dw 0xC7BD ; + .dw 0xEF5D ; + .dw 0xC7BE ; + .dw 0xBBC3 ; + .dw 0xC7BF ; + .dw 0x8969 ; + .dw 0xC7C0 ; + .dw 0x2895 ; + .dw 0xC7C1 ; + .dw 0x24ED ; + .dw 0xC7C2 ; + .dw 0x7D79 ; + .dw 0xC7C3 ; + .dw 0xEFA9 ; + .dw 0xC7C4 ; + .dw 0x61C3 ; + .dw 0xC7C5 ; + .dw 0x7737 ; + .dw 0xC7C6 ; + .dw 0x73AD ; + .dw 0xC7C7 ; + .dw 0x8C53 ; + .dw 0xC7C8 ; + .dw 0x2C2D ; + .dw 0xC7C9 ; + .dw 0x9283 ; + .dw 0xC7CA ; + .dw 0xA419 ; + .dw 0xC7CB ; + .dw 0x27AD ; + .dw 0xC7CC ; + .dw 0x345B ; + .dw 0xC7CD ; + .dw 0xAEE3 ; + .dw 0xC7CE ; + .dw 0xD4CB ; + .dw 0xC7CF ; + .dw 0xB513 ; + .dw 0xC7D0 ; + .dw 0xE289 ; + .dw 0xC7D1 ; + .dw 0x3DB5 ; + .dw 0xC7D2 ; + .dw 0xF849 ; + .dw 0xC7D3 ; + .dw 0xA93F ; + .dw 0xC7D4 ; + .dw 0x2087 ; + .dw 0xC7D5 ; + .dw 0xF68F ; + .dw 0xC7D6 ; + .dw 0x431B ; + .dw 0xC7D7 ; + .dw 0x7BEB ; + .dw 0xC7D8 ; + .dw 0xA503 ; + .dw 0xC7D9 ; + .dw 0xBBC9 ; + .dw 0xC7DA ; + .dw 0x2F1 ; + .dw 0xC7DB ; + .dw 0x8D1F ; + .dw 0xC7DC ; + .dw 0x9C6F ; + .dw 0xC7DD ; + .dw 0x4E61 ; + .dw 0xC7DE ; + .dw 0xCF2F ; + .dw 0xC7DF ; + .dw 0x25D7 ; + .dw 0xC7E0 ; + .dw 0x74B ; + .dw 0xC7E1 ; + .dw 0x4983 ; + .dw 0xC7E2 ; + .dw 0x2B0D ; + .dw 0xC7E3 ; + .dw 0xCC47 ; + .dw 0xC7E4 ; + .dw 0xA60D ; + .dw 0xC7E5 ; + .dw 0x5D77 ; + .dw 0xC7E6 ; + .dw 0x312F ; + .dw 0xC7E7 ; + .dw 0xA38B ; + .dw 0xC7E8 ; + .dw 0xCA6B ; + .dw 0xC7E9 ; + .dw 0x421D ; + .dw 0xC7EA ; + .dw 0x60B7 ; + .dw 0xC7EB ; + .dw 0xEE7 ; + .dw 0xC7EC ; + .dw 0xE637 ; + .dw 0xC7ED ; + .dw 0x58E7 ; + .dw 0xC7EE ; + .dw 0x23E1 ; + .dw 0xC7EF ; + .dw 0x5073 ; + .dw 0xC7F0 ; + .dw 0x2FC1 ; + .dw 0xC7F1 ; + .dw 0x7649 ; + .dw 0xC7F2 ; + .dw 0x281D ; + .dw 0xC7F3 ; + .dw 0x5B63 ; + .dw 0xC7F4 ; + .dw 0x339B ; + .dw 0xC7F5 ; + .dw 0xCABD ; + .dw 0xC7F6 ; + .dw 0x1FA1 ; + .dw 0xC7F7 ; + .dw 0x91B3 ; + .dw 0xC7F8 ; + .dw 0xAC07 ; + .dw 0xC7F9 ; + .dw 0x632F ; + .dw 0xC7FA ; + .dw 0x485 ; + .dw 0xC7FB ; + .dw 0xA55F ; + .dw 0xC7FC ; + .dw 0x75BD ; + .dw 0xC7FD ; + .dw 0x38FF ; + .dw 0xC7FE ; + .dw 0x755D ; + .dw 0xC7FF ; + .dw 0x5523 ; + .dw 0xE0C0 ; + .dw 0x0000 ; + .dw 0xE0A0 ; + .dw 0x8000 ; + .dw 0xE1A0 ; + .dw 0x0 ; + .dw 0xC401 ; + .dw 0x4000 ; + .dw 0xC404 ; + .dw 0xC000 ; + .dw 0xC406 ; + .dw 0xC000 ; + .dw 0xC407 ; + .dw 0xC000 ; + .dw 0xC40A ; + .dw 0x8000 ; + .dw 0xC40A ; + .dw 0xC000 ; + .dw 0xC40C ; + .dw 0x8000 ; + .dw 0xC40E ; + .dw 0x8000 ; + .dw 0xC40F ; + .dw 0x0 ; + .dw 0xC40F ; + .dw 0x4000 ; + .dw 0xC40F ; + .dw 0x8000 ; + .dw 0xC410 ; + .dw 0x8000 ; + .dw 0xC411 ; + .dw 0x8000 ; + .dw 0xC411 ; + .dw 0xC000 ; + .dw 0xC412 ; + .dw 0x4000 ; + .dw 0xC412 ; + .dw 0x8000 ; + .dw 0xC413 ; + .dw 0x0 ; + .dw 0xC413 ; + .dw 0x4000 ; + .dw 0xC413 ; + .dw 0x8000 ; + .dw 0xC413 ; + .dw 0xC000 ; + .dw 0xC414 ; + .dw 0x8000 ; + .dw 0xC414 ; + .dw 0xC000 ; + .dw 0xC415 ; + .dw 0x8000 ; + .dw 0xC415 ; + .dw 0xC000 ; + .dw 0xC418 ; + .dw 0x8000 ; + .dw 0xC418 ; + .dw 0xC000 ; + .dw 0xC417 ; + .dw 0x4000 ; + .dw 0xC417 ; + .dw 0x8000 ; + .dw 0xC417 ; + .dw 0xC000 ; + .dw 0xC419 ; + .dw 0x0 ; + .dw 0xC419 ; + .dw 0x4000 ; + .dw 0xC419 ; + .dw 0x8000 ; + .dw 0xC419 ; + .dw 0xC000 ; + .dw 0xC41A ; + .dw 0x0 ; + .dw 0xC41A ; + .dw 0x4000 ; + .dw 0xC41A ; + .dw 0x8000 ; + .dw 0xC41A ; + .dw 0xC000 ; + .dw 0xC41B ; + .dw 0x0 ; + .dw 0xC41B ; + .dw 0x4000 ; + .dw 0xC41B ; + .dw 0x8000 ; + .dw 0xC41B ; + .dw 0xC000 ; + .dw 0xC41C ; + .dw 0x0 ; + .dw 0xC41C ; + .dw 0x4000 ; + .dw 0xC41C ; + .dw 0x8000 ; + .dw 0xC41C ; + .dw 0xC000 ; + .dw 0xC41D ; + .dw 0x0 ; + .dw 0xC41D ; + .dw 0x4000 ; + .dw 0xC41D ; + .dw 0x8000 ; + .dw 0xC41D ; + .dw 0xC000 ; + .dw 0xC41E ; + .dw 0x0 ; + .dw 0xC41E ; + .dw 0x4000 ; + .dw 0xC41E ; + .dw 0x8000 ; + .dw 0xC41E ; + .dw 0xC000 ; + .dw 0xC41F ; + .dw 0x0 ; + .dw 0xC41F ; + .dw 0x4000 ; + .dw 0xC41F ; + .dw 0x8000 ; + .dw 0xC41F ; + .dw 0xC000 ; + .dw 0xC401 ; + .dw 0x0 ; + .dw 0xC401 ; + .dw 0x240 ; + .dw 0xC401 ; + .dw 0x480 ; + .dw 0xC401 ; + .dw 0x6C0 ; + .dw 0xC401 ; + .dw 0x900 ; + .dw 0xC401 ; + .dw 0xB40 ; + .dw 0xC401 ; + .dw 0xD80 ; + .dw 0xC401 ; + .dw 0xFC0 ; + .dw 0xC401 ; + .dw 0x8000 ; + .dw 0xC401 ; + .dw 0x8240 ; + .dw 0xC401 ; + .dw 0x8480 ; + .dw 0xC401 ; + .dw 0x86C0 ; + .dw 0xC401 ; + .dw 0x8900 ; + .dw 0xC401 ; + .dw 0x8B40 ; + .dw 0xC401 ; + .dw 0x8D80 ; + .dw 0xC401 ; + .dw 0x8FC0 ; + .dw 0xC401 ; + .dw 0xC000 ; + .dw 0xC401 ; + .dw 0xC240 ; + .dw 0xC401 ; + .dw 0xC480 ; + .dw 0xC401 ; + .dw 0xC6C0 ; + .dw 0xC401 ; + .dw 0xC900 ; + .dw 0xC401 ; + .dw 0xCB40 ; + .dw 0xC401 ; + .dw 0xCD80 ; + .dw 0xC401 ; + .dw 0xCFC0 ; + .dw 0xC404 ; + .dw 0x8000 ; + .dw 0xC404 ; + .dw 0x8240 ; + .dw 0xC404 ; + .dw 0x8480 ; + .dw 0xC404 ; + .dw 0x86C0 ; + .dw 0xC404 ; + .dw 0x8900 ; + .dw 0xC404 ; + .dw 0x8B40 ; + .dw 0xC404 ; + .dw 0x8D80 ; + .dw 0xC404 ; + .dw 0x8FC0 ; + .dw 0xC40C ; + .dw 0x4000 ; + .dw 0xC40C ; + .dw 0x4240 ; + .dw 0xC40C ; + .dw 0x4480 ; + .dw 0xC40C ; + .dw 0x46C0 ; + .dw 0xC40C ; + .dw 0x4900 ; + .dw 0xC40C ; + .dw 0x4B40 ; + .dw 0xC40C ; + .dw 0x4D80 ; + .dw 0xC40C ; + .dw 0x4FC0 ; + .dw 0xC40D ; + .dw 0x0 ; + .dw 0xC40D ; + .dw 0x240 ; + .dw 0xC40D ; + .dw 0x480 ; + .dw 0xC40D ; + .dw 0x6C0 ; + .dw 0xC40D ; + .dw 0x900 ; + .dw 0xC40D ; + .dw 0xB40 ; + .dw 0xC40D ; + .dw 0xD80 ; + .dw 0xC40D ; + .dw 0xFC0 ; + .dw 0xC40D ; + .dw 0x4000 ; + .dw 0xC40D ; + .dw 0x4240 ; + .dw 0xC40D ; + .dw 0x4480 ; + .dw 0xC40D ; + .dw 0x46C0 ; + .dw 0xC40D ; + .dw 0x4900 ; + .dw 0xC40D ; + .dw 0x4B40 ; + .dw 0xC40D ; + .dw 0x4D80 ; + .dw 0xC40D ; + .dw 0x4FC0 ; + .dw 0xC40D ; + .dw 0x8000 ; + .dw 0xC40D ; + .dw 0x8240 ; + .dw 0xC40D ; + .dw 0x8480 ; + .dw 0xC40D ; + .dw 0x86C0 ; + .dw 0xC40D ; + .dw 0x8900 ; + .dw 0xC40D ; + .dw 0x8B40 ; + .dw 0xC40D ; + .dw 0x8D80 ; + .dw 0xC40D ; + .dw 0x8FC0 ; + .dw 0xC40D ; + .dw 0xC000 ; + .dw 0xC40D ; + .dw 0xC240 ; + .dw 0xC40D ; + .dw 0xC480 ; + .dw 0xC40D ; + .dw 0xC6C0 ; + .dw 0xC40D ; + .dw 0xC900 ; + .dw 0xC40D ; + .dw 0xCB40 ; + .dw 0xC40D ; + .dw 0xCD80 ; + .dw 0xC40D ; + .dw 0xCFC0 ; + .dw 0xC411 ; + .dw 0x0 ; + .dw 0xC411 ; + .dw 0x240 ; + .dw 0xC411 ; + .dw 0x480 ; + .dw 0xC411 ; + .dw 0x6C0 ; + .dw 0xC411 ; + .dw 0x900 ; + .dw 0xC411 ; + .dw 0xB40 ; + .dw 0xC411 ; + .dw 0xD80 ; + .dw 0xC411 ; + .dw 0xFC0 ; + .dw 0xC411 ; + .dw 0x4000 ; + .dw 0xC411 ; + .dw 0x4240 ; + .dw 0xC411 ; + .dw 0x4480 ; + .dw 0xC411 ; + .dw 0x46C0 ; + .dw 0xC411 ; + .dw 0x4900 ; + .dw 0xC411 ; + .dw 0x4B40 ; + .dw 0xC411 ; + .dw 0x4D80 ; + .dw 0xC411 ; + .dw 0x4FC0 ; + .dw 0xC415 ; + .dw 0x0 ; + .dw 0xC415 ; + .dw 0x240 ; + .dw 0xC415 ; + .dw 0x480 ; + .dw 0xC415 ; + .dw 0x6C0 ; + .dw 0xC415 ; + .dw 0x900 ; + .dw 0xC415 ; + .dw 0xB40 ; + .dw 0xC415 ; + .dw 0xD80 ; + .dw 0xC415 ; + .dw 0xFC0 ; + .dw 0xC415 ; + .dw 0x4000 ; + .dw 0xC415 ; + .dw 0x4240 ; + .dw 0xC415 ; + .dw 0x4480 ; + .dw 0xC415 ; + .dw 0x46C0 ; + .dw 0xC415 ; + .dw 0x4900 ; + .dw 0xC415 ; + .dw 0x4B40 ; + .dw 0xC415 ; + .dw 0x4D80 ; + .dw 0xC415 ; + .dw 0x4FC0 ; + .dw 0xC418 ; + .dw 0x4000 ; + .dw 0xC418 ; + .dw 0x4240 ; + .dw 0xC418 ; + .dw 0x4480 ; + .dw 0xC418 ; + .dw 0x46C0 ; + .dw 0xC418 ; + .dw 0x4900 ; + .dw 0xC418 ; + .dw 0x4B40 ; + .dw 0xC418 ; + .dw 0x4D80 ; + .dw 0xC418 ; + .dw 0x4FC0 ; + .dw 0xC412 ; + .dw 0x9 ; + .dw 0xC412 ; + .dw 0x1B ; + .dw 0xC412 ; + .dw 0x24 ; + .dw 0xC412 ; + .dw 0x2D ; + .dw 0xC412 ; + .dw 0x36 ; + .dw 0xC412 ; + .dw 0x3F ; + .dw 0xC414 ; + .dw 0x9 ; + .dw 0xC414 ; + .dw 0x1B ; + .dw 0xC414 ; + .dw 0x24 ; + .dw 0xC414 ; + .dw 0x2D ; + .dw 0xC414 ; + .dw 0x36 ; + .dw 0xC414 ; + .dw 0x3F ; + .dw 0xC414 ; + .dw 0x4009 ; + .dw 0xC414 ; + .dw 0x401B ; + .dw 0xC414 ; + .dw 0x4024 ; + .dw 0xC414 ; + .dw 0x402D ; + .dw 0xC414 ; + .dw 0x4036 ; + .dw 0xC414 ; + .dw 0x403F ; + .dw 0xC415 ; + .dw 0x9 ; + .dw 0xC415 ; + .dw 0x1B ; + .dw 0xC415 ; + .dw 0x24 ; + .dw 0xC415 ; + .dw 0x2D ; + .dw 0xC415 ; + .dw 0x36 ; + .dw 0xC415 ; + .dw 0x3F ; + .dw 0xC415 ; + .dw 0x4009 ; + .dw 0xC415 ; + .dw 0x401B ; + .dw 0xC415 ; + .dw 0x4024 ; + .dw 0xC415 ; + .dw 0x402D ; + .dw 0xC415 ; + .dw 0x4036 ; + .dw 0xC415 ; + .dw 0x403F ; + .dw 0xC416 ; + .dw 0x9 ; + .dw 0xC416 ; + .dw 0x1B ; + .dw 0xC416 ; + .dw 0x24 ; + .dw 0xC416 ; + .dw 0x2D ; + .dw 0xC416 ; + .dw 0x36 ; + .dw 0xC416 ; + .dw 0x3F ; + .dw 0xC416 ; + .dw 0x4009 ; + .dw 0xC416 ; + .dw 0x401B ; + .dw 0xC416 ; + .dw 0x4024 ; + .dw 0xC416 ; + .dw 0x402D ; + .dw 0xC416 ; + .dw 0x4036 ; + .dw 0xC416 ; + .dw 0x403F ; + .dw 0xC416 ; + .dw 0x8009 ; + .dw 0xC416 ; + .dw 0x801B ; + .dw 0xC416 ; + .dw 0x8024 ; + .dw 0xC416 ; + .dw 0x802D ; + .dw 0xC416 ; + .dw 0x8036 ; + .dw 0xC416 ; + .dw 0x803F ; + .dw 0xC416 ; + .dw 0xC009 ; + .dw 0xC416 ; + .dw 0xC01B ; + .dw 0xC416 ; + .dw 0xC024 ; + .dw 0xC416 ; + .dw 0xC02D ; + .dw 0xC416 ; + .dw 0xC036 ; + .dw 0xC416 ; + .dw 0xC03F ; + .dw 0xC417 ; + .dw 0x9 ; + .dw 0xC417 ; + .dw 0x1B ; + .dw 0xC417 ; + .dw 0x24 ; + .dw 0xC417 ; + .dw 0x2D ; + .dw 0xC417 ; + .dw 0x36 ; + .dw 0xC417 ; + .dw 0x3F ; + .dw 0xC418 ; + .dw 0x4009 ; + .dw 0xC418 ; + .dw 0x401B ; + .dw 0xC418 ; + .dw 0x4024 ; + .dw 0xC418 ; + .dw 0x402D ; + .dw 0xC418 ; + .dw 0x4036 ; + .dw 0xC418 ; + .dw 0x403F ; + .dw 0xC600 ; + .dw 0xC000 ; + .dw 0xC601 ; + .dw 0xC000 ; + .dw 0xC603 ; + .dw 0xC000 ; + .dw 0xC605 ; + .dw 0xC000 ; + .dw 0xC608 ; + .dw 0xC000 ; + .dw 0xC60B ; + .dw 0xC000 ; + .dw 0xC60C ; + .dw 0xC000 ; + .dw 0xC60D ; + .dw 0xC000 ; + .dw 0xC606 ; + .dw 0x8000 ; + .dw 0xC608 ; + .dw 0x8000 ; + .dw 0xC60B ; + .dw 0x8000 ; + .dw 0xC60C ; + .dw 0x8000 ; + .dw 0xC60E ; + .dw 0x0 ; + .dw 0xC60E ; + .dw 0x4000 ; + .dw 0xC60E ; + .dw 0x8000 ; + .dw 0xC60E ; + .dw 0xC000 ; + .dw 0xC60F ; + .dw 0x0 ; + .dw 0xC60F ; + .dw 0x4000 ; + .dw 0xC60F ; + .dw 0x8000 ; + .dw 0xC60F ; + .dw 0xC000 ; + .dw 0xC610 ; + .dw 0x0 ; + .dw 0xC610 ; + .dw 0x4000 ; + .dw 0xC610 ; + .dw 0x8000 ; + .dw 0xC610 ; + .dw 0xC000 ; + .dw 0xC611 ; + .dw 0x0 ; + .dw 0xC611 ; + .dw 0x4000 ; + .dw 0xC611 ; + .dw 0x8000 ; + .dw 0xC611 ; + .dw 0xC000 ; + .dw 0xC612 ; + .dw 0x0 ; + .dw 0xC612 ; + .dw 0x4000 ; + .dw 0xC612 ; + .dw 0x8000 ; + .dw 0xC612 ; + .dw 0xC000 ; + .dw 0xC613 ; + .dw 0x0 ; + .dw 0xC613 ; + .dw 0x4000 ; + .dw 0xC613 ; + .dw 0x8000 ; + .dw 0xC613 ; + .dw 0xC000 ; + .dw 0xC614 ; + .dw 0x0 ; + .dw 0xC614 ; + .dw 0x4000 ; + .dw 0xC614 ; + .dw 0x8000 ; + .dw 0xC614 ; + .dw 0xC000 ; + .dw 0xC615 ; + .dw 0x0 ; + .dw 0xC615 ; + .dw 0x4000 ; + .dw 0xC615 ; + .dw 0x8000 ; + .dw 0xC615 ; + .dw 0xC000 ; + .dw 0xC616 ; + .dw 0x0 ; + .dw 0xC616 ; + .dw 0x4000 ; + .dw 0xC616 ; + .dw 0x8000 ; + .dw 0xC616 ; + .dw 0xC000 ; + .dw 0xC617 ; + .dw 0x0 ; + .dw 0xC617 ; + .dw 0x4000 ; + .dw 0xC617 ; + .dw 0x8000 ; + .dw 0xC617 ; + .dw 0xC000 ; + .dw 0xC618 ; + .dw 0x0 ; + .dw 0xC618 ; + .dw 0x4000 ; + .dw 0xC618 ; + .dw 0x8000 ; + .dw 0xC618 ; + .dw 0xC000 ; + .dw 0xC619 ; + .dw 0x0 ; + .dw 0xC619 ; + .dw 0x4000 ; + .dw 0xC619 ; + .dw 0x8000 ; + .dw 0xC619 ; + .dw 0xC000 ; + .dw 0xC61A ; + .dw 0x0 ; + .dw 0xC61A ; + .dw 0x4000 ; + .dw 0xC61A ; + .dw 0x8000 ; + .dw 0xC61A ; + .dw 0xC000 ; + .dw 0xC61B ; + .dw 0x0 ; + .dw 0xC61B ; + .dw 0x4000 ; + .dw 0xC61B ; + .dw 0x8000 ; + .dw 0xC61B ; + .dw 0xC000 ; + .dw 0xC61C ; + .dw 0x0 ; + .dw 0xC61C ; + .dw 0x4000 ; + .dw 0xC61C ; + .dw 0x8000 ; + .dw 0xC61C ; + .dw 0xC000 ; + .dw 0xC61D ; + .dw 0x0 ; + .dw 0xC61D ; + .dw 0x4000 ; + .dw 0xC61D ; + .dw 0x8000 ; + .dw 0xC61D ; + .dw 0xC000 ; + .dw 0xC61E ; + .dw 0x0 ; + .dw 0xC61E ; + .dw 0x4000 ; + .dw 0xC61E ; + .dw 0x8000 ; + .dw 0xC61E ; + .dw 0xC000 ; + .dw 0xC61F ; + .dw 0x0 ; + .dw 0xC61F ; + .dw 0x4000 ; + .dw 0xC61F ; + .dw 0x8000 ; + .dw 0xC61F ; + .dw 0xC000 ; + .dw 0xC608 ; + .dw 0x0 ; + .dw 0xC608 ; + .dw 0x9 ; + .dw 0xC608 ; + .dw 0x12 ; + .dw 0xC608 ; + .dw 0x1B ; + .dw 0xC608 ; + .dw 0x24 ; + .dw 0xC608 ; + .dw 0x2D ; + .dw 0xC608 ; + .dw 0x36 ; + .dw 0xC608 ; + .dw 0x3F ; + .dw 0xC608 ; + .dw 0x4000 ; + .dw 0xC608 ; + .dw 0x4009 ; + .dw 0xC608 ; + .dw 0x4012 ; + .dw 0xC608 ; + .dw 0x401B ; + .dw 0xC608 ; + .dw 0x4024 ; + .dw 0xC608 ; + .dw 0x402D ; + .dw 0xC608 ; + .dw 0x4036 ; + .dw 0xC608 ; + .dw 0x403F ; + .dw 0xC680 ; + .dw 0xC000 ; + .dw 0xC681 ; + .dw 0xC000 ; + .dw 0xC683 ; + .dw 0xC000 ; + .dw 0xC684 ; + .dw 0x0 ; + .dw 0xC684 ; + .dw 0x4000 ; + .dw 0xC684 ; + .dw 0x8000 ; + .dw 0xC684 ; + .dw 0xC000 ; + .dw 0xC685 ; + .dw 0x0 ; + .dw 0xC685 ; + .dw 0x4000 ; + .dw 0xC685 ; + .dw 0x8000 ; + .dw 0xC685 ; + .dw 0xC000 ; + .dw 0xC686 ; + .dw 0x0 ; + .dw 0xC686 ; + .dw 0x4000 ; + .dw 0xC686 ; + .dw 0x8000 ; + .dw 0xC686 ; + .dw 0xC000 ; + .dw 0xC687 ; + .dw 0x0 ; + .dw 0xC687 ; + .dw 0x4000 ; + .dw 0xC687 ; + .dw 0x8000 ; + .dw 0xC687 ; + .dw 0xC000 ; + .dw 0xC688 ; + .dw 0x0 ; + .dw 0xC688 ; + .dw 0x4000 ; + .dw 0xC688 ; + .dw 0x8000 ; + .dw 0xC688 ; + .dw 0xC000 ; + .dw 0xC689 ; + .dw 0x0 ; + .dw 0xC689 ; + .dw 0x4000 ; + .dw 0xC689 ; + .dw 0x8000 ; + .dw 0xC689 ; + .dw 0xC000 ; + .dw 0xC68A ; + .dw 0x0 ; + .dw 0xC68A ; + .dw 0x4000 ; + .dw 0xC68A ; + .dw 0x8000 ; + .dw 0xC68A ; + .dw 0xC000 ; + .dw 0xC68B ; + .dw 0x0 ; + .dw 0xC68B ; + .dw 0x4000 ; + .dw 0xC68B ; + .dw 0x8000 ; + .dw 0xC68B ; + .dw 0xC000 ; + .dw 0xC68C ; + .dw 0x0 ; + .dw 0xC68C ; + .dw 0x4000 ; + .dw 0xC68C ; + .dw 0x8000 ; + .dw 0xC68C ; + .dw 0xC000 ; + .dw 0xC68D ; + .dw 0x0 ; + .dw 0xC68D ; + .dw 0x4000 ; + .dw 0xC68D ; + .dw 0x8000 ; + .dw 0xC68D ; + .dw 0xC000 ; + .dw 0xC68E ; + .dw 0x0 ; + .dw 0xC68E ; + .dw 0x4000 ; + .dw 0xC68E ; + .dw 0x8000 ; + .dw 0xC68E ; + .dw 0xC000 ; + .dw 0xC68F ; + .dw 0x0 ; + .dw 0xC68F ; + .dw 0x4000 ; + .dw 0xC68F ; + .dw 0x8000 ; + .dw 0xC68F ; + .dw 0xC000 ; + .dw 0xC690 ; + .dw 0x0 ; + .dw 0xC690 ; + .dw 0x4000 ; + .dw 0xC690 ; + .dw 0x8000 ; + .dw 0xC690 ; + .dw 0xC000 ; + .dw 0xC691 ; + .dw 0x0 ; + .dw 0xC691 ; + .dw 0x4000 ; + .dw 0xC691 ; + .dw 0x8000 ; + .dw 0xC691 ; + .dw 0xC000 ; + .dw 0xC692 ; + .dw 0x0 ; + .dw 0xC692 ; + .dw 0x4000 ; + .dw 0xC692 ; + .dw 0x8000 ; + .dw 0xC692 ; + .dw 0xC000 ; + .dw 0xC693 ; + .dw 0x0 ; + .dw 0xC693 ; + .dw 0x4000 ; + .dw 0xC693 ; + .dw 0x8000 ; + .dw 0xC693 ; + .dw 0xC000 ; + .dw 0xC694 ; + .dw 0x0 ; + .dw 0xC694 ; + .dw 0x4000 ; + .dw 0xC694 ; + .dw 0x8000 ; + .dw 0xC694 ; + .dw 0xC000 ; + .dw 0xC695 ; + .dw 0x0 ; + .dw 0xC695 ; + .dw 0x4000 ; + .dw 0xC695 ; + .dw 0x8000 ; + .dw 0xC695 ; + .dw 0xC000 ; + .dw 0xC696 ; + .dw 0x0 ; + .dw 0xC696 ; + .dw 0x4000 ; + .dw 0xC696 ; + .dw 0x8000 ; + .dw 0xC696 ; + .dw 0xC000 ; + .dw 0xC697 ; + .dw 0x0 ; + .dw 0xC697 ; + .dw 0x4000 ; + .dw 0xC697 ; + .dw 0x8000 ; + .dw 0xC697 ; + .dw 0xC000 ; + .dw 0xC698 ; + .dw 0x0 ; + .dw 0xC698 ; + .dw 0x4000 ; + .dw 0xC698 ; + .dw 0x8000 ; + .dw 0xC698 ; + .dw 0xC000 ; + .dw 0xC699 ; + .dw 0x0 ; + .dw 0xC699 ; + .dw 0x4000 ; + .dw 0xC699 ; + .dw 0x8000 ; + .dw 0xC699 ; + .dw 0xC000 ; + .dw 0xC69A ; + .dw 0x0 ; + .dw 0xC69A ; + .dw 0x4000 ; + .dw 0xC69A ; + .dw 0x8000 ; + .dw 0xC69A ; + .dw 0xC000 ; + .dw 0xC69B ; + .dw 0x0 ; + .dw 0xC69B ; + .dw 0x4000 ; + .dw 0xC69B ; + .dw 0x8000 ; + .dw 0xC69B ; + .dw 0xC000 ; + .dw 0xC69C ; + .dw 0x0 ; + .dw 0xC69C ; + .dw 0x4000 ; + .dw 0xC69C ; + .dw 0x8000 ; + .dw 0xC69C ; + .dw 0xC000 ; + .dw 0xC69D ; + .dw 0x0 ; + .dw 0xC69D ; + .dw 0x4000 ; + .dw 0xC69D ; + .dw 0x8000 ; + .dw 0xC69D ; + .dw 0xC000 ; + .dw 0xC69E ; + .dw 0x0 ; + .dw 0xC69E ; + .dw 0x4000 ; + .dw 0xC69E ; + .dw 0x8000 ; + .dw 0xC69E ; + .dw 0xC000 ; + .dw 0xC69F ; + .dw 0x0 ; + .dw 0xC69F ; + .dw 0x4000 ; + .dw 0xC69F ; + .dw 0x8000 ; + .dw 0xC69F ; + .dw 0xC000 ; + .dw 0xC008 ; + .dw 0x0 ; + .dw 0xC008 ; + .dw 0x40 ; + .dw 0xC008 ; + .dw 0xC0 ; + .dw 0xC008 ; + .dw 0x140 ; + .dw 0xC008 ; + .dw 0x1C0 ; + .dw 0xC020 ; + .dw 0x0 ; + .dw 0xC040 ; + .dw 0x0 ; + .dw 0xC0A0 ; + .dw 0x0 ; + .dw 0xC0C0 ; + .dw 0x0 ; + .dw 0xC0E0 ; + .dw 0x0 ; + .dw 0xC120 ; + .dw 0x0 ; + .dw 0xC140 ; + .dw 0x0 ; + .dw 0xC160 ; + .dw 0x0 ; + .dw 0xC180 ; + .dw 0x0 ; + .dw 0xC1A0 ; + .dw 0x0 ; + .dw 0xC1C0 ; + .dw 0x0 ; + .dw 0xC1E0 ; + .dw 0x0 ; + .dw 0xC060 ; + .dw 0x2000 ; + .dw 0xC0E0 ; + .dw 0x2000 ; + .dw 0xC140 ; + .dw 0x2000 ; + .dw 0xC1A0 ; + .dw 0x2000 ; + .dw 0xC1C0 ; + .dw 0x2000 ; + .dw 0xC1E0 ; + .dw 0x2000 ; + .dw 0xC064 ; + .dw 0x0 ; + .dw 0xC0E4 ; + .dw 0x0 ; + .dw 0xC144 ; + .dw 0x0 ; + .dw 0xC1A4 ; + .dw 0x0 ; + .dw 0xC1C4 ; + .dw 0x0 ; + .dw 0xC1E4 ; + .dw 0x0 ; + .dw 0xC064 ; + .dw 0x2000 ; + .dw 0xC0E4 ; + .dw 0x2000 ; + .dw 0xC144 ; + .dw 0x2000 ; + .dw 0xC1A4 ; + .dw 0x2000 ; + .dw 0xC1C4 ; + .dw 0x2000 ; + .dw 0xC1E4 ; + .dw 0x2000 ; + .dw 0xC048 ; + .dw 0x2000 ; + .dw 0xC068 ; + .dw 0x2000 ; + .dw 0xC0A8 ; + .dw 0x2000 ; + .dw 0xC0C8 ; + .dw 0x2000 ; + .dw 0xC0E8 ; + .dw 0x2000 ; + .dw 0xC148 ; + .dw 0x2000 ; + .dw 0xC168 ; + .dw 0x2000 ; + .dw 0xC188 ; + .dw 0x2000 ; + .dw 0xC1A8 ; + .dw 0x2000 ; + .dw 0xC1C8 ; + .dw 0x2000 ; + .dw 0xC1E8 ; + .dw 0x2000 ; + .dw 0xC04C ; + .dw 0x0 ; + .dw 0xC06C ; + .dw 0x0 ; + .dw 0xC0AC ; + .dw 0x0 ; + .dw 0xC0CC ; + .dw 0x0 ; + .dw 0xC0EC ; + .dw 0x0 ; + .dw 0xC14C ; + .dw 0x0 ; + .dw 0xC16C ; + .dw 0x0 ; + .dw 0xC18C ; + .dw 0x0 ; + .dw 0xC1AC ; + .dw 0x0 ; + .dw 0xC1CC ; + .dw 0x0 ; + .dw 0xC1EC ; + .dw 0x0 ; + .dw 0xC04C ; + .dw 0x2000 ; + .dw 0xC06C ; + .dw 0x2000 ; + .dw 0xC0AC ; + .dw 0x2000 ; + .dw 0xC0CC ; + .dw 0x2000 ; + .dw 0xC0EC ; + .dw 0x2000 ; + .dw 0xC14C ; + .dw 0x2000 ; + .dw 0xC16C ; + .dw 0x2000 ; + .dw 0xC18C ; + .dw 0x2000 ; + .dw 0xC1AC ; + .dw 0x2000 ; + .dw 0xC1CC ; + .dw 0x2000 ; + .dw 0xC1EC ; + .dw 0x2000 ; + .dw 0xC20C ; + .dw 0x2040 ; + .dw 0xC20C ; + .dw 0x20C0 ; + .dw 0xC20C ; + .dw 0x2140 ; + .dw 0xC20C ; + .dw 0x21C0 ; + .dw 0xC248 ; + .dw 0x2000 ; + .dw 0xC268 ; + .dw 0x2000 ; + .dw 0xC2A8 ; + .dw 0x2000 ; + .dw 0xC2C8 ; + .dw 0x2000 ; + .dw 0xC2E8 ; + .dw 0x2000 ; + .dw 0xC348 ; + .dw 0x2000 ; + .dw 0xC368 ; + .dw 0x2000 ; + .dw 0xC388 ; + .dw 0x2000 ; + .dw 0xC3A8 ; + .dw 0x2000 ; + .dw 0xC3C8 ; + .dw 0x2000 ; + .dw 0xC3E8 ; + .dw 0x2000 ; + .dw 0xC24C ; + .dw 0x0 ; + .dw 0xC26C ; + .dw 0x0 ; + .dw 0xC2AC ; + .dw 0x0 ; + .dw 0xC2CC ; + .dw 0x0 ; + .dw 0xC2EC ; + .dw 0x0 ; + .dw 0xC34C ; + .dw 0x0 ; + .dw 0xC36C ; + .dw 0x0 ; + .dw 0xC38C ; + .dw 0x0 ; + .dw 0xC3AC ; + .dw 0x0 ; + .dw 0xC3CC ; + .dw 0x0 ; + .dw 0xC3EC ; + .dw 0x0 ; + .dw 0xC24C ; + .dw 0x2000 ; + .dw 0xC26C ; + .dw 0x2000 ; + .dw 0xC2AC ; + .dw 0x2000 ; + .dw 0xC2CC ; + .dw 0x2000 ; + .dw 0xC2EC ; + .dw 0x2000 ; + .dw 0xC34C ; + .dw 0x2000 ; + .dw 0xC36C ; + .dw 0x2000 ; + .dw 0xC38C ; + .dw 0x2000 ; + .dw 0xC3AC ; + .dw 0x2000 ; + .dw 0xC3CC ; + .dw 0x2000 ; + .dw 0xC3EC ; + .dw 0x2000 ; + .dw 0xC20D ; + .dw 0x2800 ; + .dw 0xC20E ; + .dw 0x2800 ; + .dw 0xC20F ; + .dw 0x2800 ; + .dw 0xC20D ; + .dw 0x3000 ; + .dw 0xC20E ; + .dw 0x3000 ; + .dw 0xC20F ; + .dw 0x3000 ; + .dw 0xC20D ; + .dw 0x3800 ; + .dw 0xC20E ; + .dw 0x3800 ; + .dw 0xC20F ; + .dw 0x3800 ; + .dw 0xC200 ; + .dw 0x0 ; + .dw 0xC264 ; + .dw 0x2000 ; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +CHECKREG(r5, 2871); // count of all 16 bit UI's. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 32 bit illegal opcode handler - skips bad instruction + + // handler MADE LEAN and destructive so test runs more quckly + // se_undefinedinstruction1.dsp tests using a "nice" handler + +// [--sp] = ASTAT; // save what we damage +// [--sp] = (r7 - r6); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + + // Also allow 0x22 for illegal instruction combinations (parallel) +R6 = 0x22; +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; + +dbg_fail; + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + R7 += 4; // skip offending 32 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: +// (r7 - r6) = [sp++]; +// ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_undefinedinstruction4.S b/sim/testsuite/sim/bfin/se_undefinedinstruction4.S new file mode 100644 index 0000000..b212c37 --- /dev/null +++ b/sim/testsuite/sim/bfin/se_undefinedinstruction4.S @@ -0,0 +1,1298 @@ +//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction4/se_undefinedinstruction4.dsp +// Description: 64 bit special cases Undefined Instructions in Supervisor Mode +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x10 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + A0 = 0; // reset accumulators + A1 = 0; + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests + [ -- SP ] = RETI; // enable interrupts in supervisor mode + + // **** YOUR CODE GOES HERE **** +// Starting 64bit section COUNT = 6406 + .dw 0xCF00 ; + .dw 0xFA4D ; + .dw 0x4973 ; + .dw 0x434D ; + .dw 0xCF01 ; + .dw 0x3CAF ; + .dw 0xE7F7 ; + .dw 0xACAD ; + .dw 0xCF02 ; + .dw 0xC9A3 ; + .dw 0x705D ; + .dw 0x8EFF ; + .dw 0xCF03 ; + .dw 0x242D ; + .dw 0x26ED ; + .dw 0x1C67 ; + .dw 0xCF04 ; + .dw 0xBC83 ; + .dw 0x18BB ; + .dw 0xEF95 ; + .dw 0xCF05 ; + .dw 0xDFA7 ; + .dw 0x6AD9 ; + .dw 0x7FEF ; + .dw 0xCF06 ; + .dw 0x71F3 ; + .dw 0x19CB ; + .dw 0x1F69 ; + .dw 0xCF07 ; + .dw 0xA117 ; + .dw 0x23ED ; + .dw 0xE509 ; + .dw 0xCF08 ; + .dw 0x4DF9 ; + .dw 0x31C3 ; + .dw 0x5207 ; + .dw 0xCF09 ; + .dw 0xF35D ; + .dw 0x998F ; + .dw 0xC1A7 ; + .dw 0xCF0A ; + .dw 0xA7FF ; + .dw 0x73D ; + .dw 0x4ACB ; + .dw 0xCF0B ; + .dw 0xEE29 ; + .dw 0xAAE7 ; + .dw 0x3FD3 ; + .dw 0xCF0C ; + .dw 0xD3B5 ; + .dw 0x5549 ; + .dw 0xBCB7 ; + .dw 0xCF0D ; + .dw 0xF0B7 ; + .dw 0xB91B ; + .dw 0xC01F ; + .dw 0xCF0E ; + .dw 0xC169 ; + .dw 0x3D1F ; + .dw 0xB96B ; + .dw 0xCF0F ; + .dw 0x7CD3 ; + .dw 0xFD95 ; + .dw 0x2EA1 ; + .dw 0xCF10 ; + .dw 0x8907 ; + .dw 0x6013 ; + .dw 0x467D ; + .dw 0xCF11 ; + .dw 0x7F67 ; + .dw 0xFC1F ; + .dw 0x6611 ; + .dw 0xCF12 ; + .dw 0x1BB3 ; + .dw 0xCFE1 ; + .dw 0xF609 ; + .dw 0xCF13 ; + .dw 0x6AF1 ; + .dw 0xC229 ; + .dw 0x8009 ; + .dw 0xCF14 ; + .dw 0xF619 ; + .dw 0xF2C9 ; + .dw 0xF8C7 ; + .dw 0xCF15 ; + .dw 0xE413 ; + .dw 0x99F3 ; + .dw 0x7919 ; + .dw 0xCF16 ; + .dw 0x5E8B ; + .dw 0xCA1 ; + .dw 0xED71 ; + .dw 0xCF17 ; + .dw 0x3FBB ; + .dw 0x221B ; + .dw 0xDA89 ; + .dw 0xCF18 ; + .dw 0xDFED ; + .dw 0x1565 ; + .dw 0x12DB ; + .dw 0xCF19 ; + .dw 0x95FD ; + .dw 0xB71F ; + .dw 0xB9B ; + .dw 0xCF1A ; + .dw 0xAB8F ; + .dw 0xC14F ; + .dw 0xD777 ; + .dw 0xCF1B ; + .dw 0x9427 ; + .dw 0x2E69 ; + .dw 0x5F23 ; + .dw 0xCF1C ; + .dw 0xB9F1 ; + .dw 0xFE17 ; + .dw 0x6AA1 ; + .dw 0xCF1D ; + .dw 0x642B ; + .dw 0x676B ; + .dw 0xCA2B ; + .dw 0xCF1E ; + .dw 0x4399 ; + .dw 0x8C55 ; + .dw 0x5187 ; + .dw 0xCF1F ; + .dw 0xCED5 ; + .dw 0x9163 ; + .dw 0x4B95 ; + .dw 0xCF20 ; + .dw 0xE0F9 ; + .dw 0xA3AF ; + .dw 0x72EB ; + .dw 0xCF21 ; + .dw 0x120B ; + .dw 0x9161 ; + .dw 0x4C73 ; + .dw 0xCF22 ; + .dw 0xA97F ; + .dw 0x9BC3 ; + .dw 0xF2A9 ; + .dw 0xCF23 ; + .dw 0x9B6F ; + .dw 0x15F5 ; + .dw 0x83F3 ; + .dw 0xCF24 ; + .dw 0x67D3 ; + .dw 0x4385 ; + .dw 0xEF37 ; + .dw 0xCF25 ; + .dw 0xD3A3 ; + .dw 0xFB5B ; + .dw 0x119D ; + .dw 0xCF26 ; + .dw 0xCA67 ; + .dw 0xC3F5 ; + .dw 0x2109 ; + .dw 0xCF27 ; + .dw 0x459B ; + .dw 0xC69 ; + .dw 0x6BD3 ; + .dw 0xCF28 ; + .dw 0xBD4B ; + .dw 0x82E1 ; + .dw 0xDD07 ; + .dw 0xCF29 ; + .dw 0x9131 ; + .dw 0x4A0B ; + .dw 0x503B ; + .dw 0xCF2A ; + .dw 0x3383 ; + .dw 0x55B5 ; + .dw 0x7107 ; + .dw 0xCF2B ; + .dw 0x9F5D ; + .dw 0x14B3 ; + .dw 0xF6FF ; + .dw 0xCF2C ; + .dw 0xF3B1 ; + .dw 0x53DF ; + .dw 0x9A93 ; + .dw 0xCF2D ; + .dw 0x5A59 ; + .dw 0x3879 ; + .dw 0x41AD ; + .dw 0xCF2E ; + .dw 0xDD63 ; + .dw 0x9BEF ; + .dw 0x55B3 ; + .dw 0xCF2F ; + .dw 0x9B01 ; + .dw 0x563D ; + .dw 0x598B ; + .dw 0xCF30 ; + .dw 0xF1E3 ; + .dw 0x45E1 ; + .dw 0xD327 ; + .dw 0xCF31 ; + .dw 0xF0C7 ; + .dw 0xD19D ; + .dw 0x110D ; + .dw 0xCF32 ; + .dw 0x94B7 ; + .dw 0x68CF ; + .dw 0x6ADB ; + .dw 0xCF33 ; + .dw 0x4083 ; + .dw 0xAD23 ; + .dw 0x3F8B ; + .dw 0xCF34 ; + .dw 0x55D3 ; + .dw 0x6969 ; + .dw 0x38D9 ; + .dw 0xCF35 ; + .dw 0xD261 ; + .dw 0xF353 ; + .dw 0x1595 ; + .dw 0xCF36 ; + .dw 0x8897 ; + .dw 0x9A6D ; + .dw 0x2093 ; + .dw 0xCF37 ; + .dw 0x2673 ; + .dw 0xD509 ; + .dw 0xF435 ; + .dw 0xCF38 ; + .dw 0x5093 ; + .dw 0x6F8F ; + .dw 0x93D9 ; + .dw 0xCF39 ; + .dw 0xAAE1 ; + .dw 0xE2F1 ; + .dw 0x807F ; + .dw 0xCF3A ; + .dw 0x64D ; + .dw 0xFEF7 ; + .dw 0x103D ; + .dw 0xCF3B ; + .dw 0x1665 ; + .dw 0x1959 ; + .dw 0x608F ; + .dw 0xCF3C ; + .dw 0x43D9 ; + .dw 0x2CDD ; + .dw 0x2F3F ; + .dw 0xCF3D ; + .dw 0x950B ; + .dw 0x3B49 ; + .dw 0x2681 ; + .dw 0xCF3E ; + .dw 0xEA9D ; + .dw 0x8053 ; + .dw 0xC311 ; + .dw 0xCF3F ; + .dw 0x4D3 ; + .dw 0x9311 ; + .dw 0x498B ; + .dw 0xCF40 ; + .dw 0x6909 ; + .dw 0x27C3 ; + .dw 0x2B45 ; + .dw 0xCF41 ; + .dw 0x1347 ; + .dw 0xFC37 ; + .dw 0x8C9D ; + .dw 0xCF42 ; + .dw 0xD08F ; + .dw 0xFF4B ; + .dw 0x3223 ; + .dw 0xCF43 ; + .dw 0x485 ; + .dw 0x7C05 ; + .dw 0xB5BB ; + .dw 0xCF44 ; + .dw 0x49BB ; + .dw 0x5A71 ; + .dw 0xBD1B ; + .dw 0xCF45 ; + .dw 0x27D9 ; + .dw 0x39B ; + .dw 0xE099 ; + .dw 0xCF46 ; + .dw 0x85AF ; + .dw 0xC637 ; + .dw 0xC7EF ; + .dw 0xCF47 ; + .dw 0x5D7B ; + .dw 0x9FAF ; + .dw 0xE277 ; + .dw 0xCF48 ; + .dw 0x51C9 ; + .dw 0xD04B ; + .dw 0xE427 ; + .dw 0xCF49 ; + .dw 0x747B ; + .dw 0xB7F5 ; + .dw 0x4E5 ; + .dw 0xCF4A ; + .dw 0xCBDF ; + .dw 0xFB21 ; + .dw 0x2B5B ; + .dw 0xCF4B ; + .dw 0x6F59 ; + .dw 0x716D ; + .dw 0xB07B ; + .dw 0xCF4C ; + .dw 0x42CB ; + .dw 0x46CB ; + .dw 0x9CD5 ; + .dw 0xCF4D ; + .dw 0xC98B ; + .dw 0x2C5D ; + .dw 0x57FF ; + .dw 0xCF4E ; + .dw 0xF097 ; + .dw 0xF96D ; + .dw 0x9C45 ; + .dw 0xCF4F ; + .dw 0x8743 ; + .dw 0xD053 ; + .dw 0xF01F ; + .dw 0xCF50 ; + .dw 0xD12D ; + .dw 0x79ED ; + .dw 0x18D7 ; + .dw 0xCF51 ; + .dw 0xCB3 ; + .dw 0x860F ; + .dw 0x5F57 ; + .dw 0xCF52 ; + .dw 0x41B7 ; + .dw 0xFB03 ; + .dw 0x2985 ; + .dw 0xCF53 ; + .dw 0x514F ; + .dw 0x6F ; + .dw 0x74F1 ; + .dw 0xCF54 ; + .dw 0x32AF ; + .dw 0x4413 ; + .dw 0x4F1 ; + .dw 0xCF55 ; + .dw 0xDF13 ; + .dw 0xEB77 ; + .dw 0xFDC7 ; + .dw 0xCF56 ; + .dw 0xE7BF ; + .dw 0xF8FB ; + .dw 0x8881 ; + .dw 0xCF57 ; + .dw 0xD71 ; + .dw 0xE18B ; + .dw 0x58E1 ; + .dw 0xCF58 ; + .dw 0xE66B ; + .dw 0x396B ; + .dw 0x6441 ; + .dw 0xCF59 ; + .dw 0xEAE5 ; + .dw 0xC4B9 ; + .dw 0x5D65 ; + .dw 0xCF5A ; + .dw 0x2DA9 ; + .dw 0x2BBB ; + .dw 0xD621 ; + .dw 0xCF5B ; + .dw 0x2FD1 ; + .dw 0xEB81 ; + .dw 0x56F3 ; + .dw 0xCF5C ; + .dw 0x7E67 ; + .dw 0xE6E1 ; + .dw 0x907 ; + .dw 0xCF5D ; + .dw 0x40A3 ; + .dw 0x95B3 ; + .dw 0x3501 ; + .dw 0xCF5E ; + .dw 0xBE25 ; + .dw 0x12A5 ; + .dw 0x96D ; + .dw 0xCF5F ; + .dw 0x94C9 ; + .dw 0xF7F7 ; + .dw 0xA553 ; + .dw 0xCF60 ; + .dw 0xB291 ; + .dw 0x5C7D ; + .dw 0x32ED ; + .dw 0xCF61 ; + .dw 0xABB5 ; + .dw 0x3987 ; + .dw 0x90FB ; + .dw 0xCF62 ; + .dw 0xDE61 ; + .dw 0x6B43 ; + .dw 0x5F83 ; + .dw 0xCF63 ; + .dw 0xF03D ; + .dw 0x61AF ; + .dw 0x3713 ; + .dw 0xCF64 ; + .dw 0x854D ; + .dw 0x2B4B ; + .dw 0x5ACB ; + .dw 0xCF65 ; + .dw 0x669B ; + .dw 0xC7A9 ; + .dw 0xC7B5 ; + .dw 0xCF66 ; + .dw 0x2E5D ; + .dw 0xFFE5 ; + .dw 0x8929 ; + .dw 0xCF67 ; + .dw 0xA089 ; + .dw 0x8151 ; + .dw 0xCD41 ; + .dw 0xCF68 ; + .dw 0xC17F ; + .dw 0x7ECF ; + .dw 0xB3F9 ; + .dw 0xCF69 ; + .dw 0x1689 ; + .dw 0xEA61 ; + .dw 0xC17B ; + .dw 0xCF6A ; + .dw 0xF6A1 ; + .dw 0xB5D1 ; + .dw 0xE1D5 ; + .dw 0xCF6B ; + .dw 0x8CEB ; + .dw 0xFA5 ; + .dw 0xBF9B ; + .dw 0xCF6C ; + .dw 0x9A11 ; + .dw 0x79DB ; + .dw 0x6B09 ; + .dw 0xCF6D ; + .dw 0x769B ; + .dw 0xEED1 ; + .dw 0x3BE3 ; + .dw 0xCF6E ; + .dw 0x8B95 ; + .dw 0xC2E9 ; + .dw 0x782D ; + .dw 0xCF6F ; + .dw 0x3763 ; + .dw 0x756B ; + .dw 0xE4B1 ; + .dw 0xCF70 ; + .dw 0xB2F5 ; + .dw 0x7F09 ; + .dw 0x2A1B ; + .dw 0xCF71 ; + .dw 0x9A79 ; + .dw 0x5685 ; + .dw 0x30BF ; + .dw 0xCF72 ; + .dw 0xCE41 ; + .dw 0x72D1 ; + .dw 0x301B ; + .dw 0xCF73 ; + .dw 0xAA27 ; + .dw 0x909B ; + .dw 0x818D ; + .dw 0xCF74 ; + .dw 0x5BB9 ; + .dw 0x8C95 ; + .dw 0xEA9F ; + .dw 0xCF75 ; + .dw 0x3079 ; + .dw 0x3273 ; + .dw 0x87F ; + .dw 0xCF76 ; + .dw 0x5297 ; + .dw 0x639B ; + .dw 0xC64B ; + .dw 0xCF77 ; + .dw 0x6883 ; + .dw 0xF731 ; + .dw 0xA8DF ; + .dw 0xCF78 ; + .dw 0x4387 ; + .dw 0x53CB ; + .dw 0x9CA1 ; + .dw 0xCF79 ; + .dw 0xAB55 ; + .dw 0xF8B ; + .dw 0xC01D ; + .dw 0xCF7A ; + .dw 0x3335 ; + .dw 0xA1EB ; + .dw 0xFD35 ; + .dw 0xCF7B ; + .dw 0xB3D ; + .dw 0x3F6B ; + .dw 0xF1A1 ; + .dw 0xCF7C ; + .dw 0x6EA9 ; + .dw 0x33F3 ; + .dw 0xAB8B ; + .dw 0xCF7D ; + .dw 0xBB41 ; + .dw 0xBCB7 ; + .dw 0xAA7D ; + .dw 0xCF7E ; + .dw 0x1ABD ; + .dw 0x8C9F ; + .dw 0xBBA9 ; + .dw 0xCF7F ; + .dw 0xB089 ; + .dw 0x55A3 ; + .dw 0xED41 ; + .dw 0xCF80 ; + .dw 0xB59D ; + .dw 0xC0AD ; + .dw 0xE873 ; + .dw 0xCF81 ; + .dw 0xFEA7 ; + .dw 0xB265 ; + .dw 0xF55F ; + .dw 0xCF82 ; + .dw 0x8A87 ; + .dw 0xE7F9 ; + .dw 0x64D3 ; + .dw 0xCF83 ; + .dw 0xE769 ; + .dw 0x6783 ; + .dw 0x4547 ; + .dw 0xCF84 ; + .dw 0x9597 ; + .dw 0xFBE9 ; + .dw 0xE1DD ; + .dw 0xCF85 ; + .dw 0x5239 ; + .dw 0x6397 ; + .dw 0x99C1 ; + .dw 0xCF86 ; + .dw 0xE6FF ; + .dw 0x84B ; + .dw 0x31C7 ; + .dw 0xCF87 ; + .dw 0x3E93 ; + .dw 0x6CDD ; + .dw 0xE883 ; + .dw 0xCF88 ; + .dw 0x9A81 ; + .dw 0xEB3D ; + .dw 0x310B ; + .dw 0xCF89 ; + .dw 0xA8AF ; + .dw 0x405D ; + .dw 0xDFC7 ; + .dw 0xCF8A ; + .dw 0x515B ; + .dw 0x7C13 ; + .dw 0xD483 ; + .dw 0xCF8B ; + .dw 0x1EE3 ; + .dw 0xD5E9 ; + .dw 0x2FAD ; + .dw 0xCF8C ; + .dw 0x2A93 ; + .dw 0xB0E1 ; + .dw 0xC4C1 ; + .dw 0xCF8D ; + .dw 0xD1DD ; + .dw 0xB1E7 ; + .dw 0x1E29 ; + .dw 0xCF8E ; + .dw 0xD6ED ; + .dw 0x1DB1 ; + .dw 0x2C7F ; + .dw 0xCF8F ; + .dw 0x1935 ; + .dw 0x6711 ; + .dw 0x618D ; + .dw 0xCF90 ; + .dw 0xFB4D ; + .dw 0xD003 ; + .dw 0xB185 ; + .dw 0xCF91 ; + .dw 0x1969 ; + .dw 0xD80F ; + .dw 0xDD13 ; + .dw 0xCF92 ; + .dw 0xFDE7 ; + .dw 0xF487 ; + .dw 0x54AB ; + .dw 0xCF93 ; + .dw 0x4FDB ; + .dw 0xCA39 ; + .dw 0x7EAF ; + .dw 0xCF94 ; + .dw 0xF805 ; + .dw 0xC4BF ; + .dw 0x8F77 ; + .dw 0xCF95 ; + .dw 0x24E3 ; + .dw 0x5055 ; + .dw 0x491 ; + .dw 0xCF96 ; + .dw 0x37A9 ; + .dw 0xCD9D ; + .dw 0xD301 ; + .dw 0xCF97 ; + .dw 0x2379 ; + .dw 0xDD89 ; + .dw 0xBC7B ; + .dw 0xCF98 ; + .dw 0xE1F3 ; + .dw 0x977F ; + .dw 0xED8B ; + .dw 0xCF99 ; + .dw 0xF983 ; + .dw 0xCE75 ; + .dw 0x3E75 ; + .dw 0xCF9A ; + .dw 0x4081 ; + .dw 0xF3D5 ; + .dw 0x3185 ; + .dw 0xCF9B ; + .dw 0xCB77 ; + .dw 0x47AD ; + .dw 0x97E9 ; + .dw 0xCF9C ; + .dw 0x71AF ; + .dw 0x93E1 ; + .dw 0xE25B ; + .dw 0xCF9D ; + .dw 0x9139 ; + .dw 0xCE65 ; + .dw 0x33C3 ; + .dw 0xCF9E ; + .dw 0xF4F5 ; + .dw 0xEF8D ; + .dw 0xC8D5 ; + .dw 0xCF9F ; + .dw 0x1E1 ; + .dw 0x59A7 ; + .dw 0xE7A1 ; + .dw 0xCFA0 ; + .dw 0x4241 ; + .dw 0xCB25 ; + .dw 0x4265 ; + .dw 0xCFA1 ; + .dw 0xE769 ; + .dw 0x27E1 ; + .dw 0xCD97 ; + .dw 0xCFA2 ; + .dw 0xA491 ; + .dw 0xB5C1 ; + .dw 0x427 ; + .dw 0xCFA3 ; + .dw 0x6AD7 ; + .dw 0xC611 ; + .dw 0xD5AB ; + .dw 0xCFA4 ; + .dw 0x4DA9 ; + .dw 0x8A15 ; + .dw 0x83DD ; + .dw 0xCFA5 ; + .dw 0xE503 ; + .dw 0xCB71 ; + .dw 0x2189 ; + .dw 0xCFA6 ; + .dw 0x6A27 ; + .dw 0x2EBB ; + .dw 0xE6D9 ; + .dw 0xCFA7 ; + .dw 0xDF6B ; + .dw 0x35E5 ; + .dw 0x288D ; + .dw 0xCFA8 ; + .dw 0x42DD ; + .dw 0x6A67 ; + .dw 0xD7F1 ; + .dw 0xCFA9 ; + .dw 0x143B ; + .dw 0x70F9 ; + .dw 0x319D ; + .dw 0xCFAA ; + .dw 0x919B ; + .dw 0x7C3B ; + .dw 0x1B7B ; + .dw 0xCFAB ; + .dw 0x4413 ; + .dw 0x42CB ; + .dw 0xC3FF ; + .dw 0xCFAC ; + .dw 0x7D61 ; + .dw 0x27AB ; + .dw 0x818B ; + .dw 0xCFAD ; + .dw 0x839F ; + .dw 0x7FB1 ; + .dw 0x27A3 ; + .dw 0xCFAE ; + .dw 0x932D ; + .dw 0xE719 ; + .dw 0x5449 ; + .dw 0xCFAF ; + .dw 0x1289 ; + .dw 0xDED7 ; + .dw 0xC905 ; + .dw 0xCFB0 ; + .dw 0xE641 ; + .dw 0xDFAD ; + .dw 0xF1A5 ; + .dw 0xCFB1 ; + .dw 0xC0D1 ; + .dw 0xF7BD ; + .dw 0x3423 ; + .dw 0xCFB2 ; + .dw 0xAC39 ; + .dw 0xDC73 ; + .dw 0x4545 ; + .dw 0xCFB3 ; + .dw 0x3F39 ; + .dw 0xB1D9 ; + .dw 0x3DA7 ; + .dw 0xCFB4 ; + .dw 0x86A1 ; + .dw 0xE663 ; + .dw 0xB105 ; + .dw 0xCFB5 ; + .dw 0x52A1 ; + .dw 0xA52D ; + .dw 0xB8C7 ; + .dw 0xCFB6 ; + .dw 0x9D8B ; + .dw 0xE251 ; + .dw 0xFFB3 ; + .dw 0xCFB7 ; + .dw 0xA225 ; + .dw 0x7425 ; + .dw 0xA407 ; + .dw 0xCFB8 ; + .dw 0x13C3 ; + .dw 0xD553 ; + .dw 0x9F8F ; + .dw 0xCFB9 ; + .dw 0x9ABF ; + .dw 0x6487 ; + .dw 0xE63D ; + .dw 0xCFBA ; + .dw 0x971B ; + .dw 0xEBCD ; + .dw 0xF725 ; + .dw 0xCFBB ; + .dw 0x8B4F ; + .dw 0xCED3 ; + .dw 0x691B ; + .dw 0xCFBC ; + .dw 0x3C89 ; + .dw 0xFE7B ; + .dw 0x9105 ; + .dw 0xCFBD ; + .dw 0x86D9 ; + .dw 0xC0CD ; + .dw 0x75A5 ; + .dw 0xCFBE ; + .dw 0xD961 ; + .dw 0xF4C1 ; + .dw 0x7801 ; + .dw 0xCFBF ; + .dw 0xAAA3 ; + .dw 0xC993 ; + .dw 0x92C5 ; + .dw 0xCFC0 ; + .dw 0x8D ; + .dw 0xEAB5 ; + .dw 0xCF55 ; + .dw 0xCFC1 ; + .dw 0xF94D ; + .dw 0xB307 ; + .dw 0xA575 ; + .dw 0xCFC2 ; + .dw 0x140F ; + .dw 0x4CE7 ; + .dw 0xD78B ; + .dw 0xCFC3 ; + .dw 0xF359 ; + .dw 0x4DE7 ; + .dw 0x958B ; + .dw 0xCFC4 ; + .dw 0xD893 ; + .dw 0xBA3 ; + .dw 0x8A5D ; + .dw 0xCFC5 ; + .dw 0x5149 ; + .dw 0xCB4B ; + .dw 0x21E3 ; + .dw 0xCFC6 ; + .dw 0xA65 ; + .dw 0x7A85 ; + .dw 0x2571 ; + .dw 0xCFC7 ; + .dw 0xA2DF ; + .dw 0xC7F9 ; + .dw 0xB9AF ; + .dw 0xCFC8 ; + .dw 0xF8A3 ; + .dw 0x491D ; + .dw 0xBD37 ; + .dw 0xCFC9 ; + .dw 0xFA7B ; + .dw 0x8B45 ; + .dw 0xCD ; + .dw 0xCFCA ; + .dw 0x84F3 ; + .dw 0x1C97 ; + .dw 0xA6C7 ; + .dw 0xCFCB ; + .dw 0x1349 ; + .dw 0x6CD9 ; + .dw 0xF7E3 ; + .dw 0xCFCC ; + .dw 0x738D ; + .dw 0x9209 ; + .dw 0x90F9 ; + .dw 0xCFCD ; + .dw 0x6C31 ; + .dw 0x3A3D ; + .dw 0x7921 ; + .dw 0xCFCE ; + .dw 0x18E5 ; + .dw 0xB46F ; + .dw 0xE29B ; + .dw 0xCFCF ; + .dw 0x812D ; + .dw 0x2E4B ; + .dw 0xB56B ; + .dw 0xCFD0 ; + .dw 0x87E5 ; + .dw 0x18D5 ; + .dw 0xC509 ; + .dw 0xCFD1 ; + .dw 0x8005 ; + .dw 0xFAA1 ; + .dw 0x7DC1 ; + .dw 0xCFD2 ; + .dw 0xCCC5 ; + .dw 0xBEE7 ; + .dw 0x87FB ; + .dw 0xCFD3 ; + .dw 0x6D11 ; + .dw 0xE40B ; + .dw 0x47C5 ; + .dw 0xCFD4 ; + .dw 0xDE9F ; + .dw 0x6351 ; + .dw 0x24DB ; + .dw 0xCFD5 ; + .dw 0x8803 ; + .dw 0x690D ; + .dw 0xE3F5 ; + .dw 0xCFD6 ; + .dw 0x22C9 ; + .dw 0x505 ; + .dw 0xF573 ; + .dw 0xCFD7 ; + .dw 0xC055 ; + .dw 0xB295 ; + .dw 0xA7D3 ; + .dw 0xCFD8 ; + .dw 0x305 ; + .dw 0xD61D ; + .dw 0x933B ; + .dw 0xCFD9 ; + .dw 0xC59 ; + .dw 0x8CD1 ; + .dw 0x3D47 ; + .dw 0xCFDA ; + .dw 0x9095 ; + .dw 0x8C21 ; + .dw 0xAA23 ; + .dw 0xCFDB ; + .dw 0x5D97 ; + .dw 0x376F ; + .dw 0x3C85 ; + .dw 0xCFDC ; + .dw 0xDC49 ; + .dw 0xE393 ; + .dw 0xB31B ; + .dw 0xCFDD ; + .dw 0x9871 ; + .dw 0x61FF ; + .dw 0xCF1 ; + .dw 0xCFDE ; + .dw 0xEC8D ; + .dw 0xD8B ; + .dw 0x683D ; + .dw 0xCFDF ; + .dw 0x449D ; + .dw 0x82F5 ; + .dw 0x24FF ; + .dw 0xCFE0 ; + .dw 0x708D ; + .dw 0x8629 ; + .dw 0xB5D3 ; + .dw 0xCFE1 ; + .dw 0x7FA3 ; + .dw 0xC4EB ; + .dw 0x80C7 ; + .dw 0xCFE2 ; + .dw 0xD88F ; + .dw 0x5DBF ; + .dw 0x5113 ; + .dw 0xCFE3 ; + .dw 0xF1BD ; + .dw 0x6797 ; + .dw 0xEA3B ; + .dw 0xCFE4 ; + .dw 0xB965 ; + .dw 0x2E63 ; + .dw 0x56ED ; + .dw 0xCFE5 ; + .dw 0x15B ; + .dw 0x733 ; + .dw 0x5599 ; + .dw 0xCFE6 ; + .dw 0xB249 ; + .dw 0xAAFB ; + .dw 0xC29B ; + .dw 0xCFE7 ; + .dw 0x20C1 ; + .dw 0x26A9 ; + .dw 0x39 ; + .dw 0xCFE8 ; + .dw 0xD1E5 ; + .dw 0xCC2D ; + .dw 0x8D6D ; + .dw 0xCFE9 ; + .dw 0xB4C3 ; + .dw 0xF651 ; + .dw 0xF25 ; + .dw 0xCFEA ; + .dw 0x10F3 ; + .dw 0xFB75 ; + .dw 0x3E79 ; + .dw 0xCFEB ; + .dw 0x9B55 ; + .dw 0x2A7 ; + .dw 0xFEAB ; + .dw 0xCFEC ; + .dw 0x4623 ; + .dw 0x1BCD ; + .dw 0xFA9B ; + .dw 0xCFED ; + .dw 0xA3E3 ; + .dw 0x9B9B ; + .dw 0x2B6F ; + .dw 0xCFEE ; + .dw 0x58A9 ; + .dw 0xD303 ; + .dw 0x2287 ; + .dw 0xCFEF ; + .dw 0x3AF1 ; + .dw 0xBEFF ; + .dw 0xF90B ; + .dw 0xCFF0 ; + .dw 0xCC47 ; + .dw 0xDE4D ; + .dw 0x9E43 ; + .dw 0xCFF1 ; + .dw 0xFE51 ; + .dw 0x7DC7 ; + .dw 0x79BD ; + .dw 0xCFF2 ; + .dw 0x6B1D ; + .dw 0x6835 ; + .dw 0x7AD9 ; + .dw 0xCFF3 ; + .dw 0xC635 ; + .dw 0x955D ; + .dw 0xDE57 ; + .dw 0xCFF4 ; + .dw 0x2F0B ; + .dw 0x2555 ; + .dw 0xD887 ; + .dw 0xCFF5 ; + .dw 0xCB59 ; + .dw 0xAC01 ; + .dw 0x3CEB ; + .dw 0xCFF6 ; + .dw 0xFDF5 ; + .dw 0x510D ; + .dw 0xB54D ; + .dw 0xCFF7 ; + .dw 0xD1DB ; + .dw 0xA867 ; + .dw 0x482F ; + .dw 0xCFF8 ; + .dw 0xB1C9 ; + .dw 0x5AA7 ; + .dw 0x4121 ; + .dw 0xCFF9 ; + .dw 0x83A1 ; + .dw 0x5A65 ; + .dw 0x4161 ; + .dw 0xCFFA ; + .dw 0x9E7F ; + .dw 0xF1F ; + .dw 0x7E8F ; + .dw 0xCFFB ; + .dw 0x4D1F ; + .dw 0x7C11 ; + .dw 0xA17B ; + .dw 0xCFFC ; + .dw 0xB5FD ; + .dw 0x2AF7 ; + .dw 0x5C2B ; + .dw 0xCFFD ; + .dw 0xFA4F ; + .dw 0x580D ; + .dw 0x8E77 ; + .dw 0xCFFE ; + .dw 0xEB0B ; + .dw 0x633B ; + .dw 0x9099 ; + .dw 0xCFFF ; + .dw 0xE1A1 ; + .dw 0x7B5F ; + .dw 0xC9B ; +// COUNT = 6662 + + + + // count of UI's will be in r5, which was initialized to 0 by header + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x21; +CHECKREG(r5, 256); // count of all 16 bit UI's. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + // 64 bit illegal opcode handler - skips bad instruction + + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE + R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction +CC = r7 == r6; +IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave + +dbg_fail; + +UNDEFINEDINSTRUCTION: + R7 = RETX; // Fix up return address + + R7 += 8; // skip offending 64 bit instruction + +RETX = r7; // and put back in RETX + + R5 += 1; // Increment global counter + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; + +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/se_usermode_protviol.S b/sim/testsuite/sim/bfin/se_usermode_protviol.S new file mode 100644 index 0000000..5e8a4cc --- /dev/null +++ b/sim/testsuite/sim/bfin/se_usermode_protviol.S @@ -0,0 +1,317 @@ +//Original:/proj/frio/dv/testcases/seq/se_usermode_protviol/se_usermode_protviol.dsp +// Description: User mode "Illegal Use Supervsor Resource" Exceptions +# mach: bfin +# sim: --environment operating + +#include "test.h" +.include "testutils.inc" +start + +// +// Constants and Defines +// + +include(gen_int.inc) +include(selfcheck.inc) +include(std.inc) +include(mmrs.inc) +include(symtable.inc) + +#ifndef STACKSIZE +#define STACKSIZE 0x100 // change for how much stack you need +#endif +#ifndef ITABLE +#define ITABLE 0xF0000000 +#endif + +GEN_INT_INIT(ITABLE) // set location for interrupt table + +// +// Reset/Bootstrap Code +// (Here we should set the processor operating modes, initialize registers, +// etc.) +// + +BOOT: +INIT_R_REGS(0); // initialize general purpose regs + +INIT_P_REGS(0); // initialize the pointers + +INIT_I_REGS(0); // initialize the dsp address regs +INIT_M_REGS(0); +INIT_L_REGS(0); +INIT_B_REGS(0); + +CLI R1; // inhibit events during MMR writes + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +USP = SP; + +LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer +FP = SP; // and frame pointer + +LD32(p0, EVT0); // Setup Event Vectors and Handlers + + P0 += 4; // EVT0 not used (Emulation) + + P0 += 4; // EVT1 not used (Reset) + +LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) + [ P0 ++ ] = R0; + + P0 += 4; // EVT4 not used (Global Interrupt Enable) + +LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I7HANDLE); // IVG7 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I8HANDLE); // IVG8 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I9HANDLE); // IVG9 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I10HANDLE);// IVG10 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I11HANDLE);// IVG11 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I12HANDLE);// IVG12 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I13HANDLE);// IVG13 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I14HANDLE);// IVG14 Handler + [ P0 ++ ] = R0; + +LD32_LABEL(r0, I15HANDLE);// IVG15 Handler + [ P0 ++ ] = R0; + +LD32(p0, EVT_OVERRIDE); + R0 = 0; + [ P0 ++ ] = R0; + + R1 = -1; // Change this to mask interrupts (*) +CSYNC; // wait for MMR writes to finish +STI R1; // sync and reenable events (implicit write to IMASK) + +DUMMY: + + R0 = 0 (Z); + +LT0 = r0; // set loop counters to something deterministic +LB0 = r0; +LC0 = r0; +LT1 = r0; +LB1 = r0; +LC1 = r0; + +ASTAT = r0; // reset other internal regs +SYSCFG = r0; +RETS = r0; // prevent X's breaking LINK instruction + +RETI = r0; // prevent Xs later on +RETX = r0; +RETN = r0; +RETE = r0; + + +// The following code sets up the test for running in USER mode + +LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a + // ReturnFromInterrupt (RTI) +RETI = r0; // We need to load the return address + +// Comment the following line for a USER Mode test + +// JUMP STARTSUP; // jump to code start for SUPERVISOR mode + +RTI; + +STARTSUP: +LD32_LABEL(p1, BEGIN); + +LD32(p0, EVT15); + +CLI R1; // inhibit events during write to MMR + [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start +CSYNC; // wait for it +STI R1; // reenable events with proper imask + +RAISE 15; // after we RTI, INT 15 should be taken + +RTI; + +// +// The Main Program +// + +STARTUSER: + +LD32_LABEL(sp, USTACK); // setup the user stack pointer +FP = SP; +LINK 0; // change for how much stack frame space you need. + +JUMP BEGIN; + +//********************************************************************* + +BEGIN: + + // COMMENT the following line for USER MODE tests +// [--sp] = RETI; // enable interrupts in supervisor mode + + R0 = 0; + R1 = -1; + +// the following instructions should EXCEPT + R6 = 0x2E; // EXCAUSE 0x2E means Illegal Use Supervidor Resource + +RAISE 15; +CLI R0; +STI r0; +// TESTSET (p0); // now allowed in user mode +r5 += 1; +// IDLE; // works in user mode + +USP = r1; +SEQSTAT = r1; +SYSCFG = r1; +RETI = r1; +RETX = r1; +RETN = r1; +RETE = r1; + + R2 = USP; + R2 = SEQSTAT; + R2 = SYSCFG; + R2 = RETI; + R2 = RETX; + R2 = RETN; + R2 = RETE; + + [ -- SP ] = USP; + [ -- SP ] = SEQSTAT; + [ -- SP ] = SYSCFG; + [ -- SP ] = RETI; + [ -- SP ] = RETX; + [ -- SP ] = RETN; + [ -- SP ] = RETE; + +SEQSTAT = [sp++]; +SYSCFG = [sp++]; +RETI = [sp++]; +RETX = [sp++]; +RETN = [sp++]; +RETE = [sp++]; + +RTX; +RTN; +RTI; +RTE; + + R6 = 0x22; // EXCAUSE 0x22 means Illegal Insn Combination +USP = [sp++]; + +CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); + // Xhandler counts all EXCAUSE = 0x2B; +CHECKREG(r5, 36); // count of all IF protection violations. + +END: +dbg_pass; // End the test + +//********************************************************************* + +// +// Handlers for Events +// + +NHANDLE: // NMI Handler 2 +RTN; + +XHANDLE: // Exception Handler 3 + [ -- SP ] = ASTAT; // save what we damage + [ -- SP ] = ( R7:6 ); + R7 = SEQSTAT; + R7 <<= 26; + R7 >>= 26; // only want EXCAUSE +CC = r7 == r6; +IF CC JUMP IFETCHPROTVIOL; // If EXCAUSE != 0x2E then leave + +dbg_fail; // if the EXCAUSE is wrong the test will infinite loop + +IFETCHPROTVIOL: + R7 = RETX; // Fix up return address + R7 += 2; // skip instruction +RETX = r7; // and put back in RETX + + R5 += 1; // Count + +OUT: + ( R7:6 ) = [ SP ++ ]; +ASTAT = [sp++]; +RTX; + +HWHANDLE: // HW Error Handler 5 +RTI; + +THANDLE: // Timer Handler 6 +RTI; + +I7HANDLE: // IVG 7 Handler +RTI; + +I8HANDLE: // IVG 8 Handler +RTI; + +I9HANDLE: // IVG 9 Handler +RTI; + +I10HANDLE: // IVG 10 Handler +RTI; + +I11HANDLE: // IVG 11 Handler +RTI; + +I12HANDLE: // IVG 12 Handler +RTI; + +I13HANDLE: // IVG 13 Handler +RTI; + +I14HANDLE: // IVG 14 Handler +RTI; + +I15HANDLE: // IVG 15 Handler +RTI; + + + // padding for the icache + +EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; + +// +// Data Segment +// + +.data +DATA: + .space (0x10); + +// Stack Segments (Both Kernel and User) + + .space (STACKSIZE); +KSTACK: + + .space (STACKSIZE); +USTACK: diff --git a/sim/testsuite/sim/bfin/seqstat.s b/sim/testsuite/sim/bfin/seqstat.s new file mode 100644 index 0000000..45fad2c --- /dev/null +++ b/sim/testsuite/sim/bfin/seqstat.s @@ -0,0 +1,25 @@ +# Blackfin testcase for SEQSTAT register +# mach: bfin + + .include "testutils.inc" + + .macro seqstat_test val:req + imm32 R0, \val + SEQSTAT = R0; + R1 = SEQSTAT; + CC = R7 == R1; + IF !CC JUMP 1f; + .endm + + start + + # Writes to SEQSTAT should be ignored + R7 = SEQSTAT; + + seqstat_test 0 + seqstat_test 0x1 + seqstat_test -1 + seqstat_test 0xab11cd22 + + pass +1: fail diff --git a/sim/testsuite/sim/bfin/sign.s b/sim/testsuite/sim/bfin/sign.s new file mode 100644 index 0000000..072263e --- /dev/null +++ b/sim/testsuite/sim/bfin/sign.s @@ -0,0 +1,27 @@ +# Blackfin testcase for signbits +# mach: bfin + + .include "testutils.inc" + + start + + .macro check_alu_signbits areg:req + \areg = 0; + R0 = 0x10 (Z); + \areg\().x = R0; + + imm32 r0, 0x60038; + + R0.L = SIGNBITS \areg; + + imm32 r1, 0x6fffa; + CC = R1 == R0; + if ! CC jump 1f; + .endm + + check_alu_signbits A0 + check_alu_signbits A1 + + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/simple0.s b/sim/testsuite/sim/bfin/simple0.s new file mode 100644 index 0000000..956ce11 --- /dev/null +++ b/sim/testsuite/sim/bfin/simple0.s @@ -0,0 +1,10 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 5; + R0 += -1; + DBGA ( R0.L , 4 ); + pass diff --git a/sim/testsuite/sim/bfin/sri.s b/sim/testsuite/sim/bfin/sri.s new file mode 100644 index 0000000..9f90abf --- /dev/null +++ b/sim/testsuite/sim/bfin/sri.s @@ -0,0 +1,21 @@ +# Blackfin testcase for BITMUX +# mach: bfin + + .include "testutils.inc" + + start + + r0 = 0; + p2.l = 16; + +ilp: + BITMUX( R6 , R7, A0) (ASR); + p2 += -1; + cc=p2==0; + if !cc jump ilp; + A0 = A0 >> 8; + R0 = A0.w; + [ I1 ++ ] = R0; + nop; + + pass diff --git a/sim/testsuite/sim/bfin/stk.s b/sim/testsuite/sim/bfin/stk.s new file mode 100644 index 0000000..451a11e --- /dev/null +++ b/sim/testsuite/sim/bfin/stk.s @@ -0,0 +1,78 @@ +# mach: bfin + +.include "testutils.inc" + start + + +// load up some registers. +// setup up a global pointer table and load some state. +// save the machine state and clear some of the values. +// then restore and assert some of the values to ensure that +// we maintain consitent machine state. + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = -7; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + + loadsym P0, a; + _DBG P0; + SP = P0; + FP = P0; + P1 = [ P0 ++ ]; + P2 = [ P0 ++ ]; + P0 += 4; + P4 = [ P0 ++ ]; + P5 = [ P0 ++ ]; + [ -- SP ] = ( R7:0, P5:0 ); + _DBG SP; + _DBG FP; + R0 = R0 ^ R0; + R1 = R1 ^ R1; + R2 = R2 ^ R2; + R4 = R4 ^ R4; + R5 = R5 ^ R5; + R6 = R6 ^ R6; + R7 = R7 ^ R7; + ( R7:0, P5:0 ) = [ SP ++ ]; + DBGA ( R0.L , 1 ); + DBGA ( R2.L , 3 ); + DBGA ( R7.L , 7 ); + R0 = SP; + loadsym R1, a; + CC = R0 == R1; + IF !CC JUMP abrt; + R0 = FP; + CC = R0 == R1; + CC = R0 == R1; + IF !CC JUMP abrt; + + pass +abrt: + fail + + .data +_gptab: + .dw 0x200 + .dw 0x000 + .dw 0x300 + .dw 0x400 + .dw 0x500 + .dw 0x600 + + .space (0x100) +a: + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 0xa diff --git a/sim/testsuite/sim/bfin/stk2.s b/sim/testsuite/sim/bfin/stk2.s new file mode 100644 index 0000000..d5cb975 --- /dev/null +++ b/sim/testsuite/sim/bfin/stk2.s @@ -0,0 +1,107 @@ +// load up some registers. +// setup up a global pointer table and load some state. +// save the machine state and clear some of the values. +// then restore and assert some of the values to ensure that +// we maintain consitent machine state. +# mach: bfin + + +.include "testutils.inc" + start + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = -7; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + + loadsym P0, a; + P1.L = 0x1000; +//DBG P0; +//DBG P1; + SP = P0; + FP = P0; + + CALL try; + + P1 = [ P0 ++ ]; + P2 = [ P0 ++ ]; + P0 += 4; + P4 = [ P0 ++ ]; + P5 = [ P0 ++ ]; +// DBG; + [ -- SP ] = ( R7:0, P5:0 ); +// DBG SP; +// DBG FP; + R0 = R0 ^ R0; + R1 = R1 ^ R1; + R2 = R2 ^ R2; + R4 = R4 ^ R4; + R5 = R5 ^ R5; + R6 = R6 ^ R6; + R7 = R7 ^ R7; +// DBG; + ( R7:0, P5:0 ) = [ SP ++ ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 0xfff9 ); + DBGA ( R4.L , 4 ); + DBGA ( R5.L , 5 ); + DBGA ( R6.L , 6 ); + DBGA ( R7.L , 7 ); + + R0 = SP; + loadsym R1, a; + CC = R0 == R1; + IF !CC JUMP abrt; + R0 = FP; + CC = R0 == R1; + CC = R0 == R1; + IF !CC JUMP abrt; + pass +abrt: + fail + +try: + LINK 0; + [ -- SP ] = R7; + [ -- SP ] = R0; + R7 = 0x1234 (X); + [ -- SP ] = R7; + CALL bar; + SP += 4; + R0 = [ SP ++ ]; + R7 = [ SP ++ ]; + UNLINK; + RTS; + +bar: + R0 = [ SP ]; + DBGA ( R0.L , 0x1234 ); + RTS; + + .data +_gptab: + .dw 0x200 + .dw 0x000 + .dw 0x300 + .dw 0x400 + .dw 0x500 + .dw 0x600 + + .space (0x100) +a: + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 0xa diff --git a/sim/testsuite/sim/bfin/stk3.s b/sim/testsuite/sim/bfin/stk3.s new file mode 100644 index 0000000..131f8c5 --- /dev/null +++ b/sim/testsuite/sim/bfin/stk3.s @@ -0,0 +1,106 @@ +// load up some registers. +// setup up a global pointer table and load some state. +// save the machine state and clear some of the values. +// then restore and assert some of the values to ensure that +// we maintain consitent machine state. + +# mach: bfin + +.include "testutils.inc" + start + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = -7; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + + loadsym P0, a; + P1.L = 0x1000; + _DBG P0; + _DBG P1; + SP = P0; + FP = P0; + + CALL try; + + P1 = [ P0 ++ ]; + P2 = [ P0 ++ ]; + P0 += 4; + P4 = [ P0 ++ ]; + P5 = [ P0 ++ ]; + [ -- SP ] = ( R7:0, P5:0 ); + _DBG SP; + _DBG FP; + R0 = R0 ^ R0; + R1 = R1 ^ R1; + R2 = R2 ^ R2; + R4 = R4 ^ R4; + R5 = R5 ^ R5; + R6 = R6 ^ R6; + R7 = R7 ^ R7; + ( R7:0, P5:0 ) = [ SP ++ ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 0xfff9); + DBGA ( R4.L , 4 ); + DBGA ( R5.L , 5 ); + DBGA ( R6.L , 6 ); + DBGA ( R7.L , 7 ); + R0 = SP; + loadsym R1, a; + CC = R0 == R1; + IF !CC JUMP abrt; + R0 = FP; + CC = R0 == R1; + CC = R0 == R1; + IF !CC JUMP abrt; + pass +abrt: + fail; + +try: + LINK 0; + [ -- SP ] = ( R7:0, P5:0 ); + R7 = 0x1234 (X); + [ -- SP ] = R7; + CALL bar; + SP += 4; + ( R7:0, P5:0 ) = [ SP ++ ]; + UNLINK; + RTS; + +bar: + LINK 0; + [ -- SP ] = ( R7:0, P5:0 ); + R0 = [ FP + 8 ]; + DBGA ( R0.L , 0x1234 ); + ( R7:0, P5:0 ) = [ SP ++ ]; + UNLINK; + RTS; + + .data +_gptab: + .dw 0x200 + .dw 0x000 + .dw 0x300 + .dw 0x400 + .dw 0x500 + .dw 0x600 + + .space (0x100) +a: + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 0xa diff --git a/sim/testsuite/sim/bfin/stk4.s b/sim/testsuite/sim/bfin/stk4.s new file mode 100644 index 0000000..797aa78 --- /dev/null +++ b/sim/testsuite/sim/bfin/stk4.s @@ -0,0 +1,110 @@ +// load up some registers. +// setup up a global pointer table and load some state. +// save the machine state and clear some of the values. +// then restore and assert some of the values to ensure that +// we maintain consitent machine state. +# mach: bfin + +.include "testutils.inc" + start + + R0 = 1; + R1 = 2; + R2 = 3; + R3 = -7; + R4 = 4; + R5 = 5; + R6 = 6; + R7 = 7; + + loadsym P0, a; + P1.L = 0x1000; + _DBG P0; + _DBG P1; + SP = P0; + FP = P0; + + CALL try; + + P1 = [ P0 ++ ]; + P2 = [ P0 ++ ]; + P0 += 4; + P4 = [ P0 ++ ]; + P5 = [ P0 ++ ]; + [ -- SP ] = ( R7:0, P5:0 ); + _DBG SP; + _DBG FP; + R0 = R0 ^ R0; + R1 = R1 ^ R1; + R2 = R2 ^ R2; + R4 = R4 ^ R4; + R5 = R5 ^ R5; + R6 = R6 ^ R6; + R7 = R7 ^ R7; + ( R7:0, P5:0 ) = [ SP ++ ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 0xfff9 ); + DBGA ( R4.L , 4 ); + DBGA ( R5.L , 5 ); + DBGA ( R6.L , 6 ); + DBGA ( R7.L , 7 ); + R0 = SP; + loadsym R1, a; + CC = R0 == R1; + IF !CC JUMP abrt; + R0 = FP; + CC = R0 == R1; + CC = R0 == R1; + IF !CC JUMP abrt; + pass +abrt: + fail; + +try: + LINK 0; + [ -- SP ] = ( R7:0, P5:0 ); + R7 = 0x1234 (X); + [ -- SP ] = R7; + CALL bar; + R7 = [ SP ++ ]; + ( R7:0, P5:0 ) = [ SP ++ ]; + UNLINK; + RTS; + +bar: + LINK 0; + [ -- SP ] = ( R7:0, P5:0 ); + R0 = [ FP + 8 ]; + DBGA ( R0.L , 0x1234 ); + CALL foo; + ( R7:0, P5:0 ) = [ SP ++ ]; + UNLINK; + RTS; + +foo: + DBGA ( R0.L , 0x1234 ); + RTS; + + .data +_gptab: + .dw 0x200 + .dw 0x000 + .dw 0x300 + .dw 0x400 + .dw 0x500 + .dw 0x600 + + .space (0x100) +a: + .dw 1 + .dw 2 + .dw 3 + .dw 4 + .dw 5 + .dw 6 + .dw 7 + .dw 8 + .dw 9 + .dw 0xa diff --git a/sim/testsuite/sim/bfin/stk5.s b/sim/testsuite/sim/bfin/stk5.s new file mode 100644 index 0000000..e3a8fca --- /dev/null +++ b/sim/testsuite/sim/bfin/stk5.s @@ -0,0 +1,34 @@ +# mach: bfin + +.include "testutils.inc" + start + + SP += -12; + FP = SP; + CALL _foo; + + pass + + +_printf: + LINK 0; + [ -- SP ] = ( R7:7, P5:4 ); + R5 = [ FP + 8 ]; + DBGA ( R5.L , 0x1234 ); + R5 = [ FP + 12 ]; + DBGA ( R5.L , 0xdead ); + ( R7:7, P5:4 ) = [ SP ++ ]; + UNLINK; + RTS; + +_foo: + LINK 0; + R5 = 0xdead (Z); + [ -- SP ] = R5; + R5 = 0x1234 (X); + [ -- SP ] = R5; + CALL _printf; + P5 = 8; + SP = SP + P5; + UNLINK; + RTS; diff --git a/sim/testsuite/sim/bfin/stk6.s b/sim/testsuite/sim/bfin/stk6.s new file mode 100644 index 0000000..89a5e60 --- /dev/null +++ b/sim/testsuite/sim/bfin/stk6.s @@ -0,0 +1,58 @@ +// setup a dummy stack and put values in memory 0,1,2,3...n +// then restore registers with pop instruction. +# mach: bfin + +.include "testutils.inc" + start + + SP += -12; + + P1 = SP; + R1 = 0; + P5.L = 0xdead; + SP += -((8+5)*4); // lets move the stack pointer and include the current location. i.e. 5 + P4 = (8+6); // 8 data registers and 6 pointer registers are being stored. + LSETUP ( ls0 , le0 ) LC0 = P4; +ls0: + R1 += 1; +le0: + [ P1-- ] = R1; + + ( R7:0, P5:0 ) = [ SP ++ ]; + + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 4 ); + DBGA ( R4.L , 5 ); + DBGA ( R5.L , 6 ); + DBGA ( R6.L , 7 ); + DBGA ( R7.L , 8 ); + R0 = P0; DBGA ( R0.L , 9 ); + R0 = P1; DBGA ( R0.L , 10 ); + R0 = P2; DBGA ( R0.L , 11 ); + R0 = P3; DBGA ( R0.L , 12 ); + R0 = P4; DBGA ( R0.L , 13 ); + R0 = P5; DBGA ( R0.L , 14 ); + R0 = 1; + + [ -- SP ] = ( R7:0, P5:0 ); + ( R7:0, P5:0 ) = [ SP ++ ]; + + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R2.L , 3 ); + DBGA ( R3.L , 4 ); + DBGA ( R4.L , 5 ); + DBGA ( R5.L , 6 ); + DBGA ( R6.L , 7 ); + DBGA ( R7.L , 8 ); + R0 = P0; DBGA ( R0.L , 9 ); + R0 = P1; DBGA ( R0.L , 10 ); + R0 = P2; DBGA ( R0.L , 11 ); + R0 = P3; DBGA ( R0.L , 12 ); + R0 = P4; DBGA ( R0.L , 13 ); + R0 = P5; DBGA ( R0.L , 14 ); + R0 = 1; + + pass diff --git a/sim/testsuite/sim/bfin/syscfg.s b/sim/testsuite/sim/bfin/syscfg.s new file mode 100644 index 0000000..05ebeec --- /dev/null +++ b/sim/testsuite/sim/bfin/syscfg.s @@ -0,0 +1,25 @@ +# Blackfin testcase for SYSCFG register +# mach: bfin + + .include "testutils.inc" + + .macro syscfg_test val:req + imm32 R0, \val + R0 = SYSCFG; + SYSCFG = R0; + R1 = SYSCFG; + CC = R0 == R1; + IF !CC JUMP 1f; + .endm + + start + + syscfg_test 0 + syscfg_test 1 + syscfg_test -1 + syscfg_test 0x12345678 + # leave in sane state + syscfg_test 0x30 + + pass +1: fail diff --git a/sim/testsuite/sim/bfin/tar10622.s b/sim/testsuite/sim/bfin/tar10622.s new file mode 100644 index 0000000..c3c0a37 --- /dev/null +++ b/sim/testsuite/sim/bfin/tar10622.s @@ -0,0 +1,20 @@ +# mach: bfin + +.include "testutils.inc" + start + + r2.l = 0x1234; + r2.h = 0xff90; + + r4=8; + i2=r2; + m2 = 4; + a0 = 0; + r1.l = (a0 += r4.l *r4.l) (IS) || I2 += m2 || nop; + + r0 = i2; + + dbga(r0.l, 0x1238); + dbga(r0.h, 0xff90); + + pass diff --git a/sim/testsuite/sim/bfin/test-dma.h b/sim/testsuite/sim/bfin/test-dma.h new file mode 100644 index 0000000..2227ff6 --- /dev/null +++ b/sim/testsuite/sim/bfin/test-dma.h @@ -0,0 +1,28 @@ +struct bfin_dmasg { + bu32 next_desc_addr; + bu32 start_addr; + bu16 cfg; + bu16 x_count; + bs16 x_modify; + bu16 y_count; + bs16 y_modify; +} __attribute__((packed)); + +struct bfin_dma { + bu32 next_desc_ptr; + bu32 start_addr; + + bu16 BFIN_MMR_16 (config); + bu32 _pad0; + bu16 BFIN_MMR_16 (x_count); + bs16 BFIN_MMR_16 (x_modify); + bu16 BFIN_MMR_16 (y_count); + bs16 BFIN_MMR_16 (y_modify); + bu32 curr_desc_ptr, curr_addr; + bu16 BFIN_MMR_16 (irq_status); + bu16 BFIN_MMR_16 (peripheral_map); + bu16 BFIN_MMR_16 (curr_x_count); + bu32 _pad1; + bu16 BFIN_MMR_16 (curr_y_count); + bu32 _pad2; +}; diff --git a/sim/testsuite/sim/bfin/test.h b/sim/testsuite/sim/bfin/test.h new file mode 100644 index 0000000..38788f8 --- /dev/null +++ b/sim/testsuite/sim/bfin/test.h @@ -0,0 +1,134 @@ +#ifndef __ASSEMBLER__ +typedef unsigned long bu32; +typedef long bs32; +typedef unsigned short bu16; +typedef short bs16; +typedef unsigned char bu8; +typedef char bs8; +#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) +#define BFIN_MMR_16(mmr) mmr, __pad_##mmr +#include "test-dma.h" +#else +#define __ADSPBF537__ /* XXX: Hack for .S files. */ +#endif +#ifndef __FDPIC__ +#include +#endif + +/* AZ AN AC0_COPY V_COPY CC AQ RND_MOD AC0 AC1 AV0 AV0S AV1 AV1S V VS */ + +#define _AZ (1 << 0) +#define _AN (1 << 1) +#define _AC0_COPY (1 << 2) +#define _V_COPY (1 << 3) +#define _CC (1 << 5) +#define _AQ (1 << 6) +#define _RND_MOD (1 << 8) +#define _AC0 (1 << 12) +#define _AC1 (1 << 13) +#define _AV0 (1 << 16) +#define _AV0S (1 << 17) +#define _AV1 (1 << 18) +#define _AV1S (1 << 19) +#define _V (1 << 24) +#define _VS (1 << 25) + +#define _SET 1 +#define _UNSET 0 + +#define PASS do { puts ("pass"); _exit (0); } while (0) +#define FAIL do { puts ("fail"); _exit (1); } while (0) +#define DBG_PASS do { asm volatile ("outc 'p'; outc 'a'; outc 's'; outc 's'; outc '\n'; hlt;"); } while (1) +#define DBG_FAIL do { asm volatile ("outc 'f'; outc 'a'; outc 'i'; outc 'l'; outc '\n'; abort;"); } while (1) + +#define HI(x) (((x) >> 16) & 0xffff) +#define LO(x) ((x) & 0xffff) + +#define INIT_R_REGS(val) init_r_regs val +#define INIT_P_REGS(val) init_p_regs val +#define INIT_B_REGS(val) init_b_regs val +#define INIT_I_REGS(val) init_i_regs val +#define INIT_L_REGS(val) init_l_regs val +#define INIT_M_REGS(val) init_m_regs val +#define include(...) +#define CHECK_INIT_DEF(...) nop; +#define CHECK_INIT(...) nop; +#define CHECKMEM32(...) +#define GEN_INT_INIT(...) nop; + +#define LD32_LABEL(reg, sym) loadsym reg, sym +#define LD32(reg, val) imm32 reg, val +#define CHECKREG(reg, val) CHECKREG reg, val +#define CHECKREG_SYM_JUMPLESS(reg, sym, scratch_reg) \ + loadsym scratch_reg, sym; \ + cc = reg == scratch_reg; \ + /* Need to avoid jumping for trace buffer. */ \ + if !cc jump fail_lvl; +#define CHECKREG_SYM(reg, sym, scratch_reg) \ + loadsym scratch_reg, sym; \ + cc = reg == scratch_reg; \ + if cc jump 9f; \ + dbg_fail; \ +9: + +#define WR_MMR(mmr, val, mmr_reg, val_reg) \ + imm32 mmr_reg, mmr; \ + imm32 val_reg, val; \ + [mmr_reg] = val_reg; +#define WR_MMR_LABEL(mmr, sym, mmr_reg, sym_reg) \ + loadsym sym_reg, sym; \ + imm32 mmr_reg, mmr; \ + [mmr_reg] = sym_reg; +#define RD_MMR(mmr, mmr_reg, val_reg) \ + imm32 mmr_reg, mmr; \ + val_reg = [mmr_reg]; + +/* Legacy CPLB bits */ +#define CPLB_L1_CACHABLE CPLB_L1_CHBL +#define CPLB_USER_RO CPLB_USER_RD + +#define DATA_ADDR_1 0xff800000 +#define DATA_ADDR_2 0xff900000 +#define DATA_ADDR_3 (DATA_ADDR_1 + 0x2000) + +/* The libgloss headers omit these defines. */ +#define EVT_OVERRIDE 0xFFE02100 +#define EVT_IMASK IMASK + +#define PAGE_SIZE_1K PAGE_SIZE_1KB +#define PAGE_SIZE_4K PAGE_SIZE_4KB +#define PAGE_SIZE_1M PAGE_SIZE_1MB +#define PAGE_SIZE_4M PAGE_SIZE_4MB + +#define CPLB_USER_RW (CPLB_USER_RD | CPLB_USER_WR) + +#define DMC_AB_SRAM 0x0 +#define DMC_AB_CACHE 0xc +#define DMC_ACACHE_BSRAM 0x8 + +#define CPLB_L1SRAM (1 << 5) +#define CPLB_DA0ACC (1 << 6) + +#define FAULT_CPLB0 (1 << 0) +#define FAULT_CPLB1 (1 << 1) +#define FAULT_CPLB2 (1 << 2) +#define FAULT_CPLB3 (1 << 3) +#define FAULT_CPLB4 (1 << 4) +#define FAULT_CPLB5 (1 << 5) +#define FAULT_CPLB6 (1 << 6) +#define FAULT_CPLB7 (1 << 7) +#define FAULT_CPLB8 (1 << 8) +#define FAULT_CPLB9 (1 << 9) +#define FAULT_CPLB10 (1 << 10) +#define FAULT_CPLB11 (1 << 11) +#define FAULT_CPLB12 (1 << 12) +#define FAULT_CPLB13 (1 << 13) +#define FAULT_CPLB14 (1 << 14) +#define FAULT_CPLB15 (1 << 15) +#define FAULT_READ (0 << 16) +#define FAULT_WRITE (1 << 16) +#define FAULT_USER (0 << 17) +#define FAULT_SUPV (1 << 17) +#define FAULT_DAG0 (0 << 18) +#define FAULT_DAG1 (1 << 18) +#define FAULT_ILLADDR (1 << 19) diff --git a/sim/testsuite/sim/bfin/testset.s b/sim/testsuite/sim/bfin/testset.s new file mode 100644 index 0000000..57eaa5c --- /dev/null +++ b/sim/testsuite/sim/bfin/testset.s @@ -0,0 +1,73 @@ +# Blackfin testcase for playing with TESTSET +# mach: bfin + + .include "testutils.inc" + + start + + .macro _ts val:req + /* Load value to the external data storage */ + imm32 R0, \val + [P4] = R0; + FLUSHINV[P4]; + SSYNC; + mnop; + + imm32 R1, 0xdeadbeef + imm32 R2, 0xdeadbeef + + TESTSET (P4); + SSYNC; + mnop; + mnop; + + /* TESTSET will set CC based on low byte == 0 */ + .if \val & 0xff + if CC jump 1f; + .else + if ! CC jump 1f; + .endif + + /* Regardless of CC, the byte MSB is set to 1 */ + imm32 R1, \val | 0x80 + + /* Make sure the result is what we want */ + R2 = [P4]; + FLUSHINV[P4]; + SSYNC; + mnop; + CC = R2 == R1; + if ! CC jump 1f; + jump 2f; +1: fail +2: + .endm + .macro ts val:req + _ts \val + _ts ~(\val) + .endm + + loadsym P4, _data + + ts 0x00000000 + ts 0x00000011 + ts 0x11111111 + ts 0x11111101 + ts 0x11111110 + ts 0x111111bb + ts 0xaaaaaa00 + ts 0xabcd2222 + ts 0x000000bb + ts 0x55555555 + ts 0x5555550a + ts 0x00100010 + ts 0x00100100 + ts 0x33333000 + ts 0x000000aa + + pass + +.data +_data: +.long 0 +.size _data, .-_data diff --git a/sim/testsuite/sim/bfin/testset2.s b/sim/testsuite/sim/bfin/testset2.s new file mode 100644 index 0000000..66b50be --- /dev/null +++ b/sim/testsuite/sim/bfin/testset2.s @@ -0,0 +1,37 @@ +// testset instruction +//TESTSET is an atomic test-and-set. +//If the lock was not set prior to the TESTSET, cc is set, the lock bit is set, +//and this processor gets the lock. If the lock was set +//prior to the TESTSET, cc is cleared, the lock bit is still set, +//but the processor fails to acquire the lock. +# mach: bfin + + .include "testutils.inc" + + start + + loadsym P0, datalabel; + + R0 = 0; + CC = R0; + R0 = B [ P0 ] (Z); + DBGA ( R0.L , 0 ); + TESTSET ( P0 ); + R0 = CC; + DBGA ( R0.L , 1 ); + R0 = B [ P0 ] (Z); + DBGA ( R0.L , 0x80 ); + + R0 = 0; + CC = R0; + TESTSET ( P0 ); + R0 = CC; + DBGA ( R0.L , 0 ); + R0 = B [ P0 ] (Z); + DBGA ( R0.L , 0x80 ); + + pass + + .data +datalabel: + .dw 0 diff --git a/sim/testsuite/sim/bfin/testutils.inc b/sim/testsuite/sim/bfin/testutils.inc new file mode 100644 index 0000000..60b7a3d --- /dev/null +++ b/sim/testsuite/sim/bfin/testutils.inc @@ -0,0 +1,295 @@ +# R0 and P0 are used as tmps, consider them call clobbered by these macros. + +# To build for hardware, use: +# bfin-linux-uclibc-gcc -nostdlib -g -Wa,--defsym,BFIN_HOST=1 foo.s + +# MACRO: start +# All assembler tests should start with a call to "start" + .macro start + .text + # Pad with EMUEXCPT to make sure "jump to 0" always fails +__panic: + .rep 0xf + .word 0x0025 + .endr + abort; + jump __panic; + + .global __pass +__pass: + write 1, _passmsg, 5 + exit 0 +.ifdef BFIN_JTAG +__emu_out: + /* DBGSTAT */ + imm32 P0 0xFFE05008; + +1: R7 = [P0]; + CC = BITTST (R7,0); + IF CC JUMP 1b; + + EMUDAT = R0; + RTS; +.endif + .global __fail +__fail: +.ifndef BFIN_HOST + P0.H = _rets; + P0.L = _rets; + R0 = RETS; + R0 += -4; + P1 = 8; + R2 = '9'; + LSETUP (1f, 3f) LC0 = P1; +1: + R1 = R0; + R1 >>= 28; + R1 += 0x30; + CC = R2 < R1; + IF !CC jump 2f; + R1 += 7; +2: + B[P0++] = R1; +3: + R0 <<= 4; + + write 1, _failmsg, 22 +.else + write 1, _failmsg, 5 +.endif + exit 1 + +.ifndef BFIN_HOST + .data +_failmsg: + .ascii "fail at PC=0x" +_rets: + .ascii "12345678\n" +_passmsg: + .ascii "pass\n" + .align 4 +_params: + .long 0 + .long 0 + .long 0 + .long 0 + + .text + .global __start +__start: +.else +.global ___uClibc_main; +___uClibc_main: +.global _main; +_main: +.endif + .endm + +# MACRO: system_call +# Make a libgloss/Linux system call + .macro system_call nr:req + P0 = \nr (X); + EXCPT 0; + .endm + +# MACRO: exit +# Quit the current test + .macro exit rc:req + R0 = \rc (X); +.ifndef BFIN_HOST + P0.H = _params; + P0.L = _params; + [P0] = R0; + R0 = P0; +.endif + system_call 1 + .endm + +# MACRO: pass +# Write 'pass' to stdout via syscalls and quit; +# meant for non-OS operating environments + .macro pass + CALL __pass; + .endm + +# MACRO: fail +# Write 'fail' to stdout via syscalls and quit; +# meant for non-OS operating environments + .macro fail + CALL __fail; + .endm + +# MACRO: write +# Just like the write() C function; uses system calls + .macro write fd:req, buf:req, count:req +.ifndef BFIN_HOST + P0.H = _params; + P0.L = _params; + R0 = \fd (X); + [P0] = R0; + R0.H = \buf; + R0.L = \buf; + [P0 + 4] = R0; + R0 = \count (X); + [P0 + 8] = R0; + R0 = P0; + system_call 5 +.endif + .endm + +# MACRO: outc_str +# Output a string using the debug OUTC insn + .macro outc_str ch:req, more:vararg + OUTC \ch; + .ifnb \more + outc_str \more + .endif + .endm + +# MACRO: dbg_pass +# Write 'pass' to stdout and quit (all via debug insns); +# meant for OS operating environments + .macro dbg_pass +.ifdef BFIN_JTAG + R0 = 6; + CALL __emu_out; + R0.L = 0x6170; /* 'p'=0x70 'a'=0x70 */ + R0.H = 0x7373; /* 's'=0x73 */ + CALL __emu_out; + + R0.L = 0x0A; /* newline */ + R0.H = 0x0000; + CALL __emu_out; +1: + EMUEXCPT; + JUMP 1b; +.else + outc_str 'p', 'a', 's', 's', '\n' + HLT; +.endif + .endm + +# MACRO: dbg_fail +# Write 'fail' to stdout and quit (all via debug insns); +# meant for OS operating environments + .macro dbg_fail +.ifdef BFIN_JTAG + R0 = 6; + CALL __emu_out; + R0.L = 0x6166; /* 'f'=0x66 'a'=0x61 */ + R0.H = 0x6c69; /* 'i'=0x69 'l'=0x6c */ + CALL __emu_out; + + R0.L = 0x0A; /* newline */ + R0.H = 0x0000; + CALL __emu_out; +1: + EMUEXCPT; + JUMP 1b; +.else + outc_str 'f', 'a', 'i', 'l', '\n' +.endif + ABORT; + .endm + +# MACRO: imm32 +# Load a 32bit immediate directly into a register + .macro imm32 reg:req, val:req + .if (\val) & ~0x7fff + \reg\().L = ((\val) & 0xffff); + \reg\().H = (((\val) >> 16) & 0xffff); + .else + \reg = \val; + .endif + .endm + +# MACRO: dmm32 +# Load a 32bit immediate indirectly into a register + .macro dmm32 reg:req, val:req + [--SP] = R0; + imm32 R0, \val + \reg = R0; + R0 = [SP++]; + .endm + +# MACRO: loadsym +# Load a symbol directly into a register +.ifndef BFIN_HOST + .macro loadsym reg:req, sym:req, offset=0 + \reg\().L = (\sym\() + \offset\()); + \reg\().H = (\sym\() + \offset\()); + .endm +.else + .macro loadsym reg:req, sym:req, offset=0 + [--SP] = R0; + R0 = [P3 + \sym\()@GOT17M4]; + .if \offset + [--SP] = R1; + R1 = \offset\() (Z); + R0 = R0 + R1; + R1 = [SP++]; + .endif + \reg = R0; + R0 = [SP++]; + .endm +.endif + +# MACRO: CHECKREG +# Use debug insns to verify the value of a register matches + .macro CHECKREG reg:req, val:req + DBGAL (\reg, ((\val) & 0xffff)); + DBGAH (\reg, (((\val) >> 16) & 0xffff)); + .endm + +# internal helper macros; ignore them + .macro __init_regs reg:req, max:req, x:req, val:req + .ifle (\x - \max) + imm32 \reg\()\x, \val + .endif + .endm + .macro _init_regs reg:req, max:req, val:req + __init_regs \reg, \max, 0, \val + __init_regs \reg, \max, 1, \val + __init_regs \reg, \max, 2, \val + __init_regs \reg, \max, 3, \val + __init_regs \reg, \max, 4, \val + __init_regs \reg, \max, 5, \val + __init_regs \reg, \max, 6, \val + __init_regs \reg, \max, 7, \val + .endm + +# MACRO: init_r_regs +# MACRO: init_p_regs +# MACRO: init_b_regs +# MACRO: init_i_regs +# MACRO: init_l_regs +# MACRO: init_m_regs +# Set the specified group of regs to the specified value + .macro init_r_regs val:req + _init_regs R, 7, \val + .endm + .macro init_p_regs val:req + _init_regs P, 5, \val + .endm + .macro init_b_regs val:req + _init_regs B, 3, \val + .endm + .macro init_i_regs val:req + _init_regs I, 3, \val + .endm + .macro init_l_regs val:req + _init_regs L, 3, \val + .endm + .macro init_m_regs val:req + _init_regs M, 3, \val + .endm + + // the test framework needs things to be quiet, so don't + // print things out by default. + .macro _DBG reg:req + //DBG \reg; + .endm + + .macro _DBGCMPLX reg:req + // + .endm diff --git a/sim/testsuite/sim/bfin/unlink.S b/sim/testsuite/sim/bfin/unlink.S new file mode 100644 index 0000000..978d39e --- /dev/null +++ b/sim/testsuite/sim/bfin/unlink.S @@ -0,0 +1,68 @@ +# Blackfin testcase for unlink insn with any immediate value +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + /* Set up exception handler */ + imm32 P4, EVT3; + loadsym R1, _evx; + [P4] = R1; + + /* Lower to the code we want to single step through */ + loadsym P1, _usr; + RETI = P1; + + imm32 FP, 0x800000 + imm32 R0, 0x12345678; + [FP] = R0; + imm32 R0, 0x87654321; + [FP + 4] = R0; + + RTI; + +_usr: + imm32 FP, 0x800000 + + .byte 0x01, 0xe8 +.Linsn: + .byte 0, 0 + + imm32 R0, 0x12345678; + R1 = FP; + CC = R0 == R1; + IF !CC jump _fail; + + imm32 R0, 0x87654321; + R1 = RETS; + CC = R0 == R1; + IF !CC jump _fail; + + imm32 R0, 0x800008; + R1 = SP; + CC = R0 == R1; + IF !CC jump _fail; + + loadsym P0, .Linsn; + R0 = W[P0]; + R0 += 1; + W[P0] = R0; + SSYNC; + + R0 = R0.L; + CC = R0 == 0; + IF CC jump _pass; + jump _usr; + + .align 4; +_evx: + dbg_fail; + +_pass: + dbg_pass; + +_fail: + dbg_fail; diff --git a/sim/testsuite/sim/bfin/up0.s b/sim/testsuite/sim/bfin/up0.s new file mode 100644 index 0000000..ed705b8 --- /dev/null +++ b/sim/testsuite/sim/bfin/up0.s @@ -0,0 +1,41 @@ +# mach: bfin + +.include "testutils.inc" + start + + + R0 = 1; + DBGA ( R0.L , 1 ); + + R1.L = 2; + DBGA ( R1.L , 2 ); + + R2 = 3; + A0.x = R2; + R0 = A0.x; + DBGA ( R0.L , 3 ); + + P0 = 4; + R0 = P0; + DBGA ( R0.L , 4 ); + + R0 = 45; + R1 = 22; + A1 = R0.L * R1.L, A0 = R0.H * R1.H; + _DBG A1; + + loadsym I2, foo; + P0 = I2; + R0 = 0x0333 (X); + R3 = 0x0444 (X); + + R3.L = ( A0 = R0.L * R0.L ) || [ I2 ++ ] = R3 || NOP; + DBGA ( R3.L , 0x14 ); + R0 = [ P0 ]; + DBGA ( R0.L , 0x0444 ); + + pass + + .data +foo: + .space (0x10); diff --git a/sim/testsuite/sim/bfin/usp.S b/sim/testsuite/sim/bfin/usp.S new file mode 100644 index 0000000..e77ff52 --- /dev/null +++ b/sim/testsuite/sim/bfin/usp.S @@ -0,0 +1,50 @@ +# Blackfin testcase for USP handling +# mach: bfin +# sim: --environment operating + +#include "test.h" + .include "testutils.inc" + + start + + imm32 R5, 0x44455566 + imm32 R6, 0x12345678 + imm32 R7, 0x9abcdef0 + + imm32 p0, EVT3; + loadsym r0, exception; + [p0] = r0; + + loadsym r0, usermode; + reti = r0; + + SP = R6; + USP = R7; + RTI; + +usermode: + # SP should now be USP + R1 = SP; + CC = R1 == R7; + IF !CC JUMP fail; + + # Now set SP to another value + SP = R5; + + # Move up to exception space + EXCPT 0; + +exception: + # SP should be the same as original, but USP should change + R1 = SP; + CC = R1 == R6; + IF !CC JUMP fail; + + R1 = USP; + CC = R1 == R5; + IF !CC JUMP fail; + + dbg_pass + +fail: + dbg_fail diff --git a/sim/testsuite/sim/bfin/vec-abs-2.S b/sim/testsuite/sim/bfin/vec-abs-2.S new file mode 100644 index 0000000..d171e83 --- /dev/null +++ b/sim/testsuite/sim/bfin/vec-abs-2.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x0; + R0.L = 0x8000; + R1 = ABS R0 (V); + R7 = ASTAT; + R2.H = 0x0; + R2.L = 0x7fff; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN */ + R3.H = HI(_AN); + R3.L = LO(_AN); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ V V_COPY VS */ + R3.H = HI(_AZ|_V|_V_COPY|_VS); + R3.L = LO(_AZ|_V|_V_COPY|_VS); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/vec-abs-3.S b/sim/testsuite/sim/bfin/vec-abs-3.S new file mode 100644 index 0000000..bf003a1 --- /dev/null +++ b/sim/testsuite/sim/bfin/vec-abs-3.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x8000; + R0.L = 0x0; + R1 = ABS R0 (V); + R7 = ASTAT; + R2.H = 0x7fff; + R2.L = 0x0; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN */ + R3.H = HI(_AN); + R3.L = LO(_AN); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ V V_COPY VS */ + R3.H = HI(_AZ|_V|_V_COPY|_VS); + R3.L = LO(_AZ|_V|_V_COPY|_VS); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/vec-abs.S b/sim/testsuite/sim/bfin/vec-abs.S new file mode 100644 index 0000000..97ec84f --- /dev/null +++ b/sim/testsuite/sim/bfin/vec-abs.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector ABS instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x1234; + R0.L = 0xcdef; + R1 = ABS R0 (V); + R7 = ASTAT; + R2.H = 0x1234; + R2.L = 0x3211; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ AN V V_COPY */ + R3.H = HI(_AZ|_AN|_V|_V_COPY); + R3.L = LO(_AZ|_AN|_V|_V_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: */ + R3.H = HI(0); + R3.L = LO(0); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/vec-neg-2.S b/sim/testsuite/sim/bfin/vec-neg-2.S new file mode 100644 index 0000000..9ea15ec --- /dev/null +++ b/sim/testsuite/sim/bfin/vec-neg-2.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x0; + R0.L = 0x8000; + R1 = -R0 (V); + R7 = ASTAT; + R2.H = 0x0; + R2.L = 0x7fff; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN AC0 AC0_COPY */ + R3.H = HI(_AN|_AC0|_AC0_COPY); + R3.L = LO(_AN|_AC0|_AC0_COPY); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ V V_COPY VS AC1 */ + R3.H = HI(_AZ|_V|_V_COPY|_VS|_AC1); + R3.L = LO(_AZ|_V|_V_COPY|_VS|_AC1); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/vec-neg-3.S b/sim/testsuite/sim/bfin/vec-neg-3.S new file mode 100644 index 0000000..d748213 --- /dev/null +++ b/sim/testsuite/sim/bfin/vec-neg-3.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x8000; + R0.L = 0x0; + R1 = -R0 (V); + R7 = ASTAT; + R2.H = 0x7fff; + R2.L = 0x0; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AN AC0 AC0_COPY */ + R3.H = HI(_AN|_AC1); + R3.L = LO(_AN|_AC1); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AZ V V_COPY VS AC1 */ + R3.H = HI(_AZ|_V|_V_COPY|_VS|_AC0|_AC0_COPY); + R3.L = LO(_AZ|_V|_V_COPY|_VS|_AC0|_AC0_COPY); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/vec-neg.S b/sim/testsuite/sim/bfin/vec-neg.S new file mode 100644 index 0000000..1b9b076 --- /dev/null +++ b/sim/testsuite/sim/bfin/vec-neg.S @@ -0,0 +1,42 @@ +# Blackfin testcase for vector negate instruction +# mach: bfin + +#include "test.h" + + .include "testutils.inc" + + start + + .global _test +_test: + R6 = ASTAT; + R0.H = 0x1234; + R0.L = 0xcdef; + R1 = -R0 (V); + R7 = ASTAT; + R2.H = 0xedcc; + R2.L = 0x3211; + CC = R1 == R2; + IF !CC JUMP 1f; + /* CLEARED: AZ V V_COPY AC0 AC0_COPY AC1 */ + R3.H = HI(_AZ|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); + R3.L = LO(_AZ|_V|_V_COPY|_AC0|_AC0_COPY|_AC1); + R4 = R7 & R3; + CC = R4 == 0; + IF !CC JUMP 1f; + /* SET: AN */ + R3.H = HI(_AN); + R3.L = LO(_AN); + R4 = R7 & R3; + CC = R3 == R4; + IF !CC JUMP 1f; + /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS */ + R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS); + R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS); + R4 = R6 & R3; + R5 = R7 & R3; + CC = R4 == R5; + IF !CC JUMP 1f; + pass +1: + fail diff --git a/sim/testsuite/sim/bfin/vecadd.s b/sim/testsuite/sim/bfin/vecadd.s new file mode 100644 index 0000000..7e568ec --- /dev/null +++ b/sim/testsuite/sim/bfin/vecadd.s @@ -0,0 +1,65 @@ +# mach: bfin + +.include "testutils.inc" + start + +// create two short vectors v_a, v_b +// where each element of v_a is the index +// where each element of v_b is 128-index + R2 = 0; + loadsym P0, v_a; + loadsym P1, v_b; + P2 = 0; + R3 = 128 (X); + R0 = 0; + R1 = 128 (X); +L$1: + W [ P0 ++ ] = R0; + W [ P1 ++ ] = R1; + R0 += 1; + R1 += -1; + CC = R0 < R3; + IF CC JUMP L$1 (BP); + + loadsym P0, v_a; + loadsym P1, v_b; + + CALL vecadd; + + loadsym P0, v_c; + R2 = 0; + R3 = 128 (X); +L$3: + R0 = W [ P0 ++ ] (X); + DBGA ( R0.L , 128 ); + R2 += 1; + CC = R2 < R3; + IF CC JUMP L$3; + _DBG R6; + pass + +vecadd: + + loadsym I0, v_a; + loadsym I1, v_b; + loadsym I2, v_c; + + P5 = 128 (X); + LSETUP ( L$2 , L$2end ) LC0 = P5 >> 1; + R0 = [ I0 ++ ]; + R1 = [ I1 ++ ]; +L$2: + R2 = R0 +|+ R1 || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; +L$2end: + [ I2 ++ ] = R2; + + + RTS; + + .data +v_a: + .space (512); +v_b: + .space (512); +v_c: + .space (512); diff --git a/sim/testsuite/sim/bfin/vit_max.s b/sim/testsuite/sim/bfin/vit_max.s new file mode 100644 index 0000000..35eaa41 --- /dev/null +++ b/sim/testsuite/sim/bfin/vit_max.s @@ -0,0 +1,57 @@ +# Blackfin testcase for VIT_MAX (taken from PRM) +# mach: bfin + + .include "testutils.inc" + + start + + imm32 R3, 0xFFFF0000 + imm32 R2, 0x0000FFFF + A0 = 0; + R5 = VIT_MAX (R3, R2) (ASL); + R4 = 0 (x); + CC = R5 == R4; + IF !CC JUMP 1f; + imm32 R6, 0x00000002 + R4 = A0; + CC = R4 == R6; + IF !CC JUMP 1f; + + imm32 R1, 0xFEEDBEEF + imm32 R0, 0xDEAF0000 + A0 = 0; + R7 = VIT_MAX (R1, R0) (ASR); + imm32 R4, 0xFEED0000 + CC = R4 == R7; + IF !CC JUMP 1f; + imm32 R6, 0x80000000 + R2 = A0.W; + CC = R2 == R6; + IF !CC JUMP 1f; + + imm32 R1, 0xFFFF0000 + A0 = 0; + R3.L = VIT_MAX (R1) (ASL); + R3 = R3.L; + R4 = 0 (x); + CC = R3 == R4; + IF !CC JUMP 1f; + R6 = A0.W; + CC = R6 == R4; + IF !CC JUMP 1f; + + imm32 R1, 0x1234FADE + imm32 R2, 0xFFFFFFFF + A0.W = R2; + R3.L = VIT_MAX (R1) (ASR); + R3 = R3.L; + imm32 R4 0x00001234 + CC = R4 == R3; + IF !CC JUMP 1f; + imm32 R7, 0xFFFFFFFF + R0 = A0.W; + CC = R7 == R0; + IF !CC JUMP 1f; + + pass +1: fail diff --git a/sim/testsuite/sim/bfin/viterbi2.s b/sim/testsuite/sim/bfin/viterbi2.s new file mode 100644 index 0000000..6fb9ad0 --- /dev/null +++ b/sim/testsuite/sim/bfin/viterbi2.s @@ -0,0 +1,254 @@ +# mach: bfin + +// The assembly program uses two instructions to speed the decoder inner loop: +// R6= VMAX/VMAX (R5, R4) A0>>2; +// R2 =H+L (SGN(R0)*R1); +// VMAX is a 2-way parallel comparison of four updated path metrics, resulting +// in 2 new path metrics as well as a 2 bit field indicating the selection +// results. This 2 bit field is shifted into accumulator A0. This instruction +// implements the selections of a complete butterfly for a rate 1/n system. +// The H+L(SGN) instruction is used to compute the branch metric used by each +// butterfly. It takes as input a pair of values representing the received +// symbol, and another pair of values which are +1 or -1. The latter come +// from a pre-computed table that holds all the branch metric information for +// a specific set of polynomials. As all symbols are assumed to be binary, +// distance metrics between a received symbol and a branch metric are computed +// by adding and subtracting the values of the symbol according to the +// transition of a branch. + +.include "testutils.inc" + start + + // 16 in bytes for M2 + // A few pointer initializations + // P2 points to decision history, where outputs are stored + loadsym P2, DecisionHistory + + // P4 holds address of APMFrom + loadsym P4, APMFrom; + + // P5 holds address of APMTo + loadsym P5, APMTo; + + // I0 points to precomputed d's + loadsym I0, BranchStorage; + + M2.L = 32; + + loadsym P0, InputData; + + // storage for all precomputed branch metrics + loadsym P1, BranchStorage; + + R6 = 0; R0 = 0; // inits + + R0.L = 0x0001; + R0.H = 0x0001; + [ P1 + 0 ] = R0; + R0.L = 0xffff; + R0.H = 0xffff; + [ P1 + 4 ] = R0; + R0.L = 0xffff; + R0.H = 0x0001; + [ P1 + 8 ] = R0; + R0.L = 0x0001; + R0.H = 0xffff; + [ P1 + 12 ] = R0; + R0.L = 0xffff; + R0.H = 0x0001; + [ P1 + 16 ] = R0; + R0.L = 0x0001; + R0.H = 0xffff; + [ P1 + 20 ] = R0; + R0.L = 0x0001; + R0.H = 0x0001; + [ P1 + 24 ] = R0; + R0.L = 0xffff; + R0.H = 0xffff; + [ P1 + 28 ] = R0; + R0.L = 0x0001; + R0.H = 0xffff; + [ P1 + 32 ] = R0; + R0.L = 0xffff; + R0.H = 0x0001; + [ P1 + 36 ] = R0; + R0.L = 0xffff; + R0.H = 0xffff; + [ P1 + 40 ] = R0; + R0.L = 0x0001; + R0.H = 0x0001; + [ P1 + 44 ] = R0; + R0.L = 0xffff; + R0.H = 0xffff; + [ P1 + 48 ] = R0; + R0.L = 0x0001; + R0.H = 0x0001; + [ P1 + 52 ] = R0; + R0.L = 0x0001; + R0.H = 0xffff; + [ P1 + 56 ] = R0; + R0.L = 0xffff; + R0.H = 0x0001; + [ P1 + 60 ] = R0; + + P1 = 18; + LSETUP ( L$0 , L$0end ) LC0 = P1; // SymNo loop start + +L$0: + + // Get a symbol and leave it resident in R1 + R1 = [ P0 ]; // R1=(InputData[SymNo*2+1] InputData[SymNo*2]) + P0 += 4; + + A0 = 0; + + // I0 points to precomputed D1, D0 + loadsym I0, BranchStorage; + + I1 = P4; // I1 points to APM[From] + I2 = P4; + I2 += M2; // I2 points to APM[From+16] + I3 = P5; // I3 points to APM[To] + + P1 = 16; + P1 += -1; + LSETUP ( L$1 , L$1end ) LC1 = P1; + + // APMFrom and APMTo are in alternate + // memory banks. + + R0 = [ I0 ++ ]; // load R0 = (D1 D0) + R3.L = W [ I1 ++ ]; // load RL3 = PM0 + // (R1 holds current symbol) + + R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L; // apply sum-on-sign instruction + R3.H = W [ I2 ++ ]; // now, R3 = (PM1 PM0) + +L$1: + R5 = R3 +|- R2 , R4 = R3 -|+ R2 || R0 = [ I0 ++ ] || NOP; + // R5 = (PM11 PM01) R4 = (PM10 PM00) + // and load next (D1 D0) + + R6 = VIT_MAX( R5 , R4 ) (ASR) || R3.L = W [ I1 ++ ] || NOP; + // do 2 ACS in parallel + // R6 = (nPM1 nPM0) and update to A0 + +L$1end: + + R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L || R3.H = W [ I2 ++ ] || [ I3 ++ ] = R6; + // store new path metrics in + // two consecutive locations + + R5 = R3 +|- R2 , R4 = R3 -|+ R2; + + R6 = VIT_MAX( R5 , R4 ) (ASR); + + [ I3 ++ ] = R6; + + R7 = A0.w; + [ P2 ] = R7; + P2 += 4; // store history + + FP = P4; // swap pointers From <--> To + P4 = P5; +L$0end: + P5 = FP; + + // check results + loadsym I0, DecisionHistory + + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x6ff2 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0xf99f ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x9909 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x6666 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x0096 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x6996 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x9309 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x0000 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0xffff ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0xffff ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0xf0ff ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0xcf00 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x9009 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x07f6 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x6004 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x6996 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x8338 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x3443 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x6bd6 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x6197 ); + R0.L = W [ I0 ++ ]; DBGA ( R0.L , 0x6c26 ); + R0.H = W [ I0 ++ ]; DBGA ( R0.H , 0x0990 ); + + pass + + .data + .align 8 +InputData: + .dw 0x0001 + .dw 0x0001 + .dw 0xffff + .dw 0xfffb + .dw 0x0005 + .dw 0x0001 + .dw 0xfffd + .dw 0xfffd + .dw 0x0005 + .dw 0x0001 + .dw 0x0001 + .dw 0x0001 + .dw 0xffff + .dw 0xfffb + .dw 0x0005 + .dw 0x0001 + .dw 0xfffd + .dw 0xfffd + .dw 0x0005 + .dw 0x0001 + + .align 8 +APMFrom: + .dw 0xc000 + .dw 0x0 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + .dw 0xc000 + + .align 8 +APMTo: + .space (32*8) + + .align 8 +BranchStorage: + .space (32*8) + + .align 8 +DecisionHistory: + .space (18*4) diff --git a/sim/testsuite/sim/bfin/wtf.s b/sim/testsuite/sim/bfin/wtf.s new file mode 100644 index 0000000..2ec8507 --- /dev/null +++ b/sim/testsuite/sim/bfin/wtf.s @@ -0,0 +1,26 @@ +# mach: bfin + +.include "testutils.inc" + start + + loadsym p0, foo; + r2 = p0; + r2 += 4; + [p0++]=p0; + loadsym i0, foo; + r0=[i0]; + R3 = P0; + CC = R2 == R3 + if ! CC jump _fail; + R3 = I0; + CC = R0 == R3; + if ! CC jump _fail; + +_halt0: + pass; +_fail: + fail; + + .data +foo: + .space (0x10) diff --git a/sim/testsuite/sim/bfin/x1.s b/sim/testsuite/sim/bfin/x1.s new file mode 100644 index 0000000..7ef1496 --- /dev/null +++ b/sim/testsuite/sim/bfin/x1.s @@ -0,0 +1,79 @@ +# mach: bfin + +.include "testutils.inc" + start + + +// 0.5 + imm32 r0, 0x40004000; + imm32 r1, 0x40004000; + R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); + checkreg r2, 0x40004000; + checkreg r3, 0; + + imm32 r1, 0x10001000; + + R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); + checkreg r2, 0x28002800; + checkreg r3, 0x18001800; + + R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR); + checkreg r0, 0x20002000; + checkreg r1, 0x08000800; + + R0 = 1; + R0 <<= 15; + R1 = R0 << 16; + R0 = R0 | R1; + R1 = R0; + checkreg r0, 0x80008000; + checkreg r1, 0x80008000; + + R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); + checkreg r2, 0x80008000; + checkreg r3, 0x0; + + R4 = 0; + R2 = R2 +|+ R4, R3 = R2 -|- R4 (S , ASR); + checkreg r2, 0xc000c000; + checkreg r3, 0xc000c000; + + R2 = R2 +|+ R3, R3 = R2 -|- R3 (S , ASR); + checkreg r2, 0xc000c000; + checkreg r3, 0x0; + + R4 = R2 +|+ R2, R5 = R2 -|- R2 (ASL); + checkreg r4, 0x0 + checkreg r5, 0x0 + + R2 = R2 +|+ R2, R3 = R2 -|- R2 (S , ASL); + checkreg r2, 0x80008000; + checkreg r3, 0x0; + + +imm32 r0, 0x50004000; +imm32 r1, 0x40005000; +R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL); +checkreg r2, 0x7fff7fff; +checkreg r3, 0x2000e000; +R4 = R0 +|+ R1, R5 = R0 -|- R1 (ASL); +checkreg r4, 0x20002000 +checkreg r5, 0x2000e000 + +imm32 r0, 0x30001000; +imm32 r1, 0x10003000; +R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL); +checkreg r2, 0x7fff7fff; +checkreg r3, 0x4000c000; +R4 = R0 +|+ R1, R5 = R0 -|- R1 (ASL); +checkreg r4, 0x80008000 +checkreg r5, 0x4000c000 + +imm32 r0, 0x20001fff; +imm32 r1, 0x1fff2000; +R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL); +checkreg r2, 0x7ffe7ffe; +checkreg r3, 0x0002fffe; + + + pass diff --git a/sim/testsuite/sim/bfin/zcall.s b/sim/testsuite/sim/bfin/zcall.s new file mode 100644 index 0000000..bdb82c7 --- /dev/null +++ b/sim/testsuite/sim/bfin/zcall.s @@ -0,0 +1,44 @@ +# mach: bfin + +.include "testutils.inc" + start + + FP = SP; + CALL _foo; + pass + +___main: + RTS; + +_m1: + LINK 0; + R7 = [ FP + 8 ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R7.L , 3 ); + UNLINK; + RTS; + +_m2: + LINK 0; + R7 = [ FP + 8 ]; + DBGA ( R0.L , 1 ); + DBGA ( R1.L , 2 ); + DBGA ( R7.L , 3 ); + [ -- SP ] = R7; + CALL _m1; + SP += 4; + UNLINK; + RTS; + +_foo: + LINK 0; + CALL ___main; + R7 = 3; + [ -- SP ] = R7; + R0 = 1; + R1 = 2; + CALL _m2; + SP += 4; + UNLINK; + RTS; diff --git a/sim/testsuite/sim/bfin/zeroflagrnd.s b/sim/testsuite/sim/bfin/zeroflagrnd.s new file mode 100644 index 0000000..1425c07 --- /dev/null +++ b/sim/testsuite/sim/bfin/zeroflagrnd.s @@ -0,0 +1,37 @@ +# mach: bfin + +.include "testutils.inc" + start + + init_r_regs 0; + ASTAT=R0; + + R0.L = -32768; + R0.H = -1; + R0.L = R0 (RND); + DBGA ( R0.L , 0 ); + + _DBG R0; +//R0 = ASTAT; +//DBG R0; +//DBGA ( R0.L , 0x1 ); + cc = az; + r0 = cc; + dbga( r0.l, 1); + cc = an; + r0 = cc; + dbga( r0.l, 0); + cc = av0; + r0 = cc; + dbga( r0.l, 0); + cc = av0s; + r0 = cc; + dbga( r0.l, 0); + cc = av1; + r0 = cc; + dbga( r0.l, 0); + cc = av1s; + r0 = cc; + dbga( r0.l, 0); + + pass -- 2.7.4