From 1ccc38b53b0f358489b4a107d0aca256e6eb84e0 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 6 Mar 2012 21:17:20 +0200 Subject: [PATCH] gfx: drv: use pipe specific macros to access the dsp regs Use the pipe specific macros to access these registers. Signed-off-by: Imre Deak Reviewed-by: Jani Nikula Signed-off-by: Kirill A. Shutemov --- drivers/staging/mrst/drv/mdfld_dsi_dbi.c | 32 ++-- drivers/staging/mrst/drv/mdfld_dsi_dbi_dpu.c | 46 +++--- drivers/staging/mrst/drv/mdfld_dsi_dpi.c | 32 ++-- drivers/staging/mrst/drv/mdfld_dsi_pkg_sender.c | 20 +-- .../mrst/drv/otm_hdmi/os/android/android_hdmi.c | 2 +- drivers/staging/mrst/drv/psb_drv.c | 157 +++++++++++--------- drivers/staging/mrst/drv/psb_intel_display.c | 163 ++++++++++----------- drivers/staging/mrst/drv/psb_irq.c | 40 ++--- drivers/staging/mrst/drv/psb_powermgmt.c | 108 +++++++------- drivers/staging/mrst/drv/tpo_cmd.c | 24 +-- 10 files changed, 307 insertions(+), 317 deletions(-) diff --git a/drivers/staging/mrst/drv/mdfld_dsi_dbi.c b/drivers/staging/mrst/drv/mdfld_dsi_dbi.c index ed3a550..065a77a 100644 --- a/drivers/staging/mrst/drv/mdfld_dsi_dbi.c +++ b/drivers/staging/mrst/drv/mdfld_dsi_dbi.c @@ -185,10 +185,10 @@ void mdfld_dsi_dbi_enter_dsr (struct mdfld_dsi_dbi_output * dbi_output, int pipe struct drm_crtc * crtc = dbi_output->base.base.crtc; struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL; u32 dpll_reg = MRST_DPLL_A; - u32 pipeconf_reg = PIPEACONF; - u32 dspcntr_reg = DSPACNTR; - u32 dspbase_reg = DSPABASE; - u32 dspsurf_reg = DSPASURF; + u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); + u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); + u32 dspbase_reg = PSB_DSPBASE(PSB_PIPE_A); + u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A); PSB_DEBUG_ENTRY(" \n"); @@ -202,10 +202,10 @@ void mdfld_dsi_dbi_enter_dsr (struct mdfld_dsi_dbi_output * dbi_output, int pipe if(pipe == 2) { dpll_reg = MRST_DPLL_A; - pipeconf_reg = PIPECCONF; - dspcntr_reg = DSPCCNTR; - dspbase_reg = MDFLD_DSPCBASE; - dspsurf_reg = DSPCSURF; + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); + dspbase_reg = PSB_DSPBASE(PSB_PIPE_C); + dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C); } if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) { @@ -261,8 +261,8 @@ static void mdfld_dbi_output_exit_dsr (struct mdfld_dsi_dbi_output * dbi_output, struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL; u32 reg_val; u32 dpll_reg = MRST_DPLL_A; - u32 pipeconf_reg = PIPEACONF; - u32 dspcntr_reg = DSPACNTR; + u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); + u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); /*if mode setting on-going, back off*/ if((dbi_output->mode_flags & MODE_SETTING_ON_GOING) || @@ -271,8 +271,8 @@ static void mdfld_dbi_output_exit_dsr (struct mdfld_dsi_dbi_output * dbi_output, if(pipe == 2) { dpll_reg = MRST_DPLL_A; - pipeconf_reg = PIPECCONF; - dspcntr_reg = DSPCCNTR; + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); } if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) { @@ -363,11 +363,11 @@ static bool mdfld_dbi_is_in_dsr(struct drm_device * dev) { if(REG_READ(MRST_DPLL_A) & DPLL_VCO_ENABLE) return false; - if((REG_READ(PIPEACONF) & PIPEACONF_ENABLE) || - (REG_READ(PIPECCONF) & PIPEACONF_ENABLE)) + if ((REG_READ(PSB_PIPECONF(PSB_PIPE_A)) & PIPEACONF_ENABLE) || + (REG_READ(PSB_PIPECONF(PSB_PIPE_C)) & PIPEACONF_ENABLE)) return false; - if((REG_READ(DSPACNTR) & DISPLAY_PLANE_ENABLE) || - (REG_READ(DSPCCNTR) & DISPLAY_PLANE_ENABLE)) + if ((REG_READ(PSB_DSPCNTR(PSB_PIPE_A)) & DISPLAY_PLANE_ENABLE) || + (REG_READ(PSB_DSPCNTR(PSB_PIPE_C)) & DISPLAY_PLANE_ENABLE)) return false; return true; diff --git a/drivers/staging/mrst/drv/mdfld_dsi_dbi_dpu.c b/drivers/staging/mrst/drv/mdfld_dsi_dbi_dpu.c index 491fd92..a95b590 100644 --- a/drivers/staging/mrst/drv/mdfld_dsi_dbi_dpu.c +++ b/drivers/staging/mrst/drv/mdfld_dsi_dbi_dpu.c @@ -281,20 +281,20 @@ static void mdfld_dpu_fb_plane_flush(struct mdfld_dbi_dpu_info * dpu_info, mdfld_plane_t plane) { u32 pipesrc_reg = PSB_PIPESRC(PSB_PIPE_A); - u32 dspsize_reg = DSPASIZE; - u32 dspoff_reg = DSPALINOFF; - u32 dspsurf_reg = DSPASURF; - u32 dspstride_reg = DSPASTRIDE; + u32 dspsize_reg = PSB_DSPSIZE(PSB_PIPE_A); + u32 dspoff_reg = PSB_DSPLINOFF(PSB_PIPE_A); + u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A); + u32 dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_A); u32 stride; struct psb_drm_dpu_rect * rect = &dpu_info->damage_pipea; struct drm_device * dev = dpu_info->dev; if(plane == MDFLD_PLANEC) { pipesrc_reg = PSB_PIPESRC(PSB_PIPE_C); - dspsize_reg = DSPCSIZE; - dspoff_reg = DSPCLINOFF; - dspsurf_reg = DSPCSURF; - dspstride_reg = DSPCSTRIDE; + dspsize_reg = PSB_DSPSIZE(PSB_PIPE_C); + dspoff_reg = PSB_DSPLINOFF(PSB_PIPE_C); + dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C); + dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_C); rect = &dpu_info->damage_pipec; } @@ -447,10 +447,10 @@ static int mdfld_dpu_update_fb(struct drm_device * dev) { bool pipe_updated[2]; unsigned long irq_flags; u32 dpll_reg = MRST_DPLL_A; - u32 dspcntr_reg = DSPACNTR; - u32 pipeconf_reg = PIPEACONF; - u32 dsplinoff_reg = DSPALINOFF; - u32 dspsurf_reg = DSPASURF; + u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); + u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); + u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A); + u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A); int pipe; int i; int ret; @@ -473,10 +473,10 @@ static int mdfld_dpu_update_fb(struct drm_device * dev) { pipe = dbi_output[i]->channel_num ? 2 : 0; if(pipe == 2) { - dspcntr_reg = DSPCCNTR; - pipeconf_reg = PIPECCONF; - dsplinoff_reg = DSPCLINOFF; - dspsurf_reg = DSPCSURF; + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); + dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C); + dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C); } if (!(REG_READ(MIPI_GEN_FIFO_STAT_REG(pipe)) & BIT(27)) || @@ -521,10 +521,10 @@ static int __mdfld_dbi_exit_dsr(struct mdfld_dsi_dbi_output * dbi_output, int pi struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL; u32 reg_val; u32 dpll_reg = MRST_DPLL_A; - u32 pipeconf_reg = PIPEACONF; - u32 dspcntr_reg = DSPACNTR; - u32 dspbase_reg = DSPABASE; - u32 dspsurf_reg = DSPASURF; + u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); + u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); + u32 dspbase_reg = PSB_DSPBASE(PSB_PIPE_A); + u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A); PSB_DEBUG_ENTRY("\n"); @@ -539,10 +539,10 @@ static int __mdfld_dbi_exit_dsr(struct mdfld_dsi_dbi_output * dbi_output, int pi if(pipe == 2) { dpll_reg = MRST_DPLL_A; - pipeconf_reg = PIPECCONF; - dspcntr_reg = DSPCCNTR; + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); dspbase_reg = MDFLD_DSPCBASE; - dspsurf_reg = DSPCSURF; + dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C); } if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) diff --git a/drivers/staging/mrst/drv/mdfld_dsi_dpi.c b/drivers/staging/mrst/drv/mdfld_dsi_dpi.c index 030d1c9..9250a8b 100644 --- a/drivers/staging/mrst/drv/mdfld_dsi_dpi.c +++ b/drivers/staging/mrst/drv/mdfld_dsi_dpi.c @@ -114,8 +114,8 @@ static void dsi_set_device_ready_state(struct drm_device *dev, int state, static void dsi_set_pipe_plane_enable_state(struct drm_device *dev, int state, int pipe) { struct drm_psb_private *dev_priv = dev->dev_private; - u32 pipeconf_reg = PIPEACONF; - u32 dspcntr_reg = DSPACNTR; + u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); + u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); u32 pipeconf = dev_priv->pipeconf; u32 dspcntr = dev_priv->dspcntr; @@ -125,8 +125,8 @@ static void dsi_set_pipe_plane_enable_state(struct drm_device *dev, int state, i __func__, state, pipe); if (pipe) { - pipeconf_reg = PIPECCONF; - dspcntr_reg = DSPCCNTR; + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); } else { mipi &= (~0x03); } @@ -144,7 +144,7 @@ static void dsi_set_pipe_plane_enable_state(struct drm_device *dev, int state, i REG_WRITE(dspcntr_reg, dspcntr); } else { u32 val; - u32 dspbase_reg = pipe ? MDFLD_DSPCBASE : MRST_DSPABASE; + u32 dspbase_reg = PSB_DSPBASE(pipe); /* Put DSI lanes to ULPS to disable pipe */ REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 2, 2, 1); @@ -653,12 +653,12 @@ static void mdfld_dsi_dpi_set_power(struct drm_encoder * encoder, bool on) int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder); struct drm_device * dev = dsi_config->dev; struct drm_psb_private * dev_priv = dev->dev_private; - u32 pipeconf_reg = PIPEACONF; + u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); PSB_DEBUG_ENTRY("set power %s on pipe %d\n", on ? "On" : "Off", pipe); if (pipe) - pipeconf_reg = PIPECCONF; + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); /*start up display island if it was shutdown*/ if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) @@ -874,8 +874,8 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder * encoder, struct drm_psb_private * dev_priv = dev->dev_private; int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder); - u32 pipeconf_reg = PIPEACONF; - u32 dspcntr_reg = DSPACNTR; + u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); + u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); u32 pipeconf = dev_priv->pipeconf; u32 dspcntr = dev_priv->dspcntr; @@ -884,8 +884,8 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder * encoder, PSB_DEBUG_ENTRY("set mode %dx%d on pipe %d", mode->hdisplay, mode->vdisplay, pipe); if(pipe) { - pipeconf_reg = PIPECCONF; - dspcntr_reg = DSPCCNTR; + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); } else { if (get_panel_type(dev, pipe) == TC35876X) mipi &= (~0x03); /* Use all four lanes */ @@ -924,13 +924,13 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder * encoder, mdfld_mipi_config(dsi_config, pipe); mdfld_set_pipe_timing(dsi_config, pipe); - REG_WRITE(DSPABASE, 0x00); - REG_WRITE(DSPASTRIDE, (mode->hdisplay * 4)); - REG_WRITE(DSPASIZE, + REG_WRITE(PSB_DSPBASE(PSB_PIPE_A), 0x00); + REG_WRITE(PSB_DSPSTRIDE(PSB_PIPE_A), (mode->hdisplay * 4)); + REG_WRITE(PSB_DSPSIZE(PSB_PIPE_A), ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); - REG_WRITE(DSPACNTR, 0x98000000); - REG_WRITE(DSPASURF, 0x00); + REG_WRITE(PSB_DSPCNTR(PSB_PIPE_A), 0x98000000); + REG_WRITE(PSB_DSPSURF(PSB_PIPE_A), 0x00); REG_WRITE(VGACNTRL, 0x80000000); REG_WRITE(DEVICE_READY_REG, 0x00000001); diff --git a/drivers/staging/mrst/drv/mdfld_dsi_pkg_sender.c b/drivers/staging/mrst/drv/mdfld_dsi_pkg_sender.c index 38aad70..297ae22 100644 --- a/drivers/staging/mrst/drv/mdfld_dsi_pkg_sender.c +++ b/drivers/staging/mrst/drv/mdfld_dsi_pkg_sender.c @@ -805,18 +805,18 @@ int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector * dsi_connector, int pi /*init regs*/ if(pipe == 0) { pkg_sender->dpll_reg = MRST_DPLL_A; - pkg_sender->dspcntr_reg = DSPACNTR; - pkg_sender->pipeconf_reg = PIPEACONF; - pkg_sender->dsplinoff_reg = DSPALINOFF; - pkg_sender->dspsurf_reg = DSPASURF; - pkg_sender->pipestat_reg = PIPEASTAT; + pkg_sender->dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); + pkg_sender->pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); + pkg_sender->dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A); + pkg_sender->dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A); + pkg_sender->pipestat_reg = PSB_PIPESTAT(PSB_PIPE_A); } else if (pipe == 2) { pkg_sender->dpll_reg = MRST_DPLL_A; - pkg_sender->dspcntr_reg = DSPCCNTR; - pkg_sender->pipeconf_reg = PIPECCONF; - pkg_sender->dsplinoff_reg = DSPCLINOFF; - pkg_sender->dspsurf_reg = DSPCSURF; - pkg_sender->pipestat_reg = PIPECSTAT; + pkg_sender->dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); + pkg_sender->pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); + pkg_sender->dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C); + pkg_sender->dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C); + pkg_sender->pipestat_reg = PSB_PIPESTAT(PSB_PIPE_C); } pkg_sender->mipi_intr_stat_reg = MIPI_INTR_STAT_REG(pipe); diff --git a/drivers/staging/mrst/drv/otm_hdmi/os/android/android_hdmi.c b/drivers/staging/mrst/drv/otm_hdmi/os/android/android_hdmi.c index a5ef469..1397899 100644 --- a/drivers/staging/mrst/drv/otm_hdmi/os/android/android_hdmi.c +++ b/drivers/staging/mrst/drv/otm_hdmi/os/android/android_hdmi.c @@ -1211,7 +1211,7 @@ int android_hdmi_crtc_mode_set(struct drm_crtc *crtc, width_align = (otm_adjusted_mode.width + 31) & ~31; pipebstride = 4 * width_align; - REG_WRITE(DSPBSTRIDE, pipebstride); + REG_WRITE(PSB_DSPSTRIDE(PSB_PIPE_B), pipebstride); fb_width = otm_adjusted_mode.width; fb_height = otm_adjusted_mode.height; } diff --git a/drivers/staging/mrst/drv/psb_drv.c b/drivers/staging/mrst/drv/psb_drv.c index 8d5b9a0..6b60821 100644 --- a/drivers/staging/mrst/drv/psb_drv.c +++ b/drivers/staging/mrst/drv/psb_drv.c @@ -1530,8 +1530,9 @@ static int psb_hist_enable_ioctl(struct drm_device *dev, void *data, guardband_reg.interrupt_status = 1; PSB_WVDC32(guardband_reg.data, HISTOGRAM_INT_CONTROL); - irqCtrl = PSB_RVDC32(PIPEASTAT); - PSB_WVDC32(irqCtrl | PIPE_DPST_EVENT_ENABLE, PIPEASTAT); + irqCtrl = PSB_RVDC32(PSB_PIPESTAT(PSB_PIPE_A)); + PSB_WVDC32(irqCtrl | PIPE_DPST_EVENT_ENABLE, + PSB_PIPESTAT(PSB_PIPE_A)); /* Wait for two vblanks */ } else { guardband_reg.data = PSB_RVDC32(HISTOGRAM_INT_CONTROL); @@ -1543,9 +1544,9 @@ static int psb_hist_enable_ioctl(struct drm_device *dev, void *data, ie_hist_cont_reg.ie_histogram_enable = 0; PSB_WVDC32(ie_hist_cont_reg.data, HISTOGRAM_LOGIC_CONTROL); - irqCtrl = PSB_RVDC32(PIPEASTAT); + irqCtrl = PSB_RVDC32(PSB_PIPESTAT(PSB_PIPE_A)); irqCtrl &= ~PIPE_DPST_EVENT_ENABLE; - PSB_WVDC32(irqCtrl, PIPEASTAT); + PSB_WVDC32(irqCtrl, PSB_PIPESTAT(PSB_PIPE_A)); } ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND); @@ -1747,8 +1748,8 @@ static int psb_mode_operation_ioctl(struct drm_device *dev, void *data, psb_fb = to_psb_fb(drm_fb); if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) { - REG_WRITE(DSPASURF, psb_fb->offset); - REG_READ(DSPASURF); + REG_WRITE(PSB_DSPSURF(PSB_PIPE_A), psb_fb->offset); + REG_READ(PSB_DSPSURF(PSB_PIPE_A)); ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND); } else { dev_priv->saveDSPASURF = psb_fb->offset; @@ -2207,18 +2208,27 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data, if (arg->sprite_enable_mask != 0) { if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) { PSB_WVDC32(0x1F3E, DSPARB); - PSB_WVDC32(arg->sprite.dspa_control | PSB_RVDC32(DSPACNTR), DSPACNTR); + PSB_WVDC32(arg->sprite.dspa_control | + PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_A)), + PSB_DSPCNTR(PSB_PIPE_A)); PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL); PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK); - PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF); - PSB_RVDC32(DSPASURF); - PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR); - PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE); - PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS); - PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF); - PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE); - PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF); - PSB_RVDC32(DSPCSURF); + PSB_WVDC32(PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_A)), + PSB_DSPSURF(PSB_PIPE_A)); + PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_A)); + PSB_WVDC32(arg->sprite.dspc_control, + PSB_DSPCNTR(PSB_PIPE_C)); + PSB_WVDC32(arg->sprite.dspc_stride, + PSB_DSPSTRIDE(PSB_PIPE_C)); + PSB_WVDC32(arg->sprite.dspc_position, + PSB_DSPPOS(PSB_PIPE_C)); + PSB_WVDC32(arg->sprite.dspc_linear_offset, + PSB_DSPLINOFF(PSB_PIPE_C)); + PSB_WVDC32(arg->sprite.dspc_size, + PSB_DSPSIZE(PSB_PIPE_C)); + PSB_WVDC32(arg->sprite.dspc_surface, + PSB_DSPSURF(PSB_PIPE_C)); + PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_C)); ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND); } } @@ -2226,9 +2236,10 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data, if (arg->sprite_disable_mask != 0) { if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) { PSB_WVDC32(0x3F3E, DSPARB); - PSB_WVDC32(0x0, DSPCCNTR); - PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF); - PSB_RVDC32(DSPCSURF); + PSB_WVDC32(0x0, PSB_DSPCNTR(PSB_PIPE_C)); + PSB_WVDC32(arg->sprite.dspc_surface, + PSB_DSPSURF(PSB_PIPE_C)); + PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_C)); ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND); } } @@ -2237,46 +2248,46 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data, if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) { uint32_t temp; if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) { - temp = PSB_RVDC32(DSPACNTR); + temp = PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_A)); temp &= ~DISPPLANE_PIXFORMAT_MASK; temp &= ~DISPPLANE_BOTTOM; temp |= DISPPLANE_32BPP; - PSB_WVDC32(temp, DSPACNTR); - - temp = PSB_RVDC32(DSPABASE); - PSB_WVDC32(temp, DSPABASE); - PSB_RVDC32(DSPABASE); - temp = PSB_RVDC32(DSPASURF); - PSB_WVDC32(temp, DSPASURF); - PSB_RVDC32(DSPASURF); + PSB_WVDC32(temp, PSB_DSPCNTR(PSB_PIPE_A)); + + temp = PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_A)); + PSB_WVDC32(temp, PSB_DSPBASE(PSB_PIPE_A)); + PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_A)); + temp = PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_A)); + PSB_WVDC32(temp, PSB_DSPSURF(PSB_PIPE_A)); + PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_A)); } if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) { - temp = PSB_RVDC32(DSPBCNTR); + temp = PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_B)); temp &= ~DISPPLANE_PIXFORMAT_MASK; temp &= ~DISPPLANE_BOTTOM; temp |= DISPPLANE_32BPP; - PSB_WVDC32(temp, DSPBCNTR); - - temp = PSB_RVDC32(DSPBBASE); - PSB_WVDC32(temp, DSPBBASE); - PSB_RVDC32(DSPBBASE); - temp = PSB_RVDC32(DSPBSURF); - PSB_WVDC32(temp, DSPBSURF); - PSB_RVDC32(DSPBSURF); + PSB_WVDC32(temp, PSB_DSPCNTR(PSB_PIPE_B)); + + temp = PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_B)); + PSB_WVDC32(temp, PSB_DSPBASE(PSB_PIPE_B)); + PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_B)); + temp = PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_B)); + PSB_WVDC32(temp, PSB_DSPSURF(PSB_PIPE_B)); + PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_B)); } if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) { - temp = PSB_RVDC32(DSPCCNTR); + temp = PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_C)); temp &= ~DISPPLANE_PIXFORMAT_MASK; temp &= ~DISPPLANE_BOTTOM; temp |= DISPPLANE_32BPP; - PSB_WVDC32(temp, DSPCCNTR); - - temp = PSB_RVDC32(DSPCBASE); - PSB_WVDC32(temp, DSPCBASE); - PSB_RVDC32(DSPCBASE); - temp = PSB_RVDC32(DSPCSURF); - PSB_WVDC32(temp, DSPCSURF); - PSB_RVDC32(DSPCSURF); + PSB_WVDC32(temp, PSB_DSPCNTR(PSB_PIPE_C)); + + temp = PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_C)); + PSB_WVDC32(temp, PSB_DSPBASE(PSB_PIPE_C)); + PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_C)); + temp = PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_C)); + PSB_WVDC32(temp, PSB_DSPSURF(PSB_PIPE_C)); + PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_C)); } ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND); } @@ -2286,43 +2297,43 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data, if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) { uint32_t temp; if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) { - temp = PSB_RVDC32(DSPACNTR); + temp = PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_A)); temp &= ~DISPPLANE_PIXFORMAT_MASK; temp |= DISPPLANE_32BPP_NO_ALPHA; - PSB_WVDC32(temp, DSPACNTR); - - temp = PSB_RVDC32(DSPABASE); - PSB_WVDC32(temp, DSPABASE); - PSB_RVDC32(DSPABASE); - temp = PSB_RVDC32(DSPASURF); - PSB_WVDC32(temp, DSPASURF); - PSB_RVDC32(DSPASURF); + PSB_WVDC32(temp, PSB_DSPCNTR(PSB_PIPE_A)); + + temp = PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_A)); + PSB_WVDC32(temp, PSB_DSPBASE(PSB_PIPE_A)); + PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_A)); + temp = PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_A)); + PSB_WVDC32(temp, PSB_DSPSURF(PSB_PIPE_A)); + PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_A)); } if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) { - temp = PSB_RVDC32(DSPBCNTR); + temp = PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_B)); temp &= ~DISPPLANE_PIXFORMAT_MASK; temp |= DISPPLANE_32BPP_NO_ALPHA; - PSB_WVDC32(temp, DSPBCNTR); - - temp = PSB_RVDC32(DSPBBASE); - PSB_WVDC32(temp, DSPBBASE); - PSB_RVDC32(DSPBBASE); - temp = PSB_RVDC32(DSPBSURF); - PSB_WVDC32(temp, DSPBSURF); - PSB_RVDC32(DSPBSURF); + PSB_WVDC32(temp, PSB_DSPCNTR(PSB_PIPE_B)); + + temp = PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_B)); + PSB_WVDC32(temp, PSB_DSPBASE(PSB_PIPE_B)); + PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_B)); + temp = PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_B)); + PSB_WVDC32(temp, PSB_DSPSURF(PSB_PIPE_B)); + PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_B)); } if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) { - temp = PSB_RVDC32(DSPCCNTR); + temp = PSB_RVDC32(PSB_DSPCNTR(PSB_PIPE_C)); temp &= ~DISPPLANE_PIXFORMAT_MASK; temp |= DISPPLANE_32BPP_NO_ALPHA; - PSB_WVDC32(temp, DSPCCNTR); - - temp = PSB_RVDC32(DSPCBASE); - PSB_WVDC32(temp, DSPCBASE); - PSB_RVDC32(DSPCBASE); - temp = PSB_RVDC32(DSPCSURF); - PSB_WVDC32(temp, DSPCSURF); - PSB_RVDC32(DSPCSURF); + PSB_WVDC32(temp, PSB_DSPCNTR(PSB_PIPE_C)); + + temp = PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_C)); + PSB_WVDC32(temp, PSB_DSPBASE(PSB_PIPE_C)); + PSB_RVDC32(PSB_DSPBASE(PSB_PIPE_C)); + temp = PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_C)); + PSB_WVDC32(temp, PSB_DSPSURF(PSB_PIPE_C)); + PSB_RVDC32(PSB_DSPSURF(PSB_PIPE_C)); } ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND); } diff --git a/drivers/staging/mrst/drv/psb_intel_display.c b/drivers/staging/mrst/drv/psb_intel_display.c index b5b7af1..d0e1099 100644 --- a/drivers/staging/mrst/drv/psb_intel_display.c +++ b/drivers/staging/mrst/drv/psb_intel_display.c @@ -215,8 +215,8 @@ static void psb_intel_crtc_save(struct drm_crtc *crtc) return; } - crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR); - crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF); + crtc_state->saveDSPCNTR = REG_READ(PSB_DSPCNTR(pipe)); + crtc_state->savePIPECONF = REG_READ(PSB_PIPECONF(pipe)); crtc_state->savePIPESRC = REG_READ(PSB_PIPESRC(pipe)); crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0); crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1); @@ -227,13 +227,13 @@ static void psb_intel_crtc_save(struct drm_crtc *crtc) crtc_state->saveVTOTAL = REG_READ(PSB_VTOTAL(pipe)); crtc_state->saveVBLANK = REG_READ(PSB_VBLANK(pipe)); crtc_state->saveVSYNC = REG_READ(PSB_VSYNC(pipe)); - crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE); + crtc_state->saveDSPSTRIDE = REG_READ(PSB_DSPSTRIDE(pipe)); /*NOTE: DSPSIZE DSPPOS only for psb*/ - crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE); - crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS); + crtc_state->saveDSPSIZE = REG_READ(PSB_DSPSIZE(pipe)); + crtc_state->saveDSPPOS = REG_READ(PSB_DSPPOS(pipe)); - crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE); + crtc_state->saveDSPBASE = REG_READ(PSB_DSPBASE(pipe)); DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", crtc_state->saveDSPCNTR, @@ -284,8 +284,8 @@ static void psb_intel_crtc_restore(struct drm_crtc *crtc) DRM_DEBUG( "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", - REG_READ(pipeA ? DSPACNTR : DSPBCNTR), - REG_READ(pipeA ? PIPEACONF : PIPEBCONF), + REG_READ(PSB_DSPCNTR(pipe)), + REG_READ(PSB_PIPECONF(pipe)), REG_READ(PSB_PIPESRC(pipe)), REG_READ(pipeA ? FPA0 : FPB0), REG_READ(pipeA ? FPA1 : FPB1), @@ -296,10 +296,10 @@ static void psb_intel_crtc_restore(struct drm_crtc *crtc) REG_READ(PSB_VTOTAL(pipe)), REG_READ(PSB_VBLANK(pipe)), REG_READ(PSB_VSYNC(pipe)), - REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE), - REG_READ(pipeA ? DSPASIZE : DSPBSIZE), - REG_READ(pipeA ? DSPAPOS : DSPBPOS), - REG_READ(pipeA ? DSPABASE : DSPBBASE) + REG_READ(PSB_DSPSTRIDE(pipe)), + REG_READ(PSB_DSPSIZE(pipe)), + REG_READ(PSB_DSPPOS(pipe)), + REG_READ(PSB_DSPBASE(pipe)) ); DRM_DEBUG( @@ -347,19 +347,19 @@ static void psb_intel_crtc_restore(struct drm_crtc *crtc) REG_WRITE(PSB_VTOTAL(pipe), crtc_state->saveVTOTAL); REG_WRITE(PSB_VBLANK(pipe), crtc_state->saveVBLANK); REG_WRITE(PSB_VSYNC(pipe), crtc_state->saveVSYNC); - REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE); + REG_WRITE(PSB_DSPSTRIDE(pipe), crtc_state->saveDSPSTRIDE); - REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE); - REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS); + REG_WRITE(PSB_DSPSIZE(pipe), crtc_state->saveDSPSIZE); + REG_WRITE(PSB_DSPPOS(pipe), crtc_state->saveDSPPOS); REG_WRITE(PSB_PIPESRC(pipe), crtc_state->savePIPESRC); - REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); - REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF); + REG_WRITE(PSB_DSPBASE(pipe), crtc_state->saveDSPBASE); + REG_WRITE(PSB_PIPECONF(pipe), crtc_state->savePIPECONF); psb_intel_wait_for_vblank(dev); - REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR); - REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); + REG_WRITE(PSB_DSPCNTR(pipe), crtc_state->saveDSPCNTR); + REG_WRITE(PSB_DSPBASE(pipe), crtc_state->saveDSPBASE); psb_intel_wait_for_vblank(dev); @@ -589,21 +589,7 @@ static const struct drm_crtc_helper_funcs mdfld_helper_funcs = { void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe) { int count, temp; - u32 pipeconf_reg = PIPEACONF; - - switch (pipe) { - case 0: - break; - case 1: - pipeconf_reg = PIPEBCONF; - break; - case 2: - pipeconf_reg = PIPECCONF; - break; - default: - DRM_ERROR("Illegal Pipe Number. \n"); - return; - } + u32 pipeconf_reg = PSB_PIPECONF(pipe); /* FIXME JLIU7_PO */ psb_intel_wait_for_vblank(dev); @@ -622,16 +608,16 @@ void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe) void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe) { int count, temp; - u32 pipeconf_reg = PIPEACONF; + u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); switch (pipe) { case 0: break; case 1: - pipeconf_reg = PIPEBCONF; + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B); break; case 2: - pipeconf_reg = PIPECCONF; + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); break; default: DRM_ERROR("Illegal Pipe Number. \n"); @@ -869,7 +855,7 @@ static struct drm_device globle_dev; void mdfld__intel_plane_set_alpha(int enable) { struct drm_device *dev = &globle_dev; - int dspcntr_reg = DSPACNTR; + int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); u32 dspcntr; dspcntr = REG_READ(dspcntr_reg); @@ -911,10 +897,10 @@ static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); int pipe = psb_intel_crtc->pipe; unsigned long Start, Offset; - int dsplinoff = DSPALINOFF; - int dspsurf = DSPASURF; - int dspstride = DSPASTRIDE; - int dspcntr_reg = DSPACNTR; + int dsplinoff = PSB_DSPLINOFF(PSB_PIPE_A); + int dspsurf = PSB_DSPSURF(PSB_PIPE_A); + int dspstride = PSB_DSPSTRIDE(PSB_PIPE_A); + int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); u32 dspcntr; int ret; @@ -934,19 +920,19 @@ static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, switch (pipe) { case 0: - dsplinoff = DSPALINOFF; + dsplinoff = PSB_DSPLINOFF(PSB_PIPE_A); break; case 1: - dsplinoff = DSPBLINOFF; - dspsurf = DSPBSURF; - dspstride = DSPBSTRIDE; - dspcntr_reg = DSPBCNTR; + dsplinoff = PSB_DSPLINOFF(PSB_PIPE_B); + dspsurf = PSB_DSPSURF(PSB_PIPE_B); + dspstride = PSB_DSPSTRIDE(PSB_PIPE_B); + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B); break; case 2: - dsplinoff = DSPCLINOFF; - dspsurf = DSPCSURF; - dspstride = DSPCSTRIDE; - dspcntr_reg = DSPCCNTR; + dsplinoff = PSB_DSPLINOFF(PSB_PIPE_C); + dspsurf = PSB_DSPSURF(PSB_PIPE_C); + dspstride = PSB_DSPSTRIDE(PSB_PIPE_C); + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); break; default: DRM_ERROR("Illegal Pipe Number. \n"); @@ -999,9 +985,9 @@ static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, void mdfld_disable_crtc (struct drm_device *dev, int pipe) { int dpll_reg = MRST_DPLL_A; - int dspcntr_reg = DSPACNTR; - int dspbase_reg = MRST_DSPABASE; - int pipeconf_reg = PIPEACONF; + int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); + int dspbase_reg = PSB_DSPBASE(PSB_PIPE_A); + int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); u32 temp; PSB_DEBUG_ENTRY("pipe = %d \n", pipe); @@ -1012,15 +998,15 @@ void mdfld_disable_crtc (struct drm_device *dev, int pipe) break; case 1: dpll_reg = MDFLD_DPLL_B; - dspcntr_reg = DSPBCNTR; - dspbase_reg = DSPBSURF; - pipeconf_reg = PIPEBCONF; + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B); + dspbase_reg = PSB_DSPSURF(PSB_PIPE_B); + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B); break; case 2: dpll_reg = MRST_DPLL_A; - dspcntr_reg = DSPCCNTR; - dspbase_reg = MDFLD_DSPCBASE; - pipeconf_reg = PIPECCONF; + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); + dspbase_reg = PSB_DSPBASE(PSB_PIPE_C); + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); break; default: DRM_ERROR("Illegal Pipe Number. \n"); @@ -1058,7 +1044,9 @@ void mdfld_disable_crtc (struct drm_device *dev, int pipe) temp = REG_READ(dpll_reg); if (temp & DPLL_VCO_ENABLE) { - if (((pipe != 1) && !((REG_READ(PIPEACONF) | REG_READ(PIPECCONF)) & PIPEACONF_ENABLE)) + if (((pipe != 1) && + !((REG_READ(PSB_PIPECONF(PSB_PIPE_A)) | + REG_READ(PSB_PIPECONF(PSB_PIPE_C))) & PIPEACONF_ENABLE)) || (pipe == 1)){ temp &= ~(DPLL_VCO_ENABLE); REG_WRITE(dpll_reg, temp); @@ -1091,10 +1079,10 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode) struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); int pipe = psb_intel_crtc->pipe; int dpll_reg = MRST_DPLL_A; - int dspcntr_reg = DSPACNTR; - int dspbase_reg = MRST_DSPABASE; - int pipeconf_reg = PIPEACONF; - u32 pipestat_reg = PIPEASTAT; + int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); + int dspbase_reg = PSB_DSPBASE(PSB_PIPE_A); + int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); + u32 pipestat_reg = PSB_PIPESTAT(PSB_PIPE_A); u32 pipeconf = dev_priv->pipeconf; u32 dspcntr = dev_priv->dspcntr; u32 temp; @@ -1111,19 +1099,19 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode) break; case 1: dpll_reg = DPLL_B; - dspcntr_reg = DSPBCNTR; - dspbase_reg = MRST_DSPBBASE; - pipeconf_reg = PIPEBCONF; + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B); + dspbase_reg = PSB_DSPBASE(PSB_PIPE_B); + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B); pipeconf = dev_priv->pipeconf1; dspcntr = dev_priv->dspcntr1; dpll_reg = MDFLD_DPLL_B; break; case 2: dpll_reg = MRST_DPLL_A; - dspcntr_reg = DSPCCNTR; - dspbase_reg = MDFLD_DSPCBASE; - pipeconf_reg = PIPECCONF; - pipestat_reg = PIPECSTAT; + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); + dspbase_reg = PSB_DSPBASE(PSB_PIPE_C); + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); + pipestat_reg = PSB_PIPESTAT(PSB_PIPE_C); pipeconf = dev_priv->pipeconf2; dspcntr = dev_priv->dspcntr2; break; @@ -1279,8 +1267,11 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode) temp = REG_READ(dpll_reg); if (temp & DPLL_VCO_ENABLE) { - if (((pipe != 1) && !((REG_READ(PIPEACONF) | REG_READ(PIPECCONF)) & PIPEACONF_ENABLE)) - || (pipe == 1)){ + if (((pipe != 1) && + !((REG_READ(PSB_PIPECONF(PSB_PIPE_A)) | + REG_READ(PSB_PIPECONF(PSB_PIPE_C))) & + PIPEACONF_ENABLE)) || + (pipe == 1)) { temp &= ~(DPLL_VCO_ENABLE); REG_WRITE(dpll_reg, temp); REG_READ(dpll_reg); @@ -1540,16 +1531,16 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, int pipe = psb_intel_crtc->pipe; int fp_reg = MRST_FPA0; int dpll_reg = MRST_DPLL_A; - int dspcntr_reg = DSPACNTR; - int pipeconf_reg = PIPEACONF; + int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); + int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); int htot_reg = PSB_HTOTAL(PSB_PIPE_A); int hblank_reg = PSB_HBLANK(PSB_PIPE_A); int hsync_reg = PSB_HSYNC(PSB_PIPE_A); int vtot_reg = PSB_VTOTAL(PSB_PIPE_A); int vblank_reg = PSB_VBLANK(PSB_PIPE_A); int vsync_reg = PSB_VSYNC(PSB_PIPE_A); - int dspsize_reg = DSPASIZE; - int dsppos_reg = DSPAPOS; + int dspsize_reg = PSB_DSPSIZE(PSB_PIPE_A); + int dsppos_reg = PSB_DSPPOS(PSB_PIPE_A); int pipesrc_reg = PSB_PIPESRC(PSB_PIPE_A); u32 *pipeconf = &dev_priv->pipeconf; u32 *dspcntr = &dev_priv->dspcntr; @@ -1584,16 +1575,16 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, case 1: fp_reg = FPB0; dpll_reg = DPLL_B; - dspcntr_reg = DSPBCNTR; - pipeconf_reg = PIPEBCONF; + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B); + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B); htot_reg = PSB_HTOTAL(PSB_PIPE_B); hblank_reg = PSB_HBLANK(PSB_PIPE_B); hsync_reg = PSB_HSYNC(PSB_PIPE_B); vtot_reg = PSB_VTOTAL(PSB_PIPE_B); vblank_reg = PSB_VBLANK(PSB_PIPE_B); vsync_reg = PSB_VSYNC(PSB_PIPE_B); - dspsize_reg = DSPBSIZE; - dsppos_reg = DSPBPOS; + dspsize_reg = PSB_DSPSIZE(PSB_PIPE_B); + dsppos_reg = PSB_DSPPOS(PSB_PIPE_B); pipesrc_reg = PSB_PIPESRC(PSB_PIPE_B); pipeconf = &dev_priv->pipeconf1; dspcntr = &dev_priv->dspcntr1; @@ -1602,16 +1593,16 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, break; case 2: dpll_reg = MRST_DPLL_A; - dspcntr_reg = DSPCCNTR; - pipeconf_reg = PIPECCONF; + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); htot_reg = PSB_HTOTAL(PSB_PIPE_C); hblank_reg = PSB_HBLANK(PSB_PIPE_C); hsync_reg = PSB_HSYNC(PSB_PIPE_C); vtot_reg = PSB_VTOTAL(PSB_PIPE_C); vblank_reg = PSB_VBLANK(PSB_PIPE_C); vsync_reg = PSB_VSYNC(PSB_PIPE_C); - dspsize_reg = DSPCSIZE; - dsppos_reg = DSPCPOS; + dspsize_reg = PSB_DSPSIZE(PSB_PIPE_C); + dsppos_reg = PSB_DSPPOS(PSB_PIPE_C); pipesrc_reg = PSB_PIPESRC(PSB_PIPE_C); pipeconf = &dev_priv->pipeconf2; dspcntr = &dev_priv->dspcntr2; diff --git a/drivers/staging/mrst/drv/psb_irq.c b/drivers/staging/mrst/drv/psb_irq.c index 815db73..284f6f1 100644 --- a/drivers/staging/mrst/drv/psb_irq.c +++ b/drivers/staging/mrst/drv/psb_irq.c @@ -45,13 +45,7 @@ static inline u32 psb_pipestat(int pipe) { - if (pipe == 0) - return PIPEASTAT; - if (pipe == 1) - return PIPEBSTAT; - if (pipe == 2) - return PIPECSTAT; - BUG(); + return PSB_PIPESTAT(pipe); } static inline u32 @@ -81,13 +75,7 @@ mid_pipe_vsync(int pipe) static inline u32 mid_pipeconf(int pipe) { - if (pipe == 0) - return PIPEACONF; - if (pipe == 1) - return PIPEBCONF; - if (pipe == 2) - return PIPECCONF; - BUG(); + return PSB_PIPECONF(pipe); } static void trcmd_vblank_power(unsigned type, int pipe) @@ -335,9 +323,9 @@ static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe) ie_hist_cont_reg.ie_histogram_enable = 0; PSB_WVDC32(ie_hist_cont_reg.data, HISTOGRAM_LOGIC_CONTROL); - irqCtrl = PSB_RVDC32(PIPEASTAT); + irqCtrl = PSB_RVDC32(PSB_PIPESTAT(PSB_PIPE_A)); irqCtrl &= ~PIPE_DPST_EVENT_ENABLE; - PSB_WVDC32(irqCtrl, PIPEASTAT); + PSB_WVDC32(irqCtrl, PSB_PIPESTAT(PSB_PIPE_A)); } pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); if ((pwm_reg & PWM_PHASEIN_INT_ENABLE) && @@ -849,9 +837,9 @@ void psb_disable_vblank(struct drm_device *dev, int pipe) */ u32 psb_get_vblank_counter(struct drm_device *dev, int pipe) { - uint32_t high_frame = PIPEAFRAMEHIGH; - uint32_t low_frame = PIPEAFRAMEPIXEL; - uint32_t pipeconf_reg = PIPEACONF; + uint32_t high_frame = PSB_PIPEFRAMEHIGH(PSB_PIPE_A); + uint32_t low_frame = PSB_PIPEFRAMEPIXEL(PSB_PIPE_A); + uint32_t pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); uint32_t reg_val = 0; uint32_t high1 = 0, high2 = 0, low = 0, count = 0; @@ -859,14 +847,14 @@ u32 psb_get_vblank_counter(struct drm_device *dev, int pipe) case 0: break; case 1: - high_frame = PIPEBFRAMEHIGH; - low_frame = PIPEBFRAMEPIXEL; - pipeconf_reg = PIPEBCONF; + high_frame = PSB_PIPEFRAMEHIGH(PSB_PIPE_B); + low_frame = PSB_PIPEFRAMEPIXEL(PSB_PIPE_B); + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B); break; case 2: - high_frame = PIPECFRAMEHIGH; - low_frame = PIPECFRAMEPIXEL; - pipeconf_reg = PIPECCONF; + high_frame = PSB_PIPEFRAMEHIGH(PSB_PIPE_C); + low_frame = PSB_PIPEFRAMEPIXEL(PSB_PIPE_C); + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); break; default: DRM_ERROR("%s, invalded pipe. \n", __FUNCTION__); @@ -967,7 +955,7 @@ int mdfld_irq_enable_hdmi_audio(struct drm_device *dev) u32 reg_val = 0, mask = 0; if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false)) { - reg_val = REG_READ(PIPEBCONF); + reg_val = REG_READ(PSB_PIPECONF(PSB_PIPE_B)); ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND); } diff --git a/drivers/staging/mrst/drv/psb_powermgmt.c b/drivers/staging/mrst/drv/psb_powermgmt.c index aa71a16..f340f80 100644 --- a/drivers/staging/mrst/drv/psb_powermgmt.c +++ b/drivers/staging/mrst/drv/psb_powermgmt.c @@ -477,7 +477,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) /* regester */ u32 dpll_reg = MRST_DPLL_A; u32 fp_reg = MRST_FPA0; - u32 pipeconf_reg = PIPEACONF; + u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); u32 htot_reg = PSB_HTOTAL(PSB_PIPE_A); u32 hblank_reg = PSB_HBLANK(PSB_PIPE_A); u32 hsync_reg = PSB_HSYNC(PSB_PIPE_A); @@ -485,15 +485,15 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) u32 vblank_reg = PSB_VBLANK(PSB_PIPE_A); u32 vsync_reg = PSB_VSYNC(PSB_PIPE_A); u32 pipesrc_reg = PSB_PIPESRC(PSB_PIPE_A); - u32 dspstride_reg = DSPASTRIDE; - u32 dsplinoff_reg = DSPALINOFF; - u32 dsptileoff_reg = DSPATILEOFF; - u32 dspsize_reg = DSPASIZE; - u32 dsppos_reg = DSPAPOS; - u32 dspsurf_reg = DSPASURF; + u32 dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_A); + u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A); + u32 dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_A); + u32 dspsize_reg = PSB_DSPSIZE(PSB_PIPE_A); + u32 dsppos_reg = PSB_DSPPOS(PSB_PIPE_A); + u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A); u32 mipi_reg = MIPI; - u32 dspcntr_reg = DSPACNTR; - u32 dspstatus_reg = PIPEASTAT; + u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); + u32 dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_A); u32 palette_reg = PALETTE_A; /* pointer to values */ @@ -526,7 +526,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) /* regester */ dpll_reg = MDFLD_DPLL_B; fp_reg = MDFLD_DPLL_DIV0; - pipeconf_reg = PIPEBCONF; + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B); htot_reg = PSB_HTOTAL(PSB_PIPE_B); hblank_reg = PSB_HBLANK(PSB_PIPE_B); hsync_reg = PSB_HSYNC(PSB_PIPE_B); @@ -534,14 +534,14 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) vblank_reg = PSB_VBLANK(PSB_PIPE_B); vsync_reg = PSB_VSYNC(PSB_PIPE_B); pipesrc_reg = PSB_PIPESRC(PSB_PIPE_B); - dspstride_reg = DSPBSTRIDE; - dsplinoff_reg = DSPBLINOFF; - dsptileoff_reg = DSPBTILEOFF; - dspsize_reg = DSPBSIZE; - dsppos_reg = DSPBPOS; - dspsurf_reg = DSPBSURF; - dspcntr_reg = DSPBCNTR; - dspstatus_reg = PIPEBSTAT; + dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_B); + dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_B); + dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_B); + dspsize_reg = PSB_DSPSIZE(PSB_PIPE_B); + dsppos_reg = PSB_DSPPOS(PSB_PIPE_B); + dspsurf_reg = PSB_DSPSURF(PSB_PIPE_B); + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B); + dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_B); palette_reg = PALETTE_B; /* values */ @@ -567,7 +567,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) break; case 2: /* regester */ - pipeconf_reg = PIPECCONF; + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); htot_reg = PSB_HTOTAL(PSB_PIPE_C); hblank_reg = PSB_HBLANK(PSB_PIPE_C); hsync_reg = PSB_HSYNC(PSB_PIPE_C); @@ -575,15 +575,15 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) vblank_reg = PSB_VBLANK(PSB_PIPE_C); vsync_reg = PSB_VSYNC(PSB_PIPE_C); pipesrc_reg = PSB_PIPESRC(PSB_PIPE_C); - dspstride_reg = DSPCSTRIDE; - dsplinoff_reg = DSPCLINOFF; - dsptileoff_reg = DSPCTILEOFF; - dspsize_reg = DSPCSIZE; - dsppos_reg = DSPCPOS; - dspsurf_reg = DSPCSURF; + dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_C); + dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C); + dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_C); + dspsize_reg = PSB_DSPSIZE(PSB_PIPE_C); + dsppos_reg = PSB_DSPPOS(PSB_PIPE_C); + dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C); mipi_reg = MIPI_C; - dspcntr_reg = DSPCCNTR; - dspstatus_reg = PIPECSTAT; + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); + dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_C); palette_reg = PALETTE_C; /* pointer to values */ @@ -699,7 +699,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) /* regester */ u32 dpll_reg = MRST_DPLL_A; u32 fp_reg = MRST_FPA0; - u32 pipeconf_reg = PIPEACONF; + u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); u32 htot_reg = PSB_HTOTAL(PSB_PIPE_A); u32 hblank_reg = PSB_HBLANK(PSB_PIPE_A); u32 hsync_reg = PSB_HSYNC(PSB_PIPE_A); @@ -707,15 +707,15 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) u32 vblank_reg = PSB_VBLANK(PSB_PIPE_A); u32 vsync_reg = PSB_VSYNC(PSB_PIPE_A); u32 pipesrc_reg = PSB_PIPESRC(PSB_PIPE_A); - u32 dspstride_reg = DSPASTRIDE; - u32 dsplinoff_reg = DSPALINOFF; - u32 dsptileoff_reg = DSPATILEOFF; - u32 dspsize_reg = DSPASIZE; - u32 dsppos_reg = DSPAPOS; - u32 dspsurf_reg = DSPASURF; - u32 dspstatus_reg = PIPEASTAT; + u32 dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_A); + u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A); + u32 dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_A); + u32 dspsize_reg = PSB_DSPSIZE(PSB_PIPE_A); + u32 dsppos_reg = PSB_DSPPOS(PSB_PIPE_A); + u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A); + u32 dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_A); u32 mipi_reg = MIPI; - u32 dspcntr_reg = DSPACNTR; + u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); u32 palette_reg = PALETTE_A; /* values */ @@ -749,7 +749,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) /* regester */ dpll_reg = MDFLD_DPLL_B; fp_reg = MDFLD_DPLL_DIV0; - pipeconf_reg = PIPEBCONF; + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B); htot_reg = PSB_HTOTAL(PSB_PIPE_B); hblank_reg = PSB_HBLANK(PSB_PIPE_B); hsync_reg = PSB_HSYNC(PSB_PIPE_B); @@ -757,14 +757,14 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) vblank_reg = PSB_VBLANK(PSB_PIPE_B); vsync_reg = PSB_VSYNC(PSB_PIPE_B); pipesrc_reg = PSB_PIPESRC(PSB_PIPE_B); - dspstride_reg = DSPBSTRIDE; - dsplinoff_reg = DSPBLINOFF; - dsptileoff_reg = DSPBTILEOFF; - dspsize_reg = DSPBSIZE; - dsppos_reg = DSPBPOS; - dspsurf_reg = DSPBSURF; - dspcntr_reg = DSPBCNTR; - dspstatus_reg = PIPEBSTAT; + dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_B); + dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_B); + dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_B); + dspsize_reg = PSB_DSPSIZE(PSB_PIPE_B); + dsppos_reg = PSB_DSPPOS(PSB_PIPE_B); + dspsurf_reg = PSB_DSPSURF(PSB_PIPE_B); + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B); + dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_B); palette_reg = PALETTE_B; /* values */ @@ -792,7 +792,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) dsi_output = dev_priv->dbi_output2; /* regester */ - pipeconf_reg = PIPECCONF; + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); htot_reg = PSB_HTOTAL(PSB_PIPE_C); hblank_reg = PSB_HBLANK(PSB_PIPE_C); hsync_reg = PSB_HSYNC(PSB_PIPE_C); @@ -800,15 +800,15 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) vblank_reg = PSB_VBLANK(PSB_PIPE_C); vsync_reg = PSB_VSYNC(PSB_PIPE_C); pipesrc_reg = PSB_PIPESRC(PSB_PIPE_C); - dspstride_reg = DSPCSTRIDE; - dsplinoff_reg = DSPCLINOFF; - dsptileoff_reg = DSPCTILEOFF; - dspsize_reg = DSPCSIZE; - dsppos_reg = DSPCPOS; - dspsurf_reg = DSPCSURF; + dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_C); + dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C); + dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_C); + dspsize_reg = PSB_DSPSIZE(PSB_PIPE_C); + dsppos_reg = PSB_DSPPOS(PSB_PIPE_C); + dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C); mipi_reg = MIPI_C; - dspcntr_reg = DSPCCNTR; - dspstatus_reg = PIPECSTAT; + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); + dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_C); palette_reg = PALETTE_C; /* values */ diff --git a/drivers/staging/mrst/drv/tpo_cmd.c b/drivers/staging/mrst/drv/tpo_cmd.c index 5bc327e..6f7c2ce 100644 --- a/drivers/staging/mrst/drv/tpo_cmd.c +++ b/drivers/staging/mrst/drv/tpo_cmd.c @@ -243,8 +243,8 @@ static void mdfld_dsi_dbi_mode_set(struct drm_encoder * encoder, int pipe = dsi_connector->pipe; /*regs*/ - u32 dspcntr_reg = DSPACNTR; - u32 pipeconf_reg = PIPEACONF; + u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); + u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); /*values*/ u32 dspcntr_val = dev_priv->dspcntr; @@ -262,8 +262,8 @@ static void mdfld_dsi_dbi_mode_set(struct drm_encoder * encoder, PSB_DEBUG_ENTRY("h %d v %d\n", mode->hdisplay, mode->vdisplay); if(pipe == 2) { - dspcntr_reg = DSPCCNTR; - pipeconf_reg = PIPECCONF; + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); dspcntr_val = dev_priv->dspcntr2; pipeconf_val = dev_priv->pipeconf2; } else { @@ -413,10 +413,10 @@ static void mdfld_dsi_dbi_update_fb (struct mdfld_dsi_dbi_output * dbi_output, i struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL; u32 dpll_reg = MRST_DPLL_A; - u32 dspcntr_reg = DSPACNTR; - u32 pipeconf_reg = PIPEACONF; - u32 dsplinoff_reg = DSPALINOFF; - u32 dspsurf_reg = DSPASURF; + u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); + u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); + u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A); + u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A); /*if mode setting on-going, back off*/ if((dbi_output->mode_flags & MODE_SETTING_ON_GOING) || @@ -425,10 +425,10 @@ static void mdfld_dsi_dbi_update_fb (struct mdfld_dsi_dbi_output * dbi_output, i return; if(pipe == 2) { - dspcntr_reg = DSPCCNTR; - pipeconf_reg = PIPECCONF; - dsplinoff_reg = DSPCLINOFF; - dspsurf_reg = DSPCSURF; + dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); + pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); + dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C); + dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C); } if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, true)) { -- 2.7.4