From 1c6b87ca5298358b0fa4226fc624605aa6163e68 Mon Sep 17 00:00:00 2001 From: Xingyu Wu Date: Mon, 24 Oct 2022 18:20:54 +0800 Subject: [PATCH] clk:starfive:Count PLL1 rate Count PLL1 rate through reading syscon registers. Signed-off-by: Xingyu Wu --- drivers/clk/starfive/clk-starfive-jh7110-pll.c | 6 +----- drivers/clk/starfive/clk-starfive-jh7110-sys.c | 2 -- 2 files changed, 1 insertion(+), 7 deletions(-) mode change 100755 => 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.c mode change 100755 => 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.c b/drivers/clk/starfive/clk-starfive-jh7110-pll.c old mode 100755 new mode 100644 index a82fe8c..e58dc4c --- a/drivers/clk/starfive/clk-starfive-jh7110-pll.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.c @@ -418,10 +418,6 @@ int __init clk_starfive_jh7110_pll_init(struct platform_device *pdev, .flags = 0, }; - /* pll1 use default freq and does not be changed */ - if (idx == PLL1_INDEX) - continue; - data = &pll_priv[idx]; data->dev = &pdev->dev; data->sys_syscon_regmap = pll_syscon_regmap; @@ -439,7 +435,7 @@ int __init clk_starfive_jh7110_pll_init(struct platform_device *pdev, return ret; } - dev_info(&pdev->dev, "PLL0 and PLL2 clock be set done\n"); + dev_dbg(&pdev->dev, "PLL0, PLL1 and PLL2 clock registered done\n"); /* Change PLL2 rate before other driver up */ if (PLL2_DEFAULT_FREQ) { diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c old mode 100755 new mode 100644 index 73051bb..10bb48f --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -485,7 +485,6 @@ int __init clk_starfive_jh7110_sys_init(struct platform_device *pdev, "pll0_out", "osc", 0, 1250000000); if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL0_OUT)])) return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL0_OUT)]); -#endif priv->pll[PLL_OF(JH7110_PLL1_OUT)] = clk_hw_register_fixed_rate(priv->dev, @@ -493,7 +492,6 @@ int __init clk_starfive_jh7110_sys_init(struct platform_device *pdev, if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL1_OUT)])) return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL1_OUT)]); -#ifndef CONFIG_CLK_STARFIVE_JH7110_PLL priv->pll[PLL_OF(JH7110_PLL2_OUT)] = clk_hw_register_fixed_rate(priv->dev, "pll2_out", "osc", 0, 1228800000); -- 2.7.4