From 1c4e9ae936eb4e9a6c8c22cdc38152a2a6f837a1 Mon Sep 17 00:00:00 2001 From: pengcheng chen Date: Thu, 22 Nov 2018 12:54:06 +0800 Subject: [PATCH] osd: fix osd color error when osd hdr enabled [1/1] PD#SWPL-1804 Problem: osd color error when osd hdr enabled Solution: div alpha when osd hdr enabled Verify: verified on u212 dev board Change-Id: I1f5ea0db404d1956f454bd5da2532bded89626ee Signed-off-by: pengcheng chen --- drivers/amlogic/media/osd/osd_debug.c | 6 ++++++ drivers/amlogic/media/osd/osd_hw.c | 15 +++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/amlogic/media/osd/osd_debug.c b/drivers/amlogic/media/osd/osd_debug.c index 9666960..f976439 100644 --- a/drivers/amlogic/media/osd/osd_debug.c +++ b/drivers/amlogic/media/osd/osd_debug.c @@ -199,10 +199,16 @@ static void osd_debug_dump_register_all(void) osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); reg = VPP_OSD2_BLD_V_SCOPE; osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); + reg = VD1_BLEND_SRC_CTRL; + osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); + reg = VD2_BLEND_SRC_CTRL; + osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); reg = OSD1_BLEND_SRC_CTRL; osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); reg = OSD2_BLEND_SRC_CTRL; osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); + reg = VIU_OSD_BLEND_CTRL1; + osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); reg = VPP_POSTBLEND_H_SIZE; osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); reg = VPP_OUT_H_V_SIZE; diff --git a/drivers/amlogic/media/osd/osd_hw.c b/drivers/amlogic/media/osd/osd_hw.c index 6569850..603b5b4 100644 --- a/drivers/amlogic/media/osd/osd_hw.c +++ b/drivers/amlogic/media/osd/osd_hw.c @@ -7238,6 +7238,7 @@ static void set_blend_reg(struct layer_blend_reg_s *blend_reg) { int i; u32 reg_offset = 2; + u32 osd1_alpha_div = 0, osd2_alpha_div = 0; #ifdef OSD_BLEND_SHIFT_WORKAROUND u32 osd_count = OSD_BLEND_LAYERS; #else @@ -7256,19 +7257,29 @@ static void set_blend_reg(struct layer_blend_reg_s *blend_reg) blend_reg->blend_din_en << 20| blend_reg->din_premult_en << 16| blend_reg->din_reoder_sel); + if (blend_reg->postbld_osd1_premult) + osd1_alpha_div = 1; + if (blend_reg->postbld_osd2_premult) + osd2_alpha_div = 1; + /* VIU_OSD_BLEND_CTRL1 */ + VSYNCOSD_WR_MPEG_REG(VIU_OSD_BLEND_CTRL1, + (osd1_alpha_div & 0x1) | + (3 << 4) | + ((osd2_alpha_div & 0x1) << 12) | + (3 << 16)); /* vpp osd1 blend ctrl */ VSYNCOSD_WR_MPEG_REG(OSD1_BLEND_SRC_CTRL, (0 & 0xf) << 0 | (0 & 0x1) << 4 | (blend_reg->postbld_src3_sel & 0xf) << 8 | - (blend_reg->postbld_osd1_premult & 0x1) << 16| + (0 << 16) | (1 & 0x1) << 20); /* vpp osd2 blend ctrl */ VSYNCOSD_WR_MPEG_REG(OSD2_BLEND_SRC_CTRL, (0 & 0xf) << 0 | (0 & 0x1) << 4 | (blend_reg->postbld_src4_sel & 0xf) << 8 | - (blend_reg->postbld_osd2_premult & 0x1) << 16 | + (0 << 16) | (1 & 0x1) << 20); VSYNCOSD_WR_MPEG_REG(VIU_OSD_BLEND_BLEND0_SIZE, -- 2.7.4