From 1ba0a3bbd5ed5a1bb8d0165912d9904b812af74b Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Tue, 21 Jun 2022 20:06:16 +0400 Subject: [PATCH] clk: qcom: msm8996-cpu: Rename DIV_2_INDEX to SMUX_INDEX The parent at this index is the secondary mux, which can connect not only to primary PLL/2 but also to XO. Rename the index to SMUX_INDEX to better reflect the parent. Signed-off-by: Yassine Oudjana Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220621160621.24415-2-y.oudjana@protonmail.com --- drivers/clk/qcom/clk-cpu-8996.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 4a4fde8..5dc68dc 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -61,7 +61,7 @@ #include "clk-regmap.h" enum _pmux_input { - DIV_2_INDEX = 0, + SMUX_INDEX = 0, PLL_INDEX, ACD_INDEX, ALT_INDEX, @@ -468,7 +468,7 @@ static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, case POST_RATE_CHANGE: if (cnd->new_rate < DIV_2_THRESHOLD) ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, - DIV_2_INDEX); + SMUX_INDEX); else ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ACD_INDEX); -- 2.7.4