From 1b3669a1ed320549a09185700e7e56086fc1064a Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 22 Jun 2023 15:59:31 -0700 Subject: [PATCH] intel: Initialize FF_MODE2 on all Gfx12 platforms MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit On Alchemist, the FF_MODE2 documentation says that we must set the FF_MODE2 timer values for GS and HS to 224. The hardware performance tuning guide also recommends setting the TDS timer to 4. On Tigerlake, i915 applies workarounds to set the GS timer to 224 (failing to do so can cause HS/DS unit hangs), and the TDS timer to 4 (for performance). It doesn't currently apply a HS timer there, and I'm not sure if it's strictly necessary, but given that Alchemist needed it, and the other two settings matched, let's assume that it ought to match as well. Unfortunately, there has been a bug in the i915 workarounds infrastructure for non-masked context registers where writing one field of the register zeroes out all the others. So, I believe the Tigerlake TDS timer value of 4 isn't being applied correctly there, though the register is also not readable on that platform which makes it hard to verify. So, this may also speed up tessellation. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9233 Reviewed-by: José Roberto de Souza Cc: mesa-stable Part-of: --- src/gallium/drivers/iris/iris_state.c | 29 +++++++++++++++++++++++++++++ src/intel/genxml/gen12.xml | 6 ++++++ src/intel/genxml/gen125.xml | 6 ++++++ src/intel/vulkan/genX_state.c | 29 +++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index a380312..e27274c 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -1244,6 +1244,35 @@ iris_init_render_context(struct iris_batch *batch) } #endif +#if GFX_VER == 12 + iris_emit_reg(batch, GENX(FF_MODE2), reg) { + /* On Alchemist, the FF_MODE2 docs for the GS timer say: + * + * "The timer value must be set to 224." + * + * and Wa_16011163337 indicates this is the case for all Gfx12 parts, + * and that this is necessary to avoid hanging the HS/DS units. It + * also clarifies that 224 is literally 0xE0 in the bits, not 7*32=224. + * + * The HS timer docs also have the same quote for Alchemist. I am + * unaware of a reason it needs to be set to 224 on Tigerlake, but + * we do so for consistency if nothing else. + * + * For the TDS timer value, the docs say: + * + * "For best performance, a value of 4 should be programmed." + * + * i915 also sets it this way on Tigerlake due to workarounds. + * + * The default VS timer appears to be 0, so we leave it at that. + */ + reg.GSTimerValue = 224; + reg.HSTimerValue = 224; + reg.TDSTimerValue = 4; + reg.VSTimerValue = 0; + } +#endif + #if INTEL_NEEDS_WORKAROUND_1508744258 /* The suggested workaround is: * diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index a611b54..d69e22b 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -6957,6 +6957,12 @@ + + + + + + diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml index fd330fe..26bf741 100644 --- a/src/intel/genxml/gen125.xml +++ b/src/intel/genxml/gen125.xml @@ -7445,6 +7445,12 @@ + + + + + + diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 16f95b7..cb364f0 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -484,6 +484,35 @@ init_render_queue_state(struct anv_queue *queue) } #endif +#if GFX_VER == 12 + anv_batch_write_reg(&batch, GENX(FF_MODE2), reg) { + /* On Alchemist, the FF_MODE2 docs for the GS timer say: + * + * "The timer value must be set to 224." + * + * and Wa_16011163337 indicates this is the case for all Gfx12 parts, + * and that this is necessary to avoid hanging the HS/DS units. It + * also clarifies that 224 is literally 0xE0 in the bits, not 7*32=224. + * + * The HS timer docs also have the same quote for Alchemist. I am + * unaware of a reason it needs to be set to 224 on Tigerlake, but + * we do so for consistency if nothing else. + * + * For the TDS timer value, the docs say: + * + * "For best performance, a value of 4 should be programmed." + * + * i915 also sets it this way on Tigerlake due to workarounds. + * + * The default VS timer appears to be 0, so we leave it at that. + */ + reg.GSTimerValue = 224; + reg.HSTimerValue = 224; + reg.TDSTimerValue = 4; + reg.VSTimerValue = 0; + } +#endif + #if INTEL_NEEDS_WA_1508744258 /* Disable RHWO by setting 0x7010[14] by default except during resolve * pass. -- 2.7.4