From 1ade7d1f9558805c4b3c5922f3fca2ee16f5caf7 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 20 May 2020 08:20:35 +0800 Subject: [PATCH] dt-bindings: gpio: Convert mxs to json-schema Convert the MXS GPIO binding to DT schema format using json-schema. Signed-off-by: Anson Huang Signed-off-by: Rob Herring --- .../devicetree/bindings/gpio/gpio-mxs.txt | 88 ------------- .../devicetree/bindings/gpio/gpio-mxs.yaml | 136 +++++++++++++++++++++ 2 files changed, 136 insertions(+), 88 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-mxs.txt create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mxs.yaml diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt b/Documentation/devicetree/bindings/gpio/gpio-mxs.txt deleted file mode 100644 index 1e677a4..0000000 --- a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt +++ /dev/null @@ -1,88 +0,0 @@ -* Freescale MXS GPIO controller - -The Freescale MXS GPIO controller is part of MXS PIN controller. The -GPIOs are organized in port/bank. Each port consists of 32 GPIOs. - -As the GPIO controller is embedded in the PIN controller and all the -GPIO ports share the same IO space with PIN controller, the GPIO node -will be represented as sub-nodes of MXS pinctrl node. - -Required properties for GPIO node: -- compatible : Should be "fsl,-gpio". The supported SoCs include - imx23 and imx28. -- interrupts : Should be the port interrupt shared by all 32 pins. -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells : Should be 2. The first cell is the GPIO number. - The second cell bits[3:0] is used to specify trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - -Note: Each GPIO port should have an alias correctly numbered in "aliases" -node. - -Examples: - -aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; -}; - -pinctrl@80018000 { - compatible = "fsl,imx28-pinctrl", "simple-bus"; - reg = <0x80018000 2000>; - - gpio0: gpio@0 { - compatible = "fsl,imx28-gpio"; - interrupts = <127>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@1 { - compatible = "fsl,imx28-gpio"; - interrupts = <126>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2 { - compatible = "fsl,imx28-gpio"; - interrupts = <125>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@3 { - compatible = "fsl,imx28-gpio"; - interrupts = <124>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@4 { - compatible = "fsl,imx28-gpio"; - interrupts = <123>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml new file mode 100644 index 0000000..ccf5b50 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/gpio-mxs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MXS GPIO controller + +maintainers: + - Shawn Guo + - Anson Huang + +description: | + The Freescale MXS GPIO controller is part of MXS PIN controller. + The GPIOs are organized in port/bank, each port consists of 32 GPIOs. + As the GPIO controller is embedded in the PIN controller and all the + GPIO ports share the same IO space with PIN controller, the GPIO node + will be represented as sub-nodes of MXS pinctrl node. + +properties: + compatible: + enum: + - fsl,imx23-pinctrl + - fsl,imx28-pinctrl + + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + reg: + maxItems: 1 + +patternProperties: + "gpio@[0-9]+$": + type: object + properties: + compatible: + enum: + - fsl,imx23-gpio + - fsl,imx28-gpio + + reg: + maxItems: 1 + + interrupts: + description: Should be the port interrupt shared by all 32 pins. + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + "#gpio-cells": + const: 2 + + gpio-controller: true + + required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - "#gpio-cells" + - gpio-controller + + additionalProperties: false + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + pinctrl@80018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-pinctrl"; + reg = <0x80018000 0x2000>; + + gpio@0 { + compatible = "fsl,imx28-gpio"; + reg = <0>; + interrupts = <127>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio@1 { + compatible = "fsl,imx28-gpio"; + reg = <1>; + interrupts = <126>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio@2 { + compatible = "fsl,imx28-gpio"; + reg = <2>; + interrupts = <125>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio@3 { + compatible = "fsl,imx28-gpio"; + reg = <3>; + interrupts = <124>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio@4 { + compatible = "fsl,imx28-gpio"; + reg = <4>; + interrupts = <123>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; -- 2.7.4