From 1ab1c05855c55be2a9917c517f82416a462e7a35 Mon Sep 17 00:00:00 2001 From: Jian Hu Date: Thu, 4 Apr 2019 10:36:49 +0800 Subject: [PATCH] clk: tm2: dspb clock does not work [1/1] PD#SWPL-5636 Problem: dspb clock does not work Solution: the dspb clocks describe the wrong register, fix it. Verify: test passed on tm2 ab3100 Change-Id: I9ef0fb432bc3394843fb397392fc02f5c613cec0 Signed-off-by: Jian Hu --- drivers/amlogic/clk/tm2/tm2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/amlogic/clk/tm2/tm2.c b/drivers/amlogic/clk/tm2/tm2.c index 5621ff5..529d42d 100644 --- a/drivers/amlogic/clk/tm2/tm2.c +++ b/drivers/amlogic/clk/tm2/tm2.c @@ -145,7 +145,7 @@ static MUX(dspb_clk_a_mux, HHI_DSP_CLK_CNTL, 0x7, 20, dsp_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED); static DIV(dspb_clk_a_div, HHI_DSP_CLK_CNTL, 16, 4, "dspb_clk_a_mux", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT); -static GATE(dspb_clk_a_gate, HHI_SD_EMMC_CLK_CNTL, 23, "dspb_clk_a_div", +static GATE(dspb_clk_a_gate, HHI_DSP_CLK_CNTL, 23, "dspb_clk_a_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT); static MUX(dspb_clk_b_mux, HHI_DSP_CLK_CNTL, 0x7, 28, @@ -158,7 +158,7 @@ static GATE(dspb_clk_b_gate, HHI_DSP_CLK_CNTL, 23, "dspb_clk_b_div", PNAME(dspb_parent_names) = { "dspb_clk_a_gate", "dspb_clk_b_gate" }; -static MESON_MUX(dspb_clk_mux, HHI_VPU_CLKC_CNTL, 0x1, 31, +static MESON_MUX(dspb_clk_mux, HHI_DSP_CLK_CNTL, 0x1, 31, dspb_parent_names, CLK_GET_RATE_NOCACHE); static struct clk_gate *tm2_clk_gates[] = { -- 2.7.4