From 1a4d165683ac3caf3ea0fdb207ca6d9e57970e2f Mon Sep 17 00:00:00 2001 From: Italo Nicola Date: Thu, 30 Jul 2020 16:57:55 +0000 Subject: [PATCH] pan/mdg: defer register packing This commit moves the packing of registers and other things from install_registers_instr() to midgard_emit.c, right before emitting the binary. Signed-off-by: Italo Nicola Reviewed-by: Alyssa Rosenzweig Part-of: --- src/panfrost/midgard/midgard_emit.c | 91 ++++++++++++++++++++++++++++++++++--- src/panfrost/midgard/midgard_ra.c | 72 +++++++++-------------------- 2 files changed, 105 insertions(+), 58 deletions(-) diff --git a/src/panfrost/midgard/midgard_emit.c b/src/panfrost/midgard/midgard_emit.c index b56c244..5878669 100644 --- a/src/panfrost/midgard/midgard_emit.c +++ b/src/panfrost/midgard/midgard_emit.c @@ -276,7 +276,7 @@ mir_pack_swizzle(unsigned mask, unsigned *swizzle, } static void -mir_pack_vector_srcs(midgard_instruction *ins) +mir_pack_vector_srcs(midgard_instruction *ins, midgard_vector_alu *alu) { bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->op].props); @@ -306,13 +306,13 @@ mir_pack_vector_srcs(midgard_instruction *ins) .half = half, .swizzle = swizzle }; - + unsigned p = vector_alu_srco_unsigned(pack); if (i == 0) - ins->alu.src1 = p; + alu->src1 = p; else - ins->alu.src2 = p; + alu->src2 = p; } } @@ -492,6 +492,23 @@ load_store_from_instr(midgard_instruction *ins) { midgard_load_store_word ldst = ins->load_store; ldst.op = ins->op; + + if (OP_IS_STORE(ldst.op)) { + ldst.reg = SSA_REG_FROM_FIXED(ins->src[0]) & 1; + } else { + ldst.reg = SSA_REG_FROM_FIXED(ins->dest); + } + + if (ins->src[1] != ~0) { + unsigned src = SSA_REG_FROM_FIXED(ins->src[1]); + ldst.arg_1 |= midgard_ldst_reg(src, ins->swizzle[1][0]); + } + + if (ins->src[2] != ~0) { + unsigned src = SSA_REG_FROM_FIXED(ins->src[2]); + ldst.arg_2 |= midgard_ldst_reg(src, ins->swizzle[2][0]); + } + return ldst; } @@ -500,6 +517,42 @@ texture_word_from_instr(midgard_instruction *ins) { midgard_texture_word tex = ins->texture; tex.op = ins->op; + + unsigned src1 = ins->src[1] == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->src[1]); + tex.in_reg_select = src1 & 1; + + unsigned dest = ins->dest == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->dest); + tex.out_reg_select = dest & 1; + + if (ins->src[2] != ~0) { + midgard_tex_register_select sel = { + .select = SSA_REG_FROM_FIXED(ins->src[2]) & 1, + .full = 1, + .component = ins->swizzle[2][0] + }; + uint8_t packed; + memcpy(&packed, &sel, sizeof(packed)); + tex.bias = packed; + } + + if (ins->src[3] != ~0) { + unsigned x = ins->swizzle[3][0]; + unsigned y = x + 1; + unsigned z = x + 2; + + /* Check range, TODO: half-registers */ + assert(z < 4); + + unsigned offset_reg = SSA_REG_FROM_FIXED(ins->src[3]); + tex.offset = + (1) | /* full */ + (offset_reg & 1) << 1 | /* select */ + (0 << 2) | /* upper */ + (x << 3) | /* swizzle */ + (y << 5) | /* swizzle */ + (z << 7); /* swizzle */ + } + return tex; } @@ -510,6 +563,18 @@ vector_alu_from_instr(midgard_instruction *ins) alu.op = ins->op; alu.outmod = ins->outmod; alu.reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins)); + + if (ins->has_inline_constant) { + /* Encode inline 16-bit constant. See disassembler for + * where the algorithm is from */ + + int lower_11 = ins->inline_constant & ((1 << 12) - 1); + uint16_t imm = ((lower_11 >> 8) & 0x7) | + ((lower_11 & 0xFF) << 3); + + alu.src2 = imm << 2; + } + return alu; } @@ -531,7 +596,19 @@ emit_alu_bundle(compiler_context *ctx, /* Otherwise, just emit the registers */ uint16_t reg_word = 0; - memcpy(®_word, &ins->registers, sizeof(uint16_t)); + midgard_reg_info registers = { + .src1_reg = (ins->src[0] == ~0 ? + REGISTER_UNUSED : + SSA_REG_FROM_FIXED(ins->src[0])), + .src2_reg = (ins->src[1] == ~0 ? + ins->inline_constant >> 11 : + SSA_REG_FROM_FIXED(ins->src[1])), + .src2_imm = ins->has_inline_constant, + .out_reg = (ins->dest == ~0 ? + REGISTER_UNUSED : + SSA_REG_FROM_FIXED(ins->dest)), + }; + memcpy(®_word, ®isters, sizeof(uint16_t)); util_dynarray_append(emission, uint16_t, reg_word); } @@ -555,9 +632,9 @@ emit_alu_bundle(compiler_context *ctx, if (ins->unit & UNITS_ANY_VECTOR) { mir_pack_mask_alu(ins); - mir_pack_vector_srcs(ins); - size = sizeof(midgard_vector_alu); source_alu = vector_alu_from_instr(ins); + mir_pack_vector_srcs(ins, &source_alu); + size = sizeof(midgard_vector_alu); source = &source_alu; } else if (ins->unit == ALU_ENAB_BR_COMPACT) { size = sizeof(midgard_branch_cond); diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c index e3781bb..1b8c8c3 100644 --- a/src/panfrost/midgard/midgard_ra.c +++ b/src/panfrost/midgard/midgard_ra.c @@ -685,29 +685,14 @@ install_registers_instr( dest.offset; offset_swizzle(ins->swizzle[0], src1.offset, src1.shift, dest.shift, dest_offset); - - ins->registers.src1_reg = src1.reg; - - ins->registers.src2_imm = ins->has_inline_constant; - - if (ins->has_inline_constant) { - /* Encode inline 16-bit constant. See disassembler for - * where the algorithm is from */ - - ins->registers.src2_reg = ins->inline_constant >> 11; - - int lower_11 = ins->inline_constant & ((1 << 12) - 1); - uint16_t imm = ((lower_11 >> 8) & 0x7) | - ((lower_11 & 0xFF) << 3); - - ins->alu.src2 = imm << 2; - } else { + if (!ins->has_inline_constant) offset_swizzle(ins->swizzle[1], src2.offset, src2.shift, dest.shift, dest_offset); - - ins->registers.src2_reg = src2.reg; - } - - ins->registers.out_reg = dest.reg; + if (ins->src[0] != ~0) + ins->src[0] = SSA_FIXED_REGISTER(src1.reg); + if (ins->src[1] != ~0) + ins->src[1] = SSA_FIXED_REGISTER(src2.reg); + if (ins->dest != ~0) + ins->dest = SSA_FIXED_REGISTER(dest.reg); break; } @@ -722,12 +707,12 @@ install_registers_instr( struct phys_reg src = index_to_reg(ctx, l, ins->src[0], src_shift[0]); assert(src.reg == 26 || src.reg == 27); - ins->load_store.reg = src.reg - 26; + ins->src[0] = SSA_FIXED_REGISTER(src.reg); offset_swizzle(ins->swizzle[0], src.offset, src.shift, 0, 0); } else { struct phys_reg dst = index_to_reg(ctx, l, ins->dest, dest_shift); - ins->load_store.reg = dst.reg; + ins->dest = SSA_FIXED_REGISTER(dst.reg); offset_swizzle(ins->swizzle[0], 0, 2, 2, dst.offset); mir_set_bytemask(ins, mir_bytemask(ins) << dst.offset); } @@ -741,14 +726,16 @@ install_registers_instr( struct phys_reg src = index_to_reg(ctx, l, src2, 2); unsigned component = src.offset >> src.shift; assert(component << src.shift == src.offset); - ins->load_store.arg_1 |= midgard_ldst_reg(src.reg, component); + ins->src[1] = SSA_FIXED_REGISTER(src.reg); + ins->swizzle[1][0] = component; } if (src3 != ~0) { struct phys_reg src = index_to_reg(ctx, l, src3, 2); unsigned component = src.offset >> src.shift; assert(component << src.shift == src.offset); - ins->load_store.arg_2 |= midgard_ldst_reg(src.reg, component); + ins->src[2] = SSA_FIXED_REGISTER(src.reg); + ins->swizzle[2][0] = component; } break; @@ -765,11 +752,13 @@ install_registers_instr( struct phys_reg offset = index_to_reg(ctx, l, ins->src[3], src_shift[3]); /* First, install the texture coordinate */ - ins->texture.in_reg_select = coord.reg & 1; + if (ins->src[1] != ~0) + ins->src[1] = SSA_FIXED_REGISTER(coord.reg); offset_swizzle(ins->swizzle[1], coord.offset, coord.shift, dest.shift, 0); /* Next, install the destination */ - ins->texture.out_reg_select = dest.reg & 1; + if (ins->dest != ~0) + ins->dest = SSA_FIXED_REGISTER(dest.reg); offset_swizzle(ins->swizzle[0], 0, 2, dest.shift, dest_shift == 1 ? dest.offset % 8 : dest.offset); @@ -778,33 +767,14 @@ install_registers_instr( /* If there is a register LOD/bias, use it */ if (ins->src[2] != ~0) { assert(!(lod.offset & 3)); - midgard_tex_register_select sel = { - .select = lod.reg & 1, - .full = 1, - .component = lod.offset / 4 - }; - - uint8_t packed; - memcpy(&packed, &sel, sizeof(packed)); - ins->texture.bias = packed; + ins->src[2] = SSA_FIXED_REGISTER(lod.reg); + ins->swizzle[2][0] = lod.offset / 4; } /* If there is an offset register, install it */ if (ins->src[3] != ~0) { - unsigned x = offset.offset / 4; - unsigned y = x + 1; - unsigned z = x + 2; - - /* Check range, TODO: half-registers */ - assert(z < 4); - - ins->texture.offset = - (1) | /* full */ - (offset.reg & 1) << 1 | /* select */ - (0 << 2) | /* upper */ - (x << 3) | /* swizzle */ - (y << 5) | /* swizzle */ - (z << 7); /* swizzle */ + ins->src[3] = SSA_FIXED_REGISTER(offset.reg); + ins->swizzle[3][0] = offset.offset / 4; } break; -- 2.7.4