From 19d434b42bba324342af5307bcb13ee3fe875fb8 Mon Sep 17 00:00:00 2001 From: Tao Jing Date: Tue, 22 Nov 2011 12:45:25 +0800 Subject: [PATCH] Port from k35: camera drivers updated to ww45 including the following patches: http://android.intel.com:8080/#change,22630 http://android.intel.com:8080/#change,22612 http://android.intel.com:8080/#change,22755 http://android.intel.com:8080/#change,22396 http://android.intel.com:8080/#change,21860 http://android.intel.com:8080/#change,22699 Change-Id: Iec91a5eb24d5bd3b7090a0f55170ce1d7064e237 Signed-off-by: Tao Jing Reviewed-on: http://android.intel.com:8080/24969 Reviewed-by: Gross, Mark Tested-by: Gross, Mark --- drivers/media/video/atomisp/atomisp_cmd.c | 36 +++- drivers/media/video/atomisp/atomisp_fops.c | 1 + drivers/media/video/atomisp/atomisp_ioctl.c | 10 + drivers/media/video/atomisp/css/hrt/gdc_defs.h | 9 + drivers/media/video/atomisp/css/hrt/sp.map.h | 215 ++++++++++----------- drivers/media/video/atomisp/css/sh_css.c | 113 ++++++----- .../media/video/atomisp/css/sh_css_accelerate.c | 42 +++- .../media/video/atomisp/css/sh_css_accelerate.h | 2 +- drivers/media/video/atomisp/css/sh_css_binary.c | 14 +- drivers/media/video/atomisp/css/sh_css_binary.h | 24 +-- .../media/video/atomisp/css/sh_css_binary_info.h | 174 ++++++----------- drivers/media/video/atomisp/css/sh_css_defs.h | 9 +- drivers/media/video/atomisp/css/sh_css_internal.h | 1 + drivers/media/video/atomisp/css/sh_css_params.c | 16 +- drivers/media/video/atomisp/css/sh_css_params.h | 3 - drivers/media/video/atomisp/css/sh_css_sp.c | 6 +- drivers/media/video/atomisp/css/sh_css_sp.h | 3 +- drivers/media/video/atomisp/css/sh_css_sp_start.c | 17 +- drivers/media/video/atomisp/css/sh_css_sp_start.h | 3 +- drivers/media/video/atomisp/css/sh_css_types.h | 12 +- .../atomisp/include/atomisp/atomisp_internal.h | 3 + drivers/media/video/mt9e013.c | 5 +- drivers/media/video/mt9m114.c | 109 +++++++++-- drivers/media/video/mt9m114.h | 46 ++++- 24 files changed, 493 insertions(+), 380 deletions(-) diff --git a/drivers/media/video/atomisp/atomisp_cmd.c b/drivers/media/video/atomisp/atomisp_cmd.c index a309c16..9034eb6 100644 --- a/drivers/media/video/atomisp/atomisp_cmd.c +++ b/drivers/media/video/atomisp/atomisp_cmd.c @@ -484,6 +484,8 @@ static int atomisp_timeout_handler(struct atomisp_device *isp, int cnt) v4l2_err(&atomisp_dev, "ISP timeout\n"); + isp->isp_timeout = true; + /* Try 5 times for autorecovery */ if (cnt < 5) { atomisp_pipe_reset(isp); @@ -589,6 +591,9 @@ void atomisp_work(struct work_struct *work) */ mutex_lock(&isp->isp_lock); + /* restore isp normal status */ + isp->isp_timeout = false; + ret = atomisp_start_binary(isp); if (ret) { mutex_unlock(&isp->isp_lock); @@ -2801,12 +2806,6 @@ static int atomisp_get_effective_resolution(struct atomisp_device *isp, ~(ATOM_ISP_STEP_WIDTH - 1)); in_fmt->height = (in_fmt->height & ~(ATOM_ISP_STEP_HEIGHT - 1)); - if (isp->params.gdc_cac_en) { - if (in_fmt->width > ISP_POST_GDC_MAX_OUTPUT_WIDTH) - in_fmt->width = ISP_POST_GDC_MAX_OUTPUT_WIDTH; - if (in_fmt->height > ISP_POST_GDC_MAX_OUTPUT_HEIGHT) - in_fmt->height = ISP_POST_GDC_MAX_OUTPUT_HEIGHT; - } } else { in_fmt->width = out_width; in_fmt->height = out_height; @@ -3145,7 +3144,7 @@ atomisp_acc_get_fw(struct atomisp_device *isp, unsigned int handle) count > 0 && i < ATOMISP_ACC_FW_MAX; i++) { if (isp->acc_fw[i] == NULL) continue; - if (isp->acc_fw[i]->handle == handle) + if (isp->acc_fw[i]->header.handle == handle) break; count--; } @@ -3277,7 +3276,7 @@ atomisp_acc_fw_alloc(struct atomisp_device *isp, break; } user_fw->fw_handle = isp->acc_fw_handle; - fw->handle = isp->acc_fw_handle; + fw->header.handle = isp->acc_fw_handle; isp->acc_fw[i] = fw; isp->acc_fw_handle++; @@ -3663,7 +3662,28 @@ int atomisp_restore_iunit_reg(struct atomisp_device *isp) int atomisp_ospm_power_island_down(struct atomisp_device *isp) { u32 pwr_cnt = 0; + int timeout = 100; + bool idle; + /* if ISP timeout, we can force powerdown */ + if (isp->isp_timeout) { + isp->isp_timeout = false; + goto done; + } + + idle = sh_css_hrt_system_is_idle(); + while (!idle && timeout--) { + udelay(20); + idle = sh_css_hrt_system_is_idle(); + } + + if (timeout < 0) { + v4l2_err(&atomisp_dev, + "Timeout to stop ISP HW\n"); + return -EINVAL; + } + +done: /* power down DPHY */ pwr_cnt = atomisp_msg_read32(isp, IUNITPHY_PORT, CSI_CONTROL); pwr_cnt |= 0x300; diff --git a/drivers/media/video/atomisp/atomisp_fops.c b/drivers/media/video/atomisp/atomisp_fops.c index 4c71265..acac218 100644 --- a/drivers/media/video/atomisp/atomisp_fops.c +++ b/drivers/media/video/atomisp/atomisp_fops.c @@ -229,6 +229,7 @@ int atomisp_init_struct(struct atomisp_device *isp) isp->sw_contex.work_queued = false; isp->sw_contex.error = false; isp->sw_contex.file_input = 0; + isp->isp_timeout = false; /* Add for channel */ if (isp->inputs[0].camera) diff --git a/drivers/media/video/atomisp/atomisp_ioctl.c b/drivers/media/video/atomisp/atomisp_ioctl.c index acf8d93..35350e4 100644 --- a/drivers/media/video/atomisp/atomisp_ioctl.c +++ b/drivers/media/video/atomisp/atomisp_ioctl.c @@ -90,6 +90,15 @@ static struct v4l2_queryctrl ci_v4l2_controls[] = { .default_value = 0, }, { + .id = V4L2_CID_POWER_LINE_FREQUENCY, + .type = V4L2_CTRL_TYPE_MENU, + .name = "Light frequency filter", + .minimum = 1, + .maximum = 2, + .step = 1, + .default_value = 1, + }, + { .id = V4L2_CID_COLORFX, .type = V4L2_CTRL_TYPE_INTEGER, .name = "Image Color Effect", @@ -1152,6 +1161,7 @@ static int atomisp_s_ctrl(struct file *file, void *fh, switch (control->id) { case V4L2_CID_HFLIP: case V4L2_CID_VFLIP: + case V4L2_CID_POWER_LINE_FREQUENCY: ret = v4l2_subdev_call(isp->inputs[isp->input_curr].camera, core, s_ctrl, control); break; diff --git a/drivers/media/video/atomisp/css/hrt/gdc_defs.h b/drivers/media/video/atomisp/css/hrt/gdc_defs.h index 864dacf..fdbc9fe 100644 --- a/drivers/media/video/atomisp/css/hrt/gdc_defs.h +++ b/drivers/media/video/atomisp/css/hrt/gdc_defs.h @@ -108,4 +108,13 @@ #define HRT_GDC_PACK_CMD(cmd) ((cmd) | (1 << HRT_GDC_CRUN_BIT)) #endif +#define HRT_GDC_MAX_DX 1023 +#define HRT_GDC_MAX_DY 1023 +#define HRT_GDC_MAX_PX (128*16) +#define HRT_GDC_MAX_PY (64*16) +#define HRT_GDC_MAX_WOIX 2048 +#define HRT_GDC_MAX_WOIY 16 +#define HRT_GDC_MAX_OXDIM 4096 +#define HRT_GDC_MAX_OYDIM 64 + #endif /* _GDC_DEFS_H_ */ diff --git a/drivers/media/video/atomisp/css/hrt/sp.map.h b/drivers/media/video/atomisp/css/hrt/sp.map.h index 7b1821f..682e902 100644 --- a/drivers/media/video/atomisp/css/hrt/sp.map.h +++ b/drivers/media/video/atomisp/css/hrt/sp.map.h @@ -33,322 +33,319 @@ _hrt_cell_load_program_from_elf_file(proc, "sp") #define HIVE_MEM_isp_vectors_per_input_line scalar_processor_dmem -#define HIVE_ADDR_isp_vectors_per_input_line 0xF38 +#define HIVE_ADDR_isp_vectors_per_input_line 0xEF8 #define HIVE_SIZE_isp_vectors_per_input_line 4 #define HIVE_MEM_sp_raw_copy_thread scalar_processor_dmem -#define HIVE_ADDR_sp_raw_copy_thread 0xA8 +#define HIVE_ADDR_sp_raw_copy_thread 0xA0 #define HIVE_SIZE_sp_raw_copy_thread 4 #define HIVE_MEM_sp_input_v_addr scalar_processor_dmem -#define HIVE_ADDR_sp_input_v_addr 0xF3C +#define HIVE_ADDR_sp_input_v_addr 0xEFC #define HIVE_SIZE_sp_input_v_addr 4 #define HIVE_MEM_dma_proxy_status scalar_processor_dmem -#define HIVE_ADDR_dma_proxy_status 0xCC +#define HIVE_ADDR_dma_proxy_status 0xC4 #define HIVE_SIZE_dma_proxy_status 4 #define HIVE_MEM_sp_bin_copy_bytes_available scalar_processor_dmem -#define HIVE_ADDR_sp_bin_copy_bytes_available 0x3914 +#define HIVE_ADDR_sp_bin_copy_bytes_available 0x27D8 #define HIVE_SIZE_sp_bin_copy_bytes_available 4 #define HIVE_MEM_sp_error scalar_processor_dmem -#define HIVE_ADDR_sp_error 0x39C0 +#define HIVE_ADDR_sp_error 0x2884 #define HIVE_SIZE_sp_error 4 #define HIVE_MEM_sp_read_sp_group_from_ddr scalar_processor_dmem -#define HIVE_ADDR_sp_read_sp_group_from_ddr 0xF40 +#define HIVE_ADDR_sp_read_sp_group_from_ddr 0xF00 #define HIVE_SIZE_sp_read_sp_group_from_ddr 4 #define HIVE_MEM_sp_raw_copy_width scalar_processor_dmem -#define HIVE_ADDR_sp_raw_copy_width 0x3990 +#define HIVE_ADDR_sp_raw_copy_width 0x2854 #define HIVE_SIZE_sp_raw_copy_width 4 #define HIVE_MEM_sp_if_a scalar_processor_dmem -#define HIVE_ADDR_sp_if_a 0x3928 +#define HIVE_ADDR_sp_if_a 0x27EC #define HIVE_SIZE_sp_if_a 48 #define HIVE_MEM_sp_no_side_band scalar_processor_dmem -#define HIVE_ADDR_sp_no_side_band 0xF44 +#define HIVE_ADDR_sp_no_side_band 0xF04 #define HIVE_SIZE_sp_no_side_band 4 #define HIVE_MEM_sp_raw_copy_max_input_width scalar_processor_dmem -#define HIVE_ADDR_sp_raw_copy_max_input_width 0x3994 +#define HIVE_ADDR_sp_raw_copy_max_input_width 0x2858 #define HIVE_SIZE_sp_raw_copy_max_input_width 4 #define HIVE_MEM_sp_ch_id scalar_processor_dmem -#define HIVE_ADDR_sp_ch_id 0xF48 +#define HIVE_ADDR_sp_ch_id 0xF08 #define HIVE_SIZE_sp_ch_id 4 #define HIVE_MEM_sp_sync_gen_vblank_cycles scalar_processor_dmem -#define HIVE_ADDR_sp_sync_gen_vblank_cycles 0xF4C +#define HIVE_ADDR_sp_sync_gen_vblank_cycles 0xF0C #define HIVE_SIZE_sp_sync_gen_vblank_cycles 4 #define HIVE_MEM_sp_prbs_seed scalar_processor_dmem -#define HIVE_ADDR_sp_prbs_seed 0xF50 +#define HIVE_ADDR_sp_prbs_seed 0xF10 #define HIVE_SIZE_sp_prbs_seed 4 #define HIVE_MEM_sp_tpg_x_mask scalar_processor_dmem -#define HIVE_ADDR_sp_tpg_x_mask 0xF54 +#define HIVE_ADDR_sp_tpg_x_mask 0xF14 #define HIVE_SIZE_sp_tpg_x_mask 4 #define HIVE_MEM_xmem_bin_addr scalar_processor_dmem -#define HIVE_ADDR_xmem_bin_addr 0xF58 +#define HIVE_ADDR_xmem_bin_addr 0xF18 #define HIVE_SIZE_xmem_bin_addr 4 #define HIVE_MEM_sp_fmt_type scalar_processor_dmem -#define HIVE_ADDR_sp_fmt_type 0xF5C +#define HIVE_ADDR_sp_fmt_type 0xF1C #define HIVE_SIZE_sp_fmt_type 4 #define HIVE_MEM_sp_uds_config scalar_processor_dmem -#define HIVE_ADDR_sp_uds_config 0x39B0 +#define HIVE_ADDR_sp_uds_config 0x2874 #define HIVE_SIZE_sp_uds_config 16 #define HIVE_MEM_sp_isp_started scalar_processor_dmem -#define HIVE_ADDR_sp_isp_started 0xF60 +#define HIVE_ADDR_sp_isp_started 0xF20 #define HIVE_SIZE_sp_isp_started 4 #define HIVE_MEM_sp_obarea_start_bq scalar_processor_dmem -#define HIVE_ADDR_sp_obarea_start_bq 0xF64 +#define HIVE_ADDR_sp_obarea_start_bq 0xF24 #define HIVE_SIZE_sp_obarea_start_bq 4 #define HIVE_MEM_sp_start_isp_thread scalar_processor_dmem -#define HIVE_ADDR_sp_start_isp_thread 0x188 +#define HIVE_ADDR_sp_start_isp_thread 0x180 #define HIVE_SIZE_sp_start_isp_thread 4 #define HIVE_MEM_sp_proxy_thread scalar_processor_dmem -#define HIVE_ADDR_sp_proxy_thread 0xD4 +#define HIVE_ADDR_sp_proxy_thread 0xCC #define HIVE_SIZE_sp_proxy_thread 4 #define HIVE_MEM_sp_bin_copy_bytes_copied scalar_processor_dmem -#define HIVE_ADDR_sp_bin_copy_bytes_copied 0x3918 +#define HIVE_ADDR_sp_bin_copy_bytes_copied 0x27DC #define HIVE_SIZE_sp_bin_copy_bytes_copied 4 #define HIVE_MEM_sp_raw_copy_height scalar_processor_dmem -#define HIVE_ADDR_sp_raw_copy_height 0x3998 +#define HIVE_ADDR_sp_raw_copy_height 0x285C #define HIVE_SIZE_sp_raw_copy_height 4 #define HIVE_MEM_sp_raw_copy_out scalar_processor_dmem -#define HIVE_ADDR_sp_raw_copy_out 0x399C +#define HIVE_ADDR_sp_raw_copy_out 0x2860 #define HIVE_SIZE_sp_raw_copy_out 4 #define HIVE_MEM_isp_sh_dma_cmd_buffer scalar_processor_dmem -#define HIVE_ADDR_isp_sh_dma_cmd_buffer 0x39C4 +#define HIVE_ADDR_isp_sh_dma_cmd_buffer 0x2888 #define HIVE_SIZE_isp_sh_dma_cmd_buffer 4 #define HIVE_MEM_sp_overlay_bg_u scalar_processor_dmem -#define HIVE_ADDR_sp_overlay_bg_u 0xF68 +#define HIVE_ADDR_sp_overlay_bg_u 0xF28 #define HIVE_SIZE_sp_overlay_bg_u 4 #define HIVE_MEM_vf_pp_args scalar_processor_dmem -#define HIVE_ADDR_vf_pp_args 0x3B20 +#define HIVE_ADDR_vf_pp_args 0x29E4 #define HIVE_SIZE_vf_pp_args 76 #define HIVE_MEM_sp_sync_gen_width scalar_processor_dmem -#define HIVE_ADDR_sp_sync_gen_width 0xF6C +#define HIVE_ADDR_sp_sync_gen_width 0xF2C #define HIVE_SIZE_sp_sync_gen_width 4 -#define HIVE_ADDR_vf_pp_dynamic_entry 0x16C7 +#define HIVE_ADDR_vf_pp_dynamic_entry 0x16E4 #define HIVE_MEM_current_thread scalar_processor_dmem -#define HIVE_ADDR_current_thread 0x39A8 +#define HIVE_ADDR_current_thread 0x286C #define HIVE_SIZE_current_thread 4 #define HIVE_MEM_sp_dma_output_block_width_b scalar_processor_dmem -#define HIVE_ADDR_sp_dma_output_block_width_b 0x3A08 +#define HIVE_ADDR_sp_dma_output_block_width_b 0x28CC #define HIVE_SIZE_sp_dma_output_block_width_b 4 #define HIVE_ADDR_sp_raw_copy_entry 0x486 #define HIVE_MEM_sp_tpg_x_delta scalar_processor_dmem -#define HIVE_ADDR_sp_tpg_x_delta 0xF70 +#define HIVE_ADDR_sp_tpg_x_delta 0xF30 #define HIVE_SIZE_sp_tpg_x_delta 4 #define HIVE_ADDR_sp_init_dmem_entry 0x77 #define HIVE_MEM_sp_overlay_v_addr scalar_processor_dmem -#define HIVE_ADDR_sp_overlay_v_addr 0xF74 +#define HIVE_ADDR_sp_overlay_v_addr 0xF34 #define HIVE_SIZE_sp_overlay_v_addr 4 #define HIVE_MEM_sp_obarea_length_bq scalar_processor_dmem -#define HIVE_ADDR_sp_obarea_length_bq 0xF78 +#define HIVE_ADDR_sp_obarea_length_bq 0xF38 #define HIVE_SIZE_sp_obarea_length_bq 4 #define HIVE_MEM_capture_pp_args scalar_processor_dmem -#define HIVE_ADDR_capture_pp_args 0x3B6C +#define HIVE_ADDR_capture_pp_args 0x2A30 #define HIVE_SIZE_capture_pp_args 12 -#define HIVE_MEM_vtmp4 scalar_processor_dmem -#define HIVE_ADDR_vtmp4 0xF7C -#define HIVE_SIZE_vtmp4 512 #define HIVE_MEM_sp_bin_copy_out scalar_processor_dmem -#define HIVE_ADDR_sp_bin_copy_out 0x391C +#define HIVE_ADDR_sp_bin_copy_out 0x27E0 #define HIVE_SIZE_sp_bin_copy_out 4 #define HIVE_MEM_sp_dma_crop_block_width_b scalar_processor_dmem -#define HIVE_ADDR_sp_dma_crop_block_width_b 0x3A0C +#define HIVE_ADDR_sp_dma_crop_block_width_b 0x28D0 #define HIVE_SIZE_sp_dma_crop_block_width_b 4 #define HIVE_MEM_sp_overlay_start_x scalar_processor_dmem -#define HIVE_ADDR_sp_overlay_start_x 0x117C +#define HIVE_ADDR_sp_overlay_start_x 0xF3C #define HIVE_SIZE_sp_overlay_start_x 4 #define HIVE_MEM_sp_output_v_addr scalar_processor_dmem -#define HIVE_ADDR_sp_output_v_addr 0x1180 +#define HIVE_ADDR_sp_output_v_addr 0xF40 #define HIVE_SIZE_sp_output_v_addr 4 #define HIVE_ADDR_sp_start_isp_entry 0x0 #define HIVE_MEM_sp_no_dma_proxy scalar_processor_dmem -#define HIVE_ADDR_sp_no_dma_proxy 0x440 +#define HIVE_ADDR_sp_no_dma_proxy 0x408 #define HIVE_SIZE_sp_no_dma_proxy 4 #define HIVE_MEM_sp_raw_copy_padded_width scalar_processor_dmem -#define HIVE_ADDR_sp_raw_copy_padded_width 0x39A0 +#define HIVE_ADDR_sp_raw_copy_padded_width 0x2864 #define HIVE_SIZE_sp_raw_copy_padded_width 4 #define HIVE_MEM_sp_current_isp_program scalar_processor_dmem -#define HIVE_ADDR_sp_current_isp_program 0xF34 +#define HIVE_ADDR_sp_current_isp_program 0xEF4 #define HIVE_SIZE_sp_current_isp_program 4 #define HIVE_MEM_sp_dma_crop_block_width_a scalar_processor_dmem -#define HIVE_ADDR_sp_dma_crop_block_width_a 0x3A10 +#define HIVE_ADDR_sp_dma_crop_block_width_a 0x28D4 #define HIVE_SIZE_sp_dma_crop_block_width_a 4 #define HIVE_MEM_sp_dma_c_block_width_b scalar_processor_dmem -#define HIVE_ADDR_sp_dma_c_block_width_b 0x3A14 +#define HIVE_ADDR_sp_dma_c_block_width_b 0x28D8 #define HIVE_SIZE_sp_dma_c_block_width_b 4 #define HIVE_MEM_isp_vectors_per_line scalar_processor_dmem -#define HIVE_ADDR_isp_vectors_per_line 0x1184 +#define HIVE_ADDR_isp_vectors_per_line 0xF44 #define HIVE_SIZE_isp_vectors_per_line 4 #define HIVE_MEM_sp_ddr_data_addr scalar_processor_dmem -#define HIVE_ADDR_sp_ddr_data_addr 0x1188 +#define HIVE_ADDR_sp_ddr_data_addr 0xF48 #define HIVE_SIZE_sp_ddr_data_addr 4 #define HIVE_ADDR_sp_gen_histogram_entry 0x353 #define HIVE_MEM_sp_group scalar_processor_dmem -#define HIVE_ADDR_sp_group 0x118C -#define HIVE_SIZE_sp_group 1160 +#define HIVE_ADDR_sp_group 0xF4C +#define HIVE_SIZE_sp_group 1164 #define HIVE_MEM_isp_uv_internal_width_vecs scalar_processor_dmem -#define HIVE_ADDR_isp_uv_internal_width_vecs 0x1614 +#define HIVE_ADDR_isp_uv_internal_width_vecs 0x13D8 #define HIVE_SIZE_isp_uv_internal_width_vecs 4 #define HIVE_MEM_sp_input_y_addr scalar_processor_dmem -#define HIVE_ADDR_sp_input_y_addr 0x1618 +#define HIVE_ADDR_sp_input_y_addr 0x13DC #define HIVE_SIZE_sp_input_y_addr 4 #define HIVE_MEM_sp_dmem_data_addr scalar_processor_dmem -#define HIVE_ADDR_sp_dmem_data_addr 0x161C +#define HIVE_ADDR_sp_dmem_data_addr 0x13E0 #define HIVE_SIZE_sp_dmem_data_addr 4 #define HIVE_MEM_sp_sw_interrupt_value scalar_processor_dmem -#define HIVE_ADDR_sp_sw_interrupt_value 0x1620 +#define HIVE_ADDR_sp_sw_interrupt_value 0x13E4 #define HIVE_SIZE_sp_sw_interrupt_value 4 #define HIVE_MEM_histogram_args scalar_processor_dmem -#define HIVE_ADDR_histogram_args 0x3920 +#define HIVE_ADDR_histogram_args 0x27E4 #define HIVE_SIZE_histogram_args 4 #define HIVE_MEM_sp_bss_size scalar_processor_dmem -#define HIVE_ADDR_sp_bss_size 0x1624 +#define HIVE_ADDR_sp_bss_size 0x13E8 #define HIVE_SIZE_sp_bss_size 4 -#define HIVE_ADDR_capture_pp_dynamic_entry 0x37F7 +#define HIVE_ADDR_capture_pp_dynamic_entry 0x350E #define HIVE_MEM_sp_tpg_y_delta scalar_processor_dmem -#define HIVE_ADDR_sp_tpg_y_delta 0x1628 +#define HIVE_ADDR_sp_tpg_y_delta 0x13EC #define HIVE_SIZE_sp_tpg_y_delta 4 #define HIVE_MEM_sp_overlay_width scalar_processor_dmem -#define HIVE_ADDR_sp_overlay_width 0x162C +#define HIVE_ADDR_sp_overlay_width 0x13F0 #define HIVE_SIZE_sp_overlay_width 4 #define HIVE_MEM_isp_sdis_horiproj_num scalar_processor_dmem -#define HIVE_ADDR_isp_sdis_horiproj_num 0x1630 +#define HIVE_ADDR_isp_sdis_horiproj_num 0x13F4 #define HIVE_SIZE_isp_sdis_horiproj_num 4 #define HIVE_MEM_sp_dma_output_block_width_a scalar_processor_dmem -#define HIVE_ADDR_sp_dma_output_block_width_a 0x3A18 +#define HIVE_ADDR_sp_dma_output_block_width_a 0x28DC #define HIVE_SIZE_sp_dma_output_block_width_a 4 #define HIVE_MEM_sp_input_mode scalar_processor_dmem -#define HIVE_ADDR_sp_input_mode 0x1634 +#define HIVE_ADDR_sp_input_mode 0x13F8 #define HIVE_SIZE_sp_input_mode 4 #define HIVE_MEM_sp_tpg_xy_mask scalar_processor_dmem -#define HIVE_ADDR_sp_tpg_xy_mask 0x1638 +#define HIVE_ADDR_sp_tpg_xy_mask 0x13FC #define HIVE_SIZE_sp_tpg_xy_mask 4 #define HIVE_MEM_sp_overlay_start_y scalar_processor_dmem -#define HIVE_ADDR_sp_overlay_start_y 0x163C +#define HIVE_ADDR_sp_overlay_start_y 0x1400 #define HIVE_SIZE_sp_overlay_start_y 4 #define HIVE_MEM_sp_sp_group_addr scalar_processor_dmem -#define HIVE_ADDR_sp_sp_group_addr 0x1640 +#define HIVE_ADDR_sp_sp_group_addr 0x1404 #define HIVE_SIZE_sp_sp_group_addr 4 #define HIVE_MEM_sp_data_size scalar_processor_dmem -#define HIVE_ADDR_sp_data_size 0x1644 +#define HIVE_ADDR_sp_data_size 0x1408 #define HIVE_SIZE_sp_data_size 4 #define HIVE_MEM_num_sp_threads scalar_processor_dmem -#define HIVE_ADDR_num_sp_threads 0x39AC +#define HIVE_ADDR_num_sp_threads 0x2870 #define HIVE_SIZE_num_sp_threads 4 #define HIVE_MEM_sp_output_y_addr scalar_processor_dmem -#define HIVE_ADDR_sp_output_y_addr 0x1648 +#define HIVE_ADDR_sp_output_y_addr 0x140C #define HIVE_SIZE_sp_output_y_addr 4 #define HIVE_MEM_bayer_conf scalar_processor_dmem -#define HIVE_ADDR_bayer_conf 0x18C +#define HIVE_ADDR_bayer_conf 0x184 #define HIVE_SIZE_bayer_conf 56 #define HIVE_MEM_sp_proxy_busy_wait scalar_processor_dmem -#define HIVE_ADDR_sp_proxy_busy_wait 0x528 +#define HIVE_ADDR_sp_proxy_busy_wait 0x4F0 #define HIVE_SIZE_sp_proxy_busy_wait 4 #define HIVE_MEM_sp_sync_gen_hblank_cycles scalar_processor_dmem -#define HIVE_ADDR_sp_sync_gen_hblank_cycles 0x164C +#define HIVE_ADDR_sp_sync_gen_hblank_cycles 0x1410 #define HIVE_SIZE_sp_sync_gen_hblank_cycles 4 #define HIVE_MEM_isp_sdis_vertproj_num scalar_processor_dmem -#define HIVE_ADDR_isp_sdis_vertproj_num 0x1650 +#define HIVE_ADDR_isp_sdis_vertproj_num 0x1414 #define HIVE_SIZE_isp_sdis_vertproj_num 4 #define HIVE_MEM_sp_sync_gen_height scalar_processor_dmem -#define HIVE_ADDR_sp_sync_gen_height 0x1654 +#define HIVE_ADDR_sp_sync_gen_height 0x1418 #define HIVE_SIZE_sp_sync_gen_height 4 #define HIVE_MEM_sp_program_input_circuit scalar_processor_dmem -#define HIVE_ADDR_sp_program_input_circuit 0x1658 +#define HIVE_ADDR_sp_program_input_circuit 0x141C #define HIVE_SIZE_sp_program_input_circuit 4 #define HIVE_MEM_sp_if_b_changed scalar_processor_dmem -#define HIVE_ADDR_sp_if_b_changed 0x3958 +#define HIVE_ADDR_sp_if_b_changed 0x281C #define HIVE_SIZE_sp_if_b_changed 4 #define HIVE_MEM_sp_dma_c_block_width_a scalar_processor_dmem -#define HIVE_ADDR_sp_dma_c_block_width_a 0x3A1C +#define HIVE_ADDR_sp_dma_c_block_width_a 0x28E0 #define HIVE_SIZE_sp_dma_c_block_width_a 4 #define HIVE_MEM_sp_dma_crop_cropping_a scalar_processor_dmem -#define HIVE_ADDR_sp_dma_crop_cropping_a 0x3A20 +#define HIVE_ADDR_sp_dma_crop_cropping_a 0x28E4 #define HIVE_SIZE_sp_dma_crop_cropping_a 4 #define HIVE_MEM_sp_dma_output_skip_vecs scalar_processor_dmem -#define HIVE_ADDR_sp_dma_output_skip_vecs 0x3A24 +#define HIVE_ADDR_sp_dma_output_skip_vecs 0x28E8 #define HIVE_SIZE_sp_dma_output_skip_vecs 4 #define HIVE_MEM_sp_vf_downscale_bits scalar_processor_dmem -#define HIVE_ADDR_sp_vf_downscale_bits 0x165C +#define HIVE_ADDR_sp_vf_downscale_bits 0x1420 #define HIVE_SIZE_sp_vf_downscale_bits 4 #define HIVE_MEM_isp_sdis_vertcoef_vectors scalar_processor_dmem -#define HIVE_ADDR_isp_sdis_vertcoef_vectors 0x1660 +#define HIVE_ADDR_isp_sdis_vertcoef_vectors 0x1424 #define HIVE_SIZE_isp_sdis_vertcoef_vectors 4 #define HIVE_MEM_sp_overlay_bg_v scalar_processor_dmem -#define HIVE_ADDR_sp_overlay_bg_v 0x1664 +#define HIVE_ADDR_sp_overlay_bg_v 0x1428 #define HIVE_SIZE_sp_overlay_bg_v 4 #define HIVE_MEM_sp_output_u_addr scalar_processor_dmem -#define HIVE_ADDR_sp_output_u_addr 0x1668 +#define HIVE_ADDR_sp_output_u_addr 0x142C #define HIVE_SIZE_sp_output_u_addr 4 #define HIVE_MEM_output_dma_info_descr scalar_processor_dmem -#define HIVE_ADDR_output_dma_info_descr 0x3AD8 +#define HIVE_ADDR_output_dma_info_descr 0x299C #define HIVE_SIZE_output_dma_info_descr 72 #define HIVE_MEM_sp_isp_input_stream_format scalar_processor_dmem -#define HIVE_ADDR_sp_isp_input_stream_format 0x166C +#define HIVE_ADDR_sp_isp_input_stream_format 0x1430 #define HIVE_SIZE_sp_isp_input_stream_format 4 #define HIVE_MEM_curr_binary_id scalar_processor_dmem #define HIVE_ADDR_curr_binary_id 0x0 #define HIVE_SIZE_curr_binary_id 4 #define HIVE_MEM_sp_dma_c_skip_vecs scalar_processor_dmem -#define HIVE_ADDR_sp_dma_c_skip_vecs 0x3A28 +#define HIVE_ADDR_sp_dma_c_skip_vecs 0x28EC #define HIVE_SIZE_sp_dma_c_skip_vecs 4 #define HIVE_MEM_sp_dma_vfout_cropping_a scalar_processor_dmem -#define HIVE_ADDR_sp_dma_vfout_cropping_a 0x3A2C +#define HIVE_ADDR_sp_dma_vfout_cropping_a 0x28F0 #define HIVE_SIZE_sp_dma_vfout_cropping_a 4 #define HIVE_MEM_sp_overlay_bg_y scalar_processor_dmem -#define HIVE_ADDR_sp_overlay_bg_y 0x1670 +#define HIVE_ADDR_sp_overlay_bg_y 0x1434 #define HIVE_SIZE_sp_overlay_bg_y 4 #define HIVE_MEM_sp_histo_addr scalar_processor_dmem -#define HIVE_ADDR_sp_histo_addr 0x3924 +#define HIVE_ADDR_sp_histo_addr 0x27E8 #define HIVE_SIZE_sp_histo_addr 4 #define HIVE_MEM_sp_overlay_u_addr scalar_processor_dmem -#define HIVE_ADDR_sp_overlay_u_addr 0x1674 +#define HIVE_ADDR_sp_overlay_u_addr 0x1438 #define HIVE_SIZE_sp_overlay_u_addr 4 #define HIVE_MEM_sp_input_u_addr scalar_processor_dmem -#define HIVE_ADDR_sp_input_u_addr 0x1678 +#define HIVE_ADDR_sp_input_u_addr 0x143C #define HIVE_SIZE_sp_input_u_addr 4 #define HIVE_MEM_sp_tpg_y_mask scalar_processor_dmem -#define HIVE_ADDR_sp_tpg_y_mask 0x167C +#define HIVE_ADDR_sp_tpg_y_mask 0x1440 #define HIVE_SIZE_sp_tpg_y_mask 4 #define HIVE_MEM_sp_si scalar_processor_dmem -#define HIVE_ADDR_sp_si 0x3A30 +#define HIVE_ADDR_sp_si 0x28F4 #define HIVE_SIZE_sp_si 68 #define HIVE_MEM_sp_debug scalar_processor_dmem -#define HIVE_ADDR_sp_debug 0x39C8 +#define HIVE_ADDR_sp_debug 0x288C #define HIVE_SIZE_sp_debug 64 #define HIVE_MEM_sp_raw_copy_raw_bit_depth scalar_processor_dmem -#define HIVE_ADDR_sp_raw_copy_raw_bit_depth 0x39A4 +#define HIVE_ADDR_sp_raw_copy_raw_bit_depth 0x2868 #define HIVE_SIZE_sp_raw_copy_raw_bit_depth 4 #define HIVE_MEM_sp_overlay_y_addr scalar_processor_dmem -#define HIVE_ADDR_sp_overlay_y_addr 0x1680 +#define HIVE_ADDR_sp_overlay_y_addr 0x1444 #define HIVE_SIZE_sp_overlay_y_addr 4 #define HIVE_MEM_isp_sdis_horicoef_vectors scalar_processor_dmem -#define HIVE_ADDR_isp_sdis_horicoef_vectors 0x1684 +#define HIVE_ADDR_isp_sdis_horicoef_vectors 0x1448 #define HIVE_SIZE_isp_sdis_horicoef_vectors 4 #define HIVE_MEM_sp_if_b scalar_processor_dmem -#define HIVE_ADDR_sp_if_b 0x395C +#define HIVE_ADDR_sp_if_b 0x2820 #define HIVE_SIZE_sp_if_b 48 #define HIVE_MEM_sp_dmem_bss_addr scalar_processor_dmem -#define HIVE_ADDR_sp_dmem_bss_addr 0x1688 +#define HIVE_ADDR_sp_dmem_bss_addr 0x144C #define HIVE_SIZE_sp_dmem_bss_addr 4 #define HIVE_MEM_sp_data scalar_processor_dmem -#define HIVE_ADDR_sp_data 0x168C -#define HIVE_SIZE_sp_data 8704 +#define HIVE_ADDR_sp_data 0x1450 +#define HIVE_SIZE_sp_data 4864 #define HIVE_MEM_sp_overlay_height scalar_processor_dmem -#define HIVE_ADDR_sp_overlay_height 0x388C +#define HIVE_ADDR_sp_overlay_height 0x2750 #define HIVE_SIZE_sp_overlay_height 4 #define HIVE_MEM_dma_proxy_kill_req scalar_processor_dmem -#define HIVE_ADDR_dma_proxy_kill_req 0x524 +#define HIVE_ADDR_dma_proxy_kill_req 0x4EC #define HIVE_SIZE_dma_proxy_kill_req 1 #define HIVE_MEM_mem_map scalar_processor_dmem -#define HIVE_ADDR_mem_map 0x3A74 +#define HIVE_ADDR_mem_map 0x2938 #define HIVE_SIZE_mem_map 100 #define HIVE_MEM_sp_proxy_running scalar_processor_dmem -#define HIVE_ADDR_sp_proxy_running 0x52C +#define HIVE_ADDR_sp_proxy_running 0x4F4 #define HIVE_SIZE_sp_proxy_running 4 #define HIVE_MEM_sp_if_a_changed scalar_processor_dmem -#define HIVE_ADDR_sp_if_a_changed 0x398C +#define HIVE_ADDR_sp_if_a_changed 0x2850 #define HIVE_SIZE_sp_if_a_changed 4 #define HIVE_MEM_vtmp1 scalar_processor_dmem -#define HIVE_ADDR_vtmp1 0x3890 +#define HIVE_ADDR_vtmp1 0x2754 #define HIVE_SIZE_vtmp1 128 #define HIVE_MEM_isp_vf_output_width_vecs scalar_processor_dmem -#define HIVE_ADDR_isp_vf_output_width_vecs 0x3910 +#define HIVE_ADDR_isp_vf_output_width_vecs 0x27D4 #define HIVE_SIZE_isp_vf_output_width_vecs 4 #define HIVE_ADDR_sp_bin_copy_entry 0x2D8 diff --git a/drivers/media/video/atomisp/css/sh_css.c b/drivers/media/video/atomisp/css/sh_css.c index b0b68ff..367944b 100644 --- a/drivers/media/video/atomisp/css/sh_css.c +++ b/drivers/media/video/atomisp/css/sh_css.c @@ -145,12 +145,10 @@ struct sh_css_capture_settings { bool bayer_ds; struct sh_css_binary copy_binary; struct sh_css_binary primary_binary; - struct sh_css_binary pre_gdc_binary; + struct sh_css_binary pre_isp_binary; struct sh_css_binary gdc_binary; - struct sh_css_binary post_gdc_binary; - struct sh_css_binary pre_anr_binary; + struct sh_css_binary post_isp_binary; struct sh_css_binary anr_binary; - struct sh_css_binary post_anr_binary; struct sh_css_binary capture_pp_binary; struct sh_css_binary vf_pp_binary; /* resolution before yuv downscaling */ @@ -164,6 +162,7 @@ struct sh_css_capture_settings { bool need_pp; struct sh_css_shading_table *shading_table; bool zoom_changed; + bool anr; }; #define DEFAULT_CAPTURE_SETTINGS \ @@ -1095,7 +1094,8 @@ start_binary(struct sh_css_binary *binary, my_css.two_ppc, false); } my_css.state = sh_css_state_executing_isp; - err = sh_css_sp_start_isp(binary, args, preview_mode); + err = sh_css_sp_start_isp(binary, args, preview_mode, + my_css.capture_settings.mode == SH_CSS_CAPTURE_MODE_LOW_LIGHT); if (err != sh_css_success) return err; @@ -1401,7 +1401,8 @@ sh_css_terminate_firmware(void) sh_css_acceleration_done(firmware); /* reload SP firmmware */ my_css.sp_bin_addr = sh_css_sp_load_program(&sh_css_sp_fw, - SP_PROG_NAME); + SP_PROG_NAME, + my_css.sp_bin_addr); /* restore SP state */ if (my_css.two_ppc) { sh_css_sp_set_if_configs(&my_css.curr_if_a_config, @@ -1593,9 +1594,10 @@ invalidate_capture_binaries(void) my_css.capture_settings.pipeline.reload = true; my_css.capture_settings.copy_binary.info = NULL; my_css.capture_settings.primary_binary.info = NULL; - my_css.capture_settings.pre_gdc_binary.info = NULL; + my_css.capture_settings.pre_isp_binary.info = NULL; my_css.capture_settings.gdc_binary.info = NULL; - my_css.capture_settings.post_gdc_binary.info = NULL; + my_css.capture_settings.post_isp_binary.info = NULL; + my_css.capture_settings.anr_binary.info = NULL; my_css.capture_settings.capture_pp_binary.info = NULL; my_css.capture_settings.vf_pp_binary.info = NULL; my_css.capture_settings.need_pp = false; @@ -1653,7 +1655,8 @@ sh_css_init(void *(*malloc_func) (size_t size), return err; sh_css_init_binary_infos(); my_css.sp_bin_addr = sh_css_sp_load_program(&sh_css_sp_fw, - SP_PROG_NAME); + SP_PROG_NAME, + my_css.sp_bin_addr); if (!my_css.sp_bin_addr) return sh_css_err_cannot_allocate_memory; sh_css_pipeline_init(&my_css.preview_settings.pipeline); @@ -2594,7 +2597,7 @@ static const struct sh_css_acc_fw * last_output_firmware(const struct sh_css_acc_fw *fw) { const struct sh_css_acc_fw *last_fw = NULL; - for (; fw; fw = fw->next) { + for (; fw; fw = fw->header.next) { if (fw->header.sp.output) last_fw = fw; } @@ -2615,7 +2618,7 @@ add_firmwares(struct sh_css_pipeline *me, { enum sh_css_err err = sh_css_success; struct sh_css_pipeline_stage *extra_stage = NULL; - for (; fw; fw = fw->next) { + for (; fw; fw = fw->header.next) { struct sh_css_frame *out = NULL; if (fw == last_fw) out = out_frame; @@ -3425,7 +3428,7 @@ init_pre_gdc_descr(struct sh_css_frame_info *in_info, in_info->raw_bit_depth = sh_css_input_format_bits_per_pixel(my_css.input_format, my_css.two_ppc); - init_offline_descr(&pre_gdc_descr, SH_CSS_BINARY_MODE_PRE_GDC, + init_offline_descr(&pre_gdc_descr, SH_CSS_BINARY_MODE_PRE_ISP, in_info, out_info, NULL); } @@ -3446,7 +3449,7 @@ init_post_gdc_descr(struct sh_css_frame_info *in_info, { *in_info = *out_info; in_info->format = SH_CSS_FRAME_FORMAT_YUV420_16; - init_offline_descr(&post_gdc_descr, SH_CSS_BINARY_MODE_POST_GDC, + init_offline_descr(&post_gdc_descr, SH_CSS_BINARY_MODE_POST_ISP, in_info, out_info, vf_info); } @@ -3459,7 +3462,7 @@ init_pre_anr_descr(struct sh_css_frame_info *in_info, in_info->raw_bit_depth = sh_css_input_format_bits_per_pixel(my_css.input_format, my_css.two_ppc); - init_offline_descr(&pre_anr_descr, SH_CSS_BINARY_MODE_PRE_ANR, + init_offline_descr(&pre_anr_descr, SH_CSS_BINARY_MODE_PRE_ISP, in_info, out_info, NULL); } @@ -3486,7 +3489,7 @@ init_post_anr_descr(struct sh_css_frame_info *in_info, in_info->raw_bit_depth = sh_css_input_format_bits_per_pixel(my_css.input_format, my_css.two_ppc); - init_offline_descr(&post_anr_descr, SH_CSS_BINARY_MODE_POST_ANR, + init_offline_descr(&post_anr_descr, SH_CSS_BINARY_MODE_POST_ISP, in_info, out_info, vf_info); } @@ -3576,7 +3579,7 @@ load_advanced_binaries(void) bool need_pp; enum sh_css_err err = sh_css_success; - if (my_css.capture_settings.pre_gdc_binary.info) + if (my_css.capture_settings.pre_isp_binary.info) return sh_css_success; err = check_vf_out_info(&my_css.capture_settings.output_info, @@ -3605,28 +3608,28 @@ load_advanced_binaries(void) /* Post-gdc */ init_post_gdc_descr(&post_in_info, &post_out_info, &vf_info); err = sh_css_binary_find(&post_gdc_descr, - &my_css.capture_settings.post_gdc_binary); + &my_css.capture_settings.post_isp_binary); if (err != sh_css_success) return err; /* Gdc */ init_gdc_descr(&gdc_in_info, - &my_css.capture_settings.post_gdc_binary.in_frame_info); + &my_css.capture_settings.post_isp_binary.in_frame_info); err = sh_css_binary_find(&gdc_descr, &my_css.capture_settings.gdc_binary); if (err != sh_css_success) return err; my_css.capture_settings.gdc_binary.left_padding = - my_css.capture_settings.post_gdc_binary.left_padding; + my_css.capture_settings.post_isp_binary.left_padding; /* Pre-gdc */ init_pre_gdc_descr(&pre_in_info, &my_css.capture_settings.gdc_binary.in_frame_info); err = sh_css_binary_find(&pre_gdc_descr, - &my_css.capture_settings.pre_gdc_binary); + &my_css.capture_settings.pre_isp_binary); if (err != sh_css_success) return err; - my_css.capture_settings.pre_gdc_binary.left_padding = + my_css.capture_settings.pre_isp_binary.left_padding = my_css.capture_settings.gdc_binary.left_padding; /* Viewfinder post-processing */ @@ -3635,7 +3638,7 @@ load_advanced_binaries(void) &my_css.capture_settings.capture_pp_binary.vf_frame_info; } else { vf_pp_in_info = - &my_css.capture_settings.post_gdc_binary.vf_frame_info; + &my_css.capture_settings.post_isp_binary.vf_frame_info; } init_vf_pp_descr(vf_pp_in_info, &my_css.capture_settings.vf_info); @@ -3646,7 +3649,7 @@ load_advanced_binaries(void) /* Copy */ err = load_copy_binary(&my_css.capture_settings.copy_binary, - &my_css.capture_settings.pre_gdc_binary); + &my_css.capture_settings.pre_isp_binary); if (err != sh_css_success) return err; @@ -3666,7 +3669,7 @@ load_low_light_binaries(void) bool need_pp; enum sh_css_err err = sh_css_success; - if (my_css.capture_settings.pre_anr_binary.info) + if (my_css.capture_settings.pre_isp_binary.info) return sh_css_success; err = check_vf_out_info(&my_css.capture_settings.output_info, @@ -3695,28 +3698,28 @@ load_low_light_binaries(void) /* Post-anr */ init_post_anr_descr(&post_in_info, &post_out_info, &vf_info); err = sh_css_binary_find(&post_anr_descr, - &my_css.capture_settings.post_anr_binary); + &my_css.capture_settings.post_isp_binary); if (err != sh_css_success) return err; /* Anr */ init_anr_descr(&anr_in_info, - &my_css.capture_settings.post_anr_binary.in_frame_info); + &my_css.capture_settings.post_isp_binary.in_frame_info); err = sh_css_binary_find(&anr_descr, &my_css.capture_settings.anr_binary); if (err != sh_css_success) return err; my_css.capture_settings.anr_binary.left_padding = - my_css.capture_settings.post_anr_binary.left_padding; + my_css.capture_settings.post_isp_binary.left_padding; /* Pre-anr */ init_pre_anr_descr(&pre_in_info, &my_css.capture_settings.anr_binary.in_frame_info); err = sh_css_binary_find(&pre_anr_descr, - &my_css.capture_settings.pre_anr_binary); + &my_css.capture_settings.pre_isp_binary); if (err != sh_css_success) return err; - my_css.capture_settings.pre_anr_binary.left_padding = + my_css.capture_settings.pre_isp_binary.left_padding = my_css.capture_settings.anr_binary.left_padding; /* Viewfinder post-processing */ @@ -3725,7 +3728,7 @@ load_low_light_binaries(void) &my_css.capture_settings.capture_pp_binary.vf_frame_info; } else { vf_pp_in_info = - &my_css.capture_settings.post_anr_binary.vf_frame_info; + &my_css.capture_settings.post_isp_binary.vf_frame_info; } init_vf_pp_descr(vf_pp_in_info, &my_css.capture_settings.vf_info); @@ -3736,7 +3739,7 @@ load_low_light_binaries(void) /* Copy */ err = load_copy_binary(&my_css.capture_settings.copy_binary, - &my_css.capture_settings.pre_anr_binary); + &my_css.capture_settings.pre_isp_binary); if (err != sh_css_success) return err; @@ -3803,12 +3806,10 @@ sh_css_capture_start(struct sh_css_frame *raw_out_frame, struct sh_css_binary *copy_binary, *primary_binary, *vf_pp_binary, - *pre_gdc_binary, + *pre_isp_binary, *gdc_binary, - *post_gdc_binary, - *pre_anr_binary, + *post_isp_binary, *anr_binary, - *post_anr_binary, *capture_pp_binary, *sc_binary = NULL; bool need_pp = false; @@ -3847,12 +3848,10 @@ sh_css_capture_start(struct sh_css_frame *raw_out_frame, copy_binary = &my_css.capture_settings.copy_binary; primary_binary = &my_css.capture_settings.primary_binary; vf_pp_binary = &my_css.capture_settings.vf_pp_binary; - pre_gdc_binary = &my_css.capture_settings.pre_gdc_binary; + pre_isp_binary = &my_css.capture_settings.pre_isp_binary; gdc_binary = &my_css.capture_settings.gdc_binary; - post_gdc_binary = &my_css.capture_settings.post_gdc_binary; - pre_anr_binary = &my_css.capture_settings.pre_anr_binary; + post_isp_binary = &my_css.capture_settings.post_isp_binary; anr_binary = &my_css.capture_settings.anr_binary; - post_anr_binary = &my_css.capture_settings.post_anr_binary; capture_pp_binary = &my_css.capture_settings.capture_pp_binary; need_pp = my_css.capture_settings.need_pp || my_css.output_stage; @@ -3887,8 +3886,8 @@ sh_css_capture_start(struct sh_css_frame *raw_out_frame, sc_binary = primary_binary; } else if (my_css.capture_settings.mode == SH_CSS_CAPTURE_MODE_ADVANCED) { - err = sh_css_pipeline_add_stage(me, pre_gdc_binary, - NULL, pre_gdc_binary->info->mode, + err = sh_css_pipeline_add_stage(me, pre_isp_binary, + NULL, pre_isp_binary->info->mode, NULL, NULL, NULL, NULL, NULL); if (err != sh_css_success) return err; @@ -3897,18 +3896,18 @@ sh_css_capture_start(struct sh_css_frame *raw_out_frame, NULL, NULL, NULL, NULL, NULL); if (err != sh_css_success) return err; - err = sh_css_pipeline_add_stage(me, post_gdc_binary, - NULL, post_gdc_binary->info->mode, + err = sh_css_pipeline_add_stage(me, post_isp_binary, + NULL, post_isp_binary->info->mode, NULL, NULL, need_pp ? NULL : out_frame, NULL, &post_stage); if (err != sh_css_success) return err; - sc_binary = pre_gdc_binary; + sc_binary = pre_isp_binary; } else if (my_css.capture_settings.mode == SH_CSS_CAPTURE_MODE_LOW_LIGHT) { - err = sh_css_pipeline_add_stage(me, pre_anr_binary, - NULL, pre_anr_binary->info->mode, + err = sh_css_pipeline_add_stage(me, pre_isp_binary, + NULL, pre_isp_binary->info->mode, NULL, NULL, NULL, NULL, NULL); if (err != sh_css_success) return err; @@ -3917,14 +3916,14 @@ sh_css_capture_start(struct sh_css_frame *raw_out_frame, NULL, NULL, NULL, NULL, NULL); if (err != sh_css_success) return err; - err = sh_css_pipeline_add_stage(me, post_anr_binary, - NULL, post_anr_binary->info->mode, + err = sh_css_pipeline_add_stage(me, post_isp_binary, + NULL, post_isp_binary->info->mode, NULL, NULL, need_pp ? NULL : out_frame, NULL, &post_stage); if (err != sh_css_success) return err; - sc_binary = pre_anr_binary; + sc_binary = pre_isp_binary; } if (need_pp) { @@ -3997,13 +3996,13 @@ sh_css_capture_start(struct sh_css_frame *raw_out_frame, } else if (my_css.capture_settings.mode == SH_CSS_CAPTURE_MODE_LOW_LIGHT) { err = sh_css_pipeline_get_stage(me, - post_anr_binary->info->mode, + post_isp_binary->info->mode, &out_stage); if (err != sh_css_success) return err; } else { err = sh_css_pipeline_get_stage(me, - post_gdc_binary->info->mode, + post_isp_binary->info->mode, &out_stage); if (err != sh_css_success) return err; @@ -4093,7 +4092,7 @@ sh_css_capture_get_grid_info(struct sh_css_grid_info *info) &my_css.capture_settings.primary_binary, info); } else { err = sh_css_binary_grid_info( - &my_css.capture_settings.pre_gdc_binary, info); + &my_css.capture_settings.pre_isp_binary, info); } return err; } @@ -4625,20 +4624,20 @@ static void append_firmware(struct sh_css_acc_fw **l, struct sh_css_acc_fw *firmware) { while (*l) - l = &(*l)->next; + l = &(*l)->header.next; *l = firmware; - firmware->next = NULL; + firmware->header.next = NULL; } static void remove_firmware(struct sh_css_acc_fw **l, struct sh_css_acc_fw *firmware) { while (*l && *l != firmware) - l = &(*l)->next; + l = &(*l)->header.next; if (!*l) return; - *l = firmware->next; - firmware->next = NULL; + *l = firmware->header.next; + firmware->header.next = NULL; } /* Load firmware for acceleration */ diff --git a/drivers/media/video/atomisp/css/sh_css_accelerate.c b/drivers/media/video/atomisp/css/sh_css_accelerate.c index ab6fc85..befd0d6 100644 --- a/drivers/media/video/atomisp/css/sh_css_accelerate.c +++ b/drivers/media/video/atomisp/css/sh_css_accelerate.c @@ -28,15 +28,23 @@ #include "sh_css_accelerate.h" #if !defined(C_RUN) && !defined(HRT_UNSCHED) -static void -sh_css_acc_upload_isp_code(const struct sh_css_acc_fw *firmware) +static const unsigned char * +sh_css_acc_upload_isp_code(struct sh_css_acc_fw *firmware) { const unsigned char *blob = SH_CSS_ACC_ISP_CODE(firmware); unsigned size = SH_CSS_ACC_ISP_SIZE(firmware); - const unsigned char *binary = sh_css_load_blob(blob, size); + const unsigned char *binary = firmware->header.isp_code; + + if (!binary) { + binary = sh_css_load_blob(blob, size); + firmware->header.isp_code = binary; + } + if (!binary) + return NULL; sh_css_sp_dmem_store((unsigned int)firmware->header.sp.isp_code, &binary, sizeof(binary)); + return binary; } #endif @@ -77,8 +85,14 @@ sh_css_acc_unload(const struct sh_css_acc_fw *firmware) struct sh_css_acc_fw_hdr *header = (struct sh_css_acc_fw_hdr *)&firmware->header; sh_css_free(header->sp_args); - header->sp_args = NULL; - header->loaded = false; + if (header->sp_code) + hrt_isp_css_mm_free((void *)header->sp_code); + if (header->isp_code) + hrt_isp_css_mm_free((void *)header->isp_code); + header->sp_args = NULL; + header->sp_code = NULL; + header->isp_code = NULL; + header->loaded = false; } /* Set argument of size to value */ @@ -107,7 +121,7 @@ sh_css_argument_type(struct sh_css_acc_fw *firmware, unsigned num) /* Set host private data for argument */ enum sh_css_err sh_css_argument_set_host(struct sh_css_acc_fw *firmware, - unsigned num, void *host) + unsigned num, void *host) { if (!firmware->header.sp_args) return sh_css_err_invalid_arguments; @@ -179,6 +193,11 @@ sh_css_acc_start(struct sh_css_acc_fw *firmware, bool has_extension_args = (args != NULL); bool is_extension = (header->type != SH_CSS_ACC_STANDALONE); const struct sh_css_sp_fw *sp_fw = &header->sp.fw; + const unsigned char *sp_program; +#if !defined(C_RUN) && !defined(HRT_UNSCHED) + const unsigned char *isp_program; +#endif + *(const void **)&sp_fw->text = SH_CSS_ACC_SP_CODE(firmware); *(const void **)&sp_fw->data = SH_CSS_ACC_SP_DATA(firmware); @@ -187,10 +206,16 @@ sh_css_acc_start(struct sh_css_acc_fw *firmware, if (has_extension_args != is_extension) return sh_css_err_invalid_arguments; - if (!sh_css_sp_load_program(sp_fw, SH_CSS_ACC_PROG_NAME(firmware))) + sp_program = sh_css_sp_load_program(sp_fw, + SH_CSS_ACC_PROG_NAME(firmware), + (void *)firmware->header.sp_code); + if (!sp_program) return sh_css_err_cannot_allocate_memory; + firmware->header.sp_code = sp_program; #if !defined(C_RUN) && !defined(HRT_UNSCHED) - sh_css_acc_upload_isp_code(firmware); + isp_program = sh_css_acc_upload_isp_code(firmware); + if (!isp_program) + return sh_css_err_cannot_allocate_memory; #endif #ifdef C_RUN @@ -243,3 +268,4 @@ void sh_css_acc_abort(struct sh_css_acc_fw *firmware) unsigned int t = true; upload_int(firmware->header.sp.css_abort, &t); } + diff --git a/drivers/media/video/atomisp/css/sh_css_accelerate.h b/drivers/media/video/atomisp/css/sh_css_accelerate.h index ce139b1..2fbe208 100644 --- a/drivers/media/video/atomisp/css/sh_css_accelerate.h +++ b/drivers/media/video/atomisp/css/sh_css_accelerate.h @@ -48,7 +48,7 @@ sh_css_argument_type(struct sh_css_acc_fw *firmware, unsigned int num); /* Set host private data for argument */ enum sh_css_err sh_css_argument_set_host(struct sh_css_acc_fw *firmware, - unsigned num, void *host); + unsigned num, void *host); /* Get host private data for argument */ void * diff --git a/drivers/media/video/atomisp/css/sh_css_binary.c b/drivers/media/video/atomisp/css/sh_css_binary.c index e451509..7db1a5d 100644 --- a/drivers/media/video/atomisp/css/sh_css_binary.c +++ b/drivers/media/video/atomisp/css/sh_css_binary.c @@ -135,24 +135,18 @@ init_binary_info(struct sh_css_binary_info *info, bool *binary_found) case SH_CSS_BINARY_ID_CAPTURE_PP: _init_binary_info(info, ISP_CAPTURE_PP_); break; - case SH_CSS_BINARY_ID_PRE_GDC: - _init_binary_info(info, ISP_PRE_GDC_); + case SH_CSS_BINARY_ID_PRE_ISP: + _init_binary_info(info, ISP_PRE_ISP_); break; case SH_CSS_BINARY_ID_GDC: _init_binary_info(info, ISP_GDC_); break; - case SH_CSS_BINARY_ID_POST_GDC: - _init_binary_info(info, ISP_POST_GDC_); - break; - case SH_CSS_BINARY_ID_PRE_ANR: - _init_binary_info(info, ISP_PRE_ANR_); + case SH_CSS_BINARY_ID_POST_ISP: + _init_binary_info(info, ISP_POST_ISP_); break; case SH_CSS_BINARY_ID_ANR: _init_binary_info(info, ISP_ANR_); break; - case SH_CSS_BINARY_ID_POST_ANR: - _init_binary_info(info, ISP_POST_ANR_); - break; case SH_CSS_BINARY_ID_PREVIEW_DZ: _init_binary_info(info, ISP_PREVIEW_DZ_); break; diff --git a/drivers/media/video/atomisp/css/sh_css_binary.h b/drivers/media/video/atomisp/css/sh_css_binary.h index c3e4b67..b6c5b25 100644 --- a/drivers/media/video/atomisp/css/sh_css_binary.h +++ b/drivers/media/video/atomisp/css/sh_css_binary.h @@ -33,17 +33,15 @@ #define SH_CSS_BINARY_MODE_PREVIEW 1 #define SH_CSS_BINARY_MODE_PRIMARY 2 #define SH_CSS_BINARY_MODE_VIDEO 3 -#define SH_CSS_BINARY_MODE_PRE_GDC 4 +#define SH_CSS_BINARY_MODE_PRE_ISP 4 #define SH_CSS_BINARY_MODE_GDC 5 -#define SH_CSS_BINARY_MODE_POST_GDC 6 -#define SH_CSS_BINARY_MODE_PRE_ANR 7 -#define SH_CSS_BINARY_MODE_ANR 8 -#define SH_CSS_BINARY_MODE_POST_ANR 9 -#define SH_CSS_BINARY_MODE_CAPTURE_PP 10 -#define SH_CSS_BINARY_MODE_BAYER_DS 11 -#define SH_CSS_BINARY_MODE_VF_PP 12 -#define SH_CSS_BINARY_NUM_MODES 13 -#define SH_CSS_BINARY_MODE_NONE 14 +#define SH_CSS_BINARY_MODE_POST_ISP 6 +#define SH_CSS_BINARY_MODE_ANR 7 +#define SH_CSS_BINARY_MODE_CAPTURE_PP 8 +#define SH_CSS_BINARY_MODE_BAYER_DS 9 +#define SH_CSS_BINARY_MODE_VF_PP 10 +#define SH_CSS_BINARY_NUM_MODES 11 +#define SH_CSS_BINARY_MODE_NONE 12 /* Indicate where binaries can read input from */ #define SH_CSS_BINARY_INPUT_SENSOR 0 @@ -61,12 +59,10 @@ enum sh_css_binary_id { SH_CSS_BINARY_ID_BAYER_DS, SH_CSS_BINARY_ID_VF_PP, SH_CSS_BINARY_ID_CAPTURE_PP, - SH_CSS_BINARY_ID_PRE_GDC, + SH_CSS_BINARY_ID_PRE_ISP, SH_CSS_BINARY_ID_GDC, - SH_CSS_BINARY_ID_POST_GDC, - SH_CSS_BINARY_ID_PRE_ANR, + SH_CSS_BINARY_ID_POST_ISP, SH_CSS_BINARY_ID_ANR, - SH_CSS_BINARY_ID_POST_ANR, SH_CSS_BINARY_ID_PREVIEW_DS, SH_CSS_BINARY_ID_PREVIEW_DZ, SH_CSS_BINARY_ID_PRIMARY_DS, diff --git a/drivers/media/video/atomisp/css/sh_css_binary_info.h b/drivers/media/video/atomisp/css/sh_css_binary_info.h index 46f486e..a1b24bf 100644 --- a/drivers/media/video/atomisp/css/sh_css_binary_info.h +++ b/drivers/media/video/atomisp/css/sh_css_binary_info.h @@ -164,64 +164,63 @@ #define ISP_GDC_C_SUBSAMPLING SH_CSS_DEFAULT_C_SUBSAMPLING #define ISP_GDC_FIXED_S3A_DECI_LOG 0 -/* Post GDC */ -#define ISP_POST_GDC_BINARY_ID SH_CSS_BINARY_ID_POST_GDC -#define ISP_POST_GDC_BINARY isp_postgdc_var -#define ISP_POST_GDC_MODE SH_CSS_BINARY_MODE_POST_GDC -#define ISP_POST_GDC_PIPELINING 2 -#define ISP_POST_GDC_ENABLE_VF_VECEVEN 1 -#define ISP_POST_GDC_ENABLE_DS 0 -#define ISP_POST_GDC_ENABLE_FPNR 0 -#define ISP_POST_GDC_ENABLE_SC 0 -#define ISP_POST_GDC_ENABLE_S3A 0 -#define ISP_POST_GDC_ENABLE_SDIS 0 -#define ISP_POST_GDC_ENABLE_UDS 0 -#define ISP_POST_GDC_OUTPUT_NUM_CHUNKS 1 -#define ISP_POST_GDC_DUMMY_BUF_VECTORS 0 -#define ISP_POST_GDC_LEFT_CROPPING SH_CSS_MAX_LEFT_CROPPING -#define ISP_POST_GDC_TOP_CROPPING 8 -#define ISP_POST_GDC_ENABLE_DVS_ENVELOPE 0 -#define ISP_POST_GDC_MAX_DVS_ENVELOPE_WIDTH 0 -#define ISP_POST_GDC_MAX_DVS_ENVELOPE_HEIGHT 0 -#define ISP_POST_GDC_MAX_VF_LOG_DOWNSCALE 2 -/* limited due to VMEM shortage */ -#define ISP_POST_GDC_MAX_OUTPUT_WIDTH 4352 /* was 4416 */ -#define ISP_POST_GDC_MAX_OUTPUT_HEIGHT 3312 -#define ISP_POST_GDC_MIN_OUTPUT_WIDTH SH_CSS_MIN_SENSOR_WIDTH -#define ISP_POST_GDC_MIN_OUTPUT_HEIGHT SH_CSS_MIN_SENSOR_HEIGHT -#define ISP_POST_GDC_OUTPUT_FORMATS SH_CSS_CAPTURE_OUTPUT_FORMATS -#define ISP_POST_GDC_INPUT SH_CSS_BINARY_INPUT_MEMORY -#define ISP_POST_GDC_C_SUBSAMPLING SH_CSS_DEFAULT_C_SUBSAMPLING -#define ISP_POST_GDC_FIXED_S3A_DECI_LOG 0 +/* Post ISP */ +#define ISP_POST_ISP_BINARY_ID SH_CSS_BINARY_ID_POST_ISP +#define ISP_POST_ISP_BINARY isp_postisp_var +#define ISP_POST_ISP_MODE SH_CSS_BINARY_MODE_POST_ISP +#define ISP_POST_ISP_PIPELINING 2 +#define ISP_POST_ISP_ENABLE_VF_VECEVEN 1 +#define ISP_POST_ISP_ENABLE_DS 0 +#define ISP_POST_ISP_ENABLE_FPNR 0 +#define ISP_POST_ISP_ENABLE_SC 0 +#define ISP_POST_ISP_ENABLE_S3A 0 +#define ISP_POST_ISP_ENABLE_SDIS 0 +#define ISP_POST_ISP_ENABLE_UDS 0 +#define ISP_POST_ISP_OUTPUT_NUM_CHUNKS 2 +#define ISP_POST_ISP_DUMMY_BUF_VECTORS 0 +#define ISP_POST_ISP_LEFT_CROPPING SH_CSS_MAX_LEFT_CROPPING +#define ISP_POST_ISP_TOP_CROPPING 8 +#define ISP_POST_ISP_ENABLE_DVS_ENVELOPE 0 +#define ISP_POST_ISP_MAX_DVS_ENVELOPE_WIDTH 0 +#define ISP_POST_ISP_MAX_DVS_ENVELOPE_HEIGHT 0 +#define ISP_POST_ISP_MAX_VF_LOG_DOWNSCALE 2 +#define ISP_POST_ISP_MAX_OUTPUT_WIDTH SH_CSS_MAX_SENSOR_WIDTH +#define ISP_POST_ISP_MAX_OUTPUT_HEIGHT SH_CSS_MAX_SENSOR_HEIGHT +#define ISP_POST_ISP_MIN_OUTPUT_WIDTH SH_CSS_MIN_SENSOR_WIDTH +#define ISP_POST_ISP_MIN_OUTPUT_HEIGHT SH_CSS_MIN_SENSOR_HEIGHT +#define ISP_POST_ISP_OUTPUT_FORMATS SH_CSS_CAPTURE_OUTPUT_FORMATS +#define ISP_POST_ISP_INPUT SH_CSS_BINARY_INPUT_MEMORY +#define ISP_POST_ISP_C_SUBSAMPLING SH_CSS_DEFAULT_C_SUBSAMPLING +#define ISP_POST_ISP_FIXED_S3A_DECI_LOG 0 -/* Pre GDC */ -#define ISP_PRE_GDC_BINARY_ID SH_CSS_BINARY_ID_PRE_GDC -#define ISP_PRE_GDC_BINARY isp_pregdc_var -#define ISP_PRE_GDC_MODE SH_CSS_BINARY_MODE_PRE_GDC -#define ISP_PRE_GDC_ENABLE_FPNR 1 -#define ISP_PRE_GDC_ENABLE_SC 1 -#define ISP_PRE_GDC_ENABLE_S3A 1 -#define ISP_PRE_GDC_ENABLE_SDIS 1 -#define ISP_PRE_GDC_ENABLE_DS 0 -#define ISP_PRE_GDC_ENABLE_VF_VECEVEN 0 -#define ISP_PRE_GDC_ENABLE_UDS 0 -#define ISP_PRE_GDC_PIPELINING 1 -#define ISP_PRE_GDC_OUTPUT_NUM_CHUNKS 1 -#define ISP_PRE_GDC_DUMMY_BUF_VECTORS 0 -#define ISP_PRE_GDC_LEFT_CROPPING 0 -#define ISP_PRE_GDC_TOP_CROPPING 0 -#define ISP_PRE_GDC_ENABLE_DVS_ENVELOPE 0 -#define ISP_PRE_GDC_MAX_DVS_ENVELOPE_WIDTH 0 -#define ISP_PRE_GDC_MAX_DVS_ENVELOPE_HEIGHT 0 -#define ISP_PRE_GDC_MAX_OUTPUT_WIDTH SH_CSS_MAX_SENSOR_WIDTH -#define ISP_PRE_GDC_MAX_OUTPUT_HEIGHT SH_CSS_MAX_SENSOR_HEIGHT -#define ISP_PRE_GDC_MIN_OUTPUT_WIDTH SH_CSS_MIN_SENSOR_WIDTH -#define ISP_PRE_GDC_MIN_OUTPUT_HEIGHT SH_CSS_MIN_SENSOR_HEIGHT -#define ISP_PRE_GDC_OUTPUT_FORMATS { SH_CSS_FRAME_FORMAT_QPLANE6 } -#define ISP_PRE_GDC_MAX_VF_LOG_DOWNSCALE 0 -#define ISP_PRE_GDC_INPUT SH_CSS_BINARY_INPUT_VARIABLE -#define ISP_PRE_GDC_C_SUBSAMPLING SH_CSS_DEFAULT_C_SUBSAMPLING -#define ISP_PRE_GDC_FIXED_S3A_DECI_LOG 0 +/* Pre ISP */ +#define ISP_PRE_ISP_BINARY_ID SH_CSS_BINARY_ID_PRE_ISP +#define ISP_PRE_ISP_BINARY isp_preisp_var +#define ISP_PRE_ISP_MODE SH_CSS_BINARY_MODE_PRE_ISP +#define ISP_PRE_ISP_ENABLE_FPNR 1 +#define ISP_PRE_ISP_ENABLE_SC 1 +#define ISP_PRE_ISP_ENABLE_S3A 1 +#define ISP_PRE_ISP_ENABLE_SDIS 1 +#define ISP_PRE_ISP_ENABLE_DS 0 +#define ISP_PRE_ISP_ENABLE_VF_VECEVEN 0 +#define ISP_PRE_ISP_ENABLE_UDS 0 +#define ISP_PRE_ISP_PIPELINING 1 +#define ISP_PRE_ISP_OUTPUT_NUM_CHUNKS 1 +#define ISP_PRE_ISP_DUMMY_BUF_VECTORS 0 +#define ISP_PRE_ISP_LEFT_CROPPING 0 +#define ISP_PRE_ISP_TOP_CROPPING 0 +#define ISP_PRE_ISP_ENABLE_DVS_ENVELOPE 0 +#define ISP_PRE_ISP_MAX_DVS_ENVELOPE_WIDTH 0 +#define ISP_PRE_ISP_MAX_DVS_ENVELOPE_HEIGHT 0 +#define ISP_PRE_ISP_MAX_OUTPUT_WIDTH SH_CSS_MAX_SENSOR_WIDTH +#define ISP_PRE_ISP_MAX_OUTPUT_HEIGHT SH_CSS_MAX_SENSOR_HEIGHT +#define ISP_PRE_ISP_MIN_OUTPUT_WIDTH SH_CSS_MIN_SENSOR_WIDTH +#define ISP_PRE_ISP_MIN_OUTPUT_HEIGHT SH_CSS_MIN_SENSOR_HEIGHT +#define ISP_PRE_ISP_OUTPUT_FORMATS SH_CSS_PRE_ISP_OUTPUT_FORMATS +#define ISP_PRE_ISP_MAX_VF_LOG_DOWNSCALE 0 +#define ISP_PRE_ISP_INPUT SH_CSS_BINARY_INPUT_VARIABLE +#define ISP_PRE_ISP_C_SUBSAMPLING SH_CSS_DEFAULT_C_SUBSAMPLING +#define ISP_PRE_ISP_FIXED_S3A_DECI_LOG 0 /* ANR */ #define ISP_ANR_BINARY_ID SH_CSS_BINARY_ID_ANR @@ -242,7 +241,7 @@ #define ISP_ANR_ENABLE_DVS_ENVELOPE 0 #define ISP_ANR_MAX_DVS_ENVELOPE_WIDTH 0 #define ISP_ANR_MAX_DVS_ENVELOPE_HEIGHT 0 -#define ISP_ANR_MAX_OUTPUT_WIDTH 3264 +#define ISP_ANR_MAX_OUTPUT_WIDTH 3840 #define ISP_ANR_MAX_OUTPUT_HEIGHT SH_CSS_MAX_SENSOR_HEIGHT #define ISP_ANR_MIN_OUTPUT_WIDTH SH_CSS_MIN_SENSOR_WIDTH #define ISP_ANR_MIN_OUTPUT_HEIGHT SH_CSS_MIN_SENSOR_HEIGHT @@ -252,65 +251,6 @@ #define ISP_ANR_C_SUBSAMPLING SH_CSS_DEFAULT_C_SUBSAMPLING #define ISP_ANR_FIXED_S3A_DECI_LOG 0 -/* Post ANR */ -#define ISP_POST_ANR_BINARY_ID SH_CSS_BINARY_ID_POST_ANR -#define ISP_POST_ANR_BINARY isp_postanr_var -#define ISP_POST_ANR_MODE SH_CSS_BINARY_MODE_POST_ANR -#define ISP_POST_ANR_PIPELINING 2 -#define ISP_POST_ANR_ENABLE_VF_VECEVEN 1 -#define ISP_POST_ANR_ENABLE_DS 0 -#define ISP_POST_ANR_ENABLE_FPNR 0 -#define ISP_POST_ANR_ENABLE_SC 0 -#define ISP_POST_ANR_ENABLE_S3A 0 -#define ISP_POST_ANR_ENABLE_SDIS 0 -#define ISP_POST_ANR_ENABLE_UDS 0 -#define ISP_POST_ANR_OUTPUT_NUM_CHUNKS 1 -#define ISP_POST_ANR_DUMMY_BUF_VECTORS 0 -#define ISP_POST_ANR_LEFT_CROPPING SH_CSS_MAX_LEFT_CROPPING -#define ISP_POST_ANR_TOP_CROPPING 8 -#define ISP_POST_ANR_ENABLE_DVS_ENVELOPE 0 -#define ISP_POST_ANR_MAX_DVS_ENVELOPE_WIDTH 0 -#define ISP_POST_ANR_MAX_DVS_ENVELOPE_HEIGHT 0 -#define ISP_POST_ANR_MAX_VF_LOG_DOWNSCALE 2 -/* limited due to VMEM shortage */ -#define ISP_POST_ANR_MAX_OUTPUT_WIDTH 3264 -#define ISP_POST_ANR_MAX_OUTPUT_HEIGHT SH_CSS_MAX_SENSOR_HEIGHT -#define ISP_POST_ANR_MIN_OUTPUT_WIDTH SH_CSS_MIN_SENSOR_WIDTH -#define ISP_POST_ANR_MIN_OUTPUT_HEIGHT SH_CSS_MIN_SENSOR_HEIGHT -#define ISP_POST_ANR_OUTPUT_FORMATS SH_CSS_CAPTURE_OUTPUT_FORMATS -#define ISP_POST_ANR_INPUT SH_CSS_BINARY_INPUT_MEMORY -#define ISP_POST_ANR_C_SUBSAMPLING SH_CSS_DEFAULT_C_SUBSAMPLING -#define ISP_POST_ANR_FIXED_S3A_DECI_LOG 0 - -/* Pre ANR */ -#define ISP_PRE_ANR_BINARY_ID SH_CSS_BINARY_ID_PRE_ANR -#define ISP_PRE_ANR_BINARY isp_preanr_var -#define ISP_PRE_ANR_MODE SH_CSS_BINARY_MODE_PRE_ANR -#define ISP_PRE_ANR_ENABLE_FPNR 1 -#define ISP_PRE_ANR_ENABLE_SC 1 -#define ISP_PRE_ANR_ENABLE_S3A 1 -#define ISP_PRE_ANR_ENABLE_SDIS 1 -#define ISP_PRE_ANR_ENABLE_DS 0 -#define ISP_PRE_ANR_ENABLE_VF_VECEVEN 0 -#define ISP_PRE_ANR_ENABLE_UDS 0 -#define ISP_PRE_ANR_PIPELINING 1 -#define ISP_PRE_ANR_OUTPUT_NUM_CHUNKS 1 -#define ISP_PRE_ANR_DUMMY_BUF_VECTORS 0 -#define ISP_PRE_ANR_LEFT_CROPPING 0 -#define ISP_PRE_ANR_TOP_CROPPING 0 -#define ISP_PRE_ANR_ENABLE_DVS_ENVELOPE 0 -#define ISP_PRE_ANR_MAX_DVS_ENVELOPE_WIDTH 0 -#define ISP_PRE_ANR_MAX_DVS_ENVELOPE_HEIGHT 0 -#define ISP_PRE_ANR_MAX_OUTPUT_WIDTH SH_CSS_MAX_SENSOR_WIDTH -#define ISP_PRE_ANR_MAX_OUTPUT_HEIGHT SH_CSS_MAX_SENSOR_HEIGHT -#define ISP_PRE_ANR_MIN_OUTPUT_WIDTH SH_CSS_MIN_SENSOR_WIDTH -#define ISP_PRE_ANR_MIN_OUTPUT_HEIGHT SH_CSS_MIN_SENSOR_HEIGHT -#define ISP_PRE_ANR_OUTPUT_FORMATS { SH_CSS_FRAME_FORMAT_RAW } -#define ISP_PRE_ANR_MAX_VF_LOG_DOWNSCALE 0 -#define ISP_PRE_ANR_INPUT SH_CSS_BINARY_INPUT_VARIABLE -#define ISP_PRE_ANR_C_SUBSAMPLING SH_CSS_DEFAULT_C_SUBSAMPLING -#define ISP_PRE_ANR_FIXED_S3A_DECI_LOG 0 - /* Preview DS */ #define ISP_PREVIEW_DS_BINARY_ID SH_CSS_BINARY_ID_PREVIEW_DS #define ISP_PREVIEW_DS_BINARY isp_preview_ds diff --git a/drivers/media/video/atomisp/css/sh_css_defs.h b/drivers/media/video/atomisp/css/sh_css_defs.h index e7b99c4..89bf6df 100644 --- a/drivers/media/video/atomisp/css/sh_css_defs.h +++ b/drivers/media/video/atomisp/css/sh_css_defs.h @@ -64,8 +64,7 @@ #define SH_CSS_MAX_LEFT_CROPPING 8 #endif -#define SH_CSS_SP_MAX_WIDTH 2560 -#define SH_CSS_SP_MAX_OVERLAY_WIDTH 640 +#define SH_CSS_SP_MAX_WIDTH 1280 /* This is the maximum grid we can handle in the ISP binaries. * The host code makes sure no bigger grid is ever selected. */ @@ -324,6 +323,12 @@ SH_CSS_FRAME_FORMAT_RGBA888 \ } +#define SH_CSS_PRE_ISP_OUTPUT_FORMATS \ + { \ + SH_CSS_FRAME_FORMAT_RAW, \ + SH_CSS_FRAME_FORMAT_QPLANE6 \ + } + /* Fixed resolution primaries only output this format */ #define SH_CSS_FIXED_PRIMARY_FORMAT SH_CSS_FRAME_FORMAT_NV12 diff --git a/drivers/media/video/atomisp/css/sh_css_internal.h b/drivers/media/video/atomisp/css/sh_css_internal.h index 086591e..4303bed 100644 --- a/drivers/media/video/atomisp/css/sh_css_internal.h +++ b/drivers/media/video/atomisp/css/sh_css_internal.h @@ -187,6 +187,7 @@ struct sh_css_sp_group { unsigned int sp_run_copy; void *xmem_bin_addr; void *xmem_map_addr; + unsigned anr; struct sh_css_frame sp_in_frame; struct sh_css_frame sp_out_frame; struct sh_css_frame sp_ref_in_frame; diff --git a/drivers/media/video/atomisp/css/sh_css_params.c b/drivers/media/video/atomisp/css/sh_css_params.c index 25c3c93..499194c 100644 --- a/drivers/media/video/atomisp/css/sh_css_params.c +++ b/drivers/media/video/atomisp/css/sh_css_params.c @@ -527,8 +527,8 @@ static const struct sh_css_tnr_config default_tnr_config = { static const struct sh_css_tnr_config disabled_tnr_config = { .gain = 0, - .threshold_y = 65535, - .threshold_uv = 65535, + .threshold_y = 0, + .threshold_uv = 0, }; static const struct sh_css_ob_config default_ob_config = { @@ -1537,18 +1537,6 @@ sh_css_get_anr_config(const struct sh_css_anr_config **config) *config = anr_config; } -void -sh_css_set_anr_threshold(int threshold) -{ - struct sh_css_anr_config - **config = sh_css_malloc(sizeof(struct sh_css_anr_config *)); - sh_css_get_anr_config((const struct sh_css_anr_config **)config); - (*config)->threshold = threshold; - sh_css_set_anr_config(*config); - if (config) - sh_css_free(config); -} - static bool alloc(void **ptr, unsigned int bytes) { diff --git a/drivers/media/video/atomisp/css/sh_css_params.h b/drivers/media/video/atomisp/css/sh_css_params.h index e99441b..cbf505b 100644 --- a/drivers/media/video/atomisp/css/sh_css_params.h +++ b/drivers/media/video/atomisp/css/sh_css_params.h @@ -91,9 +91,6 @@ sh_css_get_tnr_config(const struct sh_css_tnr_config **tnr_config); /* ANR */ void -sh_css_set_anr_threshold(int threshold); - -void sh_css_set_anr_config(const struct sh_css_anr_config *anr_config); void diff --git a/drivers/media/video/atomisp/css/sh_css_sp.c b/drivers/media/video/atomisp/css/sh_css_sp.c index 409e570..916b50c 100644 --- a/drivers/media/video/atomisp/css/sh_css_sp.c +++ b/drivers/media/video/atomisp/css/sh_css_sp.c @@ -301,6 +301,8 @@ sh_css_sp_configure_dvs(const struct sh_css_binary *binary, motion_y = clamp(motion_y, -half_env_y, half_env_y); uds_xc += motion_x; uds_yc += motion_y; + /* uds can be pipelined, remove top lines */ + crop_y = 2; } else if (binary->info->enable_ds) { env_width = binary->dvs_envelope_width; env_height = binary->dvs_envelope_height; @@ -510,7 +512,8 @@ sh_css_sp_set_overlay(const struct sh_css_overlay *overlay) enum sh_css_err sh_css_sp_start_isp(struct sh_css_binary *binary, const struct sh_css_binary_args *args, - bool preview_mode) + bool preview_mode, + bool low_light) { unsigned int dx, dy; enum sh_css_err err = sh_css_success; @@ -556,6 +559,7 @@ sh_css_sp_start_isp(struct sh_css_binary *binary, sh_css_sp_group.xmem_bin_addr = binary->info->xmem_addr; sh_css_sp_group.xmem_map_addr = sh_css_params_ddr_address_map(); + sh_css_sp_group.anr = low_light; store_sp_int(sp_isp_started, 0); diff --git a/drivers/media/video/atomisp/css/sh_css_sp.h b/drivers/media/video/atomisp/css/sh_css_sp.h index 7acd6d1..57ca20e 100644 --- a/drivers/media/video/atomisp/css/sh_css_sp.h +++ b/drivers/media/video/atomisp/css/sh_css_sp.h @@ -87,7 +87,8 @@ sh_css_sp_get_sw_interrupt_value(void); enum sh_css_err sh_css_sp_start_isp(struct sh_css_binary *binary, const struct sh_css_binary_args *args, - bool preview_mode); + bool preview_mode, + bool low_light); void sh_css_sp_get_debug_state(struct sh_css_sp_debug_state *state); diff --git a/drivers/media/video/atomisp/css/sh_css_sp_start.c b/drivers/media/video/atomisp/css/sh_css_sp_start.c index 1ec6624..83f115d 100644 --- a/drivers/media/video/atomisp/css/sh_css_sp_start.c +++ b/drivers/media/video/atomisp/css/sh_css_sp_start.c @@ -52,14 +52,17 @@ sh_css_sp_start(unsigned int start_address) } - void * -sh_css_sp_load_program(const struct sh_css_sp_fw *fw, const char *sp_prog) +void * +sh_css_sp_load_program(const struct sh_css_sp_fw *fw, const char *sp_prog, + void *code_addr) { - void *code_addr; - - /* store code (text section) to DDR */ - code_addr = hrt_isp_css_mm_alloc(fw->text_size); - hrt_isp_css_mm_store(code_addr, fw->text, fw->text_size); + if (!code_addr) { + /* store code (text section) to DDR */ + code_addr = hrt_isp_css_mm_alloc(fw->text_size); + if (!code_addr) + return NULL; + hrt_isp_css_mm_store(code_addr, fw->text, fw->text_size); + } /* Set the correct start address for the SP program */ sh_css_sp_activate_program(fw, code_addr, sp_prog); diff --git a/drivers/media/video/atomisp/css/sh_css_sp_start.h b/drivers/media/video/atomisp/css/sh_css_sp_start.h index 0b79963..39ad094 100644 --- a/drivers/media/video/atomisp/css/sh_css_sp_start.h +++ b/drivers/media/video/atomisp/css/sh_css_sp_start.h @@ -74,7 +74,8 @@ void sh_css_sp_start(unsigned int start_address); void * -sh_css_sp_load_program(const struct sh_css_sp_fw *fw, const char *sp_prog); +sh_css_sp_load_program(const struct sh_css_sp_fw *fw, const char *sp_prog, + void *code_addr); void sh_css_sp_activate_program(const struct sh_css_sp_fw *fw, diff --git a/drivers/media/video/atomisp/css/sh_css_types.h b/drivers/media/video/atomisp/css/sh_css_types.h index 2ffa1a6..48fd9bf 100644 --- a/drivers/media/video/atomisp/css/sh_css_types.h +++ b/drivers/media/video/atomisp/css/sh_css_types.h @@ -740,16 +740,20 @@ struct sh_css_acc_fw_hdr { struct { unsigned int size; /* Size of isp blob */ } isp; + /* To create a sequence of accelerators */ + struct sh_css_acc_fw *next; + /* Firmware handle between user space and kernel */ + unsigned int handle; + /* Hmm pointer of allocated SP code */ + const unsigned char *sp_code; + /* Hmm pointer of allocated ISP code */ + const unsigned char *isp_code; }; /* Firmware. Containing header and actual blobs */ struct sh_css_acc_fw { /* firmware header */ struct sh_css_acc_fw_hdr header; - /* To create a sequence of accelerators */ - struct sh_css_acc_fw *next; - /* Firmware handle between user space and kernel */ - unsigned int handle; /* followed by prog_name, sp arg types, sp blob and isp blob */ #ifdef __HIVECC unsigned char data[1]; /* Not C89 */ diff --git a/drivers/media/video/atomisp/include/atomisp/atomisp_internal.h b/drivers/media/video/atomisp/include/atomisp/atomisp_internal.h index e0b5286..769cc0a 100644 --- a/drivers/media/video/atomisp/include/atomisp/atomisp_internal.h +++ b/drivers/media/video/atomisp/include/atomisp/atomisp_internal.h @@ -269,6 +269,9 @@ struct atomisp_device { __u32 snr_max_width; __u32 snr_max_height; __u32 snr_pixelformat; + + /* isp timeout status flag */ + bool isp_timeout; }; #define v4l2_dev_to_atomisp_device(dev) \ diff --git a/drivers/media/video/mt9e013.c b/drivers/media/video/mt9e013.c index 4c2b9b2..ad7d606 100644 --- a/drivers/media/video/mt9e013.c +++ b/drivers/media/video/mt9e013.c @@ -733,6 +733,7 @@ static int mt9e013_otp_read(struct v4l2_subdev *sd, if (!(ready & MT9E013_OTP_READY_REG_OK)) { v4l2_info(client, "%s: OTP memory was initialized with error\n", __func__); + ret = -EIO; goto out; } ret = mt9e013_read_reg_array(client, MT9E013_OTP_DATA_SIZE, @@ -749,9 +750,11 @@ static int mt9e013_otp_read(struct v4l2_subdev *sd, goto out; } ret = copy_to_user(data, buf, size); - if (ret) + if (ret) { v4l2_err(client, "%s: failed to copy OTP data to user\n", __func__); + ret = -EFAULT; + } out: kfree(buf); diff --git a/drivers/media/video/mt9m114.c b/drivers/media/video/mt9m114.c index b61fa96..800b9f6 100644 --- a/drivers/media/video/mt9m114.c +++ b/drivers/media/video/mt9m114.c @@ -445,7 +445,7 @@ static int mt9m114_set_suspend(struct v4l2_subdev *sd) if (ret) return ret; - ret = mt9m114_wait_state(sd, 100); + ret = mt9m114_wait_state(sd, MT9M114_WAIT_STAT_TIMEOUT); return ret; } @@ -467,7 +467,7 @@ static int mt9m114_init_common(struct v4l2_subdev *sd) if (ret) return -EINVAL; - ret = mt9m114_wait_state(sd, 100); + ret = mt9m114_wait_state(sd, MT9M114_WAIT_STAT_TIMEOUT); return ret; } @@ -660,13 +660,12 @@ static int mt9m114_s_power(struct v4l2_subdev *sd, int power) struct mt9m114_device *dev = to_mt9m114_sensor(sd); struct i2c_client *client = v4l2_get_subdevdata(sd); - /* Disable flip when power on */ - dev->flip = (dev->flip | (0x0001<<1)) & (~0x0001); if (power == 0) return power_down(sd); else { if (power_up(sd)) return -EINVAL; + return mt9m114_init_common(sd); } } @@ -794,20 +793,27 @@ static int mt9m114_set_mbus_fmt(struct v4l2_subdev *sd, switch (res_index->res) { case MT9M114_RES_QVGA: ret = mt9m114_write_reg_array(c, mt9m114_qvga_init); - mt9m114_write_reg(c, MISENSOR_16BIT, 0xC834, dev->flip | 0x0110); + /* set sensor read_mode to Skipping */ + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_SKIPPING_SET); break; case MT9M114_RES_VGA: ret = mt9m114_write_reg_array(c, mt9m114_vga_init); - mt9m114_write_reg(c, MISENSOR_16BIT, - 0xC834, dev->flip | 0x0330); + /* set sensor read_mode to Summing */ + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_SUMMING_SET); break; case MT9M114_RES_720P: ret = mt9m114_write_reg_array(c, mt9m114_720p_init); - mt9m114_write_reg(c, MISENSOR_16BIT, 0xC834, dev->flip); + /* set sensor read_mode to Normal */ + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_NORMAL_SET); break; case MT9M114_RES_960P: ret = mt9m114_write_reg_array(c, mt9m114_960P_init); - mt9m114_write_reg(c, MISENSOR_16BIT, 0xC834, dev->flip); + /* set sensor read_mode to Normal */ + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_NORMAL_SET); break; default: v4l2_err(sd, "set resolution: %d failed!\n", res_index->res); @@ -819,7 +825,7 @@ static int mt9m114_set_mbus_fmt(struct v4l2_subdev *sd, if (mt9m114_write_reg_array(c, mt9m114_common)) return -EINVAL; - if (mt9m114_wait_state(sd, 100)) + if (mt9m114_wait_state(sd, MT9M114_WAIT_STAT_TIMEOUT)) return -EINVAL; if (mt9m114_set_suspend(sd)) @@ -891,6 +897,33 @@ static int mt9m114_g_fnumber_range(struct v4l2_subdev *sd, s32 * val) return 0; } +static int mt9m114_s_freq(struct v4l2_subdev *sd, s32 val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + int ret; + + if (val != MT9M114_FLICKER_MODE_50HZ && + val != MT9M114_FLICKER_MODE_60HZ) + return -EINVAL; + + if (val == MT9M114_FLICKER_MODE_50HZ) { + ret = mt9m114_write_reg_array(c, mt9m114_antiflicker_50hz); + if (ret < 0) + return ret; + } else { + ret = mt9m114_write_reg_array(c, mt9m114_antiflicker_60hz); + if (ret < 0) + return ret; + } + + ret = mt9m114_wait_state(sd, MT9M114_WAIT_STAT_TIMEOUT); + if (ret == 0) + dev->lightfreq = val; + + return ret; +} + static struct mt9m114_control mt9m114_controls[] = { { .qc = { @@ -954,7 +987,20 @@ static struct mt9m114_control mt9m114_controls[] = { .flags = 0, }, .query = mt9m114_g_fnumber_range, - } + }, + { + .qc = { + .id = V4L2_CID_POWER_LINE_FREQUENCY, + .type = V4L2_CTRL_TYPE_MENU, + .name = "Light frequency filter", + .minimum = 1, + .maximum = 2, /* 1: 50Hz, 2:60Hz */ + .step = 1, + .default_value = 1, + .flags = 0, + }, + .tweak = mt9m114_s_freq, + }, }; #define N_CONTROLS (ARRAY_SIZE(mt9m114_controls)) @@ -1082,7 +1128,10 @@ static int mt9m114_t_hflip(struct v4l2_subdev *sd, int value) /* ctx B */ err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x01, 0x01); err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x01, 0x01); - dev->flip |= 0x0003; + + /* enable vert_flip and horz_mirror */ + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_F_M_MASK, MISENSOR_F_M_EN); dev->bpat = MT9M114_BPAT_GRGRBGBG; } else { @@ -1092,7 +1141,10 @@ static int mt9m114_t_hflip(struct v4l2_subdev *sd, int value) /* ctx B */ err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x01, 0x00); err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x01, 0x00); - dev->flip = (dev->flip | (0x0001<<1)) & (~0x0001); + + /* enable vert_flip and disable horz_mirror */ + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_F_M_MASK, MISENSOR_F_EN); dev->bpat = MT9M114_BPAT_BGBGGRGR; } @@ -1135,7 +1187,10 @@ static int mt9m114_t_vflip(struct v4l2_subdev *sd, int value) /* ctx B */ err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x02, 0x01); err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x02, 0x01); - dev->flip &= (~0x0003); + + /* disable vert_flip and horz_mirror */ + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_F_M_MASK, MISENSOR_F_M_DIS); } else { /* disable H flip - ctx A */ err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x02, 0x00); @@ -1143,13 +1198,16 @@ static int mt9m114_t_vflip(struct v4l2_subdev *sd, int value) /* ctx B */ err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x02, 0x00); err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x02, 0x00); - dev->flip = (dev->flip | (0x0001<<1)) & (~0x0001); + + /* enable vert_flip and disable horz_mirror */ + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_F_M_MASK, MISENSOR_F_EN); } err += mt9m114_write_reg(c, MISENSOR_8BIT, 0x8404, 0x06); udelay(10); - return err; + return !!err; } static int mt9m114_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) @@ -1208,6 +1266,13 @@ static int mt9m114_s_stream(struct v4l2_subdev *sd, int enable) struct i2c_client *c = v4l2_get_subdevdata(sd); if (enable) { + ret = mt9m114_write_reg_array(c, mt9m114_common); + if (ret < 0) + return ret; + ret = mt9m114_wait_state(sd, MT9M114_WAIT_STAT_TIMEOUT); + if (ret < 0) + return ret; + ret = mt9m114_set_streaming(sd); /* * here we wait for sensor's 3A algorithm to be @@ -1244,10 +1309,22 @@ static int mt9m114_enum_frameintervals(struct v4l2_subdev *sd, struct v4l2_frmivalenum *fival) { unsigned int index = fival->index; + int i; if (index >= N_RES) return -EINVAL; + /* find out the first equal or bigger size */ + for (i = 0; i < N_RES; i++) { + if ((mt9m114_res[i].width >= fival->width) && + (mt9m114_res[i].height >= fival->height)) + break; + } + if (i == N_RES) + i--; + + index = i; + fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; fival->discrete.numerator = 1; fival->discrete.denominator = mt9m114_res[index].fps; diff --git a/drivers/media/video/mt9m114.h b/drivers/media/video/mt9m114.h index bcf33d9..3169f8c 100644 --- a/drivers/media/video/mt9m114.h +++ b/drivers/media/video/mt9m114.h @@ -57,6 +57,26 @@ #define MISENSOR_TOK_POLL 0xfc00 /* token indicating poll instruction */ #define MISENSOR_TOK_RMW 0x0010 /* RMW operation */ #define MISENSOR_TOK_MASK 0xfff0 +#define MISENSOR_FLIP_EN (1<<1) /* enable vert_flip */ +#define MISENSOR_MIRROR_EN (1<<0) /* enable horz_mirror */ + +/* mask to set sensor read_mode via misensor_rmw_reg */ +#define MISENSOR_R_MODE_MASK 0x0330 +/* mask to set sensor vert_flip and horz_mirror */ +#define MISENSOR_F_M_MASK 0x0003 + +/* bits set to set sensor read_mode via misensor_rmw_reg */ +#define MISENSOR_SKIPPING_SET 0x0011 +#define MISENSOR_SUMMING_SET 0x0033 +#define MISENSOR_NORMAL_SET 0x0000 + +/* bits set to set sensor vert_flip and horz_mirror */ +#define MISENSOR_F_M_EN (MISENSOR_FLIP_EN | MISENSOR_MIRROR_EN) +#define MISENSOR_F_EN MISENSOR_FLIP_EN +#define MISENSOR_F_M_DIS (MISENSOR_FLIP_EN & MISENSOR_MIRROR_EN) + +/* sensor register that control sensor read-mode and mirror */ +#define MISENSOR_READ_MODE 0xC834 #define SENSOR_DETECTED 1 #define SENSOR_NOT_DETECTED 0 @@ -93,7 +113,9 @@ #define MT9M114_FOCAL_LENGTH_DEM 100 #define MT9M114_F_NUMBER_DEFAULT_NUM 24 #define MT9M114_F_NUMBER_DEM 10 - +#define MT9M114_WAIT_STAT_TIMEOUT 100 +#define MT9M114_FLICKER_MODE_50HZ 1 +#define MT9M114_FLICKER_MODE_60HZ 2 /* * focal length bits definition: * bits 31-16: numerator, bits 15-0: denominator @@ -218,8 +240,7 @@ struct mt9m114_device { unsigned int mipi_lanes; char name[32]; - /* flip information */ - u32 flip; + u8 lightfreq; }; struct mt9m114_format_struct { @@ -404,7 +425,6 @@ static struct misensor_reg const mt9m114_720p_init[] = { {MISENSOR_16BIT, 0xC816, 0x0060}, {MISENSOR_16BIT, 0xC818, 0x02D3}, {MISENSOR_16BIT, 0xC826, 0x0020}, - {MISENSOR_16BIT, 0xC834, 0x0000}, {MISENSOR_16BIT, 0xC854, 0x0000}, @@ -455,7 +475,6 @@ static struct misensor_reg const mt9m114_vga_init[] = { {MISENSOR_16BIT, 0xC816, 0x00E0}, {MISENSOR_16BIT, 0xC818, 0x01E3}, {MISENSOR_16BIT, 0xC826, 0x0020}, - {MISENSOR_16BIT, 0xC834, 0x0330}, {MISENSOR_16BIT, 0xC854, 0x0000}, {MISENSOR_16BIT, 0xC856, 0x0000}, {MISENSOR_16BIT, 0xC858, 0x0280}, @@ -496,7 +515,6 @@ static struct misensor_reg const mt9m114_960P_init[] = { {MISENSOR_16BIT, 0xC816, 0x0060}, {MISENSOR_16BIT, 0xC818, 0x03C3}, {MISENSOR_16BIT, 0xC826, 0x0020}, - {MISENSOR_16BIT, 0xC834, 0x0000}, {MISENSOR_16BIT, 0xC854, 0x0000}, {MISENSOR_16BIT, 0xC856, 0x0000}, {MISENSOR_16BIT, 0xC858, 0x0500}, @@ -538,6 +556,22 @@ static struct misensor_reg const mt9m114_common[] = { {MISENSOR_TOK_TERM, 0, 0} }; +static struct misensor_reg const mt9m114_antiflicker_50hz[] = { + {MISENSOR_16BIT, 0x098E, 0xC88B}, + {MISENSOR_8BIT, 0xC88B, 0x32}, + {MISENSOR_8BIT, 0xDC00, 0x28}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_antiflicker_60hz[] = { + {MISENSOR_16BIT, 0x098E, 0xC88B}, + {MISENSOR_8BIT, 0xC88B, 0x3C}, + {MISENSOR_8BIT, 0xDC00, 0x28}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + static struct misensor_reg const mt9m114_iq[] = { /* [Step3-Recommended] [Sensor optimization] */ {MISENSOR_16BIT, 0x316A, 0x8270}, -- 2.7.4