From 19c6e1b44748e1f1d54f1a70b608ffd4a813b7fd Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Sun, 21 Aug 2022 20:51:58 -0700 Subject: [PATCH] intel/compiler: Create and use struct for TES thread payload MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Acked-by: Lionel Landwerlin Reviewed-by: Marcin Ślusarz Reviewed-by: Kenneth Graunke Acked-by: Ian Romanick Part-of: --- src/intel/compiler/brw_fs.cpp | 3 +-- src/intel/compiler/brw_fs.h | 14 ++++++++++++++ src/intel/compiler/brw_fs_nir.cpp | 15 ++++++--------- src/intel/compiler/brw_fs_thread_payload.cpp | 16 ++++++++++++++++ src/intel/compiler/brw_fs_visitor.cpp | 2 +- 5 files changed, 38 insertions(+), 12 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 871a6aa..9c9ff5f 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -6683,8 +6683,7 @@ fs_visitor::run_tes() { assert(stage == MESA_SHADER_TESS_EVAL); - /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */ - payload().num_regs = 5; + payload_ = new tes_thread_payload(); emit_nir_code(); diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 8947bbe..f716110 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -101,6 +101,15 @@ struct tcs_thread_payload : public thread_payload { fs_reg icp_handle_start; }; +struct tes_thread_payload : public thread_payload { + tes_thread_payload(); + + fs_reg patch_urb_input; + fs_reg primitive_id; + fs_reg coords[3]; + fs_reg urb_output; +}; + struct fs_thread_payload : public thread_payload { fs_thread_payload(const fs_visitor &v, bool &source_depth_to_render_target, @@ -434,6 +443,11 @@ public: return *static_cast(this->payload_); } + tes_thread_payload &tes_payload() { + assert(stage == MESA_SHADER_TESS_EVAL); + return *static_cast(this->payload_); + } + fs_thread_payload &fs_payload() { assert(stage == MESA_SHADER_FRAGMENT); return *static_cast(this->payload_); diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index fb12ceb..5a57dc3 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -3045,13 +3045,12 @@ fs_visitor::nir_emit_tes_intrinsic(const fs_builder &bld, switch (instr->intrinsic) { case nir_intrinsic_load_primitive_id: - bld.MOV(dest, fs_reg(brw_vec1_grf(0, 1))); + bld.MOV(dest, tes_payload().primitive_id); break; + case nir_intrinsic_load_tess_coord: - /* gl_TessCoord is part of the payload in g1-3 */ - for (unsigned i = 0; i < 3; i++) { - bld.MOV(offset(dest, bld, i), fs_reg(brw_vec8_grf(1 + i, 0))); - } + for (unsigned i = 0; i < 3; i++) + bld.MOV(offset(dest, bld, i), tes_payload().coords[i]); break; case nir_intrinsic_load_input: @@ -3080,8 +3079,7 @@ fs_visitor::nir_emit_tes_intrinsic(const fs_builder &bld, } else { /* Replicate the patch handle to all enabled channels */ fs_reg srcs[URB_LOGICAL_NUM_SRCS]; - srcs[URB_LOGICAL_SRC_HANDLE] = - retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD); + srcs[URB_LOGICAL_SRC_HANDLE] = tes_payload().patch_urb_input; if (first_component != 0) { unsigned read_components = @@ -3112,8 +3110,7 @@ fs_visitor::nir_emit_tes_intrinsic(const fs_builder &bld, unsigned num_components = instr->num_components; fs_reg srcs[URB_LOGICAL_NUM_SRCS]; - srcs[URB_LOGICAL_SRC_HANDLE] = - retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD); + srcs[URB_LOGICAL_SRC_HANDLE] = tes_payload().patch_urb_input; srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset; if (first_component != 0) { diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp index aa5435f..c2f22d8 100644 --- a/src/intel/compiler/brw_fs_thread_payload.cpp +++ b/src/intel/compiler/brw_fs_thread_payload.cpp @@ -58,6 +58,22 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v) } } +tes_thread_payload::tes_thread_payload() +{ + /* R0: Thread Header. */ + patch_urb_input = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD); + primitive_id = brw_vec1_grf(0, 1); + + /* R1-3: gl_TessCoord.xyz. */ + for (unsigned i = 0; i < 3; i++) + coords[i] = brw_vec8_grf(1 + i, 0); + + /* R4: URB output handles. */ + urb_output = retype(brw_vec8_grf(4, 0), BRW_REGISTER_TYPE_UD); + + num_regs = 5; +} + static inline void setup_fs_payload_gfx6(fs_thread_payload &payload, const fs_visitor &v, diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index 12e25bc..bddf6d1 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -771,7 +771,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) fs_reg urb_handle; if (stage == MESA_SHADER_TESS_EVAL) - urb_handle = fs_reg(retype(brw_vec8_grf(4, 0), BRW_REGISTER_TYPE_UD)); + urb_handle = tes_payload().urb_output; else urb_handle = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD)); -- 2.7.4