From 19ba573a57ff6125a26ff9ae94cf43c36129645f Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Thu, 20 Mar 2014 17:37:00 -0400 Subject: [PATCH] nvc0/ir: move sample id to second source arg to fix sampler2DMS The nvc0 texfetch instruction expects the sample id to be in the second source (usually used for the offset) rather than as part of the texture coordinate. This fixes all the sampler2DMS/Array tests on nvc0. Signed-off-by: Ilia Mirkin Reviewed-by: Christoph Bumiller Cc: "10.1" --- .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 14 +++++++++++--- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 2 +- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 3840f75..c0d1475 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -666,8 +666,9 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) const int dim = i->tex.target.getDim() + i->tex.target.isCube(); const int arg = i->tex.target.getArgCount(); const int lyr = arg - (i->tex.target.isMS() ? 2 : 1); + const int chipset = prog->getTarget()->getChipset(); - if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET) { + if (chipset >= NVISA_GK104_CHIPSET) { if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) { WARN("indirect TEX not implemented\n"); } @@ -697,7 +698,7 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) } } else // (nvc0) generate and move the tsc/tic/array source to the front - if (dim != arg || i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) { + if (i->tex.target.isArray() || i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) { LValue *src = new_LValue(func, FILE_GPR); // 0xttxsaaaa Value *arrayIndex = i->tex.target.isArray() ? i->getSrc(lyr) : NULL; @@ -728,6 +729,13 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) i->setSrc(0, src); } + // For nvc0, the sample id has to be in the second operand, as the offset + // does. Right now we don't know how to pass both in, and this case can't + // happen with OpenGL. On nve0, the sample id is part of the texture + // coordinate argument. + assert(chipset >= NVISA_GK104_CHIPSET || + !i->tex.useOffsets || !i->tex.target.isMS()); + // offset is last source (lod 1st, dc 2nd) if (i->tex.useOffsets) { uint32_t value = 0; @@ -741,7 +749,7 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) i->setSrc(s, bld.loadImm(NULL, value)); } - if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET) { + if (chipset >= NVISA_GK104_CHIPSET) { // // If TEX requires more than 4 sources, the 2nd register tuple must be // aligned to 4, even if it consists of just a single 4-byte register. diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp index 1ace9f5f..60a6a3f 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp @@ -1914,7 +1914,7 @@ RegAlloc::InsertConstraintsPass::texConstraintNVC0(TexInstruction *tex) s = tex->srcCount(0xff); n = 0; } else { - s = tex->tex.target.getArgCount(); + s = tex->tex.target.getArgCount() - tex->tex.target.isMS(); if (!tex->tex.target.isArray() && (tex->tex.rIndirectSrc >= 0 || tex->tex.sIndirectSrc >= 0)) ++s; -- 2.7.4